Commit | Line | Data |
---|---|---|
45244b87 ED |
1 | /* |
2 | * Copyright © 2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "i915_drv.h" | |
29 | #include "intel_drv.h" | |
30 | ||
31 | /* HDMI/DVI modes ignore everything but the last 2 items. So we share | |
32 | * them for both DP and FDI transports, allowing those ports to | |
33 | * automatically adapt to HDMI connections as well | |
34 | */ | |
35 | static const u32 hsw_ddi_translations_dp[] = { | |
36 | 0x00FFFFFF, 0x0006000E, /* DP parameters */ | |
37 | 0x00D75FFF, 0x0005000A, | |
38 | 0x00C30FFF, 0x00040006, | |
39 | 0x80AAAFFF, 0x000B0000, | |
40 | 0x00FFFFFF, 0x0005000A, | |
41 | 0x00D75FFF, 0x000C0004, | |
42 | 0x80C30FFF, 0x000B0000, | |
43 | 0x00FFFFFF, 0x00040006, | |
44 | 0x80D75FFF, 0x000B0000, | |
45 | 0x00FFFFFF, 0x00040006 /* HDMI parameters */ | |
46 | }; | |
47 | ||
48 | static const u32 hsw_ddi_translations_fdi[] = { | |
49 | 0x00FFFFFF, 0x0007000E, /* FDI parameters */ | |
50 | 0x00D75FFF, 0x000F000A, | |
51 | 0x00C30FFF, 0x00060006, | |
52 | 0x00AAAFFF, 0x001E0000, | |
53 | 0x00FFFFFF, 0x000F000A, | |
54 | 0x00D75FFF, 0x00160004, | |
55 | 0x00C30FFF, 0x001E0000, | |
56 | 0x00FFFFFF, 0x00060006, | |
57 | 0x00D75FFF, 0x001E0000, | |
58 | 0x00FFFFFF, 0x00040006 /* HDMI parameters */ | |
59 | }; | |
60 | ||
61 | /* On Haswell, DDI port buffers must be programmed with correct values | |
62 | * in advance. The buffer values are different for FDI and DP modes, | |
63 | * but the HDMI/DVI fields are shared among those. So we program the DDI | |
64 | * in either FDI or DP modes only, as HDMI connections will work with both | |
65 | * of those | |
66 | */ | |
67 | void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port, bool use_fdi_mode) | |
68 | { | |
69 | struct drm_i915_private *dev_priv = dev->dev_private; | |
70 | u32 reg; | |
71 | int i; | |
72 | const u32 *ddi_translations = ((use_fdi_mode) ? | |
73 | hsw_ddi_translations_fdi : | |
74 | hsw_ddi_translations_dp); | |
75 | ||
76 | DRM_DEBUG_DRIVER("Initializing DDI buffers for port %c in %s mode\n", | |
77 | port_name(port), | |
78 | use_fdi_mode ? "FDI" : "DP"); | |
79 | ||
80 | WARN((use_fdi_mode && (port != PORT_E)), | |
81 | "Programming port %c in FDI mode, this probably will not work.\n", | |
82 | port_name(port)); | |
83 | ||
84 | for (i=0, reg=DDI_BUF_TRANS(port); i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) { | |
85 | I915_WRITE(reg, ddi_translations[i]); | |
86 | reg += 4; | |
87 | } | |
88 | } | |
89 | ||
90 | /* Program DDI buffers translations for DP. By default, program ports A-D in DP | |
91 | * mode and port E for FDI. | |
92 | */ | |
93 | void intel_prepare_ddi(struct drm_device *dev) | |
94 | { | |
95 | int port; | |
96 | ||
97 | if (IS_HASWELL(dev)) { | |
98 | for (port = PORT_A; port < PORT_E; port++) | |
99 | intel_prepare_ddi_buffers(dev, port, false); | |
100 | ||
101 | /* DDI E is the suggested one to work in FDI mode, so program is as such by | |
102 | * default. It will have to be re-programmed in case a digital DP output | |
103 | * will be detected on it | |
104 | */ | |
105 | intel_prepare_ddi_buffers(dev, PORT_E, true); | |
106 | } | |
107 | } | |
c82e4d26 ED |
108 | |
109 | static const long hsw_ddi_buf_ctl_values[] = { | |
110 | DDI_BUF_EMP_400MV_0DB_HSW, | |
111 | DDI_BUF_EMP_400MV_3_5DB_HSW, | |
112 | DDI_BUF_EMP_400MV_6DB_HSW, | |
113 | DDI_BUF_EMP_400MV_9_5DB_HSW, | |
114 | DDI_BUF_EMP_600MV_0DB_HSW, | |
115 | DDI_BUF_EMP_600MV_3_5DB_HSW, | |
116 | DDI_BUF_EMP_600MV_6DB_HSW, | |
117 | DDI_BUF_EMP_800MV_0DB_HSW, | |
118 | DDI_BUF_EMP_800MV_3_5DB_HSW | |
119 | }; | |
120 | ||
121 | ||
122 | /* Starting with Haswell, different DDI ports can work in FDI mode for | |
123 | * connection to the PCH-located connectors. For this, it is necessary to train | |
124 | * both the DDI port and PCH receiver for the desired DDI buffer settings. | |
125 | * | |
126 | * The recommended port to work in FDI mode is DDI E, which we use here. Also, | |
127 | * please note that when FDI mode is active on DDI E, it shares 2 lines with | |
128 | * DDI A (which is used for eDP) | |
129 | */ | |
130 | ||
131 | void hsw_fdi_link_train(struct drm_crtc *crtc) | |
132 | { | |
133 | struct drm_device *dev = crtc->dev; | |
134 | struct drm_i915_private *dev_priv = dev->dev_private; | |
135 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
136 | int pipe = intel_crtc->pipe; | |
137 | u32 reg, temp, i; | |
138 | ||
139 | /* Configure CPU PLL, wait for warmup */ | |
140 | I915_WRITE(SPLL_CTL, | |
141 | SPLL_PLL_ENABLE | | |
142 | SPLL_PLL_FREQ_1350MHz | | |
143 | SPLL_PLL_SCC); | |
144 | ||
145 | /* Use SPLL to drive the output when in FDI mode */ | |
146 | I915_WRITE(PORT_CLK_SEL(PORT_E), | |
147 | PORT_CLK_SEL_SPLL); | |
148 | I915_WRITE(PIPE_CLK_SEL(pipe), | |
149 | PIPE_CLK_SEL_PORT(PORT_E)); | |
150 | ||
151 | udelay(20); | |
152 | ||
153 | /* Start the training iterating through available voltages and emphasis */ | |
154 | for (i=0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values); i++) { | |
155 | /* Configure DP_TP_CTL with auto-training */ | |
156 | I915_WRITE(DP_TP_CTL(PORT_E), | |
157 | DP_TP_CTL_FDI_AUTOTRAIN | | |
158 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | | |
159 | DP_TP_CTL_LINK_TRAIN_PAT1 | | |
160 | DP_TP_CTL_ENABLE); | |
161 | ||
162 | /* Configure and enable DDI_BUF_CTL for DDI E with next voltage */ | |
163 | temp = I915_READ(DDI_BUF_CTL(PORT_E)); | |
164 | temp = (temp & ~DDI_BUF_EMP_MASK); | |
165 | I915_WRITE(DDI_BUF_CTL(PORT_E), | |
166 | temp | | |
167 | DDI_BUF_CTL_ENABLE | | |
168 | DDI_PORT_WIDTH_X2 | | |
169 | hsw_ddi_buf_ctl_values[i]); | |
170 | ||
171 | udelay(600); | |
172 | ||
173 | /* Enable CPU FDI Receiver with auto-training */ | |
174 | reg = FDI_RX_CTL(pipe); | |
175 | I915_WRITE(reg, | |
176 | I915_READ(reg) | | |
177 | FDI_LINK_TRAIN_AUTO | | |
178 | FDI_RX_ENABLE | | |
179 | FDI_LINK_TRAIN_PATTERN_1_CPT | | |
180 | FDI_RX_ENHANCE_FRAME_ENABLE | | |
181 | FDI_PORT_WIDTH_2X_LPT | | |
182 | FDI_RX_PLL_ENABLE); | |
183 | POSTING_READ(reg); | |
184 | udelay(100); | |
185 | ||
186 | temp = I915_READ(DP_TP_STATUS(PORT_E)); | |
187 | if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { | |
188 | DRM_DEBUG_DRIVER("BUF_CTL training done on %d step\n", i); | |
189 | ||
190 | /* Enable normal pixel sending for FDI */ | |
191 | I915_WRITE(DP_TP_CTL(PORT_E), | |
192 | DP_TP_CTL_FDI_AUTOTRAIN | | |
193 | DP_TP_CTL_LINK_TRAIN_NORMAL | | |
194 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | | |
195 | DP_TP_CTL_ENABLE); | |
196 | ||
197 | /* Enable PIPE_DDI_FUNC_CTL for the pipe to work in FDI mode */ | |
198 | temp = I915_READ(DDI_FUNC_CTL(pipe)); | |
199 | temp &= ~PIPE_DDI_PORT_MASK; | |
200 | temp |= PIPE_DDI_SELECT_PORT(PORT_E) | | |
201 | PIPE_DDI_MODE_SELECT_FDI | | |
202 | PIPE_DDI_FUNC_ENABLE | | |
203 | PIPE_DDI_PORT_WIDTH_X2; | |
204 | I915_WRITE(DDI_FUNC_CTL(pipe), | |
205 | temp); | |
206 | break; | |
207 | } else { | |
208 | DRM_ERROR("Error training BUF_CTL %d\n", i); | |
209 | ||
210 | /* Disable DP_TP_CTL and FDI_RX_CTL) and retry */ | |
211 | I915_WRITE(DP_TP_CTL(PORT_E), | |
212 | I915_READ(DP_TP_CTL(PORT_E)) & | |
213 | ~DP_TP_CTL_ENABLE); | |
214 | I915_WRITE(FDI_RX_CTL(pipe), | |
215 | I915_READ(FDI_RX_CTL(pipe)) & | |
216 | ~FDI_RX_PLL_ENABLE); | |
217 | continue; | |
218 | } | |
219 | } | |
220 | ||
221 | DRM_DEBUG_KMS("FDI train done.\n"); | |
222 | } | |
0e72a5b5 ED |
223 | |
224 | /* For DDI connections, it is possible to support different outputs over the | |
225 | * same DDI port, such as HDMI or DP or even VGA via FDI. So we don't know by | |
226 | * the time the output is detected what exactly is on the other end of it. This | |
227 | * function aims at providing support for this detection and proper output | |
228 | * configuration. | |
229 | */ | |
230 | void intel_ddi_init(struct drm_device *dev, enum port port) | |
231 | { | |
232 | /* For now, we don't do any proper output detection and assume that we | |
233 | * handle HDMI only */ | |
234 | ||
235 | switch(port){ | |
236 | case PORT_A: | |
237 | /* We don't handle eDP and DP yet */ | |
238 | DRM_DEBUG_DRIVER("Found digital output on DDI port A\n"); | |
239 | break; | |
240 | /* Assume that the ports B, C and D are working in HDMI mode for now */ | |
241 | case PORT_B: | |
242 | case PORT_C: | |
243 | case PORT_D: | |
244 | intel_hdmi_init(dev, DDI_BUF_CTL(port)); | |
245 | break; | |
246 | default: | |
247 | DRM_DEBUG_DRIVER("No handlers defined for port %d, skipping DDI initialization\n", | |
248 | port); | |
249 | break; | |
250 | } | |
251 | } |