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drm/i915/ddi: warn instead of oops on invalid ddi encoder type
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ddi.c
CommitLineData
45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include "i915_drv.h"
29#include "intel_drv.h"
30
10122051
JN		 31struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
f8896f5d 34 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
10122051
JN		 35};
36
45244b87
ED		 37/* HDMI/DVI modes ignore everything but the last 2 items. So we share
38 * them for both DP and FDI transports, allowing those ports to
39 * automatically adapt to HDMI connections as well
40 */
10122051 41static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
f8896f5d
DW		 42 { 0x00FFFFFF, 0x0006000E, 0x0 },
43 { 0x00D75FFF, 0x0005000A, 0x0 },
44 { 0x00C30FFF, 0x00040006, 0x0 },
45 { 0x80AAAFFF, 0x000B0000, 0x0 },
46 { 0x00FFFFFF, 0x0005000A, 0x0 },
47 { 0x00D75FFF, 0x000C0004, 0x0 },
48 { 0x80C30FFF, 0x000B0000, 0x0 },
49 { 0x00FFFFFF, 0x00040006, 0x0 },
50 { 0x80D75FFF, 0x000B0000, 0x0 },
45244b87
ED		 51};
52
10122051 53static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
f8896f5d
DW		 54 { 0x00FFFFFF, 0x0007000E, 0x0 },
55 { 0x00D75FFF, 0x000F000A, 0x0 },
56 { 0x00C30FFF, 0x00060006, 0x0 },
57 { 0x00AAAFFF, 0x001E0000, 0x0 },
58 { 0x00FFFFFF, 0x000F000A, 0x0 },
59 { 0x00D75FFF, 0x00160004, 0x0 },
60 { 0x00C30FFF, 0x001E0000, 0x0 },
61 { 0x00FFFFFF, 0x00060006, 0x0 },
62 { 0x00D75FFF, 0x001E0000, 0x0 },
6acab15a
PZ		 63};
64
10122051
JN		 65static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
66 /* Idx NT mV d T mV d db */
f8896f5d
DW		 67 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
68 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
69 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
70 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
71 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
72 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
73 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
74 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
75 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
76 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
77 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
78 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
45244b87
ED		 79};
80
10122051 81static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
f8896f5d
DW		 82 { 0x00FFFFFF, 0x00000012, 0x0 },
83 { 0x00EBAFFF, 0x00020011, 0x0 },
84 { 0x00C71FFF, 0x0006000F, 0x0 },
85 { 0x00AAAFFF, 0x000E000A, 0x0 },
86 { 0x00FFFFFF, 0x00020011, 0x0 },
87 { 0x00DB6FFF, 0x0005000F, 0x0 },
88 { 0x00BEEFFF, 0x000A000C, 0x0 },
89 { 0x00FFFFFF, 0x0005000F, 0x0 },
90 { 0x00DB6FFF, 0x000A000C, 0x0 },
300644c7
PZ		 91};
92
10122051 93static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
f8896f5d
DW		 94 { 0x00FFFFFF, 0x0007000E, 0x0 },
95 { 0x00D75FFF, 0x000E000A, 0x0 },
96 { 0x00BEFFFF, 0x00140006, 0x0 },
97 { 0x80B2CFFF, 0x001B0002, 0x0 },
98 { 0x00FFFFFF, 0x000E000A, 0x0 },
99 { 0x00DB6FFF, 0x00160005, 0x0 },
100 { 0x80C71FFF, 0x001A0002, 0x0 },
101 { 0x00F7DFFF, 0x00180004, 0x0 },
102 { 0x80D75FFF, 0x001B0002, 0x0 },
e58623cb
AR		 103};
104
10122051 105static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
f8896f5d
DW		 106 { 0x00FFFFFF, 0x0001000E, 0x0 },
107 { 0x00D75FFF, 0x0004000A, 0x0 },
108 { 0x00C30FFF, 0x00070006, 0x0 },
109 { 0x00AAAFFF, 0x000C0000, 0x0 },
110 { 0x00FFFFFF, 0x0004000A, 0x0 },
111 { 0x00D75FFF, 0x00090004, 0x0 },
112 { 0x00C30FFF, 0x000C0000, 0x0 },
113 { 0x00FFFFFF, 0x00070006, 0x0 },
114 { 0x00D75FFF, 0x000C0000, 0x0 },
e58623cb
AR		 115};
116
10122051
JN		 117static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
118 /* Idx NT mV d T mV df db */
f8896f5d
DW		 119 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
120 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
121 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
122 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
123 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
124 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
125 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
126 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
127 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
128 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
a26aa8ba
DL		 129};
130
5f8b2531 131/* Skylake H and S */
7f88e3af 132static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
f8896f5d
DW		 133 { 0x00002016, 0x000000A0, 0x0 },
134 { 0x00005012, 0x0000009B, 0x0 },
135 { 0x00007011, 0x00000088, 0x0 },
136 { 0x00009010, 0x000000C7, 0x0 },
137 { 0x00002016, 0x0000009B, 0x0 },
138 { 0x00005012, 0x00000088, 0x0 },
139 { 0x00007011, 0x000000C7, 0x0 },
140 { 0x00002016, 0x000000DF, 0x0 },
141 { 0x00005012, 0x000000C7, 0x0 },
7f88e3af
DL		 142};
143
f8896f5d
DW		 144/* Skylake U */
145static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
5f8b2531 146 { 0x0000201B, 0x000000A2, 0x0 },
f8896f5d
DW		 147 { 0x00005012, 0x00000088, 0x0 },
148 { 0x00007011, 0x00000087, 0x0 },
5f8b2531
RV		 149 { 0x80009010, 0x000000C7, 0x1 }, /* Uses I_boost level 0x1 */
150 { 0x0000201B, 0x0000009D, 0x0 },
f8896f5d
DW		 151 { 0x00005012, 0x000000C7, 0x0 },
152 { 0x00007011, 0x000000C7, 0x0 },
153 { 0x00002016, 0x00000088, 0x0 },
154 { 0x00005012, 0x000000C7, 0x0 },
155};
156
5f8b2531
RV		 157/* Skylake Y */
158static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
f8896f5d
DW		 159 { 0x00000018, 0x000000A2, 0x0 },
160 { 0x00005012, 0x00000088, 0x0 },
161 { 0x00007011, 0x00000087, 0x0 },
5f8b2531 162 { 0x80009010, 0x000000C7, 0x3 }, /* Uses I_boost level 0x3 */
f8896f5d
DW		 163 { 0x00000018, 0x0000009D, 0x0 },
164 { 0x00005012, 0x000000C7, 0x0 },
165 { 0x00007011, 0x000000C7, 0x0 },
166 { 0x00000018, 0x00000088, 0x0 },
167 { 0x00005012, 0x000000C7, 0x0 },
168};
169
170/*
5f8b2531 171 * Skylake H and S
f8896f5d
DW		 172 * eDP 1.4 low vswing translation parameters
173 */
7ad14a29 174static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
f8896f5d
DW		 175 { 0x00000018, 0x000000A8, 0x0 },
176 { 0x00004013, 0x000000A9, 0x0 },
177 { 0x00007011, 0x000000A2, 0x0 },
178 { 0x00009010, 0x0000009C, 0x0 },
179 { 0x00000018, 0x000000A9, 0x0 },
180 { 0x00006013, 0x000000A2, 0x0 },
181 { 0x00007011, 0x000000A6, 0x0 },
182 { 0x00000018, 0x000000AB, 0x0 },
183 { 0x00007013, 0x0000009F, 0x0 },
184 { 0x00000018, 0x000000DF, 0x0 },
185};
186
187/*
188 * Skylake U
189 * eDP 1.4 low vswing translation parameters
190 */
191static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
192 { 0x00000018, 0x000000A8, 0x0 },
193 { 0x00004013, 0x000000A9, 0x0 },
194 { 0x00007011, 0x000000A2, 0x0 },
195 { 0x00009010, 0x0000009C, 0x0 },
196 { 0x00000018, 0x000000A9, 0x0 },
197 { 0x00006013, 0x000000A2, 0x0 },
198 { 0x00007011, 0x000000A6, 0x0 },
199 { 0x00002016, 0x000000AB, 0x0 },
200 { 0x00005013, 0x0000009F, 0x0 },
201 { 0x00000018, 0x000000DF, 0x0 },
7ad14a29
SJ		 202};
203
f8896f5d 204/*
5f8b2531 205 * Skylake Y
f8896f5d
DW		 206 * eDP 1.4 low vswing translation parameters
207 */
5f8b2531 208static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
f8896f5d
DW		 209 { 0x00000018, 0x000000A8, 0x0 },
210 { 0x00004013, 0x000000AB, 0x0 },
211 { 0x00007011, 0x000000A4, 0x0 },
212 { 0x00009010, 0x000000DF, 0x0 },
213 { 0x00000018, 0x000000AA, 0x0 },
214 { 0x00006013, 0x000000A4, 0x0 },
215 { 0x00007011, 0x0000009D, 0x0 },
216 { 0x00000018, 0x000000A0, 0x0 },
217 { 0x00006012, 0x000000DF, 0x0 },
218 { 0x00000018, 0x0000008A, 0x0 },
219};
7ad14a29 220
5f8b2531 221/* Skylake U, H and S */
7f88e3af 222static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
f8896f5d
DW		 223 { 0x00000018, 0x000000AC, 0x0 },
224 { 0x00005012, 0x0000009D, 0x0 },
225 { 0x00007011, 0x00000088, 0x0 },
226 { 0x00000018, 0x000000A1, 0x0 },
227 { 0x00000018, 0x00000098, 0x0 },
228 { 0x00004013, 0x00000088, 0x0 },
229 { 0x00006012, 0x00000087, 0x0 },
230 { 0x00000018, 0x000000DF, 0x0 },
231 { 0x00003015, 0x00000087, 0x0 }, /* Default */
232 { 0x00003015, 0x000000C7, 0x0 },
233 { 0x00000018, 0x000000C7, 0x0 },
234};
235
5f8b2531
RV		 236/* Skylake Y */
237static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
f8896f5d
DW		 238 { 0x00000018, 0x000000A1, 0x0 },
239 { 0x00005012, 0x000000DF, 0x0 },
240 { 0x00007011, 0x00000084, 0x0 },
241 { 0x00000018, 0x000000A4, 0x0 },
242 { 0x00000018, 0x0000009D, 0x0 },
243 { 0x00004013, 0x00000080, 0x0 },
244 { 0x00006013, 0x000000C7, 0x0 },
245 { 0x00000018, 0x0000008A, 0x0 },
246 { 0x00003015, 0x000000C7, 0x0 }, /* Default */
5f8b2531 247 { 0x80003015, 0x000000C7, 0x7 }, /* Uses I_boost level 0x7 */
f8896f5d 248 { 0x00000018, 0x000000C7, 0x0 },
7f88e3af
DL		 249};
250
96fb9f9b
VK		 251struct bxt_ddi_buf_trans {
252 u32 margin; /* swing value */
253 u32 scale; /* scale value */
254 u32 enable; /* scale enable */
255 u32 deemphasis;
256 bool default_index; /* true if the entry represents default value */
257};
258
96fb9f9b
VK		 259static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
260 /* Idx NT mV diff db */
fe4c63c8
ID		 261 { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */
262 { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
263 { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */
264 { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
265 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
266 { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
267 { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */
268 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
269 { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
f8896f5d 270 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
96fb9f9b
VK		 271};
272
d9d7000d
SJ		 273static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
274 /* Idx NT mV diff db */
275 { 26, 0, 0, 128, false }, /* 0: 200 0 */
276 { 38, 0, 0, 112, false }, /* 1: 200 1.5 */
277 { 48, 0, 0, 96, false }, /* 2: 200 4 */
278 { 54, 0, 0, 69, false }, /* 3: 200 6 */
279 { 32, 0, 0, 128, false }, /* 4: 250 0 */
280 { 48, 0, 0, 104, false }, /* 5: 250 1.5 */
281 { 54, 0, 0, 85, false }, /* 6: 250 4 */
282 { 43, 0, 0, 128, false }, /* 7: 300 0 */
283 { 54, 0, 0, 101, false }, /* 8: 300 1.5 */
284 { 48, 0, 0, 128, false }, /* 9: 300 0 */
285};
286
96fb9f9b
VK		 287/* BSpec has 2 recommended values - entries 0 and 8.
288 * Using the entry with higher vswing.
289 */
290static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
291 /* Idx NT mV diff db */
fe4c63c8
ID		 292 { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */
293 { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
294 { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */
295 { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
296 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
297 { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
298 { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */
299 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
300 { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
96fb9f9b
VK		 301 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
302};
303
f8896f5d
DW		 304static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
305 enum port port, int type);
306
a1e6ad66
ID		 307static void ddi_get_encoder_port(struct intel_encoder *intel_encoder,
308 struct intel_digital_port **dig_port,
309 enum port *port)
fc914639 310{
0bdee30e 311 struct drm_encoder *encoder = &intel_encoder->base;
fc914639
PZ		 312 int type = intel_encoder->type;
313
0e32b39c 314 if (type == INTEL_OUTPUT_DP_MST) {
a1e6ad66
ID		 315 *dig_port = enc_to_mst(encoder)->primary;
316 *port = (*dig_port)->port;
0e32b39c 317 } else if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
00c09d70 318 type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
a1e6ad66
ID		 319 *dig_port = enc_to_dig_port(encoder);
320 *port = (*dig_port)->port;
fc914639 321 } else if (type == INTEL_OUTPUT_ANALOG) {
a1e6ad66
ID		 322 *dig_port = NULL;
323 *port = PORT_E;
fc914639 324 } else {
85b98a4c 325 WARN(1, "Invalid DDI encoder type %d\n", type);
fc914639
PZ		 326 }
327}
328
a1e6ad66
ID		 329enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
330{
331 struct intel_digital_port *dig_port;
332 enum port port;
333
334 ddi_get_encoder_port(intel_encoder, &dig_port, &port);
335
336 return port;
337}
338
ce3b7e9b
DL		 339static bool
340intel_dig_port_supports_hdmi(const struct intel_digital_port *intel_dig_port)
341{
342 return intel_dig_port->hdmi.hdmi_reg;
343}
344
f8896f5d
DW		 345static const struct ddi_buf_trans *skl_get_buf_trans_dp(struct drm_device *dev,
346 int *n_entries)
347{
f8896f5d 348 const struct ddi_buf_trans *ddi_translations;
f8896f5d 349
5f8b2531
RV		 350 if (IS_SKL_ULX(dev)) {
351 ddi_translations = skl_y_ddi_translations_dp;
352 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
f8896f5d
DW		 353 } else if (IS_SKL_ULT(dev)) {
354 ddi_translations = skl_u_ddi_translations_dp;
355 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
356 } else {
357 ddi_translations = skl_ddi_translations_dp;
358 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
359 }
360
361 return ddi_translations;
362}
363
364static const struct ddi_buf_trans *skl_get_buf_trans_edp(struct drm_device *dev,
365 int *n_entries)
366{
367 struct drm_i915_private *dev_priv = dev->dev_private;
368 const struct ddi_buf_trans *ddi_translations;
f8896f5d 369
5f8b2531 370 if (IS_SKL_ULX(dev)) {
f8896f5d 371 if (dev_priv->edp_low_vswing) {
5f8b2531
RV		 372 ddi_translations = skl_y_ddi_translations_edp;
373 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
f8896f5d 374 } else {
5f8b2531
RV		 375 ddi_translations = skl_y_ddi_translations_dp;
376 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
f8896f5d
DW		 377 }
378 } else if (IS_SKL_ULT(dev)) {
379 if (dev_priv->edp_low_vswing) {
380 ddi_translations = skl_u_ddi_translations_edp;
381 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
382 } else {
383 ddi_translations = skl_u_ddi_translations_dp;
384 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
385 }
386 } else {
387 if (dev_priv->edp_low_vswing) {
388 ddi_translations = skl_ddi_translations_edp;
389 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
390 } else {
391 ddi_translations = skl_ddi_translations_dp;
392 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
393 }
394 }
395
396 return ddi_translations;
397}
398
399static const struct ddi_buf_trans *
400skl_get_buf_trans_hdmi(struct drm_device *dev,
401 int *n_entries)
402{
f8896f5d 403 const struct ddi_buf_trans *ddi_translations;
f8896f5d 404
5f8b2531
RV		 405 if (IS_SKL_ULX(dev)) {
406 ddi_translations = skl_y_ddi_translations_hdmi;
407 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
f8896f5d
DW		 408 } else {
409 ddi_translations = skl_ddi_translations_hdmi;
410 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
411 }
412
413 return ddi_translations;
414}
415
e58623cb
AR		 416/*
417 * Starting with Haswell, DDI port buffers must be programmed with correct
418 * values in advance. The buffer values are different for FDI and DP modes,
45244b87
ED		 419 * but the HDMI/DVI fields are shared among those. So we program the DDI
420 * in either FDI or DP modes only, as HDMI connections will work with both
421 * of those
422 */
faa0cdbe
ID		 423static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port,
424 bool supports_hdmi)
45244b87
ED		 425{
426 struct drm_i915_private *dev_priv = dev->dev_private;
75067dde 427 u32 iboost_bit = 0;
7ff44670 428 int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry,
7ad14a29 429 size;
6acab15a 430 int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
10122051
JN		 431 const struct ddi_buf_trans *ddi_translations_fdi;
432 const struct ddi_buf_trans *ddi_translations_dp;
433 const struct ddi_buf_trans *ddi_translations_edp;
434 const struct ddi_buf_trans *ddi_translations_hdmi;
435 const struct ddi_buf_trans *ddi_translations;
e58623cb 436
96fb9f9b 437 if (IS_BROXTON(dev)) {
faa0cdbe 438 if (!supports_hdmi)
96fb9f9b
VK		 439 return;
440
441 /* Vswing programming for HDMI */
442 bxt_ddi_vswing_sequence(dev, hdmi_level, port,
443 INTEL_OUTPUT_HDMI);
444 return;
445 } else if (IS_SKYLAKE(dev)) {
c30400fc 446 ddi_translations_fdi = NULL;
f8896f5d
DW		 447 ddi_translations_dp =
448 skl_get_buf_trans_dp(dev, &n_dp_entries);
449 ddi_translations_edp =
450 skl_get_buf_trans_edp(dev, &n_edp_entries);
451 ddi_translations_hdmi =
452 skl_get_buf_trans_hdmi(dev, &n_hdmi_entries);
453 hdmi_default_entry = 8;
75067dde
AK		 454 /* If we're boosting the current, set bit 31 of trans1 */
455 if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level ||
456 dev_priv->vbt.ddi_port_info[port].dp_boost_level)
457 iboost_bit = 1<<31;
7f88e3af 458 } else if (IS_BROADWELL(dev)) {
e58623cb
AR		 459 ddi_translations_fdi = bdw_ddi_translations_fdi;
460 ddi_translations_dp = bdw_ddi_translations_dp;
300644c7 461 ddi_translations_edp = bdw_ddi_translations_edp;
a26aa8ba 462 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
7ad14a29
SJ		 463 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
464 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 465 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
7ff44670 466 hdmi_default_entry = 7;
e58623cb
AR		 467 } else if (IS_HASWELL(dev)) {
468 ddi_translations_fdi = hsw_ddi_translations_fdi;
469 ddi_translations_dp = hsw_ddi_translations_dp;
300644c7 470 ddi_translations_edp = hsw_ddi_translations_dp;
a26aa8ba 471 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
7ad14a29 472 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
10122051 473 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
7ff44670 474 hdmi_default_entry = 6;
e58623cb
AR		 475 } else {
476 WARN(1, "ddi translation table missing\n");
300644c7 477 ddi_translations_edp = bdw_ddi_translations_dp;
e58623cb
AR		 478 ddi_translations_fdi = bdw_ddi_translations_fdi;
479 ddi_translations_dp = bdw_ddi_translations_dp;
a26aa8ba 480 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
7ad14a29
SJ		 481 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
482 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 483 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
7ff44670 484 hdmi_default_entry = 7;
e58623cb
AR		 485 }
486
300644c7
PZ		 487 switch (port) {
488 case PORT_A:
489 ddi_translations = ddi_translations_edp;
7ad14a29 490 size = n_edp_entries;
300644c7
PZ		 491 break;
492 case PORT_B:
493 case PORT_C:
300644c7 494 ddi_translations = ddi_translations_dp;
7ad14a29 495 size = n_dp_entries;
300644c7 496 break;
77d8d009 497 case PORT_D:
7ad14a29 498 if (intel_dp_is_edp(dev, PORT_D)) {
77d8d009 499 ddi_translations = ddi_translations_edp;
7ad14a29
SJ		 500 size = n_edp_entries;
501 } else {
77d8d009 502 ddi_translations = ddi_translations_dp;
7ad14a29
SJ		 503 size = n_dp_entries;
504 }
77d8d009 505 break;
300644c7 506 case PORT_E:
7f88e3af
DL		 507 if (ddi_translations_fdi)
508 ddi_translations = ddi_translations_fdi;
509 else
510 ddi_translations = ddi_translations_dp;
7ad14a29 511 size = n_dp_entries;
300644c7
PZ		 512 break;
513 default:
514 BUG();
515 }
45244b87 516
9712e688
VS		 517 for (i = 0; i < size; i++) {
518 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
519 ddi_translations[i].trans1 | iboost_bit);
520 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
521 ddi_translations[i].trans2);
45244b87 522 }
ce4dd49e 523
faa0cdbe 524 if (!supports_hdmi)
ce3b7e9b
DL		 525 return;
526
ce4dd49e
DL		 527 /* Choose a good default if VBT is badly populated */
528 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
529 hdmi_level >= n_hdmi_entries)
7ff44670 530 hdmi_level = hdmi_default_entry;
ce4dd49e 531
6acab15a 532 /* Entry 9 is for HDMI: */
9712e688
VS		 533 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
534 ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
535 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
536 ddi_translations_hdmi[hdmi_level].trans2);
45244b87
ED		 537}
538
539/* Program DDI buffers translations for DP. By default, program ports A-D in DP
540 * mode and port E for FDI.
541 */
542void intel_prepare_ddi(struct drm_device *dev)
543{
faa0cdbe 544 struct intel_encoder *intel_encoder;
b403745c 545 bool visited[I915_MAX_PORTS] = { 0, };
45244b87 546
0d536cb4
PZ		 547 if (!HAS_DDI(dev))
548 return;
45244b87 549
faa0cdbe
ID		 550 for_each_intel_encoder(dev, intel_encoder) {
551 struct intel_digital_port *intel_dig_port;
552 enum port port;
553 bool supports_hdmi;
554
555 ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
556
557 if (visited[port])
b403745c
DL		 558 continue;
559
faa0cdbe
ID		 560 supports_hdmi = intel_dig_port &&
561 intel_dig_port_supports_hdmi(intel_dig_port);
562
563 intel_prepare_ddi_buffers(dev, port, supports_hdmi);
564 visited[port] = true;
b403745c 565 }
45244b87 566}
c82e4d26 567
248138b5
PZ		 568static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
569 enum port port)
570{
571 uint32_t reg = DDI_BUF_CTL(port);
572 int i;
573
3449ca85 574 for (i = 0; i < 16; i++) {
248138b5
PZ		 575 udelay(1);
576 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
577 return;
578 }
579 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
580}
c82e4d26
ED		 581
582/* Starting with Haswell, different DDI ports can work in FDI mode for
583 * connection to the PCH-located connectors. For this, it is necessary to train
584 * both the DDI port and PCH receiver for the desired DDI buffer settings.
585 *
586 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
587 * please note that when FDI mode is active on DDI E, it shares 2 lines with
588 * DDI A (which is used for eDP)
589 */
590
591void hsw_fdi_link_train(struct drm_crtc *crtc)
592{
593 struct drm_device *dev = crtc->dev;
594 struct drm_i915_private *dev_priv = dev->dev_private;
595 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
04945641 596 u32 temp, i, rx_ctl_val;
c82e4d26 597
04945641
PZ		 598 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
599 * mode set "sequence for CRT port" document:
600 * - TP1 to TP2 time with the default value
601 * - FDI delay to 90h
8693a824
DL		 602 *
603 * WaFDIAutoLinkSetTimingOverrride:hsw
04945641
PZ		 604 */
605 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
606 FDI_RX_PWRDN_LANE0_VAL(2) |
607 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
608
609 /* Enable the PCH Receiver FDI PLL */
3e68320e 610 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
33d29b14 611 FDI_RX_PLL_ENABLE |
6e3c9717 612 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
04945641
PZ		 613 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
614 POSTING_READ(_FDI_RXA_CTL);
615 udelay(220);
616
617 /* Switch from Rawclk to PCDclk */
618 rx_ctl_val |= FDI_PCDCLK;
619 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
620
621 /* Configure Port Clock Select */
6e3c9717
ACO		 622 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
623 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
04945641
PZ		 624
625 /* Start the training iterating through available voltages and emphasis,
626 * testing each value twice. */
10122051 627 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
c82e4d26
ED		 628 /* Configure DP_TP_CTL with auto-training */
629 I915_WRITE(DP_TP_CTL(PORT_E),
630 DP_TP_CTL_FDI_AUTOTRAIN |
631 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
632 DP_TP_CTL_LINK_TRAIN_PAT1 |
633 DP_TP_CTL_ENABLE);
634
876a8cdf
DL		 635 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
636 * DDI E does not support port reversal, the functionality is
637 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
638 * port reversal bit */
c82e4d26 639 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641 640 DDI_BUF_CTL_ENABLE |
6e3c9717 641 ((intel_crtc->config->fdi_lanes - 1) << 1) |
c5fe6a06 642 DDI_BUF_TRANS_SELECT(i / 2));
04945641 643 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 644
645 udelay(600);
646
04945641
PZ		 647 /* Program PCH FDI Receiver TU */
648 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
649
650 /* Enable PCH FDI Receiver with auto-training */
651 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
652 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
653 POSTING_READ(_FDI_RXA_CTL);
654
655 /* Wait for FDI receiver lane calibration */
656 udelay(30);
657
658 /* Unset FDI_RX_MISC pwrdn lanes */
659 temp = I915_READ(_FDI_RXA_MISC);
660 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
661 I915_WRITE(_FDI_RXA_MISC, temp);
662 POSTING_READ(_FDI_RXA_MISC);
663
664 /* Wait for FDI auto training time */
665 udelay(5);
c82e4d26
ED		 666
667 temp = I915_READ(DP_TP_STATUS(PORT_E));
668 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 669 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
c82e4d26
ED		 670
671 /* Enable normal pixel sending for FDI */
672 I915_WRITE(DP_TP_CTL(PORT_E),
04945641
PZ		 673 DP_TP_CTL_FDI_AUTOTRAIN |
674 DP_TP_CTL_LINK_TRAIN_NORMAL |
675 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
676 DP_TP_CTL_ENABLE);
c82e4d26 677
04945641 678 return;
c82e4d26 679 }
04945641 680
248138b5
PZ		 681 temp = I915_READ(DDI_BUF_CTL(PORT_E));
682 temp &= ~DDI_BUF_CTL_ENABLE;
683 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
684 POSTING_READ(DDI_BUF_CTL(PORT_E));
685
04945641 686 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
248138b5
PZ		 687 temp = I915_READ(DP_TP_CTL(PORT_E));
688 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
689 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
690 I915_WRITE(DP_TP_CTL(PORT_E), temp);
691 POSTING_READ(DP_TP_CTL(PORT_E));
692
693 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
04945641
PZ		 694
695 rx_ctl_val &= ~FDI_RX_ENABLE;
696 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
248138b5 697 POSTING_READ(_FDI_RXA_CTL);
04945641
PZ		 698
699 /* Reset FDI_RX_MISC pwrdn lanes */
700 temp = I915_READ(_FDI_RXA_MISC);
701 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
702 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
703 I915_WRITE(_FDI_RXA_MISC, temp);
248138b5 704 POSTING_READ(_FDI_RXA_MISC);
c82e4d26
ED		 705 }
706
04945641 707 DRM_ERROR("FDI link training failed!\n");
c82e4d26 708}
0e72a5b5 709
44905a27
DA		 710void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
711{
712 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
713 struct intel_digital_port *intel_dig_port =
714 enc_to_dig_port(&encoder->base);
715
716 intel_dp->DP = intel_dig_port->saved_port_bits |
c5fe6a06 717 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
901c2daf 718 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
44905a27
DA		 719}
720
8d9ddbcb
PZ		 721static struct intel_encoder *
722intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
723{
724 struct drm_device *dev = crtc->dev;
725 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
726 struct intel_encoder *intel_encoder, *ret = NULL;
727 int num_encoders = 0;
728
729 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
730 ret = intel_encoder;
731 num_encoders++;
732 }
733
734 if (num_encoders != 1)
84f44ce7
VS		 735 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
736 pipe_name(intel_crtc->pipe));
8d9ddbcb
PZ		 737
738 BUG_ON(ret == NULL);
739 return ret;
740}
741
bcddf610 742struct intel_encoder *
3165c074 743intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
d0737e1d 744{
3165c074
ACO		 745 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
746 struct intel_encoder *ret = NULL;
747 struct drm_atomic_state *state;
da3ced29
ACO		 748 struct drm_connector *connector;
749 struct drm_connector_state *connector_state;
d0737e1d 750 int num_encoders = 0;
3165c074 751 int i;
d0737e1d 752
3165c074
ACO		 753 state = crtc_state->base.state;
754
da3ced29
ACO		 755 for_each_connector_in_state(state, connector, connector_state, i) {
756 if (connector_state->crtc != crtc_state->base.crtc)
3165c074
ACO		 757 continue;
758
da3ced29 759 ret = to_intel_encoder(connector_state->best_encoder);
3165c074 760 num_encoders++;
d0737e1d
ACO		 761 }
762
763 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
764 pipe_name(crtc->pipe));
765
766 BUG_ON(ret == NULL);
767 return ret;
768}
769
1c0b85c5 770#define LC_FREQ 2700
27893390 771#define LC_FREQ_2K U64_C(LC_FREQ * 2000)
1c0b85c5
DL		 772
773#define P_MIN 2
774#define P_MAX 64
775#define P_INC 2
776
777/* Constraints for PLL good behavior */
778#define REF_MIN 48
779#define REF_MAX 400
780#define VCO_MIN 2400
781#define VCO_MAX 4800
782
27893390
DL		 783#define abs_diff(a, b) ({ \
784 typeof(a) __a = (a); \
785 typeof(b) __b = (b); \
786 (void) (&__a == &__b); \
787 __a > __b ? (__a - __b) : (__b - __a); })
1c0b85c5 788
63582983 789struct hsw_wrpll_rnp {
1c0b85c5
DL		 790 unsigned p, n2, r2;
791};
792
63582983 793static unsigned hsw_wrpll_get_budget_for_freq(int clock)
6441ab5f 794{
1c0b85c5
DL		 795 unsigned budget;
796
797 switch (clock) {
798 case 25175000:
799 case 25200000:
800 case 27000000:
801 case 27027000:
802 case 37762500:
803 case 37800000:
804 case 40500000:
805 case 40541000:
806 case 54000000:
807 case 54054000:
808 case 59341000:
809 case 59400000:
810 case 72000000:
811 case 74176000:
812 case 74250000:
813 case 81000000:
814 case 81081000:
815 case 89012000:
816 case 89100000:
817 case 108000000:
818 case 108108000:
819 case 111264000:
820 case 111375000:
821 case 148352000:
822 case 148500000:
823 case 162000000:
824 case 162162000:
825 case 222525000:
826 case 222750000:
827 case 296703000:
828 case 297000000:
829 budget = 0;
830 break;
831 case 233500000:
832 case 245250000:
833 case 247750000:
834 case 253250000:
835 case 298000000:
836 budget = 1500;
837 break;
838 case 169128000:
839 case 169500000:
840 case 179500000:
841 case 202000000:
842 budget = 2000;
843 break;
844 case 256250000:
845 case 262500000:
846 case 270000000:
847 case 272500000:
848 case 273750000:
849 case 280750000:
850 case 281250000:
851 case 286000000:
852 case 291750000:
853 budget = 4000;
854 break;
855 case 267250000:
856 case 268500000:
857 budget = 5000;
858 break;
859 default:
860 budget = 1000;
861 break;
862 }
6441ab5f 863
1c0b85c5
DL		 864 return budget;
865}
866
63582983
DL		 867static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget,
868 unsigned r2, unsigned n2, unsigned p,
869 struct hsw_wrpll_rnp *best)
1c0b85c5
DL		 870{
871 uint64_t a, b, c, d, diff, diff_best;
6441ab5f 872
1c0b85c5
DL		 873 /* No best (r,n,p) yet */
874 if (best->p == 0) {
875 best->p = p;
876 best->n2 = n2;
877 best->r2 = r2;
878 return;
879 }
6441ab5f 880
1c0b85c5
DL		 881 /*
882 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
883 * freq2k.
884 *
885 * delta = 1e6 *
886 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
887 * freq2k;
888 *
889 * and we would like delta <= budget.
890 *
891 * If the discrepancy is above the PPM-based budget, always prefer to
892 * improve upon the previous solution. However, if you're within the
893 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
894 */
895 a = freq2k * budget * p * r2;
896 b = freq2k * budget * best->p * best->r2;
27893390
DL		 897 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
898 diff_best = abs_diff(freq2k * best->p * best->r2,
899 LC_FREQ_2K * best->n2);
1c0b85c5
DL		 900 c = 1000000 * diff;
901 d = 1000000 * diff_best;
902
903 if (a < c && b < d) {
904 /* If both are above the budget, pick the closer */
905 if (best->p * best->r2 * diff < p * r2 * diff_best) {
906 best->p = p;
907 best->n2 = n2;
908 best->r2 = r2;
909 }
910 } else if (a >= c && b < d) {
911 /* If A is below the threshold but B is above it? Update. */
912 best->p = p;
913 best->n2 = n2;
914 best->r2 = r2;
915 } else if (a >= c && b >= d) {
916 /* Both are below the limit, so pick the higher n2/(r2*r2) */
917 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
918 best->p = p;
919 best->n2 = n2;
920 best->r2 = r2;
921 }
922 }
923 /* Otherwise a < c && b >= d, do nothing */
924}
925
63582983 926static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, int reg)
11578553
JB		 927{
928 int refclk = LC_FREQ;
929 int n, p, r;
930 u32 wrpll;
931
932 wrpll = I915_READ(reg);
114fe488
DV		 933 switch (wrpll & WRPLL_PLL_REF_MASK) {
934 case WRPLL_PLL_SSC:
935 case WRPLL_PLL_NON_SSC:
11578553
JB		 936 /*
937 * We could calculate spread here, but our checking
938 * code only cares about 5% accuracy, and spread is a max of
939 * 0.5% downspread.
940 */
941 refclk = 135;
942 break;
114fe488 943 case WRPLL_PLL_LCPLL:
11578553
JB		 944 refclk = LC_FREQ;
945 break;
946 default:
947 WARN(1, "bad wrpll refclk\n");
948 return 0;
949 }
950
951 r = wrpll & WRPLL_DIVIDER_REF_MASK;
952 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
953 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
954
20f0ec16
JB		 955 /* Convert to KHz, p & r have a fixed point portion */
956 return (refclk * n * 100) / (p * r);
11578553
JB		 957}
958
540e732c
S		 959static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
960 uint32_t dpll)
961{
962 uint32_t cfgcr1_reg, cfgcr2_reg;
963 uint32_t cfgcr1_val, cfgcr2_val;
964 uint32_t p0, p1, p2, dco_freq;
965
966 cfgcr1_reg = GET_CFG_CR1_REG(dpll);
967 cfgcr2_reg = GET_CFG_CR2_REG(dpll);
968
969 cfgcr1_val = I915_READ(cfgcr1_reg);
970 cfgcr2_val = I915_READ(cfgcr2_reg);
971
972 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
973 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
974
975 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
976 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
977 else
978 p1 = 1;
979
980
981 switch (p0) {
982 case DPLL_CFGCR2_PDIV_1:
983 p0 = 1;
984 break;
985 case DPLL_CFGCR2_PDIV_2:
986 p0 = 2;
987 break;
988 case DPLL_CFGCR2_PDIV_3:
989 p0 = 3;
990 break;
991 case DPLL_CFGCR2_PDIV_7:
992 p0 = 7;
993 break;
994 }
995
996 switch (p2) {
997 case DPLL_CFGCR2_KDIV_5:
998 p2 = 5;
999 break;
1000 case DPLL_CFGCR2_KDIV_2:
1001 p2 = 2;
1002 break;
1003 case DPLL_CFGCR2_KDIV_3:
1004 p2 = 3;
1005 break;
1006 case DPLL_CFGCR2_KDIV_1:
1007 p2 = 1;
1008 break;
1009 }
1010
1011 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
1012
1013 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
1014 1000) / 0x8000;
1015
1016 return dco_freq / (p0 * p1 * p2 * 5);
1017}
1018
398a017e
VS		 1019static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1020{
1021 int dotclock;
1022
1023 if (pipe_config->has_pch_encoder)
1024 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1025 &pipe_config->fdi_m_n);
1026 else if (pipe_config->has_dp_encoder)
1027 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1028 &pipe_config->dp_m_n);
1029 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1030 dotclock = pipe_config->port_clock * 2 / 3;
1031 else
1032 dotclock = pipe_config->port_clock;
1033
1034 if (pipe_config->pixel_multiplier)
1035 dotclock /= pipe_config->pixel_multiplier;
1036
1037 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1038}
540e732c
S		 1039
1040static void skl_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1041 struct intel_crtc_state *pipe_config)
540e732c
S		 1042{
1043 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
540e732c
S		 1044 int link_clock = 0;
1045 uint32_t dpll_ctl1, dpll;
1046
134ffa44 1047 dpll = pipe_config->ddi_pll_sel;
540e732c
S		 1048
1049 dpll_ctl1 = I915_READ(DPLL_CTRL1);
1050
1051 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
1052 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
1053 } else {
71cd8423
DL		 1054 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
1055 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
540e732c
S		 1056
1057 switch (link_clock) {
71cd8423 1058 case DPLL_CTRL1_LINK_RATE_810:
540e732c
S		 1059 link_clock = 81000;
1060 break;
71cd8423 1061 case DPLL_CTRL1_LINK_RATE_1080:
a8f3ef61
SJ		 1062 link_clock = 108000;
1063 break;
71cd8423 1064 case DPLL_CTRL1_LINK_RATE_1350:
540e732c
S		 1065 link_clock = 135000;
1066 break;
71cd8423 1067 case DPLL_CTRL1_LINK_RATE_1620:
a8f3ef61
SJ		 1068 link_clock = 162000;
1069 break;
71cd8423 1070 case DPLL_CTRL1_LINK_RATE_2160:
a8f3ef61
SJ		 1071 link_clock = 216000;
1072 break;
71cd8423 1073 case DPLL_CTRL1_LINK_RATE_2700:
540e732c
S		 1074 link_clock = 270000;
1075 break;
1076 default:
1077 WARN(1, "Unsupported link rate\n");
1078 break;
1079 }
1080 link_clock *= 2;
1081 }
1082
1083 pipe_config->port_clock = link_clock;
1084
398a017e 1085 ddi_dotclock_get(pipe_config);
540e732c
S		 1086}
1087
3d51278a 1088static void hsw_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1089 struct intel_crtc_state *pipe_config)
11578553
JB		 1090{
1091 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
11578553
JB		 1092 int link_clock = 0;
1093 u32 val, pll;
1094
26804afd 1095 val = pipe_config->ddi_pll_sel;
11578553
JB		 1096 switch (val & PORT_CLK_SEL_MASK) {
1097 case PORT_CLK_SEL_LCPLL_810:
1098 link_clock = 81000;
1099 break;
1100 case PORT_CLK_SEL_LCPLL_1350:
1101 link_clock = 135000;
1102 break;
1103 case PORT_CLK_SEL_LCPLL_2700:
1104 link_clock = 270000;
1105 break;
1106 case PORT_CLK_SEL_WRPLL1:
63582983 1107 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
11578553
JB		 1108 break;
1109 case PORT_CLK_SEL_WRPLL2:
63582983 1110 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
11578553
JB		 1111 break;
1112 case PORT_CLK_SEL_SPLL:
1113 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1114 if (pll == SPLL_PLL_FREQ_810MHz)
1115 link_clock = 81000;
1116 else if (pll == SPLL_PLL_FREQ_1350MHz)
1117 link_clock = 135000;
1118 else if (pll == SPLL_PLL_FREQ_2700MHz)
1119 link_clock = 270000;
1120 else {
1121 WARN(1, "bad spll freq\n");
1122 return;
1123 }
1124 break;
1125 default:
1126 WARN(1, "bad port clock sel\n");
1127 return;
1128 }
1129
1130 pipe_config->port_clock = link_clock * 2;
1131
398a017e 1132 ddi_dotclock_get(pipe_config);
11578553
JB		 1133}
1134
977bb38d
S		 1135static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
1136 enum intel_dpll_id dpll)
1137{
aa610dcb
ID		 1138 struct intel_shared_dpll *pll;
1139 struct intel_dpll_hw_state *state;
1140 intel_clock_t clock;
1141
1142 /* For DDI ports we always use a shared PLL. */
1143 if (WARN_ON(dpll == DPLL_ID_PRIVATE))
1144 return 0;
1145
1146 pll = &dev_priv->shared_dplls[dpll];
1147 state = &pll->config.hw_state;
1148
1149 clock.m1 = 2;
1150 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1151 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1152 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1153 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1154 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1155 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1156
1157 return chv_calc_dpll_params(100000, &clock);
977bb38d
S		 1158}
1159
1160static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1161 struct intel_crtc_state *pipe_config)
1162{
1163 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1164 enum port port = intel_ddi_get_encoder_port(encoder);
1165 uint32_t dpll = port;
1166
398a017e 1167 pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);
977bb38d 1168
398a017e 1169 ddi_dotclock_get(pipe_config);
977bb38d
S		 1170}
1171
3d51278a 1172void intel_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1173 struct intel_crtc_state *pipe_config)
3d51278a 1174{
22606a18
DL		 1175 struct drm_device *dev = encoder->base.dev;
1176
1177 if (INTEL_INFO(dev)->gen <= 8)
1178 hsw_ddi_clock_get(encoder, pipe_config);
977bb38d 1179 else if (IS_SKYLAKE(dev))
22606a18 1180 skl_ddi_clock_get(encoder, pipe_config);
977bb38d
S		 1181 else if (IS_BROXTON(dev))
1182 bxt_ddi_clock_get(encoder, pipe_config);
3d51278a
DV		 1183}
1184
1c0b85c5 1185static void
d664c0ce
DL		 1186hsw_ddi_calculate_wrpll(int clock /* in Hz */,
1187 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
1c0b85c5
DL		 1188{
1189 uint64_t freq2k;
1190 unsigned p, n2, r2;
63582983 1191 struct hsw_wrpll_rnp best = { 0, 0, 0 };
1c0b85c5
DL		 1192 unsigned budget;
1193
1194 freq2k = clock / 100;
1195
63582983 1196 budget = hsw_wrpll_get_budget_for_freq(clock);
1c0b85c5
DL		 1197
1198 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
1199 * and directly pass the LC PLL to it. */
1200 if (freq2k == 5400000) {
1201 *n2_out = 2;
1202 *p_out = 1;
1203 *r2_out = 2;
1204 return;
1205 }
1206
1207 /*
1208 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
1209 * the WR PLL.
1210 *
1211 * We want R so that REF_MIN <= Ref <= REF_MAX.
1212 * Injecting R2 = 2 * R gives:
1213 * REF_MAX * r2 > LC_FREQ * 2 and
1214 * REF_MIN * r2 < LC_FREQ * 2
1215 *
1216 * Which means the desired boundaries for r2 are:
1217 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
1218 *
1219 */
1220 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
1221 r2 <= LC_FREQ * 2 / REF_MIN;
1222 r2++) {
1223
1224 /*
1225 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
1226 *
1227 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
1228 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
1229 * VCO_MAX * r2 > n2 * LC_FREQ and
1230 * VCO_MIN * r2 < n2 * LC_FREQ)
1231 *
1232 * Which means the desired boundaries for n2 are:
1233 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
1234 */
1235 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
1236 n2 <= VCO_MAX * r2 / LC_FREQ;
1237 n2++) {
1238
1239 for (p = P_MIN; p <= P_MAX; p += P_INC)
63582983
DL		 1240 hsw_wrpll_update_rnp(freq2k, budget,
1241 r2, n2, p, &best);
1c0b85c5
DL		 1242 }
1243 }
6441ab5f 1244
1c0b85c5
DL		 1245 *n2_out = best.n2;
1246 *p_out = best.p;
1247 *r2_out = best.r2;
6441ab5f
PZ		 1248}
1249
0220ab6e 1250static bool
d664c0ce 1251hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 1252 struct intel_crtc_state *crtc_state,
96f3f1f9 1253 struct intel_encoder *intel_encoder)
6441ab5f 1254{
96f3f1f9
VS		 1255 int clock = crtc_state->port_clock;
1256
d664c0ce 1257 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
e0b01be4 1258 struct intel_shared_dpll *pll;
716c2e55 1259 uint32_t val;
1c0b85c5 1260 unsigned p, n2, r2;
6441ab5f 1261
d664c0ce 1262 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
0694001b 1263
114fe488 1264 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
0694001b
PZ		 1265 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
1266 WRPLL_DIVIDER_POST(p);
1267
dd3cd74a
ACO		 1268 memset(&crtc_state->dpll_hw_state, 0,
1269 sizeof(crtc_state->dpll_hw_state));
1270
190f68c5 1271 crtc_state->dpll_hw_state.wrpll = val;
6441ab5f 1272
190f68c5 1273 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
716c2e55
DV		 1274 if (pll == NULL) {
1275 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1276 pipe_name(intel_crtc->pipe));
1277 return false;
0694001b 1278 }
d452c5b6 1279
190f68c5 1280 crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
6441ab5f
PZ		 1281 }
1282
6441ab5f
PZ		 1283 return true;
1284}
1285
dc253813
DL		 1286struct skl_wrpll_context {
1287 uint64_t min_deviation; /* current minimal deviation */
1288 uint64_t central_freq; /* chosen central freq */
1289 uint64_t dco_freq; /* chosen dco freq */
1290 unsigned int p; /* chosen divider */
1291};
1292
1293static void skl_wrpll_context_init(struct skl_wrpll_context *ctx)
1294{
1295 memset(ctx, 0, sizeof(*ctx));
1296
1297 ctx->min_deviation = U64_MAX;
1298}
1299
1300/* DCO freq must be within +1%/-6% of the DCO central freq */
1301#define SKL_DCO_MAX_PDEVIATION 100
1302#define SKL_DCO_MAX_NDEVIATION 600
1303
1304static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx,
1305 uint64_t central_freq,
1306 uint64_t dco_freq,
1307 unsigned int divider)
1308{
1309 uint64_t deviation;
1310
1311 deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq),
1312 central_freq);
1313
1314 /* positive deviation */
1315 if (dco_freq >= central_freq) {
1316 if (deviation < SKL_DCO_MAX_PDEVIATION &&
1317 deviation < ctx->min_deviation) {
1318 ctx->min_deviation = deviation;
1319 ctx->central_freq = central_freq;
1320 ctx->dco_freq = dco_freq;
1321 ctx->p = divider;
1322 }
1323 /* negative deviation */
1324 } else if (deviation < SKL_DCO_MAX_NDEVIATION &&
1325 deviation < ctx->min_deviation) {
1326 ctx->min_deviation = deviation;
1327 ctx->central_freq = central_freq;
1328 ctx->dco_freq = dco_freq;
1329 ctx->p = divider;
1330 }
dc253813
DL		 1331}
1332
1333static void skl_wrpll_get_multipliers(unsigned int p,
1334 unsigned int *p0 /* out */,
1335 unsigned int *p1 /* out */,
1336 unsigned int *p2 /* out */)
1337{
1338 /* even dividers */
1339 if (p % 2 == 0) {
1340 unsigned int half = p / 2;
1341
1342 if (half == 1 || half == 2 || half == 3 || half == 5) {
1343 *p0 = 2;
1344 *p1 = 1;
1345 *p2 = half;
1346 } else if (half % 2 == 0) {
1347 *p0 = 2;
1348 *p1 = half / 2;
1349 *p2 = 2;
1350 } else if (half % 3 == 0) {
1351 *p0 = 3;
1352 *p1 = half / 3;
1353 *p2 = 2;
1354 } else if (half % 7 == 0) {
1355 *p0 = 7;
1356 *p1 = half / 7;
1357 *p2 = 2;
1358 }
1359 } else if (p == 3 || p == 9) { /* 3, 5, 7, 9, 15, 21, 35 */
1360 *p0 = 3;
1361 *p1 = 1;
1362 *p2 = p / 3;
1363 } else if (p == 5 || p == 7) {
1364 *p0 = p;
1365 *p1 = 1;
1366 *p2 = 1;
1367 } else if (p == 15) {
1368 *p0 = 3;
1369 *p1 = 1;
1370 *p2 = 5;
1371 } else if (p == 21) {
1372 *p0 = 7;
1373 *p1 = 1;
1374 *p2 = 3;
1375 } else if (p == 35) {
1376 *p0 = 7;
1377 *p1 = 1;
1378 *p2 = 5;
1379 }
1380}
1381
82d35437
S		 1382struct skl_wrpll_params {
1383 uint32_t dco_fraction;
1384 uint32_t dco_integer;
1385 uint32_t qdiv_ratio;
1386 uint32_t qdiv_mode;
1387 uint32_t kdiv;
1388 uint32_t pdiv;
1389 uint32_t central_freq;
1390};
1391
76516fbc
DL		 1392static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
1393 uint64_t afe_clock,
1394 uint64_t central_freq,
1395 uint32_t p0, uint32_t p1, uint32_t p2)
1396{
1397 uint64_t dco_freq;
1398
76516fbc
DL		 1399 switch (central_freq) {
1400 case 9600000000ULL:
1401 params->central_freq = 0;
1402 break;
1403 case 9000000000ULL:
1404 params->central_freq = 1;
1405 break;
1406 case 8400000000ULL:
1407 params->central_freq = 3;
1408 }
1409
1410 switch (p0) {
1411 case 1:
1412 params->pdiv = 0;
1413 break;
1414 case 2:
1415 params->pdiv = 1;
1416 break;
1417 case 3:
1418 params->pdiv = 2;
1419 break;
1420 case 7:
1421 params->pdiv = 4;
1422 break;
1423 default:
1424 WARN(1, "Incorrect PDiv\n");
1425 }
1426
1427 switch (p2) {
1428 case 5:
1429 params->kdiv = 0;
1430 break;
1431 case 2:
1432 params->kdiv = 1;
1433 break;
1434 case 3:
1435 params->kdiv = 2;
1436 break;
1437 case 1:
1438 params->kdiv = 3;
1439 break;
1440 default:
1441 WARN(1, "Incorrect KDiv\n");
1442 }
1443
1444 params->qdiv_ratio = p1;
1445 params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1;
1446
1447 dco_freq = p0 * p1 * p2 * afe_clock;
1448
1449 /*
1450 * Intermediate values are in Hz.
1451 * Divide by MHz to match bsepc
1452 */
30a7862d 1453 params->dco_integer = div_u64(dco_freq, 24 * MHz(1));
76516fbc 1454 params->dco_fraction =
30a7862d
DL		 1455 div_u64((div_u64(dco_freq, 24) -
1456 params->dco_integer * MHz(1)) * 0x8000, MHz(1));
76516fbc
DL		 1457}
1458
318bd821 1459static bool
82d35437
S		 1460skl_ddi_calculate_wrpll(int clock /* in Hz */,
1461 struct skl_wrpll_params *wrpll_params)
1462{
1463 uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
21318cce
DL		 1464 uint64_t dco_central_freq[3] = {8400000000ULL,
1465 9000000000ULL,
1466 9600000000ULL};
dc253813
DL		 1467 static const int even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20,
1468 24, 28, 30, 32, 36, 40, 42, 44,
1469 48, 52, 54, 56, 60, 64, 66, 68,
1470 70, 72, 76, 78, 80, 84, 88, 90,
1471 92, 96, 98 };
1472 static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 };
1473 static const struct {
1474 const int *list;
1475 int n_dividers;
1476 } dividers[] = {
1477 { even_dividers, ARRAY_SIZE(even_dividers) },
1478 { odd_dividers, ARRAY_SIZE(odd_dividers) },
1479 };
1480 struct skl_wrpll_context ctx;
1481 unsigned int dco, d, i;
1482 unsigned int p0, p1, p2;
1483
1484 skl_wrpll_context_init(&ctx);
1485
1486 for (d = 0; d < ARRAY_SIZE(dividers); d++) {
1487 for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
1488 for (i = 0; i < dividers[d].n_dividers; i++) {
1489 unsigned int p = dividers[d].list[i];
1490 uint64_t dco_freq = p * afe_clock;
1491
1492 skl_wrpll_try_divider(&ctx,
1493 dco_central_freq[dco],
1494 dco_freq,
1495 p);
e7ad9878
DL		 1496 /*
1497 * Skip the remaining dividers if we're sure to
1498 * have found the definitive divider, we can't
1499 * improve a 0 deviation.
1500 */
1501 if (ctx.min_deviation == 0)
1502 goto skip_remaining_dividers;
82d35437
S		 1503 }
1504 }
267db663 1505
e7ad9878 1506skip_remaining_dividers:
267db663
DL		 1507 /*
1508 * If a solution is found with an even divider, prefer
1509 * this one.
1510 */
1511 if (d == 0 && ctx.p)
1512 break;
82d35437
S		 1513 }
1514
dc253813
DL		 1515 if (!ctx.p) {
1516 DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock);
318bd821 1517 return false;
dc253813 1518 }
82d35437 1519
dc253813
DL		 1520 /*
1521 * gcc incorrectly analyses that these can be used without being
1522 * initialized. To be fair, it's hard to guess.
1523 */
1524 p0 = p1 = p2 = 0;
1525 skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2);
1526 skl_wrpll_params_populate(wrpll_params, afe_clock, ctx.central_freq,
1527 p0, p1, p2);
318bd821
DL		 1528
1529 return true;
82d35437
S		 1530}
1531
82d35437
S		 1532static bool
1533skl_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 1534 struct intel_crtc_state *crtc_state,
96f3f1f9 1535 struct intel_encoder *intel_encoder)
82d35437
S		 1536{
1537 struct intel_shared_dpll *pll;
1538 uint32_t ctrl1, cfgcr1, cfgcr2;
96f3f1f9 1539 int clock = crtc_state->port_clock;
82d35437
S		 1540
1541 /*
1542 * See comment in intel_dpll_hw_state to understand why we always use 0
1543 * as the DPLL id in this function.
1544 */
1545
1546 ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1547
1548 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1549 struct skl_wrpll_params wrpll_params = { 0, };
1550
1551 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1552
318bd821
DL		 1553 if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params))
1554 return false;
82d35437
S		 1555
1556 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
1557 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1558 wrpll_params.dco_integer;
1559
1560 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1561 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1562 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1563 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1564 wrpll_params.central_freq;
1565 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
840b32b7
VS		 1566 switch (crtc_state->port_clock / 2) {
1567 case 81000:
71cd8423 1568 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
82d35437 1569 break;
840b32b7 1570 case 135000:
71cd8423 1571 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
82d35437 1572 break;
840b32b7 1573 case 270000:
71cd8423 1574 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
82d35437
S		 1575 break;
1576 }
1577
1578 cfgcr1 = cfgcr2 = 0;
1579 } else /* eDP */
1580 return true;
1581
dd3cd74a
ACO		 1582 memset(&crtc_state->dpll_hw_state, 0,
1583 sizeof(crtc_state->dpll_hw_state));
1584
190f68c5
ACO		 1585 crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1586 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
1587 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
82d35437 1588
190f68c5 1589 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
82d35437
S		 1590 if (pll == NULL) {
1591 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1592 pipe_name(intel_crtc->pipe));
1593 return false;
1594 }
1595
1596 /* shared DPLL id 0 is DPLL 1 */
190f68c5 1597 crtc_state->ddi_pll_sel = pll->id + 1;
82d35437
S		 1598
1599 return true;
1600}
0220ab6e 1601
d683f3bc
S		 1602/* bxt clock parameters */
1603struct bxt_clk_div {
64987fc5 1604 int clock;
d683f3bc
S		 1605 uint32_t p1;
1606 uint32_t p2;
1607 uint32_t m2_int;
1608 uint32_t m2_frac;
1609 bool m2_frac_en;
1610 uint32_t n;
d683f3bc
S		 1611};
1612
1613/* pre-calculated values for DP linkrates */
64987fc5
SJ		 1614static const struct bxt_clk_div bxt_dp_clk_val[] = {
1615 {162000, 4, 2, 32, 1677722, 1, 1},
1616 {270000, 4, 1, 27, 0, 0, 1},
1617 {540000, 2, 1, 27, 0, 0, 1},
1618 {216000, 3, 2, 32, 1677722, 1, 1},
1619 {243000, 4, 1, 24, 1258291, 1, 1},
1620 {324000, 4, 1, 32, 1677722, 1, 1},
1621 {432000, 3, 1, 32, 1677722, 1, 1}
d683f3bc
S		 1622};
1623
1624static bool
1625bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
1626 struct intel_crtc_state *crtc_state,
96f3f1f9 1627 struct intel_encoder *intel_encoder)
d683f3bc
S		 1628{
1629 struct intel_shared_dpll *pll;
1630 struct bxt_clk_div clk_div = {0};
b6dc71f3
VK		 1631 int vco = 0;
1632 uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
e6292556 1633 uint32_t lanestagger;
96f3f1f9 1634 int clock = crtc_state->port_clock;
d683f3bc
S		 1635
1636 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1637 intel_clock_t best_clock;
1638
1639 /* Calculate HDMI div */
1640 /*
1641 * FIXME: tie the following calculation into
1642 * i9xx_crtc_compute_clock
1643 */
1644 if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) {
1645 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
1646 clock, pipe_name(intel_crtc->pipe));
1647 return false;
1648 }
1649
1650 clk_div.p1 = best_clock.p1;
1651 clk_div.p2 = best_clock.p2;
1652 WARN_ON(best_clock.m1 != 2);
1653 clk_div.n = best_clock.n;
1654 clk_div.m2_int = best_clock.m2 >> 22;
1655 clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
1656 clk_div.m2_frac_en = clk_div.m2_frac != 0;
1657
b6dc71f3 1658 vco = best_clock.vco;
d683f3bc
S		 1659 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
1660 intel_encoder->type == INTEL_OUTPUT_EDP) {
64987fc5 1661 int i;
d683f3bc 1662
64987fc5
SJ		 1663 clk_div = bxt_dp_clk_val[0];
1664 for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
1665 if (bxt_dp_clk_val[i].clock == clock) {
1666 clk_div = bxt_dp_clk_val[i];
1667 break;
1668 }
d683f3bc 1669 }
b6dc71f3
VK		 1670 vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
1671 }
1672
e6292556 1673 if (vco >= 6200000 && vco <= 6700000) {
b6dc71f3
VK		 1674 prop_coef = 4;
1675 int_coef = 9;
1676 gain_ctl = 3;
1677 targ_cnt = 8;
1678 } else if ((vco > 5400000 && vco < 6200000) ||
1679 (vco >= 4800000 && vco < 5400000)) {
1680 prop_coef = 5;
1681 int_coef = 11;
1682 gain_ctl = 3;
1683 targ_cnt = 9;
b6dc71f3
VK		 1684 } else if (vco == 5400000) {
1685 prop_coef = 3;
1686 int_coef = 8;
1687 gain_ctl = 1;
1688 targ_cnt = 9;
1689 } else {
1690 DRM_ERROR("Invalid VCO\n");
1691 return false;
d683f3bc
S		 1692 }
1693
dd3cd74a
ACO		 1694 memset(&crtc_state->dpll_hw_state, 0,
1695 sizeof(crtc_state->dpll_hw_state));
1696
e0681e38
VK		 1697 if (clock > 270000)
1698 lanestagger = 0x18;
1699 else if (clock > 135000)
1700 lanestagger = 0x0d;
1701 else if (clock > 67000)
1702 lanestagger = 0x07;
1703 else if (clock > 33000)
1704 lanestagger = 0x04;
1705 else
1706 lanestagger = 0x02;
1707
d683f3bc
S		 1708 crtc_state->dpll_hw_state.ebb0 =
1709 PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
1710 crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
1711 crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n);
1712 crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac;
1713
1714 if (clk_div.m2_frac_en)
1715 crtc_state->dpll_hw_state.pll3 =
1716 PORT_PLL_M2_FRAC_ENABLE;
1717
1718 crtc_state->dpll_hw_state.pll6 =
b6dc71f3 1719 prop_coef | PORT_PLL_INT_COEFF(int_coef);
d683f3bc 1720 crtc_state->dpll_hw_state.pll6 |=
b6dc71f3
VK		 1721 PORT_PLL_GAIN_CTL(gain_ctl);
1722
1723 crtc_state->dpll_hw_state.pll8 = targ_cnt;
d683f3bc 1724
05712c15
ID		 1725 crtc_state->dpll_hw_state.pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT;
1726
e6292556
VK		 1727 crtc_state->dpll_hw_state.pll10 =
1728 PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT)
1729 | PORT_PLL_DCO_AMP_OVR_EN_H;
d683f3bc 1730
05712c15
ID		 1731 crtc_state->dpll_hw_state.ebb4 = PORT_PLL_10BIT_CLK_ENABLE;
1732
d683f3bc 1733 crtc_state->dpll_hw_state.pcsdw12 =
e0681e38 1734 LANESTAGGER_STRAP_OVRD | lanestagger;
d683f3bc
S		 1735
1736 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1737 if (pll == NULL) {
1738 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1739 pipe_name(intel_crtc->pipe));
1740 return false;
1741 }
1742
1743 /* shared DPLL id 0 is DPLL A */
1744 crtc_state->ddi_pll_sel = pll->id;
1745
1746 return true;
1747}
1748
0220ab6e
DL		 1749/*
1750 * Tries to find a *shared* PLL for the CRTC and store it in
1751 * intel_crtc->ddi_pll_sel.
1752 *
1753 * For private DPLLs, compute_config() should do the selection for us. This
1754 * function should be folded into compute_config() eventually.
1755 */
190f68c5
ACO		 1756bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
1757 struct intel_crtc_state *crtc_state)
0220ab6e 1758{
82d35437 1759 struct drm_device *dev = intel_crtc->base.dev;
d0737e1d 1760 struct intel_encoder *intel_encoder =
3165c074 1761 intel_ddi_get_crtc_new_encoder(crtc_state);
0220ab6e 1762
82d35437 1763 if (IS_SKYLAKE(dev))
190f68c5 1764 return skl_ddi_pll_select(intel_crtc, crtc_state,
96f3f1f9 1765 intel_encoder);
d683f3bc
S		 1766 else if (IS_BROXTON(dev))
1767 return bxt_ddi_pll_select(intel_crtc, crtc_state,
96f3f1f9 1768 intel_encoder);
82d35437 1769 else
190f68c5 1770 return hsw_ddi_pll_select(intel_crtc, crtc_state,
96f3f1f9 1771 intel_encoder);
0220ab6e
DL		 1772}
1773
dae84799
PZ		 1774void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1775{
1776 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1777 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1778 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
6e3c9717 1779 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
dae84799
PZ		 1780 int type = intel_encoder->type;
1781 uint32_t temp;
1782
0e32b39c 1783 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
c9809791 1784 temp = TRANS_MSA_SYNC_CLK;
6e3c9717 1785 switch (intel_crtc->config->pipe_bpp) {
dae84799 1786 case 18:
c9809791 1787 temp |= TRANS_MSA_6_BPC;
dae84799
PZ		 1788 break;
1789 case 24:
c9809791 1790 temp |= TRANS_MSA_8_BPC;
dae84799
PZ		 1791 break;
1792 case 30:
c9809791 1793 temp |= TRANS_MSA_10_BPC;
dae84799
PZ		 1794 break;
1795 case 36:
c9809791 1796 temp |= TRANS_MSA_12_BPC;
dae84799
PZ		 1797 break;
1798 default:
4e53c2e0 1799 BUG();
dae84799 1800 }
c9809791 1801 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 1802 }
1803}
1804
0e32b39c
DA		 1805void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1806{
1807 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1808 struct drm_device *dev = crtc->dev;
1809 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1810 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
0e32b39c
DA		 1811 uint32_t temp;
1812 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1813 if (state == true)
1814 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1815 else
1816 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1817 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1818}
1819
8228c251 1820void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
8d9ddbcb
PZ		 1821{
1822 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1823 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
7739c33b 1824 struct drm_encoder *encoder = &intel_encoder->base;
c7670b10
PZ		 1825 struct drm_device *dev = crtc->dev;
1826 struct drm_i915_private *dev_priv = dev->dev_private;
8d9ddbcb 1827 enum pipe pipe = intel_crtc->pipe;
6e3c9717 1828 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
174edf1f 1829 enum port port = intel_ddi_get_encoder_port(intel_encoder);
7739c33b 1830 int type = intel_encoder->type;
8d9ddbcb
PZ		 1831 uint32_t temp;
1832
ad80a810
PZ		 1833 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1834 temp = TRANS_DDI_FUNC_ENABLE;
174edf1f 1835 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252 1836
6e3c9717 1837 switch (intel_crtc->config->pipe_bpp) {
dfcef252 1838 case 18:
ad80a810 1839 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 1840 break;
1841 case 24:
ad80a810 1842 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 1843 break;
1844 case 30:
ad80a810 1845 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 1846 break;
1847 case 36:
ad80a810 1848 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 1849 break;
1850 default:
4e53c2e0 1851 BUG();
dfcef252 1852 }
72662e10 1853
6e3c9717 1854 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 1855 temp |= TRANS_DDI_PVSYNC;
6e3c9717 1856 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 1857 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 1858
e6f0bfc4
PZ		 1859 if (cpu_transcoder == TRANSCODER_EDP) {
1860 switch (pipe) {
1861 case PIPE_A:
c7670b10
PZ		 1862 /* On Haswell, can only use the always-on power well for
1863 * eDP when not using the panel fitter, and when not
1864 * using motion blur mitigation (which we don't
1865 * support). */
fabf6e51 1866 if (IS_HASWELL(dev) &&
6e3c9717
ACO		 1867 (intel_crtc->config->pch_pfit.enabled ||
1868 intel_crtc->config->pch_pfit.force_thru))
d6dd9eb1
DV		 1869 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1870 else
1871 temp |= TRANS_DDI_EDP_INPUT_A_ON;
e6f0bfc4
PZ		 1872 break;
1873 case PIPE_B:
1874 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1875 break;
1876 case PIPE_C:
1877 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1878 break;
1879 default:
1880 BUG();
1881 break;
1882 }
1883 }
1884
7739c33b 1885 if (type == INTEL_OUTPUT_HDMI) {
6e3c9717 1886 if (intel_crtc->config->has_hdmi_sink)
ad80a810 1887 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 1888 else
ad80a810 1889 temp |= TRANS_DDI_MODE_SELECT_DVI;
8d9ddbcb 1890
7739c33b 1891 } else if (type == INTEL_OUTPUT_ANALOG) {
ad80a810 1892 temp |= TRANS_DDI_MODE_SELECT_FDI;
6e3c9717 1893 temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
7739c33b
PZ		 1894
1895 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1896 type == INTEL_OUTPUT_EDP) {
1897 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1898
0e32b39c
DA		 1899 if (intel_dp->is_mst) {
1900 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1901 } else
1902 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1903
90a6b7b0 1904 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
0e32b39c
DA		 1905 } else if (type == INTEL_OUTPUT_DP_MST) {
1906 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
1907
1908 if (intel_dp->is_mst) {
1909 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1910 } else
1911 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
7739c33b 1912
90a6b7b0 1913 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
8d9ddbcb 1914 } else {
84f44ce7
VS		 1915 WARN(1, "Invalid encoder type %d for pipe %c\n",
1916 intel_encoder->type, pipe_name(pipe));
8d9ddbcb
PZ		 1917 }
1918
ad80a810 1919 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 1920}
72662e10 1921
ad80a810
PZ		 1922void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1923 enum transcoder cpu_transcoder)
8d9ddbcb 1924{
ad80a810 1925 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
8d9ddbcb
PZ		 1926 uint32_t val = I915_READ(reg);
1927
0e32b39c 1928 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
ad80a810 1929 val |= TRANS_DDI_PORT_NONE;
8d9ddbcb 1930 I915_WRITE(reg, val);
72662e10
ED		 1931}
1932
bcbc889b
PZ		 1933bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1934{
1935 struct drm_device *dev = intel_connector->base.dev;
1936 struct drm_i915_private *dev_priv = dev->dev_private;
1937 struct intel_encoder *intel_encoder = intel_connector->encoder;
1938 int type = intel_connector->base.connector_type;
1939 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1940 enum pipe pipe = 0;
1941 enum transcoder cpu_transcoder;
882244a3 1942 enum intel_display_power_domain power_domain;
bcbc889b
PZ		 1943 uint32_t tmp;
1944
882244a3 1945 power_domain = intel_display_port_power_domain(intel_encoder);
f458ebbc 1946 if (!intel_display_power_is_enabled(dev_priv, power_domain))
882244a3
PZ		 1947 return false;
1948
bcbc889b
PZ		 1949 if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1950 return false;
1951
1952 if (port == PORT_A)
1953 cpu_transcoder = TRANSCODER_EDP;
1954 else
1a240d4d 1955 cpu_transcoder = (enum transcoder) pipe;
bcbc889b
PZ		 1956
1957 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1958
1959 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1960 case TRANS_DDI_MODE_SELECT_HDMI:
1961 case TRANS_DDI_MODE_SELECT_DVI:
1962 return (type == DRM_MODE_CONNECTOR_HDMIA);
1963
1964 case TRANS_DDI_MODE_SELECT_DP_SST:
1965 if (type == DRM_MODE_CONNECTOR_eDP)
1966 return true;
bcbc889b 1967 return (type == DRM_MODE_CONNECTOR_DisplayPort);
0e32b39c
DA		 1968 case TRANS_DDI_MODE_SELECT_DP_MST:
1969 /* if the transcoder is in MST state then
1970 * connector isn't connected */
1971 return false;
bcbc889b
PZ		 1972
1973 case TRANS_DDI_MODE_SELECT_FDI:
1974 return (type == DRM_MODE_CONNECTOR_VGA);
1975
1976 default:
1977 return false;
1978 }
1979}
1980
85234cdc
DV		 1981bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1982 enum pipe *pipe)
1983{
1984 struct drm_device *dev = encoder->base.dev;
1985 struct drm_i915_private *dev_priv = dev->dev_private;
fe43d3f5 1986 enum port port = intel_ddi_get_encoder_port(encoder);
6d129bea 1987 enum intel_display_power_domain power_domain;
85234cdc
DV		 1988 u32 tmp;
1989 int i;
1990
6d129bea 1991 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 1992 if (!intel_display_power_is_enabled(dev_priv, power_domain))
6d129bea
ID		 1993 return false;
1994
fe43d3f5 1995 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc
DV		 1996
1997 if (!(tmp & DDI_BUF_CTL_ENABLE))
1998 return false;
1999
ad80a810
PZ		 2000 if (port == PORT_A) {
2001 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 2002
ad80a810
PZ		 2003 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
2004 case TRANS_DDI_EDP_INPUT_A_ON:
2005 case TRANS_DDI_EDP_INPUT_A_ONOFF:
2006 *pipe = PIPE_A;
2007 break;
2008 case TRANS_DDI_EDP_INPUT_B_ONOFF:
2009 *pipe = PIPE_B;
2010 break;
2011 case TRANS_DDI_EDP_INPUT_C_ONOFF:
2012 *pipe = PIPE_C;
2013 break;
2014 }
2015
2016 return true;
2017 } else {
2018 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
2019 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
2020
2021 if ((tmp & TRANS_DDI_PORT_MASK)
2022 == TRANS_DDI_SELECT_PORT(port)) {
0e32b39c
DA		 2023 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST)
2024 return false;
2025
ad80a810
PZ		 2026 *pipe = i;
2027 return true;
2028 }
85234cdc
DV		 2029 }
2030 }
2031
84f44ce7 2032 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
85234cdc 2033
22f9fe50 2034 return false;
85234cdc
DV		 2035}
2036
fc914639
PZ		 2037void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
2038{
2039 struct drm_crtc *crtc = &intel_crtc->base;
2040 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
2041 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
2042 enum port port = intel_ddi_get_encoder_port(intel_encoder);
6e3c9717 2043 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 2044
bb523fc0
PZ		 2045 if (cpu_transcoder != TRANSCODER_EDP)
2046 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2047 TRANS_CLK_SEL_PORT(port));
fc914639
PZ		 2048}
2049
2050void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
2051{
2052 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
6e3c9717 2053 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 2054
bb523fc0
PZ		 2055 if (cpu_transcoder != TRANSCODER_EDP)
2056 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2057 TRANS_CLK_SEL_DISABLED);
fc914639
PZ		 2058}
2059
f8896f5d
DW		 2060static void skl_ddi_set_iboost(struct drm_device *dev, u32 level,
2061 enum port port, int type)
2062{
2063 struct drm_i915_private *dev_priv = dev->dev_private;
2064 const struct ddi_buf_trans *ddi_translations;
2065 uint8_t iboost;
75067dde 2066 uint8_t dp_iboost, hdmi_iboost;
f8896f5d
DW		 2067 int n_entries;
2068 u32 reg;
2069
75067dde
AK		 2070 /* VBT may override standard boost values */
2071 dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
2072 hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2073
f8896f5d 2074 if (type == INTEL_OUTPUT_DISPLAYPORT) {
75067dde
AK		 2075 if (dp_iboost) {
2076 iboost = dp_iboost;
2077 } else {
2078 ddi_translations = skl_get_buf_trans_dp(dev, &n_entries);
2079 iboost = ddi_translations[port].i_boost;
2080 }
f8896f5d 2081 } else if (type == INTEL_OUTPUT_EDP) {
75067dde
AK		 2082 if (dp_iboost) {
2083 iboost = dp_iboost;
2084 } else {
2085 ddi_translations = skl_get_buf_trans_edp(dev, &n_entries);
2086 iboost = ddi_translations[port].i_boost;
2087 }
f8896f5d 2088 } else if (type == INTEL_OUTPUT_HDMI) {
75067dde
AK		 2089 if (hdmi_iboost) {
2090 iboost = hdmi_iboost;
2091 } else {
2092 ddi_translations = skl_get_buf_trans_hdmi(dev, &n_entries);
2093 iboost = ddi_translations[port].i_boost;
2094 }
f8896f5d
DW		 2095 } else {
2096 return;
2097 }
2098
2099 /* Make sure that the requested I_boost is valid */
2100 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2101 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2102 return;
2103 }
2104
2105 reg = I915_READ(DISPIO_CR_TX_BMU_CR0);
2106 reg &= ~BALANCE_LEG_MASK(port);
2107 reg &= ~(1 << (BALANCE_LEG_DISABLE_SHIFT + port));
2108
2109 if (iboost)
2110 reg |= iboost << BALANCE_LEG_SHIFT(port);
2111 else
2112 reg |= 1 << (BALANCE_LEG_DISABLE_SHIFT + port);
2113
2114 I915_WRITE(DISPIO_CR_TX_BMU_CR0, reg);
2115}
2116
2117static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
2118 enum port port, int type)
96fb9f9b
VK		 2119{
2120 struct drm_i915_private *dev_priv = dev->dev_private;
2121 const struct bxt_ddi_buf_trans *ddi_translations;
2122 u32 n_entries, i;
2123 uint32_t val;
2124
d9d7000d
SJ		 2125 if (type == INTEL_OUTPUT_EDP && dev_priv->edp_low_vswing) {
2126 n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
2127 ddi_translations = bxt_ddi_translations_edp;
2128 } else if (type == INTEL_OUTPUT_DISPLAYPORT
2129 || type == INTEL_OUTPUT_EDP) {
96fb9f9b
VK		 2130 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
2131 ddi_translations = bxt_ddi_translations_dp;
2132 } else if (type == INTEL_OUTPUT_HDMI) {
2133 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
2134 ddi_translations = bxt_ddi_translations_hdmi;
2135 } else {
2136 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
2137 type);
2138 return;
2139 }
2140
2141 /* Check if default value has to be used */
2142 if (level >= n_entries ||
2143 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
2144 for (i = 0; i < n_entries; i++) {
2145 if (ddi_translations[i].default_index) {
2146 level = i;
2147 break;
2148 }
2149 }
2150 }
2151
2152 /*
2153 * While we write to the group register to program all lanes at once we
2154 * can read only lane registers and we pick lanes 0/1 for that.
2155 */
2156 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
2157 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
2158 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
2159
2160 val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
2161 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
2162 val |= ddi_translations[level].margin << MARGIN_000_SHIFT |
2163 ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
2164 I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
2165
2166 val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
9c58a049 2167 val &= ~SCALE_DCOMP_METHOD;
96fb9f9b 2168 if (ddi_translations[level].enable)
9c58a049
SJ		 2169 val |= SCALE_DCOMP_METHOD;
2170
2171 if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
2172 DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set");
2173
96fb9f9b
VK		 2174 I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
2175
2176 val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
2177 val &= ~DE_EMPHASIS;
2178 val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
2179 I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
2180
2181 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
2182 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
2183 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
2184}
2185
f8896f5d
DW		 2186static uint32_t translate_signal_level(int signal_levels)
2187{
2188 uint32_t level;
2189
2190 switch (signal_levels) {
2191 default:
2192 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2193 signal_levels);
2194 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2195 level = 0;
2196 break;
2197 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2198 level = 1;
2199 break;
2200 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2201 level = 2;
2202 break;
2203 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
2204 level = 3;
2205 break;
2206
2207 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2208 level = 4;
2209 break;
2210 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2211 level = 5;
2212 break;
2213 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2214 level = 6;
2215 break;
2216
2217 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2218 level = 7;
2219 break;
2220 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2221 level = 8;
2222 break;
2223
2224 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2225 level = 9;
2226 break;
2227 }
2228
2229 return level;
2230}
2231
2232uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2233{
2234 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2235 struct drm_device *dev = dport->base.base.dev;
2236 struct intel_encoder *encoder = &dport->base;
2237 uint8_t train_set = intel_dp->train_set[0];
2238 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2239 DP_TRAIN_PRE_EMPHASIS_MASK);
2240 enum port port = dport->port;
2241 uint32_t level;
2242
2243 level = translate_signal_level(signal_levels);
2244
2245 if (IS_SKYLAKE(dev))
2246 skl_ddi_set_iboost(dev, level, port, encoder->type);
2247 else if (IS_BROXTON(dev))
2248 bxt_ddi_vswing_sequence(dev, level, port, encoder->type);
2249
2250 return DDI_BUF_TRANS_SELECT(level);
2251}
2252
00c09d70 2253static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
6441ab5f 2254{
c19b0669 2255 struct drm_encoder *encoder = &intel_encoder->base;
efa80add
S		 2256 struct drm_device *dev = encoder->dev;
2257 struct drm_i915_private *dev_priv = dev->dev_private;
30cf6db8 2258 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
6441ab5f 2259 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 2260 int type = intel_encoder->type;
96fb9f9b 2261 int hdmi_level;
6441ab5f 2262
82a4d9c0
PZ		 2263 if (type == INTEL_OUTPUT_EDP) {
2264 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4be73780 2265 intel_edp_panel_on(intel_dp);
82a4d9c0 2266 }
6441ab5f 2267
efa80add 2268 if (IS_SKYLAKE(dev)) {
6e3c9717 2269 uint32_t dpll = crtc->config->ddi_pll_sel;
efa80add
S		 2270 uint32_t val;
2271
5416d871
DL		 2272 /*
2273 * DPLL0 is used for eDP and is the only "private" DPLL (as
2274 * opposed to shared) on SKL
2275 */
2276 if (type == INTEL_OUTPUT_EDP) {
2277 WARN_ON(dpll != SKL_DPLL0);
2278
2279 val = I915_READ(DPLL_CTRL1);
2280
2281 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
2282 DPLL_CTRL1_SSC(dpll) |
71cd8423 2283 DPLL_CTRL1_LINK_RATE_MASK(dpll));
6e3c9717 2284 val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6);
5416d871
DL		 2285
2286 I915_WRITE(DPLL_CTRL1, val);
2287 POSTING_READ(DPLL_CTRL1);
2288 }
2289
2290 /* DDI -> PLL mapping */
efa80add
S		 2291 val = I915_READ(DPLL_CTRL2);
2292
2293 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2294 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2295 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
2296 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2297
2298 I915_WRITE(DPLL_CTRL2, val);
5416d871 2299
1ab23380 2300 } else if (INTEL_INFO(dev)->gen < 9) {
6e3c9717
ACO		 2301 WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE);
2302 I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel);
efa80add 2303 }
c19b0669 2304
82a4d9c0 2305 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
c19b0669 2306 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
30cf6db8 2307
901c2daf
VS		 2308 intel_dp_set_link_params(intel_dp, crtc->config);
2309
44905a27 2310 intel_ddi_init_dp_buf_reg(intel_encoder);
c19b0669
PZ		 2311
2312 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2313 intel_dp_start_link_train(intel_dp);
2314 intel_dp_complete_link_train(intel_dp);
23f08d83 2315 if (port != PORT_A || INTEL_INFO(dev)->gen >= 9)
3ab9c637 2316 intel_dp_stop_link_train(intel_dp);
30cf6db8
DV		 2317 } else if (type == INTEL_OUTPUT_HDMI) {
2318 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2319
96fb9f9b
VK		 2320 if (IS_BROXTON(dev)) {
2321 hdmi_level = dev_priv->vbt.
2322 ddi_port_info[port].hdmi_level_shift;
2323 bxt_ddi_vswing_sequence(dev, hdmi_level, port,
2324 INTEL_OUTPUT_HDMI);
2325 }
30cf6db8 2326 intel_hdmi->set_infoframes(encoder,
6e3c9717
ACO		 2327 crtc->config->has_hdmi_sink,
2328 &crtc->config->base.adjusted_mode);
c19b0669 2329 }
6441ab5f
PZ		 2330}
2331
00c09d70 2332static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
6441ab5f
PZ		 2333{
2334 struct drm_encoder *encoder = &intel_encoder->base;
efa80add
S		 2335 struct drm_device *dev = encoder->dev;
2336 struct drm_i915_private *dev_priv = dev->dev_private;
6441ab5f 2337 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 2338 int type = intel_encoder->type;
2886e93f 2339 uint32_t val;
a836bdf9 2340 bool wait = false;
2886e93f
PZ		 2341
2342 val = I915_READ(DDI_BUF_CTL(port));
2343 if (val & DDI_BUF_CTL_ENABLE) {
2344 val &= ~DDI_BUF_CTL_ENABLE;
2345 I915_WRITE(DDI_BUF_CTL(port), val);
a836bdf9 2346 wait = true;
2886e93f 2347 }
6441ab5f 2348
a836bdf9
PZ		 2349 val = I915_READ(DP_TP_CTL(port));
2350 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2351 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2352 I915_WRITE(DP_TP_CTL(port), val);
2353
2354 if (wait)
2355 intel_wait_ddi_buf_idle(dev_priv, port);
2356
76bb80ed 2357 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
82a4d9c0 2358 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
76bb80ed 2359 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
24f3e092 2360 intel_edp_panel_vdd_on(intel_dp);
4be73780 2361 intel_edp_panel_off(intel_dp);
82a4d9c0
PZ		 2362 }
2363
efa80add
S		 2364 if (IS_SKYLAKE(dev))
2365 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
2366 DPLL_CTRL2_DDI_CLK_OFF(port)));
1ab23380 2367 else if (INTEL_INFO(dev)->gen < 9)
efa80add 2368 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
6441ab5f
PZ		 2369}
2370
00c09d70 2371static void intel_enable_ddi(struct intel_encoder *intel_encoder)
72662e10 2372{
6547fef8 2373 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 2374 struct drm_crtc *crtc = encoder->crtc;
2375 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6547fef8 2376 struct drm_device *dev = encoder->dev;
72662e10 2377 struct drm_i915_private *dev_priv = dev->dev_private;
6547fef8
PZ		 2378 enum port port = intel_ddi_get_encoder_port(intel_encoder);
2379 int type = intel_encoder->type;
72662e10 2380
6547fef8 2381 if (type == INTEL_OUTPUT_HDMI) {
876a8cdf
DL		 2382 struct intel_digital_port *intel_dig_port =
2383 enc_to_dig_port(encoder);
2384
6547fef8
PZ		 2385 /* In HDMI/DVI mode, the port width, and swing/emphasis values
2386 * are ignored so nothing special needs to be done besides
2387 * enabling the port.
2388 */
876a8cdf 2389 I915_WRITE(DDI_BUF_CTL(port),
bcf53de4
SM		 2390 intel_dig_port->saved_port_bits |
2391 DDI_BUF_CTL_ENABLE);
d6c50ff8
PZ		 2392 } else if (type == INTEL_OUTPUT_EDP) {
2393 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2394
23f08d83 2395 if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
3ab9c637
ID		 2396 intel_dp_stop_link_train(intel_dp);
2397
4be73780 2398 intel_edp_backlight_on(intel_dp);
0bc12bcb 2399 intel_psr_enable(intel_dp);
c395578e 2400 intel_edp_drrs_enable(intel_dp);
6547fef8 2401 }
7b9f35a6 2402
6e3c9717 2403 if (intel_crtc->config->has_audio) {
d45a0bf5 2404 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
69bfe1a9 2405 intel_audio_codec_enable(intel_encoder);
7b9f35a6 2406 }
5ab432ef
DV		 2407}
2408
00c09d70 2409static void intel_disable_ddi(struct intel_encoder *intel_encoder)
5ab432ef 2410{
d6c50ff8 2411 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 2412 struct drm_crtc *crtc = encoder->crtc;
2413 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d6c50ff8 2414 int type = intel_encoder->type;
7b9f35a6
WX		 2415 struct drm_device *dev = encoder->dev;
2416 struct drm_i915_private *dev_priv = dev->dev_private;
d6c50ff8 2417
6e3c9717 2418 if (intel_crtc->config->has_audio) {
69bfe1a9 2419 intel_audio_codec_disable(intel_encoder);
d45a0bf5
PZ		 2420 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
2421 }
2831d842 2422
d6c50ff8
PZ		 2423 if (type == INTEL_OUTPUT_EDP) {
2424 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2425
c395578e 2426 intel_edp_drrs_disable(intel_dp);
0bc12bcb 2427 intel_psr_disable(intel_dp);
4be73780 2428 intel_edp_backlight_off(intel_dp);
d6c50ff8 2429 }
72662e10 2430}
79f689aa 2431
e0b01be4
DV		 2432static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
2433 struct intel_shared_dpll *pll)
2434{
3e369b76 2435 I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
e0b01be4
DV		 2436 POSTING_READ(WRPLL_CTL(pll->id));
2437 udelay(20);
2438}
2439
12030431
DV		 2440static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv,
2441 struct intel_shared_dpll *pll)
2442{
2443 uint32_t val;
2444
2445 val = I915_READ(WRPLL_CTL(pll->id));
12030431
DV		 2446 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
2447 POSTING_READ(WRPLL_CTL(pll->id));
2448}
2449
d452c5b6
DV		 2450static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2451 struct intel_shared_dpll *pll,
2452 struct intel_dpll_hw_state *hw_state)
2453{
2454 uint32_t val;
2455
f458ebbc 2456 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
d452c5b6
DV		 2457 return false;
2458
2459 val = I915_READ(WRPLL_CTL(pll->id));
2460 hw_state->wrpll = val;
2461
2462 return val & WRPLL_PLL_ENABLE;
2463}
2464
ca1381b5 2465static const char * const hsw_ddi_pll_names[] = {
9cd86933
DV		 2466 "WRPLL 1",
2467 "WRPLL 2",
2468};
2469
143b307c 2470static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
79f689aa 2471{
9cd86933
DV		 2472 int i;
2473
716c2e55 2474 dev_priv->num_shared_dpll = 2;
9cd86933 2475
716c2e55 2476 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9cd86933
DV		 2477 dev_priv->shared_dplls[i].id = i;
2478 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
12030431 2479 dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable;
e0b01be4 2480 dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable;
d452c5b6
DV		 2481 dev_priv->shared_dplls[i].get_hw_state =
2482 hsw_ddi_pll_get_hw_state;
9cd86933 2483 }
143b307c
DL		 2484}
2485
d1a2dc78
S		 2486static const char * const skl_ddi_pll_names[] = {
2487 "DPLL 1",
2488 "DPLL 2",
2489 "DPLL 3",
2490};
2491
2492struct skl_dpll_regs {
2493 u32 ctl, cfgcr1, cfgcr2;
2494};
2495
2496/* this array is indexed by the *shared* pll id */
2497static const struct skl_dpll_regs skl_dpll_regs[3] = {
2498 {
2499 /* DPLL 1 */
2500 .ctl = LCPLL2_CTL,
2501 .cfgcr1 = DPLL1_CFGCR1,
2502 .cfgcr2 = DPLL1_CFGCR2,
2503 },
2504 {
2505 /* DPLL 2 */
2506 .ctl = WRPLL_CTL1,
2507 .cfgcr1 = DPLL2_CFGCR1,
2508 .cfgcr2 = DPLL2_CFGCR2,
2509 },
2510 {
2511 /* DPLL 3 */
2512 .ctl = WRPLL_CTL2,
2513 .cfgcr1 = DPLL3_CFGCR1,
2514 .cfgcr2 = DPLL3_CFGCR2,
2515 },
2516};
2517
2518static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
2519 struct intel_shared_dpll *pll)
2520{
2521 uint32_t val;
2522 unsigned int dpll;
2523 const struct skl_dpll_regs *regs = skl_dpll_regs;
2524
2525 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2526 dpll = pll->id + 1;
2527
2528 val = I915_READ(DPLL_CTRL1);
2529
2530 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) |
71cd8423 2531 DPLL_CTRL1_LINK_RATE_MASK(dpll));
d1a2dc78
S		 2532 val |= pll->config.hw_state.ctrl1 << (dpll * 6);
2533
2534 I915_WRITE(DPLL_CTRL1, val);
2535 POSTING_READ(DPLL_CTRL1);
2536
2537 I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);
2538 I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);
2539 POSTING_READ(regs[pll->id].cfgcr1);
2540 POSTING_READ(regs[pll->id].cfgcr2);
2541
2542 /* the enable bit is always bit 31 */
2543 I915_WRITE(regs[pll->id].ctl,
2544 I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);
2545
2546 if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5))
2547 DRM_ERROR("DPLL %d not locked\n", dpll);
2548}
2549
2550static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
2551 struct intel_shared_dpll *pll)
2552{
2553 const struct skl_dpll_regs *regs = skl_dpll_regs;
2554
2555 /* the enable bit is always bit 31 */
2556 I915_WRITE(regs[pll->id].ctl,
2557 I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
2558 POSTING_READ(regs[pll->id].ctl);
2559}
2560
2561static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2562 struct intel_shared_dpll *pll,
2563 struct intel_dpll_hw_state *hw_state)
2564{
2565 uint32_t val;
2566 unsigned int dpll;
2567 const struct skl_dpll_regs *regs = skl_dpll_regs;
2568
2569 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2570 return false;
2571
2572 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2573 dpll = pll->id + 1;
2574
2575 val = I915_READ(regs[pll->id].ctl);
2576 if (!(val & LCPLL_PLL_ENABLE))
2577 return false;
2578
2579 val = I915_READ(DPLL_CTRL1);
2580 hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f;
2581
2582 /* avoid reading back stale values if HDMI mode is not enabled */
2583 if (val & DPLL_CTRL1_HDMI_MODE(dpll)) {
2584 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
2585 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
2586 }
2587
2588 return true;
2589}
2590
2591static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
2592{
2593 int i;
2594
2595 dev_priv->num_shared_dpll = 3;
2596
2597 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2598 dev_priv->shared_dplls[i].id = i;
2599 dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i];
2600 dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable;
2601 dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable;
2602 dev_priv->shared_dplls[i].get_hw_state =
2603 skl_ddi_pll_get_hw_state;
2604 }
2605}
2606
5c6706e5
VK		 2607static void broxton_phy_init(struct drm_i915_private *dev_priv,
2608 enum dpio_phy phy)
2609{
2610 enum port port;
2611 uint32_t val;
2612
2613 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
2614 val |= GT_DISPLAY_POWER_ON(phy);
2615 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
2616
2617 /* Considering 10ms timeout until BSpec is updated */
2618 if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
2619 DRM_ERROR("timeout during PHY%d power on\n", phy);
2620
2621 for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A);
2622 port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
2623 int lane;
2624
2625 for (lane = 0; lane < 4; lane++) {
2626 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
2627 /*
2628 * Note that on CHV this flag is called UPAR, but has
2629 * the same function.
2630 */
2631 val &= ~LATENCY_OPTIM;
2632 if (lane != 1)
2633 val |= LATENCY_OPTIM;
2634
2635 I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
2636 }
2637 }
2638
2639 /* Program PLL Rcomp code offset */
2640 val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
2641 val &= ~IREF0RC_OFFSET_MASK;
2642 val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
2643 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
2644
2645 val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
2646 val &= ~IREF1RC_OFFSET_MASK;
2647 val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
2648 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
2649
2650 /* Program power gating */
2651 val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
2652 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
2653 SUS_CLK_CONFIG;
2654 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
2655
2656 if (phy == DPIO_PHY0) {
2657 val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
2658 val |= DW6_OLDO_DYN_PWR_DOWN_EN;
2659 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
2660 }
2661
2662 val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
2663 val &= ~OCL2_LDOFUSE_PWR_DIS;
2664 /*
2665 * On PHY1 disable power on the second channel, since no port is
2666 * connected there. On PHY0 both channels have a port, so leave it
2667 * enabled.
2668 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
2669 * power down the second channel on PHY0 as well.
2670 */
2671 if (phy == DPIO_PHY1)
2672 val |= OCL2_LDOFUSE_PWR_DIS;
2673 I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
2674
2675 if (phy == DPIO_PHY0) {
2676 uint32_t grc_code;
2677 /*
2678 * PHY0 isn't connected to an RCOMP resistor so copy over
2679 * the corresponding calibrated value from PHY1, and disable
2680 * the automatic calibration on PHY0.
2681 */
2682 if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE,
2683 10))
2684 DRM_ERROR("timeout waiting for PHY1 GRC\n");
2685
2686 val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1));
2687 val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
2688 grc_code = val << GRC_CODE_FAST_SHIFT |
2689 val << GRC_CODE_SLOW_SHIFT |
2690 val;
2691 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
2692
2693 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
2694 val |= GRC_DIS | GRC_RDY_OVRD;
2695 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
2696 }
2697
2698 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2699 val |= COMMON_RESET_DIS;
2700 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2701}
2702
2703void broxton_ddi_phy_init(struct drm_device *dev)
2704{
2705 /* Enable PHY1 first since it provides Rcomp for PHY0 */
2706 broxton_phy_init(dev->dev_private, DPIO_PHY1);
2707 broxton_phy_init(dev->dev_private, DPIO_PHY0);
2708}
2709
2710static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
2711 enum dpio_phy phy)
2712{
2713 uint32_t val;
2714
2715 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2716 val &= ~COMMON_RESET_DIS;
2717 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2718}
2719
2720void broxton_ddi_phy_uninit(struct drm_device *dev)
2721{
2722 struct drm_i915_private *dev_priv = dev->dev_private;
2723
2724 broxton_phy_uninit(dev_priv, DPIO_PHY1);
2725 broxton_phy_uninit(dev_priv, DPIO_PHY0);
2726
2727 /* FIXME: do this in broxton_phy_uninit per phy */
2728 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0);
2729}
2730
dfb82408
S		 2731static const char * const bxt_ddi_pll_names[] = {
2732 "PORT PLL A",
2733 "PORT PLL B",
2734 "PORT PLL C",
2735};
2736
2737static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
2738 struct intel_shared_dpll *pll)
2739{
2740 uint32_t temp;
2741 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2742
2743 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2744 temp &= ~PORT_PLL_REF_SEL;
2745 /* Non-SSC reference */
2746 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2747
2748 /* Disable 10 bit clock */
2749 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2750 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2751 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2752
2753 /* Write P1 & P2 */
2754 temp = I915_READ(BXT_PORT_PLL_EBB_0(port));
2755 temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK);
2756 temp |= pll->config.hw_state.ebb0;
2757 I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp);
2758
2759 /* Write M2 integer */
2760 temp = I915_READ(BXT_PORT_PLL(port, 0));
2761 temp &= ~PORT_PLL_M2_MASK;
2762 temp |= pll->config.hw_state.pll0;
2763 I915_WRITE(BXT_PORT_PLL(port, 0), temp);
2764
2765 /* Write N */
2766 temp = I915_READ(BXT_PORT_PLL(port, 1));
2767 temp &= ~PORT_PLL_N_MASK;
2768 temp |= pll->config.hw_state.pll1;
2769 I915_WRITE(BXT_PORT_PLL(port, 1), temp);
2770
2771 /* Write M2 fraction */
2772 temp = I915_READ(BXT_PORT_PLL(port, 2));
2773 temp &= ~PORT_PLL_M2_FRAC_MASK;
2774 temp |= pll->config.hw_state.pll2;
2775 I915_WRITE(BXT_PORT_PLL(port, 2), temp);
2776
2777 /* Write M2 fraction enable */
2778 temp = I915_READ(BXT_PORT_PLL(port, 3));
2779 temp &= ~PORT_PLL_M2_FRAC_ENABLE;
2780 temp |= pll->config.hw_state.pll3;
2781 I915_WRITE(BXT_PORT_PLL(port, 3), temp);
2782
2783 /* Write coeff */
2784 temp = I915_READ(BXT_PORT_PLL(port, 6));
2785 temp &= ~PORT_PLL_PROP_COEFF_MASK;
2786 temp &= ~PORT_PLL_INT_COEFF_MASK;
2787 temp &= ~PORT_PLL_GAIN_CTL_MASK;
2788 temp |= pll->config.hw_state.pll6;
2789 I915_WRITE(BXT_PORT_PLL(port, 6), temp);
2790
2791 /* Write calibration val */
2792 temp = I915_READ(BXT_PORT_PLL(port, 8));
2793 temp &= ~PORT_PLL_TARGET_CNT_MASK;
2794 temp |= pll->config.hw_state.pll8;
2795 I915_WRITE(BXT_PORT_PLL(port, 8), temp);
2796
b6dc71f3
VK		 2797 temp = I915_READ(BXT_PORT_PLL(port, 9));
2798 temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
05712c15 2799 temp |= pll->config.hw_state.pll9;
b6dc71f3
VK		 2800 I915_WRITE(BXT_PORT_PLL(port, 9), temp);
2801
2802 temp = I915_READ(BXT_PORT_PLL(port, 10));
2803 temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
2804 temp &= ~PORT_PLL_DCO_AMP_MASK;
2805 temp |= pll->config.hw_state.pll10;
2806 I915_WRITE(BXT_PORT_PLL(port, 10), temp);
dfb82408
S		 2807
2808 /* Recalibrate with new settings */
2809 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2810 temp |= PORT_PLL_RECALIBRATE;
2811 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
05712c15
ID		 2812 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2813 temp |= pll->config.hw_state.ebb4;
dfb82408
S		 2814 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2815
2816 /* Enable PLL */
2817 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2818 temp |= PORT_PLL_ENABLE;
2819 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2820 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2821
2822 if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
2823 PORT_PLL_LOCK), 200))
2824 DRM_ERROR("PLL %d not locked\n", port);
2825
2826 /*
2827 * While we write to the group register to program all lanes at once we
2828 * can read only lane registers and we pick lanes 0/1 for that.
2829 */
2830 temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2831 temp &= ~LANE_STAGGER_MASK;
2832 temp &= ~LANESTAGGER_STRAP_OVRD;
2833 temp |= pll->config.hw_state.pcsdw12;
2834 I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp);
2835}
2836
2837static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
2838 struct intel_shared_dpll *pll)
2839{
2840 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2841 uint32_t temp;
2842
2843 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2844 temp &= ~PORT_PLL_ENABLE;
2845 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2846 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2847}
2848
2849static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2850 struct intel_shared_dpll *pll,
2851 struct intel_dpll_hw_state *hw_state)
2852{
2853 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2854 uint32_t val;
2855
2856 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2857 return false;
2858
2859 val = I915_READ(BXT_PORT_PLL_ENABLE(port));
2860 if (!(val & PORT_PLL_ENABLE))
2861 return false;
2862
2863 hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port));
793dfa59
ID		 2864 hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK;
2865
05712c15
ID		 2866 hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(port));
2867 hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE;
2868
dfb82408 2869 hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0));
793dfa59
ID		 2870 hw_state->pll0 &= PORT_PLL_M2_MASK;
2871
dfb82408 2872 hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1));
793dfa59
ID		 2873 hw_state->pll1 &= PORT_PLL_N_MASK;
2874
dfb82408 2875 hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2));
793dfa59
ID		 2876 hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK;
2877
dfb82408 2878 hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
793dfa59
ID		 2879 hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE;
2880
dfb82408 2881 hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
793dfa59
ID		 2882 hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK |
2883 PORT_PLL_INT_COEFF_MASK |
2884 PORT_PLL_GAIN_CTL_MASK;
2885
dfb82408 2886 hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
793dfa59
ID		 2887 hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK;
2888
05712c15
ID		 2889 hw_state->pll9 = I915_READ(BXT_PORT_PLL(port, 9));
2890 hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK;
2891
b6dc71f3 2892 hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10));
793dfa59
ID		 2893 hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H |
2894 PORT_PLL_DCO_AMP_MASK;
2895
dfb82408
S		 2896 /*
2897 * While we write to the group register to program all lanes at once we
2898 * can read only lane registers. We configure all lanes the same way, so
2899 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
2900 */
2901 hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
b5dada82 2902 if (I915_READ(BXT_PORT_PCS_DW12_LN23(port)) != hw_state->pcsdw12)
dfb82408
S		 2903 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
2904 hw_state->pcsdw12,
2905 I915_READ(BXT_PORT_PCS_DW12_LN23(port)));
793dfa59 2906 hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD;
dfb82408
S		 2907
2908 return true;
2909}
2910
2911static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv)
2912{
2913 int i;
2914
2915 dev_priv->num_shared_dpll = 3;
2916
2917 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2918 dev_priv->shared_dplls[i].id = i;
2919 dev_priv->shared_dplls[i].name = bxt_ddi_pll_names[i];
2920 dev_priv->shared_dplls[i].disable = bxt_ddi_pll_disable;
2921 dev_priv->shared_dplls[i].enable = bxt_ddi_pll_enable;
2922 dev_priv->shared_dplls[i].get_hw_state =
2923 bxt_ddi_pll_get_hw_state;
2924 }
2925}
2926
143b307c
DL		 2927void intel_ddi_pll_init(struct drm_device *dev)
2928{
2929 struct drm_i915_private *dev_priv = dev->dev_private;
2930 uint32_t val = I915_READ(LCPLL_CTL);
2931
d1a2dc78
S		 2932 if (IS_SKYLAKE(dev))
2933 skl_shared_dplls_init(dev_priv);
dfb82408
S		 2934 else if (IS_BROXTON(dev))
2935 bxt_shared_dplls_init(dev_priv);
d1a2dc78
S		 2936 else
2937 hsw_shared_dplls_init(dev_priv);
79f689aa 2938
121643c2 2939 if (IS_SKYLAKE(dev)) {
d9062ae5
DL		 2940 int cdclk_freq;
2941
2942 cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5d96d8af 2943 dev_priv->skl_boot_cdclk = cdclk_freq;
121643c2
S		 2944 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
2945 DRM_ERROR("LCPLL1 is disabled\n");
5d96d8af
DL		 2946 else
2947 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
f8437dd1
VK		 2948 } else if (IS_BROXTON(dev)) {
2949 broxton_init_cdclk(dev);
5c6706e5 2950 broxton_ddi_phy_init(dev);
121643c2
S		 2951 } else {
2952 /*
2953 * The LCPLL register should be turned on by the BIOS. For now
2954 * let's just check its state and print errors in case
2955 * something is wrong. Don't even try to turn it on.
2956 */
2957
2958 if (val & LCPLL_CD_SOURCE_FCLK)
2959 DRM_ERROR("CDCLK source is not LCPLL\n");
79f689aa 2960
121643c2
S		 2961 if (val & LCPLL_PLL_DISABLE)
2962 DRM_ERROR("LCPLL is disabled\n");
2963 }
79f689aa 2964}
c19b0669
PZ		 2965
2966void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
2967{
174edf1f
PZ		 2968 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2969 struct intel_dp *intel_dp = &intel_dig_port->dp;
c19b0669 2970 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
174edf1f 2971 enum port port = intel_dig_port->port;
c19b0669 2972 uint32_t val;
f3e227df 2973 bool wait = false;
c19b0669
PZ		 2974
2975 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2976 val = I915_READ(DDI_BUF_CTL(port));
2977 if (val & DDI_BUF_CTL_ENABLE) {
2978 val &= ~DDI_BUF_CTL_ENABLE;
2979 I915_WRITE(DDI_BUF_CTL(port), val);
2980 wait = true;
2981 }
2982
2983 val = I915_READ(DP_TP_CTL(port));
2984 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2985 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2986 I915_WRITE(DP_TP_CTL(port), val);
2987 POSTING_READ(DP_TP_CTL(port));
2988
2989 if (wait)
2990 intel_wait_ddi_buf_idle(dev_priv, port);
2991 }
2992
0e32b39c 2993 val = DP_TP_CTL_ENABLE |
c19b0669 2994 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
0e32b39c
DA		 2995 if (intel_dp->is_mst)
2996 val |= DP_TP_CTL_MODE_MST;
2997 else {
2998 val |= DP_TP_CTL_MODE_SST;
2999 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3000 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3001 }
c19b0669
PZ		 3002 I915_WRITE(DP_TP_CTL(port), val);
3003 POSTING_READ(DP_TP_CTL(port));
3004
3005 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3006 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
3007 POSTING_READ(DDI_BUF_CTL(port));
3008
3009 udelay(600);
3010}
00c09d70 3011
1ad960f2
PZ		 3012void intel_ddi_fdi_disable(struct drm_crtc *crtc)
3013{
3014 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
3015 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
3016 uint32_t val;
3017
3018 intel_ddi_post_disable(intel_encoder);
3019
3020 val = I915_READ(_FDI_RXA_CTL);
3021 val &= ~FDI_RX_ENABLE;
3022 I915_WRITE(_FDI_RXA_CTL, val);
3023
3024 val = I915_READ(_FDI_RXA_MISC);
3025 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3026 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3027 I915_WRITE(_FDI_RXA_MISC, val);
3028
3029 val = I915_READ(_FDI_RXA_CTL);
3030 val &= ~FDI_PCDCLK;
3031 I915_WRITE(_FDI_RXA_CTL, val);
3032
3033 val = I915_READ(_FDI_RXA_CTL);
3034 val &= ~FDI_RX_PLL_ENABLE;
3035 I915_WRITE(_FDI_RXA_CTL, val);
3036}
3037
6801c18c 3038void intel_ddi_get_config(struct intel_encoder *encoder,
5cec258b 3039 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 3040{
3041 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
3042 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
0cb09a97 3043 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
bbd440fb 3044 struct intel_hdmi *intel_hdmi;
045ac3b5
JB		 3045 u32 temp, flags = 0;
3046
3047 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3048 if (temp & TRANS_DDI_PHSYNC)
3049 flags |= DRM_MODE_FLAG_PHSYNC;
3050 else
3051 flags |= DRM_MODE_FLAG_NHSYNC;
3052 if (temp & TRANS_DDI_PVSYNC)
3053 flags |= DRM_MODE_FLAG_PVSYNC;
3054 else
3055 flags |= DRM_MODE_FLAG_NVSYNC;
3056
2d112de7 3057 pipe_config->base.adjusted_mode.flags |= flags;
42571aef
VS		 3058
3059 switch (temp & TRANS_DDI_BPC_MASK) {
3060 case TRANS_DDI_BPC_6:
3061 pipe_config->pipe_bpp = 18;
3062 break;
3063 case TRANS_DDI_BPC_8:
3064 pipe_config->pipe_bpp = 24;
3065 break;
3066 case TRANS_DDI_BPC_10:
3067 pipe_config->pipe_bpp = 30;
3068 break;
3069 case TRANS_DDI_BPC_12:
3070 pipe_config->pipe_bpp = 36;
3071 break;
3072 default:
3073 break;
3074 }
eb14cb74
VS		 3075
3076 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3077 case TRANS_DDI_MODE_SELECT_HDMI:
6897b4b5 3078 pipe_config->has_hdmi_sink = true;
bbd440fb
DV		 3079 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
3080
3081 if (intel_hdmi->infoframe_enabled(&encoder->base))
3082 pipe_config->has_infoframe = true;
cbc572a9 3083 break;
eb14cb74
VS		 3084 case TRANS_DDI_MODE_SELECT_DVI:
3085 case TRANS_DDI_MODE_SELECT_FDI:
3086 break;
3087 case TRANS_DDI_MODE_SELECT_DP_SST:
3088 case TRANS_DDI_MODE_SELECT_DP_MST:
3089 pipe_config->has_dp_encoder = true;
90a6b7b0
VS		 3090 pipe_config->lane_count =
3091 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
eb14cb74
VS		 3092 intel_dp_get_m_n(intel_crtc, pipe_config);
3093 break;
3094 default:
3095 break;
3096 }
10214420 3097
f458ebbc 3098 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
a60551b1 3099 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
82910ac6 3100 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
a60551b1
PZ		 3101 pipe_config->has_audio = true;
3102 }
9ed109a7 3103
10214420
DV		 3104 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
3105 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
3106 /*
3107 * This is a big fat ugly hack.
3108 *
3109 * Some machines in UEFI boot mode provide us a VBT that has 18
3110 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3111 * unknown we fail to light up. Yet the same BIOS boots up with
3112 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3113 * max, not what it tells us to use.
3114 *
3115 * Note: This will still be broken if the eDP panel is not lit
3116 * up by the BIOS, and thus we can't get the mode at module
3117 * load.
3118 */
3119 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3120 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
3121 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
3122 }
11578553 3123
22606a18 3124 intel_ddi_clock_get(encoder, pipe_config);
045ac3b5
JB		 3125}
3126
00c09d70
PZ		 3127static void intel_ddi_destroy(struct drm_encoder *encoder)
3128{
3129 /* HDMI has nothing special to destroy, so we can go with this. */
3130 intel_dp_encoder_destroy(encoder);
3131}
3132
5bfe2ac0 3133static bool intel_ddi_compute_config(struct intel_encoder *encoder,
5cec258b 3134 struct intel_crtc_state *pipe_config)
00c09d70 3135{
5bfe2ac0 3136 int type = encoder->type;
eccb140b 3137 int port = intel_ddi_get_encoder_port(encoder);
00c09d70 3138
5bfe2ac0 3139 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
00c09d70 3140
eccb140b
DV		 3141 if (port == PORT_A)
3142 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3143
00c09d70 3144 if (type == INTEL_OUTPUT_HDMI)
5bfe2ac0 3145 return intel_hdmi_compute_config(encoder, pipe_config);
00c09d70 3146 else
5bfe2ac0 3147 return intel_dp_compute_config(encoder, pipe_config);
00c09d70
PZ		 3148}
3149
3150static const struct drm_encoder_funcs intel_ddi_funcs = {
3151 .destroy = intel_ddi_destroy,
3152};
3153
4a28ae58
PZ		 3154static struct intel_connector *
3155intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
3156{
3157 struct intel_connector *connector;
3158 enum port port = intel_dig_port->port;
3159
9bdbd0b9 3160 connector = intel_connector_alloc();
4a28ae58
PZ		 3161 if (!connector)
3162 return NULL;
3163
3164 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
3165 if (!intel_dp_init_connector(intel_dig_port, connector)) {
3166 kfree(connector);
3167 return NULL;
3168 }
3169
3170 return connector;
3171}
3172
3173static struct intel_connector *
3174intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
3175{
3176 struct intel_connector *connector;
3177 enum port port = intel_dig_port->port;
3178
9bdbd0b9 3179 connector = intel_connector_alloc();
4a28ae58
PZ		 3180 if (!connector)
3181 return NULL;
3182
3183 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
3184 intel_hdmi_init_connector(intel_dig_port, connector);
3185
3186 return connector;
3187}
3188
00c09d70
PZ		 3189void intel_ddi_init(struct drm_device *dev, enum port port)
3190{
876a8cdf 3191 struct drm_i915_private *dev_priv = dev->dev_private;
00c09d70
PZ		 3192 struct intel_digital_port *intel_dig_port;
3193 struct intel_encoder *intel_encoder;
3194 struct drm_encoder *encoder;
311a2094
PZ		 3195 bool init_hdmi, init_dp;
3196
3197 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
3198 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
3199 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
3200 if (!init_dp && !init_hdmi) {
500ea70d 3201 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
311a2094 3202 port_name(port));
500ea70d 3203 return;
311a2094 3204 }
00c09d70 3205
b14c5679 3206 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
00c09d70
PZ		 3207 if (!intel_dig_port)
3208 return;
3209
00c09d70
PZ		 3210 intel_encoder = &intel_dig_port->base;
3211 encoder = &intel_encoder->base;
3212
3213 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
3214 DRM_MODE_ENCODER_TMDS);
00c09d70 3215
5bfe2ac0 3216 intel_encoder->compute_config = intel_ddi_compute_config;
00c09d70
PZ		 3217 intel_encoder->enable = intel_enable_ddi;
3218 intel_encoder->pre_enable = intel_ddi_pre_enable;
3219 intel_encoder->disable = intel_disable_ddi;
3220 intel_encoder->post_disable = intel_ddi_post_disable;
3221 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
045ac3b5 3222 intel_encoder->get_config = intel_ddi_get_config;
00c09d70
PZ		 3223
3224 intel_dig_port->port = port;
bcf53de4
SM		 3225 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
3226 (DDI_BUF_PORT_REVERSAL |
3227 DDI_A_4_LANES);
00c09d70
PZ		 3228
3229 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
f68d697e 3230 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
bc079e8b 3231 intel_encoder->cloneable = 0;
00c09d70 3232
f68d697e
CW		 3233 if (init_dp) {
3234 if (!intel_ddi_init_dp_connector(intel_dig_port))
3235 goto err;
13cf5504 3236
f68d697e 3237 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
cf1d5883
SJ		 3238 /*
3239 * On BXT A0/A1, sw needs to activate DDIA HPD logic and
3240 * interrupts to check the external panel connection.
3241 */
3242 if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0)
3243 && port == PORT_B)
3244 dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port;
3245 else
3246 dev_priv->hotplug.irq_port[port] = intel_dig_port;
f68d697e 3247 }
21a8e6a4 3248
311a2094
PZ		 3249 /* In theory we don't need the encoder->type check, but leave it just in
3250 * case we have some really bad VBTs... */
f68d697e
CW		 3251 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
3252 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
3253 goto err;
21a8e6a4 3254 }
f68d697e
CW		 3255
3256 return;
3257
3258err:
3259 drm_encoder_cleanup(encoder);
3260 kfree(intel_dig_port);
00c09d70 3261}
Linux kernel - Deliverables
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