projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915/bxt: VSwing programming sequence
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ddi.c
CommitLineData
45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include "i915_drv.h"
29#include "intel_drv.h"
30
10122051
JN		 31struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
34};
35
45244b87
ED		 36/* HDMI/DVI modes ignore everything but the last 2 items. So we share
37 * them for both DP and FDI transports, allowing those ports to
38 * automatically adapt to HDMI connections as well
39 */
10122051
JN		 40static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
41 { 0x00FFFFFF, 0x0006000E },
42 { 0x00D75FFF, 0x0005000A },
43 { 0x00C30FFF, 0x00040006 },
44 { 0x80AAAFFF, 0x000B0000 },
45 { 0x00FFFFFF, 0x0005000A },
46 { 0x00D75FFF, 0x000C0004 },
47 { 0x80C30FFF, 0x000B0000 },
48 { 0x00FFFFFF, 0x00040006 },
49 { 0x80D75FFF, 0x000B0000 },
45244b87
ED		 50};
51
10122051
JN		 52static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
53 { 0x00FFFFFF, 0x0007000E },
54 { 0x00D75FFF, 0x000F000A },
55 { 0x00C30FFF, 0x00060006 },
56 { 0x00AAAFFF, 0x001E0000 },
57 { 0x00FFFFFF, 0x000F000A },
58 { 0x00D75FFF, 0x00160004 },
59 { 0x00C30FFF, 0x001E0000 },
60 { 0x00FFFFFF, 0x00060006 },
61 { 0x00D75FFF, 0x001E0000 },
6acab15a
PZ		 62};
63
10122051
JN		 64static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
65 /* Idx NT mV d T mV d db */
66 { 0x00FFFFFF, 0x0006000E }, /* 0: 400 400 0 */
67 { 0x00E79FFF, 0x000E000C }, /* 1: 400 500 2 */
68 { 0x00D75FFF, 0x0005000A }, /* 2: 400 600 3.5 */
69 { 0x00FFFFFF, 0x0005000A }, /* 3: 600 600 0 */
70 { 0x00E79FFF, 0x001D0007 }, /* 4: 600 750 2 */
71 { 0x00D75FFF, 0x000C0004 }, /* 5: 600 900 3.5 */
72 { 0x00FFFFFF, 0x00040006 }, /* 6: 800 800 0 */
73 { 0x80E79FFF, 0x00030002 }, /* 7: 800 1000 2 */
74 { 0x00FFFFFF, 0x00140005 }, /* 8: 850 850 0 */
75 { 0x00FFFFFF, 0x000C0004 }, /* 9: 900 900 0 */
76 { 0x00FFFFFF, 0x001C0003 }, /* 10: 950 950 0 */
77 { 0x80FFFFFF, 0x00030002 }, /* 11: 1000 1000 0 */
45244b87
ED		 78};
79
10122051
JN		 80static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
81 { 0x00FFFFFF, 0x00000012 },
82 { 0x00EBAFFF, 0x00020011 },
83 { 0x00C71FFF, 0x0006000F },
84 { 0x00AAAFFF, 0x000E000A },
85 { 0x00FFFFFF, 0x00020011 },
86 { 0x00DB6FFF, 0x0005000F },
87 { 0x00BEEFFF, 0x000A000C },
88 { 0x00FFFFFF, 0x0005000F },
89 { 0x00DB6FFF, 0x000A000C },
300644c7
PZ		 90};
91
10122051
JN		 92static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
93 { 0x00FFFFFF, 0x0007000E },
94 { 0x00D75FFF, 0x000E000A },
95 { 0x00BEFFFF, 0x00140006 },
96 { 0x80B2CFFF, 0x001B0002 },
97 { 0x00FFFFFF, 0x000E000A },
17b523ba 98 { 0x00DB6FFF, 0x00160005 },
6805b2a7 99 { 0x80C71FFF, 0x001A0002 },
10122051
JN		 100 { 0x00F7DFFF, 0x00180004 },
101 { 0x80D75FFF, 0x001B0002 },
e58623cb
AR		 102};
103
10122051
JN		 104static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
105 { 0x00FFFFFF, 0x0001000E },
106 { 0x00D75FFF, 0x0004000A },
107 { 0x00C30FFF, 0x00070006 },
108 { 0x00AAAFFF, 0x000C0000 },
109 { 0x00FFFFFF, 0x0004000A },
110 { 0x00D75FFF, 0x00090004 },
111 { 0x00C30FFF, 0x000C0000 },
112 { 0x00FFFFFF, 0x00070006 },
113 { 0x00D75FFF, 0x000C0000 },
e58623cb
AR		 114};
115
10122051
JN		 116static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
117 /* Idx NT mV d T mV df db */
118 { 0x00FFFFFF, 0x0007000E }, /* 0: 400 400 0 */
119 { 0x00D75FFF, 0x000E000A }, /* 1: 400 600 3.5 */
120 { 0x00BEFFFF, 0x00140006 }, /* 2: 400 800 6 */
121 { 0x00FFFFFF, 0x0009000D }, /* 3: 450 450 0 */
122 { 0x00FFFFFF, 0x000E000A }, /* 4: 600 600 0 */
123 { 0x00D7FFFF, 0x00140006 }, /* 5: 600 800 2.5 */
124 { 0x80CB2FFF, 0x001B0002 }, /* 6: 600 1000 4.5 */
125 { 0x00FFFFFF, 0x00140006 }, /* 7: 800 800 0 */
126 { 0x80E79FFF, 0x001B0002 }, /* 8: 800 1000 2 */
127 { 0x80FFFFFF, 0x001B0002 }, /* 9: 1000 1000 0 */
a26aa8ba
DL		 128};
129
7f88e3af 130static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
6c930688
DL		 131 { 0x00000018, 0x000000a2 },
132 { 0x00004014, 0x0000009B },
7f88e3af 133 { 0x00006012, 0x00000088 },
6c930688
DL		 134 { 0x00008010, 0x00000087 },
135 { 0x00000018, 0x0000009B },
7f88e3af 136 { 0x00004014, 0x00000088 },
6c930688 137 { 0x00006012, 0x00000087 },
7f88e3af 138 { 0x00000018, 0x00000088 },
6c930688 139 { 0x00004014, 0x00000087 },
7f88e3af
DL		 140};
141
7ad14a29
SJ		 142/* eDP 1.4 low vswing translation parameters */
143static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
144 { 0x00000018, 0x000000a8 },
145 { 0x00002016, 0x000000ab },
146 { 0x00006012, 0x000000a2 },
147 { 0x00008010, 0x00000088 },
148 { 0x00000018, 0x000000ab },
149 { 0x00004014, 0x000000a2 },
150 { 0x00006012, 0x000000a6 },
151 { 0x00000018, 0x000000a2 },
152 { 0x00005013, 0x0000009c },
153 { 0x00000018, 0x00000088 },
154};
155
156
7f88e3af 157static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
b7192a56
SJ		 158 { 0x00000018, 0x000000ac },
159 { 0x00005012, 0x0000009d },
160 { 0x00007011, 0x00000088 },
161 { 0x00000018, 0x000000a1 },
162 { 0x00000018, 0x00000098 },
163 { 0x00004013, 0x00000088 },
164 { 0x00006012, 0x00000087 },
165 { 0x00000018, 0x000000df },
166 { 0x00003015, 0x00000087 },
167 { 0x00003015, 0x000000c7 },
168 { 0x00000018, 0x000000c7 },
7f88e3af
DL		 169};
170
96fb9f9b
VK		 171struct bxt_ddi_buf_trans {
172 u32 margin; /* swing value */
173 u32 scale; /* scale value */
174 u32 enable; /* scale enable */
175 u32 deemphasis;
176 bool default_index; /* true if the entry represents default value */
177};
178
179/* BSpec does not define separate vswing/pre-emphasis values for eDP.
180 * Using DP values for eDP as well.
181 */
182static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
183 /* Idx NT mV diff db */
184 { 52, 0, 0, 128, true }, /* 0: 400 0 */
185 { 78, 0, 0, 85, false }, /* 1: 400 3.5 */
186 { 104, 0, 0, 64, false }, /* 2: 400 6 */
187 { 154, 0, 0, 43, false }, /* 3: 400 9.5 */
188 { 77, 0, 0, 128, false }, /* 4: 600 0 */
189 { 116, 0, 0, 85, false }, /* 5: 600 3.5 */
190 { 154, 0, 0, 64, false }, /* 6: 600 6 */
191 { 102, 0, 0, 128, false }, /* 7: 800 0 */
192 { 154, 0, 0, 85, false }, /* 8: 800 3.5 */
193 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
194};
195
196/* BSpec has 2 recommended values - entries 0 and 8.
197 * Using the entry with higher vswing.
198 */
199static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
200 /* Idx NT mV diff db */
201 { 52, 0, 0, 128, false }, /* 0: 400 0 */
202 { 52, 0, 0, 85, false }, /* 1: 400 3.5 */
203 { 52, 0, 0, 64, false }, /* 2: 400 6 */
204 { 42, 0, 0, 43, false }, /* 3: 400 9.5 */
205 { 77, 0, 0, 128, false }, /* 4: 600 0 */
206 { 77, 0, 0, 85, false }, /* 5: 600 3.5 */
207 { 77, 0, 0, 64, false }, /* 6: 600 6 */
208 { 102, 0, 0, 128, false }, /* 7: 800 0 */
209 { 102, 0, 0, 85, false }, /* 8: 800 3.5 */
210 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
211};
212
20f4dbe4 213enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
fc914639 214{
0bdee30e 215 struct drm_encoder *encoder = &intel_encoder->base;
fc914639
PZ		 216 int type = intel_encoder->type;
217
0e32b39c
DA		 218 if (type == INTEL_OUTPUT_DP_MST) {
219 struct intel_digital_port *intel_dig_port = enc_to_mst(encoder)->primary;
220 return intel_dig_port->port;
221 } else if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
00c09d70 222 type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
174edf1f
PZ		 223 struct intel_digital_port *intel_dig_port =
224 enc_to_dig_port(encoder);
225 return intel_dig_port->port;
0bdee30e 226
fc914639
PZ		 227 } else if (type == INTEL_OUTPUT_ANALOG) {
228 return PORT_E;
0bdee30e 229
fc914639
PZ		 230 } else {
231 DRM_ERROR("Invalid DDI encoder type %d\n", type);
232 BUG();
233 }
234}
235
ce3b7e9b
DL		 236static bool
237intel_dig_port_supports_hdmi(const struct intel_digital_port *intel_dig_port)
238{
239 return intel_dig_port->hdmi.hdmi_reg;
240}
241
e58623cb
AR		 242/*
243 * Starting with Haswell, DDI port buffers must be programmed with correct
244 * values in advance. The buffer values are different for FDI and DP modes,
45244b87
ED		 245 * but the HDMI/DVI fields are shared among those. So we program the DDI
246 * in either FDI or DP modes only, as HDMI connections will work with both
247 * of those
248 */
b403745c
DL		 249static void intel_prepare_ddi_buffers(struct drm_device *dev,
250 struct intel_digital_port *intel_dig_port)
45244b87
ED		 251{
252 struct drm_i915_private *dev_priv = dev->dev_private;
253 u32 reg;
b403745c 254 int port = intel_dig_port->port;
7ff44670 255 int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry,
7ad14a29 256 size;
6acab15a 257 int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
10122051
JN		 258 const struct ddi_buf_trans *ddi_translations_fdi;
259 const struct ddi_buf_trans *ddi_translations_dp;
260 const struct ddi_buf_trans *ddi_translations_edp;
261 const struct ddi_buf_trans *ddi_translations_hdmi;
262 const struct ddi_buf_trans *ddi_translations;
e58623cb 263
96fb9f9b
VK		 264 if (IS_BROXTON(dev)) {
265 if (!intel_dig_port_supports_hdmi(intel_dig_port))
266 return;
267
268 /* Vswing programming for HDMI */
269 bxt_ddi_vswing_sequence(dev, hdmi_level, port,
270 INTEL_OUTPUT_HDMI);
271 return;
272 } else if (IS_SKYLAKE(dev)) {
7f88e3af
DL		 273 ddi_translations_fdi = NULL;
274 ddi_translations_dp = skl_ddi_translations_dp;
7ad14a29
SJ		 275 n_dp_entries = ARRAY_SIZE(skl_ddi_translations_dp);
276 if (dev_priv->vbt.edp_low_vswing) {
277 ddi_translations_edp = skl_ddi_translations_edp;
278 n_edp_entries = ARRAY_SIZE(skl_ddi_translations_edp);
279 } else {
280 ddi_translations_edp = skl_ddi_translations_dp;
281 n_edp_entries = ARRAY_SIZE(skl_ddi_translations_dp);
282 }
283
7f88e3af
DL		 284 ddi_translations_hdmi = skl_ddi_translations_hdmi;
285 n_hdmi_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
b7192a56 286 hdmi_default_entry = 7;
7f88e3af 287 } else if (IS_BROADWELL(dev)) {
e58623cb
AR		 288 ddi_translations_fdi = bdw_ddi_translations_fdi;
289 ddi_translations_dp = bdw_ddi_translations_dp;
300644c7 290 ddi_translations_edp = bdw_ddi_translations_edp;
a26aa8ba 291 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
7ad14a29
SJ		 292 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
293 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 294 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
7ff44670 295 hdmi_default_entry = 7;
e58623cb
AR		 296 } else if (IS_HASWELL(dev)) {
297 ddi_translations_fdi = hsw_ddi_translations_fdi;
298 ddi_translations_dp = hsw_ddi_translations_dp;
300644c7 299 ddi_translations_edp = hsw_ddi_translations_dp;
a26aa8ba 300 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
7ad14a29 301 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
10122051 302 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
7ff44670 303 hdmi_default_entry = 6;
e58623cb
AR		 304 } else {
305 WARN(1, "ddi translation table missing\n");
300644c7 306 ddi_translations_edp = bdw_ddi_translations_dp;
e58623cb
AR		 307 ddi_translations_fdi = bdw_ddi_translations_fdi;
308 ddi_translations_dp = bdw_ddi_translations_dp;
a26aa8ba 309 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
7ad14a29
SJ		 310 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
311 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 312 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
7ff44670 313 hdmi_default_entry = 7;
e58623cb
AR		 314 }
315
300644c7
PZ		 316 switch (port) {
317 case PORT_A:
318 ddi_translations = ddi_translations_edp;
7ad14a29 319 size = n_edp_entries;
300644c7
PZ		 320 break;
321 case PORT_B:
322 case PORT_C:
300644c7 323 ddi_translations = ddi_translations_dp;
7ad14a29 324 size = n_dp_entries;
300644c7 325 break;
77d8d009 326 case PORT_D:
7ad14a29 327 if (intel_dp_is_edp(dev, PORT_D)) {
77d8d009 328 ddi_translations = ddi_translations_edp;
7ad14a29
SJ		 329 size = n_edp_entries;
330 } else {
77d8d009 331 ddi_translations = ddi_translations_dp;
7ad14a29
SJ		 332 size = n_dp_entries;
333 }
77d8d009 334 break;
300644c7 335 case PORT_E:
7f88e3af
DL		 336 if (ddi_translations_fdi)
337 ddi_translations = ddi_translations_fdi;
338 else
339 ddi_translations = ddi_translations_dp;
7ad14a29 340 size = n_dp_entries;
300644c7
PZ		 341 break;
342 default:
343 BUG();
344 }
45244b87 345
7ad14a29 346 for (i = 0, reg = DDI_BUF_TRANS(port); i < size; i++) {
10122051
JN		 347 I915_WRITE(reg, ddi_translations[i].trans1);
348 reg += 4;
349 I915_WRITE(reg, ddi_translations[i].trans2);
45244b87
ED		 350 reg += 4;
351 }
ce4dd49e 352
ce3b7e9b
DL		 353 if (!intel_dig_port_supports_hdmi(intel_dig_port))
354 return;
355
ce4dd49e
DL		 356 /* Choose a good default if VBT is badly populated */
357 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
358 hdmi_level >= n_hdmi_entries)
7ff44670 359 hdmi_level = hdmi_default_entry;
ce4dd49e 360
6acab15a 361 /* Entry 9 is for HDMI: */
10122051
JN		 362 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans1);
363 reg += 4;
364 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans2);
365 reg += 4;
45244b87
ED		 366}
367
368/* Program DDI buffers translations for DP. By default, program ports A-D in DP
369 * mode and port E for FDI.
370 */
371void intel_prepare_ddi(struct drm_device *dev)
372{
b403745c
DL		 373 struct intel_digital_port *intel_dig_port;
374 bool visited[I915_MAX_PORTS] = { 0, };
45244b87 375
0d536cb4
PZ		 376 if (!HAS_DDI(dev))
377 return;
45244b87 378
b403745c
DL		 379 for_each_digital_port(dev, intel_dig_port) {
380 if (visited[intel_dig_port->port])
381 continue;
382
383 intel_prepare_ddi_buffers(dev, intel_dig_port);
384 visited[intel_dig_port->port] = true;
385 }
45244b87 386}
c82e4d26 387
248138b5
PZ		 388static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
389 enum port port)
390{
391 uint32_t reg = DDI_BUF_CTL(port);
392 int i;
393
3449ca85 394 for (i = 0; i < 16; i++) {
248138b5
PZ		 395 udelay(1);
396 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
397 return;
398 }
399 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
400}
c82e4d26
ED		 401
402/* Starting with Haswell, different DDI ports can work in FDI mode for
403 * connection to the PCH-located connectors. For this, it is necessary to train
404 * both the DDI port and PCH receiver for the desired DDI buffer settings.
405 *
406 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
407 * please note that when FDI mode is active on DDI E, it shares 2 lines with
408 * DDI A (which is used for eDP)
409 */
410
411void hsw_fdi_link_train(struct drm_crtc *crtc)
412{
413 struct drm_device *dev = crtc->dev;
414 struct drm_i915_private *dev_priv = dev->dev_private;
415 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
04945641 416 u32 temp, i, rx_ctl_val;
c82e4d26 417
04945641
PZ		 418 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
419 * mode set "sequence for CRT port" document:
420 * - TP1 to TP2 time with the default value
421 * - FDI delay to 90h
8693a824
DL		 422 *
423 * WaFDIAutoLinkSetTimingOverrride:hsw
04945641
PZ		 424 */
425 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
426 FDI_RX_PWRDN_LANE0_VAL(2) |
427 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
428
429 /* Enable the PCH Receiver FDI PLL */
3e68320e 430 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
33d29b14 431 FDI_RX_PLL_ENABLE |
6e3c9717 432 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
04945641
PZ		 433 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
434 POSTING_READ(_FDI_RXA_CTL);
435 udelay(220);
436
437 /* Switch from Rawclk to PCDclk */
438 rx_ctl_val |= FDI_PCDCLK;
439 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
440
441 /* Configure Port Clock Select */
6e3c9717
ACO		 442 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
443 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
04945641
PZ		 444
445 /* Start the training iterating through available voltages and emphasis,
446 * testing each value twice. */
10122051 447 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
c82e4d26
ED		 448 /* Configure DP_TP_CTL with auto-training */
449 I915_WRITE(DP_TP_CTL(PORT_E),
450 DP_TP_CTL_FDI_AUTOTRAIN |
451 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
452 DP_TP_CTL_LINK_TRAIN_PAT1 |
453 DP_TP_CTL_ENABLE);
454
876a8cdf
DL		 455 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
456 * DDI E does not support port reversal, the functionality is
457 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
458 * port reversal bit */
c82e4d26 459 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641 460 DDI_BUF_CTL_ENABLE |
6e3c9717 461 ((intel_crtc->config->fdi_lanes - 1) << 1) |
c5fe6a06 462 DDI_BUF_TRANS_SELECT(i / 2));
04945641 463 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 464
465 udelay(600);
466
04945641
PZ		 467 /* Program PCH FDI Receiver TU */
468 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
469
470 /* Enable PCH FDI Receiver with auto-training */
471 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
472 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
473 POSTING_READ(_FDI_RXA_CTL);
474
475 /* Wait for FDI receiver lane calibration */
476 udelay(30);
477
478 /* Unset FDI_RX_MISC pwrdn lanes */
479 temp = I915_READ(_FDI_RXA_MISC);
480 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
481 I915_WRITE(_FDI_RXA_MISC, temp);
482 POSTING_READ(_FDI_RXA_MISC);
483
484 /* Wait for FDI auto training time */
485 udelay(5);
c82e4d26
ED		 486
487 temp = I915_READ(DP_TP_STATUS(PORT_E));
488 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 489 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
c82e4d26
ED		 490
491 /* Enable normal pixel sending for FDI */
492 I915_WRITE(DP_TP_CTL(PORT_E),
04945641
PZ		 493 DP_TP_CTL_FDI_AUTOTRAIN |
494 DP_TP_CTL_LINK_TRAIN_NORMAL |
495 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
496 DP_TP_CTL_ENABLE);
c82e4d26 497
04945641 498 return;
c82e4d26 499 }
04945641 500
248138b5
PZ		 501 temp = I915_READ(DDI_BUF_CTL(PORT_E));
502 temp &= ~DDI_BUF_CTL_ENABLE;
503 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
504 POSTING_READ(DDI_BUF_CTL(PORT_E));
505
04945641 506 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
248138b5
PZ		 507 temp = I915_READ(DP_TP_CTL(PORT_E));
508 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
509 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
510 I915_WRITE(DP_TP_CTL(PORT_E), temp);
511 POSTING_READ(DP_TP_CTL(PORT_E));
512
513 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
04945641
PZ		 514
515 rx_ctl_val &= ~FDI_RX_ENABLE;
516 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
248138b5 517 POSTING_READ(_FDI_RXA_CTL);
04945641
PZ		 518
519 /* Reset FDI_RX_MISC pwrdn lanes */
520 temp = I915_READ(_FDI_RXA_MISC);
521 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
522 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
523 I915_WRITE(_FDI_RXA_MISC, temp);
248138b5 524 POSTING_READ(_FDI_RXA_MISC);
c82e4d26
ED		 525 }
526
04945641 527 DRM_ERROR("FDI link training failed!\n");
c82e4d26 528}
0e72a5b5 529
44905a27
DA		 530void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
531{
532 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
533 struct intel_digital_port *intel_dig_port =
534 enc_to_dig_port(&encoder->base);
535
536 intel_dp->DP = intel_dig_port->saved_port_bits |
c5fe6a06 537 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
44905a27
DA		 538 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
539
540}
541
8d9ddbcb
PZ		 542static struct intel_encoder *
543intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
544{
545 struct drm_device *dev = crtc->dev;
546 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
547 struct intel_encoder *intel_encoder, *ret = NULL;
548 int num_encoders = 0;
549
550 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
551 ret = intel_encoder;
552 num_encoders++;
553 }
554
555 if (num_encoders != 1)
84f44ce7
VS		 556 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
557 pipe_name(intel_crtc->pipe));
8d9ddbcb
PZ		 558
559 BUG_ON(ret == NULL);
560 return ret;
561}
562
bcddf610 563struct intel_encoder *
3165c074 564intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
d0737e1d 565{
3165c074
ACO		 566 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
567 struct intel_encoder *ret = NULL;
568 struct drm_atomic_state *state;
d0737e1d 569 int num_encoders = 0;
3165c074 570 int i;
d0737e1d 571
3165c074
ACO		 572 state = crtc_state->base.state;
573
574 for (i = 0; i < state->num_connector; i++) {
575 if (!state->connectors[i] ||
576 state->connector_states[i]->crtc != crtc_state->base.crtc)
577 continue;
578
579 ret = to_intel_encoder(state->connector_states[i]->best_encoder);
580 num_encoders++;
d0737e1d
ACO		 581 }
582
583 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
584 pipe_name(crtc->pipe));
585
586 BUG_ON(ret == NULL);
587 return ret;
588}
589
1c0b85c5 590#define LC_FREQ 2700
27893390 591#define LC_FREQ_2K U64_C(LC_FREQ * 2000)
1c0b85c5
DL		 592
593#define P_MIN 2
594#define P_MAX 64
595#define P_INC 2
596
597/* Constraints for PLL good behavior */
598#define REF_MIN 48
599#define REF_MAX 400
600#define VCO_MIN 2400
601#define VCO_MAX 4800
602
27893390
DL		 603#define abs_diff(a, b) ({ \
604 typeof(a) __a = (a); \
605 typeof(b) __b = (b); \
606 (void) (&__a == &__b); \
607 __a > __b ? (__a - __b) : (__b - __a); })
1c0b85c5
DL		 608
609struct wrpll_rnp {
610 unsigned p, n2, r2;
611};
612
613static unsigned wrpll_get_budget_for_freq(int clock)
6441ab5f 614{
1c0b85c5
DL		 615 unsigned budget;
616
617 switch (clock) {
618 case 25175000:
619 case 25200000:
620 case 27000000:
621 case 27027000:
622 case 37762500:
623 case 37800000:
624 case 40500000:
625 case 40541000:
626 case 54000000:
627 case 54054000:
628 case 59341000:
629 case 59400000:
630 case 72000000:
631 case 74176000:
632 case 74250000:
633 case 81000000:
634 case 81081000:
635 case 89012000:
636 case 89100000:
637 case 108000000:
638 case 108108000:
639 case 111264000:
640 case 111375000:
641 case 148352000:
642 case 148500000:
643 case 162000000:
644 case 162162000:
645 case 222525000:
646 case 222750000:
647 case 296703000:
648 case 297000000:
649 budget = 0;
650 break;
651 case 233500000:
652 case 245250000:
653 case 247750000:
654 case 253250000:
655 case 298000000:
656 budget = 1500;
657 break;
658 case 169128000:
659 case 169500000:
660 case 179500000:
661 case 202000000:
662 budget = 2000;
663 break;
664 case 256250000:
665 case 262500000:
666 case 270000000:
667 case 272500000:
668 case 273750000:
669 case 280750000:
670 case 281250000:
671 case 286000000:
672 case 291750000:
673 budget = 4000;
674 break;
675 case 267250000:
676 case 268500000:
677 budget = 5000;
678 break;
679 default:
680 budget = 1000;
681 break;
682 }
6441ab5f 683
1c0b85c5
DL		 684 return budget;
685}
686
687static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
688 unsigned r2, unsigned n2, unsigned p,
689 struct wrpll_rnp *best)
690{
691 uint64_t a, b, c, d, diff, diff_best;
6441ab5f 692
1c0b85c5
DL		 693 /* No best (r,n,p) yet */
694 if (best->p == 0) {
695 best->p = p;
696 best->n2 = n2;
697 best->r2 = r2;
698 return;
699 }
6441ab5f 700
1c0b85c5
DL		 701 /*
702 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
703 * freq2k.
704 *
705 * delta = 1e6 *
706 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
707 * freq2k;
708 *
709 * and we would like delta <= budget.
710 *
711 * If the discrepancy is above the PPM-based budget, always prefer to
712 * improve upon the previous solution. However, if you're within the
713 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
714 */
715 a = freq2k * budget * p * r2;
716 b = freq2k * budget * best->p * best->r2;
27893390
DL		 717 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
718 diff_best = abs_diff(freq2k * best->p * best->r2,
719 LC_FREQ_2K * best->n2);
1c0b85c5
DL		 720 c = 1000000 * diff;
721 d = 1000000 * diff_best;
722
723 if (a < c && b < d) {
724 /* If both are above the budget, pick the closer */
725 if (best->p * best->r2 * diff < p * r2 * diff_best) {
726 best->p = p;
727 best->n2 = n2;
728 best->r2 = r2;
729 }
730 } else if (a >= c && b < d) {
731 /* If A is below the threshold but B is above it? Update. */
732 best->p = p;
733 best->n2 = n2;
734 best->r2 = r2;
735 } else if (a >= c && b >= d) {
736 /* Both are below the limit, so pick the higher n2/(r2*r2) */
737 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
738 best->p = p;
739 best->n2 = n2;
740 best->r2 = r2;
741 }
742 }
743 /* Otherwise a < c && b >= d, do nothing */
744}
745
11578553
JB		 746static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
747 int reg)
748{
749 int refclk = LC_FREQ;
750 int n, p, r;
751 u32 wrpll;
752
753 wrpll = I915_READ(reg);
114fe488
DV		 754 switch (wrpll & WRPLL_PLL_REF_MASK) {
755 case WRPLL_PLL_SSC:
756 case WRPLL_PLL_NON_SSC:
11578553
JB		 757 /*
758 * We could calculate spread here, but our checking
759 * code only cares about 5% accuracy, and spread is a max of
760 * 0.5% downspread.
761 */
762 refclk = 135;
763 break;
114fe488 764 case WRPLL_PLL_LCPLL:
11578553
JB		 765 refclk = LC_FREQ;
766 break;
767 default:
768 WARN(1, "bad wrpll refclk\n");
769 return 0;
770 }
771
772 r = wrpll & WRPLL_DIVIDER_REF_MASK;
773 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
774 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
775
20f0ec16
JB		 776 /* Convert to KHz, p & r have a fixed point portion */
777 return (refclk * n * 100) / (p * r);
11578553
JB		 778}
779
540e732c
S		 780static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
781 uint32_t dpll)
782{
783 uint32_t cfgcr1_reg, cfgcr2_reg;
784 uint32_t cfgcr1_val, cfgcr2_val;
785 uint32_t p0, p1, p2, dco_freq;
786
787 cfgcr1_reg = GET_CFG_CR1_REG(dpll);
788 cfgcr2_reg = GET_CFG_CR2_REG(dpll);
789
790 cfgcr1_val = I915_READ(cfgcr1_reg);
791 cfgcr2_val = I915_READ(cfgcr2_reg);
792
793 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
794 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
795
796 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
797 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
798 else
799 p1 = 1;
800
801
802 switch (p0) {
803 case DPLL_CFGCR2_PDIV_1:
804 p0 = 1;
805 break;
806 case DPLL_CFGCR2_PDIV_2:
807 p0 = 2;
808 break;
809 case DPLL_CFGCR2_PDIV_3:
810 p0 = 3;
811 break;
812 case DPLL_CFGCR2_PDIV_7:
813 p0 = 7;
814 break;
815 }
816
817 switch (p2) {
818 case DPLL_CFGCR2_KDIV_5:
819 p2 = 5;
820 break;
821 case DPLL_CFGCR2_KDIV_2:
822 p2 = 2;
823 break;
824 case DPLL_CFGCR2_KDIV_3:
825 p2 = 3;
826 break;
827 case DPLL_CFGCR2_KDIV_1:
828 p2 = 1;
829 break;
830 }
831
832 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
833
834 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
835 1000) / 0x8000;
836
837 return dco_freq / (p0 * p1 * p2 * 5);
838}
839
840
841static void skl_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 842 struct intel_crtc_state *pipe_config)
540e732c
S		 843{
844 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
540e732c
S		 845 int link_clock = 0;
846 uint32_t dpll_ctl1, dpll;
847
134ffa44 848 dpll = pipe_config->ddi_pll_sel;
540e732c
S		 849
850 dpll_ctl1 = I915_READ(DPLL_CTRL1);
851
852 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
853 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
854 } else {
855 link_clock = dpll_ctl1 & DPLL_CRTL1_LINK_RATE_MASK(dpll);
856 link_clock >>= DPLL_CRTL1_LINK_RATE_SHIFT(dpll);
857
858 switch (link_clock) {
859 case DPLL_CRTL1_LINK_RATE_810:
860 link_clock = 81000;
861 break;
a8f3ef61
SJ		 862 case DPLL_CRTL1_LINK_RATE_1080:
863 link_clock = 108000;
864 break;
540e732c
S		 865 case DPLL_CRTL1_LINK_RATE_1350:
866 link_clock = 135000;
867 break;
a8f3ef61
SJ		 868 case DPLL_CRTL1_LINK_RATE_1620:
869 link_clock = 162000;
870 break;
871 case DPLL_CRTL1_LINK_RATE_2160:
872 link_clock = 216000;
873 break;
540e732c
S		 874 case DPLL_CRTL1_LINK_RATE_2700:
875 link_clock = 270000;
876 break;
877 default:
878 WARN(1, "Unsupported link rate\n");
879 break;
880 }
881 link_clock *= 2;
882 }
883
884 pipe_config->port_clock = link_clock;
885
886 if (pipe_config->has_dp_encoder)
2d112de7 887 pipe_config->base.adjusted_mode.crtc_clock =
540e732c
S		 888 intel_dotclock_calculate(pipe_config->port_clock,
889 &pipe_config->dp_m_n);
890 else
2d112de7 891 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
540e732c
S		 892}
893
3d51278a 894static void hsw_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 895 struct intel_crtc_state *pipe_config)
11578553
JB		 896{
897 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
11578553
JB		 898 int link_clock = 0;
899 u32 val, pll;
900
26804afd 901 val = pipe_config->ddi_pll_sel;
11578553
JB		 902 switch (val & PORT_CLK_SEL_MASK) {
903 case PORT_CLK_SEL_LCPLL_810:
904 link_clock = 81000;
905 break;
906 case PORT_CLK_SEL_LCPLL_1350:
907 link_clock = 135000;
908 break;
909 case PORT_CLK_SEL_LCPLL_2700:
910 link_clock = 270000;
911 break;
912 case PORT_CLK_SEL_WRPLL1:
913 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
914 break;
915 case PORT_CLK_SEL_WRPLL2:
916 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
917 break;
918 case PORT_CLK_SEL_SPLL:
919 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
920 if (pll == SPLL_PLL_FREQ_810MHz)
921 link_clock = 81000;
922 else if (pll == SPLL_PLL_FREQ_1350MHz)
923 link_clock = 135000;
924 else if (pll == SPLL_PLL_FREQ_2700MHz)
925 link_clock = 270000;
926 else {
927 WARN(1, "bad spll freq\n");
928 return;
929 }
930 break;
931 default:
932 WARN(1, "bad port clock sel\n");
933 return;
934 }
935
936 pipe_config->port_clock = link_clock * 2;
937
938 if (pipe_config->has_pch_encoder)
2d112de7 939 pipe_config->base.adjusted_mode.crtc_clock =
11578553
JB		 940 intel_dotclock_calculate(pipe_config->port_clock,
941 &pipe_config->fdi_m_n);
942 else if (pipe_config->has_dp_encoder)
2d112de7 943 pipe_config->base.adjusted_mode.crtc_clock =
11578553
JB		 944 intel_dotclock_calculate(pipe_config->port_clock,
945 &pipe_config->dp_m_n);
946 else
2d112de7 947 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
11578553
JB		 948}
949
977bb38d
S		 950static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
951 enum intel_dpll_id dpll)
952{
953 /* FIXME formula not available in bspec */
954 return 0;
955}
956
957static void bxt_ddi_clock_get(struct intel_encoder *encoder,
958 struct intel_crtc_state *pipe_config)
959{
960 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
961 enum port port = intel_ddi_get_encoder_port(encoder);
962 uint32_t dpll = port;
963
964 pipe_config->port_clock =
965 bxt_calc_pll_link(dev_priv, dpll);
966
967 if (pipe_config->has_dp_encoder)
968 pipe_config->base.adjusted_mode.crtc_clock =
969 intel_dotclock_calculate(pipe_config->port_clock,
970 &pipe_config->dp_m_n);
971 else
972 pipe_config->base.adjusted_mode.crtc_clock =
973 pipe_config->port_clock;
974}
975
3d51278a 976void intel_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 977 struct intel_crtc_state *pipe_config)
3d51278a 978{
22606a18
DL		 979 struct drm_device *dev = encoder->base.dev;
980
981 if (INTEL_INFO(dev)->gen <= 8)
982 hsw_ddi_clock_get(encoder, pipe_config);
977bb38d 983 else if (IS_SKYLAKE(dev))
22606a18 984 skl_ddi_clock_get(encoder, pipe_config);
977bb38d
S		 985 else if (IS_BROXTON(dev))
986 bxt_ddi_clock_get(encoder, pipe_config);
3d51278a
DV		 987}
988
1c0b85c5 989static void
d664c0ce
DL		 990hsw_ddi_calculate_wrpll(int clock /* in Hz */,
991 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
1c0b85c5
DL		 992{
993 uint64_t freq2k;
994 unsigned p, n2, r2;
995 struct wrpll_rnp best = { 0, 0, 0 };
996 unsigned budget;
997
998 freq2k = clock / 100;
999
1000 budget = wrpll_get_budget_for_freq(clock);
1001
1002 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
1003 * and directly pass the LC PLL to it. */
1004 if (freq2k == 5400000) {
1005 *n2_out = 2;
1006 *p_out = 1;
1007 *r2_out = 2;
1008 return;
1009 }
1010
1011 /*
1012 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
1013 * the WR PLL.
1014 *
1015 * We want R so that REF_MIN <= Ref <= REF_MAX.
1016 * Injecting R2 = 2 * R gives:
1017 * REF_MAX * r2 > LC_FREQ * 2 and
1018 * REF_MIN * r2 < LC_FREQ * 2
1019 *
1020 * Which means the desired boundaries for r2 are:
1021 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
1022 *
1023 */
1024 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
1025 r2 <= LC_FREQ * 2 / REF_MIN;
1026 r2++) {
1027
1028 /*
1029 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
1030 *
1031 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
1032 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
1033 * VCO_MAX * r2 > n2 * LC_FREQ and
1034 * VCO_MIN * r2 < n2 * LC_FREQ)
1035 *
1036 * Which means the desired boundaries for n2 are:
1037 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
1038 */
1039 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
1040 n2 <= VCO_MAX * r2 / LC_FREQ;
1041 n2++) {
1042
1043 for (p = P_MIN; p <= P_MAX; p += P_INC)
1044 wrpll_update_rnp(freq2k, budget,
1045 r2, n2, p, &best);
1046 }
1047 }
6441ab5f 1048
1c0b85c5
DL		 1049 *n2_out = best.n2;
1050 *p_out = best.p;
1051 *r2_out = best.r2;
6441ab5f
PZ		 1052}
1053
0220ab6e 1054static bool
d664c0ce 1055hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 1056 struct intel_crtc_state *crtc_state,
d664c0ce
DL		 1057 struct intel_encoder *intel_encoder,
1058 int clock)
6441ab5f 1059{
d664c0ce 1060 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
e0b01be4 1061 struct intel_shared_dpll *pll;
716c2e55 1062 uint32_t val;
1c0b85c5 1063 unsigned p, n2, r2;
6441ab5f 1064
d664c0ce 1065 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
0694001b 1066
114fe488 1067 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
0694001b
PZ		 1068 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
1069 WRPLL_DIVIDER_POST(p);
1070
190f68c5 1071 crtc_state->dpll_hw_state.wrpll = val;
6441ab5f 1072
190f68c5 1073 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
716c2e55
DV		 1074 if (pll == NULL) {
1075 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1076 pipe_name(intel_crtc->pipe));
1077 return false;
0694001b 1078 }
d452c5b6 1079
190f68c5 1080 crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
6441ab5f
PZ		 1081 }
1082
6441ab5f
PZ		 1083 return true;
1084}
1085
82d35437
S		 1086struct skl_wrpll_params {
1087 uint32_t dco_fraction;
1088 uint32_t dco_integer;
1089 uint32_t qdiv_ratio;
1090 uint32_t qdiv_mode;
1091 uint32_t kdiv;
1092 uint32_t pdiv;
1093 uint32_t central_freq;
1094};
1095
1096static void
1097skl_ddi_calculate_wrpll(int clock /* in Hz */,
1098 struct skl_wrpll_params *wrpll_params)
1099{
1100 uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
21318cce
DL		 1101 uint64_t dco_central_freq[3] = {8400000000ULL,
1102 9000000000ULL,
1103 9600000000ULL};
82d35437
S		 1104 uint32_t min_dco_deviation = 400;
1105 uint32_t min_dco_index = 3;
1106 uint32_t P0[4] = {1, 2, 3, 7};
1107 uint32_t P2[4] = {1, 2, 3, 5};
1108 bool found = false;
1109 uint32_t candidate_p = 0;
1110 uint32_t candidate_p0[3] = {0}, candidate_p1[3] = {0};
1111 uint32_t candidate_p2[3] = {0};
1112 uint32_t dco_central_freq_deviation[3];
1113 uint32_t i, P1, k, dco_count;
1114 bool retry_with_odd = false;
1115 uint64_t dco_freq;
1116
1117 /* Determine P0, P1 or P2 */
1118 for (dco_count = 0; dco_count < 3; dco_count++) {
1119 found = false;
1120 candidate_p =
1121 div64_u64(dco_central_freq[dco_count], afe_clock);
1122 if (retry_with_odd == false)
1123 candidate_p = (candidate_p % 2 == 0 ?
1124 candidate_p : candidate_p + 1);
1125
1126 for (P1 = 1; P1 < candidate_p; P1++) {
1127 for (i = 0; i < 4; i++) {
1128 if (!(P0[i] != 1 || P1 == 1))
1129 continue;
1130
1131 for (k = 0; k < 4; k++) {
1132 if (P1 != 1 && P2[k] != 2)
1133 continue;
1134
1135 if (candidate_p == P0[i] * P1 * P2[k]) {
1136 /* Found possible P0, P1, P2 */
1137 found = true;
1138 candidate_p0[dco_count] = P0[i];
1139 candidate_p1[dco_count] = P1;
1140 candidate_p2[dco_count] = P2[k];
1141 goto found;
1142 }
1143
1144 }
1145 }
1146 }
1147
1148found:
1149 if (found) {
1150 dco_central_freq_deviation[dco_count] =
1151 div64_u64(10000 *
1152 abs_diff((candidate_p * afe_clock),
1153 dco_central_freq[dco_count]),
1154 dco_central_freq[dco_count]);
1155
1156 if (dco_central_freq_deviation[dco_count] <
1157 min_dco_deviation) {
1158 min_dco_deviation =
1159 dco_central_freq_deviation[dco_count];
1160 min_dco_index = dco_count;
1161 }
1162 }
1163
1164 if (min_dco_index > 2 && dco_count == 2) {
1165 retry_with_odd = true;
1166 dco_count = 0;
1167 }
1168 }
1169
1170 if (min_dco_index > 2) {
1171 WARN(1, "No valid values found for the given pixel clock\n");
1172 } else {
1173 wrpll_params->central_freq = dco_central_freq[min_dco_index];
1174
1175 switch (dco_central_freq[min_dco_index]) {
21318cce 1176 case 9600000000ULL:
82d35437
S		 1177 wrpll_params->central_freq = 0;
1178 break;
21318cce 1179 case 9000000000ULL:
82d35437
S		 1180 wrpll_params->central_freq = 1;
1181 break;
21318cce 1182 case 8400000000ULL:
82d35437
S		 1183 wrpll_params->central_freq = 3;
1184 }
1185
1186 switch (candidate_p0[min_dco_index]) {
1187 case 1:
1188 wrpll_params->pdiv = 0;
1189 break;
1190 case 2:
1191 wrpll_params->pdiv = 1;
1192 break;
1193 case 3:
1194 wrpll_params->pdiv = 2;
1195 break;
1196 case 7:
1197 wrpll_params->pdiv = 4;
1198 break;
1199 default:
1200 WARN(1, "Incorrect PDiv\n");
1201 }
1202
1203 switch (candidate_p2[min_dco_index]) {
1204 case 5:
1205 wrpll_params->kdiv = 0;
1206 break;
1207 case 2:
1208 wrpll_params->kdiv = 1;
1209 break;
1210 case 3:
1211 wrpll_params->kdiv = 2;
1212 break;
1213 case 1:
1214 wrpll_params->kdiv = 3;
1215 break;
1216 default:
1217 WARN(1, "Incorrect KDiv\n");
1218 }
1219
1220 wrpll_params->qdiv_ratio = candidate_p1[min_dco_index];
1221 wrpll_params->qdiv_mode =
1222 (wrpll_params->qdiv_ratio == 1) ? 0 : 1;
1223
1224 dco_freq = candidate_p0[min_dco_index] *
1225 candidate_p1[min_dco_index] *
1226 candidate_p2[min_dco_index] * afe_clock;
1227
1228 /*
1229 * Intermediate values are in Hz.
1230 * Divide by MHz to match bsepc
1231 */
1232 wrpll_params->dco_integer = div_u64(dco_freq, (24 * MHz(1)));
1233 wrpll_params->dco_fraction =
1234 div_u64(((div_u64(dco_freq, 24) -
1235 wrpll_params->dco_integer * MHz(1)) * 0x8000), MHz(1));
1236
1237 }
1238}
1239
1240
1241static bool
1242skl_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 1243 struct intel_crtc_state *crtc_state,
82d35437
S		 1244 struct intel_encoder *intel_encoder,
1245 int clock)
1246{
1247 struct intel_shared_dpll *pll;
1248 uint32_t ctrl1, cfgcr1, cfgcr2;
1249
1250 /*
1251 * See comment in intel_dpll_hw_state to understand why we always use 0
1252 * as the DPLL id in this function.
1253 */
1254
1255 ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1256
1257 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1258 struct skl_wrpll_params wrpll_params = { 0, };
1259
1260 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1261
1262 skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params);
1263
1264 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
1265 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1266 wrpll_params.dco_integer;
1267
1268 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1269 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1270 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1271 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1272 wrpll_params.central_freq;
1273 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
1274 struct drm_encoder *encoder = &intel_encoder->base;
1275 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1276
1277 switch (intel_dp->link_bw) {
1278 case DP_LINK_BW_1_62:
1279 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810, 0);
1280 break;
1281 case DP_LINK_BW_2_7:
1282 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350, 0);
1283 break;
1284 case DP_LINK_BW_5_4:
1285 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700, 0);
1286 break;
1287 }
1288
1289 cfgcr1 = cfgcr2 = 0;
1290 } else /* eDP */
1291 return true;
1292
190f68c5
ACO		 1293 crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1294 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
1295 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
82d35437 1296
190f68c5 1297 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
82d35437
S		 1298 if (pll == NULL) {
1299 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1300 pipe_name(intel_crtc->pipe));
1301 return false;
1302 }
1303
1304 /* shared DPLL id 0 is DPLL 1 */
190f68c5 1305 crtc_state->ddi_pll_sel = pll->id + 1;
82d35437
S		 1306
1307 return true;
1308}
0220ab6e 1309
d683f3bc
S		 1310/* bxt clock parameters */
1311struct bxt_clk_div {
1312 uint32_t p1;
1313 uint32_t p2;
1314 uint32_t m2_int;
1315 uint32_t m2_frac;
1316 bool m2_frac_en;
1317 uint32_t n;
1318 uint32_t prop_coef;
1319 uint32_t int_coef;
1320 uint32_t gain_ctl;
1321 uint32_t targ_cnt;
1322 uint32_t lanestagger;
1323};
1324
1325/* pre-calculated values for DP linkrates */
1326static struct bxt_clk_div bxt_dp_clk_val[7] = {
1327 /* 162 */ {4, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
1328 /* 270 */ {4, 1, 27, 0, 0, 1, 3, 8, 1, 9, 0xd},
1329 /* 540 */ {2, 1, 27, 0, 0, 1, 3, 8, 1, 9, 0x18},
1330 /* 216 */ {3, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
1331 /* 243 */ {4, 1, 24, 1258291, 1, 1, 5, 11, 2, 9, 0xd},
1332 /* 324 */ {4, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
1333 /* 432 */ {3, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0x18}
1334};
1335
1336static bool
1337bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
1338 struct intel_crtc_state *crtc_state,
1339 struct intel_encoder *intel_encoder,
1340 int clock)
1341{
1342 struct intel_shared_dpll *pll;
1343 struct bxt_clk_div clk_div = {0};
1344
1345 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1346 intel_clock_t best_clock;
1347
1348 /* Calculate HDMI div */
1349 /*
1350 * FIXME: tie the following calculation into
1351 * i9xx_crtc_compute_clock
1352 */
1353 if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) {
1354 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
1355 clock, pipe_name(intel_crtc->pipe));
1356 return false;
1357 }
1358
1359 clk_div.p1 = best_clock.p1;
1360 clk_div.p2 = best_clock.p2;
1361 WARN_ON(best_clock.m1 != 2);
1362 clk_div.n = best_clock.n;
1363 clk_div.m2_int = best_clock.m2 >> 22;
1364 clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
1365 clk_div.m2_frac_en = clk_div.m2_frac != 0;
1366
1367 /* FIXME: set coef, gain, targcnt based on freq band */
1368 clk_div.prop_coef = 5;
1369 clk_div.int_coef = 11;
1370 clk_div.gain_ctl = 2;
1371 clk_div.targ_cnt = 9;
1372 if (clock > 270000)
1373 clk_div.lanestagger = 0x18;
1374 else if (clock > 135000)
1375 clk_div.lanestagger = 0x0d;
1376 else if (clock > 67000)
1377 clk_div.lanestagger = 0x07;
1378 else if (clock > 33000)
1379 clk_div.lanestagger = 0x04;
1380 else
1381 clk_div.lanestagger = 0x02;
1382 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
1383 intel_encoder->type == INTEL_OUTPUT_EDP) {
1384 struct drm_encoder *encoder = &intel_encoder->base;
1385 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1386
1387 switch (intel_dp->link_bw) {
1388 case DP_LINK_BW_1_62:
1389 clk_div = bxt_dp_clk_val[0];
1390 break;
1391 case DP_LINK_BW_2_7:
1392 clk_div = bxt_dp_clk_val[1];
1393 break;
1394 case DP_LINK_BW_5_4:
1395 clk_div = bxt_dp_clk_val[2];
1396 break;
1397 default:
1398 clk_div = bxt_dp_clk_val[0];
1399 DRM_ERROR("Unknown link rate\n");
1400 }
1401 }
1402
1403 crtc_state->dpll_hw_state.ebb0 =
1404 PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
1405 crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
1406 crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n);
1407 crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac;
1408
1409 if (clk_div.m2_frac_en)
1410 crtc_state->dpll_hw_state.pll3 =
1411 PORT_PLL_M2_FRAC_ENABLE;
1412
1413 crtc_state->dpll_hw_state.pll6 =
1414 clk_div.prop_coef | PORT_PLL_INT_COEFF(clk_div.int_coef);
1415 crtc_state->dpll_hw_state.pll6 |=
1416 PORT_PLL_GAIN_CTL(clk_div.gain_ctl);
1417
1418 crtc_state->dpll_hw_state.pll8 = clk_div.targ_cnt;
1419
1420 crtc_state->dpll_hw_state.pcsdw12 =
1421 LANESTAGGER_STRAP_OVRD | clk_div.lanestagger;
1422
1423 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1424 if (pll == NULL) {
1425 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1426 pipe_name(intel_crtc->pipe));
1427 return false;
1428 }
1429
1430 /* shared DPLL id 0 is DPLL A */
1431 crtc_state->ddi_pll_sel = pll->id;
1432
1433 return true;
1434}
1435
0220ab6e
DL		 1436/*
1437 * Tries to find a *shared* PLL for the CRTC and store it in
1438 * intel_crtc->ddi_pll_sel.
1439 *
1440 * For private DPLLs, compute_config() should do the selection for us. This
1441 * function should be folded into compute_config() eventually.
1442 */
190f68c5
ACO		 1443bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
1444 struct intel_crtc_state *crtc_state)
0220ab6e 1445{
82d35437 1446 struct drm_device *dev = intel_crtc->base.dev;
d0737e1d 1447 struct intel_encoder *intel_encoder =
3165c074 1448 intel_ddi_get_crtc_new_encoder(crtc_state);
190f68c5 1449 int clock = crtc_state->port_clock;
0220ab6e 1450
82d35437 1451 if (IS_SKYLAKE(dev))
190f68c5
ACO		 1452 return skl_ddi_pll_select(intel_crtc, crtc_state,
1453 intel_encoder, clock);
d683f3bc
S		 1454 else if (IS_BROXTON(dev))
1455 return bxt_ddi_pll_select(intel_crtc, crtc_state,
1456 intel_encoder, clock);
82d35437 1457 else
190f68c5
ACO		 1458 return hsw_ddi_pll_select(intel_crtc, crtc_state,
1459 intel_encoder, clock);
0220ab6e
DL		 1460}
1461
dae84799
PZ		 1462void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1463{
1464 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1465 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1466 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
6e3c9717 1467 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
dae84799
PZ		 1468 int type = intel_encoder->type;
1469 uint32_t temp;
1470
0e32b39c 1471 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
c9809791 1472 temp = TRANS_MSA_SYNC_CLK;
6e3c9717 1473 switch (intel_crtc->config->pipe_bpp) {
dae84799 1474 case 18:
c9809791 1475 temp |= TRANS_MSA_6_BPC;
dae84799
PZ		 1476 break;
1477 case 24:
c9809791 1478 temp |= TRANS_MSA_8_BPC;
dae84799
PZ		 1479 break;
1480 case 30:
c9809791 1481 temp |= TRANS_MSA_10_BPC;
dae84799
PZ		 1482 break;
1483 case 36:
c9809791 1484 temp |= TRANS_MSA_12_BPC;
dae84799
PZ		 1485 break;
1486 default:
4e53c2e0 1487 BUG();
dae84799 1488 }
c9809791 1489 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 1490 }
1491}
1492
0e32b39c
DA		 1493void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1494{
1495 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1496 struct drm_device *dev = crtc->dev;
1497 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1498 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
0e32b39c
DA		 1499 uint32_t temp;
1500 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1501 if (state == true)
1502 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1503 else
1504 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1505 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1506}
1507
8228c251 1508void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
8d9ddbcb
PZ		 1509{
1510 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1511 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
7739c33b 1512 struct drm_encoder *encoder = &intel_encoder->base;
c7670b10
PZ		 1513 struct drm_device *dev = crtc->dev;
1514 struct drm_i915_private *dev_priv = dev->dev_private;
8d9ddbcb 1515 enum pipe pipe = intel_crtc->pipe;
6e3c9717 1516 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
174edf1f 1517 enum port port = intel_ddi_get_encoder_port(intel_encoder);
7739c33b 1518 int type = intel_encoder->type;
8d9ddbcb
PZ		 1519 uint32_t temp;
1520
ad80a810
PZ		 1521 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1522 temp = TRANS_DDI_FUNC_ENABLE;
174edf1f 1523 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252 1524
6e3c9717 1525 switch (intel_crtc->config->pipe_bpp) {
dfcef252 1526 case 18:
ad80a810 1527 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 1528 break;
1529 case 24:
ad80a810 1530 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 1531 break;
1532 case 30:
ad80a810 1533 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 1534 break;
1535 case 36:
ad80a810 1536 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 1537 break;
1538 default:
4e53c2e0 1539 BUG();
dfcef252 1540 }
72662e10 1541
6e3c9717 1542 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 1543 temp |= TRANS_DDI_PVSYNC;
6e3c9717 1544 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 1545 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 1546
e6f0bfc4
PZ		 1547 if (cpu_transcoder == TRANSCODER_EDP) {
1548 switch (pipe) {
1549 case PIPE_A:
c7670b10
PZ		 1550 /* On Haswell, can only use the always-on power well for
1551 * eDP when not using the panel fitter, and when not
1552 * using motion blur mitigation (which we don't
1553 * support). */
fabf6e51 1554 if (IS_HASWELL(dev) &&
6e3c9717
ACO		 1555 (intel_crtc->config->pch_pfit.enabled ||
1556 intel_crtc->config->pch_pfit.force_thru))
d6dd9eb1
DV		 1557 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1558 else
1559 temp |= TRANS_DDI_EDP_INPUT_A_ON;
e6f0bfc4
PZ		 1560 break;
1561 case PIPE_B:
1562 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1563 break;
1564 case PIPE_C:
1565 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1566 break;
1567 default:
1568 BUG();
1569 break;
1570 }
1571 }
1572
7739c33b 1573 if (type == INTEL_OUTPUT_HDMI) {
6e3c9717 1574 if (intel_crtc->config->has_hdmi_sink)
ad80a810 1575 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 1576 else
ad80a810 1577 temp |= TRANS_DDI_MODE_SELECT_DVI;
8d9ddbcb 1578
7739c33b 1579 } else if (type == INTEL_OUTPUT_ANALOG) {
ad80a810 1580 temp |= TRANS_DDI_MODE_SELECT_FDI;
6e3c9717 1581 temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
7739c33b
PZ		 1582
1583 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1584 type == INTEL_OUTPUT_EDP) {
1585 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1586
0e32b39c
DA		 1587 if (intel_dp->is_mst) {
1588 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1589 } else
1590 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1591
1592 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
1593 } else if (type == INTEL_OUTPUT_DP_MST) {
1594 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
1595
1596 if (intel_dp->is_mst) {
1597 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1598 } else
1599 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
7739c33b 1600
17aa6be9 1601 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
8d9ddbcb 1602 } else {
84f44ce7
VS		 1603 WARN(1, "Invalid encoder type %d for pipe %c\n",
1604 intel_encoder->type, pipe_name(pipe));
8d9ddbcb
PZ		 1605 }
1606
ad80a810 1607 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 1608}
72662e10 1609
ad80a810
PZ		 1610void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1611 enum transcoder cpu_transcoder)
8d9ddbcb 1612{
ad80a810 1613 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
8d9ddbcb
PZ		 1614 uint32_t val = I915_READ(reg);
1615
0e32b39c 1616 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
ad80a810 1617 val |= TRANS_DDI_PORT_NONE;
8d9ddbcb 1618 I915_WRITE(reg, val);
72662e10
ED		 1619}
1620
bcbc889b
PZ		 1621bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1622{
1623 struct drm_device *dev = intel_connector->base.dev;
1624 struct drm_i915_private *dev_priv = dev->dev_private;
1625 struct intel_encoder *intel_encoder = intel_connector->encoder;
1626 int type = intel_connector->base.connector_type;
1627 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1628 enum pipe pipe = 0;
1629 enum transcoder cpu_transcoder;
882244a3 1630 enum intel_display_power_domain power_domain;
bcbc889b
PZ		 1631 uint32_t tmp;
1632
882244a3 1633 power_domain = intel_display_port_power_domain(intel_encoder);
f458ebbc 1634 if (!intel_display_power_is_enabled(dev_priv, power_domain))
882244a3
PZ		 1635 return false;
1636
bcbc889b
PZ		 1637 if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1638 return false;
1639
1640 if (port == PORT_A)
1641 cpu_transcoder = TRANSCODER_EDP;
1642 else
1a240d4d 1643 cpu_transcoder = (enum transcoder) pipe;
bcbc889b
PZ		 1644
1645 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1646
1647 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1648 case TRANS_DDI_MODE_SELECT_HDMI:
1649 case TRANS_DDI_MODE_SELECT_DVI:
1650 return (type == DRM_MODE_CONNECTOR_HDMIA);
1651
1652 case TRANS_DDI_MODE_SELECT_DP_SST:
1653 if (type == DRM_MODE_CONNECTOR_eDP)
1654 return true;
bcbc889b 1655 return (type == DRM_MODE_CONNECTOR_DisplayPort);
0e32b39c
DA		 1656 case TRANS_DDI_MODE_SELECT_DP_MST:
1657 /* if the transcoder is in MST state then
1658 * connector isn't connected */
1659 return false;
bcbc889b
PZ		 1660
1661 case TRANS_DDI_MODE_SELECT_FDI:
1662 return (type == DRM_MODE_CONNECTOR_VGA);
1663
1664 default:
1665 return false;
1666 }
1667}
1668
85234cdc
DV		 1669bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1670 enum pipe *pipe)
1671{
1672 struct drm_device *dev = encoder->base.dev;
1673 struct drm_i915_private *dev_priv = dev->dev_private;
fe43d3f5 1674 enum port port = intel_ddi_get_encoder_port(encoder);
6d129bea 1675 enum intel_display_power_domain power_domain;
85234cdc
DV		 1676 u32 tmp;
1677 int i;
1678
6d129bea 1679 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 1680 if (!intel_display_power_is_enabled(dev_priv, power_domain))
6d129bea
ID		 1681 return false;
1682
fe43d3f5 1683 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc
DV		 1684
1685 if (!(tmp & DDI_BUF_CTL_ENABLE))
1686 return false;
1687
ad80a810
PZ		 1688 if (port == PORT_A) {
1689 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 1690
ad80a810
PZ		 1691 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1692 case TRANS_DDI_EDP_INPUT_A_ON:
1693 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1694 *pipe = PIPE_A;
1695 break;
1696 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1697 *pipe = PIPE_B;
1698 break;
1699 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1700 *pipe = PIPE_C;
1701 break;
1702 }
1703
1704 return true;
1705 } else {
1706 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1707 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1708
1709 if ((tmp & TRANS_DDI_PORT_MASK)
1710 == TRANS_DDI_SELECT_PORT(port)) {
0e32b39c
DA		 1711 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST)
1712 return false;
1713
ad80a810
PZ		 1714 *pipe = i;
1715 return true;
1716 }
85234cdc
DV		 1717 }
1718 }
1719
84f44ce7 1720 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
85234cdc 1721
22f9fe50 1722 return false;
85234cdc
DV		 1723}
1724
fc914639
PZ		 1725void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1726{
1727 struct drm_crtc *crtc = &intel_crtc->base;
1728 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1729 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1730 enum port port = intel_ddi_get_encoder_port(intel_encoder);
6e3c9717 1731 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 1732
bb523fc0
PZ		 1733 if (cpu_transcoder != TRANSCODER_EDP)
1734 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1735 TRANS_CLK_SEL_PORT(port));
fc914639
PZ		 1736}
1737
1738void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1739{
1740 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
6e3c9717 1741 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 1742
bb523fc0
PZ		 1743 if (cpu_transcoder != TRANSCODER_EDP)
1744 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1745 TRANS_CLK_SEL_DISABLED);
fc914639
PZ		 1746}
1747
96fb9f9b
VK		 1748void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
1749 enum port port, int type)
1750{
1751 struct drm_i915_private *dev_priv = dev->dev_private;
1752 const struct bxt_ddi_buf_trans *ddi_translations;
1753 u32 n_entries, i;
1754 uint32_t val;
1755
1756 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1757 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
1758 ddi_translations = bxt_ddi_translations_dp;
1759 } else if (type == INTEL_OUTPUT_HDMI) {
1760 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
1761 ddi_translations = bxt_ddi_translations_hdmi;
1762 } else {
1763 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
1764 type);
1765 return;
1766 }
1767
1768 /* Check if default value has to be used */
1769 if (level >= n_entries ||
1770 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
1771 for (i = 0; i < n_entries; i++) {
1772 if (ddi_translations[i].default_index) {
1773 level = i;
1774 break;
1775 }
1776 }
1777 }
1778
1779 /*
1780 * While we write to the group register to program all lanes at once we
1781 * can read only lane registers and we pick lanes 0/1 for that.
1782 */
1783 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
1784 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
1785 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
1786
1787 val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
1788 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
1789 val |= ddi_translations[level].margin << MARGIN_000_SHIFT |
1790 ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
1791 I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
1792
1793 val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
1794 val &= ~UNIQE_TRANGE_EN_METHOD;
1795 if (ddi_translations[level].enable)
1796 val |= UNIQE_TRANGE_EN_METHOD;
1797 I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
1798
1799 val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
1800 val &= ~DE_EMPHASIS;
1801 val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
1802 I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
1803
1804 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
1805 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
1806 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
1807}
1808
00c09d70 1809static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
6441ab5f 1810{
c19b0669 1811 struct drm_encoder *encoder = &intel_encoder->base;
efa80add
S		 1812 struct drm_device *dev = encoder->dev;
1813 struct drm_i915_private *dev_priv = dev->dev_private;
30cf6db8 1814 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
6441ab5f 1815 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 1816 int type = intel_encoder->type;
96fb9f9b 1817 int hdmi_level;
6441ab5f 1818
82a4d9c0
PZ		 1819 if (type == INTEL_OUTPUT_EDP) {
1820 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4be73780 1821 intel_edp_panel_on(intel_dp);
82a4d9c0 1822 }
6441ab5f 1823
efa80add 1824 if (IS_SKYLAKE(dev)) {
6e3c9717 1825 uint32_t dpll = crtc->config->ddi_pll_sel;
efa80add
S		 1826 uint32_t val;
1827
5416d871
DL		 1828 /*
1829 * DPLL0 is used for eDP and is the only "private" DPLL (as
1830 * opposed to shared) on SKL
1831 */
1832 if (type == INTEL_OUTPUT_EDP) {
1833 WARN_ON(dpll != SKL_DPLL0);
1834
1835 val = I915_READ(DPLL_CTRL1);
1836
1837 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
1838 DPLL_CTRL1_SSC(dpll) |
1839 DPLL_CRTL1_LINK_RATE_MASK(dpll));
6e3c9717 1840 val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6);
5416d871
DL		 1841
1842 I915_WRITE(DPLL_CTRL1, val);
1843 POSTING_READ(DPLL_CTRL1);
1844 }
1845
1846 /* DDI -> PLL mapping */
efa80add
S		 1847 val = I915_READ(DPLL_CTRL2);
1848
1849 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
1850 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
1851 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
1852 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
1853
1854 I915_WRITE(DPLL_CTRL2, val);
5416d871 1855
1ab23380 1856 } else if (INTEL_INFO(dev)->gen < 9) {
6e3c9717
ACO		 1857 WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE);
1858 I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel);
efa80add 1859 }
c19b0669 1860
82a4d9c0 1861 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
c19b0669 1862 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
30cf6db8 1863
44905a27 1864 intel_ddi_init_dp_buf_reg(intel_encoder);
c19b0669
PZ		 1865
1866 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1867 intel_dp_start_link_train(intel_dp);
1868 intel_dp_complete_link_train(intel_dp);
23f08d83 1869 if (port != PORT_A || INTEL_INFO(dev)->gen >= 9)
3ab9c637 1870 intel_dp_stop_link_train(intel_dp);
30cf6db8
DV		 1871 } else if (type == INTEL_OUTPUT_HDMI) {
1872 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1873
96fb9f9b
VK		 1874 if (IS_BROXTON(dev)) {
1875 hdmi_level = dev_priv->vbt.
1876 ddi_port_info[port].hdmi_level_shift;
1877 bxt_ddi_vswing_sequence(dev, hdmi_level, port,
1878 INTEL_OUTPUT_HDMI);
1879 }
30cf6db8 1880 intel_hdmi->set_infoframes(encoder,
6e3c9717
ACO		 1881 crtc->config->has_hdmi_sink,
1882 &crtc->config->base.adjusted_mode);
c19b0669 1883 }
6441ab5f
PZ		 1884}
1885
00c09d70 1886static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
6441ab5f
PZ		 1887{
1888 struct drm_encoder *encoder = &intel_encoder->base;
efa80add
S		 1889 struct drm_device *dev = encoder->dev;
1890 struct drm_i915_private *dev_priv = dev->dev_private;
6441ab5f 1891 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 1892 int type = intel_encoder->type;
2886e93f 1893 uint32_t val;
a836bdf9 1894 bool wait = false;
2886e93f
PZ		 1895
1896 val = I915_READ(DDI_BUF_CTL(port));
1897 if (val & DDI_BUF_CTL_ENABLE) {
1898 val &= ~DDI_BUF_CTL_ENABLE;
1899 I915_WRITE(DDI_BUF_CTL(port), val);
a836bdf9 1900 wait = true;
2886e93f 1901 }
6441ab5f 1902
a836bdf9
PZ		 1903 val = I915_READ(DP_TP_CTL(port));
1904 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1905 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1906 I915_WRITE(DP_TP_CTL(port), val);
1907
1908 if (wait)
1909 intel_wait_ddi_buf_idle(dev_priv, port);
1910
76bb80ed 1911 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
82a4d9c0 1912 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
76bb80ed 1913 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
24f3e092 1914 intel_edp_panel_vdd_on(intel_dp);
4be73780 1915 intel_edp_panel_off(intel_dp);
82a4d9c0
PZ		 1916 }
1917
efa80add
S		 1918 if (IS_SKYLAKE(dev))
1919 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
1920 DPLL_CTRL2_DDI_CLK_OFF(port)));
1ab23380 1921 else if (INTEL_INFO(dev)->gen < 9)
efa80add 1922 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
6441ab5f
PZ		 1923}
1924
00c09d70 1925static void intel_enable_ddi(struct intel_encoder *intel_encoder)
72662e10 1926{
6547fef8 1927 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 1928 struct drm_crtc *crtc = encoder->crtc;
1929 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6547fef8 1930 struct drm_device *dev = encoder->dev;
72662e10 1931 struct drm_i915_private *dev_priv = dev->dev_private;
6547fef8
PZ		 1932 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1933 int type = intel_encoder->type;
72662e10 1934
6547fef8 1935 if (type == INTEL_OUTPUT_HDMI) {
876a8cdf
DL		 1936 struct intel_digital_port *intel_dig_port =
1937 enc_to_dig_port(encoder);
1938
6547fef8
PZ		 1939 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1940 * are ignored so nothing special needs to be done besides
1941 * enabling the port.
1942 */
876a8cdf 1943 I915_WRITE(DDI_BUF_CTL(port),
bcf53de4
SM		 1944 intel_dig_port->saved_port_bits |
1945 DDI_BUF_CTL_ENABLE);
d6c50ff8
PZ		 1946 } else if (type == INTEL_OUTPUT_EDP) {
1947 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1948
23f08d83 1949 if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
3ab9c637
ID		 1950 intel_dp_stop_link_train(intel_dp);
1951
4be73780 1952 intel_edp_backlight_on(intel_dp);
0bc12bcb 1953 intel_psr_enable(intel_dp);
c395578e 1954 intel_edp_drrs_enable(intel_dp);
6547fef8 1955 }
7b9f35a6 1956
6e3c9717 1957 if (intel_crtc->config->has_audio) {
d45a0bf5 1958 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
69bfe1a9 1959 intel_audio_codec_enable(intel_encoder);
7b9f35a6 1960 }
5ab432ef
DV		 1961}
1962
00c09d70 1963static void intel_disable_ddi(struct intel_encoder *intel_encoder)
5ab432ef 1964{
d6c50ff8 1965 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 1966 struct drm_crtc *crtc = encoder->crtc;
1967 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d6c50ff8 1968 int type = intel_encoder->type;
7b9f35a6
WX		 1969 struct drm_device *dev = encoder->dev;
1970 struct drm_i915_private *dev_priv = dev->dev_private;
d6c50ff8 1971
6e3c9717 1972 if (intel_crtc->config->has_audio) {
69bfe1a9 1973 intel_audio_codec_disable(intel_encoder);
d45a0bf5
PZ		 1974 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
1975 }
2831d842 1976
d6c50ff8
PZ		 1977 if (type == INTEL_OUTPUT_EDP) {
1978 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1979
c395578e 1980 intel_edp_drrs_disable(intel_dp);
0bc12bcb 1981 intel_psr_disable(intel_dp);
4be73780 1982 intel_edp_backlight_off(intel_dp);
d6c50ff8 1983 }
72662e10 1984}
79f689aa 1985
e0b01be4
DV		 1986static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
1987 struct intel_shared_dpll *pll)
1988{
3e369b76 1989 I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
e0b01be4
DV		 1990 POSTING_READ(WRPLL_CTL(pll->id));
1991 udelay(20);
1992}
1993
12030431
DV		 1994static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv,
1995 struct intel_shared_dpll *pll)
1996{
1997 uint32_t val;
1998
1999 val = I915_READ(WRPLL_CTL(pll->id));
12030431
DV		 2000 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
2001 POSTING_READ(WRPLL_CTL(pll->id));
2002}
2003
d452c5b6
DV		 2004static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2005 struct intel_shared_dpll *pll,
2006 struct intel_dpll_hw_state *hw_state)
2007{
2008 uint32_t val;
2009
f458ebbc 2010 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
d452c5b6
DV		 2011 return false;
2012
2013 val = I915_READ(WRPLL_CTL(pll->id));
2014 hw_state->wrpll = val;
2015
2016 return val & WRPLL_PLL_ENABLE;
2017}
2018
ca1381b5 2019static const char * const hsw_ddi_pll_names[] = {
9cd86933
DV		 2020 "WRPLL 1",
2021 "WRPLL 2",
2022};
2023
143b307c 2024static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
79f689aa 2025{
9cd86933
DV		 2026 int i;
2027
716c2e55 2028 dev_priv->num_shared_dpll = 2;
9cd86933 2029
716c2e55 2030 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9cd86933
DV		 2031 dev_priv->shared_dplls[i].id = i;
2032 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
12030431 2033 dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable;
e0b01be4 2034 dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable;
d452c5b6
DV		 2035 dev_priv->shared_dplls[i].get_hw_state =
2036 hsw_ddi_pll_get_hw_state;
9cd86933 2037 }
143b307c
DL		 2038}
2039
d1a2dc78
S		 2040static const char * const skl_ddi_pll_names[] = {
2041 "DPLL 1",
2042 "DPLL 2",
2043 "DPLL 3",
2044};
2045
2046struct skl_dpll_regs {
2047 u32 ctl, cfgcr1, cfgcr2;
2048};
2049
2050/* this array is indexed by the *shared* pll id */
2051static const struct skl_dpll_regs skl_dpll_regs[3] = {
2052 {
2053 /* DPLL 1 */
2054 .ctl = LCPLL2_CTL,
2055 .cfgcr1 = DPLL1_CFGCR1,
2056 .cfgcr2 = DPLL1_CFGCR2,
2057 },
2058 {
2059 /* DPLL 2 */
2060 .ctl = WRPLL_CTL1,
2061 .cfgcr1 = DPLL2_CFGCR1,
2062 .cfgcr2 = DPLL2_CFGCR2,
2063 },
2064 {
2065 /* DPLL 3 */
2066 .ctl = WRPLL_CTL2,
2067 .cfgcr1 = DPLL3_CFGCR1,
2068 .cfgcr2 = DPLL3_CFGCR2,
2069 },
2070};
2071
2072static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
2073 struct intel_shared_dpll *pll)
2074{
2075 uint32_t val;
2076 unsigned int dpll;
2077 const struct skl_dpll_regs *regs = skl_dpll_regs;
2078
2079 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2080 dpll = pll->id + 1;
2081
2082 val = I915_READ(DPLL_CTRL1);
2083
2084 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) |
2085 DPLL_CRTL1_LINK_RATE_MASK(dpll));
2086 val |= pll->config.hw_state.ctrl1 << (dpll * 6);
2087
2088 I915_WRITE(DPLL_CTRL1, val);
2089 POSTING_READ(DPLL_CTRL1);
2090
2091 I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);
2092 I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);
2093 POSTING_READ(regs[pll->id].cfgcr1);
2094 POSTING_READ(regs[pll->id].cfgcr2);
2095
2096 /* the enable bit is always bit 31 */
2097 I915_WRITE(regs[pll->id].ctl,
2098 I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);
2099
2100 if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5))
2101 DRM_ERROR("DPLL %d not locked\n", dpll);
2102}
2103
2104static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
2105 struct intel_shared_dpll *pll)
2106{
2107 const struct skl_dpll_regs *regs = skl_dpll_regs;
2108
2109 /* the enable bit is always bit 31 */
2110 I915_WRITE(regs[pll->id].ctl,
2111 I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
2112 POSTING_READ(regs[pll->id].ctl);
2113}
2114
2115static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2116 struct intel_shared_dpll *pll,
2117 struct intel_dpll_hw_state *hw_state)
2118{
2119 uint32_t val;
2120 unsigned int dpll;
2121 const struct skl_dpll_regs *regs = skl_dpll_regs;
2122
2123 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2124 return false;
2125
2126 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2127 dpll = pll->id + 1;
2128
2129 val = I915_READ(regs[pll->id].ctl);
2130 if (!(val & LCPLL_PLL_ENABLE))
2131 return false;
2132
2133 val = I915_READ(DPLL_CTRL1);
2134 hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f;
2135
2136 /* avoid reading back stale values if HDMI mode is not enabled */
2137 if (val & DPLL_CTRL1_HDMI_MODE(dpll)) {
2138 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
2139 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
2140 }
2141
2142 return true;
2143}
2144
2145static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
2146{
2147 int i;
2148
2149 dev_priv->num_shared_dpll = 3;
2150
2151 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2152 dev_priv->shared_dplls[i].id = i;
2153 dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i];
2154 dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable;
2155 dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable;
2156 dev_priv->shared_dplls[i].get_hw_state =
2157 skl_ddi_pll_get_hw_state;
2158 }
2159}
2160
5c6706e5
VK		 2161static void broxton_phy_init(struct drm_i915_private *dev_priv,
2162 enum dpio_phy phy)
2163{
2164 enum port port;
2165 uint32_t val;
2166
2167 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
2168 val |= GT_DISPLAY_POWER_ON(phy);
2169 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
2170
2171 /* Considering 10ms timeout until BSpec is updated */
2172 if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
2173 DRM_ERROR("timeout during PHY%d power on\n", phy);
2174
2175 for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A);
2176 port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
2177 int lane;
2178
2179 for (lane = 0; lane < 4; lane++) {
2180 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
2181 /*
2182 * Note that on CHV this flag is called UPAR, but has
2183 * the same function.
2184 */
2185 val &= ~LATENCY_OPTIM;
2186 if (lane != 1)
2187 val |= LATENCY_OPTIM;
2188
2189 I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
2190 }
2191 }
2192
2193 /* Program PLL Rcomp code offset */
2194 val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
2195 val &= ~IREF0RC_OFFSET_MASK;
2196 val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
2197 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
2198
2199 val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
2200 val &= ~IREF1RC_OFFSET_MASK;
2201 val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
2202 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
2203
2204 /* Program power gating */
2205 val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
2206 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
2207 SUS_CLK_CONFIG;
2208 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
2209
2210 if (phy == DPIO_PHY0) {
2211 val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
2212 val |= DW6_OLDO_DYN_PWR_DOWN_EN;
2213 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
2214 }
2215
2216 val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
2217 val &= ~OCL2_LDOFUSE_PWR_DIS;
2218 /*
2219 * On PHY1 disable power on the second channel, since no port is
2220 * connected there. On PHY0 both channels have a port, so leave it
2221 * enabled.
2222 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
2223 * power down the second channel on PHY0 as well.
2224 */
2225 if (phy == DPIO_PHY1)
2226 val |= OCL2_LDOFUSE_PWR_DIS;
2227 I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
2228
2229 if (phy == DPIO_PHY0) {
2230 uint32_t grc_code;
2231 /*
2232 * PHY0 isn't connected to an RCOMP resistor so copy over
2233 * the corresponding calibrated value from PHY1, and disable
2234 * the automatic calibration on PHY0.
2235 */
2236 if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE,
2237 10))
2238 DRM_ERROR("timeout waiting for PHY1 GRC\n");
2239
2240 val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1));
2241 val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
2242 grc_code = val << GRC_CODE_FAST_SHIFT |
2243 val << GRC_CODE_SLOW_SHIFT |
2244 val;
2245 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
2246
2247 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
2248 val |= GRC_DIS | GRC_RDY_OVRD;
2249 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
2250 }
2251
2252 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2253 val |= COMMON_RESET_DIS;
2254 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2255}
2256
2257void broxton_ddi_phy_init(struct drm_device *dev)
2258{
2259 /* Enable PHY1 first since it provides Rcomp for PHY0 */
2260 broxton_phy_init(dev->dev_private, DPIO_PHY1);
2261 broxton_phy_init(dev->dev_private, DPIO_PHY0);
2262}
2263
2264static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
2265 enum dpio_phy phy)
2266{
2267 uint32_t val;
2268
2269 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2270 val &= ~COMMON_RESET_DIS;
2271 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2272}
2273
2274void broxton_ddi_phy_uninit(struct drm_device *dev)
2275{
2276 struct drm_i915_private *dev_priv = dev->dev_private;
2277
2278 broxton_phy_uninit(dev_priv, DPIO_PHY1);
2279 broxton_phy_uninit(dev_priv, DPIO_PHY0);
2280
2281 /* FIXME: do this in broxton_phy_uninit per phy */
2282 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0);
2283}
2284
dfb82408
S		 2285static const char * const bxt_ddi_pll_names[] = {
2286 "PORT PLL A",
2287 "PORT PLL B",
2288 "PORT PLL C",
2289};
2290
2291static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
2292 struct intel_shared_dpll *pll)
2293{
2294 uint32_t temp;
2295 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2296
2297 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2298 temp &= ~PORT_PLL_REF_SEL;
2299 /* Non-SSC reference */
2300 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2301
2302 /* Disable 10 bit clock */
2303 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2304 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2305 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2306
2307 /* Write P1 & P2 */
2308 temp = I915_READ(BXT_PORT_PLL_EBB_0(port));
2309 temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK);
2310 temp |= pll->config.hw_state.ebb0;
2311 I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp);
2312
2313 /* Write M2 integer */
2314 temp = I915_READ(BXT_PORT_PLL(port, 0));
2315 temp &= ~PORT_PLL_M2_MASK;
2316 temp |= pll->config.hw_state.pll0;
2317 I915_WRITE(BXT_PORT_PLL(port, 0), temp);
2318
2319 /* Write N */
2320 temp = I915_READ(BXT_PORT_PLL(port, 1));
2321 temp &= ~PORT_PLL_N_MASK;
2322 temp |= pll->config.hw_state.pll1;
2323 I915_WRITE(BXT_PORT_PLL(port, 1), temp);
2324
2325 /* Write M2 fraction */
2326 temp = I915_READ(BXT_PORT_PLL(port, 2));
2327 temp &= ~PORT_PLL_M2_FRAC_MASK;
2328 temp |= pll->config.hw_state.pll2;
2329 I915_WRITE(BXT_PORT_PLL(port, 2), temp);
2330
2331 /* Write M2 fraction enable */
2332 temp = I915_READ(BXT_PORT_PLL(port, 3));
2333 temp &= ~PORT_PLL_M2_FRAC_ENABLE;
2334 temp |= pll->config.hw_state.pll3;
2335 I915_WRITE(BXT_PORT_PLL(port, 3), temp);
2336
2337 /* Write coeff */
2338 temp = I915_READ(BXT_PORT_PLL(port, 6));
2339 temp &= ~PORT_PLL_PROP_COEFF_MASK;
2340 temp &= ~PORT_PLL_INT_COEFF_MASK;
2341 temp &= ~PORT_PLL_GAIN_CTL_MASK;
2342 temp |= pll->config.hw_state.pll6;
2343 I915_WRITE(BXT_PORT_PLL(port, 6), temp);
2344
2345 /* Write calibration val */
2346 temp = I915_READ(BXT_PORT_PLL(port, 8));
2347 temp &= ~PORT_PLL_TARGET_CNT_MASK;
2348 temp |= pll->config.hw_state.pll8;
2349 I915_WRITE(BXT_PORT_PLL(port, 8), temp);
2350
2351 /*
2352 * FIXME: program PORT_PLL_9/i_lockthresh according to the latest
2353 * specification update.
2354 */
2355
2356 /* Recalibrate with new settings */
2357 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2358 temp |= PORT_PLL_RECALIBRATE;
2359 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2360 /* Enable 10 bit clock */
2361 temp |= PORT_PLL_10BIT_CLK_ENABLE;
2362 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2363
2364 /* Enable PLL */
2365 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2366 temp |= PORT_PLL_ENABLE;
2367 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2368 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2369
2370 if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
2371 PORT_PLL_LOCK), 200))
2372 DRM_ERROR("PLL %d not locked\n", port);
2373
2374 /*
2375 * While we write to the group register to program all lanes at once we
2376 * can read only lane registers and we pick lanes 0/1 for that.
2377 */
2378 temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2379 temp &= ~LANE_STAGGER_MASK;
2380 temp &= ~LANESTAGGER_STRAP_OVRD;
2381 temp |= pll->config.hw_state.pcsdw12;
2382 I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp);
2383}
2384
2385static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
2386 struct intel_shared_dpll *pll)
2387{
2388 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2389 uint32_t temp;
2390
2391 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2392 temp &= ~PORT_PLL_ENABLE;
2393 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2394 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2395}
2396
2397static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2398 struct intel_shared_dpll *pll,
2399 struct intel_dpll_hw_state *hw_state)
2400{
2401 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2402 uint32_t val;
2403
2404 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2405 return false;
2406
2407 val = I915_READ(BXT_PORT_PLL_ENABLE(port));
2408 if (!(val & PORT_PLL_ENABLE))
2409 return false;
2410
2411 hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port));
2412 hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0));
2413 hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1));
2414 hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2));
2415 hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
2416 hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
2417 hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
2418 /*
2419 * While we write to the group register to program all lanes at once we
2420 * can read only lane registers. We configure all lanes the same way, so
2421 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
2422 */
2423 hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2424 if (I915_READ(BXT_PORT_PCS_DW12_LN23(port) != hw_state->pcsdw12))
2425 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
2426 hw_state->pcsdw12,
2427 I915_READ(BXT_PORT_PCS_DW12_LN23(port)));
2428
2429 return true;
2430}
2431
2432static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv)
2433{
2434 int i;
2435
2436 dev_priv->num_shared_dpll = 3;
2437
2438 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2439 dev_priv->shared_dplls[i].id = i;
2440 dev_priv->shared_dplls[i].name = bxt_ddi_pll_names[i];
2441 dev_priv->shared_dplls[i].disable = bxt_ddi_pll_disable;
2442 dev_priv->shared_dplls[i].enable = bxt_ddi_pll_enable;
2443 dev_priv->shared_dplls[i].get_hw_state =
2444 bxt_ddi_pll_get_hw_state;
2445 }
2446}
2447
143b307c
DL		 2448void intel_ddi_pll_init(struct drm_device *dev)
2449{
2450 struct drm_i915_private *dev_priv = dev->dev_private;
2451 uint32_t val = I915_READ(LCPLL_CTL);
2452
d1a2dc78
S		 2453 if (IS_SKYLAKE(dev))
2454 skl_shared_dplls_init(dev_priv);
dfb82408
S		 2455 else if (IS_BROXTON(dev))
2456 bxt_shared_dplls_init(dev_priv);
d1a2dc78
S		 2457 else
2458 hsw_shared_dplls_init(dev_priv);
79f689aa 2459
b2b877ff 2460 DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
1652d19e 2461 dev_priv->display.get_display_clock_speed(dev));
79f689aa 2462
121643c2
S		 2463 if (IS_SKYLAKE(dev)) {
2464 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
2465 DRM_ERROR("LCPLL1 is disabled\n");
f8437dd1
VK		 2466 } else if (IS_BROXTON(dev)) {
2467 broxton_init_cdclk(dev);
5c6706e5 2468 broxton_ddi_phy_init(dev);
121643c2
S		 2469 } else {
2470 /*
2471 * The LCPLL register should be turned on by the BIOS. For now
2472 * let's just check its state and print errors in case
2473 * something is wrong. Don't even try to turn it on.
2474 */
2475
2476 if (val & LCPLL_CD_SOURCE_FCLK)
2477 DRM_ERROR("CDCLK source is not LCPLL\n");
79f689aa 2478
121643c2
S		 2479 if (val & LCPLL_PLL_DISABLE)
2480 DRM_ERROR("LCPLL is disabled\n");
2481 }
79f689aa 2482}
c19b0669
PZ		 2483
2484void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
2485{
174edf1f
PZ		 2486 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2487 struct intel_dp *intel_dp = &intel_dig_port->dp;
c19b0669 2488 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
174edf1f 2489 enum port port = intel_dig_port->port;
c19b0669 2490 uint32_t val;
f3e227df 2491 bool wait = false;
c19b0669
PZ		 2492
2493 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2494 val = I915_READ(DDI_BUF_CTL(port));
2495 if (val & DDI_BUF_CTL_ENABLE) {
2496 val &= ~DDI_BUF_CTL_ENABLE;
2497 I915_WRITE(DDI_BUF_CTL(port), val);
2498 wait = true;
2499 }
2500
2501 val = I915_READ(DP_TP_CTL(port));
2502 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2503 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2504 I915_WRITE(DP_TP_CTL(port), val);
2505 POSTING_READ(DP_TP_CTL(port));
2506
2507 if (wait)
2508 intel_wait_ddi_buf_idle(dev_priv, port);
2509 }
2510
0e32b39c 2511 val = DP_TP_CTL_ENABLE |
c19b0669 2512 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
0e32b39c
DA		 2513 if (intel_dp->is_mst)
2514 val |= DP_TP_CTL_MODE_MST;
2515 else {
2516 val |= DP_TP_CTL_MODE_SST;
2517 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2518 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
2519 }
c19b0669
PZ		 2520 I915_WRITE(DP_TP_CTL(port), val);
2521 POSTING_READ(DP_TP_CTL(port));
2522
2523 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
2524 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
2525 POSTING_READ(DDI_BUF_CTL(port));
2526
2527 udelay(600);
2528}
00c09d70 2529
1ad960f2
PZ		 2530void intel_ddi_fdi_disable(struct drm_crtc *crtc)
2531{
2532 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
2533 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
2534 uint32_t val;
2535
2536 intel_ddi_post_disable(intel_encoder);
2537
2538 val = I915_READ(_FDI_RXA_CTL);
2539 val &= ~FDI_RX_ENABLE;
2540 I915_WRITE(_FDI_RXA_CTL, val);
2541
2542 val = I915_READ(_FDI_RXA_MISC);
2543 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
2544 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2545 I915_WRITE(_FDI_RXA_MISC, val);
2546
2547 val = I915_READ(_FDI_RXA_CTL);
2548 val &= ~FDI_PCDCLK;
2549 I915_WRITE(_FDI_RXA_CTL, val);
2550
2551 val = I915_READ(_FDI_RXA_CTL);
2552 val &= ~FDI_RX_PLL_ENABLE;
2553 I915_WRITE(_FDI_RXA_CTL, val);
2554}
2555
00c09d70
PZ		 2556static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
2557{
0e32b39c
DA		 2558 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&intel_encoder->base);
2559 int type = intel_dig_port->base.type;
2560
2561 if (type != INTEL_OUTPUT_DISPLAYPORT &&
2562 type != INTEL_OUTPUT_EDP &&
2563 type != INTEL_OUTPUT_UNKNOWN) {
2564 return;
2565 }
00c09d70 2566
0e32b39c 2567 intel_dp_hot_plug(intel_encoder);
00c09d70
PZ		 2568}
2569
6801c18c 2570void intel_ddi_get_config(struct intel_encoder *encoder,
5cec258b 2571 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 2572{
2573 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
2574 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
0cb09a97 2575 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
bbd440fb 2576 struct intel_hdmi *intel_hdmi;
045ac3b5
JB		 2577 u32 temp, flags = 0;
2578
2579 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2580 if (temp & TRANS_DDI_PHSYNC)
2581 flags |= DRM_MODE_FLAG_PHSYNC;
2582 else
2583 flags |= DRM_MODE_FLAG_NHSYNC;
2584 if (temp & TRANS_DDI_PVSYNC)
2585 flags |= DRM_MODE_FLAG_PVSYNC;
2586 else
2587 flags |= DRM_MODE_FLAG_NVSYNC;
2588
2d112de7 2589 pipe_config->base.adjusted_mode.flags |= flags;
42571aef
VS		 2590
2591 switch (temp & TRANS_DDI_BPC_MASK) {
2592 case TRANS_DDI_BPC_6:
2593 pipe_config->pipe_bpp = 18;
2594 break;
2595 case TRANS_DDI_BPC_8:
2596 pipe_config->pipe_bpp = 24;
2597 break;
2598 case TRANS_DDI_BPC_10:
2599 pipe_config->pipe_bpp = 30;
2600 break;
2601 case TRANS_DDI_BPC_12:
2602 pipe_config->pipe_bpp = 36;
2603 break;
2604 default:
2605 break;
2606 }
eb14cb74
VS		 2607
2608 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
2609 case TRANS_DDI_MODE_SELECT_HDMI:
6897b4b5 2610 pipe_config->has_hdmi_sink = true;
bbd440fb
DV		 2611 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2612
2613 if (intel_hdmi->infoframe_enabled(&encoder->base))
2614 pipe_config->has_infoframe = true;
cbc572a9 2615 break;
eb14cb74
VS		 2616 case TRANS_DDI_MODE_SELECT_DVI:
2617 case TRANS_DDI_MODE_SELECT_FDI:
2618 break;
2619 case TRANS_DDI_MODE_SELECT_DP_SST:
2620 case TRANS_DDI_MODE_SELECT_DP_MST:
2621 pipe_config->has_dp_encoder = true;
2622 intel_dp_get_m_n(intel_crtc, pipe_config);
2623 break;
2624 default:
2625 break;
2626 }
10214420 2627
f458ebbc 2628 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
a60551b1 2629 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
82910ac6 2630 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
a60551b1
PZ		 2631 pipe_config->has_audio = true;
2632 }
9ed109a7 2633
10214420
DV		 2634 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
2635 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2636 /*
2637 * This is a big fat ugly hack.
2638 *
2639 * Some machines in UEFI boot mode provide us a VBT that has 18
2640 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2641 * unknown we fail to light up. Yet the same BIOS boots up with
2642 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2643 * max, not what it tells us to use.
2644 *
2645 * Note: This will still be broken if the eDP panel is not lit
2646 * up by the BIOS, and thus we can't get the mode at module
2647 * load.
2648 */
2649 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2650 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2651 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2652 }
11578553 2653
22606a18 2654 intel_ddi_clock_get(encoder, pipe_config);
045ac3b5
JB		 2655}
2656
00c09d70
PZ		 2657static void intel_ddi_destroy(struct drm_encoder *encoder)
2658{
2659 /* HDMI has nothing special to destroy, so we can go with this. */
2660 intel_dp_encoder_destroy(encoder);
2661}
2662
5bfe2ac0 2663static bool intel_ddi_compute_config(struct intel_encoder *encoder,
5cec258b 2664 struct intel_crtc_state *pipe_config)
00c09d70 2665{
5bfe2ac0 2666 int type = encoder->type;
eccb140b 2667 int port = intel_ddi_get_encoder_port(encoder);
00c09d70 2668
5bfe2ac0 2669 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
00c09d70 2670
eccb140b
DV		 2671 if (port == PORT_A)
2672 pipe_config->cpu_transcoder = TRANSCODER_EDP;
2673
00c09d70 2674 if (type == INTEL_OUTPUT_HDMI)
5bfe2ac0 2675 return intel_hdmi_compute_config(encoder, pipe_config);
00c09d70 2676 else
5bfe2ac0 2677 return intel_dp_compute_config(encoder, pipe_config);
00c09d70
PZ		 2678}
2679
2680static const struct drm_encoder_funcs intel_ddi_funcs = {
2681 .destroy = intel_ddi_destroy,
2682};
2683
4a28ae58
PZ		 2684static struct intel_connector *
2685intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
2686{
2687 struct intel_connector *connector;
2688 enum port port = intel_dig_port->port;
2689
9bdbd0b9 2690 connector = intel_connector_alloc();
4a28ae58
PZ		 2691 if (!connector)
2692 return NULL;
2693
2694 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
2695 if (!intel_dp_init_connector(intel_dig_port, connector)) {
2696 kfree(connector);
2697 return NULL;
2698 }
2699
2700 return connector;
2701}
2702
2703static struct intel_connector *
2704intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
2705{
2706 struct intel_connector *connector;
2707 enum port port = intel_dig_port->port;
2708
9bdbd0b9 2709 connector = intel_connector_alloc();
4a28ae58
PZ		 2710 if (!connector)
2711 return NULL;
2712
2713 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
2714 intel_hdmi_init_connector(intel_dig_port, connector);
2715
2716 return connector;
2717}
2718
00c09d70
PZ		 2719void intel_ddi_init(struct drm_device *dev, enum port port)
2720{
876a8cdf 2721 struct drm_i915_private *dev_priv = dev->dev_private;
00c09d70
PZ		 2722 struct intel_digital_port *intel_dig_port;
2723 struct intel_encoder *intel_encoder;
2724 struct drm_encoder *encoder;
311a2094
PZ		 2725 bool init_hdmi, init_dp;
2726
2727 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
2728 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
2729 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
2730 if (!init_dp && !init_hdmi) {
f68d697e 2731 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n",
311a2094
PZ		 2732 port_name(port));
2733 init_hdmi = true;
2734 init_dp = true;
2735 }
00c09d70 2736
b14c5679 2737 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
00c09d70
PZ		 2738 if (!intel_dig_port)
2739 return;
2740
00c09d70
PZ		 2741 intel_encoder = &intel_dig_port->base;
2742 encoder = &intel_encoder->base;
2743
2744 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
2745 DRM_MODE_ENCODER_TMDS);
00c09d70 2746
5bfe2ac0 2747 intel_encoder->compute_config = intel_ddi_compute_config;
00c09d70
PZ		 2748 intel_encoder->enable = intel_enable_ddi;
2749 intel_encoder->pre_enable = intel_ddi_pre_enable;
2750 intel_encoder->disable = intel_disable_ddi;
2751 intel_encoder->post_disable = intel_ddi_post_disable;
2752 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
045ac3b5 2753 intel_encoder->get_config = intel_ddi_get_config;
00c09d70
PZ		 2754
2755 intel_dig_port->port = port;
bcf53de4
SM		 2756 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
2757 (DDI_BUF_PORT_REVERSAL |
2758 DDI_A_4_LANES);
00c09d70
PZ		 2759
2760 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
f68d697e 2761 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
bc079e8b 2762 intel_encoder->cloneable = 0;
00c09d70
PZ		 2763 intel_encoder->hot_plug = intel_ddi_hot_plug;
2764
f68d697e
CW		 2765 if (init_dp) {
2766 if (!intel_ddi_init_dp_connector(intel_dig_port))
2767 goto err;
13cf5504 2768
f68d697e
CW		 2769 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
2770 dev_priv->hpd_irq_port[port] = intel_dig_port;
2771 }
21a8e6a4 2772
311a2094
PZ		 2773 /* In theory we don't need the encoder->type check, but leave it just in
2774 * case we have some really bad VBTs... */
f68d697e
CW		 2775 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
2776 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
2777 goto err;
21a8e6a4 2778 }
f68d697e
CW		 2779
2780 return;
2781
2782err:
2783 drm_encoder_cleanup(encoder);
2784 kfree(intel_dig_port);
00c09d70 2785}
Linux kernel - Deliverables
This page took 0.341787 seconds and 5 git commands to generate.