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drm/i915: abstract get config for cpu transcoder
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ddi.c
CommitLineData
45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include "i915_drv.h"
29#include "intel_drv.h"
30
10122051
JN		 31struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
f8896f5d 34 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
10122051
JN		 35};
36
45244b87
ED		 37/* HDMI/DVI modes ignore everything but the last 2 items. So we share
38 * them for both DP and FDI transports, allowing those ports to
39 * automatically adapt to HDMI connections as well
40 */
10122051 41static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
f8896f5d
DW		 42 { 0x00FFFFFF, 0x0006000E, 0x0 },
43 { 0x00D75FFF, 0x0005000A, 0x0 },
44 { 0x00C30FFF, 0x00040006, 0x0 },
45 { 0x80AAAFFF, 0x000B0000, 0x0 },
46 { 0x00FFFFFF, 0x0005000A, 0x0 },
47 { 0x00D75FFF, 0x000C0004, 0x0 },
48 { 0x80C30FFF, 0x000B0000, 0x0 },
49 { 0x00FFFFFF, 0x00040006, 0x0 },
50 { 0x80D75FFF, 0x000B0000, 0x0 },
45244b87
ED		 51};
52
10122051 53static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
f8896f5d
DW		 54 { 0x00FFFFFF, 0x0007000E, 0x0 },
55 { 0x00D75FFF, 0x000F000A, 0x0 },
56 { 0x00C30FFF, 0x00060006, 0x0 },
57 { 0x00AAAFFF, 0x001E0000, 0x0 },
58 { 0x00FFFFFF, 0x000F000A, 0x0 },
59 { 0x00D75FFF, 0x00160004, 0x0 },
60 { 0x00C30FFF, 0x001E0000, 0x0 },
61 { 0x00FFFFFF, 0x00060006, 0x0 },
62 { 0x00D75FFF, 0x001E0000, 0x0 },
6acab15a
PZ		 63};
64
10122051
JN		 65static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
66 /* Idx NT mV d T mV d db */
f8896f5d
DW		 67 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
68 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
69 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
70 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
71 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
72 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
73 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
74 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
75 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
76 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
77 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
78 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
45244b87
ED		 79};
80
10122051 81static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
f8896f5d
DW		 82 { 0x00FFFFFF, 0x00000012, 0x0 },
83 { 0x00EBAFFF, 0x00020011, 0x0 },
84 { 0x00C71FFF, 0x0006000F, 0x0 },
85 { 0x00AAAFFF, 0x000E000A, 0x0 },
86 { 0x00FFFFFF, 0x00020011, 0x0 },
87 { 0x00DB6FFF, 0x0005000F, 0x0 },
88 { 0x00BEEFFF, 0x000A000C, 0x0 },
89 { 0x00FFFFFF, 0x0005000F, 0x0 },
90 { 0x00DB6FFF, 0x000A000C, 0x0 },
300644c7
PZ		 91};
92
10122051 93static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
f8896f5d
DW		 94 { 0x00FFFFFF, 0x0007000E, 0x0 },
95 { 0x00D75FFF, 0x000E000A, 0x0 },
96 { 0x00BEFFFF, 0x00140006, 0x0 },
97 { 0x80B2CFFF, 0x001B0002, 0x0 },
98 { 0x00FFFFFF, 0x000E000A, 0x0 },
99 { 0x00DB6FFF, 0x00160005, 0x0 },
100 { 0x80C71FFF, 0x001A0002, 0x0 },
101 { 0x00F7DFFF, 0x00180004, 0x0 },
102 { 0x80D75FFF, 0x001B0002, 0x0 },
e58623cb
AR		 103};
104
10122051 105static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
f8896f5d
DW		 106 { 0x00FFFFFF, 0x0001000E, 0x0 },
107 { 0x00D75FFF, 0x0004000A, 0x0 },
108 { 0x00C30FFF, 0x00070006, 0x0 },
109 { 0x00AAAFFF, 0x000C0000, 0x0 },
110 { 0x00FFFFFF, 0x0004000A, 0x0 },
111 { 0x00D75FFF, 0x00090004, 0x0 },
112 { 0x00C30FFF, 0x000C0000, 0x0 },
113 { 0x00FFFFFF, 0x00070006, 0x0 },
114 { 0x00D75FFF, 0x000C0000, 0x0 },
e58623cb
AR		 115};
116
10122051
JN		 117static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
118 /* Idx NT mV d T mV df db */
f8896f5d
DW		 119 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
120 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
121 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
122 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
123 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
124 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
125 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
126 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
127 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
128 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
a26aa8ba
DL		 129};
130
5f8b2531 131/* Skylake H and S */
7f88e3af 132static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
f8896f5d
DW		 133 { 0x00002016, 0x000000A0, 0x0 },
134 { 0x00005012, 0x0000009B, 0x0 },
135 { 0x00007011, 0x00000088, 0x0 },
d7097cff 136 { 0x80009010, 0x000000C0, 0x1 },
f8896f5d
DW		 137 { 0x00002016, 0x0000009B, 0x0 },
138 { 0x00005012, 0x00000088, 0x0 },
d7097cff 139 { 0x80007011, 0x000000C0, 0x1 },
f8896f5d 140 { 0x00002016, 0x000000DF, 0x0 },
d7097cff 141 { 0x80005012, 0x000000C0, 0x1 },
7f88e3af
DL		 142};
143
f8896f5d
DW		 144/* Skylake U */
145static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
5f8b2531 146 { 0x0000201B, 0x000000A2, 0x0 },
f8896f5d 147 { 0x00005012, 0x00000088, 0x0 },
63ebce1f 148 { 0x80007011, 0x000000CD, 0x0 },
d7097cff 149 { 0x80009010, 0x000000C0, 0x1 },
5f8b2531 150 { 0x0000201B, 0x0000009D, 0x0 },
d7097cff
RV		 151 { 0x80005012, 0x000000C0, 0x1 },
152 { 0x80007011, 0x000000C0, 0x1 },
f8896f5d 153 { 0x00002016, 0x00000088, 0x0 },
d7097cff 154 { 0x80005012, 0x000000C0, 0x1 },
f8896f5d
DW		 155};
156
5f8b2531
RV		 157/* Skylake Y */
158static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
f8896f5d
DW		 159 { 0x00000018, 0x000000A2, 0x0 },
160 { 0x00005012, 0x00000088, 0x0 },
63ebce1f 161 { 0x80007011, 0x000000CD, 0x0 },
d7097cff 162 { 0x80009010, 0x000000C0, 0x3 },
f8896f5d 163 { 0x00000018, 0x0000009D, 0x0 },
d7097cff
RV		 164 { 0x80005012, 0x000000C0, 0x3 },
165 { 0x80007011, 0x000000C0, 0x3 },
f8896f5d 166 { 0x00000018, 0x00000088, 0x0 },
d7097cff 167 { 0x80005012, 0x000000C0, 0x3 },
f8896f5d
DW		 168};
169
170/*
5f8b2531 171 * Skylake H and S
f8896f5d
DW		 172 * eDP 1.4 low vswing translation parameters
173 */
7ad14a29 174static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
f8896f5d
DW		 175 { 0x00000018, 0x000000A8, 0x0 },
176 { 0x00004013, 0x000000A9, 0x0 },
177 { 0x00007011, 0x000000A2, 0x0 },
178 { 0x00009010, 0x0000009C, 0x0 },
179 { 0x00000018, 0x000000A9, 0x0 },
180 { 0x00006013, 0x000000A2, 0x0 },
181 { 0x00007011, 0x000000A6, 0x0 },
182 { 0x00000018, 0x000000AB, 0x0 },
183 { 0x00007013, 0x0000009F, 0x0 },
184 { 0x00000018, 0x000000DF, 0x0 },
185};
186
187/*
188 * Skylake U
189 * eDP 1.4 low vswing translation parameters
190 */
191static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
192 { 0x00000018, 0x000000A8, 0x0 },
193 { 0x00004013, 0x000000A9, 0x0 },
194 { 0x00007011, 0x000000A2, 0x0 },
195 { 0x00009010, 0x0000009C, 0x0 },
196 { 0x00000018, 0x000000A9, 0x0 },
197 { 0x00006013, 0x000000A2, 0x0 },
198 { 0x00007011, 0x000000A6, 0x0 },
199 { 0x00002016, 0x000000AB, 0x0 },
200 { 0x00005013, 0x0000009F, 0x0 },
201 { 0x00000018, 0x000000DF, 0x0 },
7ad14a29
SJ		 202};
203
f8896f5d 204/*
5f8b2531 205 * Skylake Y
f8896f5d
DW		 206 * eDP 1.4 low vswing translation parameters
207 */
5f8b2531 208static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
f8896f5d
DW		 209 { 0x00000018, 0x000000A8, 0x0 },
210 { 0x00004013, 0x000000AB, 0x0 },
211 { 0x00007011, 0x000000A4, 0x0 },
212 { 0x00009010, 0x000000DF, 0x0 },
213 { 0x00000018, 0x000000AA, 0x0 },
214 { 0x00006013, 0x000000A4, 0x0 },
215 { 0x00007011, 0x0000009D, 0x0 },
216 { 0x00000018, 0x000000A0, 0x0 },
217 { 0x00006012, 0x000000DF, 0x0 },
218 { 0x00000018, 0x0000008A, 0x0 },
219};
7ad14a29 220
5f8b2531 221/* Skylake U, H and S */
7f88e3af 222static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
f8896f5d
DW		 223 { 0x00000018, 0x000000AC, 0x0 },
224 { 0x00005012, 0x0000009D, 0x0 },
225 { 0x00007011, 0x00000088, 0x0 },
226 { 0x00000018, 0x000000A1, 0x0 },
227 { 0x00000018, 0x00000098, 0x0 },
228 { 0x00004013, 0x00000088, 0x0 },
2e78416e 229 { 0x80006012, 0x000000CD, 0x1 },
f8896f5d 230 { 0x00000018, 0x000000DF, 0x0 },
2e78416e
RV		 231 { 0x80003015, 0x000000CD, 0x1 }, /* Default */
232 { 0x80003015, 0x000000C0, 0x1 },
233 { 0x80000018, 0x000000C0, 0x1 },
f8896f5d
DW		 234};
235
5f8b2531
RV		 236/* Skylake Y */
237static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
f8896f5d
DW		 238 { 0x00000018, 0x000000A1, 0x0 },
239 { 0x00005012, 0x000000DF, 0x0 },
2e78416e 240 { 0x80007011, 0x000000CB, 0x3 },
f8896f5d
DW		 241 { 0x00000018, 0x000000A4, 0x0 },
242 { 0x00000018, 0x0000009D, 0x0 },
243 { 0x00004013, 0x00000080, 0x0 },
2e78416e 244 { 0x80006013, 0x000000C0, 0x3 },
f8896f5d 245 { 0x00000018, 0x0000008A, 0x0 },
2e78416e
RV		 246 { 0x80003015, 0x000000C0, 0x3 }, /* Default */
247 { 0x80003015, 0x000000C0, 0x3 },
248 { 0x80000018, 0x000000C0, 0x3 },
7f88e3af
DL		 249};
250
96fb9f9b
VK		 251struct bxt_ddi_buf_trans {
252 u32 margin; /* swing value */
253 u32 scale; /* scale value */
254 u32 enable; /* scale enable */
255 u32 deemphasis;
256 bool default_index; /* true if the entry represents default value */
257};
258
96fb9f9b
VK		 259static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
260 /* Idx NT mV diff db */
fe4c63c8
ID		 261 { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */
262 { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
263 { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */
264 { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
265 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
266 { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
267 { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */
268 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
269 { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
f8896f5d 270 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
96fb9f9b
VK		 271};
272
d9d7000d
SJ		 273static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
274 /* Idx NT mV diff db */
275 { 26, 0, 0, 128, false }, /* 0: 200 0 */
276 { 38, 0, 0, 112, false }, /* 1: 200 1.5 */
277 { 48, 0, 0, 96, false }, /* 2: 200 4 */
278 { 54, 0, 0, 69, false }, /* 3: 200 6 */
279 { 32, 0, 0, 128, false }, /* 4: 250 0 */
280 { 48, 0, 0, 104, false }, /* 5: 250 1.5 */
281 { 54, 0, 0, 85, false }, /* 6: 250 4 */
282 { 43, 0, 0, 128, false }, /* 7: 300 0 */
283 { 54, 0, 0, 101, false }, /* 8: 300 1.5 */
284 { 48, 0, 0, 128, false }, /* 9: 300 0 */
285};
286
96fb9f9b
VK		 287/* BSpec has 2 recommended values - entries 0 and 8.
288 * Using the entry with higher vswing.
289 */
290static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
291 /* Idx NT mV diff db */
fe4c63c8
ID		 292 { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */
293 { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
294 { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */
295 { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
296 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
297 { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
298 { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */
299 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
300 { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
96fb9f9b
VK		 301 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
302};
303
78ab0bae
VS		 304static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
305 u32 level, enum port port, int type);
f8896f5d 306
a1e6ad66
ID		 307static void ddi_get_encoder_port(struct intel_encoder *intel_encoder,
308 struct intel_digital_port **dig_port,
309 enum port *port)
fc914639 310{
0bdee30e 311 struct drm_encoder *encoder = &intel_encoder->base;
fc914639 312
8cd21b7f
JN		 313 switch (intel_encoder->type) {
314 case INTEL_OUTPUT_DP_MST:
a1e6ad66
ID		 315 *dig_port = enc_to_mst(encoder)->primary;
316 *port = (*dig_port)->port;
8cd21b7f
JN		 317 break;
318 case INTEL_OUTPUT_DISPLAYPORT:
319 case INTEL_OUTPUT_EDP:
320 case INTEL_OUTPUT_HDMI:
321 case INTEL_OUTPUT_UNKNOWN:
a1e6ad66
ID		 322 *dig_port = enc_to_dig_port(encoder);
323 *port = (*dig_port)->port;
8cd21b7f
JN		 324 break;
325 case INTEL_OUTPUT_ANALOG:
a1e6ad66
ID		 326 *dig_port = NULL;
327 *port = PORT_E;
8cd21b7f
JN		 328 break;
329 default:
330 WARN(1, "Invalid DDI encoder type %d\n", intel_encoder->type);
331 break;
fc914639
PZ		 332 }
333}
334
a1e6ad66
ID		 335enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
336{
337 struct intel_digital_port *dig_port;
338 enum port port;
339
340 ddi_get_encoder_port(intel_encoder, &dig_port, &port);
341
342 return port;
343}
344
acee2998 345static const struct ddi_buf_trans *
78ab0bae 346skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 347{
78ab0bae 348 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
5f8b2531 349 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
acee2998 350 return skl_y_ddi_translations_dp;
78ab0bae 351 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) {
f8896f5d 352 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
acee2998 353 return skl_u_ddi_translations_dp;
f8896f5d 354 } else {
f8896f5d 355 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
acee2998 356 return skl_ddi_translations_dp;
f8896f5d 357 }
f8896f5d
DW		 358}
359
acee2998 360static const struct ddi_buf_trans *
78ab0bae 361skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 362{
cd1101cb 363 if (dev_priv->edp_low_vswing) {
78ab0bae 364 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
5f8b2531 365 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
acee2998 366 return skl_y_ddi_translations_edp;
78ab0bae 367 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) {
f8896f5d 368 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
acee2998 369 return skl_u_ddi_translations_edp;
f8896f5d 370 } else {
f8896f5d 371 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
acee2998 372 return skl_ddi_translations_edp;
f8896f5d
DW		 373 }
374 }
cd1101cb 375
78ab0bae 376 return skl_get_buf_trans_dp(dev_priv, n_entries);
f8896f5d
DW		 377}
378
379static const struct ddi_buf_trans *
78ab0bae 380skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 381{
78ab0bae 382 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
5f8b2531 383 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
acee2998 384 return skl_y_ddi_translations_hdmi;
f8896f5d 385 } else {
f8896f5d 386 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
acee2998 387 return skl_ddi_translations_hdmi;
f8896f5d 388 }
f8896f5d
DW		 389}
390
e58623cb
AR		 391/*
392 * Starting with Haswell, DDI port buffers must be programmed with correct
393 * values in advance. The buffer values are different for FDI and DP modes,
45244b87
ED		 394 * but the HDMI/DVI fields are shared among those. So we program the DDI
395 * in either FDI or DP modes only, as HDMI connections will work with both
396 * of those
397 */
6a7e4f99 398void intel_prepare_ddi_buffer(struct intel_encoder *encoder)
45244b87 399{
6a7e4f99 400 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
75067dde 401 u32 iboost_bit = 0;
7ff44670 402 int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry,
7ad14a29 403 size;
6a7e4f99
VS		 404 int hdmi_level;
405 enum port port;
10122051
JN		 406 const struct ddi_buf_trans *ddi_translations_fdi;
407 const struct ddi_buf_trans *ddi_translations_dp;
408 const struct ddi_buf_trans *ddi_translations_edp;
409 const struct ddi_buf_trans *ddi_translations_hdmi;
410 const struct ddi_buf_trans *ddi_translations;
e58623cb 411
6a7e4f99
VS		 412 port = intel_ddi_get_encoder_port(encoder);
413 hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
414
78ab0bae 415 if (IS_BROXTON(dev_priv)) {
6a7e4f99 416 if (encoder->type != INTEL_OUTPUT_HDMI)
96fb9f9b
VK		 417 return;
418
419 /* Vswing programming for HDMI */
78ab0bae 420 bxt_ddi_vswing_sequence(dev_priv, hdmi_level, port,
96fb9f9b
VK		 421 INTEL_OUTPUT_HDMI);
422 return;
6a7e4f99
VS		 423 }
424
425 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
c30400fc 426 ddi_translations_fdi = NULL;
f8896f5d 427 ddi_translations_dp =
78ab0bae 428 skl_get_buf_trans_dp(dev_priv, &n_dp_entries);
f8896f5d 429 ddi_translations_edp =
78ab0bae 430 skl_get_buf_trans_edp(dev_priv, &n_edp_entries);
f8896f5d 431 ddi_translations_hdmi =
78ab0bae 432 skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
f8896f5d 433 hdmi_default_entry = 8;
75067dde
AK		 434 /* If we're boosting the current, set bit 31 of trans1 */
435 if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level ||
436 dev_priv->vbt.ddi_port_info[port].dp_boost_level)
437 iboost_bit = 1<<31;
10afa0b6 438
ceccad59
VS		 439 if (WARN_ON(encoder->type == INTEL_OUTPUT_EDP &&
440 port != PORT_A && port != PORT_E &&
441 n_edp_entries > 9))
10afa0b6 442 n_edp_entries = 9;
78ab0bae 443 } else if (IS_BROADWELL(dev_priv)) {
e58623cb
AR		 444 ddi_translations_fdi = bdw_ddi_translations_fdi;
445 ddi_translations_dp = bdw_ddi_translations_dp;
300644c7 446 ddi_translations_edp = bdw_ddi_translations_edp;
a26aa8ba 447 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
7ad14a29
SJ		 448 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
449 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 450 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
7ff44670 451 hdmi_default_entry = 7;
78ab0bae 452 } else if (IS_HASWELL(dev_priv)) {
e58623cb
AR		 453 ddi_translations_fdi = hsw_ddi_translations_fdi;
454 ddi_translations_dp = hsw_ddi_translations_dp;
300644c7 455 ddi_translations_edp = hsw_ddi_translations_dp;
a26aa8ba 456 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
7ad14a29 457 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
10122051 458 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
7ff44670 459 hdmi_default_entry = 6;
e58623cb
AR		 460 } else {
461 WARN(1, "ddi translation table missing\n");
300644c7 462 ddi_translations_edp = bdw_ddi_translations_dp;
e58623cb
AR		 463 ddi_translations_fdi = bdw_ddi_translations_fdi;
464 ddi_translations_dp = bdw_ddi_translations_dp;
a26aa8ba 465 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
7ad14a29
SJ		 466 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
467 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 468 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
7ff44670 469 hdmi_default_entry = 7;
e58623cb
AR		 470 }
471
6a7e4f99
VS		 472 switch (encoder->type) {
473 case INTEL_OUTPUT_EDP:
300644c7 474 ddi_translations = ddi_translations_edp;
7ad14a29 475 size = n_edp_entries;
300644c7 476 break;
6a7e4f99
VS		 477 case INTEL_OUTPUT_DISPLAYPORT:
478 case INTEL_OUTPUT_HDMI:
300644c7 479 ddi_translations = ddi_translations_dp;
7ad14a29 480 size = n_dp_entries;
300644c7 481 break;
6a7e4f99
VS		 482 case INTEL_OUTPUT_ANALOG:
483 ddi_translations = ddi_translations_fdi;
7ad14a29 484 size = n_dp_entries;
300644c7
PZ		 485 break;
486 default:
487 BUG();
488 }
45244b87 489
9712e688
VS		 490 for (i = 0; i < size; i++) {
491 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
492 ddi_translations[i].trans1 | iboost_bit);
493 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
494 ddi_translations[i].trans2);
45244b87 495 }
ce4dd49e 496
6a7e4f99 497 if (encoder->type != INTEL_OUTPUT_HDMI)
ce3b7e9b
DL		 498 return;
499
ce4dd49e
DL		 500 /* Choose a good default if VBT is badly populated */
501 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
502 hdmi_level >= n_hdmi_entries)
7ff44670 503 hdmi_level = hdmi_default_entry;
ce4dd49e 504
6acab15a 505 /* Entry 9 is for HDMI: */
9712e688
VS		 506 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
507 ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
508 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
509 ddi_translations_hdmi[hdmi_level].trans2);
45244b87
ED		 510}
511
248138b5
PZ		 512static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
513 enum port port)
514{
f0f59a00 515 i915_reg_t reg = DDI_BUF_CTL(port);
248138b5
PZ		 516 int i;
517
3449ca85 518 for (i = 0; i < 16; i++) {
248138b5
PZ		 519 udelay(1);
520 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
521 return;
522 }
523 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
524}
c82e4d26
ED		 525
526/* Starting with Haswell, different DDI ports can work in FDI mode for
527 * connection to the PCH-located connectors. For this, it is necessary to train
528 * both the DDI port and PCH receiver for the desired DDI buffer settings.
529 *
530 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
531 * please note that when FDI mode is active on DDI E, it shares 2 lines with
532 * DDI A (which is used for eDP)
533 */
534
535void hsw_fdi_link_train(struct drm_crtc *crtc)
536{
537 struct drm_device *dev = crtc->dev;
538 struct drm_i915_private *dev_priv = dev->dev_private;
539 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6a7e4f99 540 struct intel_encoder *encoder;
04945641 541 u32 temp, i, rx_ctl_val;
c82e4d26 542
6a7e4f99
VS		 543 for_each_encoder_on_crtc(dev, crtc, encoder) {
544 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
545 intel_prepare_ddi_buffer(encoder);
546 }
547
04945641
PZ		 548 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
549 * mode set "sequence for CRT port" document:
550 * - TP1 to TP2 time with the default value
551 * - FDI delay to 90h
8693a824
DL		 552 *
553 * WaFDIAutoLinkSetTimingOverrride:hsw
04945641 554 */
eede3b53 555 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
04945641
PZ		 556 FDI_RX_PWRDN_LANE0_VAL(2) |
557 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
558
559 /* Enable the PCH Receiver FDI PLL */
3e68320e 560 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
33d29b14 561 FDI_RX_PLL_ENABLE |
6e3c9717 562 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
eede3b53
VS		 563 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
564 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 565 udelay(220);
566
567 /* Switch from Rawclk to PCDclk */
568 rx_ctl_val |= FDI_PCDCLK;
eede3b53 569 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
04945641
PZ		 570
571 /* Configure Port Clock Select */
6e3c9717
ACO		 572 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
573 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
04945641
PZ		 574
575 /* Start the training iterating through available voltages and emphasis,
576 * testing each value twice. */
10122051 577 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
c82e4d26
ED		 578 /* Configure DP_TP_CTL with auto-training */
579 I915_WRITE(DP_TP_CTL(PORT_E),
580 DP_TP_CTL_FDI_AUTOTRAIN |
581 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
582 DP_TP_CTL_LINK_TRAIN_PAT1 |
583 DP_TP_CTL_ENABLE);
584
876a8cdf
DL		 585 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
586 * DDI E does not support port reversal, the functionality is
587 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
588 * port reversal bit */
c82e4d26 589 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641 590 DDI_BUF_CTL_ENABLE |
6e3c9717 591 ((intel_crtc->config->fdi_lanes - 1) << 1) |
c5fe6a06 592 DDI_BUF_TRANS_SELECT(i / 2));
04945641 593 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 594
595 udelay(600);
596
04945641 597 /* Program PCH FDI Receiver TU */
eede3b53 598 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
04945641
PZ		 599
600 /* Enable PCH FDI Receiver with auto-training */
601 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
eede3b53
VS		 602 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
603 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 604
605 /* Wait for FDI receiver lane calibration */
606 udelay(30);
607
608 /* Unset FDI_RX_MISC pwrdn lanes */
eede3b53 609 temp = I915_READ(FDI_RX_MISC(PIPE_A));
04945641 610 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
eede3b53
VS		 611 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
612 POSTING_READ(FDI_RX_MISC(PIPE_A));
04945641
PZ		 613
614 /* Wait for FDI auto training time */
615 udelay(5);
c82e4d26
ED		 616
617 temp = I915_READ(DP_TP_STATUS(PORT_E));
618 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 619 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
a308ccb3
VS		 620 break;
621 }
c82e4d26 622
a308ccb3
VS		 623 /*
624 * Leave things enabled even if we failed to train FDI.
625 * Results in less fireworks from the state checker.
626 */
627 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
628 DRM_ERROR("FDI link training failed!\n");
629 break;
c82e4d26 630 }
04945641 631
248138b5
PZ		 632 temp = I915_READ(DDI_BUF_CTL(PORT_E));
633 temp &= ~DDI_BUF_CTL_ENABLE;
634 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
635 POSTING_READ(DDI_BUF_CTL(PORT_E));
636
04945641 637 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
248138b5
PZ		 638 temp = I915_READ(DP_TP_CTL(PORT_E));
639 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
640 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
641 I915_WRITE(DP_TP_CTL(PORT_E), temp);
642 POSTING_READ(DP_TP_CTL(PORT_E));
643
644 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
04945641
PZ		 645
646 rx_ctl_val &= ~FDI_RX_ENABLE;
eede3b53
VS		 647 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
648 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 649
650 /* Reset FDI_RX_MISC pwrdn lanes */
eede3b53 651 temp = I915_READ(FDI_RX_MISC(PIPE_A));
04945641
PZ		 652 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
653 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
eede3b53
VS		 654 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
655 POSTING_READ(FDI_RX_MISC(PIPE_A));
c82e4d26
ED		 656 }
657
a308ccb3
VS		 658 /* Enable normal pixel sending for FDI */
659 I915_WRITE(DP_TP_CTL(PORT_E),
660 DP_TP_CTL_FDI_AUTOTRAIN |
661 DP_TP_CTL_LINK_TRAIN_NORMAL |
662 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
663 DP_TP_CTL_ENABLE);
c82e4d26 664}
0e72a5b5 665
44905a27
DA		 666void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
667{
668 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
669 struct intel_digital_port *intel_dig_port =
670 enc_to_dig_port(&encoder->base);
671
672 intel_dp->DP = intel_dig_port->saved_port_bits |
c5fe6a06 673 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
901c2daf 674 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
44905a27
DA		 675}
676
8d9ddbcb
PZ		 677static struct intel_encoder *
678intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
679{
680 struct drm_device *dev = crtc->dev;
681 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
682 struct intel_encoder *intel_encoder, *ret = NULL;
683 int num_encoders = 0;
684
685 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
686 ret = intel_encoder;
687 num_encoders++;
688 }
689
690 if (num_encoders != 1)
84f44ce7
VS		 691 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
692 pipe_name(intel_crtc->pipe));
8d9ddbcb
PZ		 693
694 BUG_ON(ret == NULL);
695 return ret;
696}
697
bcddf610 698struct intel_encoder *
3165c074 699intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
d0737e1d 700{
3165c074
ACO		 701 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
702 struct intel_encoder *ret = NULL;
703 struct drm_atomic_state *state;
da3ced29
ACO		 704 struct drm_connector *connector;
705 struct drm_connector_state *connector_state;
d0737e1d 706 int num_encoders = 0;
3165c074 707 int i;
d0737e1d 708
3165c074
ACO		 709 state = crtc_state->base.state;
710
da3ced29
ACO		 711 for_each_connector_in_state(state, connector, connector_state, i) {
712 if (connector_state->crtc != crtc_state->base.crtc)
3165c074
ACO		 713 continue;
714
da3ced29 715 ret = to_intel_encoder(connector_state->best_encoder);
3165c074 716 num_encoders++;
d0737e1d
ACO		 717 }
718
719 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
720 pipe_name(crtc->pipe));
721
722 BUG_ON(ret == NULL);
723 return ret;
724}
725
1c0b85c5 726#define LC_FREQ 2700
1c0b85c5 727
f0f59a00
VS		 728static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
729 i915_reg_t reg)
11578553
JB		 730{
731 int refclk = LC_FREQ;
732 int n, p, r;
733 u32 wrpll;
734
735 wrpll = I915_READ(reg);
114fe488
DV		 736 switch (wrpll & WRPLL_PLL_REF_MASK) {
737 case WRPLL_PLL_SSC:
738 case WRPLL_PLL_NON_SSC:
11578553
JB		 739 /*
740 * We could calculate spread here, but our checking
741 * code only cares about 5% accuracy, and spread is a max of
742 * 0.5% downspread.
743 */
744 refclk = 135;
745 break;
114fe488 746 case WRPLL_PLL_LCPLL:
11578553
JB		 747 refclk = LC_FREQ;
748 break;
749 default:
750 WARN(1, "bad wrpll refclk\n");
751 return 0;
752 }
753
754 r = wrpll & WRPLL_DIVIDER_REF_MASK;
755 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
756 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
757
20f0ec16
JB		 758 /* Convert to KHz, p & r have a fixed point portion */
759 return (refclk * n * 100) / (p * r);
11578553
JB		 760}
761
540e732c
S		 762static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
763 uint32_t dpll)
764{
f0f59a00 765 i915_reg_t cfgcr1_reg, cfgcr2_reg;
540e732c
S		 766 uint32_t cfgcr1_val, cfgcr2_val;
767 uint32_t p0, p1, p2, dco_freq;
768
923c1241
VS		 769 cfgcr1_reg = DPLL_CFGCR1(dpll);
770 cfgcr2_reg = DPLL_CFGCR2(dpll);
540e732c
S		 771
772 cfgcr1_val = I915_READ(cfgcr1_reg);
773 cfgcr2_val = I915_READ(cfgcr2_reg);
774
775 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
776 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
777
778 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
779 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
780 else
781 p1 = 1;
782
783
784 switch (p0) {
785 case DPLL_CFGCR2_PDIV_1:
786 p0 = 1;
787 break;
788 case DPLL_CFGCR2_PDIV_2:
789 p0 = 2;
790 break;
791 case DPLL_CFGCR2_PDIV_3:
792 p0 = 3;
793 break;
794 case DPLL_CFGCR2_PDIV_7:
795 p0 = 7;
796 break;
797 }
798
799 switch (p2) {
800 case DPLL_CFGCR2_KDIV_5:
801 p2 = 5;
802 break;
803 case DPLL_CFGCR2_KDIV_2:
804 p2 = 2;
805 break;
806 case DPLL_CFGCR2_KDIV_3:
807 p2 = 3;
808 break;
809 case DPLL_CFGCR2_KDIV_1:
810 p2 = 1;
811 break;
812 }
813
814 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
815
816 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
817 1000) / 0x8000;
818
819 return dco_freq / (p0 * p1 * p2 * 5);
820}
821
398a017e
VS		 822static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
823{
824 int dotclock;
825
826 if (pipe_config->has_pch_encoder)
827 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
828 &pipe_config->fdi_m_n);
829 else if (pipe_config->has_dp_encoder)
830 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
831 &pipe_config->dp_m_n);
832 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
833 dotclock = pipe_config->port_clock * 2 / 3;
834 else
835 dotclock = pipe_config->port_clock;
836
837 if (pipe_config->pixel_multiplier)
838 dotclock /= pipe_config->pixel_multiplier;
839
840 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
841}
540e732c
S		 842
843static void skl_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 844 struct intel_crtc_state *pipe_config)
540e732c
S		 845{
846 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
540e732c
S		 847 int link_clock = 0;
848 uint32_t dpll_ctl1, dpll;
849
134ffa44 850 dpll = pipe_config->ddi_pll_sel;
540e732c
S		 851
852 dpll_ctl1 = I915_READ(DPLL_CTRL1);
853
854 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
855 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
856 } else {
71cd8423
DL		 857 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
858 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
540e732c
S		 859
860 switch (link_clock) {
71cd8423 861 case DPLL_CTRL1_LINK_RATE_810:
540e732c
S		 862 link_clock = 81000;
863 break;
71cd8423 864 case DPLL_CTRL1_LINK_RATE_1080:
a8f3ef61
SJ		 865 link_clock = 108000;
866 break;
71cd8423 867 case DPLL_CTRL1_LINK_RATE_1350:
540e732c
S		 868 link_clock = 135000;
869 break;
71cd8423 870 case DPLL_CTRL1_LINK_RATE_1620:
a8f3ef61
SJ		 871 link_clock = 162000;
872 break;
71cd8423 873 case DPLL_CTRL1_LINK_RATE_2160:
a8f3ef61
SJ		 874 link_clock = 216000;
875 break;
71cd8423 876 case DPLL_CTRL1_LINK_RATE_2700:
540e732c
S		 877 link_clock = 270000;
878 break;
879 default:
880 WARN(1, "Unsupported link rate\n");
881 break;
882 }
883 link_clock *= 2;
884 }
885
886 pipe_config->port_clock = link_clock;
887
398a017e 888 ddi_dotclock_get(pipe_config);
540e732c
S		 889}
890
3d51278a 891static void hsw_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 892 struct intel_crtc_state *pipe_config)
11578553
JB		 893{
894 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
11578553
JB		 895 int link_clock = 0;
896 u32 val, pll;
897
26804afd 898 val = pipe_config->ddi_pll_sel;
11578553
JB		 899 switch (val & PORT_CLK_SEL_MASK) {
900 case PORT_CLK_SEL_LCPLL_810:
901 link_clock = 81000;
902 break;
903 case PORT_CLK_SEL_LCPLL_1350:
904 link_clock = 135000;
905 break;
906 case PORT_CLK_SEL_LCPLL_2700:
907 link_clock = 270000;
908 break;
909 case PORT_CLK_SEL_WRPLL1:
01403de3 910 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
11578553
JB		 911 break;
912 case PORT_CLK_SEL_WRPLL2:
01403de3 913 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
11578553
JB		 914 break;
915 case PORT_CLK_SEL_SPLL:
916 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
917 if (pll == SPLL_PLL_FREQ_810MHz)
918 link_clock = 81000;
919 else if (pll == SPLL_PLL_FREQ_1350MHz)
920 link_clock = 135000;
921 else if (pll == SPLL_PLL_FREQ_2700MHz)
922 link_clock = 270000;
923 else {
924 WARN(1, "bad spll freq\n");
925 return;
926 }
927 break;
928 default:
929 WARN(1, "bad port clock sel\n");
930 return;
931 }
932
933 pipe_config->port_clock = link_clock * 2;
934
398a017e 935 ddi_dotclock_get(pipe_config);
11578553
JB		 936}
937
977bb38d
S		 938static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
939 enum intel_dpll_id dpll)
940{
aa610dcb
ID		 941 struct intel_shared_dpll *pll;
942 struct intel_dpll_hw_state *state;
943 intel_clock_t clock;
944
945 /* For DDI ports we always use a shared PLL. */
946 if (WARN_ON(dpll == DPLL_ID_PRIVATE))
947 return 0;
948
949 pll = &dev_priv->shared_dplls[dpll];
950 state = &pll->config.hw_state;
951
952 clock.m1 = 2;
953 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
954 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
955 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
956 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
957 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
958 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
959
960 return chv_calc_dpll_params(100000, &clock);
977bb38d
S		 961}
962
963static void bxt_ddi_clock_get(struct intel_encoder *encoder,
964 struct intel_crtc_state *pipe_config)
965{
966 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
967 enum port port = intel_ddi_get_encoder_port(encoder);
968 uint32_t dpll = port;
969
398a017e 970 pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);
977bb38d 971
398a017e 972 ddi_dotclock_get(pipe_config);
977bb38d
S		 973}
974
3d51278a 975void intel_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 976 struct intel_crtc_state *pipe_config)
3d51278a 977{
22606a18
DL		 978 struct drm_device *dev = encoder->base.dev;
979
980 if (INTEL_INFO(dev)->gen <= 8)
981 hsw_ddi_clock_get(encoder, pipe_config);
ef11bdb3 982 else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
22606a18 983 skl_ddi_clock_get(encoder, pipe_config);
977bb38d
S		 984 else if (IS_BROXTON(dev))
985 bxt_ddi_clock_get(encoder, pipe_config);
3d51278a
DV		 986}
987
0220ab6e 988static bool
d664c0ce 989hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 990 struct intel_crtc_state *crtc_state,
96f3f1f9 991 struct intel_encoder *intel_encoder)
6441ab5f 992{
daedf20a 993 struct intel_shared_dpll *pll;
6441ab5f 994
9d16da65
ACO		 995 pll = intel_get_shared_dpll(intel_crtc, crtc_state,
996 intel_encoder);
997 if (!pll)
998 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
999 pipe_name(intel_crtc->pipe));
1000
1001 return pll;
6441ab5f
PZ		 1002}
1003
82d35437
S		 1004static bool
1005skl_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 1006 struct intel_crtc_state *crtc_state,
96f3f1f9 1007 struct intel_encoder *intel_encoder)
82d35437
S		 1008{
1009 struct intel_shared_dpll *pll;
82d35437 1010
daedf20a 1011 pll = intel_get_shared_dpll(intel_crtc, crtc_state, intel_encoder);
82d35437
S		 1012 if (pll == NULL) {
1013 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1014 pipe_name(intel_crtc->pipe));
1015 return false;
1016 }
1017
82d35437
S		 1018 return true;
1019}
0220ab6e 1020
d683f3bc
S		 1021static bool
1022bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
1023 struct intel_crtc_state *crtc_state,
96f3f1f9 1024 struct intel_encoder *intel_encoder)
d683f3bc 1025{
34177c24 1026 return !!intel_get_shared_dpll(intel_crtc, crtc_state, intel_encoder);
d683f3bc
S		 1027}
1028
0220ab6e
DL		 1029/*
1030 * Tries to find a *shared* PLL for the CRTC and store it in
1031 * intel_crtc->ddi_pll_sel.
1032 *
1033 * For private DPLLs, compute_config() should do the selection for us. This
1034 * function should be folded into compute_config() eventually.
1035 */
190f68c5
ACO		 1036bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
1037 struct intel_crtc_state *crtc_state)
0220ab6e 1038{
82d35437 1039 struct drm_device *dev = intel_crtc->base.dev;
d0737e1d 1040 struct intel_encoder *intel_encoder =
3165c074 1041 intel_ddi_get_crtc_new_encoder(crtc_state);
0220ab6e 1042
ef11bdb3 1043 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
190f68c5 1044 return skl_ddi_pll_select(intel_crtc, crtc_state,
96f3f1f9 1045 intel_encoder);
d683f3bc
S		 1046 else if (IS_BROXTON(dev))
1047 return bxt_ddi_pll_select(intel_crtc, crtc_state,
96f3f1f9 1048 intel_encoder);
82d35437 1049 else
190f68c5 1050 return hsw_ddi_pll_select(intel_crtc, crtc_state,
96f3f1f9 1051 intel_encoder);
0220ab6e
DL		 1052}
1053
dae84799
PZ		 1054void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1055{
1056 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1057 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1058 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
6e3c9717 1059 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
dae84799
PZ		 1060 int type = intel_encoder->type;
1061 uint32_t temp;
1062
0e32b39c 1063 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
c9809791 1064 temp = TRANS_MSA_SYNC_CLK;
6e3c9717 1065 switch (intel_crtc->config->pipe_bpp) {
dae84799 1066 case 18:
c9809791 1067 temp |= TRANS_MSA_6_BPC;
dae84799
PZ		 1068 break;
1069 case 24:
c9809791 1070 temp |= TRANS_MSA_8_BPC;
dae84799
PZ		 1071 break;
1072 case 30:
c9809791 1073 temp |= TRANS_MSA_10_BPC;
dae84799
PZ		 1074 break;
1075 case 36:
c9809791 1076 temp |= TRANS_MSA_12_BPC;
dae84799
PZ		 1077 break;
1078 default:
4e53c2e0 1079 BUG();
dae84799 1080 }
c9809791 1081 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 1082 }
1083}
1084
0e32b39c
DA		 1085void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1086{
1087 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1088 struct drm_device *dev = crtc->dev;
1089 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1090 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
0e32b39c
DA		 1091 uint32_t temp;
1092 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1093 if (state == true)
1094 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1095 else
1096 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1097 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1098}
1099
8228c251 1100void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
8d9ddbcb
PZ		 1101{
1102 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1103 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
7739c33b 1104 struct drm_encoder *encoder = &intel_encoder->base;
c7670b10
PZ		 1105 struct drm_device *dev = crtc->dev;
1106 struct drm_i915_private *dev_priv = dev->dev_private;
8d9ddbcb 1107 enum pipe pipe = intel_crtc->pipe;
6e3c9717 1108 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
174edf1f 1109 enum port port = intel_ddi_get_encoder_port(intel_encoder);
7739c33b 1110 int type = intel_encoder->type;
8d9ddbcb
PZ		 1111 uint32_t temp;
1112
ad80a810
PZ		 1113 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1114 temp = TRANS_DDI_FUNC_ENABLE;
174edf1f 1115 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252 1116
6e3c9717 1117 switch (intel_crtc->config->pipe_bpp) {
dfcef252 1118 case 18:
ad80a810 1119 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 1120 break;
1121 case 24:
ad80a810 1122 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 1123 break;
1124 case 30:
ad80a810 1125 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 1126 break;
1127 case 36:
ad80a810 1128 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 1129 break;
1130 default:
4e53c2e0 1131 BUG();
dfcef252 1132 }
72662e10 1133
6e3c9717 1134 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 1135 temp |= TRANS_DDI_PVSYNC;
6e3c9717 1136 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 1137 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 1138
e6f0bfc4
PZ		 1139 if (cpu_transcoder == TRANSCODER_EDP) {
1140 switch (pipe) {
1141 case PIPE_A:
c7670b10
PZ		 1142 /* On Haswell, can only use the always-on power well for
1143 * eDP when not using the panel fitter, and when not
1144 * using motion blur mitigation (which we don't
1145 * support). */
fabf6e51 1146 if (IS_HASWELL(dev) &&
6e3c9717
ACO		 1147 (intel_crtc->config->pch_pfit.enabled ||
1148 intel_crtc->config->pch_pfit.force_thru))
d6dd9eb1
DV		 1149 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1150 else
1151 temp |= TRANS_DDI_EDP_INPUT_A_ON;
e6f0bfc4
PZ		 1152 break;
1153 case PIPE_B:
1154 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1155 break;
1156 case PIPE_C:
1157 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1158 break;
1159 default:
1160 BUG();
1161 break;
1162 }
1163 }
1164
7739c33b 1165 if (type == INTEL_OUTPUT_HDMI) {
6e3c9717 1166 if (intel_crtc->config->has_hdmi_sink)
ad80a810 1167 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 1168 else
ad80a810 1169 temp |= TRANS_DDI_MODE_SELECT_DVI;
8d9ddbcb 1170
7739c33b 1171 } else if (type == INTEL_OUTPUT_ANALOG) {
ad80a810 1172 temp |= TRANS_DDI_MODE_SELECT_FDI;
6e3c9717 1173 temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
7739c33b
PZ		 1174
1175 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1176 type == INTEL_OUTPUT_EDP) {
1177 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1178
0e32b39c
DA		 1179 if (intel_dp->is_mst) {
1180 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1181 } else
1182 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1183
90a6b7b0 1184 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
0e32b39c
DA		 1185 } else if (type == INTEL_OUTPUT_DP_MST) {
1186 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
1187
1188 if (intel_dp->is_mst) {
1189 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1190 } else
1191 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
7739c33b 1192
90a6b7b0 1193 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
8d9ddbcb 1194 } else {
84f44ce7
VS		 1195 WARN(1, "Invalid encoder type %d for pipe %c\n",
1196 intel_encoder->type, pipe_name(pipe));
8d9ddbcb
PZ		 1197 }
1198
ad80a810 1199 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 1200}
72662e10 1201
ad80a810
PZ		 1202void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1203 enum transcoder cpu_transcoder)
8d9ddbcb 1204{
f0f59a00 1205 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
8d9ddbcb
PZ		 1206 uint32_t val = I915_READ(reg);
1207
0e32b39c 1208 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
ad80a810 1209 val |= TRANS_DDI_PORT_NONE;
8d9ddbcb 1210 I915_WRITE(reg, val);
72662e10
ED		 1211}
1212
bcbc889b
PZ		 1213bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1214{
1215 struct drm_device *dev = intel_connector->base.dev;
1216 struct drm_i915_private *dev_priv = dev->dev_private;
1217 struct intel_encoder *intel_encoder = intel_connector->encoder;
1218 int type = intel_connector->base.connector_type;
1219 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1220 enum pipe pipe = 0;
1221 enum transcoder cpu_transcoder;
882244a3 1222 enum intel_display_power_domain power_domain;
bcbc889b 1223 uint32_t tmp;
e27daab4 1224 bool ret;
bcbc889b 1225
882244a3 1226 power_domain = intel_display_port_power_domain(intel_encoder);
e27daab4 1227 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
882244a3
PZ		 1228 return false;
1229
e27daab4
ID		 1230 if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) {
1231 ret = false;
1232 goto out;
1233 }
bcbc889b
PZ		 1234
1235 if (port == PORT_A)
1236 cpu_transcoder = TRANSCODER_EDP;
1237 else
1a240d4d 1238 cpu_transcoder = (enum transcoder) pipe;
bcbc889b
PZ		 1239
1240 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1241
1242 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1243 case TRANS_DDI_MODE_SELECT_HDMI:
1244 case TRANS_DDI_MODE_SELECT_DVI:
e27daab4
ID		 1245 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1246 break;
bcbc889b
PZ		 1247
1248 case TRANS_DDI_MODE_SELECT_DP_SST:
e27daab4
ID		 1249 ret = type == DRM_MODE_CONNECTOR_eDP ||
1250 type == DRM_MODE_CONNECTOR_DisplayPort;
1251 break;
1252
0e32b39c
DA		 1253 case TRANS_DDI_MODE_SELECT_DP_MST:
1254 /* if the transcoder is in MST state then
1255 * connector isn't connected */
e27daab4
ID		 1256 ret = false;
1257 break;
bcbc889b
PZ		 1258
1259 case TRANS_DDI_MODE_SELECT_FDI:
e27daab4
ID		 1260 ret = type == DRM_MODE_CONNECTOR_VGA;
1261 break;
bcbc889b
PZ		 1262
1263 default:
e27daab4
ID		 1264 ret = false;
1265 break;
bcbc889b 1266 }
e27daab4
ID		 1267
1268out:
1269 intel_display_power_put(dev_priv, power_domain);
1270
1271 return ret;
bcbc889b
PZ		 1272}
1273
85234cdc
DV		 1274bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1275 enum pipe *pipe)
1276{
1277 struct drm_device *dev = encoder->base.dev;
1278 struct drm_i915_private *dev_priv = dev->dev_private;
fe43d3f5 1279 enum port port = intel_ddi_get_encoder_port(encoder);
6d129bea 1280 enum intel_display_power_domain power_domain;
85234cdc
DV		 1281 u32 tmp;
1282 int i;
e27daab4 1283 bool ret;
85234cdc 1284
6d129bea 1285 power_domain = intel_display_port_power_domain(encoder);
e27daab4 1286 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
6d129bea
ID		 1287 return false;
1288
e27daab4
ID		 1289 ret = false;
1290
fe43d3f5 1291 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc
DV		 1292
1293 if (!(tmp & DDI_BUF_CTL_ENABLE))
e27daab4 1294 goto out;
85234cdc 1295
ad80a810
PZ		 1296 if (port == PORT_A) {
1297 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 1298
ad80a810
PZ		 1299 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1300 case TRANS_DDI_EDP_INPUT_A_ON:
1301 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1302 *pipe = PIPE_A;
1303 break;
1304 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1305 *pipe = PIPE_B;
1306 break;
1307 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1308 *pipe = PIPE_C;
1309 break;
1310 }
1311
e27daab4 1312 ret = true;
ad80a810 1313
e27daab4
ID		 1314 goto out;
1315 }
0e32b39c 1316
e27daab4
ID		 1317 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1318 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1319
1320 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) {
1321 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
1322 TRANS_DDI_MODE_SELECT_DP_MST)
1323 goto out;
1324
1325 *pipe = i;
1326 ret = true;
1327
1328 goto out;
85234cdc
DV		 1329 }
1330 }
1331
84f44ce7 1332 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
85234cdc 1333
e27daab4
ID		 1334out:
1335 intel_display_power_put(dev_priv, power_domain);
1336
1337 return ret;
85234cdc
DV		 1338}
1339
fc914639
PZ		 1340void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1341{
1342 struct drm_crtc *crtc = &intel_crtc->base;
7d4aefd0
SS		 1343 struct drm_device *dev = crtc->dev;
1344 struct drm_i915_private *dev_priv = dev->dev_private;
fc914639
PZ		 1345 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1346 enum port port = intel_ddi_get_encoder_port(intel_encoder);
6e3c9717 1347 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 1348
bb523fc0
PZ		 1349 if (cpu_transcoder != TRANSCODER_EDP)
1350 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1351 TRANS_CLK_SEL_PORT(port));
fc914639
PZ		 1352}
1353
1354void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1355{
1356 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
6e3c9717 1357 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 1358
bb523fc0
PZ		 1359 if (cpu_transcoder != TRANSCODER_EDP)
1360 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1361 TRANS_CLK_SEL_DISABLED);
fc914639
PZ		 1362}
1363
78ab0bae
VS		 1364static void skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
1365 u32 level, enum port port, int type)
f8896f5d 1366{
f8896f5d
DW		 1367 const struct ddi_buf_trans *ddi_translations;
1368 uint8_t iboost;
75067dde 1369 uint8_t dp_iboost, hdmi_iboost;
f8896f5d
DW		 1370 int n_entries;
1371 u32 reg;
1372
75067dde
AK		 1373 /* VBT may override standard boost values */
1374 dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
1375 hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
1376
f8896f5d 1377 if (type == INTEL_OUTPUT_DISPLAYPORT) {
75067dde
AK		 1378 if (dp_iboost) {
1379 iboost = dp_iboost;
1380 } else {
78ab0bae 1381 ddi_translations = skl_get_buf_trans_dp(dev_priv, &n_entries);
e4d4c05b 1382 iboost = ddi_translations[level].i_boost;
75067dde 1383 }
f8896f5d 1384 } else if (type == INTEL_OUTPUT_EDP) {
75067dde
AK		 1385 if (dp_iboost) {
1386 iboost = dp_iboost;
1387 } else {
78ab0bae 1388 ddi_translations = skl_get_buf_trans_edp(dev_priv, &n_entries);
10afa0b6
VS		 1389
1390 if (WARN_ON(port != PORT_A &&
1391 port != PORT_E && n_entries > 9))
1392 n_entries = 9;
1393
e4d4c05b 1394 iboost = ddi_translations[level].i_boost;
75067dde 1395 }
f8896f5d 1396 } else if (type == INTEL_OUTPUT_HDMI) {
75067dde
AK		 1397 if (hdmi_iboost) {
1398 iboost = hdmi_iboost;
1399 } else {
78ab0bae 1400 ddi_translations = skl_get_buf_trans_hdmi(dev_priv, &n_entries);
e4d4c05b 1401 iboost = ddi_translations[level].i_boost;
75067dde 1402 }
f8896f5d
DW		 1403 } else {
1404 return;
1405 }
1406
1407 /* Make sure that the requested I_boost is valid */
1408 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
1409 DRM_ERROR("Invalid I_boost value %u\n", iboost);
1410 return;
1411 }
1412
1413 reg = I915_READ(DISPIO_CR_TX_BMU_CR0);
1414 reg &= ~BALANCE_LEG_MASK(port);
1415 reg &= ~(1 << (BALANCE_LEG_DISABLE_SHIFT + port));
1416
1417 if (iboost)
1418 reg |= iboost << BALANCE_LEG_SHIFT(port);
1419 else
1420 reg |= 1 << (BALANCE_LEG_DISABLE_SHIFT + port);
1421
1422 I915_WRITE(DISPIO_CR_TX_BMU_CR0, reg);
1423}
1424
78ab0bae
VS		 1425static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
1426 u32 level, enum port port, int type)
96fb9f9b 1427{
96fb9f9b
VK		 1428 const struct bxt_ddi_buf_trans *ddi_translations;
1429 u32 n_entries, i;
1430 uint32_t val;
1431
d9d7000d
SJ		 1432 if (type == INTEL_OUTPUT_EDP && dev_priv->edp_low_vswing) {
1433 n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
1434 ddi_translations = bxt_ddi_translations_edp;
1435 } else if (type == INTEL_OUTPUT_DISPLAYPORT
1436 || type == INTEL_OUTPUT_EDP) {
96fb9f9b
VK		 1437 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
1438 ddi_translations = bxt_ddi_translations_dp;
1439 } else if (type == INTEL_OUTPUT_HDMI) {
1440 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
1441 ddi_translations = bxt_ddi_translations_hdmi;
1442 } else {
1443 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
1444 type);
1445 return;
1446 }
1447
1448 /* Check if default value has to be used */
1449 if (level >= n_entries ||
1450 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
1451 for (i = 0; i < n_entries; i++) {
1452 if (ddi_translations[i].default_index) {
1453 level = i;
1454 break;
1455 }
1456 }
1457 }
1458
1459 /*
1460 * While we write to the group register to program all lanes at once we
1461 * can read only lane registers and we pick lanes 0/1 for that.
1462 */
1463 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
1464 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
1465 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
1466
1467 val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
1468 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
1469 val |= ddi_translations[level].margin << MARGIN_000_SHIFT |
1470 ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
1471 I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
1472
1473 val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
9c58a049 1474 val &= ~SCALE_DCOMP_METHOD;
96fb9f9b 1475 if (ddi_translations[level].enable)
9c58a049
SJ		 1476 val |= SCALE_DCOMP_METHOD;
1477
1478 if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
1479 DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set");
1480
96fb9f9b
VK		 1481 I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
1482
1483 val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
1484 val &= ~DE_EMPHASIS;
1485 val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
1486 I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
1487
1488 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
1489 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
1490 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
1491}
1492
f8896f5d
DW		 1493static uint32_t translate_signal_level(int signal_levels)
1494{
1495 uint32_t level;
1496
1497 switch (signal_levels) {
1498 default:
1499 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n",
1500 signal_levels);
1501 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1502 level = 0;
1503 break;
1504 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1505 level = 1;
1506 break;
1507 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1508 level = 2;
1509 break;
1510 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
1511 level = 3;
1512 break;
1513
1514 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1515 level = 4;
1516 break;
1517 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1518 level = 5;
1519 break;
1520 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1521 level = 6;
1522 break;
1523
1524 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1525 level = 7;
1526 break;
1527 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1528 level = 8;
1529 break;
1530
1531 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1532 level = 9;
1533 break;
1534 }
1535
1536 return level;
1537}
1538
1539uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
1540{
1541 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
78ab0bae 1542 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
f8896f5d
DW		 1543 struct intel_encoder *encoder = &dport->base;
1544 uint8_t train_set = intel_dp->train_set[0];
1545 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1546 DP_TRAIN_PRE_EMPHASIS_MASK);
1547 enum port port = dport->port;
1548 uint32_t level;
1549
1550 level = translate_signal_level(signal_levels);
1551
78ab0bae
VS		 1552 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
1553 skl_ddi_set_iboost(dev_priv, level, port, encoder->type);
1554 else if (IS_BROXTON(dev_priv))
1555 bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
f8896f5d
DW		 1556
1557 return DDI_BUF_TRANS_SELECT(level);
1558}
1559
e404ba8d
VS		 1560void intel_ddi_clk_select(struct intel_encoder *encoder,
1561 const struct intel_crtc_state *pipe_config)
6441ab5f 1562{
e404ba8d
VS		 1563 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1564 enum port port = intel_ddi_get_encoder_port(encoder);
6441ab5f 1565
e404ba8d
VS		 1566 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1567 uint32_t dpll = pipe_config->ddi_pll_sel;
efa80add
S		 1568 uint32_t val;
1569
5416d871 1570 /* DDI -> PLL mapping */
efa80add
S		 1571 val = I915_READ(DPLL_CTRL2);
1572
1573 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
1574 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
1575 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
1576 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
1577
1578 I915_WRITE(DPLL_CTRL2, val);
5416d871 1579
e404ba8d
VS		 1580 } else if (INTEL_INFO(dev_priv)->gen < 9) {
1581 WARN_ON(pipe_config->ddi_pll_sel == PORT_CLK_SEL_NONE);
1582 I915_WRITE(PORT_CLK_SEL(port), pipe_config->ddi_pll_sel);
efa80add 1583 }
e404ba8d
VS		 1584}
1585
1586static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
1587{
1588 struct drm_encoder *encoder = &intel_encoder->base;
6a7e4f99 1589 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
e404ba8d
VS		 1590 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
1591 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1592 int type = intel_encoder->type;
6a7e4f99
VS		 1593
1594 intel_prepare_ddi_buffer(intel_encoder);
e404ba8d
VS		 1595
1596 if (type == INTEL_OUTPUT_EDP) {
1597 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1598 intel_edp_panel_on(intel_dp);
1599 }
1600
1601 intel_ddi_clk_select(intel_encoder, crtc->config);
c19b0669 1602
82a4d9c0 1603 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
c19b0669 1604 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
30cf6db8 1605
901c2daf
VS		 1606 intel_dp_set_link_params(intel_dp, crtc->config);
1607
44905a27 1608 intel_ddi_init_dp_buf_reg(intel_encoder);
c19b0669
PZ		 1609
1610 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1611 intel_dp_start_link_train(intel_dp);
6a7e4f99 1612 if (port != PORT_A || INTEL_INFO(dev_priv)->gen >= 9)
3ab9c637 1613 intel_dp_stop_link_train(intel_dp);
30cf6db8
DV		 1614 } else if (type == INTEL_OUTPUT_HDMI) {
1615 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1616
1617 intel_hdmi->set_infoframes(encoder,
6e3c9717
ACO		 1618 crtc->config->has_hdmi_sink,
1619 &crtc->config->base.adjusted_mode);
c19b0669 1620 }
6441ab5f
PZ		 1621}
1622
00c09d70 1623static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
6441ab5f
PZ		 1624{
1625 struct drm_encoder *encoder = &intel_encoder->base;
efa80add
S		 1626 struct drm_device *dev = encoder->dev;
1627 struct drm_i915_private *dev_priv = dev->dev_private;
6441ab5f 1628 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 1629 int type = intel_encoder->type;
2886e93f 1630 uint32_t val;
a836bdf9 1631 bool wait = false;
2886e93f
PZ		 1632
1633 val = I915_READ(DDI_BUF_CTL(port));
1634 if (val & DDI_BUF_CTL_ENABLE) {
1635 val &= ~DDI_BUF_CTL_ENABLE;
1636 I915_WRITE(DDI_BUF_CTL(port), val);
a836bdf9 1637 wait = true;
2886e93f 1638 }
6441ab5f 1639
a836bdf9
PZ		 1640 val = I915_READ(DP_TP_CTL(port));
1641 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1642 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1643 I915_WRITE(DP_TP_CTL(port), val);
1644
1645 if (wait)
1646 intel_wait_ddi_buf_idle(dev_priv, port);
1647
76bb80ed 1648 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
82a4d9c0 1649 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
76bb80ed 1650 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
24f3e092 1651 intel_edp_panel_vdd_on(intel_dp);
4be73780 1652 intel_edp_panel_off(intel_dp);
82a4d9c0
PZ		 1653 }
1654
ef11bdb3 1655 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
efa80add
S		 1656 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
1657 DPLL_CTRL2_DDI_CLK_OFF(port)));
1ab23380 1658 else if (INTEL_INFO(dev)->gen < 9)
efa80add 1659 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
6441ab5f
PZ		 1660}
1661
00c09d70 1662static void intel_enable_ddi(struct intel_encoder *intel_encoder)
72662e10 1663{
6547fef8 1664 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 1665 struct drm_crtc *crtc = encoder->crtc;
1666 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6547fef8 1667 struct drm_device *dev = encoder->dev;
72662e10 1668 struct drm_i915_private *dev_priv = dev->dev_private;
6547fef8
PZ		 1669 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1670 int type = intel_encoder->type;
72662e10 1671
6547fef8 1672 if (type == INTEL_OUTPUT_HDMI) {
876a8cdf
DL		 1673 struct intel_digital_port *intel_dig_port =
1674 enc_to_dig_port(encoder);
1675
6547fef8
PZ		 1676 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1677 * are ignored so nothing special needs to be done besides
1678 * enabling the port.
1679 */
876a8cdf 1680 I915_WRITE(DDI_BUF_CTL(port),
bcf53de4
SM		 1681 intel_dig_port->saved_port_bits |
1682 DDI_BUF_CTL_ENABLE);
d6c50ff8
PZ		 1683 } else if (type == INTEL_OUTPUT_EDP) {
1684 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1685
23f08d83 1686 if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
3ab9c637
ID		 1687 intel_dp_stop_link_train(intel_dp);
1688
4be73780 1689 intel_edp_backlight_on(intel_dp);
0bc12bcb 1690 intel_psr_enable(intel_dp);
c395578e 1691 intel_edp_drrs_enable(intel_dp);
6547fef8 1692 }
7b9f35a6 1693
6e3c9717 1694 if (intel_crtc->config->has_audio) {
d45a0bf5 1695 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
69bfe1a9 1696 intel_audio_codec_enable(intel_encoder);
7b9f35a6 1697 }
5ab432ef
DV		 1698}
1699
00c09d70 1700static void intel_disable_ddi(struct intel_encoder *intel_encoder)
5ab432ef 1701{
d6c50ff8 1702 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 1703 struct drm_crtc *crtc = encoder->crtc;
1704 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d6c50ff8 1705 int type = intel_encoder->type;
7b9f35a6
WX		 1706 struct drm_device *dev = encoder->dev;
1707 struct drm_i915_private *dev_priv = dev->dev_private;
d6c50ff8 1708
6e3c9717 1709 if (intel_crtc->config->has_audio) {
69bfe1a9 1710 intel_audio_codec_disable(intel_encoder);
d45a0bf5
PZ		 1711 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
1712 }
2831d842 1713
d6c50ff8
PZ		 1714 if (type == INTEL_OUTPUT_EDP) {
1715 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1716
c395578e 1717 intel_edp_drrs_disable(intel_dp);
0bc12bcb 1718 intel_psr_disable(intel_dp);
4be73780 1719 intel_edp_backlight_off(intel_dp);
d6c50ff8 1720 }
72662e10 1721}
79f689aa 1722
5c6706e5
VK		 1723static void broxton_phy_init(struct drm_i915_private *dev_priv,
1724 enum dpio_phy phy)
1725{
1726 enum port port;
1727 uint32_t val;
1728
1729 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
1730 val |= GT_DISPLAY_POWER_ON(phy);
1731 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
1732
1733 /* Considering 10ms timeout until BSpec is updated */
1734 if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
1735 DRM_ERROR("timeout during PHY%d power on\n", phy);
1736
1737 for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A);
1738 port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
1739 int lane;
1740
1741 for (lane = 0; lane < 4; lane++) {
1742 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
1743 /*
1744 * Note that on CHV this flag is called UPAR, but has
1745 * the same function.
1746 */
1747 val &= ~LATENCY_OPTIM;
1748 if (lane != 1)
1749 val |= LATENCY_OPTIM;
1750
1751 I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
1752 }
1753 }
1754
1755 /* Program PLL Rcomp code offset */
1756 val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
1757 val &= ~IREF0RC_OFFSET_MASK;
1758 val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
1759 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
1760
1761 val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
1762 val &= ~IREF1RC_OFFSET_MASK;
1763 val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
1764 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
1765
1766 /* Program power gating */
1767 val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
1768 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
1769 SUS_CLK_CONFIG;
1770 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
1771
1772 if (phy == DPIO_PHY0) {
1773 val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
1774 val |= DW6_OLDO_DYN_PWR_DOWN_EN;
1775 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
1776 }
1777
1778 val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
1779 val &= ~OCL2_LDOFUSE_PWR_DIS;
1780 /*
1781 * On PHY1 disable power on the second channel, since no port is
1782 * connected there. On PHY0 both channels have a port, so leave it
1783 * enabled.
1784 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
1785 * power down the second channel on PHY0 as well.
1786 */
1787 if (phy == DPIO_PHY1)
1788 val |= OCL2_LDOFUSE_PWR_DIS;
1789 I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
1790
1791 if (phy == DPIO_PHY0) {
1792 uint32_t grc_code;
1793 /*
1794 * PHY0 isn't connected to an RCOMP resistor so copy over
1795 * the corresponding calibrated value from PHY1, and disable
1796 * the automatic calibration on PHY0.
1797 */
1798 if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE,
1799 10))
1800 DRM_ERROR("timeout waiting for PHY1 GRC\n");
1801
1802 val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1));
1803 val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
1804 grc_code = val << GRC_CODE_FAST_SHIFT |
1805 val << GRC_CODE_SLOW_SHIFT |
1806 val;
1807 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
1808
1809 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
1810 val |= GRC_DIS | GRC_RDY_OVRD;
1811 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
1812 }
1813
1814 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
1815 val |= COMMON_RESET_DIS;
1816 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
1817}
1818
1819void broxton_ddi_phy_init(struct drm_device *dev)
1820{
1821 /* Enable PHY1 first since it provides Rcomp for PHY0 */
1822 broxton_phy_init(dev->dev_private, DPIO_PHY1);
1823 broxton_phy_init(dev->dev_private, DPIO_PHY0);
1824}
1825
1826static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
1827 enum dpio_phy phy)
1828{
1829 uint32_t val;
1830
1831 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
1832 val &= ~COMMON_RESET_DIS;
1833 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
1834}
1835
1836void broxton_ddi_phy_uninit(struct drm_device *dev)
1837{
1838 struct drm_i915_private *dev_priv = dev->dev_private;
1839
1840 broxton_phy_uninit(dev_priv, DPIO_PHY1);
1841 broxton_phy_uninit(dev_priv, DPIO_PHY0);
1842
1843 /* FIXME: do this in broxton_phy_uninit per phy */
1844 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0);
1845}
1846
ad64217b 1847void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
c19b0669 1848{
ad64217b
ACO		 1849 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1850 struct drm_i915_private *dev_priv =
1851 to_i915(intel_dig_port->base.base.dev);
174edf1f 1852 enum port port = intel_dig_port->port;
c19b0669 1853 uint32_t val;
f3e227df 1854 bool wait = false;
c19b0669
PZ		 1855
1856 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
1857 val = I915_READ(DDI_BUF_CTL(port));
1858 if (val & DDI_BUF_CTL_ENABLE) {
1859 val &= ~DDI_BUF_CTL_ENABLE;
1860 I915_WRITE(DDI_BUF_CTL(port), val);
1861 wait = true;
1862 }
1863
1864 val = I915_READ(DP_TP_CTL(port));
1865 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1866 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1867 I915_WRITE(DP_TP_CTL(port), val);
1868 POSTING_READ(DP_TP_CTL(port));
1869
1870 if (wait)
1871 intel_wait_ddi_buf_idle(dev_priv, port);
1872 }
1873
0e32b39c 1874 val = DP_TP_CTL_ENABLE |
c19b0669 1875 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
0e32b39c
DA		 1876 if (intel_dp->is_mst)
1877 val |= DP_TP_CTL_MODE_MST;
1878 else {
1879 val |= DP_TP_CTL_MODE_SST;
1880 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1881 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
1882 }
c19b0669
PZ		 1883 I915_WRITE(DP_TP_CTL(port), val);
1884 POSTING_READ(DP_TP_CTL(port));
1885
1886 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
1887 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
1888 POSTING_READ(DDI_BUF_CTL(port));
1889
1890 udelay(600);
1891}
00c09d70 1892
1ad960f2
PZ		 1893void intel_ddi_fdi_disable(struct drm_crtc *crtc)
1894{
1895 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1896 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1897 uint32_t val;
1898
1899 intel_ddi_post_disable(intel_encoder);
1900
eede3b53 1901 val = I915_READ(FDI_RX_CTL(PIPE_A));
1ad960f2 1902 val &= ~FDI_RX_ENABLE;
eede3b53 1903 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
1ad960f2 1904
eede3b53 1905 val = I915_READ(FDI_RX_MISC(PIPE_A));
1ad960f2
PZ		 1906 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1907 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
eede3b53 1908 I915_WRITE(FDI_RX_MISC(PIPE_A), val);
1ad960f2 1909
eede3b53 1910 val = I915_READ(FDI_RX_CTL(PIPE_A));
1ad960f2 1911 val &= ~FDI_PCDCLK;
eede3b53 1912 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
1ad960f2 1913
eede3b53 1914 val = I915_READ(FDI_RX_CTL(PIPE_A));
1ad960f2 1915 val &= ~FDI_RX_PLL_ENABLE;
eede3b53 1916 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
1ad960f2
PZ		 1917}
1918
3d52ccf5
LY		 1919bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
1920 struct intel_crtc *intel_crtc)
1921{
1922 u32 temp;
1923
e27daab4 1924 if (intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
3d52ccf5 1925 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
e27daab4
ID		 1926
1927 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
1928
3d52ccf5
LY		 1929 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
1930 return true;
1931 }
e27daab4 1932
3d52ccf5
LY		 1933 return false;
1934}
1935
6801c18c 1936void intel_ddi_get_config(struct intel_encoder *encoder,
5cec258b 1937 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 1938{
1939 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1940 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
0cb09a97 1941 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
bbd440fb 1942 struct intel_hdmi *intel_hdmi;
045ac3b5
JB		 1943 u32 temp, flags = 0;
1944
1945 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1946 if (temp & TRANS_DDI_PHSYNC)
1947 flags |= DRM_MODE_FLAG_PHSYNC;
1948 else
1949 flags |= DRM_MODE_FLAG_NHSYNC;
1950 if (temp & TRANS_DDI_PVSYNC)
1951 flags |= DRM_MODE_FLAG_PVSYNC;
1952 else
1953 flags |= DRM_MODE_FLAG_NVSYNC;
1954
2d112de7 1955 pipe_config->base.adjusted_mode.flags |= flags;
42571aef
VS		 1956
1957 switch (temp & TRANS_DDI_BPC_MASK) {
1958 case TRANS_DDI_BPC_6:
1959 pipe_config->pipe_bpp = 18;
1960 break;
1961 case TRANS_DDI_BPC_8:
1962 pipe_config->pipe_bpp = 24;
1963 break;
1964 case TRANS_DDI_BPC_10:
1965 pipe_config->pipe_bpp = 30;
1966 break;
1967 case TRANS_DDI_BPC_12:
1968 pipe_config->pipe_bpp = 36;
1969 break;
1970 default:
1971 break;
1972 }
eb14cb74
VS		 1973
1974 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
1975 case TRANS_DDI_MODE_SELECT_HDMI:
6897b4b5 1976 pipe_config->has_hdmi_sink = true;
bbd440fb
DV		 1977 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1978
cda0aaaf 1979 if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
bbd440fb 1980 pipe_config->has_infoframe = true;
cbc572a9 1981 break;
eb14cb74
VS		 1982 case TRANS_DDI_MODE_SELECT_DVI:
1983 case TRANS_DDI_MODE_SELECT_FDI:
1984 break;
1985 case TRANS_DDI_MODE_SELECT_DP_SST:
1986 case TRANS_DDI_MODE_SELECT_DP_MST:
1987 pipe_config->has_dp_encoder = true;
90a6b7b0
VS		 1988 pipe_config->lane_count =
1989 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
eb14cb74
VS		 1990 intel_dp_get_m_n(intel_crtc, pipe_config);
1991 break;
1992 default:
1993 break;
1994 }
10214420 1995
3d52ccf5
LY		 1996 pipe_config->has_audio =
1997 intel_ddi_is_audio_enabled(dev_priv, intel_crtc);
9ed109a7 1998
10214420
DV		 1999 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
2000 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2001 /*
2002 * This is a big fat ugly hack.
2003 *
2004 * Some machines in UEFI boot mode provide us a VBT that has 18
2005 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2006 * unknown we fail to light up. Yet the same BIOS boots up with
2007 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2008 * max, not what it tells us to use.
2009 *
2010 * Note: This will still be broken if the eDP panel is not lit
2011 * up by the BIOS, and thus we can't get the mode at module
2012 * load.
2013 */
2014 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2015 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2016 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2017 }
11578553 2018
22606a18 2019 intel_ddi_clock_get(encoder, pipe_config);
045ac3b5
JB		 2020}
2021
00c09d70
PZ		 2022static void intel_ddi_destroy(struct drm_encoder *encoder)
2023{
2024 /* HDMI has nothing special to destroy, so we can go with this. */
2025 intel_dp_encoder_destroy(encoder);
2026}
2027
5bfe2ac0 2028static bool intel_ddi_compute_config(struct intel_encoder *encoder,
5cec258b 2029 struct intel_crtc_state *pipe_config)
00c09d70 2030{
5bfe2ac0 2031 int type = encoder->type;
eccb140b 2032 int port = intel_ddi_get_encoder_port(encoder);
00c09d70 2033
5bfe2ac0 2034 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
00c09d70 2035
eccb140b
DV		 2036 if (port == PORT_A)
2037 pipe_config->cpu_transcoder = TRANSCODER_EDP;
2038
00c09d70 2039 if (type == INTEL_OUTPUT_HDMI)
5bfe2ac0 2040 return intel_hdmi_compute_config(encoder, pipe_config);
00c09d70 2041 else
5bfe2ac0 2042 return intel_dp_compute_config(encoder, pipe_config);
00c09d70
PZ		 2043}
2044
2045static const struct drm_encoder_funcs intel_ddi_funcs = {
2046 .destroy = intel_ddi_destroy,
2047};
2048
4a28ae58
PZ		 2049static struct intel_connector *
2050intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
2051{
2052 struct intel_connector *connector;
2053 enum port port = intel_dig_port->port;
2054
9bdbd0b9 2055 connector = intel_connector_alloc();
4a28ae58
PZ		 2056 if (!connector)
2057 return NULL;
2058
2059 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
2060 if (!intel_dp_init_connector(intel_dig_port, connector)) {
2061 kfree(connector);
2062 return NULL;
2063 }
2064
2065 return connector;
2066}
2067
2068static struct intel_connector *
2069intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
2070{
2071 struct intel_connector *connector;
2072 enum port port = intel_dig_port->port;
2073
9bdbd0b9 2074 connector = intel_connector_alloc();
4a28ae58
PZ		 2075 if (!connector)
2076 return NULL;
2077
2078 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
2079 intel_hdmi_init_connector(intel_dig_port, connector);
2080
2081 return connector;
2082}
2083
00c09d70
PZ		 2084void intel_ddi_init(struct drm_device *dev, enum port port)
2085{
876a8cdf 2086 struct drm_i915_private *dev_priv = dev->dev_private;
00c09d70
PZ		 2087 struct intel_digital_port *intel_dig_port;
2088 struct intel_encoder *intel_encoder;
2089 struct drm_encoder *encoder;
311a2094 2090 bool init_hdmi, init_dp;
10e7bec3
VS		 2091 int max_lanes;
2092
2093 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
2094 switch (port) {
2095 case PORT_A:
2096 max_lanes = 4;
2097 break;
2098 case PORT_E:
2099 max_lanes = 0;
2100 break;
2101 default:
2102 max_lanes = 4;
2103 break;
2104 }
2105 } else {
2106 switch (port) {
2107 case PORT_A:
2108 max_lanes = 2;
2109 break;
2110 case PORT_E:
2111 max_lanes = 2;
2112 break;
2113 default:
2114 max_lanes = 4;
2115 break;
2116 }
2117 }
311a2094
PZ		 2118
2119 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
2120 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
2121 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
2122 if (!init_dp && !init_hdmi) {
500ea70d 2123 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
311a2094 2124 port_name(port));
500ea70d 2125 return;
311a2094 2126 }
00c09d70 2127
b14c5679 2128 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
00c09d70
PZ		 2129 if (!intel_dig_port)
2130 return;
2131
00c09d70
PZ		 2132 intel_encoder = &intel_dig_port->base;
2133 encoder = &intel_encoder->base;
2134
2135 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
13a3d91f 2136 DRM_MODE_ENCODER_TMDS, NULL);
00c09d70 2137
5bfe2ac0 2138 intel_encoder->compute_config = intel_ddi_compute_config;
00c09d70
PZ		 2139 intel_encoder->enable = intel_enable_ddi;
2140 intel_encoder->pre_enable = intel_ddi_pre_enable;
2141 intel_encoder->disable = intel_disable_ddi;
2142 intel_encoder->post_disable = intel_ddi_post_disable;
2143 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
045ac3b5 2144 intel_encoder->get_config = intel_ddi_get_config;
00c09d70
PZ		 2145
2146 intel_dig_port->port = port;
bcf53de4
SM		 2147 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
2148 (DDI_BUF_PORT_REVERSAL |
2149 DDI_A_4_LANES);
00c09d70 2150
6c566dc9
MR		 2151 /*
2152 * Bspec says that DDI_A_4_LANES is the only supported configuration
2153 * for Broxton. Yet some BIOS fail to set this bit on port A if eDP
2154 * wasn't lit up at boot. Force this bit on in our internal
2155 * configuration so that we use the proper lane count for our
2156 * calculations.
2157 */
2158 if (IS_BROXTON(dev) && port == PORT_A) {
2159 if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
2160 DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
2161 intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
ed8d60f4 2162 max_lanes = 4;
6c566dc9
MR		 2163 }
2164 }
2165
ed8d60f4
MR		 2166 intel_dig_port->max_lanes = max_lanes;
2167
00c09d70 2168 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
f68d697e 2169 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
bc079e8b 2170 intel_encoder->cloneable = 0;
00c09d70 2171
f68d697e
CW		 2172 if (init_dp) {
2173 if (!intel_ddi_init_dp_connector(intel_dig_port))
2174 goto err;
13cf5504 2175
f68d697e 2176 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
cf1d5883
SJ		 2177 /*
2178 * On BXT A0/A1, sw needs to activate DDIA HPD logic and
2179 * interrupts to check the external panel connection.
2180 */
e87a005d 2181 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) && port == PORT_B)
cf1d5883
SJ		 2182 dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port;
2183 else
2184 dev_priv->hotplug.irq_port[port] = intel_dig_port;
f68d697e 2185 }
21a8e6a4 2186
311a2094
PZ		 2187 /* In theory we don't need the encoder->type check, but leave it just in
2188 * case we have some really bad VBTs... */
f68d697e
CW		 2189 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
2190 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
2191 goto err;
21a8e6a4 2192 }
f68d697e
CW		 2193
2194 return;
2195
2196err:
2197 drm_encoder_cleanup(encoder);
2198 kfree(intel_dig_port);
00c09d70 2199}
Linux kernel - Deliverables
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