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drm/i915/bxt: eDP low vswing support
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ddi.c
CommitLineData
45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include "i915_drv.h"
29#include "intel_drv.h"
30
10122051
JN		 31struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
f8896f5d 34 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
10122051
JN		 35};
36
45244b87
ED		 37/* HDMI/DVI modes ignore everything but the last 2 items. So we share
38 * them for both DP and FDI transports, allowing those ports to
39 * automatically adapt to HDMI connections as well
40 */
10122051 41static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
f8896f5d
DW		 42 { 0x00FFFFFF, 0x0006000E, 0x0 },
43 { 0x00D75FFF, 0x0005000A, 0x0 },
44 { 0x00C30FFF, 0x00040006, 0x0 },
45 { 0x80AAAFFF, 0x000B0000, 0x0 },
46 { 0x00FFFFFF, 0x0005000A, 0x0 },
47 { 0x00D75FFF, 0x000C0004, 0x0 },
48 { 0x80C30FFF, 0x000B0000, 0x0 },
49 { 0x00FFFFFF, 0x00040006, 0x0 },
50 { 0x80D75FFF, 0x000B0000, 0x0 },
45244b87
ED		 51};
52
10122051 53static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
f8896f5d
DW		 54 { 0x00FFFFFF, 0x0007000E, 0x0 },
55 { 0x00D75FFF, 0x000F000A, 0x0 },
56 { 0x00C30FFF, 0x00060006, 0x0 },
57 { 0x00AAAFFF, 0x001E0000, 0x0 },
58 { 0x00FFFFFF, 0x000F000A, 0x0 },
59 { 0x00D75FFF, 0x00160004, 0x0 },
60 { 0x00C30FFF, 0x001E0000, 0x0 },
61 { 0x00FFFFFF, 0x00060006, 0x0 },
62 { 0x00D75FFF, 0x001E0000, 0x0 },
6acab15a
PZ		 63};
64
10122051
JN		 65static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
66 /* Idx NT mV d T mV d db */
f8896f5d
DW		 67 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
68 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
69 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
70 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
71 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
72 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
73 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
74 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
75 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
76 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
77 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
78 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
45244b87
ED		 79};
80
10122051 81static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
f8896f5d
DW		 82 { 0x00FFFFFF, 0x00000012, 0x0 },
83 { 0x00EBAFFF, 0x00020011, 0x0 },
84 { 0x00C71FFF, 0x0006000F, 0x0 },
85 { 0x00AAAFFF, 0x000E000A, 0x0 },
86 { 0x00FFFFFF, 0x00020011, 0x0 },
87 { 0x00DB6FFF, 0x0005000F, 0x0 },
88 { 0x00BEEFFF, 0x000A000C, 0x0 },
89 { 0x00FFFFFF, 0x0005000F, 0x0 },
90 { 0x00DB6FFF, 0x000A000C, 0x0 },
300644c7
PZ		 91};
92
10122051 93static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
f8896f5d
DW		 94 { 0x00FFFFFF, 0x0007000E, 0x0 },
95 { 0x00D75FFF, 0x000E000A, 0x0 },
96 { 0x00BEFFFF, 0x00140006, 0x0 },
97 { 0x80B2CFFF, 0x001B0002, 0x0 },
98 { 0x00FFFFFF, 0x000E000A, 0x0 },
99 { 0x00DB6FFF, 0x00160005, 0x0 },
100 { 0x80C71FFF, 0x001A0002, 0x0 },
101 { 0x00F7DFFF, 0x00180004, 0x0 },
102 { 0x80D75FFF, 0x001B0002, 0x0 },
e58623cb
AR		 103};
104
10122051 105static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
f8896f5d
DW		 106 { 0x00FFFFFF, 0x0001000E, 0x0 },
107 { 0x00D75FFF, 0x0004000A, 0x0 },
108 { 0x00C30FFF, 0x00070006, 0x0 },
109 { 0x00AAAFFF, 0x000C0000, 0x0 },
110 { 0x00FFFFFF, 0x0004000A, 0x0 },
111 { 0x00D75FFF, 0x00090004, 0x0 },
112 { 0x00C30FFF, 0x000C0000, 0x0 },
113 { 0x00FFFFFF, 0x00070006, 0x0 },
114 { 0x00D75FFF, 0x000C0000, 0x0 },
e58623cb
AR		 115};
116
10122051
JN		 117static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
118 /* Idx NT mV d T mV df db */
f8896f5d
DW		 119 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
120 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
121 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
122 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
123 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
124 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
125 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
126 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
127 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
128 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
a26aa8ba
DL		 129};
130
5f8b2531 131/* Skylake H and S */
7f88e3af 132static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
f8896f5d
DW		 133 { 0x00002016, 0x000000A0, 0x0 },
134 { 0x00005012, 0x0000009B, 0x0 },
135 { 0x00007011, 0x00000088, 0x0 },
136 { 0x00009010, 0x000000C7, 0x0 },
137 { 0x00002016, 0x0000009B, 0x0 },
138 { 0x00005012, 0x00000088, 0x0 },
139 { 0x00007011, 0x000000C7, 0x0 },
140 { 0x00002016, 0x000000DF, 0x0 },
141 { 0x00005012, 0x000000C7, 0x0 },
7f88e3af
DL		 142};
143
f8896f5d
DW		 144/* Skylake U */
145static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
5f8b2531 146 { 0x0000201B, 0x000000A2, 0x0 },
f8896f5d
DW		 147 { 0x00005012, 0x00000088, 0x0 },
148 { 0x00007011, 0x00000087, 0x0 },
5f8b2531
RV		 149 { 0x80009010, 0x000000C7, 0x1 }, /* Uses I_boost level 0x1 */
150 { 0x0000201B, 0x0000009D, 0x0 },
f8896f5d
DW		 151 { 0x00005012, 0x000000C7, 0x0 },
152 { 0x00007011, 0x000000C7, 0x0 },
153 { 0x00002016, 0x00000088, 0x0 },
154 { 0x00005012, 0x000000C7, 0x0 },
155};
156
5f8b2531
RV		 157/* Skylake Y */
158static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
f8896f5d
DW		 159 { 0x00000018, 0x000000A2, 0x0 },
160 { 0x00005012, 0x00000088, 0x0 },
161 { 0x00007011, 0x00000087, 0x0 },
5f8b2531 162 { 0x80009010, 0x000000C7, 0x3 }, /* Uses I_boost level 0x3 */
f8896f5d
DW		 163 { 0x00000018, 0x0000009D, 0x0 },
164 { 0x00005012, 0x000000C7, 0x0 },
165 { 0x00007011, 0x000000C7, 0x0 },
166 { 0x00000018, 0x00000088, 0x0 },
167 { 0x00005012, 0x000000C7, 0x0 },
168};
169
170/*
5f8b2531 171 * Skylake H and S
f8896f5d
DW		 172 * eDP 1.4 low vswing translation parameters
173 */
7ad14a29 174static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
f8896f5d
DW		 175 { 0x00000018, 0x000000A8, 0x0 },
176 { 0x00004013, 0x000000A9, 0x0 },
177 { 0x00007011, 0x000000A2, 0x0 },
178 { 0x00009010, 0x0000009C, 0x0 },
179 { 0x00000018, 0x000000A9, 0x0 },
180 { 0x00006013, 0x000000A2, 0x0 },
181 { 0x00007011, 0x000000A6, 0x0 },
182 { 0x00000018, 0x000000AB, 0x0 },
183 { 0x00007013, 0x0000009F, 0x0 },
184 { 0x00000018, 0x000000DF, 0x0 },
185};
186
187/*
188 * Skylake U
189 * eDP 1.4 low vswing translation parameters
190 */
191static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
192 { 0x00000018, 0x000000A8, 0x0 },
193 { 0x00004013, 0x000000A9, 0x0 },
194 { 0x00007011, 0x000000A2, 0x0 },
195 { 0x00009010, 0x0000009C, 0x0 },
196 { 0x00000018, 0x000000A9, 0x0 },
197 { 0x00006013, 0x000000A2, 0x0 },
198 { 0x00007011, 0x000000A6, 0x0 },
199 { 0x00002016, 0x000000AB, 0x0 },
200 { 0x00005013, 0x0000009F, 0x0 },
201 { 0x00000018, 0x000000DF, 0x0 },
7ad14a29
SJ		 202};
203
f8896f5d 204/*
5f8b2531 205 * Skylake Y
f8896f5d
DW		 206 * eDP 1.4 low vswing translation parameters
207 */
5f8b2531 208static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
f8896f5d
DW		 209 { 0x00000018, 0x000000A8, 0x0 },
210 { 0x00004013, 0x000000AB, 0x0 },
211 { 0x00007011, 0x000000A4, 0x0 },
212 { 0x00009010, 0x000000DF, 0x0 },
213 { 0x00000018, 0x000000AA, 0x0 },
214 { 0x00006013, 0x000000A4, 0x0 },
215 { 0x00007011, 0x0000009D, 0x0 },
216 { 0x00000018, 0x000000A0, 0x0 },
217 { 0x00006012, 0x000000DF, 0x0 },
218 { 0x00000018, 0x0000008A, 0x0 },
219};
7ad14a29 220
5f8b2531 221/* Skylake U, H and S */
7f88e3af 222static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
f8896f5d
DW		 223 { 0x00000018, 0x000000AC, 0x0 },
224 { 0x00005012, 0x0000009D, 0x0 },
225 { 0x00007011, 0x00000088, 0x0 },
226 { 0x00000018, 0x000000A1, 0x0 },
227 { 0x00000018, 0x00000098, 0x0 },
228 { 0x00004013, 0x00000088, 0x0 },
229 { 0x00006012, 0x00000087, 0x0 },
230 { 0x00000018, 0x000000DF, 0x0 },
231 { 0x00003015, 0x00000087, 0x0 }, /* Default */
232 { 0x00003015, 0x000000C7, 0x0 },
233 { 0x00000018, 0x000000C7, 0x0 },
234};
235
5f8b2531
RV		 236/* Skylake Y */
237static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
f8896f5d
DW		 238 { 0x00000018, 0x000000A1, 0x0 },
239 { 0x00005012, 0x000000DF, 0x0 },
240 { 0x00007011, 0x00000084, 0x0 },
241 { 0x00000018, 0x000000A4, 0x0 },
242 { 0x00000018, 0x0000009D, 0x0 },
243 { 0x00004013, 0x00000080, 0x0 },
244 { 0x00006013, 0x000000C7, 0x0 },
245 { 0x00000018, 0x0000008A, 0x0 },
246 { 0x00003015, 0x000000C7, 0x0 }, /* Default */
5f8b2531 247 { 0x80003015, 0x000000C7, 0x7 }, /* Uses I_boost level 0x7 */
f8896f5d 248 { 0x00000018, 0x000000C7, 0x0 },
7f88e3af
DL		 249};
250
96fb9f9b
VK		 251struct bxt_ddi_buf_trans {
252 u32 margin; /* swing value */
253 u32 scale; /* scale value */
254 u32 enable; /* scale enable */
255 u32 deemphasis;
256 bool default_index; /* true if the entry represents default value */
257};
258
96fb9f9b
VK		 259static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
260 /* Idx NT mV diff db */
fe4c63c8
ID		 261 { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */
262 { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
263 { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */
264 { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
265 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
266 { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
267 { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */
268 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
269 { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
f8896f5d 270 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
96fb9f9b
VK		 271};
272
d9d7000d
SJ		 273static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
274 /* Idx NT mV diff db */
275 { 26, 0, 0, 128, false }, /* 0: 200 0 */
276 { 38, 0, 0, 112, false }, /* 1: 200 1.5 */
277 { 48, 0, 0, 96, false }, /* 2: 200 4 */
278 { 54, 0, 0, 69, false }, /* 3: 200 6 */
279 { 32, 0, 0, 128, false }, /* 4: 250 0 */
280 { 48, 0, 0, 104, false }, /* 5: 250 1.5 */
281 { 54, 0, 0, 85, false }, /* 6: 250 4 */
282 { 43, 0, 0, 128, false }, /* 7: 300 0 */
283 { 54, 0, 0, 101, false }, /* 8: 300 1.5 */
284 { 48, 0, 0, 128, false }, /* 9: 300 0 */
285};
286
96fb9f9b
VK		 287/* BSpec has 2 recommended values - entries 0 and 8.
288 * Using the entry with higher vswing.
289 */
290static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
291 /* Idx NT mV diff db */
fe4c63c8
ID		 292 { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */
293 { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
294 { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */
295 { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
296 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
297 { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
298 { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */
299 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
300 { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
96fb9f9b
VK		 301 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
302};
303
f8896f5d
DW		 304static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
305 enum port port, int type);
306
a1e6ad66
ID		 307static void ddi_get_encoder_port(struct intel_encoder *intel_encoder,
308 struct intel_digital_port **dig_port,
309 enum port *port)
fc914639 310{
0bdee30e 311 struct drm_encoder *encoder = &intel_encoder->base;
fc914639
PZ		 312 int type = intel_encoder->type;
313
0e32b39c 314 if (type == INTEL_OUTPUT_DP_MST) {
a1e6ad66
ID		 315 *dig_port = enc_to_mst(encoder)->primary;
316 *port = (*dig_port)->port;
0e32b39c 317 } else if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
00c09d70 318 type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
a1e6ad66
ID		 319 *dig_port = enc_to_dig_port(encoder);
320 *port = (*dig_port)->port;
fc914639 321 } else if (type == INTEL_OUTPUT_ANALOG) {
a1e6ad66
ID		 322 *dig_port = NULL;
323 *port = PORT_E;
fc914639
PZ		 324 } else {
325 DRM_ERROR("Invalid DDI encoder type %d\n", type);
326 BUG();
327 }
328}
329
a1e6ad66
ID		 330enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
331{
332 struct intel_digital_port *dig_port;
333 enum port port;
334
335 ddi_get_encoder_port(intel_encoder, &dig_port, &port);
336
337 return port;
338}
339
ce3b7e9b
DL		 340static bool
341intel_dig_port_supports_hdmi(const struct intel_digital_port *intel_dig_port)
342{
343 return intel_dig_port->hdmi.hdmi_reg;
344}
345
f8896f5d
DW		 346static const struct ddi_buf_trans *skl_get_buf_trans_dp(struct drm_device *dev,
347 int *n_entries)
348{
f8896f5d 349 const struct ddi_buf_trans *ddi_translations;
f8896f5d 350
5f8b2531
RV		 351 if (IS_SKL_ULX(dev)) {
352 ddi_translations = skl_y_ddi_translations_dp;
353 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
f8896f5d
DW		 354 } else if (IS_SKL_ULT(dev)) {
355 ddi_translations = skl_u_ddi_translations_dp;
356 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
357 } else {
358 ddi_translations = skl_ddi_translations_dp;
359 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
360 }
361
362 return ddi_translations;
363}
364
365static const struct ddi_buf_trans *skl_get_buf_trans_edp(struct drm_device *dev,
366 int *n_entries)
367{
368 struct drm_i915_private *dev_priv = dev->dev_private;
369 const struct ddi_buf_trans *ddi_translations;
f8896f5d 370
5f8b2531 371 if (IS_SKL_ULX(dev)) {
f8896f5d 372 if (dev_priv->edp_low_vswing) {
5f8b2531
RV		 373 ddi_translations = skl_y_ddi_translations_edp;
374 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
f8896f5d 375 } else {
5f8b2531
RV		 376 ddi_translations = skl_y_ddi_translations_dp;
377 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
f8896f5d
DW		 378 }
379 } else if (IS_SKL_ULT(dev)) {
380 if (dev_priv->edp_low_vswing) {
381 ddi_translations = skl_u_ddi_translations_edp;
382 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
383 } else {
384 ddi_translations = skl_u_ddi_translations_dp;
385 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
386 }
387 } else {
388 if (dev_priv->edp_low_vswing) {
389 ddi_translations = skl_ddi_translations_edp;
390 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
391 } else {
392 ddi_translations = skl_ddi_translations_dp;
393 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
394 }
395 }
396
397 return ddi_translations;
398}
399
400static const struct ddi_buf_trans *
401skl_get_buf_trans_hdmi(struct drm_device *dev,
402 int *n_entries)
403{
f8896f5d 404 const struct ddi_buf_trans *ddi_translations;
f8896f5d 405
5f8b2531
RV		 406 if (IS_SKL_ULX(dev)) {
407 ddi_translations = skl_y_ddi_translations_hdmi;
408 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
f8896f5d
DW		 409 } else {
410 ddi_translations = skl_ddi_translations_hdmi;
411 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
412 }
413
414 return ddi_translations;
415}
416
e58623cb
AR		 417/*
418 * Starting with Haswell, DDI port buffers must be programmed with correct
419 * values in advance. The buffer values are different for FDI and DP modes,
45244b87
ED		 420 * but the HDMI/DVI fields are shared among those. So we program the DDI
421 * in either FDI or DP modes only, as HDMI connections will work with both
422 * of those
423 */
faa0cdbe
ID		 424static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port,
425 bool supports_hdmi)
45244b87
ED		 426{
427 struct drm_i915_private *dev_priv = dev->dev_private;
75067dde 428 u32 iboost_bit = 0;
7ff44670 429 int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry,
7ad14a29 430 size;
6acab15a 431 int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
10122051
JN		 432 const struct ddi_buf_trans *ddi_translations_fdi;
433 const struct ddi_buf_trans *ddi_translations_dp;
434 const struct ddi_buf_trans *ddi_translations_edp;
435 const struct ddi_buf_trans *ddi_translations_hdmi;
436 const struct ddi_buf_trans *ddi_translations;
e58623cb 437
96fb9f9b 438 if (IS_BROXTON(dev)) {
faa0cdbe 439 if (!supports_hdmi)
96fb9f9b
VK		 440 return;
441
442 /* Vswing programming for HDMI */
443 bxt_ddi_vswing_sequence(dev, hdmi_level, port,
444 INTEL_OUTPUT_HDMI);
445 return;
446 } else if (IS_SKYLAKE(dev)) {
c30400fc 447 ddi_translations_fdi = NULL;
f8896f5d
DW		 448 ddi_translations_dp =
449 skl_get_buf_trans_dp(dev, &n_dp_entries);
450 ddi_translations_edp =
451 skl_get_buf_trans_edp(dev, &n_edp_entries);
452 ddi_translations_hdmi =
453 skl_get_buf_trans_hdmi(dev, &n_hdmi_entries);
454 hdmi_default_entry = 8;
75067dde
AK		 455 /* If we're boosting the current, set bit 31 of trans1 */
456 if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level ||
457 dev_priv->vbt.ddi_port_info[port].dp_boost_level)
458 iboost_bit = 1<<31;
7f88e3af 459 } else if (IS_BROADWELL(dev)) {
e58623cb
AR		 460 ddi_translations_fdi = bdw_ddi_translations_fdi;
461 ddi_translations_dp = bdw_ddi_translations_dp;
300644c7 462 ddi_translations_edp = bdw_ddi_translations_edp;
a26aa8ba 463 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
7ad14a29
SJ		 464 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
465 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 466 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
7ff44670 467 hdmi_default_entry = 7;
e58623cb
AR		 468 } else if (IS_HASWELL(dev)) {
469 ddi_translations_fdi = hsw_ddi_translations_fdi;
470 ddi_translations_dp = hsw_ddi_translations_dp;
300644c7 471 ddi_translations_edp = hsw_ddi_translations_dp;
a26aa8ba 472 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
7ad14a29 473 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
10122051 474 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
7ff44670 475 hdmi_default_entry = 6;
e58623cb
AR		 476 } else {
477 WARN(1, "ddi translation table missing\n");
300644c7 478 ddi_translations_edp = bdw_ddi_translations_dp;
e58623cb
AR		 479 ddi_translations_fdi = bdw_ddi_translations_fdi;
480 ddi_translations_dp = bdw_ddi_translations_dp;
a26aa8ba 481 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
7ad14a29
SJ		 482 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
483 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 484 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
7ff44670 485 hdmi_default_entry = 7;
e58623cb
AR		 486 }
487
300644c7
PZ		 488 switch (port) {
489 case PORT_A:
490 ddi_translations = ddi_translations_edp;
7ad14a29 491 size = n_edp_entries;
300644c7
PZ		 492 break;
493 case PORT_B:
494 case PORT_C:
300644c7 495 ddi_translations = ddi_translations_dp;
7ad14a29 496 size = n_dp_entries;
300644c7 497 break;
77d8d009 498 case PORT_D:
7ad14a29 499 if (intel_dp_is_edp(dev, PORT_D)) {
77d8d009 500 ddi_translations = ddi_translations_edp;
7ad14a29
SJ		 501 size = n_edp_entries;
502 } else {
77d8d009 503 ddi_translations = ddi_translations_dp;
7ad14a29
SJ		 504 size = n_dp_entries;
505 }
77d8d009 506 break;
300644c7 507 case PORT_E:
7f88e3af
DL		 508 if (ddi_translations_fdi)
509 ddi_translations = ddi_translations_fdi;
510 else
511 ddi_translations = ddi_translations_dp;
7ad14a29 512 size = n_dp_entries;
300644c7
PZ		 513 break;
514 default:
515 BUG();
516 }
45244b87 517
9712e688
VS		 518 for (i = 0; i < size; i++) {
519 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
520 ddi_translations[i].trans1 | iboost_bit);
521 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
522 ddi_translations[i].trans2);
45244b87 523 }
ce4dd49e 524
faa0cdbe 525 if (!supports_hdmi)
ce3b7e9b
DL		 526 return;
527
ce4dd49e
DL		 528 /* Choose a good default if VBT is badly populated */
529 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
530 hdmi_level >= n_hdmi_entries)
7ff44670 531 hdmi_level = hdmi_default_entry;
ce4dd49e 532
6acab15a 533 /* Entry 9 is for HDMI: */
9712e688
VS		 534 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
535 ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
536 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
537 ddi_translations_hdmi[hdmi_level].trans2);
45244b87
ED		 538}
539
540/* Program DDI buffers translations for DP. By default, program ports A-D in DP
541 * mode and port E for FDI.
542 */
543void intel_prepare_ddi(struct drm_device *dev)
544{
faa0cdbe 545 struct intel_encoder *intel_encoder;
b403745c 546 bool visited[I915_MAX_PORTS] = { 0, };
45244b87 547
0d536cb4
PZ		 548 if (!HAS_DDI(dev))
549 return;
45244b87 550
faa0cdbe
ID		 551 for_each_intel_encoder(dev, intel_encoder) {
552 struct intel_digital_port *intel_dig_port;
553 enum port port;
554 bool supports_hdmi;
555
556 ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
557
558 if (visited[port])
b403745c
DL		 559 continue;
560
faa0cdbe
ID		 561 supports_hdmi = intel_dig_port &&
562 intel_dig_port_supports_hdmi(intel_dig_port);
563
564 intel_prepare_ddi_buffers(dev, port, supports_hdmi);
565 visited[port] = true;
b403745c 566 }
45244b87 567}
c82e4d26 568
248138b5
PZ		 569static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
570 enum port port)
571{
572 uint32_t reg = DDI_BUF_CTL(port);
573 int i;
574
3449ca85 575 for (i = 0; i < 16; i++) {
248138b5
PZ		 576 udelay(1);
577 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
578 return;
579 }
580 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
581}
c82e4d26
ED		 582
583/* Starting with Haswell, different DDI ports can work in FDI mode for
584 * connection to the PCH-located connectors. For this, it is necessary to train
585 * both the DDI port and PCH receiver for the desired DDI buffer settings.
586 *
587 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
588 * please note that when FDI mode is active on DDI E, it shares 2 lines with
589 * DDI A (which is used for eDP)
590 */
591
592void hsw_fdi_link_train(struct drm_crtc *crtc)
593{
594 struct drm_device *dev = crtc->dev;
595 struct drm_i915_private *dev_priv = dev->dev_private;
596 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
04945641 597 u32 temp, i, rx_ctl_val;
c82e4d26 598
04945641
PZ		 599 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
600 * mode set "sequence for CRT port" document:
601 * - TP1 to TP2 time with the default value
602 * - FDI delay to 90h
8693a824
DL		 603 *
604 * WaFDIAutoLinkSetTimingOverrride:hsw
04945641
PZ		 605 */
606 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
607 FDI_RX_PWRDN_LANE0_VAL(2) |
608 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
609
610 /* Enable the PCH Receiver FDI PLL */
3e68320e 611 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
33d29b14 612 FDI_RX_PLL_ENABLE |
6e3c9717 613 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
04945641
PZ		 614 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
615 POSTING_READ(_FDI_RXA_CTL);
616 udelay(220);
617
618 /* Switch from Rawclk to PCDclk */
619 rx_ctl_val |= FDI_PCDCLK;
620 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
621
622 /* Configure Port Clock Select */
6e3c9717
ACO		 623 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
624 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
04945641
PZ		 625
626 /* Start the training iterating through available voltages and emphasis,
627 * testing each value twice. */
10122051 628 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
c82e4d26
ED		 629 /* Configure DP_TP_CTL with auto-training */
630 I915_WRITE(DP_TP_CTL(PORT_E),
631 DP_TP_CTL_FDI_AUTOTRAIN |
632 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
633 DP_TP_CTL_LINK_TRAIN_PAT1 |
634 DP_TP_CTL_ENABLE);
635
876a8cdf
DL		 636 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
637 * DDI E does not support port reversal, the functionality is
638 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
639 * port reversal bit */
c82e4d26 640 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641 641 DDI_BUF_CTL_ENABLE |
6e3c9717 642 ((intel_crtc->config->fdi_lanes - 1) << 1) |
c5fe6a06 643 DDI_BUF_TRANS_SELECT(i / 2));
04945641 644 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 645
646 udelay(600);
647
04945641
PZ		 648 /* Program PCH FDI Receiver TU */
649 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
650
651 /* Enable PCH FDI Receiver with auto-training */
652 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
653 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
654 POSTING_READ(_FDI_RXA_CTL);
655
656 /* Wait for FDI receiver lane calibration */
657 udelay(30);
658
659 /* Unset FDI_RX_MISC pwrdn lanes */
660 temp = I915_READ(_FDI_RXA_MISC);
661 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
662 I915_WRITE(_FDI_RXA_MISC, temp);
663 POSTING_READ(_FDI_RXA_MISC);
664
665 /* Wait for FDI auto training time */
666 udelay(5);
c82e4d26
ED		 667
668 temp = I915_READ(DP_TP_STATUS(PORT_E));
669 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 670 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
c82e4d26
ED		 671
672 /* Enable normal pixel sending for FDI */
673 I915_WRITE(DP_TP_CTL(PORT_E),
04945641
PZ		 674 DP_TP_CTL_FDI_AUTOTRAIN |
675 DP_TP_CTL_LINK_TRAIN_NORMAL |
676 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
677 DP_TP_CTL_ENABLE);
c82e4d26 678
04945641 679 return;
c82e4d26 680 }
04945641 681
248138b5
PZ		 682 temp = I915_READ(DDI_BUF_CTL(PORT_E));
683 temp &= ~DDI_BUF_CTL_ENABLE;
684 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
685 POSTING_READ(DDI_BUF_CTL(PORT_E));
686
04945641 687 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
248138b5
PZ		 688 temp = I915_READ(DP_TP_CTL(PORT_E));
689 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
690 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
691 I915_WRITE(DP_TP_CTL(PORT_E), temp);
692 POSTING_READ(DP_TP_CTL(PORT_E));
693
694 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
04945641
PZ		 695
696 rx_ctl_val &= ~FDI_RX_ENABLE;
697 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
248138b5 698 POSTING_READ(_FDI_RXA_CTL);
04945641
PZ		 699
700 /* Reset FDI_RX_MISC pwrdn lanes */
701 temp = I915_READ(_FDI_RXA_MISC);
702 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
703 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
704 I915_WRITE(_FDI_RXA_MISC, temp);
248138b5 705 POSTING_READ(_FDI_RXA_MISC);
c82e4d26
ED		 706 }
707
04945641 708 DRM_ERROR("FDI link training failed!\n");
c82e4d26 709}
0e72a5b5 710
44905a27
DA		 711void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
712{
713 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
714 struct intel_digital_port *intel_dig_port =
715 enc_to_dig_port(&encoder->base);
716
717 intel_dp->DP = intel_dig_port->saved_port_bits |
c5fe6a06 718 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
901c2daf 719 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
44905a27
DA		 720}
721
8d9ddbcb
PZ		 722static struct intel_encoder *
723intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
724{
725 struct drm_device *dev = crtc->dev;
726 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
727 struct intel_encoder *intel_encoder, *ret = NULL;
728 int num_encoders = 0;
729
730 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
731 ret = intel_encoder;
732 num_encoders++;
733 }
734
735 if (num_encoders != 1)
84f44ce7
VS		 736 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
737 pipe_name(intel_crtc->pipe));
8d9ddbcb
PZ		 738
739 BUG_ON(ret == NULL);
740 return ret;
741}
742
bcddf610 743struct intel_encoder *
3165c074 744intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
d0737e1d 745{
3165c074
ACO		 746 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
747 struct intel_encoder *ret = NULL;
748 struct drm_atomic_state *state;
da3ced29
ACO		 749 struct drm_connector *connector;
750 struct drm_connector_state *connector_state;
d0737e1d 751 int num_encoders = 0;
3165c074 752 int i;
d0737e1d 753
3165c074
ACO		 754 state = crtc_state->base.state;
755
da3ced29
ACO		 756 for_each_connector_in_state(state, connector, connector_state, i) {
757 if (connector_state->crtc != crtc_state->base.crtc)
3165c074
ACO		 758 continue;
759
da3ced29 760 ret = to_intel_encoder(connector_state->best_encoder);
3165c074 761 num_encoders++;
d0737e1d
ACO		 762 }
763
764 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
765 pipe_name(crtc->pipe));
766
767 BUG_ON(ret == NULL);
768 return ret;
769}
770
1c0b85c5 771#define LC_FREQ 2700
27893390 772#define LC_FREQ_2K U64_C(LC_FREQ * 2000)
1c0b85c5
DL		 773
774#define P_MIN 2
775#define P_MAX 64
776#define P_INC 2
777
778/* Constraints for PLL good behavior */
779#define REF_MIN 48
780#define REF_MAX 400
781#define VCO_MIN 2400
782#define VCO_MAX 4800
783
27893390
DL		 784#define abs_diff(a, b) ({ \
785 typeof(a) __a = (a); \
786 typeof(b) __b = (b); \
787 (void) (&__a == &__b); \
788 __a > __b ? (__a - __b) : (__b - __a); })
1c0b85c5 789
63582983 790struct hsw_wrpll_rnp {
1c0b85c5
DL		 791 unsigned p, n2, r2;
792};
793
63582983 794static unsigned hsw_wrpll_get_budget_for_freq(int clock)
6441ab5f 795{
1c0b85c5
DL		 796 unsigned budget;
797
798 switch (clock) {
799 case 25175000:
800 case 25200000:
801 case 27000000:
802 case 27027000:
803 case 37762500:
804 case 37800000:
805 case 40500000:
806 case 40541000:
807 case 54000000:
808 case 54054000:
809 case 59341000:
810 case 59400000:
811 case 72000000:
812 case 74176000:
813 case 74250000:
814 case 81000000:
815 case 81081000:
816 case 89012000:
817 case 89100000:
818 case 108000000:
819 case 108108000:
820 case 111264000:
821 case 111375000:
822 case 148352000:
823 case 148500000:
824 case 162000000:
825 case 162162000:
826 case 222525000:
827 case 222750000:
828 case 296703000:
829 case 297000000:
830 budget = 0;
831 break;
832 case 233500000:
833 case 245250000:
834 case 247750000:
835 case 253250000:
836 case 298000000:
837 budget = 1500;
838 break;
839 case 169128000:
840 case 169500000:
841 case 179500000:
842 case 202000000:
843 budget = 2000;
844 break;
845 case 256250000:
846 case 262500000:
847 case 270000000:
848 case 272500000:
849 case 273750000:
850 case 280750000:
851 case 281250000:
852 case 286000000:
853 case 291750000:
854 budget = 4000;
855 break;
856 case 267250000:
857 case 268500000:
858 budget = 5000;
859 break;
860 default:
861 budget = 1000;
862 break;
863 }
6441ab5f 864
1c0b85c5
DL		 865 return budget;
866}
867
63582983
DL		 868static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget,
869 unsigned r2, unsigned n2, unsigned p,
870 struct hsw_wrpll_rnp *best)
1c0b85c5
DL		 871{
872 uint64_t a, b, c, d, diff, diff_best;
6441ab5f 873
1c0b85c5
DL		 874 /* No best (r,n,p) yet */
875 if (best->p == 0) {
876 best->p = p;
877 best->n2 = n2;
878 best->r2 = r2;
879 return;
880 }
6441ab5f 881
1c0b85c5
DL		 882 /*
883 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
884 * freq2k.
885 *
886 * delta = 1e6 *
887 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
888 * freq2k;
889 *
890 * and we would like delta <= budget.
891 *
892 * If the discrepancy is above the PPM-based budget, always prefer to
893 * improve upon the previous solution. However, if you're within the
894 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
895 */
896 a = freq2k * budget * p * r2;
897 b = freq2k * budget * best->p * best->r2;
27893390
DL		 898 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
899 diff_best = abs_diff(freq2k * best->p * best->r2,
900 LC_FREQ_2K * best->n2);
1c0b85c5
DL		 901 c = 1000000 * diff;
902 d = 1000000 * diff_best;
903
904 if (a < c && b < d) {
905 /* If both are above the budget, pick the closer */
906 if (best->p * best->r2 * diff < p * r2 * diff_best) {
907 best->p = p;
908 best->n2 = n2;
909 best->r2 = r2;
910 }
911 } else if (a >= c && b < d) {
912 /* If A is below the threshold but B is above it? Update. */
913 best->p = p;
914 best->n2 = n2;
915 best->r2 = r2;
916 } else if (a >= c && b >= d) {
917 /* Both are below the limit, so pick the higher n2/(r2*r2) */
918 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
919 best->p = p;
920 best->n2 = n2;
921 best->r2 = r2;
922 }
923 }
924 /* Otherwise a < c && b >= d, do nothing */
925}
926
63582983 927static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, int reg)
11578553
JB		 928{
929 int refclk = LC_FREQ;
930 int n, p, r;
931 u32 wrpll;
932
933 wrpll = I915_READ(reg);
114fe488
DV		 934 switch (wrpll & WRPLL_PLL_REF_MASK) {
935 case WRPLL_PLL_SSC:
936 case WRPLL_PLL_NON_SSC:
11578553
JB		 937 /*
938 * We could calculate spread here, but our checking
939 * code only cares about 5% accuracy, and spread is a max of
940 * 0.5% downspread.
941 */
942 refclk = 135;
943 break;
114fe488 944 case WRPLL_PLL_LCPLL:
11578553
JB		 945 refclk = LC_FREQ;
946 break;
947 default:
948 WARN(1, "bad wrpll refclk\n");
949 return 0;
950 }
951
952 r = wrpll & WRPLL_DIVIDER_REF_MASK;
953 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
954 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
955
20f0ec16
JB		 956 /* Convert to KHz, p & r have a fixed point portion */
957 return (refclk * n * 100) / (p * r);
11578553
JB		 958}
959
540e732c
S		 960static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
961 uint32_t dpll)
962{
963 uint32_t cfgcr1_reg, cfgcr2_reg;
964 uint32_t cfgcr1_val, cfgcr2_val;
965 uint32_t p0, p1, p2, dco_freq;
966
967 cfgcr1_reg = GET_CFG_CR1_REG(dpll);
968 cfgcr2_reg = GET_CFG_CR2_REG(dpll);
969
970 cfgcr1_val = I915_READ(cfgcr1_reg);
971 cfgcr2_val = I915_READ(cfgcr2_reg);
972
973 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
974 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
975
976 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
977 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
978 else
979 p1 = 1;
980
981
982 switch (p0) {
983 case DPLL_CFGCR2_PDIV_1:
984 p0 = 1;
985 break;
986 case DPLL_CFGCR2_PDIV_2:
987 p0 = 2;
988 break;
989 case DPLL_CFGCR2_PDIV_3:
990 p0 = 3;
991 break;
992 case DPLL_CFGCR2_PDIV_7:
993 p0 = 7;
994 break;
995 }
996
997 switch (p2) {
998 case DPLL_CFGCR2_KDIV_5:
999 p2 = 5;
1000 break;
1001 case DPLL_CFGCR2_KDIV_2:
1002 p2 = 2;
1003 break;
1004 case DPLL_CFGCR2_KDIV_3:
1005 p2 = 3;
1006 break;
1007 case DPLL_CFGCR2_KDIV_1:
1008 p2 = 1;
1009 break;
1010 }
1011
1012 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
1013
1014 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
1015 1000) / 0x8000;
1016
1017 return dco_freq / (p0 * p1 * p2 * 5);
1018}
1019
398a017e
VS		 1020static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1021{
1022 int dotclock;
1023
1024 if (pipe_config->has_pch_encoder)
1025 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1026 &pipe_config->fdi_m_n);
1027 else if (pipe_config->has_dp_encoder)
1028 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1029 &pipe_config->dp_m_n);
1030 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1031 dotclock = pipe_config->port_clock * 2 / 3;
1032 else
1033 dotclock = pipe_config->port_clock;
1034
1035 if (pipe_config->pixel_multiplier)
1036 dotclock /= pipe_config->pixel_multiplier;
1037
1038 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1039}
540e732c
S		 1040
1041static void skl_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1042 struct intel_crtc_state *pipe_config)
540e732c
S		 1043{
1044 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
540e732c
S		 1045 int link_clock = 0;
1046 uint32_t dpll_ctl1, dpll;
1047
134ffa44 1048 dpll = pipe_config->ddi_pll_sel;
540e732c
S		 1049
1050 dpll_ctl1 = I915_READ(DPLL_CTRL1);
1051
1052 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
1053 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
1054 } else {
71cd8423
DL		 1055 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
1056 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
540e732c
S		 1057
1058 switch (link_clock) {
71cd8423 1059 case DPLL_CTRL1_LINK_RATE_810:
540e732c
S		 1060 link_clock = 81000;
1061 break;
71cd8423 1062 case DPLL_CTRL1_LINK_RATE_1080:
a8f3ef61
SJ		 1063 link_clock = 108000;
1064 break;
71cd8423 1065 case DPLL_CTRL1_LINK_RATE_1350:
540e732c
S		 1066 link_clock = 135000;
1067 break;
71cd8423 1068 case DPLL_CTRL1_LINK_RATE_1620:
a8f3ef61
SJ		 1069 link_clock = 162000;
1070 break;
71cd8423 1071 case DPLL_CTRL1_LINK_RATE_2160:
a8f3ef61
SJ		 1072 link_clock = 216000;
1073 break;
71cd8423 1074 case DPLL_CTRL1_LINK_RATE_2700:
540e732c
S		 1075 link_clock = 270000;
1076 break;
1077 default:
1078 WARN(1, "Unsupported link rate\n");
1079 break;
1080 }
1081 link_clock *= 2;
1082 }
1083
1084 pipe_config->port_clock = link_clock;
1085
398a017e 1086 ddi_dotclock_get(pipe_config);
540e732c
S		 1087}
1088
3d51278a 1089static void hsw_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1090 struct intel_crtc_state *pipe_config)
11578553
JB		 1091{
1092 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
11578553
JB		 1093 int link_clock = 0;
1094 u32 val, pll;
1095
26804afd 1096 val = pipe_config->ddi_pll_sel;
11578553
JB		 1097 switch (val & PORT_CLK_SEL_MASK) {
1098 case PORT_CLK_SEL_LCPLL_810:
1099 link_clock = 81000;
1100 break;
1101 case PORT_CLK_SEL_LCPLL_1350:
1102 link_clock = 135000;
1103 break;
1104 case PORT_CLK_SEL_LCPLL_2700:
1105 link_clock = 270000;
1106 break;
1107 case PORT_CLK_SEL_WRPLL1:
63582983 1108 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
11578553
JB		 1109 break;
1110 case PORT_CLK_SEL_WRPLL2:
63582983 1111 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
11578553
JB		 1112 break;
1113 case PORT_CLK_SEL_SPLL:
1114 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1115 if (pll == SPLL_PLL_FREQ_810MHz)
1116 link_clock = 81000;
1117 else if (pll == SPLL_PLL_FREQ_1350MHz)
1118 link_clock = 135000;
1119 else if (pll == SPLL_PLL_FREQ_2700MHz)
1120 link_clock = 270000;
1121 else {
1122 WARN(1, "bad spll freq\n");
1123 return;
1124 }
1125 break;
1126 default:
1127 WARN(1, "bad port clock sel\n");
1128 return;
1129 }
1130
1131 pipe_config->port_clock = link_clock * 2;
1132
398a017e 1133 ddi_dotclock_get(pipe_config);
11578553
JB		 1134}
1135
977bb38d
S		 1136static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
1137 enum intel_dpll_id dpll)
1138{
aa610dcb
ID		 1139 struct intel_shared_dpll *pll;
1140 struct intel_dpll_hw_state *state;
1141 intel_clock_t clock;
1142
1143 /* For DDI ports we always use a shared PLL. */
1144 if (WARN_ON(dpll == DPLL_ID_PRIVATE))
1145 return 0;
1146
1147 pll = &dev_priv->shared_dplls[dpll];
1148 state = &pll->config.hw_state;
1149
1150 clock.m1 = 2;
1151 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1152 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1153 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1154 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1155 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1156 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1157
1158 return chv_calc_dpll_params(100000, &clock);
977bb38d
S		 1159}
1160
1161static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1162 struct intel_crtc_state *pipe_config)
1163{
1164 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1165 enum port port = intel_ddi_get_encoder_port(encoder);
1166 uint32_t dpll = port;
1167
398a017e 1168 pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);
977bb38d 1169
398a017e 1170 ddi_dotclock_get(pipe_config);
977bb38d
S		 1171}
1172
3d51278a 1173void intel_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1174 struct intel_crtc_state *pipe_config)
3d51278a 1175{
22606a18
DL		 1176 struct drm_device *dev = encoder->base.dev;
1177
1178 if (INTEL_INFO(dev)->gen <= 8)
1179 hsw_ddi_clock_get(encoder, pipe_config);
977bb38d 1180 else if (IS_SKYLAKE(dev))
22606a18 1181 skl_ddi_clock_get(encoder, pipe_config);
977bb38d
S		 1182 else if (IS_BROXTON(dev))
1183 bxt_ddi_clock_get(encoder, pipe_config);
3d51278a
DV		 1184}
1185
1c0b85c5 1186static void
d664c0ce
DL		 1187hsw_ddi_calculate_wrpll(int clock /* in Hz */,
1188 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
1c0b85c5
DL		 1189{
1190 uint64_t freq2k;
1191 unsigned p, n2, r2;
63582983 1192 struct hsw_wrpll_rnp best = { 0, 0, 0 };
1c0b85c5
DL		 1193 unsigned budget;
1194
1195 freq2k = clock / 100;
1196
63582983 1197 budget = hsw_wrpll_get_budget_for_freq(clock);
1c0b85c5
DL		 1198
1199 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
1200 * and directly pass the LC PLL to it. */
1201 if (freq2k == 5400000) {
1202 *n2_out = 2;
1203 *p_out = 1;
1204 *r2_out = 2;
1205 return;
1206 }
1207
1208 /*
1209 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
1210 * the WR PLL.
1211 *
1212 * We want R so that REF_MIN <= Ref <= REF_MAX.
1213 * Injecting R2 = 2 * R gives:
1214 * REF_MAX * r2 > LC_FREQ * 2 and
1215 * REF_MIN * r2 < LC_FREQ * 2
1216 *
1217 * Which means the desired boundaries for r2 are:
1218 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
1219 *
1220 */
1221 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
1222 r2 <= LC_FREQ * 2 / REF_MIN;
1223 r2++) {
1224
1225 /*
1226 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
1227 *
1228 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
1229 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
1230 * VCO_MAX * r2 > n2 * LC_FREQ and
1231 * VCO_MIN * r2 < n2 * LC_FREQ)
1232 *
1233 * Which means the desired boundaries for n2 are:
1234 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
1235 */
1236 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
1237 n2 <= VCO_MAX * r2 / LC_FREQ;
1238 n2++) {
1239
1240 for (p = P_MIN; p <= P_MAX; p += P_INC)
63582983
DL		 1241 hsw_wrpll_update_rnp(freq2k, budget,
1242 r2, n2, p, &best);
1c0b85c5
DL		 1243 }
1244 }
6441ab5f 1245
1c0b85c5
DL		 1246 *n2_out = best.n2;
1247 *p_out = best.p;
1248 *r2_out = best.r2;
6441ab5f
PZ		 1249}
1250
0220ab6e 1251static bool
d664c0ce 1252hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 1253 struct intel_crtc_state *crtc_state,
96f3f1f9 1254 struct intel_encoder *intel_encoder)
6441ab5f 1255{
96f3f1f9
VS		 1256 int clock = crtc_state->port_clock;
1257
d664c0ce 1258 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
e0b01be4 1259 struct intel_shared_dpll *pll;
716c2e55 1260 uint32_t val;
1c0b85c5 1261 unsigned p, n2, r2;
6441ab5f 1262
d664c0ce 1263 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
0694001b 1264
114fe488 1265 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
0694001b
PZ		 1266 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
1267 WRPLL_DIVIDER_POST(p);
1268
dd3cd74a
ACO		 1269 memset(&crtc_state->dpll_hw_state, 0,
1270 sizeof(crtc_state->dpll_hw_state));
1271
190f68c5 1272 crtc_state->dpll_hw_state.wrpll = val;
6441ab5f 1273
190f68c5 1274 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
716c2e55
DV		 1275 if (pll == NULL) {
1276 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1277 pipe_name(intel_crtc->pipe));
1278 return false;
0694001b 1279 }
d452c5b6 1280
190f68c5 1281 crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
6441ab5f
PZ		 1282 }
1283
6441ab5f
PZ		 1284 return true;
1285}
1286
dc253813
DL		 1287struct skl_wrpll_context {
1288 uint64_t min_deviation; /* current minimal deviation */
1289 uint64_t central_freq; /* chosen central freq */
1290 uint64_t dco_freq; /* chosen dco freq */
1291 unsigned int p; /* chosen divider */
1292};
1293
1294static void skl_wrpll_context_init(struct skl_wrpll_context *ctx)
1295{
1296 memset(ctx, 0, sizeof(*ctx));
1297
1298 ctx->min_deviation = U64_MAX;
1299}
1300
1301/* DCO freq must be within +1%/-6% of the DCO central freq */
1302#define SKL_DCO_MAX_PDEVIATION 100
1303#define SKL_DCO_MAX_NDEVIATION 600
1304
1305static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx,
1306 uint64_t central_freq,
1307 uint64_t dco_freq,
1308 unsigned int divider)
1309{
1310 uint64_t deviation;
1311
1312 deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq),
1313 central_freq);
1314
1315 /* positive deviation */
1316 if (dco_freq >= central_freq) {
1317 if (deviation < SKL_DCO_MAX_PDEVIATION &&
1318 deviation < ctx->min_deviation) {
1319 ctx->min_deviation = deviation;
1320 ctx->central_freq = central_freq;
1321 ctx->dco_freq = dco_freq;
1322 ctx->p = divider;
1323 }
1324 /* negative deviation */
1325 } else if (deviation < SKL_DCO_MAX_NDEVIATION &&
1326 deviation < ctx->min_deviation) {
1327 ctx->min_deviation = deviation;
1328 ctx->central_freq = central_freq;
1329 ctx->dco_freq = dco_freq;
1330 ctx->p = divider;
1331 }
dc253813
DL		 1332}
1333
1334static void skl_wrpll_get_multipliers(unsigned int p,
1335 unsigned int *p0 /* out */,
1336 unsigned int *p1 /* out */,
1337 unsigned int *p2 /* out */)
1338{
1339 /* even dividers */
1340 if (p % 2 == 0) {
1341 unsigned int half = p / 2;
1342
1343 if (half == 1 || half == 2 || half == 3 || half == 5) {
1344 *p0 = 2;
1345 *p1 = 1;
1346 *p2 = half;
1347 } else if (half % 2 == 0) {
1348 *p0 = 2;
1349 *p1 = half / 2;
1350 *p2 = 2;
1351 } else if (half % 3 == 0) {
1352 *p0 = 3;
1353 *p1 = half / 3;
1354 *p2 = 2;
1355 } else if (half % 7 == 0) {
1356 *p0 = 7;
1357 *p1 = half / 7;
1358 *p2 = 2;
1359 }
1360 } else if (p == 3 || p == 9) { /* 3, 5, 7, 9, 15, 21, 35 */
1361 *p0 = 3;
1362 *p1 = 1;
1363 *p2 = p / 3;
1364 } else if (p == 5 || p == 7) {
1365 *p0 = p;
1366 *p1 = 1;
1367 *p2 = 1;
1368 } else if (p == 15) {
1369 *p0 = 3;
1370 *p1 = 1;
1371 *p2 = 5;
1372 } else if (p == 21) {
1373 *p0 = 7;
1374 *p1 = 1;
1375 *p2 = 3;
1376 } else if (p == 35) {
1377 *p0 = 7;
1378 *p1 = 1;
1379 *p2 = 5;
1380 }
1381}
1382
82d35437
S		 1383struct skl_wrpll_params {
1384 uint32_t dco_fraction;
1385 uint32_t dco_integer;
1386 uint32_t qdiv_ratio;
1387 uint32_t qdiv_mode;
1388 uint32_t kdiv;
1389 uint32_t pdiv;
1390 uint32_t central_freq;
1391};
1392
76516fbc
DL		 1393static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
1394 uint64_t afe_clock,
1395 uint64_t central_freq,
1396 uint32_t p0, uint32_t p1, uint32_t p2)
1397{
1398 uint64_t dco_freq;
1399
76516fbc
DL		 1400 switch (central_freq) {
1401 case 9600000000ULL:
1402 params->central_freq = 0;
1403 break;
1404 case 9000000000ULL:
1405 params->central_freq = 1;
1406 break;
1407 case 8400000000ULL:
1408 params->central_freq = 3;
1409 }
1410
1411 switch (p0) {
1412 case 1:
1413 params->pdiv = 0;
1414 break;
1415 case 2:
1416 params->pdiv = 1;
1417 break;
1418 case 3:
1419 params->pdiv = 2;
1420 break;
1421 case 7:
1422 params->pdiv = 4;
1423 break;
1424 default:
1425 WARN(1, "Incorrect PDiv\n");
1426 }
1427
1428 switch (p2) {
1429 case 5:
1430 params->kdiv = 0;
1431 break;
1432 case 2:
1433 params->kdiv = 1;
1434 break;
1435 case 3:
1436 params->kdiv = 2;
1437 break;
1438 case 1:
1439 params->kdiv = 3;
1440 break;
1441 default:
1442 WARN(1, "Incorrect KDiv\n");
1443 }
1444
1445 params->qdiv_ratio = p1;
1446 params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1;
1447
1448 dco_freq = p0 * p1 * p2 * afe_clock;
1449
1450 /*
1451 * Intermediate values are in Hz.
1452 * Divide by MHz to match bsepc
1453 */
30a7862d 1454 params->dco_integer = div_u64(dco_freq, 24 * MHz(1));
76516fbc 1455 params->dco_fraction =
30a7862d
DL		 1456 div_u64((div_u64(dco_freq, 24) -
1457 params->dco_integer * MHz(1)) * 0x8000, MHz(1));
76516fbc
DL		 1458}
1459
318bd821 1460static bool
82d35437
S		 1461skl_ddi_calculate_wrpll(int clock /* in Hz */,
1462 struct skl_wrpll_params *wrpll_params)
1463{
1464 uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
21318cce
DL		 1465 uint64_t dco_central_freq[3] = {8400000000ULL,
1466 9000000000ULL,
1467 9600000000ULL};
dc253813
DL		 1468 static const int even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20,
1469 24, 28, 30, 32, 36, 40, 42, 44,
1470 48, 52, 54, 56, 60, 64, 66, 68,
1471 70, 72, 76, 78, 80, 84, 88, 90,
1472 92, 96, 98 };
1473 static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 };
1474 static const struct {
1475 const int *list;
1476 int n_dividers;
1477 } dividers[] = {
1478 { even_dividers, ARRAY_SIZE(even_dividers) },
1479 { odd_dividers, ARRAY_SIZE(odd_dividers) },
1480 };
1481 struct skl_wrpll_context ctx;
1482 unsigned int dco, d, i;
1483 unsigned int p0, p1, p2;
1484
1485 skl_wrpll_context_init(&ctx);
1486
1487 for (d = 0; d < ARRAY_SIZE(dividers); d++) {
1488 for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
1489 for (i = 0; i < dividers[d].n_dividers; i++) {
1490 unsigned int p = dividers[d].list[i];
1491 uint64_t dco_freq = p * afe_clock;
1492
1493 skl_wrpll_try_divider(&ctx,
1494 dco_central_freq[dco],
1495 dco_freq,
1496 p);
e7ad9878
DL		 1497 /*
1498 * Skip the remaining dividers if we're sure to
1499 * have found the definitive divider, we can't
1500 * improve a 0 deviation.
1501 */
1502 if (ctx.min_deviation == 0)
1503 goto skip_remaining_dividers;
82d35437
S		 1504 }
1505 }
267db663 1506
e7ad9878 1507skip_remaining_dividers:
267db663
DL		 1508 /*
1509 * If a solution is found with an even divider, prefer
1510 * this one.
1511 */
1512 if (d == 0 && ctx.p)
1513 break;
82d35437
S		 1514 }
1515
dc253813
DL		 1516 if (!ctx.p) {
1517 DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock);
318bd821 1518 return false;
dc253813 1519 }
82d35437 1520
dc253813
DL		 1521 /*
1522 * gcc incorrectly analyses that these can be used without being
1523 * initialized. To be fair, it's hard to guess.
1524 */
1525 p0 = p1 = p2 = 0;
1526 skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2);
1527 skl_wrpll_params_populate(wrpll_params, afe_clock, ctx.central_freq,
1528 p0, p1, p2);
318bd821
DL		 1529
1530 return true;
82d35437
S		 1531}
1532
82d35437
S		 1533static bool
1534skl_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 1535 struct intel_crtc_state *crtc_state,
96f3f1f9 1536 struct intel_encoder *intel_encoder)
82d35437
S		 1537{
1538 struct intel_shared_dpll *pll;
1539 uint32_t ctrl1, cfgcr1, cfgcr2;
96f3f1f9 1540 int clock = crtc_state->port_clock;
82d35437
S		 1541
1542 /*
1543 * See comment in intel_dpll_hw_state to understand why we always use 0
1544 * as the DPLL id in this function.
1545 */
1546
1547 ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1548
1549 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1550 struct skl_wrpll_params wrpll_params = { 0, };
1551
1552 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1553
318bd821
DL		 1554 if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params))
1555 return false;
82d35437
S		 1556
1557 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
1558 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1559 wrpll_params.dco_integer;
1560
1561 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1562 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1563 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1564 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1565 wrpll_params.central_freq;
1566 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
840b32b7
VS		 1567 switch (crtc_state->port_clock / 2) {
1568 case 81000:
71cd8423 1569 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
82d35437 1570 break;
840b32b7 1571 case 135000:
71cd8423 1572 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
82d35437 1573 break;
840b32b7 1574 case 270000:
71cd8423 1575 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
82d35437
S		 1576 break;
1577 }
1578
1579 cfgcr1 = cfgcr2 = 0;
1580 } else /* eDP */
1581 return true;
1582
dd3cd74a
ACO		 1583 memset(&crtc_state->dpll_hw_state, 0,
1584 sizeof(crtc_state->dpll_hw_state));
1585
190f68c5
ACO		 1586 crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1587 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
1588 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
82d35437 1589
190f68c5 1590 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
82d35437
S		 1591 if (pll == NULL) {
1592 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1593 pipe_name(intel_crtc->pipe));
1594 return false;
1595 }
1596
1597 /* shared DPLL id 0 is DPLL 1 */
190f68c5 1598 crtc_state->ddi_pll_sel = pll->id + 1;
82d35437
S		 1599
1600 return true;
1601}
0220ab6e 1602
d683f3bc
S		 1603/* bxt clock parameters */
1604struct bxt_clk_div {
64987fc5 1605 int clock;
d683f3bc
S		 1606 uint32_t p1;
1607 uint32_t p2;
1608 uint32_t m2_int;
1609 uint32_t m2_frac;
1610 bool m2_frac_en;
1611 uint32_t n;
d683f3bc
S		 1612};
1613
1614/* pre-calculated values for DP linkrates */
64987fc5
SJ		 1615static const struct bxt_clk_div bxt_dp_clk_val[] = {
1616 {162000, 4, 2, 32, 1677722, 1, 1},
1617 {270000, 4, 1, 27, 0, 0, 1},
1618 {540000, 2, 1, 27, 0, 0, 1},
1619 {216000, 3, 2, 32, 1677722, 1, 1},
1620 {243000, 4, 1, 24, 1258291, 1, 1},
1621 {324000, 4, 1, 32, 1677722, 1, 1},
1622 {432000, 3, 1, 32, 1677722, 1, 1}
d683f3bc
S		 1623};
1624
1625static bool
1626bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
1627 struct intel_crtc_state *crtc_state,
96f3f1f9 1628 struct intel_encoder *intel_encoder)
d683f3bc
S		 1629{
1630 struct intel_shared_dpll *pll;
1631 struct bxt_clk_div clk_div = {0};
b6dc71f3
VK		 1632 int vco = 0;
1633 uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
e6292556 1634 uint32_t lanestagger;
96f3f1f9 1635 int clock = crtc_state->port_clock;
d683f3bc
S		 1636
1637 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1638 intel_clock_t best_clock;
1639
1640 /* Calculate HDMI div */
1641 /*
1642 * FIXME: tie the following calculation into
1643 * i9xx_crtc_compute_clock
1644 */
1645 if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) {
1646 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
1647 clock, pipe_name(intel_crtc->pipe));
1648 return false;
1649 }
1650
1651 clk_div.p1 = best_clock.p1;
1652 clk_div.p2 = best_clock.p2;
1653 WARN_ON(best_clock.m1 != 2);
1654 clk_div.n = best_clock.n;
1655 clk_div.m2_int = best_clock.m2 >> 22;
1656 clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
1657 clk_div.m2_frac_en = clk_div.m2_frac != 0;
1658
b6dc71f3 1659 vco = best_clock.vco;
d683f3bc
S		 1660 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
1661 intel_encoder->type == INTEL_OUTPUT_EDP) {
64987fc5 1662 int i;
d683f3bc 1663
64987fc5
SJ		 1664 clk_div = bxt_dp_clk_val[0];
1665 for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
1666 if (bxt_dp_clk_val[i].clock == clock) {
1667 clk_div = bxt_dp_clk_val[i];
1668 break;
1669 }
d683f3bc 1670 }
b6dc71f3
VK		 1671 vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
1672 }
1673
e6292556 1674 if (vco >= 6200000 && vco <= 6700000) {
b6dc71f3
VK		 1675 prop_coef = 4;
1676 int_coef = 9;
1677 gain_ctl = 3;
1678 targ_cnt = 8;
1679 } else if ((vco > 5400000 && vco < 6200000) ||
1680 (vco >= 4800000 && vco < 5400000)) {
1681 prop_coef = 5;
1682 int_coef = 11;
1683 gain_ctl = 3;
1684 targ_cnt = 9;
b6dc71f3
VK		 1685 } else if (vco == 5400000) {
1686 prop_coef = 3;
1687 int_coef = 8;
1688 gain_ctl = 1;
1689 targ_cnt = 9;
1690 } else {
1691 DRM_ERROR("Invalid VCO\n");
1692 return false;
d683f3bc
S		 1693 }
1694
dd3cd74a
ACO		 1695 memset(&crtc_state->dpll_hw_state, 0,
1696 sizeof(crtc_state->dpll_hw_state));
1697
e0681e38
VK		 1698 if (clock > 270000)
1699 lanestagger = 0x18;
1700 else if (clock > 135000)
1701 lanestagger = 0x0d;
1702 else if (clock > 67000)
1703 lanestagger = 0x07;
1704 else if (clock > 33000)
1705 lanestagger = 0x04;
1706 else
1707 lanestagger = 0x02;
1708
d683f3bc
S		 1709 crtc_state->dpll_hw_state.ebb0 =
1710 PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
1711 crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
1712 crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n);
1713 crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac;
1714
1715 if (clk_div.m2_frac_en)
1716 crtc_state->dpll_hw_state.pll3 =
1717 PORT_PLL_M2_FRAC_ENABLE;
1718
1719 crtc_state->dpll_hw_state.pll6 =
b6dc71f3 1720 prop_coef | PORT_PLL_INT_COEFF(int_coef);
d683f3bc 1721 crtc_state->dpll_hw_state.pll6 |=
b6dc71f3
VK		 1722 PORT_PLL_GAIN_CTL(gain_ctl);
1723
1724 crtc_state->dpll_hw_state.pll8 = targ_cnt;
d683f3bc 1725
05712c15
ID		 1726 crtc_state->dpll_hw_state.pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT;
1727
e6292556
VK		 1728 crtc_state->dpll_hw_state.pll10 =
1729 PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT)
1730 | PORT_PLL_DCO_AMP_OVR_EN_H;
d683f3bc 1731
05712c15
ID		 1732 crtc_state->dpll_hw_state.ebb4 = PORT_PLL_10BIT_CLK_ENABLE;
1733
d683f3bc 1734 crtc_state->dpll_hw_state.pcsdw12 =
e0681e38 1735 LANESTAGGER_STRAP_OVRD | lanestagger;
d683f3bc
S		 1736
1737 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1738 if (pll == NULL) {
1739 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1740 pipe_name(intel_crtc->pipe));
1741 return false;
1742 }
1743
1744 /* shared DPLL id 0 is DPLL A */
1745 crtc_state->ddi_pll_sel = pll->id;
1746
1747 return true;
1748}
1749
0220ab6e
DL		 1750/*
1751 * Tries to find a *shared* PLL for the CRTC and store it in
1752 * intel_crtc->ddi_pll_sel.
1753 *
1754 * For private DPLLs, compute_config() should do the selection for us. This
1755 * function should be folded into compute_config() eventually.
1756 */
190f68c5
ACO		 1757bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
1758 struct intel_crtc_state *crtc_state)
0220ab6e 1759{
82d35437 1760 struct drm_device *dev = intel_crtc->base.dev;
d0737e1d 1761 struct intel_encoder *intel_encoder =
3165c074 1762 intel_ddi_get_crtc_new_encoder(crtc_state);
0220ab6e 1763
82d35437 1764 if (IS_SKYLAKE(dev))
190f68c5 1765 return skl_ddi_pll_select(intel_crtc, crtc_state,
96f3f1f9 1766 intel_encoder);
d683f3bc
S		 1767 else if (IS_BROXTON(dev))
1768 return bxt_ddi_pll_select(intel_crtc, crtc_state,
96f3f1f9 1769 intel_encoder);
82d35437 1770 else
190f68c5 1771 return hsw_ddi_pll_select(intel_crtc, crtc_state,
96f3f1f9 1772 intel_encoder);
0220ab6e
DL		 1773}
1774
dae84799
PZ		 1775void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1776{
1777 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1778 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1779 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
6e3c9717 1780 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
dae84799
PZ		 1781 int type = intel_encoder->type;
1782 uint32_t temp;
1783
0e32b39c 1784 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
c9809791 1785 temp = TRANS_MSA_SYNC_CLK;
6e3c9717 1786 switch (intel_crtc->config->pipe_bpp) {
dae84799 1787 case 18:
c9809791 1788 temp |= TRANS_MSA_6_BPC;
dae84799
PZ		 1789 break;
1790 case 24:
c9809791 1791 temp |= TRANS_MSA_8_BPC;
dae84799
PZ		 1792 break;
1793 case 30:
c9809791 1794 temp |= TRANS_MSA_10_BPC;
dae84799
PZ		 1795 break;
1796 case 36:
c9809791 1797 temp |= TRANS_MSA_12_BPC;
dae84799
PZ		 1798 break;
1799 default:
4e53c2e0 1800 BUG();
dae84799 1801 }
c9809791 1802 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 1803 }
1804}
1805
0e32b39c
DA		 1806void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1807{
1808 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1809 struct drm_device *dev = crtc->dev;
1810 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1811 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
0e32b39c
DA		 1812 uint32_t temp;
1813 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1814 if (state == true)
1815 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1816 else
1817 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1818 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1819}
1820
8228c251 1821void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
8d9ddbcb
PZ		 1822{
1823 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1824 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
7739c33b 1825 struct drm_encoder *encoder = &intel_encoder->base;
c7670b10
PZ		 1826 struct drm_device *dev = crtc->dev;
1827 struct drm_i915_private *dev_priv = dev->dev_private;
8d9ddbcb 1828 enum pipe pipe = intel_crtc->pipe;
6e3c9717 1829 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
174edf1f 1830 enum port port = intel_ddi_get_encoder_port(intel_encoder);
7739c33b 1831 int type = intel_encoder->type;
8d9ddbcb
PZ		 1832 uint32_t temp;
1833
ad80a810
PZ		 1834 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1835 temp = TRANS_DDI_FUNC_ENABLE;
174edf1f 1836 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252 1837
6e3c9717 1838 switch (intel_crtc->config->pipe_bpp) {
dfcef252 1839 case 18:
ad80a810 1840 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 1841 break;
1842 case 24:
ad80a810 1843 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 1844 break;
1845 case 30:
ad80a810 1846 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 1847 break;
1848 case 36:
ad80a810 1849 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 1850 break;
1851 default:
4e53c2e0 1852 BUG();
dfcef252 1853 }
72662e10 1854
6e3c9717 1855 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 1856 temp |= TRANS_DDI_PVSYNC;
6e3c9717 1857 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 1858 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 1859
e6f0bfc4
PZ		 1860 if (cpu_transcoder == TRANSCODER_EDP) {
1861 switch (pipe) {
1862 case PIPE_A:
c7670b10
PZ		 1863 /* On Haswell, can only use the always-on power well for
1864 * eDP when not using the panel fitter, and when not
1865 * using motion blur mitigation (which we don't
1866 * support). */
fabf6e51 1867 if (IS_HASWELL(dev) &&
6e3c9717
ACO		 1868 (intel_crtc->config->pch_pfit.enabled ||
1869 intel_crtc->config->pch_pfit.force_thru))
d6dd9eb1
DV		 1870 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1871 else
1872 temp |= TRANS_DDI_EDP_INPUT_A_ON;
e6f0bfc4
PZ		 1873 break;
1874 case PIPE_B:
1875 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1876 break;
1877 case PIPE_C:
1878 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1879 break;
1880 default:
1881 BUG();
1882 break;
1883 }
1884 }
1885
7739c33b 1886 if (type == INTEL_OUTPUT_HDMI) {
6e3c9717 1887 if (intel_crtc->config->has_hdmi_sink)
ad80a810 1888 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 1889 else
ad80a810 1890 temp |= TRANS_DDI_MODE_SELECT_DVI;
8d9ddbcb 1891
7739c33b 1892 } else if (type == INTEL_OUTPUT_ANALOG) {
ad80a810 1893 temp |= TRANS_DDI_MODE_SELECT_FDI;
6e3c9717 1894 temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
7739c33b
PZ		 1895
1896 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1897 type == INTEL_OUTPUT_EDP) {
1898 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1899
0e32b39c
DA		 1900 if (intel_dp->is_mst) {
1901 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1902 } else
1903 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1904
90a6b7b0 1905 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
0e32b39c
DA		 1906 } else if (type == INTEL_OUTPUT_DP_MST) {
1907 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
1908
1909 if (intel_dp->is_mst) {
1910 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1911 } else
1912 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
7739c33b 1913
90a6b7b0 1914 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
8d9ddbcb 1915 } else {
84f44ce7
VS		 1916 WARN(1, "Invalid encoder type %d for pipe %c\n",
1917 intel_encoder->type, pipe_name(pipe));
8d9ddbcb
PZ		 1918 }
1919
ad80a810 1920 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 1921}
72662e10 1922
ad80a810
PZ		 1923void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1924 enum transcoder cpu_transcoder)
8d9ddbcb 1925{
ad80a810 1926 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
8d9ddbcb
PZ		 1927 uint32_t val = I915_READ(reg);
1928
0e32b39c 1929 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
ad80a810 1930 val |= TRANS_DDI_PORT_NONE;
8d9ddbcb 1931 I915_WRITE(reg, val);
72662e10
ED		 1932}
1933
bcbc889b
PZ		 1934bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1935{
1936 struct drm_device *dev = intel_connector->base.dev;
1937 struct drm_i915_private *dev_priv = dev->dev_private;
1938 struct intel_encoder *intel_encoder = intel_connector->encoder;
1939 int type = intel_connector->base.connector_type;
1940 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1941 enum pipe pipe = 0;
1942 enum transcoder cpu_transcoder;
882244a3 1943 enum intel_display_power_domain power_domain;
bcbc889b
PZ		 1944 uint32_t tmp;
1945
882244a3 1946 power_domain = intel_display_port_power_domain(intel_encoder);
f458ebbc 1947 if (!intel_display_power_is_enabled(dev_priv, power_domain))
882244a3
PZ		 1948 return false;
1949
bcbc889b
PZ		 1950 if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1951 return false;
1952
1953 if (port == PORT_A)
1954 cpu_transcoder = TRANSCODER_EDP;
1955 else
1a240d4d 1956 cpu_transcoder = (enum transcoder) pipe;
bcbc889b
PZ		 1957
1958 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1959
1960 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1961 case TRANS_DDI_MODE_SELECT_HDMI:
1962 case TRANS_DDI_MODE_SELECT_DVI:
1963 return (type == DRM_MODE_CONNECTOR_HDMIA);
1964
1965 case TRANS_DDI_MODE_SELECT_DP_SST:
1966 if (type == DRM_MODE_CONNECTOR_eDP)
1967 return true;
bcbc889b 1968 return (type == DRM_MODE_CONNECTOR_DisplayPort);
0e32b39c
DA		 1969 case TRANS_DDI_MODE_SELECT_DP_MST:
1970 /* if the transcoder is in MST state then
1971 * connector isn't connected */
1972 return false;
bcbc889b
PZ		 1973
1974 case TRANS_DDI_MODE_SELECT_FDI:
1975 return (type == DRM_MODE_CONNECTOR_VGA);
1976
1977 default:
1978 return false;
1979 }
1980}
1981
85234cdc
DV		 1982bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1983 enum pipe *pipe)
1984{
1985 struct drm_device *dev = encoder->base.dev;
1986 struct drm_i915_private *dev_priv = dev->dev_private;
fe43d3f5 1987 enum port port = intel_ddi_get_encoder_port(encoder);
6d129bea 1988 enum intel_display_power_domain power_domain;
85234cdc
DV		 1989 u32 tmp;
1990 int i;
1991
6d129bea 1992 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 1993 if (!intel_display_power_is_enabled(dev_priv, power_domain))
6d129bea
ID		 1994 return false;
1995
fe43d3f5 1996 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc
DV		 1997
1998 if (!(tmp & DDI_BUF_CTL_ENABLE))
1999 return false;
2000
ad80a810
PZ		 2001 if (port == PORT_A) {
2002 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 2003
ad80a810
PZ		 2004 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
2005 case TRANS_DDI_EDP_INPUT_A_ON:
2006 case TRANS_DDI_EDP_INPUT_A_ONOFF:
2007 *pipe = PIPE_A;
2008 break;
2009 case TRANS_DDI_EDP_INPUT_B_ONOFF:
2010 *pipe = PIPE_B;
2011 break;
2012 case TRANS_DDI_EDP_INPUT_C_ONOFF:
2013 *pipe = PIPE_C;
2014 break;
2015 }
2016
2017 return true;
2018 } else {
2019 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
2020 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
2021
2022 if ((tmp & TRANS_DDI_PORT_MASK)
2023 == TRANS_DDI_SELECT_PORT(port)) {
0e32b39c
DA		 2024 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST)
2025 return false;
2026
ad80a810
PZ		 2027 *pipe = i;
2028 return true;
2029 }
85234cdc
DV		 2030 }
2031 }
2032
84f44ce7 2033 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
85234cdc 2034
22f9fe50 2035 return false;
85234cdc
DV		 2036}
2037
fc914639
PZ		 2038void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
2039{
2040 struct drm_crtc *crtc = &intel_crtc->base;
2041 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
2042 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
2043 enum port port = intel_ddi_get_encoder_port(intel_encoder);
6e3c9717 2044 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 2045
bb523fc0
PZ		 2046 if (cpu_transcoder != TRANSCODER_EDP)
2047 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2048 TRANS_CLK_SEL_PORT(port));
fc914639
PZ		 2049}
2050
2051void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
2052{
2053 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
6e3c9717 2054 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 2055
bb523fc0
PZ		 2056 if (cpu_transcoder != TRANSCODER_EDP)
2057 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2058 TRANS_CLK_SEL_DISABLED);
fc914639
PZ		 2059}
2060
f8896f5d
DW		 2061static void skl_ddi_set_iboost(struct drm_device *dev, u32 level,
2062 enum port port, int type)
2063{
2064 struct drm_i915_private *dev_priv = dev->dev_private;
2065 const struct ddi_buf_trans *ddi_translations;
2066 uint8_t iboost;
75067dde 2067 uint8_t dp_iboost, hdmi_iboost;
f8896f5d
DW		 2068 int n_entries;
2069 u32 reg;
2070
75067dde
AK		 2071 /* VBT may override standard boost values */
2072 dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
2073 hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2074
f8896f5d 2075 if (type == INTEL_OUTPUT_DISPLAYPORT) {
75067dde
AK		 2076 if (dp_iboost) {
2077 iboost = dp_iboost;
2078 } else {
2079 ddi_translations = skl_get_buf_trans_dp(dev, &n_entries);
2080 iboost = ddi_translations[port].i_boost;
2081 }
f8896f5d 2082 } else if (type == INTEL_OUTPUT_EDP) {
75067dde
AK		 2083 if (dp_iboost) {
2084 iboost = dp_iboost;
2085 } else {
2086 ddi_translations = skl_get_buf_trans_edp(dev, &n_entries);
2087 iboost = ddi_translations[port].i_boost;
2088 }
f8896f5d 2089 } else if (type == INTEL_OUTPUT_HDMI) {
75067dde
AK		 2090 if (hdmi_iboost) {
2091 iboost = hdmi_iboost;
2092 } else {
2093 ddi_translations = skl_get_buf_trans_hdmi(dev, &n_entries);
2094 iboost = ddi_translations[port].i_boost;
2095 }
f8896f5d
DW		 2096 } else {
2097 return;
2098 }
2099
2100 /* Make sure that the requested I_boost is valid */
2101 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2102 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2103 return;
2104 }
2105
2106 reg = I915_READ(DISPIO_CR_TX_BMU_CR0);
2107 reg &= ~BALANCE_LEG_MASK(port);
2108 reg &= ~(1 << (BALANCE_LEG_DISABLE_SHIFT + port));
2109
2110 if (iboost)
2111 reg |= iboost << BALANCE_LEG_SHIFT(port);
2112 else
2113 reg |= 1 << (BALANCE_LEG_DISABLE_SHIFT + port);
2114
2115 I915_WRITE(DISPIO_CR_TX_BMU_CR0, reg);
2116}
2117
2118static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
2119 enum port port, int type)
96fb9f9b
VK		 2120{
2121 struct drm_i915_private *dev_priv = dev->dev_private;
2122 const struct bxt_ddi_buf_trans *ddi_translations;
2123 u32 n_entries, i;
2124 uint32_t val;
2125
d9d7000d
SJ		 2126 if (type == INTEL_OUTPUT_EDP && dev_priv->edp_low_vswing) {
2127 n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
2128 ddi_translations = bxt_ddi_translations_edp;
2129 } else if (type == INTEL_OUTPUT_DISPLAYPORT
2130 || type == INTEL_OUTPUT_EDP) {
96fb9f9b
VK		 2131 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
2132 ddi_translations = bxt_ddi_translations_dp;
2133 } else if (type == INTEL_OUTPUT_HDMI) {
2134 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
2135 ddi_translations = bxt_ddi_translations_hdmi;
2136 } else {
2137 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
2138 type);
2139 return;
2140 }
2141
2142 /* Check if default value has to be used */
2143 if (level >= n_entries ||
2144 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
2145 for (i = 0; i < n_entries; i++) {
2146 if (ddi_translations[i].default_index) {
2147 level = i;
2148 break;
2149 }
2150 }
2151 }
2152
2153 /*
2154 * While we write to the group register to program all lanes at once we
2155 * can read only lane registers and we pick lanes 0/1 for that.
2156 */
2157 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
2158 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
2159 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
2160
2161 val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
2162 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
2163 val |= ddi_translations[level].margin << MARGIN_000_SHIFT |
2164 ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
2165 I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
2166
2167 val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
2168 val &= ~UNIQE_TRANGE_EN_METHOD;
2169 if (ddi_translations[level].enable)
2170 val |= UNIQE_TRANGE_EN_METHOD;
2171 I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
2172
2173 val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
2174 val &= ~DE_EMPHASIS;
2175 val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
2176 I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
2177
2178 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
2179 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
2180 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
2181}
2182
f8896f5d
DW		 2183static uint32_t translate_signal_level(int signal_levels)
2184{
2185 uint32_t level;
2186
2187 switch (signal_levels) {
2188 default:
2189 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2190 signal_levels);
2191 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2192 level = 0;
2193 break;
2194 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2195 level = 1;
2196 break;
2197 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2198 level = 2;
2199 break;
2200 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
2201 level = 3;
2202 break;
2203
2204 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2205 level = 4;
2206 break;
2207 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2208 level = 5;
2209 break;
2210 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2211 level = 6;
2212 break;
2213
2214 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2215 level = 7;
2216 break;
2217 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2218 level = 8;
2219 break;
2220
2221 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2222 level = 9;
2223 break;
2224 }
2225
2226 return level;
2227}
2228
2229uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2230{
2231 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2232 struct drm_device *dev = dport->base.base.dev;
2233 struct intel_encoder *encoder = &dport->base;
2234 uint8_t train_set = intel_dp->train_set[0];
2235 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2236 DP_TRAIN_PRE_EMPHASIS_MASK);
2237 enum port port = dport->port;
2238 uint32_t level;
2239
2240 level = translate_signal_level(signal_levels);
2241
2242 if (IS_SKYLAKE(dev))
2243 skl_ddi_set_iboost(dev, level, port, encoder->type);
2244 else if (IS_BROXTON(dev))
2245 bxt_ddi_vswing_sequence(dev, level, port, encoder->type);
2246
2247 return DDI_BUF_TRANS_SELECT(level);
2248}
2249
00c09d70 2250static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
6441ab5f 2251{
c19b0669 2252 struct drm_encoder *encoder = &intel_encoder->base;
efa80add
S		 2253 struct drm_device *dev = encoder->dev;
2254 struct drm_i915_private *dev_priv = dev->dev_private;
30cf6db8 2255 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
6441ab5f 2256 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 2257 int type = intel_encoder->type;
96fb9f9b 2258 int hdmi_level;
6441ab5f 2259
82a4d9c0
PZ		 2260 if (type == INTEL_OUTPUT_EDP) {
2261 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4be73780 2262 intel_edp_panel_on(intel_dp);
82a4d9c0 2263 }
6441ab5f 2264
efa80add 2265 if (IS_SKYLAKE(dev)) {
6e3c9717 2266 uint32_t dpll = crtc->config->ddi_pll_sel;
efa80add
S		 2267 uint32_t val;
2268
5416d871
DL		 2269 /*
2270 * DPLL0 is used for eDP and is the only "private" DPLL (as
2271 * opposed to shared) on SKL
2272 */
2273 if (type == INTEL_OUTPUT_EDP) {
2274 WARN_ON(dpll != SKL_DPLL0);
2275
2276 val = I915_READ(DPLL_CTRL1);
2277
2278 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
2279 DPLL_CTRL1_SSC(dpll) |
71cd8423 2280 DPLL_CTRL1_LINK_RATE_MASK(dpll));
6e3c9717 2281 val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6);
5416d871
DL		 2282
2283 I915_WRITE(DPLL_CTRL1, val);
2284 POSTING_READ(DPLL_CTRL1);
2285 }
2286
2287 /* DDI -> PLL mapping */
efa80add
S		 2288 val = I915_READ(DPLL_CTRL2);
2289
2290 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2291 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2292 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
2293 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2294
2295 I915_WRITE(DPLL_CTRL2, val);
5416d871 2296
1ab23380 2297 } else if (INTEL_INFO(dev)->gen < 9) {
6e3c9717
ACO		 2298 WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE);
2299 I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel);
efa80add 2300 }
c19b0669 2301
82a4d9c0 2302 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
c19b0669 2303 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
30cf6db8 2304
901c2daf
VS		 2305 intel_dp_set_link_params(intel_dp, crtc->config);
2306
44905a27 2307 intel_ddi_init_dp_buf_reg(intel_encoder);
c19b0669
PZ		 2308
2309 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2310 intel_dp_start_link_train(intel_dp);
2311 intel_dp_complete_link_train(intel_dp);
23f08d83 2312 if (port != PORT_A || INTEL_INFO(dev)->gen >= 9)
3ab9c637 2313 intel_dp_stop_link_train(intel_dp);
30cf6db8
DV		 2314 } else if (type == INTEL_OUTPUT_HDMI) {
2315 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2316
96fb9f9b
VK		 2317 if (IS_BROXTON(dev)) {
2318 hdmi_level = dev_priv->vbt.
2319 ddi_port_info[port].hdmi_level_shift;
2320 bxt_ddi_vswing_sequence(dev, hdmi_level, port,
2321 INTEL_OUTPUT_HDMI);
2322 }
30cf6db8 2323 intel_hdmi->set_infoframes(encoder,
6e3c9717
ACO		 2324 crtc->config->has_hdmi_sink,
2325 &crtc->config->base.adjusted_mode);
c19b0669 2326 }
6441ab5f
PZ		 2327}
2328
00c09d70 2329static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
6441ab5f
PZ		 2330{
2331 struct drm_encoder *encoder = &intel_encoder->base;
efa80add
S		 2332 struct drm_device *dev = encoder->dev;
2333 struct drm_i915_private *dev_priv = dev->dev_private;
6441ab5f 2334 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 2335 int type = intel_encoder->type;
2886e93f 2336 uint32_t val;
a836bdf9 2337 bool wait = false;
2886e93f
PZ		 2338
2339 val = I915_READ(DDI_BUF_CTL(port));
2340 if (val & DDI_BUF_CTL_ENABLE) {
2341 val &= ~DDI_BUF_CTL_ENABLE;
2342 I915_WRITE(DDI_BUF_CTL(port), val);
a836bdf9 2343 wait = true;
2886e93f 2344 }
6441ab5f 2345
a836bdf9
PZ		 2346 val = I915_READ(DP_TP_CTL(port));
2347 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2348 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2349 I915_WRITE(DP_TP_CTL(port), val);
2350
2351 if (wait)
2352 intel_wait_ddi_buf_idle(dev_priv, port);
2353
76bb80ed 2354 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
82a4d9c0 2355 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
76bb80ed 2356 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
24f3e092 2357 intel_edp_panel_vdd_on(intel_dp);
4be73780 2358 intel_edp_panel_off(intel_dp);
82a4d9c0
PZ		 2359 }
2360
efa80add
S		 2361 if (IS_SKYLAKE(dev))
2362 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
2363 DPLL_CTRL2_DDI_CLK_OFF(port)));
1ab23380 2364 else if (INTEL_INFO(dev)->gen < 9)
efa80add 2365 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
6441ab5f
PZ		 2366}
2367
00c09d70 2368static void intel_enable_ddi(struct intel_encoder *intel_encoder)
72662e10 2369{
6547fef8 2370 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 2371 struct drm_crtc *crtc = encoder->crtc;
2372 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6547fef8 2373 struct drm_device *dev = encoder->dev;
72662e10 2374 struct drm_i915_private *dev_priv = dev->dev_private;
6547fef8
PZ		 2375 enum port port = intel_ddi_get_encoder_port(intel_encoder);
2376 int type = intel_encoder->type;
72662e10 2377
6547fef8 2378 if (type == INTEL_OUTPUT_HDMI) {
876a8cdf
DL		 2379 struct intel_digital_port *intel_dig_port =
2380 enc_to_dig_port(encoder);
2381
6547fef8
PZ		 2382 /* In HDMI/DVI mode, the port width, and swing/emphasis values
2383 * are ignored so nothing special needs to be done besides
2384 * enabling the port.
2385 */
876a8cdf 2386 I915_WRITE(DDI_BUF_CTL(port),
bcf53de4
SM		 2387 intel_dig_port->saved_port_bits |
2388 DDI_BUF_CTL_ENABLE);
d6c50ff8
PZ		 2389 } else if (type == INTEL_OUTPUT_EDP) {
2390 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2391
23f08d83 2392 if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
3ab9c637
ID		 2393 intel_dp_stop_link_train(intel_dp);
2394
4be73780 2395 intel_edp_backlight_on(intel_dp);
0bc12bcb 2396 intel_psr_enable(intel_dp);
c395578e 2397 intel_edp_drrs_enable(intel_dp);
6547fef8 2398 }
7b9f35a6 2399
6e3c9717 2400 if (intel_crtc->config->has_audio) {
d45a0bf5 2401 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
69bfe1a9 2402 intel_audio_codec_enable(intel_encoder);
7b9f35a6 2403 }
5ab432ef
DV		 2404}
2405
00c09d70 2406static void intel_disable_ddi(struct intel_encoder *intel_encoder)
5ab432ef 2407{
d6c50ff8 2408 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 2409 struct drm_crtc *crtc = encoder->crtc;
2410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d6c50ff8 2411 int type = intel_encoder->type;
7b9f35a6
WX		 2412 struct drm_device *dev = encoder->dev;
2413 struct drm_i915_private *dev_priv = dev->dev_private;
d6c50ff8 2414
6e3c9717 2415 if (intel_crtc->config->has_audio) {
69bfe1a9 2416 intel_audio_codec_disable(intel_encoder);
d45a0bf5
PZ		 2417 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
2418 }
2831d842 2419
d6c50ff8
PZ		 2420 if (type == INTEL_OUTPUT_EDP) {
2421 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2422
c395578e 2423 intel_edp_drrs_disable(intel_dp);
0bc12bcb 2424 intel_psr_disable(intel_dp);
4be73780 2425 intel_edp_backlight_off(intel_dp);
d6c50ff8 2426 }
72662e10 2427}
79f689aa 2428
e0b01be4
DV		 2429static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
2430 struct intel_shared_dpll *pll)
2431{
3e369b76 2432 I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
e0b01be4
DV		 2433 POSTING_READ(WRPLL_CTL(pll->id));
2434 udelay(20);
2435}
2436
12030431
DV		 2437static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv,
2438 struct intel_shared_dpll *pll)
2439{
2440 uint32_t val;
2441
2442 val = I915_READ(WRPLL_CTL(pll->id));
12030431
DV		 2443 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
2444 POSTING_READ(WRPLL_CTL(pll->id));
2445}
2446
d452c5b6
DV		 2447static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2448 struct intel_shared_dpll *pll,
2449 struct intel_dpll_hw_state *hw_state)
2450{
2451 uint32_t val;
2452
f458ebbc 2453 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
d452c5b6
DV		 2454 return false;
2455
2456 val = I915_READ(WRPLL_CTL(pll->id));
2457 hw_state->wrpll = val;
2458
2459 return val & WRPLL_PLL_ENABLE;
2460}
2461
ca1381b5 2462static const char * const hsw_ddi_pll_names[] = {
9cd86933
DV		 2463 "WRPLL 1",
2464 "WRPLL 2",
2465};
2466
143b307c 2467static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
79f689aa 2468{
9cd86933
DV		 2469 int i;
2470
716c2e55 2471 dev_priv->num_shared_dpll = 2;
9cd86933 2472
716c2e55 2473 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9cd86933
DV		 2474 dev_priv->shared_dplls[i].id = i;
2475 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
12030431 2476 dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable;
e0b01be4 2477 dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable;
d452c5b6
DV		 2478 dev_priv->shared_dplls[i].get_hw_state =
2479 hsw_ddi_pll_get_hw_state;
9cd86933 2480 }
143b307c
DL		 2481}
2482
d1a2dc78
S		 2483static const char * const skl_ddi_pll_names[] = {
2484 "DPLL 1",
2485 "DPLL 2",
2486 "DPLL 3",
2487};
2488
2489struct skl_dpll_regs {
2490 u32 ctl, cfgcr1, cfgcr2;
2491};
2492
2493/* this array is indexed by the *shared* pll id */
2494static const struct skl_dpll_regs skl_dpll_regs[3] = {
2495 {
2496 /* DPLL 1 */
2497 .ctl = LCPLL2_CTL,
2498 .cfgcr1 = DPLL1_CFGCR1,
2499 .cfgcr2 = DPLL1_CFGCR2,
2500 },
2501 {
2502 /* DPLL 2 */
2503 .ctl = WRPLL_CTL1,
2504 .cfgcr1 = DPLL2_CFGCR1,
2505 .cfgcr2 = DPLL2_CFGCR2,
2506 },
2507 {
2508 /* DPLL 3 */
2509 .ctl = WRPLL_CTL2,
2510 .cfgcr1 = DPLL3_CFGCR1,
2511 .cfgcr2 = DPLL3_CFGCR2,
2512 },
2513};
2514
2515static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
2516 struct intel_shared_dpll *pll)
2517{
2518 uint32_t val;
2519 unsigned int dpll;
2520 const struct skl_dpll_regs *regs = skl_dpll_regs;
2521
2522 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2523 dpll = pll->id + 1;
2524
2525 val = I915_READ(DPLL_CTRL1);
2526
2527 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) |
71cd8423 2528 DPLL_CTRL1_LINK_RATE_MASK(dpll));
d1a2dc78
S		 2529 val |= pll->config.hw_state.ctrl1 << (dpll * 6);
2530
2531 I915_WRITE(DPLL_CTRL1, val);
2532 POSTING_READ(DPLL_CTRL1);
2533
2534 I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);
2535 I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);
2536 POSTING_READ(regs[pll->id].cfgcr1);
2537 POSTING_READ(regs[pll->id].cfgcr2);
2538
2539 /* the enable bit is always bit 31 */
2540 I915_WRITE(regs[pll->id].ctl,
2541 I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);
2542
2543 if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5))
2544 DRM_ERROR("DPLL %d not locked\n", dpll);
2545}
2546
2547static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
2548 struct intel_shared_dpll *pll)
2549{
2550 const struct skl_dpll_regs *regs = skl_dpll_regs;
2551
2552 /* the enable bit is always bit 31 */
2553 I915_WRITE(regs[pll->id].ctl,
2554 I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
2555 POSTING_READ(regs[pll->id].ctl);
2556}
2557
2558static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2559 struct intel_shared_dpll *pll,
2560 struct intel_dpll_hw_state *hw_state)
2561{
2562 uint32_t val;
2563 unsigned int dpll;
2564 const struct skl_dpll_regs *regs = skl_dpll_regs;
2565
2566 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2567 return false;
2568
2569 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2570 dpll = pll->id + 1;
2571
2572 val = I915_READ(regs[pll->id].ctl);
2573 if (!(val & LCPLL_PLL_ENABLE))
2574 return false;
2575
2576 val = I915_READ(DPLL_CTRL1);
2577 hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f;
2578
2579 /* avoid reading back stale values if HDMI mode is not enabled */
2580 if (val & DPLL_CTRL1_HDMI_MODE(dpll)) {
2581 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
2582 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
2583 }
2584
2585 return true;
2586}
2587
2588static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
2589{
2590 int i;
2591
2592 dev_priv->num_shared_dpll = 3;
2593
2594 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2595 dev_priv->shared_dplls[i].id = i;
2596 dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i];
2597 dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable;
2598 dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable;
2599 dev_priv->shared_dplls[i].get_hw_state =
2600 skl_ddi_pll_get_hw_state;
2601 }
2602}
2603
5c6706e5
VK		 2604static void broxton_phy_init(struct drm_i915_private *dev_priv,
2605 enum dpio_phy phy)
2606{
2607 enum port port;
2608 uint32_t val;
2609
2610 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
2611 val |= GT_DISPLAY_POWER_ON(phy);
2612 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
2613
2614 /* Considering 10ms timeout until BSpec is updated */
2615 if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
2616 DRM_ERROR("timeout during PHY%d power on\n", phy);
2617
2618 for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A);
2619 port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
2620 int lane;
2621
2622 for (lane = 0; lane < 4; lane++) {
2623 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
2624 /*
2625 * Note that on CHV this flag is called UPAR, but has
2626 * the same function.
2627 */
2628 val &= ~LATENCY_OPTIM;
2629 if (lane != 1)
2630 val |= LATENCY_OPTIM;
2631
2632 I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
2633 }
2634 }
2635
2636 /* Program PLL Rcomp code offset */
2637 val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
2638 val &= ~IREF0RC_OFFSET_MASK;
2639 val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
2640 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
2641
2642 val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
2643 val &= ~IREF1RC_OFFSET_MASK;
2644 val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
2645 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
2646
2647 /* Program power gating */
2648 val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
2649 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
2650 SUS_CLK_CONFIG;
2651 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
2652
2653 if (phy == DPIO_PHY0) {
2654 val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
2655 val |= DW6_OLDO_DYN_PWR_DOWN_EN;
2656 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
2657 }
2658
2659 val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
2660 val &= ~OCL2_LDOFUSE_PWR_DIS;
2661 /*
2662 * On PHY1 disable power on the second channel, since no port is
2663 * connected there. On PHY0 both channels have a port, so leave it
2664 * enabled.
2665 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
2666 * power down the second channel on PHY0 as well.
2667 */
2668 if (phy == DPIO_PHY1)
2669 val |= OCL2_LDOFUSE_PWR_DIS;
2670 I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
2671
2672 if (phy == DPIO_PHY0) {
2673 uint32_t grc_code;
2674 /*
2675 * PHY0 isn't connected to an RCOMP resistor so copy over
2676 * the corresponding calibrated value from PHY1, and disable
2677 * the automatic calibration on PHY0.
2678 */
2679 if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE,
2680 10))
2681 DRM_ERROR("timeout waiting for PHY1 GRC\n");
2682
2683 val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1));
2684 val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
2685 grc_code = val << GRC_CODE_FAST_SHIFT |
2686 val << GRC_CODE_SLOW_SHIFT |
2687 val;
2688 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
2689
2690 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
2691 val |= GRC_DIS | GRC_RDY_OVRD;
2692 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
2693 }
2694
2695 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2696 val |= COMMON_RESET_DIS;
2697 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2698}
2699
2700void broxton_ddi_phy_init(struct drm_device *dev)
2701{
2702 /* Enable PHY1 first since it provides Rcomp for PHY0 */
2703 broxton_phy_init(dev->dev_private, DPIO_PHY1);
2704 broxton_phy_init(dev->dev_private, DPIO_PHY0);
2705}
2706
2707static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
2708 enum dpio_phy phy)
2709{
2710 uint32_t val;
2711
2712 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2713 val &= ~COMMON_RESET_DIS;
2714 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2715}
2716
2717void broxton_ddi_phy_uninit(struct drm_device *dev)
2718{
2719 struct drm_i915_private *dev_priv = dev->dev_private;
2720
2721 broxton_phy_uninit(dev_priv, DPIO_PHY1);
2722 broxton_phy_uninit(dev_priv, DPIO_PHY0);
2723
2724 /* FIXME: do this in broxton_phy_uninit per phy */
2725 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0);
2726}
2727
dfb82408
S		 2728static const char * const bxt_ddi_pll_names[] = {
2729 "PORT PLL A",
2730 "PORT PLL B",
2731 "PORT PLL C",
2732};
2733
2734static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
2735 struct intel_shared_dpll *pll)
2736{
2737 uint32_t temp;
2738 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2739
2740 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2741 temp &= ~PORT_PLL_REF_SEL;
2742 /* Non-SSC reference */
2743 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2744
2745 /* Disable 10 bit clock */
2746 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2747 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2748 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2749
2750 /* Write P1 & P2 */
2751 temp = I915_READ(BXT_PORT_PLL_EBB_0(port));
2752 temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK);
2753 temp |= pll->config.hw_state.ebb0;
2754 I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp);
2755
2756 /* Write M2 integer */
2757 temp = I915_READ(BXT_PORT_PLL(port, 0));
2758 temp &= ~PORT_PLL_M2_MASK;
2759 temp |= pll->config.hw_state.pll0;
2760 I915_WRITE(BXT_PORT_PLL(port, 0), temp);
2761
2762 /* Write N */
2763 temp = I915_READ(BXT_PORT_PLL(port, 1));
2764 temp &= ~PORT_PLL_N_MASK;
2765 temp |= pll->config.hw_state.pll1;
2766 I915_WRITE(BXT_PORT_PLL(port, 1), temp);
2767
2768 /* Write M2 fraction */
2769 temp = I915_READ(BXT_PORT_PLL(port, 2));
2770 temp &= ~PORT_PLL_M2_FRAC_MASK;
2771 temp |= pll->config.hw_state.pll2;
2772 I915_WRITE(BXT_PORT_PLL(port, 2), temp);
2773
2774 /* Write M2 fraction enable */
2775 temp = I915_READ(BXT_PORT_PLL(port, 3));
2776 temp &= ~PORT_PLL_M2_FRAC_ENABLE;
2777 temp |= pll->config.hw_state.pll3;
2778 I915_WRITE(BXT_PORT_PLL(port, 3), temp);
2779
2780 /* Write coeff */
2781 temp = I915_READ(BXT_PORT_PLL(port, 6));
2782 temp &= ~PORT_PLL_PROP_COEFF_MASK;
2783 temp &= ~PORT_PLL_INT_COEFF_MASK;
2784 temp &= ~PORT_PLL_GAIN_CTL_MASK;
2785 temp |= pll->config.hw_state.pll6;
2786 I915_WRITE(BXT_PORT_PLL(port, 6), temp);
2787
2788 /* Write calibration val */
2789 temp = I915_READ(BXT_PORT_PLL(port, 8));
2790 temp &= ~PORT_PLL_TARGET_CNT_MASK;
2791 temp |= pll->config.hw_state.pll8;
2792 I915_WRITE(BXT_PORT_PLL(port, 8), temp);
2793
b6dc71f3
VK		 2794 temp = I915_READ(BXT_PORT_PLL(port, 9));
2795 temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
05712c15 2796 temp |= pll->config.hw_state.pll9;
b6dc71f3
VK		 2797 I915_WRITE(BXT_PORT_PLL(port, 9), temp);
2798
2799 temp = I915_READ(BXT_PORT_PLL(port, 10));
2800 temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
2801 temp &= ~PORT_PLL_DCO_AMP_MASK;
2802 temp |= pll->config.hw_state.pll10;
2803 I915_WRITE(BXT_PORT_PLL(port, 10), temp);
dfb82408
S		 2804
2805 /* Recalibrate with new settings */
2806 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2807 temp |= PORT_PLL_RECALIBRATE;
2808 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
05712c15
ID		 2809 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2810 temp |= pll->config.hw_state.ebb4;
dfb82408
S		 2811 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2812
2813 /* Enable PLL */
2814 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2815 temp |= PORT_PLL_ENABLE;
2816 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2817 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2818
2819 if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
2820 PORT_PLL_LOCK), 200))
2821 DRM_ERROR("PLL %d not locked\n", port);
2822
2823 /*
2824 * While we write to the group register to program all lanes at once we
2825 * can read only lane registers and we pick lanes 0/1 for that.
2826 */
2827 temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2828 temp &= ~LANE_STAGGER_MASK;
2829 temp &= ~LANESTAGGER_STRAP_OVRD;
2830 temp |= pll->config.hw_state.pcsdw12;
2831 I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp);
2832}
2833
2834static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
2835 struct intel_shared_dpll *pll)
2836{
2837 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2838 uint32_t temp;
2839
2840 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2841 temp &= ~PORT_PLL_ENABLE;
2842 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2843 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2844}
2845
2846static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2847 struct intel_shared_dpll *pll,
2848 struct intel_dpll_hw_state *hw_state)
2849{
2850 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2851 uint32_t val;
2852
2853 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2854 return false;
2855
2856 val = I915_READ(BXT_PORT_PLL_ENABLE(port));
2857 if (!(val & PORT_PLL_ENABLE))
2858 return false;
2859
2860 hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port));
793dfa59
ID		 2861 hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK;
2862
05712c15
ID		 2863 hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(port));
2864 hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE;
2865
dfb82408 2866 hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0));
793dfa59
ID		 2867 hw_state->pll0 &= PORT_PLL_M2_MASK;
2868
dfb82408 2869 hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1));
793dfa59
ID		 2870 hw_state->pll1 &= PORT_PLL_N_MASK;
2871
dfb82408 2872 hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2));
793dfa59
ID		 2873 hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK;
2874
dfb82408 2875 hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
793dfa59
ID		 2876 hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE;
2877
dfb82408 2878 hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
793dfa59
ID		 2879 hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK |
2880 PORT_PLL_INT_COEFF_MASK |
2881 PORT_PLL_GAIN_CTL_MASK;
2882
dfb82408 2883 hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
793dfa59
ID		 2884 hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK;
2885
05712c15
ID		 2886 hw_state->pll9 = I915_READ(BXT_PORT_PLL(port, 9));
2887 hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK;
2888
b6dc71f3 2889 hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10));
793dfa59
ID		 2890 hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H |
2891 PORT_PLL_DCO_AMP_MASK;
2892
dfb82408
S		 2893 /*
2894 * While we write to the group register to program all lanes at once we
2895 * can read only lane registers. We configure all lanes the same way, so
2896 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
2897 */
2898 hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
b5dada82 2899 if (I915_READ(BXT_PORT_PCS_DW12_LN23(port)) != hw_state->pcsdw12)
dfb82408
S		 2900 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
2901 hw_state->pcsdw12,
2902 I915_READ(BXT_PORT_PCS_DW12_LN23(port)));
793dfa59 2903 hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD;
dfb82408
S		 2904
2905 return true;
2906}
2907
2908static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv)
2909{
2910 int i;
2911
2912 dev_priv->num_shared_dpll = 3;
2913
2914 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2915 dev_priv->shared_dplls[i].id = i;
2916 dev_priv->shared_dplls[i].name = bxt_ddi_pll_names[i];
2917 dev_priv->shared_dplls[i].disable = bxt_ddi_pll_disable;
2918 dev_priv->shared_dplls[i].enable = bxt_ddi_pll_enable;
2919 dev_priv->shared_dplls[i].get_hw_state =
2920 bxt_ddi_pll_get_hw_state;
2921 }
2922}
2923
143b307c
DL		 2924void intel_ddi_pll_init(struct drm_device *dev)
2925{
2926 struct drm_i915_private *dev_priv = dev->dev_private;
2927 uint32_t val = I915_READ(LCPLL_CTL);
2928
d1a2dc78
S		 2929 if (IS_SKYLAKE(dev))
2930 skl_shared_dplls_init(dev_priv);
dfb82408
S		 2931 else if (IS_BROXTON(dev))
2932 bxt_shared_dplls_init(dev_priv);
d1a2dc78
S		 2933 else
2934 hsw_shared_dplls_init(dev_priv);
79f689aa 2935
121643c2 2936 if (IS_SKYLAKE(dev)) {
d9062ae5
DL		 2937 int cdclk_freq;
2938
2939 cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5d96d8af 2940 dev_priv->skl_boot_cdclk = cdclk_freq;
121643c2
S		 2941 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
2942 DRM_ERROR("LCPLL1 is disabled\n");
5d96d8af
DL		 2943 else
2944 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
f8437dd1
VK		 2945 } else if (IS_BROXTON(dev)) {
2946 broxton_init_cdclk(dev);
5c6706e5 2947 broxton_ddi_phy_init(dev);
121643c2
S		 2948 } else {
2949 /*
2950 * The LCPLL register should be turned on by the BIOS. For now
2951 * let's just check its state and print errors in case
2952 * something is wrong. Don't even try to turn it on.
2953 */
2954
2955 if (val & LCPLL_CD_SOURCE_FCLK)
2956 DRM_ERROR("CDCLK source is not LCPLL\n");
79f689aa 2957
121643c2
S		 2958 if (val & LCPLL_PLL_DISABLE)
2959 DRM_ERROR("LCPLL is disabled\n");
2960 }
79f689aa 2961}
c19b0669
PZ		 2962
2963void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
2964{
174edf1f
PZ		 2965 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2966 struct intel_dp *intel_dp = &intel_dig_port->dp;
c19b0669 2967 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
174edf1f 2968 enum port port = intel_dig_port->port;
c19b0669 2969 uint32_t val;
f3e227df 2970 bool wait = false;
c19b0669
PZ		 2971
2972 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2973 val = I915_READ(DDI_BUF_CTL(port));
2974 if (val & DDI_BUF_CTL_ENABLE) {
2975 val &= ~DDI_BUF_CTL_ENABLE;
2976 I915_WRITE(DDI_BUF_CTL(port), val);
2977 wait = true;
2978 }
2979
2980 val = I915_READ(DP_TP_CTL(port));
2981 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2982 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2983 I915_WRITE(DP_TP_CTL(port), val);
2984 POSTING_READ(DP_TP_CTL(port));
2985
2986 if (wait)
2987 intel_wait_ddi_buf_idle(dev_priv, port);
2988 }
2989
0e32b39c 2990 val = DP_TP_CTL_ENABLE |
c19b0669 2991 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
0e32b39c
DA		 2992 if (intel_dp->is_mst)
2993 val |= DP_TP_CTL_MODE_MST;
2994 else {
2995 val |= DP_TP_CTL_MODE_SST;
2996 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2997 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
2998 }
c19b0669
PZ		 2999 I915_WRITE(DP_TP_CTL(port), val);
3000 POSTING_READ(DP_TP_CTL(port));
3001
3002 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3003 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
3004 POSTING_READ(DDI_BUF_CTL(port));
3005
3006 udelay(600);
3007}
00c09d70 3008
1ad960f2
PZ		 3009void intel_ddi_fdi_disable(struct drm_crtc *crtc)
3010{
3011 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
3012 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
3013 uint32_t val;
3014
3015 intel_ddi_post_disable(intel_encoder);
3016
3017 val = I915_READ(_FDI_RXA_CTL);
3018 val &= ~FDI_RX_ENABLE;
3019 I915_WRITE(_FDI_RXA_CTL, val);
3020
3021 val = I915_READ(_FDI_RXA_MISC);
3022 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3023 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3024 I915_WRITE(_FDI_RXA_MISC, val);
3025
3026 val = I915_READ(_FDI_RXA_CTL);
3027 val &= ~FDI_PCDCLK;
3028 I915_WRITE(_FDI_RXA_CTL, val);
3029
3030 val = I915_READ(_FDI_RXA_CTL);
3031 val &= ~FDI_RX_PLL_ENABLE;
3032 I915_WRITE(_FDI_RXA_CTL, val);
3033}
3034
6801c18c 3035void intel_ddi_get_config(struct intel_encoder *encoder,
5cec258b 3036 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 3037{
3038 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
3039 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
0cb09a97 3040 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
bbd440fb 3041 struct intel_hdmi *intel_hdmi;
045ac3b5
JB		 3042 u32 temp, flags = 0;
3043
3044 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3045 if (temp & TRANS_DDI_PHSYNC)
3046 flags |= DRM_MODE_FLAG_PHSYNC;
3047 else
3048 flags |= DRM_MODE_FLAG_NHSYNC;
3049 if (temp & TRANS_DDI_PVSYNC)
3050 flags |= DRM_MODE_FLAG_PVSYNC;
3051 else
3052 flags |= DRM_MODE_FLAG_NVSYNC;
3053
2d112de7 3054 pipe_config->base.adjusted_mode.flags |= flags;
42571aef
VS		 3055
3056 switch (temp & TRANS_DDI_BPC_MASK) {
3057 case TRANS_DDI_BPC_6:
3058 pipe_config->pipe_bpp = 18;
3059 break;
3060 case TRANS_DDI_BPC_8:
3061 pipe_config->pipe_bpp = 24;
3062 break;
3063 case TRANS_DDI_BPC_10:
3064 pipe_config->pipe_bpp = 30;
3065 break;
3066 case TRANS_DDI_BPC_12:
3067 pipe_config->pipe_bpp = 36;
3068 break;
3069 default:
3070 break;
3071 }
eb14cb74
VS		 3072
3073 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3074 case TRANS_DDI_MODE_SELECT_HDMI:
6897b4b5 3075 pipe_config->has_hdmi_sink = true;
bbd440fb
DV		 3076 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
3077
3078 if (intel_hdmi->infoframe_enabled(&encoder->base))
3079 pipe_config->has_infoframe = true;
cbc572a9 3080 break;
eb14cb74
VS		 3081 case TRANS_DDI_MODE_SELECT_DVI:
3082 case TRANS_DDI_MODE_SELECT_FDI:
3083 break;
3084 case TRANS_DDI_MODE_SELECT_DP_SST:
3085 case TRANS_DDI_MODE_SELECT_DP_MST:
3086 pipe_config->has_dp_encoder = true;
90a6b7b0
VS		 3087 pipe_config->lane_count =
3088 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
eb14cb74
VS		 3089 intel_dp_get_m_n(intel_crtc, pipe_config);
3090 break;
3091 default:
3092 break;
3093 }
10214420 3094
f458ebbc 3095 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
a60551b1 3096 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
82910ac6 3097 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
a60551b1
PZ		 3098 pipe_config->has_audio = true;
3099 }
9ed109a7 3100
10214420
DV		 3101 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
3102 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
3103 /*
3104 * This is a big fat ugly hack.
3105 *
3106 * Some machines in UEFI boot mode provide us a VBT that has 18
3107 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3108 * unknown we fail to light up. Yet the same BIOS boots up with
3109 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3110 * max, not what it tells us to use.
3111 *
3112 * Note: This will still be broken if the eDP panel is not lit
3113 * up by the BIOS, and thus we can't get the mode at module
3114 * load.
3115 */
3116 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3117 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
3118 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
3119 }
11578553 3120
22606a18 3121 intel_ddi_clock_get(encoder, pipe_config);
045ac3b5
JB		 3122}
3123
00c09d70
PZ		 3124static void intel_ddi_destroy(struct drm_encoder *encoder)
3125{
3126 /* HDMI has nothing special to destroy, so we can go with this. */
3127 intel_dp_encoder_destroy(encoder);
3128}
3129
5bfe2ac0 3130static bool intel_ddi_compute_config(struct intel_encoder *encoder,
5cec258b 3131 struct intel_crtc_state *pipe_config)
00c09d70 3132{
5bfe2ac0 3133 int type = encoder->type;
eccb140b 3134 int port = intel_ddi_get_encoder_port(encoder);
00c09d70 3135
5bfe2ac0 3136 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
00c09d70 3137
eccb140b
DV		 3138 if (port == PORT_A)
3139 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3140
00c09d70 3141 if (type == INTEL_OUTPUT_HDMI)
5bfe2ac0 3142 return intel_hdmi_compute_config(encoder, pipe_config);
00c09d70 3143 else
5bfe2ac0 3144 return intel_dp_compute_config(encoder, pipe_config);
00c09d70
PZ		 3145}
3146
3147static const struct drm_encoder_funcs intel_ddi_funcs = {
3148 .destroy = intel_ddi_destroy,
3149};
3150
4a28ae58
PZ		 3151static struct intel_connector *
3152intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
3153{
3154 struct intel_connector *connector;
3155 enum port port = intel_dig_port->port;
3156
9bdbd0b9 3157 connector = intel_connector_alloc();
4a28ae58
PZ		 3158 if (!connector)
3159 return NULL;
3160
3161 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
3162 if (!intel_dp_init_connector(intel_dig_port, connector)) {
3163 kfree(connector);
3164 return NULL;
3165 }
3166
3167 return connector;
3168}
3169
3170static struct intel_connector *
3171intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
3172{
3173 struct intel_connector *connector;
3174 enum port port = intel_dig_port->port;
3175
9bdbd0b9 3176 connector = intel_connector_alloc();
4a28ae58
PZ		 3177 if (!connector)
3178 return NULL;
3179
3180 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
3181 intel_hdmi_init_connector(intel_dig_port, connector);
3182
3183 return connector;
3184}
3185
00c09d70
PZ		 3186void intel_ddi_init(struct drm_device *dev, enum port port)
3187{
876a8cdf 3188 struct drm_i915_private *dev_priv = dev->dev_private;
00c09d70
PZ		 3189 struct intel_digital_port *intel_dig_port;
3190 struct intel_encoder *intel_encoder;
3191 struct drm_encoder *encoder;
311a2094
PZ		 3192 bool init_hdmi, init_dp;
3193
3194 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
3195 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
3196 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
3197 if (!init_dp && !init_hdmi) {
500ea70d 3198 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
311a2094 3199 port_name(port));
500ea70d 3200 return;
311a2094 3201 }
00c09d70 3202
b14c5679 3203 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
00c09d70
PZ		 3204 if (!intel_dig_port)
3205 return;
3206
00c09d70
PZ		 3207 intel_encoder = &intel_dig_port->base;
3208 encoder = &intel_encoder->base;
3209
3210 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
3211 DRM_MODE_ENCODER_TMDS);
00c09d70 3212
5bfe2ac0 3213 intel_encoder->compute_config = intel_ddi_compute_config;
00c09d70
PZ		 3214 intel_encoder->enable = intel_enable_ddi;
3215 intel_encoder->pre_enable = intel_ddi_pre_enable;
3216 intel_encoder->disable = intel_disable_ddi;
3217 intel_encoder->post_disable = intel_ddi_post_disable;
3218 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
045ac3b5 3219 intel_encoder->get_config = intel_ddi_get_config;
00c09d70
PZ		 3220
3221 intel_dig_port->port = port;
bcf53de4
SM		 3222 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
3223 (DDI_BUF_PORT_REVERSAL |
3224 DDI_A_4_LANES);
00c09d70
PZ		 3225
3226 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
f68d697e 3227 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
bc079e8b 3228 intel_encoder->cloneable = 0;
00c09d70 3229
f68d697e
CW		 3230 if (init_dp) {
3231 if (!intel_ddi_init_dp_connector(intel_dig_port))
3232 goto err;
13cf5504 3233
f68d697e 3234 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
cf1d5883
SJ		 3235 /*
3236 * On BXT A0/A1, sw needs to activate DDIA HPD logic and
3237 * interrupts to check the external panel connection.
3238 */
3239 if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0)
3240 && port == PORT_B)
3241 dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port;
3242 else
3243 dev_priv->hotplug.irq_port[port] = intel_dig_port;
f68d697e 3244 }
21a8e6a4 3245
311a2094
PZ		 3246 /* In theory we don't need the encoder->type check, but leave it just in
3247 * case we have some really bad VBTs... */
f68d697e
CW		 3248 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
3249 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
3250 goto err;
21a8e6a4 3251 }
f68d697e
CW		 3252
3253 return;
3254
3255err:
3256 drm_encoder_cleanup(encoder);
3257 kfree(intel_dig_port);
00c09d70 3258}
Linux kernel - Deliverables
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