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45244b87 ED |
1 | /* |
2 | * Copyright © 2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "i915_drv.h" | |
29 | #include "intel_drv.h" | |
30 | ||
31 | /* HDMI/DVI modes ignore everything but the last 2 items. So we share | |
32 | * them for both DP and FDI transports, allowing those ports to | |
33 | * automatically adapt to HDMI connections as well | |
34 | */ | |
35 | static const u32 hsw_ddi_translations_dp[] = { | |
36 | 0x00FFFFFF, 0x0006000E, /* DP parameters */ | |
37 | 0x00D75FFF, 0x0005000A, | |
38 | 0x00C30FFF, 0x00040006, | |
39 | 0x80AAAFFF, 0x000B0000, | |
40 | 0x00FFFFFF, 0x0005000A, | |
41 | 0x00D75FFF, 0x000C0004, | |
42 | 0x80C30FFF, 0x000B0000, | |
43 | 0x00FFFFFF, 0x00040006, | |
44 | 0x80D75FFF, 0x000B0000, | |
45244b87 ED |
45 | }; |
46 | ||
47 | static const u32 hsw_ddi_translations_fdi[] = { | |
48 | 0x00FFFFFF, 0x0007000E, /* FDI parameters */ | |
49 | 0x00D75FFF, 0x000F000A, | |
50 | 0x00C30FFF, 0x00060006, | |
51 | 0x00AAAFFF, 0x001E0000, | |
52 | 0x00FFFFFF, 0x000F000A, | |
53 | 0x00D75FFF, 0x00160004, | |
54 | 0x00C30FFF, 0x001E0000, | |
55 | 0x00FFFFFF, 0x00060006, | |
56 | 0x00D75FFF, 0x001E0000, | |
6acab15a PZ |
57 | }; |
58 | ||
59 | static const u32 hsw_ddi_translations_hdmi[] = { | |
60 | /* Idx NT mV diff T mV diff db */ | |
61 | 0x00FFFFFF, 0x0006000E, /* 0: 400 400 0 */ | |
62 | 0x00E79FFF, 0x000E000C, /* 1: 400 500 2 */ | |
63 | 0x00D75FFF, 0x0005000A, /* 2: 400 600 3.5 */ | |
64 | 0x00FFFFFF, 0x0005000A, /* 3: 600 600 0 */ | |
65 | 0x00E79FFF, 0x001D0007, /* 4: 600 750 2 */ | |
66 | 0x00D75FFF, 0x000C0004, /* 5: 600 900 3.5 */ | |
67 | 0x00FFFFFF, 0x00040006, /* 6: 800 800 0 */ | |
68 | 0x80E79FFF, 0x00030002, /* 7: 800 1000 2 */ | |
69 | 0x00FFFFFF, 0x00140005, /* 8: 850 850 0 */ | |
70 | 0x00FFFFFF, 0x000C0004, /* 9: 900 900 0 */ | |
71 | 0x00FFFFFF, 0x001C0003, /* 10: 950 950 0 */ | |
72 | 0x80FFFFFF, 0x00030002, /* 11: 1000 1000 0 */ | |
45244b87 ED |
73 | }; |
74 | ||
e58623cb AR |
75 | static const u32 bdw_ddi_translations_dp[] = { |
76 | 0x00FFFFFF, 0x0007000E, /* DP parameters */ | |
77 | 0x00D75FFF, 0x000E000A, | |
78 | 0x00BEFFFF, 0x00140006, | |
79 | 0x00FFFFFF, 0x000E000A, | |
80 | 0x00D75FFF, 0x00180004, | |
81 | 0x80CB2FFF, 0x001B0002, | |
82 | 0x00F7DFFF, 0x00180004, | |
83 | 0x80D75FFF, 0x001B0002, | |
84 | 0x80FFFFFF, 0x001B0002, | |
85 | 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/ | |
86 | }; | |
87 | ||
88 | static const u32 bdw_ddi_translations_fdi[] = { | |
89 | 0x00FFFFFF, 0x0001000E, /* FDI parameters */ | |
90 | 0x00D75FFF, 0x0004000A, | |
91 | 0x00C30FFF, 0x00070006, | |
92 | 0x00AAAFFF, 0x000C0000, | |
93 | 0x00FFFFFF, 0x0004000A, | |
94 | 0x00D75FFF, 0x00090004, | |
95 | 0x00C30FFF, 0x000C0000, | |
96 | 0x00FFFFFF, 0x00070006, | |
97 | 0x00D75FFF, 0x000C0000, | |
98 | 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/ | |
99 | }; | |
100 | ||
20f4dbe4 | 101 | enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder) |
fc914639 | 102 | { |
0bdee30e | 103 | struct drm_encoder *encoder = &intel_encoder->base; |
fc914639 PZ |
104 | int type = intel_encoder->type; |
105 | ||
174edf1f | 106 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || |
00c09d70 | 107 | type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) { |
174edf1f PZ |
108 | struct intel_digital_port *intel_dig_port = |
109 | enc_to_dig_port(encoder); | |
110 | return intel_dig_port->port; | |
0bdee30e | 111 | |
fc914639 PZ |
112 | } else if (type == INTEL_OUTPUT_ANALOG) { |
113 | return PORT_E; | |
0bdee30e | 114 | |
fc914639 PZ |
115 | } else { |
116 | DRM_ERROR("Invalid DDI encoder type %d\n", type); | |
117 | BUG(); | |
118 | } | |
119 | } | |
120 | ||
e58623cb AR |
121 | /* |
122 | * Starting with Haswell, DDI port buffers must be programmed with correct | |
123 | * values in advance. The buffer values are different for FDI and DP modes, | |
45244b87 ED |
124 | * but the HDMI/DVI fields are shared among those. So we program the DDI |
125 | * in either FDI or DP modes only, as HDMI connections will work with both | |
126 | * of those | |
127 | */ | |
ad8d270c | 128 | static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port) |
45244b87 ED |
129 | { |
130 | struct drm_i915_private *dev_priv = dev->dev_private; | |
131 | u32 reg; | |
132 | int i; | |
6acab15a | 133 | int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift; |
e58623cb AR |
134 | const u32 *ddi_translations_fdi; |
135 | const u32 *ddi_translations_dp; | |
136 | const u32 *ddi_translations; | |
137 | ||
138 | if (IS_BROADWELL(dev)) { | |
139 | ddi_translations_fdi = bdw_ddi_translations_fdi; | |
140 | ddi_translations_dp = bdw_ddi_translations_dp; | |
141 | } else if (IS_HASWELL(dev)) { | |
142 | ddi_translations_fdi = hsw_ddi_translations_fdi; | |
143 | ddi_translations_dp = hsw_ddi_translations_dp; | |
144 | } else { | |
145 | WARN(1, "ddi translation table missing\n"); | |
146 | ddi_translations_fdi = bdw_ddi_translations_fdi; | |
147 | ddi_translations_dp = bdw_ddi_translations_dp; | |
148 | } | |
149 | ||
150 | ddi_translations = ((port == PORT_E) ? | |
151 | ddi_translations_fdi : | |
152 | ddi_translations_dp); | |
45244b87 | 153 | |
f72d19f0 PZ |
154 | for (i = 0, reg = DDI_BUF_TRANS(port); |
155 | i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) { | |
45244b87 ED |
156 | I915_WRITE(reg, ddi_translations[i]); |
157 | reg += 4; | |
158 | } | |
6acab15a PZ |
159 | /* Entry 9 is for HDMI: */ |
160 | for (i = 0; i < 2; i++) { | |
161 | I915_WRITE(reg, hsw_ddi_translations_hdmi[hdmi_level * 2 + i]); | |
162 | reg += 4; | |
163 | } | |
45244b87 ED |
164 | } |
165 | ||
166 | /* Program DDI buffers translations for DP. By default, program ports A-D in DP | |
167 | * mode and port E for FDI. | |
168 | */ | |
169 | void intel_prepare_ddi(struct drm_device *dev) | |
170 | { | |
171 | int port; | |
172 | ||
0d536cb4 PZ |
173 | if (!HAS_DDI(dev)) |
174 | return; | |
45244b87 | 175 | |
ad8d270c PZ |
176 | for (port = PORT_A; port <= PORT_E; port++) |
177 | intel_prepare_ddi_buffers(dev, port); | |
45244b87 | 178 | } |
c82e4d26 ED |
179 | |
180 | static const long hsw_ddi_buf_ctl_values[] = { | |
181 | DDI_BUF_EMP_400MV_0DB_HSW, | |
182 | DDI_BUF_EMP_400MV_3_5DB_HSW, | |
183 | DDI_BUF_EMP_400MV_6DB_HSW, | |
184 | DDI_BUF_EMP_400MV_9_5DB_HSW, | |
185 | DDI_BUF_EMP_600MV_0DB_HSW, | |
186 | DDI_BUF_EMP_600MV_3_5DB_HSW, | |
187 | DDI_BUF_EMP_600MV_6DB_HSW, | |
188 | DDI_BUF_EMP_800MV_0DB_HSW, | |
189 | DDI_BUF_EMP_800MV_3_5DB_HSW | |
190 | }; | |
191 | ||
248138b5 PZ |
192 | static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, |
193 | enum port port) | |
194 | { | |
195 | uint32_t reg = DDI_BUF_CTL(port); | |
196 | int i; | |
197 | ||
198 | for (i = 0; i < 8; i++) { | |
199 | udelay(1); | |
200 | if (I915_READ(reg) & DDI_BUF_IS_IDLE) | |
201 | return; | |
202 | } | |
203 | DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port)); | |
204 | } | |
c82e4d26 ED |
205 | |
206 | /* Starting with Haswell, different DDI ports can work in FDI mode for | |
207 | * connection to the PCH-located connectors. For this, it is necessary to train | |
208 | * both the DDI port and PCH receiver for the desired DDI buffer settings. | |
209 | * | |
210 | * The recommended port to work in FDI mode is DDI E, which we use here. Also, | |
211 | * please note that when FDI mode is active on DDI E, it shares 2 lines with | |
212 | * DDI A (which is used for eDP) | |
213 | */ | |
214 | ||
215 | void hsw_fdi_link_train(struct drm_crtc *crtc) | |
216 | { | |
217 | struct drm_device *dev = crtc->dev; | |
218 | struct drm_i915_private *dev_priv = dev->dev_private; | |
219 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
04945641 | 220 | u32 temp, i, rx_ctl_val; |
c82e4d26 | 221 | |
04945641 PZ |
222 | /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the |
223 | * mode set "sequence for CRT port" document: | |
224 | * - TP1 to TP2 time with the default value | |
225 | * - FDI delay to 90h | |
8693a824 DL |
226 | * |
227 | * WaFDIAutoLinkSetTimingOverrride:hsw | |
04945641 PZ |
228 | */ |
229 | I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) | | |
230 | FDI_RX_PWRDN_LANE0_VAL(2) | | |
231 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
232 | ||
233 | /* Enable the PCH Receiver FDI PLL */ | |
3e68320e | 234 | rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | |
33d29b14 | 235 | FDI_RX_PLL_ENABLE | |
627eb5a3 | 236 | FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
04945641 PZ |
237 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); |
238 | POSTING_READ(_FDI_RXA_CTL); | |
239 | udelay(220); | |
240 | ||
241 | /* Switch from Rawclk to PCDclk */ | |
242 | rx_ctl_val |= FDI_PCDCLK; | |
243 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); | |
244 | ||
245 | /* Configure Port Clock Select */ | |
246 | I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel); | |
247 | ||
248 | /* Start the training iterating through available voltages and emphasis, | |
249 | * testing each value twice. */ | |
250 | for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) { | |
c82e4d26 ED |
251 | /* Configure DP_TP_CTL with auto-training */ |
252 | I915_WRITE(DP_TP_CTL(PORT_E), | |
253 | DP_TP_CTL_FDI_AUTOTRAIN | | |
254 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | | |
255 | DP_TP_CTL_LINK_TRAIN_PAT1 | | |
256 | DP_TP_CTL_ENABLE); | |
257 | ||
876a8cdf DL |
258 | /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. |
259 | * DDI E does not support port reversal, the functionality is | |
260 | * achieved on the PCH side in FDI_RX_CTL, so no need to set the | |
261 | * port reversal bit */ | |
c82e4d26 | 262 | I915_WRITE(DDI_BUF_CTL(PORT_E), |
04945641 | 263 | DDI_BUF_CTL_ENABLE | |
33d29b14 | 264 | ((intel_crtc->config.fdi_lanes - 1) << 1) | |
04945641 PZ |
265 | hsw_ddi_buf_ctl_values[i / 2]); |
266 | POSTING_READ(DDI_BUF_CTL(PORT_E)); | |
c82e4d26 ED |
267 | |
268 | udelay(600); | |
269 | ||
04945641 PZ |
270 | /* Program PCH FDI Receiver TU */ |
271 | I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64)); | |
272 | ||
273 | /* Enable PCH FDI Receiver with auto-training */ | |
274 | rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; | |
275 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); | |
276 | POSTING_READ(_FDI_RXA_CTL); | |
277 | ||
278 | /* Wait for FDI receiver lane calibration */ | |
279 | udelay(30); | |
280 | ||
281 | /* Unset FDI_RX_MISC pwrdn lanes */ | |
282 | temp = I915_READ(_FDI_RXA_MISC); | |
283 | temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); | |
284 | I915_WRITE(_FDI_RXA_MISC, temp); | |
285 | POSTING_READ(_FDI_RXA_MISC); | |
286 | ||
287 | /* Wait for FDI auto training time */ | |
288 | udelay(5); | |
c82e4d26 ED |
289 | |
290 | temp = I915_READ(DP_TP_STATUS(PORT_E)); | |
291 | if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { | |
04945641 | 292 | DRM_DEBUG_KMS("FDI link training done on step %d\n", i); |
c82e4d26 ED |
293 | |
294 | /* Enable normal pixel sending for FDI */ | |
295 | I915_WRITE(DP_TP_CTL(PORT_E), | |
04945641 PZ |
296 | DP_TP_CTL_FDI_AUTOTRAIN | |
297 | DP_TP_CTL_LINK_TRAIN_NORMAL | | |
298 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | | |
299 | DP_TP_CTL_ENABLE); | |
c82e4d26 | 300 | |
04945641 | 301 | return; |
c82e4d26 | 302 | } |
04945641 | 303 | |
248138b5 PZ |
304 | temp = I915_READ(DDI_BUF_CTL(PORT_E)); |
305 | temp &= ~DDI_BUF_CTL_ENABLE; | |
306 | I915_WRITE(DDI_BUF_CTL(PORT_E), temp); | |
307 | POSTING_READ(DDI_BUF_CTL(PORT_E)); | |
308 | ||
04945641 | 309 | /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ |
248138b5 PZ |
310 | temp = I915_READ(DP_TP_CTL(PORT_E)); |
311 | temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
312 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
313 | I915_WRITE(DP_TP_CTL(PORT_E), temp); | |
314 | POSTING_READ(DP_TP_CTL(PORT_E)); | |
315 | ||
316 | intel_wait_ddi_buf_idle(dev_priv, PORT_E); | |
04945641 PZ |
317 | |
318 | rx_ctl_val &= ~FDI_RX_ENABLE; | |
319 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); | |
248138b5 | 320 | POSTING_READ(_FDI_RXA_CTL); |
04945641 PZ |
321 | |
322 | /* Reset FDI_RX_MISC pwrdn lanes */ | |
323 | temp = I915_READ(_FDI_RXA_MISC); | |
324 | temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); | |
325 | temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); | |
326 | I915_WRITE(_FDI_RXA_MISC, temp); | |
248138b5 | 327 | POSTING_READ(_FDI_RXA_MISC); |
c82e4d26 ED |
328 | } |
329 | ||
04945641 | 330 | DRM_ERROR("FDI link training failed!\n"); |
c82e4d26 | 331 | } |
0e72a5b5 | 332 | |
c7d8be30 | 333 | static void intel_ddi_mode_set(struct intel_encoder *encoder) |
72662e10 | 334 | { |
c7d8be30 DV |
335 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
336 | int port = intel_ddi_get_encoder_port(encoder); | |
337 | int pipe = crtc->pipe; | |
338 | int type = encoder->type; | |
339 | struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; | |
72662e10 | 340 | |
bf98a726 | 341 | DRM_DEBUG_KMS("Preparing DDI mode on port %c, pipe %c\n", |
247d89f6 | 342 | port_name(port), pipe_name(pipe)); |
72662e10 | 343 | |
c7d8be30 | 344 | crtc->eld_vld = false; |
247d89f6 | 345 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
c7d8be30 | 346 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
876a8cdf | 347 | struct intel_digital_port *intel_dig_port = |
c7d8be30 | 348 | enc_to_dig_port(&encoder->base); |
4f07854d | 349 | |
bcf53de4 | 350 | intel_dp->DP = intel_dig_port->saved_port_bits | |
876a8cdf | 351 | DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW; |
17aa6be9 | 352 | intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); |
247d89f6 | 353 | |
8fed6193 TI |
354 | if (intel_dp->has_audio) { |
355 | DRM_DEBUG_DRIVER("DP audio on pipe %c on DDI\n", | |
c7d8be30 | 356 | pipe_name(crtc->pipe)); |
8fed6193 TI |
357 | |
358 | /* write eld */ | |
359 | DRM_DEBUG_DRIVER("DP audio: write eld information\n"); | |
c7d8be30 | 360 | intel_write_eld(&encoder->base, adjusted_mode); |
8fed6193 | 361 | } |
247d89f6 | 362 | } else if (type == INTEL_OUTPUT_HDMI) { |
c7d8be30 | 363 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
247d89f6 PZ |
364 | |
365 | if (intel_hdmi->has_audio) { | |
366 | /* Proper support for digital audio needs a new logic | |
367 | * and a new set of registers, so we leave it for future | |
368 | * patch bombing. | |
369 | */ | |
370 | DRM_DEBUG_DRIVER("HDMI audio on pipe %c on DDI\n", | |
c7d8be30 | 371 | pipe_name(crtc->pipe)); |
247d89f6 PZ |
372 | |
373 | /* write eld */ | |
374 | DRM_DEBUG_DRIVER("HDMI audio: write eld information\n"); | |
c7d8be30 | 375 | intel_write_eld(&encoder->base, adjusted_mode); |
247d89f6 | 376 | } |
72662e10 | 377 | |
c7d8be30 | 378 | intel_hdmi->set_infoframes(&encoder->base, adjusted_mode); |
247d89f6 | 379 | } |
8d9ddbcb PZ |
380 | } |
381 | ||
382 | static struct intel_encoder * | |
383 | intel_ddi_get_crtc_encoder(struct drm_crtc *crtc) | |
384 | { | |
385 | struct drm_device *dev = crtc->dev; | |
386 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
387 | struct intel_encoder *intel_encoder, *ret = NULL; | |
388 | int num_encoders = 0; | |
389 | ||
390 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { | |
391 | ret = intel_encoder; | |
392 | num_encoders++; | |
393 | } | |
394 | ||
395 | if (num_encoders != 1) | |
84f44ce7 VS |
396 | WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders, |
397 | pipe_name(intel_crtc->pipe)); | |
8d9ddbcb PZ |
398 | |
399 | BUG_ON(ret == NULL); | |
400 | return ret; | |
401 | } | |
402 | ||
6441ab5f PZ |
403 | void intel_ddi_put_crtc_pll(struct drm_crtc *crtc) |
404 | { | |
405 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
406 | struct intel_ddi_plls *plls = &dev_priv->ddi_plls; | |
407 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
408 | uint32_t val; | |
409 | ||
410 | switch (intel_crtc->ddi_pll_sel) { | |
411 | case PORT_CLK_SEL_SPLL: | |
412 | plls->spll_refcount--; | |
413 | if (plls->spll_refcount == 0) { | |
414 | DRM_DEBUG_KMS("Disabling SPLL\n"); | |
415 | val = I915_READ(SPLL_CTL); | |
416 | WARN_ON(!(val & SPLL_PLL_ENABLE)); | |
417 | I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); | |
418 | POSTING_READ(SPLL_CTL); | |
419 | } | |
420 | break; | |
421 | case PORT_CLK_SEL_WRPLL1: | |
422 | plls->wrpll1_refcount--; | |
423 | if (plls->wrpll1_refcount == 0) { | |
424 | DRM_DEBUG_KMS("Disabling WRPLL 1\n"); | |
425 | val = I915_READ(WRPLL_CTL1); | |
426 | WARN_ON(!(val & WRPLL_PLL_ENABLE)); | |
427 | I915_WRITE(WRPLL_CTL1, val & ~WRPLL_PLL_ENABLE); | |
428 | POSTING_READ(WRPLL_CTL1); | |
429 | } | |
430 | break; | |
431 | case PORT_CLK_SEL_WRPLL2: | |
432 | plls->wrpll2_refcount--; | |
433 | if (plls->wrpll2_refcount == 0) { | |
434 | DRM_DEBUG_KMS("Disabling WRPLL 2\n"); | |
435 | val = I915_READ(WRPLL_CTL2); | |
436 | WARN_ON(!(val & WRPLL_PLL_ENABLE)); | |
437 | I915_WRITE(WRPLL_CTL2, val & ~WRPLL_PLL_ENABLE); | |
438 | POSTING_READ(WRPLL_CTL2); | |
439 | } | |
440 | break; | |
441 | } | |
442 | ||
443 | WARN(plls->spll_refcount < 0, "Invalid SPLL refcount\n"); | |
444 | WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n"); | |
445 | WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n"); | |
446 | ||
447 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_NONE; | |
448 | } | |
449 | ||
1c0b85c5 DL |
450 | #define LC_FREQ 2700 |
451 | #define LC_FREQ_2K (LC_FREQ * 2000) | |
452 | ||
453 | #define P_MIN 2 | |
454 | #define P_MAX 64 | |
455 | #define P_INC 2 | |
456 | ||
457 | /* Constraints for PLL good behavior */ | |
458 | #define REF_MIN 48 | |
459 | #define REF_MAX 400 | |
460 | #define VCO_MIN 2400 | |
461 | #define VCO_MAX 4800 | |
462 | ||
463 | #define ABS_DIFF(a, b) ((a > b) ? (a - b) : (b - a)) | |
464 | ||
465 | struct wrpll_rnp { | |
466 | unsigned p, n2, r2; | |
467 | }; | |
468 | ||
469 | static unsigned wrpll_get_budget_for_freq(int clock) | |
6441ab5f | 470 | { |
1c0b85c5 DL |
471 | unsigned budget; |
472 | ||
473 | switch (clock) { | |
474 | case 25175000: | |
475 | case 25200000: | |
476 | case 27000000: | |
477 | case 27027000: | |
478 | case 37762500: | |
479 | case 37800000: | |
480 | case 40500000: | |
481 | case 40541000: | |
482 | case 54000000: | |
483 | case 54054000: | |
484 | case 59341000: | |
485 | case 59400000: | |
486 | case 72000000: | |
487 | case 74176000: | |
488 | case 74250000: | |
489 | case 81000000: | |
490 | case 81081000: | |
491 | case 89012000: | |
492 | case 89100000: | |
493 | case 108000000: | |
494 | case 108108000: | |
495 | case 111264000: | |
496 | case 111375000: | |
497 | case 148352000: | |
498 | case 148500000: | |
499 | case 162000000: | |
500 | case 162162000: | |
501 | case 222525000: | |
502 | case 222750000: | |
503 | case 296703000: | |
504 | case 297000000: | |
505 | budget = 0; | |
506 | break; | |
507 | case 233500000: | |
508 | case 245250000: | |
509 | case 247750000: | |
510 | case 253250000: | |
511 | case 298000000: | |
512 | budget = 1500; | |
513 | break; | |
514 | case 169128000: | |
515 | case 169500000: | |
516 | case 179500000: | |
517 | case 202000000: | |
518 | budget = 2000; | |
519 | break; | |
520 | case 256250000: | |
521 | case 262500000: | |
522 | case 270000000: | |
523 | case 272500000: | |
524 | case 273750000: | |
525 | case 280750000: | |
526 | case 281250000: | |
527 | case 286000000: | |
528 | case 291750000: | |
529 | budget = 4000; | |
530 | break; | |
531 | case 267250000: | |
532 | case 268500000: | |
533 | budget = 5000; | |
534 | break; | |
535 | default: | |
536 | budget = 1000; | |
537 | break; | |
538 | } | |
6441ab5f | 539 | |
1c0b85c5 DL |
540 | return budget; |
541 | } | |
542 | ||
543 | static void wrpll_update_rnp(uint64_t freq2k, unsigned budget, | |
544 | unsigned r2, unsigned n2, unsigned p, | |
545 | struct wrpll_rnp *best) | |
546 | { | |
547 | uint64_t a, b, c, d, diff, diff_best; | |
6441ab5f | 548 | |
1c0b85c5 DL |
549 | /* No best (r,n,p) yet */ |
550 | if (best->p == 0) { | |
551 | best->p = p; | |
552 | best->n2 = n2; | |
553 | best->r2 = r2; | |
554 | return; | |
555 | } | |
6441ab5f | 556 | |
1c0b85c5 DL |
557 | /* |
558 | * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to | |
559 | * freq2k. | |
560 | * | |
561 | * delta = 1e6 * | |
562 | * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) / | |
563 | * freq2k; | |
564 | * | |
565 | * and we would like delta <= budget. | |
566 | * | |
567 | * If the discrepancy is above the PPM-based budget, always prefer to | |
568 | * improve upon the previous solution. However, if you're within the | |
569 | * budget, try to maximize Ref * VCO, that is N / (P * R^2). | |
570 | */ | |
571 | a = freq2k * budget * p * r2; | |
572 | b = freq2k * budget * best->p * best->r2; | |
573 | diff = ABS_DIFF((freq2k * p * r2), (LC_FREQ_2K * n2)); | |
574 | diff_best = ABS_DIFF((freq2k * best->p * best->r2), | |
575 | (LC_FREQ_2K * best->n2)); | |
576 | c = 1000000 * diff; | |
577 | d = 1000000 * diff_best; | |
578 | ||
579 | if (a < c && b < d) { | |
580 | /* If both are above the budget, pick the closer */ | |
581 | if (best->p * best->r2 * diff < p * r2 * diff_best) { | |
582 | best->p = p; | |
583 | best->n2 = n2; | |
584 | best->r2 = r2; | |
585 | } | |
586 | } else if (a >= c && b < d) { | |
587 | /* If A is below the threshold but B is above it? Update. */ | |
588 | best->p = p; | |
589 | best->n2 = n2; | |
590 | best->r2 = r2; | |
591 | } else if (a >= c && b >= d) { | |
592 | /* Both are below the limit, so pick the higher n2/(r2*r2) */ | |
593 | if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) { | |
594 | best->p = p; | |
595 | best->n2 = n2; | |
596 | best->r2 = r2; | |
597 | } | |
598 | } | |
599 | /* Otherwise a < c && b >= d, do nothing */ | |
600 | } | |
601 | ||
602 | static void | |
603 | intel_ddi_calculate_wrpll(int clock /* in Hz */, | |
604 | unsigned *r2_out, unsigned *n2_out, unsigned *p_out) | |
605 | { | |
606 | uint64_t freq2k; | |
607 | unsigned p, n2, r2; | |
608 | struct wrpll_rnp best = { 0, 0, 0 }; | |
609 | unsigned budget; | |
610 | ||
611 | freq2k = clock / 100; | |
612 | ||
613 | budget = wrpll_get_budget_for_freq(clock); | |
614 | ||
615 | /* Special case handling for 540 pixel clock: bypass WR PLL entirely | |
616 | * and directly pass the LC PLL to it. */ | |
617 | if (freq2k == 5400000) { | |
618 | *n2_out = 2; | |
619 | *p_out = 1; | |
620 | *r2_out = 2; | |
621 | return; | |
622 | } | |
623 | ||
624 | /* | |
625 | * Ref = LC_FREQ / R, where Ref is the actual reference input seen by | |
626 | * the WR PLL. | |
627 | * | |
628 | * We want R so that REF_MIN <= Ref <= REF_MAX. | |
629 | * Injecting R2 = 2 * R gives: | |
630 | * REF_MAX * r2 > LC_FREQ * 2 and | |
631 | * REF_MIN * r2 < LC_FREQ * 2 | |
632 | * | |
633 | * Which means the desired boundaries for r2 are: | |
634 | * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN | |
635 | * | |
636 | */ | |
637 | for (r2 = LC_FREQ * 2 / REF_MAX + 1; | |
638 | r2 <= LC_FREQ * 2 / REF_MIN; | |
639 | r2++) { | |
640 | ||
641 | /* | |
642 | * VCO = N * Ref, that is: VCO = N * LC_FREQ / R | |
643 | * | |
644 | * Once again we want VCO_MIN <= VCO <= VCO_MAX. | |
645 | * Injecting R2 = 2 * R and N2 = 2 * N, we get: | |
646 | * VCO_MAX * r2 > n2 * LC_FREQ and | |
647 | * VCO_MIN * r2 < n2 * LC_FREQ) | |
648 | * | |
649 | * Which means the desired boundaries for n2 are: | |
650 | * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ | |
651 | */ | |
652 | for (n2 = VCO_MIN * r2 / LC_FREQ + 1; | |
653 | n2 <= VCO_MAX * r2 / LC_FREQ; | |
654 | n2++) { | |
655 | ||
656 | for (p = P_MIN; p <= P_MAX; p += P_INC) | |
657 | wrpll_update_rnp(freq2k, budget, | |
658 | r2, n2, p, &best); | |
659 | } | |
660 | } | |
6441ab5f | 661 | |
1c0b85c5 DL |
662 | *n2_out = best.n2; |
663 | *p_out = best.p; | |
664 | *r2_out = best.r2; | |
6441ab5f | 665 | |
1c0b85c5 DL |
666 | DRM_DEBUG_KMS("WRPLL: %dHz refresh rate with p=%d, n2=%d r2=%d\n", |
667 | clock, *p_out, *n2_out, *r2_out); | |
6441ab5f PZ |
668 | } |
669 | ||
ff9a6750 | 670 | bool intel_ddi_pll_mode_set(struct drm_crtc *crtc) |
6441ab5f PZ |
671 | { |
672 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
673 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
068759bd | 674 | struct drm_encoder *encoder = &intel_encoder->base; |
6441ab5f PZ |
675 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
676 | struct intel_ddi_plls *plls = &dev_priv->ddi_plls; | |
677 | int type = intel_encoder->type; | |
678 | enum pipe pipe = intel_crtc->pipe; | |
679 | uint32_t reg, val; | |
ff9a6750 | 680 | int clock = intel_crtc->config.port_clock; |
6441ab5f PZ |
681 | |
682 | /* TODO: reuse PLLs when possible (compare values) */ | |
683 | ||
684 | intel_ddi_put_crtc_pll(crtc); | |
685 | ||
068759bd PZ |
686 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
687 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
688 | ||
689 | switch (intel_dp->link_bw) { | |
690 | case DP_LINK_BW_1_62: | |
691 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810; | |
692 | break; | |
693 | case DP_LINK_BW_2_7: | |
694 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350; | |
695 | break; | |
696 | case DP_LINK_BW_5_4: | |
697 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700; | |
698 | break; | |
699 | default: | |
700 | DRM_ERROR("Link bandwidth %d unsupported\n", | |
701 | intel_dp->link_bw); | |
702 | return false; | |
703 | } | |
704 | ||
705 | /* We don't need to turn any PLL on because we'll use LCPLL. */ | |
706 | return true; | |
707 | ||
708 | } else if (type == INTEL_OUTPUT_HDMI) { | |
1c0b85c5 | 709 | unsigned p, n2, r2; |
6441ab5f PZ |
710 | |
711 | if (plls->wrpll1_refcount == 0) { | |
712 | DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n", | |
713 | pipe_name(pipe)); | |
714 | plls->wrpll1_refcount++; | |
715 | reg = WRPLL_CTL1; | |
716 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL1; | |
717 | } else if (plls->wrpll2_refcount == 0) { | |
718 | DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n", | |
719 | pipe_name(pipe)); | |
720 | plls->wrpll2_refcount++; | |
721 | reg = WRPLL_CTL2; | |
722 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL2; | |
723 | } else { | |
724 | DRM_ERROR("No WRPLLs available!\n"); | |
725 | return false; | |
726 | } | |
727 | ||
728 | WARN(I915_READ(reg) & WRPLL_PLL_ENABLE, | |
729 | "WRPLL already enabled\n"); | |
730 | ||
1c0b85c5 | 731 | intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p); |
6441ab5f PZ |
732 | |
733 | val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 | | |
734 | WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) | | |
735 | WRPLL_DIVIDER_POST(p); | |
736 | ||
737 | } else if (type == INTEL_OUTPUT_ANALOG) { | |
738 | if (plls->spll_refcount == 0) { | |
739 | DRM_DEBUG_KMS("Using SPLL on pipe %c\n", | |
740 | pipe_name(pipe)); | |
741 | plls->spll_refcount++; | |
742 | reg = SPLL_CTL; | |
743 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL; | |
00037c2e DL |
744 | } else { |
745 | DRM_ERROR("SPLL already in use\n"); | |
746 | return false; | |
6441ab5f PZ |
747 | } |
748 | ||
749 | WARN(I915_READ(reg) & SPLL_PLL_ENABLE, | |
750 | "SPLL already enabled\n"); | |
751 | ||
39bc66c9 | 752 | val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC; |
6441ab5f PZ |
753 | |
754 | } else { | |
755 | WARN(1, "Invalid DDI encoder type %d\n", type); | |
756 | return false; | |
757 | } | |
758 | ||
759 | I915_WRITE(reg, val); | |
760 | udelay(20); | |
761 | ||
762 | return true; | |
763 | } | |
764 | ||
dae84799 PZ |
765 | void intel_ddi_set_pipe_settings(struct drm_crtc *crtc) |
766 | { | |
767 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
768 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
769 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
3b117c8f | 770 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
dae84799 PZ |
771 | int type = intel_encoder->type; |
772 | uint32_t temp; | |
773 | ||
774 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { | |
775 | ||
c9809791 | 776 | temp = TRANS_MSA_SYNC_CLK; |
965e0c48 | 777 | switch (intel_crtc->config.pipe_bpp) { |
dae84799 | 778 | case 18: |
c9809791 | 779 | temp |= TRANS_MSA_6_BPC; |
dae84799 PZ |
780 | break; |
781 | case 24: | |
c9809791 | 782 | temp |= TRANS_MSA_8_BPC; |
dae84799 PZ |
783 | break; |
784 | case 30: | |
c9809791 | 785 | temp |= TRANS_MSA_10_BPC; |
dae84799 PZ |
786 | break; |
787 | case 36: | |
c9809791 | 788 | temp |= TRANS_MSA_12_BPC; |
dae84799 PZ |
789 | break; |
790 | default: | |
4e53c2e0 | 791 | BUG(); |
dae84799 | 792 | } |
c9809791 | 793 | I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); |
dae84799 PZ |
794 | } |
795 | } | |
796 | ||
8228c251 | 797 | void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) |
8d9ddbcb PZ |
798 | { |
799 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
800 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
7739c33b | 801 | struct drm_encoder *encoder = &intel_encoder->base; |
c7670b10 PZ |
802 | struct drm_device *dev = crtc->dev; |
803 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8d9ddbcb | 804 | enum pipe pipe = intel_crtc->pipe; |
3b117c8f | 805 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
174edf1f | 806 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
7739c33b | 807 | int type = intel_encoder->type; |
8d9ddbcb PZ |
808 | uint32_t temp; |
809 | ||
ad80a810 PZ |
810 | /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ |
811 | temp = TRANS_DDI_FUNC_ENABLE; | |
174edf1f | 812 | temp |= TRANS_DDI_SELECT_PORT(port); |
dfcef252 | 813 | |
965e0c48 | 814 | switch (intel_crtc->config.pipe_bpp) { |
dfcef252 | 815 | case 18: |
ad80a810 | 816 | temp |= TRANS_DDI_BPC_6; |
dfcef252 PZ |
817 | break; |
818 | case 24: | |
ad80a810 | 819 | temp |= TRANS_DDI_BPC_8; |
dfcef252 PZ |
820 | break; |
821 | case 30: | |
ad80a810 | 822 | temp |= TRANS_DDI_BPC_10; |
dfcef252 PZ |
823 | break; |
824 | case 36: | |
ad80a810 | 825 | temp |= TRANS_DDI_BPC_12; |
dfcef252 PZ |
826 | break; |
827 | default: | |
4e53c2e0 | 828 | BUG(); |
dfcef252 | 829 | } |
72662e10 | 830 | |
a666283e | 831 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) |
ad80a810 | 832 | temp |= TRANS_DDI_PVSYNC; |
a666283e | 833 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) |
ad80a810 | 834 | temp |= TRANS_DDI_PHSYNC; |
f63eb7c4 | 835 | |
e6f0bfc4 PZ |
836 | if (cpu_transcoder == TRANSCODER_EDP) { |
837 | switch (pipe) { | |
838 | case PIPE_A: | |
c7670b10 PZ |
839 | /* On Haswell, can only use the always-on power well for |
840 | * eDP when not using the panel fitter, and when not | |
841 | * using motion blur mitigation (which we don't | |
842 | * support). */ | |
843 | if (IS_HASWELL(dev) && intel_crtc->config.pch_pfit.enabled) | |
d6dd9eb1 DV |
844 | temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; |
845 | else | |
846 | temp |= TRANS_DDI_EDP_INPUT_A_ON; | |
e6f0bfc4 PZ |
847 | break; |
848 | case PIPE_B: | |
849 | temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; | |
850 | break; | |
851 | case PIPE_C: | |
852 | temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; | |
853 | break; | |
854 | default: | |
855 | BUG(); | |
856 | break; | |
857 | } | |
858 | } | |
859 | ||
7739c33b PZ |
860 | if (type == INTEL_OUTPUT_HDMI) { |
861 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
8d9ddbcb PZ |
862 | |
863 | if (intel_hdmi->has_hdmi_sink) | |
ad80a810 | 864 | temp |= TRANS_DDI_MODE_SELECT_HDMI; |
8d9ddbcb | 865 | else |
ad80a810 | 866 | temp |= TRANS_DDI_MODE_SELECT_DVI; |
8d9ddbcb | 867 | |
7739c33b | 868 | } else if (type == INTEL_OUTPUT_ANALOG) { |
ad80a810 | 869 | temp |= TRANS_DDI_MODE_SELECT_FDI; |
33d29b14 | 870 | temp |= (intel_crtc->config.fdi_lanes - 1) << 1; |
7739c33b PZ |
871 | |
872 | } else if (type == INTEL_OUTPUT_DISPLAYPORT || | |
873 | type == INTEL_OUTPUT_EDP) { | |
874 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
875 | ||
ad80a810 | 876 | temp |= TRANS_DDI_MODE_SELECT_DP_SST; |
7739c33b | 877 | |
17aa6be9 | 878 | temp |= DDI_PORT_WIDTH(intel_dp->lane_count); |
8d9ddbcb | 879 | } else { |
84f44ce7 VS |
880 | WARN(1, "Invalid encoder type %d for pipe %c\n", |
881 | intel_encoder->type, pipe_name(pipe)); | |
8d9ddbcb PZ |
882 | } |
883 | ||
ad80a810 | 884 | I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); |
8d9ddbcb | 885 | } |
72662e10 | 886 | |
ad80a810 PZ |
887 | void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, |
888 | enum transcoder cpu_transcoder) | |
8d9ddbcb | 889 | { |
ad80a810 | 890 | uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
8d9ddbcb PZ |
891 | uint32_t val = I915_READ(reg); |
892 | ||
ad80a810 PZ |
893 | val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK); |
894 | val |= TRANS_DDI_PORT_NONE; | |
8d9ddbcb | 895 | I915_WRITE(reg, val); |
72662e10 ED |
896 | } |
897 | ||
bcbc889b PZ |
898 | bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) |
899 | { | |
900 | struct drm_device *dev = intel_connector->base.dev; | |
901 | struct drm_i915_private *dev_priv = dev->dev_private; | |
902 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
903 | int type = intel_connector->base.connector_type; | |
904 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
905 | enum pipe pipe = 0; | |
906 | enum transcoder cpu_transcoder; | |
907 | uint32_t tmp; | |
908 | ||
909 | if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) | |
910 | return false; | |
911 | ||
912 | if (port == PORT_A) | |
913 | cpu_transcoder = TRANSCODER_EDP; | |
914 | else | |
1a240d4d | 915 | cpu_transcoder = (enum transcoder) pipe; |
bcbc889b PZ |
916 | |
917 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
918 | ||
919 | switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { | |
920 | case TRANS_DDI_MODE_SELECT_HDMI: | |
921 | case TRANS_DDI_MODE_SELECT_DVI: | |
922 | return (type == DRM_MODE_CONNECTOR_HDMIA); | |
923 | ||
924 | case TRANS_DDI_MODE_SELECT_DP_SST: | |
925 | if (type == DRM_MODE_CONNECTOR_eDP) | |
926 | return true; | |
927 | case TRANS_DDI_MODE_SELECT_DP_MST: | |
928 | return (type == DRM_MODE_CONNECTOR_DisplayPort); | |
929 | ||
930 | case TRANS_DDI_MODE_SELECT_FDI: | |
931 | return (type == DRM_MODE_CONNECTOR_VGA); | |
932 | ||
933 | default: | |
934 | return false; | |
935 | } | |
936 | } | |
937 | ||
85234cdc DV |
938 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, |
939 | enum pipe *pipe) | |
940 | { | |
941 | struct drm_device *dev = encoder->base.dev; | |
942 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fe43d3f5 | 943 | enum port port = intel_ddi_get_encoder_port(encoder); |
85234cdc DV |
944 | u32 tmp; |
945 | int i; | |
946 | ||
fe43d3f5 | 947 | tmp = I915_READ(DDI_BUF_CTL(port)); |
85234cdc DV |
948 | |
949 | if (!(tmp & DDI_BUF_CTL_ENABLE)) | |
950 | return false; | |
951 | ||
ad80a810 PZ |
952 | if (port == PORT_A) { |
953 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
85234cdc | 954 | |
ad80a810 PZ |
955 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { |
956 | case TRANS_DDI_EDP_INPUT_A_ON: | |
957 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
958 | *pipe = PIPE_A; | |
959 | break; | |
960 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
961 | *pipe = PIPE_B; | |
962 | break; | |
963 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
964 | *pipe = PIPE_C; | |
965 | break; | |
966 | } | |
967 | ||
968 | return true; | |
969 | } else { | |
970 | for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) { | |
971 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(i)); | |
972 | ||
973 | if ((tmp & TRANS_DDI_PORT_MASK) | |
974 | == TRANS_DDI_SELECT_PORT(port)) { | |
975 | *pipe = i; | |
976 | return true; | |
977 | } | |
85234cdc DV |
978 | } |
979 | } | |
980 | ||
84f44ce7 | 981 | DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port)); |
85234cdc | 982 | |
22f9fe50 | 983 | return false; |
85234cdc DV |
984 | } |
985 | ||
6441ab5f PZ |
986 | static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv, |
987 | enum pipe pipe) | |
988 | { | |
989 | uint32_t temp, ret; | |
a42f704b | 990 | enum port port = I915_MAX_PORTS; |
ad80a810 PZ |
991 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
992 | pipe); | |
6441ab5f PZ |
993 | int i; |
994 | ||
ad80a810 PZ |
995 | if (cpu_transcoder == TRANSCODER_EDP) { |
996 | port = PORT_A; | |
997 | } else { | |
998 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
999 | temp &= TRANS_DDI_PORT_MASK; | |
1000 | ||
1001 | for (i = PORT_B; i <= PORT_E; i++) | |
1002 | if (temp == TRANS_DDI_SELECT_PORT(i)) | |
1003 | port = i; | |
1004 | } | |
6441ab5f | 1005 | |
a42f704b DL |
1006 | if (port == I915_MAX_PORTS) { |
1007 | WARN(1, "Pipe %c enabled on an unknown port\n", | |
1008 | pipe_name(pipe)); | |
1009 | ret = PORT_CLK_SEL_NONE; | |
1010 | } else { | |
1011 | ret = I915_READ(PORT_CLK_SEL(port)); | |
1012 | DRM_DEBUG_KMS("Pipe %c connected to port %c using clock " | |
1013 | "0x%08x\n", pipe_name(pipe), port_name(port), | |
1014 | ret); | |
1015 | } | |
6441ab5f PZ |
1016 | |
1017 | return ret; | |
1018 | } | |
1019 | ||
1020 | void intel_ddi_setup_hw_pll_state(struct drm_device *dev) | |
1021 | { | |
1022 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1023 | enum pipe pipe; | |
1024 | struct intel_crtc *intel_crtc; | |
1025 | ||
1026 | for_each_pipe(pipe) { | |
1027 | intel_crtc = | |
1028 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
1029 | ||
1030 | if (!intel_crtc->active) | |
1031 | continue; | |
1032 | ||
1033 | intel_crtc->ddi_pll_sel = intel_ddi_get_crtc_pll(dev_priv, | |
1034 | pipe); | |
1035 | ||
1036 | switch (intel_crtc->ddi_pll_sel) { | |
1037 | case PORT_CLK_SEL_SPLL: | |
1038 | dev_priv->ddi_plls.spll_refcount++; | |
1039 | break; | |
1040 | case PORT_CLK_SEL_WRPLL1: | |
1041 | dev_priv->ddi_plls.wrpll1_refcount++; | |
1042 | break; | |
1043 | case PORT_CLK_SEL_WRPLL2: | |
1044 | dev_priv->ddi_plls.wrpll2_refcount++; | |
1045 | break; | |
1046 | } | |
1047 | } | |
1048 | } | |
1049 | ||
fc914639 PZ |
1050 | void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc) |
1051 | { | |
1052 | struct drm_crtc *crtc = &intel_crtc->base; | |
1053 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
1054 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
1055 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
3b117c8f | 1056 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
fc914639 | 1057 | |
bb523fc0 PZ |
1058 | if (cpu_transcoder != TRANSCODER_EDP) |
1059 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), | |
1060 | TRANS_CLK_SEL_PORT(port)); | |
fc914639 PZ |
1061 | } |
1062 | ||
1063 | void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc) | |
1064 | { | |
1065 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; | |
3b117c8f | 1066 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
fc914639 | 1067 | |
bb523fc0 PZ |
1068 | if (cpu_transcoder != TRANSCODER_EDP) |
1069 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), | |
1070 | TRANS_CLK_SEL_DISABLED); | |
fc914639 PZ |
1071 | } |
1072 | ||
00c09d70 | 1073 | static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) |
6441ab5f | 1074 | { |
c19b0669 PZ |
1075 | struct drm_encoder *encoder = &intel_encoder->base; |
1076 | struct drm_crtc *crtc = encoder->crtc; | |
1077 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; | |
6441ab5f PZ |
1078 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1079 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
82a4d9c0 | 1080 | int type = intel_encoder->type; |
6441ab5f | 1081 | |
82a4d9c0 PZ |
1082 | if (type == INTEL_OUTPUT_EDP) { |
1083 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1084 | ironlake_edp_panel_vdd_on(intel_dp); | |
1085 | ironlake_edp_panel_on(intel_dp); | |
1086 | ironlake_edp_panel_vdd_off(intel_dp, true); | |
1087 | } | |
6441ab5f | 1088 | |
82a4d9c0 | 1089 | WARN_ON(intel_crtc->ddi_pll_sel == PORT_CLK_SEL_NONE); |
6441ab5f | 1090 | I915_WRITE(PORT_CLK_SEL(port), intel_crtc->ddi_pll_sel); |
c19b0669 | 1091 | |
82a4d9c0 | 1092 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
c19b0669 PZ |
1093 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
1094 | ||
1095 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); | |
1096 | intel_dp_start_link_train(intel_dp); | |
1097 | intel_dp_complete_link_train(intel_dp); | |
3ab9c637 ID |
1098 | if (port != PORT_A) |
1099 | intel_dp_stop_link_train(intel_dp); | |
c19b0669 | 1100 | } |
6441ab5f PZ |
1101 | } |
1102 | ||
00c09d70 | 1103 | static void intel_ddi_post_disable(struct intel_encoder *intel_encoder) |
6441ab5f PZ |
1104 | { |
1105 | struct drm_encoder *encoder = &intel_encoder->base; | |
1106 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; | |
1107 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
82a4d9c0 | 1108 | int type = intel_encoder->type; |
2886e93f | 1109 | uint32_t val; |
a836bdf9 | 1110 | bool wait = false; |
2886e93f PZ |
1111 | |
1112 | val = I915_READ(DDI_BUF_CTL(port)); | |
1113 | if (val & DDI_BUF_CTL_ENABLE) { | |
1114 | val &= ~DDI_BUF_CTL_ENABLE; | |
1115 | I915_WRITE(DDI_BUF_CTL(port), val); | |
a836bdf9 | 1116 | wait = true; |
2886e93f | 1117 | } |
6441ab5f | 1118 | |
a836bdf9 PZ |
1119 | val = I915_READ(DP_TP_CTL(port)); |
1120 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
1121 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
1122 | I915_WRITE(DP_TP_CTL(port), val); | |
1123 | ||
1124 | if (wait) | |
1125 | intel_wait_ddi_buf_idle(dev_priv, port); | |
1126 | ||
82a4d9c0 PZ |
1127 | if (type == INTEL_OUTPUT_EDP) { |
1128 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1129 | ironlake_edp_panel_vdd_on(intel_dp); | |
1130 | ironlake_edp_panel_off(intel_dp); | |
1131 | } | |
1132 | ||
6441ab5f PZ |
1133 | I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); |
1134 | } | |
1135 | ||
00c09d70 | 1136 | static void intel_enable_ddi(struct intel_encoder *intel_encoder) |
72662e10 | 1137 | { |
6547fef8 | 1138 | struct drm_encoder *encoder = &intel_encoder->base; |
7b9f35a6 WX |
1139 | struct drm_crtc *crtc = encoder->crtc; |
1140 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1141 | int pipe = intel_crtc->pipe; | |
6547fef8 | 1142 | struct drm_device *dev = encoder->dev; |
72662e10 | 1143 | struct drm_i915_private *dev_priv = dev->dev_private; |
6547fef8 PZ |
1144 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
1145 | int type = intel_encoder->type; | |
7b9f35a6 | 1146 | uint32_t tmp; |
72662e10 | 1147 | |
6547fef8 | 1148 | if (type == INTEL_OUTPUT_HDMI) { |
876a8cdf DL |
1149 | struct intel_digital_port *intel_dig_port = |
1150 | enc_to_dig_port(encoder); | |
1151 | ||
6547fef8 PZ |
1152 | /* In HDMI/DVI mode, the port width, and swing/emphasis values |
1153 | * are ignored so nothing special needs to be done besides | |
1154 | * enabling the port. | |
1155 | */ | |
876a8cdf | 1156 | I915_WRITE(DDI_BUF_CTL(port), |
bcf53de4 SM |
1157 | intel_dig_port->saved_port_bits | |
1158 | DDI_BUF_CTL_ENABLE); | |
d6c50ff8 PZ |
1159 | } else if (type == INTEL_OUTPUT_EDP) { |
1160 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1161 | ||
3ab9c637 ID |
1162 | if (port == PORT_A) |
1163 | intel_dp_stop_link_train(intel_dp); | |
1164 | ||
d6c50ff8 | 1165 | ironlake_edp_backlight_on(intel_dp); |
4906557e | 1166 | intel_edp_psr_enable(intel_dp); |
6547fef8 | 1167 | } |
7b9f35a6 | 1168 | |
c77bf565 | 1169 | if (intel_crtc->eld_vld && type != INTEL_OUTPUT_EDP) { |
7b9f35a6 WX |
1170 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); |
1171 | tmp |= ((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4)); | |
1172 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); | |
1173 | } | |
5ab432ef DV |
1174 | } |
1175 | ||
00c09d70 | 1176 | static void intel_disable_ddi(struct intel_encoder *intel_encoder) |
5ab432ef | 1177 | { |
d6c50ff8 | 1178 | struct drm_encoder *encoder = &intel_encoder->base; |
7b9f35a6 WX |
1179 | struct drm_crtc *crtc = encoder->crtc; |
1180 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1181 | int pipe = intel_crtc->pipe; | |
d6c50ff8 | 1182 | int type = intel_encoder->type; |
7b9f35a6 WX |
1183 | struct drm_device *dev = encoder->dev; |
1184 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1185 | uint32_t tmp; | |
d6c50ff8 | 1186 | |
c77bf565 PZ |
1187 | if (intel_crtc->eld_vld && type != INTEL_OUTPUT_EDP) { |
1188 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); | |
1189 | tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << | |
1190 | (pipe * 4)); | |
1191 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); | |
1192 | } | |
2831d842 | 1193 | |
d6c50ff8 PZ |
1194 | if (type == INTEL_OUTPUT_EDP) { |
1195 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1196 | ||
4906557e | 1197 | intel_edp_psr_disable(intel_dp); |
d6c50ff8 PZ |
1198 | ironlake_edp_backlight_off(intel_dp); |
1199 | } | |
72662e10 | 1200 | } |
79f689aa | 1201 | |
b8fc2f6a | 1202 | int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv) |
79f689aa | 1203 | { |
e39bf98a | 1204 | struct drm_device *dev = dev_priv->dev; |
a4006641 | 1205 | uint32_t lcpll = I915_READ(LCPLL_CTL); |
e39bf98a | 1206 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; |
a4006641 | 1207 | |
e39bf98a | 1208 | if (lcpll & LCPLL_CD_SOURCE_FCLK) { |
a4006641 | 1209 | return 800000; |
e39bf98a | 1210 | } else if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT) { |
b2b877ff | 1211 | return 450000; |
e39bf98a | 1212 | } else if (freq == LCPLL_CLK_FREQ_450) { |
b2b877ff | 1213 | return 450000; |
e39bf98a PZ |
1214 | } else if (IS_HASWELL(dev)) { |
1215 | if (IS_ULT(dev)) | |
1216 | return 337500; | |
1217 | else | |
1218 | return 540000; | |
1219 | } else { | |
1220 | if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
1221 | return 540000; | |
1222 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
1223 | return 337500; | |
1224 | else | |
1225 | return 675000; | |
1226 | } | |
79f689aa PZ |
1227 | } |
1228 | ||
1229 | void intel_ddi_pll_init(struct drm_device *dev) | |
1230 | { | |
1231 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1232 | uint32_t val = I915_READ(LCPLL_CTL); | |
1233 | ||
1234 | /* The LCPLL register should be turned on by the BIOS. For now let's | |
1235 | * just check its state and print errors in case something is wrong. | |
1236 | * Don't even try to turn it on. | |
1237 | */ | |
1238 | ||
b2b877ff | 1239 | DRM_DEBUG_KMS("CDCLK running at %dKHz\n", |
79f689aa PZ |
1240 | intel_ddi_get_cdclk_freq(dev_priv)); |
1241 | ||
1242 | if (val & LCPLL_CD_SOURCE_FCLK) | |
1243 | DRM_ERROR("CDCLK source is not LCPLL\n"); | |
1244 | ||
1245 | if (val & LCPLL_PLL_DISABLE) | |
1246 | DRM_ERROR("LCPLL is disabled\n"); | |
1247 | } | |
c19b0669 PZ |
1248 | |
1249 | void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder) | |
1250 | { | |
174edf1f PZ |
1251 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
1252 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
c19b0669 | 1253 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
174edf1f | 1254 | enum port port = intel_dig_port->port; |
c19b0669 | 1255 | uint32_t val; |
f3e227df | 1256 | bool wait = false; |
c19b0669 PZ |
1257 | |
1258 | if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) { | |
1259 | val = I915_READ(DDI_BUF_CTL(port)); | |
1260 | if (val & DDI_BUF_CTL_ENABLE) { | |
1261 | val &= ~DDI_BUF_CTL_ENABLE; | |
1262 | I915_WRITE(DDI_BUF_CTL(port), val); | |
1263 | wait = true; | |
1264 | } | |
1265 | ||
1266 | val = I915_READ(DP_TP_CTL(port)); | |
1267 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
1268 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
1269 | I915_WRITE(DP_TP_CTL(port), val); | |
1270 | POSTING_READ(DP_TP_CTL(port)); | |
1271 | ||
1272 | if (wait) | |
1273 | intel_wait_ddi_buf_idle(dev_priv, port); | |
1274 | } | |
1275 | ||
1276 | val = DP_TP_CTL_ENABLE | DP_TP_CTL_MODE_SST | | |
1277 | DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; | |
6aba5b6c | 1278 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
c19b0669 PZ |
1279 | val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; |
1280 | I915_WRITE(DP_TP_CTL(port), val); | |
1281 | POSTING_READ(DP_TP_CTL(port)); | |
1282 | ||
1283 | intel_dp->DP |= DDI_BUF_CTL_ENABLE; | |
1284 | I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP); | |
1285 | POSTING_READ(DDI_BUF_CTL(port)); | |
1286 | ||
1287 | udelay(600); | |
1288 | } | |
00c09d70 | 1289 | |
1ad960f2 PZ |
1290 | void intel_ddi_fdi_disable(struct drm_crtc *crtc) |
1291 | { | |
1292 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
1293 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
1294 | uint32_t val; | |
1295 | ||
1296 | intel_ddi_post_disable(intel_encoder); | |
1297 | ||
1298 | val = I915_READ(_FDI_RXA_CTL); | |
1299 | val &= ~FDI_RX_ENABLE; | |
1300 | I915_WRITE(_FDI_RXA_CTL, val); | |
1301 | ||
1302 | val = I915_READ(_FDI_RXA_MISC); | |
1303 | val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); | |
1304 | val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); | |
1305 | I915_WRITE(_FDI_RXA_MISC, val); | |
1306 | ||
1307 | val = I915_READ(_FDI_RXA_CTL); | |
1308 | val &= ~FDI_PCDCLK; | |
1309 | I915_WRITE(_FDI_RXA_CTL, val); | |
1310 | ||
1311 | val = I915_READ(_FDI_RXA_CTL); | |
1312 | val &= ~FDI_RX_PLL_ENABLE; | |
1313 | I915_WRITE(_FDI_RXA_CTL, val); | |
1314 | } | |
1315 | ||
00c09d70 PZ |
1316 | static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder) |
1317 | { | |
1318 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
1319 | int type = intel_encoder->type; | |
1320 | ||
1321 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) | |
1322 | intel_dp_check_link_status(intel_dp); | |
1323 | } | |
1324 | ||
6801c18c VS |
1325 | void intel_ddi_get_config(struct intel_encoder *encoder, |
1326 | struct intel_crtc_config *pipe_config) | |
045ac3b5 JB |
1327 | { |
1328 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
1329 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
1330 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; | |
1331 | u32 temp, flags = 0; | |
1332 | ||
1333 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
1334 | if (temp & TRANS_DDI_PHSYNC) | |
1335 | flags |= DRM_MODE_FLAG_PHSYNC; | |
1336 | else | |
1337 | flags |= DRM_MODE_FLAG_NHSYNC; | |
1338 | if (temp & TRANS_DDI_PVSYNC) | |
1339 | flags |= DRM_MODE_FLAG_PVSYNC; | |
1340 | else | |
1341 | flags |= DRM_MODE_FLAG_NVSYNC; | |
1342 | ||
1343 | pipe_config->adjusted_mode.flags |= flags; | |
42571aef VS |
1344 | |
1345 | switch (temp & TRANS_DDI_BPC_MASK) { | |
1346 | case TRANS_DDI_BPC_6: | |
1347 | pipe_config->pipe_bpp = 18; | |
1348 | break; | |
1349 | case TRANS_DDI_BPC_8: | |
1350 | pipe_config->pipe_bpp = 24; | |
1351 | break; | |
1352 | case TRANS_DDI_BPC_10: | |
1353 | pipe_config->pipe_bpp = 30; | |
1354 | break; | |
1355 | case TRANS_DDI_BPC_12: | |
1356 | pipe_config->pipe_bpp = 36; | |
1357 | break; | |
1358 | default: | |
1359 | break; | |
1360 | } | |
eb14cb74 VS |
1361 | |
1362 | switch (temp & TRANS_DDI_MODE_SELECT_MASK) { | |
1363 | case TRANS_DDI_MODE_SELECT_HDMI: | |
1364 | case TRANS_DDI_MODE_SELECT_DVI: | |
1365 | case TRANS_DDI_MODE_SELECT_FDI: | |
1366 | break; | |
1367 | case TRANS_DDI_MODE_SELECT_DP_SST: | |
1368 | case TRANS_DDI_MODE_SELECT_DP_MST: | |
1369 | pipe_config->has_dp_encoder = true; | |
1370 | intel_dp_get_m_n(intel_crtc, pipe_config); | |
1371 | break; | |
1372 | default: | |
1373 | break; | |
1374 | } | |
045ac3b5 JB |
1375 | } |
1376 | ||
00c09d70 PZ |
1377 | static void intel_ddi_destroy(struct drm_encoder *encoder) |
1378 | { | |
1379 | /* HDMI has nothing special to destroy, so we can go with this. */ | |
1380 | intel_dp_encoder_destroy(encoder); | |
1381 | } | |
1382 | ||
5bfe2ac0 DV |
1383 | static bool intel_ddi_compute_config(struct intel_encoder *encoder, |
1384 | struct intel_crtc_config *pipe_config) | |
00c09d70 | 1385 | { |
5bfe2ac0 | 1386 | int type = encoder->type; |
eccb140b | 1387 | int port = intel_ddi_get_encoder_port(encoder); |
00c09d70 | 1388 | |
5bfe2ac0 | 1389 | WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n"); |
00c09d70 | 1390 | |
eccb140b DV |
1391 | if (port == PORT_A) |
1392 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
1393 | ||
00c09d70 | 1394 | if (type == INTEL_OUTPUT_HDMI) |
5bfe2ac0 | 1395 | return intel_hdmi_compute_config(encoder, pipe_config); |
00c09d70 | 1396 | else |
5bfe2ac0 | 1397 | return intel_dp_compute_config(encoder, pipe_config); |
00c09d70 PZ |
1398 | } |
1399 | ||
1400 | static const struct drm_encoder_funcs intel_ddi_funcs = { | |
1401 | .destroy = intel_ddi_destroy, | |
1402 | }; | |
1403 | ||
4a28ae58 PZ |
1404 | static struct intel_connector * |
1405 | intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port) | |
1406 | { | |
1407 | struct intel_connector *connector; | |
1408 | enum port port = intel_dig_port->port; | |
1409 | ||
1410 | connector = kzalloc(sizeof(*connector), GFP_KERNEL); | |
1411 | if (!connector) | |
1412 | return NULL; | |
1413 | ||
1414 | intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); | |
1415 | if (!intel_dp_init_connector(intel_dig_port, connector)) { | |
1416 | kfree(connector); | |
1417 | return NULL; | |
1418 | } | |
1419 | ||
1420 | return connector; | |
1421 | } | |
1422 | ||
1423 | static struct intel_connector * | |
1424 | intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port) | |
1425 | { | |
1426 | struct intel_connector *connector; | |
1427 | enum port port = intel_dig_port->port; | |
1428 | ||
1429 | connector = kzalloc(sizeof(*connector), GFP_KERNEL); | |
1430 | if (!connector) | |
1431 | return NULL; | |
1432 | ||
1433 | intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); | |
1434 | intel_hdmi_init_connector(intel_dig_port, connector); | |
1435 | ||
1436 | return connector; | |
1437 | } | |
1438 | ||
00c09d70 PZ |
1439 | void intel_ddi_init(struct drm_device *dev, enum port port) |
1440 | { | |
876a8cdf | 1441 | struct drm_i915_private *dev_priv = dev->dev_private; |
00c09d70 PZ |
1442 | struct intel_digital_port *intel_dig_port; |
1443 | struct intel_encoder *intel_encoder; | |
1444 | struct drm_encoder *encoder; | |
1445 | struct intel_connector *hdmi_connector = NULL; | |
1446 | struct intel_connector *dp_connector = NULL; | |
311a2094 PZ |
1447 | bool init_hdmi, init_dp; |
1448 | ||
1449 | init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi || | |
1450 | dev_priv->vbt.ddi_port_info[port].supports_hdmi); | |
1451 | init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp; | |
1452 | if (!init_dp && !init_hdmi) { | |
1453 | DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible\n", | |
1454 | port_name(port)); | |
1455 | init_hdmi = true; | |
1456 | init_dp = true; | |
1457 | } | |
00c09d70 | 1458 | |
b14c5679 | 1459 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
00c09d70 PZ |
1460 | if (!intel_dig_port) |
1461 | return; | |
1462 | ||
00c09d70 PZ |
1463 | intel_encoder = &intel_dig_port->base; |
1464 | encoder = &intel_encoder->base; | |
1465 | ||
1466 | drm_encoder_init(dev, encoder, &intel_ddi_funcs, | |
1467 | DRM_MODE_ENCODER_TMDS); | |
00c09d70 | 1468 | |
5bfe2ac0 | 1469 | intel_encoder->compute_config = intel_ddi_compute_config; |
c7d8be30 | 1470 | intel_encoder->mode_set = intel_ddi_mode_set; |
00c09d70 PZ |
1471 | intel_encoder->enable = intel_enable_ddi; |
1472 | intel_encoder->pre_enable = intel_ddi_pre_enable; | |
1473 | intel_encoder->disable = intel_disable_ddi; | |
1474 | intel_encoder->post_disable = intel_ddi_post_disable; | |
1475 | intel_encoder->get_hw_state = intel_ddi_get_hw_state; | |
045ac3b5 | 1476 | intel_encoder->get_config = intel_ddi_get_config; |
00c09d70 PZ |
1477 | |
1478 | intel_dig_port->port = port; | |
bcf53de4 SM |
1479 | intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & |
1480 | (DDI_BUF_PORT_REVERSAL | | |
1481 | DDI_A_4_LANES); | |
00c09d70 PZ |
1482 | |
1483 | intel_encoder->type = INTEL_OUTPUT_UNKNOWN; | |
1484 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
1485 | intel_encoder->cloneable = false; | |
1486 | intel_encoder->hot_plug = intel_ddi_hot_plug; | |
1487 | ||
4a28ae58 PZ |
1488 | if (init_dp) |
1489 | dp_connector = intel_ddi_init_dp_connector(intel_dig_port); | |
21a8e6a4 | 1490 | |
311a2094 PZ |
1491 | /* In theory we don't need the encoder->type check, but leave it just in |
1492 | * case we have some really bad VBTs... */ | |
4a28ae58 PZ |
1493 | if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) |
1494 | hdmi_connector = intel_ddi_init_hdmi_connector(intel_dig_port); | |
21a8e6a4 | 1495 | |
4a28ae58 PZ |
1496 | if (!dp_connector && !hdmi_connector) { |
1497 | drm_encoder_cleanup(encoder); | |
1498 | kfree(intel_dig_port); | |
21a8e6a4 | 1499 | } |
00c09d70 | 1500 | } |