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drm/i915: Close race between processing unpin task and queueing the flip
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ddi.c
CommitLineData
45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include "i915_drv.h"
29#include "intel_drv.h"
30
31/* HDMI/DVI modes ignore everything but the last 2 items. So we share
32 * them for both DP and FDI transports, allowing those ports to
33 * automatically adapt to HDMI connections as well
34 */
35static const u32 hsw_ddi_translations_dp[] = {
36 0x00FFFFFF, 0x0006000E, /* DP parameters */
37 0x00D75FFF, 0x0005000A,
38 0x00C30FFF, 0x00040006,
39 0x80AAAFFF, 0x000B0000,
40 0x00FFFFFF, 0x0005000A,
41 0x00D75FFF, 0x000C0004,
42 0x80C30FFF, 0x000B0000,
43 0x00FFFFFF, 0x00040006,
44 0x80D75FFF, 0x000B0000,
45 0x00FFFFFF, 0x00040006 /* HDMI parameters */
46};
47
48static const u32 hsw_ddi_translations_fdi[] = {
49 0x00FFFFFF, 0x0007000E, /* FDI parameters */
50 0x00D75FFF, 0x000F000A,
51 0x00C30FFF, 0x00060006,
52 0x00AAAFFF, 0x001E0000,
53 0x00FFFFFF, 0x000F000A,
54 0x00D75FFF, 0x00160004,
55 0x00C30FFF, 0x001E0000,
56 0x00FFFFFF, 0x00060006,
57 0x00D75FFF, 0x001E0000,
58 0x00FFFFFF, 0x00040006 /* HDMI parameters */
59};
60
fc914639
PZ		 61static enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
62{
0bdee30e 63 struct drm_encoder *encoder = &intel_encoder->base;
fc914639
PZ		 64 int type = intel_encoder->type;
65
174edf1f 66 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
00c09d70 67 type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
174edf1f
PZ		 68 struct intel_digital_port *intel_dig_port =
69 enc_to_dig_port(encoder);
70 return intel_dig_port->port;
0bdee30e 71
fc914639
PZ		 72 } else if (type == INTEL_OUTPUT_ANALOG) {
73 return PORT_E;
0bdee30e 74
fc914639
PZ		 75 } else {
76 DRM_ERROR("Invalid DDI encoder type %d\n", type);
77 BUG();
78 }
79}
80
45244b87
ED		 81/* On Haswell, DDI port buffers must be programmed with correct values
82 * in advance. The buffer values are different for FDI and DP modes,
83 * but the HDMI/DVI fields are shared among those. So we program the DDI
84 * in either FDI or DP modes only, as HDMI connections will work with both
85 * of those
86 */
87void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port, bool use_fdi_mode)
88{
89 struct drm_i915_private *dev_priv = dev->dev_private;
90 u32 reg;
91 int i;
92 const u32 *ddi_translations = ((use_fdi_mode) ?
93 hsw_ddi_translations_fdi :
94 hsw_ddi_translations_dp);
95
96 DRM_DEBUG_DRIVER("Initializing DDI buffers for port %c in %s mode\n",
97 port_name(port),
98 use_fdi_mode ? "FDI" : "DP");
99
100 WARN((use_fdi_mode && (port != PORT_E)),
101 "Programming port %c in FDI mode, this probably will not work.\n",
102 port_name(port));
103
104 for (i=0, reg=DDI_BUF_TRANS(port); i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
105 I915_WRITE(reg, ddi_translations[i]);
106 reg += 4;
107 }
108}
109
110/* Program DDI buffers translations for DP. By default, program ports A-D in DP
111 * mode and port E for FDI.
112 */
113void intel_prepare_ddi(struct drm_device *dev)
114{
115 int port;
116
117 if (IS_HASWELL(dev)) {
118 for (port = PORT_A; port < PORT_E; port++)
119 intel_prepare_ddi_buffers(dev, port, false);
120
121 /* DDI E is the suggested one to work in FDI mode, so program is as such by
122 * default. It will have to be re-programmed in case a digital DP output
123 * will be detected on it
124 */
125 intel_prepare_ddi_buffers(dev, PORT_E, true);
126 }
127}
c82e4d26
ED		 128
129static const long hsw_ddi_buf_ctl_values[] = {
130 DDI_BUF_EMP_400MV_0DB_HSW,
131 DDI_BUF_EMP_400MV_3_5DB_HSW,
132 DDI_BUF_EMP_400MV_6DB_HSW,
133 DDI_BUF_EMP_400MV_9_5DB_HSW,
134 DDI_BUF_EMP_600MV_0DB_HSW,
135 DDI_BUF_EMP_600MV_3_5DB_HSW,
136 DDI_BUF_EMP_600MV_6DB_HSW,
137 DDI_BUF_EMP_800MV_0DB_HSW,
138 DDI_BUF_EMP_800MV_3_5DB_HSW
139};
140
141
142/* Starting with Haswell, different DDI ports can work in FDI mode for
143 * connection to the PCH-located connectors. For this, it is necessary to train
144 * both the DDI port and PCH receiver for the desired DDI buffer settings.
145 *
146 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
147 * please note that when FDI mode is active on DDI E, it shares 2 lines with
148 * DDI A (which is used for eDP)
149 */
150
151void hsw_fdi_link_train(struct drm_crtc *crtc)
152{
153 struct drm_device *dev = crtc->dev;
154 struct drm_i915_private *dev_priv = dev->dev_private;
155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
04945641 156 u32 temp, i, rx_ctl_val;
c82e4d26 157
04945641
PZ		 158 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
159 * mode set "sequence for CRT port" document:
160 * - TP1 to TP2 time with the default value
161 * - FDI delay to 90h
162 */
163 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
164 FDI_RX_PWRDN_LANE0_VAL(2) |
165 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
166
167 /* Enable the PCH Receiver FDI PLL */
168 rx_ctl_val = FDI_RX_PLL_ENABLE | FDI_RX_ENHANCE_FRAME_ENABLE |
169 ((intel_crtc->fdi_lanes - 1) << 19);
170 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
171 POSTING_READ(_FDI_RXA_CTL);
172 udelay(220);
173
174 /* Switch from Rawclk to PCDclk */
175 rx_ctl_val |= FDI_PCDCLK;
176 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
177
178 /* Configure Port Clock Select */
179 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel);
180
181 /* Start the training iterating through available voltages and emphasis,
182 * testing each value twice. */
183 for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) {
c82e4d26
ED		 184 /* Configure DP_TP_CTL with auto-training */
185 I915_WRITE(DP_TP_CTL(PORT_E),
186 DP_TP_CTL_FDI_AUTOTRAIN |
187 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
188 DP_TP_CTL_LINK_TRAIN_PAT1 |
189 DP_TP_CTL_ENABLE);
190
191 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage */
c82e4d26 192 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641
PZ		 193 DDI_BUF_CTL_ENABLE |
194 ((intel_crtc->fdi_lanes - 1) << 1) |
195 hsw_ddi_buf_ctl_values[i / 2]);
196 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 197
198 udelay(600);
199
04945641
PZ		 200 /* Program PCH FDI Receiver TU */
201 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
202
203 /* Enable PCH FDI Receiver with auto-training */
204 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
205 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
206 POSTING_READ(_FDI_RXA_CTL);
207
208 /* Wait for FDI receiver lane calibration */
209 udelay(30);
210
211 /* Unset FDI_RX_MISC pwrdn lanes */
212 temp = I915_READ(_FDI_RXA_MISC);
213 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
214 I915_WRITE(_FDI_RXA_MISC, temp);
215 POSTING_READ(_FDI_RXA_MISC);
216
217 /* Wait for FDI auto training time */
218 udelay(5);
c82e4d26
ED		 219
220 temp = I915_READ(DP_TP_STATUS(PORT_E));
221 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 222 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
c82e4d26
ED		 223
224 /* Enable normal pixel sending for FDI */
225 I915_WRITE(DP_TP_CTL(PORT_E),
04945641
PZ		 226 DP_TP_CTL_FDI_AUTOTRAIN |
227 DP_TP_CTL_LINK_TRAIN_NORMAL |
228 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
229 DP_TP_CTL_ENABLE);
c82e4d26 230
04945641 231 return;
c82e4d26 232 }
04945641
PZ		 233
234 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
235 I915_WRITE(DP_TP_CTL(PORT_E),
236 I915_READ(DP_TP_CTL(PORT_E)) & ~DP_TP_CTL_ENABLE);
237
238 rx_ctl_val &= ~FDI_RX_ENABLE;
239 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
240
241 /* Reset FDI_RX_MISC pwrdn lanes */
242 temp = I915_READ(_FDI_RXA_MISC);
243 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
244 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
245 I915_WRITE(_FDI_RXA_MISC, temp);
c82e4d26
ED		 246 }
247
04945641 248 DRM_ERROR("FDI link training failed!\n");
c82e4d26 249}
0e72a5b5 250
12a13a33
ED		 251/* WRPLL clock dividers */
252struct wrpll_tmds_clock {
253 u32 clock;
254 u16 p; /* Post divider */
255 u16 n2; /* Feedback divider */
256 u16 r2; /* Reference divider */
257};
258
126e9be8
PZ		 259/* Table of matching values for WRPLL clocks programming for each frequency.
260 * The code assumes this table is sorted. */
12a13a33
ED		 261static const struct wrpll_tmds_clock wrpll_tmds_clock_table[] = {
262 {19750, 38, 25, 18},
263 {20000, 48, 32, 18},
264 {21000, 36, 21, 15},
265 {21912, 42, 29, 17},
266 {22000, 36, 22, 15},
267 {23000, 36, 23, 15},
268 {23500, 40, 40, 23},
269 {23750, 26, 16, 14},
12a13a33
ED		 270 {24000, 36, 24, 15},
271 {25000, 36, 25, 15},
272 {25175, 26, 40, 33},
273 {25200, 30, 21, 15},
274 {26000, 36, 26, 15},
275 {27000, 30, 21, 14},
276 {27027, 18, 100, 111},
277 {27500, 30, 29, 19},
278 {28000, 34, 30, 17},
279 {28320, 26, 30, 22},
280 {28322, 32, 42, 25},
281 {28750, 24, 23, 18},
282 {29000, 30, 29, 18},
283 {29750, 32, 30, 17},
284 {30000, 30, 25, 15},
285 {30750, 30, 41, 24},
286 {31000, 30, 31, 18},
287 {31500, 30, 28, 16},
288 {32000, 30, 32, 18},
289 {32500, 28, 32, 19},
290 {33000, 24, 22, 15},
291 {34000, 28, 30, 17},
292 {35000, 26, 32, 19},
293 {35500, 24, 30, 19},
294 {36000, 26, 26, 15},
295 {36750, 26, 46, 26},
296 {37000, 24, 23, 14},
297 {37762, 22, 40, 26},
298 {37800, 20, 21, 15},
299 {38000, 24, 27, 16},
300 {38250, 24, 34, 20},
301 {39000, 24, 26, 15},
302 {40000, 24, 32, 18},
303 {40500, 20, 21, 14},
304 {40541, 22, 147, 89},
305 {40750, 18, 19, 14},
306 {41000, 16, 17, 14},
307 {41500, 22, 44, 26},
308 {41540, 22, 44, 26},
309 {42000, 18, 21, 15},
310 {42500, 22, 45, 26},
311 {43000, 20, 43, 27},
312 {43163, 20, 24, 15},
313 {44000, 18, 22, 15},
314 {44900, 20, 108, 65},
315 {45000, 20, 25, 15},
316 {45250, 20, 52, 31},
317 {46000, 18, 23, 15},
318 {46750, 20, 45, 26},
319 {47000, 20, 40, 23},
320 {48000, 18, 24, 15},
321 {49000, 18, 49, 30},
322 {49500, 16, 22, 15},
323 {50000, 18, 25, 15},
324 {50500, 18, 32, 19},
325 {51000, 18, 34, 20},
326 {52000, 18, 26, 15},
327 {52406, 14, 34, 25},
328 {53000, 16, 22, 14},
329 {54000, 16, 24, 15},
330 {54054, 16, 173, 108},
331 {54500, 14, 24, 17},
332 {55000, 12, 22, 18},
333 {56000, 14, 45, 31},
334 {56250, 16, 25, 15},
335 {56750, 14, 25, 17},
336 {57000, 16, 27, 16},
337 {58000, 16, 43, 25},
338 {58250, 16, 38, 22},
339 {58750, 16, 40, 23},
340 {59000, 14, 26, 17},
341 {59341, 14, 40, 26},
342 {59400, 16, 44, 25},
343 {60000, 16, 32, 18},
344 {60500, 12, 39, 29},
345 {61000, 14, 49, 31},
346 {62000, 14, 37, 23},
347 {62250, 14, 42, 26},
348 {63000, 12, 21, 15},
349 {63500, 14, 28, 17},
350 {64000, 12, 27, 19},
351 {65000, 14, 32, 19},
352 {65250, 12, 29, 20},
353 {65500, 12, 32, 22},
354 {66000, 12, 22, 15},
355 {66667, 14, 38, 22},
356 {66750, 10, 21, 17},
357 {67000, 14, 33, 19},
358 {67750, 14, 58, 33},
359 {68000, 14, 30, 17},
360 {68179, 14, 46, 26},
361 {68250, 14, 46, 26},
362 {69000, 12, 23, 15},
363 {70000, 12, 28, 18},
364 {71000, 12, 30, 19},
365 {72000, 12, 24, 15},
366 {73000, 10, 23, 17},
367 {74000, 12, 23, 14},
368 {74176, 8, 100, 91},
369 {74250, 10, 22, 16},
370 {74481, 12, 43, 26},
371 {74500, 10, 29, 21},
372 {75000, 12, 25, 15},
373 {75250, 10, 39, 28},
374 {76000, 12, 27, 16},
375 {77000, 12, 53, 31},
376 {78000, 12, 26, 15},
377 {78750, 12, 28, 16},
378 {79000, 10, 38, 26},
379 {79500, 10, 28, 19},
380 {80000, 12, 32, 18},
381 {81000, 10, 21, 14},
382 {81081, 6, 100, 111},
383 {81624, 8, 29, 24},
384 {82000, 8, 17, 14},
385 {83000, 10, 40, 26},
386 {83950, 10, 28, 18},
387 {84000, 10, 28, 18},
388 {84750, 6, 16, 17},
389 {85000, 6, 17, 18},
390 {85250, 10, 30, 19},
391 {85750, 10, 27, 17},
392 {86000, 10, 43, 27},
393 {87000, 10, 29, 18},
394 {88000, 10, 44, 27},
395 {88500, 10, 41, 25},
396 {89000, 10, 28, 17},
397 {89012, 6, 90, 91},
398 {89100, 10, 33, 20},
399 {90000, 10, 25, 15},
400 {91000, 10, 32, 19},
401 {92000, 10, 46, 27},
402 {93000, 10, 31, 18},
403 {94000, 10, 40, 23},
404 {94500, 10, 28, 16},
405 {95000, 10, 44, 25},
406 {95654, 10, 39, 22},
407 {95750, 10, 39, 22},
408 {96000, 10, 32, 18},
409 {97000, 8, 23, 16},
410 {97750, 8, 42, 29},
411 {98000, 8, 45, 31},
412 {99000, 8, 22, 15},
413 {99750, 8, 34, 23},
414 {100000, 6, 20, 18},
415 {100500, 6, 19, 17},
416 {101000, 6, 37, 33},
417 {101250, 8, 21, 14},
418 {102000, 6, 17, 15},
419 {102250, 6, 25, 22},
420 {103000, 8, 29, 19},
421 {104000, 8, 37, 24},
422 {105000, 8, 28, 18},
423 {106000, 8, 22, 14},
424 {107000, 8, 46, 29},
425 {107214, 8, 27, 17},
426 {108000, 8, 24, 15},
427 {108108, 8, 173, 108},
428 {109000, 6, 23, 19},
12a13a33
ED		 429 {110000, 6, 22, 18},
430 {110013, 6, 22, 18},
431 {110250, 8, 49, 30},
432 {110500, 8, 36, 22},
433 {111000, 8, 23, 14},
434 {111264, 8, 150, 91},
435 {111375, 8, 33, 20},
436 {112000, 8, 63, 38},
437 {112500, 8, 25, 15},
438 {113100, 8, 57, 34},
439 {113309, 8, 42, 25},
440 {114000, 8, 27, 16},
441 {115000, 6, 23, 18},
442 {116000, 8, 43, 25},
443 {117000, 8, 26, 15},
444 {117500, 8, 40, 23},
445 {118000, 6, 38, 29},
446 {119000, 8, 30, 17},
447 {119500, 8, 46, 26},
448 {119651, 8, 39, 22},
449 {120000, 8, 32, 18},
450 {121000, 6, 39, 29},
451 {121250, 6, 31, 23},
452 {121750, 6, 23, 17},
453 {122000, 6, 42, 31},
454 {122614, 6, 30, 22},
455 {123000, 6, 41, 30},
456 {123379, 6, 37, 27},
457 {124000, 6, 51, 37},
458 {125000, 6, 25, 18},
459 {125250, 4, 13, 14},
460 {125750, 4, 27, 29},
461 {126000, 6, 21, 15},
462 {127000, 6, 24, 17},
463 {127250, 6, 41, 29},
464 {128000, 6, 27, 19},
465 {129000, 6, 43, 30},
466 {129859, 4, 25, 26},
467 {130000, 6, 26, 18},
468 {130250, 6, 42, 29},
469 {131000, 6, 32, 22},
470 {131500, 6, 38, 26},
471 {131850, 6, 41, 28},
472 {132000, 6, 22, 15},
473 {132750, 6, 28, 19},
474 {133000, 6, 34, 23},
475 {133330, 6, 37, 25},
476 {134000, 6, 61, 41},
477 {135000, 6, 21, 14},
478 {135250, 6, 167, 111},
479 {136000, 6, 62, 41},
480 {137000, 6, 35, 23},
481 {138000, 6, 23, 15},
482 {138500, 6, 40, 26},
483 {138750, 6, 37, 24},
484 {139000, 6, 34, 22},
485 {139050, 6, 34, 22},
486 {139054, 6, 34, 22},
487 {140000, 6, 28, 18},
488 {141000, 6, 36, 23},
489 {141500, 6, 22, 14},
490 {142000, 6, 30, 19},
491 {143000, 6, 27, 17},
492 {143472, 4, 17, 16},
493 {144000, 6, 24, 15},
494 {145000, 6, 29, 18},
495 {146000, 6, 47, 29},
496 {146250, 6, 26, 16},
497 {147000, 6, 49, 30},
498 {147891, 6, 23, 14},
499 {148000, 6, 23, 14},
500 {148250, 6, 28, 17},
501 {148352, 4, 100, 91},
502 {148500, 6, 33, 20},
503 {149000, 6, 48, 29},
504 {150000, 6, 25, 15},
505 {151000, 4, 19, 17},
506 {152000, 6, 27, 16},
507 {152280, 6, 44, 26},
508 {153000, 6, 34, 20},
509 {154000, 6, 53, 31},
510 {155000, 6, 31, 18},
511 {155250, 6, 50, 29},
512 {155750, 6, 45, 26},
513 {156000, 6, 26, 15},
514 {157000, 6, 61, 35},
515 {157500, 6, 28, 16},
516 {158000, 6, 65, 37},
517 {158250, 6, 44, 25},
518 {159000, 6, 53, 30},
519 {159500, 6, 39, 22},
520 {160000, 6, 32, 18},
521 {161000, 4, 31, 26},
522 {162000, 4, 18, 15},
523 {162162, 4, 131, 109},
524 {162500, 4, 53, 44},
525 {163000, 4, 29, 24},
526 {164000, 4, 17, 14},
527 {165000, 4, 22, 18},
528 {166000, 4, 32, 26},
529 {167000, 4, 26, 21},
530 {168000, 4, 46, 37},
531 {169000, 4, 104, 83},
532 {169128, 4, 64, 51},
533 {169500, 4, 39, 31},
534 {170000, 4, 34, 27},
535 {171000, 4, 19, 15},
536 {172000, 4, 51, 40},
537 {172750, 4, 32, 25},
538 {172800, 4, 32, 25},
539 {173000, 4, 41, 32},
540 {174000, 4, 49, 38},
541 {174787, 4, 22, 17},
542 {175000, 4, 35, 27},
543 {176000, 4, 30, 23},
544 {177000, 4, 38, 29},
545 {178000, 4, 29, 22},
546 {178500, 4, 37, 28},
547 {179000, 4, 53, 40},
548 {179500, 4, 73, 55},
549 {180000, 4, 20, 15},
550 {181000, 4, 55, 41},
551 {182000, 4, 31, 23},
552 {183000, 4, 42, 31},
553 {184000, 4, 30, 22},
554 {184750, 4, 26, 19},
555 {185000, 4, 37, 27},
556 {186000, 4, 51, 37},
557 {187000, 4, 36, 26},
558 {188000, 4, 32, 23},
559 {189000, 4, 21, 15},
560 {190000, 4, 38, 27},
561 {190960, 4, 41, 29},
562 {191000, 4, 41, 29},
563 {192000, 4, 27, 19},
564 {192250, 4, 37, 26},
565 {193000, 4, 20, 14},
566 {193250, 4, 53, 37},
567 {194000, 4, 23, 16},
568 {194208, 4, 23, 16},
569 {195000, 4, 26, 18},
570 {196000, 4, 45, 31},
571 {197000, 4, 35, 24},
572 {197750, 4, 41, 28},
573 {198000, 4, 22, 15},
574 {198500, 4, 25, 17},
575 {199000, 4, 28, 19},
576 {200000, 4, 37, 25},
577 {201000, 4, 61, 41},
578 {202000, 4, 112, 75},
579 {202500, 4, 21, 14},
580 {203000, 4, 146, 97},
581 {204000, 4, 62, 41},
582 {204750, 4, 44, 29},
583 {205000, 4, 38, 25},
584 {206000, 4, 29, 19},
585 {207000, 4, 23, 15},
586 {207500, 4, 40, 26},
587 {208000, 4, 37, 24},
588 {208900, 4, 48, 31},
589 {209000, 4, 48, 31},
590 {209250, 4, 31, 20},
591 {210000, 4, 28, 18},
592 {211000, 4, 25, 16},
593 {212000, 4, 22, 14},
594 {213000, 4, 30, 19},
595 {213750, 4, 38, 24},
596 {214000, 4, 46, 29},
597 {214750, 4, 35, 22},
598 {215000, 4, 43, 27},
599 {216000, 4, 24, 15},
600 {217000, 4, 37, 23},
601 {218000, 4, 42, 26},
602 {218250, 4, 42, 26},
603 {218750, 4, 34, 21},
604 {219000, 4, 47, 29},
12a13a33
ED		 605 {220000, 4, 44, 27},
606 {220640, 4, 49, 30},
607 {220750, 4, 36, 22},
608 {221000, 4, 36, 22},
609 {222000, 4, 23, 14},
610 {222525, 4, 28, 17},
611 {222750, 4, 33, 20},
612 {227000, 4, 37, 22},
613 {230250, 4, 29, 17},
614 {233500, 4, 38, 22},
615 {235000, 4, 40, 23},
616 {238000, 4, 30, 17},
617 {241500, 2, 17, 19},
618 {245250, 2, 20, 22},
619 {247750, 2, 22, 24},
620 {253250, 2, 15, 16},
621 {256250, 2, 18, 19},
622 {262500, 2, 31, 32},
623 {267250, 2, 66, 67},
624 {268500, 2, 94, 95},
625 {270000, 2, 14, 14},
626 {272500, 2, 77, 76},
627 {273750, 2, 57, 56},
628 {280750, 2, 24, 23},
629 {281250, 2, 23, 22},
630 {286000, 2, 17, 16},
631 {291750, 2, 26, 24},
632 {296703, 2, 56, 51},
633 {297000, 2, 22, 20},
634 {298000, 2, 21, 19},
635};
72662e10 636
00c09d70
PZ		 637static void intel_ddi_mode_set(struct drm_encoder *encoder,
638 struct drm_display_mode *mode,
639 struct drm_display_mode *adjusted_mode)
72662e10 640{
72662e10
ED		 641 struct drm_crtc *crtc = encoder->crtc;
642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
247d89f6
PZ		 643 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
644 int port = intel_ddi_get_encoder_port(intel_encoder);
72662e10 645 int pipe = intel_crtc->pipe;
247d89f6 646 int type = intel_encoder->type;
72662e10 647
247d89f6
PZ		 648 DRM_DEBUG_KMS("Preparing DDI mode for Haswell on port %c, pipe %c\n",
649 port_name(port), pipe_name(pipe));
72662e10 650
247d89f6
PZ		 651 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
652 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4f07854d 653
247d89f6
PZ		 654 intel_dp->DP = DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW;
655 switch (intel_dp->lane_count) {
656 case 1:
657 intel_dp->DP |= DDI_PORT_WIDTH_X1;
658 break;
659 case 2:
660 intel_dp->DP |= DDI_PORT_WIDTH_X2;
661 break;
662 case 4:
663 intel_dp->DP |= DDI_PORT_WIDTH_X4;
664 break;
665 default:
666 intel_dp->DP |= DDI_PORT_WIDTH_X4;
667 WARN(1, "Unexpected DP lane count %d\n",
668 intel_dp->lane_count);
669 break;
670 }
671
8fed6193
TI		 672 if (intel_dp->has_audio) {
673 DRM_DEBUG_DRIVER("DP audio on pipe %c on DDI\n",
674 pipe_name(intel_crtc->pipe));
675
676 /* write eld */
677 DRM_DEBUG_DRIVER("DP audio: write eld information\n");
678 intel_write_eld(encoder, adjusted_mode);
679 }
680
247d89f6
PZ		 681 intel_dp_init_link_config(intel_dp);
682
683 } else if (type == INTEL_OUTPUT_HDMI) {
684 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
685
686 if (intel_hdmi->has_audio) {
687 /* Proper support for digital audio needs a new logic
688 * and a new set of registers, so we leave it for future
689 * patch bombing.
690 */
691 DRM_DEBUG_DRIVER("HDMI audio on pipe %c on DDI\n",
692 pipe_name(intel_crtc->pipe));
693
694 /* write eld */
695 DRM_DEBUG_DRIVER("HDMI audio: write eld information\n");
696 intel_write_eld(encoder, adjusted_mode);
697 }
72662e10 698
247d89f6
PZ		 699 intel_hdmi->set_infoframes(encoder, adjusted_mode);
700 }
8d9ddbcb
PZ		 701}
702
703static struct intel_encoder *
704intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
705{
706 struct drm_device *dev = crtc->dev;
707 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
708 struct intel_encoder *intel_encoder, *ret = NULL;
709 int num_encoders = 0;
710
711 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
712 ret = intel_encoder;
713 num_encoders++;
714 }
715
716 if (num_encoders != 1)
717 WARN(1, "%d encoders on crtc for pipe %d\n", num_encoders,
718 intel_crtc->pipe);
719
720 BUG_ON(ret == NULL);
721 return ret;
722}
723
6441ab5f
PZ		 724void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
725{
726 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
727 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
728 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
729 uint32_t val;
730
731 switch (intel_crtc->ddi_pll_sel) {
732 case PORT_CLK_SEL_SPLL:
733 plls->spll_refcount--;
734 if (plls->spll_refcount == 0) {
735 DRM_DEBUG_KMS("Disabling SPLL\n");
736 val = I915_READ(SPLL_CTL);
737 WARN_ON(!(val & SPLL_PLL_ENABLE));
738 I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
739 POSTING_READ(SPLL_CTL);
740 }
741 break;
742 case PORT_CLK_SEL_WRPLL1:
743 plls->wrpll1_refcount--;
744 if (plls->wrpll1_refcount == 0) {
745 DRM_DEBUG_KMS("Disabling WRPLL 1\n");
746 val = I915_READ(WRPLL_CTL1);
747 WARN_ON(!(val & WRPLL_PLL_ENABLE));
748 I915_WRITE(WRPLL_CTL1, val & ~WRPLL_PLL_ENABLE);
749 POSTING_READ(WRPLL_CTL1);
750 }
751 break;
752 case PORT_CLK_SEL_WRPLL2:
753 plls->wrpll2_refcount--;
754 if (plls->wrpll2_refcount == 0) {
755 DRM_DEBUG_KMS("Disabling WRPLL 2\n");
756 val = I915_READ(WRPLL_CTL2);
757 WARN_ON(!(val & WRPLL_PLL_ENABLE));
758 I915_WRITE(WRPLL_CTL2, val & ~WRPLL_PLL_ENABLE);
759 POSTING_READ(WRPLL_CTL2);
760 }
761 break;
762 }
763
764 WARN(plls->spll_refcount < 0, "Invalid SPLL refcount\n");
765 WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n");
766 WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n");
767
768 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_NONE;
769}
770
771static void intel_ddi_calculate_wrpll(int clock, int *p, int *n2, int *r2)
772{
773 u32 i;
774
775 for (i = 0; i < ARRAY_SIZE(wrpll_tmds_clock_table); i++)
776 if (clock <= wrpll_tmds_clock_table[i].clock)
777 break;
778
779 if (i == ARRAY_SIZE(wrpll_tmds_clock_table))
780 i--;
781
782 *p = wrpll_tmds_clock_table[i].p;
783 *n2 = wrpll_tmds_clock_table[i].n2;
784 *r2 = wrpll_tmds_clock_table[i].r2;
785
786 if (wrpll_tmds_clock_table[i].clock != clock)
787 DRM_INFO("WRPLL: using settings for %dKHz on %dKHz mode\n",
788 wrpll_tmds_clock_table[i].clock, clock);
789
790 DRM_DEBUG_KMS("WRPLL: %dKHz refresh rate with p=%d, n2=%d r2=%d\n",
791 clock, *p, *n2, *r2);
792}
793
794bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock)
795{
796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
797 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
068759bd 798 struct drm_encoder *encoder = &intel_encoder->base;
6441ab5f
PZ		 799 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
800 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
801 int type = intel_encoder->type;
802 enum pipe pipe = intel_crtc->pipe;
803 uint32_t reg, val;
804
805 /* TODO: reuse PLLs when possible (compare values) */
806
807 intel_ddi_put_crtc_pll(crtc);
808
068759bd
PZ		 809 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
810 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
811
812 switch (intel_dp->link_bw) {
813 case DP_LINK_BW_1_62:
814 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
815 break;
816 case DP_LINK_BW_2_7:
817 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
818 break;
819 case DP_LINK_BW_5_4:
820 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
821 break;
822 default:
823 DRM_ERROR("Link bandwidth %d unsupported\n",
824 intel_dp->link_bw);
825 return false;
826 }
827
828 /* We don't need to turn any PLL on because we'll use LCPLL. */
829 return true;
830
831 } else if (type == INTEL_OUTPUT_HDMI) {
6441ab5f
PZ		 832 int p, n2, r2;
833
834 if (plls->wrpll1_refcount == 0) {
835 DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n",
836 pipe_name(pipe));
837 plls->wrpll1_refcount++;
838 reg = WRPLL_CTL1;
839 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL1;
840 } else if (plls->wrpll2_refcount == 0) {
841 DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n",
842 pipe_name(pipe));
843 plls->wrpll2_refcount++;
844 reg = WRPLL_CTL2;
845 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
846 } else {
847 DRM_ERROR("No WRPLLs available!\n");
848 return false;
849 }
850
851 WARN(I915_READ(reg) & WRPLL_PLL_ENABLE,
852 "WRPLL already enabled\n");
853
854 intel_ddi_calculate_wrpll(clock, &p, &n2, &r2);
855
856 val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 |
857 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
858 WRPLL_DIVIDER_POST(p);
859
860 } else if (type == INTEL_OUTPUT_ANALOG) {
861 if (plls->spll_refcount == 0) {
862 DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
863 pipe_name(pipe));
864 plls->spll_refcount++;
865 reg = SPLL_CTL;
866 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL;
867 }
868
869 WARN(I915_READ(reg) & SPLL_PLL_ENABLE,
870 "SPLL already enabled\n");
871
39bc66c9 872 val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC;
6441ab5f
PZ		 873
874 } else {
875 WARN(1, "Invalid DDI encoder type %d\n", type);
876 return false;
877 }
878
879 I915_WRITE(reg, val);
880 udelay(20);
881
882 return true;
883}
884
dae84799
PZ		 885void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
886{
887 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
888 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
889 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
c9809791 890 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
dae84799
PZ		 891 int type = intel_encoder->type;
892 uint32_t temp;
893
894 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
895
c9809791 896 temp = TRANS_MSA_SYNC_CLK;
dae84799
PZ		 897 switch (intel_crtc->bpp) {
898 case 18:
c9809791 899 temp |= TRANS_MSA_6_BPC;
dae84799
PZ		 900 break;
901 case 24:
c9809791 902 temp |= TRANS_MSA_8_BPC;
dae84799
PZ		 903 break;
904 case 30:
c9809791 905 temp |= TRANS_MSA_10_BPC;
dae84799
PZ		 906 break;
907 case 36:
c9809791 908 temp |= TRANS_MSA_12_BPC;
dae84799
PZ		 909 break;
910 default:
c9809791
PZ		 911 temp |= TRANS_MSA_8_BPC;
912 WARN(1, "%d bpp unsupported by DDI function\n",
dae84799
PZ		 913 intel_crtc->bpp);
914 }
c9809791 915 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 916 }
917}
918
8d9ddbcb
PZ		 919void intel_ddi_enable_pipe_func(struct drm_crtc *crtc)
920{
921 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
922 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
7739c33b 923 struct drm_encoder *encoder = &intel_encoder->base;
8d9ddbcb
PZ		 924 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
925 enum pipe pipe = intel_crtc->pipe;
ad80a810 926 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
174edf1f 927 enum port port = intel_ddi_get_encoder_port(intel_encoder);
7739c33b 928 int type = intel_encoder->type;
8d9ddbcb
PZ		 929 uint32_t temp;
930
ad80a810
PZ		 931 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
932 temp = TRANS_DDI_FUNC_ENABLE;
174edf1f 933 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252
PZ		 934
935 switch (intel_crtc->bpp) {
936 case 18:
ad80a810 937 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 938 break;
939 case 24:
ad80a810 940 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 941 break;
942 case 30:
ad80a810 943 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 944 break;
945 case 36:
ad80a810 946 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 947 break;
948 default:
ad80a810 949 WARN(1, "%d bpp unsupported by transcoder DDI function\n",
dfcef252
PZ		 950 intel_crtc->bpp);
951 }
72662e10 952
8d9ddbcb 953 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 954 temp |= TRANS_DDI_PVSYNC;
8d9ddbcb 955 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 956 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 957
e6f0bfc4
PZ		 958 if (cpu_transcoder == TRANSCODER_EDP) {
959 switch (pipe) {
960 case PIPE_A:
961 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
962 break;
963 case PIPE_B:
964 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
965 break;
966 case PIPE_C:
967 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
968 break;
969 default:
970 BUG();
971 break;
972 }
973 }
974
7739c33b
PZ		 975 if (type == INTEL_OUTPUT_HDMI) {
976 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
8d9ddbcb
PZ		 977
978 if (intel_hdmi->has_hdmi_sink)
ad80a810 979 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 980 else
ad80a810 981 temp |= TRANS_DDI_MODE_SELECT_DVI;
8d9ddbcb 982
7739c33b 983 } else if (type == INTEL_OUTPUT_ANALOG) {
ad80a810 984 temp |= TRANS_DDI_MODE_SELECT_FDI;
349d7e5d 985 temp |= (intel_crtc->fdi_lanes - 1) << 1;
7739c33b
PZ		 986
987 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
988 type == INTEL_OUTPUT_EDP) {
989 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
990
ad80a810 991 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
7739c33b
PZ		 992
993 switch (intel_dp->lane_count) {
994 case 1:
ad80a810 995 temp |= TRANS_DDI_PORT_WIDTH_X1;
7739c33b
PZ		 996 break;
997 case 2:
ad80a810 998 temp |= TRANS_DDI_PORT_WIDTH_X2;
7739c33b
PZ		 999 break;
1000 case 4:
ad80a810 1001 temp |= TRANS_DDI_PORT_WIDTH_X4;
7739c33b
PZ		 1002 break;
1003 default:
ad80a810 1004 temp |= TRANS_DDI_PORT_WIDTH_X4;
7739c33b
PZ		 1005 WARN(1, "Unsupported lane count %d\n",
1006 intel_dp->lane_count);
1007 }
1008
8d9ddbcb
PZ		 1009 } else {
1010 WARN(1, "Invalid encoder type %d for pipe %d\n",
1011 intel_encoder->type, pipe);
1012 }
1013
ad80a810 1014 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 1015}
72662e10 1016
ad80a810
PZ		 1017void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1018 enum transcoder cpu_transcoder)
8d9ddbcb 1019{
ad80a810 1020 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
8d9ddbcb
PZ		 1021 uint32_t val = I915_READ(reg);
1022
ad80a810
PZ		 1023 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK);
1024 val |= TRANS_DDI_PORT_NONE;
8d9ddbcb 1025 I915_WRITE(reg, val);
72662e10
ED		 1026}
1027
bcbc889b
PZ		 1028bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1029{
1030 struct drm_device *dev = intel_connector->base.dev;
1031 struct drm_i915_private *dev_priv = dev->dev_private;
1032 struct intel_encoder *intel_encoder = intel_connector->encoder;
1033 int type = intel_connector->base.connector_type;
1034 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1035 enum pipe pipe = 0;
1036 enum transcoder cpu_transcoder;
1037 uint32_t tmp;
1038
1039 if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1040 return false;
1041
1042 if (port == PORT_A)
1043 cpu_transcoder = TRANSCODER_EDP;
1044 else
1045 cpu_transcoder = pipe;
1046
1047 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1048
1049 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1050 case TRANS_DDI_MODE_SELECT_HDMI:
1051 case TRANS_DDI_MODE_SELECT_DVI:
1052 return (type == DRM_MODE_CONNECTOR_HDMIA);
1053
1054 case TRANS_DDI_MODE_SELECT_DP_SST:
1055 if (type == DRM_MODE_CONNECTOR_eDP)
1056 return true;
1057 case TRANS_DDI_MODE_SELECT_DP_MST:
1058 return (type == DRM_MODE_CONNECTOR_DisplayPort);
1059
1060 case TRANS_DDI_MODE_SELECT_FDI:
1061 return (type == DRM_MODE_CONNECTOR_VGA);
1062
1063 default:
1064 return false;
1065 }
1066}
1067
85234cdc
DV		 1068bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1069 enum pipe *pipe)
1070{
1071 struct drm_device *dev = encoder->base.dev;
1072 struct drm_i915_private *dev_priv = dev->dev_private;
fe43d3f5 1073 enum port port = intel_ddi_get_encoder_port(encoder);
85234cdc
DV		 1074 u32 tmp;
1075 int i;
1076
fe43d3f5 1077 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc
DV		 1078
1079 if (!(tmp & DDI_BUF_CTL_ENABLE))
1080 return false;
1081
ad80a810
PZ		 1082 if (port == PORT_A) {
1083 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 1084
ad80a810
PZ		 1085 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1086 case TRANS_DDI_EDP_INPUT_A_ON:
1087 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1088 *pipe = PIPE_A;
1089 break;
1090 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1091 *pipe = PIPE_B;
1092 break;
1093 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1094 *pipe = PIPE_C;
1095 break;
1096 }
1097
1098 return true;
1099 } else {
1100 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1101 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1102
1103 if ((tmp & TRANS_DDI_PORT_MASK)
1104 == TRANS_DDI_SELECT_PORT(port)) {
1105 *pipe = i;
1106 return true;
1107 }
85234cdc
DV		 1108 }
1109 }
1110
fe43d3f5 1111 DRM_DEBUG_KMS("No pipe for ddi port %i found\n", port);
85234cdc
DV		 1112
1113 return true;
1114}
1115
6441ab5f
PZ		 1116static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv,
1117 enum pipe pipe)
1118{
1119 uint32_t temp, ret;
1120 enum port port;
ad80a810
PZ		 1121 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1122 pipe);
6441ab5f
PZ		 1123 int i;
1124
ad80a810
PZ		 1125 if (cpu_transcoder == TRANSCODER_EDP) {
1126 port = PORT_A;
1127 } else {
1128 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1129 temp &= TRANS_DDI_PORT_MASK;
1130
1131 for (i = PORT_B; i <= PORT_E; i++)
1132 if (temp == TRANS_DDI_SELECT_PORT(i))
1133 port = i;
1134 }
6441ab5f
PZ		 1135
1136 ret = I915_READ(PORT_CLK_SEL(port));
1137
1138 DRM_DEBUG_KMS("Pipe %c connected to port %c using clock 0x%08x\n",
1139 pipe_name(pipe), port_name(port), ret);
1140
1141 return ret;
1142}
1143
1144void intel_ddi_setup_hw_pll_state(struct drm_device *dev)
1145{
1146 struct drm_i915_private *dev_priv = dev->dev_private;
1147 enum pipe pipe;
1148 struct intel_crtc *intel_crtc;
1149
1150 for_each_pipe(pipe) {
1151 intel_crtc =
1152 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1153
1154 if (!intel_crtc->active)
1155 continue;
1156
1157 intel_crtc->ddi_pll_sel = intel_ddi_get_crtc_pll(dev_priv,
1158 pipe);
1159
1160 switch (intel_crtc->ddi_pll_sel) {
1161 case PORT_CLK_SEL_SPLL:
1162 dev_priv->ddi_plls.spll_refcount++;
1163 break;
1164 case PORT_CLK_SEL_WRPLL1:
1165 dev_priv->ddi_plls.wrpll1_refcount++;
1166 break;
1167 case PORT_CLK_SEL_WRPLL2:
1168 dev_priv->ddi_plls.wrpll2_refcount++;
1169 break;
1170 }
1171 }
1172}
1173
fc914639
PZ		 1174void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1175{
1176 struct drm_crtc *crtc = &intel_crtc->base;
1177 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1178 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1179 enum port port = intel_ddi_get_encoder_port(intel_encoder);
bb523fc0 1180 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
fc914639 1181
bb523fc0
PZ		 1182 if (cpu_transcoder != TRANSCODER_EDP)
1183 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1184 TRANS_CLK_SEL_PORT(port));
fc914639
PZ		 1185}
1186
1187void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1188{
1189 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
bb523fc0 1190 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
fc914639 1191
bb523fc0
PZ		 1192 if (cpu_transcoder != TRANSCODER_EDP)
1193 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1194 TRANS_CLK_SEL_DISABLED);
fc914639
PZ		 1195}
1196
00c09d70 1197static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
6441ab5f 1198{
c19b0669
PZ		 1199 struct drm_encoder *encoder = &intel_encoder->base;
1200 struct drm_crtc *crtc = encoder->crtc;
1201 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
6441ab5f
PZ		 1202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1203 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 1204 int type = intel_encoder->type;
6441ab5f 1205
82a4d9c0
PZ		 1206 if (type == INTEL_OUTPUT_EDP) {
1207 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1208 ironlake_edp_panel_vdd_on(intel_dp);
1209 ironlake_edp_panel_on(intel_dp);
1210 ironlake_edp_panel_vdd_off(intel_dp, true);
1211 }
6441ab5f 1212
82a4d9c0 1213 WARN_ON(intel_crtc->ddi_pll_sel == PORT_CLK_SEL_NONE);
6441ab5f 1214 I915_WRITE(PORT_CLK_SEL(port), intel_crtc->ddi_pll_sel);
c19b0669 1215
82a4d9c0 1216 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
c19b0669
PZ		 1217 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1218
1219 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1220 intel_dp_start_link_train(intel_dp);
1221 intel_dp_complete_link_train(intel_dp);
1222 }
6441ab5f
PZ		 1223}
1224
2886e93f
PZ		 1225static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
1226 enum port port)
1227{
1228 uint32_t reg = DDI_BUF_CTL(port);
1229 int i;
1230
1231 for (i = 0; i < 8; i++) {
1232 udelay(1);
1233 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
1234 return;
1235 }
1236 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
1237}
1238
00c09d70 1239static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
6441ab5f
PZ		 1240{
1241 struct drm_encoder *encoder = &intel_encoder->base;
1242 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1243 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 1244 int type = intel_encoder->type;
2886e93f 1245 uint32_t val;
a836bdf9 1246 bool wait = false;
2886e93f
PZ		 1247
1248 val = I915_READ(DDI_BUF_CTL(port));
1249 if (val & DDI_BUF_CTL_ENABLE) {
1250 val &= ~DDI_BUF_CTL_ENABLE;
1251 I915_WRITE(DDI_BUF_CTL(port), val);
a836bdf9 1252 wait = true;
2886e93f 1253 }
6441ab5f 1254
a836bdf9
PZ		 1255 val = I915_READ(DP_TP_CTL(port));
1256 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1257 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1258 I915_WRITE(DP_TP_CTL(port), val);
1259
1260 if (wait)
1261 intel_wait_ddi_buf_idle(dev_priv, port);
1262
82a4d9c0
PZ		 1263 if (type == INTEL_OUTPUT_EDP) {
1264 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1265 ironlake_edp_panel_vdd_on(intel_dp);
1266 ironlake_edp_panel_off(intel_dp);
1267 }
1268
6441ab5f
PZ		 1269 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1270}
1271
00c09d70 1272static void intel_enable_ddi(struct intel_encoder *intel_encoder)
72662e10 1273{
6547fef8
PZ		 1274 struct drm_encoder *encoder = &intel_encoder->base;
1275 struct drm_device *dev = encoder->dev;
72662e10 1276 struct drm_i915_private *dev_priv = dev->dev_private;
6547fef8
PZ		 1277 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1278 int type = intel_encoder->type;
72662e10 1279
6547fef8
PZ		 1280 if (type == INTEL_OUTPUT_HDMI) {
1281 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1282 * are ignored so nothing special needs to be done besides
1283 * enabling the port.
1284 */
1285 I915_WRITE(DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE);
d6c50ff8
PZ		 1286 } else if (type == INTEL_OUTPUT_EDP) {
1287 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1288
1289 ironlake_edp_backlight_on(intel_dp);
6547fef8 1290 }
5ab432ef
DV		 1291}
1292
00c09d70 1293static void intel_disable_ddi(struct intel_encoder *intel_encoder)
5ab432ef 1294{
d6c50ff8
PZ		 1295 struct drm_encoder *encoder = &intel_encoder->base;
1296 int type = intel_encoder->type;
1297
1298 if (type == INTEL_OUTPUT_EDP) {
1299 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1300
1301 ironlake_edp_backlight_off(intel_dp);
1302 }
72662e10 1303}
79f689aa 1304
b8fc2f6a 1305int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
79f689aa
PZ		 1306{
1307 if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT)
1308 return 450;
1309 else if ((I915_READ(LCPLL_CTL) & LCPLL_CLK_FREQ_MASK) ==
1310 LCPLL_CLK_FREQ_450)
1311 return 450;
d567b07f
PZ		 1312 else if (IS_ULT(dev_priv->dev))
1313 return 338;
79f689aa
PZ		 1314 else
1315 return 540;
1316}
1317
1318void intel_ddi_pll_init(struct drm_device *dev)
1319{
1320 struct drm_i915_private *dev_priv = dev->dev_private;
1321 uint32_t val = I915_READ(LCPLL_CTL);
1322
1323 /* The LCPLL register should be turned on by the BIOS. For now let's
1324 * just check its state and print errors in case something is wrong.
1325 * Don't even try to turn it on.
1326 */
1327
1328 DRM_DEBUG_KMS("CDCLK running at %dMHz\n",
1329 intel_ddi_get_cdclk_freq(dev_priv));
1330
1331 if (val & LCPLL_CD_SOURCE_FCLK)
1332 DRM_ERROR("CDCLK source is not LCPLL\n");
1333
1334 if (val & LCPLL_PLL_DISABLE)
1335 DRM_ERROR("LCPLL is disabled\n");
1336}
c19b0669
PZ		 1337
1338void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
1339{
174edf1f
PZ		 1340 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
1341 struct intel_dp *intel_dp = &intel_dig_port->dp;
c19b0669 1342 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
174edf1f 1343 enum port port = intel_dig_port->port;
c19b0669
PZ		 1344 bool wait;
1345 uint32_t val;
1346
1347 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
1348 val = I915_READ(DDI_BUF_CTL(port));
1349 if (val & DDI_BUF_CTL_ENABLE) {
1350 val &= ~DDI_BUF_CTL_ENABLE;
1351 I915_WRITE(DDI_BUF_CTL(port), val);
1352 wait = true;
1353 }
1354
1355 val = I915_READ(DP_TP_CTL(port));
1356 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1357 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1358 I915_WRITE(DP_TP_CTL(port), val);
1359 POSTING_READ(DP_TP_CTL(port));
1360
1361 if (wait)
1362 intel_wait_ddi_buf_idle(dev_priv, port);
1363 }
1364
1365 val = DP_TP_CTL_ENABLE | DP_TP_CTL_MODE_SST |
1366 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
1367 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
1368 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
1369 I915_WRITE(DP_TP_CTL(port), val);
1370 POSTING_READ(DP_TP_CTL(port));
1371
1372 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
1373 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
1374 POSTING_READ(DDI_BUF_CTL(port));
1375
1376 udelay(600);
1377}
00c09d70 1378
1ad960f2
PZ		 1379void intel_ddi_fdi_disable(struct drm_crtc *crtc)
1380{
1381 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1382 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1383 uint32_t val;
1384
1385 intel_ddi_post_disable(intel_encoder);
1386
1387 val = I915_READ(_FDI_RXA_CTL);
1388 val &= ~FDI_RX_ENABLE;
1389 I915_WRITE(_FDI_RXA_CTL, val);
1390
1391 val = I915_READ(_FDI_RXA_MISC);
1392 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1393 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1394 I915_WRITE(_FDI_RXA_MISC, val);
1395
1396 val = I915_READ(_FDI_RXA_CTL);
1397 val &= ~FDI_PCDCLK;
1398 I915_WRITE(_FDI_RXA_CTL, val);
1399
1400 val = I915_READ(_FDI_RXA_CTL);
1401 val &= ~FDI_RX_PLL_ENABLE;
1402 I915_WRITE(_FDI_RXA_CTL, val);
1403}
1404
00c09d70
PZ		 1405static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
1406{
1407 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
1408 int type = intel_encoder->type;
1409
1410 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP)
1411 intel_dp_check_link_status(intel_dp);
1412}
1413
1414static void intel_ddi_destroy(struct drm_encoder *encoder)
1415{
1416 /* HDMI has nothing special to destroy, so we can go with this. */
1417 intel_dp_encoder_destroy(encoder);
1418}
1419
1420static bool intel_ddi_mode_fixup(struct drm_encoder *encoder,
1421 const struct drm_display_mode *mode,
1422 struct drm_display_mode *adjusted_mode)
1423{
1424 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1425 int type = intel_encoder->type;
1426
1427 WARN(type == INTEL_OUTPUT_UNKNOWN, "mode_fixup() on unknown output!\n");
1428
1429 if (type == INTEL_OUTPUT_HDMI)
1430 return intel_hdmi_mode_fixup(encoder, mode, adjusted_mode);
1431 else
1432 return intel_dp_mode_fixup(encoder, mode, adjusted_mode);
1433}
1434
1435static const struct drm_encoder_funcs intel_ddi_funcs = {
1436 .destroy = intel_ddi_destroy,
1437};
1438
1439static const struct drm_encoder_helper_funcs intel_ddi_helper_funcs = {
1440 .mode_fixup = intel_ddi_mode_fixup,
1441 .mode_set = intel_ddi_mode_set,
1442 .disable = intel_encoder_noop,
1443};
1444
1445void intel_ddi_init(struct drm_device *dev, enum port port)
1446{
1447 struct intel_digital_port *intel_dig_port;
1448 struct intel_encoder *intel_encoder;
1449 struct drm_encoder *encoder;
1450 struct intel_connector *hdmi_connector = NULL;
1451 struct intel_connector *dp_connector = NULL;
1452
1453 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
1454 if (!intel_dig_port)
1455 return;
1456
1457 dp_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1458 if (!dp_connector) {
1459 kfree(intel_dig_port);
1460 return;
1461 }
1462
1463 if (port != PORT_A) {
1464 hdmi_connector = kzalloc(sizeof(struct intel_connector),
1465 GFP_KERNEL);
1466 if (!hdmi_connector) {
1467 kfree(dp_connector);
1468 kfree(intel_dig_port);
1469 return;
1470 }
1471 }
1472
1473 intel_encoder = &intel_dig_port->base;
1474 encoder = &intel_encoder->base;
1475
1476 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
1477 DRM_MODE_ENCODER_TMDS);
1478 drm_encoder_helper_add(encoder, &intel_ddi_helper_funcs);
1479
1480 intel_encoder->enable = intel_enable_ddi;
1481 intel_encoder->pre_enable = intel_ddi_pre_enable;
1482 intel_encoder->disable = intel_disable_ddi;
1483 intel_encoder->post_disable = intel_ddi_post_disable;
1484 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
1485
1486 intel_dig_port->port = port;
1487 if (hdmi_connector)
1488 intel_dig_port->hdmi.sdvox_reg = DDI_BUF_CTL(port);
1489 else
1490 intel_dig_port->hdmi.sdvox_reg = 0;
1491 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
1492
1493 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
1494 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1495 intel_encoder->cloneable = false;
1496 intel_encoder->hot_plug = intel_ddi_hot_plug;
1497
1498 if (hdmi_connector)
1499 intel_hdmi_init_connector(intel_dig_port, hdmi_connector);
1500 intel_dp_init_connector(intel_dig_port, dp_connector);
1501}
Linux kernel - Deliverables
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