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drm/i915: add haswell_set_pipeconf
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ddi.c
CommitLineData
45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include "i915_drv.h"
29#include "intel_drv.h"
30
31/* HDMI/DVI modes ignore everything but the last 2 items. So we share
32 * them for both DP and FDI transports, allowing those ports to
33 * automatically adapt to HDMI connections as well
34 */
35static const u32 hsw_ddi_translations_dp[] = {
36 0x00FFFFFF, 0x0006000E, /* DP parameters */
37 0x00D75FFF, 0x0005000A,
38 0x00C30FFF, 0x00040006,
39 0x80AAAFFF, 0x000B0000,
40 0x00FFFFFF, 0x0005000A,
41 0x00D75FFF, 0x000C0004,
42 0x80C30FFF, 0x000B0000,
43 0x00FFFFFF, 0x00040006,
44 0x80D75FFF, 0x000B0000,
45 0x00FFFFFF, 0x00040006 /* HDMI parameters */
46};
47
48static const u32 hsw_ddi_translations_fdi[] = {
49 0x00FFFFFF, 0x0007000E, /* FDI parameters */
50 0x00D75FFF, 0x000F000A,
51 0x00C30FFF, 0x00060006,
52 0x00AAAFFF, 0x001E0000,
53 0x00FFFFFF, 0x000F000A,
54 0x00D75FFF, 0x00160004,
55 0x00C30FFF, 0x001E0000,
56 0x00FFFFFF, 0x00060006,
57 0x00D75FFF, 0x001E0000,
58 0x00FFFFFF, 0x00040006 /* HDMI parameters */
59};
60
fc914639
PZ		 61static enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
62{
63 int type = intel_encoder->type;
64
65 if (type == INTEL_OUTPUT_HDMI) {
66 struct intel_hdmi *intel_hdmi =
67 enc_to_intel_hdmi(&intel_encoder->base);
68 return intel_hdmi->ddi_port;
69 } else if (type == INTEL_OUTPUT_ANALOG) {
70 return PORT_E;
71 } else {
72 DRM_ERROR("Invalid DDI encoder type %d\n", type);
73 BUG();
74 }
75}
76
45244b87
ED		 77/* On Haswell, DDI port buffers must be programmed with correct values
78 * in advance. The buffer values are different for FDI and DP modes,
79 * but the HDMI/DVI fields are shared among those. So we program the DDI
80 * in either FDI or DP modes only, as HDMI connections will work with both
81 * of those
82 */
83void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port, bool use_fdi_mode)
84{
85 struct drm_i915_private *dev_priv = dev->dev_private;
86 u32 reg;
87 int i;
88 const u32 *ddi_translations = ((use_fdi_mode) ?
89 hsw_ddi_translations_fdi :
90 hsw_ddi_translations_dp);
91
92 DRM_DEBUG_DRIVER("Initializing DDI buffers for port %c in %s mode\n",
93 port_name(port),
94 use_fdi_mode ? "FDI" : "DP");
95
96 WARN((use_fdi_mode && (port != PORT_E)),
97 "Programming port %c in FDI mode, this probably will not work.\n",
98 port_name(port));
99
100 for (i=0, reg=DDI_BUF_TRANS(port); i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
101 I915_WRITE(reg, ddi_translations[i]);
102 reg += 4;
103 }
104}
105
106/* Program DDI buffers translations for DP. By default, program ports A-D in DP
107 * mode and port E for FDI.
108 */
109void intel_prepare_ddi(struct drm_device *dev)
110{
111 int port;
112
113 if (IS_HASWELL(dev)) {
114 for (port = PORT_A; port < PORT_E; port++)
115 intel_prepare_ddi_buffers(dev, port, false);
116
117 /* DDI E is the suggested one to work in FDI mode, so program is as such by
118 * default. It will have to be re-programmed in case a digital DP output
119 * will be detected on it
120 */
121 intel_prepare_ddi_buffers(dev, PORT_E, true);
122 }
123}
c82e4d26
ED		 124
125static const long hsw_ddi_buf_ctl_values[] = {
126 DDI_BUF_EMP_400MV_0DB_HSW,
127 DDI_BUF_EMP_400MV_3_5DB_HSW,
128 DDI_BUF_EMP_400MV_6DB_HSW,
129 DDI_BUF_EMP_400MV_9_5DB_HSW,
130 DDI_BUF_EMP_600MV_0DB_HSW,
131 DDI_BUF_EMP_600MV_3_5DB_HSW,
132 DDI_BUF_EMP_600MV_6DB_HSW,
133 DDI_BUF_EMP_800MV_0DB_HSW,
134 DDI_BUF_EMP_800MV_3_5DB_HSW
135};
136
137
138/* Starting with Haswell, different DDI ports can work in FDI mode for
139 * connection to the PCH-located connectors. For this, it is necessary to train
140 * both the DDI port and PCH receiver for the desired DDI buffer settings.
141 *
142 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
143 * please note that when FDI mode is active on DDI E, it shares 2 lines with
144 * DDI A (which is used for eDP)
145 */
146
147void hsw_fdi_link_train(struct drm_crtc *crtc)
148{
149 struct drm_device *dev = crtc->dev;
150 struct drm_i915_private *dev_priv = dev->dev_private;
151 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
152 int pipe = intel_crtc->pipe;
153 u32 reg, temp, i;
154
155 /* Configure CPU PLL, wait for warmup */
156 I915_WRITE(SPLL_CTL,
157 SPLL_PLL_ENABLE |
158 SPLL_PLL_FREQ_1350MHz |
159 SPLL_PLL_SCC);
160
161 /* Use SPLL to drive the output when in FDI mode */
162 I915_WRITE(PORT_CLK_SEL(PORT_E),
163 PORT_CLK_SEL_SPLL);
c82e4d26
ED		 164
165 udelay(20);
166
167 /* Start the training iterating through available voltages and emphasis */
168 for (i=0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values); i++) {
169 /* Configure DP_TP_CTL with auto-training */
170 I915_WRITE(DP_TP_CTL(PORT_E),
171 DP_TP_CTL_FDI_AUTOTRAIN |
172 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
173 DP_TP_CTL_LINK_TRAIN_PAT1 |
174 DP_TP_CTL_ENABLE);
175
176 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage */
177 temp = I915_READ(DDI_BUF_CTL(PORT_E));
178 temp = (temp & ~DDI_BUF_EMP_MASK);
179 I915_WRITE(DDI_BUF_CTL(PORT_E),
180 temp |
181 DDI_BUF_CTL_ENABLE |
182 DDI_PORT_WIDTH_X2 |
183 hsw_ddi_buf_ctl_values[i]);
184
185 udelay(600);
186
4acf5186
ED		 187 /* We need to program FDI_RX_MISC with the default TP1 to TP2
188 * values before enabling the receiver, and configure the delay
189 * for the FDI timing generator to 90h. Luckily, all the other
190 * bits are supposed to be zeroed, so we can write those values
191 * directly.
192 */
193 I915_WRITE(FDI_RX_MISC(pipe), FDI_RX_TP1_TO_TP2_48 |
194 FDI_RX_FDI_DELAY_90);
195
c82e4d26
ED		 196 /* Enable CPU FDI Receiver with auto-training */
197 reg = FDI_RX_CTL(pipe);
198 I915_WRITE(reg,
199 I915_READ(reg) |
200 FDI_LINK_TRAIN_AUTO |
201 FDI_RX_ENABLE |
202 FDI_LINK_TRAIN_PATTERN_1_CPT |
203 FDI_RX_ENHANCE_FRAME_ENABLE |
204 FDI_PORT_WIDTH_2X_LPT |
205 FDI_RX_PLL_ENABLE);
206 POSTING_READ(reg);
207 udelay(100);
208
209 temp = I915_READ(DP_TP_STATUS(PORT_E));
210 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
211 DRM_DEBUG_DRIVER("BUF_CTL training done on %d step\n", i);
212
213 /* Enable normal pixel sending for FDI */
214 I915_WRITE(DP_TP_CTL(PORT_E),
215 DP_TP_CTL_FDI_AUTOTRAIN |
216 DP_TP_CTL_LINK_TRAIN_NORMAL |
217 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
218 DP_TP_CTL_ENABLE);
219
c82e4d26
ED		 220 break;
221 } else {
222 DRM_ERROR("Error training BUF_CTL %d\n", i);
223
224 /* Disable DP_TP_CTL and FDI_RX_CTL) and retry */
225 I915_WRITE(DP_TP_CTL(PORT_E),
226 I915_READ(DP_TP_CTL(PORT_E)) &
227 ~DP_TP_CTL_ENABLE);
228 I915_WRITE(FDI_RX_CTL(pipe),
229 I915_READ(FDI_RX_CTL(pipe)) &
230 ~FDI_RX_PLL_ENABLE);
231 continue;
232 }
233 }
234
235 DRM_DEBUG_KMS("FDI train done.\n");
236}
0e72a5b5
ED		 237
238/* For DDI connections, it is possible to support different outputs over the
239 * same DDI port, such as HDMI or DP or even VGA via FDI. So we don't know by
240 * the time the output is detected what exactly is on the other end of it. This
241 * function aims at providing support for this detection and proper output
242 * configuration.
243 */
244void intel_ddi_init(struct drm_device *dev, enum port port)
245{
246 /* For now, we don't do any proper output detection and assume that we
247 * handle HDMI only */
248
249 switch(port){
250 case PORT_A:
251 /* We don't handle eDP and DP yet */
252 DRM_DEBUG_DRIVER("Found digital output on DDI port A\n");
253 break;
254 /* Assume that the ports B, C and D are working in HDMI mode for now */
255 case PORT_B:
256 case PORT_C:
257 case PORT_D:
08d644ad 258 intel_hdmi_init(dev, DDI_BUF_CTL(port), port);
0e72a5b5
ED		 259 break;
260 default:
261 DRM_DEBUG_DRIVER("No handlers defined for port %d, skipping DDI initialization\n",
262 port);
263 break;
264 }
265}
12a13a33
ED		 266
267/* WRPLL clock dividers */
268struct wrpll_tmds_clock {
269 u32 clock;
270 u16 p; /* Post divider */
271 u16 n2; /* Feedback divider */
272 u16 r2; /* Reference divider */
273};
274
126e9be8
PZ		 275/* Table of matching values for WRPLL clocks programming for each frequency.
276 * The code assumes this table is sorted. */
12a13a33
ED		 277static const struct wrpll_tmds_clock wrpll_tmds_clock_table[] = {
278 {19750, 38, 25, 18},
279 {20000, 48, 32, 18},
280 {21000, 36, 21, 15},
281 {21912, 42, 29, 17},
282 {22000, 36, 22, 15},
283 {23000, 36, 23, 15},
284 {23500, 40, 40, 23},
285 {23750, 26, 16, 14},
12a13a33
ED		 286 {24000, 36, 24, 15},
287 {25000, 36, 25, 15},
288 {25175, 26, 40, 33},
289 {25200, 30, 21, 15},
290 {26000, 36, 26, 15},
291 {27000, 30, 21, 14},
292 {27027, 18, 100, 111},
293 {27500, 30, 29, 19},
294 {28000, 34, 30, 17},
295 {28320, 26, 30, 22},
296 {28322, 32, 42, 25},
297 {28750, 24, 23, 18},
298 {29000, 30, 29, 18},
299 {29750, 32, 30, 17},
300 {30000, 30, 25, 15},
301 {30750, 30, 41, 24},
302 {31000, 30, 31, 18},
303 {31500, 30, 28, 16},
304 {32000, 30, 32, 18},
305 {32500, 28, 32, 19},
306 {33000, 24, 22, 15},
307 {34000, 28, 30, 17},
308 {35000, 26, 32, 19},
309 {35500, 24, 30, 19},
310 {36000, 26, 26, 15},
311 {36750, 26, 46, 26},
312 {37000, 24, 23, 14},
313 {37762, 22, 40, 26},
314 {37800, 20, 21, 15},
315 {38000, 24, 27, 16},
316 {38250, 24, 34, 20},
317 {39000, 24, 26, 15},
318 {40000, 24, 32, 18},
319 {40500, 20, 21, 14},
320 {40541, 22, 147, 89},
321 {40750, 18, 19, 14},
322 {41000, 16, 17, 14},
323 {41500, 22, 44, 26},
324 {41540, 22, 44, 26},
325 {42000, 18, 21, 15},
326 {42500, 22, 45, 26},
327 {43000, 20, 43, 27},
328 {43163, 20, 24, 15},
329 {44000, 18, 22, 15},
330 {44900, 20, 108, 65},
331 {45000, 20, 25, 15},
332 {45250, 20, 52, 31},
333 {46000, 18, 23, 15},
334 {46750, 20, 45, 26},
335 {47000, 20, 40, 23},
336 {48000, 18, 24, 15},
337 {49000, 18, 49, 30},
338 {49500, 16, 22, 15},
339 {50000, 18, 25, 15},
340 {50500, 18, 32, 19},
341 {51000, 18, 34, 20},
342 {52000, 18, 26, 15},
343 {52406, 14, 34, 25},
344 {53000, 16, 22, 14},
345 {54000, 16, 24, 15},
346 {54054, 16, 173, 108},
347 {54500, 14, 24, 17},
348 {55000, 12, 22, 18},
349 {56000, 14, 45, 31},
350 {56250, 16, 25, 15},
351 {56750, 14, 25, 17},
352 {57000, 16, 27, 16},
353 {58000, 16, 43, 25},
354 {58250, 16, 38, 22},
355 {58750, 16, 40, 23},
356 {59000, 14, 26, 17},
357 {59341, 14, 40, 26},
358 {59400, 16, 44, 25},
359 {60000, 16, 32, 18},
360 {60500, 12, 39, 29},
361 {61000, 14, 49, 31},
362 {62000, 14, 37, 23},
363 {62250, 14, 42, 26},
364 {63000, 12, 21, 15},
365 {63500, 14, 28, 17},
366 {64000, 12, 27, 19},
367 {65000, 14, 32, 19},
368 {65250, 12, 29, 20},
369 {65500, 12, 32, 22},
370 {66000, 12, 22, 15},
371 {66667, 14, 38, 22},
372 {66750, 10, 21, 17},
373 {67000, 14, 33, 19},
374 {67750, 14, 58, 33},
375 {68000, 14, 30, 17},
376 {68179, 14, 46, 26},
377 {68250, 14, 46, 26},
378 {69000, 12, 23, 15},
379 {70000, 12, 28, 18},
380 {71000, 12, 30, 19},
381 {72000, 12, 24, 15},
382 {73000, 10, 23, 17},
383 {74000, 12, 23, 14},
384 {74176, 8, 100, 91},
385 {74250, 10, 22, 16},
386 {74481, 12, 43, 26},
387 {74500, 10, 29, 21},
388 {75000, 12, 25, 15},
389 {75250, 10, 39, 28},
390 {76000, 12, 27, 16},
391 {77000, 12, 53, 31},
392 {78000, 12, 26, 15},
393 {78750, 12, 28, 16},
394 {79000, 10, 38, 26},
395 {79500, 10, 28, 19},
396 {80000, 12, 32, 18},
397 {81000, 10, 21, 14},
398 {81081, 6, 100, 111},
399 {81624, 8, 29, 24},
400 {82000, 8, 17, 14},
401 {83000, 10, 40, 26},
402 {83950, 10, 28, 18},
403 {84000, 10, 28, 18},
404 {84750, 6, 16, 17},
405 {85000, 6, 17, 18},
406 {85250, 10, 30, 19},
407 {85750, 10, 27, 17},
408 {86000, 10, 43, 27},
409 {87000, 10, 29, 18},
410 {88000, 10, 44, 27},
411 {88500, 10, 41, 25},
412 {89000, 10, 28, 17},
413 {89012, 6, 90, 91},
414 {89100, 10, 33, 20},
415 {90000, 10, 25, 15},
416 {91000, 10, 32, 19},
417 {92000, 10, 46, 27},
418 {93000, 10, 31, 18},
419 {94000, 10, 40, 23},
420 {94500, 10, 28, 16},
421 {95000, 10, 44, 25},
422 {95654, 10, 39, 22},
423 {95750, 10, 39, 22},
424 {96000, 10, 32, 18},
425 {97000, 8, 23, 16},
426 {97750, 8, 42, 29},
427 {98000, 8, 45, 31},
428 {99000, 8, 22, 15},
429 {99750, 8, 34, 23},
430 {100000, 6, 20, 18},
431 {100500, 6, 19, 17},
432 {101000, 6, 37, 33},
433 {101250, 8, 21, 14},
434 {102000, 6, 17, 15},
435 {102250, 6, 25, 22},
436 {103000, 8, 29, 19},
437 {104000, 8, 37, 24},
438 {105000, 8, 28, 18},
439 {106000, 8, 22, 14},
440 {107000, 8, 46, 29},
441 {107214, 8, 27, 17},
442 {108000, 8, 24, 15},
443 {108108, 8, 173, 108},
444 {109000, 6, 23, 19},
12a13a33
ED		 445 {110000, 6, 22, 18},
446 {110013, 6, 22, 18},
447 {110250, 8, 49, 30},
448 {110500, 8, 36, 22},
449 {111000, 8, 23, 14},
450 {111264, 8, 150, 91},
451 {111375, 8, 33, 20},
452 {112000, 8, 63, 38},
453 {112500, 8, 25, 15},
454 {113100, 8, 57, 34},
455 {113309, 8, 42, 25},
456 {114000, 8, 27, 16},
457 {115000, 6, 23, 18},
458 {116000, 8, 43, 25},
459 {117000, 8, 26, 15},
460 {117500, 8, 40, 23},
461 {118000, 6, 38, 29},
462 {119000, 8, 30, 17},
463 {119500, 8, 46, 26},
464 {119651, 8, 39, 22},
465 {120000, 8, 32, 18},
466 {121000, 6, 39, 29},
467 {121250, 6, 31, 23},
468 {121750, 6, 23, 17},
469 {122000, 6, 42, 31},
470 {122614, 6, 30, 22},
471 {123000, 6, 41, 30},
472 {123379, 6, 37, 27},
473 {124000, 6, 51, 37},
474 {125000, 6, 25, 18},
475 {125250, 4, 13, 14},
476 {125750, 4, 27, 29},
477 {126000, 6, 21, 15},
478 {127000, 6, 24, 17},
479 {127250, 6, 41, 29},
480 {128000, 6, 27, 19},
481 {129000, 6, 43, 30},
482 {129859, 4, 25, 26},
483 {130000, 6, 26, 18},
484 {130250, 6, 42, 29},
485 {131000, 6, 32, 22},
486 {131500, 6, 38, 26},
487 {131850, 6, 41, 28},
488 {132000, 6, 22, 15},
489 {132750, 6, 28, 19},
490 {133000, 6, 34, 23},
491 {133330, 6, 37, 25},
492 {134000, 6, 61, 41},
493 {135000, 6, 21, 14},
494 {135250, 6, 167, 111},
495 {136000, 6, 62, 41},
496 {137000, 6, 35, 23},
497 {138000, 6, 23, 15},
498 {138500, 6, 40, 26},
499 {138750, 6, 37, 24},
500 {139000, 6, 34, 22},
501 {139050, 6, 34, 22},
502 {139054, 6, 34, 22},
503 {140000, 6, 28, 18},
504 {141000, 6, 36, 23},
505 {141500, 6, 22, 14},
506 {142000, 6, 30, 19},
507 {143000, 6, 27, 17},
508 {143472, 4, 17, 16},
509 {144000, 6, 24, 15},
510 {145000, 6, 29, 18},
511 {146000, 6, 47, 29},
512 {146250, 6, 26, 16},
513 {147000, 6, 49, 30},
514 {147891, 6, 23, 14},
515 {148000, 6, 23, 14},
516 {148250, 6, 28, 17},
517 {148352, 4, 100, 91},
518 {148500, 6, 33, 20},
519 {149000, 6, 48, 29},
520 {150000, 6, 25, 15},
521 {151000, 4, 19, 17},
522 {152000, 6, 27, 16},
523 {152280, 6, 44, 26},
524 {153000, 6, 34, 20},
525 {154000, 6, 53, 31},
526 {155000, 6, 31, 18},
527 {155250, 6, 50, 29},
528 {155750, 6, 45, 26},
529 {156000, 6, 26, 15},
530 {157000, 6, 61, 35},
531 {157500, 6, 28, 16},
532 {158000, 6, 65, 37},
533 {158250, 6, 44, 25},
534 {159000, 6, 53, 30},
535 {159500, 6, 39, 22},
536 {160000, 6, 32, 18},
537 {161000, 4, 31, 26},
538 {162000, 4, 18, 15},
539 {162162, 4, 131, 109},
540 {162500, 4, 53, 44},
541 {163000, 4, 29, 24},
542 {164000, 4, 17, 14},
543 {165000, 4, 22, 18},
544 {166000, 4, 32, 26},
545 {167000, 4, 26, 21},
546 {168000, 4, 46, 37},
547 {169000, 4, 104, 83},
548 {169128, 4, 64, 51},
549 {169500, 4, 39, 31},
550 {170000, 4, 34, 27},
551 {171000, 4, 19, 15},
552 {172000, 4, 51, 40},
553 {172750, 4, 32, 25},
554 {172800, 4, 32, 25},
555 {173000, 4, 41, 32},
556 {174000, 4, 49, 38},
557 {174787, 4, 22, 17},
558 {175000, 4, 35, 27},
559 {176000, 4, 30, 23},
560 {177000, 4, 38, 29},
561 {178000, 4, 29, 22},
562 {178500, 4, 37, 28},
563 {179000, 4, 53, 40},
564 {179500, 4, 73, 55},
565 {180000, 4, 20, 15},
566 {181000, 4, 55, 41},
567 {182000, 4, 31, 23},
568 {183000, 4, 42, 31},
569 {184000, 4, 30, 22},
570 {184750, 4, 26, 19},
571 {185000, 4, 37, 27},
572 {186000, 4, 51, 37},
573 {187000, 4, 36, 26},
574 {188000, 4, 32, 23},
575 {189000, 4, 21, 15},
576 {190000, 4, 38, 27},
577 {190960, 4, 41, 29},
578 {191000, 4, 41, 29},
579 {192000, 4, 27, 19},
580 {192250, 4, 37, 26},
581 {193000, 4, 20, 14},
582 {193250, 4, 53, 37},
583 {194000, 4, 23, 16},
584 {194208, 4, 23, 16},
585 {195000, 4, 26, 18},
586 {196000, 4, 45, 31},
587 {197000, 4, 35, 24},
588 {197750, 4, 41, 28},
589 {198000, 4, 22, 15},
590 {198500, 4, 25, 17},
591 {199000, 4, 28, 19},
592 {200000, 4, 37, 25},
593 {201000, 4, 61, 41},
594 {202000, 4, 112, 75},
595 {202500, 4, 21, 14},
596 {203000, 4, 146, 97},
597 {204000, 4, 62, 41},
598 {204750, 4, 44, 29},
599 {205000, 4, 38, 25},
600 {206000, 4, 29, 19},
601 {207000, 4, 23, 15},
602 {207500, 4, 40, 26},
603 {208000, 4, 37, 24},
604 {208900, 4, 48, 31},
605 {209000, 4, 48, 31},
606 {209250, 4, 31, 20},
607 {210000, 4, 28, 18},
608 {211000, 4, 25, 16},
609 {212000, 4, 22, 14},
610 {213000, 4, 30, 19},
611 {213750, 4, 38, 24},
612 {214000, 4, 46, 29},
613 {214750, 4, 35, 22},
614 {215000, 4, 43, 27},
615 {216000, 4, 24, 15},
616 {217000, 4, 37, 23},
617 {218000, 4, 42, 26},
618 {218250, 4, 42, 26},
619 {218750, 4, 34, 21},
620 {219000, 4, 47, 29},
12a13a33
ED		 621 {220000, 4, 44, 27},
622 {220640, 4, 49, 30},
623 {220750, 4, 36, 22},
624 {221000, 4, 36, 22},
625 {222000, 4, 23, 14},
626 {222525, 4, 28, 17},
627 {222750, 4, 33, 20},
628 {227000, 4, 37, 22},
629 {230250, 4, 29, 17},
630 {233500, 4, 38, 22},
631 {235000, 4, 40, 23},
632 {238000, 4, 30, 17},
633 {241500, 2, 17, 19},
634 {245250, 2, 20, 22},
635 {247750, 2, 22, 24},
636 {253250, 2, 15, 16},
637 {256250, 2, 18, 19},
638 {262500, 2, 31, 32},
639 {267250, 2, 66, 67},
640 {268500, 2, 94, 95},
641 {270000, 2, 14, 14},
642 {272500, 2, 77, 76},
643 {273750, 2, 57, 56},
644 {280750, 2, 24, 23},
645 {281250, 2, 23, 22},
646 {286000, 2, 17, 16},
647 {291750, 2, 26, 24},
648 {296703, 2, 56, 51},
649 {297000, 2, 22, 20},
650 {298000, 2, 21, 19},
651};
72662e10
ED		 652
653void intel_ddi_mode_set(struct drm_encoder *encoder,
654 struct drm_display_mode *mode,
655 struct drm_display_mode *adjusted_mode)
656{
657 struct drm_device *dev = encoder->dev;
658 struct drm_i915_private *dev_priv = dev->dev_private;
659 struct drm_crtc *crtc = encoder->crtc;
660 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
661 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
662 int port = intel_hdmi->ddi_port;
663 int pipe = intel_crtc->pipe;
126e9be8 664 int p, n2, r2;
8d9ddbcb 665 u32 i;
72662e10
ED		 666
667 /* On Haswell, we need to enable the clocks and prepare DDI function to
668 * work in HDMI mode for this pipe.
669 */
670 DRM_DEBUG_KMS("Preparing HDMI DDI mode for Haswell on port %c, pipe %c\n", port_name(port), pipe_name(pipe));
671
126e9be8
PZ		 672 for (i = 0; i < ARRAY_SIZE(wrpll_tmds_clock_table); i++)
673 if (crtc->mode.clock <= wrpll_tmds_clock_table[i].clock)
674 break;
72662e10 675
126e9be8
PZ		 676 if (i == ARRAY_SIZE(wrpll_tmds_clock_table))
677 i--;
72662e10 678
126e9be8
PZ		 679 p = wrpll_tmds_clock_table[i].p;
680 n2 = wrpll_tmds_clock_table[i].n2;
681 r2 = wrpll_tmds_clock_table[i].r2;
72662e10 682
126e9be8
PZ		 683 if (wrpll_tmds_clock_table[i].clock != crtc->mode.clock)
684 DRM_INFO("WR PLL: using settings for %dKHz on %dKHz mode\n",
685 wrpll_tmds_clock_table[i].clock, crtc->mode.clock);
686
687 DRM_DEBUG_KMS("WR PLL: %dKHz refresh rate with p=%d, n2=%d r2=%d\n",
688 crtc->mode.clock, p, n2, r2);
72662e10 689
72662e10
ED		 690 /* Configure WR PLL 1, program the correct divider values for
691 * the desired frequency and wait for warmup */
692 I915_WRITE(WRPLL_CTL1,
693 WRPLL_PLL_ENABLE |
694 WRPLL_PLL_SELECT_LCPLL_2700 |
695 WRPLL_DIVIDER_REFERENCE(r2) |
696 WRPLL_DIVIDER_FEEDBACK(n2) |
697 WRPLL_DIVIDER_POST(p));
698
699 udelay(20);
700
701 /* Use WRPLL1 clock to drive the output to the port, and tell the pipe to use
702 * this port for connection.
703 */
704 I915_WRITE(PORT_CLK_SEL(port),
705 PORT_CLK_SEL_WRPLL1);
72662e10
ED		 706
707 udelay(20);
708
709 if (intel_hdmi->has_audio) {
710 /* Proper support for digital audio needs a new logic and a new set
711 * of registers, so we leave it for future patch bombing.
712 */
4f07854d 713 DRM_DEBUG_DRIVER("HDMI audio on pipe %c on DDI\n",
72662e10 714 pipe_name(intel_crtc->pipe));
4f07854d
WX		 715
716 /* write eld */
717 DRM_DEBUG_DRIVER("HDMI audio: write eld information\n");
718 intel_write_eld(encoder, adjusted_mode);
72662e10
ED		 719 }
720
8d9ddbcb
PZ		 721 intel_hdmi->set_infoframes(encoder, adjusted_mode);
722}
723
724static struct intel_encoder *
725intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
726{
727 struct drm_device *dev = crtc->dev;
728 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
729 struct intel_encoder *intel_encoder, *ret = NULL;
730 int num_encoders = 0;
731
732 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
733 ret = intel_encoder;
734 num_encoders++;
735 }
736
737 if (num_encoders != 1)
738 WARN(1, "%d encoders on crtc for pipe %d\n", num_encoders,
739 intel_crtc->pipe);
740
741 BUG_ON(ret == NULL);
742 return ret;
743}
744
745void intel_ddi_enable_pipe_func(struct drm_crtc *crtc)
746{
747 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
748 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
749 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
750 enum pipe pipe = intel_crtc->pipe;
751 uint32_t temp;
752
72662e10 753 /* Enable PIPE_DDI_FUNC_CTL for the pipe to work in HDMI mode */
8d9ddbcb 754 temp = PIPE_DDI_FUNC_ENABLE;
dfcef252
PZ		 755
756 switch (intel_crtc->bpp) {
757 case 18:
758 temp |= PIPE_DDI_BPC_6;
759 break;
760 case 24:
761 temp |= PIPE_DDI_BPC_8;
762 break;
763 case 30:
764 temp |= PIPE_DDI_BPC_10;
765 break;
766 case 36:
767 temp |= PIPE_DDI_BPC_12;
768 break;
769 default:
770 WARN(1, "%d bpp unsupported by pipe DDI function\n",
771 intel_crtc->bpp);
772 }
72662e10 773
8d9ddbcb 774 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
f63eb7c4 775 temp |= PIPE_DDI_PVSYNC;
8d9ddbcb 776 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
f63eb7c4
PZ		 777 temp |= PIPE_DDI_PHSYNC;
778
8d9ddbcb
PZ		 779 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
780 struct intel_hdmi *intel_hdmi =
781 enc_to_intel_hdmi(&intel_encoder->base);
782
783 if (intel_hdmi->has_hdmi_sink)
784 temp |= PIPE_DDI_MODE_SELECT_HDMI;
785 else
786 temp |= PIPE_DDI_MODE_SELECT_DVI;
787
788 temp |= PIPE_DDI_SELECT_PORT(intel_hdmi->ddi_port);
789 } else if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
790 temp |= PIPE_DDI_MODE_SELECT_FDI;
791 temp |= PIPE_DDI_SELECT_PORT(PORT_E);
792 } else {
793 WARN(1, "Invalid encoder type %d for pipe %d\n",
794 intel_encoder->type, pipe);
795 }
796
72662e10 797 I915_WRITE(DDI_FUNC_CTL(pipe), temp);
8d9ddbcb 798}
72662e10 799
8d9ddbcb
PZ		 800void intel_ddi_disable_pipe_func(struct drm_i915_private *dev_priv,
801 enum pipe pipe)
802{
803 uint32_t reg = DDI_FUNC_CTL(pipe);
804 uint32_t val = I915_READ(reg);
805
806 val &= ~(PIPE_DDI_FUNC_ENABLE | PIPE_DDI_PORT_MASK);
807 val |= PIPE_DDI_PORT_NONE;
808 I915_WRITE(reg, val);
72662e10
ED		 809}
810
85234cdc
DV		 811bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
812 enum pipe *pipe)
813{
814 struct drm_device *dev = encoder->base.dev;
815 struct drm_i915_private *dev_priv = dev->dev_private;
816 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
817 u32 tmp;
818 int i;
819
820 tmp = I915_READ(DDI_BUF_CTL(intel_hdmi->ddi_port));
821
822 if (!(tmp & DDI_BUF_CTL_ENABLE))
823 return false;
824
825 for_each_pipe(i) {
826 tmp = I915_READ(DDI_FUNC_CTL(i));
827
828 if ((tmp & PIPE_DDI_PORT_MASK)
829 == PIPE_DDI_SELECT_PORT(intel_hdmi->ddi_port)) {
830 *pipe = i;
831 return true;
832 }
833 }
834
835 DRM_DEBUG_KMS("No pipe for ddi port %i found\n", intel_hdmi->ddi_port);
836
837 return true;
838}
839
fc914639
PZ		 840void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
841{
842 struct drm_crtc *crtc = &intel_crtc->base;
843 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
844 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
845 enum port port = intel_ddi_get_encoder_port(intel_encoder);
846
847 I915_WRITE(PIPE_CLK_SEL(intel_crtc->pipe), PIPE_CLK_SEL_PORT(port));
848}
849
850void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
851{
852 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
853
854 I915_WRITE(PIPE_CLK_SEL(intel_crtc->pipe), PIPE_CLK_SEL_DISABLED);
855}
856
5ab432ef 857void intel_enable_ddi(struct intel_encoder *encoder)
72662e10 858{
5ab432ef 859 struct drm_device *dev = encoder->base.dev;
72662e10 860 struct drm_i915_private *dev_priv = dev->dev_private;
5ab432ef 861 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
72662e10
ED		 862 int port = intel_hdmi->ddi_port;
863 u32 temp;
864
865 temp = I915_READ(DDI_BUF_CTL(port));
5ab432ef 866 temp |= DDI_BUF_CTL_ENABLE;
72662e10
ED		 867
868 /* Enable DDI_BUF_CTL. In HDMI/DVI mode, the port width,
869 * and swing/emphasis values are ignored so nothing special needs
870 * to be done besides enabling the port.
871 */
5ab432ef
DV		 872 I915_WRITE(DDI_BUF_CTL(port), temp);
873}
874
875void intel_disable_ddi(struct intel_encoder *encoder)
876{
877 struct drm_device *dev = encoder->base.dev;
878 struct drm_i915_private *dev_priv = dev->dev_private;
879 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
880 int port = intel_hdmi->ddi_port;
881 u32 temp;
882
883 temp = I915_READ(DDI_BUF_CTL(port));
884 temp &= ~DDI_BUF_CTL_ENABLE;
885
886 I915_WRITE(DDI_BUF_CTL(port), temp);
72662e10 887}
79f689aa
PZ		 888
889static int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
890{
891 if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT)
892 return 450;
893 else if ((I915_READ(LCPLL_CTL) & LCPLL_CLK_FREQ_MASK) ==
894 LCPLL_CLK_FREQ_450)
895 return 450;
896 else
897 return 540;
898}
899
900void intel_ddi_pll_init(struct drm_device *dev)
901{
902 struct drm_i915_private *dev_priv = dev->dev_private;
903 uint32_t val = I915_READ(LCPLL_CTL);
904
905 /* The LCPLL register should be turned on by the BIOS. For now let's
906 * just check its state and print errors in case something is wrong.
907 * Don't even try to turn it on.
908 */
909
910 DRM_DEBUG_KMS("CDCLK running at %dMHz\n",
911 intel_ddi_get_cdclk_freq(dev_priv));
912
913 if (val & LCPLL_CD_SOURCE_FCLK)
914 DRM_ERROR("CDCLK source is not LCPLL\n");
915
916 if (val & LCPLL_PLL_DISABLE)
917 DRM_ERROR("LCPLL is disabled\n");
918}
Linux kernel - Deliverables
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