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45244b87 ED |
1 | /* |
2 | * Copyright © 2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "i915_drv.h" | |
29 | #include "intel_drv.h" | |
30 | ||
31 | /* HDMI/DVI modes ignore everything but the last 2 items. So we share | |
32 | * them for both DP and FDI transports, allowing those ports to | |
33 | * automatically adapt to HDMI connections as well | |
34 | */ | |
35 | static const u32 hsw_ddi_translations_dp[] = { | |
36 | 0x00FFFFFF, 0x0006000E, /* DP parameters */ | |
37 | 0x00D75FFF, 0x0005000A, | |
38 | 0x00C30FFF, 0x00040006, | |
39 | 0x80AAAFFF, 0x000B0000, | |
40 | 0x00FFFFFF, 0x0005000A, | |
41 | 0x00D75FFF, 0x000C0004, | |
42 | 0x80C30FFF, 0x000B0000, | |
43 | 0x00FFFFFF, 0x00040006, | |
44 | 0x80D75FFF, 0x000B0000, | |
45 | 0x00FFFFFF, 0x00040006 /* HDMI parameters */ | |
46 | }; | |
47 | ||
48 | static const u32 hsw_ddi_translations_fdi[] = { | |
49 | 0x00FFFFFF, 0x0007000E, /* FDI parameters */ | |
50 | 0x00D75FFF, 0x000F000A, | |
51 | 0x00C30FFF, 0x00060006, | |
52 | 0x00AAAFFF, 0x001E0000, | |
53 | 0x00FFFFFF, 0x000F000A, | |
54 | 0x00D75FFF, 0x00160004, | |
55 | 0x00C30FFF, 0x001E0000, | |
56 | 0x00FFFFFF, 0x00060006, | |
57 | 0x00D75FFF, 0x001E0000, | |
58 | 0x00FFFFFF, 0x00040006 /* HDMI parameters */ | |
59 | }; | |
60 | ||
fc914639 PZ |
61 | static enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder) |
62 | { | |
0bdee30e | 63 | struct drm_encoder *encoder = &intel_encoder->base; |
fc914639 PZ |
64 | int type = intel_encoder->type; |
65 | ||
174edf1f | 66 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || |
00c09d70 | 67 | type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) { |
174edf1f PZ |
68 | struct intel_digital_port *intel_dig_port = |
69 | enc_to_dig_port(encoder); | |
70 | return intel_dig_port->port; | |
0bdee30e | 71 | |
fc914639 PZ |
72 | } else if (type == INTEL_OUTPUT_ANALOG) { |
73 | return PORT_E; | |
0bdee30e | 74 | |
fc914639 PZ |
75 | } else { |
76 | DRM_ERROR("Invalid DDI encoder type %d\n", type); | |
77 | BUG(); | |
78 | } | |
79 | } | |
80 | ||
45244b87 ED |
81 | /* On Haswell, DDI port buffers must be programmed with correct values |
82 | * in advance. The buffer values are different for FDI and DP modes, | |
83 | * but the HDMI/DVI fields are shared among those. So we program the DDI | |
84 | * in either FDI or DP modes only, as HDMI connections will work with both | |
85 | * of those | |
86 | */ | |
c1f63f9d PZ |
87 | static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port, |
88 | bool use_fdi_mode) | |
45244b87 ED |
89 | { |
90 | struct drm_i915_private *dev_priv = dev->dev_private; | |
91 | u32 reg; | |
92 | int i; | |
93 | const u32 *ddi_translations = ((use_fdi_mode) ? | |
94 | hsw_ddi_translations_fdi : | |
95 | hsw_ddi_translations_dp); | |
96 | ||
f72d19f0 PZ |
97 | for (i = 0, reg = DDI_BUF_TRANS(port); |
98 | i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) { | |
45244b87 ED |
99 | I915_WRITE(reg, ddi_translations[i]); |
100 | reg += 4; | |
101 | } | |
102 | } | |
103 | ||
104 | /* Program DDI buffers translations for DP. By default, program ports A-D in DP | |
105 | * mode and port E for FDI. | |
106 | */ | |
107 | void intel_prepare_ddi(struct drm_device *dev) | |
108 | { | |
109 | int port; | |
110 | ||
0d536cb4 PZ |
111 | if (!HAS_DDI(dev)) |
112 | return; | |
45244b87 | 113 | |
0d536cb4 PZ |
114 | for (port = PORT_A; port < PORT_E; port++) |
115 | intel_prepare_ddi_buffers(dev, port, false); | |
116 | ||
117 | /* DDI E is the suggested one to work in FDI mode, so program is as such | |
118 | * by default. It will have to be re-programmed in case a digital DP | |
119 | * output will be detected on it | |
120 | */ | |
121 | intel_prepare_ddi_buffers(dev, PORT_E, true); | |
45244b87 | 122 | } |
c82e4d26 ED |
123 | |
124 | static const long hsw_ddi_buf_ctl_values[] = { | |
125 | DDI_BUF_EMP_400MV_0DB_HSW, | |
126 | DDI_BUF_EMP_400MV_3_5DB_HSW, | |
127 | DDI_BUF_EMP_400MV_6DB_HSW, | |
128 | DDI_BUF_EMP_400MV_9_5DB_HSW, | |
129 | DDI_BUF_EMP_600MV_0DB_HSW, | |
130 | DDI_BUF_EMP_600MV_3_5DB_HSW, | |
131 | DDI_BUF_EMP_600MV_6DB_HSW, | |
132 | DDI_BUF_EMP_800MV_0DB_HSW, | |
133 | DDI_BUF_EMP_800MV_3_5DB_HSW | |
134 | }; | |
135 | ||
248138b5 PZ |
136 | static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, |
137 | enum port port) | |
138 | { | |
139 | uint32_t reg = DDI_BUF_CTL(port); | |
140 | int i; | |
141 | ||
142 | for (i = 0; i < 8; i++) { | |
143 | udelay(1); | |
144 | if (I915_READ(reg) & DDI_BUF_IS_IDLE) | |
145 | return; | |
146 | } | |
147 | DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port)); | |
148 | } | |
c82e4d26 ED |
149 | |
150 | /* Starting with Haswell, different DDI ports can work in FDI mode for | |
151 | * connection to the PCH-located connectors. For this, it is necessary to train | |
152 | * both the DDI port and PCH receiver for the desired DDI buffer settings. | |
153 | * | |
154 | * The recommended port to work in FDI mode is DDI E, which we use here. Also, | |
155 | * please note that when FDI mode is active on DDI E, it shares 2 lines with | |
156 | * DDI A (which is used for eDP) | |
157 | */ | |
158 | ||
159 | void hsw_fdi_link_train(struct drm_crtc *crtc) | |
160 | { | |
161 | struct drm_device *dev = crtc->dev; | |
162 | struct drm_i915_private *dev_priv = dev->dev_private; | |
163 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
04945641 | 164 | u32 temp, i, rx_ctl_val; |
c82e4d26 | 165 | |
04945641 PZ |
166 | /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the |
167 | * mode set "sequence for CRT port" document: | |
168 | * - TP1 to TP2 time with the default value | |
169 | * - FDI delay to 90h | |
8693a824 DL |
170 | * |
171 | * WaFDIAutoLinkSetTimingOverrride:hsw | |
04945641 PZ |
172 | */ |
173 | I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) | | |
174 | FDI_RX_PWRDN_LANE0_VAL(2) | | |
175 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
176 | ||
177 | /* Enable the PCH Receiver FDI PLL */ | |
3e68320e | 178 | rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | |
33d29b14 | 179 | FDI_RX_PLL_ENABLE | |
627eb5a3 | 180 | FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
04945641 PZ |
181 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); |
182 | POSTING_READ(_FDI_RXA_CTL); | |
183 | udelay(220); | |
184 | ||
185 | /* Switch from Rawclk to PCDclk */ | |
186 | rx_ctl_val |= FDI_PCDCLK; | |
187 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); | |
188 | ||
189 | /* Configure Port Clock Select */ | |
190 | I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel); | |
191 | ||
192 | /* Start the training iterating through available voltages and emphasis, | |
193 | * testing each value twice. */ | |
194 | for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) { | |
c82e4d26 ED |
195 | /* Configure DP_TP_CTL with auto-training */ |
196 | I915_WRITE(DP_TP_CTL(PORT_E), | |
197 | DP_TP_CTL_FDI_AUTOTRAIN | | |
198 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | | |
199 | DP_TP_CTL_LINK_TRAIN_PAT1 | | |
200 | DP_TP_CTL_ENABLE); | |
201 | ||
876a8cdf DL |
202 | /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. |
203 | * DDI E does not support port reversal, the functionality is | |
204 | * achieved on the PCH side in FDI_RX_CTL, so no need to set the | |
205 | * port reversal bit */ | |
c82e4d26 | 206 | I915_WRITE(DDI_BUF_CTL(PORT_E), |
04945641 | 207 | DDI_BUF_CTL_ENABLE | |
33d29b14 | 208 | ((intel_crtc->config.fdi_lanes - 1) << 1) | |
04945641 PZ |
209 | hsw_ddi_buf_ctl_values[i / 2]); |
210 | POSTING_READ(DDI_BUF_CTL(PORT_E)); | |
c82e4d26 ED |
211 | |
212 | udelay(600); | |
213 | ||
04945641 PZ |
214 | /* Program PCH FDI Receiver TU */ |
215 | I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64)); | |
216 | ||
217 | /* Enable PCH FDI Receiver with auto-training */ | |
218 | rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; | |
219 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); | |
220 | POSTING_READ(_FDI_RXA_CTL); | |
221 | ||
222 | /* Wait for FDI receiver lane calibration */ | |
223 | udelay(30); | |
224 | ||
225 | /* Unset FDI_RX_MISC pwrdn lanes */ | |
226 | temp = I915_READ(_FDI_RXA_MISC); | |
227 | temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); | |
228 | I915_WRITE(_FDI_RXA_MISC, temp); | |
229 | POSTING_READ(_FDI_RXA_MISC); | |
230 | ||
231 | /* Wait for FDI auto training time */ | |
232 | udelay(5); | |
c82e4d26 ED |
233 | |
234 | temp = I915_READ(DP_TP_STATUS(PORT_E)); | |
235 | if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { | |
04945641 | 236 | DRM_DEBUG_KMS("FDI link training done on step %d\n", i); |
c82e4d26 ED |
237 | |
238 | /* Enable normal pixel sending for FDI */ | |
239 | I915_WRITE(DP_TP_CTL(PORT_E), | |
04945641 PZ |
240 | DP_TP_CTL_FDI_AUTOTRAIN | |
241 | DP_TP_CTL_LINK_TRAIN_NORMAL | | |
242 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | | |
243 | DP_TP_CTL_ENABLE); | |
c82e4d26 | 244 | |
04945641 | 245 | return; |
c82e4d26 | 246 | } |
04945641 | 247 | |
248138b5 PZ |
248 | temp = I915_READ(DDI_BUF_CTL(PORT_E)); |
249 | temp &= ~DDI_BUF_CTL_ENABLE; | |
250 | I915_WRITE(DDI_BUF_CTL(PORT_E), temp); | |
251 | POSTING_READ(DDI_BUF_CTL(PORT_E)); | |
252 | ||
04945641 | 253 | /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ |
248138b5 PZ |
254 | temp = I915_READ(DP_TP_CTL(PORT_E)); |
255 | temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
256 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
257 | I915_WRITE(DP_TP_CTL(PORT_E), temp); | |
258 | POSTING_READ(DP_TP_CTL(PORT_E)); | |
259 | ||
260 | intel_wait_ddi_buf_idle(dev_priv, PORT_E); | |
04945641 PZ |
261 | |
262 | rx_ctl_val &= ~FDI_RX_ENABLE; | |
263 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); | |
248138b5 | 264 | POSTING_READ(_FDI_RXA_CTL); |
04945641 PZ |
265 | |
266 | /* Reset FDI_RX_MISC pwrdn lanes */ | |
267 | temp = I915_READ(_FDI_RXA_MISC); | |
268 | temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); | |
269 | temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); | |
270 | I915_WRITE(_FDI_RXA_MISC, temp); | |
248138b5 | 271 | POSTING_READ(_FDI_RXA_MISC); |
c82e4d26 ED |
272 | } |
273 | ||
04945641 | 274 | DRM_ERROR("FDI link training failed!\n"); |
c82e4d26 | 275 | } |
0e72a5b5 | 276 | |
c7d8be30 | 277 | static void intel_ddi_mode_set(struct intel_encoder *encoder) |
72662e10 | 278 | { |
c7d8be30 DV |
279 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
280 | int port = intel_ddi_get_encoder_port(encoder); | |
281 | int pipe = crtc->pipe; | |
282 | int type = encoder->type; | |
283 | struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; | |
72662e10 | 284 | |
bf98a726 | 285 | DRM_DEBUG_KMS("Preparing DDI mode on port %c, pipe %c\n", |
247d89f6 | 286 | port_name(port), pipe_name(pipe)); |
72662e10 | 287 | |
c7d8be30 | 288 | crtc->eld_vld = false; |
247d89f6 | 289 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
c7d8be30 | 290 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
876a8cdf | 291 | struct intel_digital_port *intel_dig_port = |
c7d8be30 | 292 | enc_to_dig_port(&encoder->base); |
4f07854d | 293 | |
bcf53de4 | 294 | intel_dp->DP = intel_dig_port->saved_port_bits | |
876a8cdf | 295 | DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW; |
17aa6be9 | 296 | intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); |
247d89f6 | 297 | |
8fed6193 TI |
298 | if (intel_dp->has_audio) { |
299 | DRM_DEBUG_DRIVER("DP audio on pipe %c on DDI\n", | |
c7d8be30 | 300 | pipe_name(crtc->pipe)); |
8fed6193 TI |
301 | |
302 | /* write eld */ | |
303 | DRM_DEBUG_DRIVER("DP audio: write eld information\n"); | |
c7d8be30 | 304 | intel_write_eld(&encoder->base, adjusted_mode); |
8fed6193 TI |
305 | } |
306 | ||
247d89f6 PZ |
307 | intel_dp_init_link_config(intel_dp); |
308 | ||
309 | } else if (type == INTEL_OUTPUT_HDMI) { | |
c7d8be30 | 310 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
247d89f6 PZ |
311 | |
312 | if (intel_hdmi->has_audio) { | |
313 | /* Proper support for digital audio needs a new logic | |
314 | * and a new set of registers, so we leave it for future | |
315 | * patch bombing. | |
316 | */ | |
317 | DRM_DEBUG_DRIVER("HDMI audio on pipe %c on DDI\n", | |
c7d8be30 | 318 | pipe_name(crtc->pipe)); |
247d89f6 PZ |
319 | |
320 | /* write eld */ | |
321 | DRM_DEBUG_DRIVER("HDMI audio: write eld information\n"); | |
c7d8be30 | 322 | intel_write_eld(&encoder->base, adjusted_mode); |
247d89f6 | 323 | } |
72662e10 | 324 | |
c7d8be30 | 325 | intel_hdmi->set_infoframes(&encoder->base, adjusted_mode); |
247d89f6 | 326 | } |
8d9ddbcb PZ |
327 | } |
328 | ||
329 | static struct intel_encoder * | |
330 | intel_ddi_get_crtc_encoder(struct drm_crtc *crtc) | |
331 | { | |
332 | struct drm_device *dev = crtc->dev; | |
333 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
334 | struct intel_encoder *intel_encoder, *ret = NULL; | |
335 | int num_encoders = 0; | |
336 | ||
337 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { | |
338 | ret = intel_encoder; | |
339 | num_encoders++; | |
340 | } | |
341 | ||
342 | if (num_encoders != 1) | |
84f44ce7 VS |
343 | WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders, |
344 | pipe_name(intel_crtc->pipe)); | |
8d9ddbcb PZ |
345 | |
346 | BUG_ON(ret == NULL); | |
347 | return ret; | |
348 | } | |
349 | ||
6441ab5f PZ |
350 | void intel_ddi_put_crtc_pll(struct drm_crtc *crtc) |
351 | { | |
352 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
353 | struct intel_ddi_plls *plls = &dev_priv->ddi_plls; | |
354 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
355 | uint32_t val; | |
356 | ||
357 | switch (intel_crtc->ddi_pll_sel) { | |
358 | case PORT_CLK_SEL_SPLL: | |
359 | plls->spll_refcount--; | |
360 | if (plls->spll_refcount == 0) { | |
361 | DRM_DEBUG_KMS("Disabling SPLL\n"); | |
362 | val = I915_READ(SPLL_CTL); | |
363 | WARN_ON(!(val & SPLL_PLL_ENABLE)); | |
364 | I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); | |
365 | POSTING_READ(SPLL_CTL); | |
366 | } | |
367 | break; | |
368 | case PORT_CLK_SEL_WRPLL1: | |
369 | plls->wrpll1_refcount--; | |
370 | if (plls->wrpll1_refcount == 0) { | |
371 | DRM_DEBUG_KMS("Disabling WRPLL 1\n"); | |
372 | val = I915_READ(WRPLL_CTL1); | |
373 | WARN_ON(!(val & WRPLL_PLL_ENABLE)); | |
374 | I915_WRITE(WRPLL_CTL1, val & ~WRPLL_PLL_ENABLE); | |
375 | POSTING_READ(WRPLL_CTL1); | |
376 | } | |
377 | break; | |
378 | case PORT_CLK_SEL_WRPLL2: | |
379 | plls->wrpll2_refcount--; | |
380 | if (plls->wrpll2_refcount == 0) { | |
381 | DRM_DEBUG_KMS("Disabling WRPLL 2\n"); | |
382 | val = I915_READ(WRPLL_CTL2); | |
383 | WARN_ON(!(val & WRPLL_PLL_ENABLE)); | |
384 | I915_WRITE(WRPLL_CTL2, val & ~WRPLL_PLL_ENABLE); | |
385 | POSTING_READ(WRPLL_CTL2); | |
386 | } | |
387 | break; | |
388 | } | |
389 | ||
390 | WARN(plls->spll_refcount < 0, "Invalid SPLL refcount\n"); | |
391 | WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n"); | |
392 | WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n"); | |
393 | ||
394 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_NONE; | |
395 | } | |
396 | ||
1c0b85c5 DL |
397 | #define LC_FREQ 2700 |
398 | #define LC_FREQ_2K (LC_FREQ * 2000) | |
399 | ||
400 | #define P_MIN 2 | |
401 | #define P_MAX 64 | |
402 | #define P_INC 2 | |
403 | ||
404 | /* Constraints for PLL good behavior */ | |
405 | #define REF_MIN 48 | |
406 | #define REF_MAX 400 | |
407 | #define VCO_MIN 2400 | |
408 | #define VCO_MAX 4800 | |
409 | ||
410 | #define ABS_DIFF(a, b) ((a > b) ? (a - b) : (b - a)) | |
411 | ||
412 | struct wrpll_rnp { | |
413 | unsigned p, n2, r2; | |
414 | }; | |
415 | ||
416 | static unsigned wrpll_get_budget_for_freq(int clock) | |
6441ab5f | 417 | { |
1c0b85c5 DL |
418 | unsigned budget; |
419 | ||
420 | switch (clock) { | |
421 | case 25175000: | |
422 | case 25200000: | |
423 | case 27000000: | |
424 | case 27027000: | |
425 | case 37762500: | |
426 | case 37800000: | |
427 | case 40500000: | |
428 | case 40541000: | |
429 | case 54000000: | |
430 | case 54054000: | |
431 | case 59341000: | |
432 | case 59400000: | |
433 | case 72000000: | |
434 | case 74176000: | |
435 | case 74250000: | |
436 | case 81000000: | |
437 | case 81081000: | |
438 | case 89012000: | |
439 | case 89100000: | |
440 | case 108000000: | |
441 | case 108108000: | |
442 | case 111264000: | |
443 | case 111375000: | |
444 | case 148352000: | |
445 | case 148500000: | |
446 | case 162000000: | |
447 | case 162162000: | |
448 | case 222525000: | |
449 | case 222750000: | |
450 | case 296703000: | |
451 | case 297000000: | |
452 | budget = 0; | |
453 | break; | |
454 | case 233500000: | |
455 | case 245250000: | |
456 | case 247750000: | |
457 | case 253250000: | |
458 | case 298000000: | |
459 | budget = 1500; | |
460 | break; | |
461 | case 169128000: | |
462 | case 169500000: | |
463 | case 179500000: | |
464 | case 202000000: | |
465 | budget = 2000; | |
466 | break; | |
467 | case 256250000: | |
468 | case 262500000: | |
469 | case 270000000: | |
470 | case 272500000: | |
471 | case 273750000: | |
472 | case 280750000: | |
473 | case 281250000: | |
474 | case 286000000: | |
475 | case 291750000: | |
476 | budget = 4000; | |
477 | break; | |
478 | case 267250000: | |
479 | case 268500000: | |
480 | budget = 5000; | |
481 | break; | |
482 | default: | |
483 | budget = 1000; | |
484 | break; | |
485 | } | |
6441ab5f | 486 | |
1c0b85c5 DL |
487 | return budget; |
488 | } | |
489 | ||
490 | static void wrpll_update_rnp(uint64_t freq2k, unsigned budget, | |
491 | unsigned r2, unsigned n2, unsigned p, | |
492 | struct wrpll_rnp *best) | |
493 | { | |
494 | uint64_t a, b, c, d, diff, diff_best; | |
6441ab5f | 495 | |
1c0b85c5 DL |
496 | /* No best (r,n,p) yet */ |
497 | if (best->p == 0) { | |
498 | best->p = p; | |
499 | best->n2 = n2; | |
500 | best->r2 = r2; | |
501 | return; | |
502 | } | |
6441ab5f | 503 | |
1c0b85c5 DL |
504 | /* |
505 | * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to | |
506 | * freq2k. | |
507 | * | |
508 | * delta = 1e6 * | |
509 | * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) / | |
510 | * freq2k; | |
511 | * | |
512 | * and we would like delta <= budget. | |
513 | * | |
514 | * If the discrepancy is above the PPM-based budget, always prefer to | |
515 | * improve upon the previous solution. However, if you're within the | |
516 | * budget, try to maximize Ref * VCO, that is N / (P * R^2). | |
517 | */ | |
518 | a = freq2k * budget * p * r2; | |
519 | b = freq2k * budget * best->p * best->r2; | |
520 | diff = ABS_DIFF((freq2k * p * r2), (LC_FREQ_2K * n2)); | |
521 | diff_best = ABS_DIFF((freq2k * best->p * best->r2), | |
522 | (LC_FREQ_2K * best->n2)); | |
523 | c = 1000000 * diff; | |
524 | d = 1000000 * diff_best; | |
525 | ||
526 | if (a < c && b < d) { | |
527 | /* If both are above the budget, pick the closer */ | |
528 | if (best->p * best->r2 * diff < p * r2 * diff_best) { | |
529 | best->p = p; | |
530 | best->n2 = n2; | |
531 | best->r2 = r2; | |
532 | } | |
533 | } else if (a >= c && b < d) { | |
534 | /* If A is below the threshold but B is above it? Update. */ | |
535 | best->p = p; | |
536 | best->n2 = n2; | |
537 | best->r2 = r2; | |
538 | } else if (a >= c && b >= d) { | |
539 | /* Both are below the limit, so pick the higher n2/(r2*r2) */ | |
540 | if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) { | |
541 | best->p = p; | |
542 | best->n2 = n2; | |
543 | best->r2 = r2; | |
544 | } | |
545 | } | |
546 | /* Otherwise a < c && b >= d, do nothing */ | |
547 | } | |
548 | ||
549 | static void | |
550 | intel_ddi_calculate_wrpll(int clock /* in Hz */, | |
551 | unsigned *r2_out, unsigned *n2_out, unsigned *p_out) | |
552 | { | |
553 | uint64_t freq2k; | |
554 | unsigned p, n2, r2; | |
555 | struct wrpll_rnp best = { 0, 0, 0 }; | |
556 | unsigned budget; | |
557 | ||
558 | freq2k = clock / 100; | |
559 | ||
560 | budget = wrpll_get_budget_for_freq(clock); | |
561 | ||
562 | /* Special case handling for 540 pixel clock: bypass WR PLL entirely | |
563 | * and directly pass the LC PLL to it. */ | |
564 | if (freq2k == 5400000) { | |
565 | *n2_out = 2; | |
566 | *p_out = 1; | |
567 | *r2_out = 2; | |
568 | return; | |
569 | } | |
570 | ||
571 | /* | |
572 | * Ref = LC_FREQ / R, where Ref is the actual reference input seen by | |
573 | * the WR PLL. | |
574 | * | |
575 | * We want R so that REF_MIN <= Ref <= REF_MAX. | |
576 | * Injecting R2 = 2 * R gives: | |
577 | * REF_MAX * r2 > LC_FREQ * 2 and | |
578 | * REF_MIN * r2 < LC_FREQ * 2 | |
579 | * | |
580 | * Which means the desired boundaries for r2 are: | |
581 | * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN | |
582 | * | |
583 | */ | |
584 | for (r2 = LC_FREQ * 2 / REF_MAX + 1; | |
585 | r2 <= LC_FREQ * 2 / REF_MIN; | |
586 | r2++) { | |
587 | ||
588 | /* | |
589 | * VCO = N * Ref, that is: VCO = N * LC_FREQ / R | |
590 | * | |
591 | * Once again we want VCO_MIN <= VCO <= VCO_MAX. | |
592 | * Injecting R2 = 2 * R and N2 = 2 * N, we get: | |
593 | * VCO_MAX * r2 > n2 * LC_FREQ and | |
594 | * VCO_MIN * r2 < n2 * LC_FREQ) | |
595 | * | |
596 | * Which means the desired boundaries for n2 are: | |
597 | * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ | |
598 | */ | |
599 | for (n2 = VCO_MIN * r2 / LC_FREQ + 1; | |
600 | n2 <= VCO_MAX * r2 / LC_FREQ; | |
601 | n2++) { | |
602 | ||
603 | for (p = P_MIN; p <= P_MAX; p += P_INC) | |
604 | wrpll_update_rnp(freq2k, budget, | |
605 | r2, n2, p, &best); | |
606 | } | |
607 | } | |
6441ab5f | 608 | |
1c0b85c5 DL |
609 | *n2_out = best.n2; |
610 | *p_out = best.p; | |
611 | *r2_out = best.r2; | |
6441ab5f | 612 | |
1c0b85c5 DL |
613 | DRM_DEBUG_KMS("WRPLL: %dHz refresh rate with p=%d, n2=%d r2=%d\n", |
614 | clock, *p_out, *n2_out, *r2_out); | |
6441ab5f PZ |
615 | } |
616 | ||
ff9a6750 | 617 | bool intel_ddi_pll_mode_set(struct drm_crtc *crtc) |
6441ab5f PZ |
618 | { |
619 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
620 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
068759bd | 621 | struct drm_encoder *encoder = &intel_encoder->base; |
6441ab5f PZ |
622 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
623 | struct intel_ddi_plls *plls = &dev_priv->ddi_plls; | |
624 | int type = intel_encoder->type; | |
625 | enum pipe pipe = intel_crtc->pipe; | |
626 | uint32_t reg, val; | |
ff9a6750 | 627 | int clock = intel_crtc->config.port_clock; |
6441ab5f PZ |
628 | |
629 | /* TODO: reuse PLLs when possible (compare values) */ | |
630 | ||
631 | intel_ddi_put_crtc_pll(crtc); | |
632 | ||
068759bd PZ |
633 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
634 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
635 | ||
636 | switch (intel_dp->link_bw) { | |
637 | case DP_LINK_BW_1_62: | |
638 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810; | |
639 | break; | |
640 | case DP_LINK_BW_2_7: | |
641 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350; | |
642 | break; | |
643 | case DP_LINK_BW_5_4: | |
644 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700; | |
645 | break; | |
646 | default: | |
647 | DRM_ERROR("Link bandwidth %d unsupported\n", | |
648 | intel_dp->link_bw); | |
649 | return false; | |
650 | } | |
651 | ||
652 | /* We don't need to turn any PLL on because we'll use LCPLL. */ | |
653 | return true; | |
654 | ||
655 | } else if (type == INTEL_OUTPUT_HDMI) { | |
1c0b85c5 | 656 | unsigned p, n2, r2; |
6441ab5f PZ |
657 | |
658 | if (plls->wrpll1_refcount == 0) { | |
659 | DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n", | |
660 | pipe_name(pipe)); | |
661 | plls->wrpll1_refcount++; | |
662 | reg = WRPLL_CTL1; | |
663 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL1; | |
664 | } else if (plls->wrpll2_refcount == 0) { | |
665 | DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n", | |
666 | pipe_name(pipe)); | |
667 | plls->wrpll2_refcount++; | |
668 | reg = WRPLL_CTL2; | |
669 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL2; | |
670 | } else { | |
671 | DRM_ERROR("No WRPLLs available!\n"); | |
672 | return false; | |
673 | } | |
674 | ||
675 | WARN(I915_READ(reg) & WRPLL_PLL_ENABLE, | |
676 | "WRPLL already enabled\n"); | |
677 | ||
1c0b85c5 | 678 | intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p); |
6441ab5f PZ |
679 | |
680 | val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 | | |
681 | WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) | | |
682 | WRPLL_DIVIDER_POST(p); | |
683 | ||
684 | } else if (type == INTEL_OUTPUT_ANALOG) { | |
685 | if (plls->spll_refcount == 0) { | |
686 | DRM_DEBUG_KMS("Using SPLL on pipe %c\n", | |
687 | pipe_name(pipe)); | |
688 | plls->spll_refcount++; | |
689 | reg = SPLL_CTL; | |
690 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL; | |
00037c2e DL |
691 | } else { |
692 | DRM_ERROR("SPLL already in use\n"); | |
693 | return false; | |
6441ab5f PZ |
694 | } |
695 | ||
696 | WARN(I915_READ(reg) & SPLL_PLL_ENABLE, | |
697 | "SPLL already enabled\n"); | |
698 | ||
39bc66c9 | 699 | val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC; |
6441ab5f PZ |
700 | |
701 | } else { | |
702 | WARN(1, "Invalid DDI encoder type %d\n", type); | |
703 | return false; | |
704 | } | |
705 | ||
706 | I915_WRITE(reg, val); | |
707 | udelay(20); | |
708 | ||
709 | return true; | |
710 | } | |
711 | ||
dae84799 PZ |
712 | void intel_ddi_set_pipe_settings(struct drm_crtc *crtc) |
713 | { | |
714 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
715 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
716 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
3b117c8f | 717 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
dae84799 PZ |
718 | int type = intel_encoder->type; |
719 | uint32_t temp; | |
720 | ||
721 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { | |
722 | ||
c9809791 | 723 | temp = TRANS_MSA_SYNC_CLK; |
965e0c48 | 724 | switch (intel_crtc->config.pipe_bpp) { |
dae84799 | 725 | case 18: |
c9809791 | 726 | temp |= TRANS_MSA_6_BPC; |
dae84799 PZ |
727 | break; |
728 | case 24: | |
c9809791 | 729 | temp |= TRANS_MSA_8_BPC; |
dae84799 PZ |
730 | break; |
731 | case 30: | |
c9809791 | 732 | temp |= TRANS_MSA_10_BPC; |
dae84799 PZ |
733 | break; |
734 | case 36: | |
c9809791 | 735 | temp |= TRANS_MSA_12_BPC; |
dae84799 PZ |
736 | break; |
737 | default: | |
4e53c2e0 | 738 | BUG(); |
dae84799 | 739 | } |
c9809791 | 740 | I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); |
dae84799 PZ |
741 | } |
742 | } | |
743 | ||
8228c251 | 744 | void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) |
8d9ddbcb PZ |
745 | { |
746 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
747 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
7739c33b | 748 | struct drm_encoder *encoder = &intel_encoder->base; |
8d9ddbcb PZ |
749 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
750 | enum pipe pipe = intel_crtc->pipe; | |
3b117c8f | 751 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
174edf1f | 752 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
7739c33b | 753 | int type = intel_encoder->type; |
8d9ddbcb PZ |
754 | uint32_t temp; |
755 | ||
ad80a810 PZ |
756 | /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ |
757 | temp = TRANS_DDI_FUNC_ENABLE; | |
174edf1f | 758 | temp |= TRANS_DDI_SELECT_PORT(port); |
dfcef252 | 759 | |
965e0c48 | 760 | switch (intel_crtc->config.pipe_bpp) { |
dfcef252 | 761 | case 18: |
ad80a810 | 762 | temp |= TRANS_DDI_BPC_6; |
dfcef252 PZ |
763 | break; |
764 | case 24: | |
ad80a810 | 765 | temp |= TRANS_DDI_BPC_8; |
dfcef252 PZ |
766 | break; |
767 | case 30: | |
ad80a810 | 768 | temp |= TRANS_DDI_BPC_10; |
dfcef252 PZ |
769 | break; |
770 | case 36: | |
ad80a810 | 771 | temp |= TRANS_DDI_BPC_12; |
dfcef252 PZ |
772 | break; |
773 | default: | |
4e53c2e0 | 774 | BUG(); |
dfcef252 | 775 | } |
72662e10 | 776 | |
8d9ddbcb | 777 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
ad80a810 | 778 | temp |= TRANS_DDI_PVSYNC; |
8d9ddbcb | 779 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) |
ad80a810 | 780 | temp |= TRANS_DDI_PHSYNC; |
f63eb7c4 | 781 | |
e6f0bfc4 PZ |
782 | if (cpu_transcoder == TRANSCODER_EDP) { |
783 | switch (pipe) { | |
784 | case PIPE_A: | |
d6dd9eb1 DV |
785 | /* Can only use the always-on power well for eDP when |
786 | * not using the panel fitter, and when not using motion | |
787 | * blur mitigation (which we don't support). */ | |
b074cec8 | 788 | if (intel_crtc->config.pch_pfit.size) |
d6dd9eb1 DV |
789 | temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; |
790 | else | |
791 | temp |= TRANS_DDI_EDP_INPUT_A_ON; | |
e6f0bfc4 PZ |
792 | break; |
793 | case PIPE_B: | |
794 | temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; | |
795 | break; | |
796 | case PIPE_C: | |
797 | temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; | |
798 | break; | |
799 | default: | |
800 | BUG(); | |
801 | break; | |
802 | } | |
803 | } | |
804 | ||
7739c33b PZ |
805 | if (type == INTEL_OUTPUT_HDMI) { |
806 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
8d9ddbcb PZ |
807 | |
808 | if (intel_hdmi->has_hdmi_sink) | |
ad80a810 | 809 | temp |= TRANS_DDI_MODE_SELECT_HDMI; |
8d9ddbcb | 810 | else |
ad80a810 | 811 | temp |= TRANS_DDI_MODE_SELECT_DVI; |
8d9ddbcb | 812 | |
7739c33b | 813 | } else if (type == INTEL_OUTPUT_ANALOG) { |
ad80a810 | 814 | temp |= TRANS_DDI_MODE_SELECT_FDI; |
33d29b14 | 815 | temp |= (intel_crtc->config.fdi_lanes - 1) << 1; |
7739c33b PZ |
816 | |
817 | } else if (type == INTEL_OUTPUT_DISPLAYPORT || | |
818 | type == INTEL_OUTPUT_EDP) { | |
819 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
820 | ||
ad80a810 | 821 | temp |= TRANS_DDI_MODE_SELECT_DP_SST; |
7739c33b | 822 | |
17aa6be9 | 823 | temp |= DDI_PORT_WIDTH(intel_dp->lane_count); |
8d9ddbcb | 824 | } else { |
84f44ce7 VS |
825 | WARN(1, "Invalid encoder type %d for pipe %c\n", |
826 | intel_encoder->type, pipe_name(pipe)); | |
8d9ddbcb PZ |
827 | } |
828 | ||
ad80a810 | 829 | I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); |
8d9ddbcb | 830 | } |
72662e10 | 831 | |
ad80a810 PZ |
832 | void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, |
833 | enum transcoder cpu_transcoder) | |
8d9ddbcb | 834 | { |
ad80a810 | 835 | uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
8d9ddbcb PZ |
836 | uint32_t val = I915_READ(reg); |
837 | ||
ad80a810 PZ |
838 | val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK); |
839 | val |= TRANS_DDI_PORT_NONE; | |
8d9ddbcb | 840 | I915_WRITE(reg, val); |
72662e10 ED |
841 | } |
842 | ||
bcbc889b PZ |
843 | bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) |
844 | { | |
845 | struct drm_device *dev = intel_connector->base.dev; | |
846 | struct drm_i915_private *dev_priv = dev->dev_private; | |
847 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
848 | int type = intel_connector->base.connector_type; | |
849 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
850 | enum pipe pipe = 0; | |
851 | enum transcoder cpu_transcoder; | |
852 | uint32_t tmp; | |
853 | ||
854 | if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) | |
855 | return false; | |
856 | ||
857 | if (port == PORT_A) | |
858 | cpu_transcoder = TRANSCODER_EDP; | |
859 | else | |
1a240d4d | 860 | cpu_transcoder = (enum transcoder) pipe; |
bcbc889b PZ |
861 | |
862 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
863 | ||
864 | switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { | |
865 | case TRANS_DDI_MODE_SELECT_HDMI: | |
866 | case TRANS_DDI_MODE_SELECT_DVI: | |
867 | return (type == DRM_MODE_CONNECTOR_HDMIA); | |
868 | ||
869 | case TRANS_DDI_MODE_SELECT_DP_SST: | |
870 | if (type == DRM_MODE_CONNECTOR_eDP) | |
871 | return true; | |
872 | case TRANS_DDI_MODE_SELECT_DP_MST: | |
873 | return (type == DRM_MODE_CONNECTOR_DisplayPort); | |
874 | ||
875 | case TRANS_DDI_MODE_SELECT_FDI: | |
876 | return (type == DRM_MODE_CONNECTOR_VGA); | |
877 | ||
878 | default: | |
879 | return false; | |
880 | } | |
881 | } | |
882 | ||
85234cdc DV |
883 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, |
884 | enum pipe *pipe) | |
885 | { | |
886 | struct drm_device *dev = encoder->base.dev; | |
887 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fe43d3f5 | 888 | enum port port = intel_ddi_get_encoder_port(encoder); |
85234cdc DV |
889 | u32 tmp; |
890 | int i; | |
891 | ||
fe43d3f5 | 892 | tmp = I915_READ(DDI_BUF_CTL(port)); |
85234cdc DV |
893 | |
894 | if (!(tmp & DDI_BUF_CTL_ENABLE)) | |
895 | return false; | |
896 | ||
ad80a810 PZ |
897 | if (port == PORT_A) { |
898 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
85234cdc | 899 | |
ad80a810 PZ |
900 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { |
901 | case TRANS_DDI_EDP_INPUT_A_ON: | |
902 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
903 | *pipe = PIPE_A; | |
904 | break; | |
905 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
906 | *pipe = PIPE_B; | |
907 | break; | |
908 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
909 | *pipe = PIPE_C; | |
910 | break; | |
911 | } | |
912 | ||
913 | return true; | |
914 | } else { | |
915 | for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) { | |
916 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(i)); | |
917 | ||
918 | if ((tmp & TRANS_DDI_PORT_MASK) | |
919 | == TRANS_DDI_SELECT_PORT(port)) { | |
920 | *pipe = i; | |
921 | return true; | |
922 | } | |
85234cdc DV |
923 | } |
924 | } | |
925 | ||
84f44ce7 | 926 | DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port)); |
85234cdc | 927 | |
22f9fe50 | 928 | return false; |
85234cdc DV |
929 | } |
930 | ||
6441ab5f PZ |
931 | static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv, |
932 | enum pipe pipe) | |
933 | { | |
934 | uint32_t temp, ret; | |
a42f704b | 935 | enum port port = I915_MAX_PORTS; |
ad80a810 PZ |
936 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
937 | pipe); | |
6441ab5f PZ |
938 | int i; |
939 | ||
ad80a810 PZ |
940 | if (cpu_transcoder == TRANSCODER_EDP) { |
941 | port = PORT_A; | |
942 | } else { | |
943 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
944 | temp &= TRANS_DDI_PORT_MASK; | |
945 | ||
946 | for (i = PORT_B; i <= PORT_E; i++) | |
947 | if (temp == TRANS_DDI_SELECT_PORT(i)) | |
948 | port = i; | |
949 | } | |
6441ab5f | 950 | |
a42f704b DL |
951 | if (port == I915_MAX_PORTS) { |
952 | WARN(1, "Pipe %c enabled on an unknown port\n", | |
953 | pipe_name(pipe)); | |
954 | ret = PORT_CLK_SEL_NONE; | |
955 | } else { | |
956 | ret = I915_READ(PORT_CLK_SEL(port)); | |
957 | DRM_DEBUG_KMS("Pipe %c connected to port %c using clock " | |
958 | "0x%08x\n", pipe_name(pipe), port_name(port), | |
959 | ret); | |
960 | } | |
6441ab5f PZ |
961 | |
962 | return ret; | |
963 | } | |
964 | ||
965 | void intel_ddi_setup_hw_pll_state(struct drm_device *dev) | |
966 | { | |
967 | struct drm_i915_private *dev_priv = dev->dev_private; | |
968 | enum pipe pipe; | |
969 | struct intel_crtc *intel_crtc; | |
970 | ||
971 | for_each_pipe(pipe) { | |
972 | intel_crtc = | |
973 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
974 | ||
975 | if (!intel_crtc->active) | |
976 | continue; | |
977 | ||
978 | intel_crtc->ddi_pll_sel = intel_ddi_get_crtc_pll(dev_priv, | |
979 | pipe); | |
980 | ||
981 | switch (intel_crtc->ddi_pll_sel) { | |
982 | case PORT_CLK_SEL_SPLL: | |
983 | dev_priv->ddi_plls.spll_refcount++; | |
984 | break; | |
985 | case PORT_CLK_SEL_WRPLL1: | |
986 | dev_priv->ddi_plls.wrpll1_refcount++; | |
987 | break; | |
988 | case PORT_CLK_SEL_WRPLL2: | |
989 | dev_priv->ddi_plls.wrpll2_refcount++; | |
990 | break; | |
991 | } | |
992 | } | |
993 | } | |
994 | ||
fc914639 PZ |
995 | void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc) |
996 | { | |
997 | struct drm_crtc *crtc = &intel_crtc->base; | |
998 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
999 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
1000 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
3b117c8f | 1001 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
fc914639 | 1002 | |
bb523fc0 PZ |
1003 | if (cpu_transcoder != TRANSCODER_EDP) |
1004 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), | |
1005 | TRANS_CLK_SEL_PORT(port)); | |
fc914639 PZ |
1006 | } |
1007 | ||
1008 | void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc) | |
1009 | { | |
1010 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; | |
3b117c8f | 1011 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
fc914639 | 1012 | |
bb523fc0 PZ |
1013 | if (cpu_transcoder != TRANSCODER_EDP) |
1014 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), | |
1015 | TRANS_CLK_SEL_DISABLED); | |
fc914639 PZ |
1016 | } |
1017 | ||
00c09d70 | 1018 | static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) |
6441ab5f | 1019 | { |
c19b0669 PZ |
1020 | struct drm_encoder *encoder = &intel_encoder->base; |
1021 | struct drm_crtc *crtc = encoder->crtc; | |
1022 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; | |
6441ab5f PZ |
1023 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1024 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
82a4d9c0 | 1025 | int type = intel_encoder->type; |
6441ab5f | 1026 | |
82a4d9c0 PZ |
1027 | if (type == INTEL_OUTPUT_EDP) { |
1028 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1029 | ironlake_edp_panel_vdd_on(intel_dp); | |
1030 | ironlake_edp_panel_on(intel_dp); | |
1031 | ironlake_edp_panel_vdd_off(intel_dp, true); | |
1032 | } | |
6441ab5f | 1033 | |
82a4d9c0 | 1034 | WARN_ON(intel_crtc->ddi_pll_sel == PORT_CLK_SEL_NONE); |
6441ab5f | 1035 | I915_WRITE(PORT_CLK_SEL(port), intel_crtc->ddi_pll_sel); |
c19b0669 | 1036 | |
82a4d9c0 | 1037 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
c19b0669 PZ |
1038 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
1039 | ||
1040 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); | |
1041 | intel_dp_start_link_train(intel_dp); | |
1042 | intel_dp_complete_link_train(intel_dp); | |
3ab9c637 ID |
1043 | if (port != PORT_A) |
1044 | intel_dp_stop_link_train(intel_dp); | |
c19b0669 | 1045 | } |
6441ab5f PZ |
1046 | } |
1047 | ||
00c09d70 | 1048 | static void intel_ddi_post_disable(struct intel_encoder *intel_encoder) |
6441ab5f PZ |
1049 | { |
1050 | struct drm_encoder *encoder = &intel_encoder->base; | |
1051 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; | |
1052 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
82a4d9c0 | 1053 | int type = intel_encoder->type; |
2886e93f | 1054 | uint32_t val; |
a836bdf9 | 1055 | bool wait = false; |
2886e93f PZ |
1056 | |
1057 | val = I915_READ(DDI_BUF_CTL(port)); | |
1058 | if (val & DDI_BUF_CTL_ENABLE) { | |
1059 | val &= ~DDI_BUF_CTL_ENABLE; | |
1060 | I915_WRITE(DDI_BUF_CTL(port), val); | |
a836bdf9 | 1061 | wait = true; |
2886e93f | 1062 | } |
6441ab5f | 1063 | |
a836bdf9 PZ |
1064 | val = I915_READ(DP_TP_CTL(port)); |
1065 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
1066 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
1067 | I915_WRITE(DP_TP_CTL(port), val); | |
1068 | ||
1069 | if (wait) | |
1070 | intel_wait_ddi_buf_idle(dev_priv, port); | |
1071 | ||
82a4d9c0 PZ |
1072 | if (type == INTEL_OUTPUT_EDP) { |
1073 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1074 | ironlake_edp_panel_vdd_on(intel_dp); | |
1075 | ironlake_edp_panel_off(intel_dp); | |
1076 | } | |
1077 | ||
6441ab5f PZ |
1078 | I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); |
1079 | } | |
1080 | ||
00c09d70 | 1081 | static void intel_enable_ddi(struct intel_encoder *intel_encoder) |
72662e10 | 1082 | { |
6547fef8 | 1083 | struct drm_encoder *encoder = &intel_encoder->base; |
7b9f35a6 WX |
1084 | struct drm_crtc *crtc = encoder->crtc; |
1085 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1086 | int pipe = intel_crtc->pipe; | |
6547fef8 | 1087 | struct drm_device *dev = encoder->dev; |
72662e10 | 1088 | struct drm_i915_private *dev_priv = dev->dev_private; |
6547fef8 PZ |
1089 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
1090 | int type = intel_encoder->type; | |
7b9f35a6 | 1091 | uint32_t tmp; |
72662e10 | 1092 | |
6547fef8 | 1093 | if (type == INTEL_OUTPUT_HDMI) { |
876a8cdf DL |
1094 | struct intel_digital_port *intel_dig_port = |
1095 | enc_to_dig_port(encoder); | |
1096 | ||
6547fef8 PZ |
1097 | /* In HDMI/DVI mode, the port width, and swing/emphasis values |
1098 | * are ignored so nothing special needs to be done besides | |
1099 | * enabling the port. | |
1100 | */ | |
876a8cdf | 1101 | I915_WRITE(DDI_BUF_CTL(port), |
bcf53de4 SM |
1102 | intel_dig_port->saved_port_bits | |
1103 | DDI_BUF_CTL_ENABLE); | |
d6c50ff8 PZ |
1104 | } else if (type == INTEL_OUTPUT_EDP) { |
1105 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1106 | ||
3ab9c637 ID |
1107 | if (port == PORT_A) |
1108 | intel_dp_stop_link_train(intel_dp); | |
1109 | ||
d6c50ff8 | 1110 | ironlake_edp_backlight_on(intel_dp); |
4906557e | 1111 | intel_edp_psr_enable(intel_dp); |
6547fef8 | 1112 | } |
7b9f35a6 | 1113 | |
c77bf565 | 1114 | if (intel_crtc->eld_vld && type != INTEL_OUTPUT_EDP) { |
7b9f35a6 WX |
1115 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); |
1116 | tmp |= ((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4)); | |
1117 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); | |
1118 | } | |
5ab432ef DV |
1119 | } |
1120 | ||
00c09d70 | 1121 | static void intel_disable_ddi(struct intel_encoder *intel_encoder) |
5ab432ef | 1122 | { |
d6c50ff8 | 1123 | struct drm_encoder *encoder = &intel_encoder->base; |
7b9f35a6 WX |
1124 | struct drm_crtc *crtc = encoder->crtc; |
1125 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1126 | int pipe = intel_crtc->pipe; | |
d6c50ff8 | 1127 | int type = intel_encoder->type; |
7b9f35a6 WX |
1128 | struct drm_device *dev = encoder->dev; |
1129 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1130 | uint32_t tmp; | |
d6c50ff8 | 1131 | |
c77bf565 PZ |
1132 | if (intel_crtc->eld_vld && type != INTEL_OUTPUT_EDP) { |
1133 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); | |
1134 | tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << | |
1135 | (pipe * 4)); | |
1136 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); | |
1137 | } | |
2831d842 | 1138 | |
d6c50ff8 PZ |
1139 | if (type == INTEL_OUTPUT_EDP) { |
1140 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1141 | ||
4906557e | 1142 | intel_edp_psr_disable(intel_dp); |
d6c50ff8 PZ |
1143 | ironlake_edp_backlight_off(intel_dp); |
1144 | } | |
72662e10 | 1145 | } |
79f689aa | 1146 | |
b8fc2f6a | 1147 | int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv) |
79f689aa PZ |
1148 | { |
1149 | if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
b2b877ff | 1150 | return 450000; |
79f689aa PZ |
1151 | else if ((I915_READ(LCPLL_CTL) & LCPLL_CLK_FREQ_MASK) == |
1152 | LCPLL_CLK_FREQ_450) | |
b2b877ff | 1153 | return 450000; |
d567b07f | 1154 | else if (IS_ULT(dev_priv->dev)) |
b2b877ff | 1155 | return 337500; |
79f689aa | 1156 | else |
b2b877ff | 1157 | return 540000; |
79f689aa PZ |
1158 | } |
1159 | ||
1160 | void intel_ddi_pll_init(struct drm_device *dev) | |
1161 | { | |
1162 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1163 | uint32_t val = I915_READ(LCPLL_CTL); | |
1164 | ||
1165 | /* The LCPLL register should be turned on by the BIOS. For now let's | |
1166 | * just check its state and print errors in case something is wrong. | |
1167 | * Don't even try to turn it on. | |
1168 | */ | |
1169 | ||
b2b877ff | 1170 | DRM_DEBUG_KMS("CDCLK running at %dKHz\n", |
79f689aa PZ |
1171 | intel_ddi_get_cdclk_freq(dev_priv)); |
1172 | ||
1173 | if (val & LCPLL_CD_SOURCE_FCLK) | |
1174 | DRM_ERROR("CDCLK source is not LCPLL\n"); | |
1175 | ||
1176 | if (val & LCPLL_PLL_DISABLE) | |
1177 | DRM_ERROR("LCPLL is disabled\n"); | |
1178 | } | |
c19b0669 PZ |
1179 | |
1180 | void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder) | |
1181 | { | |
174edf1f PZ |
1182 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
1183 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
c19b0669 | 1184 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
174edf1f | 1185 | enum port port = intel_dig_port->port; |
c19b0669 | 1186 | uint32_t val; |
f3e227df | 1187 | bool wait = false; |
c19b0669 PZ |
1188 | |
1189 | if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) { | |
1190 | val = I915_READ(DDI_BUF_CTL(port)); | |
1191 | if (val & DDI_BUF_CTL_ENABLE) { | |
1192 | val &= ~DDI_BUF_CTL_ENABLE; | |
1193 | I915_WRITE(DDI_BUF_CTL(port), val); | |
1194 | wait = true; | |
1195 | } | |
1196 | ||
1197 | val = I915_READ(DP_TP_CTL(port)); | |
1198 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
1199 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
1200 | I915_WRITE(DP_TP_CTL(port), val); | |
1201 | POSTING_READ(DP_TP_CTL(port)); | |
1202 | ||
1203 | if (wait) | |
1204 | intel_wait_ddi_buf_idle(dev_priv, port); | |
1205 | } | |
1206 | ||
1207 | val = DP_TP_CTL_ENABLE | DP_TP_CTL_MODE_SST | | |
1208 | DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; | |
1209 | if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN) | |
1210 | val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; | |
1211 | I915_WRITE(DP_TP_CTL(port), val); | |
1212 | POSTING_READ(DP_TP_CTL(port)); | |
1213 | ||
1214 | intel_dp->DP |= DDI_BUF_CTL_ENABLE; | |
1215 | I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP); | |
1216 | POSTING_READ(DDI_BUF_CTL(port)); | |
1217 | ||
1218 | udelay(600); | |
1219 | } | |
00c09d70 | 1220 | |
1ad960f2 PZ |
1221 | void intel_ddi_fdi_disable(struct drm_crtc *crtc) |
1222 | { | |
1223 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
1224 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
1225 | uint32_t val; | |
1226 | ||
1227 | intel_ddi_post_disable(intel_encoder); | |
1228 | ||
1229 | val = I915_READ(_FDI_RXA_CTL); | |
1230 | val &= ~FDI_RX_ENABLE; | |
1231 | I915_WRITE(_FDI_RXA_CTL, val); | |
1232 | ||
1233 | val = I915_READ(_FDI_RXA_MISC); | |
1234 | val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); | |
1235 | val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); | |
1236 | I915_WRITE(_FDI_RXA_MISC, val); | |
1237 | ||
1238 | val = I915_READ(_FDI_RXA_CTL); | |
1239 | val &= ~FDI_PCDCLK; | |
1240 | I915_WRITE(_FDI_RXA_CTL, val); | |
1241 | ||
1242 | val = I915_READ(_FDI_RXA_CTL); | |
1243 | val &= ~FDI_RX_PLL_ENABLE; | |
1244 | I915_WRITE(_FDI_RXA_CTL, val); | |
1245 | } | |
1246 | ||
00c09d70 PZ |
1247 | static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder) |
1248 | { | |
1249 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
1250 | int type = intel_encoder->type; | |
1251 | ||
1252 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) | |
1253 | intel_dp_check_link_status(intel_dp); | |
1254 | } | |
1255 | ||
045ac3b5 JB |
1256 | static void intel_ddi_get_config(struct intel_encoder *encoder, |
1257 | struct intel_crtc_config *pipe_config) | |
1258 | { | |
1259 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
1260 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
1261 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; | |
1262 | u32 temp, flags = 0; | |
1263 | ||
1264 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
1265 | if (temp & TRANS_DDI_PHSYNC) | |
1266 | flags |= DRM_MODE_FLAG_PHSYNC; | |
1267 | else | |
1268 | flags |= DRM_MODE_FLAG_NHSYNC; | |
1269 | if (temp & TRANS_DDI_PVSYNC) | |
1270 | flags |= DRM_MODE_FLAG_PVSYNC; | |
1271 | else | |
1272 | flags |= DRM_MODE_FLAG_NVSYNC; | |
1273 | ||
1274 | pipe_config->adjusted_mode.flags |= flags; | |
045ac3b5 JB |
1275 | } |
1276 | ||
00c09d70 PZ |
1277 | static void intel_ddi_destroy(struct drm_encoder *encoder) |
1278 | { | |
1279 | /* HDMI has nothing special to destroy, so we can go with this. */ | |
1280 | intel_dp_encoder_destroy(encoder); | |
1281 | } | |
1282 | ||
5bfe2ac0 DV |
1283 | static bool intel_ddi_compute_config(struct intel_encoder *encoder, |
1284 | struct intel_crtc_config *pipe_config) | |
00c09d70 | 1285 | { |
5bfe2ac0 | 1286 | int type = encoder->type; |
eccb140b | 1287 | int port = intel_ddi_get_encoder_port(encoder); |
00c09d70 | 1288 | |
5bfe2ac0 | 1289 | WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n"); |
00c09d70 | 1290 | |
eccb140b DV |
1291 | if (port == PORT_A) |
1292 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
1293 | ||
00c09d70 | 1294 | if (type == INTEL_OUTPUT_HDMI) |
5bfe2ac0 | 1295 | return intel_hdmi_compute_config(encoder, pipe_config); |
00c09d70 | 1296 | else |
5bfe2ac0 | 1297 | return intel_dp_compute_config(encoder, pipe_config); |
00c09d70 PZ |
1298 | } |
1299 | ||
1300 | static const struct drm_encoder_funcs intel_ddi_funcs = { | |
1301 | .destroy = intel_ddi_destroy, | |
1302 | }; | |
1303 | ||
00c09d70 PZ |
1304 | void intel_ddi_init(struct drm_device *dev, enum port port) |
1305 | { | |
876a8cdf | 1306 | struct drm_i915_private *dev_priv = dev->dev_private; |
00c09d70 PZ |
1307 | struct intel_digital_port *intel_dig_port; |
1308 | struct intel_encoder *intel_encoder; | |
1309 | struct drm_encoder *encoder; | |
1310 | struct intel_connector *hdmi_connector = NULL; | |
1311 | struct intel_connector *dp_connector = NULL; | |
1312 | ||
1313 | intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL); | |
1314 | if (!intel_dig_port) | |
1315 | return; | |
1316 | ||
1317 | dp_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); | |
1318 | if (!dp_connector) { | |
1319 | kfree(intel_dig_port); | |
1320 | return; | |
1321 | } | |
1322 | ||
00c09d70 PZ |
1323 | intel_encoder = &intel_dig_port->base; |
1324 | encoder = &intel_encoder->base; | |
1325 | ||
1326 | drm_encoder_init(dev, encoder, &intel_ddi_funcs, | |
1327 | DRM_MODE_ENCODER_TMDS); | |
00c09d70 | 1328 | |
5bfe2ac0 | 1329 | intel_encoder->compute_config = intel_ddi_compute_config; |
c7d8be30 | 1330 | intel_encoder->mode_set = intel_ddi_mode_set; |
00c09d70 PZ |
1331 | intel_encoder->enable = intel_enable_ddi; |
1332 | intel_encoder->pre_enable = intel_ddi_pre_enable; | |
1333 | intel_encoder->disable = intel_disable_ddi; | |
1334 | intel_encoder->post_disable = intel_ddi_post_disable; | |
1335 | intel_encoder->get_hw_state = intel_ddi_get_hw_state; | |
045ac3b5 | 1336 | intel_encoder->get_config = intel_ddi_get_config; |
00c09d70 PZ |
1337 | |
1338 | intel_dig_port->port = port; | |
bcf53de4 SM |
1339 | intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & |
1340 | (DDI_BUF_PORT_REVERSAL | | |
1341 | DDI_A_4_LANES); | |
00c09d70 PZ |
1342 | intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); |
1343 | ||
1344 | intel_encoder->type = INTEL_OUTPUT_UNKNOWN; | |
1345 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
1346 | intel_encoder->cloneable = false; | |
1347 | intel_encoder->hot_plug = intel_ddi_hot_plug; | |
1348 | ||
b2f246a8 | 1349 | if (!intel_dp_init_connector(intel_dig_port, dp_connector)) { |
15b1d171 PZ |
1350 | drm_encoder_cleanup(encoder); |
1351 | kfree(intel_dig_port); | |
b2f246a8 | 1352 | kfree(dp_connector); |
16c25533 | 1353 | return; |
b2f246a8 | 1354 | } |
21a8e6a4 DV |
1355 | |
1356 | if (intel_encoder->type != INTEL_OUTPUT_EDP) { | |
1357 | hdmi_connector = kzalloc(sizeof(struct intel_connector), | |
1358 | GFP_KERNEL); | |
1359 | if (!hdmi_connector) { | |
1360 | return; | |
1361 | } | |
1362 | ||
1363 | intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); | |
1364 | intel_hdmi_init_connector(intel_dig_port, hdmi_connector); | |
1365 | } | |
00c09d70 | 1366 | } |