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drm/i915: Refactor platform specifics out of intel_get_shared_dpll()
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ddi.c
CommitLineData
45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include "i915_drv.h"
29#include "intel_drv.h"
30
10122051
JN		 31struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
f8896f5d 34 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
10122051
JN		 35};
36
45244b87
ED		 37/* HDMI/DVI modes ignore everything but the last 2 items. So we share
38 * them for both DP and FDI transports, allowing those ports to
39 * automatically adapt to HDMI connections as well
40 */
10122051 41static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
f8896f5d
DW		 42 { 0x00FFFFFF, 0x0006000E, 0x0 },
43 { 0x00D75FFF, 0x0005000A, 0x0 },
44 { 0x00C30FFF, 0x00040006, 0x0 },
45 { 0x80AAAFFF, 0x000B0000, 0x0 },
46 { 0x00FFFFFF, 0x0005000A, 0x0 },
47 { 0x00D75FFF, 0x000C0004, 0x0 },
48 { 0x80C30FFF, 0x000B0000, 0x0 },
49 { 0x00FFFFFF, 0x00040006, 0x0 },
50 { 0x80D75FFF, 0x000B0000, 0x0 },
45244b87
ED		 51};
52
10122051 53static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
f8896f5d
DW		 54 { 0x00FFFFFF, 0x0007000E, 0x0 },
55 { 0x00D75FFF, 0x000F000A, 0x0 },
56 { 0x00C30FFF, 0x00060006, 0x0 },
57 { 0x00AAAFFF, 0x001E0000, 0x0 },
58 { 0x00FFFFFF, 0x000F000A, 0x0 },
59 { 0x00D75FFF, 0x00160004, 0x0 },
60 { 0x00C30FFF, 0x001E0000, 0x0 },
61 { 0x00FFFFFF, 0x00060006, 0x0 },
62 { 0x00D75FFF, 0x001E0000, 0x0 },
6acab15a
PZ		 63};
64
10122051
JN		 65static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
66 /* Idx NT mV d T mV d db */
f8896f5d
DW		 67 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
68 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
69 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
70 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
71 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
72 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
73 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
74 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
75 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
76 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
77 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
78 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
45244b87
ED		 79};
80
10122051 81static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
f8896f5d
DW		 82 { 0x00FFFFFF, 0x00000012, 0x0 },
83 { 0x00EBAFFF, 0x00020011, 0x0 },
84 { 0x00C71FFF, 0x0006000F, 0x0 },
85 { 0x00AAAFFF, 0x000E000A, 0x0 },
86 { 0x00FFFFFF, 0x00020011, 0x0 },
87 { 0x00DB6FFF, 0x0005000F, 0x0 },
88 { 0x00BEEFFF, 0x000A000C, 0x0 },
89 { 0x00FFFFFF, 0x0005000F, 0x0 },
90 { 0x00DB6FFF, 0x000A000C, 0x0 },
300644c7
PZ		 91};
92
10122051 93static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
f8896f5d
DW		 94 { 0x00FFFFFF, 0x0007000E, 0x0 },
95 { 0x00D75FFF, 0x000E000A, 0x0 },
96 { 0x00BEFFFF, 0x00140006, 0x0 },
97 { 0x80B2CFFF, 0x001B0002, 0x0 },
98 { 0x00FFFFFF, 0x000E000A, 0x0 },
99 { 0x00DB6FFF, 0x00160005, 0x0 },
100 { 0x80C71FFF, 0x001A0002, 0x0 },
101 { 0x00F7DFFF, 0x00180004, 0x0 },
102 { 0x80D75FFF, 0x001B0002, 0x0 },
e58623cb
AR		 103};
104
10122051 105static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
f8896f5d
DW		 106 { 0x00FFFFFF, 0x0001000E, 0x0 },
107 { 0x00D75FFF, 0x0004000A, 0x0 },
108 { 0x00C30FFF, 0x00070006, 0x0 },
109 { 0x00AAAFFF, 0x000C0000, 0x0 },
110 { 0x00FFFFFF, 0x0004000A, 0x0 },
111 { 0x00D75FFF, 0x00090004, 0x0 },
112 { 0x00C30FFF, 0x000C0000, 0x0 },
113 { 0x00FFFFFF, 0x00070006, 0x0 },
114 { 0x00D75FFF, 0x000C0000, 0x0 },
e58623cb
AR		 115};
116
10122051
JN		 117static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
118 /* Idx NT mV d T mV df db */
f8896f5d
DW		 119 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
120 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
121 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
122 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
123 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
124 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
125 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
126 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
127 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
128 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
a26aa8ba
DL		 129};
130
5f8b2531 131/* Skylake H and S */
7f88e3af 132static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
f8896f5d
DW		 133 { 0x00002016, 0x000000A0, 0x0 },
134 { 0x00005012, 0x0000009B, 0x0 },
135 { 0x00007011, 0x00000088, 0x0 },
d7097cff 136 { 0x80009010, 0x000000C0, 0x1 },
f8896f5d
DW		 137 { 0x00002016, 0x0000009B, 0x0 },
138 { 0x00005012, 0x00000088, 0x0 },
d7097cff 139 { 0x80007011, 0x000000C0, 0x1 },
f8896f5d 140 { 0x00002016, 0x000000DF, 0x0 },
d7097cff 141 { 0x80005012, 0x000000C0, 0x1 },
7f88e3af
DL		 142};
143
f8896f5d
DW		 144/* Skylake U */
145static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
5f8b2531 146 { 0x0000201B, 0x000000A2, 0x0 },
f8896f5d 147 { 0x00005012, 0x00000088, 0x0 },
63ebce1f 148 { 0x80007011, 0x000000CD, 0x0 },
d7097cff 149 { 0x80009010, 0x000000C0, 0x1 },
5f8b2531 150 { 0x0000201B, 0x0000009D, 0x0 },
d7097cff
RV		 151 { 0x80005012, 0x000000C0, 0x1 },
152 { 0x80007011, 0x000000C0, 0x1 },
f8896f5d 153 { 0x00002016, 0x00000088, 0x0 },
d7097cff 154 { 0x80005012, 0x000000C0, 0x1 },
f8896f5d
DW		 155};
156
5f8b2531
RV		 157/* Skylake Y */
158static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
f8896f5d
DW		 159 { 0x00000018, 0x000000A2, 0x0 },
160 { 0x00005012, 0x00000088, 0x0 },
63ebce1f 161 { 0x80007011, 0x000000CD, 0x0 },
d7097cff 162 { 0x80009010, 0x000000C0, 0x3 },
f8896f5d 163 { 0x00000018, 0x0000009D, 0x0 },
d7097cff
RV		 164 { 0x80005012, 0x000000C0, 0x3 },
165 { 0x80007011, 0x000000C0, 0x3 },
f8896f5d 166 { 0x00000018, 0x00000088, 0x0 },
d7097cff 167 { 0x80005012, 0x000000C0, 0x3 },
f8896f5d
DW		 168};
169
170/*
5f8b2531 171 * Skylake H and S
f8896f5d
DW		 172 * eDP 1.4 low vswing translation parameters
173 */
7ad14a29 174static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
f8896f5d
DW		 175 { 0x00000018, 0x000000A8, 0x0 },
176 { 0x00004013, 0x000000A9, 0x0 },
177 { 0x00007011, 0x000000A2, 0x0 },
178 { 0x00009010, 0x0000009C, 0x0 },
179 { 0x00000018, 0x000000A9, 0x0 },
180 { 0x00006013, 0x000000A2, 0x0 },
181 { 0x00007011, 0x000000A6, 0x0 },
182 { 0x00000018, 0x000000AB, 0x0 },
183 { 0x00007013, 0x0000009F, 0x0 },
184 { 0x00000018, 0x000000DF, 0x0 },
185};
186
187/*
188 * Skylake U
189 * eDP 1.4 low vswing translation parameters
190 */
191static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
192 { 0x00000018, 0x000000A8, 0x0 },
193 { 0x00004013, 0x000000A9, 0x0 },
194 { 0x00007011, 0x000000A2, 0x0 },
195 { 0x00009010, 0x0000009C, 0x0 },
196 { 0x00000018, 0x000000A9, 0x0 },
197 { 0x00006013, 0x000000A2, 0x0 },
198 { 0x00007011, 0x000000A6, 0x0 },
199 { 0x00002016, 0x000000AB, 0x0 },
200 { 0x00005013, 0x0000009F, 0x0 },
201 { 0x00000018, 0x000000DF, 0x0 },
7ad14a29
SJ		 202};
203
f8896f5d 204/*
5f8b2531 205 * Skylake Y
f8896f5d
DW		 206 * eDP 1.4 low vswing translation parameters
207 */
5f8b2531 208static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
f8896f5d
DW		 209 { 0x00000018, 0x000000A8, 0x0 },
210 { 0x00004013, 0x000000AB, 0x0 },
211 { 0x00007011, 0x000000A4, 0x0 },
212 { 0x00009010, 0x000000DF, 0x0 },
213 { 0x00000018, 0x000000AA, 0x0 },
214 { 0x00006013, 0x000000A4, 0x0 },
215 { 0x00007011, 0x0000009D, 0x0 },
216 { 0x00000018, 0x000000A0, 0x0 },
217 { 0x00006012, 0x000000DF, 0x0 },
218 { 0x00000018, 0x0000008A, 0x0 },
219};
7ad14a29 220
5f8b2531 221/* Skylake U, H and S */
7f88e3af 222static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
f8896f5d
DW		 223 { 0x00000018, 0x000000AC, 0x0 },
224 { 0x00005012, 0x0000009D, 0x0 },
225 { 0x00007011, 0x00000088, 0x0 },
226 { 0x00000018, 0x000000A1, 0x0 },
227 { 0x00000018, 0x00000098, 0x0 },
228 { 0x00004013, 0x00000088, 0x0 },
2e78416e 229 { 0x80006012, 0x000000CD, 0x1 },
f8896f5d 230 { 0x00000018, 0x000000DF, 0x0 },
2e78416e
RV		 231 { 0x80003015, 0x000000CD, 0x1 }, /* Default */
232 { 0x80003015, 0x000000C0, 0x1 },
233 { 0x80000018, 0x000000C0, 0x1 },
f8896f5d
DW		 234};
235
5f8b2531
RV		 236/* Skylake Y */
237static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
f8896f5d
DW		 238 { 0x00000018, 0x000000A1, 0x0 },
239 { 0x00005012, 0x000000DF, 0x0 },
2e78416e 240 { 0x80007011, 0x000000CB, 0x3 },
f8896f5d
DW		 241 { 0x00000018, 0x000000A4, 0x0 },
242 { 0x00000018, 0x0000009D, 0x0 },
243 { 0x00004013, 0x00000080, 0x0 },
2e78416e 244 { 0x80006013, 0x000000C0, 0x3 },
f8896f5d 245 { 0x00000018, 0x0000008A, 0x0 },
2e78416e
RV		 246 { 0x80003015, 0x000000C0, 0x3 }, /* Default */
247 { 0x80003015, 0x000000C0, 0x3 },
248 { 0x80000018, 0x000000C0, 0x3 },
7f88e3af
DL		 249};
250
96fb9f9b
VK		 251struct bxt_ddi_buf_trans {
252 u32 margin; /* swing value */
253 u32 scale; /* scale value */
254 u32 enable; /* scale enable */
255 u32 deemphasis;
256 bool default_index; /* true if the entry represents default value */
257};
258
96fb9f9b
VK		 259static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
260 /* Idx NT mV diff db */
fe4c63c8
ID		 261 { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */
262 { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
263 { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */
264 { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
265 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
266 { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
267 { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */
268 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
269 { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
f8896f5d 270 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
96fb9f9b
VK		 271};
272
d9d7000d
SJ		 273static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
274 /* Idx NT mV diff db */
275 { 26, 0, 0, 128, false }, /* 0: 200 0 */
276 { 38, 0, 0, 112, false }, /* 1: 200 1.5 */
277 { 48, 0, 0, 96, false }, /* 2: 200 4 */
278 { 54, 0, 0, 69, false }, /* 3: 200 6 */
279 { 32, 0, 0, 128, false }, /* 4: 250 0 */
280 { 48, 0, 0, 104, false }, /* 5: 250 1.5 */
281 { 54, 0, 0, 85, false }, /* 6: 250 4 */
282 { 43, 0, 0, 128, false }, /* 7: 300 0 */
283 { 54, 0, 0, 101, false }, /* 8: 300 1.5 */
284 { 48, 0, 0, 128, false }, /* 9: 300 0 */
285};
286
96fb9f9b
VK		 287/* BSpec has 2 recommended values - entries 0 and 8.
288 * Using the entry with higher vswing.
289 */
290static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
291 /* Idx NT mV diff db */
fe4c63c8
ID		 292 { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */
293 { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
294 { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */
295 { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
296 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
297 { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
298 { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */
299 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
300 { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
96fb9f9b
VK		 301 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
302};
303
78ab0bae
VS		 304static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
305 u32 level, enum port port, int type);
f8896f5d 306
a1e6ad66
ID		 307static void ddi_get_encoder_port(struct intel_encoder *intel_encoder,
308 struct intel_digital_port **dig_port,
309 enum port *port)
fc914639 310{
0bdee30e 311 struct drm_encoder *encoder = &intel_encoder->base;
fc914639 312
8cd21b7f
JN		 313 switch (intel_encoder->type) {
314 case INTEL_OUTPUT_DP_MST:
a1e6ad66
ID		 315 *dig_port = enc_to_mst(encoder)->primary;
316 *port = (*dig_port)->port;
8cd21b7f
JN		 317 break;
318 case INTEL_OUTPUT_DISPLAYPORT:
319 case INTEL_OUTPUT_EDP:
320 case INTEL_OUTPUT_HDMI:
321 case INTEL_OUTPUT_UNKNOWN:
a1e6ad66
ID		 322 *dig_port = enc_to_dig_port(encoder);
323 *port = (*dig_port)->port;
8cd21b7f
JN		 324 break;
325 case INTEL_OUTPUT_ANALOG:
a1e6ad66
ID		 326 *dig_port = NULL;
327 *port = PORT_E;
8cd21b7f
JN		 328 break;
329 default:
330 WARN(1, "Invalid DDI encoder type %d\n", intel_encoder->type);
331 break;
fc914639
PZ		 332 }
333}
334
a1e6ad66
ID		 335enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
336{
337 struct intel_digital_port *dig_port;
338 enum port port;
339
340 ddi_get_encoder_port(intel_encoder, &dig_port, &port);
341
342 return port;
343}
344
acee2998 345static const struct ddi_buf_trans *
78ab0bae 346skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 347{
78ab0bae 348 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
5f8b2531 349 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
acee2998 350 return skl_y_ddi_translations_dp;
78ab0bae 351 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) {
f8896f5d 352 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
acee2998 353 return skl_u_ddi_translations_dp;
f8896f5d 354 } else {
f8896f5d 355 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
acee2998 356 return skl_ddi_translations_dp;
f8896f5d 357 }
f8896f5d
DW		 358}
359
acee2998 360static const struct ddi_buf_trans *
78ab0bae 361skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 362{
cd1101cb 363 if (dev_priv->edp_low_vswing) {
78ab0bae 364 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
5f8b2531 365 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
acee2998 366 return skl_y_ddi_translations_edp;
78ab0bae 367 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) {
f8896f5d 368 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
acee2998 369 return skl_u_ddi_translations_edp;
f8896f5d 370 } else {
f8896f5d 371 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
acee2998 372 return skl_ddi_translations_edp;
f8896f5d
DW		 373 }
374 }
cd1101cb 375
78ab0bae 376 return skl_get_buf_trans_dp(dev_priv, n_entries);
f8896f5d
DW		 377}
378
379static const struct ddi_buf_trans *
78ab0bae 380skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 381{
78ab0bae 382 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
5f8b2531 383 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
acee2998 384 return skl_y_ddi_translations_hdmi;
f8896f5d 385 } else {
f8896f5d 386 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
acee2998 387 return skl_ddi_translations_hdmi;
f8896f5d 388 }
f8896f5d
DW		 389}
390
e58623cb
AR		 391/*
392 * Starting with Haswell, DDI port buffers must be programmed with correct
393 * values in advance. The buffer values are different for FDI and DP modes,
45244b87
ED		 394 * but the HDMI/DVI fields are shared among those. So we program the DDI
395 * in either FDI or DP modes only, as HDMI connections will work with both
396 * of those
397 */
6a7e4f99 398void intel_prepare_ddi_buffer(struct intel_encoder *encoder)
45244b87 399{
6a7e4f99 400 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
75067dde 401 u32 iboost_bit = 0;
7ff44670 402 int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry,
7ad14a29 403 size;
6a7e4f99
VS		 404 int hdmi_level;
405 enum port port;
10122051
JN		 406 const struct ddi_buf_trans *ddi_translations_fdi;
407 const struct ddi_buf_trans *ddi_translations_dp;
408 const struct ddi_buf_trans *ddi_translations_edp;
409 const struct ddi_buf_trans *ddi_translations_hdmi;
410 const struct ddi_buf_trans *ddi_translations;
e58623cb 411
6a7e4f99
VS		 412 port = intel_ddi_get_encoder_port(encoder);
413 hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
414
78ab0bae 415 if (IS_BROXTON(dev_priv)) {
6a7e4f99 416 if (encoder->type != INTEL_OUTPUT_HDMI)
96fb9f9b
VK		 417 return;
418
419 /* Vswing programming for HDMI */
78ab0bae 420 bxt_ddi_vswing_sequence(dev_priv, hdmi_level, port,
96fb9f9b
VK		 421 INTEL_OUTPUT_HDMI);
422 return;
6a7e4f99
VS		 423 }
424
425 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
c30400fc 426 ddi_translations_fdi = NULL;
f8896f5d 427 ddi_translations_dp =
78ab0bae 428 skl_get_buf_trans_dp(dev_priv, &n_dp_entries);
f8896f5d 429 ddi_translations_edp =
78ab0bae 430 skl_get_buf_trans_edp(dev_priv, &n_edp_entries);
f8896f5d 431 ddi_translations_hdmi =
78ab0bae 432 skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
f8896f5d 433 hdmi_default_entry = 8;
75067dde
AK		 434 /* If we're boosting the current, set bit 31 of trans1 */
435 if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level ||
436 dev_priv->vbt.ddi_port_info[port].dp_boost_level)
437 iboost_bit = 1<<31;
10afa0b6 438
ceccad59
VS		 439 if (WARN_ON(encoder->type == INTEL_OUTPUT_EDP &&
440 port != PORT_A && port != PORT_E &&
441 n_edp_entries > 9))
10afa0b6 442 n_edp_entries = 9;
78ab0bae 443 } else if (IS_BROADWELL(dev_priv)) {
e58623cb
AR		 444 ddi_translations_fdi = bdw_ddi_translations_fdi;
445 ddi_translations_dp = bdw_ddi_translations_dp;
300644c7 446 ddi_translations_edp = bdw_ddi_translations_edp;
a26aa8ba 447 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
7ad14a29
SJ		 448 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
449 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 450 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
7ff44670 451 hdmi_default_entry = 7;
78ab0bae 452 } else if (IS_HASWELL(dev_priv)) {
e58623cb
AR		 453 ddi_translations_fdi = hsw_ddi_translations_fdi;
454 ddi_translations_dp = hsw_ddi_translations_dp;
300644c7 455 ddi_translations_edp = hsw_ddi_translations_dp;
a26aa8ba 456 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
7ad14a29 457 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
10122051 458 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
7ff44670 459 hdmi_default_entry = 6;
e58623cb
AR		 460 } else {
461 WARN(1, "ddi translation table missing\n");
300644c7 462 ddi_translations_edp = bdw_ddi_translations_dp;
e58623cb
AR		 463 ddi_translations_fdi = bdw_ddi_translations_fdi;
464 ddi_translations_dp = bdw_ddi_translations_dp;
a26aa8ba 465 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
7ad14a29
SJ		 466 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
467 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 468 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
7ff44670 469 hdmi_default_entry = 7;
e58623cb
AR		 470 }
471
6a7e4f99
VS		 472 switch (encoder->type) {
473 case INTEL_OUTPUT_EDP:
300644c7 474 ddi_translations = ddi_translations_edp;
7ad14a29 475 size = n_edp_entries;
300644c7 476 break;
6a7e4f99
VS		 477 case INTEL_OUTPUT_DISPLAYPORT:
478 case INTEL_OUTPUT_HDMI:
300644c7 479 ddi_translations = ddi_translations_dp;
7ad14a29 480 size = n_dp_entries;
300644c7 481 break;
6a7e4f99
VS		 482 case INTEL_OUTPUT_ANALOG:
483 ddi_translations = ddi_translations_fdi;
7ad14a29 484 size = n_dp_entries;
300644c7
PZ		 485 break;
486 default:
487 BUG();
488 }
45244b87 489
9712e688
VS		 490 for (i = 0; i < size; i++) {
491 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
492 ddi_translations[i].trans1 | iboost_bit);
493 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
494 ddi_translations[i].trans2);
45244b87 495 }
ce4dd49e 496
6a7e4f99 497 if (encoder->type != INTEL_OUTPUT_HDMI)
ce3b7e9b
DL		 498 return;
499
ce4dd49e
DL		 500 /* Choose a good default if VBT is badly populated */
501 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
502 hdmi_level >= n_hdmi_entries)
7ff44670 503 hdmi_level = hdmi_default_entry;
ce4dd49e 504
6acab15a 505 /* Entry 9 is for HDMI: */
9712e688
VS		 506 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
507 ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
508 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
509 ddi_translations_hdmi[hdmi_level].trans2);
45244b87
ED		 510}
511
248138b5
PZ		 512static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
513 enum port port)
514{
f0f59a00 515 i915_reg_t reg = DDI_BUF_CTL(port);
248138b5
PZ		 516 int i;
517
3449ca85 518 for (i = 0; i < 16; i++) {
248138b5
PZ		 519 udelay(1);
520 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
521 return;
522 }
523 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
524}
c82e4d26
ED		 525
526/* Starting with Haswell, different DDI ports can work in FDI mode for
527 * connection to the PCH-located connectors. For this, it is necessary to train
528 * both the DDI port and PCH receiver for the desired DDI buffer settings.
529 *
530 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
531 * please note that when FDI mode is active on DDI E, it shares 2 lines with
532 * DDI A (which is used for eDP)
533 */
534
535void hsw_fdi_link_train(struct drm_crtc *crtc)
536{
537 struct drm_device *dev = crtc->dev;
538 struct drm_i915_private *dev_priv = dev->dev_private;
539 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6a7e4f99 540 struct intel_encoder *encoder;
04945641 541 u32 temp, i, rx_ctl_val;
c82e4d26 542
6a7e4f99
VS		 543 for_each_encoder_on_crtc(dev, crtc, encoder) {
544 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
545 intel_prepare_ddi_buffer(encoder);
546 }
547
04945641
PZ		 548 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
549 * mode set "sequence for CRT port" document:
550 * - TP1 to TP2 time with the default value
551 * - FDI delay to 90h
8693a824
DL		 552 *
553 * WaFDIAutoLinkSetTimingOverrride:hsw
04945641 554 */
eede3b53 555 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
04945641
PZ		 556 FDI_RX_PWRDN_LANE0_VAL(2) |
557 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
558
559 /* Enable the PCH Receiver FDI PLL */
3e68320e 560 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
33d29b14 561 FDI_RX_PLL_ENABLE |
6e3c9717 562 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
eede3b53
VS		 563 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
564 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 565 udelay(220);
566
567 /* Switch from Rawclk to PCDclk */
568 rx_ctl_val |= FDI_PCDCLK;
eede3b53 569 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
04945641
PZ		 570
571 /* Configure Port Clock Select */
6e3c9717
ACO		 572 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
573 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
04945641
PZ		 574
575 /* Start the training iterating through available voltages and emphasis,
576 * testing each value twice. */
10122051 577 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
c82e4d26
ED		 578 /* Configure DP_TP_CTL with auto-training */
579 I915_WRITE(DP_TP_CTL(PORT_E),
580 DP_TP_CTL_FDI_AUTOTRAIN |
581 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
582 DP_TP_CTL_LINK_TRAIN_PAT1 |
583 DP_TP_CTL_ENABLE);
584
876a8cdf
DL		 585 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
586 * DDI E does not support port reversal, the functionality is
587 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
588 * port reversal bit */
c82e4d26 589 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641 590 DDI_BUF_CTL_ENABLE |
6e3c9717 591 ((intel_crtc->config->fdi_lanes - 1) << 1) |
c5fe6a06 592 DDI_BUF_TRANS_SELECT(i / 2));
04945641 593 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 594
595 udelay(600);
596
04945641 597 /* Program PCH FDI Receiver TU */
eede3b53 598 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
04945641
PZ		 599
600 /* Enable PCH FDI Receiver with auto-training */
601 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
eede3b53
VS		 602 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
603 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 604
605 /* Wait for FDI receiver lane calibration */
606 udelay(30);
607
608 /* Unset FDI_RX_MISC pwrdn lanes */
eede3b53 609 temp = I915_READ(FDI_RX_MISC(PIPE_A));
04945641 610 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
eede3b53
VS		 611 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
612 POSTING_READ(FDI_RX_MISC(PIPE_A));
04945641
PZ		 613
614 /* Wait for FDI auto training time */
615 udelay(5);
c82e4d26
ED		 616
617 temp = I915_READ(DP_TP_STATUS(PORT_E));
618 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 619 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
a308ccb3
VS		 620 break;
621 }
c82e4d26 622
a308ccb3
VS		 623 /*
624 * Leave things enabled even if we failed to train FDI.
625 * Results in less fireworks from the state checker.
626 */
627 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
628 DRM_ERROR("FDI link training failed!\n");
629 break;
c82e4d26 630 }
04945641 631
248138b5
PZ		 632 temp = I915_READ(DDI_BUF_CTL(PORT_E));
633 temp &= ~DDI_BUF_CTL_ENABLE;
634 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
635 POSTING_READ(DDI_BUF_CTL(PORT_E));
636
04945641 637 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
248138b5
PZ		 638 temp = I915_READ(DP_TP_CTL(PORT_E));
639 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
640 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
641 I915_WRITE(DP_TP_CTL(PORT_E), temp);
642 POSTING_READ(DP_TP_CTL(PORT_E));
643
644 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
04945641
PZ		 645
646 rx_ctl_val &= ~FDI_RX_ENABLE;
eede3b53
VS		 647 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
648 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 649
650 /* Reset FDI_RX_MISC pwrdn lanes */
eede3b53 651 temp = I915_READ(FDI_RX_MISC(PIPE_A));
04945641
PZ		 652 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
653 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
eede3b53
VS		 654 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
655 POSTING_READ(FDI_RX_MISC(PIPE_A));
c82e4d26
ED		 656 }
657
a308ccb3
VS		 658 /* Enable normal pixel sending for FDI */
659 I915_WRITE(DP_TP_CTL(PORT_E),
660 DP_TP_CTL_FDI_AUTOTRAIN |
661 DP_TP_CTL_LINK_TRAIN_NORMAL |
662 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
663 DP_TP_CTL_ENABLE);
c82e4d26 664}
0e72a5b5 665
44905a27
DA		 666void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
667{
668 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
669 struct intel_digital_port *intel_dig_port =
670 enc_to_dig_port(&encoder->base);
671
672 intel_dp->DP = intel_dig_port->saved_port_bits |
c5fe6a06 673 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
901c2daf 674 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
44905a27
DA		 675}
676
8d9ddbcb
PZ		 677static struct intel_encoder *
678intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
679{
680 struct drm_device *dev = crtc->dev;
681 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
682 struct intel_encoder *intel_encoder, *ret = NULL;
683 int num_encoders = 0;
684
685 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
686 ret = intel_encoder;
687 num_encoders++;
688 }
689
690 if (num_encoders != 1)
84f44ce7
VS		 691 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
692 pipe_name(intel_crtc->pipe));
8d9ddbcb
PZ		 693
694 BUG_ON(ret == NULL);
695 return ret;
696}
697
bcddf610 698struct intel_encoder *
3165c074 699intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
d0737e1d 700{
3165c074
ACO		 701 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
702 struct intel_encoder *ret = NULL;
703 struct drm_atomic_state *state;
da3ced29
ACO		 704 struct drm_connector *connector;
705 struct drm_connector_state *connector_state;
d0737e1d 706 int num_encoders = 0;
3165c074 707 int i;
d0737e1d 708
3165c074
ACO		 709 state = crtc_state->base.state;
710
da3ced29
ACO		 711 for_each_connector_in_state(state, connector, connector_state, i) {
712 if (connector_state->crtc != crtc_state->base.crtc)
3165c074
ACO		 713 continue;
714
da3ced29 715 ret = to_intel_encoder(connector_state->best_encoder);
3165c074 716 num_encoders++;
d0737e1d
ACO		 717 }
718
719 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
720 pipe_name(crtc->pipe));
721
722 BUG_ON(ret == NULL);
723 return ret;
724}
725
1c0b85c5 726#define LC_FREQ 2700
27893390 727#define LC_FREQ_2K U64_C(LC_FREQ * 2000)
1c0b85c5
DL		 728
729#define P_MIN 2
730#define P_MAX 64
731#define P_INC 2
732
733/* Constraints for PLL good behavior */
734#define REF_MIN 48
735#define REF_MAX 400
736#define VCO_MIN 2400
737#define VCO_MAX 4800
738
27893390
DL		 739#define abs_diff(a, b) ({ \
740 typeof(a) __a = (a); \
741 typeof(b) __b = (b); \
742 (void) (&__a == &__b); \
743 __a > __b ? (__a - __b) : (__b - __a); })
1c0b85c5 744
63582983 745struct hsw_wrpll_rnp {
1c0b85c5
DL		 746 unsigned p, n2, r2;
747};
748
63582983 749static unsigned hsw_wrpll_get_budget_for_freq(int clock)
6441ab5f 750{
1c0b85c5
DL		 751 unsigned budget;
752
753 switch (clock) {
754 case 25175000:
755 case 25200000:
756 case 27000000:
757 case 27027000:
758 case 37762500:
759 case 37800000:
760 case 40500000:
761 case 40541000:
762 case 54000000:
763 case 54054000:
764 case 59341000:
765 case 59400000:
766 case 72000000:
767 case 74176000:
768 case 74250000:
769 case 81000000:
770 case 81081000:
771 case 89012000:
772 case 89100000:
773 case 108000000:
774 case 108108000:
775 case 111264000:
776 case 111375000:
777 case 148352000:
778 case 148500000:
779 case 162000000:
780 case 162162000:
781 case 222525000:
782 case 222750000:
783 case 296703000:
784 case 297000000:
785 budget = 0;
786 break;
787 case 233500000:
788 case 245250000:
789 case 247750000:
790 case 253250000:
791 case 298000000:
792 budget = 1500;
793 break;
794 case 169128000:
795 case 169500000:
796 case 179500000:
797 case 202000000:
798 budget = 2000;
799 break;
800 case 256250000:
801 case 262500000:
802 case 270000000:
803 case 272500000:
804 case 273750000:
805 case 280750000:
806 case 281250000:
807 case 286000000:
808 case 291750000:
809 budget = 4000;
810 break;
811 case 267250000:
812 case 268500000:
813 budget = 5000;
814 break;
815 default:
816 budget = 1000;
817 break;
818 }
6441ab5f 819
1c0b85c5
DL		 820 return budget;
821}
822
63582983
DL		 823static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget,
824 unsigned r2, unsigned n2, unsigned p,
825 struct hsw_wrpll_rnp *best)
1c0b85c5
DL		 826{
827 uint64_t a, b, c, d, diff, diff_best;
6441ab5f 828
1c0b85c5
DL		 829 /* No best (r,n,p) yet */
830 if (best->p == 0) {
831 best->p = p;
832 best->n2 = n2;
833 best->r2 = r2;
834 return;
835 }
6441ab5f 836
1c0b85c5
DL		 837 /*
838 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
839 * freq2k.
840 *
841 * delta = 1e6 *
842 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
843 * freq2k;
844 *
845 * and we would like delta <= budget.
846 *
847 * If the discrepancy is above the PPM-based budget, always prefer to
848 * improve upon the previous solution. However, if you're within the
849 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
850 */
851 a = freq2k * budget * p * r2;
852 b = freq2k * budget * best->p * best->r2;
27893390
DL		 853 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
854 diff_best = abs_diff(freq2k * best->p * best->r2,
855 LC_FREQ_2K * best->n2);
1c0b85c5
DL		 856 c = 1000000 * diff;
857 d = 1000000 * diff_best;
858
859 if (a < c && b < d) {
860 /* If both are above the budget, pick the closer */
861 if (best->p * best->r2 * diff < p * r2 * diff_best) {
862 best->p = p;
863 best->n2 = n2;
864 best->r2 = r2;
865 }
866 } else if (a >= c && b < d) {
867 /* If A is below the threshold but B is above it? Update. */
868 best->p = p;
869 best->n2 = n2;
870 best->r2 = r2;
871 } else if (a >= c && b >= d) {
872 /* Both are below the limit, so pick the higher n2/(r2*r2) */
873 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
874 best->p = p;
875 best->n2 = n2;
876 best->r2 = r2;
877 }
878 }
879 /* Otherwise a < c && b >= d, do nothing */
880}
881
f0f59a00
VS		 882static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
883 i915_reg_t reg)
11578553
JB		 884{
885 int refclk = LC_FREQ;
886 int n, p, r;
887 u32 wrpll;
888
889 wrpll = I915_READ(reg);
114fe488
DV		 890 switch (wrpll & WRPLL_PLL_REF_MASK) {
891 case WRPLL_PLL_SSC:
892 case WRPLL_PLL_NON_SSC:
11578553
JB		 893 /*
894 * We could calculate spread here, but our checking
895 * code only cares about 5% accuracy, and spread is a max of
896 * 0.5% downspread.
897 */
898 refclk = 135;
899 break;
114fe488 900 case WRPLL_PLL_LCPLL:
11578553
JB		 901 refclk = LC_FREQ;
902 break;
903 default:
904 WARN(1, "bad wrpll refclk\n");
905 return 0;
906 }
907
908 r = wrpll & WRPLL_DIVIDER_REF_MASK;
909 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
910 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
911
20f0ec16
JB		 912 /* Convert to KHz, p & r have a fixed point portion */
913 return (refclk * n * 100) / (p * r);
11578553
JB		 914}
915
540e732c
S		 916static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
917 uint32_t dpll)
918{
f0f59a00 919 i915_reg_t cfgcr1_reg, cfgcr2_reg;
540e732c
S		 920 uint32_t cfgcr1_val, cfgcr2_val;
921 uint32_t p0, p1, p2, dco_freq;
922
923c1241
VS		 923 cfgcr1_reg = DPLL_CFGCR1(dpll);
924 cfgcr2_reg = DPLL_CFGCR2(dpll);
540e732c
S		 925
926 cfgcr1_val = I915_READ(cfgcr1_reg);
927 cfgcr2_val = I915_READ(cfgcr2_reg);
928
929 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
930 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
931
932 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
933 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
934 else
935 p1 = 1;
936
937
938 switch (p0) {
939 case DPLL_CFGCR2_PDIV_1:
940 p0 = 1;
941 break;
942 case DPLL_CFGCR2_PDIV_2:
943 p0 = 2;
944 break;
945 case DPLL_CFGCR2_PDIV_3:
946 p0 = 3;
947 break;
948 case DPLL_CFGCR2_PDIV_7:
949 p0 = 7;
950 break;
951 }
952
953 switch (p2) {
954 case DPLL_CFGCR2_KDIV_5:
955 p2 = 5;
956 break;
957 case DPLL_CFGCR2_KDIV_2:
958 p2 = 2;
959 break;
960 case DPLL_CFGCR2_KDIV_3:
961 p2 = 3;
962 break;
963 case DPLL_CFGCR2_KDIV_1:
964 p2 = 1;
965 break;
966 }
967
968 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
969
970 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
971 1000) / 0x8000;
972
973 return dco_freq / (p0 * p1 * p2 * 5);
974}
975
398a017e
VS		 976static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
977{
978 int dotclock;
979
980 if (pipe_config->has_pch_encoder)
981 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
982 &pipe_config->fdi_m_n);
983 else if (pipe_config->has_dp_encoder)
984 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
985 &pipe_config->dp_m_n);
986 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
987 dotclock = pipe_config->port_clock * 2 / 3;
988 else
989 dotclock = pipe_config->port_clock;
990
991 if (pipe_config->pixel_multiplier)
992 dotclock /= pipe_config->pixel_multiplier;
993
994 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
995}
540e732c
S		 996
997static void skl_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 998 struct intel_crtc_state *pipe_config)
540e732c
S		 999{
1000 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
540e732c
S		 1001 int link_clock = 0;
1002 uint32_t dpll_ctl1, dpll;
1003
134ffa44 1004 dpll = pipe_config->ddi_pll_sel;
540e732c
S		 1005
1006 dpll_ctl1 = I915_READ(DPLL_CTRL1);
1007
1008 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
1009 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
1010 } else {
71cd8423
DL		 1011 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
1012 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
540e732c
S		 1013
1014 switch (link_clock) {
71cd8423 1015 case DPLL_CTRL1_LINK_RATE_810:
540e732c
S		 1016 link_clock = 81000;
1017 break;
71cd8423 1018 case DPLL_CTRL1_LINK_RATE_1080:
a8f3ef61
SJ		 1019 link_clock = 108000;
1020 break;
71cd8423 1021 case DPLL_CTRL1_LINK_RATE_1350:
540e732c
S		 1022 link_clock = 135000;
1023 break;
71cd8423 1024 case DPLL_CTRL1_LINK_RATE_1620:
a8f3ef61
SJ		 1025 link_clock = 162000;
1026 break;
71cd8423 1027 case DPLL_CTRL1_LINK_RATE_2160:
a8f3ef61
SJ		 1028 link_clock = 216000;
1029 break;
71cd8423 1030 case DPLL_CTRL1_LINK_RATE_2700:
540e732c
S		 1031 link_clock = 270000;
1032 break;
1033 default:
1034 WARN(1, "Unsupported link rate\n");
1035 break;
1036 }
1037 link_clock *= 2;
1038 }
1039
1040 pipe_config->port_clock = link_clock;
1041
398a017e 1042 ddi_dotclock_get(pipe_config);
540e732c
S		 1043}
1044
3d51278a 1045static void hsw_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1046 struct intel_crtc_state *pipe_config)
11578553
JB		 1047{
1048 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
11578553
JB		 1049 int link_clock = 0;
1050 u32 val, pll;
1051
26804afd 1052 val = pipe_config->ddi_pll_sel;
11578553
JB		 1053 switch (val & PORT_CLK_SEL_MASK) {
1054 case PORT_CLK_SEL_LCPLL_810:
1055 link_clock = 81000;
1056 break;
1057 case PORT_CLK_SEL_LCPLL_1350:
1058 link_clock = 135000;
1059 break;
1060 case PORT_CLK_SEL_LCPLL_2700:
1061 link_clock = 270000;
1062 break;
1063 case PORT_CLK_SEL_WRPLL1:
01403de3 1064 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
11578553
JB		 1065 break;
1066 case PORT_CLK_SEL_WRPLL2:
01403de3 1067 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
11578553
JB		 1068 break;
1069 case PORT_CLK_SEL_SPLL:
1070 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1071 if (pll == SPLL_PLL_FREQ_810MHz)
1072 link_clock = 81000;
1073 else if (pll == SPLL_PLL_FREQ_1350MHz)
1074 link_clock = 135000;
1075 else if (pll == SPLL_PLL_FREQ_2700MHz)
1076 link_clock = 270000;
1077 else {
1078 WARN(1, "bad spll freq\n");
1079 return;
1080 }
1081 break;
1082 default:
1083 WARN(1, "bad port clock sel\n");
1084 return;
1085 }
1086
1087 pipe_config->port_clock = link_clock * 2;
1088
398a017e 1089 ddi_dotclock_get(pipe_config);
11578553
JB		 1090}
1091
977bb38d
S		 1092static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
1093 enum intel_dpll_id dpll)
1094{
aa610dcb
ID		 1095 struct intel_shared_dpll *pll;
1096 struct intel_dpll_hw_state *state;
1097 intel_clock_t clock;
1098
1099 /* For DDI ports we always use a shared PLL. */
1100 if (WARN_ON(dpll == DPLL_ID_PRIVATE))
1101 return 0;
1102
1103 pll = &dev_priv->shared_dplls[dpll];
1104 state = &pll->config.hw_state;
1105
1106 clock.m1 = 2;
1107 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1108 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1109 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1110 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1111 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1112 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1113
1114 return chv_calc_dpll_params(100000, &clock);
977bb38d
S		 1115}
1116
1117static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1118 struct intel_crtc_state *pipe_config)
1119{
1120 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1121 enum port port = intel_ddi_get_encoder_port(encoder);
1122 uint32_t dpll = port;
1123
398a017e 1124 pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);
977bb38d 1125
398a017e 1126 ddi_dotclock_get(pipe_config);
977bb38d
S		 1127}
1128
3d51278a 1129void intel_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1130 struct intel_crtc_state *pipe_config)
3d51278a 1131{
22606a18
DL		 1132 struct drm_device *dev = encoder->base.dev;
1133
1134 if (INTEL_INFO(dev)->gen <= 8)
1135 hsw_ddi_clock_get(encoder, pipe_config);
ef11bdb3 1136 else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
22606a18 1137 skl_ddi_clock_get(encoder, pipe_config);
977bb38d
S		 1138 else if (IS_BROXTON(dev))
1139 bxt_ddi_clock_get(encoder, pipe_config);
3d51278a
DV		 1140}
1141
1c0b85c5 1142static void
d664c0ce
DL		 1143hsw_ddi_calculate_wrpll(int clock /* in Hz */,
1144 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
1c0b85c5
DL		 1145{
1146 uint64_t freq2k;
1147 unsigned p, n2, r2;
63582983 1148 struct hsw_wrpll_rnp best = { 0, 0, 0 };
1c0b85c5
DL		 1149 unsigned budget;
1150
1151 freq2k = clock / 100;
1152
63582983 1153 budget = hsw_wrpll_get_budget_for_freq(clock);
1c0b85c5
DL		 1154
1155 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
1156 * and directly pass the LC PLL to it. */
1157 if (freq2k == 5400000) {
1158 *n2_out = 2;
1159 *p_out = 1;
1160 *r2_out = 2;
1161 return;
1162 }
1163
1164 /*
1165 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
1166 * the WR PLL.
1167 *
1168 * We want R so that REF_MIN <= Ref <= REF_MAX.
1169 * Injecting R2 = 2 * R gives:
1170 * REF_MAX * r2 > LC_FREQ * 2 and
1171 * REF_MIN * r2 < LC_FREQ * 2
1172 *
1173 * Which means the desired boundaries for r2 are:
1174 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
1175 *
1176 */
1177 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
1178 r2 <= LC_FREQ * 2 / REF_MIN;
1179 r2++) {
1180
1181 /*
1182 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
1183 *
1184 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
1185 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
1186 * VCO_MAX * r2 > n2 * LC_FREQ and
1187 * VCO_MIN * r2 < n2 * LC_FREQ)
1188 *
1189 * Which means the desired boundaries for n2 are:
1190 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
1191 */
1192 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
1193 n2 <= VCO_MAX * r2 / LC_FREQ;
1194 n2++) {
1195
1196 for (p = P_MIN; p <= P_MAX; p += P_INC)
63582983
DL		 1197 hsw_wrpll_update_rnp(freq2k, budget,
1198 r2, n2, p, &best);
1c0b85c5
DL		 1199 }
1200 }
6441ab5f 1201
1c0b85c5
DL		 1202 *n2_out = best.n2;
1203 *p_out = best.p;
1204 *r2_out = best.r2;
6441ab5f
PZ		 1205}
1206
0220ab6e 1207static bool
d664c0ce 1208hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 1209 struct intel_crtc_state *crtc_state,
96f3f1f9 1210 struct intel_encoder *intel_encoder)
6441ab5f 1211{
8106ddbd 1212 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
96f3f1f9
VS		 1213 int clock = crtc_state->port_clock;
1214
d664c0ce 1215 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
e0b01be4 1216 struct intel_shared_dpll *pll;
716c2e55 1217 uint32_t val;
1c0b85c5 1218 unsigned p, n2, r2;
6441ab5f 1219
d664c0ce 1220 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
0694001b 1221
114fe488 1222 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
0694001b
PZ		 1223 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
1224 WRPLL_DIVIDER_POST(p);
1225
dd3cd74a
ACO		 1226 memset(&crtc_state->dpll_hw_state, 0,
1227 sizeof(crtc_state->dpll_hw_state));
1228
190f68c5 1229 crtc_state->dpll_hw_state.wrpll = val;
6441ab5f 1230
190f68c5 1231 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
716c2e55
DV		 1232 if (pll == NULL) {
1233 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1234 pipe_name(intel_crtc->pipe));
1235 return false;
0694001b 1236 }
d452c5b6 1237
190f68c5 1238 crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
00490c22
ML		 1239 } else if (crtc_state->ddi_pll_sel == PORT_CLK_SEL_SPLL) {
1240 struct drm_atomic_state *state = crtc_state->base.state;
1241 struct intel_shared_dpll_config *spll =
1242 &intel_atomic_get_shared_dpll_state(state)[DPLL_ID_SPLL];
1243
1244 if (spll->crtc_mask &&
1245 WARN_ON(spll->hw_state.spll != crtc_state->dpll_hw_state.spll))
1246 return false;
1247
8106ddbd
ACO		 1248 crtc_state->shared_dpll =
1249 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_SPLL);
00490c22
ML		 1250 spll->hw_state.spll = crtc_state->dpll_hw_state.spll;
1251 spll->crtc_mask |= 1 << intel_crtc->pipe;
6441ab5f
PZ		 1252 }
1253
6441ab5f
PZ		 1254 return true;
1255}
1256
dc253813
DL		 1257struct skl_wrpll_context {
1258 uint64_t min_deviation; /* current minimal deviation */
1259 uint64_t central_freq; /* chosen central freq */
1260 uint64_t dco_freq; /* chosen dco freq */
1261 unsigned int p; /* chosen divider */
1262};
1263
1264static void skl_wrpll_context_init(struct skl_wrpll_context *ctx)
1265{
1266 memset(ctx, 0, sizeof(*ctx));
1267
1268 ctx->min_deviation = U64_MAX;
1269}
1270
1271/* DCO freq must be within +1%/-6% of the DCO central freq */
1272#define SKL_DCO_MAX_PDEVIATION 100
1273#define SKL_DCO_MAX_NDEVIATION 600
1274
1275static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx,
1276 uint64_t central_freq,
1277 uint64_t dco_freq,
1278 unsigned int divider)
1279{
1280 uint64_t deviation;
1281
1282 deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq),
1283 central_freq);
1284
1285 /* positive deviation */
1286 if (dco_freq >= central_freq) {
1287 if (deviation < SKL_DCO_MAX_PDEVIATION &&
1288 deviation < ctx->min_deviation) {
1289 ctx->min_deviation = deviation;
1290 ctx->central_freq = central_freq;
1291 ctx->dco_freq = dco_freq;
1292 ctx->p = divider;
1293 }
1294 /* negative deviation */
1295 } else if (deviation < SKL_DCO_MAX_NDEVIATION &&
1296 deviation < ctx->min_deviation) {
1297 ctx->min_deviation = deviation;
1298 ctx->central_freq = central_freq;
1299 ctx->dco_freq = dco_freq;
1300 ctx->p = divider;
1301 }
dc253813
DL		 1302}
1303
1304static void skl_wrpll_get_multipliers(unsigned int p,
1305 unsigned int *p0 /* out */,
1306 unsigned int *p1 /* out */,
1307 unsigned int *p2 /* out */)
1308{
1309 /* even dividers */
1310 if (p % 2 == 0) {
1311 unsigned int half = p / 2;
1312
1313 if (half == 1 || half == 2 || half == 3 || half == 5) {
1314 *p0 = 2;
1315 *p1 = 1;
1316 *p2 = half;
1317 } else if (half % 2 == 0) {
1318 *p0 = 2;
1319 *p1 = half / 2;
1320 *p2 = 2;
1321 } else if (half % 3 == 0) {
1322 *p0 = 3;
1323 *p1 = half / 3;
1324 *p2 = 2;
1325 } else if (half % 7 == 0) {
1326 *p0 = 7;
1327 *p1 = half / 7;
1328 *p2 = 2;
1329 }
1330 } else if (p == 3 || p == 9) { /* 3, 5, 7, 9, 15, 21, 35 */
1331 *p0 = 3;
1332 *p1 = 1;
1333 *p2 = p / 3;
1334 } else if (p == 5 || p == 7) {
1335 *p0 = p;
1336 *p1 = 1;
1337 *p2 = 1;
1338 } else if (p == 15) {
1339 *p0 = 3;
1340 *p1 = 1;
1341 *p2 = 5;
1342 } else if (p == 21) {
1343 *p0 = 7;
1344 *p1 = 1;
1345 *p2 = 3;
1346 } else if (p == 35) {
1347 *p0 = 7;
1348 *p1 = 1;
1349 *p2 = 5;
1350 }
1351}
1352
82d35437
S		 1353struct skl_wrpll_params {
1354 uint32_t dco_fraction;
1355 uint32_t dco_integer;
1356 uint32_t qdiv_ratio;
1357 uint32_t qdiv_mode;
1358 uint32_t kdiv;
1359 uint32_t pdiv;
1360 uint32_t central_freq;
1361};
1362
76516fbc
DL		 1363static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
1364 uint64_t afe_clock,
1365 uint64_t central_freq,
1366 uint32_t p0, uint32_t p1, uint32_t p2)
1367{
1368 uint64_t dco_freq;
1369
76516fbc
DL		 1370 switch (central_freq) {
1371 case 9600000000ULL:
1372 params->central_freq = 0;
1373 break;
1374 case 9000000000ULL:
1375 params->central_freq = 1;
1376 break;
1377 case 8400000000ULL:
1378 params->central_freq = 3;
1379 }
1380
1381 switch (p0) {
1382 case 1:
1383 params->pdiv = 0;
1384 break;
1385 case 2:
1386 params->pdiv = 1;
1387 break;
1388 case 3:
1389 params->pdiv = 2;
1390 break;
1391 case 7:
1392 params->pdiv = 4;
1393 break;
1394 default:
1395 WARN(1, "Incorrect PDiv\n");
1396 }
1397
1398 switch (p2) {
1399 case 5:
1400 params->kdiv = 0;
1401 break;
1402 case 2:
1403 params->kdiv = 1;
1404 break;
1405 case 3:
1406 params->kdiv = 2;
1407 break;
1408 case 1:
1409 params->kdiv = 3;
1410 break;
1411 default:
1412 WARN(1, "Incorrect KDiv\n");
1413 }
1414
1415 params->qdiv_ratio = p1;
1416 params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1;
1417
1418 dco_freq = p0 * p1 * p2 * afe_clock;
1419
1420 /*
1421 * Intermediate values are in Hz.
1422 * Divide by MHz to match bsepc
1423 */
30a7862d 1424 params->dco_integer = div_u64(dco_freq, 24 * MHz(1));
76516fbc 1425 params->dco_fraction =
30a7862d
DL		 1426 div_u64((div_u64(dco_freq, 24) -
1427 params->dco_integer * MHz(1)) * 0x8000, MHz(1));
76516fbc
DL		 1428}
1429
318bd821 1430static bool
82d35437
S		 1431skl_ddi_calculate_wrpll(int clock /* in Hz */,
1432 struct skl_wrpll_params *wrpll_params)
1433{
1434 uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
21318cce
DL		 1435 uint64_t dco_central_freq[3] = {8400000000ULL,
1436 9000000000ULL,
1437 9600000000ULL};
dc253813
DL		 1438 static const int even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20,
1439 24, 28, 30, 32, 36, 40, 42, 44,
1440 48, 52, 54, 56, 60, 64, 66, 68,
1441 70, 72, 76, 78, 80, 84, 88, 90,
1442 92, 96, 98 };
1443 static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 };
1444 static const struct {
1445 const int *list;
1446 int n_dividers;
1447 } dividers[] = {
1448 { even_dividers, ARRAY_SIZE(even_dividers) },
1449 { odd_dividers, ARRAY_SIZE(odd_dividers) },
1450 };
1451 struct skl_wrpll_context ctx;
1452 unsigned int dco, d, i;
1453 unsigned int p0, p1, p2;
1454
1455 skl_wrpll_context_init(&ctx);
1456
1457 for (d = 0; d < ARRAY_SIZE(dividers); d++) {
1458 for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
1459 for (i = 0; i < dividers[d].n_dividers; i++) {
1460 unsigned int p = dividers[d].list[i];
1461 uint64_t dco_freq = p * afe_clock;
1462
1463 skl_wrpll_try_divider(&ctx,
1464 dco_central_freq[dco],
1465 dco_freq,
1466 p);
e7ad9878
DL		 1467 /*
1468 * Skip the remaining dividers if we're sure to
1469 * have found the definitive divider, we can't
1470 * improve a 0 deviation.
1471 */
1472 if (ctx.min_deviation == 0)
1473 goto skip_remaining_dividers;
82d35437
S		 1474 }
1475 }
267db663 1476
e7ad9878 1477skip_remaining_dividers:
267db663
DL		 1478 /*
1479 * If a solution is found with an even divider, prefer
1480 * this one.
1481 */
1482 if (d == 0 && ctx.p)
1483 break;
82d35437
S		 1484 }
1485
dc253813
DL		 1486 if (!ctx.p) {
1487 DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock);
318bd821 1488 return false;
dc253813 1489 }
82d35437 1490
dc253813
DL		 1491 /*
1492 * gcc incorrectly analyses that these can be used without being
1493 * initialized. To be fair, it's hard to guess.
1494 */
1495 p0 = p1 = p2 = 0;
1496 skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2);
1497 skl_wrpll_params_populate(wrpll_params, afe_clock, ctx.central_freq,
1498 p0, p1, p2);
318bd821
DL		 1499
1500 return true;
82d35437
S		 1501}
1502
82d35437
S		 1503static bool
1504skl_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 1505 struct intel_crtc_state *crtc_state,
96f3f1f9 1506 struct intel_encoder *intel_encoder)
82d35437
S		 1507{
1508 struct intel_shared_dpll *pll;
1509 uint32_t ctrl1, cfgcr1, cfgcr2;
96f3f1f9 1510 int clock = crtc_state->port_clock;
82d35437
S		 1511
1512 /*
1513 * See comment in intel_dpll_hw_state to understand why we always use 0
1514 * as the DPLL id in this function.
1515 */
1516
1517 ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1518
1519 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1520 struct skl_wrpll_params wrpll_params = { 0, };
1521
1522 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1523
318bd821
DL		 1524 if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params))
1525 return false;
82d35437
S		 1526
1527 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
1528 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1529 wrpll_params.dco_integer;
1530
1531 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1532 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1533 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1534 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1535 wrpll_params.central_freq;
78385cb3
L		 1536 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
1537 intel_encoder->type == INTEL_OUTPUT_DP_MST) {
840b32b7
VS		 1538 switch (crtc_state->port_clock / 2) {
1539 case 81000:
71cd8423 1540 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
82d35437 1541 break;
840b32b7 1542 case 135000:
71cd8423 1543 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
82d35437 1544 break;
840b32b7 1545 case 270000:
71cd8423 1546 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
82d35437
S		 1547 break;
1548 }
1549
1550 cfgcr1 = cfgcr2 = 0;
5a01d5b6 1551 } else if (intel_encoder->type == INTEL_OUTPUT_EDP) {
82d35437 1552 return true;
5a01d5b6
L		 1553 } else
1554 return false;
82d35437 1555
dd3cd74a
ACO		 1556 memset(&crtc_state->dpll_hw_state, 0,
1557 sizeof(crtc_state->dpll_hw_state));
1558
190f68c5
ACO		 1559 crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1560 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
1561 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
82d35437 1562
190f68c5 1563 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
82d35437
S		 1564 if (pll == NULL) {
1565 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1566 pipe_name(intel_crtc->pipe));
1567 return false;
1568 }
1569
1570 /* shared DPLL id 0 is DPLL 1 */
190f68c5 1571 crtc_state->ddi_pll_sel = pll->id + 1;
82d35437
S		 1572
1573 return true;
1574}
0220ab6e 1575
d683f3bc
S		 1576/* bxt clock parameters */
1577struct bxt_clk_div {
64987fc5 1578 int clock;
d683f3bc
S		 1579 uint32_t p1;
1580 uint32_t p2;
1581 uint32_t m2_int;
1582 uint32_t m2_frac;
1583 bool m2_frac_en;
1584 uint32_t n;
d683f3bc
S		 1585};
1586
1587/* pre-calculated values for DP linkrates */
64987fc5
SJ		 1588static const struct bxt_clk_div bxt_dp_clk_val[] = {
1589 {162000, 4, 2, 32, 1677722, 1, 1},
1590 {270000, 4, 1, 27, 0, 0, 1},
1591 {540000, 2, 1, 27, 0, 0, 1},
1592 {216000, 3, 2, 32, 1677722, 1, 1},
1593 {243000, 4, 1, 24, 1258291, 1, 1},
1594 {324000, 4, 1, 32, 1677722, 1, 1},
1595 {432000, 3, 1, 32, 1677722, 1, 1}
d683f3bc
S		 1596};
1597
1598static bool
1599bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
1600 struct intel_crtc_state *crtc_state,
96f3f1f9 1601 struct intel_encoder *intel_encoder)
d683f3bc
S		 1602{
1603 struct intel_shared_dpll *pll;
1604 struct bxt_clk_div clk_div = {0};
b6dc71f3
VK		 1605 int vco = 0;
1606 uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
e6292556 1607 uint32_t lanestagger;
96f3f1f9 1608 int clock = crtc_state->port_clock;
d683f3bc
S		 1609
1610 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1611 intel_clock_t best_clock;
1612
1613 /* Calculate HDMI div */
1614 /*
1615 * FIXME: tie the following calculation into
1616 * i9xx_crtc_compute_clock
1617 */
1618 if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) {
1619 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
1620 clock, pipe_name(intel_crtc->pipe));
1621 return false;
1622 }
1623
1624 clk_div.p1 = best_clock.p1;
1625 clk_div.p2 = best_clock.p2;
1626 WARN_ON(best_clock.m1 != 2);
1627 clk_div.n = best_clock.n;
1628 clk_div.m2_int = best_clock.m2 >> 22;
1629 clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
1630 clk_div.m2_frac_en = clk_div.m2_frac != 0;
1631
b6dc71f3 1632 vco = best_clock.vco;
d683f3bc
S		 1633 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
1634 intel_encoder->type == INTEL_OUTPUT_EDP) {
64987fc5 1635 int i;
d683f3bc 1636
64987fc5
SJ		 1637 clk_div = bxt_dp_clk_val[0];
1638 for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
1639 if (bxt_dp_clk_val[i].clock == clock) {
1640 clk_div = bxt_dp_clk_val[i];
1641 break;
1642 }
d683f3bc 1643 }
b6dc71f3
VK		 1644 vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
1645 }
1646
e6292556 1647 if (vco >= 6200000 && vco <= 6700000) {
b6dc71f3
VK		 1648 prop_coef = 4;
1649 int_coef = 9;
1650 gain_ctl = 3;
1651 targ_cnt = 8;
1652 } else if ((vco > 5400000 && vco < 6200000) ||
1653 (vco >= 4800000 && vco < 5400000)) {
1654 prop_coef = 5;
1655 int_coef = 11;
1656 gain_ctl = 3;
1657 targ_cnt = 9;
b6dc71f3
VK		 1658 } else if (vco == 5400000) {
1659 prop_coef = 3;
1660 int_coef = 8;
1661 gain_ctl = 1;
1662 targ_cnt = 9;
1663 } else {
1664 DRM_ERROR("Invalid VCO\n");
1665 return false;
d683f3bc
S		 1666 }
1667
dd3cd74a
ACO		 1668 memset(&crtc_state->dpll_hw_state, 0,
1669 sizeof(crtc_state->dpll_hw_state));
1670
e0681e38
VK		 1671 if (clock > 270000)
1672 lanestagger = 0x18;
1673 else if (clock > 135000)
1674 lanestagger = 0x0d;
1675 else if (clock > 67000)
1676 lanestagger = 0x07;
1677 else if (clock > 33000)
1678 lanestagger = 0x04;
1679 else
1680 lanestagger = 0x02;
1681
d683f3bc
S		 1682 crtc_state->dpll_hw_state.ebb0 =
1683 PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
1684 crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
1685 crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n);
1686 crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac;
1687
1688 if (clk_div.m2_frac_en)
1689 crtc_state->dpll_hw_state.pll3 =
1690 PORT_PLL_M2_FRAC_ENABLE;
1691
1692 crtc_state->dpll_hw_state.pll6 =
b6dc71f3 1693 prop_coef | PORT_PLL_INT_COEFF(int_coef);
d683f3bc 1694 crtc_state->dpll_hw_state.pll6 |=
b6dc71f3
VK		 1695 PORT_PLL_GAIN_CTL(gain_ctl);
1696
1697 crtc_state->dpll_hw_state.pll8 = targ_cnt;
d683f3bc 1698
05712c15
ID		 1699 crtc_state->dpll_hw_state.pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT;
1700
e6292556
VK		 1701 crtc_state->dpll_hw_state.pll10 =
1702 PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT)
1703 | PORT_PLL_DCO_AMP_OVR_EN_H;
d683f3bc 1704
05712c15
ID		 1705 crtc_state->dpll_hw_state.ebb4 = PORT_PLL_10BIT_CLK_ENABLE;
1706
d683f3bc 1707 crtc_state->dpll_hw_state.pcsdw12 =
e0681e38 1708 LANESTAGGER_STRAP_OVRD | lanestagger;
d683f3bc
S		 1709
1710 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1711 if (pll == NULL) {
1712 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1713 pipe_name(intel_crtc->pipe));
1714 return false;
1715 }
1716
1717 /* shared DPLL id 0 is DPLL A */
1718 crtc_state->ddi_pll_sel = pll->id;
1719
1720 return true;
1721}
1722
0220ab6e
DL		 1723/*
1724 * Tries to find a *shared* PLL for the CRTC and store it in
1725 * intel_crtc->ddi_pll_sel.
1726 *
1727 * For private DPLLs, compute_config() should do the selection for us. This
1728 * function should be folded into compute_config() eventually.
1729 */
190f68c5
ACO		 1730bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
1731 struct intel_crtc_state *crtc_state)
0220ab6e 1732{
82d35437 1733 struct drm_device *dev = intel_crtc->base.dev;
d0737e1d 1734 struct intel_encoder *intel_encoder =
3165c074 1735 intel_ddi_get_crtc_new_encoder(crtc_state);
0220ab6e 1736
ef11bdb3 1737 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
190f68c5 1738 return skl_ddi_pll_select(intel_crtc, crtc_state,
96f3f1f9 1739 intel_encoder);
d683f3bc
S		 1740 else if (IS_BROXTON(dev))
1741 return bxt_ddi_pll_select(intel_crtc, crtc_state,
96f3f1f9 1742 intel_encoder);
82d35437 1743 else
190f68c5 1744 return hsw_ddi_pll_select(intel_crtc, crtc_state,
96f3f1f9 1745 intel_encoder);
0220ab6e
DL		 1746}
1747
dae84799
PZ		 1748void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1749{
1750 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1751 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1752 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
6e3c9717 1753 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
dae84799
PZ		 1754 int type = intel_encoder->type;
1755 uint32_t temp;
1756
0e32b39c 1757 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
c9809791 1758 temp = TRANS_MSA_SYNC_CLK;
6e3c9717 1759 switch (intel_crtc->config->pipe_bpp) {
dae84799 1760 case 18:
c9809791 1761 temp |= TRANS_MSA_6_BPC;
dae84799
PZ		 1762 break;
1763 case 24:
c9809791 1764 temp |= TRANS_MSA_8_BPC;
dae84799
PZ		 1765 break;
1766 case 30:
c9809791 1767 temp |= TRANS_MSA_10_BPC;
dae84799
PZ		 1768 break;
1769 case 36:
c9809791 1770 temp |= TRANS_MSA_12_BPC;
dae84799
PZ		 1771 break;
1772 default:
4e53c2e0 1773 BUG();
dae84799 1774 }
c9809791 1775 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 1776 }
1777}
1778
0e32b39c
DA		 1779void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1780{
1781 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1782 struct drm_device *dev = crtc->dev;
1783 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1784 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
0e32b39c
DA		 1785 uint32_t temp;
1786 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1787 if (state == true)
1788 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1789 else
1790 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1791 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1792}
1793
8228c251 1794void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
8d9ddbcb
PZ		 1795{
1796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1797 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
7739c33b 1798 struct drm_encoder *encoder = &intel_encoder->base;
c7670b10
PZ		 1799 struct drm_device *dev = crtc->dev;
1800 struct drm_i915_private *dev_priv = dev->dev_private;
8d9ddbcb 1801 enum pipe pipe = intel_crtc->pipe;
6e3c9717 1802 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
174edf1f 1803 enum port port = intel_ddi_get_encoder_port(intel_encoder);
7739c33b 1804 int type = intel_encoder->type;
8d9ddbcb
PZ		 1805 uint32_t temp;
1806
ad80a810
PZ		 1807 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1808 temp = TRANS_DDI_FUNC_ENABLE;
174edf1f 1809 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252 1810
6e3c9717 1811 switch (intel_crtc->config->pipe_bpp) {
dfcef252 1812 case 18:
ad80a810 1813 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 1814 break;
1815 case 24:
ad80a810 1816 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 1817 break;
1818 case 30:
ad80a810 1819 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 1820 break;
1821 case 36:
ad80a810 1822 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 1823 break;
1824 default:
4e53c2e0 1825 BUG();
dfcef252 1826 }
72662e10 1827
6e3c9717 1828 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 1829 temp |= TRANS_DDI_PVSYNC;
6e3c9717 1830 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 1831 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 1832
e6f0bfc4
PZ		 1833 if (cpu_transcoder == TRANSCODER_EDP) {
1834 switch (pipe) {
1835 case PIPE_A:
c7670b10
PZ		 1836 /* On Haswell, can only use the always-on power well for
1837 * eDP when not using the panel fitter, and when not
1838 * using motion blur mitigation (which we don't
1839 * support). */
fabf6e51 1840 if (IS_HASWELL(dev) &&
6e3c9717
ACO		 1841 (intel_crtc->config->pch_pfit.enabled ||
1842 intel_crtc->config->pch_pfit.force_thru))
d6dd9eb1
DV		 1843 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1844 else
1845 temp |= TRANS_DDI_EDP_INPUT_A_ON;
e6f0bfc4
PZ		 1846 break;
1847 case PIPE_B:
1848 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1849 break;
1850 case PIPE_C:
1851 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1852 break;
1853 default:
1854 BUG();
1855 break;
1856 }
1857 }
1858
7739c33b 1859 if (type == INTEL_OUTPUT_HDMI) {
6e3c9717 1860 if (intel_crtc->config->has_hdmi_sink)
ad80a810 1861 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 1862 else
ad80a810 1863 temp |= TRANS_DDI_MODE_SELECT_DVI;
8d9ddbcb 1864
7739c33b 1865 } else if (type == INTEL_OUTPUT_ANALOG) {
ad80a810 1866 temp |= TRANS_DDI_MODE_SELECT_FDI;
6e3c9717 1867 temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
7739c33b
PZ		 1868
1869 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1870 type == INTEL_OUTPUT_EDP) {
1871 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1872
0e32b39c
DA		 1873 if (intel_dp->is_mst) {
1874 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1875 } else
1876 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1877
90a6b7b0 1878 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
0e32b39c
DA		 1879 } else if (type == INTEL_OUTPUT_DP_MST) {
1880 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
1881
1882 if (intel_dp->is_mst) {
1883 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1884 } else
1885 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
7739c33b 1886
90a6b7b0 1887 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
8d9ddbcb 1888 } else {
84f44ce7
VS		 1889 WARN(1, "Invalid encoder type %d for pipe %c\n",
1890 intel_encoder->type, pipe_name(pipe));
8d9ddbcb
PZ		 1891 }
1892
ad80a810 1893 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 1894}
72662e10 1895
ad80a810
PZ		 1896void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1897 enum transcoder cpu_transcoder)
8d9ddbcb 1898{
f0f59a00 1899 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
8d9ddbcb
PZ		 1900 uint32_t val = I915_READ(reg);
1901
0e32b39c 1902 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
ad80a810 1903 val |= TRANS_DDI_PORT_NONE;
8d9ddbcb 1904 I915_WRITE(reg, val);
72662e10
ED		 1905}
1906
bcbc889b
PZ		 1907bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1908{
1909 struct drm_device *dev = intel_connector->base.dev;
1910 struct drm_i915_private *dev_priv = dev->dev_private;
1911 struct intel_encoder *intel_encoder = intel_connector->encoder;
1912 int type = intel_connector->base.connector_type;
1913 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1914 enum pipe pipe = 0;
1915 enum transcoder cpu_transcoder;
882244a3 1916 enum intel_display_power_domain power_domain;
bcbc889b 1917 uint32_t tmp;
e27daab4 1918 bool ret;
bcbc889b 1919
882244a3 1920 power_domain = intel_display_port_power_domain(intel_encoder);
e27daab4 1921 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
882244a3
PZ		 1922 return false;
1923
e27daab4
ID		 1924 if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) {
1925 ret = false;
1926 goto out;
1927 }
bcbc889b
PZ		 1928
1929 if (port == PORT_A)
1930 cpu_transcoder = TRANSCODER_EDP;
1931 else
1a240d4d 1932 cpu_transcoder = (enum transcoder) pipe;
bcbc889b
PZ		 1933
1934 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1935
1936 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1937 case TRANS_DDI_MODE_SELECT_HDMI:
1938 case TRANS_DDI_MODE_SELECT_DVI:
e27daab4
ID		 1939 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1940 break;
bcbc889b
PZ		 1941
1942 case TRANS_DDI_MODE_SELECT_DP_SST:
e27daab4
ID		 1943 ret = type == DRM_MODE_CONNECTOR_eDP ||
1944 type == DRM_MODE_CONNECTOR_DisplayPort;
1945 break;
1946
0e32b39c
DA		 1947 case TRANS_DDI_MODE_SELECT_DP_MST:
1948 /* if the transcoder is in MST state then
1949 * connector isn't connected */
e27daab4
ID		 1950 ret = false;
1951 break;
bcbc889b
PZ		 1952
1953 case TRANS_DDI_MODE_SELECT_FDI:
e27daab4
ID		 1954 ret = type == DRM_MODE_CONNECTOR_VGA;
1955 break;
bcbc889b
PZ		 1956
1957 default:
e27daab4
ID		 1958 ret = false;
1959 break;
bcbc889b 1960 }
e27daab4
ID		 1961
1962out:
1963 intel_display_power_put(dev_priv, power_domain);
1964
1965 return ret;
bcbc889b
PZ		 1966}
1967
85234cdc
DV		 1968bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1969 enum pipe *pipe)
1970{
1971 struct drm_device *dev = encoder->base.dev;
1972 struct drm_i915_private *dev_priv = dev->dev_private;
fe43d3f5 1973 enum port port = intel_ddi_get_encoder_port(encoder);
6d129bea 1974 enum intel_display_power_domain power_domain;
85234cdc
DV		 1975 u32 tmp;
1976 int i;
e27daab4 1977 bool ret;
85234cdc 1978
6d129bea 1979 power_domain = intel_display_port_power_domain(encoder);
e27daab4 1980 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
6d129bea
ID		 1981 return false;
1982
e27daab4
ID		 1983 ret = false;
1984
fe43d3f5 1985 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc
DV		 1986
1987 if (!(tmp & DDI_BUF_CTL_ENABLE))
e27daab4 1988 goto out;
85234cdc 1989
ad80a810
PZ		 1990 if (port == PORT_A) {
1991 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 1992
ad80a810
PZ		 1993 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1994 case TRANS_DDI_EDP_INPUT_A_ON:
1995 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1996 *pipe = PIPE_A;
1997 break;
1998 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1999 *pipe = PIPE_B;
2000 break;
2001 case TRANS_DDI_EDP_INPUT_C_ONOFF:
2002 *pipe = PIPE_C;
2003 break;
2004 }
2005
e27daab4 2006 ret = true;
ad80a810 2007
e27daab4
ID		 2008 goto out;
2009 }
0e32b39c 2010
e27daab4
ID		 2011 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
2012 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
2013
2014 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) {
2015 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
2016 TRANS_DDI_MODE_SELECT_DP_MST)
2017 goto out;
2018
2019 *pipe = i;
2020 ret = true;
2021
2022 goto out;
85234cdc
DV		 2023 }
2024 }
2025
84f44ce7 2026 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
85234cdc 2027
e27daab4
ID		 2028out:
2029 intel_display_power_put(dev_priv, power_domain);
2030
2031 return ret;
85234cdc
DV		 2032}
2033
fc914639
PZ		 2034void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
2035{
2036 struct drm_crtc *crtc = &intel_crtc->base;
7d4aefd0
SS		 2037 struct drm_device *dev = crtc->dev;
2038 struct drm_i915_private *dev_priv = dev->dev_private;
fc914639
PZ		 2039 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
2040 enum port port = intel_ddi_get_encoder_port(intel_encoder);
6e3c9717 2041 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 2042
bb523fc0
PZ		 2043 if (cpu_transcoder != TRANSCODER_EDP)
2044 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2045 TRANS_CLK_SEL_PORT(port));
fc914639
PZ		 2046}
2047
2048void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
2049{
2050 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
6e3c9717 2051 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 2052
bb523fc0
PZ		 2053 if (cpu_transcoder != TRANSCODER_EDP)
2054 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2055 TRANS_CLK_SEL_DISABLED);
fc914639
PZ		 2056}
2057
78ab0bae
VS		 2058static void skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
2059 u32 level, enum port port, int type)
f8896f5d 2060{
f8896f5d
DW		 2061 const struct ddi_buf_trans *ddi_translations;
2062 uint8_t iboost;
75067dde 2063 uint8_t dp_iboost, hdmi_iboost;
f8896f5d
DW		 2064 int n_entries;
2065 u32 reg;
2066
75067dde
AK		 2067 /* VBT may override standard boost values */
2068 dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
2069 hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2070
f8896f5d 2071 if (type == INTEL_OUTPUT_DISPLAYPORT) {
75067dde
AK		 2072 if (dp_iboost) {
2073 iboost = dp_iboost;
2074 } else {
78ab0bae 2075 ddi_translations = skl_get_buf_trans_dp(dev_priv, &n_entries);
e4d4c05b 2076 iboost = ddi_translations[level].i_boost;
75067dde 2077 }
f8896f5d 2078 } else if (type == INTEL_OUTPUT_EDP) {
75067dde
AK		 2079 if (dp_iboost) {
2080 iboost = dp_iboost;
2081 } else {
78ab0bae 2082 ddi_translations = skl_get_buf_trans_edp(dev_priv, &n_entries);
10afa0b6
VS		 2083
2084 if (WARN_ON(port != PORT_A &&
2085 port != PORT_E && n_entries > 9))
2086 n_entries = 9;
2087
e4d4c05b 2088 iboost = ddi_translations[level].i_boost;
75067dde 2089 }
f8896f5d 2090 } else if (type == INTEL_OUTPUT_HDMI) {
75067dde
AK		 2091 if (hdmi_iboost) {
2092 iboost = hdmi_iboost;
2093 } else {
78ab0bae 2094 ddi_translations = skl_get_buf_trans_hdmi(dev_priv, &n_entries);
e4d4c05b 2095 iboost = ddi_translations[level].i_boost;
75067dde 2096 }
f8896f5d
DW		 2097 } else {
2098 return;
2099 }
2100
2101 /* Make sure that the requested I_boost is valid */
2102 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2103 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2104 return;
2105 }
2106
2107 reg = I915_READ(DISPIO_CR_TX_BMU_CR0);
2108 reg &= ~BALANCE_LEG_MASK(port);
2109 reg &= ~(1 << (BALANCE_LEG_DISABLE_SHIFT + port));
2110
2111 if (iboost)
2112 reg |= iboost << BALANCE_LEG_SHIFT(port);
2113 else
2114 reg |= 1 << (BALANCE_LEG_DISABLE_SHIFT + port);
2115
2116 I915_WRITE(DISPIO_CR_TX_BMU_CR0, reg);
2117}
2118
78ab0bae
VS		 2119static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
2120 u32 level, enum port port, int type)
96fb9f9b 2121{
96fb9f9b
VK		 2122 const struct bxt_ddi_buf_trans *ddi_translations;
2123 u32 n_entries, i;
2124 uint32_t val;
2125
d9d7000d
SJ		 2126 if (type == INTEL_OUTPUT_EDP && dev_priv->edp_low_vswing) {
2127 n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
2128 ddi_translations = bxt_ddi_translations_edp;
2129 } else if (type == INTEL_OUTPUT_DISPLAYPORT
2130 || type == INTEL_OUTPUT_EDP) {
96fb9f9b
VK		 2131 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
2132 ddi_translations = bxt_ddi_translations_dp;
2133 } else if (type == INTEL_OUTPUT_HDMI) {
2134 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
2135 ddi_translations = bxt_ddi_translations_hdmi;
2136 } else {
2137 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
2138 type);
2139 return;
2140 }
2141
2142 /* Check if default value has to be used */
2143 if (level >= n_entries ||
2144 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
2145 for (i = 0; i < n_entries; i++) {
2146 if (ddi_translations[i].default_index) {
2147 level = i;
2148 break;
2149 }
2150 }
2151 }
2152
2153 /*
2154 * While we write to the group register to program all lanes at once we
2155 * can read only lane registers and we pick lanes 0/1 for that.
2156 */
2157 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
2158 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
2159 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
2160
2161 val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
2162 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
2163 val |= ddi_translations[level].margin << MARGIN_000_SHIFT |
2164 ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
2165 I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
2166
2167 val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
9c58a049 2168 val &= ~SCALE_DCOMP_METHOD;
96fb9f9b 2169 if (ddi_translations[level].enable)
9c58a049
SJ		 2170 val |= SCALE_DCOMP_METHOD;
2171
2172 if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
2173 DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set");
2174
96fb9f9b
VK		 2175 I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
2176
2177 val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
2178 val &= ~DE_EMPHASIS;
2179 val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
2180 I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
2181
2182 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
2183 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
2184 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
2185}
2186
f8896f5d
DW		 2187static uint32_t translate_signal_level(int signal_levels)
2188{
2189 uint32_t level;
2190
2191 switch (signal_levels) {
2192 default:
2193 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2194 signal_levels);
2195 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2196 level = 0;
2197 break;
2198 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2199 level = 1;
2200 break;
2201 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2202 level = 2;
2203 break;
2204 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
2205 level = 3;
2206 break;
2207
2208 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2209 level = 4;
2210 break;
2211 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2212 level = 5;
2213 break;
2214 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2215 level = 6;
2216 break;
2217
2218 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2219 level = 7;
2220 break;
2221 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2222 level = 8;
2223 break;
2224
2225 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2226 level = 9;
2227 break;
2228 }
2229
2230 return level;
2231}
2232
2233uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2234{
2235 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
78ab0bae 2236 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
f8896f5d
DW		 2237 struct intel_encoder *encoder = &dport->base;
2238 uint8_t train_set = intel_dp->train_set[0];
2239 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2240 DP_TRAIN_PRE_EMPHASIS_MASK);
2241 enum port port = dport->port;
2242 uint32_t level;
2243
2244 level = translate_signal_level(signal_levels);
2245
78ab0bae
VS		 2246 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
2247 skl_ddi_set_iboost(dev_priv, level, port, encoder->type);
2248 else if (IS_BROXTON(dev_priv))
2249 bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
f8896f5d
DW		 2250
2251 return DDI_BUF_TRANS_SELECT(level);
2252}
2253
e404ba8d
VS		 2254void intel_ddi_clk_select(struct intel_encoder *encoder,
2255 const struct intel_crtc_state *pipe_config)
6441ab5f 2256{
e404ba8d
VS		 2257 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2258 enum port port = intel_ddi_get_encoder_port(encoder);
6441ab5f 2259
e404ba8d
VS		 2260 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
2261 uint32_t dpll = pipe_config->ddi_pll_sel;
efa80add
S		 2262 uint32_t val;
2263
5416d871
DL		 2264 /*
2265 * DPLL0 is used for eDP and is the only "private" DPLL (as
2266 * opposed to shared) on SKL
2267 */
e404ba8d 2268 if (encoder->type == INTEL_OUTPUT_EDP) {
5416d871
DL		 2269 WARN_ON(dpll != SKL_DPLL0);
2270
2271 val = I915_READ(DPLL_CTRL1);
2272
2273 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
2274 DPLL_CTRL1_SSC(dpll) |
71cd8423 2275 DPLL_CTRL1_LINK_RATE_MASK(dpll));
e404ba8d 2276 val |= pipe_config->dpll_hw_state.ctrl1 << (dpll * 6);
5416d871
DL		 2277
2278 I915_WRITE(DPLL_CTRL1, val);
2279 POSTING_READ(DPLL_CTRL1);
2280 }
2281
2282 /* DDI -> PLL mapping */
efa80add
S		 2283 val = I915_READ(DPLL_CTRL2);
2284
2285 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2286 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2287 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
2288 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2289
2290 I915_WRITE(DPLL_CTRL2, val);
5416d871 2291
e404ba8d
VS		 2292 } else if (INTEL_INFO(dev_priv)->gen < 9) {
2293 WARN_ON(pipe_config->ddi_pll_sel == PORT_CLK_SEL_NONE);
2294 I915_WRITE(PORT_CLK_SEL(port), pipe_config->ddi_pll_sel);
efa80add 2295 }
e404ba8d
VS		 2296}
2297
2298static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
2299{
2300 struct drm_encoder *encoder = &intel_encoder->base;
6a7e4f99 2301 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
e404ba8d
VS		 2302 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
2303 enum port port = intel_ddi_get_encoder_port(intel_encoder);
2304 int type = intel_encoder->type;
6a7e4f99
VS		 2305
2306 intel_prepare_ddi_buffer(intel_encoder);
e404ba8d
VS		 2307
2308 if (type == INTEL_OUTPUT_EDP) {
2309 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2310 intel_edp_panel_on(intel_dp);
2311 }
2312
2313 intel_ddi_clk_select(intel_encoder, crtc->config);
c19b0669 2314
82a4d9c0 2315 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
c19b0669 2316 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
30cf6db8 2317
901c2daf
VS		 2318 intel_dp_set_link_params(intel_dp, crtc->config);
2319
44905a27 2320 intel_ddi_init_dp_buf_reg(intel_encoder);
c19b0669
PZ		 2321
2322 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2323 intel_dp_start_link_train(intel_dp);
6a7e4f99 2324 if (port != PORT_A || INTEL_INFO(dev_priv)->gen >= 9)
3ab9c637 2325 intel_dp_stop_link_train(intel_dp);
30cf6db8
DV		 2326 } else if (type == INTEL_OUTPUT_HDMI) {
2327 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2328
2329 intel_hdmi->set_infoframes(encoder,
6e3c9717
ACO		 2330 crtc->config->has_hdmi_sink,
2331 &crtc->config->base.adjusted_mode);
c19b0669 2332 }
6441ab5f
PZ		 2333}
2334
00c09d70 2335static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
6441ab5f
PZ		 2336{
2337 struct drm_encoder *encoder = &intel_encoder->base;
efa80add
S		 2338 struct drm_device *dev = encoder->dev;
2339 struct drm_i915_private *dev_priv = dev->dev_private;
6441ab5f 2340 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 2341 int type = intel_encoder->type;
2886e93f 2342 uint32_t val;
a836bdf9 2343 bool wait = false;
2886e93f
PZ		 2344
2345 val = I915_READ(DDI_BUF_CTL(port));
2346 if (val & DDI_BUF_CTL_ENABLE) {
2347 val &= ~DDI_BUF_CTL_ENABLE;
2348 I915_WRITE(DDI_BUF_CTL(port), val);
a836bdf9 2349 wait = true;
2886e93f 2350 }
6441ab5f 2351
a836bdf9
PZ		 2352 val = I915_READ(DP_TP_CTL(port));
2353 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2354 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2355 I915_WRITE(DP_TP_CTL(port), val);
2356
2357 if (wait)
2358 intel_wait_ddi_buf_idle(dev_priv, port);
2359
76bb80ed 2360 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
82a4d9c0 2361 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
76bb80ed 2362 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
24f3e092 2363 intel_edp_panel_vdd_on(intel_dp);
4be73780 2364 intel_edp_panel_off(intel_dp);
82a4d9c0
PZ		 2365 }
2366
ef11bdb3 2367 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
efa80add
S		 2368 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
2369 DPLL_CTRL2_DDI_CLK_OFF(port)));
1ab23380 2370 else if (INTEL_INFO(dev)->gen < 9)
efa80add 2371 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
6441ab5f
PZ		 2372}
2373
00c09d70 2374static void intel_enable_ddi(struct intel_encoder *intel_encoder)
72662e10 2375{
6547fef8 2376 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 2377 struct drm_crtc *crtc = encoder->crtc;
2378 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6547fef8 2379 struct drm_device *dev = encoder->dev;
72662e10 2380 struct drm_i915_private *dev_priv = dev->dev_private;
6547fef8
PZ		 2381 enum port port = intel_ddi_get_encoder_port(intel_encoder);
2382 int type = intel_encoder->type;
72662e10 2383
6547fef8 2384 if (type == INTEL_OUTPUT_HDMI) {
876a8cdf
DL		 2385 struct intel_digital_port *intel_dig_port =
2386 enc_to_dig_port(encoder);
2387
6547fef8
PZ		 2388 /* In HDMI/DVI mode, the port width, and swing/emphasis values
2389 * are ignored so nothing special needs to be done besides
2390 * enabling the port.
2391 */
876a8cdf 2392 I915_WRITE(DDI_BUF_CTL(port),
bcf53de4
SM		 2393 intel_dig_port->saved_port_bits |
2394 DDI_BUF_CTL_ENABLE);
d6c50ff8
PZ		 2395 } else if (type == INTEL_OUTPUT_EDP) {
2396 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2397
23f08d83 2398 if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
3ab9c637
ID		 2399 intel_dp_stop_link_train(intel_dp);
2400
4be73780 2401 intel_edp_backlight_on(intel_dp);
0bc12bcb 2402 intel_psr_enable(intel_dp);
c395578e 2403 intel_edp_drrs_enable(intel_dp);
6547fef8 2404 }
7b9f35a6 2405
6e3c9717 2406 if (intel_crtc->config->has_audio) {
d45a0bf5 2407 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
69bfe1a9 2408 intel_audio_codec_enable(intel_encoder);
7b9f35a6 2409 }
5ab432ef
DV		 2410}
2411
00c09d70 2412static void intel_disable_ddi(struct intel_encoder *intel_encoder)
5ab432ef 2413{
d6c50ff8 2414 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 2415 struct drm_crtc *crtc = encoder->crtc;
2416 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d6c50ff8 2417 int type = intel_encoder->type;
7b9f35a6
WX		 2418 struct drm_device *dev = encoder->dev;
2419 struct drm_i915_private *dev_priv = dev->dev_private;
d6c50ff8 2420
6e3c9717 2421 if (intel_crtc->config->has_audio) {
69bfe1a9 2422 intel_audio_codec_disable(intel_encoder);
d45a0bf5
PZ		 2423 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
2424 }
2831d842 2425
d6c50ff8
PZ		 2426 if (type == INTEL_OUTPUT_EDP) {
2427 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2428
c395578e 2429 intel_edp_drrs_disable(intel_dp);
0bc12bcb 2430 intel_psr_disable(intel_dp);
4be73780 2431 intel_edp_backlight_off(intel_dp);
d6c50ff8 2432 }
72662e10 2433}
79f689aa 2434
5c6706e5
VK		 2435static void broxton_phy_init(struct drm_i915_private *dev_priv,
2436 enum dpio_phy phy)
2437{
2438 enum port port;
2439 uint32_t val;
2440
2441 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
2442 val |= GT_DISPLAY_POWER_ON(phy);
2443 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
2444
2445 /* Considering 10ms timeout until BSpec is updated */
2446 if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
2447 DRM_ERROR("timeout during PHY%d power on\n", phy);
2448
2449 for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A);
2450 port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
2451 int lane;
2452
2453 for (lane = 0; lane < 4; lane++) {
2454 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
2455 /*
2456 * Note that on CHV this flag is called UPAR, but has
2457 * the same function.
2458 */
2459 val &= ~LATENCY_OPTIM;
2460 if (lane != 1)
2461 val |= LATENCY_OPTIM;
2462
2463 I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
2464 }
2465 }
2466
2467 /* Program PLL Rcomp code offset */
2468 val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
2469 val &= ~IREF0RC_OFFSET_MASK;
2470 val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
2471 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
2472
2473 val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
2474 val &= ~IREF1RC_OFFSET_MASK;
2475 val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
2476 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
2477
2478 /* Program power gating */
2479 val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
2480 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
2481 SUS_CLK_CONFIG;
2482 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
2483
2484 if (phy == DPIO_PHY0) {
2485 val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
2486 val |= DW6_OLDO_DYN_PWR_DOWN_EN;
2487 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
2488 }
2489
2490 val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
2491 val &= ~OCL2_LDOFUSE_PWR_DIS;
2492 /*
2493 * On PHY1 disable power on the second channel, since no port is
2494 * connected there. On PHY0 both channels have a port, so leave it
2495 * enabled.
2496 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
2497 * power down the second channel on PHY0 as well.
2498 */
2499 if (phy == DPIO_PHY1)
2500 val |= OCL2_LDOFUSE_PWR_DIS;
2501 I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
2502
2503 if (phy == DPIO_PHY0) {
2504 uint32_t grc_code;
2505 /*
2506 * PHY0 isn't connected to an RCOMP resistor so copy over
2507 * the corresponding calibrated value from PHY1, and disable
2508 * the automatic calibration on PHY0.
2509 */
2510 if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE,
2511 10))
2512 DRM_ERROR("timeout waiting for PHY1 GRC\n");
2513
2514 val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1));
2515 val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
2516 grc_code = val << GRC_CODE_FAST_SHIFT |
2517 val << GRC_CODE_SLOW_SHIFT |
2518 val;
2519 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
2520
2521 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
2522 val |= GRC_DIS | GRC_RDY_OVRD;
2523 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
2524 }
2525
2526 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2527 val |= COMMON_RESET_DIS;
2528 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2529}
2530
2531void broxton_ddi_phy_init(struct drm_device *dev)
2532{
2533 /* Enable PHY1 first since it provides Rcomp for PHY0 */
2534 broxton_phy_init(dev->dev_private, DPIO_PHY1);
2535 broxton_phy_init(dev->dev_private, DPIO_PHY0);
2536}
2537
2538static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
2539 enum dpio_phy phy)
2540{
2541 uint32_t val;
2542
2543 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2544 val &= ~COMMON_RESET_DIS;
2545 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2546}
2547
2548void broxton_ddi_phy_uninit(struct drm_device *dev)
2549{
2550 struct drm_i915_private *dev_priv = dev->dev_private;
2551
2552 broxton_phy_uninit(dev_priv, DPIO_PHY1);
2553 broxton_phy_uninit(dev_priv, DPIO_PHY0);
2554
2555 /* FIXME: do this in broxton_phy_uninit per phy */
2556 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0);
2557}
2558
ad64217b 2559void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
c19b0669 2560{
ad64217b
ACO		 2561 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2562 struct drm_i915_private *dev_priv =
2563 to_i915(intel_dig_port->base.base.dev);
174edf1f 2564 enum port port = intel_dig_port->port;
c19b0669 2565 uint32_t val;
f3e227df 2566 bool wait = false;
c19b0669
PZ		 2567
2568 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2569 val = I915_READ(DDI_BUF_CTL(port));
2570 if (val & DDI_BUF_CTL_ENABLE) {
2571 val &= ~DDI_BUF_CTL_ENABLE;
2572 I915_WRITE(DDI_BUF_CTL(port), val);
2573 wait = true;
2574 }
2575
2576 val = I915_READ(DP_TP_CTL(port));
2577 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2578 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2579 I915_WRITE(DP_TP_CTL(port), val);
2580 POSTING_READ(DP_TP_CTL(port));
2581
2582 if (wait)
2583 intel_wait_ddi_buf_idle(dev_priv, port);
2584 }
2585
0e32b39c 2586 val = DP_TP_CTL_ENABLE |
c19b0669 2587 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
0e32b39c
DA		 2588 if (intel_dp->is_mst)
2589 val |= DP_TP_CTL_MODE_MST;
2590 else {
2591 val |= DP_TP_CTL_MODE_SST;
2592 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2593 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
2594 }
c19b0669
PZ		 2595 I915_WRITE(DP_TP_CTL(port), val);
2596 POSTING_READ(DP_TP_CTL(port));
2597
2598 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
2599 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
2600 POSTING_READ(DDI_BUF_CTL(port));
2601
2602 udelay(600);
2603}
00c09d70 2604
1ad960f2
PZ		 2605void intel_ddi_fdi_disable(struct drm_crtc *crtc)
2606{
2607 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
2608 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
2609 uint32_t val;
2610
2611 intel_ddi_post_disable(intel_encoder);
2612
eede3b53 2613 val = I915_READ(FDI_RX_CTL(PIPE_A));
1ad960f2 2614 val &= ~FDI_RX_ENABLE;
eede3b53 2615 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
1ad960f2 2616
eede3b53 2617 val = I915_READ(FDI_RX_MISC(PIPE_A));
1ad960f2
PZ		 2618 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
2619 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
eede3b53 2620 I915_WRITE(FDI_RX_MISC(PIPE_A), val);
1ad960f2 2621
eede3b53 2622 val = I915_READ(FDI_RX_CTL(PIPE_A));
1ad960f2 2623 val &= ~FDI_PCDCLK;
eede3b53 2624 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
1ad960f2 2625
eede3b53 2626 val = I915_READ(FDI_RX_CTL(PIPE_A));
1ad960f2 2627 val &= ~FDI_RX_PLL_ENABLE;
eede3b53 2628 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
1ad960f2
PZ		 2629}
2630
3d52ccf5
LY		 2631bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
2632 struct intel_crtc *intel_crtc)
2633{
2634 u32 temp;
2635
e27daab4 2636 if (intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
3d52ccf5 2637 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
e27daab4
ID		 2638
2639 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
2640
3d52ccf5
LY		 2641 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
2642 return true;
2643 }
e27daab4 2644
3d52ccf5
LY		 2645 return false;
2646}
2647
6801c18c 2648void intel_ddi_get_config(struct intel_encoder *encoder,
5cec258b 2649 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 2650{
2651 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
2652 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
0cb09a97 2653 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
bbd440fb 2654 struct intel_hdmi *intel_hdmi;
045ac3b5
JB		 2655 u32 temp, flags = 0;
2656
2657 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2658 if (temp & TRANS_DDI_PHSYNC)
2659 flags |= DRM_MODE_FLAG_PHSYNC;
2660 else
2661 flags |= DRM_MODE_FLAG_NHSYNC;
2662 if (temp & TRANS_DDI_PVSYNC)
2663 flags |= DRM_MODE_FLAG_PVSYNC;
2664 else
2665 flags |= DRM_MODE_FLAG_NVSYNC;
2666
2d112de7 2667 pipe_config->base.adjusted_mode.flags |= flags;
42571aef
VS		 2668
2669 switch (temp & TRANS_DDI_BPC_MASK) {
2670 case TRANS_DDI_BPC_6:
2671 pipe_config->pipe_bpp = 18;
2672 break;
2673 case TRANS_DDI_BPC_8:
2674 pipe_config->pipe_bpp = 24;
2675 break;
2676 case TRANS_DDI_BPC_10:
2677 pipe_config->pipe_bpp = 30;
2678 break;
2679 case TRANS_DDI_BPC_12:
2680 pipe_config->pipe_bpp = 36;
2681 break;
2682 default:
2683 break;
2684 }
eb14cb74
VS		 2685
2686 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
2687 case TRANS_DDI_MODE_SELECT_HDMI:
6897b4b5 2688 pipe_config->has_hdmi_sink = true;
bbd440fb
DV		 2689 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2690
cda0aaaf 2691 if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
bbd440fb 2692 pipe_config->has_infoframe = true;
cbc572a9 2693 break;
eb14cb74
VS		 2694 case TRANS_DDI_MODE_SELECT_DVI:
2695 case TRANS_DDI_MODE_SELECT_FDI:
2696 break;
2697 case TRANS_DDI_MODE_SELECT_DP_SST:
2698 case TRANS_DDI_MODE_SELECT_DP_MST:
2699 pipe_config->has_dp_encoder = true;
90a6b7b0
VS		 2700 pipe_config->lane_count =
2701 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
eb14cb74
VS		 2702 intel_dp_get_m_n(intel_crtc, pipe_config);
2703 break;
2704 default:
2705 break;
2706 }
10214420 2707
3d52ccf5
LY		 2708 pipe_config->has_audio =
2709 intel_ddi_is_audio_enabled(dev_priv, intel_crtc);
9ed109a7 2710
10214420
DV		 2711 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
2712 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2713 /*
2714 * This is a big fat ugly hack.
2715 *
2716 * Some machines in UEFI boot mode provide us a VBT that has 18
2717 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2718 * unknown we fail to light up. Yet the same BIOS boots up with
2719 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2720 * max, not what it tells us to use.
2721 *
2722 * Note: This will still be broken if the eDP panel is not lit
2723 * up by the BIOS, and thus we can't get the mode at module
2724 * load.
2725 */
2726 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2727 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2728 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2729 }
11578553 2730
22606a18 2731 intel_ddi_clock_get(encoder, pipe_config);
045ac3b5
JB		 2732}
2733
00c09d70
PZ		 2734static void intel_ddi_destroy(struct drm_encoder *encoder)
2735{
2736 /* HDMI has nothing special to destroy, so we can go with this. */
2737 intel_dp_encoder_destroy(encoder);
2738}
2739
5bfe2ac0 2740static bool intel_ddi_compute_config(struct intel_encoder *encoder,
5cec258b 2741 struct intel_crtc_state *pipe_config)
00c09d70 2742{
5bfe2ac0 2743 int type = encoder->type;
eccb140b 2744 int port = intel_ddi_get_encoder_port(encoder);
00c09d70 2745
5bfe2ac0 2746 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
00c09d70 2747
eccb140b
DV		 2748 if (port == PORT_A)
2749 pipe_config->cpu_transcoder = TRANSCODER_EDP;
2750
00c09d70 2751 if (type == INTEL_OUTPUT_HDMI)
5bfe2ac0 2752 return intel_hdmi_compute_config(encoder, pipe_config);
00c09d70 2753 else
5bfe2ac0 2754 return intel_dp_compute_config(encoder, pipe_config);
00c09d70
PZ		 2755}
2756
2757static const struct drm_encoder_funcs intel_ddi_funcs = {
2758 .destroy = intel_ddi_destroy,
2759};
2760
4a28ae58
PZ		 2761static struct intel_connector *
2762intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
2763{
2764 struct intel_connector *connector;
2765 enum port port = intel_dig_port->port;
2766
9bdbd0b9 2767 connector = intel_connector_alloc();
4a28ae58
PZ		 2768 if (!connector)
2769 return NULL;
2770
2771 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
2772 if (!intel_dp_init_connector(intel_dig_port, connector)) {
2773 kfree(connector);
2774 return NULL;
2775 }
2776
2777 return connector;
2778}
2779
2780static struct intel_connector *
2781intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
2782{
2783 struct intel_connector *connector;
2784 enum port port = intel_dig_port->port;
2785
9bdbd0b9 2786 connector = intel_connector_alloc();
4a28ae58
PZ		 2787 if (!connector)
2788 return NULL;
2789
2790 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
2791 intel_hdmi_init_connector(intel_dig_port, connector);
2792
2793 return connector;
2794}
2795
00c09d70
PZ		 2796void intel_ddi_init(struct drm_device *dev, enum port port)
2797{
876a8cdf 2798 struct drm_i915_private *dev_priv = dev->dev_private;
00c09d70
PZ		 2799 struct intel_digital_port *intel_dig_port;
2800 struct intel_encoder *intel_encoder;
2801 struct drm_encoder *encoder;
311a2094 2802 bool init_hdmi, init_dp;
10e7bec3
VS		 2803 int max_lanes;
2804
2805 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
2806 switch (port) {
2807 case PORT_A:
2808 max_lanes = 4;
2809 break;
2810 case PORT_E:
2811 max_lanes = 0;
2812 break;
2813 default:
2814 max_lanes = 4;
2815 break;
2816 }
2817 } else {
2818 switch (port) {
2819 case PORT_A:
2820 max_lanes = 2;
2821 break;
2822 case PORT_E:
2823 max_lanes = 2;
2824 break;
2825 default:
2826 max_lanes = 4;
2827 break;
2828 }
2829 }
311a2094
PZ		 2830
2831 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
2832 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
2833 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
2834 if (!init_dp && !init_hdmi) {
500ea70d 2835 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
311a2094 2836 port_name(port));
500ea70d 2837 return;
311a2094 2838 }
00c09d70 2839
b14c5679 2840 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
00c09d70
PZ		 2841 if (!intel_dig_port)
2842 return;
2843
00c09d70
PZ		 2844 intel_encoder = &intel_dig_port->base;
2845 encoder = &intel_encoder->base;
2846
2847 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
13a3d91f 2848 DRM_MODE_ENCODER_TMDS, NULL);
00c09d70 2849
5bfe2ac0 2850 intel_encoder->compute_config = intel_ddi_compute_config;
00c09d70
PZ		 2851 intel_encoder->enable = intel_enable_ddi;
2852 intel_encoder->pre_enable = intel_ddi_pre_enable;
2853 intel_encoder->disable = intel_disable_ddi;
2854 intel_encoder->post_disable = intel_ddi_post_disable;
2855 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
045ac3b5 2856 intel_encoder->get_config = intel_ddi_get_config;
00c09d70
PZ		 2857
2858 intel_dig_port->port = port;
bcf53de4
SM		 2859 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
2860 (DDI_BUF_PORT_REVERSAL |
2861 DDI_A_4_LANES);
00c09d70 2862
6c566dc9
MR		 2863 /*
2864 * Bspec says that DDI_A_4_LANES is the only supported configuration
2865 * for Broxton. Yet some BIOS fail to set this bit on port A if eDP
2866 * wasn't lit up at boot. Force this bit on in our internal
2867 * configuration so that we use the proper lane count for our
2868 * calculations.
2869 */
2870 if (IS_BROXTON(dev) && port == PORT_A) {
2871 if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
2872 DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
2873 intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
ed8d60f4 2874 max_lanes = 4;
6c566dc9
MR		 2875 }
2876 }
2877
ed8d60f4
MR		 2878 intel_dig_port->max_lanes = max_lanes;
2879
00c09d70 2880 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
f68d697e 2881 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
bc079e8b 2882 intel_encoder->cloneable = 0;
00c09d70 2883
f68d697e
CW		 2884 if (init_dp) {
2885 if (!intel_ddi_init_dp_connector(intel_dig_port))
2886 goto err;
13cf5504 2887
f68d697e 2888 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
cf1d5883
SJ		 2889 /*
2890 * On BXT A0/A1, sw needs to activate DDIA HPD logic and
2891 * interrupts to check the external panel connection.
2892 */
e87a005d 2893 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) && port == PORT_B)
cf1d5883
SJ		 2894 dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port;
2895 else
2896 dev_priv->hotplug.irq_port[port] = intel_dig_port;
f68d697e 2897 }
21a8e6a4 2898
311a2094
PZ		 2899 /* In theory we don't need the encoder->type check, but leave it just in
2900 * case we have some really bad VBTs... */
f68d697e
CW		 2901 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
2902 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
2903 goto err;
21a8e6a4 2904 }
f68d697e
CW		 2905
2906 return;
2907
2908err:
2909 drm_encoder_cleanup(encoder);
2910 kfree(intel_dig_port);
00c09d70 2911}
Linux kernel - Deliverables
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