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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
760285e7 DH |
40 | #include <drm/drm_dp_helper.h> |
41 | #include <drm/drm_crtc_helper.h> | |
c0f372b3 | 42 | #include <linux/dma_remapping.h> |
79e53945 | 43 | |
ef9348c8 CML |
44 | #define DIV_ROUND_CLOSEST_ULL(ll, d) \ |
45 | ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; }) | |
46 | ||
3dec0095 | 47 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
6b383a7f | 48 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 49 | |
f1f644dc JB |
50 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
51 | struct intel_crtc_config *pipe_config); | |
18442d08 VS |
52 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
53 | struct intel_crtc_config *pipe_config); | |
f1f644dc | 54 | |
e7457a9a DL |
55 | static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
56 | int x, int y, struct drm_framebuffer *old_fb); | |
eb1bfe80 JB |
57 | static int intel_framebuffer_init(struct drm_device *dev, |
58 | struct intel_framebuffer *ifb, | |
59 | struct drm_mode_fb_cmd2 *mode_cmd, | |
60 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
61 | static void intel_dp_set_m_n(struct intel_crtc *crtc); |
62 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); | |
63 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
29407aab DV |
64 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
65 | struct intel_link_m_n *m_n); | |
66 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); | |
229fca97 DV |
67 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
68 | static void intel_set_pipe_csc(struct drm_crtc *crtc); | |
bdd4b6a6 | 69 | static void vlv_prepare_pll(struct intel_crtc *crtc); |
e7457a9a | 70 | |
79e53945 | 71 | typedef struct { |
0206e353 | 72 | int min, max; |
79e53945 JB |
73 | } intel_range_t; |
74 | ||
75 | typedef struct { | |
0206e353 AJ |
76 | int dot_limit; |
77 | int p2_slow, p2_fast; | |
79e53945 JB |
78 | } intel_p2_t; |
79 | ||
d4906093 ML |
80 | typedef struct intel_limit intel_limit_t; |
81 | struct intel_limit { | |
0206e353 AJ |
82 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
83 | intel_p2_t p2; | |
d4906093 | 84 | }; |
79e53945 | 85 | |
d2acd215 DV |
86 | int |
87 | intel_pch_rawclk(struct drm_device *dev) | |
88 | { | |
89 | struct drm_i915_private *dev_priv = dev->dev_private; | |
90 | ||
91 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
92 | ||
93 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
94 | } | |
95 | ||
021357ac CW |
96 | static inline u32 /* units of 100MHz */ |
97 | intel_fdi_link_freq(struct drm_device *dev) | |
98 | { | |
8b99e68c CW |
99 | if (IS_GEN5(dev)) { |
100 | struct drm_i915_private *dev_priv = dev->dev_private; | |
101 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
102 | } else | |
103 | return 27; | |
021357ac CW |
104 | } |
105 | ||
5d536e28 | 106 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 107 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 108 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 109 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
110 | .m = { .min = 96, .max = 140 }, |
111 | .m1 = { .min = 18, .max = 26 }, | |
112 | .m2 = { .min = 6, .max = 16 }, | |
113 | .p = { .min = 4, .max = 128 }, | |
114 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
115 | .p2 = { .dot_limit = 165000, |
116 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
117 | }; |
118 | ||
5d536e28 DV |
119 | static const intel_limit_t intel_limits_i8xx_dvo = { |
120 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 121 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 122 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
123 | .m = { .min = 96, .max = 140 }, |
124 | .m1 = { .min = 18, .max = 26 }, | |
125 | .m2 = { .min = 6, .max = 16 }, | |
126 | .p = { .min = 4, .max = 128 }, | |
127 | .p1 = { .min = 2, .max = 33 }, | |
128 | .p2 = { .dot_limit = 165000, | |
129 | .p2_slow = 4, .p2_fast = 4 }, | |
130 | }; | |
131 | ||
e4b36699 | 132 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 133 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 134 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 135 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
136 | .m = { .min = 96, .max = 140 }, |
137 | .m1 = { .min = 18, .max = 26 }, | |
138 | .m2 = { .min = 6, .max = 16 }, | |
139 | .p = { .min = 4, .max = 128 }, | |
140 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
141 | .p2 = { .dot_limit = 165000, |
142 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 143 | }; |
273e27ca | 144 | |
e4b36699 | 145 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
146 | .dot = { .min = 20000, .max = 400000 }, |
147 | .vco = { .min = 1400000, .max = 2800000 }, | |
148 | .n = { .min = 1, .max = 6 }, | |
149 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
150 | .m1 = { .min = 8, .max = 18 }, |
151 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
152 | .p = { .min = 5, .max = 80 }, |
153 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
154 | .p2 = { .dot_limit = 200000, |
155 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
156 | }; |
157 | ||
158 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
159 | .dot = { .min = 20000, .max = 400000 }, |
160 | .vco = { .min = 1400000, .max = 2800000 }, | |
161 | .n = { .min = 1, .max = 6 }, | |
162 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
163 | .m1 = { .min = 8, .max = 18 }, |
164 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
165 | .p = { .min = 7, .max = 98 }, |
166 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
167 | .p2 = { .dot_limit = 112000, |
168 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
169 | }; |
170 | ||
273e27ca | 171 | |
e4b36699 | 172 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
173 | .dot = { .min = 25000, .max = 270000 }, |
174 | .vco = { .min = 1750000, .max = 3500000}, | |
175 | .n = { .min = 1, .max = 4 }, | |
176 | .m = { .min = 104, .max = 138 }, | |
177 | .m1 = { .min = 17, .max = 23 }, | |
178 | .m2 = { .min = 5, .max = 11 }, | |
179 | .p = { .min = 10, .max = 30 }, | |
180 | .p1 = { .min = 1, .max = 3}, | |
181 | .p2 = { .dot_limit = 270000, | |
182 | .p2_slow = 10, | |
183 | .p2_fast = 10 | |
044c7c41 | 184 | }, |
e4b36699 KP |
185 | }; |
186 | ||
187 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
188 | .dot = { .min = 22000, .max = 400000 }, |
189 | .vco = { .min = 1750000, .max = 3500000}, | |
190 | .n = { .min = 1, .max = 4 }, | |
191 | .m = { .min = 104, .max = 138 }, | |
192 | .m1 = { .min = 16, .max = 23 }, | |
193 | .m2 = { .min = 5, .max = 11 }, | |
194 | .p = { .min = 5, .max = 80 }, | |
195 | .p1 = { .min = 1, .max = 8}, | |
196 | .p2 = { .dot_limit = 165000, | |
197 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
198 | }; |
199 | ||
200 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
201 | .dot = { .min = 20000, .max = 115000 }, |
202 | .vco = { .min = 1750000, .max = 3500000 }, | |
203 | .n = { .min = 1, .max = 3 }, | |
204 | .m = { .min = 104, .max = 138 }, | |
205 | .m1 = { .min = 17, .max = 23 }, | |
206 | .m2 = { .min = 5, .max = 11 }, | |
207 | .p = { .min = 28, .max = 112 }, | |
208 | .p1 = { .min = 2, .max = 8 }, | |
209 | .p2 = { .dot_limit = 0, | |
210 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 211 | }, |
e4b36699 KP |
212 | }; |
213 | ||
214 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
215 | .dot = { .min = 80000, .max = 224000 }, |
216 | .vco = { .min = 1750000, .max = 3500000 }, | |
217 | .n = { .min = 1, .max = 3 }, | |
218 | .m = { .min = 104, .max = 138 }, | |
219 | .m1 = { .min = 17, .max = 23 }, | |
220 | .m2 = { .min = 5, .max = 11 }, | |
221 | .p = { .min = 14, .max = 42 }, | |
222 | .p1 = { .min = 2, .max = 6 }, | |
223 | .p2 = { .dot_limit = 0, | |
224 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 225 | }, |
e4b36699 KP |
226 | }; |
227 | ||
f2b115e6 | 228 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
229 | .dot = { .min = 20000, .max = 400000}, |
230 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 231 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
232 | .n = { .min = 3, .max = 6 }, |
233 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 234 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
235 | .m1 = { .min = 0, .max = 0 }, |
236 | .m2 = { .min = 0, .max = 254 }, | |
237 | .p = { .min = 5, .max = 80 }, | |
238 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
239 | .p2 = { .dot_limit = 200000, |
240 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
241 | }; |
242 | ||
f2b115e6 | 243 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
244 | .dot = { .min = 20000, .max = 400000 }, |
245 | .vco = { .min = 1700000, .max = 3500000 }, | |
246 | .n = { .min = 3, .max = 6 }, | |
247 | .m = { .min = 2, .max = 256 }, | |
248 | .m1 = { .min = 0, .max = 0 }, | |
249 | .m2 = { .min = 0, .max = 254 }, | |
250 | .p = { .min = 7, .max = 112 }, | |
251 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
252 | .p2 = { .dot_limit = 112000, |
253 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
254 | }; |
255 | ||
273e27ca EA |
256 | /* Ironlake / Sandybridge |
257 | * | |
258 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
259 | * the range value for them is (actual_value - 2). | |
260 | */ | |
b91ad0ec | 261 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
262 | .dot = { .min = 25000, .max = 350000 }, |
263 | .vco = { .min = 1760000, .max = 3510000 }, | |
264 | .n = { .min = 1, .max = 5 }, | |
265 | .m = { .min = 79, .max = 127 }, | |
266 | .m1 = { .min = 12, .max = 22 }, | |
267 | .m2 = { .min = 5, .max = 9 }, | |
268 | .p = { .min = 5, .max = 80 }, | |
269 | .p1 = { .min = 1, .max = 8 }, | |
270 | .p2 = { .dot_limit = 225000, | |
271 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
272 | }; |
273 | ||
b91ad0ec | 274 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
275 | .dot = { .min = 25000, .max = 350000 }, |
276 | .vco = { .min = 1760000, .max = 3510000 }, | |
277 | .n = { .min = 1, .max = 3 }, | |
278 | .m = { .min = 79, .max = 118 }, | |
279 | .m1 = { .min = 12, .max = 22 }, | |
280 | .m2 = { .min = 5, .max = 9 }, | |
281 | .p = { .min = 28, .max = 112 }, | |
282 | .p1 = { .min = 2, .max = 8 }, | |
283 | .p2 = { .dot_limit = 225000, | |
284 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
285 | }; |
286 | ||
287 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
288 | .dot = { .min = 25000, .max = 350000 }, |
289 | .vco = { .min = 1760000, .max = 3510000 }, | |
290 | .n = { .min = 1, .max = 3 }, | |
291 | .m = { .min = 79, .max = 127 }, | |
292 | .m1 = { .min = 12, .max = 22 }, | |
293 | .m2 = { .min = 5, .max = 9 }, | |
294 | .p = { .min = 14, .max = 56 }, | |
295 | .p1 = { .min = 2, .max = 8 }, | |
296 | .p2 = { .dot_limit = 225000, | |
297 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
298 | }; |
299 | ||
273e27ca | 300 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 301 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
302 | .dot = { .min = 25000, .max = 350000 }, |
303 | .vco = { .min = 1760000, .max = 3510000 }, | |
304 | .n = { .min = 1, .max = 2 }, | |
305 | .m = { .min = 79, .max = 126 }, | |
306 | .m1 = { .min = 12, .max = 22 }, | |
307 | .m2 = { .min = 5, .max = 9 }, | |
308 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 309 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
310 | .p2 = { .dot_limit = 225000, |
311 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
312 | }; |
313 | ||
314 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
315 | .dot = { .min = 25000, .max = 350000 }, |
316 | .vco = { .min = 1760000, .max = 3510000 }, | |
317 | .n = { .min = 1, .max = 3 }, | |
318 | .m = { .min = 79, .max = 126 }, | |
319 | .m1 = { .min = 12, .max = 22 }, | |
320 | .m2 = { .min = 5, .max = 9 }, | |
321 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 322 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
323 | .p2 = { .dot_limit = 225000, |
324 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
325 | }; |
326 | ||
dc730512 | 327 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
328 | /* |
329 | * These are the data rate limits (measured in fast clocks) | |
330 | * since those are the strictest limits we have. The fast | |
331 | * clock and actual rate limits are more relaxed, so checking | |
332 | * them would make no difference. | |
333 | */ | |
334 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 335 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 336 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
337 | .m1 = { .min = 2, .max = 3 }, |
338 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 339 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 340 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
341 | }; |
342 | ||
ef9348c8 CML |
343 | static const intel_limit_t intel_limits_chv = { |
344 | /* | |
345 | * These are the data rate limits (measured in fast clocks) | |
346 | * since those are the strictest limits we have. The fast | |
347 | * clock and actual rate limits are more relaxed, so checking | |
348 | * them would make no difference. | |
349 | */ | |
350 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
351 | .vco = { .min = 4860000, .max = 6700000 }, | |
352 | .n = { .min = 1, .max = 1 }, | |
353 | .m1 = { .min = 2, .max = 2 }, | |
354 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
355 | .p1 = { .min = 2, .max = 4 }, | |
356 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
357 | }; | |
358 | ||
6b4bf1c4 VS |
359 | static void vlv_clock(int refclk, intel_clock_t *clock) |
360 | { | |
361 | clock->m = clock->m1 * clock->m2; | |
362 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
363 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
364 | return; | |
fb03ac01 VS |
365 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
366 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
6b4bf1c4 VS |
367 | } |
368 | ||
e0638cdf PZ |
369 | /** |
370 | * Returns whether any output on the specified pipe is of the specified type | |
371 | */ | |
372 | static bool intel_pipe_has_type(struct drm_crtc *crtc, int type) | |
373 | { | |
374 | struct drm_device *dev = crtc->dev; | |
375 | struct intel_encoder *encoder; | |
376 | ||
377 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
378 | if (encoder->type == type) | |
379 | return true; | |
380 | ||
381 | return false; | |
382 | } | |
383 | ||
1b894b59 CW |
384 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
385 | int refclk) | |
2c07245f | 386 | { |
b91ad0ec | 387 | struct drm_device *dev = crtc->dev; |
2c07245f | 388 | const intel_limit_t *limit; |
b91ad0ec ZW |
389 | |
390 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 391 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 392 | if (refclk == 100000) |
b91ad0ec ZW |
393 | limit = &intel_limits_ironlake_dual_lvds_100m; |
394 | else | |
395 | limit = &intel_limits_ironlake_dual_lvds; | |
396 | } else { | |
1b894b59 | 397 | if (refclk == 100000) |
b91ad0ec ZW |
398 | limit = &intel_limits_ironlake_single_lvds_100m; |
399 | else | |
400 | limit = &intel_limits_ironlake_single_lvds; | |
401 | } | |
c6bb3538 | 402 | } else |
b91ad0ec | 403 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
404 | |
405 | return limit; | |
406 | } | |
407 | ||
044c7c41 ML |
408 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
409 | { | |
410 | struct drm_device *dev = crtc->dev; | |
044c7c41 ML |
411 | const intel_limit_t *limit; |
412 | ||
413 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 414 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 415 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 416 | else |
e4b36699 | 417 | limit = &intel_limits_g4x_single_channel_lvds; |
044c7c41 ML |
418 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
419 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 420 | limit = &intel_limits_g4x_hdmi; |
044c7c41 | 421 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 422 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 423 | } else /* The option is for other outputs */ |
e4b36699 | 424 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
425 | |
426 | return limit; | |
427 | } | |
428 | ||
1b894b59 | 429 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
79e53945 JB |
430 | { |
431 | struct drm_device *dev = crtc->dev; | |
432 | const intel_limit_t *limit; | |
433 | ||
bad720ff | 434 | if (HAS_PCH_SPLIT(dev)) |
1b894b59 | 435 | limit = intel_ironlake_limit(crtc, refclk); |
2c07245f | 436 | else if (IS_G4X(dev)) { |
044c7c41 | 437 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 438 | } else if (IS_PINEVIEW(dev)) { |
2177832f | 439 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 440 | limit = &intel_limits_pineview_lvds; |
2177832f | 441 | else |
f2b115e6 | 442 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
443 | } else if (IS_CHERRYVIEW(dev)) { |
444 | limit = &intel_limits_chv; | |
a0c4da24 | 445 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 446 | limit = &intel_limits_vlv; |
a6c45cf0 CW |
447 | } else if (!IS_GEN2(dev)) { |
448 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
449 | limit = &intel_limits_i9xx_lvds; | |
450 | else | |
451 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 JB |
452 | } else { |
453 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 454 | limit = &intel_limits_i8xx_lvds; |
5d536e28 | 455 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO)) |
e4b36699 | 456 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
457 | else |
458 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
459 | } |
460 | return limit; | |
461 | } | |
462 | ||
f2b115e6 AJ |
463 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
464 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 465 | { |
2177832f SL |
466 | clock->m = clock->m2 + 2; |
467 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
468 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
469 | return; | |
fb03ac01 VS |
470 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
471 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
2177832f SL |
472 | } |
473 | ||
7429e9d4 DV |
474 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
475 | { | |
476 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
477 | } | |
478 | ||
ac58c3f0 | 479 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
2177832f | 480 | { |
7429e9d4 | 481 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 482 | clock->p = clock->p1 * clock->p2; |
ed5ca77e VS |
483 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
484 | return; | |
fb03ac01 VS |
485 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
486 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
79e53945 JB |
487 | } |
488 | ||
ef9348c8 CML |
489 | static void chv_clock(int refclk, intel_clock_t *clock) |
490 | { | |
491 | clock->m = clock->m1 * clock->m2; | |
492 | clock->p = clock->p1 * clock->p2; | |
493 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
494 | return; | |
495 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, | |
496 | clock->n << 22); | |
497 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
498 | } | |
499 | ||
7c04d1d9 | 500 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
501 | /** |
502 | * Returns whether the given set of divisors are valid for a given refclk with | |
503 | * the given connectors. | |
504 | */ | |
505 | ||
1b894b59 CW |
506 | static bool intel_PLL_is_valid(struct drm_device *dev, |
507 | const intel_limit_t *limit, | |
508 | const intel_clock_t *clock) | |
79e53945 | 509 | { |
f01b7962 VS |
510 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
511 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 512 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 513 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 514 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 515 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 516 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 517 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 VS |
518 | |
519 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev)) | |
520 | if (clock->m1 <= clock->m2) | |
521 | INTELPllInvalid("m1 <= m2\n"); | |
522 | ||
523 | if (!IS_VALLEYVIEW(dev)) { | |
524 | if (clock->p < limit->p.min || limit->p.max < clock->p) | |
525 | INTELPllInvalid("p out of range\n"); | |
526 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
527 | INTELPllInvalid("m out of range\n"); | |
528 | } | |
529 | ||
79e53945 | 530 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 531 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
532 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
533 | * connector, etc., rather than just a single range. | |
534 | */ | |
535 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 536 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
537 | |
538 | return true; | |
539 | } | |
540 | ||
d4906093 | 541 | static bool |
ee9300bb | 542 | i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
cec2f356 SP |
543 | int target, int refclk, intel_clock_t *match_clock, |
544 | intel_clock_t *best_clock) | |
79e53945 JB |
545 | { |
546 | struct drm_device *dev = crtc->dev; | |
79e53945 | 547 | intel_clock_t clock; |
79e53945 JB |
548 | int err = target; |
549 | ||
a210b028 | 550 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 551 | /* |
a210b028 DV |
552 | * For LVDS just rely on its current settings for dual-channel. |
553 | * We haven't figured out how to reliably set up different | |
554 | * single/dual channel state, if we even can. | |
79e53945 | 555 | */ |
1974cad0 | 556 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
557 | clock.p2 = limit->p2.p2_fast; |
558 | else | |
559 | clock.p2 = limit->p2.p2_slow; | |
560 | } else { | |
561 | if (target < limit->p2.dot_limit) | |
562 | clock.p2 = limit->p2.p2_slow; | |
563 | else | |
564 | clock.p2 = limit->p2.p2_fast; | |
565 | } | |
566 | ||
0206e353 | 567 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 568 | |
42158660 ZY |
569 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
570 | clock.m1++) { | |
571 | for (clock.m2 = limit->m2.min; | |
572 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 573 | if (clock.m2 >= clock.m1) |
42158660 ZY |
574 | break; |
575 | for (clock.n = limit->n.min; | |
576 | clock.n <= limit->n.max; clock.n++) { | |
577 | for (clock.p1 = limit->p1.min; | |
578 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
579 | int this_err; |
580 | ||
ac58c3f0 DV |
581 | i9xx_clock(refclk, &clock); |
582 | if (!intel_PLL_is_valid(dev, limit, | |
583 | &clock)) | |
584 | continue; | |
585 | if (match_clock && | |
586 | clock.p != match_clock->p) | |
587 | continue; | |
588 | ||
589 | this_err = abs(clock.dot - target); | |
590 | if (this_err < err) { | |
591 | *best_clock = clock; | |
592 | err = this_err; | |
593 | } | |
594 | } | |
595 | } | |
596 | } | |
597 | } | |
598 | ||
599 | return (err != target); | |
600 | } | |
601 | ||
602 | static bool | |
ee9300bb DV |
603 | pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
604 | int target, int refclk, intel_clock_t *match_clock, | |
605 | intel_clock_t *best_clock) | |
79e53945 JB |
606 | { |
607 | struct drm_device *dev = crtc->dev; | |
79e53945 | 608 | intel_clock_t clock; |
79e53945 JB |
609 | int err = target; |
610 | ||
a210b028 | 611 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 612 | /* |
a210b028 DV |
613 | * For LVDS just rely on its current settings for dual-channel. |
614 | * We haven't figured out how to reliably set up different | |
615 | * single/dual channel state, if we even can. | |
79e53945 | 616 | */ |
1974cad0 | 617 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
618 | clock.p2 = limit->p2.p2_fast; |
619 | else | |
620 | clock.p2 = limit->p2.p2_slow; | |
621 | } else { | |
622 | if (target < limit->p2.dot_limit) | |
623 | clock.p2 = limit->p2.p2_slow; | |
624 | else | |
625 | clock.p2 = limit->p2.p2_fast; | |
626 | } | |
627 | ||
0206e353 | 628 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 629 | |
42158660 ZY |
630 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
631 | clock.m1++) { | |
632 | for (clock.m2 = limit->m2.min; | |
633 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
634 | for (clock.n = limit->n.min; |
635 | clock.n <= limit->n.max; clock.n++) { | |
636 | for (clock.p1 = limit->p1.min; | |
637 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
638 | int this_err; |
639 | ||
ac58c3f0 | 640 | pineview_clock(refclk, &clock); |
1b894b59 CW |
641 | if (!intel_PLL_is_valid(dev, limit, |
642 | &clock)) | |
79e53945 | 643 | continue; |
cec2f356 SP |
644 | if (match_clock && |
645 | clock.p != match_clock->p) | |
646 | continue; | |
79e53945 JB |
647 | |
648 | this_err = abs(clock.dot - target); | |
649 | if (this_err < err) { | |
650 | *best_clock = clock; | |
651 | err = this_err; | |
652 | } | |
653 | } | |
654 | } | |
655 | } | |
656 | } | |
657 | ||
658 | return (err != target); | |
659 | } | |
660 | ||
d4906093 | 661 | static bool |
ee9300bb DV |
662 | g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
663 | int target, int refclk, intel_clock_t *match_clock, | |
664 | intel_clock_t *best_clock) | |
d4906093 ML |
665 | { |
666 | struct drm_device *dev = crtc->dev; | |
d4906093 ML |
667 | intel_clock_t clock; |
668 | int max_n; | |
669 | bool found; | |
6ba770dc AJ |
670 | /* approximately equals target * 0.00585 */ |
671 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
672 | found = false; |
673 | ||
674 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 675 | if (intel_is_dual_link_lvds(dev)) |
d4906093 ML |
676 | clock.p2 = limit->p2.p2_fast; |
677 | else | |
678 | clock.p2 = limit->p2.p2_slow; | |
679 | } else { | |
680 | if (target < limit->p2.dot_limit) | |
681 | clock.p2 = limit->p2.p2_slow; | |
682 | else | |
683 | clock.p2 = limit->p2.p2_fast; | |
684 | } | |
685 | ||
686 | memset(best_clock, 0, sizeof(*best_clock)); | |
687 | max_n = limit->n.max; | |
f77f13e2 | 688 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 689 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 690 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
691 | for (clock.m1 = limit->m1.max; |
692 | clock.m1 >= limit->m1.min; clock.m1--) { | |
693 | for (clock.m2 = limit->m2.max; | |
694 | clock.m2 >= limit->m2.min; clock.m2--) { | |
695 | for (clock.p1 = limit->p1.max; | |
696 | clock.p1 >= limit->p1.min; clock.p1--) { | |
697 | int this_err; | |
698 | ||
ac58c3f0 | 699 | i9xx_clock(refclk, &clock); |
1b894b59 CW |
700 | if (!intel_PLL_is_valid(dev, limit, |
701 | &clock)) | |
d4906093 | 702 | continue; |
1b894b59 CW |
703 | |
704 | this_err = abs(clock.dot - target); | |
d4906093 ML |
705 | if (this_err < err_most) { |
706 | *best_clock = clock; | |
707 | err_most = this_err; | |
708 | max_n = clock.n; | |
709 | found = true; | |
710 | } | |
711 | } | |
712 | } | |
713 | } | |
714 | } | |
2c07245f ZW |
715 | return found; |
716 | } | |
717 | ||
a0c4da24 | 718 | static bool |
ee9300bb DV |
719 | vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
720 | int target, int refclk, intel_clock_t *match_clock, | |
721 | intel_clock_t *best_clock) | |
a0c4da24 | 722 | { |
f01b7962 | 723 | struct drm_device *dev = crtc->dev; |
6b4bf1c4 | 724 | intel_clock_t clock; |
69e4f900 | 725 | unsigned int bestppm = 1000000; |
27e639bf VS |
726 | /* min update 19.2 MHz */ |
727 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 728 | bool found = false; |
a0c4da24 | 729 | |
6b4bf1c4 VS |
730 | target *= 5; /* fast clock */ |
731 | ||
732 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
733 | |
734 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 735 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 736 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 737 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 738 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 739 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 740 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 741 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
69e4f900 VS |
742 | unsigned int ppm, diff; |
743 | ||
6b4bf1c4 VS |
744 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
745 | refclk * clock.m1); | |
746 | ||
747 | vlv_clock(refclk, &clock); | |
43b0ac53 | 748 | |
f01b7962 VS |
749 | if (!intel_PLL_is_valid(dev, limit, |
750 | &clock)) | |
43b0ac53 VS |
751 | continue; |
752 | ||
6b4bf1c4 VS |
753 | diff = abs(clock.dot - target); |
754 | ppm = div_u64(1000000ULL * diff, target); | |
755 | ||
756 | if (ppm < 100 && clock.p > best_clock->p) { | |
43b0ac53 | 757 | bestppm = 0; |
6b4bf1c4 | 758 | *best_clock = clock; |
49e497ef | 759 | found = true; |
43b0ac53 | 760 | } |
6b4bf1c4 | 761 | |
c686122c | 762 | if (bestppm >= 10 && ppm < bestppm - 10) { |
69e4f900 | 763 | bestppm = ppm; |
6b4bf1c4 | 764 | *best_clock = clock; |
49e497ef | 765 | found = true; |
a0c4da24 JB |
766 | } |
767 | } | |
768 | } | |
769 | } | |
770 | } | |
a0c4da24 | 771 | |
49e497ef | 772 | return found; |
a0c4da24 | 773 | } |
a4fc5ed6 | 774 | |
ef9348c8 CML |
775 | static bool |
776 | chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, | |
777 | int target, int refclk, intel_clock_t *match_clock, | |
778 | intel_clock_t *best_clock) | |
779 | { | |
780 | struct drm_device *dev = crtc->dev; | |
781 | intel_clock_t clock; | |
782 | uint64_t m2; | |
783 | int found = false; | |
784 | ||
785 | memset(best_clock, 0, sizeof(*best_clock)); | |
786 | ||
787 | /* | |
788 | * Based on hardware doc, the n always set to 1, and m1 always | |
789 | * set to 2. If requires to support 200Mhz refclk, we need to | |
790 | * revisit this because n may not 1 anymore. | |
791 | */ | |
792 | clock.n = 1, clock.m1 = 2; | |
793 | target *= 5; /* fast clock */ | |
794 | ||
795 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
796 | for (clock.p2 = limit->p2.p2_fast; | |
797 | clock.p2 >= limit->p2.p2_slow; | |
798 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
799 | ||
800 | clock.p = clock.p1 * clock.p2; | |
801 | ||
802 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
803 | clock.n) << 22, refclk * clock.m1); | |
804 | ||
805 | if (m2 > INT_MAX/clock.m1) | |
806 | continue; | |
807 | ||
808 | clock.m2 = m2; | |
809 | ||
810 | chv_clock(refclk, &clock); | |
811 | ||
812 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
813 | continue; | |
814 | ||
815 | /* based on hardware requirement, prefer bigger p | |
816 | */ | |
817 | if (clock.p > best_clock->p) { | |
818 | *best_clock = clock; | |
819 | found = true; | |
820 | } | |
821 | } | |
822 | } | |
823 | ||
824 | return found; | |
825 | } | |
826 | ||
20ddf665 VS |
827 | bool intel_crtc_active(struct drm_crtc *crtc) |
828 | { | |
829 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
830 | ||
831 | /* Be paranoid as we can arrive here with only partial | |
832 | * state retrieved from the hardware during setup. | |
833 | * | |
241bfc38 | 834 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
835 | * as Haswell has gained clock readout/fastboot support. |
836 | * | |
66e514c1 | 837 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 VS |
838 | * properly reconstruct framebuffers. |
839 | */ | |
f4510a27 | 840 | return intel_crtc->active && crtc->primary->fb && |
241bfc38 | 841 | intel_crtc->config.adjusted_mode.crtc_clock; |
20ddf665 VS |
842 | } |
843 | ||
a5c961d1 PZ |
844 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
845 | enum pipe pipe) | |
846 | { | |
847 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
848 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
849 | ||
3b117c8f | 850 | return intel_crtc->config.cpu_transcoder; |
a5c961d1 PZ |
851 | } |
852 | ||
57e22f4a | 853 | static void g4x_wait_for_vblank(struct drm_device *dev, int pipe) |
a928d536 PZ |
854 | { |
855 | struct drm_i915_private *dev_priv = dev->dev_private; | |
57e22f4a | 856 | u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe); |
a928d536 PZ |
857 | |
858 | frame = I915_READ(frame_reg); | |
859 | ||
860 | if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) | |
93937071 | 861 | WARN(1, "vblank wait timed out\n"); |
a928d536 PZ |
862 | } |
863 | ||
9d0498a2 JB |
864 | /** |
865 | * intel_wait_for_vblank - wait for vblank on a given pipe | |
866 | * @dev: drm device | |
867 | * @pipe: pipe to wait for | |
868 | * | |
869 | * Wait for vblank to occur on a given pipe. Needed for various bits of | |
870 | * mode setting code. | |
871 | */ | |
872 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) | |
79e53945 | 873 | { |
9d0498a2 | 874 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 875 | int pipestat_reg = PIPESTAT(pipe); |
9d0498a2 | 876 | |
57e22f4a VS |
877 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
878 | g4x_wait_for_vblank(dev, pipe); | |
a928d536 PZ |
879 | return; |
880 | } | |
881 | ||
300387c0 CW |
882 | /* Clear existing vblank status. Note this will clear any other |
883 | * sticky status fields as well. | |
884 | * | |
885 | * This races with i915_driver_irq_handler() with the result | |
886 | * that either function could miss a vblank event. Here it is not | |
887 | * fatal, as we will either wait upon the next vblank interrupt or | |
888 | * timeout. Generally speaking intel_wait_for_vblank() is only | |
889 | * called during modeset at which time the GPU should be idle and | |
890 | * should *not* be performing page flips and thus not waiting on | |
891 | * vblanks... | |
892 | * Currently, the result of us stealing a vblank from the irq | |
893 | * handler is that a single frame will be skipped during swapbuffers. | |
894 | */ | |
895 | I915_WRITE(pipestat_reg, | |
896 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); | |
897 | ||
9d0498a2 | 898 | /* Wait for vblank interrupt bit to set */ |
481b6af3 CW |
899 | if (wait_for(I915_READ(pipestat_reg) & |
900 | PIPE_VBLANK_INTERRUPT_STATUS, | |
901 | 50)) | |
9d0498a2 JB |
902 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
903 | } | |
904 | ||
fbf49ea2 VS |
905 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
906 | { | |
907 | struct drm_i915_private *dev_priv = dev->dev_private; | |
908 | u32 reg = PIPEDSL(pipe); | |
909 | u32 line1, line2; | |
910 | u32 line_mask; | |
911 | ||
912 | if (IS_GEN2(dev)) | |
913 | line_mask = DSL_LINEMASK_GEN2; | |
914 | else | |
915 | line_mask = DSL_LINEMASK_GEN3; | |
916 | ||
917 | line1 = I915_READ(reg) & line_mask; | |
918 | mdelay(5); | |
919 | line2 = I915_READ(reg) & line_mask; | |
920 | ||
921 | return line1 == line2; | |
922 | } | |
923 | ||
ab7ad7f6 KP |
924 | /* |
925 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
9d0498a2 JB |
926 | * @dev: drm device |
927 | * @pipe: pipe to wait for | |
928 | * | |
929 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
930 | * spinning on the vblank interrupt status bit, since we won't actually | |
931 | * see an interrupt when the pipe is disabled. | |
932 | * | |
ab7ad7f6 KP |
933 | * On Gen4 and above: |
934 | * wait for the pipe register state bit to turn off | |
935 | * | |
936 | * Otherwise: | |
937 | * wait for the display line value to settle (it usually | |
938 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 939 | * |
9d0498a2 | 940 | */ |
58e10eb9 | 941 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
9d0498a2 JB |
942 | { |
943 | struct drm_i915_private *dev_priv = dev->dev_private; | |
702e7a56 PZ |
944 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
945 | pipe); | |
ab7ad7f6 KP |
946 | |
947 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 948 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
949 | |
950 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
951 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
952 | 100)) | |
284637d9 | 953 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 954 | } else { |
ab7ad7f6 | 955 | /* Wait for the display line to settle */ |
fbf49ea2 | 956 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 957 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 958 | } |
79e53945 JB |
959 | } |
960 | ||
b0ea7d37 DL |
961 | /* |
962 | * ibx_digital_port_connected - is the specified port connected? | |
963 | * @dev_priv: i915 private structure | |
964 | * @port: the port to test | |
965 | * | |
966 | * Returns true if @port is connected, false otherwise. | |
967 | */ | |
968 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, | |
969 | struct intel_digital_port *port) | |
970 | { | |
971 | u32 bit; | |
972 | ||
c36346e3 | 973 | if (HAS_PCH_IBX(dev_priv->dev)) { |
eba905b2 | 974 | switch (port->port) { |
c36346e3 DL |
975 | case PORT_B: |
976 | bit = SDE_PORTB_HOTPLUG; | |
977 | break; | |
978 | case PORT_C: | |
979 | bit = SDE_PORTC_HOTPLUG; | |
980 | break; | |
981 | case PORT_D: | |
982 | bit = SDE_PORTD_HOTPLUG; | |
983 | break; | |
984 | default: | |
985 | return true; | |
986 | } | |
987 | } else { | |
eba905b2 | 988 | switch (port->port) { |
c36346e3 DL |
989 | case PORT_B: |
990 | bit = SDE_PORTB_HOTPLUG_CPT; | |
991 | break; | |
992 | case PORT_C: | |
993 | bit = SDE_PORTC_HOTPLUG_CPT; | |
994 | break; | |
995 | case PORT_D: | |
996 | bit = SDE_PORTD_HOTPLUG_CPT; | |
997 | break; | |
998 | default: | |
999 | return true; | |
1000 | } | |
b0ea7d37 DL |
1001 | } |
1002 | ||
1003 | return I915_READ(SDEISR) & bit; | |
1004 | } | |
1005 | ||
b24e7179 JB |
1006 | static const char *state_string(bool enabled) |
1007 | { | |
1008 | return enabled ? "on" : "off"; | |
1009 | } | |
1010 | ||
1011 | /* Only for pre-ILK configs */ | |
55607e8a DV |
1012 | void assert_pll(struct drm_i915_private *dev_priv, |
1013 | enum pipe pipe, bool state) | |
b24e7179 JB |
1014 | { |
1015 | int reg; | |
1016 | u32 val; | |
1017 | bool cur_state; | |
1018 | ||
1019 | reg = DPLL(pipe); | |
1020 | val = I915_READ(reg); | |
1021 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
1022 | WARN(cur_state != state, | |
1023 | "PLL state assertion failure (expected %s, current %s)\n", | |
1024 | state_string(state), state_string(cur_state)); | |
1025 | } | |
b24e7179 | 1026 | |
23538ef1 JN |
1027 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
1028 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
1029 | { | |
1030 | u32 val; | |
1031 | bool cur_state; | |
1032 | ||
1033 | mutex_lock(&dev_priv->dpio_lock); | |
1034 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); | |
1035 | mutex_unlock(&dev_priv->dpio_lock); | |
1036 | ||
1037 | cur_state = val & DSI_PLL_VCO_EN; | |
1038 | WARN(cur_state != state, | |
1039 | "DSI PLL state assertion failure (expected %s, current %s)\n", | |
1040 | state_string(state), state_string(cur_state)); | |
1041 | } | |
1042 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1043 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
1044 | ||
55607e8a | 1045 | struct intel_shared_dpll * |
e2b78267 DV |
1046 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
1047 | { | |
1048 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1049 | ||
a43f6e0f | 1050 | if (crtc->config.shared_dpll < 0) |
e2b78267 DV |
1051 | return NULL; |
1052 | ||
a43f6e0f | 1053 | return &dev_priv->shared_dplls[crtc->config.shared_dpll]; |
e2b78267 DV |
1054 | } |
1055 | ||
040484af | 1056 | /* For ILK+ */ |
55607e8a DV |
1057 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1058 | struct intel_shared_dpll *pll, | |
1059 | bool state) | |
040484af | 1060 | { |
040484af | 1061 | bool cur_state; |
5358901f | 1062 | struct intel_dpll_hw_state hw_state; |
040484af | 1063 | |
9d82aa17 ED |
1064 | if (HAS_PCH_LPT(dev_priv->dev)) { |
1065 | DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n"); | |
1066 | return; | |
1067 | } | |
1068 | ||
92b27b08 | 1069 | if (WARN (!pll, |
46edb027 | 1070 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 1071 | return; |
ee7b9f93 | 1072 | |
5358901f | 1073 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
92b27b08 | 1074 | WARN(cur_state != state, |
5358901f DV |
1075 | "%s assertion failure (expected %s, current %s)\n", |
1076 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 1077 | } |
040484af JB |
1078 | |
1079 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1080 | enum pipe pipe, bool state) | |
1081 | { | |
1082 | int reg; | |
1083 | u32 val; | |
1084 | bool cur_state; | |
ad80a810 PZ |
1085 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1086 | pipe); | |
040484af | 1087 | |
affa9354 PZ |
1088 | if (HAS_DDI(dev_priv->dev)) { |
1089 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 1090 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 1091 | val = I915_READ(reg); |
ad80a810 | 1092 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
1093 | } else { |
1094 | reg = FDI_TX_CTL(pipe); | |
1095 | val = I915_READ(reg); | |
1096 | cur_state = !!(val & FDI_TX_ENABLE); | |
1097 | } | |
040484af JB |
1098 | WARN(cur_state != state, |
1099 | "FDI TX state assertion failure (expected %s, current %s)\n", | |
1100 | state_string(state), state_string(cur_state)); | |
1101 | } | |
1102 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1103 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1104 | ||
1105 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1106 | enum pipe pipe, bool state) | |
1107 | { | |
1108 | int reg; | |
1109 | u32 val; | |
1110 | bool cur_state; | |
1111 | ||
d63fa0dc PZ |
1112 | reg = FDI_RX_CTL(pipe); |
1113 | val = I915_READ(reg); | |
1114 | cur_state = !!(val & FDI_RX_ENABLE); | |
040484af JB |
1115 | WARN(cur_state != state, |
1116 | "FDI RX state assertion failure (expected %s, current %s)\n", | |
1117 | state_string(state), state_string(cur_state)); | |
1118 | } | |
1119 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1120 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1121 | ||
1122 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1123 | enum pipe pipe) | |
1124 | { | |
1125 | int reg; | |
1126 | u32 val; | |
1127 | ||
1128 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1129 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1130 | return; |
1131 | ||
bf507ef7 | 1132 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1133 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1134 | return; |
1135 | ||
040484af JB |
1136 | reg = FDI_TX_CTL(pipe); |
1137 | val = I915_READ(reg); | |
1138 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); | |
1139 | } | |
1140 | ||
55607e8a DV |
1141 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1142 | enum pipe pipe, bool state) | |
040484af JB |
1143 | { |
1144 | int reg; | |
1145 | u32 val; | |
55607e8a | 1146 | bool cur_state; |
040484af JB |
1147 | |
1148 | reg = FDI_RX_CTL(pipe); | |
1149 | val = I915_READ(reg); | |
55607e8a DV |
1150 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
1151 | WARN(cur_state != state, | |
1152 | "FDI RX PLL assertion failure (expected %s, current %s)\n", | |
1153 | state_string(state), state_string(cur_state)); | |
040484af JB |
1154 | } |
1155 | ||
ea0760cf JB |
1156 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1157 | enum pipe pipe) | |
1158 | { | |
1159 | int pp_reg, lvds_reg; | |
1160 | u32 val; | |
1161 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1162 | bool locked = true; |
ea0760cf JB |
1163 | |
1164 | if (HAS_PCH_SPLIT(dev_priv->dev)) { | |
1165 | pp_reg = PCH_PP_CONTROL; | |
1166 | lvds_reg = PCH_LVDS; | |
1167 | } else { | |
1168 | pp_reg = PP_CONTROL; | |
1169 | lvds_reg = LVDS; | |
1170 | } | |
1171 | ||
1172 | val = I915_READ(pp_reg); | |
1173 | if (!(val & PANEL_POWER_ON) || | |
1174 | ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) | |
1175 | locked = false; | |
1176 | ||
1177 | if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) | |
1178 | panel_pipe = PIPE_B; | |
1179 | ||
1180 | WARN(panel_pipe == pipe && locked, | |
1181 | "panel assertion failure, pipe %c regs locked\n", | |
9db4a9c7 | 1182 | pipe_name(pipe)); |
ea0760cf JB |
1183 | } |
1184 | ||
93ce0ba6 JN |
1185 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1186 | enum pipe pipe, bool state) | |
1187 | { | |
1188 | struct drm_device *dev = dev_priv->dev; | |
1189 | bool cur_state; | |
1190 | ||
d9d82081 | 1191 | if (IS_845G(dev) || IS_I865G(dev)) |
93ce0ba6 | 1192 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; |
d9d82081 | 1193 | else |
5efb3e28 | 1194 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 JN |
1195 | |
1196 | WARN(cur_state != state, | |
1197 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", | |
1198 | pipe_name(pipe), state_string(state), state_string(cur_state)); | |
1199 | } | |
1200 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1201 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1202 | ||
b840d907 JB |
1203 | void assert_pipe(struct drm_i915_private *dev_priv, |
1204 | enum pipe pipe, bool state) | |
b24e7179 JB |
1205 | { |
1206 | int reg; | |
1207 | u32 val; | |
63d7bbe9 | 1208 | bool cur_state; |
702e7a56 PZ |
1209 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1210 | pipe); | |
b24e7179 | 1211 | |
8e636784 DV |
1212 | /* if we need the pipe A quirk it must be always on */ |
1213 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
1214 | state = true; | |
1215 | ||
da7e29bd | 1216 | if (!intel_display_power_enabled(dev_priv, |
b97186f0 | 1217 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
69310161 PZ |
1218 | cur_state = false; |
1219 | } else { | |
1220 | reg = PIPECONF(cpu_transcoder); | |
1221 | val = I915_READ(reg); | |
1222 | cur_state = !!(val & PIPECONF_ENABLE); | |
1223 | } | |
1224 | ||
63d7bbe9 JB |
1225 | WARN(cur_state != state, |
1226 | "pipe %c assertion failure (expected %s, current %s)\n", | |
9db4a9c7 | 1227 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1228 | } |
1229 | ||
931872fc CW |
1230 | static void assert_plane(struct drm_i915_private *dev_priv, |
1231 | enum plane plane, bool state) | |
b24e7179 JB |
1232 | { |
1233 | int reg; | |
1234 | u32 val; | |
931872fc | 1235 | bool cur_state; |
b24e7179 JB |
1236 | |
1237 | reg = DSPCNTR(plane); | |
1238 | val = I915_READ(reg); | |
931872fc CW |
1239 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
1240 | WARN(cur_state != state, | |
1241 | "plane %c assertion failure (expected %s, current %s)\n", | |
1242 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1243 | } |
1244 | ||
931872fc CW |
1245 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1246 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1247 | ||
b24e7179 JB |
1248 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1249 | enum pipe pipe) | |
1250 | { | |
653e1026 | 1251 | struct drm_device *dev = dev_priv->dev; |
b24e7179 JB |
1252 | int reg, i; |
1253 | u32 val; | |
1254 | int cur_pipe; | |
1255 | ||
653e1026 VS |
1256 | /* Primary planes are fixed to pipes on gen4+ */ |
1257 | if (INTEL_INFO(dev)->gen >= 4) { | |
28c05794 AJ |
1258 | reg = DSPCNTR(pipe); |
1259 | val = I915_READ(reg); | |
83f26f16 | 1260 | WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1261 | "plane %c assertion failure, should be disabled but not\n", |
1262 | plane_name(pipe)); | |
19ec1358 | 1263 | return; |
28c05794 | 1264 | } |
19ec1358 | 1265 | |
b24e7179 | 1266 | /* Need to check both planes against the pipe */ |
08e2a7de | 1267 | for_each_pipe(i) { |
b24e7179 JB |
1268 | reg = DSPCNTR(i); |
1269 | val = I915_READ(reg); | |
1270 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1271 | DISPPLANE_SEL_PIPE_SHIFT; | |
1272 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, | |
9db4a9c7 JB |
1273 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1274 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1275 | } |
1276 | } | |
1277 | ||
19332d7a JB |
1278 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1279 | enum pipe pipe) | |
1280 | { | |
20674eef | 1281 | struct drm_device *dev = dev_priv->dev; |
1fe47785 | 1282 | int reg, sprite; |
19332d7a JB |
1283 | u32 val; |
1284 | ||
20674eef | 1285 | if (IS_VALLEYVIEW(dev)) { |
1fe47785 DL |
1286 | for_each_sprite(pipe, sprite) { |
1287 | reg = SPCNTR(pipe, sprite); | |
20674eef | 1288 | val = I915_READ(reg); |
83f26f16 | 1289 | WARN(val & SP_ENABLE, |
20674eef | 1290 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1291 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1292 | } |
1293 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
1294 | reg = SPRCTL(pipe); | |
19332d7a | 1295 | val = I915_READ(reg); |
83f26f16 | 1296 | WARN(val & SPRITE_ENABLE, |
06da8da2 | 1297 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1298 | plane_name(pipe), pipe_name(pipe)); |
1299 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
1300 | reg = DVSCNTR(pipe); | |
19332d7a | 1301 | val = I915_READ(reg); |
83f26f16 | 1302 | WARN(val & DVS_ENABLE, |
06da8da2 | 1303 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1304 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1305 | } |
1306 | } | |
1307 | ||
89eff4be | 1308 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1309 | { |
1310 | u32 val; | |
1311 | bool enabled; | |
1312 | ||
89eff4be | 1313 | WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1314 | |
92f2584a JB |
1315 | val = I915_READ(PCH_DREF_CONTROL); |
1316 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1317 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
1318 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); | |
1319 | } | |
1320 | ||
ab9412ba DV |
1321 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1322 | enum pipe pipe) | |
92f2584a JB |
1323 | { |
1324 | int reg; | |
1325 | u32 val; | |
1326 | bool enabled; | |
1327 | ||
ab9412ba | 1328 | reg = PCH_TRANSCONF(pipe); |
92f2584a JB |
1329 | val = I915_READ(reg); |
1330 | enabled = !!(val & TRANS_ENABLE); | |
9db4a9c7 JB |
1331 | WARN(enabled, |
1332 | "transcoder assertion failed, should be off on pipe %c but is still active\n", | |
1333 | pipe_name(pipe)); | |
92f2584a JB |
1334 | } |
1335 | ||
4e634389 KP |
1336 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1337 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1338 | { |
1339 | if ((val & DP_PORT_EN) == 0) | |
1340 | return false; | |
1341 | ||
1342 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1343 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1344 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1345 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1346 | return false; | |
44f37d1f CML |
1347 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1348 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1349 | return false; | |
f0575e92 KP |
1350 | } else { |
1351 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1352 | return false; | |
1353 | } | |
1354 | return true; | |
1355 | } | |
1356 | ||
1519b995 KP |
1357 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1358 | enum pipe pipe, u32 val) | |
1359 | { | |
dc0fa718 | 1360 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1361 | return false; |
1362 | ||
1363 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1364 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1365 | return false; |
44f37d1f CML |
1366 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1367 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1368 | return false; | |
1519b995 | 1369 | } else { |
dc0fa718 | 1370 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1371 | return false; |
1372 | } | |
1373 | return true; | |
1374 | } | |
1375 | ||
1376 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1377 | enum pipe pipe, u32 val) | |
1378 | { | |
1379 | if ((val & LVDS_PORT_EN) == 0) | |
1380 | return false; | |
1381 | ||
1382 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1383 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1384 | return false; | |
1385 | } else { | |
1386 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1387 | return false; | |
1388 | } | |
1389 | return true; | |
1390 | } | |
1391 | ||
1392 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1393 | enum pipe pipe, u32 val) | |
1394 | { | |
1395 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1396 | return false; | |
1397 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1398 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1399 | return false; | |
1400 | } else { | |
1401 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1402 | return false; | |
1403 | } | |
1404 | return true; | |
1405 | } | |
1406 | ||
291906f1 | 1407 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1408 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1409 | { |
47a05eca | 1410 | u32 val = I915_READ(reg); |
4e634389 | 1411 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1412 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1413 | reg, pipe_name(pipe)); |
de9a35ab | 1414 | |
75c5da27 DV |
1415 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
1416 | && (val & DP_PIPEB_SELECT), | |
de9a35ab | 1417 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1418 | } |
1419 | ||
1420 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1421 | enum pipe pipe, int reg) | |
1422 | { | |
47a05eca | 1423 | u32 val = I915_READ(reg); |
b70ad586 | 1424 | WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1425 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1426 | reg, pipe_name(pipe)); |
de9a35ab | 1427 | |
dc0fa718 | 1428 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1429 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1430 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1431 | } |
1432 | ||
1433 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1434 | enum pipe pipe) | |
1435 | { | |
1436 | int reg; | |
1437 | u32 val; | |
291906f1 | 1438 | |
f0575e92 KP |
1439 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1440 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1441 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1442 | |
1443 | reg = PCH_ADPA; | |
1444 | val = I915_READ(reg); | |
b70ad586 | 1445 | WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1446 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1447 | pipe_name(pipe)); |
291906f1 JB |
1448 | |
1449 | reg = PCH_LVDS; | |
1450 | val = I915_READ(reg); | |
b70ad586 | 1451 | WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1452 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1453 | pipe_name(pipe)); |
291906f1 | 1454 | |
e2debe91 PZ |
1455 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1456 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1457 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1458 | } |
1459 | ||
40e9cf64 JB |
1460 | static void intel_init_dpio(struct drm_device *dev) |
1461 | { | |
1462 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1463 | ||
1464 | if (!IS_VALLEYVIEW(dev)) | |
1465 | return; | |
1466 | ||
a09caddd CML |
1467 | /* |
1468 | * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C), | |
1469 | * CHV x1 PHY (DP/HDMI D) | |
1470 | * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C) | |
1471 | */ | |
1472 | if (IS_CHERRYVIEW(dev)) { | |
1473 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2; | |
1474 | DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO; | |
1475 | } else { | |
1476 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; | |
1477 | } | |
5382f5f3 JB |
1478 | } |
1479 | ||
1480 | static void intel_reset_dpio(struct drm_device *dev) | |
1481 | { | |
1482 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1483 | ||
1484 | if (!IS_VALLEYVIEW(dev)) | |
1485 | return; | |
1486 | ||
e5cbfbfb ID |
1487 | /* |
1488 | * Enable the CRI clock source so we can get at the display and the | |
1489 | * reference clock for VGA hotplug / manual detection. | |
1490 | */ | |
404faabc | 1491 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | |
e5cbfbfb | 1492 | DPLL_REFA_CLK_ENABLE_VLV | |
404faabc ID |
1493 | DPLL_INTEGRATED_CRI_CLK_VLV); |
1494 | ||
076ed3b2 CML |
1495 | if (IS_CHERRYVIEW(dev)) { |
1496 | enum dpio_phy phy; | |
1497 | u32 val; | |
1498 | ||
1499 | for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) { | |
1500 | /* Poll for phypwrgood signal */ | |
1501 | if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & | |
1502 | PHY_POWERGOOD(phy), 1)) | |
1503 | DRM_ERROR("Display PHY %d is not power up\n", phy); | |
1504 | ||
1505 | /* | |
1506 | * Deassert common lane reset for PHY. | |
1507 | * | |
1508 | * This should only be done on init and resume from S3 | |
1509 | * with both PLLs disabled, or we risk losing DPIO and | |
1510 | * PLL synchronization. | |
1511 | */ | |
1512 | val = I915_READ(DISPLAY_PHY_CONTROL); | |
1513 | I915_WRITE(DISPLAY_PHY_CONTROL, | |
1514 | PHY_COM_LANE_RESET_DEASSERT(phy, val)); | |
1515 | } | |
1516 | ||
1517 | } else { | |
1518 | /* | |
1519 | * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - | |
1520 | * 6. De-assert cmn_reset/side_reset. Same as VLV X0. | |
1521 | * a. GUnit 0x2110 bit[0] set to 1 (def 0) | |
1522 | * b. The other bits such as sfr settings / modesel may all | |
1523 | * be set to 0. | |
1524 | * | |
1525 | * This should only be done on init and resume from S3 with | |
1526 | * both PLLs disabled, or we risk losing DPIO and PLL | |
1527 | * synchronization. | |
1528 | */ | |
1529 | I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); | |
1530 | } | |
40e9cf64 JB |
1531 | } |
1532 | ||
426115cf | 1533 | static void vlv_enable_pll(struct intel_crtc *crtc) |
87442f73 | 1534 | { |
426115cf DV |
1535 | struct drm_device *dev = crtc->base.dev; |
1536 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1537 | int reg = DPLL(crtc->pipe); | |
1538 | u32 dpll = crtc->config.dpll_hw_state.dpll; | |
87442f73 | 1539 | |
426115cf | 1540 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 DV |
1541 | |
1542 | /* No really, not for ILK+ */ | |
1543 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); | |
1544 | ||
1545 | /* PLL is protected by panel, make sure we can write it */ | |
1546 | if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) | |
426115cf | 1547 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1548 | |
426115cf DV |
1549 | I915_WRITE(reg, dpll); |
1550 | POSTING_READ(reg); | |
1551 | udelay(150); | |
1552 | ||
1553 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1554 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1555 | ||
1556 | I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md); | |
1557 | POSTING_READ(DPLL_MD(crtc->pipe)); | |
87442f73 DV |
1558 | |
1559 | /* We do this three times for luck */ | |
426115cf | 1560 | I915_WRITE(reg, dpll); |
87442f73 DV |
1561 | POSTING_READ(reg); |
1562 | udelay(150); /* wait for warmup */ | |
426115cf | 1563 | I915_WRITE(reg, dpll); |
87442f73 DV |
1564 | POSTING_READ(reg); |
1565 | udelay(150); /* wait for warmup */ | |
426115cf | 1566 | I915_WRITE(reg, dpll); |
87442f73 DV |
1567 | POSTING_READ(reg); |
1568 | udelay(150); /* wait for warmup */ | |
1569 | } | |
1570 | ||
9d556c99 CML |
1571 | static void chv_enable_pll(struct intel_crtc *crtc) |
1572 | { | |
1573 | struct drm_device *dev = crtc->base.dev; | |
1574 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1575 | int pipe = crtc->pipe; | |
1576 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9d556c99 CML |
1577 | u32 tmp; |
1578 | ||
1579 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1580 | ||
1581 | BUG_ON(!IS_CHERRYVIEW(dev_priv->dev)); | |
1582 | ||
1583 | mutex_lock(&dev_priv->dpio_lock); | |
1584 | ||
1585 | /* Enable back the 10bit clock to display controller */ | |
1586 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1587 | tmp |= DPIO_DCLKP_EN; | |
1588 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1589 | ||
1590 | /* | |
1591 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1592 | */ | |
1593 | udelay(1); | |
1594 | ||
1595 | /* Enable PLL */ | |
a11b0703 | 1596 | I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll); |
9d556c99 CML |
1597 | |
1598 | /* Check PLL is locked */ | |
a11b0703 | 1599 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1600 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1601 | ||
a11b0703 VS |
1602 | /* not sure when this should be written */ |
1603 | I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md); | |
1604 | POSTING_READ(DPLL_MD(pipe)); | |
1605 | ||
9d556c99 CML |
1606 | mutex_unlock(&dev_priv->dpio_lock); |
1607 | } | |
1608 | ||
66e3d5c0 | 1609 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1610 | { |
66e3d5c0 DV |
1611 | struct drm_device *dev = crtc->base.dev; |
1612 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1613 | int reg = DPLL(crtc->pipe); | |
1614 | u32 dpll = crtc->config.dpll_hw_state.dpll; | |
63d7bbe9 | 1615 | |
66e3d5c0 | 1616 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1617 | |
63d7bbe9 | 1618 | /* No really, not for ILK+ */ |
3d13ef2e | 1619 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1620 | |
1621 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1622 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1623 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1624 | |
66e3d5c0 DV |
1625 | I915_WRITE(reg, dpll); |
1626 | ||
1627 | /* Wait for the clocks to stabilize. */ | |
1628 | POSTING_READ(reg); | |
1629 | udelay(150); | |
1630 | ||
1631 | if (INTEL_INFO(dev)->gen >= 4) { | |
1632 | I915_WRITE(DPLL_MD(crtc->pipe), | |
1633 | crtc->config.dpll_hw_state.dpll_md); | |
1634 | } else { | |
1635 | /* The pixel multiplier can only be updated once the | |
1636 | * DPLL is enabled and the clocks are stable. | |
1637 | * | |
1638 | * So write it again. | |
1639 | */ | |
1640 | I915_WRITE(reg, dpll); | |
1641 | } | |
63d7bbe9 JB |
1642 | |
1643 | /* We do this three times for luck */ | |
66e3d5c0 | 1644 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1645 | POSTING_READ(reg); |
1646 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1647 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1648 | POSTING_READ(reg); |
1649 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1650 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1651 | POSTING_READ(reg); |
1652 | udelay(150); /* wait for warmup */ | |
1653 | } | |
1654 | ||
1655 | /** | |
50b44a44 | 1656 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1657 | * @dev_priv: i915 private structure |
1658 | * @pipe: pipe PLL to disable | |
1659 | * | |
1660 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1661 | * | |
1662 | * Note! This is for pre-ILK only. | |
1663 | */ | |
50b44a44 | 1664 | static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
63d7bbe9 | 1665 | { |
63d7bbe9 JB |
1666 | /* Don't disable pipe A or pipe A PLLs if needed */ |
1667 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1668 | return; | |
1669 | ||
1670 | /* Make sure the pipe isn't still relying on us */ | |
1671 | assert_pipe_disabled(dev_priv, pipe); | |
1672 | ||
50b44a44 DV |
1673 | I915_WRITE(DPLL(pipe), 0); |
1674 | POSTING_READ(DPLL(pipe)); | |
63d7bbe9 JB |
1675 | } |
1676 | ||
f6071166 JB |
1677 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1678 | { | |
1679 | u32 val = 0; | |
1680 | ||
1681 | /* Make sure the pipe isn't still relying on us */ | |
1682 | assert_pipe_disabled(dev_priv, pipe); | |
1683 | ||
e5cbfbfb ID |
1684 | /* |
1685 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1686 | * The latter is needed for VGA hotplug / manual detection. | |
1687 | */ | |
f6071166 | 1688 | if (pipe == PIPE_B) |
e5cbfbfb | 1689 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV; |
f6071166 JB |
1690 | I915_WRITE(DPLL(pipe), val); |
1691 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1692 | |
1693 | } | |
1694 | ||
1695 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1696 | { | |
d752048d | 1697 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1698 | u32 val; |
1699 | ||
a11b0703 VS |
1700 | /* Make sure the pipe isn't still relying on us */ |
1701 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1702 | |
a11b0703 VS |
1703 | /* Set PLL en = 0 */ |
1704 | val = DPLL_SSC_REF_CLOCK_CHV; | |
1705 | if (pipe != PIPE_A) | |
1706 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1707 | I915_WRITE(DPLL(pipe), val); | |
1708 | POSTING_READ(DPLL(pipe)); | |
d752048d VS |
1709 | |
1710 | mutex_lock(&dev_priv->dpio_lock); | |
1711 | ||
1712 | /* Disable 10bit clock to display controller */ | |
1713 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1714 | val &= ~DPIO_DCLKP_EN; | |
1715 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1716 | ||
1717 | mutex_unlock(&dev_priv->dpio_lock); | |
f6071166 JB |
1718 | } |
1719 | ||
e4607fcf CML |
1720 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
1721 | struct intel_digital_port *dport) | |
89b667f8 JB |
1722 | { |
1723 | u32 port_mask; | |
00fc31b7 | 1724 | int dpll_reg; |
89b667f8 | 1725 | |
e4607fcf CML |
1726 | switch (dport->port) { |
1727 | case PORT_B: | |
89b667f8 | 1728 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1729 | dpll_reg = DPLL(0); |
e4607fcf CML |
1730 | break; |
1731 | case PORT_C: | |
89b667f8 | 1732 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 CML |
1733 | dpll_reg = DPLL(0); |
1734 | break; | |
1735 | case PORT_D: | |
1736 | port_mask = DPLL_PORTD_READY_MASK; | |
1737 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1738 | break; |
1739 | default: | |
1740 | BUG(); | |
1741 | } | |
89b667f8 | 1742 | |
00fc31b7 | 1743 | if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000)) |
89b667f8 | 1744 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", |
00fc31b7 | 1745 | port_name(dport->port), I915_READ(dpll_reg)); |
89b667f8 JB |
1746 | } |
1747 | ||
b14b1055 DV |
1748 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
1749 | { | |
1750 | struct drm_device *dev = crtc->base.dev; | |
1751 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1752 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
1753 | ||
1754 | WARN_ON(!pll->refcount); | |
1755 | if (pll->active == 0) { | |
1756 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); | |
1757 | WARN_ON(pll->on); | |
1758 | assert_shared_dpll_disabled(dev_priv, pll); | |
1759 | ||
1760 | pll->mode_set(dev_priv, pll); | |
1761 | } | |
1762 | } | |
1763 | ||
92f2584a | 1764 | /** |
85b3894f | 1765 | * intel_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1766 | * @dev_priv: i915 private structure |
1767 | * @pipe: pipe PLL to enable | |
1768 | * | |
1769 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1770 | * drives the transcoder clock. | |
1771 | */ | |
85b3894f | 1772 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1773 | { |
3d13ef2e DL |
1774 | struct drm_device *dev = crtc->base.dev; |
1775 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1776 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1777 | |
87a875bb | 1778 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1779 | return; |
1780 | ||
1781 | if (WARN_ON(pll->refcount == 0)) | |
1782 | return; | |
ee7b9f93 | 1783 | |
46edb027 DV |
1784 | DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n", |
1785 | pll->name, pll->active, pll->on, | |
e2b78267 | 1786 | crtc->base.base.id); |
92f2584a | 1787 | |
cdbd2316 DV |
1788 | if (pll->active++) { |
1789 | WARN_ON(!pll->on); | |
e9d6944e | 1790 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1791 | return; |
1792 | } | |
f4a091c7 | 1793 | WARN_ON(pll->on); |
ee7b9f93 | 1794 | |
46edb027 | 1795 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1796 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1797 | pll->on = true; |
92f2584a JB |
1798 | } |
1799 | ||
e2b78267 | 1800 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1801 | { |
3d13ef2e DL |
1802 | struct drm_device *dev = crtc->base.dev; |
1803 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1804 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1805 | |
92f2584a | 1806 | /* PCH only available on ILK+ */ |
3d13ef2e | 1807 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
87a875bb | 1808 | if (WARN_ON(pll == NULL)) |
ee7b9f93 | 1809 | return; |
92f2584a | 1810 | |
48da64a8 CW |
1811 | if (WARN_ON(pll->refcount == 0)) |
1812 | return; | |
7a419866 | 1813 | |
46edb027 DV |
1814 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1815 | pll->name, pll->active, pll->on, | |
e2b78267 | 1816 | crtc->base.base.id); |
7a419866 | 1817 | |
48da64a8 | 1818 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1819 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1820 | return; |
1821 | } | |
1822 | ||
e9d6944e | 1823 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1824 | WARN_ON(!pll->on); |
cdbd2316 | 1825 | if (--pll->active) |
7a419866 | 1826 | return; |
ee7b9f93 | 1827 | |
46edb027 | 1828 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1829 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1830 | pll->on = false; |
92f2584a JB |
1831 | } |
1832 | ||
b8a4f404 PZ |
1833 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1834 | enum pipe pipe) | |
040484af | 1835 | { |
23670b32 | 1836 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1837 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1838 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
23670b32 | 1839 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1840 | |
1841 | /* PCH only available on ILK+ */ | |
3d13ef2e | 1842 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
040484af JB |
1843 | |
1844 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1845 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1846 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1847 | |
1848 | /* FDI must be feeding us bits for PCH ports */ | |
1849 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1850 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1851 | ||
23670b32 DV |
1852 | if (HAS_PCH_CPT(dev)) { |
1853 | /* Workaround: Set the timing override bit before enabling the | |
1854 | * pch transcoder. */ | |
1855 | reg = TRANS_CHICKEN2(pipe); | |
1856 | val = I915_READ(reg); | |
1857 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1858 | I915_WRITE(reg, val); | |
59c859d6 | 1859 | } |
23670b32 | 1860 | |
ab9412ba | 1861 | reg = PCH_TRANSCONF(pipe); |
040484af | 1862 | val = I915_READ(reg); |
5f7f726d | 1863 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1864 | |
1865 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1866 | /* | |
1867 | * make the BPC in transcoder be consistent with | |
1868 | * that in pipeconf reg. | |
1869 | */ | |
dfd07d72 DV |
1870 | val &= ~PIPECONF_BPC_MASK; |
1871 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1872 | } |
5f7f726d PZ |
1873 | |
1874 | val &= ~TRANS_INTERLACE_MASK; | |
1875 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 PZ |
1876 | if (HAS_PCH_IBX(dev_priv->dev) && |
1877 | intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) | |
1878 | val |= TRANS_LEGACY_INTERLACED_ILK; | |
1879 | else | |
1880 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1881 | else |
1882 | val |= TRANS_PROGRESSIVE; | |
1883 | ||
040484af JB |
1884 | I915_WRITE(reg, val | TRANS_ENABLE); |
1885 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 1886 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1887 | } |
1888 | ||
8fb033d7 | 1889 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1890 | enum transcoder cpu_transcoder) |
040484af | 1891 | { |
8fb033d7 | 1892 | u32 val, pipeconf_val; |
8fb033d7 PZ |
1893 | |
1894 | /* PCH only available on ILK+ */ | |
3d13ef2e | 1895 | BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5); |
8fb033d7 | 1896 | |
8fb033d7 | 1897 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1898 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1899 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1900 | |
223a6fdf PZ |
1901 | /* Workaround: set timing override bit. */ |
1902 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1903 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf PZ |
1904 | I915_WRITE(_TRANSA_CHICKEN2, val); |
1905 | ||
25f3ef11 | 1906 | val = TRANS_ENABLE; |
937bb610 | 1907 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1908 | |
9a76b1c6 PZ |
1909 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1910 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1911 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1912 | else |
1913 | val |= TRANS_PROGRESSIVE; | |
1914 | ||
ab9412ba DV |
1915 | I915_WRITE(LPT_TRANSCONF, val); |
1916 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 1917 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1918 | } |
1919 | ||
b8a4f404 PZ |
1920 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1921 | enum pipe pipe) | |
040484af | 1922 | { |
23670b32 DV |
1923 | struct drm_device *dev = dev_priv->dev; |
1924 | uint32_t reg, val; | |
040484af JB |
1925 | |
1926 | /* FDI relies on the transcoder */ | |
1927 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1928 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1929 | ||
291906f1 JB |
1930 | /* Ports must be off as well */ |
1931 | assert_pch_ports_disabled(dev_priv, pipe); | |
1932 | ||
ab9412ba | 1933 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1934 | val = I915_READ(reg); |
1935 | val &= ~TRANS_ENABLE; | |
1936 | I915_WRITE(reg, val); | |
1937 | /* wait for PCH transcoder off, transcoder state */ | |
1938 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 1939 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 DV |
1940 | |
1941 | if (!HAS_PCH_IBX(dev)) { | |
1942 | /* Workaround: Clear the timing override chicken bit again. */ | |
1943 | reg = TRANS_CHICKEN2(pipe); | |
1944 | val = I915_READ(reg); | |
1945 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1946 | I915_WRITE(reg, val); | |
1947 | } | |
040484af JB |
1948 | } |
1949 | ||
ab4d966c | 1950 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1951 | { |
8fb033d7 PZ |
1952 | u32 val; |
1953 | ||
ab9412ba | 1954 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1955 | val &= ~TRANS_ENABLE; |
ab9412ba | 1956 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1957 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 1958 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 1959 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1960 | |
1961 | /* Workaround: clear timing override bit. */ | |
1962 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1963 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf | 1964 | I915_WRITE(_TRANSA_CHICKEN2, val); |
040484af JB |
1965 | } |
1966 | ||
b24e7179 | 1967 | /** |
309cfea8 | 1968 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 1969 | * @crtc: crtc responsible for the pipe |
b24e7179 | 1970 | * |
0372264a | 1971 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 1972 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 1973 | */ |
e1fdc473 | 1974 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1975 | { |
0372264a PZ |
1976 | struct drm_device *dev = crtc->base.dev; |
1977 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1978 | enum pipe pipe = crtc->pipe; | |
702e7a56 PZ |
1979 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1980 | pipe); | |
1a240d4d | 1981 | enum pipe pch_transcoder; |
b24e7179 JB |
1982 | int reg; |
1983 | u32 val; | |
1984 | ||
58c6eaa2 | 1985 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 1986 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
1987 | assert_sprites_disabled(dev_priv, pipe); |
1988 | ||
681e5811 | 1989 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
1990 | pch_transcoder = TRANSCODER_A; |
1991 | else | |
1992 | pch_transcoder = pipe; | |
1993 | ||
b24e7179 JB |
1994 | /* |
1995 | * A pipe without a PLL won't actually be able to drive bits from | |
1996 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1997 | * need the check. | |
1998 | */ | |
1999 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
fbf3218a | 2000 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
2001 | assert_dsi_pll_enabled(dev_priv); |
2002 | else | |
2003 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 2004 | else { |
30421c4f | 2005 | if (crtc->config.has_pch_encoder) { |
040484af | 2006 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 2007 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
2008 | assert_fdi_tx_pll_enabled(dev_priv, |
2009 | (enum pipe) cpu_transcoder); | |
040484af JB |
2010 | } |
2011 | /* FIXME: assert CPU port conditions for SNB+ */ | |
2012 | } | |
b24e7179 | 2013 | |
702e7a56 | 2014 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2015 | val = I915_READ(reg); |
7ad25d48 PZ |
2016 | if (val & PIPECONF_ENABLE) { |
2017 | WARN_ON(!(pipe == PIPE_A && | |
2018 | dev_priv->quirks & QUIRK_PIPEA_FORCE)); | |
00d70b15 | 2019 | return; |
7ad25d48 | 2020 | } |
00d70b15 CW |
2021 | |
2022 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2023 | POSTING_READ(reg); |
b24e7179 JB |
2024 | } |
2025 | ||
2026 | /** | |
309cfea8 | 2027 | * intel_disable_pipe - disable a pipe, asserting requirements |
b24e7179 JB |
2028 | * @dev_priv: i915 private structure |
2029 | * @pipe: pipe to disable | |
2030 | * | |
2031 | * Disable @pipe, making sure that various hardware specific requirements | |
2032 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. | |
2033 | * | |
2034 | * @pipe should be %PIPE_A or %PIPE_B. | |
2035 | * | |
2036 | * Will wait until the pipe has shut down before returning. | |
2037 | */ | |
2038 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, | |
2039 | enum pipe pipe) | |
2040 | { | |
702e7a56 PZ |
2041 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
2042 | pipe); | |
b24e7179 JB |
2043 | int reg; |
2044 | u32 val; | |
2045 | ||
2046 | /* | |
2047 | * Make sure planes won't keep trying to pump pixels to us, | |
2048 | * or we might hang the display. | |
2049 | */ | |
2050 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2051 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2052 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 JB |
2053 | |
2054 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
2055 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
2056 | return; | |
2057 | ||
702e7a56 | 2058 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2059 | val = I915_READ(reg); |
00d70b15 CW |
2060 | if ((val & PIPECONF_ENABLE) == 0) |
2061 | return; | |
2062 | ||
2063 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); | |
b24e7179 JB |
2064 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
2065 | } | |
2066 | ||
d74362c9 KP |
2067 | /* |
2068 | * Plane regs are double buffered, going from enabled->disabled needs a | |
2069 | * trigger in order to latch. The display address reg provides this. | |
2070 | */ | |
1dba99f4 VS |
2071 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
2072 | enum plane plane) | |
d74362c9 | 2073 | { |
3d13ef2e DL |
2074 | struct drm_device *dev = dev_priv->dev; |
2075 | u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); | |
1dba99f4 VS |
2076 | |
2077 | I915_WRITE(reg, I915_READ(reg)); | |
2078 | POSTING_READ(reg); | |
d74362c9 KP |
2079 | } |
2080 | ||
b24e7179 | 2081 | /** |
262ca2b0 | 2082 | * intel_enable_primary_hw_plane - enable the primary plane on a given pipe |
b24e7179 JB |
2083 | * @dev_priv: i915 private structure |
2084 | * @plane: plane to enable | |
2085 | * @pipe: pipe being fed | |
2086 | * | |
2087 | * Enable @plane on @pipe, making sure that @pipe is running first. | |
2088 | */ | |
262ca2b0 MR |
2089 | static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv, |
2090 | enum plane plane, enum pipe pipe) | |
b24e7179 | 2091 | { |
939c2fe8 VS |
2092 | struct intel_crtc *intel_crtc = |
2093 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
b24e7179 JB |
2094 | int reg; |
2095 | u32 val; | |
2096 | ||
2097 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
2098 | assert_pipe_enabled(dev_priv, pipe); | |
2099 | ||
98ec7739 VS |
2100 | if (intel_crtc->primary_enabled) |
2101 | return; | |
0037f71c | 2102 | |
4c445e0e | 2103 | intel_crtc->primary_enabled = true; |
939c2fe8 | 2104 | |
b24e7179 JB |
2105 | reg = DSPCNTR(plane); |
2106 | val = I915_READ(reg); | |
10efa932 | 2107 | WARN_ON(val & DISPLAY_PLANE_ENABLE); |
00d70b15 CW |
2108 | |
2109 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); | |
1dba99f4 | 2110 | intel_flush_primary_plane(dev_priv, plane); |
b24e7179 JB |
2111 | } |
2112 | ||
b24e7179 | 2113 | /** |
262ca2b0 | 2114 | * intel_disable_primary_hw_plane - disable the primary hardware plane |
b24e7179 JB |
2115 | * @dev_priv: i915 private structure |
2116 | * @plane: plane to disable | |
2117 | * @pipe: pipe consuming the data | |
2118 | * | |
2119 | * Disable @plane; should be an independent operation. | |
2120 | */ | |
262ca2b0 MR |
2121 | static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv, |
2122 | enum plane plane, enum pipe pipe) | |
b24e7179 | 2123 | { |
939c2fe8 VS |
2124 | struct intel_crtc *intel_crtc = |
2125 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
b24e7179 JB |
2126 | int reg; |
2127 | u32 val; | |
2128 | ||
98ec7739 VS |
2129 | if (!intel_crtc->primary_enabled) |
2130 | return; | |
0037f71c | 2131 | |
4c445e0e | 2132 | intel_crtc->primary_enabled = false; |
939c2fe8 | 2133 | |
b24e7179 JB |
2134 | reg = DSPCNTR(plane); |
2135 | val = I915_READ(reg); | |
10efa932 | 2136 | WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0); |
00d70b15 CW |
2137 | |
2138 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); | |
1dba99f4 | 2139 | intel_flush_primary_plane(dev_priv, plane); |
b24e7179 JB |
2140 | } |
2141 | ||
693db184 CW |
2142 | static bool need_vtd_wa(struct drm_device *dev) |
2143 | { | |
2144 | #ifdef CONFIG_INTEL_IOMMU | |
2145 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2146 | return true; | |
2147 | #endif | |
2148 | return false; | |
2149 | } | |
2150 | ||
a57ce0b2 JB |
2151 | static int intel_align_height(struct drm_device *dev, int height, bool tiled) |
2152 | { | |
2153 | int tile_height; | |
2154 | ||
2155 | tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1; | |
2156 | return ALIGN(height, tile_height); | |
2157 | } | |
2158 | ||
127bd2ac | 2159 | int |
48b956c5 | 2160 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
05394f39 | 2161 | struct drm_i915_gem_object *obj, |
a4872ba6 | 2162 | struct intel_engine_cs *pipelined) |
6b95a207 | 2163 | { |
ce453d81 | 2164 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
2165 | u32 alignment; |
2166 | int ret; | |
2167 | ||
05394f39 | 2168 | switch (obj->tiling_mode) { |
6b95a207 | 2169 | case I915_TILING_NONE: |
534843da CW |
2170 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
2171 | alignment = 128 * 1024; | |
a6c45cf0 | 2172 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
2173 | alignment = 4 * 1024; |
2174 | else | |
2175 | alignment = 64 * 1024; | |
6b95a207 KH |
2176 | break; |
2177 | case I915_TILING_X: | |
2178 | /* pin() will align the object as required by fence */ | |
2179 | alignment = 0; | |
2180 | break; | |
2181 | case I915_TILING_Y: | |
80075d49 | 2182 | WARN(1, "Y tiled bo slipped through, driver bug!\n"); |
6b95a207 KH |
2183 | return -EINVAL; |
2184 | default: | |
2185 | BUG(); | |
2186 | } | |
2187 | ||
693db184 CW |
2188 | /* Note that the w/a also requires 64 PTE of padding following the |
2189 | * bo. We currently fill all unused PTE with the shadow page and so | |
2190 | * we should always have valid PTE following the scanout preventing | |
2191 | * the VT-d warning. | |
2192 | */ | |
2193 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2194 | alignment = 256 * 1024; | |
2195 | ||
ce453d81 | 2196 | dev_priv->mm.interruptible = false; |
2da3b9b9 | 2197 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
48b956c5 | 2198 | if (ret) |
ce453d81 | 2199 | goto err_interruptible; |
6b95a207 KH |
2200 | |
2201 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2202 | * fence, whereas 965+ only requires a fence if using | |
2203 | * framebuffer compression. For simplicity, we always install | |
2204 | * a fence as the cost is not that onerous. | |
2205 | */ | |
06d98131 | 2206 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
2207 | if (ret) |
2208 | goto err_unpin; | |
1690e1eb | 2209 | |
9a5a53b3 | 2210 | i915_gem_object_pin_fence(obj); |
6b95a207 | 2211 | |
ce453d81 | 2212 | dev_priv->mm.interruptible = true; |
6b95a207 | 2213 | return 0; |
48b956c5 CW |
2214 | |
2215 | err_unpin: | |
cc98b413 | 2216 | i915_gem_object_unpin_from_display_plane(obj); |
ce453d81 CW |
2217 | err_interruptible: |
2218 | dev_priv->mm.interruptible = true; | |
48b956c5 | 2219 | return ret; |
6b95a207 KH |
2220 | } |
2221 | ||
1690e1eb CW |
2222 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
2223 | { | |
2224 | i915_gem_object_unpin_fence(obj); | |
cc98b413 | 2225 | i915_gem_object_unpin_from_display_plane(obj); |
1690e1eb CW |
2226 | } |
2227 | ||
c2c75131 DV |
2228 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2229 | * is assumed to be a power-of-two. */ | |
bc752862 CW |
2230 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
2231 | unsigned int tiling_mode, | |
2232 | unsigned int cpp, | |
2233 | unsigned int pitch) | |
c2c75131 | 2234 | { |
bc752862 CW |
2235 | if (tiling_mode != I915_TILING_NONE) { |
2236 | unsigned int tile_rows, tiles; | |
c2c75131 | 2237 | |
bc752862 CW |
2238 | tile_rows = *y / 8; |
2239 | *y %= 8; | |
c2c75131 | 2240 | |
bc752862 CW |
2241 | tiles = *x / (512/cpp); |
2242 | *x %= 512/cpp; | |
2243 | ||
2244 | return tile_rows * pitch * 8 + tiles * 4096; | |
2245 | } else { | |
2246 | unsigned int offset; | |
2247 | ||
2248 | offset = *y * pitch + *x * cpp; | |
2249 | *y = 0; | |
2250 | *x = (offset & 4095) / cpp; | |
2251 | return offset & -4096; | |
2252 | } | |
c2c75131 DV |
2253 | } |
2254 | ||
46f297fb JB |
2255 | int intel_format_to_fourcc(int format) |
2256 | { | |
2257 | switch (format) { | |
2258 | case DISPPLANE_8BPP: | |
2259 | return DRM_FORMAT_C8; | |
2260 | case DISPPLANE_BGRX555: | |
2261 | return DRM_FORMAT_XRGB1555; | |
2262 | case DISPPLANE_BGRX565: | |
2263 | return DRM_FORMAT_RGB565; | |
2264 | default: | |
2265 | case DISPPLANE_BGRX888: | |
2266 | return DRM_FORMAT_XRGB8888; | |
2267 | case DISPPLANE_RGBX888: | |
2268 | return DRM_FORMAT_XBGR8888; | |
2269 | case DISPPLANE_BGRX101010: | |
2270 | return DRM_FORMAT_XRGB2101010; | |
2271 | case DISPPLANE_RGBX101010: | |
2272 | return DRM_FORMAT_XBGR2101010; | |
2273 | } | |
2274 | } | |
2275 | ||
484b41dd | 2276 | static bool intel_alloc_plane_obj(struct intel_crtc *crtc, |
46f297fb JB |
2277 | struct intel_plane_config *plane_config) |
2278 | { | |
2279 | struct drm_device *dev = crtc->base.dev; | |
2280 | struct drm_i915_gem_object *obj = NULL; | |
2281 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2282 | u32 base = plane_config->base; | |
2283 | ||
ff2652ea CW |
2284 | if (plane_config->size == 0) |
2285 | return false; | |
2286 | ||
46f297fb JB |
2287 | obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base, |
2288 | plane_config->size); | |
2289 | if (!obj) | |
484b41dd | 2290 | return false; |
46f297fb JB |
2291 | |
2292 | if (plane_config->tiled) { | |
2293 | obj->tiling_mode = I915_TILING_X; | |
66e514c1 | 2294 | obj->stride = crtc->base.primary->fb->pitches[0]; |
46f297fb JB |
2295 | } |
2296 | ||
66e514c1 DA |
2297 | mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format; |
2298 | mode_cmd.width = crtc->base.primary->fb->width; | |
2299 | mode_cmd.height = crtc->base.primary->fb->height; | |
2300 | mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0]; | |
46f297fb JB |
2301 | |
2302 | mutex_lock(&dev->struct_mutex); | |
2303 | ||
66e514c1 | 2304 | if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb), |
484b41dd | 2305 | &mode_cmd, obj)) { |
46f297fb JB |
2306 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2307 | goto out_unref_obj; | |
2308 | } | |
2309 | ||
2310 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2311 | |
2312 | DRM_DEBUG_KMS("plane fb obj %p\n", obj); | |
2313 | return true; | |
46f297fb JB |
2314 | |
2315 | out_unref_obj: | |
2316 | drm_gem_object_unreference(&obj->base); | |
2317 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2318 | return false; |
2319 | } | |
2320 | ||
2321 | static void intel_find_plane_obj(struct intel_crtc *intel_crtc, | |
2322 | struct intel_plane_config *plane_config) | |
2323 | { | |
2324 | struct drm_device *dev = intel_crtc->base.dev; | |
2325 | struct drm_crtc *c; | |
2326 | struct intel_crtc *i; | |
2327 | struct intel_framebuffer *fb; | |
2328 | ||
66e514c1 | 2329 | if (!intel_crtc->base.primary->fb) |
484b41dd JB |
2330 | return; |
2331 | ||
2332 | if (intel_alloc_plane_obj(intel_crtc, plane_config)) | |
2333 | return; | |
2334 | ||
66e514c1 DA |
2335 | kfree(intel_crtc->base.primary->fb); |
2336 | intel_crtc->base.primary->fb = NULL; | |
484b41dd JB |
2337 | |
2338 | /* | |
2339 | * Failed to alloc the obj, check to see if we should share | |
2340 | * an fb with another CRTC instead | |
2341 | */ | |
70e1e0ec | 2342 | for_each_crtc(dev, c) { |
484b41dd JB |
2343 | i = to_intel_crtc(c); |
2344 | ||
2345 | if (c == &intel_crtc->base) | |
2346 | continue; | |
2347 | ||
66e514c1 | 2348 | if (!i->active || !c->primary->fb) |
484b41dd JB |
2349 | continue; |
2350 | ||
66e514c1 | 2351 | fb = to_intel_framebuffer(c->primary->fb); |
484b41dd | 2352 | if (i915_gem_obj_ggtt_offset(fb->obj) == plane_config->base) { |
66e514c1 DA |
2353 | drm_framebuffer_reference(c->primary->fb); |
2354 | intel_crtc->base.primary->fb = c->primary->fb; | |
484b41dd JB |
2355 | break; |
2356 | } | |
2357 | } | |
46f297fb JB |
2358 | } |
2359 | ||
29b9bde6 DV |
2360 | static void i9xx_update_primary_plane(struct drm_crtc *crtc, |
2361 | struct drm_framebuffer *fb, | |
2362 | int x, int y) | |
81255565 JB |
2363 | { |
2364 | struct drm_device *dev = crtc->dev; | |
2365 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2366 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2367 | struct intel_framebuffer *intel_fb; | |
05394f39 | 2368 | struct drm_i915_gem_object *obj; |
81255565 | 2369 | int plane = intel_crtc->plane; |
e506a0c6 | 2370 | unsigned long linear_offset; |
81255565 | 2371 | u32 dspcntr; |
5eddb70b | 2372 | u32 reg; |
81255565 | 2373 | |
81255565 JB |
2374 | intel_fb = to_intel_framebuffer(fb); |
2375 | obj = intel_fb->obj; | |
81255565 | 2376 | |
5eddb70b CW |
2377 | reg = DSPCNTR(plane); |
2378 | dspcntr = I915_READ(reg); | |
81255565 JB |
2379 | /* Mask out pixel format bits in case we change it */ |
2380 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
57779d06 VS |
2381 | switch (fb->pixel_format) { |
2382 | case DRM_FORMAT_C8: | |
81255565 JB |
2383 | dspcntr |= DISPPLANE_8BPP; |
2384 | break; | |
57779d06 VS |
2385 | case DRM_FORMAT_XRGB1555: |
2386 | case DRM_FORMAT_ARGB1555: | |
2387 | dspcntr |= DISPPLANE_BGRX555; | |
81255565 | 2388 | break; |
57779d06 VS |
2389 | case DRM_FORMAT_RGB565: |
2390 | dspcntr |= DISPPLANE_BGRX565; | |
2391 | break; | |
2392 | case DRM_FORMAT_XRGB8888: | |
2393 | case DRM_FORMAT_ARGB8888: | |
2394 | dspcntr |= DISPPLANE_BGRX888; | |
2395 | break; | |
2396 | case DRM_FORMAT_XBGR8888: | |
2397 | case DRM_FORMAT_ABGR8888: | |
2398 | dspcntr |= DISPPLANE_RGBX888; | |
2399 | break; | |
2400 | case DRM_FORMAT_XRGB2101010: | |
2401 | case DRM_FORMAT_ARGB2101010: | |
2402 | dspcntr |= DISPPLANE_BGRX101010; | |
2403 | break; | |
2404 | case DRM_FORMAT_XBGR2101010: | |
2405 | case DRM_FORMAT_ABGR2101010: | |
2406 | dspcntr |= DISPPLANE_RGBX101010; | |
81255565 JB |
2407 | break; |
2408 | default: | |
baba133a | 2409 | BUG(); |
81255565 | 2410 | } |
57779d06 | 2411 | |
a6c45cf0 | 2412 | if (INTEL_INFO(dev)->gen >= 4) { |
05394f39 | 2413 | if (obj->tiling_mode != I915_TILING_NONE) |
81255565 JB |
2414 | dspcntr |= DISPPLANE_TILED; |
2415 | else | |
2416 | dspcntr &= ~DISPPLANE_TILED; | |
2417 | } | |
2418 | ||
de1aa629 VS |
2419 | if (IS_G4X(dev)) |
2420 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2421 | ||
5eddb70b | 2422 | I915_WRITE(reg, dspcntr); |
81255565 | 2423 | |
e506a0c6 | 2424 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
81255565 | 2425 | |
c2c75131 DV |
2426 | if (INTEL_INFO(dev)->gen >= 4) { |
2427 | intel_crtc->dspaddr_offset = | |
bc752862 CW |
2428 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2429 | fb->bits_per_pixel / 8, | |
2430 | fb->pitches[0]); | |
c2c75131 DV |
2431 | linear_offset -= intel_crtc->dspaddr_offset; |
2432 | } else { | |
e506a0c6 | 2433 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2434 | } |
e506a0c6 | 2435 | |
f343c5f6 BW |
2436 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2437 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2438 | fb->pitches[0]); | |
01f2c773 | 2439 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2440 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2441 | I915_WRITE(DSPSURF(plane), |
2442 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2443 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2444 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2445 | } else |
f343c5f6 | 2446 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2447 | POSTING_READ(reg); |
17638cd6 JB |
2448 | } |
2449 | ||
29b9bde6 DV |
2450 | static void ironlake_update_primary_plane(struct drm_crtc *crtc, |
2451 | struct drm_framebuffer *fb, | |
2452 | int x, int y) | |
17638cd6 JB |
2453 | { |
2454 | struct drm_device *dev = crtc->dev; | |
2455 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2456 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2457 | struct intel_framebuffer *intel_fb; | |
2458 | struct drm_i915_gem_object *obj; | |
2459 | int plane = intel_crtc->plane; | |
e506a0c6 | 2460 | unsigned long linear_offset; |
17638cd6 JB |
2461 | u32 dspcntr; |
2462 | u32 reg; | |
2463 | ||
17638cd6 JB |
2464 | intel_fb = to_intel_framebuffer(fb); |
2465 | obj = intel_fb->obj; | |
2466 | ||
2467 | reg = DSPCNTR(plane); | |
2468 | dspcntr = I915_READ(reg); | |
2469 | /* Mask out pixel format bits in case we change it */ | |
2470 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
57779d06 VS |
2471 | switch (fb->pixel_format) { |
2472 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2473 | dspcntr |= DISPPLANE_8BPP; |
2474 | break; | |
57779d06 VS |
2475 | case DRM_FORMAT_RGB565: |
2476 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2477 | break; |
57779d06 VS |
2478 | case DRM_FORMAT_XRGB8888: |
2479 | case DRM_FORMAT_ARGB8888: | |
2480 | dspcntr |= DISPPLANE_BGRX888; | |
2481 | break; | |
2482 | case DRM_FORMAT_XBGR8888: | |
2483 | case DRM_FORMAT_ABGR8888: | |
2484 | dspcntr |= DISPPLANE_RGBX888; | |
2485 | break; | |
2486 | case DRM_FORMAT_XRGB2101010: | |
2487 | case DRM_FORMAT_ARGB2101010: | |
2488 | dspcntr |= DISPPLANE_BGRX101010; | |
2489 | break; | |
2490 | case DRM_FORMAT_XBGR2101010: | |
2491 | case DRM_FORMAT_ABGR2101010: | |
2492 | dspcntr |= DISPPLANE_RGBX101010; | |
17638cd6 JB |
2493 | break; |
2494 | default: | |
baba133a | 2495 | BUG(); |
17638cd6 JB |
2496 | } |
2497 | ||
2498 | if (obj->tiling_mode != I915_TILING_NONE) | |
2499 | dspcntr |= DISPPLANE_TILED; | |
2500 | else | |
2501 | dspcntr &= ~DISPPLANE_TILED; | |
2502 | ||
b42c6009 | 2503 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
1f5d76db PZ |
2504 | dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE; |
2505 | else | |
2506 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
17638cd6 JB |
2507 | |
2508 | I915_WRITE(reg, dspcntr); | |
2509 | ||
e506a0c6 | 2510 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
c2c75131 | 2511 | intel_crtc->dspaddr_offset = |
bc752862 CW |
2512 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2513 | fb->bits_per_pixel / 8, | |
2514 | fb->pitches[0]); | |
c2c75131 | 2515 | linear_offset -= intel_crtc->dspaddr_offset; |
17638cd6 | 2516 | |
f343c5f6 BW |
2517 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2518 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2519 | fb->pitches[0]); | |
01f2c773 | 2520 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2521 | I915_WRITE(DSPSURF(plane), |
2522 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2523 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2524 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2525 | } else { | |
2526 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2527 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2528 | } | |
17638cd6 | 2529 | POSTING_READ(reg); |
17638cd6 JB |
2530 | } |
2531 | ||
2532 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ | |
2533 | static int | |
2534 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
2535 | int x, int y, enum mode_set_atomic state) | |
2536 | { | |
2537 | struct drm_device *dev = crtc->dev; | |
2538 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 2539 | |
6b8e6ed0 CW |
2540 | if (dev_priv->display.disable_fbc) |
2541 | dev_priv->display.disable_fbc(dev); | |
3dec0095 | 2542 | intel_increase_pllclock(crtc); |
81255565 | 2543 | |
29b9bde6 DV |
2544 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
2545 | ||
2546 | return 0; | |
81255565 JB |
2547 | } |
2548 | ||
96a02917 VS |
2549 | void intel_display_handle_reset(struct drm_device *dev) |
2550 | { | |
2551 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2552 | struct drm_crtc *crtc; | |
2553 | ||
2554 | /* | |
2555 | * Flips in the rings have been nuked by the reset, | |
2556 | * so complete all pending flips so that user space | |
2557 | * will get its events and not get stuck. | |
2558 | * | |
2559 | * Also update the base address of all primary | |
2560 | * planes to the the last fb to make sure we're | |
2561 | * showing the correct fb after a reset. | |
2562 | * | |
2563 | * Need to make two loops over the crtcs so that we | |
2564 | * don't try to grab a crtc mutex before the | |
2565 | * pending_flip_queue really got woken up. | |
2566 | */ | |
2567 | ||
70e1e0ec | 2568 | for_each_crtc(dev, crtc) { |
96a02917 VS |
2569 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2570 | enum plane plane = intel_crtc->plane; | |
2571 | ||
2572 | intel_prepare_page_flip(dev, plane); | |
2573 | intel_finish_page_flip_plane(dev, plane); | |
2574 | } | |
2575 | ||
70e1e0ec | 2576 | for_each_crtc(dev, crtc) { |
96a02917 VS |
2577 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2578 | ||
2579 | mutex_lock(&crtc->mutex); | |
947fdaad CW |
2580 | /* |
2581 | * FIXME: Once we have proper support for primary planes (and | |
2582 | * disabling them without disabling the entire crtc) allow again | |
66e514c1 | 2583 | * a NULL crtc->primary->fb. |
947fdaad | 2584 | */ |
f4510a27 | 2585 | if (intel_crtc->active && crtc->primary->fb) |
262ca2b0 | 2586 | dev_priv->display.update_primary_plane(crtc, |
66e514c1 | 2587 | crtc->primary->fb, |
262ca2b0 MR |
2588 | crtc->x, |
2589 | crtc->y); | |
96a02917 VS |
2590 | mutex_unlock(&crtc->mutex); |
2591 | } | |
2592 | } | |
2593 | ||
14667a4b CW |
2594 | static int |
2595 | intel_finish_fb(struct drm_framebuffer *old_fb) | |
2596 | { | |
2597 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; | |
2598 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2599 | bool was_interruptible = dev_priv->mm.interruptible; | |
2600 | int ret; | |
2601 | ||
14667a4b CW |
2602 | /* Big Hammer, we also need to ensure that any pending |
2603 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
2604 | * current scanout is retired before unpinning the old | |
2605 | * framebuffer. | |
2606 | * | |
2607 | * This should only fail upon a hung GPU, in which case we | |
2608 | * can safely continue. | |
2609 | */ | |
2610 | dev_priv->mm.interruptible = false; | |
2611 | ret = i915_gem_object_finish_gpu(obj); | |
2612 | dev_priv->mm.interruptible = was_interruptible; | |
2613 | ||
2614 | return ret; | |
2615 | } | |
2616 | ||
7d5e3799 CW |
2617 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
2618 | { | |
2619 | struct drm_device *dev = crtc->dev; | |
2620 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2621 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2622 | unsigned long flags; | |
2623 | bool pending; | |
2624 | ||
2625 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
2626 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
2627 | return false; | |
2628 | ||
2629 | spin_lock_irqsave(&dev->event_lock, flags); | |
2630 | pending = to_intel_crtc(crtc)->unpin_work != NULL; | |
2631 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
2632 | ||
2633 | return pending; | |
2634 | } | |
2635 | ||
5c3b82e2 | 2636 | static int |
3c4fdcfb | 2637 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
94352cf9 | 2638 | struct drm_framebuffer *fb) |
79e53945 JB |
2639 | { |
2640 | struct drm_device *dev = crtc->dev; | |
6b8e6ed0 | 2641 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 2642 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
94352cf9 | 2643 | struct drm_framebuffer *old_fb; |
5c3b82e2 | 2644 | int ret; |
79e53945 | 2645 | |
7d5e3799 CW |
2646 | if (intel_crtc_has_pending_flip(crtc)) { |
2647 | DRM_ERROR("pipe is still busy with an old pageflip\n"); | |
2648 | return -EBUSY; | |
2649 | } | |
2650 | ||
79e53945 | 2651 | /* no fb bound */ |
94352cf9 | 2652 | if (!fb) { |
a5071c2f | 2653 | DRM_ERROR("No FB bound\n"); |
5c3b82e2 CW |
2654 | return 0; |
2655 | } | |
2656 | ||
7eb552ae | 2657 | if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) { |
84f44ce7 VS |
2658 | DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n", |
2659 | plane_name(intel_crtc->plane), | |
2660 | INTEL_INFO(dev)->num_pipes); | |
5c3b82e2 | 2661 | return -EINVAL; |
79e53945 JB |
2662 | } |
2663 | ||
5c3b82e2 | 2664 | mutex_lock(&dev->struct_mutex); |
265db958 | 2665 | ret = intel_pin_and_fence_fb_obj(dev, |
94352cf9 | 2666 | to_intel_framebuffer(fb)->obj, |
919926ae | 2667 | NULL); |
8ac36ec1 | 2668 | mutex_unlock(&dev->struct_mutex); |
5c3b82e2 | 2669 | if (ret != 0) { |
a5071c2f | 2670 | DRM_ERROR("pin & fence failed\n"); |
5c3b82e2 CW |
2671 | return ret; |
2672 | } | |
79e53945 | 2673 | |
bb2043de DL |
2674 | /* |
2675 | * Update pipe size and adjust fitter if needed: the reason for this is | |
2676 | * that in compute_mode_changes we check the native mode (not the pfit | |
2677 | * mode) to see if we can flip rather than do a full mode set. In the | |
2678 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
2679 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
2680 | * sized surface. | |
2681 | * | |
2682 | * To fix this properly, we need to hoist the checks up into | |
2683 | * compute_mode_changes (or above), check the actual pfit state and | |
2684 | * whether the platform allows pfit disable with pipe active, and only | |
2685 | * then update the pipesrc and pfit state, even on the flip path. | |
2686 | */ | |
d330a953 | 2687 | if (i915.fastboot) { |
d7bf63f2 DL |
2688 | const struct drm_display_mode *adjusted_mode = |
2689 | &intel_crtc->config.adjusted_mode; | |
2690 | ||
4d6a3e63 | 2691 | I915_WRITE(PIPESRC(intel_crtc->pipe), |
d7bf63f2 DL |
2692 | ((adjusted_mode->crtc_hdisplay - 1) << 16) | |
2693 | (adjusted_mode->crtc_vdisplay - 1)); | |
fd4daa9c | 2694 | if (!intel_crtc->config.pch_pfit.enabled && |
4d6a3e63 JB |
2695 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
2696 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
2697 | I915_WRITE(PF_CTL(intel_crtc->pipe), 0); | |
2698 | I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0); | |
2699 | I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0); | |
2700 | } | |
0637d60d JB |
2701 | intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay; |
2702 | intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay; | |
4d6a3e63 JB |
2703 | } |
2704 | ||
29b9bde6 | 2705 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
3c4fdcfb | 2706 | |
f4510a27 MR |
2707 | old_fb = crtc->primary->fb; |
2708 | crtc->primary->fb = fb; | |
6c4c86f5 DV |
2709 | crtc->x = x; |
2710 | crtc->y = y; | |
94352cf9 | 2711 | |
b7f1de28 | 2712 | if (old_fb) { |
d7697eea DV |
2713 | if (intel_crtc->active && old_fb != fb) |
2714 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
8ac36ec1 | 2715 | mutex_lock(&dev->struct_mutex); |
1690e1eb | 2716 | intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); |
8ac36ec1 | 2717 | mutex_unlock(&dev->struct_mutex); |
b7f1de28 | 2718 | } |
652c393a | 2719 | |
8ac36ec1 | 2720 | mutex_lock(&dev->struct_mutex); |
6b8e6ed0 | 2721 | intel_update_fbc(dev); |
4906557e | 2722 | intel_edp_psr_update(dev); |
5c3b82e2 | 2723 | mutex_unlock(&dev->struct_mutex); |
79e53945 | 2724 | |
5c3b82e2 | 2725 | return 0; |
79e53945 JB |
2726 | } |
2727 | ||
5e84e1a4 ZW |
2728 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
2729 | { | |
2730 | struct drm_device *dev = crtc->dev; | |
2731 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2732 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2733 | int pipe = intel_crtc->pipe; | |
2734 | u32 reg, temp; | |
2735 | ||
2736 | /* enable normal train */ | |
2737 | reg = FDI_TX_CTL(pipe); | |
2738 | temp = I915_READ(reg); | |
61e499bf | 2739 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
2740 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2741 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
2742 | } else { |
2743 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2744 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 2745 | } |
5e84e1a4 ZW |
2746 | I915_WRITE(reg, temp); |
2747 | ||
2748 | reg = FDI_RX_CTL(pipe); | |
2749 | temp = I915_READ(reg); | |
2750 | if (HAS_PCH_CPT(dev)) { | |
2751 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2752 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
2753 | } else { | |
2754 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2755 | temp |= FDI_LINK_TRAIN_NONE; | |
2756 | } | |
2757 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
2758 | ||
2759 | /* wait one idle pattern time */ | |
2760 | POSTING_READ(reg); | |
2761 | udelay(1000); | |
357555c0 JB |
2762 | |
2763 | /* IVB wants error correction enabled */ | |
2764 | if (IS_IVYBRIDGE(dev)) | |
2765 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
2766 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
2767 | } |
2768 | ||
1fbc0d78 | 2769 | static bool pipe_has_enabled_pch(struct intel_crtc *crtc) |
1e833f40 | 2770 | { |
1fbc0d78 DV |
2771 | return crtc->base.enabled && crtc->active && |
2772 | crtc->config.has_pch_encoder; | |
1e833f40 DV |
2773 | } |
2774 | ||
01a415fd DV |
2775 | static void ivb_modeset_global_resources(struct drm_device *dev) |
2776 | { | |
2777 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2778 | struct intel_crtc *pipe_B_crtc = | |
2779 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
2780 | struct intel_crtc *pipe_C_crtc = | |
2781 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]); | |
2782 | uint32_t temp; | |
2783 | ||
1e833f40 DV |
2784 | /* |
2785 | * When everything is off disable fdi C so that we could enable fdi B | |
2786 | * with all lanes. Note that we don't care about enabled pipes without | |
2787 | * an enabled pch encoder. | |
2788 | */ | |
2789 | if (!pipe_has_enabled_pch(pipe_B_crtc) && | |
2790 | !pipe_has_enabled_pch(pipe_C_crtc)) { | |
01a415fd DV |
2791 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
2792 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
2793 | ||
2794 | temp = I915_READ(SOUTH_CHICKEN1); | |
2795 | temp &= ~FDI_BC_BIFURCATION_SELECT; | |
2796 | DRM_DEBUG_KMS("disabling fdi C rx\n"); | |
2797 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
2798 | } | |
2799 | } | |
2800 | ||
8db9d77b ZW |
2801 | /* The FDI link training functions for ILK/Ibexpeak. */ |
2802 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
2803 | { | |
2804 | struct drm_device *dev = crtc->dev; | |
2805 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2806 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2807 | int pipe = intel_crtc->pipe; | |
5eddb70b | 2808 | u32 reg, temp, tries; |
8db9d77b | 2809 | |
1c8562f6 | 2810 | /* FDI needs bits from pipe first */ |
0fc932b8 | 2811 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 2812 | |
e1a44743 AJ |
2813 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2814 | for train result */ | |
5eddb70b CW |
2815 | reg = FDI_RX_IMR(pipe); |
2816 | temp = I915_READ(reg); | |
e1a44743 AJ |
2817 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2818 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2819 | I915_WRITE(reg, temp); |
2820 | I915_READ(reg); | |
e1a44743 AJ |
2821 | udelay(150); |
2822 | ||
8db9d77b | 2823 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2824 | reg = FDI_TX_CTL(pipe); |
2825 | temp = I915_READ(reg); | |
627eb5a3 DV |
2826 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2827 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
2828 | temp &= ~FDI_LINK_TRAIN_NONE; |
2829 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 2830 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2831 | |
5eddb70b CW |
2832 | reg = FDI_RX_CTL(pipe); |
2833 | temp = I915_READ(reg); | |
8db9d77b ZW |
2834 | temp &= ~FDI_LINK_TRAIN_NONE; |
2835 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
2836 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2837 | ||
2838 | POSTING_READ(reg); | |
8db9d77b ZW |
2839 | udelay(150); |
2840 | ||
5b2adf89 | 2841 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
2842 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
2843 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
2844 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 2845 | |
5eddb70b | 2846 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2847 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2848 | temp = I915_READ(reg); |
8db9d77b ZW |
2849 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2850 | ||
2851 | if ((temp & FDI_RX_BIT_LOCK)) { | |
2852 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 2853 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
2854 | break; |
2855 | } | |
8db9d77b | 2856 | } |
e1a44743 | 2857 | if (tries == 5) |
5eddb70b | 2858 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2859 | |
2860 | /* Train 2 */ | |
5eddb70b CW |
2861 | reg = FDI_TX_CTL(pipe); |
2862 | temp = I915_READ(reg); | |
8db9d77b ZW |
2863 | temp &= ~FDI_LINK_TRAIN_NONE; |
2864 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2865 | I915_WRITE(reg, temp); |
8db9d77b | 2866 | |
5eddb70b CW |
2867 | reg = FDI_RX_CTL(pipe); |
2868 | temp = I915_READ(reg); | |
8db9d77b ZW |
2869 | temp &= ~FDI_LINK_TRAIN_NONE; |
2870 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2871 | I915_WRITE(reg, temp); |
8db9d77b | 2872 | |
5eddb70b CW |
2873 | POSTING_READ(reg); |
2874 | udelay(150); | |
8db9d77b | 2875 | |
5eddb70b | 2876 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2877 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2878 | temp = I915_READ(reg); |
8db9d77b ZW |
2879 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2880 | ||
2881 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 2882 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
2883 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2884 | break; | |
2885 | } | |
8db9d77b | 2886 | } |
e1a44743 | 2887 | if (tries == 5) |
5eddb70b | 2888 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2889 | |
2890 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 2891 | |
8db9d77b ZW |
2892 | } |
2893 | ||
0206e353 | 2894 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
2895 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
2896 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
2897 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
2898 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
2899 | }; | |
2900 | ||
2901 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
2902 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
2903 | { | |
2904 | struct drm_device *dev = crtc->dev; | |
2905 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2906 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2907 | int pipe = intel_crtc->pipe; | |
fa37d39e | 2908 | u32 reg, temp, i, retry; |
8db9d77b | 2909 | |
e1a44743 AJ |
2910 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2911 | for train result */ | |
5eddb70b CW |
2912 | reg = FDI_RX_IMR(pipe); |
2913 | temp = I915_READ(reg); | |
e1a44743 AJ |
2914 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2915 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2916 | I915_WRITE(reg, temp); |
2917 | ||
2918 | POSTING_READ(reg); | |
e1a44743 AJ |
2919 | udelay(150); |
2920 | ||
8db9d77b | 2921 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2922 | reg = FDI_TX_CTL(pipe); |
2923 | temp = I915_READ(reg); | |
627eb5a3 DV |
2924 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2925 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
2926 | temp &= ~FDI_LINK_TRAIN_NONE; |
2927 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2928 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2929 | /* SNB-B */ | |
2930 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 2931 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2932 | |
d74cf324 DV |
2933 | I915_WRITE(FDI_RX_MISC(pipe), |
2934 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
2935 | ||
5eddb70b CW |
2936 | reg = FDI_RX_CTL(pipe); |
2937 | temp = I915_READ(reg); | |
8db9d77b ZW |
2938 | if (HAS_PCH_CPT(dev)) { |
2939 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2940 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2941 | } else { | |
2942 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2943 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2944 | } | |
5eddb70b CW |
2945 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2946 | ||
2947 | POSTING_READ(reg); | |
8db9d77b ZW |
2948 | udelay(150); |
2949 | ||
0206e353 | 2950 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2951 | reg = FDI_TX_CTL(pipe); |
2952 | temp = I915_READ(reg); | |
8db9d77b ZW |
2953 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2954 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2955 | I915_WRITE(reg, temp); |
2956 | ||
2957 | POSTING_READ(reg); | |
8db9d77b ZW |
2958 | udelay(500); |
2959 | ||
fa37d39e SP |
2960 | for (retry = 0; retry < 5; retry++) { |
2961 | reg = FDI_RX_IIR(pipe); | |
2962 | temp = I915_READ(reg); | |
2963 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2964 | if (temp & FDI_RX_BIT_LOCK) { | |
2965 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
2966 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
2967 | break; | |
2968 | } | |
2969 | udelay(50); | |
8db9d77b | 2970 | } |
fa37d39e SP |
2971 | if (retry < 5) |
2972 | break; | |
8db9d77b ZW |
2973 | } |
2974 | if (i == 4) | |
5eddb70b | 2975 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2976 | |
2977 | /* Train 2 */ | |
5eddb70b CW |
2978 | reg = FDI_TX_CTL(pipe); |
2979 | temp = I915_READ(reg); | |
8db9d77b ZW |
2980 | temp &= ~FDI_LINK_TRAIN_NONE; |
2981 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2982 | if (IS_GEN6(dev)) { | |
2983 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2984 | /* SNB-B */ | |
2985 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
2986 | } | |
5eddb70b | 2987 | I915_WRITE(reg, temp); |
8db9d77b | 2988 | |
5eddb70b CW |
2989 | reg = FDI_RX_CTL(pipe); |
2990 | temp = I915_READ(reg); | |
8db9d77b ZW |
2991 | if (HAS_PCH_CPT(dev)) { |
2992 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2993 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
2994 | } else { | |
2995 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2996 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2997 | } | |
5eddb70b CW |
2998 | I915_WRITE(reg, temp); |
2999 | ||
3000 | POSTING_READ(reg); | |
8db9d77b ZW |
3001 | udelay(150); |
3002 | ||
0206e353 | 3003 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3004 | reg = FDI_TX_CTL(pipe); |
3005 | temp = I915_READ(reg); | |
8db9d77b ZW |
3006 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3007 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3008 | I915_WRITE(reg, temp); |
3009 | ||
3010 | POSTING_READ(reg); | |
8db9d77b ZW |
3011 | udelay(500); |
3012 | ||
fa37d39e SP |
3013 | for (retry = 0; retry < 5; retry++) { |
3014 | reg = FDI_RX_IIR(pipe); | |
3015 | temp = I915_READ(reg); | |
3016 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3017 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3018 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3019 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3020 | break; | |
3021 | } | |
3022 | udelay(50); | |
8db9d77b | 3023 | } |
fa37d39e SP |
3024 | if (retry < 5) |
3025 | break; | |
8db9d77b ZW |
3026 | } |
3027 | if (i == 4) | |
5eddb70b | 3028 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3029 | |
3030 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3031 | } | |
3032 | ||
357555c0 JB |
3033 | /* Manual link training for Ivy Bridge A0 parts */ |
3034 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3035 | { | |
3036 | struct drm_device *dev = crtc->dev; | |
3037 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3038 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3039 | int pipe = intel_crtc->pipe; | |
139ccd3f | 3040 | u32 reg, temp, i, j; |
357555c0 JB |
3041 | |
3042 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3043 | for train result */ | |
3044 | reg = FDI_RX_IMR(pipe); | |
3045 | temp = I915_READ(reg); | |
3046 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3047 | temp &= ~FDI_RX_BIT_LOCK; | |
3048 | I915_WRITE(reg, temp); | |
3049 | ||
3050 | POSTING_READ(reg); | |
3051 | udelay(150); | |
3052 | ||
01a415fd DV |
3053 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3054 | I915_READ(FDI_RX_IIR(pipe))); | |
3055 | ||
139ccd3f JB |
3056 | /* Try each vswing and preemphasis setting twice before moving on */ |
3057 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3058 | /* disable first in case we need to retry */ | |
3059 | reg = FDI_TX_CTL(pipe); | |
3060 | temp = I915_READ(reg); | |
3061 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3062 | temp &= ~FDI_TX_ENABLE; | |
3063 | I915_WRITE(reg, temp); | |
357555c0 | 3064 | |
139ccd3f JB |
3065 | reg = FDI_RX_CTL(pipe); |
3066 | temp = I915_READ(reg); | |
3067 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3068 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3069 | temp &= ~FDI_RX_ENABLE; | |
3070 | I915_WRITE(reg, temp); | |
357555c0 | 3071 | |
139ccd3f | 3072 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3073 | reg = FDI_TX_CTL(pipe); |
3074 | temp = I915_READ(reg); | |
139ccd3f JB |
3075 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
3076 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
3077 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; | |
357555c0 | 3078 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3079 | temp |= snb_b_fdi_train_param[j/2]; |
3080 | temp |= FDI_COMPOSITE_SYNC; | |
3081 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3082 | |
139ccd3f JB |
3083 | I915_WRITE(FDI_RX_MISC(pipe), |
3084 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3085 | |
139ccd3f | 3086 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3087 | temp = I915_READ(reg); |
139ccd3f JB |
3088 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3089 | temp |= FDI_COMPOSITE_SYNC; | |
3090 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3091 | |
139ccd3f JB |
3092 | POSTING_READ(reg); |
3093 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3094 | |
139ccd3f JB |
3095 | for (i = 0; i < 4; i++) { |
3096 | reg = FDI_RX_IIR(pipe); | |
3097 | temp = I915_READ(reg); | |
3098 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3099 | |
139ccd3f JB |
3100 | if (temp & FDI_RX_BIT_LOCK || |
3101 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3102 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3103 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3104 | i); | |
3105 | break; | |
3106 | } | |
3107 | udelay(1); /* should be 0.5us */ | |
3108 | } | |
3109 | if (i == 4) { | |
3110 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3111 | continue; | |
3112 | } | |
357555c0 | 3113 | |
139ccd3f | 3114 | /* Train 2 */ |
357555c0 JB |
3115 | reg = FDI_TX_CTL(pipe); |
3116 | temp = I915_READ(reg); | |
139ccd3f JB |
3117 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3118 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3119 | I915_WRITE(reg, temp); | |
3120 | ||
3121 | reg = FDI_RX_CTL(pipe); | |
3122 | temp = I915_READ(reg); | |
3123 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3124 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3125 | I915_WRITE(reg, temp); |
3126 | ||
3127 | POSTING_READ(reg); | |
139ccd3f | 3128 | udelay(2); /* should be 1.5us */ |
357555c0 | 3129 | |
139ccd3f JB |
3130 | for (i = 0; i < 4; i++) { |
3131 | reg = FDI_RX_IIR(pipe); | |
3132 | temp = I915_READ(reg); | |
3133 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3134 | |
139ccd3f JB |
3135 | if (temp & FDI_RX_SYMBOL_LOCK || |
3136 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3137 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3138 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3139 | i); | |
3140 | goto train_done; | |
3141 | } | |
3142 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3143 | } |
139ccd3f JB |
3144 | if (i == 4) |
3145 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3146 | } |
357555c0 | 3147 | |
139ccd3f | 3148 | train_done: |
357555c0 JB |
3149 | DRM_DEBUG_KMS("FDI train done.\n"); |
3150 | } | |
3151 | ||
88cefb6c | 3152 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3153 | { |
88cefb6c | 3154 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3155 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3156 | int pipe = intel_crtc->pipe; |
5eddb70b | 3157 | u32 reg, temp; |
79e53945 | 3158 | |
c64e311e | 3159 | |
c98e9dcf | 3160 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3161 | reg = FDI_RX_CTL(pipe); |
3162 | temp = I915_READ(reg); | |
627eb5a3 DV |
3163 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
3164 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
dfd07d72 | 3165 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3166 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3167 | ||
3168 | POSTING_READ(reg); | |
c98e9dcf JB |
3169 | udelay(200); |
3170 | ||
3171 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3172 | temp = I915_READ(reg); |
3173 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3174 | ||
3175 | POSTING_READ(reg); | |
c98e9dcf JB |
3176 | udelay(200); |
3177 | ||
20749730 PZ |
3178 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3179 | reg = FDI_TX_CTL(pipe); | |
3180 | temp = I915_READ(reg); | |
3181 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3182 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3183 | |
20749730 PZ |
3184 | POSTING_READ(reg); |
3185 | udelay(100); | |
6be4a607 | 3186 | } |
0e23b99d JB |
3187 | } |
3188 | ||
88cefb6c DV |
3189 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3190 | { | |
3191 | struct drm_device *dev = intel_crtc->base.dev; | |
3192 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3193 | int pipe = intel_crtc->pipe; | |
3194 | u32 reg, temp; | |
3195 | ||
3196 | /* Switch from PCDclk to Rawclk */ | |
3197 | reg = FDI_RX_CTL(pipe); | |
3198 | temp = I915_READ(reg); | |
3199 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3200 | ||
3201 | /* Disable CPU FDI TX PLL */ | |
3202 | reg = FDI_TX_CTL(pipe); | |
3203 | temp = I915_READ(reg); | |
3204 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3205 | ||
3206 | POSTING_READ(reg); | |
3207 | udelay(100); | |
3208 | ||
3209 | reg = FDI_RX_CTL(pipe); | |
3210 | temp = I915_READ(reg); | |
3211 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3212 | ||
3213 | /* Wait for the clocks to turn off. */ | |
3214 | POSTING_READ(reg); | |
3215 | udelay(100); | |
3216 | } | |
3217 | ||
0fc932b8 JB |
3218 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3219 | { | |
3220 | struct drm_device *dev = crtc->dev; | |
3221 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3222 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3223 | int pipe = intel_crtc->pipe; | |
3224 | u32 reg, temp; | |
3225 | ||
3226 | /* disable CPU FDI tx and PCH FDI rx */ | |
3227 | reg = FDI_TX_CTL(pipe); | |
3228 | temp = I915_READ(reg); | |
3229 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3230 | POSTING_READ(reg); | |
3231 | ||
3232 | reg = FDI_RX_CTL(pipe); | |
3233 | temp = I915_READ(reg); | |
3234 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3235 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3236 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3237 | ||
3238 | POSTING_READ(reg); | |
3239 | udelay(100); | |
3240 | ||
3241 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3242 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3243 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3244 | |
3245 | /* still set train pattern 1 */ | |
3246 | reg = FDI_TX_CTL(pipe); | |
3247 | temp = I915_READ(reg); | |
3248 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3249 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3250 | I915_WRITE(reg, temp); | |
3251 | ||
3252 | reg = FDI_RX_CTL(pipe); | |
3253 | temp = I915_READ(reg); | |
3254 | if (HAS_PCH_CPT(dev)) { | |
3255 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3256 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3257 | } else { | |
3258 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3259 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3260 | } | |
3261 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3262 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3263 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3264 | I915_WRITE(reg, temp); |
3265 | ||
3266 | POSTING_READ(reg); | |
3267 | udelay(100); | |
3268 | } | |
3269 | ||
5dce5b93 CW |
3270 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3271 | { | |
3272 | struct intel_crtc *crtc; | |
3273 | ||
3274 | /* Note that we don't need to be called with mode_config.lock here | |
3275 | * as our list of CRTC objects is static for the lifetime of the | |
3276 | * device and so cannot disappear as we iterate. Similarly, we can | |
3277 | * happily treat the predicates as racy, atomic checks as userspace | |
3278 | * cannot claim and pin a new fb without at least acquring the | |
3279 | * struct_mutex and so serialising with us. | |
3280 | */ | |
d3fcc808 | 3281 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3282 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3283 | continue; | |
3284 | ||
3285 | if (crtc->unpin_work) | |
3286 | intel_wait_for_vblank(dev, crtc->pipe); | |
3287 | ||
3288 | return true; | |
3289 | } | |
3290 | ||
3291 | return false; | |
3292 | } | |
3293 | ||
46a55d30 | 3294 | void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3295 | { |
0f91128d | 3296 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3297 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 | 3298 | |
f4510a27 | 3299 | if (crtc->primary->fb == NULL) |
e6c3a2a6 CW |
3300 | return; |
3301 | ||
2c10d571 DV |
3302 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
3303 | ||
eed6d67d DV |
3304 | WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue, |
3305 | !intel_crtc_has_pending_flip(crtc), | |
3306 | 60*HZ) == 0); | |
5bb61643 | 3307 | |
0f91128d | 3308 | mutex_lock(&dev->struct_mutex); |
f4510a27 | 3309 | intel_finish_fb(crtc->primary->fb); |
0f91128d | 3310 | mutex_unlock(&dev->struct_mutex); |
e6c3a2a6 CW |
3311 | } |
3312 | ||
e615efe4 ED |
3313 | /* Program iCLKIP clock to the desired frequency */ |
3314 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3315 | { | |
3316 | struct drm_device *dev = crtc->dev; | |
3317 | struct drm_i915_private *dev_priv = dev->dev_private; | |
241bfc38 | 3318 | int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock; |
e615efe4 ED |
3319 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3320 | u32 temp; | |
3321 | ||
09153000 DV |
3322 | mutex_lock(&dev_priv->dpio_lock); |
3323 | ||
e615efe4 ED |
3324 | /* It is necessary to ungate the pixclk gate prior to programming |
3325 | * the divisors, and gate it back when it is done. | |
3326 | */ | |
3327 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3328 | ||
3329 | /* Disable SSCCTL */ | |
3330 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
3331 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
3332 | SBI_SSCCTL_DISABLE, | |
3333 | SBI_ICLK); | |
e615efe4 ED |
3334 | |
3335 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3336 | if (clock == 20000) { |
e615efe4 ED |
3337 | auxdiv = 1; |
3338 | divsel = 0x41; | |
3339 | phaseinc = 0x20; | |
3340 | } else { | |
3341 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3342 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3343 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3344 | * convert the virtual clock precision to KHz here for higher |
3345 | * precision. | |
3346 | */ | |
3347 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3348 | u32 iclk_pi_range = 64; | |
3349 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3350 | ||
12d7ceed | 3351 | desired_divisor = (iclk_virtual_root_freq / clock); |
e615efe4 ED |
3352 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3353 | pi_value = desired_divisor % iclk_pi_range; | |
3354 | ||
3355 | auxdiv = 0; | |
3356 | divsel = msb_divisor_value - 2; | |
3357 | phaseinc = pi_value; | |
3358 | } | |
3359 | ||
3360 | /* This should not happen with any sane values */ | |
3361 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3362 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3363 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3364 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3365 | ||
3366 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3367 | clock, |
e615efe4 ED |
3368 | auxdiv, |
3369 | divsel, | |
3370 | phasedir, | |
3371 | phaseinc); | |
3372 | ||
3373 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 3374 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
3375 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3376 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
3377 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
3378 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
3379 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
3380 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 3381 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
3382 | |
3383 | /* Program SSCAUXDIV */ | |
988d6ee8 | 3384 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
3385 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3386 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 3387 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
3388 | |
3389 | /* Enable modulator and associated divider */ | |
988d6ee8 | 3390 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 3391 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 3392 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
3393 | |
3394 | /* Wait for initialization time */ | |
3395 | udelay(24); | |
3396 | ||
3397 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 DV |
3398 | |
3399 | mutex_unlock(&dev_priv->dpio_lock); | |
e615efe4 ED |
3400 | } |
3401 | ||
275f01b2 DV |
3402 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
3403 | enum pipe pch_transcoder) | |
3404 | { | |
3405 | struct drm_device *dev = crtc->base.dev; | |
3406 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3407 | enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; | |
3408 | ||
3409 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
3410 | I915_READ(HTOTAL(cpu_transcoder))); | |
3411 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
3412 | I915_READ(HBLANK(cpu_transcoder))); | |
3413 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
3414 | I915_READ(HSYNC(cpu_transcoder))); | |
3415 | ||
3416 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
3417 | I915_READ(VTOTAL(cpu_transcoder))); | |
3418 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
3419 | I915_READ(VBLANK(cpu_transcoder))); | |
3420 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
3421 | I915_READ(VSYNC(cpu_transcoder))); | |
3422 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
3423 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
3424 | } | |
3425 | ||
1fbc0d78 DV |
3426 | static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev) |
3427 | { | |
3428 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3429 | uint32_t temp; | |
3430 | ||
3431 | temp = I915_READ(SOUTH_CHICKEN1); | |
3432 | if (temp & FDI_BC_BIFURCATION_SELECT) | |
3433 | return; | |
3434 | ||
3435 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
3436 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
3437 | ||
3438 | temp |= FDI_BC_BIFURCATION_SELECT; | |
3439 | DRM_DEBUG_KMS("enabling fdi C rx\n"); | |
3440 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
3441 | POSTING_READ(SOUTH_CHICKEN1); | |
3442 | } | |
3443 | ||
3444 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
3445 | { | |
3446 | struct drm_device *dev = intel_crtc->base.dev; | |
3447 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3448 | ||
3449 | switch (intel_crtc->pipe) { | |
3450 | case PIPE_A: | |
3451 | break; | |
3452 | case PIPE_B: | |
3453 | if (intel_crtc->config.fdi_lanes > 2) | |
3454 | WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); | |
3455 | else | |
3456 | cpt_enable_fdi_bc_bifurcation(dev); | |
3457 | ||
3458 | break; | |
3459 | case PIPE_C: | |
3460 | cpt_enable_fdi_bc_bifurcation(dev); | |
3461 | ||
3462 | break; | |
3463 | default: | |
3464 | BUG(); | |
3465 | } | |
3466 | } | |
3467 | ||
f67a559d JB |
3468 | /* |
3469 | * Enable PCH resources required for PCH ports: | |
3470 | * - PCH PLLs | |
3471 | * - FDI training & RX/TX | |
3472 | * - update transcoder timings | |
3473 | * - DP transcoding bits | |
3474 | * - transcoder | |
3475 | */ | |
3476 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
3477 | { |
3478 | struct drm_device *dev = crtc->dev; | |
3479 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3480 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3481 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 3482 | u32 reg, temp; |
2c07245f | 3483 | |
ab9412ba | 3484 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 3485 | |
1fbc0d78 DV |
3486 | if (IS_IVYBRIDGE(dev)) |
3487 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
3488 | ||
cd986abb DV |
3489 | /* Write the TU size bits before fdi link training, so that error |
3490 | * detection works. */ | |
3491 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
3492 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
3493 | ||
c98e9dcf | 3494 | /* For PCH output, training FDI link */ |
674cf967 | 3495 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 3496 | |
3ad8a208 DV |
3497 | /* We need to program the right clock selection before writing the pixel |
3498 | * mutliplier into the DPLL. */ | |
303b81e0 | 3499 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 3500 | u32 sel; |
4b645f14 | 3501 | |
c98e9dcf | 3502 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
3503 | temp |= TRANS_DPLL_ENABLE(pipe); |
3504 | sel = TRANS_DPLLB_SEL(pipe); | |
a43f6e0f | 3505 | if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
3506 | temp |= sel; |
3507 | else | |
3508 | temp &= ~sel; | |
c98e9dcf | 3509 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 3510 | } |
5eddb70b | 3511 | |
3ad8a208 DV |
3512 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
3513 | * transcoder, and we actually should do this to not upset any PCH | |
3514 | * transcoder that already use the clock when we share it. | |
3515 | * | |
3516 | * Note that enable_shared_dpll tries to do the right thing, but | |
3517 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
3518 | * the right LVDS enable sequence. */ | |
85b3894f | 3519 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 3520 | |
d9b6cb56 JB |
3521 | /* set transcoder timing, panel must allow it */ |
3522 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 3523 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 3524 | |
303b81e0 | 3525 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 3526 | |
c98e9dcf JB |
3527 | /* For PCH DP, enable TRANS_DP_CTL */ |
3528 | if (HAS_PCH_CPT(dev) && | |
417e822d KP |
3529 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
3530 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
dfd07d72 | 3531 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
5eddb70b CW |
3532 | reg = TRANS_DP_CTL(pipe); |
3533 | temp = I915_READ(reg); | |
3534 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
3535 | TRANS_DP_SYNC_MASK | |
3536 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
3537 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
3538 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 3539 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
3540 | |
3541 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 3542 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 3543 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 3544 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
3545 | |
3546 | switch (intel_trans_dp_port_sel(crtc)) { | |
3547 | case PCH_DP_B: | |
5eddb70b | 3548 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
3549 | break; |
3550 | case PCH_DP_C: | |
5eddb70b | 3551 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
3552 | break; |
3553 | case PCH_DP_D: | |
5eddb70b | 3554 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
3555 | break; |
3556 | default: | |
e95d41e1 | 3557 | BUG(); |
32f9d658 | 3558 | } |
2c07245f | 3559 | |
5eddb70b | 3560 | I915_WRITE(reg, temp); |
6be4a607 | 3561 | } |
b52eb4dc | 3562 | |
b8a4f404 | 3563 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
3564 | } |
3565 | ||
1507e5bd PZ |
3566 | static void lpt_pch_enable(struct drm_crtc *crtc) |
3567 | { | |
3568 | struct drm_device *dev = crtc->dev; | |
3569 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3570 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3b117c8f | 3571 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
1507e5bd | 3572 | |
ab9412ba | 3573 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 3574 | |
8c52b5e8 | 3575 | lpt_program_iclkip(crtc); |
1507e5bd | 3576 | |
0540e488 | 3577 | /* Set transcoder timing. */ |
275f01b2 | 3578 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 3579 | |
937bb610 | 3580 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
3581 | } |
3582 | ||
e2b78267 | 3583 | static void intel_put_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3584 | { |
e2b78267 | 3585 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
ee7b9f93 JB |
3586 | |
3587 | if (pll == NULL) | |
3588 | return; | |
3589 | ||
3590 | if (pll->refcount == 0) { | |
46edb027 | 3591 | WARN(1, "bad %s refcount\n", pll->name); |
ee7b9f93 JB |
3592 | return; |
3593 | } | |
3594 | ||
f4a091c7 DV |
3595 | if (--pll->refcount == 0) { |
3596 | WARN_ON(pll->on); | |
3597 | WARN_ON(pll->active); | |
3598 | } | |
3599 | ||
a43f6e0f | 3600 | crtc->config.shared_dpll = DPLL_ID_PRIVATE; |
ee7b9f93 JB |
3601 | } |
3602 | ||
b89a1d39 | 3603 | static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3604 | { |
e2b78267 DV |
3605 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
3606 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
3607 | enum intel_dpll_id i; | |
ee7b9f93 | 3608 | |
ee7b9f93 | 3609 | if (pll) { |
46edb027 DV |
3610 | DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n", |
3611 | crtc->base.base.id, pll->name); | |
e2b78267 | 3612 | intel_put_shared_dpll(crtc); |
ee7b9f93 JB |
3613 | } |
3614 | ||
98b6bd99 DV |
3615 | if (HAS_PCH_IBX(dev_priv->dev)) { |
3616 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 3617 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 3618 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 3619 | |
46edb027 DV |
3620 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
3621 | crtc->base.base.id, pll->name); | |
98b6bd99 | 3622 | |
f2a69f44 DV |
3623 | WARN_ON(pll->refcount); |
3624 | ||
98b6bd99 DV |
3625 | goto found; |
3626 | } | |
3627 | ||
e72f9fbf DV |
3628 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3629 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 JB |
3630 | |
3631 | /* Only want to check enabled timings first */ | |
3632 | if (pll->refcount == 0) | |
3633 | continue; | |
3634 | ||
b89a1d39 DV |
3635 | if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state, |
3636 | sizeof(pll->hw_state)) == 0) { | |
46edb027 | 3637 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n", |
e2b78267 | 3638 | crtc->base.base.id, |
46edb027 | 3639 | pll->name, pll->refcount, pll->active); |
ee7b9f93 JB |
3640 | |
3641 | goto found; | |
3642 | } | |
3643 | } | |
3644 | ||
3645 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
3646 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3647 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 | 3648 | if (pll->refcount == 0) { |
46edb027 DV |
3649 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
3650 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
3651 | goto found; |
3652 | } | |
3653 | } | |
3654 | ||
3655 | return NULL; | |
3656 | ||
3657 | found: | |
f2a69f44 DV |
3658 | if (pll->refcount == 0) |
3659 | pll->hw_state = crtc->config.dpll_hw_state; | |
3660 | ||
a43f6e0f | 3661 | crtc->config.shared_dpll = i; |
46edb027 DV |
3662 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
3663 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 3664 | |
cdbd2316 | 3665 | pll->refcount++; |
e04c7350 | 3666 | |
ee7b9f93 JB |
3667 | return pll; |
3668 | } | |
3669 | ||
a1520318 | 3670 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
3671 | { |
3672 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 3673 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
3674 | u32 temp; |
3675 | ||
3676 | temp = I915_READ(dslreg); | |
3677 | udelay(500); | |
3678 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 3679 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 3680 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
3681 | } |
3682 | } | |
3683 | ||
b074cec8 JB |
3684 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
3685 | { | |
3686 | struct drm_device *dev = crtc->base.dev; | |
3687 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3688 | int pipe = crtc->pipe; | |
3689 | ||
fd4daa9c | 3690 | if (crtc->config.pch_pfit.enabled) { |
b074cec8 JB |
3691 | /* Force use of hard-coded filter coefficients |
3692 | * as some pre-programmed values are broken, | |
3693 | * e.g. x201. | |
3694 | */ | |
3695 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
3696 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
3697 | PF_PIPE_SEL_IVB(pipe)); | |
3698 | else | |
3699 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
3700 | I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos); | |
3701 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size); | |
d4270e57 JB |
3702 | } |
3703 | } | |
3704 | ||
bb53d4ae VS |
3705 | static void intel_enable_planes(struct drm_crtc *crtc) |
3706 | { | |
3707 | struct drm_device *dev = crtc->dev; | |
3708 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 3709 | struct drm_plane *plane; |
bb53d4ae VS |
3710 | struct intel_plane *intel_plane; |
3711 | ||
af2b653b MR |
3712 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
3713 | intel_plane = to_intel_plane(plane); | |
bb53d4ae VS |
3714 | if (intel_plane->pipe == pipe) |
3715 | intel_plane_restore(&intel_plane->base); | |
af2b653b | 3716 | } |
bb53d4ae VS |
3717 | } |
3718 | ||
3719 | static void intel_disable_planes(struct drm_crtc *crtc) | |
3720 | { | |
3721 | struct drm_device *dev = crtc->dev; | |
3722 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 3723 | struct drm_plane *plane; |
bb53d4ae VS |
3724 | struct intel_plane *intel_plane; |
3725 | ||
af2b653b MR |
3726 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
3727 | intel_plane = to_intel_plane(plane); | |
bb53d4ae VS |
3728 | if (intel_plane->pipe == pipe) |
3729 | intel_plane_disable(&intel_plane->base); | |
af2b653b | 3730 | } |
bb53d4ae VS |
3731 | } |
3732 | ||
20bc8673 | 3733 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 3734 | { |
cea165c3 VS |
3735 | struct drm_device *dev = crtc->base.dev; |
3736 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 PZ |
3737 | |
3738 | if (!crtc->config.ips_enabled) | |
3739 | return; | |
3740 | ||
cea165c3 VS |
3741 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
3742 | intel_wait_for_vblank(dev, crtc->pipe); | |
3743 | ||
d77e4531 | 3744 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 3745 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
3746 | mutex_lock(&dev_priv->rps.hw_lock); |
3747 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
3748 | mutex_unlock(&dev_priv->rps.hw_lock); | |
3749 | /* Quoting Art Runyan: "its not safe to expect any particular | |
3750 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
3751 | * mailbox." Moreover, the mailbox may return a bogus state, |
3752 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
3753 | */ |
3754 | } else { | |
3755 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
3756 | /* The bit only becomes 1 in the next vblank, so this wait here | |
3757 | * is essentially intel_wait_for_vblank. If we don't have this | |
3758 | * and don't wait for vblanks until the end of crtc_enable, then | |
3759 | * the HW state readout code will complain that the expected | |
3760 | * IPS_CTL value is not the one we read. */ | |
3761 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
3762 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
3763 | } | |
d77e4531 PZ |
3764 | } |
3765 | ||
20bc8673 | 3766 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
3767 | { |
3768 | struct drm_device *dev = crtc->base.dev; | |
3769 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3770 | ||
3771 | if (!crtc->config.ips_enabled) | |
3772 | return; | |
3773 | ||
3774 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 3775 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
3776 | mutex_lock(&dev_priv->rps.hw_lock); |
3777 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
3778 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
3779 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
3780 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
3781 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 3782 | } else { |
2a114cc1 | 3783 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
3784 | POSTING_READ(IPS_CTL); |
3785 | } | |
d77e4531 PZ |
3786 | |
3787 | /* We need to wait for a vblank before we can disable the plane. */ | |
3788 | intel_wait_for_vblank(dev, crtc->pipe); | |
3789 | } | |
3790 | ||
3791 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
3792 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
3793 | { | |
3794 | struct drm_device *dev = crtc->dev; | |
3795 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3796 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3797 | enum pipe pipe = intel_crtc->pipe; | |
3798 | int palreg = PALETTE(pipe); | |
3799 | int i; | |
3800 | bool reenable_ips = false; | |
3801 | ||
3802 | /* The clocks have to be on to load the palette. */ | |
3803 | if (!crtc->enabled || !intel_crtc->active) | |
3804 | return; | |
3805 | ||
3806 | if (!HAS_PCH_SPLIT(dev_priv->dev)) { | |
3807 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) | |
3808 | assert_dsi_pll_enabled(dev_priv); | |
3809 | else | |
3810 | assert_pll_enabled(dev_priv, pipe); | |
3811 | } | |
3812 | ||
3813 | /* use legacy palette for Ironlake */ | |
3814 | if (HAS_PCH_SPLIT(dev)) | |
3815 | palreg = LGC_PALETTE(pipe); | |
3816 | ||
3817 | /* Workaround : Do not read or write the pipe palette/gamma data while | |
3818 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
3819 | */ | |
41e6fc4c | 3820 | if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled && |
d77e4531 PZ |
3821 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
3822 | GAMMA_MODE_MODE_SPLIT)) { | |
3823 | hsw_disable_ips(intel_crtc); | |
3824 | reenable_ips = true; | |
3825 | } | |
3826 | ||
3827 | for (i = 0; i < 256; i++) { | |
3828 | I915_WRITE(palreg + 4 * i, | |
3829 | (intel_crtc->lut_r[i] << 16) | | |
3830 | (intel_crtc->lut_g[i] << 8) | | |
3831 | intel_crtc->lut_b[i]); | |
3832 | } | |
3833 | ||
3834 | if (reenable_ips) | |
3835 | hsw_enable_ips(intel_crtc); | |
3836 | } | |
3837 | ||
d3eedb1a VS |
3838 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
3839 | { | |
3840 | if (!enable && intel_crtc->overlay) { | |
3841 | struct drm_device *dev = intel_crtc->base.dev; | |
3842 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3843 | ||
3844 | mutex_lock(&dev->struct_mutex); | |
3845 | dev_priv->mm.interruptible = false; | |
3846 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
3847 | dev_priv->mm.interruptible = true; | |
3848 | mutex_unlock(&dev->struct_mutex); | |
3849 | } | |
3850 | ||
3851 | /* Let userspace switch the overlay on again. In most cases userspace | |
3852 | * has to recompute where to put it anyway. | |
3853 | */ | |
3854 | } | |
3855 | ||
3856 | /** | |
3857 | * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware | |
3858 | * cursor plane briefly if not already running after enabling the display | |
3859 | * plane. | |
3860 | * This workaround avoids occasional blank screens when self refresh is | |
3861 | * enabled. | |
3862 | */ | |
3863 | static void | |
3864 | g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe) | |
3865 | { | |
3866 | u32 cntl = I915_READ(CURCNTR(pipe)); | |
3867 | ||
3868 | if ((cntl & CURSOR_MODE) == 0) { | |
3869 | u32 fw_bcl_self = I915_READ(FW_BLC_SELF); | |
3870 | ||
3871 | I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN); | |
3872 | I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX); | |
3873 | intel_wait_for_vblank(dev_priv->dev, pipe); | |
3874 | I915_WRITE(CURCNTR(pipe), cntl); | |
3875 | I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); | |
3876 | I915_WRITE(FW_BLC_SELF, fw_bcl_self); | |
3877 | } | |
3878 | } | |
3879 | ||
3880 | static void intel_crtc_enable_planes(struct drm_crtc *crtc) | |
a5c4d7bc VS |
3881 | { |
3882 | struct drm_device *dev = crtc->dev; | |
3883 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3884 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3885 | int pipe = intel_crtc->pipe; | |
3886 | int plane = intel_crtc->plane; | |
3887 | ||
3888 | intel_enable_primary_hw_plane(dev_priv, plane, pipe); | |
3889 | intel_enable_planes(crtc); | |
d3eedb1a VS |
3890 | /* The fixup needs to happen before cursor is enabled */ |
3891 | if (IS_G4X(dev)) | |
3892 | g4x_fixup_plane(dev_priv, pipe); | |
a5c4d7bc | 3893 | intel_crtc_update_cursor(crtc, true); |
d3eedb1a | 3894 | intel_crtc_dpms_overlay(intel_crtc, true); |
a5c4d7bc VS |
3895 | |
3896 | hsw_enable_ips(intel_crtc); | |
3897 | ||
3898 | mutex_lock(&dev->struct_mutex); | |
3899 | intel_update_fbc(dev); | |
71b1c373 | 3900 | intel_edp_psr_update(dev); |
a5c4d7bc VS |
3901 | mutex_unlock(&dev->struct_mutex); |
3902 | } | |
3903 | ||
d3eedb1a | 3904 | static void intel_crtc_disable_planes(struct drm_crtc *crtc) |
a5c4d7bc VS |
3905 | { |
3906 | struct drm_device *dev = crtc->dev; | |
3907 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3908 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3909 | int pipe = intel_crtc->pipe; | |
3910 | int plane = intel_crtc->plane; | |
3911 | ||
3912 | intel_crtc_wait_for_pending_flips(crtc); | |
87b6b101 | 3913 | drm_crtc_vblank_off(crtc); |
a5c4d7bc VS |
3914 | |
3915 | if (dev_priv->fbc.plane == plane) | |
3916 | intel_disable_fbc(dev); | |
3917 | ||
3918 | hsw_disable_ips(intel_crtc); | |
3919 | ||
d3eedb1a | 3920 | intel_crtc_dpms_overlay(intel_crtc, false); |
a5c4d7bc VS |
3921 | intel_crtc_update_cursor(crtc, false); |
3922 | intel_disable_planes(crtc); | |
3923 | intel_disable_primary_hw_plane(dev_priv, plane, pipe); | |
3924 | } | |
3925 | ||
f67a559d JB |
3926 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
3927 | { | |
3928 | struct drm_device *dev = crtc->dev; | |
3929 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3930 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3931 | struct intel_encoder *encoder; |
f67a559d | 3932 | int pipe = intel_crtc->pipe; |
29407aab | 3933 | enum plane plane = intel_crtc->plane; |
f67a559d | 3934 | |
08a48469 DV |
3935 | WARN_ON(!crtc->enabled); |
3936 | ||
f67a559d JB |
3937 | if (intel_crtc->active) |
3938 | return; | |
3939 | ||
b14b1055 DV |
3940 | if (intel_crtc->config.has_pch_encoder) |
3941 | intel_prepare_shared_dpll(intel_crtc); | |
3942 | ||
29407aab DV |
3943 | if (intel_crtc->config.has_dp_encoder) |
3944 | intel_dp_set_m_n(intel_crtc); | |
3945 | ||
3946 | intel_set_pipe_timings(intel_crtc); | |
3947 | ||
3948 | if (intel_crtc->config.has_pch_encoder) { | |
3949 | intel_cpu_transcoder_set_m_n(intel_crtc, | |
3950 | &intel_crtc->config.fdi_m_n); | |
3951 | } | |
3952 | ||
3953 | ironlake_set_pipeconf(crtc); | |
3954 | ||
3955 | /* Set up the display plane register */ | |
3956 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); | |
3957 | POSTING_READ(DSPCNTR(plane)); | |
3958 | ||
3959 | dev_priv->display.update_primary_plane(crtc, crtc->primary->fb, | |
3960 | crtc->x, crtc->y); | |
3961 | ||
f67a559d | 3962 | intel_crtc->active = true; |
8664281b PZ |
3963 | |
3964 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
3965 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); | |
3966 | ||
f6736a1a | 3967 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
3968 | if (encoder->pre_enable) |
3969 | encoder->pre_enable(encoder); | |
f67a559d | 3970 | |
5bfe2ac0 | 3971 | if (intel_crtc->config.has_pch_encoder) { |
fff367c7 DV |
3972 | /* Note: FDI PLL enabling _must_ be done before we enable the |
3973 | * cpu pipes, hence this is separate from all the other fdi/pch | |
3974 | * enabling. */ | |
88cefb6c | 3975 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
3976 | } else { |
3977 | assert_fdi_tx_disabled(dev_priv, pipe); | |
3978 | assert_fdi_rx_disabled(dev_priv, pipe); | |
3979 | } | |
f67a559d | 3980 | |
b074cec8 | 3981 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 3982 | |
9c54c0dd JB |
3983 | /* |
3984 | * On ILK+ LUT must be loaded before the pipe is running but with | |
3985 | * clocks enabled | |
3986 | */ | |
3987 | intel_crtc_load_lut(crtc); | |
3988 | ||
f37fcc2a | 3989 | intel_update_watermarks(crtc); |
e1fdc473 | 3990 | intel_enable_pipe(intel_crtc); |
f67a559d | 3991 | |
5bfe2ac0 | 3992 | if (intel_crtc->config.has_pch_encoder) |
f67a559d | 3993 | ironlake_pch_enable(crtc); |
c98e9dcf | 3994 | |
fa5c73b1 DV |
3995 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3996 | encoder->enable(encoder); | |
61b77ddd DV |
3997 | |
3998 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 3999 | cpt_verify_modeset(dev, intel_crtc->pipe); |
6ce94100 | 4000 | |
d3eedb1a | 4001 | intel_crtc_enable_planes(crtc); |
a5c4d7bc | 4002 | |
87b6b101 | 4003 | drm_crtc_vblank_on(crtc); |
6be4a607 JB |
4004 | } |
4005 | ||
42db64ef PZ |
4006 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4007 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4008 | { | |
f5adf94e | 4009 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4010 | } |
4011 | ||
e4916946 PZ |
4012 | /* |
4013 | * This implements the workaround described in the "notes" section of the mode | |
4014 | * set sequence documentation. When going from no pipes or single pipe to | |
4015 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
4016 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
4017 | */ | |
4018 | static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) | |
4019 | { | |
4020 | struct drm_device *dev = crtc->base.dev; | |
4021 | struct intel_crtc *crtc_it, *other_active_crtc = NULL; | |
4022 | ||
4023 | /* We want to get the other_active_crtc only if there's only 1 other | |
4024 | * active crtc. */ | |
d3fcc808 | 4025 | for_each_intel_crtc(dev, crtc_it) { |
e4916946 PZ |
4026 | if (!crtc_it->active || crtc_it == crtc) |
4027 | continue; | |
4028 | ||
4029 | if (other_active_crtc) | |
4030 | return; | |
4031 | ||
4032 | other_active_crtc = crtc_it; | |
4033 | } | |
4034 | if (!other_active_crtc) | |
4035 | return; | |
4036 | ||
4037 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4038 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4039 | } | |
4040 | ||
4f771f10 PZ |
4041 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4042 | { | |
4043 | struct drm_device *dev = crtc->dev; | |
4044 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4045 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4046 | struct intel_encoder *encoder; | |
4047 | int pipe = intel_crtc->pipe; | |
229fca97 | 4048 | enum plane plane = intel_crtc->plane; |
4f771f10 PZ |
4049 | |
4050 | WARN_ON(!crtc->enabled); | |
4051 | ||
4052 | if (intel_crtc->active) | |
4053 | return; | |
4054 | ||
229fca97 DV |
4055 | if (intel_crtc->config.has_dp_encoder) |
4056 | intel_dp_set_m_n(intel_crtc); | |
4057 | ||
4058 | intel_set_pipe_timings(intel_crtc); | |
4059 | ||
4060 | if (intel_crtc->config.has_pch_encoder) { | |
4061 | intel_cpu_transcoder_set_m_n(intel_crtc, | |
4062 | &intel_crtc->config.fdi_m_n); | |
4063 | } | |
4064 | ||
4065 | haswell_set_pipeconf(crtc); | |
4066 | ||
4067 | intel_set_pipe_csc(crtc); | |
4068 | ||
4069 | /* Set up the display plane register */ | |
4070 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE); | |
4071 | POSTING_READ(DSPCNTR(plane)); | |
4072 | ||
4073 | dev_priv->display.update_primary_plane(crtc, crtc->primary->fb, | |
4074 | crtc->x, crtc->y); | |
4075 | ||
4f771f10 | 4076 | intel_crtc->active = true; |
8664281b PZ |
4077 | |
4078 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
4079 | if (intel_crtc->config.has_pch_encoder) | |
4080 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); | |
4081 | ||
5bfe2ac0 | 4082 | if (intel_crtc->config.has_pch_encoder) |
04945641 | 4083 | dev_priv->display.fdi_link_train(crtc); |
4f771f10 PZ |
4084 | |
4085 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
4086 | if (encoder->pre_enable) | |
4087 | encoder->pre_enable(encoder); | |
4088 | ||
1f544388 | 4089 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 4090 | |
b074cec8 | 4091 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
4092 | |
4093 | /* | |
4094 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4095 | * clocks enabled | |
4096 | */ | |
4097 | intel_crtc_load_lut(crtc); | |
4098 | ||
1f544388 | 4099 | intel_ddi_set_pipe_settings(crtc); |
8228c251 | 4100 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 4101 | |
f37fcc2a | 4102 | intel_update_watermarks(crtc); |
e1fdc473 | 4103 | intel_enable_pipe(intel_crtc); |
42db64ef | 4104 | |
5bfe2ac0 | 4105 | if (intel_crtc->config.has_pch_encoder) |
1507e5bd | 4106 | lpt_pch_enable(crtc); |
4f771f10 | 4107 | |
8807e55b | 4108 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 4109 | encoder->enable(encoder); |
8807e55b JN |
4110 | intel_opregion_notify_encoder(encoder, true); |
4111 | } | |
4f771f10 | 4112 | |
e4916946 PZ |
4113 | /* If we change the relative order between pipe/planes enabling, we need |
4114 | * to change the workaround. */ | |
4115 | haswell_mode_set_planes_workaround(intel_crtc); | |
d3eedb1a | 4116 | intel_crtc_enable_planes(crtc); |
f2752282 | 4117 | |
87b6b101 | 4118 | drm_crtc_vblank_on(crtc); |
4f771f10 PZ |
4119 | } |
4120 | ||
3f8dce3a DV |
4121 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
4122 | { | |
4123 | struct drm_device *dev = crtc->base.dev; | |
4124 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4125 | int pipe = crtc->pipe; | |
4126 | ||
4127 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
4128 | * it's in use. The hw state code will make sure we get this right. */ | |
fd4daa9c | 4129 | if (crtc->config.pch_pfit.enabled) { |
3f8dce3a DV |
4130 | I915_WRITE(PF_CTL(pipe), 0); |
4131 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
4132 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
4133 | } | |
4134 | } | |
4135 | ||
6be4a607 JB |
4136 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
4137 | { | |
4138 | struct drm_device *dev = crtc->dev; | |
4139 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4140 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4141 | struct intel_encoder *encoder; |
6be4a607 | 4142 | int pipe = intel_crtc->pipe; |
5eddb70b | 4143 | u32 reg, temp; |
b52eb4dc | 4144 | |
f7abfe8b CW |
4145 | if (!intel_crtc->active) |
4146 | return; | |
4147 | ||
d3eedb1a | 4148 | intel_crtc_disable_planes(crtc); |
a5c4d7bc | 4149 | |
ea9d758d DV |
4150 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4151 | encoder->disable(encoder); | |
4152 | ||
d925c59a DV |
4153 | if (intel_crtc->config.has_pch_encoder) |
4154 | intel_set_pch_fifo_underrun_reporting(dev, pipe, false); | |
4155 | ||
b24e7179 | 4156 | intel_disable_pipe(dev_priv, pipe); |
32f9d658 | 4157 | |
3f8dce3a | 4158 | ironlake_pfit_disable(intel_crtc); |
2c07245f | 4159 | |
bf49ec8c DV |
4160 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4161 | if (encoder->post_disable) | |
4162 | encoder->post_disable(encoder); | |
2c07245f | 4163 | |
d925c59a DV |
4164 | if (intel_crtc->config.has_pch_encoder) { |
4165 | ironlake_fdi_disable(crtc); | |
913d8d11 | 4166 | |
d925c59a DV |
4167 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
4168 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); | |
6be4a607 | 4169 | |
d925c59a DV |
4170 | if (HAS_PCH_CPT(dev)) { |
4171 | /* disable TRANS_DP_CTL */ | |
4172 | reg = TRANS_DP_CTL(pipe); | |
4173 | temp = I915_READ(reg); | |
4174 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
4175 | TRANS_DP_PORT_SEL_MASK); | |
4176 | temp |= TRANS_DP_PORT_SEL_NONE; | |
4177 | I915_WRITE(reg, temp); | |
4178 | ||
4179 | /* disable DPLL_SEL */ | |
4180 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 4181 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 4182 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 4183 | } |
e3421a18 | 4184 | |
d925c59a | 4185 | /* disable PCH DPLL */ |
e72f9fbf | 4186 | intel_disable_shared_dpll(intel_crtc); |
8db9d77b | 4187 | |
d925c59a DV |
4188 | ironlake_fdi_pll_disable(intel_crtc); |
4189 | } | |
6b383a7f | 4190 | |
f7abfe8b | 4191 | intel_crtc->active = false; |
46ba614c | 4192 | intel_update_watermarks(crtc); |
d1ebd816 BW |
4193 | |
4194 | mutex_lock(&dev->struct_mutex); | |
6b383a7f | 4195 | intel_update_fbc(dev); |
71b1c373 | 4196 | intel_edp_psr_update(dev); |
d1ebd816 | 4197 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 4198 | } |
1b3c7a47 | 4199 | |
4f771f10 | 4200 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 4201 | { |
4f771f10 PZ |
4202 | struct drm_device *dev = crtc->dev; |
4203 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 4204 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 PZ |
4205 | struct intel_encoder *encoder; |
4206 | int pipe = intel_crtc->pipe; | |
3b117c8f | 4207 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee7b9f93 | 4208 | |
4f771f10 PZ |
4209 | if (!intel_crtc->active) |
4210 | return; | |
4211 | ||
d3eedb1a | 4212 | intel_crtc_disable_planes(crtc); |
dda9a66a | 4213 | |
8807e55b JN |
4214 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4215 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 4216 | encoder->disable(encoder); |
8807e55b | 4217 | } |
4f771f10 | 4218 | |
8664281b PZ |
4219 | if (intel_crtc->config.has_pch_encoder) |
4220 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false); | |
4f771f10 PZ |
4221 | intel_disable_pipe(dev_priv, pipe); |
4222 | ||
ad80a810 | 4223 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 4224 | |
3f8dce3a | 4225 | ironlake_pfit_disable(intel_crtc); |
4f771f10 | 4226 | |
1f544388 | 4227 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 PZ |
4228 | |
4229 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
4230 | if (encoder->post_disable) | |
4231 | encoder->post_disable(encoder); | |
4232 | ||
88adfff1 | 4233 | if (intel_crtc->config.has_pch_encoder) { |
ab4d966c | 4234 | lpt_disable_pch_transcoder(dev_priv); |
8664281b | 4235 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
1ad960f2 | 4236 | intel_ddi_fdi_disable(crtc); |
83616634 | 4237 | } |
4f771f10 PZ |
4238 | |
4239 | intel_crtc->active = false; | |
46ba614c | 4240 | intel_update_watermarks(crtc); |
4f771f10 PZ |
4241 | |
4242 | mutex_lock(&dev->struct_mutex); | |
4243 | intel_update_fbc(dev); | |
71b1c373 | 4244 | intel_edp_psr_update(dev); |
4f771f10 PZ |
4245 | mutex_unlock(&dev->struct_mutex); |
4246 | } | |
4247 | ||
ee7b9f93 JB |
4248 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
4249 | { | |
4250 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e72f9fbf | 4251 | intel_put_shared_dpll(intel_crtc); |
ee7b9f93 JB |
4252 | } |
4253 | ||
6441ab5f PZ |
4254 | static void haswell_crtc_off(struct drm_crtc *crtc) |
4255 | { | |
4256 | intel_ddi_put_crtc_pll(crtc); | |
4257 | } | |
4258 | ||
2dd24552 JB |
4259 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
4260 | { | |
4261 | struct drm_device *dev = crtc->base.dev; | |
4262 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4263 | struct intel_crtc_config *pipe_config = &crtc->config; | |
4264 | ||
328d8e82 | 4265 | if (!crtc->config.gmch_pfit.control) |
2dd24552 JB |
4266 | return; |
4267 | ||
2dd24552 | 4268 | /* |
c0b03411 DV |
4269 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
4270 | * according to register description and PRM. | |
2dd24552 | 4271 | */ |
c0b03411 DV |
4272 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
4273 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 4274 | |
b074cec8 JB |
4275 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
4276 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
4277 | |
4278 | /* Border color in case we don't scale up to the full screen. Black by | |
4279 | * default, change to something else for debugging. */ | |
4280 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
4281 | } |
4282 | ||
77d22dca ID |
4283 | #define for_each_power_domain(domain, mask) \ |
4284 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
4285 | if ((1 << (domain)) & (mask)) | |
4286 | ||
319be8ae ID |
4287 | enum intel_display_power_domain |
4288 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
4289 | { | |
4290 | struct drm_device *dev = intel_encoder->base.dev; | |
4291 | struct intel_digital_port *intel_dig_port; | |
4292 | ||
4293 | switch (intel_encoder->type) { | |
4294 | case INTEL_OUTPUT_UNKNOWN: | |
4295 | /* Only DDI platforms should ever use this output type */ | |
4296 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
4297 | case INTEL_OUTPUT_DISPLAYPORT: | |
4298 | case INTEL_OUTPUT_HDMI: | |
4299 | case INTEL_OUTPUT_EDP: | |
4300 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
4301 | switch (intel_dig_port->port) { | |
4302 | case PORT_A: | |
4303 | return POWER_DOMAIN_PORT_DDI_A_4_LANES; | |
4304 | case PORT_B: | |
4305 | return POWER_DOMAIN_PORT_DDI_B_4_LANES; | |
4306 | case PORT_C: | |
4307 | return POWER_DOMAIN_PORT_DDI_C_4_LANES; | |
4308 | case PORT_D: | |
4309 | return POWER_DOMAIN_PORT_DDI_D_4_LANES; | |
4310 | default: | |
4311 | WARN_ON_ONCE(1); | |
4312 | return POWER_DOMAIN_PORT_OTHER; | |
4313 | } | |
4314 | case INTEL_OUTPUT_ANALOG: | |
4315 | return POWER_DOMAIN_PORT_CRT; | |
4316 | case INTEL_OUTPUT_DSI: | |
4317 | return POWER_DOMAIN_PORT_DSI; | |
4318 | default: | |
4319 | return POWER_DOMAIN_PORT_OTHER; | |
4320 | } | |
4321 | } | |
4322 | ||
4323 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) | |
77d22dca | 4324 | { |
319be8ae ID |
4325 | struct drm_device *dev = crtc->dev; |
4326 | struct intel_encoder *intel_encoder; | |
4327 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4328 | enum pipe pipe = intel_crtc->pipe; | |
4329 | bool pfit_enabled = intel_crtc->config.pch_pfit.enabled; | |
77d22dca ID |
4330 | unsigned long mask; |
4331 | enum transcoder transcoder; | |
4332 | ||
4333 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); | |
4334 | ||
4335 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); | |
4336 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
4337 | if (pfit_enabled) | |
4338 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); | |
4339 | ||
319be8ae ID |
4340 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
4341 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); | |
4342 | ||
77d22dca ID |
4343 | return mask; |
4344 | } | |
4345 | ||
4346 | void intel_display_set_init_power(struct drm_i915_private *dev_priv, | |
4347 | bool enable) | |
4348 | { | |
4349 | if (dev_priv->power_domains.init_power_on == enable) | |
4350 | return; | |
4351 | ||
4352 | if (enable) | |
4353 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); | |
4354 | else | |
4355 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); | |
4356 | ||
4357 | dev_priv->power_domains.init_power_on = enable; | |
4358 | } | |
4359 | ||
4360 | static void modeset_update_crtc_power_domains(struct drm_device *dev) | |
4361 | { | |
4362 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4363 | unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; | |
4364 | struct intel_crtc *crtc; | |
4365 | ||
4366 | /* | |
4367 | * First get all needed power domains, then put all unneeded, to avoid | |
4368 | * any unnecessary toggling of the power wells. | |
4369 | */ | |
d3fcc808 | 4370 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
4371 | enum intel_display_power_domain domain; |
4372 | ||
4373 | if (!crtc->base.enabled) | |
4374 | continue; | |
4375 | ||
319be8ae | 4376 | pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base); |
77d22dca ID |
4377 | |
4378 | for_each_power_domain(domain, pipe_domains[crtc->pipe]) | |
4379 | intel_display_power_get(dev_priv, domain); | |
4380 | } | |
4381 | ||
d3fcc808 | 4382 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
4383 | enum intel_display_power_domain domain; |
4384 | ||
4385 | for_each_power_domain(domain, crtc->enabled_power_domains) | |
4386 | intel_display_power_put(dev_priv, domain); | |
4387 | ||
4388 | crtc->enabled_power_domains = pipe_domains[crtc->pipe]; | |
4389 | } | |
4390 | ||
4391 | intel_display_set_init_power(dev_priv, false); | |
4392 | } | |
4393 | ||
586f49dc | 4394 | int valleyview_get_vco(struct drm_i915_private *dev_priv) |
30a970c6 | 4395 | { |
586f49dc | 4396 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
30a970c6 | 4397 | |
586f49dc JB |
4398 | /* Obtain SKU information */ |
4399 | mutex_lock(&dev_priv->dpio_lock); | |
4400 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
4401 | CCK_FUSE_HPLL_FREQ_MASK; | |
4402 | mutex_unlock(&dev_priv->dpio_lock); | |
30a970c6 | 4403 | |
586f49dc | 4404 | return vco_freq[hpll_freq]; |
30a970c6 JB |
4405 | } |
4406 | ||
4407 | /* Adjust CDclk dividers to allow high res or save power if possible */ | |
4408 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
4409 | { | |
4410 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4411 | u32 val, cmd; | |
4412 | ||
d60c4473 ID |
4413 | WARN_ON(valleyview_cur_cdclk(dev_priv) != dev_priv->vlv_cdclk_freq); |
4414 | dev_priv->vlv_cdclk_freq = cdclk; | |
4415 | ||
30a970c6 JB |
4416 | if (cdclk >= 320) /* jump to highest voltage for 400MHz too */ |
4417 | cmd = 2; | |
4418 | else if (cdclk == 266) | |
4419 | cmd = 1; | |
4420 | else | |
4421 | cmd = 0; | |
4422 | ||
4423 | mutex_lock(&dev_priv->rps.hw_lock); | |
4424 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
4425 | val &= ~DSPFREQGUAR_MASK; | |
4426 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
4427 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
4428 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
4429 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
4430 | 50)) { | |
4431 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
4432 | } | |
4433 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4434 | ||
4435 | if (cdclk == 400) { | |
4436 | u32 divider, vco; | |
4437 | ||
4438 | vco = valleyview_get_vco(dev_priv); | |
4439 | divider = ((vco << 1) / cdclk) - 1; | |
4440 | ||
4441 | mutex_lock(&dev_priv->dpio_lock); | |
4442 | /* adjust cdclk divider */ | |
4443 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
4444 | val &= ~0xf; | |
4445 | val |= divider; | |
4446 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
4447 | mutex_unlock(&dev_priv->dpio_lock); | |
4448 | } | |
4449 | ||
4450 | mutex_lock(&dev_priv->dpio_lock); | |
4451 | /* adjust self-refresh exit latency value */ | |
4452 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
4453 | val &= ~0x7f; | |
4454 | ||
4455 | /* | |
4456 | * For high bandwidth configs, we set a higher latency in the bunit | |
4457 | * so that the core display fetch happens in time to avoid underruns. | |
4458 | */ | |
4459 | if (cdclk == 400) | |
4460 | val |= 4500 / 250; /* 4.5 usec */ | |
4461 | else | |
4462 | val |= 3000 / 250; /* 3.0 usec */ | |
4463 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
4464 | mutex_unlock(&dev_priv->dpio_lock); | |
4465 | ||
4466 | /* Since we changed the CDclk, we need to update the GMBUSFREQ too */ | |
4467 | intel_i2c_reset(dev); | |
4468 | } | |
4469 | ||
d60c4473 | 4470 | int valleyview_cur_cdclk(struct drm_i915_private *dev_priv) |
30a970c6 JB |
4471 | { |
4472 | int cur_cdclk, vco; | |
4473 | int divider; | |
4474 | ||
4475 | vco = valleyview_get_vco(dev_priv); | |
4476 | ||
4477 | mutex_lock(&dev_priv->dpio_lock); | |
4478 | divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
4479 | mutex_unlock(&dev_priv->dpio_lock); | |
4480 | ||
4481 | divider &= 0xf; | |
4482 | ||
4483 | cur_cdclk = (vco << 1) / (divider + 1); | |
4484 | ||
4485 | return cur_cdclk; | |
4486 | } | |
4487 | ||
4488 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, | |
4489 | int max_pixclk) | |
4490 | { | |
30a970c6 JB |
4491 | /* |
4492 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
4493 | * 200MHz | |
4494 | * 267MHz | |
4495 | * 320MHz | |
4496 | * 400MHz | |
4497 | * So we check to see whether we're above 90% of the lower bin and | |
4498 | * adjust if needed. | |
4499 | */ | |
4500 | if (max_pixclk > 288000) { | |
4501 | return 400; | |
4502 | } else if (max_pixclk > 240000) { | |
4503 | return 320; | |
4504 | } else | |
4505 | return 266; | |
4506 | /* Looks like the 200MHz CDclk freq doesn't work on some configs */ | |
4507 | } | |
4508 | ||
2f2d7aa1 VS |
4509 | /* compute the max pixel clock for new configuration */ |
4510 | static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv) | |
30a970c6 JB |
4511 | { |
4512 | struct drm_device *dev = dev_priv->dev; | |
4513 | struct intel_crtc *intel_crtc; | |
4514 | int max_pixclk = 0; | |
4515 | ||
d3fcc808 | 4516 | for_each_intel_crtc(dev, intel_crtc) { |
2f2d7aa1 | 4517 | if (intel_crtc->new_enabled) |
30a970c6 | 4518 | max_pixclk = max(max_pixclk, |
2f2d7aa1 | 4519 | intel_crtc->new_config->adjusted_mode.crtc_clock); |
30a970c6 JB |
4520 | } |
4521 | ||
4522 | return max_pixclk; | |
4523 | } | |
4524 | ||
4525 | static void valleyview_modeset_global_pipes(struct drm_device *dev, | |
2f2d7aa1 | 4526 | unsigned *prepare_pipes) |
30a970c6 JB |
4527 | { |
4528 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4529 | struct intel_crtc *intel_crtc; | |
2f2d7aa1 | 4530 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
30a970c6 | 4531 | |
d60c4473 ID |
4532 | if (valleyview_calc_cdclk(dev_priv, max_pixclk) == |
4533 | dev_priv->vlv_cdclk_freq) | |
30a970c6 JB |
4534 | return; |
4535 | ||
2f2d7aa1 | 4536 | /* disable/enable all currently active pipes while we change cdclk */ |
d3fcc808 | 4537 | for_each_intel_crtc(dev, intel_crtc) |
30a970c6 JB |
4538 | if (intel_crtc->base.enabled) |
4539 | *prepare_pipes |= (1 << intel_crtc->pipe); | |
4540 | } | |
4541 | ||
4542 | static void valleyview_modeset_global_resources(struct drm_device *dev) | |
4543 | { | |
4544 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2f2d7aa1 | 4545 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
30a970c6 JB |
4546 | int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); |
4547 | ||
d60c4473 | 4548 | if (req_cdclk != dev_priv->vlv_cdclk_freq) |
30a970c6 | 4549 | valleyview_set_cdclk(dev, req_cdclk); |
77961eb9 | 4550 | modeset_update_crtc_power_domains(dev); |
30a970c6 JB |
4551 | } |
4552 | ||
89b667f8 JB |
4553 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
4554 | { | |
4555 | struct drm_device *dev = crtc->dev; | |
5b18e57c | 4556 | struct drm_i915_private *dev_priv = dev->dev_private; |
89b667f8 JB |
4557 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4558 | struct intel_encoder *encoder; | |
4559 | int pipe = intel_crtc->pipe; | |
5b18e57c | 4560 | int plane = intel_crtc->plane; |
23538ef1 | 4561 | bool is_dsi; |
5b18e57c | 4562 | u32 dspcntr; |
89b667f8 JB |
4563 | |
4564 | WARN_ON(!crtc->enabled); | |
4565 | ||
4566 | if (intel_crtc->active) | |
4567 | return; | |
4568 | ||
bdd4b6a6 DV |
4569 | vlv_prepare_pll(intel_crtc); |
4570 | ||
5b18e57c DV |
4571 | /* Set up the display plane register */ |
4572 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
4573 | ||
4574 | if (intel_crtc->config.has_dp_encoder) | |
4575 | intel_dp_set_m_n(intel_crtc); | |
4576 | ||
4577 | intel_set_pipe_timings(intel_crtc); | |
4578 | ||
4579 | /* pipesrc and dspsize control the size that is scaled from, | |
4580 | * which should always be the user's requested size. | |
4581 | */ | |
4582 | I915_WRITE(DSPSIZE(plane), | |
4583 | ((intel_crtc->config.pipe_src_h - 1) << 16) | | |
4584 | (intel_crtc->config.pipe_src_w - 1)); | |
4585 | I915_WRITE(DSPPOS(plane), 0); | |
4586 | ||
4587 | i9xx_set_pipeconf(intel_crtc); | |
4588 | ||
4589 | I915_WRITE(DSPCNTR(plane), dspcntr); | |
4590 | POSTING_READ(DSPCNTR(plane)); | |
4591 | ||
4592 | dev_priv->display.update_primary_plane(crtc, crtc->primary->fb, | |
4593 | crtc->x, crtc->y); | |
4594 | ||
89b667f8 | 4595 | intel_crtc->active = true; |
89b667f8 | 4596 | |
4a3436e8 VS |
4597 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
4598 | ||
89b667f8 JB |
4599 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4600 | if (encoder->pre_pll_enable) | |
4601 | encoder->pre_pll_enable(encoder); | |
4602 | ||
23538ef1 JN |
4603 | is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI); |
4604 | ||
9d556c99 CML |
4605 | if (!is_dsi) { |
4606 | if (IS_CHERRYVIEW(dev)) | |
4607 | chv_enable_pll(intel_crtc); | |
4608 | else | |
4609 | vlv_enable_pll(intel_crtc); | |
4610 | } | |
89b667f8 JB |
4611 | |
4612 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
4613 | if (encoder->pre_enable) | |
4614 | encoder->pre_enable(encoder); | |
4615 | ||
2dd24552 JB |
4616 | i9xx_pfit_enable(intel_crtc); |
4617 | ||
63cbb074 VS |
4618 | intel_crtc_load_lut(crtc); |
4619 | ||
f37fcc2a | 4620 | intel_update_watermarks(crtc); |
e1fdc473 | 4621 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 4622 | |
5004945f JN |
4623 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4624 | encoder->enable(encoder); | |
9ab0460b VS |
4625 | |
4626 | intel_crtc_enable_planes(crtc); | |
d40d9187 | 4627 | |
87b6b101 | 4628 | drm_crtc_vblank_on(crtc); |
56b80e1f VS |
4629 | |
4630 | /* Underruns don't raise interrupts, so check manually. */ | |
4631 | i9xx_check_fifo_underruns(dev); | |
89b667f8 JB |
4632 | } |
4633 | ||
f13c2ef3 DV |
4634 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
4635 | { | |
4636 | struct drm_device *dev = crtc->base.dev; | |
4637 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4638 | ||
4639 | I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0); | |
4640 | I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1); | |
4641 | } | |
4642 | ||
0b8765c6 | 4643 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
4644 | { |
4645 | struct drm_device *dev = crtc->dev; | |
5b18e57c | 4646 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 4647 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 4648 | struct intel_encoder *encoder; |
79e53945 | 4649 | int pipe = intel_crtc->pipe; |
5b18e57c DV |
4650 | int plane = intel_crtc->plane; |
4651 | u32 dspcntr; | |
79e53945 | 4652 | |
08a48469 DV |
4653 | WARN_ON(!crtc->enabled); |
4654 | ||
f7abfe8b CW |
4655 | if (intel_crtc->active) |
4656 | return; | |
4657 | ||
f13c2ef3 DV |
4658 | i9xx_set_pll_dividers(intel_crtc); |
4659 | ||
5b18e57c DV |
4660 | /* Set up the display plane register */ |
4661 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
4662 | ||
4663 | if (pipe == 0) | |
4664 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; | |
4665 | else | |
4666 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
4667 | ||
4668 | if (intel_crtc->config.has_dp_encoder) | |
4669 | intel_dp_set_m_n(intel_crtc); | |
4670 | ||
4671 | intel_set_pipe_timings(intel_crtc); | |
4672 | ||
4673 | /* pipesrc and dspsize control the size that is scaled from, | |
4674 | * which should always be the user's requested size. | |
4675 | */ | |
4676 | I915_WRITE(DSPSIZE(plane), | |
4677 | ((intel_crtc->config.pipe_src_h - 1) << 16) | | |
4678 | (intel_crtc->config.pipe_src_w - 1)); | |
4679 | I915_WRITE(DSPPOS(plane), 0); | |
4680 | ||
4681 | i9xx_set_pipeconf(intel_crtc); | |
4682 | ||
4683 | I915_WRITE(DSPCNTR(plane), dspcntr); | |
4684 | POSTING_READ(DSPCNTR(plane)); | |
4685 | ||
4686 | dev_priv->display.update_primary_plane(crtc, crtc->primary->fb, | |
4687 | crtc->x, crtc->y); | |
4688 | ||
f7abfe8b | 4689 | intel_crtc->active = true; |
6b383a7f | 4690 | |
4a3436e8 VS |
4691 | if (!IS_GEN2(dev)) |
4692 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
4693 | ||
9d6d9f19 MK |
4694 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4695 | if (encoder->pre_enable) | |
4696 | encoder->pre_enable(encoder); | |
4697 | ||
f6736a1a DV |
4698 | i9xx_enable_pll(intel_crtc); |
4699 | ||
2dd24552 JB |
4700 | i9xx_pfit_enable(intel_crtc); |
4701 | ||
63cbb074 VS |
4702 | intel_crtc_load_lut(crtc); |
4703 | ||
f37fcc2a | 4704 | intel_update_watermarks(crtc); |
e1fdc473 | 4705 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 4706 | |
fa5c73b1 DV |
4707 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4708 | encoder->enable(encoder); | |
9ab0460b VS |
4709 | |
4710 | intel_crtc_enable_planes(crtc); | |
d40d9187 | 4711 | |
4a3436e8 VS |
4712 | /* |
4713 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4714 | * So don't enable underrun reporting before at least some planes | |
4715 | * are enabled. | |
4716 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4717 | * but leave the pipe running. | |
4718 | */ | |
4719 | if (IS_GEN2(dev)) | |
4720 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
4721 | ||
87b6b101 | 4722 | drm_crtc_vblank_on(crtc); |
56b80e1f VS |
4723 | |
4724 | /* Underruns don't raise interrupts, so check manually. */ | |
4725 | i9xx_check_fifo_underruns(dev); | |
0b8765c6 | 4726 | } |
79e53945 | 4727 | |
87476d63 DV |
4728 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
4729 | { | |
4730 | struct drm_device *dev = crtc->base.dev; | |
4731 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 4732 | |
328d8e82 DV |
4733 | if (!crtc->config.gmch_pfit.control) |
4734 | return; | |
87476d63 | 4735 | |
328d8e82 | 4736 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 4737 | |
328d8e82 DV |
4738 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
4739 | I915_READ(PFIT_CONTROL)); | |
4740 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
4741 | } |
4742 | ||
0b8765c6 JB |
4743 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
4744 | { | |
4745 | struct drm_device *dev = crtc->dev; | |
4746 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4747 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4748 | struct intel_encoder *encoder; |
0b8765c6 | 4749 | int pipe = intel_crtc->pipe; |
ef9c3aee | 4750 | |
f7abfe8b CW |
4751 | if (!intel_crtc->active) |
4752 | return; | |
4753 | ||
4a3436e8 VS |
4754 | /* |
4755 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4756 | * So diasble underrun reporting before all the planes get disabled. | |
4757 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4758 | * but leave the pipe running. | |
4759 | */ | |
4760 | if (IS_GEN2(dev)) | |
4761 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false); | |
4762 | ||
9ab0460b VS |
4763 | intel_crtc_disable_planes(crtc); |
4764 | ||
ea9d758d DV |
4765 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4766 | encoder->disable(encoder); | |
4767 | ||
6304cd91 VS |
4768 | /* |
4769 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
4770 | * wait for planes to fully turn off before disabling the pipe. | |
4771 | */ | |
4772 | if (IS_GEN2(dev)) | |
4773 | intel_wait_for_vblank(dev, pipe); | |
4774 | ||
b24e7179 | 4775 | intel_disable_pipe(dev_priv, pipe); |
24a1f16d | 4776 | |
87476d63 | 4777 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 4778 | |
89b667f8 JB |
4779 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4780 | if (encoder->post_disable) | |
4781 | encoder->post_disable(encoder); | |
4782 | ||
076ed3b2 CML |
4783 | if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) { |
4784 | if (IS_CHERRYVIEW(dev)) | |
4785 | chv_disable_pll(dev_priv, pipe); | |
4786 | else if (IS_VALLEYVIEW(dev)) | |
4787 | vlv_disable_pll(dev_priv, pipe); | |
4788 | else | |
4789 | i9xx_disable_pll(dev_priv, pipe); | |
4790 | } | |
0b8765c6 | 4791 | |
4a3436e8 VS |
4792 | if (!IS_GEN2(dev)) |
4793 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false); | |
4794 | ||
f7abfe8b | 4795 | intel_crtc->active = false; |
46ba614c | 4796 | intel_update_watermarks(crtc); |
f37fcc2a | 4797 | |
efa9624e | 4798 | mutex_lock(&dev->struct_mutex); |
6b383a7f | 4799 | intel_update_fbc(dev); |
71b1c373 | 4800 | intel_edp_psr_update(dev); |
efa9624e | 4801 | mutex_unlock(&dev->struct_mutex); |
0b8765c6 JB |
4802 | } |
4803 | ||
ee7b9f93 JB |
4804 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
4805 | { | |
4806 | } | |
4807 | ||
976f8a20 DV |
4808 | static void intel_crtc_update_sarea(struct drm_crtc *crtc, |
4809 | bool enabled) | |
2c07245f ZW |
4810 | { |
4811 | struct drm_device *dev = crtc->dev; | |
4812 | struct drm_i915_master_private *master_priv; | |
4813 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4814 | int pipe = intel_crtc->pipe; | |
79e53945 JB |
4815 | |
4816 | if (!dev->primary->master) | |
4817 | return; | |
4818 | ||
4819 | master_priv = dev->primary->master->driver_priv; | |
4820 | if (!master_priv->sarea_priv) | |
4821 | return; | |
4822 | ||
79e53945 JB |
4823 | switch (pipe) { |
4824 | case 0: | |
4825 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; | |
4826 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; | |
4827 | break; | |
4828 | case 1: | |
4829 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; | |
4830 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; | |
4831 | break; | |
4832 | default: | |
9db4a9c7 | 4833 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
79e53945 JB |
4834 | break; |
4835 | } | |
79e53945 JB |
4836 | } |
4837 | ||
976f8a20 DV |
4838 | /** |
4839 | * Sets the power management mode of the pipe and plane. | |
4840 | */ | |
4841 | void intel_crtc_update_dpms(struct drm_crtc *crtc) | |
4842 | { | |
4843 | struct drm_device *dev = crtc->dev; | |
4844 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4845 | struct intel_encoder *intel_encoder; | |
4846 | bool enable = false; | |
4847 | ||
4848 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) | |
4849 | enable |= intel_encoder->connectors_active; | |
4850 | ||
4851 | if (enable) | |
4852 | dev_priv->display.crtc_enable(crtc); | |
4853 | else | |
4854 | dev_priv->display.crtc_disable(crtc); | |
4855 | ||
4856 | intel_crtc_update_sarea(crtc, enable); | |
4857 | } | |
4858 | ||
cdd59983 CW |
4859 | static void intel_crtc_disable(struct drm_crtc *crtc) |
4860 | { | |
cdd59983 | 4861 | struct drm_device *dev = crtc->dev; |
976f8a20 | 4862 | struct drm_connector *connector; |
ee7b9f93 | 4863 | struct drm_i915_private *dev_priv = dev->dev_private; |
cdd59983 | 4864 | |
976f8a20 DV |
4865 | /* crtc should still be enabled when we disable it. */ |
4866 | WARN_ON(!crtc->enabled); | |
4867 | ||
4868 | dev_priv->display.crtc_disable(crtc); | |
4869 | intel_crtc_update_sarea(crtc, false); | |
ee7b9f93 JB |
4870 | dev_priv->display.off(crtc); |
4871 | ||
931872fc | 4872 | assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); |
93ce0ba6 | 4873 | assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe); |
931872fc | 4874 | assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); |
cdd59983 | 4875 | |
f4510a27 | 4876 | if (crtc->primary->fb) { |
cdd59983 | 4877 | mutex_lock(&dev->struct_mutex); |
f4510a27 | 4878 | intel_unpin_fb_obj(to_intel_framebuffer(crtc->primary->fb)->obj); |
cdd59983 | 4879 | mutex_unlock(&dev->struct_mutex); |
f4510a27 | 4880 | crtc->primary->fb = NULL; |
976f8a20 DV |
4881 | } |
4882 | ||
4883 | /* Update computed state. */ | |
4884 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4885 | if (!connector->encoder || !connector->encoder->crtc) | |
4886 | continue; | |
4887 | ||
4888 | if (connector->encoder->crtc != crtc) | |
4889 | continue; | |
4890 | ||
4891 | connector->dpms = DRM_MODE_DPMS_OFF; | |
4892 | to_intel_encoder(connector->encoder)->connectors_active = false; | |
cdd59983 CW |
4893 | } |
4894 | } | |
4895 | ||
ea5b213a | 4896 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 4897 | { |
4ef69c7a | 4898 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 4899 | |
ea5b213a CW |
4900 | drm_encoder_cleanup(encoder); |
4901 | kfree(intel_encoder); | |
7e7d76c3 JB |
4902 | } |
4903 | ||
9237329d | 4904 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
5ab432ef DV |
4905 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
4906 | * state of the entire output pipe. */ | |
9237329d | 4907 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
7e7d76c3 | 4908 | { |
5ab432ef DV |
4909 | if (mode == DRM_MODE_DPMS_ON) { |
4910 | encoder->connectors_active = true; | |
4911 | ||
b2cabb0e | 4912 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef DV |
4913 | } else { |
4914 | encoder->connectors_active = false; | |
4915 | ||
b2cabb0e | 4916 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef | 4917 | } |
79e53945 JB |
4918 | } |
4919 | ||
0a91ca29 DV |
4920 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
4921 | * internal consistency). */ | |
b980514c | 4922 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 4923 | { |
0a91ca29 DV |
4924 | if (connector->get_hw_state(connector)) { |
4925 | struct intel_encoder *encoder = connector->encoder; | |
4926 | struct drm_crtc *crtc; | |
4927 | bool encoder_enabled; | |
4928 | enum pipe pipe; | |
4929 | ||
4930 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
4931 | connector->base.base.id, | |
4932 | drm_get_connector_name(&connector->base)); | |
4933 | ||
4934 | WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, | |
4935 | "wrong connector dpms state\n"); | |
4936 | WARN(connector->base.encoder != &encoder->base, | |
4937 | "active connector not linked to encoder\n"); | |
4938 | WARN(!encoder->connectors_active, | |
4939 | "encoder->connectors_active not set\n"); | |
4940 | ||
4941 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); | |
4942 | WARN(!encoder_enabled, "encoder not enabled\n"); | |
4943 | if (WARN_ON(!encoder->base.crtc)) | |
4944 | return; | |
4945 | ||
4946 | crtc = encoder->base.crtc; | |
4947 | ||
4948 | WARN(!crtc->enabled, "crtc not enabled\n"); | |
4949 | WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); | |
4950 | WARN(pipe != to_intel_crtc(crtc)->pipe, | |
4951 | "encoder active on the wrong pipe\n"); | |
4952 | } | |
79e53945 JB |
4953 | } |
4954 | ||
5ab432ef DV |
4955 | /* Even simpler default implementation, if there's really no special case to |
4956 | * consider. */ | |
4957 | void intel_connector_dpms(struct drm_connector *connector, int mode) | |
79e53945 | 4958 | { |
5ab432ef DV |
4959 | /* All the simple cases only support two dpms states. */ |
4960 | if (mode != DRM_MODE_DPMS_ON) | |
4961 | mode = DRM_MODE_DPMS_OFF; | |
d4270e57 | 4962 | |
5ab432ef DV |
4963 | if (mode == connector->dpms) |
4964 | return; | |
4965 | ||
4966 | connector->dpms = mode; | |
4967 | ||
4968 | /* Only need to change hw state when actually enabled */ | |
c9976dcf CW |
4969 | if (connector->encoder) |
4970 | intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); | |
0a91ca29 | 4971 | |
b980514c | 4972 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
4973 | } |
4974 | ||
f0947c37 DV |
4975 | /* Simple connector->get_hw_state implementation for encoders that support only |
4976 | * one connector and no cloning and hence the encoder state determines the state | |
4977 | * of the connector. */ | |
4978 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 4979 | { |
24929352 | 4980 | enum pipe pipe = 0; |
f0947c37 | 4981 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 4982 | |
f0947c37 | 4983 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
4984 | } |
4985 | ||
1857e1da DV |
4986 | static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
4987 | struct intel_crtc_config *pipe_config) | |
4988 | { | |
4989 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4990 | struct intel_crtc *pipe_B_crtc = | |
4991 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
4992 | ||
4993 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", | |
4994 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4995 | if (pipe_config->fdi_lanes > 4) { | |
4996 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
4997 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4998 | return false; | |
4999 | } | |
5000 | ||
bafb6553 | 5001 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
5002 | if (pipe_config->fdi_lanes > 2) { |
5003 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
5004 | pipe_config->fdi_lanes); | |
5005 | return false; | |
5006 | } else { | |
5007 | return true; | |
5008 | } | |
5009 | } | |
5010 | ||
5011 | if (INTEL_INFO(dev)->num_pipes == 2) | |
5012 | return true; | |
5013 | ||
5014 | /* Ivybridge 3 pipe is really complicated */ | |
5015 | switch (pipe) { | |
5016 | case PIPE_A: | |
5017 | return true; | |
5018 | case PIPE_B: | |
5019 | if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled && | |
5020 | pipe_config->fdi_lanes > 2) { | |
5021 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
5022 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5023 | return false; | |
5024 | } | |
5025 | return true; | |
5026 | case PIPE_C: | |
1e833f40 | 5027 | if (!pipe_has_enabled_pch(pipe_B_crtc) || |
1857e1da DV |
5028 | pipe_B_crtc->config.fdi_lanes <= 2) { |
5029 | if (pipe_config->fdi_lanes > 2) { | |
5030 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
5031 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5032 | return false; | |
5033 | } | |
5034 | } else { | |
5035 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); | |
5036 | return false; | |
5037 | } | |
5038 | return true; | |
5039 | default: | |
5040 | BUG(); | |
5041 | } | |
5042 | } | |
5043 | ||
e29c22c0 DV |
5044 | #define RETRY 1 |
5045 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5046 | struct intel_crtc_config *pipe_config) | |
877d48d5 | 5047 | { |
1857e1da | 5048 | struct drm_device *dev = intel_crtc->base.dev; |
877d48d5 | 5049 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
ff9a6750 | 5050 | int lane, link_bw, fdi_dotclock; |
e29c22c0 | 5051 | bool setup_ok, needs_recompute = false; |
877d48d5 | 5052 | |
e29c22c0 | 5053 | retry: |
877d48d5 DV |
5054 | /* FDI is a binary signal running at ~2.7GHz, encoding |
5055 | * each output octet as 10 bits. The actual frequency | |
5056 | * is stored as a divider into a 100MHz clock, and the | |
5057 | * mode pixel clock is stored in units of 1KHz. | |
5058 | * Hence the bw of each lane in terms of the mode signal | |
5059 | * is: | |
5060 | */ | |
5061 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
5062 | ||
241bfc38 | 5063 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 5064 | |
2bd89a07 | 5065 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
5066 | pipe_config->pipe_bpp); |
5067 | ||
5068 | pipe_config->fdi_lanes = lane; | |
5069 | ||
2bd89a07 | 5070 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 5071 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 5072 | |
e29c22c0 DV |
5073 | setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
5074 | intel_crtc->pipe, pipe_config); | |
5075 | if (!setup_ok && pipe_config->pipe_bpp > 6*3) { | |
5076 | pipe_config->pipe_bpp -= 2*3; | |
5077 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
5078 | pipe_config->pipe_bpp); | |
5079 | needs_recompute = true; | |
5080 | pipe_config->bw_constrained = true; | |
5081 | ||
5082 | goto retry; | |
5083 | } | |
5084 | ||
5085 | if (needs_recompute) | |
5086 | return RETRY; | |
5087 | ||
5088 | return setup_ok ? 0 : -EINVAL; | |
877d48d5 DV |
5089 | } |
5090 | ||
42db64ef PZ |
5091 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5092 | struct intel_crtc_config *pipe_config) | |
5093 | { | |
d330a953 | 5094 | pipe_config->ips_enabled = i915.enable_ips && |
3c4ca58c | 5095 | hsw_crtc_supports_ips(crtc) && |
b6dfdc9b | 5096 | pipe_config->pipe_bpp <= 24; |
42db64ef PZ |
5097 | } |
5098 | ||
a43f6e0f | 5099 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
e29c22c0 | 5100 | struct intel_crtc_config *pipe_config) |
79e53945 | 5101 | { |
a43f6e0f | 5102 | struct drm_device *dev = crtc->base.dev; |
b8cecdf5 | 5103 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
89749350 | 5104 | |
ad3a4479 | 5105 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 VS |
5106 | if (INTEL_INFO(dev)->gen < 4) { |
5107 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5108 | int clock_limit = | |
5109 | dev_priv->display.get_display_clock_speed(dev); | |
5110 | ||
5111 | /* | |
5112 | * Enable pixel doubling when the dot clock | |
5113 | * is > 90% of the (display) core speed. | |
5114 | * | |
b397c96b VS |
5115 | * GDG double wide on either pipe, |
5116 | * otherwise pipe A only. | |
cf532bb2 | 5117 | */ |
b397c96b | 5118 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
241bfc38 | 5119 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
ad3a4479 | 5120 | clock_limit *= 2; |
cf532bb2 | 5121 | pipe_config->double_wide = true; |
ad3a4479 VS |
5122 | } |
5123 | ||
241bfc38 | 5124 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
e29c22c0 | 5125 | return -EINVAL; |
2c07245f | 5126 | } |
89749350 | 5127 | |
1d1d0e27 VS |
5128 | /* |
5129 | * Pipe horizontal size must be even in: | |
5130 | * - DVO ganged mode | |
5131 | * - LVDS dual channel mode | |
5132 | * - Double wide pipe | |
5133 | */ | |
5134 | if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && | |
5135 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) | |
5136 | pipe_config->pipe_src_w &= ~1; | |
5137 | ||
8693a824 DL |
5138 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
5139 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
5140 | */ |
5141 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
5142 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | |
e29c22c0 | 5143 | return -EINVAL; |
44f46b42 | 5144 | |
bd080ee5 | 5145 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { |
5d2d38dd | 5146 | pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ |
bd080ee5 | 5147 | } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { |
5d2d38dd DV |
5148 | /* only a 8bpc pipe, with 6bpc dither through the panel fitter |
5149 | * for lvds. */ | |
5150 | pipe_config->pipe_bpp = 8*3; | |
5151 | } | |
5152 | ||
f5adf94e | 5153 | if (HAS_IPS(dev)) |
a43f6e0f DV |
5154 | hsw_compute_ips_config(crtc, pipe_config); |
5155 | ||
5156 | /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old | |
5157 | * clock survives for now. */ | |
5158 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
5159 | pipe_config->shared_dpll = crtc->config.shared_dpll; | |
42db64ef | 5160 | |
877d48d5 | 5161 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 5162 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 5163 | |
e29c22c0 | 5164 | return 0; |
79e53945 JB |
5165 | } |
5166 | ||
25eb05fc JB |
5167 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
5168 | { | |
5169 | return 400000; /* FIXME */ | |
5170 | } | |
5171 | ||
e70236a8 JB |
5172 | static int i945_get_display_clock_speed(struct drm_device *dev) |
5173 | { | |
5174 | return 400000; | |
5175 | } | |
79e53945 | 5176 | |
e70236a8 | 5177 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 5178 | { |
e70236a8 JB |
5179 | return 333000; |
5180 | } | |
79e53945 | 5181 | |
e70236a8 JB |
5182 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
5183 | { | |
5184 | return 200000; | |
5185 | } | |
79e53945 | 5186 | |
257a7ffc DV |
5187 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
5188 | { | |
5189 | u16 gcfgc = 0; | |
5190 | ||
5191 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
5192 | ||
5193 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
5194 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
5195 | return 267000; | |
5196 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: | |
5197 | return 333000; | |
5198 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: | |
5199 | return 444000; | |
5200 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: | |
5201 | return 200000; | |
5202 | default: | |
5203 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
5204 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
5205 | return 133000; | |
5206 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: | |
5207 | return 167000; | |
5208 | } | |
5209 | } | |
5210 | ||
e70236a8 JB |
5211 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
5212 | { | |
5213 | u16 gcfgc = 0; | |
79e53945 | 5214 | |
e70236a8 JB |
5215 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
5216 | ||
5217 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
5218 | return 133000; | |
5219 | else { | |
5220 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
5221 | case GC_DISPLAY_CLOCK_333_MHZ: | |
5222 | return 333000; | |
5223 | default: | |
5224 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
5225 | return 190000; | |
79e53945 | 5226 | } |
e70236a8 JB |
5227 | } |
5228 | } | |
5229 | ||
5230 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
5231 | { | |
5232 | return 266000; | |
5233 | } | |
5234 | ||
5235 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
5236 | { | |
5237 | u16 hpllcc = 0; | |
5238 | /* Assume that the hardware is in the high speed state. This | |
5239 | * should be the default. | |
5240 | */ | |
5241 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
5242 | case GC_CLOCK_133_200: | |
5243 | case GC_CLOCK_100_200: | |
5244 | return 200000; | |
5245 | case GC_CLOCK_166_250: | |
5246 | return 250000; | |
5247 | case GC_CLOCK_100_133: | |
79e53945 | 5248 | return 133000; |
e70236a8 | 5249 | } |
79e53945 | 5250 | |
e70236a8 JB |
5251 | /* Shouldn't happen */ |
5252 | return 0; | |
5253 | } | |
79e53945 | 5254 | |
e70236a8 JB |
5255 | static int i830_get_display_clock_speed(struct drm_device *dev) |
5256 | { | |
5257 | return 133000; | |
79e53945 JB |
5258 | } |
5259 | ||
2c07245f | 5260 | static void |
a65851af | 5261 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 5262 | { |
a65851af VS |
5263 | while (*num > DATA_LINK_M_N_MASK || |
5264 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
5265 | *num >>= 1; |
5266 | *den >>= 1; | |
5267 | } | |
5268 | } | |
5269 | ||
a65851af VS |
5270 | static void compute_m_n(unsigned int m, unsigned int n, |
5271 | uint32_t *ret_m, uint32_t *ret_n) | |
5272 | { | |
5273 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
5274 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
5275 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
5276 | } | |
5277 | ||
e69d0bc1 DV |
5278 | void |
5279 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
5280 | int pixel_clock, int link_clock, | |
5281 | struct intel_link_m_n *m_n) | |
2c07245f | 5282 | { |
e69d0bc1 | 5283 | m_n->tu = 64; |
a65851af VS |
5284 | |
5285 | compute_m_n(bits_per_pixel * pixel_clock, | |
5286 | link_clock * nlanes * 8, | |
5287 | &m_n->gmch_m, &m_n->gmch_n); | |
5288 | ||
5289 | compute_m_n(pixel_clock, link_clock, | |
5290 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
5291 | } |
5292 | ||
a7615030 CW |
5293 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
5294 | { | |
d330a953 JN |
5295 | if (i915.panel_use_ssc >= 0) |
5296 | return i915.panel_use_ssc != 0; | |
41aa3448 | 5297 | return dev_priv->vbt.lvds_use_ssc |
435793df | 5298 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
5299 | } |
5300 | ||
c65d77d8 JB |
5301 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
5302 | { | |
5303 | struct drm_device *dev = crtc->dev; | |
5304 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5305 | int refclk; | |
5306 | ||
a0c4da24 | 5307 | if (IS_VALLEYVIEW(dev)) { |
9a0ea498 | 5308 | refclk = 100000; |
a0c4da24 | 5309 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 5310 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
5311 | refclk = dev_priv->vbt.lvds_ssc_freq; |
5312 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
5313 | } else if (!IS_GEN2(dev)) { |
5314 | refclk = 96000; | |
5315 | } else { | |
5316 | refclk = 48000; | |
5317 | } | |
5318 | ||
5319 | return refclk; | |
5320 | } | |
5321 | ||
7429e9d4 | 5322 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 5323 | { |
7df00d7a | 5324 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 5325 | } |
f47709a9 | 5326 | |
7429e9d4 DV |
5327 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
5328 | { | |
5329 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
5330 | } |
5331 | ||
f47709a9 | 5332 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
a7516a05 JB |
5333 | intel_clock_t *reduced_clock) |
5334 | { | |
f47709a9 | 5335 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
5336 | u32 fp, fp2 = 0; |
5337 | ||
5338 | if (IS_PINEVIEW(dev)) { | |
7429e9d4 | 5339 | fp = pnv_dpll_compute_fp(&crtc->config.dpll); |
a7516a05 | 5340 | if (reduced_clock) |
7429e9d4 | 5341 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 5342 | } else { |
7429e9d4 | 5343 | fp = i9xx_dpll_compute_fp(&crtc->config.dpll); |
a7516a05 | 5344 | if (reduced_clock) |
7429e9d4 | 5345 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
5346 | } |
5347 | ||
8bcc2795 | 5348 | crtc->config.dpll_hw_state.fp0 = fp; |
a7516a05 | 5349 | |
f47709a9 DV |
5350 | crtc->lowfreq_avail = false; |
5351 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && | |
d330a953 | 5352 | reduced_clock && i915.powersave) { |
8bcc2795 | 5353 | crtc->config.dpll_hw_state.fp1 = fp2; |
f47709a9 | 5354 | crtc->lowfreq_avail = true; |
a7516a05 | 5355 | } else { |
8bcc2795 | 5356 | crtc->config.dpll_hw_state.fp1 = fp; |
a7516a05 JB |
5357 | } |
5358 | } | |
5359 | ||
5e69f97f CML |
5360 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
5361 | pipe) | |
89b667f8 JB |
5362 | { |
5363 | u32 reg_val; | |
5364 | ||
5365 | /* | |
5366 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
5367 | * and set it to a reasonable value instead. | |
5368 | */ | |
ab3c759a | 5369 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
5370 | reg_val &= 0xffffff00; |
5371 | reg_val |= 0x00000030; | |
ab3c759a | 5372 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 5373 | |
ab3c759a | 5374 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
5375 | reg_val &= 0x8cffffff; |
5376 | reg_val = 0x8c000000; | |
ab3c759a | 5377 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 5378 | |
ab3c759a | 5379 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 5380 | reg_val &= 0xffffff00; |
ab3c759a | 5381 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 5382 | |
ab3c759a | 5383 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
5384 | reg_val &= 0x00ffffff; |
5385 | reg_val |= 0xb0000000; | |
ab3c759a | 5386 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
5387 | } |
5388 | ||
b551842d DV |
5389 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
5390 | struct intel_link_m_n *m_n) | |
5391 | { | |
5392 | struct drm_device *dev = crtc->base.dev; | |
5393 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5394 | int pipe = crtc->pipe; | |
5395 | ||
e3b95f1e DV |
5396 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
5397 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
5398 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
5399 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
5400 | } |
5401 | ||
5402 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
5403 | struct intel_link_m_n *m_n) | |
5404 | { | |
5405 | struct drm_device *dev = crtc->base.dev; | |
5406 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5407 | int pipe = crtc->pipe; | |
5408 | enum transcoder transcoder = crtc->config.cpu_transcoder; | |
5409 | ||
5410 | if (INTEL_INFO(dev)->gen >= 5) { | |
5411 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
5412 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
5413 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
5414 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
5415 | } else { | |
e3b95f1e DV |
5416 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
5417 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
5418 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
5419 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
5420 | } |
5421 | } | |
5422 | ||
03afc4a2 DV |
5423 | static void intel_dp_set_m_n(struct intel_crtc *crtc) |
5424 | { | |
5425 | if (crtc->config.has_pch_encoder) | |
5426 | intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); | |
5427 | else | |
5428 | intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); | |
5429 | } | |
5430 | ||
f47709a9 | 5431 | static void vlv_update_pll(struct intel_crtc *crtc) |
bdd4b6a6 DV |
5432 | { |
5433 | u32 dpll, dpll_md; | |
5434 | ||
5435 | /* | |
5436 | * Enable DPIO clock input. We should never disable the reference | |
5437 | * clock for pipe B, since VGA hotplug / manual detection depends | |
5438 | * on it. | |
5439 | */ | |
5440 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | | |
5441 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; | |
5442 | /* We should never disable this, set it here for state tracking */ | |
5443 | if (crtc->pipe == PIPE_B) | |
5444 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
5445 | dpll |= DPLL_VCO_ENABLE; | |
5446 | crtc->config.dpll_hw_state.dpll = dpll; | |
5447 | ||
5448 | dpll_md = (crtc->config.pixel_multiplier - 1) | |
5449 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
5450 | crtc->config.dpll_hw_state.dpll_md = dpll_md; | |
5451 | } | |
5452 | ||
5453 | static void vlv_prepare_pll(struct intel_crtc *crtc) | |
a0c4da24 | 5454 | { |
f47709a9 | 5455 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 5456 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 5457 | int pipe = crtc->pipe; |
bdd4b6a6 | 5458 | u32 mdiv; |
a0c4da24 | 5459 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 5460 | u32 coreclk, reg_val; |
a0c4da24 | 5461 | |
09153000 DV |
5462 | mutex_lock(&dev_priv->dpio_lock); |
5463 | ||
f47709a9 DV |
5464 | bestn = crtc->config.dpll.n; |
5465 | bestm1 = crtc->config.dpll.m1; | |
5466 | bestm2 = crtc->config.dpll.m2; | |
5467 | bestp1 = crtc->config.dpll.p1; | |
5468 | bestp2 = crtc->config.dpll.p2; | |
a0c4da24 | 5469 | |
89b667f8 JB |
5470 | /* See eDP HDMI DPIO driver vbios notes doc */ |
5471 | ||
5472 | /* PLL B needs special handling */ | |
bdd4b6a6 | 5473 | if (pipe == PIPE_B) |
5e69f97f | 5474 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
5475 | |
5476 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 5477 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
5478 | |
5479 | /* Disable target IRef on PLL */ | |
ab3c759a | 5480 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 5481 | reg_val &= 0x00ffffff; |
ab3c759a | 5482 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
5483 | |
5484 | /* Disable fast lock */ | |
ab3c759a | 5485 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
5486 | |
5487 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
5488 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
5489 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
5490 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 5491 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
5492 | |
5493 | /* | |
5494 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
5495 | * but we don't support that). | |
5496 | * Note: don't use the DAC post divider as it seems unstable. | |
5497 | */ | |
5498 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 5499 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 5500 | |
a0c4da24 | 5501 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 5502 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 5503 | |
89b667f8 | 5504 | /* Set HBR and RBR LPF coefficients */ |
ff9a6750 | 5505 | if (crtc->config.port_clock == 162000 || |
99750bd4 | 5506 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) || |
89b667f8 | 5507 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) |
ab3c759a | 5508 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 5509 | 0x009f0003); |
89b667f8 | 5510 | else |
ab3c759a | 5511 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
5512 | 0x00d0000f); |
5513 | ||
5514 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) || | |
5515 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) { | |
5516 | /* Use SSC source */ | |
bdd4b6a6 | 5517 | if (pipe == PIPE_A) |
ab3c759a | 5518 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5519 | 0x0df40000); |
5520 | else | |
ab3c759a | 5521 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5522 | 0x0df70000); |
5523 | } else { /* HDMI or VGA */ | |
5524 | /* Use bend source */ | |
bdd4b6a6 | 5525 | if (pipe == PIPE_A) |
ab3c759a | 5526 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5527 | 0x0df70000); |
5528 | else | |
ab3c759a | 5529 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5530 | 0x0df40000); |
5531 | } | |
a0c4da24 | 5532 | |
ab3c759a | 5533 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 JB |
5534 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
5535 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) || | |
5536 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) | |
5537 | coreclk |= 0x01000000; | |
ab3c759a | 5538 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 5539 | |
ab3c759a | 5540 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
09153000 | 5541 | mutex_unlock(&dev_priv->dpio_lock); |
a0c4da24 JB |
5542 | } |
5543 | ||
9d556c99 CML |
5544 | static void chv_update_pll(struct intel_crtc *crtc) |
5545 | { | |
5546 | struct drm_device *dev = crtc->base.dev; | |
5547 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5548 | int pipe = crtc->pipe; | |
5549 | int dpll_reg = DPLL(crtc->pipe); | |
5550 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
580d3811 | 5551 | u32 loopfilter, intcoeff; |
9d556c99 CML |
5552 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
5553 | int refclk; | |
5554 | ||
a11b0703 VS |
5555 | crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV | |
5556 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | | |
5557 | DPLL_VCO_ENABLE; | |
5558 | if (pipe != PIPE_A) | |
5559 | crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
5560 | ||
5561 | crtc->config.dpll_hw_state.dpll_md = | |
5562 | (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
9d556c99 CML |
5563 | |
5564 | bestn = crtc->config.dpll.n; | |
5565 | bestm2_frac = crtc->config.dpll.m2 & 0x3fffff; | |
5566 | bestm1 = crtc->config.dpll.m1; | |
5567 | bestm2 = crtc->config.dpll.m2 >> 22; | |
5568 | bestp1 = crtc->config.dpll.p1; | |
5569 | bestp2 = crtc->config.dpll.p2; | |
5570 | ||
5571 | /* | |
5572 | * Enable Refclk and SSC | |
5573 | */ | |
a11b0703 VS |
5574 | I915_WRITE(dpll_reg, |
5575 | crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); | |
5576 | ||
5577 | mutex_lock(&dev_priv->dpio_lock); | |
9d556c99 | 5578 | |
9d556c99 CML |
5579 | /* p1 and p2 divider */ |
5580 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
5581 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
5582 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
5583 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
5584 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
5585 | ||
5586 | /* Feedback post-divider - m2 */ | |
5587 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
5588 | ||
5589 | /* Feedback refclk divider - n and m1 */ | |
5590 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
5591 | DPIO_CHV_M1_DIV_BY_2 | | |
5592 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
5593 | ||
5594 | /* M2 fraction division */ | |
5595 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); | |
5596 | ||
5597 | /* M2 fraction division enable */ | |
5598 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), | |
5599 | DPIO_CHV_FRAC_DIV_EN | | |
5600 | (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT)); | |
5601 | ||
5602 | /* Loop filter */ | |
5603 | refclk = i9xx_get_refclk(&crtc->base, 0); | |
5604 | loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT | | |
5605 | 2 << DPIO_CHV_GAIN_CTRL_SHIFT; | |
5606 | if (refclk == 100000) | |
5607 | intcoeff = 11; | |
5608 | else if (refclk == 38400) | |
5609 | intcoeff = 10; | |
5610 | else | |
5611 | intcoeff = 9; | |
5612 | loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT; | |
5613 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); | |
5614 | ||
5615 | /* AFC Recal */ | |
5616 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
5617 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
5618 | DPIO_AFC_RECAL); | |
5619 | ||
5620 | mutex_unlock(&dev_priv->dpio_lock); | |
5621 | } | |
5622 | ||
f47709a9 DV |
5623 | static void i9xx_update_pll(struct intel_crtc *crtc, |
5624 | intel_clock_t *reduced_clock, | |
eb1cbe48 DV |
5625 | int num_connectors) |
5626 | { | |
f47709a9 | 5627 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 5628 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
5629 | u32 dpll; |
5630 | bool is_sdvo; | |
f47709a9 | 5631 | struct dpll *clock = &crtc->config.dpll; |
eb1cbe48 | 5632 | |
f47709a9 | 5633 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 5634 | |
f47709a9 DV |
5635 | is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) || |
5636 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
5637 | |
5638 | dpll = DPLL_VGA_MODE_DIS; | |
5639 | ||
f47709a9 | 5640 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
5641 | dpll |= DPLLB_MODE_LVDS; |
5642 | else | |
5643 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 5644 | |
ef1b460d | 5645 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
198a037f DV |
5646 | dpll |= (crtc->config.pixel_multiplier - 1) |
5647 | << SDVO_MULTIPLIER_SHIFT_HIRES; | |
eb1cbe48 | 5648 | } |
198a037f DV |
5649 | |
5650 | if (is_sdvo) | |
4a33e48d | 5651 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 5652 | |
f47709a9 | 5653 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) |
4a33e48d | 5654 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
5655 | |
5656 | /* compute bitmask from p1 value */ | |
5657 | if (IS_PINEVIEW(dev)) | |
5658 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
5659 | else { | |
5660 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5661 | if (IS_G4X(dev) && reduced_clock) | |
5662 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
5663 | } | |
5664 | switch (clock->p2) { | |
5665 | case 5: | |
5666 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
5667 | break; | |
5668 | case 7: | |
5669 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
5670 | break; | |
5671 | case 10: | |
5672 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
5673 | break; | |
5674 | case 14: | |
5675 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
5676 | break; | |
5677 | } | |
5678 | if (INTEL_INFO(dev)->gen >= 4) | |
5679 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
5680 | ||
09ede541 | 5681 | if (crtc->config.sdvo_tv_clock) |
eb1cbe48 | 5682 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
f47709a9 | 5683 | else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
5684 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
5685 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
5686 | else | |
5687 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5688 | ||
5689 | dpll |= DPLL_VCO_ENABLE; | |
8bcc2795 DV |
5690 | crtc->config.dpll_hw_state.dpll = dpll; |
5691 | ||
eb1cbe48 | 5692 | if (INTEL_INFO(dev)->gen >= 4) { |
ef1b460d DV |
5693 | u32 dpll_md = (crtc->config.pixel_multiplier - 1) |
5694 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
8bcc2795 | 5695 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
5696 | } |
5697 | } | |
5698 | ||
f47709a9 | 5699 | static void i8xx_update_pll(struct intel_crtc *crtc, |
f47709a9 | 5700 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
5701 | int num_connectors) |
5702 | { | |
f47709a9 | 5703 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 5704 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 5705 | u32 dpll; |
f47709a9 | 5706 | struct dpll *clock = &crtc->config.dpll; |
eb1cbe48 | 5707 | |
f47709a9 | 5708 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 5709 | |
eb1cbe48 DV |
5710 | dpll = DPLL_VGA_MODE_DIS; |
5711 | ||
f47709a9 | 5712 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
5713 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
5714 | } else { | |
5715 | if (clock->p1 == 2) | |
5716 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
5717 | else | |
5718 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5719 | if (clock->p2 == 4) | |
5720 | dpll |= PLL_P2_DIVIDE_BY_4; | |
5721 | } | |
5722 | ||
4a33e48d DV |
5723 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO)) |
5724 | dpll |= DPLL_DVO_2X_MODE; | |
5725 | ||
f47709a9 | 5726 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
5727 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
5728 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
5729 | else | |
5730 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5731 | ||
5732 | dpll |= DPLL_VCO_ENABLE; | |
8bcc2795 | 5733 | crtc->config.dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
5734 | } |
5735 | ||
8a654f3b | 5736 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
5737 | { |
5738 | struct drm_device *dev = intel_crtc->base.dev; | |
5739 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5740 | enum pipe pipe = intel_crtc->pipe; | |
3b117c8f | 5741 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
8a654f3b DV |
5742 | struct drm_display_mode *adjusted_mode = |
5743 | &intel_crtc->config.adjusted_mode; | |
1caea6e9 VS |
5744 | uint32_t crtc_vtotal, crtc_vblank_end; |
5745 | int vsyncshift = 0; | |
4d8a62ea DV |
5746 | |
5747 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
5748 | * the hw state checker will get angry at the mismatch. */ | |
5749 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
5750 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 5751 | |
609aeaca | 5752 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 5753 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
5754 | crtc_vtotal -= 1; |
5755 | crtc_vblank_end -= 1; | |
609aeaca VS |
5756 | |
5757 | if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO)) | |
5758 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; | |
5759 | else | |
5760 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
5761 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
5762 | if (vsyncshift < 0) |
5763 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
5764 | } |
5765 | ||
5766 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 5767 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 5768 | |
fe2b8f9d | 5769 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
5770 | (adjusted_mode->crtc_hdisplay - 1) | |
5771 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 5772 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
5773 | (adjusted_mode->crtc_hblank_start - 1) | |
5774 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 5775 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
5776 | (adjusted_mode->crtc_hsync_start - 1) | |
5777 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
5778 | ||
fe2b8f9d | 5779 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 5780 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 5781 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 5782 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 5783 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 5784 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 5785 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
5786 | (adjusted_mode->crtc_vsync_start - 1) | |
5787 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
5788 | ||
b5e508d4 PZ |
5789 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
5790 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
5791 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
5792 | * bits. */ | |
5793 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
5794 | (pipe == PIPE_B || pipe == PIPE_C)) | |
5795 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
5796 | ||
b0e77b9c PZ |
5797 | /* pipesrc controls the size that is scaled from, which should |
5798 | * always be the user's requested size. | |
5799 | */ | |
5800 | I915_WRITE(PIPESRC(pipe), | |
37327abd VS |
5801 | ((intel_crtc->config.pipe_src_w - 1) << 16) | |
5802 | (intel_crtc->config.pipe_src_h - 1)); | |
b0e77b9c PZ |
5803 | } |
5804 | ||
1bd1bd80 DV |
5805 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5806 | struct intel_crtc_config *pipe_config) | |
5807 | { | |
5808 | struct drm_device *dev = crtc->base.dev; | |
5809 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5810 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
5811 | uint32_t tmp; | |
5812 | ||
5813 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
5814 | pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; | |
5815 | pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
5816 | tmp = I915_READ(HBLANK(cpu_transcoder)); | |
5817 | pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; | |
5818 | pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
5819 | tmp = I915_READ(HSYNC(cpu_transcoder)); | |
5820 | pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; | |
5821 | pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
5822 | ||
5823 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
5824 | pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; | |
5825 | pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
5826 | tmp = I915_READ(VBLANK(cpu_transcoder)); | |
5827 | pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; | |
5828 | pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
5829 | tmp = I915_READ(VSYNC(cpu_transcoder)); | |
5830 | pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; | |
5831 | pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
5832 | ||
5833 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
5834 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; | |
5835 | pipe_config->adjusted_mode.crtc_vtotal += 1; | |
5836 | pipe_config->adjusted_mode.crtc_vblank_end += 1; | |
5837 | } | |
5838 | ||
5839 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
5840 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
5841 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
5842 | ||
5843 | pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h; | |
5844 | pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
5845 | } |
5846 | ||
f6a83288 DV |
5847 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5848 | struct intel_crtc_config *pipe_config) | |
babea61d | 5849 | { |
f6a83288 DV |
5850 | mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay; |
5851 | mode->htotal = pipe_config->adjusted_mode.crtc_htotal; | |
5852 | mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start; | |
5853 | mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end; | |
babea61d | 5854 | |
f6a83288 DV |
5855 | mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay; |
5856 | mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal; | |
5857 | mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start; | |
5858 | mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end; | |
babea61d | 5859 | |
f6a83288 | 5860 | mode->flags = pipe_config->adjusted_mode.flags; |
babea61d | 5861 | |
f6a83288 DV |
5862 | mode->clock = pipe_config->adjusted_mode.crtc_clock; |
5863 | mode->flags |= pipe_config->adjusted_mode.flags; | |
babea61d JB |
5864 | } |
5865 | ||
84b046f3 DV |
5866 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
5867 | { | |
5868 | struct drm_device *dev = intel_crtc->base.dev; | |
5869 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5870 | uint32_t pipeconf; | |
5871 | ||
9f11a9e4 | 5872 | pipeconf = 0; |
84b046f3 | 5873 | |
67c72a12 DV |
5874 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
5875 | I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE) | |
5876 | pipeconf |= PIPECONF_ENABLE; | |
5877 | ||
cf532bb2 VS |
5878 | if (intel_crtc->config.double_wide) |
5879 | pipeconf |= PIPECONF_DOUBLE_WIDE; | |
84b046f3 | 5880 | |
ff9ce46e DV |
5881 | /* only g4x and later have fancy bpc/dither controls */ |
5882 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { | |
ff9ce46e DV |
5883 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
5884 | if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30) | |
5885 | pipeconf |= PIPECONF_DITHER_EN | | |
84b046f3 | 5886 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 5887 | |
ff9ce46e DV |
5888 | switch (intel_crtc->config.pipe_bpp) { |
5889 | case 18: | |
5890 | pipeconf |= PIPECONF_6BPC; | |
5891 | break; | |
5892 | case 24: | |
5893 | pipeconf |= PIPECONF_8BPC; | |
5894 | break; | |
5895 | case 30: | |
5896 | pipeconf |= PIPECONF_10BPC; | |
5897 | break; | |
5898 | default: | |
5899 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
5900 | BUG(); | |
84b046f3 DV |
5901 | } |
5902 | } | |
5903 | ||
5904 | if (HAS_PIPE_CXSR(dev)) { | |
5905 | if (intel_crtc->lowfreq_avail) { | |
5906 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
5907 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
5908 | } else { | |
5909 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
5910 | } |
5911 | } | |
5912 | ||
efc2cfff VS |
5913 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
5914 | if (INTEL_INFO(dev)->gen < 4 || | |
5915 | intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO)) | |
5916 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; | |
5917 | else | |
5918 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
5919 | } else | |
84b046f3 DV |
5920 | pipeconf |= PIPECONF_PROGRESSIVE; |
5921 | ||
9f11a9e4 DV |
5922 | if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range) |
5923 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; | |
9c8e09b7 | 5924 | |
84b046f3 DV |
5925 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
5926 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
5927 | } | |
5928 | ||
f564048e | 5929 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
f564048e | 5930 | int x, int y, |
94352cf9 | 5931 | struct drm_framebuffer *fb) |
79e53945 JB |
5932 | { |
5933 | struct drm_device *dev = crtc->dev; | |
5934 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5935 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
c751ce4f | 5936 | int refclk, num_connectors = 0; |
652c393a | 5937 | intel_clock_t clock, reduced_clock; |
a16af721 | 5938 | bool ok, has_reduced_clock = false; |
e9fd1c02 | 5939 | bool is_lvds = false, is_dsi = false; |
5eddb70b | 5940 | struct intel_encoder *encoder; |
d4906093 | 5941 | const intel_limit_t *limit; |
79e53945 | 5942 | |
6c2b7c12 | 5943 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5eddb70b | 5944 | switch (encoder->type) { |
79e53945 JB |
5945 | case INTEL_OUTPUT_LVDS: |
5946 | is_lvds = true; | |
5947 | break; | |
e9fd1c02 JN |
5948 | case INTEL_OUTPUT_DSI: |
5949 | is_dsi = true; | |
5950 | break; | |
79e53945 | 5951 | } |
43565a06 | 5952 | |
c751ce4f | 5953 | num_connectors++; |
79e53945 JB |
5954 | } |
5955 | ||
f2335330 | 5956 | if (is_dsi) |
5b18e57c | 5957 | return 0; |
f2335330 JN |
5958 | |
5959 | if (!intel_crtc->config.clock_set) { | |
5960 | refclk = i9xx_get_refclk(crtc, num_connectors); | |
79e53945 | 5961 | |
e9fd1c02 JN |
5962 | /* |
5963 | * Returns a set of divisors for the desired target clock with | |
5964 | * the given refclk, or FALSE. The returned values represent | |
5965 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
5966 | * 2) / p1 / p2. | |
5967 | */ | |
5968 | limit = intel_limit(crtc, refclk); | |
5969 | ok = dev_priv->display.find_dpll(limit, crtc, | |
5970 | intel_crtc->config.port_clock, | |
5971 | refclk, NULL, &clock); | |
f2335330 | 5972 | if (!ok) { |
e9fd1c02 JN |
5973 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
5974 | return -EINVAL; | |
5975 | } | |
79e53945 | 5976 | |
f2335330 JN |
5977 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
5978 | /* | |
5979 | * Ensure we match the reduced clock's P to the target | |
5980 | * clock. If the clocks don't match, we can't switch | |
5981 | * the display clock by using the FP0/FP1. In such case | |
5982 | * we will disable the LVDS downclock feature. | |
5983 | */ | |
5984 | has_reduced_clock = | |
5985 | dev_priv->display.find_dpll(limit, crtc, | |
5986 | dev_priv->lvds_downclock, | |
5987 | refclk, &clock, | |
5988 | &reduced_clock); | |
5989 | } | |
5990 | /* Compat-code for transition, will disappear. */ | |
f47709a9 DV |
5991 | intel_crtc->config.dpll.n = clock.n; |
5992 | intel_crtc->config.dpll.m1 = clock.m1; | |
5993 | intel_crtc->config.dpll.m2 = clock.m2; | |
5994 | intel_crtc->config.dpll.p1 = clock.p1; | |
5995 | intel_crtc->config.dpll.p2 = clock.p2; | |
5996 | } | |
7026d4ac | 5997 | |
e9fd1c02 | 5998 | if (IS_GEN2(dev)) { |
8a654f3b | 5999 | i8xx_update_pll(intel_crtc, |
2a8f64ca VP |
6000 | has_reduced_clock ? &reduced_clock : NULL, |
6001 | num_connectors); | |
9d556c99 CML |
6002 | } else if (IS_CHERRYVIEW(dev)) { |
6003 | chv_update_pll(intel_crtc); | |
e9fd1c02 | 6004 | } else if (IS_VALLEYVIEW(dev)) { |
f2335330 | 6005 | vlv_update_pll(intel_crtc); |
e9fd1c02 | 6006 | } else { |
f47709a9 | 6007 | i9xx_update_pll(intel_crtc, |
eb1cbe48 | 6008 | has_reduced_clock ? &reduced_clock : NULL, |
eba905b2 | 6009 | num_connectors); |
e9fd1c02 | 6010 | } |
79e53945 | 6011 | |
c8f7a0db | 6012 | return 0; |
f564048e EA |
6013 | } |
6014 | ||
2fa2fe9a DV |
6015 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
6016 | struct intel_crtc_config *pipe_config) | |
6017 | { | |
6018 | struct drm_device *dev = crtc->base.dev; | |
6019 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6020 | uint32_t tmp; | |
6021 | ||
dc9e7dec VS |
6022 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
6023 | return; | |
6024 | ||
2fa2fe9a | 6025 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
6026 | if (!(tmp & PFIT_ENABLE)) |
6027 | return; | |
2fa2fe9a | 6028 | |
06922821 | 6029 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
6030 | if (INTEL_INFO(dev)->gen < 4) { |
6031 | if (crtc->pipe != PIPE_B) | |
6032 | return; | |
2fa2fe9a DV |
6033 | } else { |
6034 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
6035 | return; | |
6036 | } | |
6037 | ||
06922821 | 6038 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
6039 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
6040 | if (INTEL_INFO(dev)->gen < 5) | |
6041 | pipe_config->gmch_pfit.lvds_border_bits = | |
6042 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
6043 | } | |
6044 | ||
acbec814 JB |
6045 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
6046 | struct intel_crtc_config *pipe_config) | |
6047 | { | |
6048 | struct drm_device *dev = crtc->base.dev; | |
6049 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6050 | int pipe = pipe_config->cpu_transcoder; | |
6051 | intel_clock_t clock; | |
6052 | u32 mdiv; | |
662c6ecb | 6053 | int refclk = 100000; |
acbec814 JB |
6054 | |
6055 | mutex_lock(&dev_priv->dpio_lock); | |
ab3c759a | 6056 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
acbec814 JB |
6057 | mutex_unlock(&dev_priv->dpio_lock); |
6058 | ||
6059 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
6060 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
6061 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
6062 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
6063 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
6064 | ||
f646628b | 6065 | vlv_clock(refclk, &clock); |
acbec814 | 6066 | |
f646628b VS |
6067 | /* clock.dot is the fast clock */ |
6068 | pipe_config->port_clock = clock.dot / 5; | |
acbec814 JB |
6069 | } |
6070 | ||
1ad292b5 JB |
6071 | static void i9xx_get_plane_config(struct intel_crtc *crtc, |
6072 | struct intel_plane_config *plane_config) | |
6073 | { | |
6074 | struct drm_device *dev = crtc->base.dev; | |
6075 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6076 | u32 val, base, offset; | |
6077 | int pipe = crtc->pipe, plane = crtc->plane; | |
6078 | int fourcc, pixel_format; | |
6079 | int aligned_height; | |
6080 | ||
66e514c1 DA |
6081 | crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL); |
6082 | if (!crtc->base.primary->fb) { | |
1ad292b5 JB |
6083 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
6084 | return; | |
6085 | } | |
6086 | ||
6087 | val = I915_READ(DSPCNTR(plane)); | |
6088 | ||
6089 | if (INTEL_INFO(dev)->gen >= 4) | |
6090 | if (val & DISPPLANE_TILED) | |
6091 | plane_config->tiled = true; | |
6092 | ||
6093 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
6094 | fourcc = intel_format_to_fourcc(pixel_format); | |
66e514c1 DA |
6095 | crtc->base.primary->fb->pixel_format = fourcc; |
6096 | crtc->base.primary->fb->bits_per_pixel = | |
1ad292b5 JB |
6097 | drm_format_plane_cpp(fourcc, 0) * 8; |
6098 | ||
6099 | if (INTEL_INFO(dev)->gen >= 4) { | |
6100 | if (plane_config->tiled) | |
6101 | offset = I915_READ(DSPTILEOFF(plane)); | |
6102 | else | |
6103 | offset = I915_READ(DSPLINOFF(plane)); | |
6104 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
6105 | } else { | |
6106 | base = I915_READ(DSPADDR(plane)); | |
6107 | } | |
6108 | plane_config->base = base; | |
6109 | ||
6110 | val = I915_READ(PIPESRC(pipe)); | |
66e514c1 DA |
6111 | crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1; |
6112 | crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
6113 | |
6114 | val = I915_READ(DSPSTRIDE(pipe)); | |
66e514c1 | 6115 | crtc->base.primary->fb->pitches[0] = val & 0xffffff80; |
1ad292b5 | 6116 | |
66e514c1 | 6117 | aligned_height = intel_align_height(dev, crtc->base.primary->fb->height, |
1ad292b5 JB |
6118 | plane_config->tiled); |
6119 | ||
66e514c1 | 6120 | plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] * |
1ad292b5 JB |
6121 | aligned_height, PAGE_SIZE); |
6122 | ||
6123 | DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
66e514c1 DA |
6124 | pipe, plane, crtc->base.primary->fb->width, |
6125 | crtc->base.primary->fb->height, | |
6126 | crtc->base.primary->fb->bits_per_pixel, base, | |
6127 | crtc->base.primary->fb->pitches[0], | |
1ad292b5 JB |
6128 | plane_config->size); |
6129 | ||
6130 | } | |
6131 | ||
70b23a98 VS |
6132 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
6133 | struct intel_crtc_config *pipe_config) | |
6134 | { | |
6135 | struct drm_device *dev = crtc->base.dev; | |
6136 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6137 | int pipe = pipe_config->cpu_transcoder; | |
6138 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
6139 | intel_clock_t clock; | |
6140 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2; | |
6141 | int refclk = 100000; | |
6142 | ||
6143 | mutex_lock(&dev_priv->dpio_lock); | |
6144 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); | |
6145 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
6146 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
6147 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
6148 | mutex_unlock(&dev_priv->dpio_lock); | |
6149 | ||
6150 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
6151 | clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff); | |
6152 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; | |
6153 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
6154 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
6155 | ||
6156 | chv_clock(refclk, &clock); | |
6157 | ||
6158 | /* clock.dot is the fast clock */ | |
6159 | pipe_config->port_clock = clock.dot / 5; | |
6160 | } | |
6161 | ||
0e8ffe1b DV |
6162 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
6163 | struct intel_crtc_config *pipe_config) | |
6164 | { | |
6165 | struct drm_device *dev = crtc->base.dev; | |
6166 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6167 | uint32_t tmp; | |
6168 | ||
b5482bd0 ID |
6169 | if (!intel_display_power_enabled(dev_priv, |
6170 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
6171 | return false; | |
6172 | ||
e143a21c | 6173 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 6174 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 6175 | |
0e8ffe1b DV |
6176 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
6177 | if (!(tmp & PIPECONF_ENABLE)) | |
6178 | return false; | |
6179 | ||
42571aef VS |
6180 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
6181 | switch (tmp & PIPECONF_BPC_MASK) { | |
6182 | case PIPECONF_6BPC: | |
6183 | pipe_config->pipe_bpp = 18; | |
6184 | break; | |
6185 | case PIPECONF_8BPC: | |
6186 | pipe_config->pipe_bpp = 24; | |
6187 | break; | |
6188 | case PIPECONF_10BPC: | |
6189 | pipe_config->pipe_bpp = 30; | |
6190 | break; | |
6191 | default: | |
6192 | break; | |
6193 | } | |
6194 | } | |
6195 | ||
b5a9fa09 DV |
6196 | if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
6197 | pipe_config->limited_color_range = true; | |
6198 | ||
282740f7 VS |
6199 | if (INTEL_INFO(dev)->gen < 4) |
6200 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
6201 | ||
1bd1bd80 DV |
6202 | intel_get_pipe_timings(crtc, pipe_config); |
6203 | ||
2fa2fe9a DV |
6204 | i9xx_get_pfit_config(crtc, pipe_config); |
6205 | ||
6c49f241 DV |
6206 | if (INTEL_INFO(dev)->gen >= 4) { |
6207 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
6208 | pipe_config->pixel_multiplier = | |
6209 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
6210 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 6211 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
6212 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
6213 | tmp = I915_READ(DPLL(crtc->pipe)); | |
6214 | pipe_config->pixel_multiplier = | |
6215 | ((tmp & SDVO_MULTIPLIER_MASK) | |
6216 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
6217 | } else { | |
6218 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
6219 | * port and will be fixed up in the encoder->get_config | |
6220 | * function. */ | |
6221 | pipe_config->pixel_multiplier = 1; | |
6222 | } | |
8bcc2795 DV |
6223 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
6224 | if (!IS_VALLEYVIEW(dev)) { | |
6225 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); | |
6226 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
6227 | } else { |
6228 | /* Mask out read-only status bits. */ | |
6229 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
6230 | DPLL_PORTC_READY_MASK | | |
6231 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 6232 | } |
6c49f241 | 6233 | |
70b23a98 VS |
6234 | if (IS_CHERRYVIEW(dev)) |
6235 | chv_crtc_clock_get(crtc, pipe_config); | |
6236 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
6237 | vlv_crtc_clock_get(crtc, pipe_config); |
6238 | else | |
6239 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 6240 | |
0e8ffe1b DV |
6241 | return true; |
6242 | } | |
6243 | ||
dde86e2d | 6244 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
6245 | { |
6246 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6247 | struct drm_mode_config *mode_config = &dev->mode_config; | |
13d83a67 | 6248 | struct intel_encoder *encoder; |
74cfd7ac | 6249 | u32 val, final; |
13d83a67 | 6250 | bool has_lvds = false; |
199e5d79 | 6251 | bool has_cpu_edp = false; |
199e5d79 | 6252 | bool has_panel = false; |
99eb6a01 KP |
6253 | bool has_ck505 = false; |
6254 | bool can_ssc = false; | |
13d83a67 JB |
6255 | |
6256 | /* We need to take the global config into account */ | |
199e5d79 KP |
6257 | list_for_each_entry(encoder, &mode_config->encoder_list, |
6258 | base.head) { | |
6259 | switch (encoder->type) { | |
6260 | case INTEL_OUTPUT_LVDS: | |
6261 | has_panel = true; | |
6262 | has_lvds = true; | |
6263 | break; | |
6264 | case INTEL_OUTPUT_EDP: | |
6265 | has_panel = true; | |
2de6905f | 6266 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
6267 | has_cpu_edp = true; |
6268 | break; | |
13d83a67 JB |
6269 | } |
6270 | } | |
6271 | ||
99eb6a01 | 6272 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 6273 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
6274 | can_ssc = has_ck505; |
6275 | } else { | |
6276 | has_ck505 = false; | |
6277 | can_ssc = true; | |
6278 | } | |
6279 | ||
2de6905f ID |
6280 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
6281 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
6282 | |
6283 | /* Ironlake: try to setup display ref clock before DPLL | |
6284 | * enabling. This is only under driver's control after | |
6285 | * PCH B stepping, previous chipset stepping should be | |
6286 | * ignoring this setting. | |
6287 | */ | |
74cfd7ac CW |
6288 | val = I915_READ(PCH_DREF_CONTROL); |
6289 | ||
6290 | /* As we must carefully and slowly disable/enable each source in turn, | |
6291 | * compute the final state we want first and check if we need to | |
6292 | * make any changes at all. | |
6293 | */ | |
6294 | final = val; | |
6295 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
6296 | if (has_ck505) | |
6297 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
6298 | else | |
6299 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
6300 | ||
6301 | final &= ~DREF_SSC_SOURCE_MASK; | |
6302 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
6303 | final &= ~DREF_SSC1_ENABLE; | |
6304 | ||
6305 | if (has_panel) { | |
6306 | final |= DREF_SSC_SOURCE_ENABLE; | |
6307 | ||
6308 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
6309 | final |= DREF_SSC1_ENABLE; | |
6310 | ||
6311 | if (has_cpu_edp) { | |
6312 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
6313 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
6314 | else | |
6315 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
6316 | } else | |
6317 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
6318 | } else { | |
6319 | final |= DREF_SSC_SOURCE_DISABLE; | |
6320 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
6321 | } | |
6322 | ||
6323 | if (final == val) | |
6324 | return; | |
6325 | ||
13d83a67 | 6326 | /* Always enable nonspread source */ |
74cfd7ac | 6327 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 6328 | |
99eb6a01 | 6329 | if (has_ck505) |
74cfd7ac | 6330 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 6331 | else |
74cfd7ac | 6332 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 6333 | |
199e5d79 | 6334 | if (has_panel) { |
74cfd7ac CW |
6335 | val &= ~DREF_SSC_SOURCE_MASK; |
6336 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 6337 | |
199e5d79 | 6338 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 6339 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 6340 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 6341 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 6342 | } else |
74cfd7ac | 6343 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
6344 | |
6345 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 6346 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
6347 | POSTING_READ(PCH_DREF_CONTROL); |
6348 | udelay(200); | |
6349 | ||
74cfd7ac | 6350 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
6351 | |
6352 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 6353 | if (has_cpu_edp) { |
99eb6a01 | 6354 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 6355 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 6356 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 6357 | } else |
74cfd7ac | 6358 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 6359 | } else |
74cfd7ac | 6360 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 6361 | |
74cfd7ac | 6362 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
6363 | POSTING_READ(PCH_DREF_CONTROL); |
6364 | udelay(200); | |
6365 | } else { | |
6366 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
6367 | ||
74cfd7ac | 6368 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
6369 | |
6370 | /* Turn off CPU output */ | |
74cfd7ac | 6371 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 6372 | |
74cfd7ac | 6373 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
6374 | POSTING_READ(PCH_DREF_CONTROL); |
6375 | udelay(200); | |
6376 | ||
6377 | /* Turn off the SSC source */ | |
74cfd7ac CW |
6378 | val &= ~DREF_SSC_SOURCE_MASK; |
6379 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
6380 | |
6381 | /* Turn off SSC1 */ | |
74cfd7ac | 6382 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 6383 | |
74cfd7ac | 6384 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
6385 | POSTING_READ(PCH_DREF_CONTROL); |
6386 | udelay(200); | |
6387 | } | |
74cfd7ac CW |
6388 | |
6389 | BUG_ON(val != final); | |
13d83a67 JB |
6390 | } |
6391 | ||
f31f2d55 | 6392 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 6393 | { |
f31f2d55 | 6394 | uint32_t tmp; |
dde86e2d | 6395 | |
0ff066a9 PZ |
6396 | tmp = I915_READ(SOUTH_CHICKEN2); |
6397 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
6398 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 6399 | |
0ff066a9 PZ |
6400 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
6401 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
6402 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 6403 | |
0ff066a9 PZ |
6404 | tmp = I915_READ(SOUTH_CHICKEN2); |
6405 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
6406 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 6407 | |
0ff066a9 PZ |
6408 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
6409 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
6410 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
6411 | } |
6412 | ||
6413 | /* WaMPhyProgramming:hsw */ | |
6414 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
6415 | { | |
6416 | uint32_t tmp; | |
dde86e2d PZ |
6417 | |
6418 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
6419 | tmp &= ~(0xFF << 24); | |
6420 | tmp |= (0x12 << 24); | |
6421 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
6422 | ||
dde86e2d PZ |
6423 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
6424 | tmp |= (1 << 11); | |
6425 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
6426 | ||
6427 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
6428 | tmp |= (1 << 11); | |
6429 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
6430 | ||
dde86e2d PZ |
6431 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
6432 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
6433 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
6434 | ||
6435 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
6436 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
6437 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
6438 | ||
0ff066a9 PZ |
6439 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
6440 | tmp &= ~(7 << 13); | |
6441 | tmp |= (5 << 13); | |
6442 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 6443 | |
0ff066a9 PZ |
6444 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
6445 | tmp &= ~(7 << 13); | |
6446 | tmp |= (5 << 13); | |
6447 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
6448 | |
6449 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
6450 | tmp &= ~0xFF; | |
6451 | tmp |= 0x1C; | |
6452 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
6453 | ||
6454 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
6455 | tmp &= ~0xFF; | |
6456 | tmp |= 0x1C; | |
6457 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
6458 | ||
6459 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
6460 | tmp &= ~(0xFF << 16); | |
6461 | tmp |= (0x1C << 16); | |
6462 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
6463 | ||
6464 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
6465 | tmp &= ~(0xFF << 16); | |
6466 | tmp |= (0x1C << 16); | |
6467 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
6468 | ||
0ff066a9 PZ |
6469 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
6470 | tmp |= (1 << 27); | |
6471 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 6472 | |
0ff066a9 PZ |
6473 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
6474 | tmp |= (1 << 27); | |
6475 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 6476 | |
0ff066a9 PZ |
6477 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
6478 | tmp &= ~(0xF << 28); | |
6479 | tmp |= (4 << 28); | |
6480 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 6481 | |
0ff066a9 PZ |
6482 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
6483 | tmp &= ~(0xF << 28); | |
6484 | tmp |= (4 << 28); | |
6485 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
6486 | } |
6487 | ||
2fa86a1f PZ |
6488 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
6489 | * Programming" based on the parameters passed: | |
6490 | * - Sequence to enable CLKOUT_DP | |
6491 | * - Sequence to enable CLKOUT_DP without spread | |
6492 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
6493 | */ | |
6494 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
6495 | bool with_fdi) | |
f31f2d55 PZ |
6496 | { |
6497 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
6498 | uint32_t reg, tmp; |
6499 | ||
6500 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
6501 | with_spread = true; | |
6502 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && | |
6503 | with_fdi, "LP PCH doesn't have FDI\n")) | |
6504 | with_fdi = false; | |
f31f2d55 PZ |
6505 | |
6506 | mutex_lock(&dev_priv->dpio_lock); | |
6507 | ||
6508 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
6509 | tmp &= ~SBI_SSCCTL_DISABLE; | |
6510 | tmp |= SBI_SSCCTL_PATHALT; | |
6511 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
6512 | ||
6513 | udelay(24); | |
6514 | ||
2fa86a1f PZ |
6515 | if (with_spread) { |
6516 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
6517 | tmp &= ~SBI_SSCCTL_PATHALT; | |
6518 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 6519 | |
2fa86a1f PZ |
6520 | if (with_fdi) { |
6521 | lpt_reset_fdi_mphy(dev_priv); | |
6522 | lpt_program_fdi_mphy(dev_priv); | |
6523 | } | |
6524 | } | |
dde86e2d | 6525 | |
2fa86a1f PZ |
6526 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
6527 | SBI_GEN0 : SBI_DBUFF0; | |
6528 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
6529 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
6530 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 DV |
6531 | |
6532 | mutex_unlock(&dev_priv->dpio_lock); | |
dde86e2d PZ |
6533 | } |
6534 | ||
47701c3b PZ |
6535 | /* Sequence to disable CLKOUT_DP */ |
6536 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
6537 | { | |
6538 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6539 | uint32_t reg, tmp; | |
6540 | ||
6541 | mutex_lock(&dev_priv->dpio_lock); | |
6542 | ||
6543 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? | |
6544 | SBI_GEN0 : SBI_DBUFF0; | |
6545 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
6546 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
6547 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
6548 | ||
6549 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
6550 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
6551 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
6552 | tmp |= SBI_SSCCTL_PATHALT; | |
6553 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
6554 | udelay(32); | |
6555 | } | |
6556 | tmp |= SBI_SSCCTL_DISABLE; | |
6557 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
6558 | } | |
6559 | ||
6560 | mutex_unlock(&dev_priv->dpio_lock); | |
6561 | } | |
6562 | ||
bf8fa3d3 PZ |
6563 | static void lpt_init_pch_refclk(struct drm_device *dev) |
6564 | { | |
6565 | struct drm_mode_config *mode_config = &dev->mode_config; | |
6566 | struct intel_encoder *encoder; | |
6567 | bool has_vga = false; | |
6568 | ||
6569 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { | |
6570 | switch (encoder->type) { | |
6571 | case INTEL_OUTPUT_ANALOG: | |
6572 | has_vga = true; | |
6573 | break; | |
6574 | } | |
6575 | } | |
6576 | ||
47701c3b PZ |
6577 | if (has_vga) |
6578 | lpt_enable_clkout_dp(dev, true, true); | |
6579 | else | |
6580 | lpt_disable_clkout_dp(dev); | |
bf8fa3d3 PZ |
6581 | } |
6582 | ||
dde86e2d PZ |
6583 | /* |
6584 | * Initialize reference clocks when the driver loads | |
6585 | */ | |
6586 | void intel_init_pch_refclk(struct drm_device *dev) | |
6587 | { | |
6588 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
6589 | ironlake_init_pch_refclk(dev); | |
6590 | else if (HAS_PCH_LPT(dev)) | |
6591 | lpt_init_pch_refclk(dev); | |
6592 | } | |
6593 | ||
d9d444cb JB |
6594 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
6595 | { | |
6596 | struct drm_device *dev = crtc->dev; | |
6597 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6598 | struct intel_encoder *encoder; | |
d9d444cb JB |
6599 | int num_connectors = 0; |
6600 | bool is_lvds = false; | |
6601 | ||
6c2b7c12 | 6602 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
d9d444cb JB |
6603 | switch (encoder->type) { |
6604 | case INTEL_OUTPUT_LVDS: | |
6605 | is_lvds = true; | |
6606 | break; | |
d9d444cb JB |
6607 | } |
6608 | num_connectors++; | |
6609 | } | |
6610 | ||
6611 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 6612 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 6613 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 6614 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
6615 | } |
6616 | ||
6617 | return 120000; | |
6618 | } | |
6619 | ||
6ff93609 | 6620 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 6621 | { |
c8203565 | 6622 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
6623 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6624 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
6625 | uint32_t val; |
6626 | ||
78114071 | 6627 | val = 0; |
c8203565 | 6628 | |
965e0c48 | 6629 | switch (intel_crtc->config.pipe_bpp) { |
c8203565 | 6630 | case 18: |
dfd07d72 | 6631 | val |= PIPECONF_6BPC; |
c8203565 PZ |
6632 | break; |
6633 | case 24: | |
dfd07d72 | 6634 | val |= PIPECONF_8BPC; |
c8203565 PZ |
6635 | break; |
6636 | case 30: | |
dfd07d72 | 6637 | val |= PIPECONF_10BPC; |
c8203565 PZ |
6638 | break; |
6639 | case 36: | |
dfd07d72 | 6640 | val |= PIPECONF_12BPC; |
c8203565 PZ |
6641 | break; |
6642 | default: | |
cc769b62 PZ |
6643 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
6644 | BUG(); | |
c8203565 PZ |
6645 | } |
6646 | ||
d8b32247 | 6647 | if (intel_crtc->config.dither) |
c8203565 PZ |
6648 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
6649 | ||
6ff93609 | 6650 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
6651 | val |= PIPECONF_INTERLACED_ILK; |
6652 | else | |
6653 | val |= PIPECONF_PROGRESSIVE; | |
6654 | ||
50f3b016 | 6655 | if (intel_crtc->config.limited_color_range) |
3685a8f3 | 6656 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 6657 | |
c8203565 PZ |
6658 | I915_WRITE(PIPECONF(pipe), val); |
6659 | POSTING_READ(PIPECONF(pipe)); | |
6660 | } | |
6661 | ||
86d3efce VS |
6662 | /* |
6663 | * Set up the pipe CSC unit. | |
6664 | * | |
6665 | * Currently only full range RGB to limited range RGB conversion | |
6666 | * is supported, but eventually this should handle various | |
6667 | * RGB<->YCbCr scenarios as well. | |
6668 | */ | |
50f3b016 | 6669 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
6670 | { |
6671 | struct drm_device *dev = crtc->dev; | |
6672 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6673 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6674 | int pipe = intel_crtc->pipe; | |
6675 | uint16_t coeff = 0x7800; /* 1.0 */ | |
6676 | ||
6677 | /* | |
6678 | * TODO: Check what kind of values actually come out of the pipe | |
6679 | * with these coeff/postoff values and adjust to get the best | |
6680 | * accuracy. Perhaps we even need to take the bpc value into | |
6681 | * consideration. | |
6682 | */ | |
6683 | ||
50f3b016 | 6684 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
6685 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
6686 | ||
6687 | /* | |
6688 | * GY/GU and RY/RU should be the other way around according | |
6689 | * to BSpec, but reality doesn't agree. Just set them up in | |
6690 | * a way that results in the correct picture. | |
6691 | */ | |
6692 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
6693 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
6694 | ||
6695 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
6696 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
6697 | ||
6698 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
6699 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
6700 | ||
6701 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
6702 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
6703 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
6704 | ||
6705 | if (INTEL_INFO(dev)->gen > 6) { | |
6706 | uint16_t postoff = 0; | |
6707 | ||
50f3b016 | 6708 | if (intel_crtc->config.limited_color_range) |
32cf0cb0 | 6709 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
6710 | |
6711 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
6712 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
6713 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
6714 | ||
6715 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
6716 | } else { | |
6717 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
6718 | ||
50f3b016 | 6719 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
6720 | mode |= CSC_BLACK_SCREEN_OFFSET; |
6721 | ||
6722 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
6723 | } | |
6724 | } | |
6725 | ||
6ff93609 | 6726 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 6727 | { |
756f85cf PZ |
6728 | struct drm_device *dev = crtc->dev; |
6729 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 6730 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 6731 | enum pipe pipe = intel_crtc->pipe; |
3b117c8f | 6732 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee2b0b38 PZ |
6733 | uint32_t val; |
6734 | ||
3eff4faa | 6735 | val = 0; |
ee2b0b38 | 6736 | |
756f85cf | 6737 | if (IS_HASWELL(dev) && intel_crtc->config.dither) |
ee2b0b38 PZ |
6738 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
6739 | ||
6ff93609 | 6740 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
6741 | val |= PIPECONF_INTERLACED_ILK; |
6742 | else | |
6743 | val |= PIPECONF_PROGRESSIVE; | |
6744 | ||
702e7a56 PZ |
6745 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
6746 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
6747 | |
6748 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
6749 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf PZ |
6750 | |
6751 | if (IS_BROADWELL(dev)) { | |
6752 | val = 0; | |
6753 | ||
6754 | switch (intel_crtc->config.pipe_bpp) { | |
6755 | case 18: | |
6756 | val |= PIPEMISC_DITHER_6_BPC; | |
6757 | break; | |
6758 | case 24: | |
6759 | val |= PIPEMISC_DITHER_8_BPC; | |
6760 | break; | |
6761 | case 30: | |
6762 | val |= PIPEMISC_DITHER_10_BPC; | |
6763 | break; | |
6764 | case 36: | |
6765 | val |= PIPEMISC_DITHER_12_BPC; | |
6766 | break; | |
6767 | default: | |
6768 | /* Case prevented by pipe_config_set_bpp. */ | |
6769 | BUG(); | |
6770 | } | |
6771 | ||
6772 | if (intel_crtc->config.dither) | |
6773 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; | |
6774 | ||
6775 | I915_WRITE(PIPEMISC(pipe), val); | |
6776 | } | |
ee2b0b38 PZ |
6777 | } |
6778 | ||
6591c6e4 | 6779 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
6591c6e4 PZ |
6780 | intel_clock_t *clock, |
6781 | bool *has_reduced_clock, | |
6782 | intel_clock_t *reduced_clock) | |
6783 | { | |
6784 | struct drm_device *dev = crtc->dev; | |
6785 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6786 | struct intel_encoder *intel_encoder; | |
6787 | int refclk; | |
d4906093 | 6788 | const intel_limit_t *limit; |
a16af721 | 6789 | bool ret, is_lvds = false; |
79e53945 | 6790 | |
6591c6e4 PZ |
6791 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
6792 | switch (intel_encoder->type) { | |
79e53945 JB |
6793 | case INTEL_OUTPUT_LVDS: |
6794 | is_lvds = true; | |
6795 | break; | |
79e53945 JB |
6796 | } |
6797 | } | |
6798 | ||
d9d444cb | 6799 | refclk = ironlake_get_refclk(crtc); |
79e53945 | 6800 | |
d4906093 ML |
6801 | /* |
6802 | * Returns a set of divisors for the desired target clock with the given | |
6803 | * refclk, or FALSE. The returned values represent the clock equation: | |
6804 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
6805 | */ | |
1b894b59 | 6806 | limit = intel_limit(crtc, refclk); |
ff9a6750 DV |
6807 | ret = dev_priv->display.find_dpll(limit, crtc, |
6808 | to_intel_crtc(crtc)->config.port_clock, | |
ee9300bb | 6809 | refclk, NULL, clock); |
6591c6e4 PZ |
6810 | if (!ret) |
6811 | return false; | |
cda4b7d3 | 6812 | |
ddc9003c | 6813 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
6814 | /* |
6815 | * Ensure we match the reduced clock's P to the target clock. | |
6816 | * If the clocks don't match, we can't switch the display clock | |
6817 | * by using the FP0/FP1. In such case we will disable the LVDS | |
6818 | * downclock feature. | |
6819 | */ | |
ee9300bb DV |
6820 | *has_reduced_clock = |
6821 | dev_priv->display.find_dpll(limit, crtc, | |
6822 | dev_priv->lvds_downclock, | |
6823 | refclk, clock, | |
6824 | reduced_clock); | |
652c393a | 6825 | } |
61e9653f | 6826 | |
6591c6e4 PZ |
6827 | return true; |
6828 | } | |
6829 | ||
d4b1931c PZ |
6830 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
6831 | { | |
6832 | /* | |
6833 | * Account for spread spectrum to avoid | |
6834 | * oversubscribing the link. Max center spread | |
6835 | * is 2.5%; use 5% for safety's sake. | |
6836 | */ | |
6837 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 6838 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
6839 | } |
6840 | ||
7429e9d4 | 6841 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 6842 | { |
7429e9d4 | 6843 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
6844 | } |
6845 | ||
de13a2e3 | 6846 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
7429e9d4 | 6847 | u32 *fp, |
9a7c7890 | 6848 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 6849 | { |
de13a2e3 | 6850 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
6851 | struct drm_device *dev = crtc->dev; |
6852 | struct drm_i915_private *dev_priv = dev->dev_private; | |
de13a2e3 PZ |
6853 | struct intel_encoder *intel_encoder; |
6854 | uint32_t dpll; | |
6cc5f341 | 6855 | int factor, num_connectors = 0; |
09ede541 | 6856 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 6857 | |
de13a2e3 PZ |
6858 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
6859 | switch (intel_encoder->type) { | |
79e53945 JB |
6860 | case INTEL_OUTPUT_LVDS: |
6861 | is_lvds = true; | |
6862 | break; | |
6863 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 6864 | case INTEL_OUTPUT_HDMI: |
79e53945 | 6865 | is_sdvo = true; |
79e53945 | 6866 | break; |
79e53945 | 6867 | } |
43565a06 | 6868 | |
c751ce4f | 6869 | num_connectors++; |
79e53945 | 6870 | } |
79e53945 | 6871 | |
c1858123 | 6872 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
6873 | factor = 21; |
6874 | if (is_lvds) { | |
6875 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 6876 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 6877 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 6878 | factor = 25; |
09ede541 | 6879 | } else if (intel_crtc->config.sdvo_tv_clock) |
8febb297 | 6880 | factor = 20; |
c1858123 | 6881 | |
7429e9d4 | 6882 | if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor)) |
7d0ac5b7 | 6883 | *fp |= FP_CB_TUNE; |
2c07245f | 6884 | |
9a7c7890 DV |
6885 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
6886 | *fp2 |= FP_CB_TUNE; | |
6887 | ||
5eddb70b | 6888 | dpll = 0; |
2c07245f | 6889 | |
a07d6787 EA |
6890 | if (is_lvds) |
6891 | dpll |= DPLLB_MODE_LVDS; | |
6892 | else | |
6893 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 6894 | |
ef1b460d DV |
6895 | dpll |= (intel_crtc->config.pixel_multiplier - 1) |
6896 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | |
198a037f DV |
6897 | |
6898 | if (is_sdvo) | |
4a33e48d | 6899 | dpll |= DPLL_SDVO_HIGH_SPEED; |
9566e9af | 6900 | if (intel_crtc->config.has_dp_encoder) |
4a33e48d | 6901 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 6902 | |
a07d6787 | 6903 | /* compute bitmask from p1 value */ |
7429e9d4 | 6904 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 6905 | /* also FPA1 */ |
7429e9d4 | 6906 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 6907 | |
7429e9d4 | 6908 | switch (intel_crtc->config.dpll.p2) { |
a07d6787 EA |
6909 | case 5: |
6910 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
6911 | break; | |
6912 | case 7: | |
6913 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
6914 | break; | |
6915 | case 10: | |
6916 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
6917 | break; | |
6918 | case 14: | |
6919 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
6920 | break; | |
79e53945 JB |
6921 | } |
6922 | ||
b4c09f3b | 6923 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 6924 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
6925 | else |
6926 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6927 | ||
959e16d6 | 6928 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
6929 | } |
6930 | ||
6931 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, | |
de13a2e3 PZ |
6932 | int x, int y, |
6933 | struct drm_framebuffer *fb) | |
6934 | { | |
6935 | struct drm_device *dev = crtc->dev; | |
de13a2e3 | 6936 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
de13a2e3 PZ |
6937 | int num_connectors = 0; |
6938 | intel_clock_t clock, reduced_clock; | |
cbbab5bd | 6939 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 6940 | bool ok, has_reduced_clock = false; |
8b47047b | 6941 | bool is_lvds = false; |
de13a2e3 | 6942 | struct intel_encoder *encoder; |
e2b78267 | 6943 | struct intel_shared_dpll *pll; |
de13a2e3 PZ |
6944 | |
6945 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
6946 | switch (encoder->type) { | |
6947 | case INTEL_OUTPUT_LVDS: | |
6948 | is_lvds = true; | |
6949 | break; | |
de13a2e3 PZ |
6950 | } |
6951 | ||
6952 | num_connectors++; | |
a07d6787 | 6953 | } |
79e53945 | 6954 | |
5dc5298b PZ |
6955 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
6956 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 6957 | |
ff9a6750 | 6958 | ok = ironlake_compute_clocks(crtc, &clock, |
de13a2e3 | 6959 | &has_reduced_clock, &reduced_clock); |
ee9300bb | 6960 | if (!ok && !intel_crtc->config.clock_set) { |
de13a2e3 PZ |
6961 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
6962 | return -EINVAL; | |
79e53945 | 6963 | } |
f47709a9 DV |
6964 | /* Compat-code for transition, will disappear. */ |
6965 | if (!intel_crtc->config.clock_set) { | |
6966 | intel_crtc->config.dpll.n = clock.n; | |
6967 | intel_crtc->config.dpll.m1 = clock.m1; | |
6968 | intel_crtc->config.dpll.m2 = clock.m2; | |
6969 | intel_crtc->config.dpll.p1 = clock.p1; | |
6970 | intel_crtc->config.dpll.p2 = clock.p2; | |
6971 | } | |
79e53945 | 6972 | |
5dc5298b | 6973 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
8b47047b | 6974 | if (intel_crtc->config.has_pch_encoder) { |
7429e9d4 | 6975 | fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll); |
cbbab5bd | 6976 | if (has_reduced_clock) |
7429e9d4 | 6977 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 6978 | |
7429e9d4 | 6979 | dpll = ironlake_compute_dpll(intel_crtc, |
cbbab5bd DV |
6980 | &fp, &reduced_clock, |
6981 | has_reduced_clock ? &fp2 : NULL); | |
6982 | ||
959e16d6 | 6983 | intel_crtc->config.dpll_hw_state.dpll = dpll; |
66e985c0 DV |
6984 | intel_crtc->config.dpll_hw_state.fp0 = fp; |
6985 | if (has_reduced_clock) | |
6986 | intel_crtc->config.dpll_hw_state.fp1 = fp2; | |
6987 | else | |
6988 | intel_crtc->config.dpll_hw_state.fp1 = fp; | |
6989 | ||
b89a1d39 | 6990 | pll = intel_get_shared_dpll(intel_crtc); |
ee7b9f93 | 6991 | if (pll == NULL) { |
84f44ce7 | 6992 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
29407aab | 6993 | pipe_name(intel_crtc->pipe)); |
4b645f14 JB |
6994 | return -EINVAL; |
6995 | } | |
ee7b9f93 | 6996 | } else |
e72f9fbf | 6997 | intel_put_shared_dpll(intel_crtc); |
79e53945 | 6998 | |
d330a953 | 6999 | if (is_lvds && has_reduced_clock && i915.powersave) |
bcd644e0 DV |
7000 | intel_crtc->lowfreq_avail = true; |
7001 | else | |
7002 | intel_crtc->lowfreq_avail = false; | |
e2b78267 | 7003 | |
c8f7a0db | 7004 | return 0; |
79e53945 JB |
7005 | } |
7006 | ||
eb14cb74 VS |
7007 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
7008 | struct intel_link_m_n *m_n) | |
7009 | { | |
7010 | struct drm_device *dev = crtc->base.dev; | |
7011 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7012 | enum pipe pipe = crtc->pipe; | |
7013 | ||
7014 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
7015 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
7016 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
7017 | & ~TU_SIZE_MASK; | |
7018 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
7019 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
7020 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7021 | } | |
7022 | ||
7023 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
7024 | enum transcoder transcoder, | |
7025 | struct intel_link_m_n *m_n) | |
72419203 DV |
7026 | { |
7027 | struct drm_device *dev = crtc->base.dev; | |
7028 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 7029 | enum pipe pipe = crtc->pipe; |
72419203 | 7030 | |
eb14cb74 VS |
7031 | if (INTEL_INFO(dev)->gen >= 5) { |
7032 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
7033 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
7034 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
7035 | & ~TU_SIZE_MASK; | |
7036 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
7037 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
7038 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7039 | } else { | |
7040 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
7041 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
7042 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
7043 | & ~TU_SIZE_MASK; | |
7044 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
7045 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
7046 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7047 | } | |
7048 | } | |
7049 | ||
7050 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
7051 | struct intel_crtc_config *pipe_config) | |
7052 | { | |
7053 | if (crtc->config.has_pch_encoder) | |
7054 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); | |
7055 | else | |
7056 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
7057 | &pipe_config->dp_m_n); | |
7058 | } | |
72419203 | 7059 | |
eb14cb74 VS |
7060 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
7061 | struct intel_crtc_config *pipe_config) | |
7062 | { | |
7063 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
7064 | &pipe_config->fdi_m_n); | |
72419203 DV |
7065 | } |
7066 | ||
2fa2fe9a DV |
7067 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
7068 | struct intel_crtc_config *pipe_config) | |
7069 | { | |
7070 | struct drm_device *dev = crtc->base.dev; | |
7071 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7072 | uint32_t tmp; | |
7073 | ||
7074 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
7075 | ||
7076 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 7077 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
7078 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
7079 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
7080 | |
7081 | /* We currently do not free assignements of panel fitters on | |
7082 | * ivb/hsw (since we don't use the higher upscaling modes which | |
7083 | * differentiates them) so just WARN about this case for now. */ | |
7084 | if (IS_GEN7(dev)) { | |
7085 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
7086 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
7087 | } | |
2fa2fe9a | 7088 | } |
79e53945 JB |
7089 | } |
7090 | ||
4c6baa59 JB |
7091 | static void ironlake_get_plane_config(struct intel_crtc *crtc, |
7092 | struct intel_plane_config *plane_config) | |
7093 | { | |
7094 | struct drm_device *dev = crtc->base.dev; | |
7095 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7096 | u32 val, base, offset; | |
7097 | int pipe = crtc->pipe, plane = crtc->plane; | |
7098 | int fourcc, pixel_format; | |
7099 | int aligned_height; | |
7100 | ||
66e514c1 DA |
7101 | crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL); |
7102 | if (!crtc->base.primary->fb) { | |
4c6baa59 JB |
7103 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
7104 | return; | |
7105 | } | |
7106 | ||
7107 | val = I915_READ(DSPCNTR(plane)); | |
7108 | ||
7109 | if (INTEL_INFO(dev)->gen >= 4) | |
7110 | if (val & DISPPLANE_TILED) | |
7111 | plane_config->tiled = true; | |
7112 | ||
7113 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
7114 | fourcc = intel_format_to_fourcc(pixel_format); | |
66e514c1 DA |
7115 | crtc->base.primary->fb->pixel_format = fourcc; |
7116 | crtc->base.primary->fb->bits_per_pixel = | |
4c6baa59 JB |
7117 | drm_format_plane_cpp(fourcc, 0) * 8; |
7118 | ||
7119 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
7120 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
7121 | offset = I915_READ(DSPOFFSET(plane)); | |
7122 | } else { | |
7123 | if (plane_config->tiled) | |
7124 | offset = I915_READ(DSPTILEOFF(plane)); | |
7125 | else | |
7126 | offset = I915_READ(DSPLINOFF(plane)); | |
7127 | } | |
7128 | plane_config->base = base; | |
7129 | ||
7130 | val = I915_READ(PIPESRC(pipe)); | |
66e514c1 DA |
7131 | crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1; |
7132 | crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
7133 | |
7134 | val = I915_READ(DSPSTRIDE(pipe)); | |
66e514c1 | 7135 | crtc->base.primary->fb->pitches[0] = val & 0xffffff80; |
4c6baa59 | 7136 | |
66e514c1 | 7137 | aligned_height = intel_align_height(dev, crtc->base.primary->fb->height, |
4c6baa59 JB |
7138 | plane_config->tiled); |
7139 | ||
66e514c1 | 7140 | plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] * |
4c6baa59 JB |
7141 | aligned_height, PAGE_SIZE); |
7142 | ||
7143 | DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
66e514c1 DA |
7144 | pipe, plane, crtc->base.primary->fb->width, |
7145 | crtc->base.primary->fb->height, | |
7146 | crtc->base.primary->fb->bits_per_pixel, base, | |
7147 | crtc->base.primary->fb->pitches[0], | |
4c6baa59 JB |
7148 | plane_config->size); |
7149 | } | |
7150 | ||
0e8ffe1b DV |
7151 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
7152 | struct intel_crtc_config *pipe_config) | |
7153 | { | |
7154 | struct drm_device *dev = crtc->base.dev; | |
7155 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7156 | uint32_t tmp; | |
7157 | ||
e143a21c | 7158 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 7159 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 7160 | |
0e8ffe1b DV |
7161 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
7162 | if (!(tmp & PIPECONF_ENABLE)) | |
7163 | return false; | |
7164 | ||
42571aef VS |
7165 | switch (tmp & PIPECONF_BPC_MASK) { |
7166 | case PIPECONF_6BPC: | |
7167 | pipe_config->pipe_bpp = 18; | |
7168 | break; | |
7169 | case PIPECONF_8BPC: | |
7170 | pipe_config->pipe_bpp = 24; | |
7171 | break; | |
7172 | case PIPECONF_10BPC: | |
7173 | pipe_config->pipe_bpp = 30; | |
7174 | break; | |
7175 | case PIPECONF_12BPC: | |
7176 | pipe_config->pipe_bpp = 36; | |
7177 | break; | |
7178 | default: | |
7179 | break; | |
7180 | } | |
7181 | ||
b5a9fa09 DV |
7182 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
7183 | pipe_config->limited_color_range = true; | |
7184 | ||
ab9412ba | 7185 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
7186 | struct intel_shared_dpll *pll; |
7187 | ||
88adfff1 DV |
7188 | pipe_config->has_pch_encoder = true; |
7189 | ||
627eb5a3 DV |
7190 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
7191 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
7192 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
7193 | |
7194 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 7195 | |
c0d43d62 | 7196 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
7197 | pipe_config->shared_dpll = |
7198 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
7199 | } else { |
7200 | tmp = I915_READ(PCH_DPLL_SEL); | |
7201 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
7202 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
7203 | else | |
7204 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
7205 | } | |
66e985c0 DV |
7206 | |
7207 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
7208 | ||
7209 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
7210 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
7211 | |
7212 | tmp = pipe_config->dpll_hw_state.dpll; | |
7213 | pipe_config->pixel_multiplier = | |
7214 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
7215 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
7216 | |
7217 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
7218 | } else { |
7219 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
7220 | } |
7221 | ||
1bd1bd80 DV |
7222 | intel_get_pipe_timings(crtc, pipe_config); |
7223 | ||
2fa2fe9a DV |
7224 | ironlake_get_pfit_config(crtc, pipe_config); |
7225 | ||
0e8ffe1b DV |
7226 | return true; |
7227 | } | |
7228 | ||
be256dc7 PZ |
7229 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
7230 | { | |
7231 | struct drm_device *dev = dev_priv->dev; | |
7232 | struct intel_ddi_plls *plls = &dev_priv->ddi_plls; | |
7233 | struct intel_crtc *crtc; | |
be256dc7 | 7234 | |
d3fcc808 | 7235 | for_each_intel_crtc(dev, crtc) |
798183c5 | 7236 | WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
7237 | pipe_name(crtc->pipe)); |
7238 | ||
7239 | WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); | |
7240 | WARN(plls->spll_refcount, "SPLL enabled\n"); | |
7241 | WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n"); | |
7242 | WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n"); | |
7243 | WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); | |
7244 | WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
7245 | "CPU PWM1 enabled\n"); | |
7246 | WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, | |
7247 | "CPU PWM2 enabled\n"); | |
7248 | WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, | |
7249 | "PCH PWM1 enabled\n"); | |
7250 | WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, | |
7251 | "Utility pin enabled\n"); | |
7252 | WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); | |
7253 | ||
9926ada1 PZ |
7254 | /* |
7255 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
7256 | * interrupts remain enabled. We used to check for that, but since it's | |
7257 | * gen-specific and since we only disable LCPLL after we fully disable | |
7258 | * the interrupts, the check below should be enough. | |
7259 | */ | |
7260 | WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n"); | |
be256dc7 PZ |
7261 | } |
7262 | ||
3c4c9b81 PZ |
7263 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
7264 | { | |
7265 | struct drm_device *dev = dev_priv->dev; | |
7266 | ||
7267 | if (IS_HASWELL(dev)) { | |
7268 | mutex_lock(&dev_priv->rps.hw_lock); | |
7269 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
7270 | val)) | |
7271 | DRM_ERROR("Failed to disable D_COMP\n"); | |
7272 | mutex_unlock(&dev_priv->rps.hw_lock); | |
7273 | } else { | |
7274 | I915_WRITE(D_COMP, val); | |
7275 | } | |
7276 | POSTING_READ(D_COMP); | |
be256dc7 PZ |
7277 | } |
7278 | ||
7279 | /* | |
7280 | * This function implements pieces of two sequences from BSpec: | |
7281 | * - Sequence for display software to disable LCPLL | |
7282 | * - Sequence for display software to allow package C8+ | |
7283 | * The steps implemented here are just the steps that actually touch the LCPLL | |
7284 | * register. Callers should take care of disabling all the display engine | |
7285 | * functions, doing the mode unset, fixing interrupts, etc. | |
7286 | */ | |
6ff58d53 PZ |
7287 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
7288 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
7289 | { |
7290 | uint32_t val; | |
7291 | ||
7292 | assert_can_disable_lcpll(dev_priv); | |
7293 | ||
7294 | val = I915_READ(LCPLL_CTL); | |
7295 | ||
7296 | if (switch_to_fclk) { | |
7297 | val |= LCPLL_CD_SOURCE_FCLK; | |
7298 | I915_WRITE(LCPLL_CTL, val); | |
7299 | ||
7300 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
7301 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
7302 | DRM_ERROR("Switching to FCLK failed\n"); | |
7303 | ||
7304 | val = I915_READ(LCPLL_CTL); | |
7305 | } | |
7306 | ||
7307 | val |= LCPLL_PLL_DISABLE; | |
7308 | I915_WRITE(LCPLL_CTL, val); | |
7309 | POSTING_READ(LCPLL_CTL); | |
7310 | ||
7311 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
7312 | DRM_ERROR("LCPLL still locked\n"); | |
7313 | ||
7314 | val = I915_READ(D_COMP); | |
7315 | val |= D_COMP_COMP_DISABLE; | |
3c4c9b81 | 7316 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
7317 | ndelay(100); |
7318 | ||
7319 | if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1)) | |
7320 | DRM_ERROR("D_COMP RCOMP still in progress\n"); | |
7321 | ||
7322 | if (allow_power_down) { | |
7323 | val = I915_READ(LCPLL_CTL); | |
7324 | val |= LCPLL_POWER_DOWN_ALLOW; | |
7325 | I915_WRITE(LCPLL_CTL, val); | |
7326 | POSTING_READ(LCPLL_CTL); | |
7327 | } | |
7328 | } | |
7329 | ||
7330 | /* | |
7331 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
7332 | * source. | |
7333 | */ | |
6ff58d53 | 7334 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
7335 | { |
7336 | uint32_t val; | |
a8a8bd54 | 7337 | unsigned long irqflags; |
be256dc7 PZ |
7338 | |
7339 | val = I915_READ(LCPLL_CTL); | |
7340 | ||
7341 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
7342 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
7343 | return; | |
7344 | ||
a8a8bd54 PZ |
7345 | /* |
7346 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
7347 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
7348 | * | |
7349 | * The other problem is that hsw_restore_lcpll() is called as part of | |
7350 | * the runtime PM resume sequence, so we can't just call | |
7351 | * gen6_gt_force_wake_get() because that function calls | |
7352 | * intel_runtime_pm_get(), and we can't change the runtime PM refcount | |
7353 | * while we are on the resume sequence. So to solve this problem we have | |
7354 | * to call special forcewake code that doesn't touch runtime PM and | |
7355 | * doesn't enable the forcewake delayed work. | |
7356 | */ | |
7357 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
7358 | if (dev_priv->uncore.forcewake_count++ == 0) | |
7359 | dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL); | |
7360 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
215733fa | 7361 | |
be256dc7 PZ |
7362 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
7363 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
7364 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 7365 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
7366 | } |
7367 | ||
7368 | val = I915_READ(D_COMP); | |
7369 | val |= D_COMP_COMP_FORCE; | |
7370 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 7371 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
7372 | |
7373 | val = I915_READ(LCPLL_CTL); | |
7374 | val &= ~LCPLL_PLL_DISABLE; | |
7375 | I915_WRITE(LCPLL_CTL, val); | |
7376 | ||
7377 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
7378 | DRM_ERROR("LCPLL not locked yet\n"); | |
7379 | ||
7380 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
7381 | val = I915_READ(LCPLL_CTL); | |
7382 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
7383 | I915_WRITE(LCPLL_CTL, val); | |
7384 | ||
7385 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
7386 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
7387 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
7388 | } | |
215733fa | 7389 | |
a8a8bd54 PZ |
7390 | /* See the big comment above. */ |
7391 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
7392 | if (--dev_priv->uncore.forcewake_count == 0) | |
7393 | dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL); | |
7394 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
be256dc7 PZ |
7395 | } |
7396 | ||
765dab67 PZ |
7397 | /* |
7398 | * Package states C8 and deeper are really deep PC states that can only be | |
7399 | * reached when all the devices on the system allow it, so even if the graphics | |
7400 | * device allows PC8+, it doesn't mean the system will actually get to these | |
7401 | * states. Our driver only allows PC8+ when going into runtime PM. | |
7402 | * | |
7403 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
7404 | * well is disabled and most interrupts are disabled, and these are also | |
7405 | * requirements for runtime PM. When these conditions are met, we manually do | |
7406 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
7407 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
7408 | * hang the machine. | |
7409 | * | |
7410 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
7411 | * the state of some registers, so when we come back from PC8+ we need to | |
7412 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
7413 | * need to take care of the registers kept by RC6. Notice that this happens even | |
7414 | * if we don't put the device in PCI D3 state (which is what currently happens | |
7415 | * because of the runtime PM support). | |
7416 | * | |
7417 | * For more, read "Display Sequences for Package C8" on the hardware | |
7418 | * documentation. | |
7419 | */ | |
a14cb6fc | 7420 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 7421 | { |
c67a470b PZ |
7422 | struct drm_device *dev = dev_priv->dev; |
7423 | uint32_t val; | |
7424 | ||
c67a470b PZ |
7425 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
7426 | ||
c67a470b PZ |
7427 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
7428 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
7429 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
7430 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
7431 | } | |
7432 | ||
7433 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
7434 | hsw_disable_lcpll(dev_priv, true, true); |
7435 | } | |
7436 | ||
a14cb6fc | 7437 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
7438 | { |
7439 | struct drm_device *dev = dev_priv->dev; | |
7440 | uint32_t val; | |
7441 | ||
c67a470b PZ |
7442 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
7443 | ||
7444 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
7445 | lpt_init_pch_refclk(dev); |
7446 | ||
7447 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
7448 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
7449 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
7450 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
7451 | } | |
7452 | ||
7453 | intel_prepare_ddi(dev); | |
c67a470b PZ |
7454 | } |
7455 | ||
9a952a0d PZ |
7456 | static void snb_modeset_global_resources(struct drm_device *dev) |
7457 | { | |
7458 | modeset_update_crtc_power_domains(dev); | |
7459 | } | |
7460 | ||
4f074129 ID |
7461 | static void haswell_modeset_global_resources(struct drm_device *dev) |
7462 | { | |
da723569 | 7463 | modeset_update_crtc_power_domains(dev); |
d6dd9eb1 DV |
7464 | } |
7465 | ||
09b4ddf9 | 7466 | static int haswell_crtc_mode_set(struct drm_crtc *crtc, |
09b4ddf9 PZ |
7467 | int x, int y, |
7468 | struct drm_framebuffer *fb) | |
7469 | { | |
09b4ddf9 | 7470 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
09b4ddf9 | 7471 | |
566b734a | 7472 | if (!intel_ddi_pll_select(intel_crtc)) |
6441ab5f | 7473 | return -EINVAL; |
566b734a | 7474 | intel_ddi_pll_enable(intel_crtc); |
6441ab5f | 7475 | |
644cef34 DV |
7476 | intel_crtc->lowfreq_avail = false; |
7477 | ||
c8f7a0db | 7478 | return 0; |
79e53945 JB |
7479 | } |
7480 | ||
0e8ffe1b DV |
7481 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
7482 | struct intel_crtc_config *pipe_config) | |
7483 | { | |
7484 | struct drm_device *dev = crtc->base.dev; | |
7485 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 7486 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
7487 | uint32_t tmp; |
7488 | ||
b5482bd0 ID |
7489 | if (!intel_display_power_enabled(dev_priv, |
7490 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
7491 | return false; | |
7492 | ||
e143a21c | 7493 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
7494 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
7495 | ||
eccb140b DV |
7496 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
7497 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
7498 | enum pipe trans_edp_pipe; | |
7499 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
7500 | default: | |
7501 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
7502 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
7503 | case TRANS_DDI_EDP_INPUT_A_ON: | |
7504 | trans_edp_pipe = PIPE_A; | |
7505 | break; | |
7506 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
7507 | trans_edp_pipe = PIPE_B; | |
7508 | break; | |
7509 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
7510 | trans_edp_pipe = PIPE_C; | |
7511 | break; | |
7512 | } | |
7513 | ||
7514 | if (trans_edp_pipe == crtc->pipe) | |
7515 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
7516 | } | |
7517 | ||
da7e29bd | 7518 | if (!intel_display_power_enabled(dev_priv, |
eccb140b | 7519 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
7520 | return false; |
7521 | ||
eccb140b | 7522 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
7523 | if (!(tmp & PIPECONF_ENABLE)) |
7524 | return false; | |
7525 | ||
88adfff1 | 7526 | /* |
f196e6be | 7527 | * Haswell has only FDI/PCH transcoder A. It is which is connected to |
88adfff1 DV |
7528 | * DDI E. So just check whether this pipe is wired to DDI E and whether |
7529 | * the PCH transcoder is on. | |
7530 | */ | |
eccb140b | 7531 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); |
88adfff1 | 7532 | if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) && |
ab9412ba | 7533 | I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { |
88adfff1 DV |
7534 | pipe_config->has_pch_encoder = true; |
7535 | ||
627eb5a3 DV |
7536 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); |
7537 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
7538 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
7539 | |
7540 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
627eb5a3 DV |
7541 | } |
7542 | ||
1bd1bd80 DV |
7543 | intel_get_pipe_timings(crtc, pipe_config); |
7544 | ||
2fa2fe9a | 7545 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
da7e29bd | 7546 | if (intel_display_power_enabled(dev_priv, pfit_domain)) |
2fa2fe9a | 7547 | ironlake_get_pfit_config(crtc, pipe_config); |
88adfff1 | 7548 | |
e59150dc JB |
7549 | if (IS_HASWELL(dev)) |
7550 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
7551 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 7552 | |
6c49f241 DV |
7553 | pipe_config->pixel_multiplier = 1; |
7554 | ||
0e8ffe1b DV |
7555 | return true; |
7556 | } | |
7557 | ||
1a91510d JN |
7558 | static struct { |
7559 | int clock; | |
7560 | u32 config; | |
7561 | } hdmi_audio_clock[] = { | |
7562 | { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, | |
7563 | { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ | |
7564 | { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, | |
7565 | { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, | |
7566 | { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, | |
7567 | { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, | |
7568 | { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, | |
7569 | { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, | |
7570 | { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, | |
7571 | { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, | |
7572 | }; | |
7573 | ||
7574 | /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ | |
7575 | static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode) | |
7576 | { | |
7577 | int i; | |
7578 | ||
7579 | for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { | |
7580 | if (mode->clock == hdmi_audio_clock[i].clock) | |
7581 | break; | |
7582 | } | |
7583 | ||
7584 | if (i == ARRAY_SIZE(hdmi_audio_clock)) { | |
7585 | DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock); | |
7586 | i = 1; | |
7587 | } | |
7588 | ||
7589 | DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n", | |
7590 | hdmi_audio_clock[i].clock, | |
7591 | hdmi_audio_clock[i].config); | |
7592 | ||
7593 | return hdmi_audio_clock[i].config; | |
7594 | } | |
7595 | ||
3a9627f4 WF |
7596 | static bool intel_eld_uptodate(struct drm_connector *connector, |
7597 | int reg_eldv, uint32_t bits_eldv, | |
7598 | int reg_elda, uint32_t bits_elda, | |
7599 | int reg_edid) | |
7600 | { | |
7601 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7602 | uint8_t *eld = connector->eld; | |
7603 | uint32_t i; | |
7604 | ||
7605 | i = I915_READ(reg_eldv); | |
7606 | i &= bits_eldv; | |
7607 | ||
7608 | if (!eld[0]) | |
7609 | return !i; | |
7610 | ||
7611 | if (!i) | |
7612 | return false; | |
7613 | ||
7614 | i = I915_READ(reg_elda); | |
7615 | i &= ~bits_elda; | |
7616 | I915_WRITE(reg_elda, i); | |
7617 | ||
7618 | for (i = 0; i < eld[2]; i++) | |
7619 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) | |
7620 | return false; | |
7621 | ||
7622 | return true; | |
7623 | } | |
7624 | ||
e0dac65e | 7625 | static void g4x_write_eld(struct drm_connector *connector, |
34427052 JN |
7626 | struct drm_crtc *crtc, |
7627 | struct drm_display_mode *mode) | |
e0dac65e WF |
7628 | { |
7629 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7630 | uint8_t *eld = connector->eld; | |
7631 | uint32_t eldv; | |
7632 | uint32_t len; | |
7633 | uint32_t i; | |
7634 | ||
7635 | i = I915_READ(G4X_AUD_VID_DID); | |
7636 | ||
7637 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) | |
7638 | eldv = G4X_ELDV_DEVCL_DEVBLC; | |
7639 | else | |
7640 | eldv = G4X_ELDV_DEVCTG; | |
7641 | ||
3a9627f4 WF |
7642 | if (intel_eld_uptodate(connector, |
7643 | G4X_AUD_CNTL_ST, eldv, | |
7644 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, | |
7645 | G4X_HDMIW_HDMIEDID)) | |
7646 | return; | |
7647 | ||
e0dac65e WF |
7648 | i = I915_READ(G4X_AUD_CNTL_ST); |
7649 | i &= ~(eldv | G4X_ELD_ADDR); | |
7650 | len = (i >> 9) & 0x1f; /* ELD buffer size */ | |
7651 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
7652 | ||
7653 | if (!eld[0]) | |
7654 | return; | |
7655 | ||
7656 | len = min_t(uint8_t, eld[2], len); | |
7657 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7658 | for (i = 0; i < len; i++) | |
7659 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); | |
7660 | ||
7661 | i = I915_READ(G4X_AUD_CNTL_ST); | |
7662 | i |= eldv; | |
7663 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
7664 | } | |
7665 | ||
83358c85 | 7666 | static void haswell_write_eld(struct drm_connector *connector, |
34427052 JN |
7667 | struct drm_crtc *crtc, |
7668 | struct drm_display_mode *mode) | |
83358c85 WX |
7669 | { |
7670 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7671 | uint8_t *eld = connector->eld; | |
83358c85 WX |
7672 | uint32_t eldv; |
7673 | uint32_t i; | |
7674 | int len; | |
7675 | int pipe = to_intel_crtc(crtc)->pipe; | |
7676 | int tmp; | |
7677 | ||
7678 | int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe); | |
7679 | int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe); | |
7680 | int aud_config = HSW_AUD_CFG(pipe); | |
7681 | int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD; | |
7682 | ||
83358c85 WX |
7683 | /* Audio output enable */ |
7684 | DRM_DEBUG_DRIVER("HDMI audio: enable codec\n"); | |
7685 | tmp = I915_READ(aud_cntrl_st2); | |
7686 | tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4)); | |
7687 | I915_WRITE(aud_cntrl_st2, tmp); | |
c7905792 | 7688 | POSTING_READ(aud_cntrl_st2); |
83358c85 | 7689 | |
c7905792 | 7690 | assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe); |
83358c85 WX |
7691 | |
7692 | /* Set ELD valid state */ | |
7693 | tmp = I915_READ(aud_cntrl_st2); | |
7e7cb34f | 7694 | DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp); |
83358c85 WX |
7695 | tmp |= (AUDIO_ELD_VALID_A << (pipe * 4)); |
7696 | I915_WRITE(aud_cntrl_st2, tmp); | |
7697 | tmp = I915_READ(aud_cntrl_st2); | |
7e7cb34f | 7698 | DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp); |
83358c85 WX |
7699 | |
7700 | /* Enable HDMI mode */ | |
7701 | tmp = I915_READ(aud_config); | |
7e7cb34f | 7702 | DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp); |
83358c85 WX |
7703 | /* clear N_programing_enable and N_value_index */ |
7704 | tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE); | |
7705 | I915_WRITE(aud_config, tmp); | |
7706 | ||
7707 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); | |
7708 | ||
7709 | eldv = AUDIO_ELD_VALID_A << (pipe * 4); | |
7710 | ||
7711 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { | |
7712 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
7713 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
7714 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ | |
1a91510d JN |
7715 | } else { |
7716 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); | |
7717 | } | |
83358c85 WX |
7718 | |
7719 | if (intel_eld_uptodate(connector, | |
7720 | aud_cntrl_st2, eldv, | |
7721 | aud_cntl_st, IBX_ELD_ADDRESS, | |
7722 | hdmiw_hdmiedid)) | |
7723 | return; | |
7724 | ||
7725 | i = I915_READ(aud_cntrl_st2); | |
7726 | i &= ~eldv; | |
7727 | I915_WRITE(aud_cntrl_st2, i); | |
7728 | ||
7729 | if (!eld[0]) | |
7730 | return; | |
7731 | ||
7732 | i = I915_READ(aud_cntl_st); | |
7733 | i &= ~IBX_ELD_ADDRESS; | |
7734 | I915_WRITE(aud_cntl_st, i); | |
7735 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ | |
7736 | DRM_DEBUG_DRIVER("port num:%d\n", i); | |
7737 | ||
7738 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
7739 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7740 | for (i = 0; i < len; i++) | |
7741 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
7742 | ||
7743 | i = I915_READ(aud_cntrl_st2); | |
7744 | i |= eldv; | |
7745 | I915_WRITE(aud_cntrl_st2, i); | |
7746 | ||
7747 | } | |
7748 | ||
e0dac65e | 7749 | static void ironlake_write_eld(struct drm_connector *connector, |
34427052 JN |
7750 | struct drm_crtc *crtc, |
7751 | struct drm_display_mode *mode) | |
e0dac65e WF |
7752 | { |
7753 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7754 | uint8_t *eld = connector->eld; | |
7755 | uint32_t eldv; | |
7756 | uint32_t i; | |
7757 | int len; | |
7758 | int hdmiw_hdmiedid; | |
b6daa025 | 7759 | int aud_config; |
e0dac65e WF |
7760 | int aud_cntl_st; |
7761 | int aud_cntrl_st2; | |
9b138a83 | 7762 | int pipe = to_intel_crtc(crtc)->pipe; |
e0dac65e | 7763 | |
b3f33cbf | 7764 | if (HAS_PCH_IBX(connector->dev)) { |
9b138a83 WX |
7765 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); |
7766 | aud_config = IBX_AUD_CFG(pipe); | |
7767 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); | |
1202b4c6 | 7768 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
9ca2fe73 ML |
7769 | } else if (IS_VALLEYVIEW(connector->dev)) { |
7770 | hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); | |
7771 | aud_config = VLV_AUD_CFG(pipe); | |
7772 | aud_cntl_st = VLV_AUD_CNTL_ST(pipe); | |
7773 | aud_cntrl_st2 = VLV_AUD_CNTL_ST2; | |
e0dac65e | 7774 | } else { |
9b138a83 WX |
7775 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); |
7776 | aud_config = CPT_AUD_CFG(pipe); | |
7777 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); | |
1202b4c6 | 7778 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
e0dac65e WF |
7779 | } |
7780 | ||
9b138a83 | 7781 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
e0dac65e | 7782 | |
9ca2fe73 ML |
7783 | if (IS_VALLEYVIEW(connector->dev)) { |
7784 | struct intel_encoder *intel_encoder; | |
7785 | struct intel_digital_port *intel_dig_port; | |
7786 | ||
7787 | intel_encoder = intel_attached_encoder(connector); | |
7788 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
7789 | i = intel_dig_port->port; | |
7790 | } else { | |
7791 | i = I915_READ(aud_cntl_st); | |
7792 | i = (i >> 29) & DIP_PORT_SEL_MASK; | |
7793 | /* DIP_Port_Select, 0x1 = PortB */ | |
7794 | } | |
7795 | ||
e0dac65e WF |
7796 | if (!i) { |
7797 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); | |
7798 | /* operate blindly on all ports */ | |
1202b4c6 WF |
7799 | eldv = IBX_ELD_VALIDB; |
7800 | eldv |= IBX_ELD_VALIDB << 4; | |
7801 | eldv |= IBX_ELD_VALIDB << 8; | |
e0dac65e | 7802 | } else { |
2582a850 | 7803 | DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i)); |
1202b4c6 | 7804 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
e0dac65e WF |
7805 | } |
7806 | ||
3a9627f4 WF |
7807 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
7808 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
7809 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
b6daa025 | 7810 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
1a91510d JN |
7811 | } else { |
7812 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); | |
7813 | } | |
e0dac65e | 7814 | |
3a9627f4 WF |
7815 | if (intel_eld_uptodate(connector, |
7816 | aud_cntrl_st2, eldv, | |
7817 | aud_cntl_st, IBX_ELD_ADDRESS, | |
7818 | hdmiw_hdmiedid)) | |
7819 | return; | |
7820 | ||
e0dac65e WF |
7821 | i = I915_READ(aud_cntrl_st2); |
7822 | i &= ~eldv; | |
7823 | I915_WRITE(aud_cntrl_st2, i); | |
7824 | ||
7825 | if (!eld[0]) | |
7826 | return; | |
7827 | ||
e0dac65e | 7828 | i = I915_READ(aud_cntl_st); |
1202b4c6 | 7829 | i &= ~IBX_ELD_ADDRESS; |
e0dac65e WF |
7830 | I915_WRITE(aud_cntl_st, i); |
7831 | ||
7832 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
7833 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7834 | for (i = 0; i < len; i++) | |
7835 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
7836 | ||
7837 | i = I915_READ(aud_cntrl_st2); | |
7838 | i |= eldv; | |
7839 | I915_WRITE(aud_cntrl_st2, i); | |
7840 | } | |
7841 | ||
7842 | void intel_write_eld(struct drm_encoder *encoder, | |
7843 | struct drm_display_mode *mode) | |
7844 | { | |
7845 | struct drm_crtc *crtc = encoder->crtc; | |
7846 | struct drm_connector *connector; | |
7847 | struct drm_device *dev = encoder->dev; | |
7848 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7849 | ||
7850 | connector = drm_select_eld(encoder, mode); | |
7851 | if (!connector) | |
7852 | return; | |
7853 | ||
7854 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", | |
7855 | connector->base.id, | |
7856 | drm_get_connector_name(connector), | |
7857 | connector->encoder->base.id, | |
7858 | drm_get_encoder_name(connector->encoder)); | |
7859 | ||
7860 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; | |
7861 | ||
7862 | if (dev_priv->display.write_eld) | |
34427052 | 7863 | dev_priv->display.write_eld(connector, crtc, mode); |
e0dac65e WF |
7864 | } |
7865 | ||
560b85bb CW |
7866 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
7867 | { | |
7868 | struct drm_device *dev = crtc->dev; | |
7869 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7870 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7871 | bool visible = base != 0; | |
7872 | u32 cntl; | |
7873 | ||
7874 | if (intel_crtc->cursor_visible == visible) | |
7875 | return; | |
7876 | ||
9db4a9c7 | 7877 | cntl = I915_READ(_CURACNTR); |
560b85bb CW |
7878 | if (visible) { |
7879 | /* On these chipsets we can only modify the base whilst | |
7880 | * the cursor is disabled. | |
7881 | */ | |
9db4a9c7 | 7882 | I915_WRITE(_CURABASE, base); |
560b85bb CW |
7883 | |
7884 | cntl &= ~(CURSOR_FORMAT_MASK); | |
7885 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ | |
7886 | cntl |= CURSOR_ENABLE | | |
7887 | CURSOR_GAMMA_ENABLE | | |
7888 | CURSOR_FORMAT_ARGB; | |
7889 | } else | |
7890 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); | |
9db4a9c7 | 7891 | I915_WRITE(_CURACNTR, cntl); |
560b85bb CW |
7892 | |
7893 | intel_crtc->cursor_visible = visible; | |
7894 | } | |
7895 | ||
7896 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) | |
7897 | { | |
7898 | struct drm_device *dev = crtc->dev; | |
7899 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7900 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7901 | int pipe = intel_crtc->pipe; | |
7902 | bool visible = base != 0; | |
7903 | ||
7904 | if (intel_crtc->cursor_visible != visible) { | |
4726e0b0 | 7905 | int16_t width = intel_crtc->cursor_width; |
548f245b | 7906 | uint32_t cntl = I915_READ(CURCNTR(pipe)); |
560b85bb CW |
7907 | if (base) { |
7908 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); | |
4726e0b0 SK |
7909 | cntl |= MCURSOR_GAMMA_ENABLE; |
7910 | ||
7911 | switch (width) { | |
7912 | case 64: | |
7913 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
7914 | break; | |
7915 | case 128: | |
7916 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
7917 | break; | |
7918 | case 256: | |
7919 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
7920 | break; | |
7921 | default: | |
7922 | WARN_ON(1); | |
7923 | return; | |
7924 | } | |
560b85bb CW |
7925 | cntl |= pipe << 28; /* Connect to correct pipe */ |
7926 | } else { | |
7927 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
7928 | cntl |= CURSOR_MODE_DISABLE; | |
7929 | } | |
9db4a9c7 | 7930 | I915_WRITE(CURCNTR(pipe), cntl); |
560b85bb CW |
7931 | |
7932 | intel_crtc->cursor_visible = visible; | |
7933 | } | |
7934 | /* and commit changes on next vblank */ | |
b2ea8ef5 | 7935 | POSTING_READ(CURCNTR(pipe)); |
9db4a9c7 | 7936 | I915_WRITE(CURBASE(pipe), base); |
b2ea8ef5 | 7937 | POSTING_READ(CURBASE(pipe)); |
560b85bb CW |
7938 | } |
7939 | ||
65a21cd6 JB |
7940 | static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) |
7941 | { | |
7942 | struct drm_device *dev = crtc->dev; | |
7943 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7944 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7945 | int pipe = intel_crtc->pipe; | |
7946 | bool visible = base != 0; | |
7947 | ||
7948 | if (intel_crtc->cursor_visible != visible) { | |
4726e0b0 | 7949 | int16_t width = intel_crtc->cursor_width; |
5efb3e28 | 7950 | uint32_t cntl = I915_READ(CURCNTR(pipe)); |
65a21cd6 JB |
7951 | if (base) { |
7952 | cntl &= ~CURSOR_MODE; | |
4726e0b0 SK |
7953 | cntl |= MCURSOR_GAMMA_ENABLE; |
7954 | switch (width) { | |
7955 | case 64: | |
7956 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
7957 | break; | |
7958 | case 128: | |
7959 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
7960 | break; | |
7961 | case 256: | |
7962 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
7963 | break; | |
7964 | default: | |
7965 | WARN_ON(1); | |
7966 | return; | |
7967 | } | |
65a21cd6 JB |
7968 | } else { |
7969 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
7970 | cntl |= CURSOR_MODE_DISABLE; | |
7971 | } | |
6bbfa1c5 | 7972 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
86d3efce | 7973 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
1f5d76db PZ |
7974 | cntl &= ~CURSOR_TRICKLE_FEED_DISABLE; |
7975 | } | |
5efb3e28 | 7976 | I915_WRITE(CURCNTR(pipe), cntl); |
65a21cd6 JB |
7977 | |
7978 | intel_crtc->cursor_visible = visible; | |
7979 | } | |
7980 | /* and commit changes on next vblank */ | |
5efb3e28 VS |
7981 | POSTING_READ(CURCNTR(pipe)); |
7982 | I915_WRITE(CURBASE(pipe), base); | |
7983 | POSTING_READ(CURBASE(pipe)); | |
65a21cd6 JB |
7984 | } |
7985 | ||
cda4b7d3 | 7986 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
7987 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
7988 | bool on) | |
cda4b7d3 CW |
7989 | { |
7990 | struct drm_device *dev = crtc->dev; | |
7991 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7992 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7993 | int pipe = intel_crtc->pipe; | |
7994 | int x = intel_crtc->cursor_x; | |
7995 | int y = intel_crtc->cursor_y; | |
d6e4db15 | 7996 | u32 base = 0, pos = 0; |
cda4b7d3 CW |
7997 | bool visible; |
7998 | ||
d6e4db15 | 7999 | if (on) |
cda4b7d3 | 8000 | base = intel_crtc->cursor_addr; |
cda4b7d3 | 8001 | |
d6e4db15 VS |
8002 | if (x >= intel_crtc->config.pipe_src_w) |
8003 | base = 0; | |
8004 | ||
8005 | if (y >= intel_crtc->config.pipe_src_h) | |
cda4b7d3 CW |
8006 | base = 0; |
8007 | ||
8008 | if (x < 0) { | |
efc9064e | 8009 | if (x + intel_crtc->cursor_width <= 0) |
cda4b7d3 CW |
8010 | base = 0; |
8011 | ||
8012 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
8013 | x = -x; | |
8014 | } | |
8015 | pos |= x << CURSOR_X_SHIFT; | |
8016 | ||
8017 | if (y < 0) { | |
efc9064e | 8018 | if (y + intel_crtc->cursor_height <= 0) |
cda4b7d3 CW |
8019 | base = 0; |
8020 | ||
8021 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
8022 | y = -y; | |
8023 | } | |
8024 | pos |= y << CURSOR_Y_SHIFT; | |
8025 | ||
8026 | visible = base != 0; | |
560b85bb | 8027 | if (!visible && !intel_crtc->cursor_visible) |
cda4b7d3 CW |
8028 | return; |
8029 | ||
5efb3e28 VS |
8030 | I915_WRITE(CURPOS(pipe), pos); |
8031 | ||
8032 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
65a21cd6 | 8033 | ivb_update_cursor(crtc, base); |
5efb3e28 VS |
8034 | else if (IS_845G(dev) || IS_I865G(dev)) |
8035 | i845_update_cursor(crtc, base); | |
8036 | else | |
8037 | i9xx_update_cursor(crtc, base); | |
cda4b7d3 CW |
8038 | } |
8039 | ||
79e53945 | 8040 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
05394f39 | 8041 | struct drm_file *file, |
79e53945 JB |
8042 | uint32_t handle, |
8043 | uint32_t width, uint32_t height) | |
8044 | { | |
8045 | struct drm_device *dev = crtc->dev; | |
8046 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8047 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 8048 | struct drm_i915_gem_object *obj; |
64f962e3 | 8049 | unsigned old_width; |
cda4b7d3 | 8050 | uint32_t addr; |
3f8bc370 | 8051 | int ret; |
79e53945 | 8052 | |
79e53945 JB |
8053 | /* if we want to turn off the cursor ignore width and height */ |
8054 | if (!handle) { | |
28c97730 | 8055 | DRM_DEBUG_KMS("cursor off\n"); |
3f8bc370 | 8056 | addr = 0; |
05394f39 | 8057 | obj = NULL; |
5004417d | 8058 | mutex_lock(&dev->struct_mutex); |
3f8bc370 | 8059 | goto finish; |
79e53945 JB |
8060 | } |
8061 | ||
4726e0b0 SK |
8062 | /* Check for which cursor types we support */ |
8063 | if (!((width == 64 && height == 64) || | |
8064 | (width == 128 && height == 128 && !IS_GEN2(dev)) || | |
8065 | (width == 256 && height == 256 && !IS_GEN2(dev)))) { | |
8066 | DRM_DEBUG("Cursor dimension not supported\n"); | |
79e53945 JB |
8067 | return -EINVAL; |
8068 | } | |
8069 | ||
05394f39 | 8070 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 8071 | if (&obj->base == NULL) |
79e53945 JB |
8072 | return -ENOENT; |
8073 | ||
05394f39 | 8074 | if (obj->base.size < width * height * 4) { |
3b25b31f | 8075 | DRM_DEBUG_KMS("buffer is to small\n"); |
34b8686e DA |
8076 | ret = -ENOMEM; |
8077 | goto fail; | |
79e53945 JB |
8078 | } |
8079 | ||
71acb5eb | 8080 | /* we only need to pin inside GTT if cursor is non-phy */ |
7f9872e0 | 8081 | mutex_lock(&dev->struct_mutex); |
3d13ef2e | 8082 | if (!INTEL_INFO(dev)->cursor_needs_physical) { |
693db184 CW |
8083 | unsigned alignment; |
8084 | ||
d9e86c0e | 8085 | if (obj->tiling_mode) { |
3b25b31f | 8086 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
d9e86c0e CW |
8087 | ret = -EINVAL; |
8088 | goto fail_locked; | |
8089 | } | |
8090 | ||
693db184 CW |
8091 | /* Note that the w/a also requires 2 PTE of padding following |
8092 | * the bo. We currently fill all unused PTE with the shadow | |
8093 | * page and so we should always have valid PTE following the | |
8094 | * cursor preventing the VT-d warning. | |
8095 | */ | |
8096 | alignment = 0; | |
8097 | if (need_vtd_wa(dev)) | |
8098 | alignment = 64*1024; | |
8099 | ||
8100 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL); | |
e7b526bb | 8101 | if (ret) { |
3b25b31f | 8102 | DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n"); |
2da3b9b9 | 8103 | goto fail_locked; |
e7b526bb CW |
8104 | } |
8105 | ||
d9e86c0e CW |
8106 | ret = i915_gem_object_put_fence(obj); |
8107 | if (ret) { | |
3b25b31f | 8108 | DRM_DEBUG_KMS("failed to release fence for cursor"); |
d9e86c0e CW |
8109 | goto fail_unpin; |
8110 | } | |
8111 | ||
f343c5f6 | 8112 | addr = i915_gem_obj_ggtt_offset(obj); |
71acb5eb | 8113 | } else { |
6eeefaf3 | 8114 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
05394f39 | 8115 | ret = i915_gem_attach_phys_object(dev, obj, |
6eeefaf3 CW |
8116 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
8117 | align); | |
71acb5eb | 8118 | if (ret) { |
3b25b31f | 8119 | DRM_DEBUG_KMS("failed to attach phys object\n"); |
7f9872e0 | 8120 | goto fail_locked; |
71acb5eb | 8121 | } |
05394f39 | 8122 | addr = obj->phys_obj->handle->busaddr; |
3f8bc370 KH |
8123 | } |
8124 | ||
a6c45cf0 | 8125 | if (IS_GEN2(dev)) |
14b60391 JB |
8126 | I915_WRITE(CURSIZE, (height << 12) | width); |
8127 | ||
3f8bc370 | 8128 | finish: |
3f8bc370 | 8129 | if (intel_crtc->cursor_bo) { |
3d13ef2e | 8130 | if (INTEL_INFO(dev)->cursor_needs_physical) { |
05394f39 | 8131 | if (intel_crtc->cursor_bo != obj) |
71acb5eb DA |
8132 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); |
8133 | } else | |
cc98b413 | 8134 | i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo); |
05394f39 | 8135 | drm_gem_object_unreference(&intel_crtc->cursor_bo->base); |
3f8bc370 | 8136 | } |
80824003 | 8137 | |
7f9872e0 | 8138 | mutex_unlock(&dev->struct_mutex); |
3f8bc370 | 8139 | |
64f962e3 CW |
8140 | old_width = intel_crtc->cursor_width; |
8141 | ||
3f8bc370 | 8142 | intel_crtc->cursor_addr = addr; |
05394f39 | 8143 | intel_crtc->cursor_bo = obj; |
cda4b7d3 CW |
8144 | intel_crtc->cursor_width = width; |
8145 | intel_crtc->cursor_height = height; | |
8146 | ||
64f962e3 CW |
8147 | if (intel_crtc->active) { |
8148 | if (old_width != width) | |
8149 | intel_update_watermarks(crtc); | |
f2f5f771 | 8150 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); |
64f962e3 | 8151 | } |
3f8bc370 | 8152 | |
79e53945 | 8153 | return 0; |
e7b526bb | 8154 | fail_unpin: |
cc98b413 | 8155 | i915_gem_object_unpin_from_display_plane(obj); |
7f9872e0 | 8156 | fail_locked: |
34b8686e | 8157 | mutex_unlock(&dev->struct_mutex); |
bc9025bd | 8158 | fail: |
05394f39 | 8159 | drm_gem_object_unreference_unlocked(&obj->base); |
34b8686e | 8160 | return ret; |
79e53945 JB |
8161 | } |
8162 | ||
8163 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
8164 | { | |
79e53945 | 8165 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 8166 | |
92e76c8c VS |
8167 | intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX); |
8168 | intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX); | |
652c393a | 8169 | |
f2f5f771 VS |
8170 | if (intel_crtc->active) |
8171 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); | |
79e53945 JB |
8172 | |
8173 | return 0; | |
b8c00ac5 DA |
8174 | } |
8175 | ||
79e53945 | 8176 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 8177 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 8178 | { |
7203425a | 8179 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 8180 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 8181 | |
7203425a | 8182 | for (i = start; i < end; i++) { |
79e53945 JB |
8183 | intel_crtc->lut_r[i] = red[i] >> 8; |
8184 | intel_crtc->lut_g[i] = green[i] >> 8; | |
8185 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
8186 | } | |
8187 | ||
8188 | intel_crtc_load_lut(crtc); | |
8189 | } | |
8190 | ||
79e53945 JB |
8191 | /* VESA 640x480x72Hz mode to set on the pipe */ |
8192 | static struct drm_display_mode load_detect_mode = { | |
8193 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
8194 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
8195 | }; | |
8196 | ||
a8bb6818 DV |
8197 | struct drm_framebuffer * |
8198 | __intel_framebuffer_create(struct drm_device *dev, | |
8199 | struct drm_mode_fb_cmd2 *mode_cmd, | |
8200 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
8201 | { |
8202 | struct intel_framebuffer *intel_fb; | |
8203 | int ret; | |
8204 | ||
8205 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
8206 | if (!intel_fb) { | |
8207 | drm_gem_object_unreference_unlocked(&obj->base); | |
8208 | return ERR_PTR(-ENOMEM); | |
8209 | } | |
8210 | ||
8211 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
8212 | if (ret) |
8213 | goto err; | |
d2dff872 CW |
8214 | |
8215 | return &intel_fb->base; | |
dd4916c5 DV |
8216 | err: |
8217 | drm_gem_object_unreference_unlocked(&obj->base); | |
8218 | kfree(intel_fb); | |
8219 | ||
8220 | return ERR_PTR(ret); | |
d2dff872 CW |
8221 | } |
8222 | ||
b5ea642a | 8223 | static struct drm_framebuffer * |
a8bb6818 DV |
8224 | intel_framebuffer_create(struct drm_device *dev, |
8225 | struct drm_mode_fb_cmd2 *mode_cmd, | |
8226 | struct drm_i915_gem_object *obj) | |
8227 | { | |
8228 | struct drm_framebuffer *fb; | |
8229 | int ret; | |
8230 | ||
8231 | ret = i915_mutex_lock_interruptible(dev); | |
8232 | if (ret) | |
8233 | return ERR_PTR(ret); | |
8234 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
8235 | mutex_unlock(&dev->struct_mutex); | |
8236 | ||
8237 | return fb; | |
8238 | } | |
8239 | ||
d2dff872 CW |
8240 | static u32 |
8241 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
8242 | { | |
8243 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
8244 | return ALIGN(pitch, 64); | |
8245 | } | |
8246 | ||
8247 | static u32 | |
8248 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
8249 | { | |
8250 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
8251 | return ALIGN(pitch * mode->vdisplay, PAGE_SIZE); | |
8252 | } | |
8253 | ||
8254 | static struct drm_framebuffer * | |
8255 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
8256 | struct drm_display_mode *mode, | |
8257 | int depth, int bpp) | |
8258 | { | |
8259 | struct drm_i915_gem_object *obj; | |
0fed39bd | 8260 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
8261 | |
8262 | obj = i915_gem_alloc_object(dev, | |
8263 | intel_framebuffer_size_for_mode(mode, bpp)); | |
8264 | if (obj == NULL) | |
8265 | return ERR_PTR(-ENOMEM); | |
8266 | ||
8267 | mode_cmd.width = mode->hdisplay; | |
8268 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
8269 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
8270 | bpp); | |
5ca0c34a | 8271 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
8272 | |
8273 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
8274 | } | |
8275 | ||
8276 | static struct drm_framebuffer * | |
8277 | mode_fits_in_fbdev(struct drm_device *dev, | |
8278 | struct drm_display_mode *mode) | |
8279 | { | |
4520f53a | 8280 | #ifdef CONFIG_DRM_I915_FBDEV |
d2dff872 CW |
8281 | struct drm_i915_private *dev_priv = dev->dev_private; |
8282 | struct drm_i915_gem_object *obj; | |
8283 | struct drm_framebuffer *fb; | |
8284 | ||
4c0e5528 | 8285 | if (!dev_priv->fbdev) |
d2dff872 CW |
8286 | return NULL; |
8287 | ||
4c0e5528 | 8288 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
8289 | return NULL; |
8290 | ||
4c0e5528 DV |
8291 | obj = dev_priv->fbdev->fb->obj; |
8292 | BUG_ON(!obj); | |
8293 | ||
8bcd4553 | 8294 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
8295 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
8296 | fb->bits_per_pixel)) | |
d2dff872 CW |
8297 | return NULL; |
8298 | ||
01f2c773 | 8299 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
8300 | return NULL; |
8301 | ||
8302 | return fb; | |
4520f53a DV |
8303 | #else |
8304 | return NULL; | |
8305 | #endif | |
d2dff872 CW |
8306 | } |
8307 | ||
d2434ab7 | 8308 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 8309 | struct drm_display_mode *mode, |
8261b191 | 8310 | struct intel_load_detect_pipe *old) |
79e53945 JB |
8311 | { |
8312 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
8313 | struct intel_encoder *intel_encoder = |
8314 | intel_attached_encoder(connector); | |
79e53945 | 8315 | struct drm_crtc *possible_crtc; |
4ef69c7a | 8316 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
8317 | struct drm_crtc *crtc = NULL; |
8318 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 8319 | struct drm_framebuffer *fb; |
79e53945 JB |
8320 | int i = -1; |
8321 | ||
d2dff872 CW |
8322 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
8323 | connector->base.id, drm_get_connector_name(connector), | |
8324 | encoder->base.id, drm_get_encoder_name(encoder)); | |
8325 | ||
79e53945 JB |
8326 | /* |
8327 | * Algorithm gets a little messy: | |
7a5e4805 | 8328 | * |
79e53945 JB |
8329 | * - if the connector already has an assigned crtc, use it (but make |
8330 | * sure it's on first) | |
7a5e4805 | 8331 | * |
79e53945 JB |
8332 | * - try to find the first unused crtc that can drive this connector, |
8333 | * and use that if we find one | |
79e53945 JB |
8334 | */ |
8335 | ||
8336 | /* See if we already have a CRTC for this connector */ | |
8337 | if (encoder->crtc) { | |
8338 | crtc = encoder->crtc; | |
8261b191 | 8339 | |
7b24056b DV |
8340 | mutex_lock(&crtc->mutex); |
8341 | ||
24218aac | 8342 | old->dpms_mode = connector->dpms; |
8261b191 CW |
8343 | old->load_detect_temp = false; |
8344 | ||
8345 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
8346 | if (connector->dpms != DRM_MODE_DPMS_ON) |
8347 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 8348 | |
7173188d | 8349 | return true; |
79e53945 JB |
8350 | } |
8351 | ||
8352 | /* Find an unused one (if possible) */ | |
70e1e0ec | 8353 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
8354 | i++; |
8355 | if (!(encoder->possible_crtcs & (1 << i))) | |
8356 | continue; | |
8357 | if (!possible_crtc->enabled) { | |
8358 | crtc = possible_crtc; | |
8359 | break; | |
8360 | } | |
79e53945 JB |
8361 | } |
8362 | ||
8363 | /* | |
8364 | * If we didn't find an unused CRTC, don't use any. | |
8365 | */ | |
8366 | if (!crtc) { | |
7173188d CW |
8367 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
8368 | return false; | |
79e53945 JB |
8369 | } |
8370 | ||
7b24056b | 8371 | mutex_lock(&crtc->mutex); |
fc303101 DV |
8372 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
8373 | to_intel_connector(connector)->new_encoder = intel_encoder; | |
79e53945 JB |
8374 | |
8375 | intel_crtc = to_intel_crtc(crtc); | |
412b61d8 VS |
8376 | intel_crtc->new_enabled = true; |
8377 | intel_crtc->new_config = &intel_crtc->config; | |
24218aac | 8378 | old->dpms_mode = connector->dpms; |
8261b191 | 8379 | old->load_detect_temp = true; |
d2dff872 | 8380 | old->release_fb = NULL; |
79e53945 | 8381 | |
6492711d CW |
8382 | if (!mode) |
8383 | mode = &load_detect_mode; | |
79e53945 | 8384 | |
d2dff872 CW |
8385 | /* We need a framebuffer large enough to accommodate all accesses |
8386 | * that the plane may generate whilst we perform load detection. | |
8387 | * We can not rely on the fbcon either being present (we get called | |
8388 | * during its initialisation to detect all boot displays, or it may | |
8389 | * not even exist) or that it is large enough to satisfy the | |
8390 | * requested mode. | |
8391 | */ | |
94352cf9 DV |
8392 | fb = mode_fits_in_fbdev(dev, mode); |
8393 | if (fb == NULL) { | |
d2dff872 | 8394 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
8395 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
8396 | old->release_fb = fb; | |
d2dff872 CW |
8397 | } else |
8398 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 8399 | if (IS_ERR(fb)) { |
d2dff872 | 8400 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 8401 | goto fail; |
79e53945 | 8402 | } |
79e53945 | 8403 | |
c0c36b94 | 8404 | if (intel_set_mode(crtc, mode, 0, 0, fb)) { |
6492711d | 8405 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
8406 | if (old->release_fb) |
8407 | old->release_fb->funcs->destroy(old->release_fb); | |
412b61d8 | 8408 | goto fail; |
79e53945 | 8409 | } |
7173188d | 8410 | |
79e53945 | 8411 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 8412 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 8413 | return true; |
412b61d8 VS |
8414 | |
8415 | fail: | |
8416 | intel_crtc->new_enabled = crtc->enabled; | |
8417 | if (intel_crtc->new_enabled) | |
8418 | intel_crtc->new_config = &intel_crtc->config; | |
8419 | else | |
8420 | intel_crtc->new_config = NULL; | |
8421 | mutex_unlock(&crtc->mutex); | |
8422 | return false; | |
79e53945 JB |
8423 | } |
8424 | ||
d2434ab7 | 8425 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
8261b191 | 8426 | struct intel_load_detect_pipe *old) |
79e53945 | 8427 | { |
d2434ab7 DV |
8428 | struct intel_encoder *intel_encoder = |
8429 | intel_attached_encoder(connector); | |
4ef69c7a | 8430 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 8431 | struct drm_crtc *crtc = encoder->crtc; |
412b61d8 | 8432 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 8433 | |
d2dff872 CW |
8434 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
8435 | connector->base.id, drm_get_connector_name(connector), | |
8436 | encoder->base.id, drm_get_encoder_name(encoder)); | |
8437 | ||
8261b191 | 8438 | if (old->load_detect_temp) { |
fc303101 DV |
8439 | to_intel_connector(connector)->new_encoder = NULL; |
8440 | intel_encoder->new_crtc = NULL; | |
412b61d8 VS |
8441 | intel_crtc->new_enabled = false; |
8442 | intel_crtc->new_config = NULL; | |
fc303101 | 8443 | intel_set_mode(crtc, NULL, 0, 0, NULL); |
d2dff872 | 8444 | |
36206361 DV |
8445 | if (old->release_fb) { |
8446 | drm_framebuffer_unregister_private(old->release_fb); | |
8447 | drm_framebuffer_unreference(old->release_fb); | |
8448 | } | |
d2dff872 | 8449 | |
67c96400 | 8450 | mutex_unlock(&crtc->mutex); |
0622a53c | 8451 | return; |
79e53945 JB |
8452 | } |
8453 | ||
c751ce4f | 8454 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
8455 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
8456 | connector->funcs->dpms(connector, old->dpms_mode); | |
7b24056b DV |
8457 | |
8458 | mutex_unlock(&crtc->mutex); | |
79e53945 JB |
8459 | } |
8460 | ||
da4a1efa VS |
8461 | static int i9xx_pll_refclk(struct drm_device *dev, |
8462 | const struct intel_crtc_config *pipe_config) | |
8463 | { | |
8464 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8465 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
8466 | ||
8467 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 8468 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
8469 | else if (HAS_PCH_SPLIT(dev)) |
8470 | return 120000; | |
8471 | else if (!IS_GEN2(dev)) | |
8472 | return 96000; | |
8473 | else | |
8474 | return 48000; | |
8475 | } | |
8476 | ||
79e53945 | 8477 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc JB |
8478 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
8479 | struct intel_crtc_config *pipe_config) | |
79e53945 | 8480 | { |
f1f644dc | 8481 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 8482 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 8483 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 8484 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
8485 | u32 fp; |
8486 | intel_clock_t clock; | |
da4a1efa | 8487 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
8488 | |
8489 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 8490 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 8491 | else |
293623f7 | 8492 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
8493 | |
8494 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
8495 | if (IS_PINEVIEW(dev)) { |
8496 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
8497 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
8498 | } else { |
8499 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
8500 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
8501 | } | |
8502 | ||
a6c45cf0 | 8503 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
8504 | if (IS_PINEVIEW(dev)) |
8505 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
8506 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
8507 | else |
8508 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
8509 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
8510 | ||
8511 | switch (dpll & DPLL_MODE_MASK) { | |
8512 | case DPLLB_MODE_DAC_SERIAL: | |
8513 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
8514 | 5 : 10; | |
8515 | break; | |
8516 | case DPLLB_MODE_LVDS: | |
8517 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
8518 | 7 : 14; | |
8519 | break; | |
8520 | default: | |
28c97730 | 8521 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 8522 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 8523 | return; |
79e53945 JB |
8524 | } |
8525 | ||
ac58c3f0 | 8526 | if (IS_PINEVIEW(dev)) |
da4a1efa | 8527 | pineview_clock(refclk, &clock); |
ac58c3f0 | 8528 | else |
da4a1efa | 8529 | i9xx_clock(refclk, &clock); |
79e53945 | 8530 | } else { |
0fb58223 | 8531 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 8532 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
8533 | |
8534 | if (is_lvds) { | |
8535 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
8536 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
8537 | |
8538 | if (lvds & LVDS_CLKB_POWER_UP) | |
8539 | clock.p2 = 7; | |
8540 | else | |
8541 | clock.p2 = 14; | |
79e53945 JB |
8542 | } else { |
8543 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
8544 | clock.p1 = 2; | |
8545 | else { | |
8546 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
8547 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
8548 | } | |
8549 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
8550 | clock.p2 = 4; | |
8551 | else | |
8552 | clock.p2 = 2; | |
79e53945 | 8553 | } |
da4a1efa VS |
8554 | |
8555 | i9xx_clock(refclk, &clock); | |
79e53945 JB |
8556 | } |
8557 | ||
18442d08 VS |
8558 | /* |
8559 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 8560 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
8561 | * encoder's get_config() function. |
8562 | */ | |
8563 | pipe_config->port_clock = clock.dot; | |
f1f644dc JB |
8564 | } |
8565 | ||
6878da05 VS |
8566 | int intel_dotclock_calculate(int link_freq, |
8567 | const struct intel_link_m_n *m_n) | |
f1f644dc | 8568 | { |
f1f644dc JB |
8569 | /* |
8570 | * The calculation for the data clock is: | |
1041a02f | 8571 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 8572 | * But we want to avoid losing precison if possible, so: |
1041a02f | 8573 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
8574 | * |
8575 | * and the link clock is simpler: | |
1041a02f | 8576 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
8577 | */ |
8578 | ||
6878da05 VS |
8579 | if (!m_n->link_n) |
8580 | return 0; | |
f1f644dc | 8581 | |
6878da05 VS |
8582 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
8583 | } | |
f1f644dc | 8584 | |
18442d08 VS |
8585 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
8586 | struct intel_crtc_config *pipe_config) | |
6878da05 VS |
8587 | { |
8588 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 8589 | |
18442d08 VS |
8590 | /* read out port_clock from the DPLL */ |
8591 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 8592 | |
f1f644dc | 8593 | /* |
18442d08 | 8594 | * This value does not include pixel_multiplier. |
241bfc38 | 8595 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
8596 | * agree once we know their relationship in the encoder's |
8597 | * get_config() function. | |
79e53945 | 8598 | */ |
241bfc38 | 8599 | pipe_config->adjusted_mode.crtc_clock = |
18442d08 VS |
8600 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
8601 | &pipe_config->fdi_m_n); | |
79e53945 JB |
8602 | } |
8603 | ||
8604 | /** Returns the currently programmed mode of the given pipe. */ | |
8605 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
8606 | struct drm_crtc *crtc) | |
8607 | { | |
548f245b | 8608 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 8609 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3b117c8f | 8610 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
79e53945 | 8611 | struct drm_display_mode *mode; |
f1f644dc | 8612 | struct intel_crtc_config pipe_config; |
fe2b8f9d PZ |
8613 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
8614 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
8615 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
8616 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 8617 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
8618 | |
8619 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
8620 | if (!mode) | |
8621 | return NULL; | |
8622 | ||
f1f644dc JB |
8623 | /* |
8624 | * Construct a pipe_config sufficient for getting the clock info | |
8625 | * back out of crtc_clock_get. | |
8626 | * | |
8627 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
8628 | * to use a real value here instead. | |
8629 | */ | |
293623f7 | 8630 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 8631 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
8632 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
8633 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
8634 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
8635 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
8636 | ||
773ae034 | 8637 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
79e53945 JB |
8638 | mode->hdisplay = (htot & 0xffff) + 1; |
8639 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
8640 | mode->hsync_start = (hsync & 0xffff) + 1; | |
8641 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
8642 | mode->vdisplay = (vtot & 0xffff) + 1; | |
8643 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
8644 | mode->vsync_start = (vsync & 0xffff) + 1; | |
8645 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
8646 | ||
8647 | drm_mode_set_name(mode); | |
79e53945 JB |
8648 | |
8649 | return mode; | |
8650 | } | |
8651 | ||
3dec0095 | 8652 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
652c393a JB |
8653 | { |
8654 | struct drm_device *dev = crtc->dev; | |
fbee40df | 8655 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a JB |
8656 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8657 | int pipe = intel_crtc->pipe; | |
dbdc6479 JB |
8658 | int dpll_reg = DPLL(pipe); |
8659 | int dpll; | |
652c393a | 8660 | |
bad720ff | 8661 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
8662 | return; |
8663 | ||
8664 | if (!dev_priv->lvds_downclock_avail) | |
8665 | return; | |
8666 | ||
dbdc6479 | 8667 | dpll = I915_READ(dpll_reg); |
652c393a | 8668 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
44d98a61 | 8669 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
652c393a | 8670 | |
8ac5a6d5 | 8671 | assert_panel_unlocked(dev_priv, pipe); |
652c393a JB |
8672 | |
8673 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; | |
8674 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 8675 | intel_wait_for_vblank(dev, pipe); |
dbdc6479 | 8676 | |
652c393a JB |
8677 | dpll = I915_READ(dpll_reg); |
8678 | if (dpll & DISPLAY_RATE_SELECT_FPA1) | |
44d98a61 | 8679 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
652c393a | 8680 | } |
652c393a JB |
8681 | } |
8682 | ||
8683 | static void intel_decrease_pllclock(struct drm_crtc *crtc) | |
8684 | { | |
8685 | struct drm_device *dev = crtc->dev; | |
fbee40df | 8686 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 8687 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
652c393a | 8688 | |
bad720ff | 8689 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
8690 | return; |
8691 | ||
8692 | if (!dev_priv->lvds_downclock_avail) | |
8693 | return; | |
8694 | ||
8695 | /* | |
8696 | * Since this is called by a timer, we should never get here in | |
8697 | * the manual case. | |
8698 | */ | |
8699 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
dc257cf1 DV |
8700 | int pipe = intel_crtc->pipe; |
8701 | int dpll_reg = DPLL(pipe); | |
8702 | int dpll; | |
f6e5b160 | 8703 | |
44d98a61 | 8704 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 8705 | |
8ac5a6d5 | 8706 | assert_panel_unlocked(dev_priv, pipe); |
652c393a | 8707 | |
dc257cf1 | 8708 | dpll = I915_READ(dpll_reg); |
652c393a JB |
8709 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
8710 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 8711 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
8712 | dpll = I915_READ(dpll_reg); |
8713 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 8714 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
8715 | } |
8716 | ||
8717 | } | |
8718 | ||
f047e395 CW |
8719 | void intel_mark_busy(struct drm_device *dev) |
8720 | { | |
c67a470b PZ |
8721 | struct drm_i915_private *dev_priv = dev->dev_private; |
8722 | ||
f62a0076 CW |
8723 | if (dev_priv->mm.busy) |
8724 | return; | |
8725 | ||
43694d69 | 8726 | intel_runtime_pm_get(dev_priv); |
c67a470b | 8727 | i915_update_gfx_val(dev_priv); |
f62a0076 | 8728 | dev_priv->mm.busy = true; |
f047e395 CW |
8729 | } |
8730 | ||
8731 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 8732 | { |
c67a470b | 8733 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 8734 | struct drm_crtc *crtc; |
652c393a | 8735 | |
f62a0076 CW |
8736 | if (!dev_priv->mm.busy) |
8737 | return; | |
8738 | ||
8739 | dev_priv->mm.busy = false; | |
8740 | ||
d330a953 | 8741 | if (!i915.powersave) |
bb4cdd53 | 8742 | goto out; |
652c393a | 8743 | |
70e1e0ec | 8744 | for_each_crtc(dev, crtc) { |
f4510a27 | 8745 | if (!crtc->primary->fb) |
652c393a JB |
8746 | continue; |
8747 | ||
725a5b54 | 8748 | intel_decrease_pllclock(crtc); |
652c393a | 8749 | } |
b29c19b6 | 8750 | |
3d13ef2e | 8751 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 8752 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 PZ |
8753 | |
8754 | out: | |
43694d69 | 8755 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
8756 | } |
8757 | ||
c65355bb | 8758 | void intel_mark_fb_busy(struct drm_i915_gem_object *obj, |
a4872ba6 | 8759 | struct intel_engine_cs *ring) |
652c393a | 8760 | { |
f047e395 CW |
8761 | struct drm_device *dev = obj->base.dev; |
8762 | struct drm_crtc *crtc; | |
652c393a | 8763 | |
d330a953 | 8764 | if (!i915.powersave) |
acb87dfb CW |
8765 | return; |
8766 | ||
70e1e0ec | 8767 | for_each_crtc(dev, crtc) { |
f4510a27 | 8768 | if (!crtc->primary->fb) |
652c393a JB |
8769 | continue; |
8770 | ||
f4510a27 | 8771 | if (to_intel_framebuffer(crtc->primary->fb)->obj != obj) |
c65355bb CW |
8772 | continue; |
8773 | ||
8774 | intel_increase_pllclock(crtc); | |
8775 | if (ring && intel_fbc_enabled(dev)) | |
8776 | ring->fbc_dirty = true; | |
652c393a JB |
8777 | } |
8778 | } | |
8779 | ||
79e53945 JB |
8780 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
8781 | { | |
8782 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
8783 | struct drm_device *dev = crtc->dev; |
8784 | struct intel_unpin_work *work; | |
8785 | unsigned long flags; | |
8786 | ||
8787 | spin_lock_irqsave(&dev->event_lock, flags); | |
8788 | work = intel_crtc->unpin_work; | |
8789 | intel_crtc->unpin_work = NULL; | |
8790 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
8791 | ||
8792 | if (work) { | |
8793 | cancel_work_sync(&work->work); | |
8794 | kfree(work); | |
8795 | } | |
79e53945 | 8796 | |
40ccc72b MK |
8797 | intel_crtc_cursor_set(crtc, NULL, 0, 0, 0); |
8798 | ||
79e53945 | 8799 | drm_crtc_cleanup(crtc); |
67e77c5a | 8800 | |
79e53945 JB |
8801 | kfree(intel_crtc); |
8802 | } | |
8803 | ||
6b95a207 KH |
8804 | static void intel_unpin_work_fn(struct work_struct *__work) |
8805 | { | |
8806 | struct intel_unpin_work *work = | |
8807 | container_of(__work, struct intel_unpin_work, work); | |
b4a98e57 | 8808 | struct drm_device *dev = work->crtc->dev; |
6b95a207 | 8809 | |
b4a98e57 | 8810 | mutex_lock(&dev->struct_mutex); |
1690e1eb | 8811 | intel_unpin_fb_obj(work->old_fb_obj); |
05394f39 CW |
8812 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
8813 | drm_gem_object_unreference(&work->old_fb_obj->base); | |
d9e86c0e | 8814 | |
b4a98e57 CW |
8815 | intel_update_fbc(dev); |
8816 | mutex_unlock(&dev->struct_mutex); | |
8817 | ||
8818 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); | |
8819 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); | |
8820 | ||
6b95a207 KH |
8821 | kfree(work); |
8822 | } | |
8823 | ||
1afe3e9d | 8824 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 8825 | struct drm_crtc *crtc) |
6b95a207 | 8826 | { |
fbee40df | 8827 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
8828 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8829 | struct intel_unpin_work *work; | |
6b95a207 KH |
8830 | unsigned long flags; |
8831 | ||
8832 | /* Ignore early vblank irqs */ | |
8833 | if (intel_crtc == NULL) | |
8834 | return; | |
8835 | ||
8836 | spin_lock_irqsave(&dev->event_lock, flags); | |
8837 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
8838 | |
8839 | /* Ensure we don't miss a work->pending update ... */ | |
8840 | smp_rmb(); | |
8841 | ||
8842 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
8843 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8844 | return; | |
8845 | } | |
8846 | ||
e7d841ca CW |
8847 | /* and that the unpin work is consistent wrt ->pending. */ |
8848 | smp_rmb(); | |
8849 | ||
6b95a207 | 8850 | intel_crtc->unpin_work = NULL; |
6b95a207 | 8851 | |
45a066eb RC |
8852 | if (work->event) |
8853 | drm_send_vblank_event(dev, intel_crtc->pipe, work->event); | |
6b95a207 | 8854 | |
87b6b101 | 8855 | drm_crtc_vblank_put(crtc); |
0af7e4df | 8856 | |
6b95a207 KH |
8857 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8858 | ||
2c10d571 | 8859 | wake_up_all(&dev_priv->pending_flip_queue); |
b4a98e57 CW |
8860 | |
8861 | queue_work(dev_priv->wq, &work->work); | |
e5510fac JB |
8862 | |
8863 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); | |
6b95a207 KH |
8864 | } |
8865 | ||
1afe3e9d JB |
8866 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
8867 | { | |
fbee40df | 8868 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
8869 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
8870 | ||
49b14a5c | 8871 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
8872 | } |
8873 | ||
8874 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
8875 | { | |
fbee40df | 8876 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
8877 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
8878 | ||
49b14a5c | 8879 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
8880 | } |
8881 | ||
75f7f3ec VS |
8882 | /* Is 'a' after or equal to 'b'? */ |
8883 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
8884 | { | |
8885 | return !((a - b) & 0x80000000); | |
8886 | } | |
8887 | ||
8888 | static bool page_flip_finished(struct intel_crtc *crtc) | |
8889 | { | |
8890 | struct drm_device *dev = crtc->base.dev; | |
8891 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8892 | ||
8893 | /* | |
8894 | * The relevant registers doen't exist on pre-ctg. | |
8895 | * As the flip done interrupt doesn't trigger for mmio | |
8896 | * flips on gmch platforms, a flip count check isn't | |
8897 | * really needed there. But since ctg has the registers, | |
8898 | * include it in the check anyway. | |
8899 | */ | |
8900 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
8901 | return true; | |
8902 | ||
8903 | /* | |
8904 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
8905 | * used the same base address. In that case the mmio flip might | |
8906 | * have completed, but the CS hasn't even executed the flip yet. | |
8907 | * | |
8908 | * A flip count check isn't enough as the CS might have updated | |
8909 | * the base address just after start of vblank, but before we | |
8910 | * managed to process the interrupt. This means we'd complete the | |
8911 | * CS flip too soon. | |
8912 | * | |
8913 | * Combining both checks should get us a good enough result. It may | |
8914 | * still happen that the CS flip has been executed, but has not | |
8915 | * yet actually completed. But in case the base address is the same | |
8916 | * anyway, we don't really care. | |
8917 | */ | |
8918 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
8919 | crtc->unpin_work->gtt_offset && | |
8920 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)), | |
8921 | crtc->unpin_work->flip_count); | |
8922 | } | |
8923 | ||
6b95a207 KH |
8924 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
8925 | { | |
fbee40df | 8926 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
8927 | struct intel_crtc *intel_crtc = |
8928 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
8929 | unsigned long flags; | |
8930 | ||
e7d841ca CW |
8931 | /* NB: An MMIO update of the plane base pointer will also |
8932 | * generate a page-flip completion irq, i.e. every modeset | |
8933 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
8934 | */ | |
6b95a207 | 8935 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 8936 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 8937 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
8938 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8939 | } | |
8940 | ||
eba905b2 | 8941 | static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
e7d841ca CW |
8942 | { |
8943 | /* Ensure that the work item is consistent when activating it ... */ | |
8944 | smp_wmb(); | |
8945 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); | |
8946 | /* and that it is marked active as soon as the irq could fire. */ | |
8947 | smp_wmb(); | |
8948 | } | |
8949 | ||
8c9f3aaf JB |
8950 | static int intel_gen2_queue_flip(struct drm_device *dev, |
8951 | struct drm_crtc *crtc, | |
8952 | struct drm_framebuffer *fb, | |
ed8d1975 | 8953 | struct drm_i915_gem_object *obj, |
a4872ba6 | 8954 | struct intel_engine_cs *ring, |
ed8d1975 | 8955 | uint32_t flags) |
8c9f3aaf | 8956 | { |
8c9f3aaf | 8957 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
8958 | u32 flip_mask; |
8959 | int ret; | |
8960 | ||
6d90c952 | 8961 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 8962 | if (ret) |
4fa62c89 | 8963 | return ret; |
8c9f3aaf JB |
8964 | |
8965 | /* Can't queue multiple flips, so wait for the previous | |
8966 | * one to finish before executing the next. | |
8967 | */ | |
8968 | if (intel_crtc->plane) | |
8969 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
8970 | else | |
8971 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
8972 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
8973 | intel_ring_emit(ring, MI_NOOP); | |
8974 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
8975 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
8976 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 8977 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 | 8978 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca CW |
8979 | |
8980 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 8981 | __intel_ring_advance(ring); |
83d4092b | 8982 | return 0; |
8c9f3aaf JB |
8983 | } |
8984 | ||
8985 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
8986 | struct drm_crtc *crtc, | |
8987 | struct drm_framebuffer *fb, | |
ed8d1975 | 8988 | struct drm_i915_gem_object *obj, |
a4872ba6 | 8989 | struct intel_engine_cs *ring, |
ed8d1975 | 8990 | uint32_t flags) |
8c9f3aaf | 8991 | { |
8c9f3aaf | 8992 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
8993 | u32 flip_mask; |
8994 | int ret; | |
8995 | ||
6d90c952 | 8996 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 8997 | if (ret) |
4fa62c89 | 8998 | return ret; |
8c9f3aaf JB |
8999 | |
9000 | if (intel_crtc->plane) | |
9001 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
9002 | else | |
9003 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
9004 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
9005 | intel_ring_emit(ring, MI_NOOP); | |
9006 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
9007 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9008 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9009 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 DV |
9010 | intel_ring_emit(ring, MI_NOOP); |
9011 | ||
e7d841ca | 9012 | intel_mark_page_flip_active(intel_crtc); |
09246732 | 9013 | __intel_ring_advance(ring); |
83d4092b | 9014 | return 0; |
8c9f3aaf JB |
9015 | } |
9016 | ||
9017 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
9018 | struct drm_crtc *crtc, | |
9019 | struct drm_framebuffer *fb, | |
ed8d1975 | 9020 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9021 | struct intel_engine_cs *ring, |
ed8d1975 | 9022 | uint32_t flags) |
8c9f3aaf JB |
9023 | { |
9024 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9025 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9026 | uint32_t pf, pipesrc; | |
9027 | int ret; | |
9028 | ||
6d90c952 | 9029 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 9030 | if (ret) |
4fa62c89 | 9031 | return ret; |
8c9f3aaf JB |
9032 | |
9033 | /* i965+ uses the linear or tiled offsets from the | |
9034 | * Display Registers (which do not change across a page-flip) | |
9035 | * so we need only reprogram the base address. | |
9036 | */ | |
6d90c952 DV |
9037 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
9038 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9039 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9040 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | |
c2c75131 | 9041 | obj->tiling_mode); |
8c9f3aaf JB |
9042 | |
9043 | /* XXX Enabling the panel-fitter across page-flip is so far | |
9044 | * untested on non-native modes, so ignore it for now. | |
9045 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
9046 | */ | |
9047 | pf = 0; | |
9048 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 9049 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
9050 | |
9051 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9052 | __intel_ring_advance(ring); |
83d4092b | 9053 | return 0; |
8c9f3aaf JB |
9054 | } |
9055 | ||
9056 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
9057 | struct drm_crtc *crtc, | |
9058 | struct drm_framebuffer *fb, | |
ed8d1975 | 9059 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9060 | struct intel_engine_cs *ring, |
ed8d1975 | 9061 | uint32_t flags) |
8c9f3aaf JB |
9062 | { |
9063 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9064 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9065 | uint32_t pf, pipesrc; | |
9066 | int ret; | |
9067 | ||
6d90c952 | 9068 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 9069 | if (ret) |
4fa62c89 | 9070 | return ret; |
8c9f3aaf | 9071 | |
6d90c952 DV |
9072 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
9073 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9074 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
75f7f3ec | 9075 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8c9f3aaf | 9076 | |
dc257cf1 DV |
9077 | /* Contrary to the suggestions in the documentation, |
9078 | * "Enable Panel Fitter" does not seem to be required when page | |
9079 | * flipping with a non-native mode, and worse causes a normal | |
9080 | * modeset to fail. | |
9081 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
9082 | */ | |
9083 | pf = 0; | |
8c9f3aaf | 9084 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 9085 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
9086 | |
9087 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9088 | __intel_ring_advance(ring); |
83d4092b | 9089 | return 0; |
8c9f3aaf JB |
9090 | } |
9091 | ||
7c9017e5 JB |
9092 | static int intel_gen7_queue_flip(struct drm_device *dev, |
9093 | struct drm_crtc *crtc, | |
9094 | struct drm_framebuffer *fb, | |
ed8d1975 | 9095 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9096 | struct intel_engine_cs *ring, |
ed8d1975 | 9097 | uint32_t flags) |
7c9017e5 | 9098 | { |
7c9017e5 | 9099 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 9100 | uint32_t plane_bit = 0; |
ffe74d75 CW |
9101 | int len, ret; |
9102 | ||
eba905b2 | 9103 | switch (intel_crtc->plane) { |
cb05d8de DV |
9104 | case PLANE_A: |
9105 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
9106 | break; | |
9107 | case PLANE_B: | |
9108 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
9109 | break; | |
9110 | case PLANE_C: | |
9111 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
9112 | break; | |
9113 | default: | |
9114 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 9115 | return -ENODEV; |
cb05d8de DV |
9116 | } |
9117 | ||
ffe74d75 | 9118 | len = 4; |
f476828a | 9119 | if (ring->id == RCS) { |
ffe74d75 | 9120 | len += 6; |
f476828a DL |
9121 | /* |
9122 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
9123 | * 48bits addresses, and we need a NOOP for the batch size to | |
9124 | * stay even. | |
9125 | */ | |
9126 | if (IS_GEN8(dev)) | |
9127 | len += 2; | |
9128 | } | |
ffe74d75 | 9129 | |
f66fab8e VS |
9130 | /* |
9131 | * BSpec MI_DISPLAY_FLIP for IVB: | |
9132 | * "The full packet must be contained within the same cache line." | |
9133 | * | |
9134 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
9135 | * cacheline, if we ever start emitting more commands before | |
9136 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
9137 | * then do the cacheline alignment, and finally emit the | |
9138 | * MI_DISPLAY_FLIP. | |
9139 | */ | |
9140 | ret = intel_ring_cacheline_align(ring); | |
9141 | if (ret) | |
4fa62c89 | 9142 | return ret; |
f66fab8e | 9143 | |
ffe74d75 | 9144 | ret = intel_ring_begin(ring, len); |
7c9017e5 | 9145 | if (ret) |
4fa62c89 | 9146 | return ret; |
7c9017e5 | 9147 | |
ffe74d75 CW |
9148 | /* Unmask the flip-done completion message. Note that the bspec says that |
9149 | * we should do this for both the BCS and RCS, and that we must not unmask | |
9150 | * more than one flip event at any time (or ensure that one flip message | |
9151 | * can be sent by waiting for flip-done prior to queueing new flips). | |
9152 | * Experimentation says that BCS works despite DERRMR masking all | |
9153 | * flip-done completion events and that unmasking all planes at once | |
9154 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
9155 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
9156 | */ | |
9157 | if (ring->id == RCS) { | |
9158 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
9159 | intel_ring_emit(ring, DERRMR); | |
9160 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
9161 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
9162 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a DL |
9163 | if (IS_GEN8(dev)) |
9164 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) | | |
9165 | MI_SRM_LRM_GLOBAL_GTT); | |
9166 | else | |
9167 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | | |
9168 | MI_SRM_LRM_GLOBAL_GTT); | |
ffe74d75 CW |
9169 | intel_ring_emit(ring, DERRMR); |
9170 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
f476828a DL |
9171 | if (IS_GEN8(dev)) { |
9172 | intel_ring_emit(ring, 0); | |
9173 | intel_ring_emit(ring, MI_NOOP); | |
9174 | } | |
ffe74d75 CW |
9175 | } |
9176 | ||
cb05d8de | 9177 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 9178 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
75f7f3ec | 9179 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
7c9017e5 | 9180 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca CW |
9181 | |
9182 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9183 | __intel_ring_advance(ring); |
83d4092b | 9184 | return 0; |
7c9017e5 JB |
9185 | } |
9186 | ||
8c9f3aaf JB |
9187 | static int intel_default_queue_flip(struct drm_device *dev, |
9188 | struct drm_crtc *crtc, | |
9189 | struct drm_framebuffer *fb, | |
ed8d1975 | 9190 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9191 | struct intel_engine_cs *ring, |
ed8d1975 | 9192 | uint32_t flags) |
8c9f3aaf JB |
9193 | { |
9194 | return -ENODEV; | |
9195 | } | |
9196 | ||
6b95a207 KH |
9197 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
9198 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
9199 | struct drm_pending_vblank_event *event, |
9200 | uint32_t page_flip_flags) | |
6b95a207 KH |
9201 | { |
9202 | struct drm_device *dev = crtc->dev; | |
9203 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 9204 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
4a35f83b | 9205 | struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj; |
6b95a207 KH |
9206 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
9207 | struct intel_unpin_work *work; | |
a4872ba6 | 9208 | struct intel_engine_cs *ring; |
8c9f3aaf | 9209 | unsigned long flags; |
52e68630 | 9210 | int ret; |
6b95a207 | 9211 | |
e6a595d2 | 9212 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 9213 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
9214 | return -EINVAL; |
9215 | ||
9216 | /* | |
9217 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
9218 | * Note that pitch changes could also affect these register. | |
9219 | */ | |
9220 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
9221 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
9222 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
9223 | return -EINVAL; |
9224 | ||
f900db47 CW |
9225 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
9226 | goto out_hang; | |
9227 | ||
b14c5679 | 9228 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
9229 | if (work == NULL) |
9230 | return -ENOMEM; | |
9231 | ||
6b95a207 | 9232 | work->event = event; |
b4a98e57 | 9233 | work->crtc = crtc; |
4a35f83b | 9234 | work->old_fb_obj = to_intel_framebuffer(old_fb)->obj; |
6b95a207 KH |
9235 | INIT_WORK(&work->work, intel_unpin_work_fn); |
9236 | ||
87b6b101 | 9237 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
9238 | if (ret) |
9239 | goto free_work; | |
9240 | ||
6b95a207 KH |
9241 | /* We borrow the event spin lock for protecting unpin_work */ |
9242 | spin_lock_irqsave(&dev->event_lock, flags); | |
9243 | if (intel_crtc->unpin_work) { | |
9244 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
9245 | kfree(work); | |
87b6b101 | 9246 | drm_crtc_vblank_put(crtc); |
468f0b44 CW |
9247 | |
9248 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
6b95a207 KH |
9249 | return -EBUSY; |
9250 | } | |
9251 | intel_crtc->unpin_work = work; | |
9252 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
9253 | ||
b4a98e57 CW |
9254 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
9255 | flush_workqueue(dev_priv->wq); | |
9256 | ||
79158103 CW |
9257 | ret = i915_mutex_lock_interruptible(dev); |
9258 | if (ret) | |
9259 | goto cleanup; | |
6b95a207 | 9260 | |
75dfca80 | 9261 | /* Reference the objects for the scheduled work. */ |
05394f39 CW |
9262 | drm_gem_object_reference(&work->old_fb_obj->base); |
9263 | drm_gem_object_reference(&obj->base); | |
6b95a207 | 9264 | |
f4510a27 | 9265 | crtc->primary->fb = fb; |
96b099fd | 9266 | |
e1f99ce6 | 9267 | work->pending_flip_obj = obj; |
e1f99ce6 | 9268 | |
4e5359cd SF |
9269 | work->enable_stall_check = true; |
9270 | ||
b4a98e57 | 9271 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 9272 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 9273 | |
75f7f3ec VS |
9274 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
9275 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(intel_crtc->pipe)) + 1; | |
9276 | ||
4fa62c89 VS |
9277 | if (IS_VALLEYVIEW(dev)) { |
9278 | ring = &dev_priv->ring[BCS]; | |
9279 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
9280 | ring = obj->ring; | |
9281 | if (ring == NULL || ring->id != RCS) | |
9282 | ring = &dev_priv->ring[BCS]; | |
9283 | } else { | |
9284 | ring = &dev_priv->ring[RCS]; | |
9285 | } | |
9286 | ||
9287 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); | |
8c9f3aaf JB |
9288 | if (ret) |
9289 | goto cleanup_pending; | |
6b95a207 | 9290 | |
4fa62c89 VS |
9291 | work->gtt_offset = |
9292 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset; | |
9293 | ||
9294 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring, page_flip_flags); | |
9295 | if (ret) | |
9296 | goto cleanup_unpin; | |
9297 | ||
7782de3b | 9298 | intel_disable_fbc(dev); |
c65355bb | 9299 | intel_mark_fb_busy(obj, NULL); |
6b95a207 KH |
9300 | mutex_unlock(&dev->struct_mutex); |
9301 | ||
e5510fac JB |
9302 | trace_i915_flip_request(intel_crtc->plane, obj); |
9303 | ||
6b95a207 | 9304 | return 0; |
96b099fd | 9305 | |
4fa62c89 VS |
9306 | cleanup_unpin: |
9307 | intel_unpin_fb_obj(obj); | |
8c9f3aaf | 9308 | cleanup_pending: |
b4a98e57 | 9309 | atomic_dec(&intel_crtc->unpin_work_count); |
f4510a27 | 9310 | crtc->primary->fb = old_fb; |
05394f39 CW |
9311 | drm_gem_object_unreference(&work->old_fb_obj->base); |
9312 | drm_gem_object_unreference(&obj->base); | |
96b099fd CW |
9313 | mutex_unlock(&dev->struct_mutex); |
9314 | ||
79158103 | 9315 | cleanup: |
96b099fd CW |
9316 | spin_lock_irqsave(&dev->event_lock, flags); |
9317 | intel_crtc->unpin_work = NULL; | |
9318 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
9319 | ||
87b6b101 | 9320 | drm_crtc_vblank_put(crtc); |
7317c75e | 9321 | free_work: |
96b099fd CW |
9322 | kfree(work); |
9323 | ||
f900db47 CW |
9324 | if (ret == -EIO) { |
9325 | out_hang: | |
9326 | intel_crtc_wait_for_pending_flips(crtc); | |
9327 | ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb); | |
9328 | if (ret == 0 && event) | |
9329 | drm_send_vblank_event(dev, intel_crtc->pipe, event); | |
9330 | } | |
96b099fd | 9331 | return ret; |
6b95a207 KH |
9332 | } |
9333 | ||
f6e5b160 | 9334 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
9335 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
9336 | .load_lut = intel_crtc_load_lut, | |
f6e5b160 CW |
9337 | }; |
9338 | ||
9a935856 DV |
9339 | /** |
9340 | * intel_modeset_update_staged_output_state | |
9341 | * | |
9342 | * Updates the staged output configuration state, e.g. after we've read out the | |
9343 | * current hw state. | |
9344 | */ | |
9345 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) | |
f6e5b160 | 9346 | { |
7668851f | 9347 | struct intel_crtc *crtc; |
9a935856 DV |
9348 | struct intel_encoder *encoder; |
9349 | struct intel_connector *connector; | |
f6e5b160 | 9350 | |
9a935856 DV |
9351 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9352 | base.head) { | |
9353 | connector->new_encoder = | |
9354 | to_intel_encoder(connector->base.encoder); | |
9355 | } | |
f6e5b160 | 9356 | |
9a935856 DV |
9357 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9358 | base.head) { | |
9359 | encoder->new_crtc = | |
9360 | to_intel_crtc(encoder->base.crtc); | |
9361 | } | |
7668851f | 9362 | |
d3fcc808 | 9363 | for_each_intel_crtc(dev, crtc) { |
7668851f | 9364 | crtc->new_enabled = crtc->base.enabled; |
7bd0a8e7 VS |
9365 | |
9366 | if (crtc->new_enabled) | |
9367 | crtc->new_config = &crtc->config; | |
9368 | else | |
9369 | crtc->new_config = NULL; | |
7668851f | 9370 | } |
f6e5b160 CW |
9371 | } |
9372 | ||
9a935856 DV |
9373 | /** |
9374 | * intel_modeset_commit_output_state | |
9375 | * | |
9376 | * This function copies the stage display pipe configuration to the real one. | |
9377 | */ | |
9378 | static void intel_modeset_commit_output_state(struct drm_device *dev) | |
9379 | { | |
7668851f | 9380 | struct intel_crtc *crtc; |
9a935856 DV |
9381 | struct intel_encoder *encoder; |
9382 | struct intel_connector *connector; | |
f6e5b160 | 9383 | |
9a935856 DV |
9384 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9385 | base.head) { | |
9386 | connector->base.encoder = &connector->new_encoder->base; | |
9387 | } | |
f6e5b160 | 9388 | |
9a935856 DV |
9389 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9390 | base.head) { | |
9391 | encoder->base.crtc = &encoder->new_crtc->base; | |
9392 | } | |
7668851f | 9393 | |
d3fcc808 | 9394 | for_each_intel_crtc(dev, crtc) { |
7668851f VS |
9395 | crtc->base.enabled = crtc->new_enabled; |
9396 | } | |
9a935856 DV |
9397 | } |
9398 | ||
050f7aeb | 9399 | static void |
eba905b2 | 9400 | connected_sink_compute_bpp(struct intel_connector *connector, |
050f7aeb DV |
9401 | struct intel_crtc_config *pipe_config) |
9402 | { | |
9403 | int bpp = pipe_config->pipe_bpp; | |
9404 | ||
9405 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
9406 | connector->base.base.id, | |
9407 | drm_get_connector_name(&connector->base)); | |
9408 | ||
9409 | /* Don't use an invalid EDID bpc value */ | |
9410 | if (connector->base.display_info.bpc && | |
9411 | connector->base.display_info.bpc * 3 < bpp) { | |
9412 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
9413 | bpp, connector->base.display_info.bpc*3); | |
9414 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
9415 | } | |
9416 | ||
9417 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
9418 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
9419 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
9420 | bpp); | |
9421 | pipe_config->pipe_bpp = 24; | |
9422 | } | |
9423 | } | |
9424 | ||
4e53c2e0 | 9425 | static int |
050f7aeb DV |
9426 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
9427 | struct drm_framebuffer *fb, | |
9428 | struct intel_crtc_config *pipe_config) | |
4e53c2e0 | 9429 | { |
050f7aeb DV |
9430 | struct drm_device *dev = crtc->base.dev; |
9431 | struct intel_connector *connector; | |
4e53c2e0 DV |
9432 | int bpp; |
9433 | ||
d42264b1 DV |
9434 | switch (fb->pixel_format) { |
9435 | case DRM_FORMAT_C8: | |
4e53c2e0 DV |
9436 | bpp = 8*3; /* since we go through a colormap */ |
9437 | break; | |
d42264b1 DV |
9438 | case DRM_FORMAT_XRGB1555: |
9439 | case DRM_FORMAT_ARGB1555: | |
9440 | /* checked in intel_framebuffer_init already */ | |
9441 | if (WARN_ON(INTEL_INFO(dev)->gen > 3)) | |
9442 | return -EINVAL; | |
9443 | case DRM_FORMAT_RGB565: | |
4e53c2e0 DV |
9444 | bpp = 6*3; /* min is 18bpp */ |
9445 | break; | |
d42264b1 DV |
9446 | case DRM_FORMAT_XBGR8888: |
9447 | case DRM_FORMAT_ABGR8888: | |
9448 | /* checked in intel_framebuffer_init already */ | |
9449 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
9450 | return -EINVAL; | |
9451 | case DRM_FORMAT_XRGB8888: | |
9452 | case DRM_FORMAT_ARGB8888: | |
4e53c2e0 DV |
9453 | bpp = 8*3; |
9454 | break; | |
d42264b1 DV |
9455 | case DRM_FORMAT_XRGB2101010: |
9456 | case DRM_FORMAT_ARGB2101010: | |
9457 | case DRM_FORMAT_XBGR2101010: | |
9458 | case DRM_FORMAT_ABGR2101010: | |
9459 | /* checked in intel_framebuffer_init already */ | |
9460 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
baba133a | 9461 | return -EINVAL; |
4e53c2e0 DV |
9462 | bpp = 10*3; |
9463 | break; | |
baba133a | 9464 | /* TODO: gen4+ supports 16 bpc floating point, too. */ |
4e53c2e0 DV |
9465 | default: |
9466 | DRM_DEBUG_KMS("unsupported depth\n"); | |
9467 | return -EINVAL; | |
9468 | } | |
9469 | ||
4e53c2e0 DV |
9470 | pipe_config->pipe_bpp = bpp; |
9471 | ||
9472 | /* Clamp display bpp to EDID value */ | |
9473 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
050f7aeb | 9474 | base.head) { |
1b829e05 DV |
9475 | if (!connector->new_encoder || |
9476 | connector->new_encoder->new_crtc != crtc) | |
4e53c2e0 DV |
9477 | continue; |
9478 | ||
050f7aeb | 9479 | connected_sink_compute_bpp(connector, pipe_config); |
4e53c2e0 DV |
9480 | } |
9481 | ||
9482 | return bpp; | |
9483 | } | |
9484 | ||
644db711 DV |
9485 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
9486 | { | |
9487 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
9488 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 9489 | mode->crtc_clock, |
644db711 DV |
9490 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
9491 | mode->crtc_hsync_end, mode->crtc_htotal, | |
9492 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
9493 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
9494 | } | |
9495 | ||
c0b03411 DV |
9496 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
9497 | struct intel_crtc_config *pipe_config, | |
9498 | const char *context) | |
9499 | { | |
9500 | DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id, | |
9501 | context, pipe_name(crtc->pipe)); | |
9502 | ||
9503 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
9504 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
9505 | pipe_config->pipe_bpp, pipe_config->dither); | |
9506 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
9507 | pipe_config->has_pch_encoder, | |
9508 | pipe_config->fdi_lanes, | |
9509 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
9510 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
9511 | pipe_config->fdi_m_n.tu); | |
eb14cb74 VS |
9512 | DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
9513 | pipe_config->has_dp_encoder, | |
9514 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, | |
9515 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
9516 | pipe_config->dp_m_n.tu); | |
c0b03411 DV |
9517 | DRM_DEBUG_KMS("requested mode:\n"); |
9518 | drm_mode_debug_printmodeline(&pipe_config->requested_mode); | |
9519 | DRM_DEBUG_KMS("adjusted mode:\n"); | |
9520 | drm_mode_debug_printmodeline(&pipe_config->adjusted_mode); | |
644db711 | 9521 | intel_dump_crtc_timings(&pipe_config->adjusted_mode); |
d71b8d4a | 9522 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
9523 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
9524 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
c0b03411 DV |
9525 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
9526 | pipe_config->gmch_pfit.control, | |
9527 | pipe_config->gmch_pfit.pgm_ratios, | |
9528 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 9529 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 9530 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
9531 | pipe_config->pch_pfit.size, |
9532 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 9533 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 9534 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
c0b03411 DV |
9535 | } |
9536 | ||
bc079e8b VS |
9537 | static bool encoders_cloneable(const struct intel_encoder *a, |
9538 | const struct intel_encoder *b) | |
accfc0c5 | 9539 | { |
bc079e8b VS |
9540 | /* masks could be asymmetric, so check both ways */ |
9541 | return a == b || (a->cloneable & (1 << b->type) && | |
9542 | b->cloneable & (1 << a->type)); | |
9543 | } | |
9544 | ||
9545 | static bool check_single_encoder_cloning(struct intel_crtc *crtc, | |
9546 | struct intel_encoder *encoder) | |
9547 | { | |
9548 | struct drm_device *dev = crtc->base.dev; | |
9549 | struct intel_encoder *source_encoder; | |
9550 | ||
9551 | list_for_each_entry(source_encoder, | |
9552 | &dev->mode_config.encoder_list, base.head) { | |
9553 | if (source_encoder->new_crtc != crtc) | |
9554 | continue; | |
9555 | ||
9556 | if (!encoders_cloneable(encoder, source_encoder)) | |
9557 | return false; | |
9558 | } | |
9559 | ||
9560 | return true; | |
9561 | } | |
9562 | ||
9563 | static bool check_encoder_cloning(struct intel_crtc *crtc) | |
9564 | { | |
9565 | struct drm_device *dev = crtc->base.dev; | |
accfc0c5 DV |
9566 | struct intel_encoder *encoder; |
9567 | ||
bc079e8b VS |
9568 | list_for_each_entry(encoder, |
9569 | &dev->mode_config.encoder_list, base.head) { | |
9570 | if (encoder->new_crtc != crtc) | |
accfc0c5 DV |
9571 | continue; |
9572 | ||
bc079e8b VS |
9573 | if (!check_single_encoder_cloning(crtc, encoder)) |
9574 | return false; | |
accfc0c5 DV |
9575 | } |
9576 | ||
bc079e8b | 9577 | return true; |
accfc0c5 DV |
9578 | } |
9579 | ||
b8cecdf5 DV |
9580 | static struct intel_crtc_config * |
9581 | intel_modeset_pipe_config(struct drm_crtc *crtc, | |
4e53c2e0 | 9582 | struct drm_framebuffer *fb, |
b8cecdf5 | 9583 | struct drm_display_mode *mode) |
ee7b9f93 | 9584 | { |
7758a113 | 9585 | struct drm_device *dev = crtc->dev; |
7758a113 | 9586 | struct intel_encoder *encoder; |
b8cecdf5 | 9587 | struct intel_crtc_config *pipe_config; |
e29c22c0 DV |
9588 | int plane_bpp, ret = -EINVAL; |
9589 | bool retry = true; | |
ee7b9f93 | 9590 | |
bc079e8b | 9591 | if (!check_encoder_cloning(to_intel_crtc(crtc))) { |
accfc0c5 DV |
9592 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); |
9593 | return ERR_PTR(-EINVAL); | |
9594 | } | |
9595 | ||
b8cecdf5 DV |
9596 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
9597 | if (!pipe_config) | |
7758a113 DV |
9598 | return ERR_PTR(-ENOMEM); |
9599 | ||
b8cecdf5 DV |
9600 | drm_mode_copy(&pipe_config->adjusted_mode, mode); |
9601 | drm_mode_copy(&pipe_config->requested_mode, mode); | |
37327abd | 9602 | |
e143a21c DV |
9603 | pipe_config->cpu_transcoder = |
9604 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
c0d43d62 | 9605 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
b8cecdf5 | 9606 | |
2960bc9c ID |
9607 | /* |
9608 | * Sanitize sync polarity flags based on requested ones. If neither | |
9609 | * positive or negative polarity is requested, treat this as meaning | |
9610 | * negative polarity. | |
9611 | */ | |
9612 | if (!(pipe_config->adjusted_mode.flags & | |
9613 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) | |
9614 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; | |
9615 | ||
9616 | if (!(pipe_config->adjusted_mode.flags & | |
9617 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) | |
9618 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; | |
9619 | ||
050f7aeb DV |
9620 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
9621 | * plane pixel format and any sink constraints into account. Returns the | |
9622 | * source plane bpp so that dithering can be selected on mismatches | |
9623 | * after encoders and crtc also have had their say. */ | |
9624 | plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), | |
9625 | fb, pipe_config); | |
4e53c2e0 DV |
9626 | if (plane_bpp < 0) |
9627 | goto fail; | |
9628 | ||
e41a56be VS |
9629 | /* |
9630 | * Determine the real pipe dimensions. Note that stereo modes can | |
9631 | * increase the actual pipe size due to the frame doubling and | |
9632 | * insertion of additional space for blanks between the frame. This | |
9633 | * is stored in the crtc timings. We use the requested mode to do this | |
9634 | * computation to clearly distinguish it from the adjusted mode, which | |
9635 | * can be changed by the connectors in the below retry loop. | |
9636 | */ | |
9637 | drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE); | |
9638 | pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay; | |
9639 | pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay; | |
9640 | ||
e29c22c0 | 9641 | encoder_retry: |
ef1b460d | 9642 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 9643 | pipe_config->port_clock = 0; |
ef1b460d | 9644 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 9645 | |
135c81b8 | 9646 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
6ce70f5e | 9647 | drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE); |
135c81b8 | 9648 | |
7758a113 DV |
9649 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
9650 | * adjust it according to limitations or connector properties, and also | |
9651 | * a chance to reject the mode entirely. | |
47f1c6c9 | 9652 | */ |
7758a113 DV |
9653 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9654 | base.head) { | |
47f1c6c9 | 9655 | |
7758a113 DV |
9656 | if (&encoder->new_crtc->base != crtc) |
9657 | continue; | |
7ae89233 | 9658 | |
efea6e8e DV |
9659 | if (!(encoder->compute_config(encoder, pipe_config))) { |
9660 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
9661 | goto fail; |
9662 | } | |
ee7b9f93 | 9663 | } |
47f1c6c9 | 9664 | |
ff9a6750 DV |
9665 | /* Set default port clock if not overwritten by the encoder. Needs to be |
9666 | * done afterwards in case the encoder adjusts the mode. */ | |
9667 | if (!pipe_config->port_clock) | |
241bfc38 DL |
9668 | pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock |
9669 | * pipe_config->pixel_multiplier; | |
ff9a6750 | 9670 | |
a43f6e0f | 9671 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 9672 | if (ret < 0) { |
7758a113 DV |
9673 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
9674 | goto fail; | |
ee7b9f93 | 9675 | } |
e29c22c0 DV |
9676 | |
9677 | if (ret == RETRY) { | |
9678 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
9679 | ret = -EINVAL; | |
9680 | goto fail; | |
9681 | } | |
9682 | ||
9683 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
9684 | retry = false; | |
9685 | goto encoder_retry; | |
9686 | } | |
9687 | ||
4e53c2e0 DV |
9688 | pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; |
9689 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", | |
9690 | plane_bpp, pipe_config->pipe_bpp, pipe_config->dither); | |
9691 | ||
b8cecdf5 | 9692 | return pipe_config; |
7758a113 | 9693 | fail: |
b8cecdf5 | 9694 | kfree(pipe_config); |
e29c22c0 | 9695 | return ERR_PTR(ret); |
ee7b9f93 | 9696 | } |
47f1c6c9 | 9697 | |
e2e1ed41 DV |
9698 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
9699 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ | |
9700 | static void | |
9701 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, | |
9702 | unsigned *prepare_pipes, unsigned *disable_pipes) | |
79e53945 JB |
9703 | { |
9704 | struct intel_crtc *intel_crtc; | |
e2e1ed41 DV |
9705 | struct drm_device *dev = crtc->dev; |
9706 | struct intel_encoder *encoder; | |
9707 | struct intel_connector *connector; | |
9708 | struct drm_crtc *tmp_crtc; | |
79e53945 | 9709 | |
e2e1ed41 | 9710 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
79e53945 | 9711 | |
e2e1ed41 DV |
9712 | /* Check which crtcs have changed outputs connected to them, these need |
9713 | * to be part of the prepare_pipes mask. We don't (yet) support global | |
9714 | * modeset across multiple crtcs, so modeset_pipes will only have one | |
9715 | * bit set at most. */ | |
9716 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
9717 | base.head) { | |
9718 | if (connector->base.encoder == &connector->new_encoder->base) | |
9719 | continue; | |
79e53945 | 9720 | |
e2e1ed41 DV |
9721 | if (connector->base.encoder) { |
9722 | tmp_crtc = connector->base.encoder->crtc; | |
9723 | ||
9724 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
9725 | } | |
9726 | ||
9727 | if (connector->new_encoder) | |
9728 | *prepare_pipes |= | |
9729 | 1 << connector->new_encoder->new_crtc->pipe; | |
79e53945 JB |
9730 | } |
9731 | ||
e2e1ed41 DV |
9732 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9733 | base.head) { | |
9734 | if (encoder->base.crtc == &encoder->new_crtc->base) | |
9735 | continue; | |
9736 | ||
9737 | if (encoder->base.crtc) { | |
9738 | tmp_crtc = encoder->base.crtc; | |
9739 | ||
9740 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
9741 | } | |
9742 | ||
9743 | if (encoder->new_crtc) | |
9744 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; | |
80824003 JB |
9745 | } |
9746 | ||
7668851f | 9747 | /* Check for pipes that will be enabled/disabled ... */ |
d3fcc808 | 9748 | for_each_intel_crtc(dev, intel_crtc) { |
7668851f | 9749 | if (intel_crtc->base.enabled == intel_crtc->new_enabled) |
e2e1ed41 | 9750 | continue; |
7e7d76c3 | 9751 | |
7668851f | 9752 | if (!intel_crtc->new_enabled) |
e2e1ed41 | 9753 | *disable_pipes |= 1 << intel_crtc->pipe; |
7668851f VS |
9754 | else |
9755 | *prepare_pipes |= 1 << intel_crtc->pipe; | |
7e7d76c3 JB |
9756 | } |
9757 | ||
e2e1ed41 DV |
9758 | |
9759 | /* set_mode is also used to update properties on life display pipes. */ | |
9760 | intel_crtc = to_intel_crtc(crtc); | |
7668851f | 9761 | if (intel_crtc->new_enabled) |
e2e1ed41 DV |
9762 | *prepare_pipes |= 1 << intel_crtc->pipe; |
9763 | ||
b6c5164d DV |
9764 | /* |
9765 | * For simplicity do a full modeset on any pipe where the output routing | |
9766 | * changed. We could be more clever, but that would require us to be | |
9767 | * more careful with calling the relevant encoder->mode_set functions. | |
9768 | */ | |
e2e1ed41 DV |
9769 | if (*prepare_pipes) |
9770 | *modeset_pipes = *prepare_pipes; | |
9771 | ||
9772 | /* ... and mask these out. */ | |
9773 | *modeset_pipes &= ~(*disable_pipes); | |
9774 | *prepare_pipes &= ~(*disable_pipes); | |
b6c5164d DV |
9775 | |
9776 | /* | |
9777 | * HACK: We don't (yet) fully support global modesets. intel_set_config | |
9778 | * obies this rule, but the modeset restore mode of | |
9779 | * intel_modeset_setup_hw_state does not. | |
9780 | */ | |
9781 | *modeset_pipes &= 1 << intel_crtc->pipe; | |
9782 | *prepare_pipes &= 1 << intel_crtc->pipe; | |
e3641d3f DV |
9783 | |
9784 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", | |
9785 | *modeset_pipes, *prepare_pipes, *disable_pipes); | |
47f1c6c9 | 9786 | } |
79e53945 | 9787 | |
ea9d758d | 9788 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
f6e5b160 | 9789 | { |
ea9d758d | 9790 | struct drm_encoder *encoder; |
f6e5b160 | 9791 | struct drm_device *dev = crtc->dev; |
f6e5b160 | 9792 | |
ea9d758d DV |
9793 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
9794 | if (encoder->crtc == crtc) | |
9795 | return true; | |
9796 | ||
9797 | return false; | |
9798 | } | |
9799 | ||
9800 | static void | |
9801 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) | |
9802 | { | |
9803 | struct intel_encoder *intel_encoder; | |
9804 | struct intel_crtc *intel_crtc; | |
9805 | struct drm_connector *connector; | |
9806 | ||
9807 | list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list, | |
9808 | base.head) { | |
9809 | if (!intel_encoder->base.crtc) | |
9810 | continue; | |
9811 | ||
9812 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
9813 | ||
9814 | if (prepare_pipes & (1 << intel_crtc->pipe)) | |
9815 | intel_encoder->connectors_active = false; | |
9816 | } | |
9817 | ||
9818 | intel_modeset_commit_output_state(dev); | |
9819 | ||
7668851f | 9820 | /* Double check state. */ |
d3fcc808 | 9821 | for_each_intel_crtc(dev, intel_crtc) { |
7668851f | 9822 | WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base)); |
7bd0a8e7 VS |
9823 | WARN_ON(intel_crtc->new_config && |
9824 | intel_crtc->new_config != &intel_crtc->config); | |
9825 | WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config); | |
ea9d758d DV |
9826 | } |
9827 | ||
9828 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
9829 | if (!connector->encoder || !connector->encoder->crtc) | |
9830 | continue; | |
9831 | ||
9832 | intel_crtc = to_intel_crtc(connector->encoder->crtc); | |
9833 | ||
9834 | if (prepare_pipes & (1 << intel_crtc->pipe)) { | |
68d34720 DV |
9835 | struct drm_property *dpms_property = |
9836 | dev->mode_config.dpms_property; | |
9837 | ||
ea9d758d | 9838 | connector->dpms = DRM_MODE_DPMS_ON; |
662595df | 9839 | drm_object_property_set_value(&connector->base, |
68d34720 DV |
9840 | dpms_property, |
9841 | DRM_MODE_DPMS_ON); | |
ea9d758d DV |
9842 | |
9843 | intel_encoder = to_intel_encoder(connector->encoder); | |
9844 | intel_encoder->connectors_active = true; | |
9845 | } | |
9846 | } | |
9847 | ||
9848 | } | |
9849 | ||
3bd26263 | 9850 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 9851 | { |
3bd26263 | 9852 | int diff; |
f1f644dc JB |
9853 | |
9854 | if (clock1 == clock2) | |
9855 | return true; | |
9856 | ||
9857 | if (!clock1 || !clock2) | |
9858 | return false; | |
9859 | ||
9860 | diff = abs(clock1 - clock2); | |
9861 | ||
9862 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
9863 | return true; | |
9864 | ||
9865 | return false; | |
9866 | } | |
9867 | ||
25c5b266 DV |
9868 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
9869 | list_for_each_entry((intel_crtc), \ | |
9870 | &(dev)->mode_config.crtc_list, \ | |
9871 | base.head) \ | |
0973f18f | 9872 | if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 9873 | |
0e8ffe1b | 9874 | static bool |
2fa2fe9a DV |
9875 | intel_pipe_config_compare(struct drm_device *dev, |
9876 | struct intel_crtc_config *current_config, | |
0e8ffe1b DV |
9877 | struct intel_crtc_config *pipe_config) |
9878 | { | |
66e985c0 DV |
9879 | #define PIPE_CONF_CHECK_X(name) \ |
9880 | if (current_config->name != pipe_config->name) { \ | |
9881 | DRM_ERROR("mismatch in " #name " " \ | |
9882 | "(expected 0x%08x, found 0x%08x)\n", \ | |
9883 | current_config->name, \ | |
9884 | pipe_config->name); \ | |
9885 | return false; \ | |
9886 | } | |
9887 | ||
08a24034 DV |
9888 | #define PIPE_CONF_CHECK_I(name) \ |
9889 | if (current_config->name != pipe_config->name) { \ | |
9890 | DRM_ERROR("mismatch in " #name " " \ | |
9891 | "(expected %i, found %i)\n", \ | |
9892 | current_config->name, \ | |
9893 | pipe_config->name); \ | |
9894 | return false; \ | |
88adfff1 DV |
9895 | } |
9896 | ||
1bd1bd80 DV |
9897 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
9898 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
6f02488e | 9899 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
9900 | "(expected %i, found %i)\n", \ |
9901 | current_config->name & (mask), \ | |
9902 | pipe_config->name & (mask)); \ | |
9903 | return false; \ | |
9904 | } | |
9905 | ||
5e550656 VS |
9906 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
9907 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
9908 | DRM_ERROR("mismatch in " #name " " \ | |
9909 | "(expected %i, found %i)\n", \ | |
9910 | current_config->name, \ | |
9911 | pipe_config->name); \ | |
9912 | return false; \ | |
9913 | } | |
9914 | ||
bb760063 DV |
9915 | #define PIPE_CONF_QUIRK(quirk) \ |
9916 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
9917 | ||
eccb140b DV |
9918 | PIPE_CONF_CHECK_I(cpu_transcoder); |
9919 | ||
08a24034 DV |
9920 | PIPE_CONF_CHECK_I(has_pch_encoder); |
9921 | PIPE_CONF_CHECK_I(fdi_lanes); | |
72419203 DV |
9922 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
9923 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); | |
9924 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); | |
9925 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); | |
9926 | PIPE_CONF_CHECK_I(fdi_m_n.tu); | |
08a24034 | 9927 | |
eb14cb74 VS |
9928 | PIPE_CONF_CHECK_I(has_dp_encoder); |
9929 | PIPE_CONF_CHECK_I(dp_m_n.gmch_m); | |
9930 | PIPE_CONF_CHECK_I(dp_m_n.gmch_n); | |
9931 | PIPE_CONF_CHECK_I(dp_m_n.link_m); | |
9932 | PIPE_CONF_CHECK_I(dp_m_n.link_n); | |
9933 | PIPE_CONF_CHECK_I(dp_m_n.tu); | |
9934 | ||
1bd1bd80 DV |
9935 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay); |
9936 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal); | |
9937 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start); | |
9938 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end); | |
9939 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start); | |
9940 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end); | |
9941 | ||
9942 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay); | |
9943 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal); | |
9944 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start); | |
9945 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end); | |
9946 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start); | |
9947 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end); | |
9948 | ||
c93f54cf | 9949 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 9950 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 DV |
9951 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
9952 | IS_VALLEYVIEW(dev)) | |
9953 | PIPE_CONF_CHECK_I(limited_color_range); | |
6c49f241 | 9954 | |
9ed109a7 DV |
9955 | PIPE_CONF_CHECK_I(has_audio); |
9956 | ||
1bd1bd80 DV |
9957 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
9958 | DRM_MODE_FLAG_INTERLACE); | |
9959 | ||
bb760063 DV |
9960 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
9961 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
9962 | DRM_MODE_FLAG_PHSYNC); | |
9963 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
9964 | DRM_MODE_FLAG_NHSYNC); | |
9965 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
9966 | DRM_MODE_FLAG_PVSYNC); | |
9967 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
9968 | DRM_MODE_FLAG_NVSYNC); | |
9969 | } | |
045ac3b5 | 9970 | |
37327abd VS |
9971 | PIPE_CONF_CHECK_I(pipe_src_w); |
9972 | PIPE_CONF_CHECK_I(pipe_src_h); | |
1bd1bd80 | 9973 | |
9953599b DV |
9974 | /* |
9975 | * FIXME: BIOS likes to set up a cloned config with lvds+external | |
9976 | * screen. Since we don't yet re-compute the pipe config when moving | |
9977 | * just the lvds port away to another pipe the sw tracking won't match. | |
9978 | * | |
9979 | * Proper atomic modesets with recomputed global state will fix this. | |
9980 | * Until then just don't check gmch state for inherited modes. | |
9981 | */ | |
9982 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) { | |
9983 | PIPE_CONF_CHECK_I(gmch_pfit.control); | |
9984 | /* pfit ratios are autocomputed by the hw on gen4+ */ | |
9985 | if (INTEL_INFO(dev)->gen < 4) | |
9986 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
9987 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); | |
9988 | } | |
9989 | ||
fd4daa9c CW |
9990 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
9991 | if (current_config->pch_pfit.enabled) { | |
9992 | PIPE_CONF_CHECK_I(pch_pfit.pos); | |
9993 | PIPE_CONF_CHECK_I(pch_pfit.size); | |
9994 | } | |
2fa2fe9a | 9995 | |
e59150dc JB |
9996 | /* BDW+ don't expose a synchronous way to read the state */ |
9997 | if (IS_HASWELL(dev)) | |
9998 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 9999 | |
282740f7 VS |
10000 | PIPE_CONF_CHECK_I(double_wide); |
10001 | ||
c0d43d62 | 10002 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 10003 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 10004 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
10005 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
10006 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
c0d43d62 | 10007 | |
42571aef VS |
10008 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
10009 | PIPE_CONF_CHECK_I(pipe_bpp); | |
10010 | ||
a9a7e98a JB |
10011 | PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock); |
10012 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); | |
5e550656 | 10013 | |
66e985c0 | 10014 | #undef PIPE_CONF_CHECK_X |
08a24034 | 10015 | #undef PIPE_CONF_CHECK_I |
1bd1bd80 | 10016 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 10017 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 10018 | #undef PIPE_CONF_QUIRK |
88adfff1 | 10019 | |
0e8ffe1b DV |
10020 | return true; |
10021 | } | |
10022 | ||
91d1b4bd DV |
10023 | static void |
10024 | check_connector_state(struct drm_device *dev) | |
8af6cf88 | 10025 | { |
8af6cf88 DV |
10026 | struct intel_connector *connector; |
10027 | ||
10028 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
10029 | base.head) { | |
10030 | /* This also checks the encoder/connector hw state with the | |
10031 | * ->get_hw_state callbacks. */ | |
10032 | intel_connector_check_state(connector); | |
10033 | ||
10034 | WARN(&connector->new_encoder->base != connector->base.encoder, | |
10035 | "connector's staged encoder doesn't match current encoder\n"); | |
10036 | } | |
91d1b4bd DV |
10037 | } |
10038 | ||
10039 | static void | |
10040 | check_encoder_state(struct drm_device *dev) | |
10041 | { | |
10042 | struct intel_encoder *encoder; | |
10043 | struct intel_connector *connector; | |
8af6cf88 DV |
10044 | |
10045 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
10046 | base.head) { | |
10047 | bool enabled = false; | |
10048 | bool active = false; | |
10049 | enum pipe pipe, tracked_pipe; | |
10050 | ||
10051 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
10052 | encoder->base.base.id, | |
10053 | drm_get_encoder_name(&encoder->base)); | |
10054 | ||
10055 | WARN(&encoder->new_crtc->base != encoder->base.crtc, | |
10056 | "encoder's stage crtc doesn't match current crtc\n"); | |
10057 | WARN(encoder->connectors_active && !encoder->base.crtc, | |
10058 | "encoder's active_connectors set, but no crtc\n"); | |
10059 | ||
10060 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
10061 | base.head) { | |
10062 | if (connector->base.encoder != &encoder->base) | |
10063 | continue; | |
10064 | enabled = true; | |
10065 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) | |
10066 | active = true; | |
10067 | } | |
10068 | WARN(!!encoder->base.crtc != enabled, | |
10069 | "encoder's enabled state mismatch " | |
10070 | "(expected %i, found %i)\n", | |
10071 | !!encoder->base.crtc, enabled); | |
10072 | WARN(active && !encoder->base.crtc, | |
10073 | "active encoder with no crtc\n"); | |
10074 | ||
10075 | WARN(encoder->connectors_active != active, | |
10076 | "encoder's computed active state doesn't match tracked active state " | |
10077 | "(expected %i, found %i)\n", active, encoder->connectors_active); | |
10078 | ||
10079 | active = encoder->get_hw_state(encoder, &pipe); | |
10080 | WARN(active != encoder->connectors_active, | |
10081 | "encoder's hw state doesn't match sw tracking " | |
10082 | "(expected %i, found %i)\n", | |
10083 | encoder->connectors_active, active); | |
10084 | ||
10085 | if (!encoder->base.crtc) | |
10086 | continue; | |
10087 | ||
10088 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
10089 | WARN(active && pipe != tracked_pipe, | |
10090 | "active encoder's pipe doesn't match" | |
10091 | "(expected %i, found %i)\n", | |
10092 | tracked_pipe, pipe); | |
10093 | ||
10094 | } | |
91d1b4bd DV |
10095 | } |
10096 | ||
10097 | static void | |
10098 | check_crtc_state(struct drm_device *dev) | |
10099 | { | |
fbee40df | 10100 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
10101 | struct intel_crtc *crtc; |
10102 | struct intel_encoder *encoder; | |
10103 | struct intel_crtc_config pipe_config; | |
8af6cf88 | 10104 | |
d3fcc808 | 10105 | for_each_intel_crtc(dev, crtc) { |
8af6cf88 DV |
10106 | bool enabled = false; |
10107 | bool active = false; | |
10108 | ||
045ac3b5 JB |
10109 | memset(&pipe_config, 0, sizeof(pipe_config)); |
10110 | ||
8af6cf88 DV |
10111 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
10112 | crtc->base.base.id); | |
10113 | ||
10114 | WARN(crtc->active && !crtc->base.enabled, | |
10115 | "active crtc, but not enabled in sw tracking\n"); | |
10116 | ||
10117 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
10118 | base.head) { | |
10119 | if (encoder->base.crtc != &crtc->base) | |
10120 | continue; | |
10121 | enabled = true; | |
10122 | if (encoder->connectors_active) | |
10123 | active = true; | |
10124 | } | |
6c49f241 | 10125 | |
8af6cf88 DV |
10126 | WARN(active != crtc->active, |
10127 | "crtc's computed active state doesn't match tracked active state " | |
10128 | "(expected %i, found %i)\n", active, crtc->active); | |
10129 | WARN(enabled != crtc->base.enabled, | |
10130 | "crtc's computed enabled state doesn't match tracked enabled state " | |
10131 | "(expected %i, found %i)\n", enabled, crtc->base.enabled); | |
10132 | ||
0e8ffe1b DV |
10133 | active = dev_priv->display.get_pipe_config(crtc, |
10134 | &pipe_config); | |
d62cf62a DV |
10135 | |
10136 | /* hw state is inconsistent with the pipe A quirk */ | |
10137 | if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
10138 | active = crtc->active; | |
10139 | ||
6c49f241 DV |
10140 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
10141 | base.head) { | |
3eaba51c | 10142 | enum pipe pipe; |
6c49f241 DV |
10143 | if (encoder->base.crtc != &crtc->base) |
10144 | continue; | |
1d37b689 | 10145 | if (encoder->get_hw_state(encoder, &pipe)) |
6c49f241 DV |
10146 | encoder->get_config(encoder, &pipe_config); |
10147 | } | |
10148 | ||
0e8ffe1b DV |
10149 | WARN(crtc->active != active, |
10150 | "crtc active state doesn't match with hw state " | |
10151 | "(expected %i, found %i)\n", crtc->active, active); | |
10152 | ||
c0b03411 DV |
10153 | if (active && |
10154 | !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) { | |
10155 | WARN(1, "pipe state doesn't match!\n"); | |
10156 | intel_dump_pipe_config(crtc, &pipe_config, | |
10157 | "[hw state]"); | |
10158 | intel_dump_pipe_config(crtc, &crtc->config, | |
10159 | "[sw state]"); | |
10160 | } | |
8af6cf88 DV |
10161 | } |
10162 | } | |
10163 | ||
91d1b4bd DV |
10164 | static void |
10165 | check_shared_dpll_state(struct drm_device *dev) | |
10166 | { | |
fbee40df | 10167 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
10168 | struct intel_crtc *crtc; |
10169 | struct intel_dpll_hw_state dpll_hw_state; | |
10170 | int i; | |
5358901f DV |
10171 | |
10172 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
10173 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
10174 | int enabled_crtcs = 0, active_crtcs = 0; | |
10175 | bool active; | |
10176 | ||
10177 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
10178 | ||
10179 | DRM_DEBUG_KMS("%s\n", pll->name); | |
10180 | ||
10181 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
10182 | ||
10183 | WARN(pll->active > pll->refcount, | |
10184 | "more active pll users than references: %i vs %i\n", | |
10185 | pll->active, pll->refcount); | |
10186 | WARN(pll->active && !pll->on, | |
10187 | "pll in active use but not on in sw tracking\n"); | |
35c95375 DV |
10188 | WARN(pll->on && !pll->active, |
10189 | "pll in on but not on in use in sw tracking\n"); | |
5358901f DV |
10190 | WARN(pll->on != active, |
10191 | "pll on state mismatch (expected %i, found %i)\n", | |
10192 | pll->on, active); | |
10193 | ||
d3fcc808 | 10194 | for_each_intel_crtc(dev, crtc) { |
5358901f DV |
10195 | if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll) |
10196 | enabled_crtcs++; | |
10197 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
10198 | active_crtcs++; | |
10199 | } | |
10200 | WARN(pll->active != active_crtcs, | |
10201 | "pll active crtcs mismatch (expected %i, found %i)\n", | |
10202 | pll->active, active_crtcs); | |
10203 | WARN(pll->refcount != enabled_crtcs, | |
10204 | "pll enabled crtcs mismatch (expected %i, found %i)\n", | |
10205 | pll->refcount, enabled_crtcs); | |
66e985c0 DV |
10206 | |
10207 | WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state, | |
10208 | sizeof(dpll_hw_state)), | |
10209 | "pll hw state mismatch\n"); | |
5358901f | 10210 | } |
8af6cf88 DV |
10211 | } |
10212 | ||
91d1b4bd DV |
10213 | void |
10214 | intel_modeset_check_state(struct drm_device *dev) | |
10215 | { | |
10216 | check_connector_state(dev); | |
10217 | check_encoder_state(dev); | |
10218 | check_crtc_state(dev); | |
10219 | check_shared_dpll_state(dev); | |
10220 | } | |
10221 | ||
18442d08 VS |
10222 | void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, |
10223 | int dotclock) | |
10224 | { | |
10225 | /* | |
10226 | * FDI already provided one idea for the dotclock. | |
10227 | * Yell if the encoder disagrees. | |
10228 | */ | |
241bfc38 | 10229 | WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock), |
18442d08 | 10230 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
241bfc38 | 10231 | pipe_config->adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
10232 | } |
10233 | ||
80715b2f VS |
10234 | static void update_scanline_offset(struct intel_crtc *crtc) |
10235 | { | |
10236 | struct drm_device *dev = crtc->base.dev; | |
10237 | ||
10238 | /* | |
10239 | * The scanline counter increments at the leading edge of hsync. | |
10240 | * | |
10241 | * On most platforms it starts counting from vtotal-1 on the | |
10242 | * first active line. That means the scanline counter value is | |
10243 | * always one less than what we would expect. Ie. just after | |
10244 | * start of vblank, which also occurs at start of hsync (on the | |
10245 | * last active line), the scanline counter will read vblank_start-1. | |
10246 | * | |
10247 | * On gen2 the scanline counter starts counting from 1 instead | |
10248 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
10249 | * to keep the value positive), instead of adding one. | |
10250 | * | |
10251 | * On HSW+ the behaviour of the scanline counter depends on the output | |
10252 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
10253 | * there's an extra 1 line difference. So we need to add two instead of | |
10254 | * one to the value. | |
10255 | */ | |
10256 | if (IS_GEN2(dev)) { | |
10257 | const struct drm_display_mode *mode = &crtc->config.adjusted_mode; | |
10258 | int vtotal; | |
10259 | ||
10260 | vtotal = mode->crtc_vtotal; | |
10261 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
10262 | vtotal /= 2; | |
10263 | ||
10264 | crtc->scanline_offset = vtotal - 1; | |
10265 | } else if (HAS_DDI(dev) && | |
10266 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) { | |
10267 | crtc->scanline_offset = 2; | |
10268 | } else | |
10269 | crtc->scanline_offset = 1; | |
10270 | } | |
10271 | ||
f30da187 DV |
10272 | static int __intel_set_mode(struct drm_crtc *crtc, |
10273 | struct drm_display_mode *mode, | |
10274 | int x, int y, struct drm_framebuffer *fb) | |
a6778b3c DV |
10275 | { |
10276 | struct drm_device *dev = crtc->dev; | |
fbee40df | 10277 | struct drm_i915_private *dev_priv = dev->dev_private; |
4b4b9238 | 10278 | struct drm_display_mode *saved_mode; |
b8cecdf5 | 10279 | struct intel_crtc_config *pipe_config = NULL; |
25c5b266 DV |
10280 | struct intel_crtc *intel_crtc; |
10281 | unsigned disable_pipes, prepare_pipes, modeset_pipes; | |
c0c36b94 | 10282 | int ret = 0; |
a6778b3c | 10283 | |
4b4b9238 | 10284 | saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL); |
c0c36b94 CW |
10285 | if (!saved_mode) |
10286 | return -ENOMEM; | |
a6778b3c | 10287 | |
e2e1ed41 | 10288 | intel_modeset_affected_pipes(crtc, &modeset_pipes, |
25c5b266 DV |
10289 | &prepare_pipes, &disable_pipes); |
10290 | ||
3ac18232 | 10291 | *saved_mode = crtc->mode; |
a6778b3c | 10292 | |
25c5b266 DV |
10293 | /* Hack: Because we don't (yet) support global modeset on multiple |
10294 | * crtcs, we don't keep track of the new mode for more than one crtc. | |
10295 | * Hence simply check whether any bit is set in modeset_pipes in all the | |
10296 | * pieces of code that are not yet converted to deal with mutliple crtcs | |
10297 | * changing their mode at the same time. */ | |
25c5b266 | 10298 | if (modeset_pipes) { |
4e53c2e0 | 10299 | pipe_config = intel_modeset_pipe_config(crtc, fb, mode); |
b8cecdf5 DV |
10300 | if (IS_ERR(pipe_config)) { |
10301 | ret = PTR_ERR(pipe_config); | |
10302 | pipe_config = NULL; | |
10303 | ||
3ac18232 | 10304 | goto out; |
25c5b266 | 10305 | } |
c0b03411 DV |
10306 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
10307 | "[modeset]"); | |
50741abc | 10308 | to_intel_crtc(crtc)->new_config = pipe_config; |
25c5b266 | 10309 | } |
a6778b3c | 10310 | |
30a970c6 JB |
10311 | /* |
10312 | * See if the config requires any additional preparation, e.g. | |
10313 | * to adjust global state with pipes off. We need to do this | |
10314 | * here so we can get the modeset_pipe updated config for the new | |
10315 | * mode set on this crtc. For other crtcs we need to use the | |
10316 | * adjusted_mode bits in the crtc directly. | |
10317 | */ | |
c164f833 | 10318 | if (IS_VALLEYVIEW(dev)) { |
2f2d7aa1 | 10319 | valleyview_modeset_global_pipes(dev, &prepare_pipes); |
30a970c6 | 10320 | |
c164f833 VS |
10321 | /* may have added more to prepare_pipes than we should */ |
10322 | prepare_pipes &= ~disable_pipes; | |
10323 | } | |
10324 | ||
460da916 DV |
10325 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
10326 | intel_crtc_disable(&intel_crtc->base); | |
10327 | ||
ea9d758d DV |
10328 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
10329 | if (intel_crtc->base.enabled) | |
10330 | dev_priv->display.crtc_disable(&intel_crtc->base); | |
10331 | } | |
a6778b3c | 10332 | |
6c4c86f5 DV |
10333 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
10334 | * to set it here already despite that we pass it down the callchain. | |
f6e5b160 | 10335 | */ |
b8cecdf5 | 10336 | if (modeset_pipes) { |
25c5b266 | 10337 | crtc->mode = *mode; |
b8cecdf5 DV |
10338 | /* mode_set/enable/disable functions rely on a correct pipe |
10339 | * config. */ | |
10340 | to_intel_crtc(crtc)->config = *pipe_config; | |
50741abc | 10341 | to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config; |
c326c0a9 VS |
10342 | |
10343 | /* | |
10344 | * Calculate and store various constants which | |
10345 | * are later needed by vblank and swap-completion | |
10346 | * timestamping. They are derived from true hwmode. | |
10347 | */ | |
10348 | drm_calc_timestamping_constants(crtc, | |
10349 | &pipe_config->adjusted_mode); | |
b8cecdf5 | 10350 | } |
7758a113 | 10351 | |
ea9d758d DV |
10352 | /* Only after disabling all output pipelines that will be changed can we |
10353 | * update the the output configuration. */ | |
10354 | intel_modeset_update_state(dev, prepare_pipes); | |
f6e5b160 | 10355 | |
47fab737 DV |
10356 | if (dev_priv->display.modeset_global_resources) |
10357 | dev_priv->display.modeset_global_resources(dev); | |
10358 | ||
a6778b3c DV |
10359 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
10360 | * on the DPLL. | |
f6e5b160 | 10361 | */ |
25c5b266 | 10362 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
4c10794f DV |
10363 | struct drm_framebuffer *old_fb; |
10364 | ||
10365 | mutex_lock(&dev->struct_mutex); | |
10366 | ret = intel_pin_and_fence_fb_obj(dev, | |
10367 | to_intel_framebuffer(fb)->obj, | |
10368 | NULL); | |
10369 | if (ret != 0) { | |
10370 | DRM_ERROR("pin & fence failed\n"); | |
10371 | mutex_unlock(&dev->struct_mutex); | |
10372 | goto done; | |
10373 | } | |
10374 | old_fb = crtc->primary->fb; | |
10375 | if (old_fb) | |
10376 | intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); | |
10377 | mutex_unlock(&dev->struct_mutex); | |
10378 | ||
10379 | crtc->primary->fb = fb; | |
10380 | crtc->x = x; | |
10381 | crtc->y = y; | |
10382 | ||
4271b753 DV |
10383 | ret = dev_priv->display.crtc_mode_set(&intel_crtc->base, |
10384 | x, y, fb); | |
c0c36b94 CW |
10385 | if (ret) |
10386 | goto done; | |
a6778b3c DV |
10387 | } |
10388 | ||
10389 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ | |
80715b2f VS |
10390 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
10391 | update_scanline_offset(intel_crtc); | |
10392 | ||
25c5b266 | 10393 | dev_priv->display.crtc_enable(&intel_crtc->base); |
80715b2f | 10394 | } |
a6778b3c | 10395 | |
a6778b3c DV |
10396 | /* FIXME: add subpixel order */ |
10397 | done: | |
4b4b9238 | 10398 | if (ret && crtc->enabled) |
3ac18232 | 10399 | crtc->mode = *saved_mode; |
a6778b3c | 10400 | |
3ac18232 | 10401 | out: |
b8cecdf5 | 10402 | kfree(pipe_config); |
3ac18232 | 10403 | kfree(saved_mode); |
a6778b3c | 10404 | return ret; |
f6e5b160 CW |
10405 | } |
10406 | ||
e7457a9a DL |
10407 | static int intel_set_mode(struct drm_crtc *crtc, |
10408 | struct drm_display_mode *mode, | |
10409 | int x, int y, struct drm_framebuffer *fb) | |
f30da187 DV |
10410 | { |
10411 | int ret; | |
10412 | ||
10413 | ret = __intel_set_mode(crtc, mode, x, y, fb); | |
10414 | ||
10415 | if (ret == 0) | |
10416 | intel_modeset_check_state(crtc->dev); | |
10417 | ||
10418 | return ret; | |
10419 | } | |
10420 | ||
c0c36b94 CW |
10421 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
10422 | { | |
f4510a27 | 10423 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb); |
c0c36b94 CW |
10424 | } |
10425 | ||
25c5b266 DV |
10426 | #undef for_each_intel_crtc_masked |
10427 | ||
d9e55608 DV |
10428 | static void intel_set_config_free(struct intel_set_config *config) |
10429 | { | |
10430 | if (!config) | |
10431 | return; | |
10432 | ||
1aa4b628 DV |
10433 | kfree(config->save_connector_encoders); |
10434 | kfree(config->save_encoder_crtcs); | |
7668851f | 10435 | kfree(config->save_crtc_enabled); |
d9e55608 DV |
10436 | kfree(config); |
10437 | } | |
10438 | ||
85f9eb71 DV |
10439 | static int intel_set_config_save_state(struct drm_device *dev, |
10440 | struct intel_set_config *config) | |
10441 | { | |
7668851f | 10442 | struct drm_crtc *crtc; |
85f9eb71 DV |
10443 | struct drm_encoder *encoder; |
10444 | struct drm_connector *connector; | |
10445 | int count; | |
10446 | ||
7668851f VS |
10447 | config->save_crtc_enabled = |
10448 | kcalloc(dev->mode_config.num_crtc, | |
10449 | sizeof(bool), GFP_KERNEL); | |
10450 | if (!config->save_crtc_enabled) | |
10451 | return -ENOMEM; | |
10452 | ||
1aa4b628 DV |
10453 | config->save_encoder_crtcs = |
10454 | kcalloc(dev->mode_config.num_encoder, | |
10455 | sizeof(struct drm_crtc *), GFP_KERNEL); | |
10456 | if (!config->save_encoder_crtcs) | |
85f9eb71 DV |
10457 | return -ENOMEM; |
10458 | ||
1aa4b628 DV |
10459 | config->save_connector_encoders = |
10460 | kcalloc(dev->mode_config.num_connector, | |
10461 | sizeof(struct drm_encoder *), GFP_KERNEL); | |
10462 | if (!config->save_connector_encoders) | |
85f9eb71 DV |
10463 | return -ENOMEM; |
10464 | ||
10465 | /* Copy data. Note that driver private data is not affected. | |
10466 | * Should anything bad happen only the expected state is | |
10467 | * restored, not the drivers personal bookkeeping. | |
10468 | */ | |
7668851f | 10469 | count = 0; |
70e1e0ec | 10470 | for_each_crtc(dev, crtc) { |
7668851f VS |
10471 | config->save_crtc_enabled[count++] = crtc->enabled; |
10472 | } | |
10473 | ||
85f9eb71 DV |
10474 | count = 0; |
10475 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1aa4b628 | 10476 | config->save_encoder_crtcs[count++] = encoder->crtc; |
85f9eb71 DV |
10477 | } |
10478 | ||
10479 | count = 0; | |
10480 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1aa4b628 | 10481 | config->save_connector_encoders[count++] = connector->encoder; |
85f9eb71 DV |
10482 | } |
10483 | ||
10484 | return 0; | |
10485 | } | |
10486 | ||
10487 | static void intel_set_config_restore_state(struct drm_device *dev, | |
10488 | struct intel_set_config *config) | |
10489 | { | |
7668851f | 10490 | struct intel_crtc *crtc; |
9a935856 DV |
10491 | struct intel_encoder *encoder; |
10492 | struct intel_connector *connector; | |
85f9eb71 DV |
10493 | int count; |
10494 | ||
7668851f | 10495 | count = 0; |
d3fcc808 | 10496 | for_each_intel_crtc(dev, crtc) { |
7668851f | 10497 | crtc->new_enabled = config->save_crtc_enabled[count++]; |
7bd0a8e7 VS |
10498 | |
10499 | if (crtc->new_enabled) | |
10500 | crtc->new_config = &crtc->config; | |
10501 | else | |
10502 | crtc->new_config = NULL; | |
7668851f VS |
10503 | } |
10504 | ||
85f9eb71 | 10505 | count = 0; |
9a935856 DV |
10506 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
10507 | encoder->new_crtc = | |
10508 | to_intel_crtc(config->save_encoder_crtcs[count++]); | |
85f9eb71 DV |
10509 | } |
10510 | ||
10511 | count = 0; | |
9a935856 DV |
10512 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
10513 | connector->new_encoder = | |
10514 | to_intel_encoder(config->save_connector_encoders[count++]); | |
85f9eb71 DV |
10515 | } |
10516 | } | |
10517 | ||
e3de42b6 | 10518 | static bool |
2e57f47d | 10519 | is_crtc_connector_off(struct drm_mode_set *set) |
e3de42b6 ID |
10520 | { |
10521 | int i; | |
10522 | ||
2e57f47d CW |
10523 | if (set->num_connectors == 0) |
10524 | return false; | |
10525 | ||
10526 | if (WARN_ON(set->connectors == NULL)) | |
10527 | return false; | |
10528 | ||
10529 | for (i = 0; i < set->num_connectors; i++) | |
10530 | if (set->connectors[i]->encoder && | |
10531 | set->connectors[i]->encoder->crtc == set->crtc && | |
10532 | set->connectors[i]->dpms != DRM_MODE_DPMS_ON) | |
e3de42b6 ID |
10533 | return true; |
10534 | ||
10535 | return false; | |
10536 | } | |
10537 | ||
5e2b584e DV |
10538 | static void |
10539 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, | |
10540 | struct intel_set_config *config) | |
10541 | { | |
10542 | ||
10543 | /* We should be able to check here if the fb has the same properties | |
10544 | * and then just flip_or_move it */ | |
2e57f47d CW |
10545 | if (is_crtc_connector_off(set)) { |
10546 | config->mode_changed = true; | |
f4510a27 | 10547 | } else if (set->crtc->primary->fb != set->fb) { |
5e2b584e | 10548 | /* If we have no fb then treat it as a full mode set */ |
f4510a27 | 10549 | if (set->crtc->primary->fb == NULL) { |
319d9827 JB |
10550 | struct intel_crtc *intel_crtc = |
10551 | to_intel_crtc(set->crtc); | |
10552 | ||
d330a953 | 10553 | if (intel_crtc->active && i915.fastboot) { |
319d9827 JB |
10554 | DRM_DEBUG_KMS("crtc has no fb, will flip\n"); |
10555 | config->fb_changed = true; | |
10556 | } else { | |
10557 | DRM_DEBUG_KMS("inactive crtc, full mode set\n"); | |
10558 | config->mode_changed = true; | |
10559 | } | |
5e2b584e DV |
10560 | } else if (set->fb == NULL) { |
10561 | config->mode_changed = true; | |
72f4901e | 10562 | } else if (set->fb->pixel_format != |
f4510a27 | 10563 | set->crtc->primary->fb->pixel_format) { |
5e2b584e | 10564 | config->mode_changed = true; |
e3de42b6 | 10565 | } else { |
5e2b584e | 10566 | config->fb_changed = true; |
e3de42b6 | 10567 | } |
5e2b584e DV |
10568 | } |
10569 | ||
835c5873 | 10570 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
5e2b584e DV |
10571 | config->fb_changed = true; |
10572 | ||
10573 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { | |
10574 | DRM_DEBUG_KMS("modes are different, full mode set\n"); | |
10575 | drm_mode_debug_printmodeline(&set->crtc->mode); | |
10576 | drm_mode_debug_printmodeline(set->mode); | |
10577 | config->mode_changed = true; | |
10578 | } | |
a1d95703 CW |
10579 | |
10580 | DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n", | |
10581 | set->crtc->base.id, config->mode_changed, config->fb_changed); | |
5e2b584e DV |
10582 | } |
10583 | ||
2e431051 | 10584 | static int |
9a935856 DV |
10585 | intel_modeset_stage_output_state(struct drm_device *dev, |
10586 | struct drm_mode_set *set, | |
10587 | struct intel_set_config *config) | |
50f56119 | 10588 | { |
9a935856 DV |
10589 | struct intel_connector *connector; |
10590 | struct intel_encoder *encoder; | |
7668851f | 10591 | struct intel_crtc *crtc; |
f3f08572 | 10592 | int ro; |
50f56119 | 10593 | |
9abdda74 | 10594 | /* The upper layers ensure that we either disable a crtc or have a list |
9a935856 DV |
10595 | * of connectors. For paranoia, double-check this. */ |
10596 | WARN_ON(!set->fb && (set->num_connectors != 0)); | |
10597 | WARN_ON(set->fb && (set->num_connectors == 0)); | |
10598 | ||
9a935856 DV |
10599 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
10600 | base.head) { | |
10601 | /* Otherwise traverse passed in connector list and get encoders | |
10602 | * for them. */ | |
50f56119 | 10603 | for (ro = 0; ro < set->num_connectors; ro++) { |
9a935856 DV |
10604 | if (set->connectors[ro] == &connector->base) { |
10605 | connector->new_encoder = connector->encoder; | |
50f56119 DV |
10606 | break; |
10607 | } | |
10608 | } | |
10609 | ||
9a935856 DV |
10610 | /* If we disable the crtc, disable all its connectors. Also, if |
10611 | * the connector is on the changing crtc but not on the new | |
10612 | * connector list, disable it. */ | |
10613 | if ((!set->fb || ro == set->num_connectors) && | |
10614 | connector->base.encoder && | |
10615 | connector->base.encoder->crtc == set->crtc) { | |
10616 | connector->new_encoder = NULL; | |
10617 | ||
10618 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", | |
10619 | connector->base.base.id, | |
10620 | drm_get_connector_name(&connector->base)); | |
10621 | } | |
10622 | ||
10623 | ||
10624 | if (&connector->new_encoder->base != connector->base.encoder) { | |
50f56119 | 10625 | DRM_DEBUG_KMS("encoder changed, full mode switch\n"); |
5e2b584e | 10626 | config->mode_changed = true; |
50f56119 DV |
10627 | } |
10628 | } | |
9a935856 | 10629 | /* connector->new_encoder is now updated for all connectors. */ |
50f56119 | 10630 | |
9a935856 | 10631 | /* Update crtc of enabled connectors. */ |
9a935856 DV |
10632 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
10633 | base.head) { | |
7668851f VS |
10634 | struct drm_crtc *new_crtc; |
10635 | ||
9a935856 | 10636 | if (!connector->new_encoder) |
50f56119 DV |
10637 | continue; |
10638 | ||
9a935856 | 10639 | new_crtc = connector->new_encoder->base.crtc; |
50f56119 DV |
10640 | |
10641 | for (ro = 0; ro < set->num_connectors; ro++) { | |
9a935856 | 10642 | if (set->connectors[ro] == &connector->base) |
50f56119 DV |
10643 | new_crtc = set->crtc; |
10644 | } | |
10645 | ||
10646 | /* Make sure the new CRTC will work with the encoder */ | |
14509916 TR |
10647 | if (!drm_encoder_crtc_ok(&connector->new_encoder->base, |
10648 | new_crtc)) { | |
5e2b584e | 10649 | return -EINVAL; |
50f56119 | 10650 | } |
9a935856 DV |
10651 | connector->encoder->new_crtc = to_intel_crtc(new_crtc); |
10652 | ||
10653 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", | |
10654 | connector->base.base.id, | |
10655 | drm_get_connector_name(&connector->base), | |
10656 | new_crtc->base.id); | |
10657 | } | |
10658 | ||
10659 | /* Check for any encoders that needs to be disabled. */ | |
10660 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
10661 | base.head) { | |
5a65f358 | 10662 | int num_connectors = 0; |
9a935856 DV |
10663 | list_for_each_entry(connector, |
10664 | &dev->mode_config.connector_list, | |
10665 | base.head) { | |
10666 | if (connector->new_encoder == encoder) { | |
10667 | WARN_ON(!connector->new_encoder->new_crtc); | |
5a65f358 | 10668 | num_connectors++; |
9a935856 DV |
10669 | } |
10670 | } | |
5a65f358 PZ |
10671 | |
10672 | if (num_connectors == 0) | |
10673 | encoder->new_crtc = NULL; | |
10674 | else if (num_connectors > 1) | |
10675 | return -EINVAL; | |
10676 | ||
9a935856 DV |
10677 | /* Only now check for crtc changes so we don't miss encoders |
10678 | * that will be disabled. */ | |
10679 | if (&encoder->new_crtc->base != encoder->base.crtc) { | |
50f56119 | 10680 | DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
5e2b584e | 10681 | config->mode_changed = true; |
50f56119 DV |
10682 | } |
10683 | } | |
9a935856 | 10684 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
50f56119 | 10685 | |
d3fcc808 | 10686 | for_each_intel_crtc(dev, crtc) { |
7668851f VS |
10687 | crtc->new_enabled = false; |
10688 | ||
10689 | list_for_each_entry(encoder, | |
10690 | &dev->mode_config.encoder_list, | |
10691 | base.head) { | |
10692 | if (encoder->new_crtc == crtc) { | |
10693 | crtc->new_enabled = true; | |
10694 | break; | |
10695 | } | |
10696 | } | |
10697 | ||
10698 | if (crtc->new_enabled != crtc->base.enabled) { | |
10699 | DRM_DEBUG_KMS("crtc %sabled, full mode switch\n", | |
10700 | crtc->new_enabled ? "en" : "dis"); | |
10701 | config->mode_changed = true; | |
10702 | } | |
7bd0a8e7 VS |
10703 | |
10704 | if (crtc->new_enabled) | |
10705 | crtc->new_config = &crtc->config; | |
10706 | else | |
10707 | crtc->new_config = NULL; | |
7668851f VS |
10708 | } |
10709 | ||
2e431051 DV |
10710 | return 0; |
10711 | } | |
10712 | ||
7d00a1f5 VS |
10713 | static void disable_crtc_nofb(struct intel_crtc *crtc) |
10714 | { | |
10715 | struct drm_device *dev = crtc->base.dev; | |
10716 | struct intel_encoder *encoder; | |
10717 | struct intel_connector *connector; | |
10718 | ||
10719 | DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n", | |
10720 | pipe_name(crtc->pipe)); | |
10721 | ||
10722 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { | |
10723 | if (connector->new_encoder && | |
10724 | connector->new_encoder->new_crtc == crtc) | |
10725 | connector->new_encoder = NULL; | |
10726 | } | |
10727 | ||
10728 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { | |
10729 | if (encoder->new_crtc == crtc) | |
10730 | encoder->new_crtc = NULL; | |
10731 | } | |
10732 | ||
10733 | crtc->new_enabled = false; | |
7bd0a8e7 | 10734 | crtc->new_config = NULL; |
7d00a1f5 VS |
10735 | } |
10736 | ||
2e431051 DV |
10737 | static int intel_crtc_set_config(struct drm_mode_set *set) |
10738 | { | |
10739 | struct drm_device *dev; | |
2e431051 DV |
10740 | struct drm_mode_set save_set; |
10741 | struct intel_set_config *config; | |
10742 | int ret; | |
2e431051 | 10743 | |
8d3e375e DV |
10744 | BUG_ON(!set); |
10745 | BUG_ON(!set->crtc); | |
10746 | BUG_ON(!set->crtc->helper_private); | |
2e431051 | 10747 | |
7e53f3a4 DV |
10748 | /* Enforce sane interface api - has been abused by the fb helper. */ |
10749 | BUG_ON(!set->mode && set->fb); | |
10750 | BUG_ON(set->fb && set->num_connectors == 0); | |
431e50f7 | 10751 | |
2e431051 DV |
10752 | if (set->fb) { |
10753 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", | |
10754 | set->crtc->base.id, set->fb->base.id, | |
10755 | (int)set->num_connectors, set->x, set->y); | |
10756 | } else { | |
10757 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); | |
2e431051 DV |
10758 | } |
10759 | ||
10760 | dev = set->crtc->dev; | |
10761 | ||
10762 | ret = -ENOMEM; | |
10763 | config = kzalloc(sizeof(*config), GFP_KERNEL); | |
10764 | if (!config) | |
10765 | goto out_config; | |
10766 | ||
10767 | ret = intel_set_config_save_state(dev, config); | |
10768 | if (ret) | |
10769 | goto out_config; | |
10770 | ||
10771 | save_set.crtc = set->crtc; | |
10772 | save_set.mode = &set->crtc->mode; | |
10773 | save_set.x = set->crtc->x; | |
10774 | save_set.y = set->crtc->y; | |
f4510a27 | 10775 | save_set.fb = set->crtc->primary->fb; |
2e431051 DV |
10776 | |
10777 | /* Compute whether we need a full modeset, only an fb base update or no | |
10778 | * change at all. In the future we might also check whether only the | |
10779 | * mode changed, e.g. for LVDS where we only change the panel fitter in | |
10780 | * such cases. */ | |
10781 | intel_set_config_compute_mode_changes(set, config); | |
10782 | ||
9a935856 | 10783 | ret = intel_modeset_stage_output_state(dev, set, config); |
2e431051 DV |
10784 | if (ret) |
10785 | goto fail; | |
10786 | ||
5e2b584e | 10787 | if (config->mode_changed) { |
c0c36b94 CW |
10788 | ret = intel_set_mode(set->crtc, set->mode, |
10789 | set->x, set->y, set->fb); | |
5e2b584e | 10790 | } else if (config->fb_changed) { |
4878cae2 VS |
10791 | intel_crtc_wait_for_pending_flips(set->crtc); |
10792 | ||
4f660f49 | 10793 | ret = intel_pipe_set_base(set->crtc, |
94352cf9 | 10794 | set->x, set->y, set->fb); |
7ca51a3a JB |
10795 | /* |
10796 | * In the fastboot case this may be our only check of the | |
10797 | * state after boot. It would be better to only do it on | |
10798 | * the first update, but we don't have a nice way of doing that | |
10799 | * (and really, set_config isn't used much for high freq page | |
10800 | * flipping, so increasing its cost here shouldn't be a big | |
10801 | * deal). | |
10802 | */ | |
d330a953 | 10803 | if (i915.fastboot && ret == 0) |
7ca51a3a | 10804 | intel_modeset_check_state(set->crtc->dev); |
50f56119 DV |
10805 | } |
10806 | ||
2d05eae1 | 10807 | if (ret) { |
bf67dfeb DV |
10808 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
10809 | set->crtc->base.id, ret); | |
50f56119 | 10810 | fail: |
2d05eae1 | 10811 | intel_set_config_restore_state(dev, config); |
50f56119 | 10812 | |
7d00a1f5 VS |
10813 | /* |
10814 | * HACK: if the pipe was on, but we didn't have a framebuffer, | |
10815 | * force the pipe off to avoid oopsing in the modeset code | |
10816 | * due to fb==NULL. This should only happen during boot since | |
10817 | * we don't yet reconstruct the FB from the hardware state. | |
10818 | */ | |
10819 | if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb) | |
10820 | disable_crtc_nofb(to_intel_crtc(save_set.crtc)); | |
10821 | ||
2d05eae1 CW |
10822 | /* Try to restore the config */ |
10823 | if (config->mode_changed && | |
10824 | intel_set_mode(save_set.crtc, save_set.mode, | |
10825 | save_set.x, save_set.y, save_set.fb)) | |
10826 | DRM_ERROR("failed to restore config after modeset failure\n"); | |
10827 | } | |
50f56119 | 10828 | |
d9e55608 DV |
10829 | out_config: |
10830 | intel_set_config_free(config); | |
50f56119 DV |
10831 | return ret; |
10832 | } | |
f6e5b160 CW |
10833 | |
10834 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
f6e5b160 CW |
10835 | .cursor_set = intel_crtc_cursor_set, |
10836 | .cursor_move = intel_crtc_cursor_move, | |
10837 | .gamma_set = intel_crtc_gamma_set, | |
50f56119 | 10838 | .set_config = intel_crtc_set_config, |
f6e5b160 CW |
10839 | .destroy = intel_crtc_destroy, |
10840 | .page_flip = intel_crtc_page_flip, | |
10841 | }; | |
10842 | ||
79f689aa PZ |
10843 | static void intel_cpu_pll_init(struct drm_device *dev) |
10844 | { | |
affa9354 | 10845 | if (HAS_DDI(dev)) |
79f689aa PZ |
10846 | intel_ddi_pll_init(dev); |
10847 | } | |
10848 | ||
5358901f DV |
10849 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
10850 | struct intel_shared_dpll *pll, | |
10851 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 10852 | { |
5358901f | 10853 | uint32_t val; |
ee7b9f93 | 10854 | |
5358901f | 10855 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
10856 | hw_state->dpll = val; |
10857 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
10858 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
10859 | |
10860 | return val & DPLL_VCO_ENABLE; | |
10861 | } | |
10862 | ||
15bdd4cf DV |
10863 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
10864 | struct intel_shared_dpll *pll) | |
10865 | { | |
10866 | I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0); | |
10867 | I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1); | |
10868 | } | |
10869 | ||
e7b903d2 DV |
10870 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
10871 | struct intel_shared_dpll *pll) | |
10872 | { | |
e7b903d2 | 10873 | /* PCH refclock must be enabled first */ |
89eff4be | 10874 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 10875 | |
15bdd4cf DV |
10876 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); |
10877 | ||
10878 | /* Wait for the clocks to stabilize. */ | |
10879 | POSTING_READ(PCH_DPLL(pll->id)); | |
10880 | udelay(150); | |
10881 | ||
10882 | /* The pixel multiplier can only be updated once the | |
10883 | * DPLL is enabled and the clocks are stable. | |
10884 | * | |
10885 | * So write it again. | |
10886 | */ | |
10887 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); | |
10888 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
10889 | udelay(200); |
10890 | } | |
10891 | ||
10892 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
10893 | struct intel_shared_dpll *pll) | |
10894 | { | |
10895 | struct drm_device *dev = dev_priv->dev; | |
10896 | struct intel_crtc *crtc; | |
e7b903d2 DV |
10897 | |
10898 | /* Make sure no transcoder isn't still depending on us. */ | |
d3fcc808 | 10899 | for_each_intel_crtc(dev, crtc) { |
e7b903d2 DV |
10900 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
10901 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
10902 | } |
10903 | ||
15bdd4cf DV |
10904 | I915_WRITE(PCH_DPLL(pll->id), 0); |
10905 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
10906 | udelay(200); |
10907 | } | |
10908 | ||
46edb027 DV |
10909 | static char *ibx_pch_dpll_names[] = { |
10910 | "PCH DPLL A", | |
10911 | "PCH DPLL B", | |
10912 | }; | |
10913 | ||
7c74ade1 | 10914 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 10915 | { |
e7b903d2 | 10916 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
10917 | int i; |
10918 | ||
7c74ade1 | 10919 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 10920 | |
e72f9fbf | 10921 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
10922 | dev_priv->shared_dplls[i].id = i; |
10923 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 10924 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
10925 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
10926 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
10927 | dev_priv->shared_dplls[i].get_hw_state = |
10928 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
10929 | } |
10930 | } | |
10931 | ||
7c74ade1 DV |
10932 | static void intel_shared_dpll_init(struct drm_device *dev) |
10933 | { | |
e7b903d2 | 10934 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 DV |
10935 | |
10936 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
10937 | ibx_pch_dpll_init(dev); | |
10938 | else | |
10939 | dev_priv->num_shared_dpll = 0; | |
10940 | ||
10941 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
10942 | } |
10943 | ||
b358d0a6 | 10944 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 10945 | { |
fbee40df | 10946 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 JB |
10947 | struct intel_crtc *intel_crtc; |
10948 | int i; | |
10949 | ||
955382f3 | 10950 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
10951 | if (intel_crtc == NULL) |
10952 | return; | |
10953 | ||
10954 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); | |
10955 | ||
10956 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
10957 | for (i = 0; i < 256; i++) { |
10958 | intel_crtc->lut_r[i] = i; | |
10959 | intel_crtc->lut_g[i] = i; | |
10960 | intel_crtc->lut_b[i] = i; | |
10961 | } | |
10962 | ||
1f1c2e24 VS |
10963 | /* |
10964 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
10965 | * is hooked to plane B. Hence we want plane A feeding pipe B. | |
10966 | */ | |
80824003 JB |
10967 | intel_crtc->pipe = pipe; |
10968 | intel_crtc->plane = pipe; | |
3a77c4c4 | 10969 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 10970 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 10971 | intel_crtc->plane = !pipe; |
80824003 JB |
10972 | } |
10973 | ||
8d7849db VS |
10974 | init_waitqueue_head(&intel_crtc->vbl_wait); |
10975 | ||
22fd0fab JB |
10976 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
10977 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
10978 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
10979 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
10980 | ||
79e53945 | 10981 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 DV |
10982 | |
10983 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); | |
79e53945 JB |
10984 | } |
10985 | ||
752aa88a JB |
10986 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
10987 | { | |
10988 | struct drm_encoder *encoder = connector->base.encoder; | |
10989 | ||
10990 | WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex)); | |
10991 | ||
10992 | if (!encoder) | |
10993 | return INVALID_PIPE; | |
10994 | ||
10995 | return to_intel_crtc(encoder->crtc)->pipe; | |
10996 | } | |
10997 | ||
08d7b3d1 | 10998 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 10999 | struct drm_file *file) |
08d7b3d1 | 11000 | { |
08d7b3d1 | 11001 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
c05422d5 DV |
11002 | struct drm_mode_object *drmmode_obj; |
11003 | struct intel_crtc *crtc; | |
08d7b3d1 | 11004 | |
1cff8f6b DV |
11005 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
11006 | return -ENODEV; | |
08d7b3d1 | 11007 | |
c05422d5 DV |
11008 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
11009 | DRM_MODE_OBJECT_CRTC); | |
08d7b3d1 | 11010 | |
c05422d5 | 11011 | if (!drmmode_obj) { |
08d7b3d1 | 11012 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 11013 | return -ENOENT; |
08d7b3d1 CW |
11014 | } |
11015 | ||
c05422d5 DV |
11016 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
11017 | pipe_from_crtc_id->pipe = crtc->pipe; | |
08d7b3d1 | 11018 | |
c05422d5 | 11019 | return 0; |
08d7b3d1 CW |
11020 | } |
11021 | ||
66a9278e | 11022 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 11023 | { |
66a9278e DV |
11024 | struct drm_device *dev = encoder->base.dev; |
11025 | struct intel_encoder *source_encoder; | |
79e53945 | 11026 | int index_mask = 0; |
79e53945 JB |
11027 | int entry = 0; |
11028 | ||
66a9278e DV |
11029 | list_for_each_entry(source_encoder, |
11030 | &dev->mode_config.encoder_list, base.head) { | |
bc079e8b | 11031 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
11032 | index_mask |= (1 << entry); |
11033 | ||
79e53945 JB |
11034 | entry++; |
11035 | } | |
4ef69c7a | 11036 | |
79e53945 JB |
11037 | return index_mask; |
11038 | } | |
11039 | ||
4d302442 CW |
11040 | static bool has_edp_a(struct drm_device *dev) |
11041 | { | |
11042 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11043 | ||
11044 | if (!IS_MOBILE(dev)) | |
11045 | return false; | |
11046 | ||
11047 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
11048 | return false; | |
11049 | ||
e3589908 | 11050 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
11051 | return false; |
11052 | ||
11053 | return true; | |
11054 | } | |
11055 | ||
ba0fbca4 DL |
11056 | const char *intel_output_name(int output) |
11057 | { | |
11058 | static const char *names[] = { | |
11059 | [INTEL_OUTPUT_UNUSED] = "Unused", | |
11060 | [INTEL_OUTPUT_ANALOG] = "Analog", | |
11061 | [INTEL_OUTPUT_DVO] = "DVO", | |
11062 | [INTEL_OUTPUT_SDVO] = "SDVO", | |
11063 | [INTEL_OUTPUT_LVDS] = "LVDS", | |
11064 | [INTEL_OUTPUT_TVOUT] = "TV", | |
11065 | [INTEL_OUTPUT_HDMI] = "HDMI", | |
11066 | [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort", | |
11067 | [INTEL_OUTPUT_EDP] = "eDP", | |
11068 | [INTEL_OUTPUT_DSI] = "DSI", | |
11069 | [INTEL_OUTPUT_UNKNOWN] = "Unknown", | |
11070 | }; | |
11071 | ||
11072 | if (output < 0 || output >= ARRAY_SIZE(names) || !names[output]) | |
11073 | return "Invalid"; | |
11074 | ||
11075 | return names[output]; | |
11076 | } | |
11077 | ||
79e53945 JB |
11078 | static void intel_setup_outputs(struct drm_device *dev) |
11079 | { | |
725e30ad | 11080 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 11081 | struct intel_encoder *encoder; |
cb0953d7 | 11082 | bool dpd_is_edp = false; |
79e53945 | 11083 | |
c9093354 | 11084 | intel_lvds_init(dev); |
79e53945 | 11085 | |
7895a81d | 11086 | if (!IS_ULT(dev) && !IS_CHERRYVIEW(dev)) |
79935fca | 11087 | intel_crt_init(dev); |
cb0953d7 | 11088 | |
affa9354 | 11089 | if (HAS_DDI(dev)) { |
0e72a5b5 ED |
11090 | int found; |
11091 | ||
11092 | /* Haswell uses DDI functions to detect digital outputs */ | |
11093 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; | |
11094 | /* DDI A only supports eDP */ | |
11095 | if (found) | |
11096 | intel_ddi_init(dev, PORT_A); | |
11097 | ||
11098 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
11099 | * register */ | |
11100 | found = I915_READ(SFUSE_STRAP); | |
11101 | ||
11102 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
11103 | intel_ddi_init(dev, PORT_B); | |
11104 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
11105 | intel_ddi_init(dev, PORT_C); | |
11106 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
11107 | intel_ddi_init(dev, PORT_D); | |
11108 | } else if (HAS_PCH_SPLIT(dev)) { | |
cb0953d7 | 11109 | int found; |
5d8a7752 | 11110 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
11111 | |
11112 | if (has_edp_a(dev)) | |
11113 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 11114 | |
dc0fa718 | 11115 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 11116 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 11117 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 11118 | if (!found) |
e2debe91 | 11119 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 11120 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 11121 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
11122 | } |
11123 | ||
dc0fa718 | 11124 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 11125 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 11126 | |
dc0fa718 | 11127 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 11128 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 11129 | |
5eb08b69 | 11130 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 11131 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 11132 | |
270b3042 | 11133 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 11134 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d | 11135 | } else if (IS_VALLEYVIEW(dev)) { |
585a94b8 AB |
11136 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) { |
11137 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, | |
11138 | PORT_B); | |
11139 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED) | |
11140 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); | |
11141 | } | |
11142 | ||
6f6005a5 JB |
11143 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) { |
11144 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, | |
11145 | PORT_C); | |
11146 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) | |
5d8a7752 | 11147 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); |
6f6005a5 | 11148 | } |
19c03924 | 11149 | |
9418c1f1 VS |
11150 | if (IS_CHERRYVIEW(dev)) { |
11151 | if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) { | |
11152 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID, | |
11153 | PORT_D); | |
11154 | if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED) | |
11155 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D); | |
11156 | } | |
11157 | } | |
11158 | ||
3cfca973 | 11159 | intel_dsi_init(dev); |
103a196f | 11160 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 11161 | bool found = false; |
7d57382e | 11162 | |
e2debe91 | 11163 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 11164 | DRM_DEBUG_KMS("probing SDVOB\n"); |
e2debe91 | 11165 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
b01f2c3a JB |
11166 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
11167 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
e2debe91 | 11168 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 11169 | } |
27185ae1 | 11170 | |
e7281eab | 11171 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 11172 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 11173 | } |
13520b05 KH |
11174 | |
11175 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 11176 | |
e2debe91 | 11177 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 11178 | DRM_DEBUG_KMS("probing SDVOC\n"); |
e2debe91 | 11179 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
b01f2c3a | 11180 | } |
27185ae1 | 11181 | |
e2debe91 | 11182 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 11183 | |
b01f2c3a JB |
11184 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
11185 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
e2debe91 | 11186 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 11187 | } |
e7281eab | 11188 | if (SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 11189 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 11190 | } |
27185ae1 | 11191 | |
b01f2c3a | 11192 | if (SUPPORTS_INTEGRATED_DP(dev) && |
e7281eab | 11193 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 11194 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 11195 | } else if (IS_GEN2(dev)) |
79e53945 JB |
11196 | intel_dvo_init(dev); |
11197 | ||
103a196f | 11198 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
11199 | intel_tv_init(dev); |
11200 | ||
4ef69c7a CW |
11201 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
11202 | encoder->base.possible_crtcs = encoder->crtc_mask; | |
11203 | encoder->base.possible_clones = | |
66a9278e | 11204 | intel_encoder_clones(encoder); |
79e53945 | 11205 | } |
47356eb6 | 11206 | |
dde86e2d | 11207 | intel_init_pch_refclk(dev); |
270b3042 DV |
11208 | |
11209 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
11210 | } |
11211 | ||
11212 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
11213 | { | |
11214 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 | 11215 | |
ef2d633e DV |
11216 | drm_framebuffer_cleanup(fb); |
11217 | WARN_ON(!intel_fb->obj->framebuffer_references--); | |
11218 | drm_gem_object_unreference_unlocked(&intel_fb->obj->base); | |
79e53945 JB |
11219 | kfree(intel_fb); |
11220 | } | |
11221 | ||
11222 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 11223 | struct drm_file *file, |
79e53945 JB |
11224 | unsigned int *handle) |
11225 | { | |
11226 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 11227 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 11228 | |
05394f39 | 11229 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
11230 | } |
11231 | ||
11232 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
11233 | .destroy = intel_user_framebuffer_destroy, | |
11234 | .create_handle = intel_user_framebuffer_create_handle, | |
11235 | }; | |
11236 | ||
b5ea642a DV |
11237 | static int intel_framebuffer_init(struct drm_device *dev, |
11238 | struct intel_framebuffer *intel_fb, | |
11239 | struct drm_mode_fb_cmd2 *mode_cmd, | |
11240 | struct drm_i915_gem_object *obj) | |
79e53945 | 11241 | { |
a57ce0b2 | 11242 | int aligned_height; |
a35cdaa0 | 11243 | int pitch_limit; |
79e53945 JB |
11244 | int ret; |
11245 | ||
dd4916c5 DV |
11246 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
11247 | ||
c16ed4be CW |
11248 | if (obj->tiling_mode == I915_TILING_Y) { |
11249 | DRM_DEBUG("hardware does not support tiling Y\n"); | |
57cd6508 | 11250 | return -EINVAL; |
c16ed4be | 11251 | } |
57cd6508 | 11252 | |
c16ed4be CW |
11253 | if (mode_cmd->pitches[0] & 63) { |
11254 | DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n", | |
11255 | mode_cmd->pitches[0]); | |
57cd6508 | 11256 | return -EINVAL; |
c16ed4be | 11257 | } |
57cd6508 | 11258 | |
a35cdaa0 CW |
11259 | if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) { |
11260 | pitch_limit = 32*1024; | |
11261 | } else if (INTEL_INFO(dev)->gen >= 4) { | |
11262 | if (obj->tiling_mode) | |
11263 | pitch_limit = 16*1024; | |
11264 | else | |
11265 | pitch_limit = 32*1024; | |
11266 | } else if (INTEL_INFO(dev)->gen >= 3) { | |
11267 | if (obj->tiling_mode) | |
11268 | pitch_limit = 8*1024; | |
11269 | else | |
11270 | pitch_limit = 16*1024; | |
11271 | } else | |
11272 | /* XXX DSPC is limited to 4k tiled */ | |
11273 | pitch_limit = 8*1024; | |
11274 | ||
11275 | if (mode_cmd->pitches[0] > pitch_limit) { | |
11276 | DRM_DEBUG("%s pitch (%d) must be at less than %d\n", | |
11277 | obj->tiling_mode ? "tiled" : "linear", | |
11278 | mode_cmd->pitches[0], pitch_limit); | |
5d7bd705 | 11279 | return -EINVAL; |
c16ed4be | 11280 | } |
5d7bd705 VS |
11281 | |
11282 | if (obj->tiling_mode != I915_TILING_NONE && | |
c16ed4be CW |
11283 | mode_cmd->pitches[0] != obj->stride) { |
11284 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
11285 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 11286 | return -EINVAL; |
c16ed4be | 11287 | } |
5d7bd705 | 11288 | |
57779d06 | 11289 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 11290 | switch (mode_cmd->pixel_format) { |
57779d06 | 11291 | case DRM_FORMAT_C8: |
04b3924d VS |
11292 | case DRM_FORMAT_RGB565: |
11293 | case DRM_FORMAT_XRGB8888: | |
11294 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
11295 | break; |
11296 | case DRM_FORMAT_XRGB1555: | |
11297 | case DRM_FORMAT_ARGB1555: | |
c16ed4be | 11298 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
11299 | DRM_DEBUG("unsupported pixel format: %s\n", |
11300 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 11301 | return -EINVAL; |
c16ed4be | 11302 | } |
57779d06 VS |
11303 | break; |
11304 | case DRM_FORMAT_XBGR8888: | |
11305 | case DRM_FORMAT_ABGR8888: | |
04b3924d VS |
11306 | case DRM_FORMAT_XRGB2101010: |
11307 | case DRM_FORMAT_ARGB2101010: | |
57779d06 VS |
11308 | case DRM_FORMAT_XBGR2101010: |
11309 | case DRM_FORMAT_ABGR2101010: | |
c16ed4be | 11310 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
11311 | DRM_DEBUG("unsupported pixel format: %s\n", |
11312 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 11313 | return -EINVAL; |
c16ed4be | 11314 | } |
b5626747 | 11315 | break; |
04b3924d VS |
11316 | case DRM_FORMAT_YUYV: |
11317 | case DRM_FORMAT_UYVY: | |
11318 | case DRM_FORMAT_YVYU: | |
11319 | case DRM_FORMAT_VYUY: | |
c16ed4be | 11320 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
11321 | DRM_DEBUG("unsupported pixel format: %s\n", |
11322 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 11323 | return -EINVAL; |
c16ed4be | 11324 | } |
57cd6508 CW |
11325 | break; |
11326 | default: | |
4ee62c76 VS |
11327 | DRM_DEBUG("unsupported pixel format: %s\n", |
11328 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
11329 | return -EINVAL; |
11330 | } | |
11331 | ||
90f9a336 VS |
11332 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
11333 | if (mode_cmd->offsets[0] != 0) | |
11334 | return -EINVAL; | |
11335 | ||
a57ce0b2 JB |
11336 | aligned_height = intel_align_height(dev, mode_cmd->height, |
11337 | obj->tiling_mode); | |
53155c0a DV |
11338 | /* FIXME drm helper for size checks (especially planar formats)? */ |
11339 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
11340 | return -EINVAL; | |
11341 | ||
c7d73f6a DV |
11342 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
11343 | intel_fb->obj = obj; | |
80075d49 | 11344 | intel_fb->obj->framebuffer_references++; |
c7d73f6a | 11345 | |
79e53945 JB |
11346 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
11347 | if (ret) { | |
11348 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
11349 | return ret; | |
11350 | } | |
11351 | ||
79e53945 JB |
11352 | return 0; |
11353 | } | |
11354 | ||
79e53945 JB |
11355 | static struct drm_framebuffer * |
11356 | intel_user_framebuffer_create(struct drm_device *dev, | |
11357 | struct drm_file *filp, | |
308e5bcb | 11358 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 11359 | { |
05394f39 | 11360 | struct drm_i915_gem_object *obj; |
79e53945 | 11361 | |
308e5bcb JB |
11362 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
11363 | mode_cmd->handles[0])); | |
c8725226 | 11364 | if (&obj->base == NULL) |
cce13ff7 | 11365 | return ERR_PTR(-ENOENT); |
79e53945 | 11366 | |
d2dff872 | 11367 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
11368 | } |
11369 | ||
4520f53a | 11370 | #ifndef CONFIG_DRM_I915_FBDEV |
0632fef6 | 11371 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
11372 | { |
11373 | } | |
11374 | #endif | |
11375 | ||
79e53945 | 11376 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 11377 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 11378 | .output_poll_changed = intel_fbdev_output_poll_changed, |
79e53945 JB |
11379 | }; |
11380 | ||
e70236a8 JB |
11381 | /* Set up chip specific display functions */ |
11382 | static void intel_init_display(struct drm_device *dev) | |
11383 | { | |
11384 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11385 | ||
ee9300bb DV |
11386 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
11387 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
ef9348c8 CML |
11388 | else if (IS_CHERRYVIEW(dev)) |
11389 | dev_priv->display.find_dpll = chv_find_best_dpll; | |
ee9300bb DV |
11390 | else if (IS_VALLEYVIEW(dev)) |
11391 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
11392 | else if (IS_PINEVIEW(dev)) | |
11393 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
11394 | else | |
11395 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
11396 | ||
affa9354 | 11397 | if (HAS_DDI(dev)) { |
0e8ffe1b | 11398 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
4c6baa59 | 11399 | dev_priv->display.get_plane_config = ironlake_get_plane_config; |
09b4ddf9 | 11400 | dev_priv->display.crtc_mode_set = haswell_crtc_mode_set; |
4f771f10 PZ |
11401 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
11402 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
6441ab5f | 11403 | dev_priv->display.off = haswell_crtc_off; |
262ca2b0 MR |
11404 | dev_priv->display.update_primary_plane = |
11405 | ironlake_update_primary_plane; | |
09b4ddf9 | 11406 | } else if (HAS_PCH_SPLIT(dev)) { |
0e8ffe1b | 11407 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
4c6baa59 | 11408 | dev_priv->display.get_plane_config = ironlake_get_plane_config; |
f564048e | 11409 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
76e5a89c DV |
11410 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
11411 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
ee7b9f93 | 11412 | dev_priv->display.off = ironlake_crtc_off; |
262ca2b0 MR |
11413 | dev_priv->display.update_primary_plane = |
11414 | ironlake_update_primary_plane; | |
89b667f8 JB |
11415 | } else if (IS_VALLEYVIEW(dev)) { |
11416 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
1ad292b5 | 11417 | dev_priv->display.get_plane_config = i9xx_get_plane_config; |
89b667f8 JB |
11418 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
11419 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
11420 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
11421 | dev_priv->display.off = i9xx_crtc_off; | |
262ca2b0 MR |
11422 | dev_priv->display.update_primary_plane = |
11423 | i9xx_update_primary_plane; | |
f564048e | 11424 | } else { |
0e8ffe1b | 11425 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
1ad292b5 | 11426 | dev_priv->display.get_plane_config = i9xx_get_plane_config; |
f564048e | 11427 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
76e5a89c DV |
11428 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
11429 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
ee7b9f93 | 11430 | dev_priv->display.off = i9xx_crtc_off; |
262ca2b0 MR |
11431 | dev_priv->display.update_primary_plane = |
11432 | i9xx_update_primary_plane; | |
f564048e | 11433 | } |
e70236a8 | 11434 | |
e70236a8 | 11435 | /* Returns the core display clock speed */ |
25eb05fc JB |
11436 | if (IS_VALLEYVIEW(dev)) |
11437 | dev_priv->display.get_display_clock_speed = | |
11438 | valleyview_get_display_clock_speed; | |
11439 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) | |
e70236a8 JB |
11440 | dev_priv->display.get_display_clock_speed = |
11441 | i945_get_display_clock_speed; | |
11442 | else if (IS_I915G(dev)) | |
11443 | dev_priv->display.get_display_clock_speed = | |
11444 | i915_get_display_clock_speed; | |
257a7ffc | 11445 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
11446 | dev_priv->display.get_display_clock_speed = |
11447 | i9xx_misc_get_display_clock_speed; | |
257a7ffc DV |
11448 | else if (IS_PINEVIEW(dev)) |
11449 | dev_priv->display.get_display_clock_speed = | |
11450 | pnv_get_display_clock_speed; | |
e70236a8 JB |
11451 | else if (IS_I915GM(dev)) |
11452 | dev_priv->display.get_display_clock_speed = | |
11453 | i915gm_get_display_clock_speed; | |
11454 | else if (IS_I865G(dev)) | |
11455 | dev_priv->display.get_display_clock_speed = | |
11456 | i865_get_display_clock_speed; | |
f0f8a9ce | 11457 | else if (IS_I85X(dev)) |
e70236a8 JB |
11458 | dev_priv->display.get_display_clock_speed = |
11459 | i855_get_display_clock_speed; | |
11460 | else /* 852, 830 */ | |
11461 | dev_priv->display.get_display_clock_speed = | |
11462 | i830_get_display_clock_speed; | |
11463 | ||
7f8a8569 | 11464 | if (HAS_PCH_SPLIT(dev)) { |
f00a3ddf | 11465 | if (IS_GEN5(dev)) { |
674cf967 | 11466 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
e0dac65e | 11467 | dev_priv->display.write_eld = ironlake_write_eld; |
1398261a | 11468 | } else if (IS_GEN6(dev)) { |
674cf967 | 11469 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
e0dac65e | 11470 | dev_priv->display.write_eld = ironlake_write_eld; |
9a952a0d PZ |
11471 | dev_priv->display.modeset_global_resources = |
11472 | snb_modeset_global_resources; | |
357555c0 JB |
11473 | } else if (IS_IVYBRIDGE(dev)) { |
11474 | /* FIXME: detect B0+ stepping and use auto training */ | |
11475 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
e0dac65e | 11476 | dev_priv->display.write_eld = ironlake_write_eld; |
01a415fd DV |
11477 | dev_priv->display.modeset_global_resources = |
11478 | ivb_modeset_global_resources; | |
4e0bbc31 | 11479 | } else if (IS_HASWELL(dev) || IS_GEN8(dev)) { |
c82e4d26 | 11480 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
83358c85 | 11481 | dev_priv->display.write_eld = haswell_write_eld; |
d6dd9eb1 DV |
11482 | dev_priv->display.modeset_global_resources = |
11483 | haswell_modeset_global_resources; | |
a0e63c22 | 11484 | } |
6067aaea | 11485 | } else if (IS_G4X(dev)) { |
e0dac65e | 11486 | dev_priv->display.write_eld = g4x_write_eld; |
30a970c6 JB |
11487 | } else if (IS_VALLEYVIEW(dev)) { |
11488 | dev_priv->display.modeset_global_resources = | |
11489 | valleyview_modeset_global_resources; | |
9ca2fe73 | 11490 | dev_priv->display.write_eld = ironlake_write_eld; |
e70236a8 | 11491 | } |
8c9f3aaf JB |
11492 | |
11493 | /* Default just returns -ENODEV to indicate unsupported */ | |
11494 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
11495 | ||
11496 | switch (INTEL_INFO(dev)->gen) { | |
11497 | case 2: | |
11498 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
11499 | break; | |
11500 | ||
11501 | case 3: | |
11502 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
11503 | break; | |
11504 | ||
11505 | case 4: | |
11506 | case 5: | |
11507 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
11508 | break; | |
11509 | ||
11510 | case 6: | |
11511 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
11512 | break; | |
7c9017e5 | 11513 | case 7: |
4e0bbc31 | 11514 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
11515 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
11516 | break; | |
8c9f3aaf | 11517 | } |
7bd688cd JN |
11518 | |
11519 | intel_panel_init_backlight_funcs(dev); | |
e70236a8 JB |
11520 | } |
11521 | ||
b690e96c JB |
11522 | /* |
11523 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
11524 | * resume, or other times. This quirk makes sure that's the case for | |
11525 | * affected systems. | |
11526 | */ | |
0206e353 | 11527 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
11528 | { |
11529 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11530 | ||
11531 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 11532 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
11533 | } |
11534 | ||
435793df KP |
11535 | /* |
11536 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
11537 | */ | |
11538 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
11539 | { | |
11540 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11541 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 11542 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
11543 | } |
11544 | ||
4dca20ef | 11545 | /* |
5a15ab5b CE |
11546 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
11547 | * brightness value | |
4dca20ef CE |
11548 | */ |
11549 | static void quirk_invert_brightness(struct drm_device *dev) | |
11550 | { | |
11551 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11552 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 11553 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
11554 | } |
11555 | ||
b690e96c JB |
11556 | struct intel_quirk { |
11557 | int device; | |
11558 | int subsystem_vendor; | |
11559 | int subsystem_device; | |
11560 | void (*hook)(struct drm_device *dev); | |
11561 | }; | |
11562 | ||
5f85f176 EE |
11563 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
11564 | struct intel_dmi_quirk { | |
11565 | void (*hook)(struct drm_device *dev); | |
11566 | const struct dmi_system_id (*dmi_id_list)[]; | |
11567 | }; | |
11568 | ||
11569 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
11570 | { | |
11571 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
11572 | return 1; | |
11573 | } | |
11574 | ||
11575 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
11576 | { | |
11577 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
11578 | { | |
11579 | .callback = intel_dmi_reverse_brightness, | |
11580 | .ident = "NCR Corporation", | |
11581 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
11582 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
11583 | }, | |
11584 | }, | |
11585 | { } /* terminating entry */ | |
11586 | }, | |
11587 | .hook = quirk_invert_brightness, | |
11588 | }, | |
11589 | }; | |
11590 | ||
c43b5634 | 11591 | static struct intel_quirk intel_quirks[] = { |
b690e96c | 11592 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
0206e353 | 11593 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c | 11594 | |
b690e96c JB |
11595 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
11596 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
11597 | ||
b690e96c JB |
11598 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
11599 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
11600 | ||
a4945f95 | 11601 | /* 830 needs to leave pipe A & dpll A up */ |
dcdaed6e | 11602 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
435793df KP |
11603 | |
11604 | /* Lenovo U160 cannot use SSC on LVDS */ | |
11605 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
11606 | |
11607 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
11608 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 11609 | |
be505f64 AH |
11610 | /* Acer Aspire 5734Z must invert backlight brightness */ |
11611 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
11612 | ||
11613 | /* Acer/eMachines G725 */ | |
11614 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
11615 | ||
11616 | /* Acer/eMachines e725 */ | |
11617 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
11618 | ||
11619 | /* Acer/Packard Bell NCL20 */ | |
11620 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
11621 | ||
11622 | /* Acer Aspire 4736Z */ | |
11623 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
11624 | |
11625 | /* Acer Aspire 5336 */ | |
11626 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
b690e96c JB |
11627 | }; |
11628 | ||
11629 | static void intel_init_quirks(struct drm_device *dev) | |
11630 | { | |
11631 | struct pci_dev *d = dev->pdev; | |
11632 | int i; | |
11633 | ||
11634 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
11635 | struct intel_quirk *q = &intel_quirks[i]; | |
11636 | ||
11637 | if (d->device == q->device && | |
11638 | (d->subsystem_vendor == q->subsystem_vendor || | |
11639 | q->subsystem_vendor == PCI_ANY_ID) && | |
11640 | (d->subsystem_device == q->subsystem_device || | |
11641 | q->subsystem_device == PCI_ANY_ID)) | |
11642 | q->hook(dev); | |
11643 | } | |
5f85f176 EE |
11644 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
11645 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
11646 | intel_dmi_quirks[i].hook(dev); | |
11647 | } | |
b690e96c JB |
11648 | } |
11649 | ||
9cce37f4 JB |
11650 | /* Disable the VGA plane that we never use */ |
11651 | static void i915_disable_vga(struct drm_device *dev) | |
11652 | { | |
11653 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11654 | u8 sr1; | |
766aa1c4 | 11655 | u32 vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 11656 | |
2b37c616 | 11657 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 11658 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 11659 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
11660 | sr1 = inb(VGA_SR_DATA); |
11661 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
11662 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
11663 | udelay(300); | |
11664 | ||
11665 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); | |
11666 | POSTING_READ(vga_reg); | |
11667 | } | |
11668 | ||
f817586c DV |
11669 | void intel_modeset_init_hw(struct drm_device *dev) |
11670 | { | |
a8f78b58 ED |
11671 | intel_prepare_ddi(dev); |
11672 | ||
f817586c DV |
11673 | intel_init_clock_gating(dev); |
11674 | ||
5382f5f3 | 11675 | intel_reset_dpio(dev); |
40e9cf64 | 11676 | |
8090c6b9 | 11677 | intel_enable_gt_powersave(dev); |
f817586c DV |
11678 | } |
11679 | ||
7d708ee4 ID |
11680 | void intel_modeset_suspend_hw(struct drm_device *dev) |
11681 | { | |
11682 | intel_suspend_hw(dev); | |
11683 | } | |
11684 | ||
79e53945 JB |
11685 | void intel_modeset_init(struct drm_device *dev) |
11686 | { | |
652c393a | 11687 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 11688 | int sprite, ret; |
8cc87b75 | 11689 | enum pipe pipe; |
46f297fb | 11690 | struct intel_crtc *crtc; |
79e53945 JB |
11691 | |
11692 | drm_mode_config_init(dev); | |
11693 | ||
11694 | dev->mode_config.min_width = 0; | |
11695 | dev->mode_config.min_height = 0; | |
11696 | ||
019d96cb DA |
11697 | dev->mode_config.preferred_depth = 24; |
11698 | dev->mode_config.prefer_shadow = 1; | |
11699 | ||
e6ecefaa | 11700 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 11701 | |
b690e96c JB |
11702 | intel_init_quirks(dev); |
11703 | ||
1fa61106 ED |
11704 | intel_init_pm(dev); |
11705 | ||
e3c74757 BW |
11706 | if (INTEL_INFO(dev)->num_pipes == 0) |
11707 | return; | |
11708 | ||
e70236a8 JB |
11709 | intel_init_display(dev); |
11710 | ||
a6c45cf0 CW |
11711 | if (IS_GEN2(dev)) { |
11712 | dev->mode_config.max_width = 2048; | |
11713 | dev->mode_config.max_height = 2048; | |
11714 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
11715 | dev->mode_config.max_width = 4096; |
11716 | dev->mode_config.max_height = 4096; | |
79e53945 | 11717 | } else { |
a6c45cf0 CW |
11718 | dev->mode_config.max_width = 8192; |
11719 | dev->mode_config.max_height = 8192; | |
79e53945 | 11720 | } |
068be561 DL |
11721 | |
11722 | if (IS_GEN2(dev)) { | |
11723 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; | |
11724 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
11725 | } else { | |
11726 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
11727 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
11728 | } | |
11729 | ||
5d4545ae | 11730 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 11731 | |
28c97730 | 11732 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
11733 | INTEL_INFO(dev)->num_pipes, |
11734 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 11735 | |
8cc87b75 DL |
11736 | for_each_pipe(pipe) { |
11737 | intel_crtc_init(dev, pipe); | |
1fe47785 DL |
11738 | for_each_sprite(pipe, sprite) { |
11739 | ret = intel_plane_init(dev, pipe, sprite); | |
7f1f3851 | 11740 | if (ret) |
06da8da2 | 11741 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 11742 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 11743 | } |
79e53945 JB |
11744 | } |
11745 | ||
f42bb70d | 11746 | intel_init_dpio(dev); |
5382f5f3 | 11747 | intel_reset_dpio(dev); |
f42bb70d | 11748 | |
79f689aa | 11749 | intel_cpu_pll_init(dev); |
e72f9fbf | 11750 | intel_shared_dpll_init(dev); |
ee7b9f93 | 11751 | |
9cce37f4 JB |
11752 | /* Just disable it once at startup */ |
11753 | i915_disable_vga(dev); | |
79e53945 | 11754 | intel_setup_outputs(dev); |
11be49eb CW |
11755 | |
11756 | /* Just in case the BIOS is doing something questionable. */ | |
11757 | intel_disable_fbc(dev); | |
fa9fa083 | 11758 | |
8b687df4 | 11759 | mutex_lock(&dev->mode_config.mutex); |
fa9fa083 | 11760 | intel_modeset_setup_hw_state(dev, false); |
8b687df4 | 11761 | mutex_unlock(&dev->mode_config.mutex); |
46f297fb | 11762 | |
d3fcc808 | 11763 | for_each_intel_crtc(dev, crtc) { |
46f297fb JB |
11764 | if (!crtc->active) |
11765 | continue; | |
11766 | ||
46f297fb | 11767 | /* |
46f297fb JB |
11768 | * Note that reserving the BIOS fb up front prevents us |
11769 | * from stuffing other stolen allocations like the ring | |
11770 | * on top. This prevents some ugliness at boot time, and | |
11771 | * can even allow for smooth boot transitions if the BIOS | |
11772 | * fb is large enough for the active pipe configuration. | |
11773 | */ | |
11774 | if (dev_priv->display.get_plane_config) { | |
11775 | dev_priv->display.get_plane_config(crtc, | |
11776 | &crtc->plane_config); | |
11777 | /* | |
11778 | * If the fb is shared between multiple heads, we'll | |
11779 | * just get the first one. | |
11780 | */ | |
484b41dd | 11781 | intel_find_plane_obj(crtc, &crtc->plane_config); |
46f297fb | 11782 | } |
46f297fb | 11783 | } |
2c7111db CW |
11784 | } |
11785 | ||
24929352 DV |
11786 | static void |
11787 | intel_connector_break_all_links(struct intel_connector *connector) | |
11788 | { | |
11789 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
11790 | connector->base.encoder = NULL; | |
11791 | connector->encoder->connectors_active = false; | |
11792 | connector->encoder->base.crtc = NULL; | |
11793 | } | |
11794 | ||
7fad798e DV |
11795 | static void intel_enable_pipe_a(struct drm_device *dev) |
11796 | { | |
11797 | struct intel_connector *connector; | |
11798 | struct drm_connector *crt = NULL; | |
11799 | struct intel_load_detect_pipe load_detect_temp; | |
11800 | ||
11801 | /* We can't just switch on the pipe A, we need to set things up with a | |
11802 | * proper mode and output configuration. As a gross hack, enable pipe A | |
11803 | * by enabling the load detect pipe once. */ | |
11804 | list_for_each_entry(connector, | |
11805 | &dev->mode_config.connector_list, | |
11806 | base.head) { | |
11807 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { | |
11808 | crt = &connector->base; | |
11809 | break; | |
11810 | } | |
11811 | } | |
11812 | ||
11813 | if (!crt) | |
11814 | return; | |
11815 | ||
11816 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp)) | |
11817 | intel_release_load_detect_pipe(crt, &load_detect_temp); | |
11818 | ||
652c393a | 11819 | |
7fad798e DV |
11820 | } |
11821 | ||
fa555837 DV |
11822 | static bool |
11823 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
11824 | { | |
7eb552ae BW |
11825 | struct drm_device *dev = crtc->base.dev; |
11826 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 DV |
11827 | u32 reg, val; |
11828 | ||
7eb552ae | 11829 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
11830 | return true; |
11831 | ||
11832 | reg = DSPCNTR(!crtc->plane); | |
11833 | val = I915_READ(reg); | |
11834 | ||
11835 | if ((val & DISPLAY_PLANE_ENABLE) && | |
11836 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
11837 | return false; | |
11838 | ||
11839 | return true; | |
11840 | } | |
11841 | ||
24929352 DV |
11842 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
11843 | { | |
11844 | struct drm_device *dev = crtc->base.dev; | |
11845 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 | 11846 | u32 reg; |
24929352 | 11847 | |
24929352 | 11848 | /* Clear any frame start delays used for debugging left by the BIOS */ |
3b117c8f | 11849 | reg = PIPECONF(crtc->config.cpu_transcoder); |
24929352 DV |
11850 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
11851 | ||
d3eaf884 VS |
11852 | /* restore vblank interrupts to correct state */ |
11853 | if (crtc->active) | |
11854 | drm_vblank_on(dev, crtc->pipe); | |
11855 | else | |
11856 | drm_vblank_off(dev, crtc->pipe); | |
11857 | ||
24929352 | 11858 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
11859 | * disable the crtc (and hence change the state) if it is wrong. Note |
11860 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
11861 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
11862 | struct intel_connector *connector; |
11863 | bool plane; | |
11864 | ||
24929352 DV |
11865 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
11866 | crtc->base.base.id); | |
11867 | ||
11868 | /* Pipe has the wrong plane attached and the plane is active. | |
11869 | * Temporarily change the plane mapping and disable everything | |
11870 | * ... */ | |
11871 | plane = crtc->plane; | |
11872 | crtc->plane = !plane; | |
11873 | dev_priv->display.crtc_disable(&crtc->base); | |
11874 | crtc->plane = plane; | |
11875 | ||
11876 | /* ... and break all links. */ | |
11877 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
11878 | base.head) { | |
11879 | if (connector->encoder->base.crtc != &crtc->base) | |
11880 | continue; | |
11881 | ||
11882 | intel_connector_break_all_links(connector); | |
11883 | } | |
11884 | ||
11885 | WARN_ON(crtc->active); | |
11886 | crtc->base.enabled = false; | |
11887 | } | |
24929352 | 11888 | |
7fad798e DV |
11889 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
11890 | crtc->pipe == PIPE_A && !crtc->active) { | |
11891 | /* BIOS forgot to enable pipe A, this mostly happens after | |
11892 | * resume. Force-enable the pipe to fix this, the update_dpms | |
11893 | * call below we restore the pipe to the right state, but leave | |
11894 | * the required bits on. */ | |
11895 | intel_enable_pipe_a(dev); | |
11896 | } | |
11897 | ||
24929352 DV |
11898 | /* Adjust the state of the output pipe according to whether we |
11899 | * have active connectors/encoders. */ | |
11900 | intel_crtc_update_dpms(&crtc->base); | |
11901 | ||
11902 | if (crtc->active != crtc->base.enabled) { | |
11903 | struct intel_encoder *encoder; | |
11904 | ||
11905 | /* This can happen either due to bugs in the get_hw_state | |
11906 | * functions or because the pipe is force-enabled due to the | |
11907 | * pipe A quirk. */ | |
11908 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
11909 | crtc->base.base.id, | |
11910 | crtc->base.enabled ? "enabled" : "disabled", | |
11911 | crtc->active ? "enabled" : "disabled"); | |
11912 | ||
11913 | crtc->base.enabled = crtc->active; | |
11914 | ||
11915 | /* Because we only establish the connector -> encoder -> | |
11916 | * crtc links if something is active, this means the | |
11917 | * crtc is now deactivated. Break the links. connector | |
11918 | * -> encoder links are only establish when things are | |
11919 | * actually up, hence no need to break them. */ | |
11920 | WARN_ON(crtc->active); | |
11921 | ||
11922 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { | |
11923 | WARN_ON(encoder->connectors_active); | |
11924 | encoder->base.crtc = NULL; | |
11925 | } | |
11926 | } | |
c5ab3bc0 DV |
11927 | |
11928 | if (crtc->active || IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen < 5) { | |
4cc31489 DV |
11929 | /* |
11930 | * We start out with underrun reporting disabled to avoid races. | |
11931 | * For correct bookkeeping mark this on active crtcs. | |
11932 | * | |
c5ab3bc0 DV |
11933 | * Also on gmch platforms we dont have any hardware bits to |
11934 | * disable the underrun reporting. Which means we need to start | |
11935 | * out with underrun reporting disabled also on inactive pipes, | |
11936 | * since otherwise we'll complain about the garbage we read when | |
11937 | * e.g. coming up after runtime pm. | |
11938 | * | |
4cc31489 DV |
11939 | * No protection against concurrent access is required - at |
11940 | * worst a fifo underrun happens which also sets this to false. | |
11941 | */ | |
11942 | crtc->cpu_fifo_underrun_disabled = true; | |
11943 | crtc->pch_fifo_underrun_disabled = true; | |
80715b2f VS |
11944 | |
11945 | update_scanline_offset(crtc); | |
4cc31489 | 11946 | } |
24929352 DV |
11947 | } |
11948 | ||
11949 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
11950 | { | |
11951 | struct intel_connector *connector; | |
11952 | struct drm_device *dev = encoder->base.dev; | |
11953 | ||
11954 | /* We need to check both for a crtc link (meaning that the | |
11955 | * encoder is active and trying to read from a pipe) and the | |
11956 | * pipe itself being active. */ | |
11957 | bool has_active_crtc = encoder->base.crtc && | |
11958 | to_intel_crtc(encoder->base.crtc)->active; | |
11959 | ||
11960 | if (encoder->connectors_active && !has_active_crtc) { | |
11961 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
11962 | encoder->base.base.id, | |
11963 | drm_get_encoder_name(&encoder->base)); | |
11964 | ||
11965 | /* Connector is active, but has no active pipe. This is | |
11966 | * fallout from our resume register restoring. Disable | |
11967 | * the encoder manually again. */ | |
11968 | if (encoder->base.crtc) { | |
11969 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
11970 | encoder->base.base.id, | |
11971 | drm_get_encoder_name(&encoder->base)); | |
11972 | encoder->disable(encoder); | |
11973 | } | |
11974 | ||
11975 | /* Inconsistent output/port/pipe state happens presumably due to | |
11976 | * a bug in one of the get_hw_state functions. Or someplace else | |
11977 | * in our code, like the register restore mess on resume. Clamp | |
11978 | * things to off as a safer default. */ | |
11979 | list_for_each_entry(connector, | |
11980 | &dev->mode_config.connector_list, | |
11981 | base.head) { | |
11982 | if (connector->encoder != encoder) | |
11983 | continue; | |
11984 | ||
11985 | intel_connector_break_all_links(connector); | |
11986 | } | |
11987 | } | |
11988 | /* Enabled encoders without active connectors will be fixed in | |
11989 | * the crtc fixup. */ | |
11990 | } | |
11991 | ||
04098753 | 11992 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
11993 | { |
11994 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766aa1c4 | 11995 | u32 vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 11996 | |
04098753 ID |
11997 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
11998 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
11999 | i915_disable_vga(dev); | |
12000 | } | |
12001 | } | |
12002 | ||
12003 | void i915_redisable_vga(struct drm_device *dev) | |
12004 | { | |
12005 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12006 | ||
8dc8a27c PZ |
12007 | /* This function can be called both from intel_modeset_setup_hw_state or |
12008 | * at a very early point in our resume sequence, where the power well | |
12009 | * structures are not yet restored. Since this function is at a very | |
12010 | * paranoid "someone might have enabled VGA while we were not looking" | |
12011 | * level, just check if the power well is enabled instead of trying to | |
12012 | * follow the "don't touch the power well if we don't need it" policy | |
12013 | * the rest of the driver uses. */ | |
04098753 | 12014 | if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
12015 | return; |
12016 | ||
04098753 | 12017 | i915_redisable_vga_power_on(dev); |
0fde901f KM |
12018 | } |
12019 | ||
98ec7739 VS |
12020 | static bool primary_get_hw_state(struct intel_crtc *crtc) |
12021 | { | |
12022 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
12023 | ||
12024 | if (!crtc->active) | |
12025 | return false; | |
12026 | ||
12027 | return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE; | |
12028 | } | |
12029 | ||
30e984df | 12030 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
12031 | { |
12032 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12033 | enum pipe pipe; | |
24929352 DV |
12034 | struct intel_crtc *crtc; |
12035 | struct intel_encoder *encoder; | |
12036 | struct intel_connector *connector; | |
5358901f | 12037 | int i; |
24929352 | 12038 | |
d3fcc808 | 12039 | for_each_intel_crtc(dev, crtc) { |
88adfff1 | 12040 | memset(&crtc->config, 0, sizeof(crtc->config)); |
3b117c8f | 12041 | |
9953599b DV |
12042 | crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE; |
12043 | ||
0e8ffe1b DV |
12044 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
12045 | &crtc->config); | |
24929352 DV |
12046 | |
12047 | crtc->base.enabled = crtc->active; | |
98ec7739 | 12048 | crtc->primary_enabled = primary_get_hw_state(crtc); |
24929352 DV |
12049 | |
12050 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
12051 | crtc->base.base.id, | |
12052 | crtc->active ? "enabled" : "disabled"); | |
12053 | } | |
12054 | ||
5358901f | 12055 | /* FIXME: Smash this into the new shared dpll infrastructure. */ |
affa9354 | 12056 | if (HAS_DDI(dev)) |
6441ab5f PZ |
12057 | intel_ddi_setup_hw_pll_state(dev); |
12058 | ||
5358901f DV |
12059 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
12060 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
12061 | ||
12062 | pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state); | |
12063 | pll->active = 0; | |
d3fcc808 | 12064 | for_each_intel_crtc(dev, crtc) { |
5358901f DV |
12065 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) |
12066 | pll->active++; | |
12067 | } | |
12068 | pll->refcount = pll->active; | |
12069 | ||
35c95375 DV |
12070 | DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n", |
12071 | pll->name, pll->refcount, pll->on); | |
5358901f DV |
12072 | } |
12073 | ||
24929352 DV |
12074 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
12075 | base.head) { | |
12076 | pipe = 0; | |
12077 | ||
12078 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
12079 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
12080 | encoder->base.crtc = &crtc->base; | |
1d37b689 | 12081 | encoder->get_config(encoder, &crtc->config); |
24929352 DV |
12082 | } else { |
12083 | encoder->base.crtc = NULL; | |
12084 | } | |
12085 | ||
12086 | encoder->connectors_active = false; | |
6f2bcceb | 12087 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 DV |
12088 | encoder->base.base.id, |
12089 | drm_get_encoder_name(&encoder->base), | |
12090 | encoder->base.crtc ? "enabled" : "disabled", | |
6f2bcceb | 12091 | pipe_name(pipe)); |
24929352 DV |
12092 | } |
12093 | ||
12094 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
12095 | base.head) { | |
12096 | if (connector->get_hw_state(connector)) { | |
12097 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
12098 | connector->encoder->connectors_active = true; | |
12099 | connector->base.encoder = &connector->encoder->base; | |
12100 | } else { | |
12101 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
12102 | connector->base.encoder = NULL; | |
12103 | } | |
12104 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
12105 | connector->base.base.id, | |
12106 | drm_get_connector_name(&connector->base), | |
12107 | connector->base.encoder ? "enabled" : "disabled"); | |
12108 | } | |
30e984df DV |
12109 | } |
12110 | ||
12111 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm | |
12112 | * and i915 state tracking structures. */ | |
12113 | void intel_modeset_setup_hw_state(struct drm_device *dev, | |
12114 | bool force_restore) | |
12115 | { | |
12116 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12117 | enum pipe pipe; | |
30e984df DV |
12118 | struct intel_crtc *crtc; |
12119 | struct intel_encoder *encoder; | |
35c95375 | 12120 | int i; |
30e984df DV |
12121 | |
12122 | intel_modeset_readout_hw_state(dev); | |
24929352 | 12123 | |
babea61d JB |
12124 | /* |
12125 | * Now that we have the config, copy it to each CRTC struct | |
12126 | * Note that this could go away if we move to using crtc_config | |
12127 | * checking everywhere. | |
12128 | */ | |
d3fcc808 | 12129 | for_each_intel_crtc(dev, crtc) { |
d330a953 | 12130 | if (crtc->active && i915.fastboot) { |
f6a83288 | 12131 | intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config); |
babea61d JB |
12132 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", |
12133 | crtc->base.base.id); | |
12134 | drm_mode_debug_printmodeline(&crtc->base.mode); | |
12135 | } | |
12136 | } | |
12137 | ||
24929352 DV |
12138 | /* HW state is read out, now we need to sanitize this mess. */ |
12139 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
12140 | base.head) { | |
12141 | intel_sanitize_encoder(encoder); | |
12142 | } | |
12143 | ||
12144 | for_each_pipe(pipe) { | |
12145 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
12146 | intel_sanitize_crtc(crtc); | |
c0b03411 | 12147 | intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]"); |
24929352 | 12148 | } |
9a935856 | 12149 | |
35c95375 DV |
12150 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
12151 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
12152 | ||
12153 | if (!pll->on || pll->active) | |
12154 | continue; | |
12155 | ||
12156 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
12157 | ||
12158 | pll->disable(dev_priv, pll); | |
12159 | pll->on = false; | |
12160 | } | |
12161 | ||
96f90c54 | 12162 | if (HAS_PCH_SPLIT(dev)) |
243e6a44 VS |
12163 | ilk_wm_get_hw_state(dev); |
12164 | ||
45e2b5f6 | 12165 | if (force_restore) { |
7d0bc1ea VS |
12166 | i915_redisable_vga(dev); |
12167 | ||
f30da187 DV |
12168 | /* |
12169 | * We need to use raw interfaces for restoring state to avoid | |
12170 | * checking (bogus) intermediate states. | |
12171 | */ | |
45e2b5f6 | 12172 | for_each_pipe(pipe) { |
b5644d05 JB |
12173 | struct drm_crtc *crtc = |
12174 | dev_priv->pipe_to_crtc_mapping[pipe]; | |
f30da187 DV |
12175 | |
12176 | __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, | |
f4510a27 | 12177 | crtc->primary->fb); |
45e2b5f6 DV |
12178 | } |
12179 | } else { | |
12180 | intel_modeset_update_staged_output_state(dev); | |
12181 | } | |
8af6cf88 DV |
12182 | |
12183 | intel_modeset_check_state(dev); | |
2c7111db CW |
12184 | } |
12185 | ||
12186 | void intel_modeset_gem_init(struct drm_device *dev) | |
12187 | { | |
484b41dd JB |
12188 | struct drm_crtc *c; |
12189 | struct intel_framebuffer *fb; | |
12190 | ||
ae48434c ID |
12191 | mutex_lock(&dev->struct_mutex); |
12192 | intel_init_gt_powersave(dev); | |
12193 | mutex_unlock(&dev->struct_mutex); | |
12194 | ||
1833b134 | 12195 | intel_modeset_init_hw(dev); |
02e792fb DV |
12196 | |
12197 | intel_setup_overlay(dev); | |
484b41dd JB |
12198 | |
12199 | /* | |
12200 | * Make sure any fbs we allocated at startup are properly | |
12201 | * pinned & fenced. When we do the allocation it's too early | |
12202 | * for this. | |
12203 | */ | |
12204 | mutex_lock(&dev->struct_mutex); | |
70e1e0ec | 12205 | for_each_crtc(dev, c) { |
66e514c1 | 12206 | if (!c->primary->fb) |
484b41dd JB |
12207 | continue; |
12208 | ||
66e514c1 | 12209 | fb = to_intel_framebuffer(c->primary->fb); |
484b41dd JB |
12210 | if (intel_pin_and_fence_fb_obj(dev, fb->obj, NULL)) { |
12211 | DRM_ERROR("failed to pin boot fb on pipe %d\n", | |
12212 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
12213 | drm_framebuffer_unreference(c->primary->fb); |
12214 | c->primary->fb = NULL; | |
484b41dd JB |
12215 | } |
12216 | } | |
12217 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
12218 | } |
12219 | ||
4932e2c3 ID |
12220 | void intel_connector_unregister(struct intel_connector *intel_connector) |
12221 | { | |
12222 | struct drm_connector *connector = &intel_connector->base; | |
12223 | ||
12224 | intel_panel_destroy_backlight(connector); | |
12225 | drm_sysfs_connector_remove(connector); | |
12226 | } | |
12227 | ||
79e53945 JB |
12228 | void intel_modeset_cleanup(struct drm_device *dev) |
12229 | { | |
652c393a JB |
12230 | struct drm_i915_private *dev_priv = dev->dev_private; |
12231 | struct drm_crtc *crtc; | |
d9255d57 | 12232 | struct drm_connector *connector; |
652c393a | 12233 | |
fd0c0642 DV |
12234 | /* |
12235 | * Interrupts and polling as the first thing to avoid creating havoc. | |
12236 | * Too much stuff here (turning of rps, connectors, ...) would | |
12237 | * experience fancy races otherwise. | |
12238 | */ | |
12239 | drm_irq_uninstall(dev); | |
12240 | cancel_work_sync(&dev_priv->hotplug_work); | |
12241 | /* | |
12242 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
12243 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
12244 | */ | |
f87ea761 | 12245 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 12246 | |
652c393a JB |
12247 | mutex_lock(&dev->struct_mutex); |
12248 | ||
723bfd70 JB |
12249 | intel_unregister_dsm_handler(); |
12250 | ||
70e1e0ec | 12251 | for_each_crtc(dev, crtc) { |
652c393a | 12252 | /* Skip inactive CRTCs */ |
f4510a27 | 12253 | if (!crtc->primary->fb) |
652c393a JB |
12254 | continue; |
12255 | ||
3dec0095 | 12256 | intel_increase_pllclock(crtc); |
652c393a JB |
12257 | } |
12258 | ||
973d04f9 | 12259 | intel_disable_fbc(dev); |
e70236a8 | 12260 | |
8090c6b9 | 12261 | intel_disable_gt_powersave(dev); |
0cdab21f | 12262 | |
930ebb46 DV |
12263 | ironlake_teardown_rc6(dev); |
12264 | ||
69341a5e KH |
12265 | mutex_unlock(&dev->struct_mutex); |
12266 | ||
1630fe75 CW |
12267 | /* flush any delayed tasks or pending work */ |
12268 | flush_scheduled_work(); | |
12269 | ||
db31af1d JN |
12270 | /* destroy the backlight and sysfs files before encoders/connectors */ |
12271 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4932e2c3 ID |
12272 | struct intel_connector *intel_connector; |
12273 | ||
12274 | intel_connector = to_intel_connector(connector); | |
12275 | intel_connector->unregister(intel_connector); | |
db31af1d | 12276 | } |
d9255d57 | 12277 | |
79e53945 | 12278 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
12279 | |
12280 | intel_cleanup_overlay(dev); | |
ae48434c ID |
12281 | |
12282 | mutex_lock(&dev->struct_mutex); | |
12283 | intel_cleanup_gt_powersave(dev); | |
12284 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
12285 | } |
12286 | ||
f1c79df3 ZW |
12287 | /* |
12288 | * Return which encoder is currently attached for connector. | |
12289 | */ | |
df0e9248 | 12290 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 12291 | { |
df0e9248 CW |
12292 | return &intel_attached_encoder(connector)->base; |
12293 | } | |
f1c79df3 | 12294 | |
df0e9248 CW |
12295 | void intel_connector_attach_encoder(struct intel_connector *connector, |
12296 | struct intel_encoder *encoder) | |
12297 | { | |
12298 | connector->encoder = encoder; | |
12299 | drm_mode_connector_attach_encoder(&connector->base, | |
12300 | &encoder->base); | |
79e53945 | 12301 | } |
28d52043 DA |
12302 | |
12303 | /* | |
12304 | * set vga decode state - true == enable VGA decode | |
12305 | */ | |
12306 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
12307 | { | |
12308 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 12309 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
12310 | u16 gmch_ctrl; |
12311 | ||
75fa041d CW |
12312 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
12313 | DRM_ERROR("failed to read control word\n"); | |
12314 | return -EIO; | |
12315 | } | |
12316 | ||
c0cc8a55 CW |
12317 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
12318 | return 0; | |
12319 | ||
28d52043 DA |
12320 | if (state) |
12321 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
12322 | else | |
12323 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
12324 | |
12325 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
12326 | DRM_ERROR("failed to write control word\n"); | |
12327 | return -EIO; | |
12328 | } | |
12329 | ||
28d52043 DA |
12330 | return 0; |
12331 | } | |
c4a1d9e4 | 12332 | |
c4a1d9e4 | 12333 | struct intel_display_error_state { |
ff57f1b0 PZ |
12334 | |
12335 | u32 power_well_driver; | |
12336 | ||
63b66e5b CW |
12337 | int num_transcoders; |
12338 | ||
c4a1d9e4 CW |
12339 | struct intel_cursor_error_state { |
12340 | u32 control; | |
12341 | u32 position; | |
12342 | u32 base; | |
12343 | u32 size; | |
52331309 | 12344 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
12345 | |
12346 | struct intel_pipe_error_state { | |
ddf9c536 | 12347 | bool power_domain_on; |
c4a1d9e4 | 12348 | u32 source; |
f301b1e1 | 12349 | u32 stat; |
52331309 | 12350 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
12351 | |
12352 | struct intel_plane_error_state { | |
12353 | u32 control; | |
12354 | u32 stride; | |
12355 | u32 size; | |
12356 | u32 pos; | |
12357 | u32 addr; | |
12358 | u32 surface; | |
12359 | u32 tile_offset; | |
52331309 | 12360 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
12361 | |
12362 | struct intel_transcoder_error_state { | |
ddf9c536 | 12363 | bool power_domain_on; |
63b66e5b CW |
12364 | enum transcoder cpu_transcoder; |
12365 | ||
12366 | u32 conf; | |
12367 | ||
12368 | u32 htotal; | |
12369 | u32 hblank; | |
12370 | u32 hsync; | |
12371 | u32 vtotal; | |
12372 | u32 vblank; | |
12373 | u32 vsync; | |
12374 | } transcoder[4]; | |
c4a1d9e4 CW |
12375 | }; |
12376 | ||
12377 | struct intel_display_error_state * | |
12378 | intel_display_capture_error_state(struct drm_device *dev) | |
12379 | { | |
fbee40df | 12380 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 12381 | struct intel_display_error_state *error; |
63b66e5b CW |
12382 | int transcoders[] = { |
12383 | TRANSCODER_A, | |
12384 | TRANSCODER_B, | |
12385 | TRANSCODER_C, | |
12386 | TRANSCODER_EDP, | |
12387 | }; | |
c4a1d9e4 CW |
12388 | int i; |
12389 | ||
63b66e5b CW |
12390 | if (INTEL_INFO(dev)->num_pipes == 0) |
12391 | return NULL; | |
12392 | ||
9d1cb914 | 12393 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
12394 | if (error == NULL) |
12395 | return NULL; | |
12396 | ||
190be112 | 12397 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
12398 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
12399 | ||
52331309 | 12400 | for_each_pipe(i) { |
ddf9c536 | 12401 | error->pipe[i].power_domain_on = |
da7e29bd ID |
12402 | intel_display_power_enabled_sw(dev_priv, |
12403 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 12404 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
12405 | continue; |
12406 | ||
5efb3e28 VS |
12407 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
12408 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
12409 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
12410 | |
12411 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
12412 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 12413 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 12414 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
12415 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
12416 | } | |
ca291363 PZ |
12417 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
12418 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
12419 | if (INTEL_INFO(dev)->gen >= 4) { |
12420 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
12421 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
12422 | } | |
12423 | ||
c4a1d9e4 | 12424 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 ID |
12425 | |
12426 | if (!HAS_PCH_SPLIT(dev)) | |
12427 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); | |
63b66e5b CW |
12428 | } |
12429 | ||
12430 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
12431 | if (HAS_DDI(dev_priv->dev)) | |
12432 | error->num_transcoders++; /* Account for eDP. */ | |
12433 | ||
12434 | for (i = 0; i < error->num_transcoders; i++) { | |
12435 | enum transcoder cpu_transcoder = transcoders[i]; | |
12436 | ||
ddf9c536 | 12437 | error->transcoder[i].power_domain_on = |
da7e29bd | 12438 | intel_display_power_enabled_sw(dev_priv, |
38cc1daf | 12439 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 12440 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
12441 | continue; |
12442 | ||
63b66e5b CW |
12443 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
12444 | ||
12445 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
12446 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
12447 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
12448 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
12449 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
12450 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
12451 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
12452 | } |
12453 | ||
12454 | return error; | |
12455 | } | |
12456 | ||
edc3d884 MK |
12457 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
12458 | ||
c4a1d9e4 | 12459 | void |
edc3d884 | 12460 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
12461 | struct drm_device *dev, |
12462 | struct intel_display_error_state *error) | |
12463 | { | |
12464 | int i; | |
12465 | ||
63b66e5b CW |
12466 | if (!error) |
12467 | return; | |
12468 | ||
edc3d884 | 12469 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 12470 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 12471 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 12472 | error->power_well_driver); |
52331309 | 12473 | for_each_pipe(i) { |
edc3d884 | 12474 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 ID |
12475 | err_printf(m, " Power: %s\n", |
12476 | error->pipe[i].power_domain_on ? "on" : "off"); | |
edc3d884 | 12477 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 12478 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
12479 | |
12480 | err_printf(m, "Plane [%d]:\n", i); | |
12481 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
12482 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 12483 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
12484 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
12485 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 12486 | } |
4b71a570 | 12487 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 12488 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 12489 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
12490 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
12491 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
12492 | } |
12493 | ||
edc3d884 MK |
12494 | err_printf(m, "Cursor [%d]:\n", i); |
12495 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
12496 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
12497 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 12498 | } |
63b66e5b CW |
12499 | |
12500 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 12501 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 12502 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 ID |
12503 | err_printf(m, " Power: %s\n", |
12504 | error->transcoder[i].power_domain_on ? "on" : "off"); | |
63b66e5b CW |
12505 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
12506 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
12507 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
12508 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
12509 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
12510 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
12511 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
12512 | } | |
c4a1d9e4 | 12513 | } |