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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
760285e7 DH |
40 | #include <drm/drm_dp_helper.h> |
41 | #include <drm/drm_crtc_helper.h> | |
c0f372b3 | 42 | #include <linux/dma_remapping.h> |
79e53945 | 43 | |
3dec0095 | 44 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
6b383a7f | 45 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 46 | |
f1f644dc JB |
47 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
48 | struct intel_crtc_config *pipe_config); | |
18442d08 VS |
49 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
50 | struct intel_crtc_config *pipe_config); | |
f1f644dc | 51 | |
e7457a9a DL |
52 | static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
53 | int x, int y, struct drm_framebuffer *old_fb); | |
54 | ||
55 | ||
79e53945 | 56 | typedef struct { |
0206e353 | 57 | int min, max; |
79e53945 JB |
58 | } intel_range_t; |
59 | ||
60 | typedef struct { | |
0206e353 AJ |
61 | int dot_limit; |
62 | int p2_slow, p2_fast; | |
79e53945 JB |
63 | } intel_p2_t; |
64 | ||
d4906093 ML |
65 | typedef struct intel_limit intel_limit_t; |
66 | struct intel_limit { | |
0206e353 AJ |
67 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
68 | intel_p2_t p2; | |
d4906093 | 69 | }; |
79e53945 | 70 | |
d2acd215 DV |
71 | int |
72 | intel_pch_rawclk(struct drm_device *dev) | |
73 | { | |
74 | struct drm_i915_private *dev_priv = dev->dev_private; | |
75 | ||
76 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
77 | ||
78 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
79 | } | |
80 | ||
021357ac CW |
81 | static inline u32 /* units of 100MHz */ |
82 | intel_fdi_link_freq(struct drm_device *dev) | |
83 | { | |
8b99e68c CW |
84 | if (IS_GEN5(dev)) { |
85 | struct drm_i915_private *dev_priv = dev->dev_private; | |
86 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
87 | } else | |
88 | return 27; | |
021357ac CW |
89 | } |
90 | ||
5d536e28 | 91 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 92 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 93 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 94 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
95 | .m = { .min = 96, .max = 140 }, |
96 | .m1 = { .min = 18, .max = 26 }, | |
97 | .m2 = { .min = 6, .max = 16 }, | |
98 | .p = { .min = 4, .max = 128 }, | |
99 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
100 | .p2 = { .dot_limit = 165000, |
101 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
102 | }; |
103 | ||
5d536e28 DV |
104 | static const intel_limit_t intel_limits_i8xx_dvo = { |
105 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 106 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 107 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
108 | .m = { .min = 96, .max = 140 }, |
109 | .m1 = { .min = 18, .max = 26 }, | |
110 | .m2 = { .min = 6, .max = 16 }, | |
111 | .p = { .min = 4, .max = 128 }, | |
112 | .p1 = { .min = 2, .max = 33 }, | |
113 | .p2 = { .dot_limit = 165000, | |
114 | .p2_slow = 4, .p2_fast = 4 }, | |
115 | }; | |
116 | ||
e4b36699 | 117 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 118 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 119 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 120 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
121 | .m = { .min = 96, .max = 140 }, |
122 | .m1 = { .min = 18, .max = 26 }, | |
123 | .m2 = { .min = 6, .max = 16 }, | |
124 | .p = { .min = 4, .max = 128 }, | |
125 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
126 | .p2 = { .dot_limit = 165000, |
127 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 128 | }; |
273e27ca | 129 | |
e4b36699 | 130 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
131 | .dot = { .min = 20000, .max = 400000 }, |
132 | .vco = { .min = 1400000, .max = 2800000 }, | |
133 | .n = { .min = 1, .max = 6 }, | |
134 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
135 | .m1 = { .min = 8, .max = 18 }, |
136 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
137 | .p = { .min = 5, .max = 80 }, |
138 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
139 | .p2 = { .dot_limit = 200000, |
140 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
141 | }; |
142 | ||
143 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
144 | .dot = { .min = 20000, .max = 400000 }, |
145 | .vco = { .min = 1400000, .max = 2800000 }, | |
146 | .n = { .min = 1, .max = 6 }, | |
147 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
148 | .m1 = { .min = 8, .max = 18 }, |
149 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
150 | .p = { .min = 7, .max = 98 }, |
151 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
152 | .p2 = { .dot_limit = 112000, |
153 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
154 | }; |
155 | ||
273e27ca | 156 | |
e4b36699 | 157 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
158 | .dot = { .min = 25000, .max = 270000 }, |
159 | .vco = { .min = 1750000, .max = 3500000}, | |
160 | .n = { .min = 1, .max = 4 }, | |
161 | .m = { .min = 104, .max = 138 }, | |
162 | .m1 = { .min = 17, .max = 23 }, | |
163 | .m2 = { .min = 5, .max = 11 }, | |
164 | .p = { .min = 10, .max = 30 }, | |
165 | .p1 = { .min = 1, .max = 3}, | |
166 | .p2 = { .dot_limit = 270000, | |
167 | .p2_slow = 10, | |
168 | .p2_fast = 10 | |
044c7c41 | 169 | }, |
e4b36699 KP |
170 | }; |
171 | ||
172 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
173 | .dot = { .min = 22000, .max = 400000 }, |
174 | .vco = { .min = 1750000, .max = 3500000}, | |
175 | .n = { .min = 1, .max = 4 }, | |
176 | .m = { .min = 104, .max = 138 }, | |
177 | .m1 = { .min = 16, .max = 23 }, | |
178 | .m2 = { .min = 5, .max = 11 }, | |
179 | .p = { .min = 5, .max = 80 }, | |
180 | .p1 = { .min = 1, .max = 8}, | |
181 | .p2 = { .dot_limit = 165000, | |
182 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
183 | }; |
184 | ||
185 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
186 | .dot = { .min = 20000, .max = 115000 }, |
187 | .vco = { .min = 1750000, .max = 3500000 }, | |
188 | .n = { .min = 1, .max = 3 }, | |
189 | .m = { .min = 104, .max = 138 }, | |
190 | .m1 = { .min = 17, .max = 23 }, | |
191 | .m2 = { .min = 5, .max = 11 }, | |
192 | .p = { .min = 28, .max = 112 }, | |
193 | .p1 = { .min = 2, .max = 8 }, | |
194 | .p2 = { .dot_limit = 0, | |
195 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 196 | }, |
e4b36699 KP |
197 | }; |
198 | ||
199 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
200 | .dot = { .min = 80000, .max = 224000 }, |
201 | .vco = { .min = 1750000, .max = 3500000 }, | |
202 | .n = { .min = 1, .max = 3 }, | |
203 | .m = { .min = 104, .max = 138 }, | |
204 | .m1 = { .min = 17, .max = 23 }, | |
205 | .m2 = { .min = 5, .max = 11 }, | |
206 | .p = { .min = 14, .max = 42 }, | |
207 | .p1 = { .min = 2, .max = 6 }, | |
208 | .p2 = { .dot_limit = 0, | |
209 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 210 | }, |
e4b36699 KP |
211 | }; |
212 | ||
f2b115e6 | 213 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
214 | .dot = { .min = 20000, .max = 400000}, |
215 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 216 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
217 | .n = { .min = 3, .max = 6 }, |
218 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 219 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
220 | .m1 = { .min = 0, .max = 0 }, |
221 | .m2 = { .min = 0, .max = 254 }, | |
222 | .p = { .min = 5, .max = 80 }, | |
223 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
224 | .p2 = { .dot_limit = 200000, |
225 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
226 | }; |
227 | ||
f2b115e6 | 228 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
229 | .dot = { .min = 20000, .max = 400000 }, |
230 | .vco = { .min = 1700000, .max = 3500000 }, | |
231 | .n = { .min = 3, .max = 6 }, | |
232 | .m = { .min = 2, .max = 256 }, | |
233 | .m1 = { .min = 0, .max = 0 }, | |
234 | .m2 = { .min = 0, .max = 254 }, | |
235 | .p = { .min = 7, .max = 112 }, | |
236 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
237 | .p2 = { .dot_limit = 112000, |
238 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
239 | }; |
240 | ||
273e27ca EA |
241 | /* Ironlake / Sandybridge |
242 | * | |
243 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
244 | * the range value for them is (actual_value - 2). | |
245 | */ | |
b91ad0ec | 246 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
247 | .dot = { .min = 25000, .max = 350000 }, |
248 | .vco = { .min = 1760000, .max = 3510000 }, | |
249 | .n = { .min = 1, .max = 5 }, | |
250 | .m = { .min = 79, .max = 127 }, | |
251 | .m1 = { .min = 12, .max = 22 }, | |
252 | .m2 = { .min = 5, .max = 9 }, | |
253 | .p = { .min = 5, .max = 80 }, | |
254 | .p1 = { .min = 1, .max = 8 }, | |
255 | .p2 = { .dot_limit = 225000, | |
256 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
257 | }; |
258 | ||
b91ad0ec | 259 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
260 | .dot = { .min = 25000, .max = 350000 }, |
261 | .vco = { .min = 1760000, .max = 3510000 }, | |
262 | .n = { .min = 1, .max = 3 }, | |
263 | .m = { .min = 79, .max = 118 }, | |
264 | .m1 = { .min = 12, .max = 22 }, | |
265 | .m2 = { .min = 5, .max = 9 }, | |
266 | .p = { .min = 28, .max = 112 }, | |
267 | .p1 = { .min = 2, .max = 8 }, | |
268 | .p2 = { .dot_limit = 225000, | |
269 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
270 | }; |
271 | ||
272 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
273 | .dot = { .min = 25000, .max = 350000 }, |
274 | .vco = { .min = 1760000, .max = 3510000 }, | |
275 | .n = { .min = 1, .max = 3 }, | |
276 | .m = { .min = 79, .max = 127 }, | |
277 | .m1 = { .min = 12, .max = 22 }, | |
278 | .m2 = { .min = 5, .max = 9 }, | |
279 | .p = { .min = 14, .max = 56 }, | |
280 | .p1 = { .min = 2, .max = 8 }, | |
281 | .p2 = { .dot_limit = 225000, | |
282 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
283 | }; |
284 | ||
273e27ca | 285 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 286 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
287 | .dot = { .min = 25000, .max = 350000 }, |
288 | .vco = { .min = 1760000, .max = 3510000 }, | |
289 | .n = { .min = 1, .max = 2 }, | |
290 | .m = { .min = 79, .max = 126 }, | |
291 | .m1 = { .min = 12, .max = 22 }, | |
292 | .m2 = { .min = 5, .max = 9 }, | |
293 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 294 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
295 | .p2 = { .dot_limit = 225000, |
296 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
297 | }; |
298 | ||
299 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
300 | .dot = { .min = 25000, .max = 350000 }, |
301 | .vco = { .min = 1760000, .max = 3510000 }, | |
302 | .n = { .min = 1, .max = 3 }, | |
303 | .m = { .min = 79, .max = 126 }, | |
304 | .m1 = { .min = 12, .max = 22 }, | |
305 | .m2 = { .min = 5, .max = 9 }, | |
306 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 307 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
308 | .p2 = { .dot_limit = 225000, |
309 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
310 | }; |
311 | ||
dc730512 | 312 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
313 | /* |
314 | * These are the data rate limits (measured in fast clocks) | |
315 | * since those are the strictest limits we have. The fast | |
316 | * clock and actual rate limits are more relaxed, so checking | |
317 | * them would make no difference. | |
318 | */ | |
319 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 320 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 321 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
322 | .m1 = { .min = 2, .max = 3 }, |
323 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 324 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 325 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
326 | }; |
327 | ||
6b4bf1c4 VS |
328 | static void vlv_clock(int refclk, intel_clock_t *clock) |
329 | { | |
330 | clock->m = clock->m1 * clock->m2; | |
331 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
332 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
333 | return; | |
fb03ac01 VS |
334 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
335 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
6b4bf1c4 VS |
336 | } |
337 | ||
e0638cdf PZ |
338 | /** |
339 | * Returns whether any output on the specified pipe is of the specified type | |
340 | */ | |
341 | static bool intel_pipe_has_type(struct drm_crtc *crtc, int type) | |
342 | { | |
343 | struct drm_device *dev = crtc->dev; | |
344 | struct intel_encoder *encoder; | |
345 | ||
346 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
347 | if (encoder->type == type) | |
348 | return true; | |
349 | ||
350 | return false; | |
351 | } | |
352 | ||
1b894b59 CW |
353 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
354 | int refclk) | |
2c07245f | 355 | { |
b91ad0ec | 356 | struct drm_device *dev = crtc->dev; |
2c07245f | 357 | const intel_limit_t *limit; |
b91ad0ec ZW |
358 | |
359 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 360 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 361 | if (refclk == 100000) |
b91ad0ec ZW |
362 | limit = &intel_limits_ironlake_dual_lvds_100m; |
363 | else | |
364 | limit = &intel_limits_ironlake_dual_lvds; | |
365 | } else { | |
1b894b59 | 366 | if (refclk == 100000) |
b91ad0ec ZW |
367 | limit = &intel_limits_ironlake_single_lvds_100m; |
368 | else | |
369 | limit = &intel_limits_ironlake_single_lvds; | |
370 | } | |
c6bb3538 | 371 | } else |
b91ad0ec | 372 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
373 | |
374 | return limit; | |
375 | } | |
376 | ||
044c7c41 ML |
377 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
378 | { | |
379 | struct drm_device *dev = crtc->dev; | |
044c7c41 ML |
380 | const intel_limit_t *limit; |
381 | ||
382 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 383 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 384 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 385 | else |
e4b36699 | 386 | limit = &intel_limits_g4x_single_channel_lvds; |
044c7c41 ML |
387 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
388 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 389 | limit = &intel_limits_g4x_hdmi; |
044c7c41 | 390 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 391 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 392 | } else /* The option is for other outputs */ |
e4b36699 | 393 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
394 | |
395 | return limit; | |
396 | } | |
397 | ||
1b894b59 | 398 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
79e53945 JB |
399 | { |
400 | struct drm_device *dev = crtc->dev; | |
401 | const intel_limit_t *limit; | |
402 | ||
bad720ff | 403 | if (HAS_PCH_SPLIT(dev)) |
1b894b59 | 404 | limit = intel_ironlake_limit(crtc, refclk); |
2c07245f | 405 | else if (IS_G4X(dev)) { |
044c7c41 | 406 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 407 | } else if (IS_PINEVIEW(dev)) { |
2177832f | 408 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 409 | limit = &intel_limits_pineview_lvds; |
2177832f | 410 | else |
f2b115e6 | 411 | limit = &intel_limits_pineview_sdvo; |
a0c4da24 | 412 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 413 | limit = &intel_limits_vlv; |
a6c45cf0 CW |
414 | } else if (!IS_GEN2(dev)) { |
415 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
416 | limit = &intel_limits_i9xx_lvds; | |
417 | else | |
418 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 JB |
419 | } else { |
420 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 421 | limit = &intel_limits_i8xx_lvds; |
5d536e28 | 422 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO)) |
e4b36699 | 423 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
424 | else |
425 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
426 | } |
427 | return limit; | |
428 | } | |
429 | ||
f2b115e6 AJ |
430 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
431 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 432 | { |
2177832f SL |
433 | clock->m = clock->m2 + 2; |
434 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
435 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
436 | return; | |
fb03ac01 VS |
437 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
438 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
2177832f SL |
439 | } |
440 | ||
7429e9d4 DV |
441 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
442 | { | |
443 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
444 | } | |
445 | ||
ac58c3f0 | 446 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
2177832f | 447 | { |
7429e9d4 | 448 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 449 | clock->p = clock->p1 * clock->p2; |
ed5ca77e VS |
450 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
451 | return; | |
fb03ac01 VS |
452 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
453 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
79e53945 JB |
454 | } |
455 | ||
7c04d1d9 | 456 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
457 | /** |
458 | * Returns whether the given set of divisors are valid for a given refclk with | |
459 | * the given connectors. | |
460 | */ | |
461 | ||
1b894b59 CW |
462 | static bool intel_PLL_is_valid(struct drm_device *dev, |
463 | const intel_limit_t *limit, | |
464 | const intel_clock_t *clock) | |
79e53945 | 465 | { |
f01b7962 VS |
466 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
467 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 468 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 469 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 470 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 471 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 472 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 473 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 VS |
474 | |
475 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev)) | |
476 | if (clock->m1 <= clock->m2) | |
477 | INTELPllInvalid("m1 <= m2\n"); | |
478 | ||
479 | if (!IS_VALLEYVIEW(dev)) { | |
480 | if (clock->p < limit->p.min || limit->p.max < clock->p) | |
481 | INTELPllInvalid("p out of range\n"); | |
482 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
483 | INTELPllInvalid("m out of range\n"); | |
484 | } | |
485 | ||
79e53945 | 486 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 487 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
488 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
489 | * connector, etc., rather than just a single range. | |
490 | */ | |
491 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 492 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
493 | |
494 | return true; | |
495 | } | |
496 | ||
d4906093 | 497 | static bool |
ee9300bb | 498 | i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
cec2f356 SP |
499 | int target, int refclk, intel_clock_t *match_clock, |
500 | intel_clock_t *best_clock) | |
79e53945 JB |
501 | { |
502 | struct drm_device *dev = crtc->dev; | |
79e53945 | 503 | intel_clock_t clock; |
79e53945 JB |
504 | int err = target; |
505 | ||
a210b028 | 506 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 507 | /* |
a210b028 DV |
508 | * For LVDS just rely on its current settings for dual-channel. |
509 | * We haven't figured out how to reliably set up different | |
510 | * single/dual channel state, if we even can. | |
79e53945 | 511 | */ |
1974cad0 | 512 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
513 | clock.p2 = limit->p2.p2_fast; |
514 | else | |
515 | clock.p2 = limit->p2.p2_slow; | |
516 | } else { | |
517 | if (target < limit->p2.dot_limit) | |
518 | clock.p2 = limit->p2.p2_slow; | |
519 | else | |
520 | clock.p2 = limit->p2.p2_fast; | |
521 | } | |
522 | ||
0206e353 | 523 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 524 | |
42158660 ZY |
525 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
526 | clock.m1++) { | |
527 | for (clock.m2 = limit->m2.min; | |
528 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 529 | if (clock.m2 >= clock.m1) |
42158660 ZY |
530 | break; |
531 | for (clock.n = limit->n.min; | |
532 | clock.n <= limit->n.max; clock.n++) { | |
533 | for (clock.p1 = limit->p1.min; | |
534 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
535 | int this_err; |
536 | ||
ac58c3f0 DV |
537 | i9xx_clock(refclk, &clock); |
538 | if (!intel_PLL_is_valid(dev, limit, | |
539 | &clock)) | |
540 | continue; | |
541 | if (match_clock && | |
542 | clock.p != match_clock->p) | |
543 | continue; | |
544 | ||
545 | this_err = abs(clock.dot - target); | |
546 | if (this_err < err) { | |
547 | *best_clock = clock; | |
548 | err = this_err; | |
549 | } | |
550 | } | |
551 | } | |
552 | } | |
553 | } | |
554 | ||
555 | return (err != target); | |
556 | } | |
557 | ||
558 | static bool | |
ee9300bb DV |
559 | pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
560 | int target, int refclk, intel_clock_t *match_clock, | |
561 | intel_clock_t *best_clock) | |
79e53945 JB |
562 | { |
563 | struct drm_device *dev = crtc->dev; | |
79e53945 | 564 | intel_clock_t clock; |
79e53945 JB |
565 | int err = target; |
566 | ||
a210b028 | 567 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 568 | /* |
a210b028 DV |
569 | * For LVDS just rely on its current settings for dual-channel. |
570 | * We haven't figured out how to reliably set up different | |
571 | * single/dual channel state, if we even can. | |
79e53945 | 572 | */ |
1974cad0 | 573 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
574 | clock.p2 = limit->p2.p2_fast; |
575 | else | |
576 | clock.p2 = limit->p2.p2_slow; | |
577 | } else { | |
578 | if (target < limit->p2.dot_limit) | |
579 | clock.p2 = limit->p2.p2_slow; | |
580 | else | |
581 | clock.p2 = limit->p2.p2_fast; | |
582 | } | |
583 | ||
0206e353 | 584 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 585 | |
42158660 ZY |
586 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
587 | clock.m1++) { | |
588 | for (clock.m2 = limit->m2.min; | |
589 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
590 | for (clock.n = limit->n.min; |
591 | clock.n <= limit->n.max; clock.n++) { | |
592 | for (clock.p1 = limit->p1.min; | |
593 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
594 | int this_err; |
595 | ||
ac58c3f0 | 596 | pineview_clock(refclk, &clock); |
1b894b59 CW |
597 | if (!intel_PLL_is_valid(dev, limit, |
598 | &clock)) | |
79e53945 | 599 | continue; |
cec2f356 SP |
600 | if (match_clock && |
601 | clock.p != match_clock->p) | |
602 | continue; | |
79e53945 JB |
603 | |
604 | this_err = abs(clock.dot - target); | |
605 | if (this_err < err) { | |
606 | *best_clock = clock; | |
607 | err = this_err; | |
608 | } | |
609 | } | |
610 | } | |
611 | } | |
612 | } | |
613 | ||
614 | return (err != target); | |
615 | } | |
616 | ||
d4906093 | 617 | static bool |
ee9300bb DV |
618 | g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
619 | int target, int refclk, intel_clock_t *match_clock, | |
620 | intel_clock_t *best_clock) | |
d4906093 ML |
621 | { |
622 | struct drm_device *dev = crtc->dev; | |
d4906093 ML |
623 | intel_clock_t clock; |
624 | int max_n; | |
625 | bool found; | |
6ba770dc AJ |
626 | /* approximately equals target * 0.00585 */ |
627 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
628 | found = false; |
629 | ||
630 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 631 | if (intel_is_dual_link_lvds(dev)) |
d4906093 ML |
632 | clock.p2 = limit->p2.p2_fast; |
633 | else | |
634 | clock.p2 = limit->p2.p2_slow; | |
635 | } else { | |
636 | if (target < limit->p2.dot_limit) | |
637 | clock.p2 = limit->p2.p2_slow; | |
638 | else | |
639 | clock.p2 = limit->p2.p2_fast; | |
640 | } | |
641 | ||
642 | memset(best_clock, 0, sizeof(*best_clock)); | |
643 | max_n = limit->n.max; | |
f77f13e2 | 644 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 645 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 646 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
647 | for (clock.m1 = limit->m1.max; |
648 | clock.m1 >= limit->m1.min; clock.m1--) { | |
649 | for (clock.m2 = limit->m2.max; | |
650 | clock.m2 >= limit->m2.min; clock.m2--) { | |
651 | for (clock.p1 = limit->p1.max; | |
652 | clock.p1 >= limit->p1.min; clock.p1--) { | |
653 | int this_err; | |
654 | ||
ac58c3f0 | 655 | i9xx_clock(refclk, &clock); |
1b894b59 CW |
656 | if (!intel_PLL_is_valid(dev, limit, |
657 | &clock)) | |
d4906093 | 658 | continue; |
1b894b59 CW |
659 | |
660 | this_err = abs(clock.dot - target); | |
d4906093 ML |
661 | if (this_err < err_most) { |
662 | *best_clock = clock; | |
663 | err_most = this_err; | |
664 | max_n = clock.n; | |
665 | found = true; | |
666 | } | |
667 | } | |
668 | } | |
669 | } | |
670 | } | |
2c07245f ZW |
671 | return found; |
672 | } | |
673 | ||
a0c4da24 | 674 | static bool |
ee9300bb DV |
675 | vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
676 | int target, int refclk, intel_clock_t *match_clock, | |
677 | intel_clock_t *best_clock) | |
a0c4da24 | 678 | { |
f01b7962 | 679 | struct drm_device *dev = crtc->dev; |
6b4bf1c4 | 680 | intel_clock_t clock; |
69e4f900 | 681 | unsigned int bestppm = 1000000; |
27e639bf VS |
682 | /* min update 19.2 MHz */ |
683 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 684 | bool found = false; |
a0c4da24 | 685 | |
6b4bf1c4 VS |
686 | target *= 5; /* fast clock */ |
687 | ||
688 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
689 | |
690 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 691 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 692 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 693 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 694 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 695 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 696 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 697 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
69e4f900 VS |
698 | unsigned int ppm, diff; |
699 | ||
6b4bf1c4 VS |
700 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
701 | refclk * clock.m1); | |
702 | ||
703 | vlv_clock(refclk, &clock); | |
43b0ac53 | 704 | |
f01b7962 VS |
705 | if (!intel_PLL_is_valid(dev, limit, |
706 | &clock)) | |
43b0ac53 VS |
707 | continue; |
708 | ||
6b4bf1c4 VS |
709 | diff = abs(clock.dot - target); |
710 | ppm = div_u64(1000000ULL * diff, target); | |
711 | ||
712 | if (ppm < 100 && clock.p > best_clock->p) { | |
43b0ac53 | 713 | bestppm = 0; |
6b4bf1c4 | 714 | *best_clock = clock; |
49e497ef | 715 | found = true; |
43b0ac53 | 716 | } |
6b4bf1c4 | 717 | |
c686122c | 718 | if (bestppm >= 10 && ppm < bestppm - 10) { |
69e4f900 | 719 | bestppm = ppm; |
6b4bf1c4 | 720 | *best_clock = clock; |
49e497ef | 721 | found = true; |
a0c4da24 JB |
722 | } |
723 | } | |
724 | } | |
725 | } | |
726 | } | |
a0c4da24 | 727 | |
49e497ef | 728 | return found; |
a0c4da24 | 729 | } |
a4fc5ed6 | 730 | |
20ddf665 VS |
731 | bool intel_crtc_active(struct drm_crtc *crtc) |
732 | { | |
733 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
734 | ||
735 | /* Be paranoid as we can arrive here with only partial | |
736 | * state retrieved from the hardware during setup. | |
737 | * | |
241bfc38 | 738 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
739 | * as Haswell has gained clock readout/fastboot support. |
740 | * | |
741 | * We can ditch the crtc->fb check as soon as we can | |
742 | * properly reconstruct framebuffers. | |
743 | */ | |
744 | return intel_crtc->active && crtc->fb && | |
241bfc38 | 745 | intel_crtc->config.adjusted_mode.crtc_clock; |
20ddf665 VS |
746 | } |
747 | ||
a5c961d1 PZ |
748 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
749 | enum pipe pipe) | |
750 | { | |
751 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
752 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
753 | ||
3b117c8f | 754 | return intel_crtc->config.cpu_transcoder; |
a5c961d1 PZ |
755 | } |
756 | ||
57e22f4a | 757 | static void g4x_wait_for_vblank(struct drm_device *dev, int pipe) |
a928d536 PZ |
758 | { |
759 | struct drm_i915_private *dev_priv = dev->dev_private; | |
57e22f4a | 760 | u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe); |
a928d536 PZ |
761 | |
762 | frame = I915_READ(frame_reg); | |
763 | ||
764 | if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) | |
765 | DRM_DEBUG_KMS("vblank wait timed out\n"); | |
766 | } | |
767 | ||
9d0498a2 JB |
768 | /** |
769 | * intel_wait_for_vblank - wait for vblank on a given pipe | |
770 | * @dev: drm device | |
771 | * @pipe: pipe to wait for | |
772 | * | |
773 | * Wait for vblank to occur on a given pipe. Needed for various bits of | |
774 | * mode setting code. | |
775 | */ | |
776 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) | |
79e53945 | 777 | { |
9d0498a2 | 778 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 779 | int pipestat_reg = PIPESTAT(pipe); |
9d0498a2 | 780 | |
57e22f4a VS |
781 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
782 | g4x_wait_for_vblank(dev, pipe); | |
a928d536 PZ |
783 | return; |
784 | } | |
785 | ||
300387c0 CW |
786 | /* Clear existing vblank status. Note this will clear any other |
787 | * sticky status fields as well. | |
788 | * | |
789 | * This races with i915_driver_irq_handler() with the result | |
790 | * that either function could miss a vblank event. Here it is not | |
791 | * fatal, as we will either wait upon the next vblank interrupt or | |
792 | * timeout. Generally speaking intel_wait_for_vblank() is only | |
793 | * called during modeset at which time the GPU should be idle and | |
794 | * should *not* be performing page flips and thus not waiting on | |
795 | * vblanks... | |
796 | * Currently, the result of us stealing a vblank from the irq | |
797 | * handler is that a single frame will be skipped during swapbuffers. | |
798 | */ | |
799 | I915_WRITE(pipestat_reg, | |
800 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); | |
801 | ||
9d0498a2 | 802 | /* Wait for vblank interrupt bit to set */ |
481b6af3 CW |
803 | if (wait_for(I915_READ(pipestat_reg) & |
804 | PIPE_VBLANK_INTERRUPT_STATUS, | |
805 | 50)) | |
9d0498a2 JB |
806 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
807 | } | |
808 | ||
fbf49ea2 VS |
809 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
810 | { | |
811 | struct drm_i915_private *dev_priv = dev->dev_private; | |
812 | u32 reg = PIPEDSL(pipe); | |
813 | u32 line1, line2; | |
814 | u32 line_mask; | |
815 | ||
816 | if (IS_GEN2(dev)) | |
817 | line_mask = DSL_LINEMASK_GEN2; | |
818 | else | |
819 | line_mask = DSL_LINEMASK_GEN3; | |
820 | ||
821 | line1 = I915_READ(reg) & line_mask; | |
822 | mdelay(5); | |
823 | line2 = I915_READ(reg) & line_mask; | |
824 | ||
825 | return line1 == line2; | |
826 | } | |
827 | ||
ab7ad7f6 KP |
828 | /* |
829 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
9d0498a2 JB |
830 | * @dev: drm device |
831 | * @pipe: pipe to wait for | |
832 | * | |
833 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
834 | * spinning on the vblank interrupt status bit, since we won't actually | |
835 | * see an interrupt when the pipe is disabled. | |
836 | * | |
ab7ad7f6 KP |
837 | * On Gen4 and above: |
838 | * wait for the pipe register state bit to turn off | |
839 | * | |
840 | * Otherwise: | |
841 | * wait for the display line value to settle (it usually | |
842 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 843 | * |
9d0498a2 | 844 | */ |
58e10eb9 | 845 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
9d0498a2 JB |
846 | { |
847 | struct drm_i915_private *dev_priv = dev->dev_private; | |
702e7a56 PZ |
848 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
849 | pipe); | |
ab7ad7f6 KP |
850 | |
851 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 852 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
853 | |
854 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
855 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
856 | 100)) | |
284637d9 | 857 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 858 | } else { |
ab7ad7f6 | 859 | /* Wait for the display line to settle */ |
fbf49ea2 | 860 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 861 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 862 | } |
79e53945 JB |
863 | } |
864 | ||
b0ea7d37 DL |
865 | /* |
866 | * ibx_digital_port_connected - is the specified port connected? | |
867 | * @dev_priv: i915 private structure | |
868 | * @port: the port to test | |
869 | * | |
870 | * Returns true if @port is connected, false otherwise. | |
871 | */ | |
872 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, | |
873 | struct intel_digital_port *port) | |
874 | { | |
875 | u32 bit; | |
876 | ||
c36346e3 DL |
877 | if (HAS_PCH_IBX(dev_priv->dev)) { |
878 | switch(port->port) { | |
879 | case PORT_B: | |
880 | bit = SDE_PORTB_HOTPLUG; | |
881 | break; | |
882 | case PORT_C: | |
883 | bit = SDE_PORTC_HOTPLUG; | |
884 | break; | |
885 | case PORT_D: | |
886 | bit = SDE_PORTD_HOTPLUG; | |
887 | break; | |
888 | default: | |
889 | return true; | |
890 | } | |
891 | } else { | |
892 | switch(port->port) { | |
893 | case PORT_B: | |
894 | bit = SDE_PORTB_HOTPLUG_CPT; | |
895 | break; | |
896 | case PORT_C: | |
897 | bit = SDE_PORTC_HOTPLUG_CPT; | |
898 | break; | |
899 | case PORT_D: | |
900 | bit = SDE_PORTD_HOTPLUG_CPT; | |
901 | break; | |
902 | default: | |
903 | return true; | |
904 | } | |
b0ea7d37 DL |
905 | } |
906 | ||
907 | return I915_READ(SDEISR) & bit; | |
908 | } | |
909 | ||
b24e7179 JB |
910 | static const char *state_string(bool enabled) |
911 | { | |
912 | return enabled ? "on" : "off"; | |
913 | } | |
914 | ||
915 | /* Only for pre-ILK configs */ | |
55607e8a DV |
916 | void assert_pll(struct drm_i915_private *dev_priv, |
917 | enum pipe pipe, bool state) | |
b24e7179 JB |
918 | { |
919 | int reg; | |
920 | u32 val; | |
921 | bool cur_state; | |
922 | ||
923 | reg = DPLL(pipe); | |
924 | val = I915_READ(reg); | |
925 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
926 | WARN(cur_state != state, | |
927 | "PLL state assertion failure (expected %s, current %s)\n", | |
928 | state_string(state), state_string(cur_state)); | |
929 | } | |
b24e7179 | 930 | |
23538ef1 JN |
931 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
932 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
933 | { | |
934 | u32 val; | |
935 | bool cur_state; | |
936 | ||
937 | mutex_lock(&dev_priv->dpio_lock); | |
938 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); | |
939 | mutex_unlock(&dev_priv->dpio_lock); | |
940 | ||
941 | cur_state = val & DSI_PLL_VCO_EN; | |
942 | WARN(cur_state != state, | |
943 | "DSI PLL state assertion failure (expected %s, current %s)\n", | |
944 | state_string(state), state_string(cur_state)); | |
945 | } | |
946 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
947 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
948 | ||
55607e8a | 949 | struct intel_shared_dpll * |
e2b78267 DV |
950 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
951 | { | |
952 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
953 | ||
a43f6e0f | 954 | if (crtc->config.shared_dpll < 0) |
e2b78267 DV |
955 | return NULL; |
956 | ||
a43f6e0f | 957 | return &dev_priv->shared_dplls[crtc->config.shared_dpll]; |
e2b78267 DV |
958 | } |
959 | ||
040484af | 960 | /* For ILK+ */ |
55607e8a DV |
961 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
962 | struct intel_shared_dpll *pll, | |
963 | bool state) | |
040484af | 964 | { |
040484af | 965 | bool cur_state; |
5358901f | 966 | struct intel_dpll_hw_state hw_state; |
040484af | 967 | |
9d82aa17 ED |
968 | if (HAS_PCH_LPT(dev_priv->dev)) { |
969 | DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n"); | |
970 | return; | |
971 | } | |
972 | ||
92b27b08 | 973 | if (WARN (!pll, |
46edb027 | 974 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 975 | return; |
ee7b9f93 | 976 | |
5358901f | 977 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
92b27b08 | 978 | WARN(cur_state != state, |
5358901f DV |
979 | "%s assertion failure (expected %s, current %s)\n", |
980 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 981 | } |
040484af JB |
982 | |
983 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
984 | enum pipe pipe, bool state) | |
985 | { | |
986 | int reg; | |
987 | u32 val; | |
988 | bool cur_state; | |
ad80a810 PZ |
989 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
990 | pipe); | |
040484af | 991 | |
affa9354 PZ |
992 | if (HAS_DDI(dev_priv->dev)) { |
993 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 994 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 995 | val = I915_READ(reg); |
ad80a810 | 996 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
997 | } else { |
998 | reg = FDI_TX_CTL(pipe); | |
999 | val = I915_READ(reg); | |
1000 | cur_state = !!(val & FDI_TX_ENABLE); | |
1001 | } | |
040484af JB |
1002 | WARN(cur_state != state, |
1003 | "FDI TX state assertion failure (expected %s, current %s)\n", | |
1004 | state_string(state), state_string(cur_state)); | |
1005 | } | |
1006 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1007 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1008 | ||
1009 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1010 | enum pipe pipe, bool state) | |
1011 | { | |
1012 | int reg; | |
1013 | u32 val; | |
1014 | bool cur_state; | |
1015 | ||
d63fa0dc PZ |
1016 | reg = FDI_RX_CTL(pipe); |
1017 | val = I915_READ(reg); | |
1018 | cur_state = !!(val & FDI_RX_ENABLE); | |
040484af JB |
1019 | WARN(cur_state != state, |
1020 | "FDI RX state assertion failure (expected %s, current %s)\n", | |
1021 | state_string(state), state_string(cur_state)); | |
1022 | } | |
1023 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1024 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1025 | ||
1026 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1027 | enum pipe pipe) | |
1028 | { | |
1029 | int reg; | |
1030 | u32 val; | |
1031 | ||
1032 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1033 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1034 | return; |
1035 | ||
bf507ef7 | 1036 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1037 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1038 | return; |
1039 | ||
040484af JB |
1040 | reg = FDI_TX_CTL(pipe); |
1041 | val = I915_READ(reg); | |
1042 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); | |
1043 | } | |
1044 | ||
55607e8a DV |
1045 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1046 | enum pipe pipe, bool state) | |
040484af JB |
1047 | { |
1048 | int reg; | |
1049 | u32 val; | |
55607e8a | 1050 | bool cur_state; |
040484af JB |
1051 | |
1052 | reg = FDI_RX_CTL(pipe); | |
1053 | val = I915_READ(reg); | |
55607e8a DV |
1054 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
1055 | WARN(cur_state != state, | |
1056 | "FDI RX PLL assertion failure (expected %s, current %s)\n", | |
1057 | state_string(state), state_string(cur_state)); | |
040484af JB |
1058 | } |
1059 | ||
ea0760cf JB |
1060 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1061 | enum pipe pipe) | |
1062 | { | |
1063 | int pp_reg, lvds_reg; | |
1064 | u32 val; | |
1065 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1066 | bool locked = true; |
ea0760cf JB |
1067 | |
1068 | if (HAS_PCH_SPLIT(dev_priv->dev)) { | |
1069 | pp_reg = PCH_PP_CONTROL; | |
1070 | lvds_reg = PCH_LVDS; | |
1071 | } else { | |
1072 | pp_reg = PP_CONTROL; | |
1073 | lvds_reg = LVDS; | |
1074 | } | |
1075 | ||
1076 | val = I915_READ(pp_reg); | |
1077 | if (!(val & PANEL_POWER_ON) || | |
1078 | ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) | |
1079 | locked = false; | |
1080 | ||
1081 | if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) | |
1082 | panel_pipe = PIPE_B; | |
1083 | ||
1084 | WARN(panel_pipe == pipe && locked, | |
1085 | "panel assertion failure, pipe %c regs locked\n", | |
9db4a9c7 | 1086 | pipe_name(pipe)); |
ea0760cf JB |
1087 | } |
1088 | ||
93ce0ba6 JN |
1089 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1090 | enum pipe pipe, bool state) | |
1091 | { | |
1092 | struct drm_device *dev = dev_priv->dev; | |
1093 | bool cur_state; | |
1094 | ||
1095 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
1096 | cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE; | |
1097 | else if (IS_845G(dev) || IS_I865G(dev)) | |
1098 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; | |
1099 | else | |
1100 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; | |
1101 | ||
1102 | WARN(cur_state != state, | |
1103 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", | |
1104 | pipe_name(pipe), state_string(state), state_string(cur_state)); | |
1105 | } | |
1106 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1107 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1108 | ||
b840d907 JB |
1109 | void assert_pipe(struct drm_i915_private *dev_priv, |
1110 | enum pipe pipe, bool state) | |
b24e7179 JB |
1111 | { |
1112 | int reg; | |
1113 | u32 val; | |
63d7bbe9 | 1114 | bool cur_state; |
702e7a56 PZ |
1115 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1116 | pipe); | |
b24e7179 | 1117 | |
8e636784 DV |
1118 | /* if we need the pipe A quirk it must be always on */ |
1119 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
1120 | state = true; | |
1121 | ||
b97186f0 PZ |
1122 | if (!intel_display_power_enabled(dev_priv->dev, |
1123 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { | |
69310161 PZ |
1124 | cur_state = false; |
1125 | } else { | |
1126 | reg = PIPECONF(cpu_transcoder); | |
1127 | val = I915_READ(reg); | |
1128 | cur_state = !!(val & PIPECONF_ENABLE); | |
1129 | } | |
1130 | ||
63d7bbe9 JB |
1131 | WARN(cur_state != state, |
1132 | "pipe %c assertion failure (expected %s, current %s)\n", | |
9db4a9c7 | 1133 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1134 | } |
1135 | ||
931872fc CW |
1136 | static void assert_plane(struct drm_i915_private *dev_priv, |
1137 | enum plane plane, bool state) | |
b24e7179 JB |
1138 | { |
1139 | int reg; | |
1140 | u32 val; | |
931872fc | 1141 | bool cur_state; |
b24e7179 JB |
1142 | |
1143 | reg = DSPCNTR(plane); | |
1144 | val = I915_READ(reg); | |
931872fc CW |
1145 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
1146 | WARN(cur_state != state, | |
1147 | "plane %c assertion failure (expected %s, current %s)\n", | |
1148 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1149 | } |
1150 | ||
931872fc CW |
1151 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1152 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1153 | ||
b24e7179 JB |
1154 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1155 | enum pipe pipe) | |
1156 | { | |
653e1026 | 1157 | struct drm_device *dev = dev_priv->dev; |
b24e7179 JB |
1158 | int reg, i; |
1159 | u32 val; | |
1160 | int cur_pipe; | |
1161 | ||
653e1026 VS |
1162 | /* Primary planes are fixed to pipes on gen4+ */ |
1163 | if (INTEL_INFO(dev)->gen >= 4) { | |
28c05794 AJ |
1164 | reg = DSPCNTR(pipe); |
1165 | val = I915_READ(reg); | |
1166 | WARN((val & DISPLAY_PLANE_ENABLE), | |
1167 | "plane %c assertion failure, should be disabled but not\n", | |
1168 | plane_name(pipe)); | |
19ec1358 | 1169 | return; |
28c05794 | 1170 | } |
19ec1358 | 1171 | |
b24e7179 | 1172 | /* Need to check both planes against the pipe */ |
08e2a7de | 1173 | for_each_pipe(i) { |
b24e7179 JB |
1174 | reg = DSPCNTR(i); |
1175 | val = I915_READ(reg); | |
1176 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1177 | DISPPLANE_SEL_PIPE_SHIFT; | |
1178 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, | |
9db4a9c7 JB |
1179 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1180 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1181 | } |
1182 | } | |
1183 | ||
19332d7a JB |
1184 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1185 | enum pipe pipe) | |
1186 | { | |
20674eef | 1187 | struct drm_device *dev = dev_priv->dev; |
19332d7a JB |
1188 | int reg, i; |
1189 | u32 val; | |
1190 | ||
20674eef | 1191 | if (IS_VALLEYVIEW(dev)) { |
22d3fd46 | 1192 | for (i = 0; i < INTEL_INFO(dev)->num_sprites; i++) { |
20674eef VS |
1193 | reg = SPCNTR(pipe, i); |
1194 | val = I915_READ(reg); | |
1195 | WARN((val & SP_ENABLE), | |
1196 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", | |
1197 | sprite_name(pipe, i), pipe_name(pipe)); | |
1198 | } | |
1199 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
1200 | reg = SPRCTL(pipe); | |
19332d7a | 1201 | val = I915_READ(reg); |
20674eef | 1202 | WARN((val & SPRITE_ENABLE), |
06da8da2 | 1203 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1204 | plane_name(pipe), pipe_name(pipe)); |
1205 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
1206 | reg = DVSCNTR(pipe); | |
19332d7a | 1207 | val = I915_READ(reg); |
20674eef | 1208 | WARN((val & DVS_ENABLE), |
06da8da2 | 1209 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1210 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1211 | } |
1212 | } | |
1213 | ||
89eff4be | 1214 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1215 | { |
1216 | u32 val; | |
1217 | bool enabled; | |
1218 | ||
89eff4be | 1219 | WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1220 | |
92f2584a JB |
1221 | val = I915_READ(PCH_DREF_CONTROL); |
1222 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1223 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
1224 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); | |
1225 | } | |
1226 | ||
ab9412ba DV |
1227 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1228 | enum pipe pipe) | |
92f2584a JB |
1229 | { |
1230 | int reg; | |
1231 | u32 val; | |
1232 | bool enabled; | |
1233 | ||
ab9412ba | 1234 | reg = PCH_TRANSCONF(pipe); |
92f2584a JB |
1235 | val = I915_READ(reg); |
1236 | enabled = !!(val & TRANS_ENABLE); | |
9db4a9c7 JB |
1237 | WARN(enabled, |
1238 | "transcoder assertion failed, should be off on pipe %c but is still active\n", | |
1239 | pipe_name(pipe)); | |
92f2584a JB |
1240 | } |
1241 | ||
4e634389 KP |
1242 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1243 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1244 | { |
1245 | if ((val & DP_PORT_EN) == 0) | |
1246 | return false; | |
1247 | ||
1248 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1249 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1250 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1251 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1252 | return false; | |
1253 | } else { | |
1254 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1255 | return false; | |
1256 | } | |
1257 | return true; | |
1258 | } | |
1259 | ||
1519b995 KP |
1260 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1261 | enum pipe pipe, u32 val) | |
1262 | { | |
dc0fa718 | 1263 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1264 | return false; |
1265 | ||
1266 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1267 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 KP |
1268 | return false; |
1269 | } else { | |
dc0fa718 | 1270 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1271 | return false; |
1272 | } | |
1273 | return true; | |
1274 | } | |
1275 | ||
1276 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1277 | enum pipe pipe, u32 val) | |
1278 | { | |
1279 | if ((val & LVDS_PORT_EN) == 0) | |
1280 | return false; | |
1281 | ||
1282 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1283 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1284 | return false; | |
1285 | } else { | |
1286 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1287 | return false; | |
1288 | } | |
1289 | return true; | |
1290 | } | |
1291 | ||
1292 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1293 | enum pipe pipe, u32 val) | |
1294 | { | |
1295 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1296 | return false; | |
1297 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1298 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1299 | return false; | |
1300 | } else { | |
1301 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1302 | return false; | |
1303 | } | |
1304 | return true; | |
1305 | } | |
1306 | ||
291906f1 | 1307 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1308 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1309 | { |
47a05eca | 1310 | u32 val = I915_READ(reg); |
4e634389 | 1311 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1312 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1313 | reg, pipe_name(pipe)); |
de9a35ab | 1314 | |
75c5da27 DV |
1315 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
1316 | && (val & DP_PIPEB_SELECT), | |
de9a35ab | 1317 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1318 | } |
1319 | ||
1320 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1321 | enum pipe pipe, int reg) | |
1322 | { | |
47a05eca | 1323 | u32 val = I915_READ(reg); |
b70ad586 | 1324 | WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1325 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1326 | reg, pipe_name(pipe)); |
de9a35ab | 1327 | |
dc0fa718 | 1328 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1329 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1330 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1331 | } |
1332 | ||
1333 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1334 | enum pipe pipe) | |
1335 | { | |
1336 | int reg; | |
1337 | u32 val; | |
291906f1 | 1338 | |
f0575e92 KP |
1339 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1340 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1341 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1342 | |
1343 | reg = PCH_ADPA; | |
1344 | val = I915_READ(reg); | |
b70ad586 | 1345 | WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1346 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1347 | pipe_name(pipe)); |
291906f1 JB |
1348 | |
1349 | reg = PCH_LVDS; | |
1350 | val = I915_READ(reg); | |
b70ad586 | 1351 | WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1352 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1353 | pipe_name(pipe)); |
291906f1 | 1354 | |
e2debe91 PZ |
1355 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1356 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1357 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1358 | } |
1359 | ||
40e9cf64 JB |
1360 | static void intel_init_dpio(struct drm_device *dev) |
1361 | { | |
1362 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1363 | ||
1364 | if (!IS_VALLEYVIEW(dev)) | |
1365 | return; | |
1366 | ||
e4607fcf | 1367 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; |
5382f5f3 JB |
1368 | } |
1369 | ||
1370 | static void intel_reset_dpio(struct drm_device *dev) | |
1371 | { | |
1372 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1373 | ||
1374 | if (!IS_VALLEYVIEW(dev)) | |
1375 | return; | |
1376 | ||
e5cbfbfb ID |
1377 | /* |
1378 | * Enable the CRI clock source so we can get at the display and the | |
1379 | * reference clock for VGA hotplug / manual detection. | |
1380 | */ | |
404faabc | 1381 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | |
e5cbfbfb | 1382 | DPLL_REFA_CLK_ENABLE_VLV | |
404faabc ID |
1383 | DPLL_INTEGRATED_CRI_CLK_VLV); |
1384 | ||
40e9cf64 JB |
1385 | /* |
1386 | * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - | |
1387 | * 6. De-assert cmn_reset/side_reset. Same as VLV X0. | |
1388 | * a. GUnit 0x2110 bit[0] set to 1 (def 0) | |
1389 | * b. The other bits such as sfr settings / modesel may all be set | |
1390 | * to 0. | |
1391 | * | |
1392 | * This should only be done on init and resume from S3 with both | |
1393 | * PLLs disabled, or we risk losing DPIO and PLL synchronization. | |
1394 | */ | |
1395 | I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); | |
1396 | } | |
1397 | ||
426115cf | 1398 | static void vlv_enable_pll(struct intel_crtc *crtc) |
87442f73 | 1399 | { |
426115cf DV |
1400 | struct drm_device *dev = crtc->base.dev; |
1401 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1402 | int reg = DPLL(crtc->pipe); | |
1403 | u32 dpll = crtc->config.dpll_hw_state.dpll; | |
87442f73 | 1404 | |
426115cf | 1405 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 DV |
1406 | |
1407 | /* No really, not for ILK+ */ | |
1408 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); | |
1409 | ||
1410 | /* PLL is protected by panel, make sure we can write it */ | |
1411 | if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) | |
426115cf | 1412 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1413 | |
426115cf DV |
1414 | I915_WRITE(reg, dpll); |
1415 | POSTING_READ(reg); | |
1416 | udelay(150); | |
1417 | ||
1418 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1419 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1420 | ||
1421 | I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md); | |
1422 | POSTING_READ(DPLL_MD(crtc->pipe)); | |
87442f73 DV |
1423 | |
1424 | /* We do this three times for luck */ | |
426115cf | 1425 | I915_WRITE(reg, dpll); |
87442f73 DV |
1426 | POSTING_READ(reg); |
1427 | udelay(150); /* wait for warmup */ | |
426115cf | 1428 | I915_WRITE(reg, dpll); |
87442f73 DV |
1429 | POSTING_READ(reg); |
1430 | udelay(150); /* wait for warmup */ | |
426115cf | 1431 | I915_WRITE(reg, dpll); |
87442f73 DV |
1432 | POSTING_READ(reg); |
1433 | udelay(150); /* wait for warmup */ | |
1434 | } | |
1435 | ||
66e3d5c0 | 1436 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1437 | { |
66e3d5c0 DV |
1438 | struct drm_device *dev = crtc->base.dev; |
1439 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1440 | int reg = DPLL(crtc->pipe); | |
1441 | u32 dpll = crtc->config.dpll_hw_state.dpll; | |
63d7bbe9 | 1442 | |
66e3d5c0 | 1443 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1444 | |
63d7bbe9 | 1445 | /* No really, not for ILK+ */ |
3d13ef2e | 1446 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1447 | |
1448 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1449 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1450 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1451 | |
66e3d5c0 DV |
1452 | I915_WRITE(reg, dpll); |
1453 | ||
1454 | /* Wait for the clocks to stabilize. */ | |
1455 | POSTING_READ(reg); | |
1456 | udelay(150); | |
1457 | ||
1458 | if (INTEL_INFO(dev)->gen >= 4) { | |
1459 | I915_WRITE(DPLL_MD(crtc->pipe), | |
1460 | crtc->config.dpll_hw_state.dpll_md); | |
1461 | } else { | |
1462 | /* The pixel multiplier can only be updated once the | |
1463 | * DPLL is enabled and the clocks are stable. | |
1464 | * | |
1465 | * So write it again. | |
1466 | */ | |
1467 | I915_WRITE(reg, dpll); | |
1468 | } | |
63d7bbe9 JB |
1469 | |
1470 | /* We do this three times for luck */ | |
66e3d5c0 | 1471 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1472 | POSTING_READ(reg); |
1473 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1474 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1475 | POSTING_READ(reg); |
1476 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1477 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1478 | POSTING_READ(reg); |
1479 | udelay(150); /* wait for warmup */ | |
1480 | } | |
1481 | ||
1482 | /** | |
50b44a44 | 1483 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1484 | * @dev_priv: i915 private structure |
1485 | * @pipe: pipe PLL to disable | |
1486 | * | |
1487 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1488 | * | |
1489 | * Note! This is for pre-ILK only. | |
1490 | */ | |
50b44a44 | 1491 | static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
63d7bbe9 | 1492 | { |
63d7bbe9 JB |
1493 | /* Don't disable pipe A or pipe A PLLs if needed */ |
1494 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1495 | return; | |
1496 | ||
1497 | /* Make sure the pipe isn't still relying on us */ | |
1498 | assert_pipe_disabled(dev_priv, pipe); | |
1499 | ||
50b44a44 DV |
1500 | I915_WRITE(DPLL(pipe), 0); |
1501 | POSTING_READ(DPLL(pipe)); | |
63d7bbe9 JB |
1502 | } |
1503 | ||
f6071166 JB |
1504 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1505 | { | |
1506 | u32 val = 0; | |
1507 | ||
1508 | /* Make sure the pipe isn't still relying on us */ | |
1509 | assert_pipe_disabled(dev_priv, pipe); | |
1510 | ||
e5cbfbfb ID |
1511 | /* |
1512 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1513 | * The latter is needed for VGA hotplug / manual detection. | |
1514 | */ | |
f6071166 | 1515 | if (pipe == PIPE_B) |
e5cbfbfb | 1516 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV; |
f6071166 JB |
1517 | I915_WRITE(DPLL(pipe), val); |
1518 | POSTING_READ(DPLL(pipe)); | |
1519 | } | |
1520 | ||
e4607fcf CML |
1521 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
1522 | struct intel_digital_port *dport) | |
89b667f8 JB |
1523 | { |
1524 | u32 port_mask; | |
1525 | ||
e4607fcf CML |
1526 | switch (dport->port) { |
1527 | case PORT_B: | |
89b667f8 | 1528 | port_mask = DPLL_PORTB_READY_MASK; |
e4607fcf CML |
1529 | break; |
1530 | case PORT_C: | |
89b667f8 | 1531 | port_mask = DPLL_PORTC_READY_MASK; |
e4607fcf CML |
1532 | break; |
1533 | default: | |
1534 | BUG(); | |
1535 | } | |
89b667f8 JB |
1536 | |
1537 | if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000)) | |
1538 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", | |
be46ffd4 | 1539 | port_name(dport->port), I915_READ(DPLL(0))); |
89b667f8 JB |
1540 | } |
1541 | ||
92f2584a | 1542 | /** |
e72f9fbf | 1543 | * ironlake_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1544 | * @dev_priv: i915 private structure |
1545 | * @pipe: pipe PLL to enable | |
1546 | * | |
1547 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1548 | * drives the transcoder clock. | |
1549 | */ | |
e2b78267 | 1550 | static void ironlake_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1551 | { |
3d13ef2e DL |
1552 | struct drm_device *dev = crtc->base.dev; |
1553 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1554 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1555 | |
48da64a8 | 1556 | /* PCH PLLs only available on ILK, SNB and IVB */ |
3d13ef2e | 1557 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
87a875bb | 1558 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1559 | return; |
1560 | ||
1561 | if (WARN_ON(pll->refcount == 0)) | |
1562 | return; | |
ee7b9f93 | 1563 | |
46edb027 DV |
1564 | DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n", |
1565 | pll->name, pll->active, pll->on, | |
e2b78267 | 1566 | crtc->base.base.id); |
92f2584a | 1567 | |
cdbd2316 DV |
1568 | if (pll->active++) { |
1569 | WARN_ON(!pll->on); | |
e9d6944e | 1570 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1571 | return; |
1572 | } | |
f4a091c7 | 1573 | WARN_ON(pll->on); |
ee7b9f93 | 1574 | |
46edb027 | 1575 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1576 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1577 | pll->on = true; |
92f2584a JB |
1578 | } |
1579 | ||
e2b78267 | 1580 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1581 | { |
3d13ef2e DL |
1582 | struct drm_device *dev = crtc->base.dev; |
1583 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1584 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1585 | |
92f2584a | 1586 | /* PCH only available on ILK+ */ |
3d13ef2e | 1587 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
87a875bb | 1588 | if (WARN_ON(pll == NULL)) |
ee7b9f93 | 1589 | return; |
92f2584a | 1590 | |
48da64a8 CW |
1591 | if (WARN_ON(pll->refcount == 0)) |
1592 | return; | |
7a419866 | 1593 | |
46edb027 DV |
1594 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1595 | pll->name, pll->active, pll->on, | |
e2b78267 | 1596 | crtc->base.base.id); |
7a419866 | 1597 | |
48da64a8 | 1598 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1599 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1600 | return; |
1601 | } | |
1602 | ||
e9d6944e | 1603 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1604 | WARN_ON(!pll->on); |
cdbd2316 | 1605 | if (--pll->active) |
7a419866 | 1606 | return; |
ee7b9f93 | 1607 | |
46edb027 | 1608 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1609 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1610 | pll->on = false; |
92f2584a JB |
1611 | } |
1612 | ||
b8a4f404 PZ |
1613 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1614 | enum pipe pipe) | |
040484af | 1615 | { |
23670b32 | 1616 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1617 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1618 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
23670b32 | 1619 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1620 | |
1621 | /* PCH only available on ILK+ */ | |
3d13ef2e | 1622 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
040484af JB |
1623 | |
1624 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1625 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1626 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1627 | |
1628 | /* FDI must be feeding us bits for PCH ports */ | |
1629 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1630 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1631 | ||
23670b32 DV |
1632 | if (HAS_PCH_CPT(dev)) { |
1633 | /* Workaround: Set the timing override bit before enabling the | |
1634 | * pch transcoder. */ | |
1635 | reg = TRANS_CHICKEN2(pipe); | |
1636 | val = I915_READ(reg); | |
1637 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1638 | I915_WRITE(reg, val); | |
59c859d6 | 1639 | } |
23670b32 | 1640 | |
ab9412ba | 1641 | reg = PCH_TRANSCONF(pipe); |
040484af | 1642 | val = I915_READ(reg); |
5f7f726d | 1643 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1644 | |
1645 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1646 | /* | |
1647 | * make the BPC in transcoder be consistent with | |
1648 | * that in pipeconf reg. | |
1649 | */ | |
dfd07d72 DV |
1650 | val &= ~PIPECONF_BPC_MASK; |
1651 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1652 | } |
5f7f726d PZ |
1653 | |
1654 | val &= ~TRANS_INTERLACE_MASK; | |
1655 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 PZ |
1656 | if (HAS_PCH_IBX(dev_priv->dev) && |
1657 | intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) | |
1658 | val |= TRANS_LEGACY_INTERLACED_ILK; | |
1659 | else | |
1660 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1661 | else |
1662 | val |= TRANS_PROGRESSIVE; | |
1663 | ||
040484af JB |
1664 | I915_WRITE(reg, val | TRANS_ENABLE); |
1665 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 1666 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1667 | } |
1668 | ||
8fb033d7 | 1669 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1670 | enum transcoder cpu_transcoder) |
040484af | 1671 | { |
8fb033d7 | 1672 | u32 val, pipeconf_val; |
8fb033d7 PZ |
1673 | |
1674 | /* PCH only available on ILK+ */ | |
3d13ef2e | 1675 | BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5); |
8fb033d7 | 1676 | |
8fb033d7 | 1677 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1678 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1679 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1680 | |
223a6fdf PZ |
1681 | /* Workaround: set timing override bit. */ |
1682 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1683 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf PZ |
1684 | I915_WRITE(_TRANSA_CHICKEN2, val); |
1685 | ||
25f3ef11 | 1686 | val = TRANS_ENABLE; |
937bb610 | 1687 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1688 | |
9a76b1c6 PZ |
1689 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1690 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1691 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1692 | else |
1693 | val |= TRANS_PROGRESSIVE; | |
1694 | ||
ab9412ba DV |
1695 | I915_WRITE(LPT_TRANSCONF, val); |
1696 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 1697 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1698 | } |
1699 | ||
b8a4f404 PZ |
1700 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1701 | enum pipe pipe) | |
040484af | 1702 | { |
23670b32 DV |
1703 | struct drm_device *dev = dev_priv->dev; |
1704 | uint32_t reg, val; | |
040484af JB |
1705 | |
1706 | /* FDI relies on the transcoder */ | |
1707 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1708 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1709 | ||
291906f1 JB |
1710 | /* Ports must be off as well */ |
1711 | assert_pch_ports_disabled(dev_priv, pipe); | |
1712 | ||
ab9412ba | 1713 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1714 | val = I915_READ(reg); |
1715 | val &= ~TRANS_ENABLE; | |
1716 | I915_WRITE(reg, val); | |
1717 | /* wait for PCH transcoder off, transcoder state */ | |
1718 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 1719 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 DV |
1720 | |
1721 | if (!HAS_PCH_IBX(dev)) { | |
1722 | /* Workaround: Clear the timing override chicken bit again. */ | |
1723 | reg = TRANS_CHICKEN2(pipe); | |
1724 | val = I915_READ(reg); | |
1725 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1726 | I915_WRITE(reg, val); | |
1727 | } | |
040484af JB |
1728 | } |
1729 | ||
ab4d966c | 1730 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1731 | { |
8fb033d7 PZ |
1732 | u32 val; |
1733 | ||
ab9412ba | 1734 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1735 | val &= ~TRANS_ENABLE; |
ab9412ba | 1736 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1737 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 1738 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 1739 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1740 | |
1741 | /* Workaround: clear timing override bit. */ | |
1742 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1743 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf | 1744 | I915_WRITE(_TRANSA_CHICKEN2, val); |
040484af JB |
1745 | } |
1746 | ||
b24e7179 | 1747 | /** |
309cfea8 | 1748 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 1749 | * @crtc: crtc responsible for the pipe |
040484af | 1750 | * @pch_port: on ILK+, is this pipe driving a PCH port or not |
0372264a PZ |
1751 | * @dsi: output type is DSI |
1752 | * @wait_for_vblank: whether we should for a vblank or not after enabling it | |
b24e7179 | 1753 | * |
0372264a | 1754 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 1755 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 1756 | */ |
0372264a | 1757 | static void intel_enable_pipe(struct intel_crtc *crtc, |
851855d8 | 1758 | bool pch_port, bool dsi, bool wait_for_vblank) |
b24e7179 | 1759 | { |
0372264a PZ |
1760 | struct drm_device *dev = crtc->base.dev; |
1761 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1762 | enum pipe pipe = crtc->pipe; | |
702e7a56 PZ |
1763 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1764 | pipe); | |
1a240d4d | 1765 | enum pipe pch_transcoder; |
b24e7179 JB |
1766 | int reg; |
1767 | u32 val; | |
1768 | ||
58c6eaa2 | 1769 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 1770 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
1771 | assert_sprites_disabled(dev_priv, pipe); |
1772 | ||
681e5811 | 1773 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
1774 | pch_transcoder = TRANSCODER_A; |
1775 | else | |
1776 | pch_transcoder = pipe; | |
1777 | ||
b24e7179 JB |
1778 | /* |
1779 | * A pipe without a PLL won't actually be able to drive bits from | |
1780 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1781 | * need the check. | |
1782 | */ | |
1783 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
23538ef1 JN |
1784 | if (dsi) |
1785 | assert_dsi_pll_enabled(dev_priv); | |
1786 | else | |
1787 | assert_pll_enabled(dev_priv, pipe); | |
040484af JB |
1788 | else { |
1789 | if (pch_port) { | |
1790 | /* if driving the PCH, we need FDI enabled */ | |
cc391bbb | 1791 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
1792 | assert_fdi_tx_pll_enabled(dev_priv, |
1793 | (enum pipe) cpu_transcoder); | |
040484af JB |
1794 | } |
1795 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1796 | } | |
b24e7179 | 1797 | |
702e7a56 | 1798 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1799 | val = I915_READ(reg); |
00d70b15 CW |
1800 | if (val & PIPECONF_ENABLE) |
1801 | return; | |
1802 | ||
1803 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 PZ |
1804 | POSTING_READ(reg); |
1805 | if (wait_for_vblank) | |
1806 | intel_wait_for_vblank(dev_priv->dev, pipe); | |
b24e7179 JB |
1807 | } |
1808 | ||
1809 | /** | |
309cfea8 | 1810 | * intel_disable_pipe - disable a pipe, asserting requirements |
b24e7179 JB |
1811 | * @dev_priv: i915 private structure |
1812 | * @pipe: pipe to disable | |
1813 | * | |
1814 | * Disable @pipe, making sure that various hardware specific requirements | |
1815 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. | |
1816 | * | |
1817 | * @pipe should be %PIPE_A or %PIPE_B. | |
1818 | * | |
1819 | * Will wait until the pipe has shut down before returning. | |
1820 | */ | |
1821 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, | |
1822 | enum pipe pipe) | |
1823 | { | |
702e7a56 PZ |
1824 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1825 | pipe); | |
b24e7179 JB |
1826 | int reg; |
1827 | u32 val; | |
1828 | ||
1829 | /* | |
1830 | * Make sure planes won't keep trying to pump pixels to us, | |
1831 | * or we might hang the display. | |
1832 | */ | |
1833 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 1834 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 1835 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 JB |
1836 | |
1837 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
1838 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1839 | return; | |
1840 | ||
702e7a56 | 1841 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1842 | val = I915_READ(reg); |
00d70b15 CW |
1843 | if ((val & PIPECONF_ENABLE) == 0) |
1844 | return; | |
1845 | ||
1846 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); | |
b24e7179 JB |
1847 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
1848 | } | |
1849 | ||
d74362c9 KP |
1850 | /* |
1851 | * Plane regs are double buffered, going from enabled->disabled needs a | |
1852 | * trigger in order to latch. The display address reg provides this. | |
1853 | */ | |
1dba99f4 VS |
1854 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
1855 | enum plane plane) | |
d74362c9 | 1856 | { |
3d13ef2e DL |
1857 | struct drm_device *dev = dev_priv->dev; |
1858 | u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); | |
1dba99f4 VS |
1859 | |
1860 | I915_WRITE(reg, I915_READ(reg)); | |
1861 | POSTING_READ(reg); | |
d74362c9 KP |
1862 | } |
1863 | ||
b24e7179 | 1864 | /** |
d1de00ef | 1865 | * intel_enable_primary_plane - enable the primary plane on a given pipe |
b24e7179 JB |
1866 | * @dev_priv: i915 private structure |
1867 | * @plane: plane to enable | |
1868 | * @pipe: pipe being fed | |
1869 | * | |
1870 | * Enable @plane on @pipe, making sure that @pipe is running first. | |
1871 | */ | |
d1de00ef VS |
1872 | static void intel_enable_primary_plane(struct drm_i915_private *dev_priv, |
1873 | enum plane plane, enum pipe pipe) | |
b24e7179 | 1874 | { |
939c2fe8 VS |
1875 | struct intel_crtc *intel_crtc = |
1876 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
b24e7179 JB |
1877 | int reg; |
1878 | u32 val; | |
1879 | ||
1880 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
1881 | assert_pipe_enabled(dev_priv, pipe); | |
1882 | ||
4c445e0e | 1883 | WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n"); |
0037f71c | 1884 | |
4c445e0e | 1885 | intel_crtc->primary_enabled = true; |
939c2fe8 | 1886 | |
b24e7179 JB |
1887 | reg = DSPCNTR(plane); |
1888 | val = I915_READ(reg); | |
00d70b15 CW |
1889 | if (val & DISPLAY_PLANE_ENABLE) |
1890 | return; | |
1891 | ||
1892 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); | |
1dba99f4 | 1893 | intel_flush_primary_plane(dev_priv, plane); |
b24e7179 JB |
1894 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1895 | } | |
1896 | ||
b24e7179 | 1897 | /** |
d1de00ef | 1898 | * intel_disable_primary_plane - disable the primary plane |
b24e7179 JB |
1899 | * @dev_priv: i915 private structure |
1900 | * @plane: plane to disable | |
1901 | * @pipe: pipe consuming the data | |
1902 | * | |
1903 | * Disable @plane; should be an independent operation. | |
1904 | */ | |
d1de00ef VS |
1905 | static void intel_disable_primary_plane(struct drm_i915_private *dev_priv, |
1906 | enum plane plane, enum pipe pipe) | |
b24e7179 | 1907 | { |
939c2fe8 VS |
1908 | struct intel_crtc *intel_crtc = |
1909 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
b24e7179 JB |
1910 | int reg; |
1911 | u32 val; | |
1912 | ||
4c445e0e | 1913 | WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n"); |
0037f71c | 1914 | |
4c445e0e | 1915 | intel_crtc->primary_enabled = false; |
939c2fe8 | 1916 | |
b24e7179 JB |
1917 | reg = DSPCNTR(plane); |
1918 | val = I915_READ(reg); | |
00d70b15 CW |
1919 | if ((val & DISPLAY_PLANE_ENABLE) == 0) |
1920 | return; | |
1921 | ||
1922 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); | |
1dba99f4 | 1923 | intel_flush_primary_plane(dev_priv, plane); |
b24e7179 JB |
1924 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1925 | } | |
1926 | ||
693db184 CW |
1927 | static bool need_vtd_wa(struct drm_device *dev) |
1928 | { | |
1929 | #ifdef CONFIG_INTEL_IOMMU | |
1930 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
1931 | return true; | |
1932 | #endif | |
1933 | return false; | |
1934 | } | |
1935 | ||
a57ce0b2 JB |
1936 | static int intel_align_height(struct drm_device *dev, int height, bool tiled) |
1937 | { | |
1938 | int tile_height; | |
1939 | ||
1940 | tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1; | |
1941 | return ALIGN(height, tile_height); | |
1942 | } | |
1943 | ||
127bd2ac | 1944 | int |
48b956c5 | 1945 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
05394f39 | 1946 | struct drm_i915_gem_object *obj, |
919926ae | 1947 | struct intel_ring_buffer *pipelined) |
6b95a207 | 1948 | { |
ce453d81 | 1949 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
1950 | u32 alignment; |
1951 | int ret; | |
1952 | ||
05394f39 | 1953 | switch (obj->tiling_mode) { |
6b95a207 | 1954 | case I915_TILING_NONE: |
534843da CW |
1955 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
1956 | alignment = 128 * 1024; | |
a6c45cf0 | 1957 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
1958 | alignment = 4 * 1024; |
1959 | else | |
1960 | alignment = 64 * 1024; | |
6b95a207 KH |
1961 | break; |
1962 | case I915_TILING_X: | |
1963 | /* pin() will align the object as required by fence */ | |
1964 | alignment = 0; | |
1965 | break; | |
1966 | case I915_TILING_Y: | |
80075d49 | 1967 | WARN(1, "Y tiled bo slipped through, driver bug!\n"); |
6b95a207 KH |
1968 | return -EINVAL; |
1969 | default: | |
1970 | BUG(); | |
1971 | } | |
1972 | ||
693db184 CW |
1973 | /* Note that the w/a also requires 64 PTE of padding following the |
1974 | * bo. We currently fill all unused PTE with the shadow page and so | |
1975 | * we should always have valid PTE following the scanout preventing | |
1976 | * the VT-d warning. | |
1977 | */ | |
1978 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
1979 | alignment = 256 * 1024; | |
1980 | ||
ce453d81 | 1981 | dev_priv->mm.interruptible = false; |
2da3b9b9 | 1982 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
48b956c5 | 1983 | if (ret) |
ce453d81 | 1984 | goto err_interruptible; |
6b95a207 KH |
1985 | |
1986 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
1987 | * fence, whereas 965+ only requires a fence if using | |
1988 | * framebuffer compression. For simplicity, we always install | |
1989 | * a fence as the cost is not that onerous. | |
1990 | */ | |
06d98131 | 1991 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
1992 | if (ret) |
1993 | goto err_unpin; | |
1690e1eb | 1994 | |
9a5a53b3 | 1995 | i915_gem_object_pin_fence(obj); |
6b95a207 | 1996 | |
ce453d81 | 1997 | dev_priv->mm.interruptible = true; |
6b95a207 | 1998 | return 0; |
48b956c5 CW |
1999 | |
2000 | err_unpin: | |
cc98b413 | 2001 | i915_gem_object_unpin_from_display_plane(obj); |
ce453d81 CW |
2002 | err_interruptible: |
2003 | dev_priv->mm.interruptible = true; | |
48b956c5 | 2004 | return ret; |
6b95a207 KH |
2005 | } |
2006 | ||
1690e1eb CW |
2007 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
2008 | { | |
2009 | i915_gem_object_unpin_fence(obj); | |
cc98b413 | 2010 | i915_gem_object_unpin_from_display_plane(obj); |
1690e1eb CW |
2011 | } |
2012 | ||
c2c75131 DV |
2013 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2014 | * is assumed to be a power-of-two. */ | |
bc752862 CW |
2015 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
2016 | unsigned int tiling_mode, | |
2017 | unsigned int cpp, | |
2018 | unsigned int pitch) | |
c2c75131 | 2019 | { |
bc752862 CW |
2020 | if (tiling_mode != I915_TILING_NONE) { |
2021 | unsigned int tile_rows, tiles; | |
c2c75131 | 2022 | |
bc752862 CW |
2023 | tile_rows = *y / 8; |
2024 | *y %= 8; | |
c2c75131 | 2025 | |
bc752862 CW |
2026 | tiles = *x / (512/cpp); |
2027 | *x %= 512/cpp; | |
2028 | ||
2029 | return tile_rows * pitch * 8 + tiles * 4096; | |
2030 | } else { | |
2031 | unsigned int offset; | |
2032 | ||
2033 | offset = *y * pitch + *x * cpp; | |
2034 | *y = 0; | |
2035 | *x = (offset & 4095) / cpp; | |
2036 | return offset & -4096; | |
2037 | } | |
c2c75131 DV |
2038 | } |
2039 | ||
17638cd6 JB |
2040 | static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
2041 | int x, int y) | |
81255565 JB |
2042 | { |
2043 | struct drm_device *dev = crtc->dev; | |
2044 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2045 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2046 | struct intel_framebuffer *intel_fb; | |
05394f39 | 2047 | struct drm_i915_gem_object *obj; |
81255565 | 2048 | int plane = intel_crtc->plane; |
e506a0c6 | 2049 | unsigned long linear_offset; |
81255565 | 2050 | u32 dspcntr; |
5eddb70b | 2051 | u32 reg; |
81255565 JB |
2052 | |
2053 | switch (plane) { | |
2054 | case 0: | |
2055 | case 1: | |
2056 | break; | |
2057 | default: | |
84f44ce7 | 2058 | DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane)); |
81255565 JB |
2059 | return -EINVAL; |
2060 | } | |
2061 | ||
2062 | intel_fb = to_intel_framebuffer(fb); | |
2063 | obj = intel_fb->obj; | |
81255565 | 2064 | |
5eddb70b CW |
2065 | reg = DSPCNTR(plane); |
2066 | dspcntr = I915_READ(reg); | |
81255565 JB |
2067 | /* Mask out pixel format bits in case we change it */ |
2068 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
57779d06 VS |
2069 | switch (fb->pixel_format) { |
2070 | case DRM_FORMAT_C8: | |
81255565 JB |
2071 | dspcntr |= DISPPLANE_8BPP; |
2072 | break; | |
57779d06 VS |
2073 | case DRM_FORMAT_XRGB1555: |
2074 | case DRM_FORMAT_ARGB1555: | |
2075 | dspcntr |= DISPPLANE_BGRX555; | |
81255565 | 2076 | break; |
57779d06 VS |
2077 | case DRM_FORMAT_RGB565: |
2078 | dspcntr |= DISPPLANE_BGRX565; | |
2079 | break; | |
2080 | case DRM_FORMAT_XRGB8888: | |
2081 | case DRM_FORMAT_ARGB8888: | |
2082 | dspcntr |= DISPPLANE_BGRX888; | |
2083 | break; | |
2084 | case DRM_FORMAT_XBGR8888: | |
2085 | case DRM_FORMAT_ABGR8888: | |
2086 | dspcntr |= DISPPLANE_RGBX888; | |
2087 | break; | |
2088 | case DRM_FORMAT_XRGB2101010: | |
2089 | case DRM_FORMAT_ARGB2101010: | |
2090 | dspcntr |= DISPPLANE_BGRX101010; | |
2091 | break; | |
2092 | case DRM_FORMAT_XBGR2101010: | |
2093 | case DRM_FORMAT_ABGR2101010: | |
2094 | dspcntr |= DISPPLANE_RGBX101010; | |
81255565 JB |
2095 | break; |
2096 | default: | |
baba133a | 2097 | BUG(); |
81255565 | 2098 | } |
57779d06 | 2099 | |
a6c45cf0 | 2100 | if (INTEL_INFO(dev)->gen >= 4) { |
05394f39 | 2101 | if (obj->tiling_mode != I915_TILING_NONE) |
81255565 JB |
2102 | dspcntr |= DISPPLANE_TILED; |
2103 | else | |
2104 | dspcntr &= ~DISPPLANE_TILED; | |
2105 | } | |
2106 | ||
de1aa629 VS |
2107 | if (IS_G4X(dev)) |
2108 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2109 | ||
5eddb70b | 2110 | I915_WRITE(reg, dspcntr); |
81255565 | 2111 | |
e506a0c6 | 2112 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
81255565 | 2113 | |
c2c75131 DV |
2114 | if (INTEL_INFO(dev)->gen >= 4) { |
2115 | intel_crtc->dspaddr_offset = | |
bc752862 CW |
2116 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2117 | fb->bits_per_pixel / 8, | |
2118 | fb->pitches[0]); | |
c2c75131 DV |
2119 | linear_offset -= intel_crtc->dspaddr_offset; |
2120 | } else { | |
e506a0c6 | 2121 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2122 | } |
e506a0c6 | 2123 | |
f343c5f6 BW |
2124 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2125 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2126 | fb->pitches[0]); | |
01f2c773 | 2127 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2128 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2129 | I915_WRITE(DSPSURF(plane), |
2130 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2131 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2132 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2133 | } else |
f343c5f6 | 2134 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2135 | POSTING_READ(reg); |
81255565 | 2136 | |
17638cd6 JB |
2137 | return 0; |
2138 | } | |
2139 | ||
2140 | static int ironlake_update_plane(struct drm_crtc *crtc, | |
2141 | struct drm_framebuffer *fb, int x, int y) | |
2142 | { | |
2143 | struct drm_device *dev = crtc->dev; | |
2144 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2145 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2146 | struct intel_framebuffer *intel_fb; | |
2147 | struct drm_i915_gem_object *obj; | |
2148 | int plane = intel_crtc->plane; | |
e506a0c6 | 2149 | unsigned long linear_offset; |
17638cd6 JB |
2150 | u32 dspcntr; |
2151 | u32 reg; | |
2152 | ||
2153 | switch (plane) { | |
2154 | case 0: | |
2155 | case 1: | |
27f8227b | 2156 | case 2: |
17638cd6 JB |
2157 | break; |
2158 | default: | |
84f44ce7 | 2159 | DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane)); |
17638cd6 JB |
2160 | return -EINVAL; |
2161 | } | |
2162 | ||
2163 | intel_fb = to_intel_framebuffer(fb); | |
2164 | obj = intel_fb->obj; | |
2165 | ||
2166 | reg = DSPCNTR(plane); | |
2167 | dspcntr = I915_READ(reg); | |
2168 | /* Mask out pixel format bits in case we change it */ | |
2169 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
57779d06 VS |
2170 | switch (fb->pixel_format) { |
2171 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2172 | dspcntr |= DISPPLANE_8BPP; |
2173 | break; | |
57779d06 VS |
2174 | case DRM_FORMAT_RGB565: |
2175 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2176 | break; |
57779d06 VS |
2177 | case DRM_FORMAT_XRGB8888: |
2178 | case DRM_FORMAT_ARGB8888: | |
2179 | dspcntr |= DISPPLANE_BGRX888; | |
2180 | break; | |
2181 | case DRM_FORMAT_XBGR8888: | |
2182 | case DRM_FORMAT_ABGR8888: | |
2183 | dspcntr |= DISPPLANE_RGBX888; | |
2184 | break; | |
2185 | case DRM_FORMAT_XRGB2101010: | |
2186 | case DRM_FORMAT_ARGB2101010: | |
2187 | dspcntr |= DISPPLANE_BGRX101010; | |
2188 | break; | |
2189 | case DRM_FORMAT_XBGR2101010: | |
2190 | case DRM_FORMAT_ABGR2101010: | |
2191 | dspcntr |= DISPPLANE_RGBX101010; | |
17638cd6 JB |
2192 | break; |
2193 | default: | |
baba133a | 2194 | BUG(); |
17638cd6 JB |
2195 | } |
2196 | ||
2197 | if (obj->tiling_mode != I915_TILING_NONE) | |
2198 | dspcntr |= DISPPLANE_TILED; | |
2199 | else | |
2200 | dspcntr &= ~DISPPLANE_TILED; | |
2201 | ||
b42c6009 | 2202 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
1f5d76db PZ |
2203 | dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE; |
2204 | else | |
2205 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
17638cd6 JB |
2206 | |
2207 | I915_WRITE(reg, dspcntr); | |
2208 | ||
e506a0c6 | 2209 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
c2c75131 | 2210 | intel_crtc->dspaddr_offset = |
bc752862 CW |
2211 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2212 | fb->bits_per_pixel / 8, | |
2213 | fb->pitches[0]); | |
c2c75131 | 2214 | linear_offset -= intel_crtc->dspaddr_offset; |
17638cd6 | 2215 | |
f343c5f6 BW |
2216 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2217 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2218 | fb->pitches[0]); | |
01f2c773 | 2219 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2220 | I915_WRITE(DSPSURF(plane), |
2221 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2222 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2223 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2224 | } else { | |
2225 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2226 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2227 | } | |
17638cd6 JB |
2228 | POSTING_READ(reg); |
2229 | ||
2230 | return 0; | |
2231 | } | |
2232 | ||
2233 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ | |
2234 | static int | |
2235 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
2236 | int x, int y, enum mode_set_atomic state) | |
2237 | { | |
2238 | struct drm_device *dev = crtc->dev; | |
2239 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 2240 | |
6b8e6ed0 CW |
2241 | if (dev_priv->display.disable_fbc) |
2242 | dev_priv->display.disable_fbc(dev); | |
3dec0095 | 2243 | intel_increase_pllclock(crtc); |
81255565 | 2244 | |
6b8e6ed0 | 2245 | return dev_priv->display.update_plane(crtc, fb, x, y); |
81255565 JB |
2246 | } |
2247 | ||
96a02917 VS |
2248 | void intel_display_handle_reset(struct drm_device *dev) |
2249 | { | |
2250 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2251 | struct drm_crtc *crtc; | |
2252 | ||
2253 | /* | |
2254 | * Flips in the rings have been nuked by the reset, | |
2255 | * so complete all pending flips so that user space | |
2256 | * will get its events and not get stuck. | |
2257 | * | |
2258 | * Also update the base address of all primary | |
2259 | * planes to the the last fb to make sure we're | |
2260 | * showing the correct fb after a reset. | |
2261 | * | |
2262 | * Need to make two loops over the crtcs so that we | |
2263 | * don't try to grab a crtc mutex before the | |
2264 | * pending_flip_queue really got woken up. | |
2265 | */ | |
2266 | ||
2267 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2268 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2269 | enum plane plane = intel_crtc->plane; | |
2270 | ||
2271 | intel_prepare_page_flip(dev, plane); | |
2272 | intel_finish_page_flip_plane(dev, plane); | |
2273 | } | |
2274 | ||
2275 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2276 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2277 | ||
2278 | mutex_lock(&crtc->mutex); | |
947fdaad CW |
2279 | /* |
2280 | * FIXME: Once we have proper support for primary planes (and | |
2281 | * disabling them without disabling the entire crtc) allow again | |
2282 | * a NULL crtc->fb. | |
2283 | */ | |
2284 | if (intel_crtc->active && crtc->fb) | |
96a02917 VS |
2285 | dev_priv->display.update_plane(crtc, crtc->fb, |
2286 | crtc->x, crtc->y); | |
2287 | mutex_unlock(&crtc->mutex); | |
2288 | } | |
2289 | } | |
2290 | ||
14667a4b CW |
2291 | static int |
2292 | intel_finish_fb(struct drm_framebuffer *old_fb) | |
2293 | { | |
2294 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; | |
2295 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2296 | bool was_interruptible = dev_priv->mm.interruptible; | |
2297 | int ret; | |
2298 | ||
14667a4b CW |
2299 | /* Big Hammer, we also need to ensure that any pending |
2300 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
2301 | * current scanout is retired before unpinning the old | |
2302 | * framebuffer. | |
2303 | * | |
2304 | * This should only fail upon a hung GPU, in which case we | |
2305 | * can safely continue. | |
2306 | */ | |
2307 | dev_priv->mm.interruptible = false; | |
2308 | ret = i915_gem_object_finish_gpu(obj); | |
2309 | dev_priv->mm.interruptible = was_interruptible; | |
2310 | ||
2311 | return ret; | |
2312 | } | |
2313 | ||
198598d0 VS |
2314 | static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y) |
2315 | { | |
2316 | struct drm_device *dev = crtc->dev; | |
2317 | struct drm_i915_master_private *master_priv; | |
2318 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2319 | ||
2320 | if (!dev->primary->master) | |
2321 | return; | |
2322 | ||
2323 | master_priv = dev->primary->master->driver_priv; | |
2324 | if (!master_priv->sarea_priv) | |
2325 | return; | |
2326 | ||
2327 | switch (intel_crtc->pipe) { | |
2328 | case 0: | |
2329 | master_priv->sarea_priv->pipeA_x = x; | |
2330 | master_priv->sarea_priv->pipeA_y = y; | |
2331 | break; | |
2332 | case 1: | |
2333 | master_priv->sarea_priv->pipeB_x = x; | |
2334 | master_priv->sarea_priv->pipeB_y = y; | |
2335 | break; | |
2336 | default: | |
2337 | break; | |
2338 | } | |
2339 | } | |
2340 | ||
5c3b82e2 | 2341 | static int |
3c4fdcfb | 2342 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
94352cf9 | 2343 | struct drm_framebuffer *fb) |
79e53945 JB |
2344 | { |
2345 | struct drm_device *dev = crtc->dev; | |
6b8e6ed0 | 2346 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 2347 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
94352cf9 | 2348 | struct drm_framebuffer *old_fb; |
5c3b82e2 | 2349 | int ret; |
79e53945 JB |
2350 | |
2351 | /* no fb bound */ | |
94352cf9 | 2352 | if (!fb) { |
a5071c2f | 2353 | DRM_ERROR("No FB bound\n"); |
5c3b82e2 CW |
2354 | return 0; |
2355 | } | |
2356 | ||
7eb552ae | 2357 | if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) { |
84f44ce7 VS |
2358 | DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n", |
2359 | plane_name(intel_crtc->plane), | |
2360 | INTEL_INFO(dev)->num_pipes); | |
5c3b82e2 | 2361 | return -EINVAL; |
79e53945 JB |
2362 | } |
2363 | ||
5c3b82e2 | 2364 | mutex_lock(&dev->struct_mutex); |
265db958 | 2365 | ret = intel_pin_and_fence_fb_obj(dev, |
94352cf9 | 2366 | to_intel_framebuffer(fb)->obj, |
919926ae | 2367 | NULL); |
5c3b82e2 CW |
2368 | if (ret != 0) { |
2369 | mutex_unlock(&dev->struct_mutex); | |
a5071c2f | 2370 | DRM_ERROR("pin & fence failed\n"); |
5c3b82e2 CW |
2371 | return ret; |
2372 | } | |
79e53945 | 2373 | |
bb2043de DL |
2374 | /* |
2375 | * Update pipe size and adjust fitter if needed: the reason for this is | |
2376 | * that in compute_mode_changes we check the native mode (not the pfit | |
2377 | * mode) to see if we can flip rather than do a full mode set. In the | |
2378 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
2379 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
2380 | * sized surface. | |
2381 | * | |
2382 | * To fix this properly, we need to hoist the checks up into | |
2383 | * compute_mode_changes (or above), check the actual pfit state and | |
2384 | * whether the platform allows pfit disable with pipe active, and only | |
2385 | * then update the pipesrc and pfit state, even on the flip path. | |
2386 | */ | |
d330a953 | 2387 | if (i915.fastboot) { |
d7bf63f2 DL |
2388 | const struct drm_display_mode *adjusted_mode = |
2389 | &intel_crtc->config.adjusted_mode; | |
2390 | ||
4d6a3e63 | 2391 | I915_WRITE(PIPESRC(intel_crtc->pipe), |
d7bf63f2 DL |
2392 | ((adjusted_mode->crtc_hdisplay - 1) << 16) | |
2393 | (adjusted_mode->crtc_vdisplay - 1)); | |
fd4daa9c | 2394 | if (!intel_crtc->config.pch_pfit.enabled && |
4d6a3e63 JB |
2395 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
2396 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
2397 | I915_WRITE(PF_CTL(intel_crtc->pipe), 0); | |
2398 | I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0); | |
2399 | I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0); | |
2400 | } | |
0637d60d JB |
2401 | intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay; |
2402 | intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay; | |
4d6a3e63 JB |
2403 | } |
2404 | ||
94352cf9 | 2405 | ret = dev_priv->display.update_plane(crtc, fb, x, y); |
4e6cfefc | 2406 | if (ret) { |
94352cf9 | 2407 | intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj); |
5c3b82e2 | 2408 | mutex_unlock(&dev->struct_mutex); |
a5071c2f | 2409 | DRM_ERROR("failed to update base address\n"); |
4e6cfefc | 2410 | return ret; |
79e53945 | 2411 | } |
3c4fdcfb | 2412 | |
94352cf9 DV |
2413 | old_fb = crtc->fb; |
2414 | crtc->fb = fb; | |
6c4c86f5 DV |
2415 | crtc->x = x; |
2416 | crtc->y = y; | |
94352cf9 | 2417 | |
b7f1de28 | 2418 | if (old_fb) { |
d7697eea DV |
2419 | if (intel_crtc->active && old_fb != fb) |
2420 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1690e1eb | 2421 | intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); |
b7f1de28 | 2422 | } |
652c393a | 2423 | |
6b8e6ed0 | 2424 | intel_update_fbc(dev); |
4906557e | 2425 | intel_edp_psr_update(dev); |
5c3b82e2 | 2426 | mutex_unlock(&dev->struct_mutex); |
79e53945 | 2427 | |
198598d0 | 2428 | intel_crtc_update_sarea_pos(crtc, x, y); |
5c3b82e2 CW |
2429 | |
2430 | return 0; | |
79e53945 JB |
2431 | } |
2432 | ||
5e84e1a4 ZW |
2433 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
2434 | { | |
2435 | struct drm_device *dev = crtc->dev; | |
2436 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2437 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2438 | int pipe = intel_crtc->pipe; | |
2439 | u32 reg, temp; | |
2440 | ||
2441 | /* enable normal train */ | |
2442 | reg = FDI_TX_CTL(pipe); | |
2443 | temp = I915_READ(reg); | |
61e499bf | 2444 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
2445 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2446 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
2447 | } else { |
2448 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2449 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 2450 | } |
5e84e1a4 ZW |
2451 | I915_WRITE(reg, temp); |
2452 | ||
2453 | reg = FDI_RX_CTL(pipe); | |
2454 | temp = I915_READ(reg); | |
2455 | if (HAS_PCH_CPT(dev)) { | |
2456 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2457 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
2458 | } else { | |
2459 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2460 | temp |= FDI_LINK_TRAIN_NONE; | |
2461 | } | |
2462 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
2463 | ||
2464 | /* wait one idle pattern time */ | |
2465 | POSTING_READ(reg); | |
2466 | udelay(1000); | |
357555c0 JB |
2467 | |
2468 | /* IVB wants error correction enabled */ | |
2469 | if (IS_IVYBRIDGE(dev)) | |
2470 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
2471 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
2472 | } |
2473 | ||
1fbc0d78 | 2474 | static bool pipe_has_enabled_pch(struct intel_crtc *crtc) |
1e833f40 | 2475 | { |
1fbc0d78 DV |
2476 | return crtc->base.enabled && crtc->active && |
2477 | crtc->config.has_pch_encoder; | |
1e833f40 DV |
2478 | } |
2479 | ||
01a415fd DV |
2480 | static void ivb_modeset_global_resources(struct drm_device *dev) |
2481 | { | |
2482 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2483 | struct intel_crtc *pipe_B_crtc = | |
2484 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
2485 | struct intel_crtc *pipe_C_crtc = | |
2486 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]); | |
2487 | uint32_t temp; | |
2488 | ||
1e833f40 DV |
2489 | /* |
2490 | * When everything is off disable fdi C so that we could enable fdi B | |
2491 | * with all lanes. Note that we don't care about enabled pipes without | |
2492 | * an enabled pch encoder. | |
2493 | */ | |
2494 | if (!pipe_has_enabled_pch(pipe_B_crtc) && | |
2495 | !pipe_has_enabled_pch(pipe_C_crtc)) { | |
01a415fd DV |
2496 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
2497 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
2498 | ||
2499 | temp = I915_READ(SOUTH_CHICKEN1); | |
2500 | temp &= ~FDI_BC_BIFURCATION_SELECT; | |
2501 | DRM_DEBUG_KMS("disabling fdi C rx\n"); | |
2502 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
2503 | } | |
2504 | } | |
2505 | ||
8db9d77b ZW |
2506 | /* The FDI link training functions for ILK/Ibexpeak. */ |
2507 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
2508 | { | |
2509 | struct drm_device *dev = crtc->dev; | |
2510 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2511 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2512 | int pipe = intel_crtc->pipe; | |
0fc932b8 | 2513 | int plane = intel_crtc->plane; |
5eddb70b | 2514 | u32 reg, temp, tries; |
8db9d77b | 2515 | |
0fc932b8 JB |
2516 | /* FDI needs bits from pipe & plane first */ |
2517 | assert_pipe_enabled(dev_priv, pipe); | |
2518 | assert_plane_enabled(dev_priv, plane); | |
2519 | ||
e1a44743 AJ |
2520 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2521 | for train result */ | |
5eddb70b CW |
2522 | reg = FDI_RX_IMR(pipe); |
2523 | temp = I915_READ(reg); | |
e1a44743 AJ |
2524 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2525 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2526 | I915_WRITE(reg, temp); |
2527 | I915_READ(reg); | |
e1a44743 AJ |
2528 | udelay(150); |
2529 | ||
8db9d77b | 2530 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2531 | reg = FDI_TX_CTL(pipe); |
2532 | temp = I915_READ(reg); | |
627eb5a3 DV |
2533 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2534 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
2535 | temp &= ~FDI_LINK_TRAIN_NONE; |
2536 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 2537 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2538 | |
5eddb70b CW |
2539 | reg = FDI_RX_CTL(pipe); |
2540 | temp = I915_READ(reg); | |
8db9d77b ZW |
2541 | temp &= ~FDI_LINK_TRAIN_NONE; |
2542 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
2543 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2544 | ||
2545 | POSTING_READ(reg); | |
8db9d77b ZW |
2546 | udelay(150); |
2547 | ||
5b2adf89 | 2548 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
2549 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
2550 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
2551 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 2552 | |
5eddb70b | 2553 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2554 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2555 | temp = I915_READ(reg); |
8db9d77b ZW |
2556 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2557 | ||
2558 | if ((temp & FDI_RX_BIT_LOCK)) { | |
2559 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 2560 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
2561 | break; |
2562 | } | |
8db9d77b | 2563 | } |
e1a44743 | 2564 | if (tries == 5) |
5eddb70b | 2565 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2566 | |
2567 | /* Train 2 */ | |
5eddb70b CW |
2568 | reg = FDI_TX_CTL(pipe); |
2569 | temp = I915_READ(reg); | |
8db9d77b ZW |
2570 | temp &= ~FDI_LINK_TRAIN_NONE; |
2571 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2572 | I915_WRITE(reg, temp); |
8db9d77b | 2573 | |
5eddb70b CW |
2574 | reg = FDI_RX_CTL(pipe); |
2575 | temp = I915_READ(reg); | |
8db9d77b ZW |
2576 | temp &= ~FDI_LINK_TRAIN_NONE; |
2577 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2578 | I915_WRITE(reg, temp); |
8db9d77b | 2579 | |
5eddb70b CW |
2580 | POSTING_READ(reg); |
2581 | udelay(150); | |
8db9d77b | 2582 | |
5eddb70b | 2583 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2584 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2585 | temp = I915_READ(reg); |
8db9d77b ZW |
2586 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2587 | ||
2588 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 2589 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
2590 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2591 | break; | |
2592 | } | |
8db9d77b | 2593 | } |
e1a44743 | 2594 | if (tries == 5) |
5eddb70b | 2595 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2596 | |
2597 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 2598 | |
8db9d77b ZW |
2599 | } |
2600 | ||
0206e353 | 2601 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
2602 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
2603 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
2604 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
2605 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
2606 | }; | |
2607 | ||
2608 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
2609 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
2610 | { | |
2611 | struct drm_device *dev = crtc->dev; | |
2612 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2613 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2614 | int pipe = intel_crtc->pipe; | |
fa37d39e | 2615 | u32 reg, temp, i, retry; |
8db9d77b | 2616 | |
e1a44743 AJ |
2617 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2618 | for train result */ | |
5eddb70b CW |
2619 | reg = FDI_RX_IMR(pipe); |
2620 | temp = I915_READ(reg); | |
e1a44743 AJ |
2621 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2622 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2623 | I915_WRITE(reg, temp); |
2624 | ||
2625 | POSTING_READ(reg); | |
e1a44743 AJ |
2626 | udelay(150); |
2627 | ||
8db9d77b | 2628 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2629 | reg = FDI_TX_CTL(pipe); |
2630 | temp = I915_READ(reg); | |
627eb5a3 DV |
2631 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2632 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
2633 | temp &= ~FDI_LINK_TRAIN_NONE; |
2634 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2635 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2636 | /* SNB-B */ | |
2637 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 2638 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2639 | |
d74cf324 DV |
2640 | I915_WRITE(FDI_RX_MISC(pipe), |
2641 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
2642 | ||
5eddb70b CW |
2643 | reg = FDI_RX_CTL(pipe); |
2644 | temp = I915_READ(reg); | |
8db9d77b ZW |
2645 | if (HAS_PCH_CPT(dev)) { |
2646 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2647 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2648 | } else { | |
2649 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2650 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2651 | } | |
5eddb70b CW |
2652 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2653 | ||
2654 | POSTING_READ(reg); | |
8db9d77b ZW |
2655 | udelay(150); |
2656 | ||
0206e353 | 2657 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2658 | reg = FDI_TX_CTL(pipe); |
2659 | temp = I915_READ(reg); | |
8db9d77b ZW |
2660 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2661 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2662 | I915_WRITE(reg, temp); |
2663 | ||
2664 | POSTING_READ(reg); | |
8db9d77b ZW |
2665 | udelay(500); |
2666 | ||
fa37d39e SP |
2667 | for (retry = 0; retry < 5; retry++) { |
2668 | reg = FDI_RX_IIR(pipe); | |
2669 | temp = I915_READ(reg); | |
2670 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2671 | if (temp & FDI_RX_BIT_LOCK) { | |
2672 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
2673 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
2674 | break; | |
2675 | } | |
2676 | udelay(50); | |
8db9d77b | 2677 | } |
fa37d39e SP |
2678 | if (retry < 5) |
2679 | break; | |
8db9d77b ZW |
2680 | } |
2681 | if (i == 4) | |
5eddb70b | 2682 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2683 | |
2684 | /* Train 2 */ | |
5eddb70b CW |
2685 | reg = FDI_TX_CTL(pipe); |
2686 | temp = I915_READ(reg); | |
8db9d77b ZW |
2687 | temp &= ~FDI_LINK_TRAIN_NONE; |
2688 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2689 | if (IS_GEN6(dev)) { | |
2690 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2691 | /* SNB-B */ | |
2692 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
2693 | } | |
5eddb70b | 2694 | I915_WRITE(reg, temp); |
8db9d77b | 2695 | |
5eddb70b CW |
2696 | reg = FDI_RX_CTL(pipe); |
2697 | temp = I915_READ(reg); | |
8db9d77b ZW |
2698 | if (HAS_PCH_CPT(dev)) { |
2699 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2700 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
2701 | } else { | |
2702 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2703 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2704 | } | |
5eddb70b CW |
2705 | I915_WRITE(reg, temp); |
2706 | ||
2707 | POSTING_READ(reg); | |
8db9d77b ZW |
2708 | udelay(150); |
2709 | ||
0206e353 | 2710 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2711 | reg = FDI_TX_CTL(pipe); |
2712 | temp = I915_READ(reg); | |
8db9d77b ZW |
2713 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2714 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2715 | I915_WRITE(reg, temp); |
2716 | ||
2717 | POSTING_READ(reg); | |
8db9d77b ZW |
2718 | udelay(500); |
2719 | ||
fa37d39e SP |
2720 | for (retry = 0; retry < 5; retry++) { |
2721 | reg = FDI_RX_IIR(pipe); | |
2722 | temp = I915_READ(reg); | |
2723 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2724 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
2725 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
2726 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
2727 | break; | |
2728 | } | |
2729 | udelay(50); | |
8db9d77b | 2730 | } |
fa37d39e SP |
2731 | if (retry < 5) |
2732 | break; | |
8db9d77b ZW |
2733 | } |
2734 | if (i == 4) | |
5eddb70b | 2735 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2736 | |
2737 | DRM_DEBUG_KMS("FDI train done.\n"); | |
2738 | } | |
2739 | ||
357555c0 JB |
2740 | /* Manual link training for Ivy Bridge A0 parts */ |
2741 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
2742 | { | |
2743 | struct drm_device *dev = crtc->dev; | |
2744 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2745 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2746 | int pipe = intel_crtc->pipe; | |
139ccd3f | 2747 | u32 reg, temp, i, j; |
357555c0 JB |
2748 | |
2749 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
2750 | for train result */ | |
2751 | reg = FDI_RX_IMR(pipe); | |
2752 | temp = I915_READ(reg); | |
2753 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
2754 | temp &= ~FDI_RX_BIT_LOCK; | |
2755 | I915_WRITE(reg, temp); | |
2756 | ||
2757 | POSTING_READ(reg); | |
2758 | udelay(150); | |
2759 | ||
01a415fd DV |
2760 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
2761 | I915_READ(FDI_RX_IIR(pipe))); | |
2762 | ||
139ccd3f JB |
2763 | /* Try each vswing and preemphasis setting twice before moving on */ |
2764 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
2765 | /* disable first in case we need to retry */ | |
2766 | reg = FDI_TX_CTL(pipe); | |
2767 | temp = I915_READ(reg); | |
2768 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
2769 | temp &= ~FDI_TX_ENABLE; | |
2770 | I915_WRITE(reg, temp); | |
357555c0 | 2771 | |
139ccd3f JB |
2772 | reg = FDI_RX_CTL(pipe); |
2773 | temp = I915_READ(reg); | |
2774 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
2775 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2776 | temp &= ~FDI_RX_ENABLE; | |
2777 | I915_WRITE(reg, temp); | |
357555c0 | 2778 | |
139ccd3f | 2779 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
2780 | reg = FDI_TX_CTL(pipe); |
2781 | temp = I915_READ(reg); | |
139ccd3f JB |
2782 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2783 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
2784 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; | |
357555c0 | 2785 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
2786 | temp |= snb_b_fdi_train_param[j/2]; |
2787 | temp |= FDI_COMPOSITE_SYNC; | |
2788 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 2789 | |
139ccd3f JB |
2790 | I915_WRITE(FDI_RX_MISC(pipe), |
2791 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 2792 | |
139ccd3f | 2793 | reg = FDI_RX_CTL(pipe); |
357555c0 | 2794 | temp = I915_READ(reg); |
139ccd3f JB |
2795 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
2796 | temp |= FDI_COMPOSITE_SYNC; | |
2797 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 2798 | |
139ccd3f JB |
2799 | POSTING_READ(reg); |
2800 | udelay(1); /* should be 0.5us */ | |
357555c0 | 2801 | |
139ccd3f JB |
2802 | for (i = 0; i < 4; i++) { |
2803 | reg = FDI_RX_IIR(pipe); | |
2804 | temp = I915_READ(reg); | |
2805 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 2806 | |
139ccd3f JB |
2807 | if (temp & FDI_RX_BIT_LOCK || |
2808 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
2809 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
2810 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
2811 | i); | |
2812 | break; | |
2813 | } | |
2814 | udelay(1); /* should be 0.5us */ | |
2815 | } | |
2816 | if (i == 4) { | |
2817 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
2818 | continue; | |
2819 | } | |
357555c0 | 2820 | |
139ccd3f | 2821 | /* Train 2 */ |
357555c0 JB |
2822 | reg = FDI_TX_CTL(pipe); |
2823 | temp = I915_READ(reg); | |
139ccd3f JB |
2824 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2825 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
2826 | I915_WRITE(reg, temp); | |
2827 | ||
2828 | reg = FDI_RX_CTL(pipe); | |
2829 | temp = I915_READ(reg); | |
2830 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2831 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
2832 | I915_WRITE(reg, temp); |
2833 | ||
2834 | POSTING_READ(reg); | |
139ccd3f | 2835 | udelay(2); /* should be 1.5us */ |
357555c0 | 2836 | |
139ccd3f JB |
2837 | for (i = 0; i < 4; i++) { |
2838 | reg = FDI_RX_IIR(pipe); | |
2839 | temp = I915_READ(reg); | |
2840 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 2841 | |
139ccd3f JB |
2842 | if (temp & FDI_RX_SYMBOL_LOCK || |
2843 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
2844 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
2845 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
2846 | i); | |
2847 | goto train_done; | |
2848 | } | |
2849 | udelay(2); /* should be 1.5us */ | |
357555c0 | 2850 | } |
139ccd3f JB |
2851 | if (i == 4) |
2852 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 2853 | } |
357555c0 | 2854 | |
139ccd3f | 2855 | train_done: |
357555c0 JB |
2856 | DRM_DEBUG_KMS("FDI train done.\n"); |
2857 | } | |
2858 | ||
88cefb6c | 2859 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 2860 | { |
88cefb6c | 2861 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 2862 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 2863 | int pipe = intel_crtc->pipe; |
5eddb70b | 2864 | u32 reg, temp; |
79e53945 | 2865 | |
c64e311e | 2866 | |
c98e9dcf | 2867 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
2868 | reg = FDI_RX_CTL(pipe); |
2869 | temp = I915_READ(reg); | |
627eb5a3 DV |
2870 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
2871 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
dfd07d72 | 2872 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
2873 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
2874 | ||
2875 | POSTING_READ(reg); | |
c98e9dcf JB |
2876 | udelay(200); |
2877 | ||
2878 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
2879 | temp = I915_READ(reg); |
2880 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
2881 | ||
2882 | POSTING_READ(reg); | |
c98e9dcf JB |
2883 | udelay(200); |
2884 | ||
20749730 PZ |
2885 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
2886 | reg = FDI_TX_CTL(pipe); | |
2887 | temp = I915_READ(reg); | |
2888 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
2889 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 2890 | |
20749730 PZ |
2891 | POSTING_READ(reg); |
2892 | udelay(100); | |
6be4a607 | 2893 | } |
0e23b99d JB |
2894 | } |
2895 | ||
88cefb6c DV |
2896 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
2897 | { | |
2898 | struct drm_device *dev = intel_crtc->base.dev; | |
2899 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2900 | int pipe = intel_crtc->pipe; | |
2901 | u32 reg, temp; | |
2902 | ||
2903 | /* Switch from PCDclk to Rawclk */ | |
2904 | reg = FDI_RX_CTL(pipe); | |
2905 | temp = I915_READ(reg); | |
2906 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
2907 | ||
2908 | /* Disable CPU FDI TX PLL */ | |
2909 | reg = FDI_TX_CTL(pipe); | |
2910 | temp = I915_READ(reg); | |
2911 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
2912 | ||
2913 | POSTING_READ(reg); | |
2914 | udelay(100); | |
2915 | ||
2916 | reg = FDI_RX_CTL(pipe); | |
2917 | temp = I915_READ(reg); | |
2918 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
2919 | ||
2920 | /* Wait for the clocks to turn off. */ | |
2921 | POSTING_READ(reg); | |
2922 | udelay(100); | |
2923 | } | |
2924 | ||
0fc932b8 JB |
2925 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
2926 | { | |
2927 | struct drm_device *dev = crtc->dev; | |
2928 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2929 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2930 | int pipe = intel_crtc->pipe; | |
2931 | u32 reg, temp; | |
2932 | ||
2933 | /* disable CPU FDI tx and PCH FDI rx */ | |
2934 | reg = FDI_TX_CTL(pipe); | |
2935 | temp = I915_READ(reg); | |
2936 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
2937 | POSTING_READ(reg); | |
2938 | ||
2939 | reg = FDI_RX_CTL(pipe); | |
2940 | temp = I915_READ(reg); | |
2941 | temp &= ~(0x7 << 16); | |
dfd07d72 | 2942 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
2943 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
2944 | ||
2945 | POSTING_READ(reg); | |
2946 | udelay(100); | |
2947 | ||
2948 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
6f06ce18 JB |
2949 | if (HAS_PCH_IBX(dev)) { |
2950 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); | |
6f06ce18 | 2951 | } |
0fc932b8 JB |
2952 | |
2953 | /* still set train pattern 1 */ | |
2954 | reg = FDI_TX_CTL(pipe); | |
2955 | temp = I915_READ(reg); | |
2956 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2957 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2958 | I915_WRITE(reg, temp); | |
2959 | ||
2960 | reg = FDI_RX_CTL(pipe); | |
2961 | temp = I915_READ(reg); | |
2962 | if (HAS_PCH_CPT(dev)) { | |
2963 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2964 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2965 | } else { | |
2966 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2967 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2968 | } | |
2969 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
2970 | temp &= ~(0x07 << 16); | |
dfd07d72 | 2971 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
2972 | I915_WRITE(reg, temp); |
2973 | ||
2974 | POSTING_READ(reg); | |
2975 | udelay(100); | |
2976 | } | |
2977 | ||
5bb61643 CW |
2978 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
2979 | { | |
2980 | struct drm_device *dev = crtc->dev; | |
2981 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10d83730 | 2982 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5bb61643 CW |
2983 | unsigned long flags; |
2984 | bool pending; | |
2985 | ||
10d83730 VS |
2986 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
2987 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
5bb61643 CW |
2988 | return false; |
2989 | ||
2990 | spin_lock_irqsave(&dev->event_lock, flags); | |
2991 | pending = to_intel_crtc(crtc)->unpin_work != NULL; | |
2992 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
2993 | ||
2994 | return pending; | |
2995 | } | |
2996 | ||
5dce5b93 CW |
2997 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
2998 | { | |
2999 | struct intel_crtc *crtc; | |
3000 | ||
3001 | /* Note that we don't need to be called with mode_config.lock here | |
3002 | * as our list of CRTC objects is static for the lifetime of the | |
3003 | * device and so cannot disappear as we iterate. Similarly, we can | |
3004 | * happily treat the predicates as racy, atomic checks as userspace | |
3005 | * cannot claim and pin a new fb without at least acquring the | |
3006 | * struct_mutex and so serialising with us. | |
3007 | */ | |
3008 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
3009 | if (atomic_read(&crtc->unpin_work_count) == 0) | |
3010 | continue; | |
3011 | ||
3012 | if (crtc->unpin_work) | |
3013 | intel_wait_for_vblank(dev, crtc->pipe); | |
3014 | ||
3015 | return true; | |
3016 | } | |
3017 | ||
3018 | return false; | |
3019 | } | |
3020 | ||
e6c3a2a6 CW |
3021 | static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
3022 | { | |
0f91128d | 3023 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3024 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 CW |
3025 | |
3026 | if (crtc->fb == NULL) | |
3027 | return; | |
3028 | ||
2c10d571 DV |
3029 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
3030 | ||
5bb61643 CW |
3031 | wait_event(dev_priv->pending_flip_queue, |
3032 | !intel_crtc_has_pending_flip(crtc)); | |
3033 | ||
0f91128d CW |
3034 | mutex_lock(&dev->struct_mutex); |
3035 | intel_finish_fb(crtc->fb); | |
3036 | mutex_unlock(&dev->struct_mutex); | |
e6c3a2a6 CW |
3037 | } |
3038 | ||
e615efe4 ED |
3039 | /* Program iCLKIP clock to the desired frequency */ |
3040 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3041 | { | |
3042 | struct drm_device *dev = crtc->dev; | |
3043 | struct drm_i915_private *dev_priv = dev->dev_private; | |
241bfc38 | 3044 | int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock; |
e615efe4 ED |
3045 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3046 | u32 temp; | |
3047 | ||
09153000 DV |
3048 | mutex_lock(&dev_priv->dpio_lock); |
3049 | ||
e615efe4 ED |
3050 | /* It is necessary to ungate the pixclk gate prior to programming |
3051 | * the divisors, and gate it back when it is done. | |
3052 | */ | |
3053 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3054 | ||
3055 | /* Disable SSCCTL */ | |
3056 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
3057 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
3058 | SBI_SSCCTL_DISABLE, | |
3059 | SBI_ICLK); | |
e615efe4 ED |
3060 | |
3061 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3062 | if (clock == 20000) { |
e615efe4 ED |
3063 | auxdiv = 1; |
3064 | divsel = 0x41; | |
3065 | phaseinc = 0x20; | |
3066 | } else { | |
3067 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3068 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3069 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3070 | * convert the virtual clock precision to KHz here for higher |
3071 | * precision. | |
3072 | */ | |
3073 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3074 | u32 iclk_pi_range = 64; | |
3075 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3076 | ||
12d7ceed | 3077 | desired_divisor = (iclk_virtual_root_freq / clock); |
e615efe4 ED |
3078 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3079 | pi_value = desired_divisor % iclk_pi_range; | |
3080 | ||
3081 | auxdiv = 0; | |
3082 | divsel = msb_divisor_value - 2; | |
3083 | phaseinc = pi_value; | |
3084 | } | |
3085 | ||
3086 | /* This should not happen with any sane values */ | |
3087 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3088 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3089 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3090 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3091 | ||
3092 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3093 | clock, |
e615efe4 ED |
3094 | auxdiv, |
3095 | divsel, | |
3096 | phasedir, | |
3097 | phaseinc); | |
3098 | ||
3099 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 3100 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
3101 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3102 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
3103 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
3104 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
3105 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
3106 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 3107 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
3108 | |
3109 | /* Program SSCAUXDIV */ | |
988d6ee8 | 3110 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
3111 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3112 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 3113 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
3114 | |
3115 | /* Enable modulator and associated divider */ | |
988d6ee8 | 3116 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 3117 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 3118 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
3119 | |
3120 | /* Wait for initialization time */ | |
3121 | udelay(24); | |
3122 | ||
3123 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 DV |
3124 | |
3125 | mutex_unlock(&dev_priv->dpio_lock); | |
e615efe4 ED |
3126 | } |
3127 | ||
275f01b2 DV |
3128 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
3129 | enum pipe pch_transcoder) | |
3130 | { | |
3131 | struct drm_device *dev = crtc->base.dev; | |
3132 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3133 | enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; | |
3134 | ||
3135 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
3136 | I915_READ(HTOTAL(cpu_transcoder))); | |
3137 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
3138 | I915_READ(HBLANK(cpu_transcoder))); | |
3139 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
3140 | I915_READ(HSYNC(cpu_transcoder))); | |
3141 | ||
3142 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
3143 | I915_READ(VTOTAL(cpu_transcoder))); | |
3144 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
3145 | I915_READ(VBLANK(cpu_transcoder))); | |
3146 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
3147 | I915_READ(VSYNC(cpu_transcoder))); | |
3148 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
3149 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
3150 | } | |
3151 | ||
1fbc0d78 DV |
3152 | static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev) |
3153 | { | |
3154 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3155 | uint32_t temp; | |
3156 | ||
3157 | temp = I915_READ(SOUTH_CHICKEN1); | |
3158 | if (temp & FDI_BC_BIFURCATION_SELECT) | |
3159 | return; | |
3160 | ||
3161 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
3162 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
3163 | ||
3164 | temp |= FDI_BC_BIFURCATION_SELECT; | |
3165 | DRM_DEBUG_KMS("enabling fdi C rx\n"); | |
3166 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
3167 | POSTING_READ(SOUTH_CHICKEN1); | |
3168 | } | |
3169 | ||
3170 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
3171 | { | |
3172 | struct drm_device *dev = intel_crtc->base.dev; | |
3173 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3174 | ||
3175 | switch (intel_crtc->pipe) { | |
3176 | case PIPE_A: | |
3177 | break; | |
3178 | case PIPE_B: | |
3179 | if (intel_crtc->config.fdi_lanes > 2) | |
3180 | WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); | |
3181 | else | |
3182 | cpt_enable_fdi_bc_bifurcation(dev); | |
3183 | ||
3184 | break; | |
3185 | case PIPE_C: | |
3186 | cpt_enable_fdi_bc_bifurcation(dev); | |
3187 | ||
3188 | break; | |
3189 | default: | |
3190 | BUG(); | |
3191 | } | |
3192 | } | |
3193 | ||
f67a559d JB |
3194 | /* |
3195 | * Enable PCH resources required for PCH ports: | |
3196 | * - PCH PLLs | |
3197 | * - FDI training & RX/TX | |
3198 | * - update transcoder timings | |
3199 | * - DP transcoding bits | |
3200 | * - transcoder | |
3201 | */ | |
3202 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
3203 | { |
3204 | struct drm_device *dev = crtc->dev; | |
3205 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3206 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3207 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 3208 | u32 reg, temp; |
2c07245f | 3209 | |
ab9412ba | 3210 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 3211 | |
1fbc0d78 DV |
3212 | if (IS_IVYBRIDGE(dev)) |
3213 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
3214 | ||
cd986abb DV |
3215 | /* Write the TU size bits before fdi link training, so that error |
3216 | * detection works. */ | |
3217 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
3218 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
3219 | ||
c98e9dcf | 3220 | /* For PCH output, training FDI link */ |
674cf967 | 3221 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 3222 | |
3ad8a208 DV |
3223 | /* We need to program the right clock selection before writing the pixel |
3224 | * mutliplier into the DPLL. */ | |
303b81e0 | 3225 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 3226 | u32 sel; |
4b645f14 | 3227 | |
c98e9dcf | 3228 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
3229 | temp |= TRANS_DPLL_ENABLE(pipe); |
3230 | sel = TRANS_DPLLB_SEL(pipe); | |
a43f6e0f | 3231 | if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
3232 | temp |= sel; |
3233 | else | |
3234 | temp &= ~sel; | |
c98e9dcf | 3235 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 3236 | } |
5eddb70b | 3237 | |
3ad8a208 DV |
3238 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
3239 | * transcoder, and we actually should do this to not upset any PCH | |
3240 | * transcoder that already use the clock when we share it. | |
3241 | * | |
3242 | * Note that enable_shared_dpll tries to do the right thing, but | |
3243 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
3244 | * the right LVDS enable sequence. */ | |
3245 | ironlake_enable_shared_dpll(intel_crtc); | |
3246 | ||
d9b6cb56 JB |
3247 | /* set transcoder timing, panel must allow it */ |
3248 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 3249 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 3250 | |
303b81e0 | 3251 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 3252 | |
c98e9dcf JB |
3253 | /* For PCH DP, enable TRANS_DP_CTL */ |
3254 | if (HAS_PCH_CPT(dev) && | |
417e822d KP |
3255 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
3256 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
dfd07d72 | 3257 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
5eddb70b CW |
3258 | reg = TRANS_DP_CTL(pipe); |
3259 | temp = I915_READ(reg); | |
3260 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
3261 | TRANS_DP_SYNC_MASK | |
3262 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
3263 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
3264 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 3265 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
3266 | |
3267 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 3268 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 3269 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 3270 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
3271 | |
3272 | switch (intel_trans_dp_port_sel(crtc)) { | |
3273 | case PCH_DP_B: | |
5eddb70b | 3274 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
3275 | break; |
3276 | case PCH_DP_C: | |
5eddb70b | 3277 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
3278 | break; |
3279 | case PCH_DP_D: | |
5eddb70b | 3280 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
3281 | break; |
3282 | default: | |
e95d41e1 | 3283 | BUG(); |
32f9d658 | 3284 | } |
2c07245f | 3285 | |
5eddb70b | 3286 | I915_WRITE(reg, temp); |
6be4a607 | 3287 | } |
b52eb4dc | 3288 | |
b8a4f404 | 3289 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
3290 | } |
3291 | ||
1507e5bd PZ |
3292 | static void lpt_pch_enable(struct drm_crtc *crtc) |
3293 | { | |
3294 | struct drm_device *dev = crtc->dev; | |
3295 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3296 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3b117c8f | 3297 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
1507e5bd | 3298 | |
ab9412ba | 3299 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 3300 | |
8c52b5e8 | 3301 | lpt_program_iclkip(crtc); |
1507e5bd | 3302 | |
0540e488 | 3303 | /* Set transcoder timing. */ |
275f01b2 | 3304 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 3305 | |
937bb610 | 3306 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
3307 | } |
3308 | ||
e2b78267 | 3309 | static void intel_put_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3310 | { |
e2b78267 | 3311 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
ee7b9f93 JB |
3312 | |
3313 | if (pll == NULL) | |
3314 | return; | |
3315 | ||
3316 | if (pll->refcount == 0) { | |
46edb027 | 3317 | WARN(1, "bad %s refcount\n", pll->name); |
ee7b9f93 JB |
3318 | return; |
3319 | } | |
3320 | ||
f4a091c7 DV |
3321 | if (--pll->refcount == 0) { |
3322 | WARN_ON(pll->on); | |
3323 | WARN_ON(pll->active); | |
3324 | } | |
3325 | ||
a43f6e0f | 3326 | crtc->config.shared_dpll = DPLL_ID_PRIVATE; |
ee7b9f93 JB |
3327 | } |
3328 | ||
b89a1d39 | 3329 | static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3330 | { |
e2b78267 DV |
3331 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
3332 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
3333 | enum intel_dpll_id i; | |
ee7b9f93 | 3334 | |
ee7b9f93 | 3335 | if (pll) { |
46edb027 DV |
3336 | DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n", |
3337 | crtc->base.base.id, pll->name); | |
e2b78267 | 3338 | intel_put_shared_dpll(crtc); |
ee7b9f93 JB |
3339 | } |
3340 | ||
98b6bd99 DV |
3341 | if (HAS_PCH_IBX(dev_priv->dev)) { |
3342 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 3343 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 3344 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 3345 | |
46edb027 DV |
3346 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
3347 | crtc->base.base.id, pll->name); | |
98b6bd99 DV |
3348 | |
3349 | goto found; | |
3350 | } | |
3351 | ||
e72f9fbf DV |
3352 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3353 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 JB |
3354 | |
3355 | /* Only want to check enabled timings first */ | |
3356 | if (pll->refcount == 0) | |
3357 | continue; | |
3358 | ||
b89a1d39 DV |
3359 | if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state, |
3360 | sizeof(pll->hw_state)) == 0) { | |
46edb027 | 3361 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n", |
e2b78267 | 3362 | crtc->base.base.id, |
46edb027 | 3363 | pll->name, pll->refcount, pll->active); |
ee7b9f93 JB |
3364 | |
3365 | goto found; | |
3366 | } | |
3367 | } | |
3368 | ||
3369 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
3370 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3371 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 | 3372 | if (pll->refcount == 0) { |
46edb027 DV |
3373 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
3374 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
3375 | goto found; |
3376 | } | |
3377 | } | |
3378 | ||
3379 | return NULL; | |
3380 | ||
3381 | found: | |
a43f6e0f | 3382 | crtc->config.shared_dpll = i; |
46edb027 DV |
3383 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
3384 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 3385 | |
cdbd2316 | 3386 | if (pll->active == 0) { |
66e985c0 DV |
3387 | memcpy(&pll->hw_state, &crtc->config.dpll_hw_state, |
3388 | sizeof(pll->hw_state)); | |
3389 | ||
46edb027 | 3390 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); |
cdbd2316 | 3391 | WARN_ON(pll->on); |
e9d6944e | 3392 | assert_shared_dpll_disabled(dev_priv, pll); |
ee7b9f93 | 3393 | |
15bdd4cf | 3394 | pll->mode_set(dev_priv, pll); |
cdbd2316 DV |
3395 | } |
3396 | pll->refcount++; | |
e04c7350 | 3397 | |
ee7b9f93 JB |
3398 | return pll; |
3399 | } | |
3400 | ||
a1520318 | 3401 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
3402 | { |
3403 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 3404 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
3405 | u32 temp; |
3406 | ||
3407 | temp = I915_READ(dslreg); | |
3408 | udelay(500); | |
3409 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 3410 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 3411 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
3412 | } |
3413 | } | |
3414 | ||
b074cec8 JB |
3415 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
3416 | { | |
3417 | struct drm_device *dev = crtc->base.dev; | |
3418 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3419 | int pipe = crtc->pipe; | |
3420 | ||
fd4daa9c | 3421 | if (crtc->config.pch_pfit.enabled) { |
b074cec8 JB |
3422 | /* Force use of hard-coded filter coefficients |
3423 | * as some pre-programmed values are broken, | |
3424 | * e.g. x201. | |
3425 | */ | |
3426 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
3427 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
3428 | PF_PIPE_SEL_IVB(pipe)); | |
3429 | else | |
3430 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
3431 | I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos); | |
3432 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size); | |
d4270e57 JB |
3433 | } |
3434 | } | |
3435 | ||
bb53d4ae VS |
3436 | static void intel_enable_planes(struct drm_crtc *crtc) |
3437 | { | |
3438 | struct drm_device *dev = crtc->dev; | |
3439 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
3440 | struct intel_plane *intel_plane; | |
3441 | ||
3442 | list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head) | |
3443 | if (intel_plane->pipe == pipe) | |
3444 | intel_plane_restore(&intel_plane->base); | |
3445 | } | |
3446 | ||
3447 | static void intel_disable_planes(struct drm_crtc *crtc) | |
3448 | { | |
3449 | struct drm_device *dev = crtc->dev; | |
3450 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
3451 | struct intel_plane *intel_plane; | |
3452 | ||
3453 | list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head) | |
3454 | if (intel_plane->pipe == pipe) | |
3455 | intel_plane_disable(&intel_plane->base); | |
3456 | } | |
3457 | ||
20bc8673 | 3458 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
3459 | { |
3460 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
3461 | ||
3462 | if (!crtc->config.ips_enabled) | |
3463 | return; | |
3464 | ||
3465 | /* We can only enable IPS after we enable a plane and wait for a vblank. | |
3466 | * We guarantee that the plane is enabled by calling intel_enable_ips | |
3467 | * only after intel_enable_plane. And intel_enable_plane already waits | |
3468 | * for a vblank, so all we need to do here is to enable the IPS bit. */ | |
3469 | assert_plane_enabled(dev_priv, crtc->plane); | |
2a114cc1 BW |
3470 | if (IS_BROADWELL(crtc->base.dev)) { |
3471 | mutex_lock(&dev_priv->rps.hw_lock); | |
3472 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
3473 | mutex_unlock(&dev_priv->rps.hw_lock); | |
3474 | /* Quoting Art Runyan: "its not safe to expect any particular | |
3475 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
3476 | * mailbox." Moreover, the mailbox may return a bogus state, |
3477 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
3478 | */ |
3479 | } else { | |
3480 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
3481 | /* The bit only becomes 1 in the next vblank, so this wait here | |
3482 | * is essentially intel_wait_for_vblank. If we don't have this | |
3483 | * and don't wait for vblanks until the end of crtc_enable, then | |
3484 | * the HW state readout code will complain that the expected | |
3485 | * IPS_CTL value is not the one we read. */ | |
3486 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
3487 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
3488 | } | |
d77e4531 PZ |
3489 | } |
3490 | ||
20bc8673 | 3491 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
3492 | { |
3493 | struct drm_device *dev = crtc->base.dev; | |
3494 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3495 | ||
3496 | if (!crtc->config.ips_enabled) | |
3497 | return; | |
3498 | ||
3499 | assert_plane_enabled(dev_priv, crtc->plane); | |
2a114cc1 BW |
3500 | if (IS_BROADWELL(crtc->base.dev)) { |
3501 | mutex_lock(&dev_priv->rps.hw_lock); | |
3502 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
3503 | mutex_unlock(&dev_priv->rps.hw_lock); | |
e59150dc | 3504 | } else { |
2a114cc1 | 3505 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
3506 | POSTING_READ(IPS_CTL); |
3507 | } | |
d77e4531 PZ |
3508 | |
3509 | /* We need to wait for a vblank before we can disable the plane. */ | |
3510 | intel_wait_for_vblank(dev, crtc->pipe); | |
3511 | } | |
3512 | ||
3513 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
3514 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
3515 | { | |
3516 | struct drm_device *dev = crtc->dev; | |
3517 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3518 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3519 | enum pipe pipe = intel_crtc->pipe; | |
3520 | int palreg = PALETTE(pipe); | |
3521 | int i; | |
3522 | bool reenable_ips = false; | |
3523 | ||
3524 | /* The clocks have to be on to load the palette. */ | |
3525 | if (!crtc->enabled || !intel_crtc->active) | |
3526 | return; | |
3527 | ||
3528 | if (!HAS_PCH_SPLIT(dev_priv->dev)) { | |
3529 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) | |
3530 | assert_dsi_pll_enabled(dev_priv); | |
3531 | else | |
3532 | assert_pll_enabled(dev_priv, pipe); | |
3533 | } | |
3534 | ||
3535 | /* use legacy palette for Ironlake */ | |
3536 | if (HAS_PCH_SPLIT(dev)) | |
3537 | palreg = LGC_PALETTE(pipe); | |
3538 | ||
3539 | /* Workaround : Do not read or write the pipe palette/gamma data while | |
3540 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
3541 | */ | |
41e6fc4c | 3542 | if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled && |
d77e4531 PZ |
3543 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
3544 | GAMMA_MODE_MODE_SPLIT)) { | |
3545 | hsw_disable_ips(intel_crtc); | |
3546 | reenable_ips = true; | |
3547 | } | |
3548 | ||
3549 | for (i = 0; i < 256; i++) { | |
3550 | I915_WRITE(palreg + 4 * i, | |
3551 | (intel_crtc->lut_r[i] << 16) | | |
3552 | (intel_crtc->lut_g[i] << 8) | | |
3553 | intel_crtc->lut_b[i]); | |
3554 | } | |
3555 | ||
3556 | if (reenable_ips) | |
3557 | hsw_enable_ips(intel_crtc); | |
3558 | } | |
3559 | ||
f67a559d JB |
3560 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
3561 | { | |
3562 | struct drm_device *dev = crtc->dev; | |
3563 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3564 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3565 | struct intel_encoder *encoder; |
f67a559d JB |
3566 | int pipe = intel_crtc->pipe; |
3567 | int plane = intel_crtc->plane; | |
f67a559d | 3568 | |
08a48469 DV |
3569 | WARN_ON(!crtc->enabled); |
3570 | ||
f67a559d JB |
3571 | if (intel_crtc->active) |
3572 | return; | |
3573 | ||
3574 | intel_crtc->active = true; | |
8664281b PZ |
3575 | |
3576 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
3577 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); | |
3578 | ||
f6736a1a | 3579 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
3580 | if (encoder->pre_enable) |
3581 | encoder->pre_enable(encoder); | |
f67a559d | 3582 | |
5bfe2ac0 | 3583 | if (intel_crtc->config.has_pch_encoder) { |
fff367c7 DV |
3584 | /* Note: FDI PLL enabling _must_ be done before we enable the |
3585 | * cpu pipes, hence this is separate from all the other fdi/pch | |
3586 | * enabling. */ | |
88cefb6c | 3587 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
3588 | } else { |
3589 | assert_fdi_tx_disabled(dev_priv, pipe); | |
3590 | assert_fdi_rx_disabled(dev_priv, pipe); | |
3591 | } | |
f67a559d | 3592 | |
b074cec8 | 3593 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 3594 | |
9c54c0dd JB |
3595 | /* |
3596 | * On ILK+ LUT must be loaded before the pipe is running but with | |
3597 | * clocks enabled | |
3598 | */ | |
3599 | intel_crtc_load_lut(crtc); | |
3600 | ||
f37fcc2a | 3601 | intel_update_watermarks(crtc); |
0372264a PZ |
3602 | intel_enable_pipe(intel_crtc, intel_crtc->config.has_pch_encoder, false, |
3603 | true); | |
d1de00ef | 3604 | intel_enable_primary_plane(dev_priv, plane, pipe); |
bb53d4ae | 3605 | intel_enable_planes(crtc); |
5c38d48c | 3606 | intel_crtc_update_cursor(crtc, true); |
f67a559d | 3607 | |
5bfe2ac0 | 3608 | if (intel_crtc->config.has_pch_encoder) |
f67a559d | 3609 | ironlake_pch_enable(crtc); |
c98e9dcf | 3610 | |
d1ebd816 | 3611 | mutex_lock(&dev->struct_mutex); |
bed4a673 | 3612 | intel_update_fbc(dev); |
d1ebd816 BW |
3613 | mutex_unlock(&dev->struct_mutex); |
3614 | ||
fa5c73b1 DV |
3615 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3616 | encoder->enable(encoder); | |
61b77ddd DV |
3617 | |
3618 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 3619 | cpt_verify_modeset(dev, intel_crtc->pipe); |
6ce94100 DV |
3620 | |
3621 | /* | |
3622 | * There seems to be a race in PCH platform hw (at least on some | |
3623 | * outputs) where an enabled pipe still completes any pageflip right | |
3624 | * away (as if the pipe is off) instead of waiting for vblank. As soon | |
3625 | * as the first vblank happend, everything works as expected. Hence just | |
3626 | * wait for one vblank before returning to avoid strange things | |
3627 | * happening. | |
3628 | */ | |
3629 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
6be4a607 JB |
3630 | } |
3631 | ||
42db64ef PZ |
3632 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
3633 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
3634 | { | |
f5adf94e | 3635 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
3636 | } |
3637 | ||
dda9a66a VS |
3638 | static void haswell_crtc_enable_planes(struct drm_crtc *crtc) |
3639 | { | |
3640 | struct drm_device *dev = crtc->dev; | |
3641 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3642 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3643 | int pipe = intel_crtc->pipe; | |
3644 | int plane = intel_crtc->plane; | |
3645 | ||
d1de00ef | 3646 | intel_enable_primary_plane(dev_priv, plane, pipe); |
dda9a66a VS |
3647 | intel_enable_planes(crtc); |
3648 | intel_crtc_update_cursor(crtc, true); | |
3649 | ||
3650 | hsw_enable_ips(intel_crtc); | |
3651 | ||
3652 | mutex_lock(&dev->struct_mutex); | |
3653 | intel_update_fbc(dev); | |
3654 | mutex_unlock(&dev->struct_mutex); | |
3655 | } | |
3656 | ||
3657 | static void haswell_crtc_disable_planes(struct drm_crtc *crtc) | |
3658 | { | |
3659 | struct drm_device *dev = crtc->dev; | |
3660 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3661 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3662 | int pipe = intel_crtc->pipe; | |
3663 | int plane = intel_crtc->plane; | |
3664 | ||
3665 | intel_crtc_wait_for_pending_flips(crtc); | |
3666 | drm_vblank_off(dev, pipe); | |
3667 | ||
3668 | /* FBC must be disabled before disabling the plane on HSW. */ | |
3669 | if (dev_priv->fbc.plane == plane) | |
3670 | intel_disable_fbc(dev); | |
3671 | ||
3672 | hsw_disable_ips(intel_crtc); | |
3673 | ||
3674 | intel_crtc_update_cursor(crtc, false); | |
3675 | intel_disable_planes(crtc); | |
d1de00ef | 3676 | intel_disable_primary_plane(dev_priv, plane, pipe); |
dda9a66a VS |
3677 | } |
3678 | ||
e4916946 PZ |
3679 | /* |
3680 | * This implements the workaround described in the "notes" section of the mode | |
3681 | * set sequence documentation. When going from no pipes or single pipe to | |
3682 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
3683 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
3684 | */ | |
3685 | static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) | |
3686 | { | |
3687 | struct drm_device *dev = crtc->base.dev; | |
3688 | struct intel_crtc *crtc_it, *other_active_crtc = NULL; | |
3689 | ||
3690 | /* We want to get the other_active_crtc only if there's only 1 other | |
3691 | * active crtc. */ | |
3692 | list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) { | |
3693 | if (!crtc_it->active || crtc_it == crtc) | |
3694 | continue; | |
3695 | ||
3696 | if (other_active_crtc) | |
3697 | return; | |
3698 | ||
3699 | other_active_crtc = crtc_it; | |
3700 | } | |
3701 | if (!other_active_crtc) | |
3702 | return; | |
3703 | ||
3704 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
3705 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
3706 | } | |
3707 | ||
4f771f10 PZ |
3708 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
3709 | { | |
3710 | struct drm_device *dev = crtc->dev; | |
3711 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3712 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3713 | struct intel_encoder *encoder; | |
3714 | int pipe = intel_crtc->pipe; | |
4f771f10 PZ |
3715 | |
3716 | WARN_ON(!crtc->enabled); | |
3717 | ||
3718 | if (intel_crtc->active) | |
3719 | return; | |
3720 | ||
3721 | intel_crtc->active = true; | |
8664281b PZ |
3722 | |
3723 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
3724 | if (intel_crtc->config.has_pch_encoder) | |
3725 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); | |
3726 | ||
5bfe2ac0 | 3727 | if (intel_crtc->config.has_pch_encoder) |
04945641 | 3728 | dev_priv->display.fdi_link_train(crtc); |
4f771f10 PZ |
3729 | |
3730 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3731 | if (encoder->pre_enable) | |
3732 | encoder->pre_enable(encoder); | |
3733 | ||
1f544388 | 3734 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 3735 | |
b074cec8 | 3736 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
3737 | |
3738 | /* | |
3739 | * On ILK+ LUT must be loaded before the pipe is running but with | |
3740 | * clocks enabled | |
3741 | */ | |
3742 | intel_crtc_load_lut(crtc); | |
3743 | ||
1f544388 | 3744 | intel_ddi_set_pipe_settings(crtc); |
8228c251 | 3745 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 3746 | |
f37fcc2a | 3747 | intel_update_watermarks(crtc); |
0372264a PZ |
3748 | intel_enable_pipe(intel_crtc, intel_crtc->config.has_pch_encoder, false, |
3749 | false); | |
42db64ef | 3750 | |
5bfe2ac0 | 3751 | if (intel_crtc->config.has_pch_encoder) |
1507e5bd | 3752 | lpt_pch_enable(crtc); |
4f771f10 | 3753 | |
8807e55b | 3754 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 3755 | encoder->enable(encoder); |
8807e55b JN |
3756 | intel_opregion_notify_encoder(encoder, true); |
3757 | } | |
4f771f10 | 3758 | |
e4916946 PZ |
3759 | /* If we change the relative order between pipe/planes enabling, we need |
3760 | * to change the workaround. */ | |
3761 | haswell_mode_set_planes_workaround(intel_crtc); | |
dda9a66a | 3762 | haswell_crtc_enable_planes(crtc); |
4f771f10 PZ |
3763 | } |
3764 | ||
3f8dce3a DV |
3765 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
3766 | { | |
3767 | struct drm_device *dev = crtc->base.dev; | |
3768 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3769 | int pipe = crtc->pipe; | |
3770 | ||
3771 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
3772 | * it's in use. The hw state code will make sure we get this right. */ | |
fd4daa9c | 3773 | if (crtc->config.pch_pfit.enabled) { |
3f8dce3a DV |
3774 | I915_WRITE(PF_CTL(pipe), 0); |
3775 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
3776 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
3777 | } | |
3778 | } | |
3779 | ||
6be4a607 JB |
3780 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
3781 | { | |
3782 | struct drm_device *dev = crtc->dev; | |
3783 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3784 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3785 | struct intel_encoder *encoder; |
6be4a607 JB |
3786 | int pipe = intel_crtc->pipe; |
3787 | int plane = intel_crtc->plane; | |
5eddb70b | 3788 | u32 reg, temp; |
b52eb4dc | 3789 | |
ef9c3aee | 3790 | |
f7abfe8b CW |
3791 | if (!intel_crtc->active) |
3792 | return; | |
3793 | ||
ea9d758d DV |
3794 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3795 | encoder->disable(encoder); | |
3796 | ||
e6c3a2a6 | 3797 | intel_crtc_wait_for_pending_flips(crtc); |
6be4a607 | 3798 | drm_vblank_off(dev, pipe); |
913d8d11 | 3799 | |
5c3fe8b0 | 3800 | if (dev_priv->fbc.plane == plane) |
973d04f9 | 3801 | intel_disable_fbc(dev); |
2c07245f | 3802 | |
0d5b8c61 | 3803 | intel_crtc_update_cursor(crtc, false); |
bb53d4ae | 3804 | intel_disable_planes(crtc); |
d1de00ef | 3805 | intel_disable_primary_plane(dev_priv, plane, pipe); |
0d5b8c61 | 3806 | |
d925c59a DV |
3807 | if (intel_crtc->config.has_pch_encoder) |
3808 | intel_set_pch_fifo_underrun_reporting(dev, pipe, false); | |
3809 | ||
b24e7179 | 3810 | intel_disable_pipe(dev_priv, pipe); |
32f9d658 | 3811 | |
3f8dce3a | 3812 | ironlake_pfit_disable(intel_crtc); |
2c07245f | 3813 | |
bf49ec8c DV |
3814 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3815 | if (encoder->post_disable) | |
3816 | encoder->post_disable(encoder); | |
2c07245f | 3817 | |
d925c59a DV |
3818 | if (intel_crtc->config.has_pch_encoder) { |
3819 | ironlake_fdi_disable(crtc); | |
913d8d11 | 3820 | |
d925c59a DV |
3821 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
3822 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); | |
6be4a607 | 3823 | |
d925c59a DV |
3824 | if (HAS_PCH_CPT(dev)) { |
3825 | /* disable TRANS_DP_CTL */ | |
3826 | reg = TRANS_DP_CTL(pipe); | |
3827 | temp = I915_READ(reg); | |
3828 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
3829 | TRANS_DP_PORT_SEL_MASK); | |
3830 | temp |= TRANS_DP_PORT_SEL_NONE; | |
3831 | I915_WRITE(reg, temp); | |
3832 | ||
3833 | /* disable DPLL_SEL */ | |
3834 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 3835 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 3836 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 3837 | } |
e3421a18 | 3838 | |
d925c59a | 3839 | /* disable PCH DPLL */ |
e72f9fbf | 3840 | intel_disable_shared_dpll(intel_crtc); |
8db9d77b | 3841 | |
d925c59a DV |
3842 | ironlake_fdi_pll_disable(intel_crtc); |
3843 | } | |
6b383a7f | 3844 | |
f7abfe8b | 3845 | intel_crtc->active = false; |
46ba614c | 3846 | intel_update_watermarks(crtc); |
d1ebd816 BW |
3847 | |
3848 | mutex_lock(&dev->struct_mutex); | |
6b383a7f | 3849 | intel_update_fbc(dev); |
d1ebd816 | 3850 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 3851 | } |
1b3c7a47 | 3852 | |
4f771f10 | 3853 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 3854 | { |
4f771f10 PZ |
3855 | struct drm_device *dev = crtc->dev; |
3856 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 3857 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 PZ |
3858 | struct intel_encoder *encoder; |
3859 | int pipe = intel_crtc->pipe; | |
3b117c8f | 3860 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee7b9f93 | 3861 | |
4f771f10 PZ |
3862 | if (!intel_crtc->active) |
3863 | return; | |
3864 | ||
dda9a66a VS |
3865 | haswell_crtc_disable_planes(crtc); |
3866 | ||
8807e55b JN |
3867 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
3868 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 3869 | encoder->disable(encoder); |
8807e55b | 3870 | } |
4f771f10 | 3871 | |
8664281b PZ |
3872 | if (intel_crtc->config.has_pch_encoder) |
3873 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false); | |
4f771f10 PZ |
3874 | intel_disable_pipe(dev_priv, pipe); |
3875 | ||
ad80a810 | 3876 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 3877 | |
3f8dce3a | 3878 | ironlake_pfit_disable(intel_crtc); |
4f771f10 | 3879 | |
1f544388 | 3880 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 PZ |
3881 | |
3882 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3883 | if (encoder->post_disable) | |
3884 | encoder->post_disable(encoder); | |
3885 | ||
88adfff1 | 3886 | if (intel_crtc->config.has_pch_encoder) { |
ab4d966c | 3887 | lpt_disable_pch_transcoder(dev_priv); |
8664281b | 3888 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
1ad960f2 | 3889 | intel_ddi_fdi_disable(crtc); |
83616634 | 3890 | } |
4f771f10 PZ |
3891 | |
3892 | intel_crtc->active = false; | |
46ba614c | 3893 | intel_update_watermarks(crtc); |
4f771f10 PZ |
3894 | |
3895 | mutex_lock(&dev->struct_mutex); | |
3896 | intel_update_fbc(dev); | |
3897 | mutex_unlock(&dev->struct_mutex); | |
3898 | } | |
3899 | ||
ee7b9f93 JB |
3900 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
3901 | { | |
3902 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e72f9fbf | 3903 | intel_put_shared_dpll(intel_crtc); |
ee7b9f93 JB |
3904 | } |
3905 | ||
6441ab5f PZ |
3906 | static void haswell_crtc_off(struct drm_crtc *crtc) |
3907 | { | |
3908 | intel_ddi_put_crtc_pll(crtc); | |
3909 | } | |
3910 | ||
02e792fb DV |
3911 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
3912 | { | |
02e792fb | 3913 | if (!enable && intel_crtc->overlay) { |
23f09ce3 | 3914 | struct drm_device *dev = intel_crtc->base.dev; |
ce453d81 | 3915 | struct drm_i915_private *dev_priv = dev->dev_private; |
03f77ea5 | 3916 | |
23f09ce3 | 3917 | mutex_lock(&dev->struct_mutex); |
ce453d81 CW |
3918 | dev_priv->mm.interruptible = false; |
3919 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
3920 | dev_priv->mm.interruptible = true; | |
23f09ce3 | 3921 | mutex_unlock(&dev->struct_mutex); |
02e792fb | 3922 | } |
02e792fb | 3923 | |
5dcdbcb0 CW |
3924 | /* Let userspace switch the overlay on again. In most cases userspace |
3925 | * has to recompute where to put it anyway. | |
3926 | */ | |
02e792fb DV |
3927 | } |
3928 | ||
61bc95c1 EE |
3929 | /** |
3930 | * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware | |
3931 | * cursor plane briefly if not already running after enabling the display | |
3932 | * plane. | |
3933 | * This workaround avoids occasional blank screens when self refresh is | |
3934 | * enabled. | |
3935 | */ | |
3936 | static void | |
3937 | g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe) | |
3938 | { | |
3939 | u32 cntl = I915_READ(CURCNTR(pipe)); | |
3940 | ||
3941 | if ((cntl & CURSOR_MODE) == 0) { | |
3942 | u32 fw_bcl_self = I915_READ(FW_BLC_SELF); | |
3943 | ||
3944 | I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN); | |
3945 | I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX); | |
3946 | intel_wait_for_vblank(dev_priv->dev, pipe); | |
3947 | I915_WRITE(CURCNTR(pipe), cntl); | |
3948 | I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); | |
3949 | I915_WRITE(FW_BLC_SELF, fw_bcl_self); | |
3950 | } | |
3951 | } | |
3952 | ||
2dd24552 JB |
3953 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
3954 | { | |
3955 | struct drm_device *dev = crtc->base.dev; | |
3956 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3957 | struct intel_crtc_config *pipe_config = &crtc->config; | |
3958 | ||
328d8e82 | 3959 | if (!crtc->config.gmch_pfit.control) |
2dd24552 JB |
3960 | return; |
3961 | ||
2dd24552 | 3962 | /* |
c0b03411 DV |
3963 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
3964 | * according to register description and PRM. | |
2dd24552 | 3965 | */ |
c0b03411 DV |
3966 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
3967 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 3968 | |
b074cec8 JB |
3969 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
3970 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
3971 | |
3972 | /* Border color in case we don't scale up to the full screen. Black by | |
3973 | * default, change to something else for debugging. */ | |
3974 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
3975 | } |
3976 | ||
586f49dc | 3977 | int valleyview_get_vco(struct drm_i915_private *dev_priv) |
30a970c6 | 3978 | { |
586f49dc | 3979 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
30a970c6 | 3980 | |
586f49dc JB |
3981 | /* Obtain SKU information */ |
3982 | mutex_lock(&dev_priv->dpio_lock); | |
3983 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
3984 | CCK_FUSE_HPLL_FREQ_MASK; | |
3985 | mutex_unlock(&dev_priv->dpio_lock); | |
30a970c6 | 3986 | |
586f49dc | 3987 | return vco_freq[hpll_freq]; |
30a970c6 JB |
3988 | } |
3989 | ||
3990 | /* Adjust CDclk dividers to allow high res or save power if possible */ | |
3991 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
3992 | { | |
3993 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3994 | u32 val, cmd; | |
3995 | ||
3996 | if (cdclk >= 320) /* jump to highest voltage for 400MHz too */ | |
3997 | cmd = 2; | |
3998 | else if (cdclk == 266) | |
3999 | cmd = 1; | |
4000 | else | |
4001 | cmd = 0; | |
4002 | ||
4003 | mutex_lock(&dev_priv->rps.hw_lock); | |
4004 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
4005 | val &= ~DSPFREQGUAR_MASK; | |
4006 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
4007 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
4008 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
4009 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
4010 | 50)) { | |
4011 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
4012 | } | |
4013 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4014 | ||
4015 | if (cdclk == 400) { | |
4016 | u32 divider, vco; | |
4017 | ||
4018 | vco = valleyview_get_vco(dev_priv); | |
4019 | divider = ((vco << 1) / cdclk) - 1; | |
4020 | ||
4021 | mutex_lock(&dev_priv->dpio_lock); | |
4022 | /* adjust cdclk divider */ | |
4023 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
4024 | val &= ~0xf; | |
4025 | val |= divider; | |
4026 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
4027 | mutex_unlock(&dev_priv->dpio_lock); | |
4028 | } | |
4029 | ||
4030 | mutex_lock(&dev_priv->dpio_lock); | |
4031 | /* adjust self-refresh exit latency value */ | |
4032 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
4033 | val &= ~0x7f; | |
4034 | ||
4035 | /* | |
4036 | * For high bandwidth configs, we set a higher latency in the bunit | |
4037 | * so that the core display fetch happens in time to avoid underruns. | |
4038 | */ | |
4039 | if (cdclk == 400) | |
4040 | val |= 4500 / 250; /* 4.5 usec */ | |
4041 | else | |
4042 | val |= 3000 / 250; /* 3.0 usec */ | |
4043 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
4044 | mutex_unlock(&dev_priv->dpio_lock); | |
4045 | ||
4046 | /* Since we changed the CDclk, we need to update the GMBUSFREQ too */ | |
4047 | intel_i2c_reset(dev); | |
4048 | } | |
4049 | ||
4050 | static int valleyview_cur_cdclk(struct drm_i915_private *dev_priv) | |
4051 | { | |
4052 | int cur_cdclk, vco; | |
4053 | int divider; | |
4054 | ||
4055 | vco = valleyview_get_vco(dev_priv); | |
4056 | ||
4057 | mutex_lock(&dev_priv->dpio_lock); | |
4058 | divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
4059 | mutex_unlock(&dev_priv->dpio_lock); | |
4060 | ||
4061 | divider &= 0xf; | |
4062 | ||
4063 | cur_cdclk = (vco << 1) / (divider + 1); | |
4064 | ||
4065 | return cur_cdclk; | |
4066 | } | |
4067 | ||
4068 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, | |
4069 | int max_pixclk) | |
4070 | { | |
4071 | int cur_cdclk; | |
4072 | ||
4073 | cur_cdclk = valleyview_cur_cdclk(dev_priv); | |
4074 | ||
4075 | /* | |
4076 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
4077 | * 200MHz | |
4078 | * 267MHz | |
4079 | * 320MHz | |
4080 | * 400MHz | |
4081 | * So we check to see whether we're above 90% of the lower bin and | |
4082 | * adjust if needed. | |
4083 | */ | |
4084 | if (max_pixclk > 288000) { | |
4085 | return 400; | |
4086 | } else if (max_pixclk > 240000) { | |
4087 | return 320; | |
4088 | } else | |
4089 | return 266; | |
4090 | /* Looks like the 200MHz CDclk freq doesn't work on some configs */ | |
4091 | } | |
4092 | ||
2f2d7aa1 VS |
4093 | /* compute the max pixel clock for new configuration */ |
4094 | static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv) | |
30a970c6 JB |
4095 | { |
4096 | struct drm_device *dev = dev_priv->dev; | |
4097 | struct intel_crtc *intel_crtc; | |
4098 | int max_pixclk = 0; | |
4099 | ||
4100 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, | |
4101 | base.head) { | |
2f2d7aa1 | 4102 | if (intel_crtc->new_enabled) |
30a970c6 | 4103 | max_pixclk = max(max_pixclk, |
2f2d7aa1 | 4104 | intel_crtc->new_config->adjusted_mode.crtc_clock); |
30a970c6 JB |
4105 | } |
4106 | ||
4107 | return max_pixclk; | |
4108 | } | |
4109 | ||
4110 | static void valleyview_modeset_global_pipes(struct drm_device *dev, | |
2f2d7aa1 | 4111 | unsigned *prepare_pipes) |
30a970c6 JB |
4112 | { |
4113 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4114 | struct intel_crtc *intel_crtc; | |
2f2d7aa1 | 4115 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
30a970c6 JB |
4116 | int cur_cdclk = valleyview_cur_cdclk(dev_priv); |
4117 | ||
4118 | if (valleyview_calc_cdclk(dev_priv, max_pixclk) == cur_cdclk) | |
4119 | return; | |
4120 | ||
2f2d7aa1 | 4121 | /* disable/enable all currently active pipes while we change cdclk */ |
30a970c6 JB |
4122 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
4123 | base.head) | |
4124 | if (intel_crtc->base.enabled) | |
4125 | *prepare_pipes |= (1 << intel_crtc->pipe); | |
4126 | } | |
4127 | ||
4128 | static void valleyview_modeset_global_resources(struct drm_device *dev) | |
4129 | { | |
4130 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2f2d7aa1 | 4131 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
30a970c6 JB |
4132 | int cur_cdclk = valleyview_cur_cdclk(dev_priv); |
4133 | int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); | |
4134 | ||
4135 | if (req_cdclk != cur_cdclk) | |
4136 | valleyview_set_cdclk(dev, req_cdclk); | |
4137 | } | |
4138 | ||
89b667f8 JB |
4139 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
4140 | { | |
4141 | struct drm_device *dev = crtc->dev; | |
4142 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4143 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4144 | struct intel_encoder *encoder; | |
4145 | int pipe = intel_crtc->pipe; | |
4146 | int plane = intel_crtc->plane; | |
23538ef1 | 4147 | bool is_dsi; |
89b667f8 JB |
4148 | |
4149 | WARN_ON(!crtc->enabled); | |
4150 | ||
4151 | if (intel_crtc->active) | |
4152 | return; | |
4153 | ||
4154 | intel_crtc->active = true; | |
89b667f8 | 4155 | |
89b667f8 JB |
4156 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4157 | if (encoder->pre_pll_enable) | |
4158 | encoder->pre_pll_enable(encoder); | |
4159 | ||
23538ef1 JN |
4160 | is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI); |
4161 | ||
e9fd1c02 JN |
4162 | if (!is_dsi) |
4163 | vlv_enable_pll(intel_crtc); | |
89b667f8 JB |
4164 | |
4165 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
4166 | if (encoder->pre_enable) | |
4167 | encoder->pre_enable(encoder); | |
4168 | ||
2dd24552 JB |
4169 | i9xx_pfit_enable(intel_crtc); |
4170 | ||
63cbb074 VS |
4171 | intel_crtc_load_lut(crtc); |
4172 | ||
f37fcc2a | 4173 | intel_update_watermarks(crtc); |
0372264a | 4174 | intel_enable_pipe(intel_crtc, false, is_dsi, true); |
2d9d2b0b | 4175 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
d1de00ef | 4176 | intel_enable_primary_plane(dev_priv, plane, pipe); |
bb53d4ae | 4177 | intel_enable_planes(crtc); |
5c38d48c | 4178 | intel_crtc_update_cursor(crtc, true); |
89b667f8 | 4179 | |
89b667f8 | 4180 | intel_update_fbc(dev); |
5004945f JN |
4181 | |
4182 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
4183 | encoder->enable(encoder); | |
89b667f8 JB |
4184 | } |
4185 | ||
0b8765c6 | 4186 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
4187 | { |
4188 | struct drm_device *dev = crtc->dev; | |
79e53945 JB |
4189 | struct drm_i915_private *dev_priv = dev->dev_private; |
4190 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4191 | struct intel_encoder *encoder; |
79e53945 | 4192 | int pipe = intel_crtc->pipe; |
80824003 | 4193 | int plane = intel_crtc->plane; |
79e53945 | 4194 | |
08a48469 DV |
4195 | WARN_ON(!crtc->enabled); |
4196 | ||
f7abfe8b CW |
4197 | if (intel_crtc->active) |
4198 | return; | |
4199 | ||
4200 | intel_crtc->active = true; | |
6b383a7f | 4201 | |
9d6d9f19 MK |
4202 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4203 | if (encoder->pre_enable) | |
4204 | encoder->pre_enable(encoder); | |
4205 | ||
f6736a1a DV |
4206 | i9xx_enable_pll(intel_crtc); |
4207 | ||
2dd24552 JB |
4208 | i9xx_pfit_enable(intel_crtc); |
4209 | ||
63cbb074 VS |
4210 | intel_crtc_load_lut(crtc); |
4211 | ||
f37fcc2a | 4212 | intel_update_watermarks(crtc); |
0372264a | 4213 | intel_enable_pipe(intel_crtc, false, false, true); |
2d9d2b0b | 4214 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
d1de00ef | 4215 | intel_enable_primary_plane(dev_priv, plane, pipe); |
bb53d4ae | 4216 | intel_enable_planes(crtc); |
22e407d7 | 4217 | /* The fixup needs to happen before cursor is enabled */ |
61bc95c1 EE |
4218 | if (IS_G4X(dev)) |
4219 | g4x_fixup_plane(dev_priv, pipe); | |
22e407d7 | 4220 | intel_crtc_update_cursor(crtc, true); |
79e53945 | 4221 | |
0b8765c6 JB |
4222 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
4223 | intel_crtc_dpms_overlay(intel_crtc, true); | |
ef9c3aee | 4224 | |
f440eb13 | 4225 | intel_update_fbc(dev); |
ef9c3aee | 4226 | |
fa5c73b1 DV |
4227 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4228 | encoder->enable(encoder); | |
0b8765c6 | 4229 | } |
79e53945 | 4230 | |
87476d63 DV |
4231 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
4232 | { | |
4233 | struct drm_device *dev = crtc->base.dev; | |
4234 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 4235 | |
328d8e82 DV |
4236 | if (!crtc->config.gmch_pfit.control) |
4237 | return; | |
87476d63 | 4238 | |
328d8e82 | 4239 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 4240 | |
328d8e82 DV |
4241 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
4242 | I915_READ(PFIT_CONTROL)); | |
4243 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
4244 | } |
4245 | ||
0b8765c6 JB |
4246 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
4247 | { | |
4248 | struct drm_device *dev = crtc->dev; | |
4249 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4250 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4251 | struct intel_encoder *encoder; |
0b8765c6 JB |
4252 | int pipe = intel_crtc->pipe; |
4253 | int plane = intel_crtc->plane; | |
ef9c3aee | 4254 | |
f7abfe8b CW |
4255 | if (!intel_crtc->active) |
4256 | return; | |
4257 | ||
ea9d758d DV |
4258 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4259 | encoder->disable(encoder); | |
4260 | ||
0b8765c6 | 4261 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
e6c3a2a6 CW |
4262 | intel_crtc_wait_for_pending_flips(crtc); |
4263 | drm_vblank_off(dev, pipe); | |
0b8765c6 | 4264 | |
5c3fe8b0 | 4265 | if (dev_priv->fbc.plane == plane) |
973d04f9 | 4266 | intel_disable_fbc(dev); |
79e53945 | 4267 | |
0d5b8c61 VS |
4268 | intel_crtc_dpms_overlay(intel_crtc, false); |
4269 | intel_crtc_update_cursor(crtc, false); | |
bb53d4ae | 4270 | intel_disable_planes(crtc); |
d1de00ef | 4271 | intel_disable_primary_plane(dev_priv, plane, pipe); |
0d5b8c61 | 4272 | |
2d9d2b0b | 4273 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false); |
b24e7179 | 4274 | intel_disable_pipe(dev_priv, pipe); |
24a1f16d | 4275 | |
87476d63 | 4276 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 4277 | |
89b667f8 JB |
4278 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4279 | if (encoder->post_disable) | |
4280 | encoder->post_disable(encoder); | |
4281 | ||
f6071166 JB |
4282 | if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) |
4283 | vlv_disable_pll(dev_priv, pipe); | |
4284 | else if (!IS_VALLEYVIEW(dev)) | |
e9fd1c02 | 4285 | i9xx_disable_pll(dev_priv, pipe); |
0b8765c6 | 4286 | |
f7abfe8b | 4287 | intel_crtc->active = false; |
46ba614c | 4288 | intel_update_watermarks(crtc); |
f37fcc2a | 4289 | |
6b383a7f | 4290 | intel_update_fbc(dev); |
0b8765c6 JB |
4291 | } |
4292 | ||
ee7b9f93 JB |
4293 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
4294 | { | |
4295 | } | |
4296 | ||
976f8a20 DV |
4297 | static void intel_crtc_update_sarea(struct drm_crtc *crtc, |
4298 | bool enabled) | |
2c07245f ZW |
4299 | { |
4300 | struct drm_device *dev = crtc->dev; | |
4301 | struct drm_i915_master_private *master_priv; | |
4302 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4303 | int pipe = intel_crtc->pipe; | |
79e53945 JB |
4304 | |
4305 | if (!dev->primary->master) | |
4306 | return; | |
4307 | ||
4308 | master_priv = dev->primary->master->driver_priv; | |
4309 | if (!master_priv->sarea_priv) | |
4310 | return; | |
4311 | ||
79e53945 JB |
4312 | switch (pipe) { |
4313 | case 0: | |
4314 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; | |
4315 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; | |
4316 | break; | |
4317 | case 1: | |
4318 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; | |
4319 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; | |
4320 | break; | |
4321 | default: | |
9db4a9c7 | 4322 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
79e53945 JB |
4323 | break; |
4324 | } | |
79e53945 JB |
4325 | } |
4326 | ||
976f8a20 DV |
4327 | /** |
4328 | * Sets the power management mode of the pipe and plane. | |
4329 | */ | |
4330 | void intel_crtc_update_dpms(struct drm_crtc *crtc) | |
4331 | { | |
4332 | struct drm_device *dev = crtc->dev; | |
4333 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4334 | struct intel_encoder *intel_encoder; | |
4335 | bool enable = false; | |
4336 | ||
4337 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) | |
4338 | enable |= intel_encoder->connectors_active; | |
4339 | ||
4340 | if (enable) | |
4341 | dev_priv->display.crtc_enable(crtc); | |
4342 | else | |
4343 | dev_priv->display.crtc_disable(crtc); | |
4344 | ||
4345 | intel_crtc_update_sarea(crtc, enable); | |
4346 | } | |
4347 | ||
cdd59983 CW |
4348 | static void intel_crtc_disable(struct drm_crtc *crtc) |
4349 | { | |
cdd59983 | 4350 | struct drm_device *dev = crtc->dev; |
976f8a20 | 4351 | struct drm_connector *connector; |
ee7b9f93 | 4352 | struct drm_i915_private *dev_priv = dev->dev_private; |
7b9f35a6 | 4353 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cdd59983 | 4354 | |
976f8a20 DV |
4355 | /* crtc should still be enabled when we disable it. */ |
4356 | WARN_ON(!crtc->enabled); | |
4357 | ||
4358 | dev_priv->display.crtc_disable(crtc); | |
c77bf565 | 4359 | intel_crtc->eld_vld = false; |
976f8a20 | 4360 | intel_crtc_update_sarea(crtc, false); |
ee7b9f93 JB |
4361 | dev_priv->display.off(crtc); |
4362 | ||
931872fc | 4363 | assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); |
93ce0ba6 | 4364 | assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe); |
931872fc | 4365 | assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); |
cdd59983 CW |
4366 | |
4367 | if (crtc->fb) { | |
4368 | mutex_lock(&dev->struct_mutex); | |
1690e1eb | 4369 | intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); |
cdd59983 | 4370 | mutex_unlock(&dev->struct_mutex); |
976f8a20 DV |
4371 | crtc->fb = NULL; |
4372 | } | |
4373 | ||
4374 | /* Update computed state. */ | |
4375 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4376 | if (!connector->encoder || !connector->encoder->crtc) | |
4377 | continue; | |
4378 | ||
4379 | if (connector->encoder->crtc != crtc) | |
4380 | continue; | |
4381 | ||
4382 | connector->dpms = DRM_MODE_DPMS_OFF; | |
4383 | to_intel_encoder(connector->encoder)->connectors_active = false; | |
cdd59983 CW |
4384 | } |
4385 | } | |
4386 | ||
ea5b213a | 4387 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 4388 | { |
4ef69c7a | 4389 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 4390 | |
ea5b213a CW |
4391 | drm_encoder_cleanup(encoder); |
4392 | kfree(intel_encoder); | |
7e7d76c3 JB |
4393 | } |
4394 | ||
9237329d | 4395 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
5ab432ef DV |
4396 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
4397 | * state of the entire output pipe. */ | |
9237329d | 4398 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
7e7d76c3 | 4399 | { |
5ab432ef DV |
4400 | if (mode == DRM_MODE_DPMS_ON) { |
4401 | encoder->connectors_active = true; | |
4402 | ||
b2cabb0e | 4403 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef DV |
4404 | } else { |
4405 | encoder->connectors_active = false; | |
4406 | ||
b2cabb0e | 4407 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef | 4408 | } |
79e53945 JB |
4409 | } |
4410 | ||
0a91ca29 DV |
4411 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
4412 | * internal consistency). */ | |
b980514c | 4413 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 4414 | { |
0a91ca29 DV |
4415 | if (connector->get_hw_state(connector)) { |
4416 | struct intel_encoder *encoder = connector->encoder; | |
4417 | struct drm_crtc *crtc; | |
4418 | bool encoder_enabled; | |
4419 | enum pipe pipe; | |
4420 | ||
4421 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
4422 | connector->base.base.id, | |
4423 | drm_get_connector_name(&connector->base)); | |
4424 | ||
4425 | WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, | |
4426 | "wrong connector dpms state\n"); | |
4427 | WARN(connector->base.encoder != &encoder->base, | |
4428 | "active connector not linked to encoder\n"); | |
4429 | WARN(!encoder->connectors_active, | |
4430 | "encoder->connectors_active not set\n"); | |
4431 | ||
4432 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); | |
4433 | WARN(!encoder_enabled, "encoder not enabled\n"); | |
4434 | if (WARN_ON(!encoder->base.crtc)) | |
4435 | return; | |
4436 | ||
4437 | crtc = encoder->base.crtc; | |
4438 | ||
4439 | WARN(!crtc->enabled, "crtc not enabled\n"); | |
4440 | WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); | |
4441 | WARN(pipe != to_intel_crtc(crtc)->pipe, | |
4442 | "encoder active on the wrong pipe\n"); | |
4443 | } | |
79e53945 JB |
4444 | } |
4445 | ||
5ab432ef DV |
4446 | /* Even simpler default implementation, if there's really no special case to |
4447 | * consider. */ | |
4448 | void intel_connector_dpms(struct drm_connector *connector, int mode) | |
79e53945 | 4449 | { |
5ab432ef DV |
4450 | /* All the simple cases only support two dpms states. */ |
4451 | if (mode != DRM_MODE_DPMS_ON) | |
4452 | mode = DRM_MODE_DPMS_OFF; | |
d4270e57 | 4453 | |
5ab432ef DV |
4454 | if (mode == connector->dpms) |
4455 | return; | |
4456 | ||
4457 | connector->dpms = mode; | |
4458 | ||
4459 | /* Only need to change hw state when actually enabled */ | |
c9976dcf CW |
4460 | if (connector->encoder) |
4461 | intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); | |
0a91ca29 | 4462 | |
b980514c | 4463 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
4464 | } |
4465 | ||
f0947c37 DV |
4466 | /* Simple connector->get_hw_state implementation for encoders that support only |
4467 | * one connector and no cloning and hence the encoder state determines the state | |
4468 | * of the connector. */ | |
4469 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 4470 | { |
24929352 | 4471 | enum pipe pipe = 0; |
f0947c37 | 4472 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 4473 | |
f0947c37 | 4474 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
4475 | } |
4476 | ||
1857e1da DV |
4477 | static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
4478 | struct intel_crtc_config *pipe_config) | |
4479 | { | |
4480 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4481 | struct intel_crtc *pipe_B_crtc = | |
4482 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
4483 | ||
4484 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", | |
4485 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4486 | if (pipe_config->fdi_lanes > 4) { | |
4487 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
4488 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4489 | return false; | |
4490 | } | |
4491 | ||
bafb6553 | 4492 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
4493 | if (pipe_config->fdi_lanes > 2) { |
4494 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
4495 | pipe_config->fdi_lanes); | |
4496 | return false; | |
4497 | } else { | |
4498 | return true; | |
4499 | } | |
4500 | } | |
4501 | ||
4502 | if (INTEL_INFO(dev)->num_pipes == 2) | |
4503 | return true; | |
4504 | ||
4505 | /* Ivybridge 3 pipe is really complicated */ | |
4506 | switch (pipe) { | |
4507 | case PIPE_A: | |
4508 | return true; | |
4509 | case PIPE_B: | |
4510 | if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled && | |
4511 | pipe_config->fdi_lanes > 2) { | |
4512 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
4513 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4514 | return false; | |
4515 | } | |
4516 | return true; | |
4517 | case PIPE_C: | |
1e833f40 | 4518 | if (!pipe_has_enabled_pch(pipe_B_crtc) || |
1857e1da DV |
4519 | pipe_B_crtc->config.fdi_lanes <= 2) { |
4520 | if (pipe_config->fdi_lanes > 2) { | |
4521 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
4522 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4523 | return false; | |
4524 | } | |
4525 | } else { | |
4526 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); | |
4527 | return false; | |
4528 | } | |
4529 | return true; | |
4530 | default: | |
4531 | BUG(); | |
4532 | } | |
4533 | } | |
4534 | ||
e29c22c0 DV |
4535 | #define RETRY 1 |
4536 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
4537 | struct intel_crtc_config *pipe_config) | |
877d48d5 | 4538 | { |
1857e1da | 4539 | struct drm_device *dev = intel_crtc->base.dev; |
877d48d5 | 4540 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
ff9a6750 | 4541 | int lane, link_bw, fdi_dotclock; |
e29c22c0 | 4542 | bool setup_ok, needs_recompute = false; |
877d48d5 | 4543 | |
e29c22c0 | 4544 | retry: |
877d48d5 DV |
4545 | /* FDI is a binary signal running at ~2.7GHz, encoding |
4546 | * each output octet as 10 bits. The actual frequency | |
4547 | * is stored as a divider into a 100MHz clock, and the | |
4548 | * mode pixel clock is stored in units of 1KHz. | |
4549 | * Hence the bw of each lane in terms of the mode signal | |
4550 | * is: | |
4551 | */ | |
4552 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
4553 | ||
241bfc38 | 4554 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 4555 | |
2bd89a07 | 4556 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
4557 | pipe_config->pipe_bpp); |
4558 | ||
4559 | pipe_config->fdi_lanes = lane; | |
4560 | ||
2bd89a07 | 4561 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 4562 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 4563 | |
e29c22c0 DV |
4564 | setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
4565 | intel_crtc->pipe, pipe_config); | |
4566 | if (!setup_ok && pipe_config->pipe_bpp > 6*3) { | |
4567 | pipe_config->pipe_bpp -= 2*3; | |
4568 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
4569 | pipe_config->pipe_bpp); | |
4570 | needs_recompute = true; | |
4571 | pipe_config->bw_constrained = true; | |
4572 | ||
4573 | goto retry; | |
4574 | } | |
4575 | ||
4576 | if (needs_recompute) | |
4577 | return RETRY; | |
4578 | ||
4579 | return setup_ok ? 0 : -EINVAL; | |
877d48d5 DV |
4580 | } |
4581 | ||
42db64ef PZ |
4582 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
4583 | struct intel_crtc_config *pipe_config) | |
4584 | { | |
d330a953 | 4585 | pipe_config->ips_enabled = i915.enable_ips && |
3c4ca58c | 4586 | hsw_crtc_supports_ips(crtc) && |
b6dfdc9b | 4587 | pipe_config->pipe_bpp <= 24; |
42db64ef PZ |
4588 | } |
4589 | ||
a43f6e0f | 4590 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
e29c22c0 | 4591 | struct intel_crtc_config *pipe_config) |
79e53945 | 4592 | { |
a43f6e0f | 4593 | struct drm_device *dev = crtc->base.dev; |
b8cecdf5 | 4594 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
89749350 | 4595 | |
ad3a4479 | 4596 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 VS |
4597 | if (INTEL_INFO(dev)->gen < 4) { |
4598 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4599 | int clock_limit = | |
4600 | dev_priv->display.get_display_clock_speed(dev); | |
4601 | ||
4602 | /* | |
4603 | * Enable pixel doubling when the dot clock | |
4604 | * is > 90% of the (display) core speed. | |
4605 | * | |
b397c96b VS |
4606 | * GDG double wide on either pipe, |
4607 | * otherwise pipe A only. | |
cf532bb2 | 4608 | */ |
b397c96b | 4609 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
241bfc38 | 4610 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
ad3a4479 | 4611 | clock_limit *= 2; |
cf532bb2 | 4612 | pipe_config->double_wide = true; |
ad3a4479 VS |
4613 | } |
4614 | ||
241bfc38 | 4615 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
e29c22c0 | 4616 | return -EINVAL; |
2c07245f | 4617 | } |
89749350 | 4618 | |
1d1d0e27 VS |
4619 | /* |
4620 | * Pipe horizontal size must be even in: | |
4621 | * - DVO ganged mode | |
4622 | * - LVDS dual channel mode | |
4623 | * - Double wide pipe | |
4624 | */ | |
4625 | if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && | |
4626 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) | |
4627 | pipe_config->pipe_src_w &= ~1; | |
4628 | ||
8693a824 DL |
4629 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
4630 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
4631 | */ |
4632 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
4633 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | |
e29c22c0 | 4634 | return -EINVAL; |
44f46b42 | 4635 | |
bd080ee5 | 4636 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { |
5d2d38dd | 4637 | pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ |
bd080ee5 | 4638 | } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { |
5d2d38dd DV |
4639 | /* only a 8bpc pipe, with 6bpc dither through the panel fitter |
4640 | * for lvds. */ | |
4641 | pipe_config->pipe_bpp = 8*3; | |
4642 | } | |
4643 | ||
f5adf94e | 4644 | if (HAS_IPS(dev)) |
a43f6e0f DV |
4645 | hsw_compute_ips_config(crtc, pipe_config); |
4646 | ||
4647 | /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old | |
4648 | * clock survives for now. */ | |
4649 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
4650 | pipe_config->shared_dpll = crtc->config.shared_dpll; | |
42db64ef | 4651 | |
877d48d5 | 4652 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 4653 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 4654 | |
e29c22c0 | 4655 | return 0; |
79e53945 JB |
4656 | } |
4657 | ||
25eb05fc JB |
4658 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
4659 | { | |
4660 | return 400000; /* FIXME */ | |
4661 | } | |
4662 | ||
e70236a8 JB |
4663 | static int i945_get_display_clock_speed(struct drm_device *dev) |
4664 | { | |
4665 | return 400000; | |
4666 | } | |
79e53945 | 4667 | |
e70236a8 | 4668 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 4669 | { |
e70236a8 JB |
4670 | return 333000; |
4671 | } | |
79e53945 | 4672 | |
e70236a8 JB |
4673 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
4674 | { | |
4675 | return 200000; | |
4676 | } | |
79e53945 | 4677 | |
257a7ffc DV |
4678 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
4679 | { | |
4680 | u16 gcfgc = 0; | |
4681 | ||
4682 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
4683 | ||
4684 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
4685 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
4686 | return 267000; | |
4687 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: | |
4688 | return 333000; | |
4689 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: | |
4690 | return 444000; | |
4691 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: | |
4692 | return 200000; | |
4693 | default: | |
4694 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
4695 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
4696 | return 133000; | |
4697 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: | |
4698 | return 167000; | |
4699 | } | |
4700 | } | |
4701 | ||
e70236a8 JB |
4702 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
4703 | { | |
4704 | u16 gcfgc = 0; | |
79e53945 | 4705 | |
e70236a8 JB |
4706 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
4707 | ||
4708 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
4709 | return 133000; | |
4710 | else { | |
4711 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
4712 | case GC_DISPLAY_CLOCK_333_MHZ: | |
4713 | return 333000; | |
4714 | default: | |
4715 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
4716 | return 190000; | |
79e53945 | 4717 | } |
e70236a8 JB |
4718 | } |
4719 | } | |
4720 | ||
4721 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
4722 | { | |
4723 | return 266000; | |
4724 | } | |
4725 | ||
4726 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
4727 | { | |
4728 | u16 hpllcc = 0; | |
4729 | /* Assume that the hardware is in the high speed state. This | |
4730 | * should be the default. | |
4731 | */ | |
4732 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
4733 | case GC_CLOCK_133_200: | |
4734 | case GC_CLOCK_100_200: | |
4735 | return 200000; | |
4736 | case GC_CLOCK_166_250: | |
4737 | return 250000; | |
4738 | case GC_CLOCK_100_133: | |
79e53945 | 4739 | return 133000; |
e70236a8 | 4740 | } |
79e53945 | 4741 | |
e70236a8 JB |
4742 | /* Shouldn't happen */ |
4743 | return 0; | |
4744 | } | |
79e53945 | 4745 | |
e70236a8 JB |
4746 | static int i830_get_display_clock_speed(struct drm_device *dev) |
4747 | { | |
4748 | return 133000; | |
79e53945 JB |
4749 | } |
4750 | ||
2c07245f | 4751 | static void |
a65851af | 4752 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 4753 | { |
a65851af VS |
4754 | while (*num > DATA_LINK_M_N_MASK || |
4755 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
4756 | *num >>= 1; |
4757 | *den >>= 1; | |
4758 | } | |
4759 | } | |
4760 | ||
a65851af VS |
4761 | static void compute_m_n(unsigned int m, unsigned int n, |
4762 | uint32_t *ret_m, uint32_t *ret_n) | |
4763 | { | |
4764 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
4765 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
4766 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
4767 | } | |
4768 | ||
e69d0bc1 DV |
4769 | void |
4770 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
4771 | int pixel_clock, int link_clock, | |
4772 | struct intel_link_m_n *m_n) | |
2c07245f | 4773 | { |
e69d0bc1 | 4774 | m_n->tu = 64; |
a65851af VS |
4775 | |
4776 | compute_m_n(bits_per_pixel * pixel_clock, | |
4777 | link_clock * nlanes * 8, | |
4778 | &m_n->gmch_m, &m_n->gmch_n); | |
4779 | ||
4780 | compute_m_n(pixel_clock, link_clock, | |
4781 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
4782 | } |
4783 | ||
a7615030 CW |
4784 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
4785 | { | |
d330a953 JN |
4786 | if (i915.panel_use_ssc >= 0) |
4787 | return i915.panel_use_ssc != 0; | |
41aa3448 | 4788 | return dev_priv->vbt.lvds_use_ssc |
435793df | 4789 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
4790 | } |
4791 | ||
c65d77d8 JB |
4792 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
4793 | { | |
4794 | struct drm_device *dev = crtc->dev; | |
4795 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4796 | int refclk; | |
4797 | ||
a0c4da24 | 4798 | if (IS_VALLEYVIEW(dev)) { |
9a0ea498 | 4799 | refclk = 100000; |
a0c4da24 | 4800 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 4801 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
4802 | refclk = dev_priv->vbt.lvds_ssc_freq; |
4803 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
4804 | } else if (!IS_GEN2(dev)) { |
4805 | refclk = 96000; | |
4806 | } else { | |
4807 | refclk = 48000; | |
4808 | } | |
4809 | ||
4810 | return refclk; | |
4811 | } | |
4812 | ||
7429e9d4 | 4813 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 4814 | { |
7df00d7a | 4815 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 4816 | } |
f47709a9 | 4817 | |
7429e9d4 DV |
4818 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
4819 | { | |
4820 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
4821 | } |
4822 | ||
f47709a9 | 4823 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
a7516a05 JB |
4824 | intel_clock_t *reduced_clock) |
4825 | { | |
f47709a9 | 4826 | struct drm_device *dev = crtc->base.dev; |
a7516a05 | 4827 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 4828 | int pipe = crtc->pipe; |
a7516a05 JB |
4829 | u32 fp, fp2 = 0; |
4830 | ||
4831 | if (IS_PINEVIEW(dev)) { | |
7429e9d4 | 4832 | fp = pnv_dpll_compute_fp(&crtc->config.dpll); |
a7516a05 | 4833 | if (reduced_clock) |
7429e9d4 | 4834 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 4835 | } else { |
7429e9d4 | 4836 | fp = i9xx_dpll_compute_fp(&crtc->config.dpll); |
a7516a05 | 4837 | if (reduced_clock) |
7429e9d4 | 4838 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
4839 | } |
4840 | ||
4841 | I915_WRITE(FP0(pipe), fp); | |
8bcc2795 | 4842 | crtc->config.dpll_hw_state.fp0 = fp; |
a7516a05 | 4843 | |
f47709a9 DV |
4844 | crtc->lowfreq_avail = false; |
4845 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && | |
d330a953 | 4846 | reduced_clock && i915.powersave) { |
a7516a05 | 4847 | I915_WRITE(FP1(pipe), fp2); |
8bcc2795 | 4848 | crtc->config.dpll_hw_state.fp1 = fp2; |
f47709a9 | 4849 | crtc->lowfreq_avail = true; |
a7516a05 JB |
4850 | } else { |
4851 | I915_WRITE(FP1(pipe), fp); | |
8bcc2795 | 4852 | crtc->config.dpll_hw_state.fp1 = fp; |
a7516a05 JB |
4853 | } |
4854 | } | |
4855 | ||
5e69f97f CML |
4856 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
4857 | pipe) | |
89b667f8 JB |
4858 | { |
4859 | u32 reg_val; | |
4860 | ||
4861 | /* | |
4862 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
4863 | * and set it to a reasonable value instead. | |
4864 | */ | |
ab3c759a | 4865 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
4866 | reg_val &= 0xffffff00; |
4867 | reg_val |= 0x00000030; | |
ab3c759a | 4868 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 4869 | |
ab3c759a | 4870 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
4871 | reg_val &= 0x8cffffff; |
4872 | reg_val = 0x8c000000; | |
ab3c759a | 4873 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 4874 | |
ab3c759a | 4875 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 4876 | reg_val &= 0xffffff00; |
ab3c759a | 4877 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 4878 | |
ab3c759a | 4879 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
4880 | reg_val &= 0x00ffffff; |
4881 | reg_val |= 0xb0000000; | |
ab3c759a | 4882 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
4883 | } |
4884 | ||
b551842d DV |
4885 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
4886 | struct intel_link_m_n *m_n) | |
4887 | { | |
4888 | struct drm_device *dev = crtc->base.dev; | |
4889 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4890 | int pipe = crtc->pipe; | |
4891 | ||
e3b95f1e DV |
4892 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
4893 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
4894 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
4895 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
4896 | } |
4897 | ||
4898 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
4899 | struct intel_link_m_n *m_n) | |
4900 | { | |
4901 | struct drm_device *dev = crtc->base.dev; | |
4902 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4903 | int pipe = crtc->pipe; | |
4904 | enum transcoder transcoder = crtc->config.cpu_transcoder; | |
4905 | ||
4906 | if (INTEL_INFO(dev)->gen >= 5) { | |
4907 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
4908 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
4909 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
4910 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
4911 | } else { | |
e3b95f1e DV |
4912 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
4913 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
4914 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
4915 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
4916 | } |
4917 | } | |
4918 | ||
03afc4a2 DV |
4919 | static void intel_dp_set_m_n(struct intel_crtc *crtc) |
4920 | { | |
4921 | if (crtc->config.has_pch_encoder) | |
4922 | intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); | |
4923 | else | |
4924 | intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); | |
4925 | } | |
4926 | ||
f47709a9 | 4927 | static void vlv_update_pll(struct intel_crtc *crtc) |
a0c4da24 | 4928 | { |
f47709a9 | 4929 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 4930 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 4931 | int pipe = crtc->pipe; |
89b667f8 | 4932 | u32 dpll, mdiv; |
a0c4da24 | 4933 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
198a037f | 4934 | u32 coreclk, reg_val, dpll_md; |
a0c4da24 | 4935 | |
09153000 DV |
4936 | mutex_lock(&dev_priv->dpio_lock); |
4937 | ||
f47709a9 DV |
4938 | bestn = crtc->config.dpll.n; |
4939 | bestm1 = crtc->config.dpll.m1; | |
4940 | bestm2 = crtc->config.dpll.m2; | |
4941 | bestp1 = crtc->config.dpll.p1; | |
4942 | bestp2 = crtc->config.dpll.p2; | |
a0c4da24 | 4943 | |
89b667f8 JB |
4944 | /* See eDP HDMI DPIO driver vbios notes doc */ |
4945 | ||
4946 | /* PLL B needs special handling */ | |
4947 | if (pipe) | |
5e69f97f | 4948 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
4949 | |
4950 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 4951 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
4952 | |
4953 | /* Disable target IRef on PLL */ | |
ab3c759a | 4954 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 4955 | reg_val &= 0x00ffffff; |
ab3c759a | 4956 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
4957 | |
4958 | /* Disable fast lock */ | |
ab3c759a | 4959 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
4960 | |
4961 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
4962 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
4963 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
4964 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 4965 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
4966 | |
4967 | /* | |
4968 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
4969 | * but we don't support that). | |
4970 | * Note: don't use the DAC post divider as it seems unstable. | |
4971 | */ | |
4972 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 4973 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 4974 | |
a0c4da24 | 4975 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 4976 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 4977 | |
89b667f8 | 4978 | /* Set HBR and RBR LPF coefficients */ |
ff9a6750 | 4979 | if (crtc->config.port_clock == 162000 || |
99750bd4 | 4980 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) || |
89b667f8 | 4981 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) |
ab3c759a | 4982 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 4983 | 0x009f0003); |
89b667f8 | 4984 | else |
ab3c759a | 4985 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
4986 | 0x00d0000f); |
4987 | ||
4988 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) || | |
4989 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) { | |
4990 | /* Use SSC source */ | |
4991 | if (!pipe) | |
ab3c759a | 4992 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
4993 | 0x0df40000); |
4994 | else | |
ab3c759a | 4995 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
4996 | 0x0df70000); |
4997 | } else { /* HDMI or VGA */ | |
4998 | /* Use bend source */ | |
4999 | if (!pipe) | |
ab3c759a | 5000 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5001 | 0x0df70000); |
5002 | else | |
ab3c759a | 5003 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5004 | 0x0df40000); |
5005 | } | |
a0c4da24 | 5006 | |
ab3c759a | 5007 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 JB |
5008 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
5009 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) || | |
5010 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) | |
5011 | coreclk |= 0x01000000; | |
ab3c759a | 5012 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 5013 | |
ab3c759a | 5014 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a0c4da24 | 5015 | |
e5cbfbfb ID |
5016 | /* |
5017 | * Enable DPIO clock input. We should never disable the reference | |
5018 | * clock for pipe B, since VGA hotplug / manual detection depends | |
5019 | * on it. | |
5020 | */ | |
89b667f8 JB |
5021 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | |
5022 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; | |
f6071166 JB |
5023 | /* We should never disable this, set it here for state tracking */ |
5024 | if (pipe == PIPE_B) | |
89b667f8 | 5025 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
a0c4da24 | 5026 | dpll |= DPLL_VCO_ENABLE; |
8bcc2795 DV |
5027 | crtc->config.dpll_hw_state.dpll = dpll; |
5028 | ||
ef1b460d DV |
5029 | dpll_md = (crtc->config.pixel_multiplier - 1) |
5030 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
8bcc2795 DV |
5031 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
5032 | ||
89b667f8 JB |
5033 | if (crtc->config.has_dp_encoder) |
5034 | intel_dp_set_m_n(crtc); | |
09153000 DV |
5035 | |
5036 | mutex_unlock(&dev_priv->dpio_lock); | |
a0c4da24 JB |
5037 | } |
5038 | ||
f47709a9 DV |
5039 | static void i9xx_update_pll(struct intel_crtc *crtc, |
5040 | intel_clock_t *reduced_clock, | |
eb1cbe48 DV |
5041 | int num_connectors) |
5042 | { | |
f47709a9 | 5043 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 5044 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
5045 | u32 dpll; |
5046 | bool is_sdvo; | |
f47709a9 | 5047 | struct dpll *clock = &crtc->config.dpll; |
eb1cbe48 | 5048 | |
f47709a9 | 5049 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 5050 | |
f47709a9 DV |
5051 | is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) || |
5052 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
5053 | |
5054 | dpll = DPLL_VGA_MODE_DIS; | |
5055 | ||
f47709a9 | 5056 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
5057 | dpll |= DPLLB_MODE_LVDS; |
5058 | else | |
5059 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 5060 | |
ef1b460d | 5061 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
198a037f DV |
5062 | dpll |= (crtc->config.pixel_multiplier - 1) |
5063 | << SDVO_MULTIPLIER_SHIFT_HIRES; | |
eb1cbe48 | 5064 | } |
198a037f DV |
5065 | |
5066 | if (is_sdvo) | |
4a33e48d | 5067 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 5068 | |
f47709a9 | 5069 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) |
4a33e48d | 5070 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
5071 | |
5072 | /* compute bitmask from p1 value */ | |
5073 | if (IS_PINEVIEW(dev)) | |
5074 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
5075 | else { | |
5076 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5077 | if (IS_G4X(dev) && reduced_clock) | |
5078 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
5079 | } | |
5080 | switch (clock->p2) { | |
5081 | case 5: | |
5082 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
5083 | break; | |
5084 | case 7: | |
5085 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
5086 | break; | |
5087 | case 10: | |
5088 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
5089 | break; | |
5090 | case 14: | |
5091 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
5092 | break; | |
5093 | } | |
5094 | if (INTEL_INFO(dev)->gen >= 4) | |
5095 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
5096 | ||
09ede541 | 5097 | if (crtc->config.sdvo_tv_clock) |
eb1cbe48 | 5098 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
f47709a9 | 5099 | else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
5100 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
5101 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
5102 | else | |
5103 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5104 | ||
5105 | dpll |= DPLL_VCO_ENABLE; | |
8bcc2795 DV |
5106 | crtc->config.dpll_hw_state.dpll = dpll; |
5107 | ||
eb1cbe48 | 5108 | if (INTEL_INFO(dev)->gen >= 4) { |
ef1b460d DV |
5109 | u32 dpll_md = (crtc->config.pixel_multiplier - 1) |
5110 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
8bcc2795 | 5111 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 | 5112 | } |
66e3d5c0 DV |
5113 | |
5114 | if (crtc->config.has_dp_encoder) | |
5115 | intel_dp_set_m_n(crtc); | |
eb1cbe48 DV |
5116 | } |
5117 | ||
f47709a9 | 5118 | static void i8xx_update_pll(struct intel_crtc *crtc, |
f47709a9 | 5119 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
5120 | int num_connectors) |
5121 | { | |
f47709a9 | 5122 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 5123 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 5124 | u32 dpll; |
f47709a9 | 5125 | struct dpll *clock = &crtc->config.dpll; |
eb1cbe48 | 5126 | |
f47709a9 | 5127 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 5128 | |
eb1cbe48 DV |
5129 | dpll = DPLL_VGA_MODE_DIS; |
5130 | ||
f47709a9 | 5131 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
5132 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
5133 | } else { | |
5134 | if (clock->p1 == 2) | |
5135 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
5136 | else | |
5137 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5138 | if (clock->p2 == 4) | |
5139 | dpll |= PLL_P2_DIVIDE_BY_4; | |
5140 | } | |
5141 | ||
4a33e48d DV |
5142 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO)) |
5143 | dpll |= DPLL_DVO_2X_MODE; | |
5144 | ||
f47709a9 | 5145 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
5146 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
5147 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
5148 | else | |
5149 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5150 | ||
5151 | dpll |= DPLL_VCO_ENABLE; | |
8bcc2795 | 5152 | crtc->config.dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
5153 | } |
5154 | ||
8a654f3b | 5155 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
5156 | { |
5157 | struct drm_device *dev = intel_crtc->base.dev; | |
5158 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5159 | enum pipe pipe = intel_crtc->pipe; | |
3b117c8f | 5160 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
8a654f3b DV |
5161 | struct drm_display_mode *adjusted_mode = |
5162 | &intel_crtc->config.adjusted_mode; | |
4d8a62ea DV |
5163 | uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end; |
5164 | ||
5165 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
5166 | * the hw state checker will get angry at the mismatch. */ | |
5167 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
5168 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c PZ |
5169 | |
5170 | if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { | |
5171 | /* the chip adds 2 halflines automatically */ | |
4d8a62ea DV |
5172 | crtc_vtotal -= 1; |
5173 | crtc_vblank_end -= 1; | |
b0e77b9c PZ |
5174 | vsyncshift = adjusted_mode->crtc_hsync_start |
5175 | - adjusted_mode->crtc_htotal / 2; | |
5176 | } else { | |
5177 | vsyncshift = 0; | |
5178 | } | |
5179 | ||
5180 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 5181 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 5182 | |
fe2b8f9d | 5183 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
5184 | (adjusted_mode->crtc_hdisplay - 1) | |
5185 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 5186 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
5187 | (adjusted_mode->crtc_hblank_start - 1) | |
5188 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 5189 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
5190 | (adjusted_mode->crtc_hsync_start - 1) | |
5191 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
5192 | ||
fe2b8f9d | 5193 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 5194 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 5195 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 5196 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 5197 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 5198 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 5199 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
5200 | (adjusted_mode->crtc_vsync_start - 1) | |
5201 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
5202 | ||
b5e508d4 PZ |
5203 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
5204 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
5205 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
5206 | * bits. */ | |
5207 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
5208 | (pipe == PIPE_B || pipe == PIPE_C)) | |
5209 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
5210 | ||
b0e77b9c PZ |
5211 | /* pipesrc controls the size that is scaled from, which should |
5212 | * always be the user's requested size. | |
5213 | */ | |
5214 | I915_WRITE(PIPESRC(pipe), | |
37327abd VS |
5215 | ((intel_crtc->config.pipe_src_w - 1) << 16) | |
5216 | (intel_crtc->config.pipe_src_h - 1)); | |
b0e77b9c PZ |
5217 | } |
5218 | ||
1bd1bd80 DV |
5219 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5220 | struct intel_crtc_config *pipe_config) | |
5221 | { | |
5222 | struct drm_device *dev = crtc->base.dev; | |
5223 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5224 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
5225 | uint32_t tmp; | |
5226 | ||
5227 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
5228 | pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; | |
5229 | pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
5230 | tmp = I915_READ(HBLANK(cpu_transcoder)); | |
5231 | pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; | |
5232 | pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
5233 | tmp = I915_READ(HSYNC(cpu_transcoder)); | |
5234 | pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; | |
5235 | pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
5236 | ||
5237 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
5238 | pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; | |
5239 | pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
5240 | tmp = I915_READ(VBLANK(cpu_transcoder)); | |
5241 | pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; | |
5242 | pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
5243 | tmp = I915_READ(VSYNC(cpu_transcoder)); | |
5244 | pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; | |
5245 | pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
5246 | ||
5247 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
5248 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; | |
5249 | pipe_config->adjusted_mode.crtc_vtotal += 1; | |
5250 | pipe_config->adjusted_mode.crtc_vblank_end += 1; | |
5251 | } | |
5252 | ||
5253 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
5254 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
5255 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
5256 | ||
5257 | pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h; | |
5258 | pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
5259 | } |
5260 | ||
babea61d JB |
5261 | static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc, |
5262 | struct intel_crtc_config *pipe_config) | |
5263 | { | |
5264 | struct drm_crtc *crtc = &intel_crtc->base; | |
5265 | ||
5266 | crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay; | |
5267 | crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal; | |
5268 | crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start; | |
5269 | crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end; | |
5270 | ||
5271 | crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay; | |
5272 | crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal; | |
5273 | crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start; | |
5274 | crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end; | |
5275 | ||
5276 | crtc->mode.flags = pipe_config->adjusted_mode.flags; | |
5277 | ||
241bfc38 | 5278 | crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock; |
babea61d JB |
5279 | crtc->mode.flags |= pipe_config->adjusted_mode.flags; |
5280 | } | |
5281 | ||
84b046f3 DV |
5282 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
5283 | { | |
5284 | struct drm_device *dev = intel_crtc->base.dev; | |
5285 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5286 | uint32_t pipeconf; | |
5287 | ||
9f11a9e4 | 5288 | pipeconf = 0; |
84b046f3 | 5289 | |
67c72a12 DV |
5290 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
5291 | I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE) | |
5292 | pipeconf |= PIPECONF_ENABLE; | |
5293 | ||
cf532bb2 VS |
5294 | if (intel_crtc->config.double_wide) |
5295 | pipeconf |= PIPECONF_DOUBLE_WIDE; | |
84b046f3 | 5296 | |
ff9ce46e DV |
5297 | /* only g4x and later have fancy bpc/dither controls */ |
5298 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { | |
ff9ce46e DV |
5299 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
5300 | if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30) | |
5301 | pipeconf |= PIPECONF_DITHER_EN | | |
84b046f3 | 5302 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 5303 | |
ff9ce46e DV |
5304 | switch (intel_crtc->config.pipe_bpp) { |
5305 | case 18: | |
5306 | pipeconf |= PIPECONF_6BPC; | |
5307 | break; | |
5308 | case 24: | |
5309 | pipeconf |= PIPECONF_8BPC; | |
5310 | break; | |
5311 | case 30: | |
5312 | pipeconf |= PIPECONF_10BPC; | |
5313 | break; | |
5314 | default: | |
5315 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
5316 | BUG(); | |
84b046f3 DV |
5317 | } |
5318 | } | |
5319 | ||
5320 | if (HAS_PIPE_CXSR(dev)) { | |
5321 | if (intel_crtc->lowfreq_avail) { | |
5322 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
5323 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
5324 | } else { | |
5325 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
5326 | } |
5327 | } | |
5328 | ||
84b046f3 DV |
5329 | if (!IS_GEN2(dev) && |
5330 | intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) | |
5331 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; | |
5332 | else | |
5333 | pipeconf |= PIPECONF_PROGRESSIVE; | |
5334 | ||
9f11a9e4 DV |
5335 | if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range) |
5336 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; | |
9c8e09b7 | 5337 | |
84b046f3 DV |
5338 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
5339 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
5340 | } | |
5341 | ||
f564048e | 5342 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
f564048e | 5343 | int x, int y, |
94352cf9 | 5344 | struct drm_framebuffer *fb) |
79e53945 JB |
5345 | { |
5346 | struct drm_device *dev = crtc->dev; | |
5347 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5348 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5349 | int pipe = intel_crtc->pipe; | |
80824003 | 5350 | int plane = intel_crtc->plane; |
c751ce4f | 5351 | int refclk, num_connectors = 0; |
652c393a | 5352 | intel_clock_t clock, reduced_clock; |
84b046f3 | 5353 | u32 dspcntr; |
a16af721 | 5354 | bool ok, has_reduced_clock = false; |
e9fd1c02 | 5355 | bool is_lvds = false, is_dsi = false; |
5eddb70b | 5356 | struct intel_encoder *encoder; |
d4906093 | 5357 | const intel_limit_t *limit; |
5c3b82e2 | 5358 | int ret; |
79e53945 | 5359 | |
6c2b7c12 | 5360 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5eddb70b | 5361 | switch (encoder->type) { |
79e53945 JB |
5362 | case INTEL_OUTPUT_LVDS: |
5363 | is_lvds = true; | |
5364 | break; | |
e9fd1c02 JN |
5365 | case INTEL_OUTPUT_DSI: |
5366 | is_dsi = true; | |
5367 | break; | |
79e53945 | 5368 | } |
43565a06 | 5369 | |
c751ce4f | 5370 | num_connectors++; |
79e53945 JB |
5371 | } |
5372 | ||
f2335330 JN |
5373 | if (is_dsi) |
5374 | goto skip_dpll; | |
5375 | ||
5376 | if (!intel_crtc->config.clock_set) { | |
5377 | refclk = i9xx_get_refclk(crtc, num_connectors); | |
79e53945 | 5378 | |
e9fd1c02 JN |
5379 | /* |
5380 | * Returns a set of divisors for the desired target clock with | |
5381 | * the given refclk, or FALSE. The returned values represent | |
5382 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
5383 | * 2) / p1 / p2. | |
5384 | */ | |
5385 | limit = intel_limit(crtc, refclk); | |
5386 | ok = dev_priv->display.find_dpll(limit, crtc, | |
5387 | intel_crtc->config.port_clock, | |
5388 | refclk, NULL, &clock); | |
f2335330 | 5389 | if (!ok) { |
e9fd1c02 JN |
5390 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
5391 | return -EINVAL; | |
5392 | } | |
79e53945 | 5393 | |
f2335330 JN |
5394 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
5395 | /* | |
5396 | * Ensure we match the reduced clock's P to the target | |
5397 | * clock. If the clocks don't match, we can't switch | |
5398 | * the display clock by using the FP0/FP1. In such case | |
5399 | * we will disable the LVDS downclock feature. | |
5400 | */ | |
5401 | has_reduced_clock = | |
5402 | dev_priv->display.find_dpll(limit, crtc, | |
5403 | dev_priv->lvds_downclock, | |
5404 | refclk, &clock, | |
5405 | &reduced_clock); | |
5406 | } | |
5407 | /* Compat-code for transition, will disappear. */ | |
f47709a9 DV |
5408 | intel_crtc->config.dpll.n = clock.n; |
5409 | intel_crtc->config.dpll.m1 = clock.m1; | |
5410 | intel_crtc->config.dpll.m2 = clock.m2; | |
5411 | intel_crtc->config.dpll.p1 = clock.p1; | |
5412 | intel_crtc->config.dpll.p2 = clock.p2; | |
5413 | } | |
7026d4ac | 5414 | |
e9fd1c02 | 5415 | if (IS_GEN2(dev)) { |
8a654f3b | 5416 | i8xx_update_pll(intel_crtc, |
2a8f64ca VP |
5417 | has_reduced_clock ? &reduced_clock : NULL, |
5418 | num_connectors); | |
e9fd1c02 | 5419 | } else if (IS_VALLEYVIEW(dev)) { |
f2335330 | 5420 | vlv_update_pll(intel_crtc); |
e9fd1c02 | 5421 | } else { |
f47709a9 | 5422 | i9xx_update_pll(intel_crtc, |
eb1cbe48 | 5423 | has_reduced_clock ? &reduced_clock : NULL, |
89b667f8 | 5424 | num_connectors); |
e9fd1c02 | 5425 | } |
79e53945 | 5426 | |
f2335330 | 5427 | skip_dpll: |
79e53945 JB |
5428 | /* Set up the display plane register */ |
5429 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
5430 | ||
da6ecc5d JB |
5431 | if (!IS_VALLEYVIEW(dev)) { |
5432 | if (pipe == 0) | |
5433 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; | |
5434 | else | |
5435 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
5436 | } | |
79e53945 | 5437 | |
8a654f3b | 5438 | intel_set_pipe_timings(intel_crtc); |
5eddb70b CW |
5439 | |
5440 | /* pipesrc and dspsize control the size that is scaled from, | |
5441 | * which should always be the user's requested size. | |
79e53945 | 5442 | */ |
929c77fb | 5443 | I915_WRITE(DSPSIZE(plane), |
37327abd VS |
5444 | ((intel_crtc->config.pipe_src_h - 1) << 16) | |
5445 | (intel_crtc->config.pipe_src_w - 1)); | |
929c77fb | 5446 | I915_WRITE(DSPPOS(plane), 0); |
2c07245f | 5447 | |
84b046f3 DV |
5448 | i9xx_set_pipeconf(intel_crtc); |
5449 | ||
f564048e EA |
5450 | I915_WRITE(DSPCNTR(plane), dspcntr); |
5451 | POSTING_READ(DSPCNTR(plane)); | |
5452 | ||
94352cf9 | 5453 | ret = intel_pipe_set_base(crtc, x, y, fb); |
f564048e | 5454 | |
f564048e EA |
5455 | return ret; |
5456 | } | |
5457 | ||
2fa2fe9a DV |
5458 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5459 | struct intel_crtc_config *pipe_config) | |
5460 | { | |
5461 | struct drm_device *dev = crtc->base.dev; | |
5462 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5463 | uint32_t tmp; | |
5464 | ||
dc9e7dec VS |
5465 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
5466 | return; | |
5467 | ||
2fa2fe9a | 5468 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
5469 | if (!(tmp & PFIT_ENABLE)) |
5470 | return; | |
2fa2fe9a | 5471 | |
06922821 | 5472 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
5473 | if (INTEL_INFO(dev)->gen < 4) { |
5474 | if (crtc->pipe != PIPE_B) | |
5475 | return; | |
2fa2fe9a DV |
5476 | } else { |
5477 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
5478 | return; | |
5479 | } | |
5480 | ||
06922821 | 5481 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
5482 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
5483 | if (INTEL_INFO(dev)->gen < 5) | |
5484 | pipe_config->gmch_pfit.lvds_border_bits = | |
5485 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
5486 | } | |
5487 | ||
acbec814 JB |
5488 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5489 | struct intel_crtc_config *pipe_config) | |
5490 | { | |
5491 | struct drm_device *dev = crtc->base.dev; | |
5492 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5493 | int pipe = pipe_config->cpu_transcoder; | |
5494 | intel_clock_t clock; | |
5495 | u32 mdiv; | |
662c6ecb | 5496 | int refclk = 100000; |
acbec814 JB |
5497 | |
5498 | mutex_lock(&dev_priv->dpio_lock); | |
ab3c759a | 5499 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
acbec814 JB |
5500 | mutex_unlock(&dev_priv->dpio_lock); |
5501 | ||
5502 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
5503 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
5504 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
5505 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
5506 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
5507 | ||
f646628b | 5508 | vlv_clock(refclk, &clock); |
acbec814 | 5509 | |
f646628b VS |
5510 | /* clock.dot is the fast clock */ |
5511 | pipe_config->port_clock = clock.dot / 5; | |
acbec814 JB |
5512 | } |
5513 | ||
0e8ffe1b DV |
5514 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5515 | struct intel_crtc_config *pipe_config) | |
5516 | { | |
5517 | struct drm_device *dev = crtc->base.dev; | |
5518 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5519 | uint32_t tmp; | |
5520 | ||
e143a21c | 5521 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 5522 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 5523 | |
0e8ffe1b DV |
5524 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
5525 | if (!(tmp & PIPECONF_ENABLE)) | |
5526 | return false; | |
5527 | ||
42571aef VS |
5528 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
5529 | switch (tmp & PIPECONF_BPC_MASK) { | |
5530 | case PIPECONF_6BPC: | |
5531 | pipe_config->pipe_bpp = 18; | |
5532 | break; | |
5533 | case PIPECONF_8BPC: | |
5534 | pipe_config->pipe_bpp = 24; | |
5535 | break; | |
5536 | case PIPECONF_10BPC: | |
5537 | pipe_config->pipe_bpp = 30; | |
5538 | break; | |
5539 | default: | |
5540 | break; | |
5541 | } | |
5542 | } | |
5543 | ||
282740f7 VS |
5544 | if (INTEL_INFO(dev)->gen < 4) |
5545 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
5546 | ||
1bd1bd80 DV |
5547 | intel_get_pipe_timings(crtc, pipe_config); |
5548 | ||
2fa2fe9a DV |
5549 | i9xx_get_pfit_config(crtc, pipe_config); |
5550 | ||
6c49f241 DV |
5551 | if (INTEL_INFO(dev)->gen >= 4) { |
5552 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
5553 | pipe_config->pixel_multiplier = | |
5554 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
5555 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 5556 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
5557 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
5558 | tmp = I915_READ(DPLL(crtc->pipe)); | |
5559 | pipe_config->pixel_multiplier = | |
5560 | ((tmp & SDVO_MULTIPLIER_MASK) | |
5561 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
5562 | } else { | |
5563 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
5564 | * port and will be fixed up in the encoder->get_config | |
5565 | * function. */ | |
5566 | pipe_config->pixel_multiplier = 1; | |
5567 | } | |
8bcc2795 DV |
5568 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
5569 | if (!IS_VALLEYVIEW(dev)) { | |
5570 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); | |
5571 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
5572 | } else { |
5573 | /* Mask out read-only status bits. */ | |
5574 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
5575 | DPLL_PORTC_READY_MASK | | |
5576 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 5577 | } |
6c49f241 | 5578 | |
acbec814 JB |
5579 | if (IS_VALLEYVIEW(dev)) |
5580 | vlv_crtc_clock_get(crtc, pipe_config); | |
5581 | else | |
5582 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 5583 | |
0e8ffe1b DV |
5584 | return true; |
5585 | } | |
5586 | ||
dde86e2d | 5587 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
5588 | { |
5589 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5590 | struct drm_mode_config *mode_config = &dev->mode_config; | |
13d83a67 | 5591 | struct intel_encoder *encoder; |
74cfd7ac | 5592 | u32 val, final; |
13d83a67 | 5593 | bool has_lvds = false; |
199e5d79 | 5594 | bool has_cpu_edp = false; |
199e5d79 | 5595 | bool has_panel = false; |
99eb6a01 KP |
5596 | bool has_ck505 = false; |
5597 | bool can_ssc = false; | |
13d83a67 JB |
5598 | |
5599 | /* We need to take the global config into account */ | |
199e5d79 KP |
5600 | list_for_each_entry(encoder, &mode_config->encoder_list, |
5601 | base.head) { | |
5602 | switch (encoder->type) { | |
5603 | case INTEL_OUTPUT_LVDS: | |
5604 | has_panel = true; | |
5605 | has_lvds = true; | |
5606 | break; | |
5607 | case INTEL_OUTPUT_EDP: | |
5608 | has_panel = true; | |
2de6905f | 5609 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
5610 | has_cpu_edp = true; |
5611 | break; | |
13d83a67 JB |
5612 | } |
5613 | } | |
5614 | ||
99eb6a01 | 5615 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 5616 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
5617 | can_ssc = has_ck505; |
5618 | } else { | |
5619 | has_ck505 = false; | |
5620 | can_ssc = true; | |
5621 | } | |
5622 | ||
2de6905f ID |
5623 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
5624 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
5625 | |
5626 | /* Ironlake: try to setup display ref clock before DPLL | |
5627 | * enabling. This is only under driver's control after | |
5628 | * PCH B stepping, previous chipset stepping should be | |
5629 | * ignoring this setting. | |
5630 | */ | |
74cfd7ac CW |
5631 | val = I915_READ(PCH_DREF_CONTROL); |
5632 | ||
5633 | /* As we must carefully and slowly disable/enable each source in turn, | |
5634 | * compute the final state we want first and check if we need to | |
5635 | * make any changes at all. | |
5636 | */ | |
5637 | final = val; | |
5638 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
5639 | if (has_ck505) | |
5640 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
5641 | else | |
5642 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
5643 | ||
5644 | final &= ~DREF_SSC_SOURCE_MASK; | |
5645 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
5646 | final &= ~DREF_SSC1_ENABLE; | |
5647 | ||
5648 | if (has_panel) { | |
5649 | final |= DREF_SSC_SOURCE_ENABLE; | |
5650 | ||
5651 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
5652 | final |= DREF_SSC1_ENABLE; | |
5653 | ||
5654 | if (has_cpu_edp) { | |
5655 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
5656 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
5657 | else | |
5658 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
5659 | } else | |
5660 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
5661 | } else { | |
5662 | final |= DREF_SSC_SOURCE_DISABLE; | |
5663 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
5664 | } | |
5665 | ||
5666 | if (final == val) | |
5667 | return; | |
5668 | ||
13d83a67 | 5669 | /* Always enable nonspread source */ |
74cfd7ac | 5670 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 5671 | |
99eb6a01 | 5672 | if (has_ck505) |
74cfd7ac | 5673 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 5674 | else |
74cfd7ac | 5675 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 5676 | |
199e5d79 | 5677 | if (has_panel) { |
74cfd7ac CW |
5678 | val &= ~DREF_SSC_SOURCE_MASK; |
5679 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 5680 | |
199e5d79 | 5681 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 5682 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 5683 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 5684 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 5685 | } else |
74cfd7ac | 5686 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
5687 | |
5688 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 5689 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
5690 | POSTING_READ(PCH_DREF_CONTROL); |
5691 | udelay(200); | |
5692 | ||
74cfd7ac | 5693 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
5694 | |
5695 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 5696 | if (has_cpu_edp) { |
99eb6a01 | 5697 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 5698 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 5699 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
199e5d79 | 5700 | } |
13d83a67 | 5701 | else |
74cfd7ac | 5702 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 5703 | } else |
74cfd7ac | 5704 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 5705 | |
74cfd7ac | 5706 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
5707 | POSTING_READ(PCH_DREF_CONTROL); |
5708 | udelay(200); | |
5709 | } else { | |
5710 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
5711 | ||
74cfd7ac | 5712 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
5713 | |
5714 | /* Turn off CPU output */ | |
74cfd7ac | 5715 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 5716 | |
74cfd7ac | 5717 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
5718 | POSTING_READ(PCH_DREF_CONTROL); |
5719 | udelay(200); | |
5720 | ||
5721 | /* Turn off the SSC source */ | |
74cfd7ac CW |
5722 | val &= ~DREF_SSC_SOURCE_MASK; |
5723 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
5724 | |
5725 | /* Turn off SSC1 */ | |
74cfd7ac | 5726 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 5727 | |
74cfd7ac | 5728 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
5729 | POSTING_READ(PCH_DREF_CONTROL); |
5730 | udelay(200); | |
5731 | } | |
74cfd7ac CW |
5732 | |
5733 | BUG_ON(val != final); | |
13d83a67 JB |
5734 | } |
5735 | ||
f31f2d55 | 5736 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 5737 | { |
f31f2d55 | 5738 | uint32_t tmp; |
dde86e2d | 5739 | |
0ff066a9 PZ |
5740 | tmp = I915_READ(SOUTH_CHICKEN2); |
5741 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
5742 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 5743 | |
0ff066a9 PZ |
5744 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
5745 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
5746 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 5747 | |
0ff066a9 PZ |
5748 | tmp = I915_READ(SOUTH_CHICKEN2); |
5749 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
5750 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 5751 | |
0ff066a9 PZ |
5752 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
5753 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
5754 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
5755 | } |
5756 | ||
5757 | /* WaMPhyProgramming:hsw */ | |
5758 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
5759 | { | |
5760 | uint32_t tmp; | |
dde86e2d PZ |
5761 | |
5762 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
5763 | tmp &= ~(0xFF << 24); | |
5764 | tmp |= (0x12 << 24); | |
5765 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
5766 | ||
dde86e2d PZ |
5767 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
5768 | tmp |= (1 << 11); | |
5769 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
5770 | ||
5771 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
5772 | tmp |= (1 << 11); | |
5773 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
5774 | ||
dde86e2d PZ |
5775 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
5776 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
5777 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
5778 | ||
5779 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
5780 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
5781 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
5782 | ||
0ff066a9 PZ |
5783 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
5784 | tmp &= ~(7 << 13); | |
5785 | tmp |= (5 << 13); | |
5786 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 5787 | |
0ff066a9 PZ |
5788 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
5789 | tmp &= ~(7 << 13); | |
5790 | tmp |= (5 << 13); | |
5791 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
5792 | |
5793 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
5794 | tmp &= ~0xFF; | |
5795 | tmp |= 0x1C; | |
5796 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
5797 | ||
5798 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
5799 | tmp &= ~0xFF; | |
5800 | tmp |= 0x1C; | |
5801 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
5802 | ||
5803 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
5804 | tmp &= ~(0xFF << 16); | |
5805 | tmp |= (0x1C << 16); | |
5806 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
5807 | ||
5808 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
5809 | tmp &= ~(0xFF << 16); | |
5810 | tmp |= (0x1C << 16); | |
5811 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
5812 | ||
0ff066a9 PZ |
5813 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
5814 | tmp |= (1 << 27); | |
5815 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 5816 | |
0ff066a9 PZ |
5817 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
5818 | tmp |= (1 << 27); | |
5819 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 5820 | |
0ff066a9 PZ |
5821 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
5822 | tmp &= ~(0xF << 28); | |
5823 | tmp |= (4 << 28); | |
5824 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 5825 | |
0ff066a9 PZ |
5826 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
5827 | tmp &= ~(0xF << 28); | |
5828 | tmp |= (4 << 28); | |
5829 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
5830 | } |
5831 | ||
2fa86a1f PZ |
5832 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
5833 | * Programming" based on the parameters passed: | |
5834 | * - Sequence to enable CLKOUT_DP | |
5835 | * - Sequence to enable CLKOUT_DP without spread | |
5836 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
5837 | */ | |
5838 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
5839 | bool with_fdi) | |
f31f2d55 PZ |
5840 | { |
5841 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
5842 | uint32_t reg, tmp; |
5843 | ||
5844 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
5845 | with_spread = true; | |
5846 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && | |
5847 | with_fdi, "LP PCH doesn't have FDI\n")) | |
5848 | with_fdi = false; | |
f31f2d55 PZ |
5849 | |
5850 | mutex_lock(&dev_priv->dpio_lock); | |
5851 | ||
5852 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
5853 | tmp &= ~SBI_SSCCTL_DISABLE; | |
5854 | tmp |= SBI_SSCCTL_PATHALT; | |
5855 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
5856 | ||
5857 | udelay(24); | |
5858 | ||
2fa86a1f PZ |
5859 | if (with_spread) { |
5860 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
5861 | tmp &= ~SBI_SSCCTL_PATHALT; | |
5862 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 5863 | |
2fa86a1f PZ |
5864 | if (with_fdi) { |
5865 | lpt_reset_fdi_mphy(dev_priv); | |
5866 | lpt_program_fdi_mphy(dev_priv); | |
5867 | } | |
5868 | } | |
dde86e2d | 5869 | |
2fa86a1f PZ |
5870 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
5871 | SBI_GEN0 : SBI_DBUFF0; | |
5872 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
5873 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
5874 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 DV |
5875 | |
5876 | mutex_unlock(&dev_priv->dpio_lock); | |
dde86e2d PZ |
5877 | } |
5878 | ||
47701c3b PZ |
5879 | /* Sequence to disable CLKOUT_DP */ |
5880 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
5881 | { | |
5882 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5883 | uint32_t reg, tmp; | |
5884 | ||
5885 | mutex_lock(&dev_priv->dpio_lock); | |
5886 | ||
5887 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? | |
5888 | SBI_GEN0 : SBI_DBUFF0; | |
5889 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
5890 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
5891 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
5892 | ||
5893 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
5894 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
5895 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
5896 | tmp |= SBI_SSCCTL_PATHALT; | |
5897 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
5898 | udelay(32); | |
5899 | } | |
5900 | tmp |= SBI_SSCCTL_DISABLE; | |
5901 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
5902 | } | |
5903 | ||
5904 | mutex_unlock(&dev_priv->dpio_lock); | |
5905 | } | |
5906 | ||
bf8fa3d3 PZ |
5907 | static void lpt_init_pch_refclk(struct drm_device *dev) |
5908 | { | |
5909 | struct drm_mode_config *mode_config = &dev->mode_config; | |
5910 | struct intel_encoder *encoder; | |
5911 | bool has_vga = false; | |
5912 | ||
5913 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { | |
5914 | switch (encoder->type) { | |
5915 | case INTEL_OUTPUT_ANALOG: | |
5916 | has_vga = true; | |
5917 | break; | |
5918 | } | |
5919 | } | |
5920 | ||
47701c3b PZ |
5921 | if (has_vga) |
5922 | lpt_enable_clkout_dp(dev, true, true); | |
5923 | else | |
5924 | lpt_disable_clkout_dp(dev); | |
bf8fa3d3 PZ |
5925 | } |
5926 | ||
dde86e2d PZ |
5927 | /* |
5928 | * Initialize reference clocks when the driver loads | |
5929 | */ | |
5930 | void intel_init_pch_refclk(struct drm_device *dev) | |
5931 | { | |
5932 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
5933 | ironlake_init_pch_refclk(dev); | |
5934 | else if (HAS_PCH_LPT(dev)) | |
5935 | lpt_init_pch_refclk(dev); | |
5936 | } | |
5937 | ||
d9d444cb JB |
5938 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
5939 | { | |
5940 | struct drm_device *dev = crtc->dev; | |
5941 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5942 | struct intel_encoder *encoder; | |
d9d444cb JB |
5943 | int num_connectors = 0; |
5944 | bool is_lvds = false; | |
5945 | ||
6c2b7c12 | 5946 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
d9d444cb JB |
5947 | switch (encoder->type) { |
5948 | case INTEL_OUTPUT_LVDS: | |
5949 | is_lvds = true; | |
5950 | break; | |
d9d444cb JB |
5951 | } |
5952 | num_connectors++; | |
5953 | } | |
5954 | ||
5955 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 5956 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 5957 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 5958 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
5959 | } |
5960 | ||
5961 | return 120000; | |
5962 | } | |
5963 | ||
6ff93609 | 5964 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 5965 | { |
c8203565 | 5966 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
5967 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5968 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
5969 | uint32_t val; |
5970 | ||
78114071 | 5971 | val = 0; |
c8203565 | 5972 | |
965e0c48 | 5973 | switch (intel_crtc->config.pipe_bpp) { |
c8203565 | 5974 | case 18: |
dfd07d72 | 5975 | val |= PIPECONF_6BPC; |
c8203565 PZ |
5976 | break; |
5977 | case 24: | |
dfd07d72 | 5978 | val |= PIPECONF_8BPC; |
c8203565 PZ |
5979 | break; |
5980 | case 30: | |
dfd07d72 | 5981 | val |= PIPECONF_10BPC; |
c8203565 PZ |
5982 | break; |
5983 | case 36: | |
dfd07d72 | 5984 | val |= PIPECONF_12BPC; |
c8203565 PZ |
5985 | break; |
5986 | default: | |
cc769b62 PZ |
5987 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
5988 | BUG(); | |
c8203565 PZ |
5989 | } |
5990 | ||
d8b32247 | 5991 | if (intel_crtc->config.dither) |
c8203565 PZ |
5992 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
5993 | ||
6ff93609 | 5994 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
5995 | val |= PIPECONF_INTERLACED_ILK; |
5996 | else | |
5997 | val |= PIPECONF_PROGRESSIVE; | |
5998 | ||
50f3b016 | 5999 | if (intel_crtc->config.limited_color_range) |
3685a8f3 | 6000 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 6001 | |
c8203565 PZ |
6002 | I915_WRITE(PIPECONF(pipe), val); |
6003 | POSTING_READ(PIPECONF(pipe)); | |
6004 | } | |
6005 | ||
86d3efce VS |
6006 | /* |
6007 | * Set up the pipe CSC unit. | |
6008 | * | |
6009 | * Currently only full range RGB to limited range RGB conversion | |
6010 | * is supported, but eventually this should handle various | |
6011 | * RGB<->YCbCr scenarios as well. | |
6012 | */ | |
50f3b016 | 6013 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
6014 | { |
6015 | struct drm_device *dev = crtc->dev; | |
6016 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6017 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6018 | int pipe = intel_crtc->pipe; | |
6019 | uint16_t coeff = 0x7800; /* 1.0 */ | |
6020 | ||
6021 | /* | |
6022 | * TODO: Check what kind of values actually come out of the pipe | |
6023 | * with these coeff/postoff values and adjust to get the best | |
6024 | * accuracy. Perhaps we even need to take the bpc value into | |
6025 | * consideration. | |
6026 | */ | |
6027 | ||
50f3b016 | 6028 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
6029 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
6030 | ||
6031 | /* | |
6032 | * GY/GU and RY/RU should be the other way around according | |
6033 | * to BSpec, but reality doesn't agree. Just set them up in | |
6034 | * a way that results in the correct picture. | |
6035 | */ | |
6036 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
6037 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
6038 | ||
6039 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
6040 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
6041 | ||
6042 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
6043 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
6044 | ||
6045 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
6046 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
6047 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
6048 | ||
6049 | if (INTEL_INFO(dev)->gen > 6) { | |
6050 | uint16_t postoff = 0; | |
6051 | ||
50f3b016 | 6052 | if (intel_crtc->config.limited_color_range) |
32cf0cb0 | 6053 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
6054 | |
6055 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
6056 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
6057 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
6058 | ||
6059 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
6060 | } else { | |
6061 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
6062 | ||
50f3b016 | 6063 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
6064 | mode |= CSC_BLACK_SCREEN_OFFSET; |
6065 | ||
6066 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
6067 | } | |
6068 | } | |
6069 | ||
6ff93609 | 6070 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 6071 | { |
756f85cf PZ |
6072 | struct drm_device *dev = crtc->dev; |
6073 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 6074 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 6075 | enum pipe pipe = intel_crtc->pipe; |
3b117c8f | 6076 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee2b0b38 PZ |
6077 | uint32_t val; |
6078 | ||
3eff4faa | 6079 | val = 0; |
ee2b0b38 | 6080 | |
756f85cf | 6081 | if (IS_HASWELL(dev) && intel_crtc->config.dither) |
ee2b0b38 PZ |
6082 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
6083 | ||
6ff93609 | 6084 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
6085 | val |= PIPECONF_INTERLACED_ILK; |
6086 | else | |
6087 | val |= PIPECONF_PROGRESSIVE; | |
6088 | ||
702e7a56 PZ |
6089 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
6090 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
6091 | |
6092 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
6093 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf PZ |
6094 | |
6095 | if (IS_BROADWELL(dev)) { | |
6096 | val = 0; | |
6097 | ||
6098 | switch (intel_crtc->config.pipe_bpp) { | |
6099 | case 18: | |
6100 | val |= PIPEMISC_DITHER_6_BPC; | |
6101 | break; | |
6102 | case 24: | |
6103 | val |= PIPEMISC_DITHER_8_BPC; | |
6104 | break; | |
6105 | case 30: | |
6106 | val |= PIPEMISC_DITHER_10_BPC; | |
6107 | break; | |
6108 | case 36: | |
6109 | val |= PIPEMISC_DITHER_12_BPC; | |
6110 | break; | |
6111 | default: | |
6112 | /* Case prevented by pipe_config_set_bpp. */ | |
6113 | BUG(); | |
6114 | } | |
6115 | ||
6116 | if (intel_crtc->config.dither) | |
6117 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; | |
6118 | ||
6119 | I915_WRITE(PIPEMISC(pipe), val); | |
6120 | } | |
ee2b0b38 PZ |
6121 | } |
6122 | ||
6591c6e4 | 6123 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
6591c6e4 PZ |
6124 | intel_clock_t *clock, |
6125 | bool *has_reduced_clock, | |
6126 | intel_clock_t *reduced_clock) | |
6127 | { | |
6128 | struct drm_device *dev = crtc->dev; | |
6129 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6130 | struct intel_encoder *intel_encoder; | |
6131 | int refclk; | |
d4906093 | 6132 | const intel_limit_t *limit; |
a16af721 | 6133 | bool ret, is_lvds = false; |
79e53945 | 6134 | |
6591c6e4 PZ |
6135 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
6136 | switch (intel_encoder->type) { | |
79e53945 JB |
6137 | case INTEL_OUTPUT_LVDS: |
6138 | is_lvds = true; | |
6139 | break; | |
79e53945 JB |
6140 | } |
6141 | } | |
6142 | ||
d9d444cb | 6143 | refclk = ironlake_get_refclk(crtc); |
79e53945 | 6144 | |
d4906093 ML |
6145 | /* |
6146 | * Returns a set of divisors for the desired target clock with the given | |
6147 | * refclk, or FALSE. The returned values represent the clock equation: | |
6148 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
6149 | */ | |
1b894b59 | 6150 | limit = intel_limit(crtc, refclk); |
ff9a6750 DV |
6151 | ret = dev_priv->display.find_dpll(limit, crtc, |
6152 | to_intel_crtc(crtc)->config.port_clock, | |
ee9300bb | 6153 | refclk, NULL, clock); |
6591c6e4 PZ |
6154 | if (!ret) |
6155 | return false; | |
cda4b7d3 | 6156 | |
ddc9003c | 6157 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
6158 | /* |
6159 | * Ensure we match the reduced clock's P to the target clock. | |
6160 | * If the clocks don't match, we can't switch the display clock | |
6161 | * by using the FP0/FP1. In such case we will disable the LVDS | |
6162 | * downclock feature. | |
6163 | */ | |
ee9300bb DV |
6164 | *has_reduced_clock = |
6165 | dev_priv->display.find_dpll(limit, crtc, | |
6166 | dev_priv->lvds_downclock, | |
6167 | refclk, clock, | |
6168 | reduced_clock); | |
652c393a | 6169 | } |
61e9653f | 6170 | |
6591c6e4 PZ |
6171 | return true; |
6172 | } | |
6173 | ||
d4b1931c PZ |
6174 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
6175 | { | |
6176 | /* | |
6177 | * Account for spread spectrum to avoid | |
6178 | * oversubscribing the link. Max center spread | |
6179 | * is 2.5%; use 5% for safety's sake. | |
6180 | */ | |
6181 | u32 bps = target_clock * bpp * 21 / 20; | |
6182 | return bps / (link_bw * 8) + 1; | |
6183 | } | |
6184 | ||
7429e9d4 | 6185 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 6186 | { |
7429e9d4 | 6187 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
6188 | } |
6189 | ||
de13a2e3 | 6190 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
7429e9d4 | 6191 | u32 *fp, |
9a7c7890 | 6192 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 6193 | { |
de13a2e3 | 6194 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
6195 | struct drm_device *dev = crtc->dev; |
6196 | struct drm_i915_private *dev_priv = dev->dev_private; | |
de13a2e3 PZ |
6197 | struct intel_encoder *intel_encoder; |
6198 | uint32_t dpll; | |
6cc5f341 | 6199 | int factor, num_connectors = 0; |
09ede541 | 6200 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 6201 | |
de13a2e3 PZ |
6202 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
6203 | switch (intel_encoder->type) { | |
79e53945 JB |
6204 | case INTEL_OUTPUT_LVDS: |
6205 | is_lvds = true; | |
6206 | break; | |
6207 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 6208 | case INTEL_OUTPUT_HDMI: |
79e53945 | 6209 | is_sdvo = true; |
79e53945 | 6210 | break; |
79e53945 | 6211 | } |
43565a06 | 6212 | |
c751ce4f | 6213 | num_connectors++; |
79e53945 | 6214 | } |
79e53945 | 6215 | |
c1858123 | 6216 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
6217 | factor = 21; |
6218 | if (is_lvds) { | |
6219 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 6220 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 6221 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 6222 | factor = 25; |
09ede541 | 6223 | } else if (intel_crtc->config.sdvo_tv_clock) |
8febb297 | 6224 | factor = 20; |
c1858123 | 6225 | |
7429e9d4 | 6226 | if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor)) |
7d0ac5b7 | 6227 | *fp |= FP_CB_TUNE; |
2c07245f | 6228 | |
9a7c7890 DV |
6229 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
6230 | *fp2 |= FP_CB_TUNE; | |
6231 | ||
5eddb70b | 6232 | dpll = 0; |
2c07245f | 6233 | |
a07d6787 EA |
6234 | if (is_lvds) |
6235 | dpll |= DPLLB_MODE_LVDS; | |
6236 | else | |
6237 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 6238 | |
ef1b460d DV |
6239 | dpll |= (intel_crtc->config.pixel_multiplier - 1) |
6240 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | |
198a037f DV |
6241 | |
6242 | if (is_sdvo) | |
4a33e48d | 6243 | dpll |= DPLL_SDVO_HIGH_SPEED; |
9566e9af | 6244 | if (intel_crtc->config.has_dp_encoder) |
4a33e48d | 6245 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 6246 | |
a07d6787 | 6247 | /* compute bitmask from p1 value */ |
7429e9d4 | 6248 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 6249 | /* also FPA1 */ |
7429e9d4 | 6250 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 6251 | |
7429e9d4 | 6252 | switch (intel_crtc->config.dpll.p2) { |
a07d6787 EA |
6253 | case 5: |
6254 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
6255 | break; | |
6256 | case 7: | |
6257 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
6258 | break; | |
6259 | case 10: | |
6260 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
6261 | break; | |
6262 | case 14: | |
6263 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
6264 | break; | |
79e53945 JB |
6265 | } |
6266 | ||
b4c09f3b | 6267 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 6268 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
6269 | else |
6270 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6271 | ||
959e16d6 | 6272 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
6273 | } |
6274 | ||
6275 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, | |
de13a2e3 PZ |
6276 | int x, int y, |
6277 | struct drm_framebuffer *fb) | |
6278 | { | |
6279 | struct drm_device *dev = crtc->dev; | |
6280 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6281 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6282 | int pipe = intel_crtc->pipe; | |
6283 | int plane = intel_crtc->plane; | |
6284 | int num_connectors = 0; | |
6285 | intel_clock_t clock, reduced_clock; | |
cbbab5bd | 6286 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 6287 | bool ok, has_reduced_clock = false; |
8b47047b | 6288 | bool is_lvds = false; |
de13a2e3 | 6289 | struct intel_encoder *encoder; |
e2b78267 | 6290 | struct intel_shared_dpll *pll; |
de13a2e3 | 6291 | int ret; |
de13a2e3 PZ |
6292 | |
6293 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
6294 | switch (encoder->type) { | |
6295 | case INTEL_OUTPUT_LVDS: | |
6296 | is_lvds = true; | |
6297 | break; | |
de13a2e3 PZ |
6298 | } |
6299 | ||
6300 | num_connectors++; | |
a07d6787 | 6301 | } |
79e53945 | 6302 | |
5dc5298b PZ |
6303 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
6304 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 6305 | |
ff9a6750 | 6306 | ok = ironlake_compute_clocks(crtc, &clock, |
de13a2e3 | 6307 | &has_reduced_clock, &reduced_clock); |
ee9300bb | 6308 | if (!ok && !intel_crtc->config.clock_set) { |
de13a2e3 PZ |
6309 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
6310 | return -EINVAL; | |
79e53945 | 6311 | } |
f47709a9 DV |
6312 | /* Compat-code for transition, will disappear. */ |
6313 | if (!intel_crtc->config.clock_set) { | |
6314 | intel_crtc->config.dpll.n = clock.n; | |
6315 | intel_crtc->config.dpll.m1 = clock.m1; | |
6316 | intel_crtc->config.dpll.m2 = clock.m2; | |
6317 | intel_crtc->config.dpll.p1 = clock.p1; | |
6318 | intel_crtc->config.dpll.p2 = clock.p2; | |
6319 | } | |
79e53945 | 6320 | |
5dc5298b | 6321 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
8b47047b | 6322 | if (intel_crtc->config.has_pch_encoder) { |
7429e9d4 | 6323 | fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll); |
cbbab5bd | 6324 | if (has_reduced_clock) |
7429e9d4 | 6325 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 6326 | |
7429e9d4 | 6327 | dpll = ironlake_compute_dpll(intel_crtc, |
cbbab5bd DV |
6328 | &fp, &reduced_clock, |
6329 | has_reduced_clock ? &fp2 : NULL); | |
6330 | ||
959e16d6 | 6331 | intel_crtc->config.dpll_hw_state.dpll = dpll; |
66e985c0 DV |
6332 | intel_crtc->config.dpll_hw_state.fp0 = fp; |
6333 | if (has_reduced_clock) | |
6334 | intel_crtc->config.dpll_hw_state.fp1 = fp2; | |
6335 | else | |
6336 | intel_crtc->config.dpll_hw_state.fp1 = fp; | |
6337 | ||
b89a1d39 | 6338 | pll = intel_get_shared_dpll(intel_crtc); |
ee7b9f93 | 6339 | if (pll == NULL) { |
84f44ce7 VS |
6340 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
6341 | pipe_name(pipe)); | |
4b645f14 JB |
6342 | return -EINVAL; |
6343 | } | |
ee7b9f93 | 6344 | } else |
e72f9fbf | 6345 | intel_put_shared_dpll(intel_crtc); |
79e53945 | 6346 | |
03afc4a2 DV |
6347 | if (intel_crtc->config.has_dp_encoder) |
6348 | intel_dp_set_m_n(intel_crtc); | |
79e53945 | 6349 | |
d330a953 | 6350 | if (is_lvds && has_reduced_clock && i915.powersave) |
bcd644e0 DV |
6351 | intel_crtc->lowfreq_avail = true; |
6352 | else | |
6353 | intel_crtc->lowfreq_avail = false; | |
e2b78267 | 6354 | |
8a654f3b | 6355 | intel_set_pipe_timings(intel_crtc); |
5eddb70b | 6356 | |
ca3a0ff8 | 6357 | if (intel_crtc->config.has_pch_encoder) { |
ca3a0ff8 DV |
6358 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6359 | &intel_crtc->config.fdi_m_n); | |
6360 | } | |
2c07245f | 6361 | |
6ff93609 | 6362 | ironlake_set_pipeconf(crtc); |
79e53945 | 6363 | |
a1f9e77e PZ |
6364 | /* Set up the display plane register */ |
6365 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); | |
b24e7179 | 6366 | POSTING_READ(DSPCNTR(plane)); |
79e53945 | 6367 | |
94352cf9 | 6368 | ret = intel_pipe_set_base(crtc, x, y, fb); |
7662c8bd | 6369 | |
1857e1da | 6370 | return ret; |
79e53945 JB |
6371 | } |
6372 | ||
eb14cb74 VS |
6373 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
6374 | struct intel_link_m_n *m_n) | |
6375 | { | |
6376 | struct drm_device *dev = crtc->base.dev; | |
6377 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6378 | enum pipe pipe = crtc->pipe; | |
6379 | ||
6380 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
6381 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
6382 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
6383 | & ~TU_SIZE_MASK; | |
6384 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
6385 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
6386 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
6387 | } | |
6388 | ||
6389 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
6390 | enum transcoder transcoder, | |
6391 | struct intel_link_m_n *m_n) | |
72419203 DV |
6392 | { |
6393 | struct drm_device *dev = crtc->base.dev; | |
6394 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 6395 | enum pipe pipe = crtc->pipe; |
72419203 | 6396 | |
eb14cb74 VS |
6397 | if (INTEL_INFO(dev)->gen >= 5) { |
6398 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
6399 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
6400 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
6401 | & ~TU_SIZE_MASK; | |
6402 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
6403 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
6404 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
6405 | } else { | |
6406 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
6407 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
6408 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
6409 | & ~TU_SIZE_MASK; | |
6410 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
6411 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
6412 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
6413 | } | |
6414 | } | |
6415 | ||
6416 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
6417 | struct intel_crtc_config *pipe_config) | |
6418 | { | |
6419 | if (crtc->config.has_pch_encoder) | |
6420 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); | |
6421 | else | |
6422 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
6423 | &pipe_config->dp_m_n); | |
6424 | } | |
72419203 | 6425 | |
eb14cb74 VS |
6426 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
6427 | struct intel_crtc_config *pipe_config) | |
6428 | { | |
6429 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
6430 | &pipe_config->fdi_m_n); | |
72419203 DV |
6431 | } |
6432 | ||
2fa2fe9a DV |
6433 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
6434 | struct intel_crtc_config *pipe_config) | |
6435 | { | |
6436 | struct drm_device *dev = crtc->base.dev; | |
6437 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6438 | uint32_t tmp; | |
6439 | ||
6440 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
6441 | ||
6442 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 6443 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
6444 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
6445 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
6446 | |
6447 | /* We currently do not free assignements of panel fitters on | |
6448 | * ivb/hsw (since we don't use the higher upscaling modes which | |
6449 | * differentiates them) so just WARN about this case for now. */ | |
6450 | if (IS_GEN7(dev)) { | |
6451 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
6452 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
6453 | } | |
2fa2fe9a | 6454 | } |
79e53945 JB |
6455 | } |
6456 | ||
0e8ffe1b DV |
6457 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
6458 | struct intel_crtc_config *pipe_config) | |
6459 | { | |
6460 | struct drm_device *dev = crtc->base.dev; | |
6461 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6462 | uint32_t tmp; | |
6463 | ||
e143a21c | 6464 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 6465 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 6466 | |
0e8ffe1b DV |
6467 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
6468 | if (!(tmp & PIPECONF_ENABLE)) | |
6469 | return false; | |
6470 | ||
42571aef VS |
6471 | switch (tmp & PIPECONF_BPC_MASK) { |
6472 | case PIPECONF_6BPC: | |
6473 | pipe_config->pipe_bpp = 18; | |
6474 | break; | |
6475 | case PIPECONF_8BPC: | |
6476 | pipe_config->pipe_bpp = 24; | |
6477 | break; | |
6478 | case PIPECONF_10BPC: | |
6479 | pipe_config->pipe_bpp = 30; | |
6480 | break; | |
6481 | case PIPECONF_12BPC: | |
6482 | pipe_config->pipe_bpp = 36; | |
6483 | break; | |
6484 | default: | |
6485 | break; | |
6486 | } | |
6487 | ||
ab9412ba | 6488 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
6489 | struct intel_shared_dpll *pll; |
6490 | ||
88adfff1 DV |
6491 | pipe_config->has_pch_encoder = true; |
6492 | ||
627eb5a3 DV |
6493 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
6494 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
6495 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
6496 | |
6497 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 6498 | |
c0d43d62 | 6499 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
6500 | pipe_config->shared_dpll = |
6501 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
6502 | } else { |
6503 | tmp = I915_READ(PCH_DPLL_SEL); | |
6504 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
6505 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
6506 | else | |
6507 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
6508 | } | |
66e985c0 DV |
6509 | |
6510 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
6511 | ||
6512 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
6513 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
6514 | |
6515 | tmp = pipe_config->dpll_hw_state.dpll; | |
6516 | pipe_config->pixel_multiplier = | |
6517 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
6518 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
6519 | |
6520 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
6521 | } else { |
6522 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
6523 | } |
6524 | ||
1bd1bd80 DV |
6525 | intel_get_pipe_timings(crtc, pipe_config); |
6526 | ||
2fa2fe9a DV |
6527 | ironlake_get_pfit_config(crtc, pipe_config); |
6528 | ||
0e8ffe1b DV |
6529 | return true; |
6530 | } | |
6531 | ||
be256dc7 PZ |
6532 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
6533 | { | |
6534 | struct drm_device *dev = dev_priv->dev; | |
6535 | struct intel_ddi_plls *plls = &dev_priv->ddi_plls; | |
6536 | struct intel_crtc *crtc; | |
6537 | unsigned long irqflags; | |
bd633a7c | 6538 | uint32_t val; |
be256dc7 PZ |
6539 | |
6540 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) | |
798183c5 | 6541 | WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
6542 | pipe_name(crtc->pipe)); |
6543 | ||
6544 | WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); | |
6545 | WARN(plls->spll_refcount, "SPLL enabled\n"); | |
6546 | WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n"); | |
6547 | WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n"); | |
6548 | WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); | |
6549 | WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
6550 | "CPU PWM1 enabled\n"); | |
6551 | WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, | |
6552 | "CPU PWM2 enabled\n"); | |
6553 | WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, | |
6554 | "PCH PWM1 enabled\n"); | |
6555 | WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, | |
6556 | "Utility pin enabled\n"); | |
6557 | WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); | |
6558 | ||
6559 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
6560 | val = I915_READ(DEIMR); | |
6806e63f | 6561 | WARN((val | DE_PCH_EVENT_IVB) != 0xffffffff, |
be256dc7 PZ |
6562 | "Unexpected DEIMR bits enabled: 0x%x\n", val); |
6563 | val = I915_READ(SDEIMR); | |
bd633a7c | 6564 | WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff, |
be256dc7 PZ |
6565 | "Unexpected SDEIMR bits enabled: 0x%x\n", val); |
6566 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
6567 | } | |
6568 | ||
6569 | /* | |
6570 | * This function implements pieces of two sequences from BSpec: | |
6571 | * - Sequence for display software to disable LCPLL | |
6572 | * - Sequence for display software to allow package C8+ | |
6573 | * The steps implemented here are just the steps that actually touch the LCPLL | |
6574 | * register. Callers should take care of disabling all the display engine | |
6575 | * functions, doing the mode unset, fixing interrupts, etc. | |
6576 | */ | |
6ff58d53 PZ |
6577 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
6578 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
6579 | { |
6580 | uint32_t val; | |
6581 | ||
6582 | assert_can_disable_lcpll(dev_priv); | |
6583 | ||
6584 | val = I915_READ(LCPLL_CTL); | |
6585 | ||
6586 | if (switch_to_fclk) { | |
6587 | val |= LCPLL_CD_SOURCE_FCLK; | |
6588 | I915_WRITE(LCPLL_CTL, val); | |
6589 | ||
6590 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
6591 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
6592 | DRM_ERROR("Switching to FCLK failed\n"); | |
6593 | ||
6594 | val = I915_READ(LCPLL_CTL); | |
6595 | } | |
6596 | ||
6597 | val |= LCPLL_PLL_DISABLE; | |
6598 | I915_WRITE(LCPLL_CTL, val); | |
6599 | POSTING_READ(LCPLL_CTL); | |
6600 | ||
6601 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
6602 | DRM_ERROR("LCPLL still locked\n"); | |
6603 | ||
6604 | val = I915_READ(D_COMP); | |
6605 | val |= D_COMP_COMP_DISABLE; | |
515b2392 PZ |
6606 | mutex_lock(&dev_priv->rps.hw_lock); |
6607 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val)) | |
6608 | DRM_ERROR("Failed to disable D_COMP\n"); | |
6609 | mutex_unlock(&dev_priv->rps.hw_lock); | |
be256dc7 PZ |
6610 | POSTING_READ(D_COMP); |
6611 | ndelay(100); | |
6612 | ||
6613 | if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1)) | |
6614 | DRM_ERROR("D_COMP RCOMP still in progress\n"); | |
6615 | ||
6616 | if (allow_power_down) { | |
6617 | val = I915_READ(LCPLL_CTL); | |
6618 | val |= LCPLL_POWER_DOWN_ALLOW; | |
6619 | I915_WRITE(LCPLL_CTL, val); | |
6620 | POSTING_READ(LCPLL_CTL); | |
6621 | } | |
6622 | } | |
6623 | ||
6624 | /* | |
6625 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
6626 | * source. | |
6627 | */ | |
6ff58d53 | 6628 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
6629 | { |
6630 | uint32_t val; | |
6631 | ||
6632 | val = I915_READ(LCPLL_CTL); | |
6633 | ||
6634 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
6635 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
6636 | return; | |
6637 | ||
215733fa PZ |
6638 | /* Make sure we're not on PC8 state before disabling PC8, otherwise |
6639 | * we'll hang the machine! */ | |
0d9d349d | 6640 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 6641 | |
be256dc7 PZ |
6642 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
6643 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
6644 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 6645 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
6646 | } |
6647 | ||
6648 | val = I915_READ(D_COMP); | |
6649 | val |= D_COMP_COMP_FORCE; | |
6650 | val &= ~D_COMP_COMP_DISABLE; | |
515b2392 PZ |
6651 | mutex_lock(&dev_priv->rps.hw_lock); |
6652 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val)) | |
6653 | DRM_ERROR("Failed to enable D_COMP\n"); | |
6654 | mutex_unlock(&dev_priv->rps.hw_lock); | |
35d8f2eb | 6655 | POSTING_READ(D_COMP); |
be256dc7 PZ |
6656 | |
6657 | val = I915_READ(LCPLL_CTL); | |
6658 | val &= ~LCPLL_PLL_DISABLE; | |
6659 | I915_WRITE(LCPLL_CTL, val); | |
6660 | ||
6661 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
6662 | DRM_ERROR("LCPLL not locked yet\n"); | |
6663 | ||
6664 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
6665 | val = I915_READ(LCPLL_CTL); | |
6666 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
6667 | I915_WRITE(LCPLL_CTL, val); | |
6668 | ||
6669 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
6670 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
6671 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
6672 | } | |
215733fa | 6673 | |
0d9d349d | 6674 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
be256dc7 PZ |
6675 | } |
6676 | ||
c67a470b PZ |
6677 | void hsw_enable_pc8_work(struct work_struct *__work) |
6678 | { | |
6679 | struct drm_i915_private *dev_priv = | |
6680 | container_of(to_delayed_work(__work), struct drm_i915_private, | |
6681 | pc8.enable_work); | |
6682 | struct drm_device *dev = dev_priv->dev; | |
6683 | uint32_t val; | |
6684 | ||
7125ecb8 PZ |
6685 | WARN_ON(!HAS_PC8(dev)); |
6686 | ||
c67a470b PZ |
6687 | if (dev_priv->pc8.enabled) |
6688 | return; | |
6689 | ||
6690 | DRM_DEBUG_KMS("Enabling package C8+\n"); | |
6691 | ||
6692 | dev_priv->pc8.enabled = true; | |
6693 | ||
6694 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
6695 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
6696 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
6697 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
6698 | } | |
6699 | ||
6700 | lpt_disable_clkout_dp(dev); | |
6701 | hsw_pc8_disable_interrupts(dev); | |
6702 | hsw_disable_lcpll(dev_priv, true, true); | |
8771a7f8 PZ |
6703 | |
6704 | intel_runtime_pm_put(dev_priv); | |
c67a470b PZ |
6705 | } |
6706 | ||
6707 | static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv) | |
6708 | { | |
6709 | WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock)); | |
6710 | WARN(dev_priv->pc8.disable_count < 1, | |
6711 | "pc8.disable_count: %d\n", dev_priv->pc8.disable_count); | |
6712 | ||
6713 | dev_priv->pc8.disable_count--; | |
6714 | if (dev_priv->pc8.disable_count != 0) | |
6715 | return; | |
6716 | ||
6717 | schedule_delayed_work(&dev_priv->pc8.enable_work, | |
d330a953 | 6718 | msecs_to_jiffies(i915.pc8_timeout)); |
c67a470b PZ |
6719 | } |
6720 | ||
6721 | static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv) | |
6722 | { | |
6723 | struct drm_device *dev = dev_priv->dev; | |
6724 | uint32_t val; | |
6725 | ||
6726 | WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock)); | |
6727 | WARN(dev_priv->pc8.disable_count < 0, | |
6728 | "pc8.disable_count: %d\n", dev_priv->pc8.disable_count); | |
6729 | ||
6730 | dev_priv->pc8.disable_count++; | |
6731 | if (dev_priv->pc8.disable_count != 1) | |
6732 | return; | |
6733 | ||
7125ecb8 PZ |
6734 | WARN_ON(!HAS_PC8(dev)); |
6735 | ||
c67a470b PZ |
6736 | cancel_delayed_work_sync(&dev_priv->pc8.enable_work); |
6737 | if (!dev_priv->pc8.enabled) | |
6738 | return; | |
6739 | ||
6740 | DRM_DEBUG_KMS("Disabling package C8+\n"); | |
6741 | ||
8771a7f8 PZ |
6742 | intel_runtime_pm_get(dev_priv); |
6743 | ||
c67a470b PZ |
6744 | hsw_restore_lcpll(dev_priv); |
6745 | hsw_pc8_restore_interrupts(dev); | |
6746 | lpt_init_pch_refclk(dev); | |
6747 | ||
6748 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
6749 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
6750 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
6751 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
6752 | } | |
6753 | ||
6754 | intel_prepare_ddi(dev); | |
6755 | i915_gem_init_swizzling(dev); | |
6756 | mutex_lock(&dev_priv->rps.hw_lock); | |
6757 | gen6_update_ring_freq(dev); | |
6758 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6759 | dev_priv->pc8.enabled = false; | |
6760 | } | |
6761 | ||
6762 | void hsw_enable_package_c8(struct drm_i915_private *dev_priv) | |
6763 | { | |
7c6c2652 CW |
6764 | if (!HAS_PC8(dev_priv->dev)) |
6765 | return; | |
6766 | ||
c67a470b PZ |
6767 | mutex_lock(&dev_priv->pc8.lock); |
6768 | __hsw_enable_package_c8(dev_priv); | |
6769 | mutex_unlock(&dev_priv->pc8.lock); | |
6770 | } | |
6771 | ||
6772 | void hsw_disable_package_c8(struct drm_i915_private *dev_priv) | |
6773 | { | |
7c6c2652 CW |
6774 | if (!HAS_PC8(dev_priv->dev)) |
6775 | return; | |
6776 | ||
c67a470b PZ |
6777 | mutex_lock(&dev_priv->pc8.lock); |
6778 | __hsw_disable_package_c8(dev_priv); | |
6779 | mutex_unlock(&dev_priv->pc8.lock); | |
6780 | } | |
6781 | ||
6782 | static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv) | |
6783 | { | |
6784 | struct drm_device *dev = dev_priv->dev; | |
6785 | struct intel_crtc *crtc; | |
6786 | uint32_t val; | |
6787 | ||
6788 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) | |
6789 | if (crtc->base.enabled) | |
6790 | return false; | |
6791 | ||
6792 | /* This case is still possible since we have the i915.disable_power_well | |
6793 | * parameter and also the KVMr or something else might be requesting the | |
6794 | * power well. */ | |
6795 | val = I915_READ(HSW_PWR_WELL_DRIVER); | |
6796 | if (val != 0) { | |
6797 | DRM_DEBUG_KMS("Not enabling PC8: power well on\n"); | |
6798 | return false; | |
6799 | } | |
6800 | ||
6801 | return true; | |
6802 | } | |
6803 | ||
6804 | /* Since we're called from modeset_global_resources there's no way to | |
6805 | * symmetrically increase and decrease the refcount, so we use | |
6806 | * dev_priv->pc8.requirements_met to track whether we already have the refcount | |
6807 | * or not. | |
6808 | */ | |
6809 | static void hsw_update_package_c8(struct drm_device *dev) | |
6810 | { | |
6811 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6812 | bool allow; | |
6813 | ||
7c6c2652 CW |
6814 | if (!HAS_PC8(dev_priv->dev)) |
6815 | return; | |
6816 | ||
d330a953 | 6817 | if (!i915.enable_pc8) |
c67a470b PZ |
6818 | return; |
6819 | ||
6820 | mutex_lock(&dev_priv->pc8.lock); | |
6821 | ||
6822 | allow = hsw_can_enable_package_c8(dev_priv); | |
6823 | ||
6824 | if (allow == dev_priv->pc8.requirements_met) | |
6825 | goto done; | |
6826 | ||
6827 | dev_priv->pc8.requirements_met = allow; | |
6828 | ||
6829 | if (allow) | |
6830 | __hsw_enable_package_c8(dev_priv); | |
6831 | else | |
6832 | __hsw_disable_package_c8(dev_priv); | |
6833 | ||
6834 | done: | |
6835 | mutex_unlock(&dev_priv->pc8.lock); | |
6836 | } | |
6837 | ||
6838 | static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv) | |
6839 | { | |
7c6c2652 CW |
6840 | if (!HAS_PC8(dev_priv->dev)) |
6841 | return; | |
6842 | ||
3458122e | 6843 | mutex_lock(&dev_priv->pc8.lock); |
c67a470b PZ |
6844 | if (!dev_priv->pc8.gpu_idle) { |
6845 | dev_priv->pc8.gpu_idle = true; | |
3458122e | 6846 | __hsw_enable_package_c8(dev_priv); |
c67a470b | 6847 | } |
3458122e | 6848 | mutex_unlock(&dev_priv->pc8.lock); |
c67a470b PZ |
6849 | } |
6850 | ||
6851 | static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv) | |
6852 | { | |
7c6c2652 CW |
6853 | if (!HAS_PC8(dev_priv->dev)) |
6854 | return; | |
6855 | ||
3458122e | 6856 | mutex_lock(&dev_priv->pc8.lock); |
c67a470b PZ |
6857 | if (dev_priv->pc8.gpu_idle) { |
6858 | dev_priv->pc8.gpu_idle = false; | |
3458122e | 6859 | __hsw_disable_package_c8(dev_priv); |
c67a470b | 6860 | } |
3458122e | 6861 | mutex_unlock(&dev_priv->pc8.lock); |
be256dc7 PZ |
6862 | } |
6863 | ||
6efdf354 ID |
6864 | #define for_each_power_domain(domain, mask) \ |
6865 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
6866 | if ((1 << (domain)) & (mask)) | |
6867 | ||
6868 | static unsigned long get_pipe_power_domains(struct drm_device *dev, | |
6869 | enum pipe pipe, bool pfit_enabled) | |
6870 | { | |
6871 | unsigned long mask; | |
6872 | enum transcoder transcoder; | |
6873 | ||
6874 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); | |
6875 | ||
6876 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); | |
6877 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
6878 | if (pfit_enabled) | |
6879 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); | |
6880 | ||
6881 | return mask; | |
6882 | } | |
6883 | ||
baa70707 ID |
6884 | void intel_display_set_init_power(struct drm_device *dev, bool enable) |
6885 | { | |
6886 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6887 | ||
6888 | if (dev_priv->power_domains.init_power_on == enable) | |
6889 | return; | |
6890 | ||
6891 | if (enable) | |
6892 | intel_display_power_get(dev, POWER_DOMAIN_INIT); | |
6893 | else | |
6894 | intel_display_power_put(dev, POWER_DOMAIN_INIT); | |
6895 | ||
6896 | dev_priv->power_domains.init_power_on = enable; | |
6897 | } | |
6898 | ||
4f074129 | 6899 | static void modeset_update_power_wells(struct drm_device *dev) |
d6dd9eb1 | 6900 | { |
6efdf354 | 6901 | unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; |
d6dd9eb1 | 6902 | struct intel_crtc *crtc; |
d6dd9eb1 | 6903 | |
6efdf354 ID |
6904 | /* |
6905 | * First get all needed power domains, then put all unneeded, to avoid | |
6906 | * any unnecessary toggling of the power wells. | |
6907 | */ | |
d6dd9eb1 | 6908 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
6efdf354 ID |
6909 | enum intel_display_power_domain domain; |
6910 | ||
e7a639c4 DV |
6911 | if (!crtc->base.enabled) |
6912 | continue; | |
d6dd9eb1 | 6913 | |
6efdf354 ID |
6914 | pipe_domains[crtc->pipe] = get_pipe_power_domains(dev, |
6915 | crtc->pipe, | |
6916 | crtc->config.pch_pfit.enabled); | |
6917 | ||
6918 | for_each_power_domain(domain, pipe_domains[crtc->pipe]) | |
6919 | intel_display_power_get(dev, domain); | |
d6dd9eb1 DV |
6920 | } |
6921 | ||
6efdf354 ID |
6922 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
6923 | enum intel_display_power_domain domain; | |
6924 | ||
6925 | for_each_power_domain(domain, crtc->enabled_power_domains) | |
6926 | intel_display_power_put(dev, domain); | |
6927 | ||
6928 | crtc->enabled_power_domains = pipe_domains[crtc->pipe]; | |
6929 | } | |
baa70707 ID |
6930 | |
6931 | intel_display_set_init_power(dev, false); | |
4f074129 | 6932 | } |
c67a470b | 6933 | |
4f074129 ID |
6934 | static void haswell_modeset_global_resources(struct drm_device *dev) |
6935 | { | |
6936 | modeset_update_power_wells(dev); | |
c67a470b | 6937 | hsw_update_package_c8(dev); |
d6dd9eb1 DV |
6938 | } |
6939 | ||
09b4ddf9 | 6940 | static int haswell_crtc_mode_set(struct drm_crtc *crtc, |
09b4ddf9 PZ |
6941 | int x, int y, |
6942 | struct drm_framebuffer *fb) | |
6943 | { | |
6944 | struct drm_device *dev = crtc->dev; | |
6945 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6946 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
09b4ddf9 | 6947 | int plane = intel_crtc->plane; |
09b4ddf9 | 6948 | int ret; |
09b4ddf9 | 6949 | |
566b734a | 6950 | if (!intel_ddi_pll_select(intel_crtc)) |
6441ab5f | 6951 | return -EINVAL; |
566b734a | 6952 | intel_ddi_pll_enable(intel_crtc); |
6441ab5f | 6953 | |
03afc4a2 DV |
6954 | if (intel_crtc->config.has_dp_encoder) |
6955 | intel_dp_set_m_n(intel_crtc); | |
09b4ddf9 PZ |
6956 | |
6957 | intel_crtc->lowfreq_avail = false; | |
09b4ddf9 | 6958 | |
8a654f3b | 6959 | intel_set_pipe_timings(intel_crtc); |
09b4ddf9 | 6960 | |
ca3a0ff8 | 6961 | if (intel_crtc->config.has_pch_encoder) { |
ca3a0ff8 DV |
6962 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6963 | &intel_crtc->config.fdi_m_n); | |
6964 | } | |
09b4ddf9 | 6965 | |
6ff93609 | 6966 | haswell_set_pipeconf(crtc); |
09b4ddf9 | 6967 | |
50f3b016 | 6968 | intel_set_pipe_csc(crtc); |
86d3efce | 6969 | |
09b4ddf9 | 6970 | /* Set up the display plane register */ |
86d3efce | 6971 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE); |
09b4ddf9 PZ |
6972 | POSTING_READ(DSPCNTR(plane)); |
6973 | ||
6974 | ret = intel_pipe_set_base(crtc, x, y, fb); | |
6975 | ||
1f803ee5 | 6976 | return ret; |
79e53945 JB |
6977 | } |
6978 | ||
0e8ffe1b DV |
6979 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
6980 | struct intel_crtc_config *pipe_config) | |
6981 | { | |
6982 | struct drm_device *dev = crtc->base.dev; | |
6983 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 6984 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
6985 | uint32_t tmp; |
6986 | ||
e143a21c | 6987 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
6988 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
6989 | ||
eccb140b DV |
6990 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
6991 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
6992 | enum pipe trans_edp_pipe; | |
6993 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
6994 | default: | |
6995 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
6996 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
6997 | case TRANS_DDI_EDP_INPUT_A_ON: | |
6998 | trans_edp_pipe = PIPE_A; | |
6999 | break; | |
7000 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
7001 | trans_edp_pipe = PIPE_B; | |
7002 | break; | |
7003 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
7004 | trans_edp_pipe = PIPE_C; | |
7005 | break; | |
7006 | } | |
7007 | ||
7008 | if (trans_edp_pipe == crtc->pipe) | |
7009 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
7010 | } | |
7011 | ||
b97186f0 | 7012 | if (!intel_display_power_enabled(dev, |
eccb140b | 7013 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
7014 | return false; |
7015 | ||
eccb140b | 7016 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
7017 | if (!(tmp & PIPECONF_ENABLE)) |
7018 | return false; | |
7019 | ||
88adfff1 | 7020 | /* |
f196e6be | 7021 | * Haswell has only FDI/PCH transcoder A. It is which is connected to |
88adfff1 DV |
7022 | * DDI E. So just check whether this pipe is wired to DDI E and whether |
7023 | * the PCH transcoder is on. | |
7024 | */ | |
eccb140b | 7025 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); |
88adfff1 | 7026 | if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) && |
ab9412ba | 7027 | I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { |
88adfff1 DV |
7028 | pipe_config->has_pch_encoder = true; |
7029 | ||
627eb5a3 DV |
7030 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); |
7031 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
7032 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
7033 | |
7034 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
627eb5a3 DV |
7035 | } |
7036 | ||
1bd1bd80 DV |
7037 | intel_get_pipe_timings(crtc, pipe_config); |
7038 | ||
2fa2fe9a DV |
7039 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
7040 | if (intel_display_power_enabled(dev, pfit_domain)) | |
7041 | ironlake_get_pfit_config(crtc, pipe_config); | |
88adfff1 | 7042 | |
e59150dc JB |
7043 | if (IS_HASWELL(dev)) |
7044 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
7045 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 7046 | |
6c49f241 DV |
7047 | pipe_config->pixel_multiplier = 1; |
7048 | ||
0e8ffe1b DV |
7049 | return true; |
7050 | } | |
7051 | ||
f564048e | 7052 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
f564048e | 7053 | int x, int y, |
94352cf9 | 7054 | struct drm_framebuffer *fb) |
f564048e EA |
7055 | { |
7056 | struct drm_device *dev = crtc->dev; | |
7057 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9256aa19 | 7058 | struct intel_encoder *encoder; |
0b701d27 | 7059 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
b8cecdf5 | 7060 | struct drm_display_mode *mode = &intel_crtc->config.requested_mode; |
0b701d27 | 7061 | int pipe = intel_crtc->pipe; |
f564048e EA |
7062 | int ret; |
7063 | ||
0b701d27 | 7064 | drm_vblank_pre_modeset(dev, pipe); |
7662c8bd | 7065 | |
b8cecdf5 DV |
7066 | ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb); |
7067 | ||
79e53945 | 7068 | drm_vblank_post_modeset(dev, pipe); |
5c3b82e2 | 7069 | |
9256aa19 DV |
7070 | if (ret != 0) |
7071 | return ret; | |
7072 | ||
7073 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
7074 | DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n", | |
7075 | encoder->base.base.id, | |
7076 | drm_get_encoder_name(&encoder->base), | |
7077 | mode->base.id, mode->name); | |
36f2d1f1 | 7078 | encoder->mode_set(encoder); |
9256aa19 DV |
7079 | } |
7080 | ||
7081 | return 0; | |
79e53945 JB |
7082 | } |
7083 | ||
1a91510d JN |
7084 | static struct { |
7085 | int clock; | |
7086 | u32 config; | |
7087 | } hdmi_audio_clock[] = { | |
7088 | { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, | |
7089 | { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ | |
7090 | { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, | |
7091 | { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, | |
7092 | { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, | |
7093 | { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, | |
7094 | { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, | |
7095 | { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, | |
7096 | { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, | |
7097 | { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, | |
7098 | }; | |
7099 | ||
7100 | /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ | |
7101 | static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode) | |
7102 | { | |
7103 | int i; | |
7104 | ||
7105 | for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { | |
7106 | if (mode->clock == hdmi_audio_clock[i].clock) | |
7107 | break; | |
7108 | } | |
7109 | ||
7110 | if (i == ARRAY_SIZE(hdmi_audio_clock)) { | |
7111 | DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock); | |
7112 | i = 1; | |
7113 | } | |
7114 | ||
7115 | DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n", | |
7116 | hdmi_audio_clock[i].clock, | |
7117 | hdmi_audio_clock[i].config); | |
7118 | ||
7119 | return hdmi_audio_clock[i].config; | |
7120 | } | |
7121 | ||
3a9627f4 WF |
7122 | static bool intel_eld_uptodate(struct drm_connector *connector, |
7123 | int reg_eldv, uint32_t bits_eldv, | |
7124 | int reg_elda, uint32_t bits_elda, | |
7125 | int reg_edid) | |
7126 | { | |
7127 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7128 | uint8_t *eld = connector->eld; | |
7129 | uint32_t i; | |
7130 | ||
7131 | i = I915_READ(reg_eldv); | |
7132 | i &= bits_eldv; | |
7133 | ||
7134 | if (!eld[0]) | |
7135 | return !i; | |
7136 | ||
7137 | if (!i) | |
7138 | return false; | |
7139 | ||
7140 | i = I915_READ(reg_elda); | |
7141 | i &= ~bits_elda; | |
7142 | I915_WRITE(reg_elda, i); | |
7143 | ||
7144 | for (i = 0; i < eld[2]; i++) | |
7145 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) | |
7146 | return false; | |
7147 | ||
7148 | return true; | |
7149 | } | |
7150 | ||
e0dac65e | 7151 | static void g4x_write_eld(struct drm_connector *connector, |
34427052 JN |
7152 | struct drm_crtc *crtc, |
7153 | struct drm_display_mode *mode) | |
e0dac65e WF |
7154 | { |
7155 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7156 | uint8_t *eld = connector->eld; | |
7157 | uint32_t eldv; | |
7158 | uint32_t len; | |
7159 | uint32_t i; | |
7160 | ||
7161 | i = I915_READ(G4X_AUD_VID_DID); | |
7162 | ||
7163 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) | |
7164 | eldv = G4X_ELDV_DEVCL_DEVBLC; | |
7165 | else | |
7166 | eldv = G4X_ELDV_DEVCTG; | |
7167 | ||
3a9627f4 WF |
7168 | if (intel_eld_uptodate(connector, |
7169 | G4X_AUD_CNTL_ST, eldv, | |
7170 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, | |
7171 | G4X_HDMIW_HDMIEDID)) | |
7172 | return; | |
7173 | ||
e0dac65e WF |
7174 | i = I915_READ(G4X_AUD_CNTL_ST); |
7175 | i &= ~(eldv | G4X_ELD_ADDR); | |
7176 | len = (i >> 9) & 0x1f; /* ELD buffer size */ | |
7177 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
7178 | ||
7179 | if (!eld[0]) | |
7180 | return; | |
7181 | ||
7182 | len = min_t(uint8_t, eld[2], len); | |
7183 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7184 | for (i = 0; i < len; i++) | |
7185 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); | |
7186 | ||
7187 | i = I915_READ(G4X_AUD_CNTL_ST); | |
7188 | i |= eldv; | |
7189 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
7190 | } | |
7191 | ||
83358c85 | 7192 | static void haswell_write_eld(struct drm_connector *connector, |
34427052 JN |
7193 | struct drm_crtc *crtc, |
7194 | struct drm_display_mode *mode) | |
83358c85 WX |
7195 | { |
7196 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7197 | uint8_t *eld = connector->eld; | |
7198 | struct drm_device *dev = crtc->dev; | |
7b9f35a6 | 7199 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
83358c85 WX |
7200 | uint32_t eldv; |
7201 | uint32_t i; | |
7202 | int len; | |
7203 | int pipe = to_intel_crtc(crtc)->pipe; | |
7204 | int tmp; | |
7205 | ||
7206 | int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe); | |
7207 | int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe); | |
7208 | int aud_config = HSW_AUD_CFG(pipe); | |
7209 | int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD; | |
7210 | ||
7211 | ||
7212 | DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n"); | |
7213 | ||
7214 | /* Audio output enable */ | |
7215 | DRM_DEBUG_DRIVER("HDMI audio: enable codec\n"); | |
7216 | tmp = I915_READ(aud_cntrl_st2); | |
7217 | tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4)); | |
7218 | I915_WRITE(aud_cntrl_st2, tmp); | |
7219 | ||
7220 | /* Wait for 1 vertical blank */ | |
7221 | intel_wait_for_vblank(dev, pipe); | |
7222 | ||
7223 | /* Set ELD valid state */ | |
7224 | tmp = I915_READ(aud_cntrl_st2); | |
7e7cb34f | 7225 | DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp); |
83358c85 WX |
7226 | tmp |= (AUDIO_ELD_VALID_A << (pipe * 4)); |
7227 | I915_WRITE(aud_cntrl_st2, tmp); | |
7228 | tmp = I915_READ(aud_cntrl_st2); | |
7e7cb34f | 7229 | DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp); |
83358c85 WX |
7230 | |
7231 | /* Enable HDMI mode */ | |
7232 | tmp = I915_READ(aud_config); | |
7e7cb34f | 7233 | DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp); |
83358c85 WX |
7234 | /* clear N_programing_enable and N_value_index */ |
7235 | tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE); | |
7236 | I915_WRITE(aud_config, tmp); | |
7237 | ||
7238 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); | |
7239 | ||
7240 | eldv = AUDIO_ELD_VALID_A << (pipe * 4); | |
7b9f35a6 | 7241 | intel_crtc->eld_vld = true; |
83358c85 WX |
7242 | |
7243 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { | |
7244 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
7245 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
7246 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ | |
1a91510d JN |
7247 | } else { |
7248 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); | |
7249 | } | |
83358c85 WX |
7250 | |
7251 | if (intel_eld_uptodate(connector, | |
7252 | aud_cntrl_st2, eldv, | |
7253 | aud_cntl_st, IBX_ELD_ADDRESS, | |
7254 | hdmiw_hdmiedid)) | |
7255 | return; | |
7256 | ||
7257 | i = I915_READ(aud_cntrl_st2); | |
7258 | i &= ~eldv; | |
7259 | I915_WRITE(aud_cntrl_st2, i); | |
7260 | ||
7261 | if (!eld[0]) | |
7262 | return; | |
7263 | ||
7264 | i = I915_READ(aud_cntl_st); | |
7265 | i &= ~IBX_ELD_ADDRESS; | |
7266 | I915_WRITE(aud_cntl_st, i); | |
7267 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ | |
7268 | DRM_DEBUG_DRIVER("port num:%d\n", i); | |
7269 | ||
7270 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
7271 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7272 | for (i = 0; i < len; i++) | |
7273 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
7274 | ||
7275 | i = I915_READ(aud_cntrl_st2); | |
7276 | i |= eldv; | |
7277 | I915_WRITE(aud_cntrl_st2, i); | |
7278 | ||
7279 | } | |
7280 | ||
e0dac65e | 7281 | static void ironlake_write_eld(struct drm_connector *connector, |
34427052 JN |
7282 | struct drm_crtc *crtc, |
7283 | struct drm_display_mode *mode) | |
e0dac65e WF |
7284 | { |
7285 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7286 | uint8_t *eld = connector->eld; | |
7287 | uint32_t eldv; | |
7288 | uint32_t i; | |
7289 | int len; | |
7290 | int hdmiw_hdmiedid; | |
b6daa025 | 7291 | int aud_config; |
e0dac65e WF |
7292 | int aud_cntl_st; |
7293 | int aud_cntrl_st2; | |
9b138a83 | 7294 | int pipe = to_intel_crtc(crtc)->pipe; |
e0dac65e | 7295 | |
b3f33cbf | 7296 | if (HAS_PCH_IBX(connector->dev)) { |
9b138a83 WX |
7297 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); |
7298 | aud_config = IBX_AUD_CFG(pipe); | |
7299 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); | |
1202b4c6 | 7300 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
9ca2fe73 ML |
7301 | } else if (IS_VALLEYVIEW(connector->dev)) { |
7302 | hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); | |
7303 | aud_config = VLV_AUD_CFG(pipe); | |
7304 | aud_cntl_st = VLV_AUD_CNTL_ST(pipe); | |
7305 | aud_cntrl_st2 = VLV_AUD_CNTL_ST2; | |
e0dac65e | 7306 | } else { |
9b138a83 WX |
7307 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); |
7308 | aud_config = CPT_AUD_CFG(pipe); | |
7309 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); | |
1202b4c6 | 7310 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
e0dac65e WF |
7311 | } |
7312 | ||
9b138a83 | 7313 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
e0dac65e | 7314 | |
9ca2fe73 ML |
7315 | if (IS_VALLEYVIEW(connector->dev)) { |
7316 | struct intel_encoder *intel_encoder; | |
7317 | struct intel_digital_port *intel_dig_port; | |
7318 | ||
7319 | intel_encoder = intel_attached_encoder(connector); | |
7320 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
7321 | i = intel_dig_port->port; | |
7322 | } else { | |
7323 | i = I915_READ(aud_cntl_st); | |
7324 | i = (i >> 29) & DIP_PORT_SEL_MASK; | |
7325 | /* DIP_Port_Select, 0x1 = PortB */ | |
7326 | } | |
7327 | ||
e0dac65e WF |
7328 | if (!i) { |
7329 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); | |
7330 | /* operate blindly on all ports */ | |
1202b4c6 WF |
7331 | eldv = IBX_ELD_VALIDB; |
7332 | eldv |= IBX_ELD_VALIDB << 4; | |
7333 | eldv |= IBX_ELD_VALIDB << 8; | |
e0dac65e | 7334 | } else { |
2582a850 | 7335 | DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i)); |
1202b4c6 | 7336 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
e0dac65e WF |
7337 | } |
7338 | ||
3a9627f4 WF |
7339 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
7340 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
7341 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
b6daa025 | 7342 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
1a91510d JN |
7343 | } else { |
7344 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); | |
7345 | } | |
e0dac65e | 7346 | |
3a9627f4 WF |
7347 | if (intel_eld_uptodate(connector, |
7348 | aud_cntrl_st2, eldv, | |
7349 | aud_cntl_st, IBX_ELD_ADDRESS, | |
7350 | hdmiw_hdmiedid)) | |
7351 | return; | |
7352 | ||
e0dac65e WF |
7353 | i = I915_READ(aud_cntrl_st2); |
7354 | i &= ~eldv; | |
7355 | I915_WRITE(aud_cntrl_st2, i); | |
7356 | ||
7357 | if (!eld[0]) | |
7358 | return; | |
7359 | ||
e0dac65e | 7360 | i = I915_READ(aud_cntl_st); |
1202b4c6 | 7361 | i &= ~IBX_ELD_ADDRESS; |
e0dac65e WF |
7362 | I915_WRITE(aud_cntl_st, i); |
7363 | ||
7364 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
7365 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7366 | for (i = 0; i < len; i++) | |
7367 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
7368 | ||
7369 | i = I915_READ(aud_cntrl_st2); | |
7370 | i |= eldv; | |
7371 | I915_WRITE(aud_cntrl_st2, i); | |
7372 | } | |
7373 | ||
7374 | void intel_write_eld(struct drm_encoder *encoder, | |
7375 | struct drm_display_mode *mode) | |
7376 | { | |
7377 | struct drm_crtc *crtc = encoder->crtc; | |
7378 | struct drm_connector *connector; | |
7379 | struct drm_device *dev = encoder->dev; | |
7380 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7381 | ||
7382 | connector = drm_select_eld(encoder, mode); | |
7383 | if (!connector) | |
7384 | return; | |
7385 | ||
7386 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", | |
7387 | connector->base.id, | |
7388 | drm_get_connector_name(connector), | |
7389 | connector->encoder->base.id, | |
7390 | drm_get_encoder_name(connector->encoder)); | |
7391 | ||
7392 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; | |
7393 | ||
7394 | if (dev_priv->display.write_eld) | |
34427052 | 7395 | dev_priv->display.write_eld(connector, crtc, mode); |
e0dac65e WF |
7396 | } |
7397 | ||
560b85bb CW |
7398 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
7399 | { | |
7400 | struct drm_device *dev = crtc->dev; | |
7401 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7402 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7403 | bool visible = base != 0; | |
7404 | u32 cntl; | |
7405 | ||
7406 | if (intel_crtc->cursor_visible == visible) | |
7407 | return; | |
7408 | ||
9db4a9c7 | 7409 | cntl = I915_READ(_CURACNTR); |
560b85bb CW |
7410 | if (visible) { |
7411 | /* On these chipsets we can only modify the base whilst | |
7412 | * the cursor is disabled. | |
7413 | */ | |
9db4a9c7 | 7414 | I915_WRITE(_CURABASE, base); |
560b85bb CW |
7415 | |
7416 | cntl &= ~(CURSOR_FORMAT_MASK); | |
7417 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ | |
7418 | cntl |= CURSOR_ENABLE | | |
7419 | CURSOR_GAMMA_ENABLE | | |
7420 | CURSOR_FORMAT_ARGB; | |
7421 | } else | |
7422 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); | |
9db4a9c7 | 7423 | I915_WRITE(_CURACNTR, cntl); |
560b85bb CW |
7424 | |
7425 | intel_crtc->cursor_visible = visible; | |
7426 | } | |
7427 | ||
7428 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) | |
7429 | { | |
7430 | struct drm_device *dev = crtc->dev; | |
7431 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7432 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7433 | int pipe = intel_crtc->pipe; | |
7434 | bool visible = base != 0; | |
7435 | ||
7436 | if (intel_crtc->cursor_visible != visible) { | |
548f245b | 7437 | uint32_t cntl = I915_READ(CURCNTR(pipe)); |
560b85bb CW |
7438 | if (base) { |
7439 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); | |
7440 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
7441 | cntl |= pipe << 28; /* Connect to correct pipe */ | |
7442 | } else { | |
7443 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
7444 | cntl |= CURSOR_MODE_DISABLE; | |
7445 | } | |
9db4a9c7 | 7446 | I915_WRITE(CURCNTR(pipe), cntl); |
560b85bb CW |
7447 | |
7448 | intel_crtc->cursor_visible = visible; | |
7449 | } | |
7450 | /* and commit changes on next vblank */ | |
b2ea8ef5 | 7451 | POSTING_READ(CURCNTR(pipe)); |
9db4a9c7 | 7452 | I915_WRITE(CURBASE(pipe), base); |
b2ea8ef5 | 7453 | POSTING_READ(CURBASE(pipe)); |
560b85bb CW |
7454 | } |
7455 | ||
65a21cd6 JB |
7456 | static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) |
7457 | { | |
7458 | struct drm_device *dev = crtc->dev; | |
7459 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7460 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7461 | int pipe = intel_crtc->pipe; | |
7462 | bool visible = base != 0; | |
7463 | ||
7464 | if (intel_crtc->cursor_visible != visible) { | |
7465 | uint32_t cntl = I915_READ(CURCNTR_IVB(pipe)); | |
7466 | if (base) { | |
7467 | cntl &= ~CURSOR_MODE; | |
7468 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
7469 | } else { | |
7470 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
7471 | cntl |= CURSOR_MODE_DISABLE; | |
7472 | } | |
6bbfa1c5 | 7473 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
86d3efce | 7474 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
1f5d76db PZ |
7475 | cntl &= ~CURSOR_TRICKLE_FEED_DISABLE; |
7476 | } | |
65a21cd6 JB |
7477 | I915_WRITE(CURCNTR_IVB(pipe), cntl); |
7478 | ||
7479 | intel_crtc->cursor_visible = visible; | |
7480 | } | |
7481 | /* and commit changes on next vblank */ | |
b2ea8ef5 | 7482 | POSTING_READ(CURCNTR_IVB(pipe)); |
65a21cd6 | 7483 | I915_WRITE(CURBASE_IVB(pipe), base); |
b2ea8ef5 | 7484 | POSTING_READ(CURBASE_IVB(pipe)); |
65a21cd6 JB |
7485 | } |
7486 | ||
cda4b7d3 | 7487 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
7488 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
7489 | bool on) | |
cda4b7d3 CW |
7490 | { |
7491 | struct drm_device *dev = crtc->dev; | |
7492 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7493 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7494 | int pipe = intel_crtc->pipe; | |
7495 | int x = intel_crtc->cursor_x; | |
7496 | int y = intel_crtc->cursor_y; | |
d6e4db15 | 7497 | u32 base = 0, pos = 0; |
cda4b7d3 CW |
7498 | bool visible; |
7499 | ||
d6e4db15 | 7500 | if (on) |
cda4b7d3 | 7501 | base = intel_crtc->cursor_addr; |
cda4b7d3 | 7502 | |
d6e4db15 VS |
7503 | if (x >= intel_crtc->config.pipe_src_w) |
7504 | base = 0; | |
7505 | ||
7506 | if (y >= intel_crtc->config.pipe_src_h) | |
cda4b7d3 CW |
7507 | base = 0; |
7508 | ||
7509 | if (x < 0) { | |
efc9064e | 7510 | if (x + intel_crtc->cursor_width <= 0) |
cda4b7d3 CW |
7511 | base = 0; |
7512 | ||
7513 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
7514 | x = -x; | |
7515 | } | |
7516 | pos |= x << CURSOR_X_SHIFT; | |
7517 | ||
7518 | if (y < 0) { | |
efc9064e | 7519 | if (y + intel_crtc->cursor_height <= 0) |
cda4b7d3 CW |
7520 | base = 0; |
7521 | ||
7522 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
7523 | y = -y; | |
7524 | } | |
7525 | pos |= y << CURSOR_Y_SHIFT; | |
7526 | ||
7527 | visible = base != 0; | |
560b85bb | 7528 | if (!visible && !intel_crtc->cursor_visible) |
cda4b7d3 CW |
7529 | return; |
7530 | ||
b3dc685e | 7531 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
65a21cd6 JB |
7532 | I915_WRITE(CURPOS_IVB(pipe), pos); |
7533 | ivb_update_cursor(crtc, base); | |
7534 | } else { | |
7535 | I915_WRITE(CURPOS(pipe), pos); | |
7536 | if (IS_845G(dev) || IS_I865G(dev)) | |
7537 | i845_update_cursor(crtc, base); | |
7538 | else | |
7539 | i9xx_update_cursor(crtc, base); | |
7540 | } | |
cda4b7d3 CW |
7541 | } |
7542 | ||
79e53945 | 7543 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
05394f39 | 7544 | struct drm_file *file, |
79e53945 JB |
7545 | uint32_t handle, |
7546 | uint32_t width, uint32_t height) | |
7547 | { | |
7548 | struct drm_device *dev = crtc->dev; | |
7549 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7550 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 7551 | struct drm_i915_gem_object *obj; |
cda4b7d3 | 7552 | uint32_t addr; |
3f8bc370 | 7553 | int ret; |
79e53945 | 7554 | |
79e53945 JB |
7555 | /* if we want to turn off the cursor ignore width and height */ |
7556 | if (!handle) { | |
28c97730 | 7557 | DRM_DEBUG_KMS("cursor off\n"); |
3f8bc370 | 7558 | addr = 0; |
05394f39 | 7559 | obj = NULL; |
5004417d | 7560 | mutex_lock(&dev->struct_mutex); |
3f8bc370 | 7561 | goto finish; |
79e53945 JB |
7562 | } |
7563 | ||
7564 | /* Currently we only support 64x64 cursors */ | |
7565 | if (width != 64 || height != 64) { | |
7566 | DRM_ERROR("we currently only support 64x64 cursors\n"); | |
7567 | return -EINVAL; | |
7568 | } | |
7569 | ||
05394f39 | 7570 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 7571 | if (&obj->base == NULL) |
79e53945 JB |
7572 | return -ENOENT; |
7573 | ||
05394f39 | 7574 | if (obj->base.size < width * height * 4) { |
79e53945 | 7575 | DRM_ERROR("buffer is to small\n"); |
34b8686e DA |
7576 | ret = -ENOMEM; |
7577 | goto fail; | |
79e53945 JB |
7578 | } |
7579 | ||
71acb5eb | 7580 | /* we only need to pin inside GTT if cursor is non-phy */ |
7f9872e0 | 7581 | mutex_lock(&dev->struct_mutex); |
3d13ef2e | 7582 | if (!INTEL_INFO(dev)->cursor_needs_physical) { |
693db184 CW |
7583 | unsigned alignment; |
7584 | ||
d9e86c0e CW |
7585 | if (obj->tiling_mode) { |
7586 | DRM_ERROR("cursor cannot be tiled\n"); | |
7587 | ret = -EINVAL; | |
7588 | goto fail_locked; | |
7589 | } | |
7590 | ||
693db184 CW |
7591 | /* Note that the w/a also requires 2 PTE of padding following |
7592 | * the bo. We currently fill all unused PTE with the shadow | |
7593 | * page and so we should always have valid PTE following the | |
7594 | * cursor preventing the VT-d warning. | |
7595 | */ | |
7596 | alignment = 0; | |
7597 | if (need_vtd_wa(dev)) | |
7598 | alignment = 64*1024; | |
7599 | ||
7600 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL); | |
e7b526bb CW |
7601 | if (ret) { |
7602 | DRM_ERROR("failed to move cursor bo into the GTT\n"); | |
2da3b9b9 | 7603 | goto fail_locked; |
e7b526bb CW |
7604 | } |
7605 | ||
d9e86c0e CW |
7606 | ret = i915_gem_object_put_fence(obj); |
7607 | if (ret) { | |
2da3b9b9 | 7608 | DRM_ERROR("failed to release fence for cursor"); |
d9e86c0e CW |
7609 | goto fail_unpin; |
7610 | } | |
7611 | ||
f343c5f6 | 7612 | addr = i915_gem_obj_ggtt_offset(obj); |
71acb5eb | 7613 | } else { |
6eeefaf3 | 7614 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
05394f39 | 7615 | ret = i915_gem_attach_phys_object(dev, obj, |
6eeefaf3 CW |
7616 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
7617 | align); | |
71acb5eb DA |
7618 | if (ret) { |
7619 | DRM_ERROR("failed to attach phys object\n"); | |
7f9872e0 | 7620 | goto fail_locked; |
71acb5eb | 7621 | } |
05394f39 | 7622 | addr = obj->phys_obj->handle->busaddr; |
3f8bc370 KH |
7623 | } |
7624 | ||
a6c45cf0 | 7625 | if (IS_GEN2(dev)) |
14b60391 JB |
7626 | I915_WRITE(CURSIZE, (height << 12) | width); |
7627 | ||
3f8bc370 | 7628 | finish: |
3f8bc370 | 7629 | if (intel_crtc->cursor_bo) { |
3d13ef2e | 7630 | if (INTEL_INFO(dev)->cursor_needs_physical) { |
05394f39 | 7631 | if (intel_crtc->cursor_bo != obj) |
71acb5eb DA |
7632 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); |
7633 | } else | |
cc98b413 | 7634 | i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo); |
05394f39 | 7635 | drm_gem_object_unreference(&intel_crtc->cursor_bo->base); |
3f8bc370 | 7636 | } |
80824003 | 7637 | |
7f9872e0 | 7638 | mutex_unlock(&dev->struct_mutex); |
3f8bc370 KH |
7639 | |
7640 | intel_crtc->cursor_addr = addr; | |
05394f39 | 7641 | intel_crtc->cursor_bo = obj; |
cda4b7d3 CW |
7642 | intel_crtc->cursor_width = width; |
7643 | intel_crtc->cursor_height = height; | |
7644 | ||
f2f5f771 VS |
7645 | if (intel_crtc->active) |
7646 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); | |
3f8bc370 | 7647 | |
79e53945 | 7648 | return 0; |
e7b526bb | 7649 | fail_unpin: |
cc98b413 | 7650 | i915_gem_object_unpin_from_display_plane(obj); |
7f9872e0 | 7651 | fail_locked: |
34b8686e | 7652 | mutex_unlock(&dev->struct_mutex); |
bc9025bd | 7653 | fail: |
05394f39 | 7654 | drm_gem_object_unreference_unlocked(&obj->base); |
34b8686e | 7655 | return ret; |
79e53945 JB |
7656 | } |
7657 | ||
7658 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
7659 | { | |
79e53945 | 7660 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 7661 | |
92e76c8c VS |
7662 | intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX); |
7663 | intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX); | |
652c393a | 7664 | |
f2f5f771 VS |
7665 | if (intel_crtc->active) |
7666 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); | |
79e53945 JB |
7667 | |
7668 | return 0; | |
b8c00ac5 DA |
7669 | } |
7670 | ||
79e53945 | 7671 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 7672 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 7673 | { |
7203425a | 7674 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 7675 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 7676 | |
7203425a | 7677 | for (i = start; i < end; i++) { |
79e53945 JB |
7678 | intel_crtc->lut_r[i] = red[i] >> 8; |
7679 | intel_crtc->lut_g[i] = green[i] >> 8; | |
7680 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
7681 | } | |
7682 | ||
7683 | intel_crtc_load_lut(crtc); | |
7684 | } | |
7685 | ||
79e53945 JB |
7686 | /* VESA 640x480x72Hz mode to set on the pipe */ |
7687 | static struct drm_display_mode load_detect_mode = { | |
7688 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
7689 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
7690 | }; | |
7691 | ||
a8bb6818 DV |
7692 | static int intel_framebuffer_init(struct drm_device *dev, |
7693 | struct intel_framebuffer *ifb, | |
7694 | struct drm_mode_fb_cmd2 *mode_cmd, | |
7695 | struct drm_i915_gem_object *obj); | |
7696 | ||
7697 | struct drm_framebuffer * | |
7698 | __intel_framebuffer_create(struct drm_device *dev, | |
7699 | struct drm_mode_fb_cmd2 *mode_cmd, | |
7700 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
7701 | { |
7702 | struct intel_framebuffer *intel_fb; | |
7703 | int ret; | |
7704 | ||
7705 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
7706 | if (!intel_fb) { | |
7707 | drm_gem_object_unreference_unlocked(&obj->base); | |
7708 | return ERR_PTR(-ENOMEM); | |
7709 | } | |
7710 | ||
7711 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
7712 | if (ret) |
7713 | goto err; | |
d2dff872 CW |
7714 | |
7715 | return &intel_fb->base; | |
dd4916c5 DV |
7716 | err: |
7717 | drm_gem_object_unreference_unlocked(&obj->base); | |
7718 | kfree(intel_fb); | |
7719 | ||
7720 | return ERR_PTR(ret); | |
d2dff872 CW |
7721 | } |
7722 | ||
a8bb6818 DV |
7723 | struct drm_framebuffer * |
7724 | intel_framebuffer_create(struct drm_device *dev, | |
7725 | struct drm_mode_fb_cmd2 *mode_cmd, | |
7726 | struct drm_i915_gem_object *obj) | |
7727 | { | |
7728 | struct drm_framebuffer *fb; | |
7729 | int ret; | |
7730 | ||
7731 | ret = i915_mutex_lock_interruptible(dev); | |
7732 | if (ret) | |
7733 | return ERR_PTR(ret); | |
7734 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
7735 | mutex_unlock(&dev->struct_mutex); | |
7736 | ||
7737 | return fb; | |
7738 | } | |
7739 | ||
d2dff872 CW |
7740 | static u32 |
7741 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
7742 | { | |
7743 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
7744 | return ALIGN(pitch, 64); | |
7745 | } | |
7746 | ||
7747 | static u32 | |
7748 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
7749 | { | |
7750 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
7751 | return ALIGN(pitch * mode->vdisplay, PAGE_SIZE); | |
7752 | } | |
7753 | ||
7754 | static struct drm_framebuffer * | |
7755 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
7756 | struct drm_display_mode *mode, | |
7757 | int depth, int bpp) | |
7758 | { | |
7759 | struct drm_i915_gem_object *obj; | |
0fed39bd | 7760 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
7761 | |
7762 | obj = i915_gem_alloc_object(dev, | |
7763 | intel_framebuffer_size_for_mode(mode, bpp)); | |
7764 | if (obj == NULL) | |
7765 | return ERR_PTR(-ENOMEM); | |
7766 | ||
7767 | mode_cmd.width = mode->hdisplay; | |
7768 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
7769 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
7770 | bpp); | |
5ca0c34a | 7771 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
7772 | |
7773 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
7774 | } | |
7775 | ||
7776 | static struct drm_framebuffer * | |
7777 | mode_fits_in_fbdev(struct drm_device *dev, | |
7778 | struct drm_display_mode *mode) | |
7779 | { | |
4520f53a | 7780 | #ifdef CONFIG_DRM_I915_FBDEV |
d2dff872 CW |
7781 | struct drm_i915_private *dev_priv = dev->dev_private; |
7782 | struct drm_i915_gem_object *obj; | |
7783 | struct drm_framebuffer *fb; | |
7784 | ||
7785 | if (dev_priv->fbdev == NULL) | |
7786 | return NULL; | |
7787 | ||
8bcd4553 | 7788 | obj = dev_priv->fbdev->fb->obj; |
d2dff872 CW |
7789 | if (obj == NULL) |
7790 | return NULL; | |
7791 | ||
8bcd4553 | 7792 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
7793 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
7794 | fb->bits_per_pixel)) | |
d2dff872 CW |
7795 | return NULL; |
7796 | ||
01f2c773 | 7797 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
7798 | return NULL; |
7799 | ||
7800 | return fb; | |
4520f53a DV |
7801 | #else |
7802 | return NULL; | |
7803 | #endif | |
d2dff872 CW |
7804 | } |
7805 | ||
d2434ab7 | 7806 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 7807 | struct drm_display_mode *mode, |
8261b191 | 7808 | struct intel_load_detect_pipe *old) |
79e53945 JB |
7809 | { |
7810 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
7811 | struct intel_encoder *intel_encoder = |
7812 | intel_attached_encoder(connector); | |
79e53945 | 7813 | struct drm_crtc *possible_crtc; |
4ef69c7a | 7814 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
7815 | struct drm_crtc *crtc = NULL; |
7816 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 7817 | struct drm_framebuffer *fb; |
79e53945 JB |
7818 | int i = -1; |
7819 | ||
d2dff872 CW |
7820 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
7821 | connector->base.id, drm_get_connector_name(connector), | |
7822 | encoder->base.id, drm_get_encoder_name(encoder)); | |
7823 | ||
79e53945 JB |
7824 | /* |
7825 | * Algorithm gets a little messy: | |
7a5e4805 | 7826 | * |
79e53945 JB |
7827 | * - if the connector already has an assigned crtc, use it (but make |
7828 | * sure it's on first) | |
7a5e4805 | 7829 | * |
79e53945 JB |
7830 | * - try to find the first unused crtc that can drive this connector, |
7831 | * and use that if we find one | |
79e53945 JB |
7832 | */ |
7833 | ||
7834 | /* See if we already have a CRTC for this connector */ | |
7835 | if (encoder->crtc) { | |
7836 | crtc = encoder->crtc; | |
8261b191 | 7837 | |
7b24056b DV |
7838 | mutex_lock(&crtc->mutex); |
7839 | ||
24218aac | 7840 | old->dpms_mode = connector->dpms; |
8261b191 CW |
7841 | old->load_detect_temp = false; |
7842 | ||
7843 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
7844 | if (connector->dpms != DRM_MODE_DPMS_ON) |
7845 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 7846 | |
7173188d | 7847 | return true; |
79e53945 JB |
7848 | } |
7849 | ||
7850 | /* Find an unused one (if possible) */ | |
7851 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { | |
7852 | i++; | |
7853 | if (!(encoder->possible_crtcs & (1 << i))) | |
7854 | continue; | |
7855 | if (!possible_crtc->enabled) { | |
7856 | crtc = possible_crtc; | |
7857 | break; | |
7858 | } | |
79e53945 JB |
7859 | } |
7860 | ||
7861 | /* | |
7862 | * If we didn't find an unused CRTC, don't use any. | |
7863 | */ | |
7864 | if (!crtc) { | |
7173188d CW |
7865 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
7866 | return false; | |
79e53945 JB |
7867 | } |
7868 | ||
7b24056b | 7869 | mutex_lock(&crtc->mutex); |
fc303101 DV |
7870 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
7871 | to_intel_connector(connector)->new_encoder = intel_encoder; | |
79e53945 JB |
7872 | |
7873 | intel_crtc = to_intel_crtc(crtc); | |
412b61d8 VS |
7874 | intel_crtc->new_enabled = true; |
7875 | intel_crtc->new_config = &intel_crtc->config; | |
24218aac | 7876 | old->dpms_mode = connector->dpms; |
8261b191 | 7877 | old->load_detect_temp = true; |
d2dff872 | 7878 | old->release_fb = NULL; |
79e53945 | 7879 | |
6492711d CW |
7880 | if (!mode) |
7881 | mode = &load_detect_mode; | |
79e53945 | 7882 | |
d2dff872 CW |
7883 | /* We need a framebuffer large enough to accommodate all accesses |
7884 | * that the plane may generate whilst we perform load detection. | |
7885 | * We can not rely on the fbcon either being present (we get called | |
7886 | * during its initialisation to detect all boot displays, or it may | |
7887 | * not even exist) or that it is large enough to satisfy the | |
7888 | * requested mode. | |
7889 | */ | |
94352cf9 DV |
7890 | fb = mode_fits_in_fbdev(dev, mode); |
7891 | if (fb == NULL) { | |
d2dff872 | 7892 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
7893 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
7894 | old->release_fb = fb; | |
d2dff872 CW |
7895 | } else |
7896 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 7897 | if (IS_ERR(fb)) { |
d2dff872 | 7898 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 7899 | goto fail; |
79e53945 | 7900 | } |
79e53945 | 7901 | |
c0c36b94 | 7902 | if (intel_set_mode(crtc, mode, 0, 0, fb)) { |
6492711d | 7903 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
7904 | if (old->release_fb) |
7905 | old->release_fb->funcs->destroy(old->release_fb); | |
412b61d8 | 7906 | goto fail; |
79e53945 | 7907 | } |
7173188d | 7908 | |
79e53945 | 7909 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 7910 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 7911 | return true; |
412b61d8 VS |
7912 | |
7913 | fail: | |
7914 | intel_crtc->new_enabled = crtc->enabled; | |
7915 | if (intel_crtc->new_enabled) | |
7916 | intel_crtc->new_config = &intel_crtc->config; | |
7917 | else | |
7918 | intel_crtc->new_config = NULL; | |
7919 | mutex_unlock(&crtc->mutex); | |
7920 | return false; | |
79e53945 JB |
7921 | } |
7922 | ||
d2434ab7 | 7923 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
8261b191 | 7924 | struct intel_load_detect_pipe *old) |
79e53945 | 7925 | { |
d2434ab7 DV |
7926 | struct intel_encoder *intel_encoder = |
7927 | intel_attached_encoder(connector); | |
4ef69c7a | 7928 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 7929 | struct drm_crtc *crtc = encoder->crtc; |
412b61d8 | 7930 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 7931 | |
d2dff872 CW |
7932 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
7933 | connector->base.id, drm_get_connector_name(connector), | |
7934 | encoder->base.id, drm_get_encoder_name(encoder)); | |
7935 | ||
8261b191 | 7936 | if (old->load_detect_temp) { |
fc303101 DV |
7937 | to_intel_connector(connector)->new_encoder = NULL; |
7938 | intel_encoder->new_crtc = NULL; | |
412b61d8 VS |
7939 | intel_crtc->new_enabled = false; |
7940 | intel_crtc->new_config = NULL; | |
fc303101 | 7941 | intel_set_mode(crtc, NULL, 0, 0, NULL); |
d2dff872 | 7942 | |
36206361 DV |
7943 | if (old->release_fb) { |
7944 | drm_framebuffer_unregister_private(old->release_fb); | |
7945 | drm_framebuffer_unreference(old->release_fb); | |
7946 | } | |
d2dff872 | 7947 | |
67c96400 | 7948 | mutex_unlock(&crtc->mutex); |
0622a53c | 7949 | return; |
79e53945 JB |
7950 | } |
7951 | ||
c751ce4f | 7952 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
7953 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
7954 | connector->funcs->dpms(connector, old->dpms_mode); | |
7b24056b DV |
7955 | |
7956 | mutex_unlock(&crtc->mutex); | |
79e53945 JB |
7957 | } |
7958 | ||
da4a1efa VS |
7959 | static int i9xx_pll_refclk(struct drm_device *dev, |
7960 | const struct intel_crtc_config *pipe_config) | |
7961 | { | |
7962 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7963 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
7964 | ||
7965 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 7966 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
7967 | else if (HAS_PCH_SPLIT(dev)) |
7968 | return 120000; | |
7969 | else if (!IS_GEN2(dev)) | |
7970 | return 96000; | |
7971 | else | |
7972 | return 48000; | |
7973 | } | |
7974 | ||
79e53945 | 7975 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc JB |
7976 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
7977 | struct intel_crtc_config *pipe_config) | |
79e53945 | 7978 | { |
f1f644dc | 7979 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 7980 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 7981 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 7982 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
7983 | u32 fp; |
7984 | intel_clock_t clock; | |
da4a1efa | 7985 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
7986 | |
7987 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 7988 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 7989 | else |
293623f7 | 7990 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
7991 | |
7992 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
7993 | if (IS_PINEVIEW(dev)) { |
7994 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
7995 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
7996 | } else { |
7997 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
7998 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
7999 | } | |
8000 | ||
a6c45cf0 | 8001 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
8002 | if (IS_PINEVIEW(dev)) |
8003 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
8004 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
8005 | else |
8006 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
8007 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
8008 | ||
8009 | switch (dpll & DPLL_MODE_MASK) { | |
8010 | case DPLLB_MODE_DAC_SERIAL: | |
8011 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
8012 | 5 : 10; | |
8013 | break; | |
8014 | case DPLLB_MODE_LVDS: | |
8015 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
8016 | 7 : 14; | |
8017 | break; | |
8018 | default: | |
28c97730 | 8019 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 8020 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 8021 | return; |
79e53945 JB |
8022 | } |
8023 | ||
ac58c3f0 | 8024 | if (IS_PINEVIEW(dev)) |
da4a1efa | 8025 | pineview_clock(refclk, &clock); |
ac58c3f0 | 8026 | else |
da4a1efa | 8027 | i9xx_clock(refclk, &clock); |
79e53945 | 8028 | } else { |
0fb58223 | 8029 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 8030 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
8031 | |
8032 | if (is_lvds) { | |
8033 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
8034 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
8035 | |
8036 | if (lvds & LVDS_CLKB_POWER_UP) | |
8037 | clock.p2 = 7; | |
8038 | else | |
8039 | clock.p2 = 14; | |
79e53945 JB |
8040 | } else { |
8041 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
8042 | clock.p1 = 2; | |
8043 | else { | |
8044 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
8045 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
8046 | } | |
8047 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
8048 | clock.p2 = 4; | |
8049 | else | |
8050 | clock.p2 = 2; | |
79e53945 | 8051 | } |
da4a1efa VS |
8052 | |
8053 | i9xx_clock(refclk, &clock); | |
79e53945 JB |
8054 | } |
8055 | ||
18442d08 VS |
8056 | /* |
8057 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 8058 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
8059 | * encoder's get_config() function. |
8060 | */ | |
8061 | pipe_config->port_clock = clock.dot; | |
f1f644dc JB |
8062 | } |
8063 | ||
6878da05 VS |
8064 | int intel_dotclock_calculate(int link_freq, |
8065 | const struct intel_link_m_n *m_n) | |
f1f644dc | 8066 | { |
f1f644dc JB |
8067 | /* |
8068 | * The calculation for the data clock is: | |
1041a02f | 8069 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 8070 | * But we want to avoid losing precison if possible, so: |
1041a02f | 8071 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
8072 | * |
8073 | * and the link clock is simpler: | |
1041a02f | 8074 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
8075 | */ |
8076 | ||
6878da05 VS |
8077 | if (!m_n->link_n) |
8078 | return 0; | |
f1f644dc | 8079 | |
6878da05 VS |
8080 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
8081 | } | |
f1f644dc | 8082 | |
18442d08 VS |
8083 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
8084 | struct intel_crtc_config *pipe_config) | |
6878da05 VS |
8085 | { |
8086 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 8087 | |
18442d08 VS |
8088 | /* read out port_clock from the DPLL */ |
8089 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 8090 | |
f1f644dc | 8091 | /* |
18442d08 | 8092 | * This value does not include pixel_multiplier. |
241bfc38 | 8093 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
8094 | * agree once we know their relationship in the encoder's |
8095 | * get_config() function. | |
79e53945 | 8096 | */ |
241bfc38 | 8097 | pipe_config->adjusted_mode.crtc_clock = |
18442d08 VS |
8098 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
8099 | &pipe_config->fdi_m_n); | |
79e53945 JB |
8100 | } |
8101 | ||
8102 | /** Returns the currently programmed mode of the given pipe. */ | |
8103 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
8104 | struct drm_crtc *crtc) | |
8105 | { | |
548f245b | 8106 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 8107 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3b117c8f | 8108 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
79e53945 | 8109 | struct drm_display_mode *mode; |
f1f644dc | 8110 | struct intel_crtc_config pipe_config; |
fe2b8f9d PZ |
8111 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
8112 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
8113 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
8114 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 8115 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
8116 | |
8117 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
8118 | if (!mode) | |
8119 | return NULL; | |
8120 | ||
f1f644dc JB |
8121 | /* |
8122 | * Construct a pipe_config sufficient for getting the clock info | |
8123 | * back out of crtc_clock_get. | |
8124 | * | |
8125 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
8126 | * to use a real value here instead. | |
8127 | */ | |
293623f7 | 8128 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 8129 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
8130 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
8131 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
8132 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
8133 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
8134 | ||
773ae034 | 8135 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
79e53945 JB |
8136 | mode->hdisplay = (htot & 0xffff) + 1; |
8137 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
8138 | mode->hsync_start = (hsync & 0xffff) + 1; | |
8139 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
8140 | mode->vdisplay = (vtot & 0xffff) + 1; | |
8141 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
8142 | mode->vsync_start = (vsync & 0xffff) + 1; | |
8143 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
8144 | ||
8145 | drm_mode_set_name(mode); | |
79e53945 JB |
8146 | |
8147 | return mode; | |
8148 | } | |
8149 | ||
3dec0095 | 8150 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
652c393a JB |
8151 | { |
8152 | struct drm_device *dev = crtc->dev; | |
8153 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8154 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8155 | int pipe = intel_crtc->pipe; | |
dbdc6479 JB |
8156 | int dpll_reg = DPLL(pipe); |
8157 | int dpll; | |
652c393a | 8158 | |
bad720ff | 8159 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
8160 | return; |
8161 | ||
8162 | if (!dev_priv->lvds_downclock_avail) | |
8163 | return; | |
8164 | ||
dbdc6479 | 8165 | dpll = I915_READ(dpll_reg); |
652c393a | 8166 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
44d98a61 | 8167 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
652c393a | 8168 | |
8ac5a6d5 | 8169 | assert_panel_unlocked(dev_priv, pipe); |
652c393a JB |
8170 | |
8171 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; | |
8172 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 8173 | intel_wait_for_vblank(dev, pipe); |
dbdc6479 | 8174 | |
652c393a JB |
8175 | dpll = I915_READ(dpll_reg); |
8176 | if (dpll & DISPLAY_RATE_SELECT_FPA1) | |
44d98a61 | 8177 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
652c393a | 8178 | } |
652c393a JB |
8179 | } |
8180 | ||
8181 | static void intel_decrease_pllclock(struct drm_crtc *crtc) | |
8182 | { | |
8183 | struct drm_device *dev = crtc->dev; | |
8184 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8185 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
652c393a | 8186 | |
bad720ff | 8187 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
8188 | return; |
8189 | ||
8190 | if (!dev_priv->lvds_downclock_avail) | |
8191 | return; | |
8192 | ||
8193 | /* | |
8194 | * Since this is called by a timer, we should never get here in | |
8195 | * the manual case. | |
8196 | */ | |
8197 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
dc257cf1 DV |
8198 | int pipe = intel_crtc->pipe; |
8199 | int dpll_reg = DPLL(pipe); | |
8200 | int dpll; | |
f6e5b160 | 8201 | |
44d98a61 | 8202 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 8203 | |
8ac5a6d5 | 8204 | assert_panel_unlocked(dev_priv, pipe); |
652c393a | 8205 | |
dc257cf1 | 8206 | dpll = I915_READ(dpll_reg); |
652c393a JB |
8207 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
8208 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 8209 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
8210 | dpll = I915_READ(dpll_reg); |
8211 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 8212 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
8213 | } |
8214 | ||
8215 | } | |
8216 | ||
f047e395 CW |
8217 | void intel_mark_busy(struct drm_device *dev) |
8218 | { | |
c67a470b PZ |
8219 | struct drm_i915_private *dev_priv = dev->dev_private; |
8220 | ||
8221 | hsw_package_c8_gpu_busy(dev_priv); | |
8222 | i915_update_gfx_val(dev_priv); | |
f047e395 CW |
8223 | } |
8224 | ||
8225 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 8226 | { |
c67a470b | 8227 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 8228 | struct drm_crtc *crtc; |
652c393a | 8229 | |
c67a470b PZ |
8230 | hsw_package_c8_gpu_idle(dev_priv); |
8231 | ||
d330a953 | 8232 | if (!i915.powersave) |
652c393a JB |
8233 | return; |
8234 | ||
652c393a | 8235 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
652c393a JB |
8236 | if (!crtc->fb) |
8237 | continue; | |
8238 | ||
725a5b54 | 8239 | intel_decrease_pllclock(crtc); |
652c393a | 8240 | } |
b29c19b6 | 8241 | |
3d13ef2e | 8242 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 8243 | gen6_rps_idle(dev->dev_private); |
652c393a JB |
8244 | } |
8245 | ||
c65355bb CW |
8246 | void intel_mark_fb_busy(struct drm_i915_gem_object *obj, |
8247 | struct intel_ring_buffer *ring) | |
652c393a | 8248 | { |
f047e395 CW |
8249 | struct drm_device *dev = obj->base.dev; |
8250 | struct drm_crtc *crtc; | |
652c393a | 8251 | |
d330a953 | 8252 | if (!i915.powersave) |
acb87dfb CW |
8253 | return; |
8254 | ||
652c393a JB |
8255 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
8256 | if (!crtc->fb) | |
8257 | continue; | |
8258 | ||
c65355bb CW |
8259 | if (to_intel_framebuffer(crtc->fb)->obj != obj) |
8260 | continue; | |
8261 | ||
8262 | intel_increase_pllclock(crtc); | |
8263 | if (ring && intel_fbc_enabled(dev)) | |
8264 | ring->fbc_dirty = true; | |
652c393a JB |
8265 | } |
8266 | } | |
8267 | ||
79e53945 JB |
8268 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
8269 | { | |
8270 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
8271 | struct drm_device *dev = crtc->dev; |
8272 | struct intel_unpin_work *work; | |
8273 | unsigned long flags; | |
8274 | ||
8275 | spin_lock_irqsave(&dev->event_lock, flags); | |
8276 | work = intel_crtc->unpin_work; | |
8277 | intel_crtc->unpin_work = NULL; | |
8278 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
8279 | ||
8280 | if (work) { | |
8281 | cancel_work_sync(&work->work); | |
8282 | kfree(work); | |
8283 | } | |
79e53945 | 8284 | |
40ccc72b MK |
8285 | intel_crtc_cursor_set(crtc, NULL, 0, 0, 0); |
8286 | ||
79e53945 | 8287 | drm_crtc_cleanup(crtc); |
67e77c5a | 8288 | |
79e53945 JB |
8289 | kfree(intel_crtc); |
8290 | } | |
8291 | ||
6b95a207 KH |
8292 | static void intel_unpin_work_fn(struct work_struct *__work) |
8293 | { | |
8294 | struct intel_unpin_work *work = | |
8295 | container_of(__work, struct intel_unpin_work, work); | |
b4a98e57 | 8296 | struct drm_device *dev = work->crtc->dev; |
6b95a207 | 8297 | |
b4a98e57 | 8298 | mutex_lock(&dev->struct_mutex); |
1690e1eb | 8299 | intel_unpin_fb_obj(work->old_fb_obj); |
05394f39 CW |
8300 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
8301 | drm_gem_object_unreference(&work->old_fb_obj->base); | |
d9e86c0e | 8302 | |
b4a98e57 CW |
8303 | intel_update_fbc(dev); |
8304 | mutex_unlock(&dev->struct_mutex); | |
8305 | ||
8306 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); | |
8307 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); | |
8308 | ||
6b95a207 KH |
8309 | kfree(work); |
8310 | } | |
8311 | ||
1afe3e9d | 8312 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 8313 | struct drm_crtc *crtc) |
6b95a207 KH |
8314 | { |
8315 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6b95a207 KH |
8316 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8317 | struct intel_unpin_work *work; | |
6b95a207 KH |
8318 | unsigned long flags; |
8319 | ||
8320 | /* Ignore early vblank irqs */ | |
8321 | if (intel_crtc == NULL) | |
8322 | return; | |
8323 | ||
8324 | spin_lock_irqsave(&dev->event_lock, flags); | |
8325 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
8326 | |
8327 | /* Ensure we don't miss a work->pending update ... */ | |
8328 | smp_rmb(); | |
8329 | ||
8330 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
8331 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8332 | return; | |
8333 | } | |
8334 | ||
e7d841ca CW |
8335 | /* and that the unpin work is consistent wrt ->pending. */ |
8336 | smp_rmb(); | |
8337 | ||
6b95a207 | 8338 | intel_crtc->unpin_work = NULL; |
6b95a207 | 8339 | |
45a066eb RC |
8340 | if (work->event) |
8341 | drm_send_vblank_event(dev, intel_crtc->pipe, work->event); | |
6b95a207 | 8342 | |
0af7e4df MK |
8343 | drm_vblank_put(dev, intel_crtc->pipe); |
8344 | ||
6b95a207 KH |
8345 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8346 | ||
2c10d571 | 8347 | wake_up_all(&dev_priv->pending_flip_queue); |
b4a98e57 CW |
8348 | |
8349 | queue_work(dev_priv->wq, &work->work); | |
e5510fac JB |
8350 | |
8351 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); | |
6b95a207 KH |
8352 | } |
8353 | ||
1afe3e9d JB |
8354 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
8355 | { | |
8356 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8357 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
8358 | ||
49b14a5c | 8359 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
8360 | } |
8361 | ||
8362 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
8363 | { | |
8364 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8365 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; | |
8366 | ||
49b14a5c | 8367 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
8368 | } |
8369 | ||
6b95a207 KH |
8370 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
8371 | { | |
8372 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8373 | struct intel_crtc *intel_crtc = | |
8374 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
8375 | unsigned long flags; | |
8376 | ||
e7d841ca CW |
8377 | /* NB: An MMIO update of the plane base pointer will also |
8378 | * generate a page-flip completion irq, i.e. every modeset | |
8379 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
8380 | */ | |
6b95a207 | 8381 | spin_lock_irqsave(&dev->event_lock, flags); |
e7d841ca CW |
8382 | if (intel_crtc->unpin_work) |
8383 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); | |
6b95a207 KH |
8384 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8385 | } | |
8386 | ||
e7d841ca CW |
8387 | inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
8388 | { | |
8389 | /* Ensure that the work item is consistent when activating it ... */ | |
8390 | smp_wmb(); | |
8391 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); | |
8392 | /* and that it is marked active as soon as the irq could fire. */ | |
8393 | smp_wmb(); | |
8394 | } | |
8395 | ||
8c9f3aaf JB |
8396 | static int intel_gen2_queue_flip(struct drm_device *dev, |
8397 | struct drm_crtc *crtc, | |
8398 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8399 | struct drm_i915_gem_object *obj, |
8400 | uint32_t flags) | |
8c9f3aaf JB |
8401 | { |
8402 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8403 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8c9f3aaf | 8404 | u32 flip_mask; |
6d90c952 | 8405 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
8406 | int ret; |
8407 | ||
6d90c952 | 8408 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 8409 | if (ret) |
83d4092b | 8410 | goto err; |
8c9f3aaf | 8411 | |
6d90c952 | 8412 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 8413 | if (ret) |
83d4092b | 8414 | goto err_unpin; |
8c9f3aaf JB |
8415 | |
8416 | /* Can't queue multiple flips, so wait for the previous | |
8417 | * one to finish before executing the next. | |
8418 | */ | |
8419 | if (intel_crtc->plane) | |
8420 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
8421 | else | |
8422 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
8423 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
8424 | intel_ring_emit(ring, MI_NOOP); | |
8425 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
8426 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
8427 | intel_ring_emit(ring, fb->pitches[0]); | |
f343c5f6 | 8428 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
6d90c952 | 8429 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca CW |
8430 | |
8431 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 8432 | __intel_ring_advance(ring); |
83d4092b CW |
8433 | return 0; |
8434 | ||
8435 | err_unpin: | |
8436 | intel_unpin_fb_obj(obj); | |
8437 | err: | |
8c9f3aaf JB |
8438 | return ret; |
8439 | } | |
8440 | ||
8441 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
8442 | struct drm_crtc *crtc, | |
8443 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8444 | struct drm_i915_gem_object *obj, |
8445 | uint32_t flags) | |
8c9f3aaf JB |
8446 | { |
8447 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8448 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8c9f3aaf | 8449 | u32 flip_mask; |
6d90c952 | 8450 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
8451 | int ret; |
8452 | ||
6d90c952 | 8453 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 8454 | if (ret) |
83d4092b | 8455 | goto err; |
8c9f3aaf | 8456 | |
6d90c952 | 8457 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 8458 | if (ret) |
83d4092b | 8459 | goto err_unpin; |
8c9f3aaf JB |
8460 | |
8461 | if (intel_crtc->plane) | |
8462 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
8463 | else | |
8464 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
8465 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
8466 | intel_ring_emit(ring, MI_NOOP); | |
8467 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
8468 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
8469 | intel_ring_emit(ring, fb->pitches[0]); | |
f343c5f6 | 8470 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
6d90c952 DV |
8471 | intel_ring_emit(ring, MI_NOOP); |
8472 | ||
e7d841ca | 8473 | intel_mark_page_flip_active(intel_crtc); |
09246732 | 8474 | __intel_ring_advance(ring); |
83d4092b CW |
8475 | return 0; |
8476 | ||
8477 | err_unpin: | |
8478 | intel_unpin_fb_obj(obj); | |
8479 | err: | |
8c9f3aaf JB |
8480 | return ret; |
8481 | } | |
8482 | ||
8483 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
8484 | struct drm_crtc *crtc, | |
8485 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8486 | struct drm_i915_gem_object *obj, |
8487 | uint32_t flags) | |
8c9f3aaf JB |
8488 | { |
8489 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8490 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8491 | uint32_t pf, pipesrc; | |
6d90c952 | 8492 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
8493 | int ret; |
8494 | ||
6d90c952 | 8495 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 8496 | if (ret) |
83d4092b | 8497 | goto err; |
8c9f3aaf | 8498 | |
6d90c952 | 8499 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 8500 | if (ret) |
83d4092b | 8501 | goto err_unpin; |
8c9f3aaf JB |
8502 | |
8503 | /* i965+ uses the linear or tiled offsets from the | |
8504 | * Display Registers (which do not change across a page-flip) | |
8505 | * so we need only reprogram the base address. | |
8506 | */ | |
6d90c952 DV |
8507 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
8508 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
8509 | intel_ring_emit(ring, fb->pitches[0]); | |
c2c75131 | 8510 | intel_ring_emit(ring, |
f343c5f6 | 8511 | (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) | |
c2c75131 | 8512 | obj->tiling_mode); |
8c9f3aaf JB |
8513 | |
8514 | /* XXX Enabling the panel-fitter across page-flip is so far | |
8515 | * untested on non-native modes, so ignore it for now. | |
8516 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
8517 | */ | |
8518 | pf = 0; | |
8519 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 8520 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
8521 | |
8522 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 8523 | __intel_ring_advance(ring); |
83d4092b CW |
8524 | return 0; |
8525 | ||
8526 | err_unpin: | |
8527 | intel_unpin_fb_obj(obj); | |
8528 | err: | |
8c9f3aaf JB |
8529 | return ret; |
8530 | } | |
8531 | ||
8532 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
8533 | struct drm_crtc *crtc, | |
8534 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8535 | struct drm_i915_gem_object *obj, |
8536 | uint32_t flags) | |
8c9f3aaf JB |
8537 | { |
8538 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8539 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6d90c952 | 8540 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
8541 | uint32_t pf, pipesrc; |
8542 | int ret; | |
8543 | ||
6d90c952 | 8544 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 8545 | if (ret) |
83d4092b | 8546 | goto err; |
8c9f3aaf | 8547 | |
6d90c952 | 8548 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 8549 | if (ret) |
83d4092b | 8550 | goto err_unpin; |
8c9f3aaf | 8551 | |
6d90c952 DV |
8552 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
8553 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
8554 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
f343c5f6 | 8555 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
8c9f3aaf | 8556 | |
dc257cf1 DV |
8557 | /* Contrary to the suggestions in the documentation, |
8558 | * "Enable Panel Fitter" does not seem to be required when page | |
8559 | * flipping with a non-native mode, and worse causes a normal | |
8560 | * modeset to fail. | |
8561 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
8562 | */ | |
8563 | pf = 0; | |
8c9f3aaf | 8564 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 8565 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
8566 | |
8567 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 8568 | __intel_ring_advance(ring); |
83d4092b CW |
8569 | return 0; |
8570 | ||
8571 | err_unpin: | |
8572 | intel_unpin_fb_obj(obj); | |
8573 | err: | |
8c9f3aaf JB |
8574 | return ret; |
8575 | } | |
8576 | ||
7c9017e5 JB |
8577 | static int intel_gen7_queue_flip(struct drm_device *dev, |
8578 | struct drm_crtc *crtc, | |
8579 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8580 | struct drm_i915_gem_object *obj, |
8581 | uint32_t flags) | |
7c9017e5 JB |
8582 | { |
8583 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8584 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ffe74d75 | 8585 | struct intel_ring_buffer *ring; |
cb05d8de | 8586 | uint32_t plane_bit = 0; |
ffe74d75 CW |
8587 | int len, ret; |
8588 | ||
8589 | ring = obj->ring; | |
1c5fd085 | 8590 | if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS) |
ffe74d75 | 8591 | ring = &dev_priv->ring[BCS]; |
7c9017e5 JB |
8592 | |
8593 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); | |
8594 | if (ret) | |
83d4092b | 8595 | goto err; |
7c9017e5 | 8596 | |
cb05d8de DV |
8597 | switch(intel_crtc->plane) { |
8598 | case PLANE_A: | |
8599 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
8600 | break; | |
8601 | case PLANE_B: | |
8602 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
8603 | break; | |
8604 | case PLANE_C: | |
8605 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
8606 | break; | |
8607 | default: | |
8608 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
8609 | ret = -ENODEV; | |
ab3951eb | 8610 | goto err_unpin; |
cb05d8de DV |
8611 | } |
8612 | ||
ffe74d75 CW |
8613 | len = 4; |
8614 | if (ring->id == RCS) | |
8615 | len += 6; | |
8616 | ||
8617 | ret = intel_ring_begin(ring, len); | |
7c9017e5 | 8618 | if (ret) |
83d4092b | 8619 | goto err_unpin; |
7c9017e5 | 8620 | |
ffe74d75 CW |
8621 | /* Unmask the flip-done completion message. Note that the bspec says that |
8622 | * we should do this for both the BCS and RCS, and that we must not unmask | |
8623 | * more than one flip event at any time (or ensure that one flip message | |
8624 | * can be sent by waiting for flip-done prior to queueing new flips). | |
8625 | * Experimentation says that BCS works despite DERRMR masking all | |
8626 | * flip-done completion events and that unmasking all planes at once | |
8627 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
8628 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
8629 | */ | |
8630 | if (ring->id == RCS) { | |
8631 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
8632 | intel_ring_emit(ring, DERRMR); | |
8633 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
8634 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
8635 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
22613c96 VS |
8636 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | |
8637 | MI_SRM_LRM_GLOBAL_GTT); | |
ffe74d75 CW |
8638 | intel_ring_emit(ring, DERRMR); |
8639 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
8640 | } | |
8641 | ||
cb05d8de | 8642 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 8643 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
f343c5f6 | 8644 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
7c9017e5 | 8645 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca CW |
8646 | |
8647 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 8648 | __intel_ring_advance(ring); |
83d4092b CW |
8649 | return 0; |
8650 | ||
8651 | err_unpin: | |
8652 | intel_unpin_fb_obj(obj); | |
8653 | err: | |
7c9017e5 JB |
8654 | return ret; |
8655 | } | |
8656 | ||
8c9f3aaf JB |
8657 | static int intel_default_queue_flip(struct drm_device *dev, |
8658 | struct drm_crtc *crtc, | |
8659 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8660 | struct drm_i915_gem_object *obj, |
8661 | uint32_t flags) | |
8c9f3aaf JB |
8662 | { |
8663 | return -ENODEV; | |
8664 | } | |
8665 | ||
6b95a207 KH |
8666 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
8667 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8668 | struct drm_pending_vblank_event *event, |
8669 | uint32_t page_flip_flags) | |
6b95a207 KH |
8670 | { |
8671 | struct drm_device *dev = crtc->dev; | |
8672 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4a35f83b VS |
8673 | struct drm_framebuffer *old_fb = crtc->fb; |
8674 | struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj; | |
6b95a207 KH |
8675 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8676 | struct intel_unpin_work *work; | |
8c9f3aaf | 8677 | unsigned long flags; |
52e68630 | 8678 | int ret; |
6b95a207 | 8679 | |
e6a595d2 VS |
8680 | /* Can't change pixel format via MI display flips. */ |
8681 | if (fb->pixel_format != crtc->fb->pixel_format) | |
8682 | return -EINVAL; | |
8683 | ||
8684 | /* | |
8685 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
8686 | * Note that pitch changes could also affect these register. | |
8687 | */ | |
8688 | if (INTEL_INFO(dev)->gen > 3 && | |
8689 | (fb->offsets[0] != crtc->fb->offsets[0] || | |
8690 | fb->pitches[0] != crtc->fb->pitches[0])) | |
8691 | return -EINVAL; | |
8692 | ||
b14c5679 | 8693 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
8694 | if (work == NULL) |
8695 | return -ENOMEM; | |
8696 | ||
6b95a207 | 8697 | work->event = event; |
b4a98e57 | 8698 | work->crtc = crtc; |
4a35f83b | 8699 | work->old_fb_obj = to_intel_framebuffer(old_fb)->obj; |
6b95a207 KH |
8700 | INIT_WORK(&work->work, intel_unpin_work_fn); |
8701 | ||
7317c75e JB |
8702 | ret = drm_vblank_get(dev, intel_crtc->pipe); |
8703 | if (ret) | |
8704 | goto free_work; | |
8705 | ||
6b95a207 KH |
8706 | /* We borrow the event spin lock for protecting unpin_work */ |
8707 | spin_lock_irqsave(&dev->event_lock, flags); | |
8708 | if (intel_crtc->unpin_work) { | |
8709 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
8710 | kfree(work); | |
7317c75e | 8711 | drm_vblank_put(dev, intel_crtc->pipe); |
468f0b44 CW |
8712 | |
8713 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
6b95a207 KH |
8714 | return -EBUSY; |
8715 | } | |
8716 | intel_crtc->unpin_work = work; | |
8717 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
8718 | ||
b4a98e57 CW |
8719 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
8720 | flush_workqueue(dev_priv->wq); | |
8721 | ||
79158103 CW |
8722 | ret = i915_mutex_lock_interruptible(dev); |
8723 | if (ret) | |
8724 | goto cleanup; | |
6b95a207 | 8725 | |
75dfca80 | 8726 | /* Reference the objects for the scheduled work. */ |
05394f39 CW |
8727 | drm_gem_object_reference(&work->old_fb_obj->base); |
8728 | drm_gem_object_reference(&obj->base); | |
6b95a207 KH |
8729 | |
8730 | crtc->fb = fb; | |
96b099fd | 8731 | |
e1f99ce6 | 8732 | work->pending_flip_obj = obj; |
e1f99ce6 | 8733 | |
4e5359cd SF |
8734 | work->enable_stall_check = true; |
8735 | ||
b4a98e57 | 8736 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 8737 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 8738 | |
ed8d1975 | 8739 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags); |
8c9f3aaf JB |
8740 | if (ret) |
8741 | goto cleanup_pending; | |
6b95a207 | 8742 | |
7782de3b | 8743 | intel_disable_fbc(dev); |
c65355bb | 8744 | intel_mark_fb_busy(obj, NULL); |
6b95a207 KH |
8745 | mutex_unlock(&dev->struct_mutex); |
8746 | ||
e5510fac JB |
8747 | trace_i915_flip_request(intel_crtc->plane, obj); |
8748 | ||
6b95a207 | 8749 | return 0; |
96b099fd | 8750 | |
8c9f3aaf | 8751 | cleanup_pending: |
b4a98e57 | 8752 | atomic_dec(&intel_crtc->unpin_work_count); |
4a35f83b | 8753 | crtc->fb = old_fb; |
05394f39 CW |
8754 | drm_gem_object_unreference(&work->old_fb_obj->base); |
8755 | drm_gem_object_unreference(&obj->base); | |
96b099fd CW |
8756 | mutex_unlock(&dev->struct_mutex); |
8757 | ||
79158103 | 8758 | cleanup: |
96b099fd CW |
8759 | spin_lock_irqsave(&dev->event_lock, flags); |
8760 | intel_crtc->unpin_work = NULL; | |
8761 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
8762 | ||
7317c75e JB |
8763 | drm_vblank_put(dev, intel_crtc->pipe); |
8764 | free_work: | |
96b099fd CW |
8765 | kfree(work); |
8766 | ||
8767 | return ret; | |
6b95a207 KH |
8768 | } |
8769 | ||
f6e5b160 | 8770 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
8771 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
8772 | .load_lut = intel_crtc_load_lut, | |
f6e5b160 CW |
8773 | }; |
8774 | ||
9a935856 DV |
8775 | /** |
8776 | * intel_modeset_update_staged_output_state | |
8777 | * | |
8778 | * Updates the staged output configuration state, e.g. after we've read out the | |
8779 | * current hw state. | |
8780 | */ | |
8781 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) | |
f6e5b160 | 8782 | { |
7668851f | 8783 | struct intel_crtc *crtc; |
9a935856 DV |
8784 | struct intel_encoder *encoder; |
8785 | struct intel_connector *connector; | |
f6e5b160 | 8786 | |
9a935856 DV |
8787 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8788 | base.head) { | |
8789 | connector->new_encoder = | |
8790 | to_intel_encoder(connector->base.encoder); | |
8791 | } | |
f6e5b160 | 8792 | |
9a935856 DV |
8793 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8794 | base.head) { | |
8795 | encoder->new_crtc = | |
8796 | to_intel_crtc(encoder->base.crtc); | |
8797 | } | |
7668851f VS |
8798 | |
8799 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
8800 | base.head) { | |
8801 | crtc->new_enabled = crtc->base.enabled; | |
7bd0a8e7 VS |
8802 | |
8803 | if (crtc->new_enabled) | |
8804 | crtc->new_config = &crtc->config; | |
8805 | else | |
8806 | crtc->new_config = NULL; | |
7668851f | 8807 | } |
f6e5b160 CW |
8808 | } |
8809 | ||
9a935856 DV |
8810 | /** |
8811 | * intel_modeset_commit_output_state | |
8812 | * | |
8813 | * This function copies the stage display pipe configuration to the real one. | |
8814 | */ | |
8815 | static void intel_modeset_commit_output_state(struct drm_device *dev) | |
8816 | { | |
7668851f | 8817 | struct intel_crtc *crtc; |
9a935856 DV |
8818 | struct intel_encoder *encoder; |
8819 | struct intel_connector *connector; | |
f6e5b160 | 8820 | |
9a935856 DV |
8821 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8822 | base.head) { | |
8823 | connector->base.encoder = &connector->new_encoder->base; | |
8824 | } | |
f6e5b160 | 8825 | |
9a935856 DV |
8826 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8827 | base.head) { | |
8828 | encoder->base.crtc = &encoder->new_crtc->base; | |
8829 | } | |
7668851f VS |
8830 | |
8831 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
8832 | base.head) { | |
8833 | crtc->base.enabled = crtc->new_enabled; | |
8834 | } | |
9a935856 DV |
8835 | } |
8836 | ||
050f7aeb DV |
8837 | static void |
8838 | connected_sink_compute_bpp(struct intel_connector * connector, | |
8839 | struct intel_crtc_config *pipe_config) | |
8840 | { | |
8841 | int bpp = pipe_config->pipe_bpp; | |
8842 | ||
8843 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
8844 | connector->base.base.id, | |
8845 | drm_get_connector_name(&connector->base)); | |
8846 | ||
8847 | /* Don't use an invalid EDID bpc value */ | |
8848 | if (connector->base.display_info.bpc && | |
8849 | connector->base.display_info.bpc * 3 < bpp) { | |
8850 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
8851 | bpp, connector->base.display_info.bpc*3); | |
8852 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
8853 | } | |
8854 | ||
8855 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
8856 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
8857 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
8858 | bpp); | |
8859 | pipe_config->pipe_bpp = 24; | |
8860 | } | |
8861 | } | |
8862 | ||
4e53c2e0 | 8863 | static int |
050f7aeb DV |
8864 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
8865 | struct drm_framebuffer *fb, | |
8866 | struct intel_crtc_config *pipe_config) | |
4e53c2e0 | 8867 | { |
050f7aeb DV |
8868 | struct drm_device *dev = crtc->base.dev; |
8869 | struct intel_connector *connector; | |
4e53c2e0 DV |
8870 | int bpp; |
8871 | ||
d42264b1 DV |
8872 | switch (fb->pixel_format) { |
8873 | case DRM_FORMAT_C8: | |
4e53c2e0 DV |
8874 | bpp = 8*3; /* since we go through a colormap */ |
8875 | break; | |
d42264b1 DV |
8876 | case DRM_FORMAT_XRGB1555: |
8877 | case DRM_FORMAT_ARGB1555: | |
8878 | /* checked in intel_framebuffer_init already */ | |
8879 | if (WARN_ON(INTEL_INFO(dev)->gen > 3)) | |
8880 | return -EINVAL; | |
8881 | case DRM_FORMAT_RGB565: | |
4e53c2e0 DV |
8882 | bpp = 6*3; /* min is 18bpp */ |
8883 | break; | |
d42264b1 DV |
8884 | case DRM_FORMAT_XBGR8888: |
8885 | case DRM_FORMAT_ABGR8888: | |
8886 | /* checked in intel_framebuffer_init already */ | |
8887 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
8888 | return -EINVAL; | |
8889 | case DRM_FORMAT_XRGB8888: | |
8890 | case DRM_FORMAT_ARGB8888: | |
4e53c2e0 DV |
8891 | bpp = 8*3; |
8892 | break; | |
d42264b1 DV |
8893 | case DRM_FORMAT_XRGB2101010: |
8894 | case DRM_FORMAT_ARGB2101010: | |
8895 | case DRM_FORMAT_XBGR2101010: | |
8896 | case DRM_FORMAT_ABGR2101010: | |
8897 | /* checked in intel_framebuffer_init already */ | |
8898 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
baba133a | 8899 | return -EINVAL; |
4e53c2e0 DV |
8900 | bpp = 10*3; |
8901 | break; | |
baba133a | 8902 | /* TODO: gen4+ supports 16 bpc floating point, too. */ |
4e53c2e0 DV |
8903 | default: |
8904 | DRM_DEBUG_KMS("unsupported depth\n"); | |
8905 | return -EINVAL; | |
8906 | } | |
8907 | ||
4e53c2e0 DV |
8908 | pipe_config->pipe_bpp = bpp; |
8909 | ||
8910 | /* Clamp display bpp to EDID value */ | |
8911 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
050f7aeb | 8912 | base.head) { |
1b829e05 DV |
8913 | if (!connector->new_encoder || |
8914 | connector->new_encoder->new_crtc != crtc) | |
4e53c2e0 DV |
8915 | continue; |
8916 | ||
050f7aeb | 8917 | connected_sink_compute_bpp(connector, pipe_config); |
4e53c2e0 DV |
8918 | } |
8919 | ||
8920 | return bpp; | |
8921 | } | |
8922 | ||
644db711 DV |
8923 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
8924 | { | |
8925 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
8926 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 8927 | mode->crtc_clock, |
644db711 DV |
8928 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
8929 | mode->crtc_hsync_end, mode->crtc_htotal, | |
8930 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
8931 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
8932 | } | |
8933 | ||
c0b03411 DV |
8934 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
8935 | struct intel_crtc_config *pipe_config, | |
8936 | const char *context) | |
8937 | { | |
8938 | DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id, | |
8939 | context, pipe_name(crtc->pipe)); | |
8940 | ||
8941 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
8942 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
8943 | pipe_config->pipe_bpp, pipe_config->dither); | |
8944 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
8945 | pipe_config->has_pch_encoder, | |
8946 | pipe_config->fdi_lanes, | |
8947 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
8948 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
8949 | pipe_config->fdi_m_n.tu); | |
eb14cb74 VS |
8950 | DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
8951 | pipe_config->has_dp_encoder, | |
8952 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, | |
8953 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
8954 | pipe_config->dp_m_n.tu); | |
c0b03411 DV |
8955 | DRM_DEBUG_KMS("requested mode:\n"); |
8956 | drm_mode_debug_printmodeline(&pipe_config->requested_mode); | |
8957 | DRM_DEBUG_KMS("adjusted mode:\n"); | |
8958 | drm_mode_debug_printmodeline(&pipe_config->adjusted_mode); | |
644db711 | 8959 | intel_dump_crtc_timings(&pipe_config->adjusted_mode); |
d71b8d4a | 8960 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
8961 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
8962 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
c0b03411 DV |
8963 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
8964 | pipe_config->gmch_pfit.control, | |
8965 | pipe_config->gmch_pfit.pgm_ratios, | |
8966 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 8967 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 8968 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
8969 | pipe_config->pch_pfit.size, |
8970 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 8971 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 8972 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
c0b03411 DV |
8973 | } |
8974 | ||
accfc0c5 DV |
8975 | static bool check_encoder_cloning(struct drm_crtc *crtc) |
8976 | { | |
8977 | int num_encoders = 0; | |
8978 | bool uncloneable_encoders = false; | |
8979 | struct intel_encoder *encoder; | |
8980 | ||
8981 | list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list, | |
8982 | base.head) { | |
8983 | if (&encoder->new_crtc->base != crtc) | |
8984 | continue; | |
8985 | ||
8986 | num_encoders++; | |
8987 | if (!encoder->cloneable) | |
8988 | uncloneable_encoders = true; | |
8989 | } | |
8990 | ||
8991 | return !(num_encoders > 1 && uncloneable_encoders); | |
8992 | } | |
8993 | ||
b8cecdf5 DV |
8994 | static struct intel_crtc_config * |
8995 | intel_modeset_pipe_config(struct drm_crtc *crtc, | |
4e53c2e0 | 8996 | struct drm_framebuffer *fb, |
b8cecdf5 | 8997 | struct drm_display_mode *mode) |
ee7b9f93 | 8998 | { |
7758a113 | 8999 | struct drm_device *dev = crtc->dev; |
7758a113 | 9000 | struct intel_encoder *encoder; |
b8cecdf5 | 9001 | struct intel_crtc_config *pipe_config; |
e29c22c0 DV |
9002 | int plane_bpp, ret = -EINVAL; |
9003 | bool retry = true; | |
ee7b9f93 | 9004 | |
accfc0c5 DV |
9005 | if (!check_encoder_cloning(crtc)) { |
9006 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
9007 | return ERR_PTR(-EINVAL); | |
9008 | } | |
9009 | ||
b8cecdf5 DV |
9010 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
9011 | if (!pipe_config) | |
7758a113 DV |
9012 | return ERR_PTR(-ENOMEM); |
9013 | ||
b8cecdf5 DV |
9014 | drm_mode_copy(&pipe_config->adjusted_mode, mode); |
9015 | drm_mode_copy(&pipe_config->requested_mode, mode); | |
37327abd | 9016 | |
e143a21c DV |
9017 | pipe_config->cpu_transcoder = |
9018 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
c0d43d62 | 9019 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
b8cecdf5 | 9020 | |
2960bc9c ID |
9021 | /* |
9022 | * Sanitize sync polarity flags based on requested ones. If neither | |
9023 | * positive or negative polarity is requested, treat this as meaning | |
9024 | * negative polarity. | |
9025 | */ | |
9026 | if (!(pipe_config->adjusted_mode.flags & | |
9027 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) | |
9028 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; | |
9029 | ||
9030 | if (!(pipe_config->adjusted_mode.flags & | |
9031 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) | |
9032 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; | |
9033 | ||
050f7aeb DV |
9034 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
9035 | * plane pixel format and any sink constraints into account. Returns the | |
9036 | * source plane bpp so that dithering can be selected on mismatches | |
9037 | * after encoders and crtc also have had their say. */ | |
9038 | plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), | |
9039 | fb, pipe_config); | |
4e53c2e0 DV |
9040 | if (plane_bpp < 0) |
9041 | goto fail; | |
9042 | ||
e41a56be VS |
9043 | /* |
9044 | * Determine the real pipe dimensions. Note that stereo modes can | |
9045 | * increase the actual pipe size due to the frame doubling and | |
9046 | * insertion of additional space for blanks between the frame. This | |
9047 | * is stored in the crtc timings. We use the requested mode to do this | |
9048 | * computation to clearly distinguish it from the adjusted mode, which | |
9049 | * can be changed by the connectors in the below retry loop. | |
9050 | */ | |
9051 | drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE); | |
9052 | pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay; | |
9053 | pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay; | |
9054 | ||
e29c22c0 | 9055 | encoder_retry: |
ef1b460d | 9056 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 9057 | pipe_config->port_clock = 0; |
ef1b460d | 9058 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 9059 | |
135c81b8 | 9060 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
6ce70f5e | 9061 | drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE); |
135c81b8 | 9062 | |
7758a113 DV |
9063 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
9064 | * adjust it according to limitations or connector properties, and also | |
9065 | * a chance to reject the mode entirely. | |
47f1c6c9 | 9066 | */ |
7758a113 DV |
9067 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9068 | base.head) { | |
47f1c6c9 | 9069 | |
7758a113 DV |
9070 | if (&encoder->new_crtc->base != crtc) |
9071 | continue; | |
7ae89233 | 9072 | |
efea6e8e DV |
9073 | if (!(encoder->compute_config(encoder, pipe_config))) { |
9074 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
9075 | goto fail; |
9076 | } | |
ee7b9f93 | 9077 | } |
47f1c6c9 | 9078 | |
ff9a6750 DV |
9079 | /* Set default port clock if not overwritten by the encoder. Needs to be |
9080 | * done afterwards in case the encoder adjusts the mode. */ | |
9081 | if (!pipe_config->port_clock) | |
241bfc38 DL |
9082 | pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock |
9083 | * pipe_config->pixel_multiplier; | |
ff9a6750 | 9084 | |
a43f6e0f | 9085 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 9086 | if (ret < 0) { |
7758a113 DV |
9087 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
9088 | goto fail; | |
ee7b9f93 | 9089 | } |
e29c22c0 DV |
9090 | |
9091 | if (ret == RETRY) { | |
9092 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
9093 | ret = -EINVAL; | |
9094 | goto fail; | |
9095 | } | |
9096 | ||
9097 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
9098 | retry = false; | |
9099 | goto encoder_retry; | |
9100 | } | |
9101 | ||
4e53c2e0 DV |
9102 | pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; |
9103 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", | |
9104 | plane_bpp, pipe_config->pipe_bpp, pipe_config->dither); | |
9105 | ||
b8cecdf5 | 9106 | return pipe_config; |
7758a113 | 9107 | fail: |
b8cecdf5 | 9108 | kfree(pipe_config); |
e29c22c0 | 9109 | return ERR_PTR(ret); |
ee7b9f93 | 9110 | } |
47f1c6c9 | 9111 | |
e2e1ed41 DV |
9112 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
9113 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ | |
9114 | static void | |
9115 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, | |
9116 | unsigned *prepare_pipes, unsigned *disable_pipes) | |
79e53945 JB |
9117 | { |
9118 | struct intel_crtc *intel_crtc; | |
e2e1ed41 DV |
9119 | struct drm_device *dev = crtc->dev; |
9120 | struct intel_encoder *encoder; | |
9121 | struct intel_connector *connector; | |
9122 | struct drm_crtc *tmp_crtc; | |
79e53945 | 9123 | |
e2e1ed41 | 9124 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
79e53945 | 9125 | |
e2e1ed41 DV |
9126 | /* Check which crtcs have changed outputs connected to them, these need |
9127 | * to be part of the prepare_pipes mask. We don't (yet) support global | |
9128 | * modeset across multiple crtcs, so modeset_pipes will only have one | |
9129 | * bit set at most. */ | |
9130 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
9131 | base.head) { | |
9132 | if (connector->base.encoder == &connector->new_encoder->base) | |
9133 | continue; | |
79e53945 | 9134 | |
e2e1ed41 DV |
9135 | if (connector->base.encoder) { |
9136 | tmp_crtc = connector->base.encoder->crtc; | |
9137 | ||
9138 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
9139 | } | |
9140 | ||
9141 | if (connector->new_encoder) | |
9142 | *prepare_pipes |= | |
9143 | 1 << connector->new_encoder->new_crtc->pipe; | |
79e53945 JB |
9144 | } |
9145 | ||
e2e1ed41 DV |
9146 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9147 | base.head) { | |
9148 | if (encoder->base.crtc == &encoder->new_crtc->base) | |
9149 | continue; | |
9150 | ||
9151 | if (encoder->base.crtc) { | |
9152 | tmp_crtc = encoder->base.crtc; | |
9153 | ||
9154 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
9155 | } | |
9156 | ||
9157 | if (encoder->new_crtc) | |
9158 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; | |
80824003 JB |
9159 | } |
9160 | ||
7668851f | 9161 | /* Check for pipes that will be enabled/disabled ... */ |
e2e1ed41 DV |
9162 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
9163 | base.head) { | |
7668851f | 9164 | if (intel_crtc->base.enabled == intel_crtc->new_enabled) |
e2e1ed41 | 9165 | continue; |
7e7d76c3 | 9166 | |
7668851f | 9167 | if (!intel_crtc->new_enabled) |
e2e1ed41 | 9168 | *disable_pipes |= 1 << intel_crtc->pipe; |
7668851f VS |
9169 | else |
9170 | *prepare_pipes |= 1 << intel_crtc->pipe; | |
7e7d76c3 JB |
9171 | } |
9172 | ||
e2e1ed41 DV |
9173 | |
9174 | /* set_mode is also used to update properties on life display pipes. */ | |
9175 | intel_crtc = to_intel_crtc(crtc); | |
7668851f | 9176 | if (intel_crtc->new_enabled) |
e2e1ed41 DV |
9177 | *prepare_pipes |= 1 << intel_crtc->pipe; |
9178 | ||
b6c5164d DV |
9179 | /* |
9180 | * For simplicity do a full modeset on any pipe where the output routing | |
9181 | * changed. We could be more clever, but that would require us to be | |
9182 | * more careful with calling the relevant encoder->mode_set functions. | |
9183 | */ | |
e2e1ed41 DV |
9184 | if (*prepare_pipes) |
9185 | *modeset_pipes = *prepare_pipes; | |
9186 | ||
9187 | /* ... and mask these out. */ | |
9188 | *modeset_pipes &= ~(*disable_pipes); | |
9189 | *prepare_pipes &= ~(*disable_pipes); | |
b6c5164d DV |
9190 | |
9191 | /* | |
9192 | * HACK: We don't (yet) fully support global modesets. intel_set_config | |
9193 | * obies this rule, but the modeset restore mode of | |
9194 | * intel_modeset_setup_hw_state does not. | |
9195 | */ | |
9196 | *modeset_pipes &= 1 << intel_crtc->pipe; | |
9197 | *prepare_pipes &= 1 << intel_crtc->pipe; | |
e3641d3f DV |
9198 | |
9199 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", | |
9200 | *modeset_pipes, *prepare_pipes, *disable_pipes); | |
47f1c6c9 | 9201 | } |
79e53945 | 9202 | |
ea9d758d | 9203 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
f6e5b160 | 9204 | { |
ea9d758d | 9205 | struct drm_encoder *encoder; |
f6e5b160 | 9206 | struct drm_device *dev = crtc->dev; |
f6e5b160 | 9207 | |
ea9d758d DV |
9208 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
9209 | if (encoder->crtc == crtc) | |
9210 | return true; | |
9211 | ||
9212 | return false; | |
9213 | } | |
9214 | ||
9215 | static void | |
9216 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) | |
9217 | { | |
9218 | struct intel_encoder *intel_encoder; | |
9219 | struct intel_crtc *intel_crtc; | |
9220 | struct drm_connector *connector; | |
9221 | ||
9222 | list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list, | |
9223 | base.head) { | |
9224 | if (!intel_encoder->base.crtc) | |
9225 | continue; | |
9226 | ||
9227 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
9228 | ||
9229 | if (prepare_pipes & (1 << intel_crtc->pipe)) | |
9230 | intel_encoder->connectors_active = false; | |
9231 | } | |
9232 | ||
9233 | intel_modeset_commit_output_state(dev); | |
9234 | ||
7668851f | 9235 | /* Double check state. */ |
ea9d758d DV |
9236 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
9237 | base.head) { | |
7668851f | 9238 | WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base)); |
7bd0a8e7 VS |
9239 | WARN_ON(intel_crtc->new_config && |
9240 | intel_crtc->new_config != &intel_crtc->config); | |
9241 | WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config); | |
ea9d758d DV |
9242 | } |
9243 | ||
9244 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
9245 | if (!connector->encoder || !connector->encoder->crtc) | |
9246 | continue; | |
9247 | ||
9248 | intel_crtc = to_intel_crtc(connector->encoder->crtc); | |
9249 | ||
9250 | if (prepare_pipes & (1 << intel_crtc->pipe)) { | |
68d34720 DV |
9251 | struct drm_property *dpms_property = |
9252 | dev->mode_config.dpms_property; | |
9253 | ||
ea9d758d | 9254 | connector->dpms = DRM_MODE_DPMS_ON; |
662595df | 9255 | drm_object_property_set_value(&connector->base, |
68d34720 DV |
9256 | dpms_property, |
9257 | DRM_MODE_DPMS_ON); | |
ea9d758d DV |
9258 | |
9259 | intel_encoder = to_intel_encoder(connector->encoder); | |
9260 | intel_encoder->connectors_active = true; | |
9261 | } | |
9262 | } | |
9263 | ||
9264 | } | |
9265 | ||
3bd26263 | 9266 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 9267 | { |
3bd26263 | 9268 | int diff; |
f1f644dc JB |
9269 | |
9270 | if (clock1 == clock2) | |
9271 | return true; | |
9272 | ||
9273 | if (!clock1 || !clock2) | |
9274 | return false; | |
9275 | ||
9276 | diff = abs(clock1 - clock2); | |
9277 | ||
9278 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
9279 | return true; | |
9280 | ||
9281 | return false; | |
9282 | } | |
9283 | ||
25c5b266 DV |
9284 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
9285 | list_for_each_entry((intel_crtc), \ | |
9286 | &(dev)->mode_config.crtc_list, \ | |
9287 | base.head) \ | |
0973f18f | 9288 | if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 9289 | |
0e8ffe1b | 9290 | static bool |
2fa2fe9a DV |
9291 | intel_pipe_config_compare(struct drm_device *dev, |
9292 | struct intel_crtc_config *current_config, | |
0e8ffe1b DV |
9293 | struct intel_crtc_config *pipe_config) |
9294 | { | |
66e985c0 DV |
9295 | #define PIPE_CONF_CHECK_X(name) \ |
9296 | if (current_config->name != pipe_config->name) { \ | |
9297 | DRM_ERROR("mismatch in " #name " " \ | |
9298 | "(expected 0x%08x, found 0x%08x)\n", \ | |
9299 | current_config->name, \ | |
9300 | pipe_config->name); \ | |
9301 | return false; \ | |
9302 | } | |
9303 | ||
08a24034 DV |
9304 | #define PIPE_CONF_CHECK_I(name) \ |
9305 | if (current_config->name != pipe_config->name) { \ | |
9306 | DRM_ERROR("mismatch in " #name " " \ | |
9307 | "(expected %i, found %i)\n", \ | |
9308 | current_config->name, \ | |
9309 | pipe_config->name); \ | |
9310 | return false; \ | |
88adfff1 DV |
9311 | } |
9312 | ||
1bd1bd80 DV |
9313 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
9314 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
6f02488e | 9315 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
9316 | "(expected %i, found %i)\n", \ |
9317 | current_config->name & (mask), \ | |
9318 | pipe_config->name & (mask)); \ | |
9319 | return false; \ | |
9320 | } | |
9321 | ||
5e550656 VS |
9322 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
9323 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
9324 | DRM_ERROR("mismatch in " #name " " \ | |
9325 | "(expected %i, found %i)\n", \ | |
9326 | current_config->name, \ | |
9327 | pipe_config->name); \ | |
9328 | return false; \ | |
9329 | } | |
9330 | ||
bb760063 DV |
9331 | #define PIPE_CONF_QUIRK(quirk) \ |
9332 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
9333 | ||
eccb140b DV |
9334 | PIPE_CONF_CHECK_I(cpu_transcoder); |
9335 | ||
08a24034 DV |
9336 | PIPE_CONF_CHECK_I(has_pch_encoder); |
9337 | PIPE_CONF_CHECK_I(fdi_lanes); | |
72419203 DV |
9338 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
9339 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); | |
9340 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); | |
9341 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); | |
9342 | PIPE_CONF_CHECK_I(fdi_m_n.tu); | |
08a24034 | 9343 | |
eb14cb74 VS |
9344 | PIPE_CONF_CHECK_I(has_dp_encoder); |
9345 | PIPE_CONF_CHECK_I(dp_m_n.gmch_m); | |
9346 | PIPE_CONF_CHECK_I(dp_m_n.gmch_n); | |
9347 | PIPE_CONF_CHECK_I(dp_m_n.link_m); | |
9348 | PIPE_CONF_CHECK_I(dp_m_n.link_n); | |
9349 | PIPE_CONF_CHECK_I(dp_m_n.tu); | |
9350 | ||
1bd1bd80 DV |
9351 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay); |
9352 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal); | |
9353 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start); | |
9354 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end); | |
9355 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start); | |
9356 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end); | |
9357 | ||
9358 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay); | |
9359 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal); | |
9360 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start); | |
9361 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end); | |
9362 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start); | |
9363 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end); | |
9364 | ||
c93f54cf | 9365 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6c49f241 | 9366 | |
1bd1bd80 DV |
9367 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
9368 | DRM_MODE_FLAG_INTERLACE); | |
9369 | ||
bb760063 DV |
9370 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
9371 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
9372 | DRM_MODE_FLAG_PHSYNC); | |
9373 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
9374 | DRM_MODE_FLAG_NHSYNC); | |
9375 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
9376 | DRM_MODE_FLAG_PVSYNC); | |
9377 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
9378 | DRM_MODE_FLAG_NVSYNC); | |
9379 | } | |
045ac3b5 | 9380 | |
37327abd VS |
9381 | PIPE_CONF_CHECK_I(pipe_src_w); |
9382 | PIPE_CONF_CHECK_I(pipe_src_h); | |
1bd1bd80 | 9383 | |
2fa2fe9a DV |
9384 | PIPE_CONF_CHECK_I(gmch_pfit.control); |
9385 | /* pfit ratios are autocomputed by the hw on gen4+ */ | |
9386 | if (INTEL_INFO(dev)->gen < 4) | |
9387 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
9388 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); | |
fd4daa9c CW |
9389 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
9390 | if (current_config->pch_pfit.enabled) { | |
9391 | PIPE_CONF_CHECK_I(pch_pfit.pos); | |
9392 | PIPE_CONF_CHECK_I(pch_pfit.size); | |
9393 | } | |
2fa2fe9a | 9394 | |
e59150dc JB |
9395 | /* BDW+ don't expose a synchronous way to read the state */ |
9396 | if (IS_HASWELL(dev)) | |
9397 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 9398 | |
282740f7 VS |
9399 | PIPE_CONF_CHECK_I(double_wide); |
9400 | ||
c0d43d62 | 9401 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 9402 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 9403 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
9404 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
9405 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
c0d43d62 | 9406 | |
42571aef VS |
9407 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
9408 | PIPE_CONF_CHECK_I(pipe_bpp); | |
9409 | ||
a9a7e98a JB |
9410 | PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock); |
9411 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); | |
5e550656 | 9412 | |
66e985c0 | 9413 | #undef PIPE_CONF_CHECK_X |
08a24034 | 9414 | #undef PIPE_CONF_CHECK_I |
1bd1bd80 | 9415 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 9416 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 9417 | #undef PIPE_CONF_QUIRK |
88adfff1 | 9418 | |
0e8ffe1b DV |
9419 | return true; |
9420 | } | |
9421 | ||
91d1b4bd DV |
9422 | static void |
9423 | check_connector_state(struct drm_device *dev) | |
8af6cf88 | 9424 | { |
8af6cf88 DV |
9425 | struct intel_connector *connector; |
9426 | ||
9427 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
9428 | base.head) { | |
9429 | /* This also checks the encoder/connector hw state with the | |
9430 | * ->get_hw_state callbacks. */ | |
9431 | intel_connector_check_state(connector); | |
9432 | ||
9433 | WARN(&connector->new_encoder->base != connector->base.encoder, | |
9434 | "connector's staged encoder doesn't match current encoder\n"); | |
9435 | } | |
91d1b4bd DV |
9436 | } |
9437 | ||
9438 | static void | |
9439 | check_encoder_state(struct drm_device *dev) | |
9440 | { | |
9441 | struct intel_encoder *encoder; | |
9442 | struct intel_connector *connector; | |
8af6cf88 DV |
9443 | |
9444 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
9445 | base.head) { | |
9446 | bool enabled = false; | |
9447 | bool active = false; | |
9448 | enum pipe pipe, tracked_pipe; | |
9449 | ||
9450 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
9451 | encoder->base.base.id, | |
9452 | drm_get_encoder_name(&encoder->base)); | |
9453 | ||
9454 | WARN(&encoder->new_crtc->base != encoder->base.crtc, | |
9455 | "encoder's stage crtc doesn't match current crtc\n"); | |
9456 | WARN(encoder->connectors_active && !encoder->base.crtc, | |
9457 | "encoder's active_connectors set, but no crtc\n"); | |
9458 | ||
9459 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
9460 | base.head) { | |
9461 | if (connector->base.encoder != &encoder->base) | |
9462 | continue; | |
9463 | enabled = true; | |
9464 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) | |
9465 | active = true; | |
9466 | } | |
9467 | WARN(!!encoder->base.crtc != enabled, | |
9468 | "encoder's enabled state mismatch " | |
9469 | "(expected %i, found %i)\n", | |
9470 | !!encoder->base.crtc, enabled); | |
9471 | WARN(active && !encoder->base.crtc, | |
9472 | "active encoder with no crtc\n"); | |
9473 | ||
9474 | WARN(encoder->connectors_active != active, | |
9475 | "encoder's computed active state doesn't match tracked active state " | |
9476 | "(expected %i, found %i)\n", active, encoder->connectors_active); | |
9477 | ||
9478 | active = encoder->get_hw_state(encoder, &pipe); | |
9479 | WARN(active != encoder->connectors_active, | |
9480 | "encoder's hw state doesn't match sw tracking " | |
9481 | "(expected %i, found %i)\n", | |
9482 | encoder->connectors_active, active); | |
9483 | ||
9484 | if (!encoder->base.crtc) | |
9485 | continue; | |
9486 | ||
9487 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
9488 | WARN(active && pipe != tracked_pipe, | |
9489 | "active encoder's pipe doesn't match" | |
9490 | "(expected %i, found %i)\n", | |
9491 | tracked_pipe, pipe); | |
9492 | ||
9493 | } | |
91d1b4bd DV |
9494 | } |
9495 | ||
9496 | static void | |
9497 | check_crtc_state(struct drm_device *dev) | |
9498 | { | |
9499 | drm_i915_private_t *dev_priv = dev->dev_private; | |
9500 | struct intel_crtc *crtc; | |
9501 | struct intel_encoder *encoder; | |
9502 | struct intel_crtc_config pipe_config; | |
8af6cf88 DV |
9503 | |
9504 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
9505 | base.head) { | |
9506 | bool enabled = false; | |
9507 | bool active = false; | |
9508 | ||
045ac3b5 JB |
9509 | memset(&pipe_config, 0, sizeof(pipe_config)); |
9510 | ||
8af6cf88 DV |
9511 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
9512 | crtc->base.base.id); | |
9513 | ||
9514 | WARN(crtc->active && !crtc->base.enabled, | |
9515 | "active crtc, but not enabled in sw tracking\n"); | |
9516 | ||
9517 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
9518 | base.head) { | |
9519 | if (encoder->base.crtc != &crtc->base) | |
9520 | continue; | |
9521 | enabled = true; | |
9522 | if (encoder->connectors_active) | |
9523 | active = true; | |
9524 | } | |
6c49f241 | 9525 | |
8af6cf88 DV |
9526 | WARN(active != crtc->active, |
9527 | "crtc's computed active state doesn't match tracked active state " | |
9528 | "(expected %i, found %i)\n", active, crtc->active); | |
9529 | WARN(enabled != crtc->base.enabled, | |
9530 | "crtc's computed enabled state doesn't match tracked enabled state " | |
9531 | "(expected %i, found %i)\n", enabled, crtc->base.enabled); | |
9532 | ||
0e8ffe1b DV |
9533 | active = dev_priv->display.get_pipe_config(crtc, |
9534 | &pipe_config); | |
d62cf62a DV |
9535 | |
9536 | /* hw state is inconsistent with the pipe A quirk */ | |
9537 | if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
9538 | active = crtc->active; | |
9539 | ||
6c49f241 DV |
9540 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9541 | base.head) { | |
3eaba51c | 9542 | enum pipe pipe; |
6c49f241 DV |
9543 | if (encoder->base.crtc != &crtc->base) |
9544 | continue; | |
1d37b689 | 9545 | if (encoder->get_hw_state(encoder, &pipe)) |
6c49f241 DV |
9546 | encoder->get_config(encoder, &pipe_config); |
9547 | } | |
9548 | ||
0e8ffe1b DV |
9549 | WARN(crtc->active != active, |
9550 | "crtc active state doesn't match with hw state " | |
9551 | "(expected %i, found %i)\n", crtc->active, active); | |
9552 | ||
c0b03411 DV |
9553 | if (active && |
9554 | !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) { | |
9555 | WARN(1, "pipe state doesn't match!\n"); | |
9556 | intel_dump_pipe_config(crtc, &pipe_config, | |
9557 | "[hw state]"); | |
9558 | intel_dump_pipe_config(crtc, &crtc->config, | |
9559 | "[sw state]"); | |
9560 | } | |
8af6cf88 DV |
9561 | } |
9562 | } | |
9563 | ||
91d1b4bd DV |
9564 | static void |
9565 | check_shared_dpll_state(struct drm_device *dev) | |
9566 | { | |
9567 | drm_i915_private_t *dev_priv = dev->dev_private; | |
9568 | struct intel_crtc *crtc; | |
9569 | struct intel_dpll_hw_state dpll_hw_state; | |
9570 | int i; | |
5358901f DV |
9571 | |
9572 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
9573 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
9574 | int enabled_crtcs = 0, active_crtcs = 0; | |
9575 | bool active; | |
9576 | ||
9577 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
9578 | ||
9579 | DRM_DEBUG_KMS("%s\n", pll->name); | |
9580 | ||
9581 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
9582 | ||
9583 | WARN(pll->active > pll->refcount, | |
9584 | "more active pll users than references: %i vs %i\n", | |
9585 | pll->active, pll->refcount); | |
9586 | WARN(pll->active && !pll->on, | |
9587 | "pll in active use but not on in sw tracking\n"); | |
35c95375 DV |
9588 | WARN(pll->on && !pll->active, |
9589 | "pll in on but not on in use in sw tracking\n"); | |
5358901f DV |
9590 | WARN(pll->on != active, |
9591 | "pll on state mismatch (expected %i, found %i)\n", | |
9592 | pll->on, active); | |
9593 | ||
9594 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
9595 | base.head) { | |
9596 | if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll) | |
9597 | enabled_crtcs++; | |
9598 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
9599 | active_crtcs++; | |
9600 | } | |
9601 | WARN(pll->active != active_crtcs, | |
9602 | "pll active crtcs mismatch (expected %i, found %i)\n", | |
9603 | pll->active, active_crtcs); | |
9604 | WARN(pll->refcount != enabled_crtcs, | |
9605 | "pll enabled crtcs mismatch (expected %i, found %i)\n", | |
9606 | pll->refcount, enabled_crtcs); | |
66e985c0 DV |
9607 | |
9608 | WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state, | |
9609 | sizeof(dpll_hw_state)), | |
9610 | "pll hw state mismatch\n"); | |
5358901f | 9611 | } |
8af6cf88 DV |
9612 | } |
9613 | ||
91d1b4bd DV |
9614 | void |
9615 | intel_modeset_check_state(struct drm_device *dev) | |
9616 | { | |
9617 | check_connector_state(dev); | |
9618 | check_encoder_state(dev); | |
9619 | check_crtc_state(dev); | |
9620 | check_shared_dpll_state(dev); | |
9621 | } | |
9622 | ||
18442d08 VS |
9623 | void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, |
9624 | int dotclock) | |
9625 | { | |
9626 | /* | |
9627 | * FDI already provided one idea for the dotclock. | |
9628 | * Yell if the encoder disagrees. | |
9629 | */ | |
241bfc38 | 9630 | WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock), |
18442d08 | 9631 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
241bfc38 | 9632 | pipe_config->adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
9633 | } |
9634 | ||
f30da187 DV |
9635 | static int __intel_set_mode(struct drm_crtc *crtc, |
9636 | struct drm_display_mode *mode, | |
9637 | int x, int y, struct drm_framebuffer *fb) | |
a6778b3c DV |
9638 | { |
9639 | struct drm_device *dev = crtc->dev; | |
dbf2b54e | 9640 | drm_i915_private_t *dev_priv = dev->dev_private; |
4b4b9238 | 9641 | struct drm_display_mode *saved_mode; |
b8cecdf5 | 9642 | struct intel_crtc_config *pipe_config = NULL; |
25c5b266 DV |
9643 | struct intel_crtc *intel_crtc; |
9644 | unsigned disable_pipes, prepare_pipes, modeset_pipes; | |
c0c36b94 | 9645 | int ret = 0; |
a6778b3c | 9646 | |
4b4b9238 | 9647 | saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL); |
c0c36b94 CW |
9648 | if (!saved_mode) |
9649 | return -ENOMEM; | |
a6778b3c | 9650 | |
e2e1ed41 | 9651 | intel_modeset_affected_pipes(crtc, &modeset_pipes, |
25c5b266 DV |
9652 | &prepare_pipes, &disable_pipes); |
9653 | ||
3ac18232 | 9654 | *saved_mode = crtc->mode; |
a6778b3c | 9655 | |
25c5b266 DV |
9656 | /* Hack: Because we don't (yet) support global modeset on multiple |
9657 | * crtcs, we don't keep track of the new mode for more than one crtc. | |
9658 | * Hence simply check whether any bit is set in modeset_pipes in all the | |
9659 | * pieces of code that are not yet converted to deal with mutliple crtcs | |
9660 | * changing their mode at the same time. */ | |
25c5b266 | 9661 | if (modeset_pipes) { |
4e53c2e0 | 9662 | pipe_config = intel_modeset_pipe_config(crtc, fb, mode); |
b8cecdf5 DV |
9663 | if (IS_ERR(pipe_config)) { |
9664 | ret = PTR_ERR(pipe_config); | |
9665 | pipe_config = NULL; | |
9666 | ||
3ac18232 | 9667 | goto out; |
25c5b266 | 9668 | } |
c0b03411 DV |
9669 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
9670 | "[modeset]"); | |
50741abc | 9671 | to_intel_crtc(crtc)->new_config = pipe_config; |
25c5b266 | 9672 | } |
a6778b3c | 9673 | |
30a970c6 JB |
9674 | /* |
9675 | * See if the config requires any additional preparation, e.g. | |
9676 | * to adjust global state with pipes off. We need to do this | |
9677 | * here so we can get the modeset_pipe updated config for the new | |
9678 | * mode set on this crtc. For other crtcs we need to use the | |
9679 | * adjusted_mode bits in the crtc directly. | |
9680 | */ | |
c164f833 | 9681 | if (IS_VALLEYVIEW(dev)) { |
2f2d7aa1 | 9682 | valleyview_modeset_global_pipes(dev, &prepare_pipes); |
30a970c6 | 9683 | |
c164f833 VS |
9684 | /* may have added more to prepare_pipes than we should */ |
9685 | prepare_pipes &= ~disable_pipes; | |
9686 | } | |
9687 | ||
460da916 DV |
9688 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
9689 | intel_crtc_disable(&intel_crtc->base); | |
9690 | ||
ea9d758d DV |
9691 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
9692 | if (intel_crtc->base.enabled) | |
9693 | dev_priv->display.crtc_disable(&intel_crtc->base); | |
9694 | } | |
a6778b3c | 9695 | |
6c4c86f5 DV |
9696 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
9697 | * to set it here already despite that we pass it down the callchain. | |
f6e5b160 | 9698 | */ |
b8cecdf5 | 9699 | if (modeset_pipes) { |
25c5b266 | 9700 | crtc->mode = *mode; |
b8cecdf5 DV |
9701 | /* mode_set/enable/disable functions rely on a correct pipe |
9702 | * config. */ | |
9703 | to_intel_crtc(crtc)->config = *pipe_config; | |
50741abc | 9704 | to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config; |
c326c0a9 VS |
9705 | |
9706 | /* | |
9707 | * Calculate and store various constants which | |
9708 | * are later needed by vblank and swap-completion | |
9709 | * timestamping. They are derived from true hwmode. | |
9710 | */ | |
9711 | drm_calc_timestamping_constants(crtc, | |
9712 | &pipe_config->adjusted_mode); | |
b8cecdf5 | 9713 | } |
7758a113 | 9714 | |
ea9d758d DV |
9715 | /* Only after disabling all output pipelines that will be changed can we |
9716 | * update the the output configuration. */ | |
9717 | intel_modeset_update_state(dev, prepare_pipes); | |
f6e5b160 | 9718 | |
47fab737 DV |
9719 | if (dev_priv->display.modeset_global_resources) |
9720 | dev_priv->display.modeset_global_resources(dev); | |
9721 | ||
a6778b3c DV |
9722 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
9723 | * on the DPLL. | |
f6e5b160 | 9724 | */ |
25c5b266 | 9725 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
c0c36b94 | 9726 | ret = intel_crtc_mode_set(&intel_crtc->base, |
c0c36b94 CW |
9727 | x, y, fb); |
9728 | if (ret) | |
9729 | goto done; | |
a6778b3c DV |
9730 | } |
9731 | ||
9732 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ | |
25c5b266 DV |
9733 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) |
9734 | dev_priv->display.crtc_enable(&intel_crtc->base); | |
a6778b3c | 9735 | |
a6778b3c DV |
9736 | /* FIXME: add subpixel order */ |
9737 | done: | |
4b4b9238 | 9738 | if (ret && crtc->enabled) |
3ac18232 | 9739 | crtc->mode = *saved_mode; |
a6778b3c | 9740 | |
3ac18232 | 9741 | out: |
b8cecdf5 | 9742 | kfree(pipe_config); |
3ac18232 | 9743 | kfree(saved_mode); |
a6778b3c | 9744 | return ret; |
f6e5b160 CW |
9745 | } |
9746 | ||
e7457a9a DL |
9747 | static int intel_set_mode(struct drm_crtc *crtc, |
9748 | struct drm_display_mode *mode, | |
9749 | int x, int y, struct drm_framebuffer *fb) | |
f30da187 DV |
9750 | { |
9751 | int ret; | |
9752 | ||
9753 | ret = __intel_set_mode(crtc, mode, x, y, fb); | |
9754 | ||
9755 | if (ret == 0) | |
9756 | intel_modeset_check_state(crtc->dev); | |
9757 | ||
9758 | return ret; | |
9759 | } | |
9760 | ||
c0c36b94 CW |
9761 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
9762 | { | |
9763 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb); | |
9764 | } | |
9765 | ||
25c5b266 DV |
9766 | #undef for_each_intel_crtc_masked |
9767 | ||
d9e55608 DV |
9768 | static void intel_set_config_free(struct intel_set_config *config) |
9769 | { | |
9770 | if (!config) | |
9771 | return; | |
9772 | ||
1aa4b628 DV |
9773 | kfree(config->save_connector_encoders); |
9774 | kfree(config->save_encoder_crtcs); | |
7668851f | 9775 | kfree(config->save_crtc_enabled); |
d9e55608 DV |
9776 | kfree(config); |
9777 | } | |
9778 | ||
85f9eb71 DV |
9779 | static int intel_set_config_save_state(struct drm_device *dev, |
9780 | struct intel_set_config *config) | |
9781 | { | |
7668851f | 9782 | struct drm_crtc *crtc; |
85f9eb71 DV |
9783 | struct drm_encoder *encoder; |
9784 | struct drm_connector *connector; | |
9785 | int count; | |
9786 | ||
7668851f VS |
9787 | config->save_crtc_enabled = |
9788 | kcalloc(dev->mode_config.num_crtc, | |
9789 | sizeof(bool), GFP_KERNEL); | |
9790 | if (!config->save_crtc_enabled) | |
9791 | return -ENOMEM; | |
9792 | ||
1aa4b628 DV |
9793 | config->save_encoder_crtcs = |
9794 | kcalloc(dev->mode_config.num_encoder, | |
9795 | sizeof(struct drm_crtc *), GFP_KERNEL); | |
9796 | if (!config->save_encoder_crtcs) | |
85f9eb71 DV |
9797 | return -ENOMEM; |
9798 | ||
1aa4b628 DV |
9799 | config->save_connector_encoders = |
9800 | kcalloc(dev->mode_config.num_connector, | |
9801 | sizeof(struct drm_encoder *), GFP_KERNEL); | |
9802 | if (!config->save_connector_encoders) | |
85f9eb71 DV |
9803 | return -ENOMEM; |
9804 | ||
9805 | /* Copy data. Note that driver private data is not affected. | |
9806 | * Should anything bad happen only the expected state is | |
9807 | * restored, not the drivers personal bookkeeping. | |
9808 | */ | |
7668851f VS |
9809 | count = 0; |
9810 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
9811 | config->save_crtc_enabled[count++] = crtc->enabled; | |
9812 | } | |
9813 | ||
85f9eb71 DV |
9814 | count = 0; |
9815 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1aa4b628 | 9816 | config->save_encoder_crtcs[count++] = encoder->crtc; |
85f9eb71 DV |
9817 | } |
9818 | ||
9819 | count = 0; | |
9820 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1aa4b628 | 9821 | config->save_connector_encoders[count++] = connector->encoder; |
85f9eb71 DV |
9822 | } |
9823 | ||
9824 | return 0; | |
9825 | } | |
9826 | ||
9827 | static void intel_set_config_restore_state(struct drm_device *dev, | |
9828 | struct intel_set_config *config) | |
9829 | { | |
7668851f | 9830 | struct intel_crtc *crtc; |
9a935856 DV |
9831 | struct intel_encoder *encoder; |
9832 | struct intel_connector *connector; | |
85f9eb71 DV |
9833 | int count; |
9834 | ||
7668851f VS |
9835 | count = 0; |
9836 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
9837 | crtc->new_enabled = config->save_crtc_enabled[count++]; | |
7bd0a8e7 VS |
9838 | |
9839 | if (crtc->new_enabled) | |
9840 | crtc->new_config = &crtc->config; | |
9841 | else | |
9842 | crtc->new_config = NULL; | |
7668851f VS |
9843 | } |
9844 | ||
85f9eb71 | 9845 | count = 0; |
9a935856 DV |
9846 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
9847 | encoder->new_crtc = | |
9848 | to_intel_crtc(config->save_encoder_crtcs[count++]); | |
85f9eb71 DV |
9849 | } |
9850 | ||
9851 | count = 0; | |
9a935856 DV |
9852 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
9853 | connector->new_encoder = | |
9854 | to_intel_encoder(config->save_connector_encoders[count++]); | |
85f9eb71 DV |
9855 | } |
9856 | } | |
9857 | ||
e3de42b6 | 9858 | static bool |
2e57f47d | 9859 | is_crtc_connector_off(struct drm_mode_set *set) |
e3de42b6 ID |
9860 | { |
9861 | int i; | |
9862 | ||
2e57f47d CW |
9863 | if (set->num_connectors == 0) |
9864 | return false; | |
9865 | ||
9866 | if (WARN_ON(set->connectors == NULL)) | |
9867 | return false; | |
9868 | ||
9869 | for (i = 0; i < set->num_connectors; i++) | |
9870 | if (set->connectors[i]->encoder && | |
9871 | set->connectors[i]->encoder->crtc == set->crtc && | |
9872 | set->connectors[i]->dpms != DRM_MODE_DPMS_ON) | |
e3de42b6 ID |
9873 | return true; |
9874 | ||
9875 | return false; | |
9876 | } | |
9877 | ||
5e2b584e DV |
9878 | static void |
9879 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, | |
9880 | struct intel_set_config *config) | |
9881 | { | |
9882 | ||
9883 | /* We should be able to check here if the fb has the same properties | |
9884 | * and then just flip_or_move it */ | |
2e57f47d CW |
9885 | if (is_crtc_connector_off(set)) { |
9886 | config->mode_changed = true; | |
e3de42b6 | 9887 | } else if (set->crtc->fb != set->fb) { |
5e2b584e DV |
9888 | /* If we have no fb then treat it as a full mode set */ |
9889 | if (set->crtc->fb == NULL) { | |
319d9827 JB |
9890 | struct intel_crtc *intel_crtc = |
9891 | to_intel_crtc(set->crtc); | |
9892 | ||
d330a953 | 9893 | if (intel_crtc->active && i915.fastboot) { |
319d9827 JB |
9894 | DRM_DEBUG_KMS("crtc has no fb, will flip\n"); |
9895 | config->fb_changed = true; | |
9896 | } else { | |
9897 | DRM_DEBUG_KMS("inactive crtc, full mode set\n"); | |
9898 | config->mode_changed = true; | |
9899 | } | |
5e2b584e DV |
9900 | } else if (set->fb == NULL) { |
9901 | config->mode_changed = true; | |
72f4901e DV |
9902 | } else if (set->fb->pixel_format != |
9903 | set->crtc->fb->pixel_format) { | |
5e2b584e | 9904 | config->mode_changed = true; |
e3de42b6 | 9905 | } else { |
5e2b584e | 9906 | config->fb_changed = true; |
e3de42b6 | 9907 | } |
5e2b584e DV |
9908 | } |
9909 | ||
835c5873 | 9910 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
5e2b584e DV |
9911 | config->fb_changed = true; |
9912 | ||
9913 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { | |
9914 | DRM_DEBUG_KMS("modes are different, full mode set\n"); | |
9915 | drm_mode_debug_printmodeline(&set->crtc->mode); | |
9916 | drm_mode_debug_printmodeline(set->mode); | |
9917 | config->mode_changed = true; | |
9918 | } | |
a1d95703 CW |
9919 | |
9920 | DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n", | |
9921 | set->crtc->base.id, config->mode_changed, config->fb_changed); | |
5e2b584e DV |
9922 | } |
9923 | ||
2e431051 | 9924 | static int |
9a935856 DV |
9925 | intel_modeset_stage_output_state(struct drm_device *dev, |
9926 | struct drm_mode_set *set, | |
9927 | struct intel_set_config *config) | |
50f56119 | 9928 | { |
9a935856 DV |
9929 | struct intel_connector *connector; |
9930 | struct intel_encoder *encoder; | |
7668851f | 9931 | struct intel_crtc *crtc; |
f3f08572 | 9932 | int ro; |
50f56119 | 9933 | |
9abdda74 | 9934 | /* The upper layers ensure that we either disable a crtc or have a list |
9a935856 DV |
9935 | * of connectors. For paranoia, double-check this. */ |
9936 | WARN_ON(!set->fb && (set->num_connectors != 0)); | |
9937 | WARN_ON(set->fb && (set->num_connectors == 0)); | |
9938 | ||
9a935856 DV |
9939 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9940 | base.head) { | |
9941 | /* Otherwise traverse passed in connector list and get encoders | |
9942 | * for them. */ | |
50f56119 | 9943 | for (ro = 0; ro < set->num_connectors; ro++) { |
9a935856 DV |
9944 | if (set->connectors[ro] == &connector->base) { |
9945 | connector->new_encoder = connector->encoder; | |
50f56119 DV |
9946 | break; |
9947 | } | |
9948 | } | |
9949 | ||
9a935856 DV |
9950 | /* If we disable the crtc, disable all its connectors. Also, if |
9951 | * the connector is on the changing crtc but not on the new | |
9952 | * connector list, disable it. */ | |
9953 | if ((!set->fb || ro == set->num_connectors) && | |
9954 | connector->base.encoder && | |
9955 | connector->base.encoder->crtc == set->crtc) { | |
9956 | connector->new_encoder = NULL; | |
9957 | ||
9958 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", | |
9959 | connector->base.base.id, | |
9960 | drm_get_connector_name(&connector->base)); | |
9961 | } | |
9962 | ||
9963 | ||
9964 | if (&connector->new_encoder->base != connector->base.encoder) { | |
50f56119 | 9965 | DRM_DEBUG_KMS("encoder changed, full mode switch\n"); |
5e2b584e | 9966 | config->mode_changed = true; |
50f56119 DV |
9967 | } |
9968 | } | |
9a935856 | 9969 | /* connector->new_encoder is now updated for all connectors. */ |
50f56119 | 9970 | |
9a935856 | 9971 | /* Update crtc of enabled connectors. */ |
9a935856 DV |
9972 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9973 | base.head) { | |
7668851f VS |
9974 | struct drm_crtc *new_crtc; |
9975 | ||
9a935856 | 9976 | if (!connector->new_encoder) |
50f56119 DV |
9977 | continue; |
9978 | ||
9a935856 | 9979 | new_crtc = connector->new_encoder->base.crtc; |
50f56119 DV |
9980 | |
9981 | for (ro = 0; ro < set->num_connectors; ro++) { | |
9a935856 | 9982 | if (set->connectors[ro] == &connector->base) |
50f56119 DV |
9983 | new_crtc = set->crtc; |
9984 | } | |
9985 | ||
9986 | /* Make sure the new CRTC will work with the encoder */ | |
14509916 TR |
9987 | if (!drm_encoder_crtc_ok(&connector->new_encoder->base, |
9988 | new_crtc)) { | |
5e2b584e | 9989 | return -EINVAL; |
50f56119 | 9990 | } |
9a935856 DV |
9991 | connector->encoder->new_crtc = to_intel_crtc(new_crtc); |
9992 | ||
9993 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", | |
9994 | connector->base.base.id, | |
9995 | drm_get_connector_name(&connector->base), | |
9996 | new_crtc->base.id); | |
9997 | } | |
9998 | ||
9999 | /* Check for any encoders that needs to be disabled. */ | |
10000 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
10001 | base.head) { | |
5a65f358 | 10002 | int num_connectors = 0; |
9a935856 DV |
10003 | list_for_each_entry(connector, |
10004 | &dev->mode_config.connector_list, | |
10005 | base.head) { | |
10006 | if (connector->new_encoder == encoder) { | |
10007 | WARN_ON(!connector->new_encoder->new_crtc); | |
5a65f358 | 10008 | num_connectors++; |
9a935856 DV |
10009 | } |
10010 | } | |
5a65f358 PZ |
10011 | |
10012 | if (num_connectors == 0) | |
10013 | encoder->new_crtc = NULL; | |
10014 | else if (num_connectors > 1) | |
10015 | return -EINVAL; | |
10016 | ||
9a935856 DV |
10017 | /* Only now check for crtc changes so we don't miss encoders |
10018 | * that will be disabled. */ | |
10019 | if (&encoder->new_crtc->base != encoder->base.crtc) { | |
50f56119 | 10020 | DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
5e2b584e | 10021 | config->mode_changed = true; |
50f56119 DV |
10022 | } |
10023 | } | |
9a935856 | 10024 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
50f56119 | 10025 | |
7668851f VS |
10026 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
10027 | base.head) { | |
10028 | crtc->new_enabled = false; | |
10029 | ||
10030 | list_for_each_entry(encoder, | |
10031 | &dev->mode_config.encoder_list, | |
10032 | base.head) { | |
10033 | if (encoder->new_crtc == crtc) { | |
10034 | crtc->new_enabled = true; | |
10035 | break; | |
10036 | } | |
10037 | } | |
10038 | ||
10039 | if (crtc->new_enabled != crtc->base.enabled) { | |
10040 | DRM_DEBUG_KMS("crtc %sabled, full mode switch\n", | |
10041 | crtc->new_enabled ? "en" : "dis"); | |
10042 | config->mode_changed = true; | |
10043 | } | |
7bd0a8e7 VS |
10044 | |
10045 | if (crtc->new_enabled) | |
10046 | crtc->new_config = &crtc->config; | |
10047 | else | |
10048 | crtc->new_config = NULL; | |
7668851f VS |
10049 | } |
10050 | ||
2e431051 DV |
10051 | return 0; |
10052 | } | |
10053 | ||
7d00a1f5 VS |
10054 | static void disable_crtc_nofb(struct intel_crtc *crtc) |
10055 | { | |
10056 | struct drm_device *dev = crtc->base.dev; | |
10057 | struct intel_encoder *encoder; | |
10058 | struct intel_connector *connector; | |
10059 | ||
10060 | DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n", | |
10061 | pipe_name(crtc->pipe)); | |
10062 | ||
10063 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { | |
10064 | if (connector->new_encoder && | |
10065 | connector->new_encoder->new_crtc == crtc) | |
10066 | connector->new_encoder = NULL; | |
10067 | } | |
10068 | ||
10069 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { | |
10070 | if (encoder->new_crtc == crtc) | |
10071 | encoder->new_crtc = NULL; | |
10072 | } | |
10073 | ||
10074 | crtc->new_enabled = false; | |
7bd0a8e7 | 10075 | crtc->new_config = NULL; |
7d00a1f5 VS |
10076 | } |
10077 | ||
2e431051 DV |
10078 | static int intel_crtc_set_config(struct drm_mode_set *set) |
10079 | { | |
10080 | struct drm_device *dev; | |
2e431051 DV |
10081 | struct drm_mode_set save_set; |
10082 | struct intel_set_config *config; | |
10083 | int ret; | |
2e431051 | 10084 | |
8d3e375e DV |
10085 | BUG_ON(!set); |
10086 | BUG_ON(!set->crtc); | |
10087 | BUG_ON(!set->crtc->helper_private); | |
2e431051 | 10088 | |
7e53f3a4 DV |
10089 | /* Enforce sane interface api - has been abused by the fb helper. */ |
10090 | BUG_ON(!set->mode && set->fb); | |
10091 | BUG_ON(set->fb && set->num_connectors == 0); | |
431e50f7 | 10092 | |
2e431051 DV |
10093 | if (set->fb) { |
10094 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", | |
10095 | set->crtc->base.id, set->fb->base.id, | |
10096 | (int)set->num_connectors, set->x, set->y); | |
10097 | } else { | |
10098 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); | |
2e431051 DV |
10099 | } |
10100 | ||
10101 | dev = set->crtc->dev; | |
10102 | ||
10103 | ret = -ENOMEM; | |
10104 | config = kzalloc(sizeof(*config), GFP_KERNEL); | |
10105 | if (!config) | |
10106 | goto out_config; | |
10107 | ||
10108 | ret = intel_set_config_save_state(dev, config); | |
10109 | if (ret) | |
10110 | goto out_config; | |
10111 | ||
10112 | save_set.crtc = set->crtc; | |
10113 | save_set.mode = &set->crtc->mode; | |
10114 | save_set.x = set->crtc->x; | |
10115 | save_set.y = set->crtc->y; | |
10116 | save_set.fb = set->crtc->fb; | |
10117 | ||
10118 | /* Compute whether we need a full modeset, only an fb base update or no | |
10119 | * change at all. In the future we might also check whether only the | |
10120 | * mode changed, e.g. for LVDS where we only change the panel fitter in | |
10121 | * such cases. */ | |
10122 | intel_set_config_compute_mode_changes(set, config); | |
10123 | ||
9a935856 | 10124 | ret = intel_modeset_stage_output_state(dev, set, config); |
2e431051 DV |
10125 | if (ret) |
10126 | goto fail; | |
10127 | ||
5e2b584e | 10128 | if (config->mode_changed) { |
c0c36b94 CW |
10129 | ret = intel_set_mode(set->crtc, set->mode, |
10130 | set->x, set->y, set->fb); | |
5e2b584e | 10131 | } else if (config->fb_changed) { |
4878cae2 VS |
10132 | intel_crtc_wait_for_pending_flips(set->crtc); |
10133 | ||
4f660f49 | 10134 | ret = intel_pipe_set_base(set->crtc, |
94352cf9 | 10135 | set->x, set->y, set->fb); |
7ca51a3a JB |
10136 | /* |
10137 | * In the fastboot case this may be our only check of the | |
10138 | * state after boot. It would be better to only do it on | |
10139 | * the first update, but we don't have a nice way of doing that | |
10140 | * (and really, set_config isn't used much for high freq page | |
10141 | * flipping, so increasing its cost here shouldn't be a big | |
10142 | * deal). | |
10143 | */ | |
d330a953 | 10144 | if (i915.fastboot && ret == 0) |
7ca51a3a | 10145 | intel_modeset_check_state(set->crtc->dev); |
50f56119 DV |
10146 | } |
10147 | ||
2d05eae1 | 10148 | if (ret) { |
bf67dfeb DV |
10149 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
10150 | set->crtc->base.id, ret); | |
50f56119 | 10151 | fail: |
2d05eae1 | 10152 | intel_set_config_restore_state(dev, config); |
50f56119 | 10153 | |
7d00a1f5 VS |
10154 | /* |
10155 | * HACK: if the pipe was on, but we didn't have a framebuffer, | |
10156 | * force the pipe off to avoid oopsing in the modeset code | |
10157 | * due to fb==NULL. This should only happen during boot since | |
10158 | * we don't yet reconstruct the FB from the hardware state. | |
10159 | */ | |
10160 | if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb) | |
10161 | disable_crtc_nofb(to_intel_crtc(save_set.crtc)); | |
10162 | ||
2d05eae1 CW |
10163 | /* Try to restore the config */ |
10164 | if (config->mode_changed && | |
10165 | intel_set_mode(save_set.crtc, save_set.mode, | |
10166 | save_set.x, save_set.y, save_set.fb)) | |
10167 | DRM_ERROR("failed to restore config after modeset failure\n"); | |
10168 | } | |
50f56119 | 10169 | |
d9e55608 DV |
10170 | out_config: |
10171 | intel_set_config_free(config); | |
50f56119 DV |
10172 | return ret; |
10173 | } | |
f6e5b160 CW |
10174 | |
10175 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
f6e5b160 CW |
10176 | .cursor_set = intel_crtc_cursor_set, |
10177 | .cursor_move = intel_crtc_cursor_move, | |
10178 | .gamma_set = intel_crtc_gamma_set, | |
50f56119 | 10179 | .set_config = intel_crtc_set_config, |
f6e5b160 CW |
10180 | .destroy = intel_crtc_destroy, |
10181 | .page_flip = intel_crtc_page_flip, | |
10182 | }; | |
10183 | ||
79f689aa PZ |
10184 | static void intel_cpu_pll_init(struct drm_device *dev) |
10185 | { | |
affa9354 | 10186 | if (HAS_DDI(dev)) |
79f689aa PZ |
10187 | intel_ddi_pll_init(dev); |
10188 | } | |
10189 | ||
5358901f DV |
10190 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
10191 | struct intel_shared_dpll *pll, | |
10192 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 10193 | { |
5358901f | 10194 | uint32_t val; |
ee7b9f93 | 10195 | |
5358901f | 10196 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
10197 | hw_state->dpll = val; |
10198 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
10199 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
10200 | |
10201 | return val & DPLL_VCO_ENABLE; | |
10202 | } | |
10203 | ||
15bdd4cf DV |
10204 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
10205 | struct intel_shared_dpll *pll) | |
10206 | { | |
10207 | I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0); | |
10208 | I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1); | |
10209 | } | |
10210 | ||
e7b903d2 DV |
10211 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
10212 | struct intel_shared_dpll *pll) | |
10213 | { | |
e7b903d2 | 10214 | /* PCH refclock must be enabled first */ |
89eff4be | 10215 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 10216 | |
15bdd4cf DV |
10217 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); |
10218 | ||
10219 | /* Wait for the clocks to stabilize. */ | |
10220 | POSTING_READ(PCH_DPLL(pll->id)); | |
10221 | udelay(150); | |
10222 | ||
10223 | /* The pixel multiplier can only be updated once the | |
10224 | * DPLL is enabled and the clocks are stable. | |
10225 | * | |
10226 | * So write it again. | |
10227 | */ | |
10228 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); | |
10229 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
10230 | udelay(200); |
10231 | } | |
10232 | ||
10233 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
10234 | struct intel_shared_dpll *pll) | |
10235 | { | |
10236 | struct drm_device *dev = dev_priv->dev; | |
10237 | struct intel_crtc *crtc; | |
e7b903d2 DV |
10238 | |
10239 | /* Make sure no transcoder isn't still depending on us. */ | |
10240 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
10241 | if (intel_crtc_to_shared_dpll(crtc) == pll) | |
10242 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
10243 | } |
10244 | ||
15bdd4cf DV |
10245 | I915_WRITE(PCH_DPLL(pll->id), 0); |
10246 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
10247 | udelay(200); |
10248 | } | |
10249 | ||
46edb027 DV |
10250 | static char *ibx_pch_dpll_names[] = { |
10251 | "PCH DPLL A", | |
10252 | "PCH DPLL B", | |
10253 | }; | |
10254 | ||
7c74ade1 | 10255 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 10256 | { |
e7b903d2 | 10257 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
10258 | int i; |
10259 | ||
7c74ade1 | 10260 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 10261 | |
e72f9fbf | 10262 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
10263 | dev_priv->shared_dplls[i].id = i; |
10264 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 10265 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
10266 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
10267 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
10268 | dev_priv->shared_dplls[i].get_hw_state = |
10269 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
10270 | } |
10271 | } | |
10272 | ||
7c74ade1 DV |
10273 | static void intel_shared_dpll_init(struct drm_device *dev) |
10274 | { | |
e7b903d2 | 10275 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 DV |
10276 | |
10277 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
10278 | ibx_pch_dpll_init(dev); | |
10279 | else | |
10280 | dev_priv->num_shared_dpll = 0; | |
10281 | ||
10282 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
10283 | } |
10284 | ||
b358d0a6 | 10285 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 10286 | { |
22fd0fab | 10287 | drm_i915_private_t *dev_priv = dev->dev_private; |
79e53945 JB |
10288 | struct intel_crtc *intel_crtc; |
10289 | int i; | |
10290 | ||
955382f3 | 10291 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
10292 | if (intel_crtc == NULL) |
10293 | return; | |
10294 | ||
10295 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); | |
10296 | ||
10297 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
10298 | for (i = 0; i < 256; i++) { |
10299 | intel_crtc->lut_r[i] = i; | |
10300 | intel_crtc->lut_g[i] = i; | |
10301 | intel_crtc->lut_b[i] = i; | |
10302 | } | |
10303 | ||
1f1c2e24 VS |
10304 | /* |
10305 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
10306 | * is hooked to plane B. Hence we want plane A feeding pipe B. | |
10307 | */ | |
80824003 JB |
10308 | intel_crtc->pipe = pipe; |
10309 | intel_crtc->plane = pipe; | |
3a77c4c4 | 10310 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 10311 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 10312 | intel_crtc->plane = !pipe; |
80824003 JB |
10313 | } |
10314 | ||
22fd0fab JB |
10315 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
10316 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
10317 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
10318 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
10319 | ||
79e53945 | 10320 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
79e53945 JB |
10321 | } |
10322 | ||
752aa88a JB |
10323 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
10324 | { | |
10325 | struct drm_encoder *encoder = connector->base.encoder; | |
10326 | ||
10327 | WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex)); | |
10328 | ||
10329 | if (!encoder) | |
10330 | return INVALID_PIPE; | |
10331 | ||
10332 | return to_intel_crtc(encoder->crtc)->pipe; | |
10333 | } | |
10334 | ||
08d7b3d1 | 10335 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 10336 | struct drm_file *file) |
08d7b3d1 | 10337 | { |
08d7b3d1 | 10338 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
c05422d5 DV |
10339 | struct drm_mode_object *drmmode_obj; |
10340 | struct intel_crtc *crtc; | |
08d7b3d1 | 10341 | |
1cff8f6b DV |
10342 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
10343 | return -ENODEV; | |
08d7b3d1 | 10344 | |
c05422d5 DV |
10345 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
10346 | DRM_MODE_OBJECT_CRTC); | |
08d7b3d1 | 10347 | |
c05422d5 | 10348 | if (!drmmode_obj) { |
08d7b3d1 | 10349 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 10350 | return -ENOENT; |
08d7b3d1 CW |
10351 | } |
10352 | ||
c05422d5 DV |
10353 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
10354 | pipe_from_crtc_id->pipe = crtc->pipe; | |
08d7b3d1 | 10355 | |
c05422d5 | 10356 | return 0; |
08d7b3d1 CW |
10357 | } |
10358 | ||
66a9278e | 10359 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 10360 | { |
66a9278e DV |
10361 | struct drm_device *dev = encoder->base.dev; |
10362 | struct intel_encoder *source_encoder; | |
79e53945 | 10363 | int index_mask = 0; |
79e53945 JB |
10364 | int entry = 0; |
10365 | ||
66a9278e DV |
10366 | list_for_each_entry(source_encoder, |
10367 | &dev->mode_config.encoder_list, base.head) { | |
10368 | ||
10369 | if (encoder == source_encoder) | |
79e53945 | 10370 | index_mask |= (1 << entry); |
66a9278e DV |
10371 | |
10372 | /* Intel hw has only one MUX where enocoders could be cloned. */ | |
10373 | if (encoder->cloneable && source_encoder->cloneable) | |
10374 | index_mask |= (1 << entry); | |
10375 | ||
79e53945 JB |
10376 | entry++; |
10377 | } | |
4ef69c7a | 10378 | |
79e53945 JB |
10379 | return index_mask; |
10380 | } | |
10381 | ||
4d302442 CW |
10382 | static bool has_edp_a(struct drm_device *dev) |
10383 | { | |
10384 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10385 | ||
10386 | if (!IS_MOBILE(dev)) | |
10387 | return false; | |
10388 | ||
10389 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
10390 | return false; | |
10391 | ||
e3589908 | 10392 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
10393 | return false; |
10394 | ||
10395 | return true; | |
10396 | } | |
10397 | ||
ba0fbca4 DL |
10398 | const char *intel_output_name(int output) |
10399 | { | |
10400 | static const char *names[] = { | |
10401 | [INTEL_OUTPUT_UNUSED] = "Unused", | |
10402 | [INTEL_OUTPUT_ANALOG] = "Analog", | |
10403 | [INTEL_OUTPUT_DVO] = "DVO", | |
10404 | [INTEL_OUTPUT_SDVO] = "SDVO", | |
10405 | [INTEL_OUTPUT_LVDS] = "LVDS", | |
10406 | [INTEL_OUTPUT_TVOUT] = "TV", | |
10407 | [INTEL_OUTPUT_HDMI] = "HDMI", | |
10408 | [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort", | |
10409 | [INTEL_OUTPUT_EDP] = "eDP", | |
10410 | [INTEL_OUTPUT_DSI] = "DSI", | |
10411 | [INTEL_OUTPUT_UNKNOWN] = "Unknown", | |
10412 | }; | |
10413 | ||
10414 | if (output < 0 || output >= ARRAY_SIZE(names) || !names[output]) | |
10415 | return "Invalid"; | |
10416 | ||
10417 | return names[output]; | |
10418 | } | |
10419 | ||
79e53945 JB |
10420 | static void intel_setup_outputs(struct drm_device *dev) |
10421 | { | |
725e30ad | 10422 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 10423 | struct intel_encoder *encoder; |
cb0953d7 | 10424 | bool dpd_is_edp = false; |
79e53945 | 10425 | |
c9093354 | 10426 | intel_lvds_init(dev); |
79e53945 | 10427 | |
c40c0f5b | 10428 | if (!IS_ULT(dev)) |
79935fca | 10429 | intel_crt_init(dev); |
cb0953d7 | 10430 | |
affa9354 | 10431 | if (HAS_DDI(dev)) { |
0e72a5b5 ED |
10432 | int found; |
10433 | ||
10434 | /* Haswell uses DDI functions to detect digital outputs */ | |
10435 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; | |
10436 | /* DDI A only supports eDP */ | |
10437 | if (found) | |
10438 | intel_ddi_init(dev, PORT_A); | |
10439 | ||
10440 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
10441 | * register */ | |
10442 | found = I915_READ(SFUSE_STRAP); | |
10443 | ||
10444 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
10445 | intel_ddi_init(dev, PORT_B); | |
10446 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
10447 | intel_ddi_init(dev, PORT_C); | |
10448 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
10449 | intel_ddi_init(dev, PORT_D); | |
10450 | } else if (HAS_PCH_SPLIT(dev)) { | |
cb0953d7 | 10451 | int found; |
5d8a7752 | 10452 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
10453 | |
10454 | if (has_edp_a(dev)) | |
10455 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 10456 | |
dc0fa718 | 10457 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 10458 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 10459 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 10460 | if (!found) |
e2debe91 | 10461 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 10462 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 10463 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
10464 | } |
10465 | ||
dc0fa718 | 10466 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 10467 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 10468 | |
dc0fa718 | 10469 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 10470 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 10471 | |
5eb08b69 | 10472 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 10473 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 10474 | |
270b3042 | 10475 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 10476 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d | 10477 | } else if (IS_VALLEYVIEW(dev)) { |
585a94b8 AB |
10478 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) { |
10479 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, | |
10480 | PORT_B); | |
10481 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED) | |
10482 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); | |
10483 | } | |
10484 | ||
6f6005a5 JB |
10485 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) { |
10486 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, | |
10487 | PORT_C); | |
10488 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) | |
5d8a7752 | 10489 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); |
6f6005a5 | 10490 | } |
19c03924 | 10491 | |
3cfca973 | 10492 | intel_dsi_init(dev); |
103a196f | 10493 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 10494 | bool found = false; |
7d57382e | 10495 | |
e2debe91 | 10496 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 10497 | DRM_DEBUG_KMS("probing SDVOB\n"); |
e2debe91 | 10498 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
b01f2c3a JB |
10499 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
10500 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
e2debe91 | 10501 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 10502 | } |
27185ae1 | 10503 | |
e7281eab | 10504 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 10505 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 10506 | } |
13520b05 KH |
10507 | |
10508 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 10509 | |
e2debe91 | 10510 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 10511 | DRM_DEBUG_KMS("probing SDVOC\n"); |
e2debe91 | 10512 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
b01f2c3a | 10513 | } |
27185ae1 | 10514 | |
e2debe91 | 10515 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 10516 | |
b01f2c3a JB |
10517 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
10518 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
e2debe91 | 10519 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 10520 | } |
e7281eab | 10521 | if (SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 10522 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 10523 | } |
27185ae1 | 10524 | |
b01f2c3a | 10525 | if (SUPPORTS_INTEGRATED_DP(dev) && |
e7281eab | 10526 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 10527 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 10528 | } else if (IS_GEN2(dev)) |
79e53945 JB |
10529 | intel_dvo_init(dev); |
10530 | ||
103a196f | 10531 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
10532 | intel_tv_init(dev); |
10533 | ||
4ef69c7a CW |
10534 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
10535 | encoder->base.possible_crtcs = encoder->crtc_mask; | |
10536 | encoder->base.possible_clones = | |
66a9278e | 10537 | intel_encoder_clones(encoder); |
79e53945 | 10538 | } |
47356eb6 | 10539 | |
dde86e2d | 10540 | intel_init_pch_refclk(dev); |
270b3042 DV |
10541 | |
10542 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
10543 | } |
10544 | ||
10545 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
10546 | { | |
10547 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 | 10548 | |
ef2d633e DV |
10549 | drm_framebuffer_cleanup(fb); |
10550 | WARN_ON(!intel_fb->obj->framebuffer_references--); | |
10551 | drm_gem_object_unreference_unlocked(&intel_fb->obj->base); | |
79e53945 JB |
10552 | kfree(intel_fb); |
10553 | } | |
10554 | ||
10555 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 10556 | struct drm_file *file, |
79e53945 JB |
10557 | unsigned int *handle) |
10558 | { | |
10559 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 10560 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 10561 | |
05394f39 | 10562 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
10563 | } |
10564 | ||
10565 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
10566 | .destroy = intel_user_framebuffer_destroy, | |
10567 | .create_handle = intel_user_framebuffer_create_handle, | |
10568 | }; | |
10569 | ||
38651674 DA |
10570 | int intel_framebuffer_init(struct drm_device *dev, |
10571 | struct intel_framebuffer *intel_fb, | |
308e5bcb | 10572 | struct drm_mode_fb_cmd2 *mode_cmd, |
05394f39 | 10573 | struct drm_i915_gem_object *obj) |
79e53945 | 10574 | { |
a57ce0b2 | 10575 | int aligned_height; |
a35cdaa0 | 10576 | int pitch_limit; |
79e53945 JB |
10577 | int ret; |
10578 | ||
dd4916c5 DV |
10579 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
10580 | ||
c16ed4be CW |
10581 | if (obj->tiling_mode == I915_TILING_Y) { |
10582 | DRM_DEBUG("hardware does not support tiling Y\n"); | |
57cd6508 | 10583 | return -EINVAL; |
c16ed4be | 10584 | } |
57cd6508 | 10585 | |
c16ed4be CW |
10586 | if (mode_cmd->pitches[0] & 63) { |
10587 | DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n", | |
10588 | mode_cmd->pitches[0]); | |
57cd6508 | 10589 | return -EINVAL; |
c16ed4be | 10590 | } |
57cd6508 | 10591 | |
a35cdaa0 CW |
10592 | if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) { |
10593 | pitch_limit = 32*1024; | |
10594 | } else if (INTEL_INFO(dev)->gen >= 4) { | |
10595 | if (obj->tiling_mode) | |
10596 | pitch_limit = 16*1024; | |
10597 | else | |
10598 | pitch_limit = 32*1024; | |
10599 | } else if (INTEL_INFO(dev)->gen >= 3) { | |
10600 | if (obj->tiling_mode) | |
10601 | pitch_limit = 8*1024; | |
10602 | else | |
10603 | pitch_limit = 16*1024; | |
10604 | } else | |
10605 | /* XXX DSPC is limited to 4k tiled */ | |
10606 | pitch_limit = 8*1024; | |
10607 | ||
10608 | if (mode_cmd->pitches[0] > pitch_limit) { | |
10609 | DRM_DEBUG("%s pitch (%d) must be at less than %d\n", | |
10610 | obj->tiling_mode ? "tiled" : "linear", | |
10611 | mode_cmd->pitches[0], pitch_limit); | |
5d7bd705 | 10612 | return -EINVAL; |
c16ed4be | 10613 | } |
5d7bd705 VS |
10614 | |
10615 | if (obj->tiling_mode != I915_TILING_NONE && | |
c16ed4be CW |
10616 | mode_cmd->pitches[0] != obj->stride) { |
10617 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
10618 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 10619 | return -EINVAL; |
c16ed4be | 10620 | } |
5d7bd705 | 10621 | |
57779d06 | 10622 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 10623 | switch (mode_cmd->pixel_format) { |
57779d06 | 10624 | case DRM_FORMAT_C8: |
04b3924d VS |
10625 | case DRM_FORMAT_RGB565: |
10626 | case DRM_FORMAT_XRGB8888: | |
10627 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
10628 | break; |
10629 | case DRM_FORMAT_XRGB1555: | |
10630 | case DRM_FORMAT_ARGB1555: | |
c16ed4be | 10631 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
10632 | DRM_DEBUG("unsupported pixel format: %s\n", |
10633 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 10634 | return -EINVAL; |
c16ed4be | 10635 | } |
57779d06 VS |
10636 | break; |
10637 | case DRM_FORMAT_XBGR8888: | |
10638 | case DRM_FORMAT_ABGR8888: | |
04b3924d VS |
10639 | case DRM_FORMAT_XRGB2101010: |
10640 | case DRM_FORMAT_ARGB2101010: | |
57779d06 VS |
10641 | case DRM_FORMAT_XBGR2101010: |
10642 | case DRM_FORMAT_ABGR2101010: | |
c16ed4be | 10643 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
10644 | DRM_DEBUG("unsupported pixel format: %s\n", |
10645 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 10646 | return -EINVAL; |
c16ed4be | 10647 | } |
b5626747 | 10648 | break; |
04b3924d VS |
10649 | case DRM_FORMAT_YUYV: |
10650 | case DRM_FORMAT_UYVY: | |
10651 | case DRM_FORMAT_YVYU: | |
10652 | case DRM_FORMAT_VYUY: | |
c16ed4be | 10653 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
10654 | DRM_DEBUG("unsupported pixel format: %s\n", |
10655 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 10656 | return -EINVAL; |
c16ed4be | 10657 | } |
57cd6508 CW |
10658 | break; |
10659 | default: | |
4ee62c76 VS |
10660 | DRM_DEBUG("unsupported pixel format: %s\n", |
10661 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
10662 | return -EINVAL; |
10663 | } | |
10664 | ||
90f9a336 VS |
10665 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
10666 | if (mode_cmd->offsets[0] != 0) | |
10667 | return -EINVAL; | |
10668 | ||
a57ce0b2 JB |
10669 | aligned_height = intel_align_height(dev, mode_cmd->height, |
10670 | obj->tiling_mode); | |
53155c0a DV |
10671 | /* FIXME drm helper for size checks (especially planar formats)? */ |
10672 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
10673 | return -EINVAL; | |
10674 | ||
c7d73f6a DV |
10675 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
10676 | intel_fb->obj = obj; | |
80075d49 | 10677 | intel_fb->obj->framebuffer_references++; |
c7d73f6a | 10678 | |
79e53945 JB |
10679 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
10680 | if (ret) { | |
10681 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
10682 | return ret; | |
10683 | } | |
10684 | ||
79e53945 JB |
10685 | return 0; |
10686 | } | |
10687 | ||
79e53945 JB |
10688 | static struct drm_framebuffer * |
10689 | intel_user_framebuffer_create(struct drm_device *dev, | |
10690 | struct drm_file *filp, | |
308e5bcb | 10691 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 10692 | { |
05394f39 | 10693 | struct drm_i915_gem_object *obj; |
79e53945 | 10694 | |
308e5bcb JB |
10695 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
10696 | mode_cmd->handles[0])); | |
c8725226 | 10697 | if (&obj->base == NULL) |
cce13ff7 | 10698 | return ERR_PTR(-ENOENT); |
79e53945 | 10699 | |
d2dff872 | 10700 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
10701 | } |
10702 | ||
4520f53a | 10703 | #ifndef CONFIG_DRM_I915_FBDEV |
0632fef6 | 10704 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
10705 | { |
10706 | } | |
10707 | #endif | |
10708 | ||
79e53945 | 10709 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 10710 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 10711 | .output_poll_changed = intel_fbdev_output_poll_changed, |
79e53945 JB |
10712 | }; |
10713 | ||
e70236a8 JB |
10714 | /* Set up chip specific display functions */ |
10715 | static void intel_init_display(struct drm_device *dev) | |
10716 | { | |
10717 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10718 | ||
ee9300bb DV |
10719 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
10720 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
10721 | else if (IS_VALLEYVIEW(dev)) | |
10722 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
10723 | else if (IS_PINEVIEW(dev)) | |
10724 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
10725 | else | |
10726 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
10727 | ||
affa9354 | 10728 | if (HAS_DDI(dev)) { |
0e8ffe1b | 10729 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
09b4ddf9 | 10730 | dev_priv->display.crtc_mode_set = haswell_crtc_mode_set; |
4f771f10 PZ |
10731 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
10732 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
6441ab5f | 10733 | dev_priv->display.off = haswell_crtc_off; |
09b4ddf9 PZ |
10734 | dev_priv->display.update_plane = ironlake_update_plane; |
10735 | } else if (HAS_PCH_SPLIT(dev)) { | |
0e8ffe1b | 10736 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
f564048e | 10737 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
76e5a89c DV |
10738 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
10739 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
ee7b9f93 | 10740 | dev_priv->display.off = ironlake_crtc_off; |
17638cd6 | 10741 | dev_priv->display.update_plane = ironlake_update_plane; |
89b667f8 JB |
10742 | } else if (IS_VALLEYVIEW(dev)) { |
10743 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
10744 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; | |
10745 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
10746 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
10747 | dev_priv->display.off = i9xx_crtc_off; | |
10748 | dev_priv->display.update_plane = i9xx_update_plane; | |
f564048e | 10749 | } else { |
0e8ffe1b | 10750 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
f564048e | 10751 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
76e5a89c DV |
10752 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
10753 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
ee7b9f93 | 10754 | dev_priv->display.off = i9xx_crtc_off; |
17638cd6 | 10755 | dev_priv->display.update_plane = i9xx_update_plane; |
f564048e | 10756 | } |
e70236a8 | 10757 | |
e70236a8 | 10758 | /* Returns the core display clock speed */ |
25eb05fc JB |
10759 | if (IS_VALLEYVIEW(dev)) |
10760 | dev_priv->display.get_display_clock_speed = | |
10761 | valleyview_get_display_clock_speed; | |
10762 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) | |
e70236a8 JB |
10763 | dev_priv->display.get_display_clock_speed = |
10764 | i945_get_display_clock_speed; | |
10765 | else if (IS_I915G(dev)) | |
10766 | dev_priv->display.get_display_clock_speed = | |
10767 | i915_get_display_clock_speed; | |
257a7ffc | 10768 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
10769 | dev_priv->display.get_display_clock_speed = |
10770 | i9xx_misc_get_display_clock_speed; | |
257a7ffc DV |
10771 | else if (IS_PINEVIEW(dev)) |
10772 | dev_priv->display.get_display_clock_speed = | |
10773 | pnv_get_display_clock_speed; | |
e70236a8 JB |
10774 | else if (IS_I915GM(dev)) |
10775 | dev_priv->display.get_display_clock_speed = | |
10776 | i915gm_get_display_clock_speed; | |
10777 | else if (IS_I865G(dev)) | |
10778 | dev_priv->display.get_display_clock_speed = | |
10779 | i865_get_display_clock_speed; | |
f0f8a9ce | 10780 | else if (IS_I85X(dev)) |
e70236a8 JB |
10781 | dev_priv->display.get_display_clock_speed = |
10782 | i855_get_display_clock_speed; | |
10783 | else /* 852, 830 */ | |
10784 | dev_priv->display.get_display_clock_speed = | |
10785 | i830_get_display_clock_speed; | |
10786 | ||
7f8a8569 | 10787 | if (HAS_PCH_SPLIT(dev)) { |
f00a3ddf | 10788 | if (IS_GEN5(dev)) { |
674cf967 | 10789 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
e0dac65e | 10790 | dev_priv->display.write_eld = ironlake_write_eld; |
1398261a | 10791 | } else if (IS_GEN6(dev)) { |
674cf967 | 10792 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
e0dac65e | 10793 | dev_priv->display.write_eld = ironlake_write_eld; |
357555c0 JB |
10794 | } else if (IS_IVYBRIDGE(dev)) { |
10795 | /* FIXME: detect B0+ stepping and use auto training */ | |
10796 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
e0dac65e | 10797 | dev_priv->display.write_eld = ironlake_write_eld; |
01a415fd DV |
10798 | dev_priv->display.modeset_global_resources = |
10799 | ivb_modeset_global_resources; | |
4e0bbc31 | 10800 | } else if (IS_HASWELL(dev) || IS_GEN8(dev)) { |
c82e4d26 | 10801 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
83358c85 | 10802 | dev_priv->display.write_eld = haswell_write_eld; |
d6dd9eb1 DV |
10803 | dev_priv->display.modeset_global_resources = |
10804 | haswell_modeset_global_resources; | |
a0e63c22 | 10805 | } |
6067aaea | 10806 | } else if (IS_G4X(dev)) { |
e0dac65e | 10807 | dev_priv->display.write_eld = g4x_write_eld; |
30a970c6 JB |
10808 | } else if (IS_VALLEYVIEW(dev)) { |
10809 | dev_priv->display.modeset_global_resources = | |
10810 | valleyview_modeset_global_resources; | |
9ca2fe73 | 10811 | dev_priv->display.write_eld = ironlake_write_eld; |
e70236a8 | 10812 | } |
8c9f3aaf JB |
10813 | |
10814 | /* Default just returns -ENODEV to indicate unsupported */ | |
10815 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
10816 | ||
10817 | switch (INTEL_INFO(dev)->gen) { | |
10818 | case 2: | |
10819 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
10820 | break; | |
10821 | ||
10822 | case 3: | |
10823 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
10824 | break; | |
10825 | ||
10826 | case 4: | |
10827 | case 5: | |
10828 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
10829 | break; | |
10830 | ||
10831 | case 6: | |
10832 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
10833 | break; | |
7c9017e5 | 10834 | case 7: |
4e0bbc31 | 10835 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
10836 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
10837 | break; | |
8c9f3aaf | 10838 | } |
7bd688cd JN |
10839 | |
10840 | intel_panel_init_backlight_funcs(dev); | |
e70236a8 JB |
10841 | } |
10842 | ||
b690e96c JB |
10843 | /* |
10844 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
10845 | * resume, or other times. This quirk makes sure that's the case for | |
10846 | * affected systems. | |
10847 | */ | |
0206e353 | 10848 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
10849 | { |
10850 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10851 | ||
10852 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 10853 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
10854 | } |
10855 | ||
435793df KP |
10856 | /* |
10857 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
10858 | */ | |
10859 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
10860 | { | |
10861 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10862 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 10863 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
10864 | } |
10865 | ||
4dca20ef | 10866 | /* |
5a15ab5b CE |
10867 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
10868 | * brightness value | |
4dca20ef CE |
10869 | */ |
10870 | static void quirk_invert_brightness(struct drm_device *dev) | |
10871 | { | |
10872 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10873 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 10874 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
10875 | } |
10876 | ||
b690e96c JB |
10877 | struct intel_quirk { |
10878 | int device; | |
10879 | int subsystem_vendor; | |
10880 | int subsystem_device; | |
10881 | void (*hook)(struct drm_device *dev); | |
10882 | }; | |
10883 | ||
5f85f176 EE |
10884 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
10885 | struct intel_dmi_quirk { | |
10886 | void (*hook)(struct drm_device *dev); | |
10887 | const struct dmi_system_id (*dmi_id_list)[]; | |
10888 | }; | |
10889 | ||
10890 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
10891 | { | |
10892 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
10893 | return 1; | |
10894 | } | |
10895 | ||
10896 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
10897 | { | |
10898 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
10899 | { | |
10900 | .callback = intel_dmi_reverse_brightness, | |
10901 | .ident = "NCR Corporation", | |
10902 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
10903 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
10904 | }, | |
10905 | }, | |
10906 | { } /* terminating entry */ | |
10907 | }, | |
10908 | .hook = quirk_invert_brightness, | |
10909 | }, | |
10910 | }; | |
10911 | ||
c43b5634 | 10912 | static struct intel_quirk intel_quirks[] = { |
b690e96c | 10913 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
0206e353 | 10914 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c | 10915 | |
b690e96c JB |
10916 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
10917 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
10918 | ||
b690e96c JB |
10919 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
10920 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
10921 | ||
a4945f95 | 10922 | /* 830 needs to leave pipe A & dpll A up */ |
dcdaed6e | 10923 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
435793df KP |
10924 | |
10925 | /* Lenovo U160 cannot use SSC on LVDS */ | |
10926 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
10927 | |
10928 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
10929 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 10930 | |
be505f64 AH |
10931 | /* Acer Aspire 5734Z must invert backlight brightness */ |
10932 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
10933 | ||
10934 | /* Acer/eMachines G725 */ | |
10935 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
10936 | ||
10937 | /* Acer/eMachines e725 */ | |
10938 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
10939 | ||
10940 | /* Acer/Packard Bell NCL20 */ | |
10941 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
10942 | ||
10943 | /* Acer Aspire 4736Z */ | |
10944 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
10945 | |
10946 | /* Acer Aspire 5336 */ | |
10947 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
b690e96c JB |
10948 | }; |
10949 | ||
10950 | static void intel_init_quirks(struct drm_device *dev) | |
10951 | { | |
10952 | struct pci_dev *d = dev->pdev; | |
10953 | int i; | |
10954 | ||
10955 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
10956 | struct intel_quirk *q = &intel_quirks[i]; | |
10957 | ||
10958 | if (d->device == q->device && | |
10959 | (d->subsystem_vendor == q->subsystem_vendor || | |
10960 | q->subsystem_vendor == PCI_ANY_ID) && | |
10961 | (d->subsystem_device == q->subsystem_device || | |
10962 | q->subsystem_device == PCI_ANY_ID)) | |
10963 | q->hook(dev); | |
10964 | } | |
5f85f176 EE |
10965 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
10966 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
10967 | intel_dmi_quirks[i].hook(dev); | |
10968 | } | |
b690e96c JB |
10969 | } |
10970 | ||
9cce37f4 JB |
10971 | /* Disable the VGA plane that we never use */ |
10972 | static void i915_disable_vga(struct drm_device *dev) | |
10973 | { | |
10974 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10975 | u8 sr1; | |
766aa1c4 | 10976 | u32 vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 10977 | |
2b37c616 | 10978 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 10979 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 10980 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
10981 | sr1 = inb(VGA_SR_DATA); |
10982 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
10983 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
10984 | udelay(300); | |
10985 | ||
10986 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); | |
10987 | POSTING_READ(vga_reg); | |
10988 | } | |
10989 | ||
f817586c DV |
10990 | void intel_modeset_init_hw(struct drm_device *dev) |
10991 | { | |
a8f78b58 ED |
10992 | intel_prepare_ddi(dev); |
10993 | ||
f817586c DV |
10994 | intel_init_clock_gating(dev); |
10995 | ||
5382f5f3 | 10996 | intel_reset_dpio(dev); |
40e9cf64 | 10997 | |
79f5b2c7 | 10998 | mutex_lock(&dev->struct_mutex); |
8090c6b9 | 10999 | intel_enable_gt_powersave(dev); |
79f5b2c7 | 11000 | mutex_unlock(&dev->struct_mutex); |
f817586c DV |
11001 | } |
11002 | ||
7d708ee4 ID |
11003 | void intel_modeset_suspend_hw(struct drm_device *dev) |
11004 | { | |
11005 | intel_suspend_hw(dev); | |
11006 | } | |
11007 | ||
79e53945 JB |
11008 | void intel_modeset_init(struct drm_device *dev) |
11009 | { | |
652c393a | 11010 | struct drm_i915_private *dev_priv = dev->dev_private; |
7f1f3851 | 11011 | int i, j, ret; |
79e53945 JB |
11012 | |
11013 | drm_mode_config_init(dev); | |
11014 | ||
11015 | dev->mode_config.min_width = 0; | |
11016 | dev->mode_config.min_height = 0; | |
11017 | ||
019d96cb DA |
11018 | dev->mode_config.preferred_depth = 24; |
11019 | dev->mode_config.prefer_shadow = 1; | |
11020 | ||
e6ecefaa | 11021 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 11022 | |
b690e96c JB |
11023 | intel_init_quirks(dev); |
11024 | ||
1fa61106 ED |
11025 | intel_init_pm(dev); |
11026 | ||
e3c74757 BW |
11027 | if (INTEL_INFO(dev)->num_pipes == 0) |
11028 | return; | |
11029 | ||
e70236a8 JB |
11030 | intel_init_display(dev); |
11031 | ||
a6c45cf0 CW |
11032 | if (IS_GEN2(dev)) { |
11033 | dev->mode_config.max_width = 2048; | |
11034 | dev->mode_config.max_height = 2048; | |
11035 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
11036 | dev->mode_config.max_width = 4096; |
11037 | dev->mode_config.max_height = 4096; | |
79e53945 | 11038 | } else { |
a6c45cf0 CW |
11039 | dev->mode_config.max_width = 8192; |
11040 | dev->mode_config.max_height = 8192; | |
79e53945 | 11041 | } |
5d4545ae | 11042 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 11043 | |
28c97730 | 11044 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
11045 | INTEL_INFO(dev)->num_pipes, |
11046 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 11047 | |
08e2a7de | 11048 | for_each_pipe(i) { |
79e53945 | 11049 | intel_crtc_init(dev, i); |
22d3fd46 | 11050 | for (j = 0; j < INTEL_INFO(dev)->num_sprites; j++) { |
7f1f3851 JB |
11051 | ret = intel_plane_init(dev, i, j); |
11052 | if (ret) | |
06da8da2 VS |
11053 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
11054 | pipe_name(i), sprite_name(i, j), ret); | |
7f1f3851 | 11055 | } |
79e53945 JB |
11056 | } |
11057 | ||
f42bb70d | 11058 | intel_init_dpio(dev); |
5382f5f3 | 11059 | intel_reset_dpio(dev); |
f42bb70d | 11060 | |
79f689aa | 11061 | intel_cpu_pll_init(dev); |
e72f9fbf | 11062 | intel_shared_dpll_init(dev); |
ee7b9f93 | 11063 | |
9cce37f4 JB |
11064 | /* Just disable it once at startup */ |
11065 | i915_disable_vga(dev); | |
79e53945 | 11066 | intel_setup_outputs(dev); |
11be49eb CW |
11067 | |
11068 | /* Just in case the BIOS is doing something questionable. */ | |
11069 | intel_disable_fbc(dev); | |
2c7111db CW |
11070 | } |
11071 | ||
24929352 DV |
11072 | static void |
11073 | intel_connector_break_all_links(struct intel_connector *connector) | |
11074 | { | |
11075 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
11076 | connector->base.encoder = NULL; | |
11077 | connector->encoder->connectors_active = false; | |
11078 | connector->encoder->base.crtc = NULL; | |
11079 | } | |
11080 | ||
7fad798e DV |
11081 | static void intel_enable_pipe_a(struct drm_device *dev) |
11082 | { | |
11083 | struct intel_connector *connector; | |
11084 | struct drm_connector *crt = NULL; | |
11085 | struct intel_load_detect_pipe load_detect_temp; | |
11086 | ||
11087 | /* We can't just switch on the pipe A, we need to set things up with a | |
11088 | * proper mode and output configuration. As a gross hack, enable pipe A | |
11089 | * by enabling the load detect pipe once. */ | |
11090 | list_for_each_entry(connector, | |
11091 | &dev->mode_config.connector_list, | |
11092 | base.head) { | |
11093 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { | |
11094 | crt = &connector->base; | |
11095 | break; | |
11096 | } | |
11097 | } | |
11098 | ||
11099 | if (!crt) | |
11100 | return; | |
11101 | ||
11102 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp)) | |
11103 | intel_release_load_detect_pipe(crt, &load_detect_temp); | |
11104 | ||
652c393a | 11105 | |
7fad798e DV |
11106 | } |
11107 | ||
fa555837 DV |
11108 | static bool |
11109 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
11110 | { | |
7eb552ae BW |
11111 | struct drm_device *dev = crtc->base.dev; |
11112 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 DV |
11113 | u32 reg, val; |
11114 | ||
7eb552ae | 11115 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
11116 | return true; |
11117 | ||
11118 | reg = DSPCNTR(!crtc->plane); | |
11119 | val = I915_READ(reg); | |
11120 | ||
11121 | if ((val & DISPLAY_PLANE_ENABLE) && | |
11122 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
11123 | return false; | |
11124 | ||
11125 | return true; | |
11126 | } | |
11127 | ||
24929352 DV |
11128 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
11129 | { | |
11130 | struct drm_device *dev = crtc->base.dev; | |
11131 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 | 11132 | u32 reg; |
24929352 | 11133 | |
24929352 | 11134 | /* Clear any frame start delays used for debugging left by the BIOS */ |
3b117c8f | 11135 | reg = PIPECONF(crtc->config.cpu_transcoder); |
24929352 DV |
11136 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
11137 | ||
11138 | /* We need to sanitize the plane -> pipe mapping first because this will | |
fa555837 DV |
11139 | * disable the crtc (and hence change the state) if it is wrong. Note |
11140 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
11141 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
11142 | struct intel_connector *connector; |
11143 | bool plane; | |
11144 | ||
24929352 DV |
11145 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
11146 | crtc->base.base.id); | |
11147 | ||
11148 | /* Pipe has the wrong plane attached and the plane is active. | |
11149 | * Temporarily change the plane mapping and disable everything | |
11150 | * ... */ | |
11151 | plane = crtc->plane; | |
11152 | crtc->plane = !plane; | |
11153 | dev_priv->display.crtc_disable(&crtc->base); | |
11154 | crtc->plane = plane; | |
11155 | ||
11156 | /* ... and break all links. */ | |
11157 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
11158 | base.head) { | |
11159 | if (connector->encoder->base.crtc != &crtc->base) | |
11160 | continue; | |
11161 | ||
11162 | intel_connector_break_all_links(connector); | |
11163 | } | |
11164 | ||
11165 | WARN_ON(crtc->active); | |
11166 | crtc->base.enabled = false; | |
11167 | } | |
24929352 | 11168 | |
7fad798e DV |
11169 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
11170 | crtc->pipe == PIPE_A && !crtc->active) { | |
11171 | /* BIOS forgot to enable pipe A, this mostly happens after | |
11172 | * resume. Force-enable the pipe to fix this, the update_dpms | |
11173 | * call below we restore the pipe to the right state, but leave | |
11174 | * the required bits on. */ | |
11175 | intel_enable_pipe_a(dev); | |
11176 | } | |
11177 | ||
24929352 DV |
11178 | /* Adjust the state of the output pipe according to whether we |
11179 | * have active connectors/encoders. */ | |
11180 | intel_crtc_update_dpms(&crtc->base); | |
11181 | ||
11182 | if (crtc->active != crtc->base.enabled) { | |
11183 | struct intel_encoder *encoder; | |
11184 | ||
11185 | /* This can happen either due to bugs in the get_hw_state | |
11186 | * functions or because the pipe is force-enabled due to the | |
11187 | * pipe A quirk. */ | |
11188 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
11189 | crtc->base.base.id, | |
11190 | crtc->base.enabled ? "enabled" : "disabled", | |
11191 | crtc->active ? "enabled" : "disabled"); | |
11192 | ||
11193 | crtc->base.enabled = crtc->active; | |
11194 | ||
11195 | /* Because we only establish the connector -> encoder -> | |
11196 | * crtc links if something is active, this means the | |
11197 | * crtc is now deactivated. Break the links. connector | |
11198 | * -> encoder links are only establish when things are | |
11199 | * actually up, hence no need to break them. */ | |
11200 | WARN_ON(crtc->active); | |
11201 | ||
11202 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { | |
11203 | WARN_ON(encoder->connectors_active); | |
11204 | encoder->base.crtc = NULL; | |
11205 | } | |
11206 | } | |
11207 | } | |
11208 | ||
11209 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
11210 | { | |
11211 | struct intel_connector *connector; | |
11212 | struct drm_device *dev = encoder->base.dev; | |
11213 | ||
11214 | /* We need to check both for a crtc link (meaning that the | |
11215 | * encoder is active and trying to read from a pipe) and the | |
11216 | * pipe itself being active. */ | |
11217 | bool has_active_crtc = encoder->base.crtc && | |
11218 | to_intel_crtc(encoder->base.crtc)->active; | |
11219 | ||
11220 | if (encoder->connectors_active && !has_active_crtc) { | |
11221 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
11222 | encoder->base.base.id, | |
11223 | drm_get_encoder_name(&encoder->base)); | |
11224 | ||
11225 | /* Connector is active, but has no active pipe. This is | |
11226 | * fallout from our resume register restoring. Disable | |
11227 | * the encoder manually again. */ | |
11228 | if (encoder->base.crtc) { | |
11229 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
11230 | encoder->base.base.id, | |
11231 | drm_get_encoder_name(&encoder->base)); | |
11232 | encoder->disable(encoder); | |
11233 | } | |
11234 | ||
11235 | /* Inconsistent output/port/pipe state happens presumably due to | |
11236 | * a bug in one of the get_hw_state functions. Or someplace else | |
11237 | * in our code, like the register restore mess on resume. Clamp | |
11238 | * things to off as a safer default. */ | |
11239 | list_for_each_entry(connector, | |
11240 | &dev->mode_config.connector_list, | |
11241 | base.head) { | |
11242 | if (connector->encoder != encoder) | |
11243 | continue; | |
11244 | ||
11245 | intel_connector_break_all_links(connector); | |
11246 | } | |
11247 | } | |
11248 | /* Enabled encoders without active connectors will be fixed in | |
11249 | * the crtc fixup. */ | |
11250 | } | |
11251 | ||
44cec740 | 11252 | void i915_redisable_vga(struct drm_device *dev) |
0fde901f KM |
11253 | { |
11254 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766aa1c4 | 11255 | u32 vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 11256 | |
8dc8a27c PZ |
11257 | /* This function can be called both from intel_modeset_setup_hw_state or |
11258 | * at a very early point in our resume sequence, where the power well | |
11259 | * structures are not yet restored. Since this function is at a very | |
11260 | * paranoid "someone might have enabled VGA while we were not looking" | |
11261 | * level, just check if the power well is enabled instead of trying to | |
11262 | * follow the "don't touch the power well if we don't need it" policy | |
11263 | * the rest of the driver uses. */ | |
f9e711e9 | 11264 | if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && |
6aedd1f5 | 11265 | (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0) |
8dc8a27c PZ |
11266 | return; |
11267 | ||
e1553faa | 11268 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
0fde901f | 11269 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); |
209d5211 | 11270 | i915_disable_vga(dev); |
0fde901f KM |
11271 | } |
11272 | } | |
11273 | ||
30e984df | 11274 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
11275 | { |
11276 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11277 | enum pipe pipe; | |
24929352 DV |
11278 | struct intel_crtc *crtc; |
11279 | struct intel_encoder *encoder; | |
11280 | struct intel_connector *connector; | |
5358901f | 11281 | int i; |
24929352 | 11282 | |
0e8ffe1b DV |
11283 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
11284 | base.head) { | |
88adfff1 | 11285 | memset(&crtc->config, 0, sizeof(crtc->config)); |
3b117c8f | 11286 | |
0e8ffe1b DV |
11287 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
11288 | &crtc->config); | |
24929352 DV |
11289 | |
11290 | crtc->base.enabled = crtc->active; | |
4c445e0e | 11291 | crtc->primary_enabled = crtc->active; |
24929352 DV |
11292 | |
11293 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
11294 | crtc->base.base.id, | |
11295 | crtc->active ? "enabled" : "disabled"); | |
11296 | } | |
11297 | ||
5358901f | 11298 | /* FIXME: Smash this into the new shared dpll infrastructure. */ |
affa9354 | 11299 | if (HAS_DDI(dev)) |
6441ab5f PZ |
11300 | intel_ddi_setup_hw_pll_state(dev); |
11301 | ||
5358901f DV |
11302 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
11303 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
11304 | ||
11305 | pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state); | |
11306 | pll->active = 0; | |
11307 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
11308 | base.head) { | |
11309 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
11310 | pll->active++; | |
11311 | } | |
11312 | pll->refcount = pll->active; | |
11313 | ||
35c95375 DV |
11314 | DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n", |
11315 | pll->name, pll->refcount, pll->on); | |
5358901f DV |
11316 | } |
11317 | ||
24929352 DV |
11318 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
11319 | base.head) { | |
11320 | pipe = 0; | |
11321 | ||
11322 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
11323 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
11324 | encoder->base.crtc = &crtc->base; | |
1d37b689 | 11325 | encoder->get_config(encoder, &crtc->config); |
24929352 DV |
11326 | } else { |
11327 | encoder->base.crtc = NULL; | |
11328 | } | |
11329 | ||
11330 | encoder->connectors_active = false; | |
6f2bcceb | 11331 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 DV |
11332 | encoder->base.base.id, |
11333 | drm_get_encoder_name(&encoder->base), | |
11334 | encoder->base.crtc ? "enabled" : "disabled", | |
6f2bcceb | 11335 | pipe_name(pipe)); |
24929352 DV |
11336 | } |
11337 | ||
11338 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
11339 | base.head) { | |
11340 | if (connector->get_hw_state(connector)) { | |
11341 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
11342 | connector->encoder->connectors_active = true; | |
11343 | connector->base.encoder = &connector->encoder->base; | |
11344 | } else { | |
11345 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
11346 | connector->base.encoder = NULL; | |
11347 | } | |
11348 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
11349 | connector->base.base.id, | |
11350 | drm_get_connector_name(&connector->base), | |
11351 | connector->base.encoder ? "enabled" : "disabled"); | |
11352 | } | |
30e984df DV |
11353 | } |
11354 | ||
11355 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm | |
11356 | * and i915 state tracking structures. */ | |
11357 | void intel_modeset_setup_hw_state(struct drm_device *dev, | |
11358 | bool force_restore) | |
11359 | { | |
11360 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11361 | enum pipe pipe; | |
30e984df DV |
11362 | struct intel_crtc *crtc; |
11363 | struct intel_encoder *encoder; | |
35c95375 | 11364 | int i; |
30e984df DV |
11365 | |
11366 | intel_modeset_readout_hw_state(dev); | |
24929352 | 11367 | |
babea61d JB |
11368 | /* |
11369 | * Now that we have the config, copy it to each CRTC struct | |
11370 | * Note that this could go away if we move to using crtc_config | |
11371 | * checking everywhere. | |
11372 | */ | |
11373 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
11374 | base.head) { | |
d330a953 | 11375 | if (crtc->active && i915.fastboot) { |
babea61d JB |
11376 | intel_crtc_mode_from_pipe_config(crtc, &crtc->config); |
11377 | ||
11378 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", | |
11379 | crtc->base.base.id); | |
11380 | drm_mode_debug_printmodeline(&crtc->base.mode); | |
11381 | } | |
11382 | } | |
11383 | ||
24929352 DV |
11384 | /* HW state is read out, now we need to sanitize this mess. */ |
11385 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
11386 | base.head) { | |
11387 | intel_sanitize_encoder(encoder); | |
11388 | } | |
11389 | ||
11390 | for_each_pipe(pipe) { | |
11391 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
11392 | intel_sanitize_crtc(crtc); | |
c0b03411 | 11393 | intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]"); |
24929352 | 11394 | } |
9a935856 | 11395 | |
35c95375 DV |
11396 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
11397 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
11398 | ||
11399 | if (!pll->on || pll->active) | |
11400 | continue; | |
11401 | ||
11402 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
11403 | ||
11404 | pll->disable(dev_priv, pll); | |
11405 | pll->on = false; | |
11406 | } | |
11407 | ||
96f90c54 | 11408 | if (HAS_PCH_SPLIT(dev)) |
243e6a44 VS |
11409 | ilk_wm_get_hw_state(dev); |
11410 | ||
45e2b5f6 | 11411 | if (force_restore) { |
7d0bc1ea VS |
11412 | i915_redisable_vga(dev); |
11413 | ||
f30da187 DV |
11414 | /* |
11415 | * We need to use raw interfaces for restoring state to avoid | |
11416 | * checking (bogus) intermediate states. | |
11417 | */ | |
45e2b5f6 | 11418 | for_each_pipe(pipe) { |
b5644d05 JB |
11419 | struct drm_crtc *crtc = |
11420 | dev_priv->pipe_to_crtc_mapping[pipe]; | |
f30da187 DV |
11421 | |
11422 | __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, | |
11423 | crtc->fb); | |
45e2b5f6 DV |
11424 | } |
11425 | } else { | |
11426 | intel_modeset_update_staged_output_state(dev); | |
11427 | } | |
8af6cf88 DV |
11428 | |
11429 | intel_modeset_check_state(dev); | |
2c7111db CW |
11430 | } |
11431 | ||
11432 | void intel_modeset_gem_init(struct drm_device *dev) | |
11433 | { | |
1833b134 | 11434 | intel_modeset_init_hw(dev); |
02e792fb DV |
11435 | |
11436 | intel_setup_overlay(dev); | |
24929352 | 11437 | |
7ad228b1 | 11438 | mutex_lock(&dev->mode_config.mutex); |
45e2b5f6 | 11439 | intel_modeset_setup_hw_state(dev, false); |
7ad228b1 | 11440 | mutex_unlock(&dev->mode_config.mutex); |
79e53945 JB |
11441 | } |
11442 | ||
11443 | void intel_modeset_cleanup(struct drm_device *dev) | |
11444 | { | |
652c393a JB |
11445 | struct drm_i915_private *dev_priv = dev->dev_private; |
11446 | struct drm_crtc *crtc; | |
d9255d57 | 11447 | struct drm_connector *connector; |
652c393a | 11448 | |
fd0c0642 DV |
11449 | /* |
11450 | * Interrupts and polling as the first thing to avoid creating havoc. | |
11451 | * Too much stuff here (turning of rps, connectors, ...) would | |
11452 | * experience fancy races otherwise. | |
11453 | */ | |
11454 | drm_irq_uninstall(dev); | |
11455 | cancel_work_sync(&dev_priv->hotplug_work); | |
11456 | /* | |
11457 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
11458 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
11459 | */ | |
f87ea761 | 11460 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 11461 | |
652c393a JB |
11462 | mutex_lock(&dev->struct_mutex); |
11463 | ||
723bfd70 JB |
11464 | intel_unregister_dsm_handler(); |
11465 | ||
652c393a JB |
11466 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
11467 | /* Skip inactive CRTCs */ | |
11468 | if (!crtc->fb) | |
11469 | continue; | |
11470 | ||
3dec0095 | 11471 | intel_increase_pllclock(crtc); |
652c393a JB |
11472 | } |
11473 | ||
973d04f9 | 11474 | intel_disable_fbc(dev); |
e70236a8 | 11475 | |
8090c6b9 | 11476 | intel_disable_gt_powersave(dev); |
0cdab21f | 11477 | |
930ebb46 DV |
11478 | ironlake_teardown_rc6(dev); |
11479 | ||
69341a5e KH |
11480 | mutex_unlock(&dev->struct_mutex); |
11481 | ||
1630fe75 CW |
11482 | /* flush any delayed tasks or pending work */ |
11483 | flush_scheduled_work(); | |
11484 | ||
db31af1d JN |
11485 | /* destroy the backlight and sysfs files before encoders/connectors */ |
11486 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
11487 | intel_panel_destroy_backlight(connector); | |
d9255d57 | 11488 | drm_sysfs_connector_remove(connector); |
db31af1d | 11489 | } |
d9255d57 | 11490 | |
79e53945 | 11491 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
11492 | |
11493 | intel_cleanup_overlay(dev); | |
79e53945 JB |
11494 | } |
11495 | ||
f1c79df3 ZW |
11496 | /* |
11497 | * Return which encoder is currently attached for connector. | |
11498 | */ | |
df0e9248 | 11499 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 11500 | { |
df0e9248 CW |
11501 | return &intel_attached_encoder(connector)->base; |
11502 | } | |
f1c79df3 | 11503 | |
df0e9248 CW |
11504 | void intel_connector_attach_encoder(struct intel_connector *connector, |
11505 | struct intel_encoder *encoder) | |
11506 | { | |
11507 | connector->encoder = encoder; | |
11508 | drm_mode_connector_attach_encoder(&connector->base, | |
11509 | &encoder->base); | |
79e53945 | 11510 | } |
28d52043 DA |
11511 | |
11512 | /* | |
11513 | * set vga decode state - true == enable VGA decode | |
11514 | */ | |
11515 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
11516 | { | |
11517 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 11518 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
11519 | u16 gmch_ctrl; |
11520 | ||
75fa041d CW |
11521 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
11522 | DRM_ERROR("failed to read control word\n"); | |
11523 | return -EIO; | |
11524 | } | |
11525 | ||
c0cc8a55 CW |
11526 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
11527 | return 0; | |
11528 | ||
28d52043 DA |
11529 | if (state) |
11530 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
11531 | else | |
11532 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
11533 | |
11534 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
11535 | DRM_ERROR("failed to write control word\n"); | |
11536 | return -EIO; | |
11537 | } | |
11538 | ||
28d52043 DA |
11539 | return 0; |
11540 | } | |
c4a1d9e4 | 11541 | |
c4a1d9e4 | 11542 | struct intel_display_error_state { |
ff57f1b0 PZ |
11543 | |
11544 | u32 power_well_driver; | |
11545 | ||
63b66e5b CW |
11546 | int num_transcoders; |
11547 | ||
c4a1d9e4 CW |
11548 | struct intel_cursor_error_state { |
11549 | u32 control; | |
11550 | u32 position; | |
11551 | u32 base; | |
11552 | u32 size; | |
52331309 | 11553 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
11554 | |
11555 | struct intel_pipe_error_state { | |
ddf9c536 | 11556 | bool power_domain_on; |
c4a1d9e4 | 11557 | u32 source; |
52331309 | 11558 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
11559 | |
11560 | struct intel_plane_error_state { | |
11561 | u32 control; | |
11562 | u32 stride; | |
11563 | u32 size; | |
11564 | u32 pos; | |
11565 | u32 addr; | |
11566 | u32 surface; | |
11567 | u32 tile_offset; | |
52331309 | 11568 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
11569 | |
11570 | struct intel_transcoder_error_state { | |
ddf9c536 | 11571 | bool power_domain_on; |
63b66e5b CW |
11572 | enum transcoder cpu_transcoder; |
11573 | ||
11574 | u32 conf; | |
11575 | ||
11576 | u32 htotal; | |
11577 | u32 hblank; | |
11578 | u32 hsync; | |
11579 | u32 vtotal; | |
11580 | u32 vblank; | |
11581 | u32 vsync; | |
11582 | } transcoder[4]; | |
c4a1d9e4 CW |
11583 | }; |
11584 | ||
11585 | struct intel_display_error_state * | |
11586 | intel_display_capture_error_state(struct drm_device *dev) | |
11587 | { | |
0206e353 | 11588 | drm_i915_private_t *dev_priv = dev->dev_private; |
c4a1d9e4 | 11589 | struct intel_display_error_state *error; |
63b66e5b CW |
11590 | int transcoders[] = { |
11591 | TRANSCODER_A, | |
11592 | TRANSCODER_B, | |
11593 | TRANSCODER_C, | |
11594 | TRANSCODER_EDP, | |
11595 | }; | |
c4a1d9e4 CW |
11596 | int i; |
11597 | ||
63b66e5b CW |
11598 | if (INTEL_INFO(dev)->num_pipes == 0) |
11599 | return NULL; | |
11600 | ||
9d1cb914 | 11601 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
11602 | if (error == NULL) |
11603 | return NULL; | |
11604 | ||
190be112 | 11605 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
11606 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
11607 | ||
52331309 | 11608 | for_each_pipe(i) { |
ddf9c536 ID |
11609 | error->pipe[i].power_domain_on = |
11610 | intel_display_power_enabled_sw(dev, POWER_DOMAIN_PIPE(i)); | |
11611 | if (!error->pipe[i].power_domain_on) | |
9d1cb914 PZ |
11612 | continue; |
11613 | ||
a18c4c3d PZ |
11614 | if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) { |
11615 | error->cursor[i].control = I915_READ(CURCNTR(i)); | |
11616 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
11617 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
11618 | } else { | |
11619 | error->cursor[i].control = I915_READ(CURCNTR_IVB(i)); | |
11620 | error->cursor[i].position = I915_READ(CURPOS_IVB(i)); | |
11621 | error->cursor[i].base = I915_READ(CURBASE_IVB(i)); | |
11622 | } | |
c4a1d9e4 CW |
11623 | |
11624 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
11625 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 11626 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 11627 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
11628 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
11629 | } | |
ca291363 PZ |
11630 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
11631 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
11632 | if (INTEL_INFO(dev)->gen >= 4) { |
11633 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
11634 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
11635 | } | |
11636 | ||
c4a1d9e4 | 11637 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
63b66e5b CW |
11638 | } |
11639 | ||
11640 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
11641 | if (HAS_DDI(dev_priv->dev)) | |
11642 | error->num_transcoders++; /* Account for eDP. */ | |
11643 | ||
11644 | for (i = 0; i < error->num_transcoders; i++) { | |
11645 | enum transcoder cpu_transcoder = transcoders[i]; | |
11646 | ||
ddf9c536 | 11647 | error->transcoder[i].power_domain_on = |
38cc1daf PZ |
11648 | intel_display_power_enabled_sw(dev, |
11649 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); | |
ddf9c536 | 11650 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
11651 | continue; |
11652 | ||
63b66e5b CW |
11653 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
11654 | ||
11655 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
11656 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
11657 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
11658 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
11659 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
11660 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
11661 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
11662 | } |
11663 | ||
11664 | return error; | |
11665 | } | |
11666 | ||
edc3d884 MK |
11667 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
11668 | ||
c4a1d9e4 | 11669 | void |
edc3d884 | 11670 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
11671 | struct drm_device *dev, |
11672 | struct intel_display_error_state *error) | |
11673 | { | |
11674 | int i; | |
11675 | ||
63b66e5b CW |
11676 | if (!error) |
11677 | return; | |
11678 | ||
edc3d884 | 11679 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 11680 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 11681 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 11682 | error->power_well_driver); |
52331309 | 11683 | for_each_pipe(i) { |
edc3d884 | 11684 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 ID |
11685 | err_printf(m, " Power: %s\n", |
11686 | error->pipe[i].power_domain_on ? "on" : "off"); | |
edc3d884 | 11687 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
edc3d884 MK |
11688 | |
11689 | err_printf(m, "Plane [%d]:\n", i); | |
11690 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
11691 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 11692 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
11693 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
11694 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 11695 | } |
4b71a570 | 11696 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 11697 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 11698 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
11699 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
11700 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
11701 | } |
11702 | ||
edc3d884 MK |
11703 | err_printf(m, "Cursor [%d]:\n", i); |
11704 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
11705 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
11706 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 11707 | } |
63b66e5b CW |
11708 | |
11709 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 11710 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 11711 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 ID |
11712 | err_printf(m, " Power: %s\n", |
11713 | error->transcoder[i].power_domain_on ? "on" : "off"); | |
63b66e5b CW |
11714 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
11715 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
11716 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
11717 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
11718 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
11719 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
11720 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
11721 | } | |
c4a1d9e4 | 11722 | } |