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drm/i915: don't assert_panel_unlocked on LPT
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
32f9d658
ZW		 44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
0206e353 46bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 47static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 48static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 49
50typedef struct {
0206e353
AJ		 51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
79e53945
JB		 60} intel_clock_t;
61
62typedef struct {
0206e353 63 int min, max;
79e53945
JB		 64} intel_range_t;
65
66typedef struct {
0206e353
AJ		 67 int dot_limit;
68 int p2_slow, p2_fast;
79e53945
JB		 69} intel_p2_t;
70
71#define INTEL_P2_NUM 2
d4906093
ML		 72typedef struct intel_limit intel_limit_t;
73struct intel_limit {
0206e353
AJ		 74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 77 int, int, intel_clock_t *, intel_clock_t *);
d4906093 78};
79e53945 79
2377b741
JB		 80/* FDI */
81#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
d2acd215
DV		 83int
84intel_pch_rawclk(struct drm_device *dev)
85{
86 struct drm_i915_private *dev_priv = dev->dev_private;
87
88 WARN_ON(!HAS_PCH_SPLIT(dev));
89
90 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
91}
92
d4906093
ML		 93static bool
94intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 95 int target, int refclk, intel_clock_t *match_clock,
96 intel_clock_t *best_clock);
d4906093
ML		 97static bool
98intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 99 int target, int refclk, intel_clock_t *match_clock,
100 intel_clock_t *best_clock);
79e53945 101
a4fc5ed6
KP		 102static bool
103intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 104 int target, int refclk, intel_clock_t *match_clock,
105 intel_clock_t *best_clock);
5eb08b69 106static bool
f2b115e6 107intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 108 int target, int refclk, intel_clock_t *match_clock,
109 intel_clock_t *best_clock);
a4fc5ed6 110
a0c4da24
JB		 111static bool
112intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
113 int target, int refclk, intel_clock_t *match_clock,
114 intel_clock_t *best_clock);
115
021357ac
CW		 116static inline u32 /* units of 100MHz */
117intel_fdi_link_freq(struct drm_device *dev)
118{
8b99e68c
CW		 119 if (IS_GEN5(dev)) {
120 struct drm_i915_private *dev_priv = dev->dev_private;
121 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
122 } else
123 return 27;
021357ac
CW		 124}
125
e4b36699 126static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 127 .dot = { .min = 25000, .max = 350000 },
128 .vco = { .min = 930000, .max = 1400000 },
129 .n = { .min = 3, .max = 16 },
130 .m = { .min = 96, .max = 140 },
131 .m1 = { .min = 18, .max = 26 },
132 .m2 = { .min = 6, .max = 16 },
133 .p = { .min = 4, .max = 128 },
134 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 135 .p2 = { .dot_limit = 165000,
136 .p2_slow = 4, .p2_fast = 2 },
d4906093 137 .find_pll = intel_find_best_PLL,
e4b36699
KP		 138};
139
140static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 141 .dot = { .min = 25000, .max = 350000 },
142 .vco = { .min = 930000, .max = 1400000 },
143 .n = { .min = 3, .max = 16 },
144 .m = { .min = 96, .max = 140 },
145 .m1 = { .min = 18, .max = 26 },
146 .m2 = { .min = 6, .max = 16 },
147 .p = { .min = 4, .max = 128 },
148 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 149 .p2 = { .dot_limit = 165000,
150 .p2_slow = 14, .p2_fast = 7 },
d4906093 151 .find_pll = intel_find_best_PLL,
e4b36699 152};
273e27ca 153
e4b36699 154static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 155 .dot = { .min = 20000, .max = 400000 },
156 .vco = { .min = 1400000, .max = 2800000 },
157 .n = { .min = 1, .max = 6 },
158 .m = { .min = 70, .max = 120 },
159 .m1 = { .min = 10, .max = 22 },
160 .m2 = { .min = 5, .max = 9 },
161 .p = { .min = 5, .max = 80 },
162 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 163 .p2 = { .dot_limit = 200000,
164 .p2_slow = 10, .p2_fast = 5 },
d4906093 165 .find_pll = intel_find_best_PLL,
e4b36699
KP		 166};
167
168static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 169 .dot = { .min = 20000, .max = 400000 },
170 .vco = { .min = 1400000, .max = 2800000 },
171 .n = { .min = 1, .max = 6 },
172 .m = { .min = 70, .max = 120 },
173 .m1 = { .min = 10, .max = 22 },
174 .m2 = { .min = 5, .max = 9 },
175 .p = { .min = 7, .max = 98 },
176 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 177 .p2 = { .dot_limit = 112000,
178 .p2_slow = 14, .p2_fast = 7 },
d4906093 179 .find_pll = intel_find_best_PLL,
e4b36699
KP		 180};
181
273e27ca 182
e4b36699 183static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 184 .dot = { .min = 25000, .max = 270000 },
185 .vco = { .min = 1750000, .max = 3500000},
186 .n = { .min = 1, .max = 4 },
187 .m = { .min = 104, .max = 138 },
188 .m1 = { .min = 17, .max = 23 },
189 .m2 = { .min = 5, .max = 11 },
190 .p = { .min = 10, .max = 30 },
191 .p1 = { .min = 1, .max = 3},
192 .p2 = { .dot_limit = 270000,
193 .p2_slow = 10,
194 .p2_fast = 10
044c7c41 195 },
d4906093 196 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 197};
198
199static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 200 .dot = { .min = 22000, .max = 400000 },
201 .vco = { .min = 1750000, .max = 3500000},
202 .n = { .min = 1, .max = 4 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 16, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 5, .max = 80 },
207 .p1 = { .min = 1, .max = 8},
208 .p2 = { .dot_limit = 165000,
209 .p2_slow = 10, .p2_fast = 5 },
d4906093 210 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 211};
212
213static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 214 .dot = { .min = 20000, .max = 115000 },
215 .vco = { .min = 1750000, .max = 3500000 },
216 .n = { .min = 1, .max = 3 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 17, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 28, .max = 112 },
221 .p1 = { .min = 2, .max = 8 },
222 .p2 = { .dot_limit = 0,
223 .p2_slow = 14, .p2_fast = 14
044c7c41 224 },
d4906093 225 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 226};
227
228static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 229 .dot = { .min = 80000, .max = 224000 },
230 .vco = { .min = 1750000, .max = 3500000 },
231 .n = { .min = 1, .max = 3 },
232 .m = { .min = 104, .max = 138 },
233 .m1 = { .min = 17, .max = 23 },
234 .m2 = { .min = 5, .max = 11 },
235 .p = { .min = 14, .max = 42 },
236 .p1 = { .min = 2, .max = 6 },
237 .p2 = { .dot_limit = 0,
238 .p2_slow = 7, .p2_fast = 7
044c7c41 239 },
d4906093 240 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 241};
242
243static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 244 .dot = { .min = 161670, .max = 227000 },
245 .vco = { .min = 1750000, .max = 3500000},
246 .n = { .min = 1, .max = 2 },
247 .m = { .min = 97, .max = 108 },
248 .m1 = { .min = 0x10, .max = 0x12 },
249 .m2 = { .min = 0x05, .max = 0x06 },
250 .p = { .min = 10, .max = 20 },
251 .p1 = { .min = 1, .max = 2},
252 .p2 = { .dot_limit = 0,
273e27ca 253 .p2_slow = 10, .p2_fast = 10 },
0206e353 254 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 255};
256
f2b115e6 257static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 258 .dot = { .min = 20000, .max = 400000},
259 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 260 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 261 .n = { .min = 3, .max = 6 },
262 .m = { .min = 2, .max = 256 },
273e27ca 263 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 264 .m1 = { .min = 0, .max = 0 },
265 .m2 = { .min = 0, .max = 254 },
266 .p = { .min = 5, .max = 80 },
267 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 268 .p2 = { .dot_limit = 200000,
269 .p2_slow = 10, .p2_fast = 5 },
6115707b 270 .find_pll = intel_find_best_PLL,
e4b36699
KP		 271};
272
f2b115e6 273static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 274 .dot = { .min = 20000, .max = 400000 },
275 .vco = { .min = 1700000, .max = 3500000 },
276 .n = { .min = 3, .max = 6 },
277 .m = { .min = 2, .max = 256 },
278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 7, .max = 112 },
281 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 282 .p2 = { .dot_limit = 112000,
283 .p2_slow = 14, .p2_fast = 14 },
6115707b 284 .find_pll = intel_find_best_PLL,
e4b36699
KP		 285};
286
273e27ca
EA		 287/* Ironlake / Sandybridge
288 *
289 * We calculate clock using (register_value + 2) for N/M1/M2, so here
290 * the range value for them is (actual_value - 2).
291 */
b91ad0ec 292static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 293 .dot = { .min = 25000, .max = 350000 },
294 .vco = { .min = 1760000, .max = 3510000 },
295 .n = { .min = 1, .max = 5 },
296 .m = { .min = 79, .max = 127 },
297 .m1 = { .min = 12, .max = 22 },
298 .m2 = { .min = 5, .max = 9 },
299 .p = { .min = 5, .max = 80 },
300 .p1 = { .min = 1, .max = 8 },
301 .p2 = { .dot_limit = 225000,
302 .p2_slow = 10, .p2_fast = 5 },
4547668a 303 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 304};
305
b91ad0ec 306static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 3 },
310 .m = { .min = 79, .max = 118 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 28, .max = 112 },
314 .p1 = { .min = 2, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 317 .find_pll = intel_g4x_find_best_PLL,
318};
319
320static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 127 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 14, .max = 56 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 331 .find_pll = intel_g4x_find_best_PLL,
332};
333
273e27ca 334/* LVDS 100mhz refclk limits. */
b91ad0ec 335static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 336 .dot = { .min = 25000, .max = 350000 },
337 .vco = { .min = 1760000, .max = 3510000 },
338 .n = { .min = 1, .max = 2 },
339 .m = { .min = 79, .max = 126 },
340 .m1 = { .min = 12, .max = 22 },
341 .m2 = { .min = 5, .max = 9 },
342 .p = { .min = 28, .max = 112 },
0206e353 343 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 344 .p2 = { .dot_limit = 225000,
345 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 346 .find_pll = intel_g4x_find_best_PLL,
347};
348
349static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000 },
352 .n = { .min = 1, .max = 3 },
353 .m = { .min = 79, .max = 126 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 14, .max = 42 },
0206e353 357 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 358 .p2 = { .dot_limit = 225000,
359 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 360 .find_pll = intel_g4x_find_best_PLL,
361};
362
363static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 364 .dot = { .min = 25000, .max = 350000 },
365 .vco = { .min = 1760000, .max = 3510000},
366 .n = { .min = 1, .max = 2 },
367 .m = { .min = 81, .max = 90 },
368 .m1 = { .min = 12, .max = 22 },
369 .m2 = { .min = 5, .max = 9 },
370 .p = { .min = 10, .max = 20 },
371 .p1 = { .min = 1, .max = 2},
372 .p2 = { .dot_limit = 0,
273e27ca 373 .p2_slow = 10, .p2_fast = 10 },
0206e353 374 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 375};
376
a0c4da24
JB		 377static const intel_limit_t intel_limits_vlv_dac = {
378 .dot = { .min = 25000, .max = 270000 },
379 .vco = { .min = 4000000, .max = 6000000 },
380 .n = { .min = 1, .max = 7 },
381 .m = { .min = 22, .max = 450 }, /* guess */
382 .m1 = { .min = 2, .max = 3 },
383 .m2 = { .min = 11, .max = 156 },
384 .p = { .min = 10, .max = 30 },
385 .p1 = { .min = 2, .max = 3 },
386 .p2 = { .dot_limit = 270000,
387 .p2_slow = 2, .p2_fast = 20 },
388 .find_pll = intel_vlv_find_best_pll,
389};
390
391static const intel_limit_t intel_limits_vlv_hdmi = {
392 .dot = { .min = 20000, .max = 165000 },
17dc9257 393 .vco = { .min = 4000000, .max = 5994000},
a0c4da24
JB		 394 .n = { .min = 1, .max = 7 },
395 .m = { .min = 60, .max = 300 }, /* guess */
396 .m1 = { .min = 2, .max = 3 },
397 .m2 = { .min = 11, .max = 156 },
398 .p = { .min = 10, .max = 30 },
399 .p1 = { .min = 2, .max = 3 },
400 .p2 = { .dot_limit = 270000,
401 .p2_slow = 2, .p2_fast = 20 },
402 .find_pll = intel_vlv_find_best_pll,
403};
404
405static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 406 .dot = { .min = 25000, .max = 270000 },
407 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 408 .n = { .min = 1, .max = 7 },
74a4dd2e 409 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 410 .m1 = { .min = 2, .max = 3 },
411 .m2 = { .min = 11, .max = 156 },
412 .p = { .min = 10, .max = 30 },
413 .p1 = { .min = 2, .max = 3 },
414 .p2 = { .dot_limit = 270000,
415 .p2_slow = 2, .p2_fast = 20 },
416 .find_pll = intel_vlv_find_best_pll,
417};
418
57f350b6
JB		 419u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
420{
421 unsigned long flags;
422 u32 val = 0;
423
424 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
425 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
426 DRM_ERROR("DPIO idle wait timed out\n");
427 goto out_unlock;
428 }
429
430 I915_WRITE(DPIO_REG, reg);
431 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
432 DPIO_BYTE);
433 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
434 DRM_ERROR("DPIO read wait timed out\n");
435 goto out_unlock;
436 }
437 val = I915_READ(DPIO_DATA);
438
439out_unlock:
440 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
441 return val;
442}
443
a0c4da24
JB		 444static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
445 u32 val)
446{
447 unsigned long flags;
448
449 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
450 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
451 DRM_ERROR("DPIO idle wait timed out\n");
452 goto out_unlock;
453 }
454
455 I915_WRITE(DPIO_DATA, val);
456 I915_WRITE(DPIO_REG, reg);
457 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
458 DPIO_BYTE);
459 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
460 DRM_ERROR("DPIO write wait timed out\n");
461
462out_unlock:
463 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
464}
465
57f350b6
JB		 466static void vlv_init_dpio(struct drm_device *dev)
467{
468 struct drm_i915_private *dev_priv = dev->dev_private;
469
470 /* Reset the DPIO config */
471 I915_WRITE(DPIO_CTL, 0);
472 POSTING_READ(DPIO_CTL);
473 I915_WRITE(DPIO_CTL, 1);
474 POSTING_READ(DPIO_CTL);
475}
476
618563e3
DV		 477static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
478{
479 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
480 return 1;
481}
482
483static const struct dmi_system_id intel_dual_link_lvds[] = {
484 {
485 .callback = intel_dual_link_lvds_callback,
486 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
487 .matches = {
488 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
489 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
490 },
491 },
492 { } /* terminating entry */
493};
494
b0354385
TI		 495static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
496 unsigned int reg)
497{
498 unsigned int val;
499
121d527a
TI		 500 /* use the module option value if specified */
501 if (i915_lvds_channel_mode > 0)
502 return i915_lvds_channel_mode == 2;
503
618563e3
DV		 504 if (dmi_check_system(intel_dual_link_lvds))
505 return true;
506
b0354385
TI		 507 if (dev_priv->lvds_val)
508 val = dev_priv->lvds_val;
509 else {
510 /* BIOS should set the proper LVDS register value at boot, but
511 * in reality, it doesn't set the value when the lid is closed;
512 * we need to check "the value to be set" in VBT when LVDS
513 * register is uninitialized.
514 */
515 val = I915_READ(reg);
14d94a3d 516 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
b0354385
TI		 517 val = dev_priv->bios_lvds_val;
518 dev_priv->lvds_val = val;
519 }
520 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
521}
522
1b894b59
CW		 523static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
524 int refclk)
2c07245f 525{
b91ad0ec
ZW		 526 struct drm_device *dev = crtc->dev;
527 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 528 const intel_limit_t *limit;
b91ad0ec
ZW		 529
530 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 531 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
b91ad0ec 532 /* LVDS dual channel */
1b894b59 533 if (refclk == 100000)
b91ad0ec
ZW		 534 limit = &intel_limits_ironlake_dual_lvds_100m;
535 else
536 limit = &intel_limits_ironlake_dual_lvds;
537 } else {
1b894b59 538 if (refclk == 100000)
b91ad0ec
ZW		 539 limit = &intel_limits_ironlake_single_lvds_100m;
540 else
541 limit = &intel_limits_ironlake_single_lvds;
542 }
543 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 544 HAS_eDP)
545 limit = &intel_limits_ironlake_display_port;
2c07245f 546 else
b91ad0ec 547 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 548
549 return limit;
550}
551
044c7c41
ML		 552static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
553{
554 struct drm_device *dev = crtc->dev;
555 struct drm_i915_private *dev_priv = dev->dev_private;
556 const intel_limit_t *limit;
557
558 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 559 if (is_dual_link_lvds(dev_priv, LVDS))
044c7c41 560 /* LVDS with dual channel */
e4b36699 561 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 562 else
563 /* LVDS with dual channel */
e4b36699 564 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 565 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
566 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 567 limit = &intel_limits_g4x_hdmi;
044c7c41 568 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 569 limit = &intel_limits_g4x_sdvo;
0206e353 570 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 571 limit = &intel_limits_g4x_display_port;
044c7c41 572 } else /* The option is for other outputs */
e4b36699 573 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 574
575 return limit;
576}
577
1b894b59 578static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 579{
580 struct drm_device *dev = crtc->dev;
581 const intel_limit_t *limit;
582
bad720ff 583 if (HAS_PCH_SPLIT(dev))
1b894b59 584 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 585 else if (IS_G4X(dev)) {
044c7c41 586 limit = intel_g4x_limit(crtc);
f2b115e6 587 } else if (IS_PINEVIEW(dev)) {
2177832f 588 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 589 limit = &intel_limits_pineview_lvds;
2177832f 590 else
f2b115e6 591 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 592 } else if (IS_VALLEYVIEW(dev)) {
593 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
594 limit = &intel_limits_vlv_dac;
595 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
596 limit = &intel_limits_vlv_hdmi;
597 else
598 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 599 } else if (!IS_GEN2(dev)) {
600 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
601 limit = &intel_limits_i9xx_lvds;
602 else
603 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 604 } else {
605 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 606 limit = &intel_limits_i8xx_lvds;
79e53945 607 else
e4b36699 608 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 609 }
610 return limit;
611}
612
f2b115e6
AJ		 613/* m1 is reserved as 0 in Pineview, n is a ring counter */
614static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 615{
2177832f
SL		 616 clock->m = clock->m2 + 2;
617 clock->p = clock->p1 * clock->p2;
618 clock->vco = refclk * clock->m / clock->n;
619 clock->dot = clock->vco / clock->p;
620}
621
622static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
623{
f2b115e6
AJ		 624 if (IS_PINEVIEW(dev)) {
625 pineview_clock(refclk, clock);
2177832f
SL		 626 return;
627 }
79e53945
JB		 628 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
629 clock->p = clock->p1 * clock->p2;
630 clock->vco = refclk * clock->m / (clock->n + 2);
631 clock->dot = clock->vco / clock->p;
632}
633
79e53945
JB		 634/**
635 * Returns whether any output on the specified pipe is of the specified type
636 */
4ef69c7a 637bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 638{
4ef69c7a 639 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 640 struct intel_encoder *encoder;
641
6c2b7c12
DV		 642 for_each_encoder_on_crtc(dev, crtc, encoder)
643 if (encoder->type == type)
4ef69c7a
CW		 644 return true;
645
646 return false;
79e53945
JB		 647}
648
7c04d1d9 649#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 650/**
651 * Returns whether the given set of divisors are valid for a given refclk with
652 * the given connectors.
653 */
654
1b894b59
CW		 655static bool intel_PLL_is_valid(struct drm_device *dev,
656 const intel_limit_t *limit,
657 const intel_clock_t *clock)
79e53945 658{
79e53945 659 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 660 INTELPllInvalid("p1 out of range\n");
79e53945 661 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 662 INTELPllInvalid("p out of range\n");
79e53945 663 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 664 INTELPllInvalid("m2 out of range\n");
79e53945 665 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 666 INTELPllInvalid("m1 out of range\n");
f2b115e6 667 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 668 INTELPllInvalid("m1 <= m2\n");
79e53945 669 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 670 INTELPllInvalid("m out of range\n");
79e53945 671 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 672 INTELPllInvalid("n out of range\n");
79e53945 673 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 674 INTELPllInvalid("vco out of range\n");
79e53945
JB		 675 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
676 * connector, etc., rather than just a single range.
677 */
678 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 679 INTELPllInvalid("dot out of range\n");
79e53945
JB		 680
681 return true;
682}
683
d4906093
ML		 684static bool
685intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 686 int target, int refclk, intel_clock_t *match_clock,
687 intel_clock_t *best_clock)
d4906093 688
79e53945
JB		 689{
690 struct drm_device *dev = crtc->dev;
691 struct drm_i915_private *dev_priv = dev->dev_private;
692 intel_clock_t clock;
79e53945
JB		 693 int err = target;
694
bc5e5718 695 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 696 (I915_READ(LVDS)) != 0) {
79e53945
JB		 697 /*
698 * For LVDS, if the panel is on, just rely on its current
699 * settings for dual-channel. We haven't figured out how to
700 * reliably set up different single/dual channel state, if we
701 * even can.
702 */
b0354385 703 if (is_dual_link_lvds(dev_priv, LVDS))
79e53945
JB		 704 clock.p2 = limit->p2.p2_fast;
705 else
706 clock.p2 = limit->p2.p2_slow;
707 } else {
708 if (target < limit->p2.dot_limit)
709 clock.p2 = limit->p2.p2_slow;
710 else
711 clock.p2 = limit->p2.p2_fast;
712 }
713
0206e353 714 memset(best_clock, 0, sizeof(*best_clock));
79e53945 715
42158660
ZY		 716 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
717 clock.m1++) {
718 for (clock.m2 = limit->m2.min;
719 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 720 /* m1 is always 0 in Pineview */
721 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 722 break;
723 for (clock.n = limit->n.min;
724 clock.n <= limit->n.max; clock.n++) {
725 for (clock.p1 = limit->p1.min;
726 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 727 int this_err;
728
2177832f 729 intel_clock(dev, refclk, &clock);
1b894b59
CW		 730 if (!intel_PLL_is_valid(dev, limit,
731 &clock))
79e53945 732 continue;
cec2f356
SP		 733 if (match_clock &&
734 clock.p != match_clock->p)
735 continue;
79e53945
JB		 736
737 this_err = abs(clock.dot - target);
738 if (this_err < err) {
739 *best_clock = clock;
740 err = this_err;
741 }
742 }
743 }
744 }
745 }
746
747 return (err != target);
748}
749
d4906093
ML		 750static bool
751intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 752 int target, int refclk, intel_clock_t *match_clock,
753 intel_clock_t *best_clock)
d4906093
ML		 754{
755 struct drm_device *dev = crtc->dev;
756 struct drm_i915_private *dev_priv = dev->dev_private;
757 intel_clock_t clock;
758 int max_n;
759 bool found;
6ba770dc
AJ		 760 /* approximately equals target * 0.00585 */
761 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 762 found = false;
763
764 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 765 int lvds_reg;
766
c619eed4 767 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 768 lvds_reg = PCH_LVDS;
769 else
770 lvds_reg = LVDS;
771 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 772 LVDS_CLKB_POWER_UP)
773 clock.p2 = limit->p2.p2_fast;
774 else
775 clock.p2 = limit->p2.p2_slow;
776 } else {
777 if (target < limit->p2.dot_limit)
778 clock.p2 = limit->p2.p2_slow;
779 else
780 clock.p2 = limit->p2.p2_fast;
781 }
782
783 memset(best_clock, 0, sizeof(*best_clock));
784 max_n = limit->n.max;
f77f13e2 785 /* based on hardware requirement, prefer smaller n to precision */
d4906093 786 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 787 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 788 for (clock.m1 = limit->m1.max;
789 clock.m1 >= limit->m1.min; clock.m1--) {
790 for (clock.m2 = limit->m2.max;
791 clock.m2 >= limit->m2.min; clock.m2--) {
792 for (clock.p1 = limit->p1.max;
793 clock.p1 >= limit->p1.min; clock.p1--) {
794 int this_err;
795
2177832f 796 intel_clock(dev, refclk, &clock);
1b894b59
CW		 797 if (!intel_PLL_is_valid(dev, limit,
798 &clock))
d4906093 799 continue;
cec2f356
SP		 800 if (match_clock &&
801 clock.p != match_clock->p)
802 continue;
1b894b59
CW		 803
804 this_err = abs(clock.dot - target);
d4906093
ML		 805 if (this_err < err_most) {
806 *best_clock = clock;
807 err_most = this_err;
808 max_n = clock.n;
809 found = true;
810 }
811 }
812 }
813 }
814 }
2c07245f
ZW		 815 return found;
816}
817
5eb08b69 818static bool
f2b115e6 819intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 820 int target, int refclk, intel_clock_t *match_clock,
821 intel_clock_t *best_clock)
5eb08b69
ZW		 822{
823 struct drm_device *dev = crtc->dev;
824 intel_clock_t clock;
4547668a 825
5eb08b69
ZW		 826 if (target < 200000) {
827 clock.n = 1;
828 clock.p1 = 2;
829 clock.p2 = 10;
830 clock.m1 = 12;
831 clock.m2 = 9;
832 } else {
833 clock.n = 2;
834 clock.p1 = 1;
835 clock.p2 = 10;
836 clock.m1 = 14;
837 clock.m2 = 8;
838 }
839 intel_clock(dev, refclk, &clock);
840 memcpy(best_clock, &clock, sizeof(intel_clock_t));
841 return true;
842}
843
a4fc5ed6
KP		 844/* DisplayPort has only two frequencies, 162MHz and 270MHz */
845static bool
846intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 847 int target, int refclk, intel_clock_t *match_clock,
848 intel_clock_t *best_clock)
a4fc5ed6 849{
5eddb70b
CW		 850 intel_clock_t clock;
851 if (target < 200000) {
852 clock.p1 = 2;
853 clock.p2 = 10;
854 clock.n = 2;
855 clock.m1 = 23;
856 clock.m2 = 8;
857 } else {
858 clock.p1 = 1;
859 clock.p2 = 10;
860 clock.n = 1;
861 clock.m1 = 14;
862 clock.m2 = 2;
863 }
864 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
865 clock.p = (clock.p1 * clock.p2);
866 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
867 clock.vco = 0;
868 memcpy(best_clock, &clock, sizeof(intel_clock_t));
869 return true;
a4fc5ed6 870}
a0c4da24
JB		 871static bool
872intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
873 int target, int refclk, intel_clock_t *match_clock,
874 intel_clock_t *best_clock)
875{
876 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
877 u32 m, n, fastclk;
878 u32 updrate, minupdate, fracbits, p;
879 unsigned long bestppm, ppm, absppm;
880 int dotclk, flag;
881
af447bd3 882 flag = 0;
a0c4da24
JB		 883 dotclk = target * 1000;
884 bestppm = 1000000;
885 ppm = absppm = 0;
886 fastclk = dotclk / (2*100);
887 updrate = 0;
888 minupdate = 19200;
889 fracbits = 1;
890 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
891 bestm1 = bestm2 = bestp1 = bestp2 = 0;
892
893 /* based on hardware requirement, prefer smaller n to precision */
894 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
895 updrate = refclk / n;
896 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
897 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
898 if (p2 > 10)
899 p2 = p2 - 1;
900 p = p1 * p2;
901 /* based on hardware requirement, prefer bigger m1,m2 values */
902 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
903 m2 = (((2*(fastclk * p * n / m1 )) +
904 refclk) / (2*refclk));
905 m = m1 * m2;
906 vco = updrate * m;
907 if (vco >= limit->vco.min && vco < limit->vco.max) {
908 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
909 absppm = (ppm > 0) ? ppm : (-ppm);
910 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
911 bestppm = 0;
912 flag = 1;
913 }
914 if (absppm < bestppm - 10) {
915 bestppm = absppm;
916 flag = 1;
917 }
918 if (flag) {
919 bestn = n;
920 bestm1 = m1;
921 bestm2 = m2;
922 bestp1 = p1;
923 bestp2 = p2;
924 flag = 0;
925 }
926 }
927 }
928 }
929 }
930 }
931 best_clock->n = bestn;
932 best_clock->m1 = bestm1;
933 best_clock->m2 = bestm2;
934 best_clock->p1 = bestp1;
935 best_clock->p2 = bestp2;
936
937 return true;
938}
a4fc5ed6 939
a5c961d1
PZ		 940enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
941 enum pipe pipe)
942{
943 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
945
946 return intel_crtc->cpu_transcoder;
947}
948
a928d536
PZ		 949static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
950{
951 struct drm_i915_private *dev_priv = dev->dev_private;
952 u32 frame, frame_reg = PIPEFRAME(pipe);
953
954 frame = I915_READ(frame_reg);
955
956 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
957 DRM_DEBUG_KMS("vblank wait timed out\n");
958}
959
9d0498a2
JB		 960/**
961 * intel_wait_for_vblank - wait for vblank on a given pipe
962 * @dev: drm device
963 * @pipe: pipe to wait for
964 *
965 * Wait for vblank to occur on a given pipe. Needed for various bits of
966 * mode setting code.
967 */
968void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 969{
9d0498a2 970 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 971 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 972
a928d536
PZ		 973 if (INTEL_INFO(dev)->gen >= 5) {
974 ironlake_wait_for_vblank(dev, pipe);
975 return;
976 }
977
300387c0
CW		 978 /* Clear existing vblank status. Note this will clear any other
979 * sticky status fields as well.
980 *
981 * This races with i915_driver_irq_handler() with the result
982 * that either function could miss a vblank event. Here it is not
983 * fatal, as we will either wait upon the next vblank interrupt or
984 * timeout. Generally speaking intel_wait_for_vblank() is only
985 * called during modeset at which time the GPU should be idle and
986 * should *not* be performing page flips and thus not waiting on
987 * vblanks...
988 * Currently, the result of us stealing a vblank from the irq
989 * handler is that a single frame will be skipped during swapbuffers.
990 */
991 I915_WRITE(pipestat_reg,
992 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
993
9d0498a2 994 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 995 if (wait_for(I915_READ(pipestat_reg) &
996 PIPE_VBLANK_INTERRUPT_STATUS,
997 50))
9d0498a2
JB		 998 DRM_DEBUG_KMS("vblank wait timed out\n");
999}
1000
ab7ad7f6
KP		 1001/*
1002 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 1003 * @dev: drm device
1004 * @pipe: pipe to wait for
1005 *
1006 * After disabling a pipe, we can't wait for vblank in the usual way,
1007 * spinning on the vblank interrupt status bit, since we won't actually
1008 * see an interrupt when the pipe is disabled.
1009 *
ab7ad7f6
KP		 1010 * On Gen4 and above:
1011 * wait for the pipe register state bit to turn off
1012 *
1013 * Otherwise:
1014 * wait for the display line value to settle (it usually
1015 * ends up stopping at the start of the next frame).
58e10eb9 1016 *
9d0498a2 1017 */
58e10eb9 1018void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 1019{
1020 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 1021 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1022 pipe);
ab7ad7f6
KP		 1023
1024 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1025 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1026
1027 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1028 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1029 100))
284637d9 1030 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1031 } else {
837ba00f 1032 u32 last_line, line_mask;
58e10eb9 1033 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 1034 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1035
837ba00f
PZ		 1036 if (IS_GEN2(dev))
1037 line_mask = DSL_LINEMASK_GEN2;
1038 else
1039 line_mask = DSL_LINEMASK_GEN3;
1040
ab7ad7f6
KP		 1041 /* Wait for the display line to settle */
1042 do {
837ba00f 1043 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 1044 mdelay(5);
837ba00f 1045 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 1046 time_after(timeout, jiffies));
1047 if (time_after(jiffies, timeout))
284637d9 1048 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1049 }
79e53945
JB		 1050}
1051
b24e7179
JB		 1052static const char *state_string(bool enabled)
1053{
1054 return enabled ? "on" : "off";
1055}
1056
1057/* Only for pre-ILK configs */
1058static void assert_pll(struct drm_i915_private *dev_priv,
1059 enum pipe pipe, bool state)
1060{
1061 int reg;
1062 u32 val;
1063 bool cur_state;
1064
1065 reg = DPLL(pipe);
1066 val = I915_READ(reg);
1067 cur_state = !!(val & DPLL_VCO_ENABLE);
1068 WARN(cur_state != state,
1069 "PLL state assertion failure (expected %s, current %s)\n",
1070 state_string(state), state_string(cur_state));
1071}
1072#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1073#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1074
040484af
JB		 1075/* For ILK+ */
1076static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1077 struct intel_pch_pll *pll,
1078 struct intel_crtc *crtc,
1079 bool state)
040484af 1080{
040484af
JB		 1081 u32 val;
1082 bool cur_state;
1083
9d82aa17
ED		 1084 if (HAS_PCH_LPT(dev_priv->dev)) {
1085 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1086 return;
1087 }
1088
92b27b08
CW		 1089 if (WARN (!pll,
1090 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1091 return;
ee7b9f93 1092
92b27b08
CW		 1093 val = I915_READ(pll->pll_reg);
1094 cur_state = !!(val & DPLL_VCO_ENABLE);
1095 WARN(cur_state != state,
1096 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1097 pll->pll_reg, state_string(state), state_string(cur_state), val);
1098
1099 /* Make sure the selected PLL is correctly attached to the transcoder */
1100 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1101 u32 pch_dpll;
1102
1103 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1104 cur_state = pll->pll_reg == _PCH_DPLL_B;
1105 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1106 "PLL[%d] not attached to this transcoder %d: %08x\n",
1107 cur_state, crtc->pipe, pch_dpll)) {
1108 cur_state = !!(val >> (4*crtc->pipe + 3));
1109 WARN(cur_state != state,
1110 "PLL[%d] not %s on this transcoder %d: %08x\n",
1111 pll->pll_reg == _PCH_DPLL_B,
1112 state_string(state),
1113 crtc->pipe,
1114 val);
1115 }
d3ccbe86 1116 }
040484af 1117}
92b27b08
CW		 1118#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1119#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1120
1121static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1122 enum pipe pipe, bool state)
1123{
1124 int reg;
1125 u32 val;
1126 bool cur_state;
ad80a810
PZ		 1127 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128 pipe);
040484af 1129
bf507ef7
ED		 1130 if (IS_HASWELL(dev_priv->dev)) {
1131 /* On Haswell, DDI is used instead of FDI_TX_CTL */
ad80a810 1132 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1133 val = I915_READ(reg);
ad80a810 1134 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1135 } else {
1136 reg = FDI_TX_CTL(pipe);
1137 val = I915_READ(reg);
1138 cur_state = !!(val & FDI_TX_ENABLE);
1139 }
040484af
JB		 1140 WARN(cur_state != state,
1141 "FDI TX state assertion failure (expected %s, current %s)\n",
1142 state_string(state), state_string(cur_state));
1143}
1144#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1145#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1146
1147static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1148 enum pipe pipe, bool state)
1149{
1150 int reg;
1151 u32 val;
1152 bool cur_state;
1153
59c859d6
ED		 1154 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1155 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1156 return;
1157 } else {
1158 reg = FDI_RX_CTL(pipe);
1159 val = I915_READ(reg);
1160 cur_state = !!(val & FDI_RX_ENABLE);
1161 }
040484af
JB		 1162 WARN(cur_state != state,
1163 "FDI RX state assertion failure (expected %s, current %s)\n",
1164 state_string(state), state_string(cur_state));
1165}
1166#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1167#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1168
1169static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1170 enum pipe pipe)
1171{
1172 int reg;
1173 u32 val;
1174
1175 /* ILK FDI PLL is always enabled */
1176 if (dev_priv->info->gen == 5)
1177 return;
1178
bf507ef7
ED		 1179 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1180 if (IS_HASWELL(dev_priv->dev))
1181 return;
1182
040484af
JB		 1183 reg = FDI_TX_CTL(pipe);
1184 val = I915_READ(reg);
1185 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1186}
1187
1188static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1189 enum pipe pipe)
1190{
1191 int reg;
1192 u32 val;
1193
59c859d6
ED		 1194 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1195 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1196 return;
1197 }
040484af
JB		 1198 reg = FDI_RX_CTL(pipe);
1199 val = I915_READ(reg);
1200 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1201}
1202
ea0760cf
JB		 1203static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1204 enum pipe pipe)
1205{
1206 int pp_reg, lvds_reg;
1207 u32 val;
1208 enum pipe panel_pipe = PIPE_A;
0de3b485 1209 bool locked = true;
ea0760cf
JB		 1210
1211 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1212 pp_reg = PCH_PP_CONTROL;
1213 lvds_reg = PCH_LVDS;
1214 } else {
1215 pp_reg = PP_CONTROL;
1216 lvds_reg = LVDS;
1217 }
1218
1219 val = I915_READ(pp_reg);
1220 if (!(val & PANEL_POWER_ON) ||
1221 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1222 locked = false;
1223
1224 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1225 panel_pipe = PIPE_B;
1226
1227 WARN(panel_pipe == pipe && locked,
1228 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1229 pipe_name(pipe));
ea0760cf
JB		 1230}
1231
b840d907
JB		 1232void assert_pipe(struct drm_i915_private *dev_priv,
1233 enum pipe pipe, bool state)
b24e7179
JB		 1234{
1235 int reg;
1236 u32 val;
63d7bbe9 1237 bool cur_state;
702e7a56
PZ		 1238 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1239 pipe);
b24e7179 1240
8e636784
DV		 1241 /* if we need the pipe A quirk it must be always on */
1242 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1243 state = true;
1244
702e7a56 1245 reg = PIPECONF(cpu_transcoder);
b24e7179 1246 val = I915_READ(reg);
63d7bbe9
JB		 1247 cur_state = !!(val & PIPECONF_ENABLE);
1248 WARN(cur_state != state,
1249 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1250 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1251}
1252
931872fc
CW		 1253static void assert_plane(struct drm_i915_private *dev_priv,
1254 enum plane plane, bool state)
b24e7179
JB		 1255{
1256 int reg;
1257 u32 val;
931872fc 1258 bool cur_state;
b24e7179
JB		 1259
1260 reg = DSPCNTR(plane);
1261 val = I915_READ(reg);
931872fc
CW		 1262 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1263 WARN(cur_state != state,
1264 "plane %c assertion failure (expected %s, current %s)\n",
1265 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1266}
1267
931872fc
CW		 1268#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1269#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1270
b24e7179
JB		 1271static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1272 enum pipe pipe)
1273{
1274 int reg, i;
1275 u32 val;
1276 int cur_pipe;
1277
19ec1358 1278 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1279 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1280 reg = DSPCNTR(pipe);
1281 val = I915_READ(reg);
1282 WARN((val & DISPLAY_PLANE_ENABLE),
1283 "plane %c assertion failure, should be disabled but not\n",
1284 plane_name(pipe));
19ec1358 1285 return;
28c05794 1286 }
19ec1358 1287
b24e7179
JB		 1288 /* Need to check both planes against the pipe */
1289 for (i = 0; i < 2; i++) {
1290 reg = DSPCNTR(i);
1291 val = I915_READ(reg);
1292 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1293 DISPPLANE_SEL_PIPE_SHIFT;
1294 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1295 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1296 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1297 }
1298}
1299
92f2584a
JB		 1300static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1301{
1302 u32 val;
1303 bool enabled;
1304
9d82aa17
ED		 1305 if (HAS_PCH_LPT(dev_priv->dev)) {
1306 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1307 return;
1308 }
1309
92f2584a
JB		 1310 val = I915_READ(PCH_DREF_CONTROL);
1311 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1312 DREF_SUPERSPREAD_SOURCE_MASK));
1313 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1314}
1315
1316static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1317 enum pipe pipe)
1318{
1319 int reg;
1320 u32 val;
1321 bool enabled;
1322
1323 reg = TRANSCONF(pipe);
1324 val = I915_READ(reg);
1325 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1326 WARN(enabled,
1327 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1328 pipe_name(pipe));
92f2584a
JB		 1329}
1330
4e634389
KP		 1331static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1332 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1333{
1334 if ((val & DP_PORT_EN) == 0)
1335 return false;
1336
1337 if (HAS_PCH_CPT(dev_priv->dev)) {
1338 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1339 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1340 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1341 return false;
1342 } else {
1343 if ((val & DP_PIPE_MASK) != (pipe << 30))
1344 return false;
1345 }
1346 return true;
1347}
1348
1519b995
KP		 1349static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1350 enum pipe pipe, u32 val)
1351{
1352 if ((val & PORT_ENABLE) == 0)
1353 return false;
1354
1355 if (HAS_PCH_CPT(dev_priv->dev)) {
1356 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1357 return false;
1358 } else {
1359 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1360 return false;
1361 }
1362 return true;
1363}
1364
1365static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1366 enum pipe pipe, u32 val)
1367{
1368 if ((val & LVDS_PORT_EN) == 0)
1369 return false;
1370
1371 if (HAS_PCH_CPT(dev_priv->dev)) {
1372 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1373 return false;
1374 } else {
1375 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1376 return false;
1377 }
1378 return true;
1379}
1380
1381static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1382 enum pipe pipe, u32 val)
1383{
1384 if ((val & ADPA_DAC_ENABLE) == 0)
1385 return false;
1386 if (HAS_PCH_CPT(dev_priv->dev)) {
1387 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1388 return false;
1389 } else {
1390 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1391 return false;
1392 }
1393 return true;
1394}
1395
291906f1 1396static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1397 enum pipe pipe, int reg, u32 port_sel)
291906f1 1398{
47a05eca 1399 u32 val = I915_READ(reg);
4e634389 1400 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1401 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1402 reg, pipe_name(pipe));
de9a35ab 1403
75c5da27
DV		 1404 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1405 && (val & DP_PIPEB_SELECT),
de9a35ab 1406 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1407}
1408
1409static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1410 enum pipe pipe, int reg)
1411{
47a05eca 1412 u32 val = I915_READ(reg);
e9a851ed 1413 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1414 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1415 reg, pipe_name(pipe));
de9a35ab 1416
75c5da27
DV		 1417 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1418 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1419 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1420}
1421
1422static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1423 enum pipe pipe)
1424{
1425 int reg;
1426 u32 val;
291906f1 1427
f0575e92
KP		 1428 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1429 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1430 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1431
1432 reg = PCH_ADPA;
1433 val = I915_READ(reg);
e9a851ed 1434 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1435 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1436 pipe_name(pipe));
291906f1
JB		 1437
1438 reg = PCH_LVDS;
1439 val = I915_READ(reg);
e9a851ed 1440 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1441 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1442 pipe_name(pipe));
291906f1
JB		 1443
1444 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1445 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1446 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1447}
1448
63d7bbe9
JB		 1449/**
1450 * intel_enable_pll - enable a PLL
1451 * @dev_priv: i915 private structure
1452 * @pipe: pipe PLL to enable
1453 *
1454 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1455 * make sure the PLL reg is writable first though, since the panel write
1456 * protect mechanism may be enabled.
1457 *
1458 * Note! This is for pre-ILK only.
7434a255
TR		 1459 *
1460 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9 1461 */
a37b9b34 1462static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9
JB		 1463{
1464 int reg;
1465 u32 val;
1466
1467 /* No really, not for ILK+ */
a0c4da24 1468 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1469
1470 /* PLL is protected by panel, make sure we can write it */
1471 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1472 assert_panel_unlocked(dev_priv, pipe);
1473
1474 reg = DPLL(pipe);
1475 val = I915_READ(reg);
1476 val |= DPLL_VCO_ENABLE;
1477
1478 /* We do this three times for luck */
1479 I915_WRITE(reg, val);
1480 POSTING_READ(reg);
1481 udelay(150); /* wait for warmup */
1482 I915_WRITE(reg, val);
1483 POSTING_READ(reg);
1484 udelay(150); /* wait for warmup */
1485 I915_WRITE(reg, val);
1486 POSTING_READ(reg);
1487 udelay(150); /* wait for warmup */
1488}
1489
1490/**
1491 * intel_disable_pll - disable a PLL
1492 * @dev_priv: i915 private structure
1493 * @pipe: pipe PLL to disable
1494 *
1495 * Disable the PLL for @pipe, making sure the pipe is off first.
1496 *
1497 * Note! This is for pre-ILK only.
1498 */
1499static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1500{
1501 int reg;
1502 u32 val;
1503
1504 /* Don't disable pipe A or pipe A PLLs if needed */
1505 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1506 return;
1507
1508 /* Make sure the pipe isn't still relying on us */
1509 assert_pipe_disabled(dev_priv, pipe);
1510
1511 reg = DPLL(pipe);
1512 val = I915_READ(reg);
1513 val &= ~DPLL_VCO_ENABLE;
1514 I915_WRITE(reg, val);
1515 POSTING_READ(reg);
1516}
1517
a416edef
ED		 1518/* SBI access */
1519static void
1520intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1521{
1522 unsigned long flags;
1523
1524 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1525 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1526 100)) {
1527 DRM_ERROR("timeout waiting for SBI to become ready\n");
1528 goto out_unlock;
1529 }
1530
1531 I915_WRITE(SBI_ADDR,
1532 (reg << 16));
1533 I915_WRITE(SBI_DATA,
1534 value);
1535 I915_WRITE(SBI_CTL_STAT,
1536 SBI_BUSY |
1537 SBI_CTL_OP_CRWR);
1538
39fb50f6 1539 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1540 100)) {
1541 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1542 goto out_unlock;
1543 }
1544
1545out_unlock:
1546 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1547}
1548
1549static u32
1550intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1551{
1552 unsigned long flags;
39fb50f6 1553 u32 value = 0;
a416edef
ED		 1554
1555 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1556 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1557 100)) {
1558 DRM_ERROR("timeout waiting for SBI to become ready\n");
1559 goto out_unlock;
1560 }
1561
1562 I915_WRITE(SBI_ADDR,
1563 (reg << 16));
1564 I915_WRITE(SBI_CTL_STAT,
1565 SBI_BUSY |
1566 SBI_CTL_OP_CRRD);
1567
39fb50f6 1568 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1569 100)) {
1570 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1571 goto out_unlock;
1572 }
1573
1574 value = I915_READ(SBI_DATA);
1575
1576out_unlock:
1577 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1578 return value;
1579}
1580
92f2584a 1581/**
b6b4e185 1582 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1583 * @dev_priv: i915 private structure
1584 * @pipe: pipe PLL to enable
1585 *
1586 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1587 * drives the transcoder clock.
1588 */
b6b4e185 1589static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1590{
ee7b9f93 1591 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1592 struct intel_pch_pll *pll;
92f2584a
JB		 1593 int reg;
1594 u32 val;
1595
48da64a8 1596 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1597 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1598 pll = intel_crtc->pch_pll;
1599 if (pll == NULL)
1600 return;
1601
1602 if (WARN_ON(pll->refcount == 0))
1603 return;
ee7b9f93
JB		 1604
1605 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1606 pll->pll_reg, pll->active, pll->on,
1607 intel_crtc->base.base.id);
92f2584a
JB		 1608
1609 /* PCH refclock must be enabled first */
1610 assert_pch_refclk_enabled(dev_priv);
1611
ee7b9f93 1612 if (pll->active++ && pll->on) {
92b27b08 1613 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1614 return;
1615 }
1616
1617 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1618
1619 reg = pll->pll_reg;
92f2584a
JB		 1620 val = I915_READ(reg);
1621 val |= DPLL_VCO_ENABLE;
1622 I915_WRITE(reg, val);
1623 POSTING_READ(reg);
1624 udelay(200);
ee7b9f93
JB		 1625
1626 pll->on = true;
92f2584a
JB		 1627}
1628
ee7b9f93 1629static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1630{
ee7b9f93
JB		 1631 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1632 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1633 int reg;
ee7b9f93 1634 u32 val;
4c609cb8 1635
92f2584a
JB		 1636 /* PCH only available on ILK+ */
1637 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1638 if (pll == NULL)
1639 return;
92f2584a 1640
48da64a8
CW		 1641 if (WARN_ON(pll->refcount == 0))
1642 return;
7a419866 1643
ee7b9f93
JB		 1644 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1645 pll->pll_reg, pll->active, pll->on,
1646 intel_crtc->base.base.id);
7a419866 1647
48da64a8 1648 if (WARN_ON(pll->active == 0)) {
92b27b08 1649 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1650 return;
1651 }
1652
ee7b9f93 1653 if (--pll->active) {
92b27b08 1654 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1655 return;
ee7b9f93
JB		 1656 }
1657
1658 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1659
1660 /* Make sure transcoder isn't still depending on us */
1661 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1662
ee7b9f93 1663 reg = pll->pll_reg;
92f2584a
JB		 1664 val = I915_READ(reg);
1665 val &= ~DPLL_VCO_ENABLE;
1666 I915_WRITE(reg, val);
1667 POSTING_READ(reg);
1668 udelay(200);
ee7b9f93
JB		 1669
1670 pll->on = false;
92f2584a
JB		 1671}
1672
040484af
JB		 1673static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1674 enum pipe pipe)
1675{
1676 int reg;
5f7f726d 1677 u32 val, pipeconf_val;
7c26e5c6 1678 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
040484af
JB		 1679
1680 /* PCH only available on ILK+ */
1681 BUG_ON(dev_priv->info->gen < 5);
1682
1683 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1684 assert_pch_pll_enabled(dev_priv,
1685 to_intel_crtc(crtc)->pch_pll,
1686 to_intel_crtc(crtc));
040484af
JB		 1687
1688 /* FDI must be feeding us bits for PCH ports */
1689 assert_fdi_tx_enabled(dev_priv, pipe);
1690 assert_fdi_rx_enabled(dev_priv, pipe);
1691
59c859d6
ED		 1692 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1693 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1694 return;
1695 }
040484af
JB		 1696 reg = TRANSCONF(pipe);
1697 val = I915_READ(reg);
5f7f726d 1698 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1699
1700 if (HAS_PCH_IBX(dev_priv->dev)) {
1701 /*
1702 * make the BPC in transcoder be consistent with
1703 * that in pipeconf reg.
1704 */
1705 val &= ~PIPE_BPC_MASK;
5f7f726d 1706 val |= pipeconf_val & PIPE_BPC_MASK;
e9bcff5c 1707 }
5f7f726d
PZ		 1708
1709 val &= ~TRANS_INTERLACE_MASK;
1710 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1711 if (HAS_PCH_IBX(dev_priv->dev) &&
1712 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1713 val |= TRANS_LEGACY_INTERLACED_ILK;
1714 else
1715 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1716 else
1717 val |= TRANS_PROGRESSIVE;
1718
040484af
JB		 1719 I915_WRITE(reg, val | TRANS_ENABLE);
1720 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1721 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1722}
1723
1724static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1725 enum pipe pipe)
1726{
1727 int reg;
1728 u32 val;
1729
1730 /* FDI relies on the transcoder */
1731 assert_fdi_tx_disabled(dev_priv, pipe);
1732 assert_fdi_rx_disabled(dev_priv, pipe);
1733
291906f1
JB		 1734 /* Ports must be off as well */
1735 assert_pch_ports_disabled(dev_priv, pipe);
1736
040484af
JB		 1737 reg = TRANSCONF(pipe);
1738 val = I915_READ(reg);
1739 val &= ~TRANS_ENABLE;
1740 I915_WRITE(reg, val);
1741 /* wait for PCH transcoder off, transcoder state */
1742 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1743 DRM_ERROR("failed to disable transcoder %d\n", pipe);
040484af
JB		 1744}
1745
b24e7179 1746/**
309cfea8 1747 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1748 * @dev_priv: i915 private structure
1749 * @pipe: pipe to enable
040484af 1750 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1751 *
1752 * Enable @pipe, making sure that various hardware specific requirements
1753 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1754 *
1755 * @pipe should be %PIPE_A or %PIPE_B.
1756 *
1757 * Will wait until the pipe is actually running (i.e. first vblank) before
1758 * returning.
1759 */
040484af
JB		 1760static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1761 bool pch_port)
b24e7179 1762{
702e7a56
PZ		 1763 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1764 pipe);
b24e7179
JB		 1765 int reg;
1766 u32 val;
1767
1768 /*
1769 * A pipe without a PLL won't actually be able to drive bits from
1770 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1771 * need the check.
1772 */
1773 if (!HAS_PCH_SPLIT(dev_priv->dev))
1774 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1775 else {
1776 if (pch_port) {
1777 /* if driving the PCH, we need FDI enabled */
1778 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1779 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1780 }
1781 /* FIXME: assert CPU port conditions for SNB+ */
1782 }
b24e7179 1783
702e7a56 1784 reg = PIPECONF(cpu_transcoder);
b24e7179 1785 val = I915_READ(reg);
00d70b15
CW		 1786 if (val & PIPECONF_ENABLE)
1787 return;
1788
1789 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1790 intel_wait_for_vblank(dev_priv->dev, pipe);
1791}
1792
1793/**
309cfea8 1794 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1795 * @dev_priv: i915 private structure
1796 * @pipe: pipe to disable
1797 *
1798 * Disable @pipe, making sure that various hardware specific requirements
1799 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1800 *
1801 * @pipe should be %PIPE_A or %PIPE_B.
1802 *
1803 * Will wait until the pipe has shut down before returning.
1804 */
1805static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1806 enum pipe pipe)
1807{
702e7a56
PZ		 1808 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1809 pipe);
b24e7179
JB		 1810 int reg;
1811 u32 val;
1812
1813 /*
1814 * Make sure planes won't keep trying to pump pixels to us,
1815 * or we might hang the display.
1816 */
1817 assert_planes_disabled(dev_priv, pipe);
1818
1819 /* Don't disable pipe A or pipe A PLLs if needed */
1820 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1821 return;
1822
702e7a56 1823 reg = PIPECONF(cpu_transcoder);
b24e7179 1824 val = I915_READ(reg);
00d70b15
CW		 1825 if ((val & PIPECONF_ENABLE) == 0)
1826 return;
1827
1828 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1829 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1830}
1831
d74362c9
KP		 1832/*
1833 * Plane regs are double buffered, going from enabled->disabled needs a
1834 * trigger in order to latch. The display address reg provides this.
1835 */
6f1d69b0 1836void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1837 enum plane plane)
1838{
14f86147
DL		 1839 if (dev_priv->info->gen >= 4)
1840 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1841 else
1842 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1843}
1844
b24e7179
JB		 1845/**
1846 * intel_enable_plane - enable a display plane on a given pipe
1847 * @dev_priv: i915 private structure
1848 * @plane: plane to enable
1849 * @pipe: pipe being fed
1850 *
1851 * Enable @plane on @pipe, making sure that @pipe is running first.
1852 */
1853static void intel_enable_plane(struct drm_i915_private *dev_priv,
1854 enum plane plane, enum pipe pipe)
1855{
1856 int reg;
1857 u32 val;
1858
1859 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1860 assert_pipe_enabled(dev_priv, pipe);
1861
1862 reg = DSPCNTR(plane);
1863 val = I915_READ(reg);
00d70b15
CW		 1864 if (val & DISPLAY_PLANE_ENABLE)
1865 return;
1866
1867 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1868 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1869 intel_wait_for_vblank(dev_priv->dev, pipe);
1870}
1871
b24e7179
JB		 1872/**
1873 * intel_disable_plane - disable a display plane
1874 * @dev_priv: i915 private structure
1875 * @plane: plane to disable
1876 * @pipe: pipe consuming the data
1877 *
1878 * Disable @plane; should be an independent operation.
1879 */
1880static void intel_disable_plane(struct drm_i915_private *dev_priv,
1881 enum plane plane, enum pipe pipe)
1882{
1883 int reg;
1884 u32 val;
1885
1886 reg = DSPCNTR(plane);
1887 val = I915_READ(reg);
00d70b15
CW		 1888 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1889 return;
1890
1891 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1892 intel_flush_display_plane(dev_priv, plane);
1893 intel_wait_for_vblank(dev_priv->dev, pipe);
1894}
1895
127bd2ac 1896int
48b956c5 1897intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1898 struct drm_i915_gem_object *obj,
919926ae 1899 struct intel_ring_buffer *pipelined)
6b95a207 1900{
ce453d81 1901 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1902 u32 alignment;
1903 int ret;
1904
05394f39 1905 switch (obj->tiling_mode) {
6b95a207 1906 case I915_TILING_NONE:
534843da
CW		 1907 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1908 alignment = 128 * 1024;
a6c45cf0 1909 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1910 alignment = 4 * 1024;
1911 else
1912 alignment = 64 * 1024;
6b95a207
KH		 1913 break;
1914 case I915_TILING_X:
1915 /* pin() will align the object as required by fence */
1916 alignment = 0;
1917 break;
1918 case I915_TILING_Y:
1919 /* FIXME: Is this true? */
1920 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1921 return -EINVAL;
1922 default:
1923 BUG();
1924 }
1925
ce453d81 1926 dev_priv->mm.interruptible = false;
2da3b9b9 1927 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1928 if (ret)
ce453d81 1929 goto err_interruptible;
6b95a207
KH		 1930
1931 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1932 * fence, whereas 965+ only requires a fence if using
1933 * framebuffer compression. For simplicity, we always install
1934 * a fence as the cost is not that onerous.
1935 */
06d98131 1936 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1937 if (ret)
1938 goto err_unpin;
1690e1eb 1939
9a5a53b3 1940 i915_gem_object_pin_fence(obj);
6b95a207 1941
ce453d81 1942 dev_priv->mm.interruptible = true;
6b95a207 1943 return 0;
48b956c5
CW		 1944
1945err_unpin:
1946 i915_gem_object_unpin(obj);
ce453d81
CW		 1947err_interruptible:
1948 dev_priv->mm.interruptible = true;
48b956c5 1949 return ret;
6b95a207
KH		 1950}
1951
1690e1eb
CW		 1952void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1953{
1954 i915_gem_object_unpin_fence(obj);
1955 i915_gem_object_unpin(obj);
1956}
1957
c2c75131
DV		 1958/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1959 * is assumed to be a power-of-two. */
5a35e99e
DL		 1960unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
1961 unsigned int bpp,
1962 unsigned int pitch)
c2c75131
DV		 1963{
1964 int tile_rows, tiles;
1965
1966 tile_rows = *y / 8;
1967 *y %= 8;
1968 tiles = *x / (512/bpp);
1969 *x %= 512/bpp;
1970
1971 return tile_rows * pitch * 8 + tiles * 4096;
1972}
1973
17638cd6
JB		 1974static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1975 int x, int y)
81255565
JB		 1976{
1977 struct drm_device *dev = crtc->dev;
1978 struct drm_i915_private *dev_priv = dev->dev_private;
1979 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1980 struct intel_framebuffer *intel_fb;
05394f39 1981 struct drm_i915_gem_object *obj;
81255565 1982 int plane = intel_crtc->plane;
e506a0c6 1983 unsigned long linear_offset;
81255565 1984 u32 dspcntr;
5eddb70b 1985 u32 reg;
81255565
JB		 1986
1987 switch (plane) {
1988 case 0:
1989 case 1:
1990 break;
1991 default:
1992 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1993 return -EINVAL;
1994 }
1995
1996 intel_fb = to_intel_framebuffer(fb);
1997 obj = intel_fb->obj;
81255565 1998
5eddb70b
CW		 1999 reg = DSPCNTR(plane);
2000 dspcntr = I915_READ(reg);
81255565
JB		 2001 /* Mask out pixel format bits in case we change it */
2002 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2003 switch (fb->pixel_format) {
2004 case DRM_FORMAT_C8:
81255565
JB		 2005 dspcntr |= DISPPLANE_8BPP;
2006 break;
57779d06
VS		 2007 case DRM_FORMAT_XRGB1555:
2008 case DRM_FORMAT_ARGB1555:
2009 dspcntr |= DISPPLANE_BGRX555;
81255565 2010 break;
57779d06
VS		 2011 case DRM_FORMAT_RGB565:
2012 dspcntr |= DISPPLANE_BGRX565;
2013 break;
2014 case DRM_FORMAT_XRGB8888:
2015 case DRM_FORMAT_ARGB8888:
2016 dspcntr |= DISPPLANE_BGRX888;
2017 break;
2018 case DRM_FORMAT_XBGR8888:
2019 case DRM_FORMAT_ABGR8888:
2020 dspcntr |= DISPPLANE_RGBX888;
2021 break;
2022 case DRM_FORMAT_XRGB2101010:
2023 case DRM_FORMAT_ARGB2101010:
2024 dspcntr |= DISPPLANE_BGRX101010;
2025 break;
2026 case DRM_FORMAT_XBGR2101010:
2027 case DRM_FORMAT_ABGR2101010:
2028 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2029 break;
2030 default:
57779d06 2031 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
81255565
JB		 2032 return -EINVAL;
2033 }
57779d06 2034
a6c45cf0 2035 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2036 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2037 dspcntr |= DISPPLANE_TILED;
2038 else
2039 dspcntr &= ~DISPPLANE_TILED;
2040 }
2041
5eddb70b 2042 I915_WRITE(reg, dspcntr);
81255565 2043
e506a0c6 2044 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2045
c2c75131
DV		 2046 if (INTEL_INFO(dev)->gen >= 4) {
2047 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2048 intel_gen4_compute_offset_xtiled(&x, &y,
2049 fb->bits_per_pixel / 8,
2050 fb->pitches[0]);
c2c75131
DV		 2051 linear_offset -= intel_crtc->dspaddr_offset;
2052 } else {
e506a0c6 2053 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2054 }
e506a0c6
DV		 2055
2056 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2057 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2058 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2059 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2060 I915_MODIFY_DISPBASE(DSPSURF(plane),
2061 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2062 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2063 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2064 } else
e506a0c6 2065 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2066 POSTING_READ(reg);
81255565 2067
17638cd6
JB		 2068 return 0;
2069}
2070
2071static int ironlake_update_plane(struct drm_crtc *crtc,
2072 struct drm_framebuffer *fb, int x, int y)
2073{
2074 struct drm_device *dev = crtc->dev;
2075 struct drm_i915_private *dev_priv = dev->dev_private;
2076 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2077 struct intel_framebuffer *intel_fb;
2078 struct drm_i915_gem_object *obj;
2079 int plane = intel_crtc->plane;
e506a0c6 2080 unsigned long linear_offset;
17638cd6
JB		 2081 u32 dspcntr;
2082 u32 reg;
2083
2084 switch (plane) {
2085 case 0:
2086 case 1:
27f8227b 2087 case 2:
17638cd6
JB		 2088 break;
2089 default:
2090 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2091 return -EINVAL;
2092 }
2093
2094 intel_fb = to_intel_framebuffer(fb);
2095 obj = intel_fb->obj;
2096
2097 reg = DSPCNTR(plane);
2098 dspcntr = I915_READ(reg);
2099 /* Mask out pixel format bits in case we change it */
2100 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2101 switch (fb->pixel_format) {
2102 case DRM_FORMAT_C8:
17638cd6
JB		 2103 dspcntr |= DISPPLANE_8BPP;
2104 break;
57779d06
VS		 2105 case DRM_FORMAT_RGB565:
2106 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2107 break;
57779d06
VS		 2108 case DRM_FORMAT_XRGB8888:
2109 case DRM_FORMAT_ARGB8888:
2110 dspcntr |= DISPPLANE_BGRX888;
2111 break;
2112 case DRM_FORMAT_XBGR8888:
2113 case DRM_FORMAT_ABGR8888:
2114 dspcntr |= DISPPLANE_RGBX888;
2115 break;
2116 case DRM_FORMAT_XRGB2101010:
2117 case DRM_FORMAT_ARGB2101010:
2118 dspcntr |= DISPPLANE_BGRX101010;
2119 break;
2120 case DRM_FORMAT_XBGR2101010:
2121 case DRM_FORMAT_ABGR2101010:
2122 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2123 break;
2124 default:
57779d06 2125 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
17638cd6
JB		 2126 return -EINVAL;
2127 }
2128
2129 if (obj->tiling_mode != I915_TILING_NONE)
2130 dspcntr |= DISPPLANE_TILED;
2131 else
2132 dspcntr &= ~DISPPLANE_TILED;
2133
2134 /* must disable */
2135 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2136
2137 I915_WRITE(reg, dspcntr);
2138
e506a0c6 2139 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2140 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2141 intel_gen4_compute_offset_xtiled(&x, &y,
2142 fb->bits_per_pixel / 8,
2143 fb->pitches[0]);
c2c75131 2144 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2145
e506a0c6
DV		 2146 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2147 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2148 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2149 I915_MODIFY_DISPBASE(DSPSURF(plane),
2150 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2151 if (IS_HASWELL(dev)) {
2152 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2153 } else {
2154 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2155 I915_WRITE(DSPLINOFF(plane), linear_offset);
2156 }
17638cd6
JB		 2157 POSTING_READ(reg);
2158
2159 return 0;
2160}
2161
2162/* Assume fb object is pinned & idle & fenced and just update base pointers */
2163static int
2164intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2165 int x, int y, enum mode_set_atomic state)
2166{
2167 struct drm_device *dev = crtc->dev;
2168 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2169
6b8e6ed0
CW		 2170 if (dev_priv->display.disable_fbc)
2171 dev_priv->display.disable_fbc(dev);
3dec0095 2172 intel_increase_pllclock(crtc);
81255565 2173
6b8e6ed0 2174 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2175}
2176
14667a4b
CW		 2177static int
2178intel_finish_fb(struct drm_framebuffer *old_fb)
2179{
2180 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2181 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2182 bool was_interruptible = dev_priv->mm.interruptible;
2183 int ret;
2184
2185 wait_event(dev_priv->pending_flip_queue,
2186 atomic_read(&dev_priv->mm.wedged) ||
2187 atomic_read(&obj->pending_flip) == 0);
2188
2189 /* Big Hammer, we also need to ensure that any pending
2190 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2191 * current scanout is retired before unpinning the old
2192 * framebuffer.
2193 *
2194 * This should only fail upon a hung GPU, in which case we
2195 * can safely continue.
2196 */
2197 dev_priv->mm.interruptible = false;
2198 ret = i915_gem_object_finish_gpu(obj);
2199 dev_priv->mm.interruptible = was_interruptible;
2200
2201 return ret;
2202}
2203
198598d0
VS		 2204static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2205{
2206 struct drm_device *dev = crtc->dev;
2207 struct drm_i915_master_private *master_priv;
2208 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2209
2210 if (!dev->primary->master)
2211 return;
2212
2213 master_priv = dev->primary->master->driver_priv;
2214 if (!master_priv->sarea_priv)
2215 return;
2216
2217 switch (intel_crtc->pipe) {
2218 case 0:
2219 master_priv->sarea_priv->pipeA_x = x;
2220 master_priv->sarea_priv->pipeA_y = y;
2221 break;
2222 case 1:
2223 master_priv->sarea_priv->pipeB_x = x;
2224 master_priv->sarea_priv->pipeB_y = y;
2225 break;
2226 default:
2227 break;
2228 }
2229}
2230
5c3b82e2 2231static int
3c4fdcfb 2232intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2233 struct drm_framebuffer *fb)
79e53945
JB		 2234{
2235 struct drm_device *dev = crtc->dev;
6b8e6ed0 2236 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2237 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2238 struct drm_framebuffer *old_fb;
5c3b82e2 2239 int ret;
79e53945
JB		 2240
2241 /* no fb bound */
94352cf9 2242 if (!fb) {
a5071c2f 2243 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2244 return 0;
2245 }
2246
5826eca5
ED		 2247 if(intel_crtc->plane > dev_priv->num_pipe) {
2248 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2249 intel_crtc->plane,
2250 dev_priv->num_pipe);
5c3b82e2 2251 return -EINVAL;
79e53945
JB		 2252 }
2253
5c3b82e2 2254 mutex_lock(&dev->struct_mutex);
265db958 2255 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2256 to_intel_framebuffer(fb)->obj,
919926ae 2257 NULL);
5c3b82e2
CW		 2258 if (ret != 0) {
2259 mutex_unlock(&dev->struct_mutex);
a5071c2f 2260 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2261 return ret;
2262 }
79e53945 2263
94352cf9
DV		 2264 if (crtc->fb)
2265 intel_finish_fb(crtc->fb);
265db958 2266
94352cf9 2267 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2268 if (ret) {
94352cf9 2269 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2270 mutex_unlock(&dev->struct_mutex);
a5071c2f 2271 DRM_ERROR("failed to update base address\n");
4e6cfefc 2272 return ret;
79e53945 2273 }
3c4fdcfb 2274
94352cf9
DV		 2275 old_fb = crtc->fb;
2276 crtc->fb = fb;
6c4c86f5
DV		 2277 crtc->x = x;
2278 crtc->y = y;
94352cf9 2279
b7f1de28
CW		 2280 if (old_fb) {
2281 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2282 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2283 }
652c393a 2284
6b8e6ed0 2285 intel_update_fbc(dev);
5c3b82e2 2286 mutex_unlock(&dev->struct_mutex);
79e53945 2287
198598d0 2288 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2289
2290 return 0;
79e53945
JB		 2291}
2292
5eddb70b 2293static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2294{
2295 struct drm_device *dev = crtc->dev;
2296 struct drm_i915_private *dev_priv = dev->dev_private;
2297 u32 dpa_ctl;
2298
28c97730 2299 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2300 dpa_ctl = I915_READ(DP_A);
2301 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2302
2303 if (clock < 200000) {
2304 u32 temp;
2305 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2306 /* workaround for 160Mhz:
2307 1) program 0x4600c bits 15:0 = 0x8124
2308 2) program 0x46010 bit 0 = 1
2309 3) program 0x46034 bit 24 = 1
2310 4) program 0x64000 bit 14 = 1
2311 */
2312 temp = I915_READ(0x4600c);
2313 temp &= 0xffff0000;
2314 I915_WRITE(0x4600c, temp | 0x8124);
2315
2316 temp = I915_READ(0x46010);
2317 I915_WRITE(0x46010, temp | 1);
2318
2319 temp = I915_READ(0x46034);
2320 I915_WRITE(0x46034, temp | (1 << 24));
2321 } else {
2322 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2323 }
2324 I915_WRITE(DP_A, dpa_ctl);
2325
5eddb70b 2326 POSTING_READ(DP_A);
32f9d658
ZW		 2327 udelay(500);
2328}
2329
5e84e1a4
ZW		 2330static void intel_fdi_normal_train(struct drm_crtc *crtc)
2331{
2332 struct drm_device *dev = crtc->dev;
2333 struct drm_i915_private *dev_priv = dev->dev_private;
2334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2335 int pipe = intel_crtc->pipe;
2336 u32 reg, temp;
2337
2338 /* enable normal train */
2339 reg = FDI_TX_CTL(pipe);
2340 temp = I915_READ(reg);
61e499bf 2341 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2342 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2343 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2344 } else {
2345 temp &= ~FDI_LINK_TRAIN_NONE;
2346 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2347 }
5e84e1a4
ZW		 2348 I915_WRITE(reg, temp);
2349
2350 reg = FDI_RX_CTL(pipe);
2351 temp = I915_READ(reg);
2352 if (HAS_PCH_CPT(dev)) {
2353 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2354 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2355 } else {
2356 temp &= ~FDI_LINK_TRAIN_NONE;
2357 temp |= FDI_LINK_TRAIN_NONE;
2358 }
2359 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2360
2361 /* wait one idle pattern time */
2362 POSTING_READ(reg);
2363 udelay(1000);
357555c0
JB		 2364
2365 /* IVB wants error correction enabled */
2366 if (IS_IVYBRIDGE(dev))
2367 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2368 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2369}
2370
291427f5
JB		 2371static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2372{
2373 struct drm_i915_private *dev_priv = dev->dev_private;
2374 u32 flags = I915_READ(SOUTH_CHICKEN1);
2375
2376 flags |= FDI_PHASE_SYNC_OVR(pipe);
2377 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2378 flags |= FDI_PHASE_SYNC_EN(pipe);
2379 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2380 POSTING_READ(SOUTH_CHICKEN1);
2381}
2382
01a415fd
DV		 2383static void ivb_modeset_global_resources(struct drm_device *dev)
2384{
2385 struct drm_i915_private *dev_priv = dev->dev_private;
2386 struct intel_crtc *pipe_B_crtc =
2387 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2388 struct intel_crtc *pipe_C_crtc =
2389 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2390 uint32_t temp;
2391
2392 /* When everything is off disable fdi C so that we could enable fdi B
2393 * with all lanes. XXX: This misses the case where a pipe is not using
2394 * any pch resources and so doesn't need any fdi lanes. */
2395 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2396 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2397 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2398
2399 temp = I915_READ(SOUTH_CHICKEN1);
2400 temp &= ~FDI_BC_BIFURCATION_SELECT;
2401 DRM_DEBUG_KMS("disabling fdi C rx\n");
2402 I915_WRITE(SOUTH_CHICKEN1, temp);
2403 }
2404}
2405
8db9d77b
ZW		 2406/* The FDI link training functions for ILK/Ibexpeak. */
2407static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2408{
2409 struct drm_device *dev = crtc->dev;
2410 struct drm_i915_private *dev_priv = dev->dev_private;
2411 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2412 int pipe = intel_crtc->pipe;
0fc932b8 2413 int plane = intel_crtc->plane;
5eddb70b 2414 u32 reg, temp, tries;
8db9d77b 2415
0fc932b8
JB		 2416 /* FDI needs bits from pipe & plane first */
2417 assert_pipe_enabled(dev_priv, pipe);
2418 assert_plane_enabled(dev_priv, plane);
2419
e1a44743
AJ		 2420 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2421 for train result */
5eddb70b
CW		 2422 reg = FDI_RX_IMR(pipe);
2423 temp = I915_READ(reg);
e1a44743
AJ		 2424 temp &= ~FDI_RX_SYMBOL_LOCK;
2425 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2426 I915_WRITE(reg, temp);
2427 I915_READ(reg);
e1a44743
AJ		 2428 udelay(150);
2429
8db9d77b 2430 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2431 reg = FDI_TX_CTL(pipe);
2432 temp = I915_READ(reg);
77ffb597
AJ		 2433 temp &= ~(7 << 19);
2434 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2435 temp &= ~FDI_LINK_TRAIN_NONE;
2436 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2437 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2438
5eddb70b
CW		 2439 reg = FDI_RX_CTL(pipe);
2440 temp = I915_READ(reg);
8db9d77b
ZW		 2441 temp &= ~FDI_LINK_TRAIN_NONE;
2442 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2443 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2444
2445 POSTING_READ(reg);
8db9d77b
ZW		 2446 udelay(150);
2447
5b2adf89 2448 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2449 if (HAS_PCH_IBX(dev)) {
2450 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2451 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2452 FDI_RX_PHASE_SYNC_POINTER_EN);
2453 }
5b2adf89 2454
5eddb70b 2455 reg = FDI_RX_IIR(pipe);
e1a44743 2456 for (tries = 0; tries < 5; tries++) {
5eddb70b 2457 temp = I915_READ(reg);
8db9d77b
ZW		 2458 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2459
2460 if ((temp & FDI_RX_BIT_LOCK)) {
2461 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2462 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2463 break;
2464 }
8db9d77b 2465 }
e1a44743 2466 if (tries == 5)
5eddb70b 2467 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2468
2469 /* Train 2 */
5eddb70b
CW		 2470 reg = FDI_TX_CTL(pipe);
2471 temp = I915_READ(reg);
8db9d77b
ZW		 2472 temp &= ~FDI_LINK_TRAIN_NONE;
2473 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2474 I915_WRITE(reg, temp);
8db9d77b 2475
5eddb70b
CW		 2476 reg = FDI_RX_CTL(pipe);
2477 temp = I915_READ(reg);
8db9d77b
ZW		 2478 temp &= ~FDI_LINK_TRAIN_NONE;
2479 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2480 I915_WRITE(reg, temp);
8db9d77b 2481
5eddb70b
CW		 2482 POSTING_READ(reg);
2483 udelay(150);
8db9d77b 2484
5eddb70b 2485 reg = FDI_RX_IIR(pipe);
e1a44743 2486 for (tries = 0; tries < 5; tries++) {
5eddb70b 2487 temp = I915_READ(reg);
8db9d77b
ZW		 2488 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2489
2490 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2491 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2492 DRM_DEBUG_KMS("FDI train 2 done.\n");
2493 break;
2494 }
8db9d77b 2495 }
e1a44743 2496 if (tries == 5)
5eddb70b 2497 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2498
2499 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2500
8db9d77b
ZW		 2501}
2502
0206e353 2503static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2504 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2505 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2506 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2507 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2508};
2509
2510/* The FDI link training functions for SNB/Cougarpoint. */
2511static void gen6_fdi_link_train(struct drm_crtc *crtc)
2512{
2513 struct drm_device *dev = crtc->dev;
2514 struct drm_i915_private *dev_priv = dev->dev_private;
2515 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2516 int pipe = intel_crtc->pipe;
fa37d39e 2517 u32 reg, temp, i, retry;
8db9d77b 2518
e1a44743
AJ		 2519 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2520 for train result */
5eddb70b
CW		 2521 reg = FDI_RX_IMR(pipe);
2522 temp = I915_READ(reg);
e1a44743
AJ		 2523 temp &= ~FDI_RX_SYMBOL_LOCK;
2524 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2525 I915_WRITE(reg, temp);
2526
2527 POSTING_READ(reg);
e1a44743
AJ		 2528 udelay(150);
2529
8db9d77b 2530 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2531 reg = FDI_TX_CTL(pipe);
2532 temp = I915_READ(reg);
77ffb597
AJ		 2533 temp &= ~(7 << 19);
2534 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2535 temp &= ~FDI_LINK_TRAIN_NONE;
2536 temp |= FDI_LINK_TRAIN_PATTERN_1;
2537 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2538 /* SNB-B */
2539 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2540 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2541
d74cf324
DV		 2542 I915_WRITE(FDI_RX_MISC(pipe),
2543 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2544
5eddb70b
CW		 2545 reg = FDI_RX_CTL(pipe);
2546 temp = I915_READ(reg);
8db9d77b
ZW		 2547 if (HAS_PCH_CPT(dev)) {
2548 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2549 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2550 } else {
2551 temp &= ~FDI_LINK_TRAIN_NONE;
2552 temp |= FDI_LINK_TRAIN_PATTERN_1;
2553 }
5eddb70b
CW		 2554 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2555
2556 POSTING_READ(reg);
8db9d77b
ZW		 2557 udelay(150);
2558
291427f5
JB		 2559 if (HAS_PCH_CPT(dev))
2560 cpt_phase_pointer_enable(dev, pipe);
2561
0206e353 2562 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2563 reg = FDI_TX_CTL(pipe);
2564 temp = I915_READ(reg);
8db9d77b
ZW		 2565 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2566 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2567 I915_WRITE(reg, temp);
2568
2569 POSTING_READ(reg);
8db9d77b
ZW		 2570 udelay(500);
2571
fa37d39e
SP		 2572 for (retry = 0; retry < 5; retry++) {
2573 reg = FDI_RX_IIR(pipe);
2574 temp = I915_READ(reg);
2575 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2576 if (temp & FDI_RX_BIT_LOCK) {
2577 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2578 DRM_DEBUG_KMS("FDI train 1 done.\n");
2579 break;
2580 }
2581 udelay(50);
8db9d77b 2582 }
fa37d39e
SP		 2583 if (retry < 5)
2584 break;
8db9d77b
ZW		 2585 }
2586 if (i == 4)
5eddb70b 2587 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2588
2589 /* Train 2 */
5eddb70b
CW		 2590 reg = FDI_TX_CTL(pipe);
2591 temp = I915_READ(reg);
8db9d77b
ZW		 2592 temp &= ~FDI_LINK_TRAIN_NONE;
2593 temp |= FDI_LINK_TRAIN_PATTERN_2;
2594 if (IS_GEN6(dev)) {
2595 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2596 /* SNB-B */
2597 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2598 }
5eddb70b 2599 I915_WRITE(reg, temp);
8db9d77b 2600
5eddb70b
CW		 2601 reg = FDI_RX_CTL(pipe);
2602 temp = I915_READ(reg);
8db9d77b
ZW		 2603 if (HAS_PCH_CPT(dev)) {
2604 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2605 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2606 } else {
2607 temp &= ~FDI_LINK_TRAIN_NONE;
2608 temp |= FDI_LINK_TRAIN_PATTERN_2;
2609 }
5eddb70b
CW		 2610 I915_WRITE(reg, temp);
2611
2612 POSTING_READ(reg);
8db9d77b
ZW		 2613 udelay(150);
2614
0206e353 2615 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2616 reg = FDI_TX_CTL(pipe);
2617 temp = I915_READ(reg);
8db9d77b
ZW		 2618 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2619 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2620 I915_WRITE(reg, temp);
2621
2622 POSTING_READ(reg);
8db9d77b
ZW		 2623 udelay(500);
2624
fa37d39e
SP		 2625 for (retry = 0; retry < 5; retry++) {
2626 reg = FDI_RX_IIR(pipe);
2627 temp = I915_READ(reg);
2628 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2629 if (temp & FDI_RX_SYMBOL_LOCK) {
2630 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2631 DRM_DEBUG_KMS("FDI train 2 done.\n");
2632 break;
2633 }
2634 udelay(50);
8db9d77b 2635 }
fa37d39e
SP		 2636 if (retry < 5)
2637 break;
8db9d77b
ZW		 2638 }
2639 if (i == 4)
5eddb70b 2640 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2641
2642 DRM_DEBUG_KMS("FDI train done.\n");
2643}
2644
357555c0
JB		 2645/* Manual link training for Ivy Bridge A0 parts */
2646static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2647{
2648 struct drm_device *dev = crtc->dev;
2649 struct drm_i915_private *dev_priv = dev->dev_private;
2650 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2651 int pipe = intel_crtc->pipe;
2652 u32 reg, temp, i;
2653
2654 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2655 for train result */
2656 reg = FDI_RX_IMR(pipe);
2657 temp = I915_READ(reg);
2658 temp &= ~FDI_RX_SYMBOL_LOCK;
2659 temp &= ~FDI_RX_BIT_LOCK;
2660 I915_WRITE(reg, temp);
2661
2662 POSTING_READ(reg);
2663 udelay(150);
2664
01a415fd
DV		 2665 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2666 I915_READ(FDI_RX_IIR(pipe)));
2667
357555c0
JB		 2668 /* enable CPU FDI TX and PCH FDI RX */
2669 reg = FDI_TX_CTL(pipe);
2670 temp = I915_READ(reg);
2671 temp &= ~(7 << 19);
2672 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2673 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2674 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2675 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2676 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2677 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2678 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2679
d74cf324
DV		 2680 I915_WRITE(FDI_RX_MISC(pipe),
2681 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2682
357555c0
JB		 2683 reg = FDI_RX_CTL(pipe);
2684 temp = I915_READ(reg);
2685 temp &= ~FDI_LINK_TRAIN_AUTO;
2686 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2687 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2688 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2689 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2690
2691 POSTING_READ(reg);
2692 udelay(150);
2693
291427f5
JB		 2694 if (HAS_PCH_CPT(dev))
2695 cpt_phase_pointer_enable(dev, pipe);
2696
0206e353 2697 for (i = 0; i < 4; i++) {
357555c0
JB		 2698 reg = FDI_TX_CTL(pipe);
2699 temp = I915_READ(reg);
2700 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2701 temp |= snb_b_fdi_train_param[i];
2702 I915_WRITE(reg, temp);
2703
2704 POSTING_READ(reg);
2705 udelay(500);
2706
2707 reg = FDI_RX_IIR(pipe);
2708 temp = I915_READ(reg);
2709 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2710
2711 if (temp & FDI_RX_BIT_LOCK ||
2712 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2713 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2714 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2715 break;
2716 }
2717 }
2718 if (i == 4)
2719 DRM_ERROR("FDI train 1 fail!\n");
2720
2721 /* Train 2 */
2722 reg = FDI_TX_CTL(pipe);
2723 temp = I915_READ(reg);
2724 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2725 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2726 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2727 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2728 I915_WRITE(reg, temp);
2729
2730 reg = FDI_RX_CTL(pipe);
2731 temp = I915_READ(reg);
2732 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2733 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2734 I915_WRITE(reg, temp);
2735
2736 POSTING_READ(reg);
2737 udelay(150);
2738
0206e353 2739 for (i = 0; i < 4; i++) {
357555c0
JB		 2740 reg = FDI_TX_CTL(pipe);
2741 temp = I915_READ(reg);
2742 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2743 temp |= snb_b_fdi_train_param[i];
2744 I915_WRITE(reg, temp);
2745
2746 POSTING_READ(reg);
2747 udelay(500);
2748
2749 reg = FDI_RX_IIR(pipe);
2750 temp = I915_READ(reg);
2751 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2752
2753 if (temp & FDI_RX_SYMBOL_LOCK) {
2754 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2755 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2756 break;
2757 }
2758 }
2759 if (i == 4)
2760 DRM_ERROR("FDI train 2 fail!\n");
2761
2762 DRM_DEBUG_KMS("FDI train done.\n");
2763}
2764
88cefb6c 2765static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2766{
88cefb6c 2767 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2768 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2769 int pipe = intel_crtc->pipe;
5eddb70b 2770 u32 reg, temp;
79e53945 2771
c64e311e 2772
c98e9dcf 2773 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2774 reg = FDI_RX_CTL(pipe);
2775 temp = I915_READ(reg);
2776 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2777 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2778 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2779 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2780
2781 POSTING_READ(reg);
c98e9dcf
JB		 2782 udelay(200);
2783
2784 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2785 temp = I915_READ(reg);
2786 I915_WRITE(reg, temp | FDI_PCDCLK);
2787
2788 POSTING_READ(reg);
c98e9dcf
JB		 2789 udelay(200);
2790
bf507ef7
ED		 2791 /* On Haswell, the PLL configuration for ports and pipes is handled
2792 * separately, as part of DDI setup */
2793 if (!IS_HASWELL(dev)) {
2794 /* Enable CPU FDI TX PLL, always on for Ironlake */
2795 reg = FDI_TX_CTL(pipe);
2796 temp = I915_READ(reg);
2797 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2798 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2799
bf507ef7
ED		 2800 POSTING_READ(reg);
2801 udelay(100);
2802 }
6be4a607 2803 }
0e23b99d
JB		 2804}
2805
88cefb6c
DV		 2806static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2807{
2808 struct drm_device *dev = intel_crtc->base.dev;
2809 struct drm_i915_private *dev_priv = dev->dev_private;
2810 int pipe = intel_crtc->pipe;
2811 u32 reg, temp;
2812
2813 /* Switch from PCDclk to Rawclk */
2814 reg = FDI_RX_CTL(pipe);
2815 temp = I915_READ(reg);
2816 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2817
2818 /* Disable CPU FDI TX PLL */
2819 reg = FDI_TX_CTL(pipe);
2820 temp = I915_READ(reg);
2821 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2822
2823 POSTING_READ(reg);
2824 udelay(100);
2825
2826 reg = FDI_RX_CTL(pipe);
2827 temp = I915_READ(reg);
2828 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2829
2830 /* Wait for the clocks to turn off. */
2831 POSTING_READ(reg);
2832 udelay(100);
2833}
2834
291427f5
JB		 2835static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2836{
2837 struct drm_i915_private *dev_priv = dev->dev_private;
2838 u32 flags = I915_READ(SOUTH_CHICKEN1);
2839
2840 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2841 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2842 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2843 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2844 POSTING_READ(SOUTH_CHICKEN1);
2845}
0fc932b8
JB		 2846static void ironlake_fdi_disable(struct drm_crtc *crtc)
2847{
2848 struct drm_device *dev = crtc->dev;
2849 struct drm_i915_private *dev_priv = dev->dev_private;
2850 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2851 int pipe = intel_crtc->pipe;
2852 u32 reg, temp;
2853
2854 /* disable CPU FDI tx and PCH FDI rx */
2855 reg = FDI_TX_CTL(pipe);
2856 temp = I915_READ(reg);
2857 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2858 POSTING_READ(reg);
2859
2860 reg = FDI_RX_CTL(pipe);
2861 temp = I915_READ(reg);
2862 temp &= ~(0x7 << 16);
2863 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2864 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2865
2866 POSTING_READ(reg);
2867 udelay(100);
2868
2869 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2870 if (HAS_PCH_IBX(dev)) {
2871 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2872 I915_WRITE(FDI_RX_CHICKEN(pipe),
2873 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2874 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2875 } else if (HAS_PCH_CPT(dev)) {
2876 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2877 }
0fc932b8
JB		 2878
2879 /* still set train pattern 1 */
2880 reg = FDI_TX_CTL(pipe);
2881 temp = I915_READ(reg);
2882 temp &= ~FDI_LINK_TRAIN_NONE;
2883 temp |= FDI_LINK_TRAIN_PATTERN_1;
2884 I915_WRITE(reg, temp);
2885
2886 reg = FDI_RX_CTL(pipe);
2887 temp = I915_READ(reg);
2888 if (HAS_PCH_CPT(dev)) {
2889 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2890 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2891 } else {
2892 temp &= ~FDI_LINK_TRAIN_NONE;
2893 temp |= FDI_LINK_TRAIN_PATTERN_1;
2894 }
2895 /* BPC in FDI rx is consistent with that in PIPECONF */
2896 temp &= ~(0x07 << 16);
2897 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2898 I915_WRITE(reg, temp);
2899
2900 POSTING_READ(reg);
2901 udelay(100);
2902}
2903
5bb61643
CW		 2904static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2905{
2906 struct drm_device *dev = crtc->dev;
2907 struct drm_i915_private *dev_priv = dev->dev_private;
2908 unsigned long flags;
2909 bool pending;
2910
2911 if (atomic_read(&dev_priv->mm.wedged))
2912 return false;
2913
2914 spin_lock_irqsave(&dev->event_lock, flags);
2915 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2916 spin_unlock_irqrestore(&dev->event_lock, flags);
2917
2918 return pending;
2919}
2920
e6c3a2a6
CW		 2921static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2922{
0f91128d 2923 struct drm_device *dev = crtc->dev;
5bb61643 2924 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2925
2926 if (crtc->fb == NULL)
2927 return;
2928
5bb61643
CW		 2929 wait_event(dev_priv->pending_flip_queue,
2930 !intel_crtc_has_pending_flip(crtc));
2931
0f91128d
CW		 2932 mutex_lock(&dev->struct_mutex);
2933 intel_finish_fb(crtc->fb);
2934 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2935}
2936
fc316cbe 2937static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
040484af
JB		 2938{
2939 struct drm_device *dev = crtc->dev;
228d3e36 2940 struct intel_encoder *intel_encoder;
040484af
JB		 2941
2942 /*
2943 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2944 * must be driven by its own crtc; no sharing is possible.
2945 */
228d3e36 2946 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
228d3e36 2947 switch (intel_encoder->type) {
040484af 2948 case INTEL_OUTPUT_EDP:
228d3e36 2949 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
040484af
JB		 2950 return false;
2951 continue;
2952 }
2953 }
2954
2955 return true;
2956}
2957
fc316cbe
PZ		 2958static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2959{
2960 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2961}
2962
e615efe4
ED		 2963/* Program iCLKIP clock to the desired frequency */
2964static void lpt_program_iclkip(struct drm_crtc *crtc)
2965{
2966 struct drm_device *dev = crtc->dev;
2967 struct drm_i915_private *dev_priv = dev->dev_private;
2968 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2969 u32 temp;
2970
2971 /* It is necessary to ungate the pixclk gate prior to programming
2972 * the divisors, and gate it back when it is done.
2973 */
2974 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2975
2976 /* Disable SSCCTL */
2977 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2978 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2979 SBI_SSCCTL_DISABLE);
2980
2981 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2982 if (crtc->mode.clock == 20000) {
2983 auxdiv = 1;
2984 divsel = 0x41;
2985 phaseinc = 0x20;
2986 } else {
2987 /* The iCLK virtual clock root frequency is in MHz,
2988 * but the crtc->mode.clock in in KHz. To get the divisors,
2989 * it is necessary to divide one by another, so we
2990 * convert the virtual clock precision to KHz here for higher
2991 * precision.
2992 */
2993 u32 iclk_virtual_root_freq = 172800 * 1000;
2994 u32 iclk_pi_range = 64;
2995 u32 desired_divisor, msb_divisor_value, pi_value;
2996
2997 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2998 msb_divisor_value = desired_divisor / iclk_pi_range;
2999 pi_value = desired_divisor % iclk_pi_range;
3000
3001 auxdiv = 0;
3002 divsel = msb_divisor_value - 2;
3003 phaseinc = pi_value;
3004 }
3005
3006 /* This should not happen with any sane values */
3007 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3008 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3009 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3010 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3011
3012 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3013 crtc->mode.clock,
3014 auxdiv,
3015 divsel,
3016 phasedir,
3017 phaseinc);
3018
3019 /* Program SSCDIVINTPHASE6 */
3020 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
3021 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3022 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3023 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3024 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3025 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3026 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3027
3028 intel_sbi_write(dev_priv,
3029 SBI_SSCDIVINTPHASE6,
3030 temp);
3031
3032 /* Program SSCAUXDIV */
3033 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
3034 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3035 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3036 intel_sbi_write(dev_priv,
3037 SBI_SSCAUXDIV6,
3038 temp);
3039
3040
3041 /* Enable modulator and associated divider */
3042 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
3043 temp &= ~SBI_SSCCTL_DISABLE;
3044 intel_sbi_write(dev_priv,
3045 SBI_SSCCTL6,
3046 temp);
3047
3048 /* Wait for initialization time */
3049 udelay(24);
3050
3051 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3052}
3053
f67a559d
JB		 3054/*
3055 * Enable PCH resources required for PCH ports:
3056 * - PCH PLLs
3057 * - FDI training & RX/TX
3058 * - update transcoder timings
3059 * - DP transcoding bits
3060 * - transcoder
3061 */
3062static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3063{
3064 struct drm_device *dev = crtc->dev;
3065 struct drm_i915_private *dev_priv = dev->dev_private;
3066 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3067 int pipe = intel_crtc->pipe;
ee7b9f93 3068 u32 reg, temp;
2c07245f 3069
e7e164db
CW		 3070 assert_transcoder_disabled(dev_priv, pipe);
3071
cd986abb
DV		 3072 /* Write the TU size bits before fdi link training, so that error
3073 * detection works. */
3074 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3075 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3076
c98e9dcf 3077 /* For PCH output, training FDI link */
674cf967 3078 dev_priv->display.fdi_link_train(crtc);
2c07245f 3079
572deb37
DV		 3080 /* XXX: pch pll's can be enabled any time before we enable the PCH
3081 * transcoder, and we actually should do this to not upset any PCH
3082 * transcoder that already use the clock when we share it.
3083 *
3084 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3085 * unconditionally resets the pll - we need that to have the right LVDS
3086 * enable sequence. */
b6b4e185 3087 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3088
303b81e0 3089 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3090 u32 sel;
4b645f14 3091
c98e9dcf 3092 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3093 switch (pipe) {
3094 default:
3095 case 0:
3096 temp |= TRANSA_DPLL_ENABLE;
3097 sel = TRANSA_DPLLB_SEL;
3098 break;
3099 case 1:
3100 temp |= TRANSB_DPLL_ENABLE;
3101 sel = TRANSB_DPLLB_SEL;
3102 break;
3103 case 2:
3104 temp |= TRANSC_DPLL_ENABLE;
3105 sel = TRANSC_DPLLB_SEL;
3106 break;
d64311ab 3107 }
ee7b9f93
JB		 3108 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3109 temp |= sel;
3110 else
3111 temp &= ~sel;
c98e9dcf 3112 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3113 }
5eddb70b 3114
d9b6cb56
JB		 3115 /* set transcoder timing, panel must allow it */
3116 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3117 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3118 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3119 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3120
5eddb70b
CW		 3121 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3122 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3123 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3124 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3125
303b81e0 3126 intel_fdi_normal_train(crtc);
5e84e1a4 3127
c98e9dcf
JB		 3128 /* For PCH DP, enable TRANS_DP_CTL */
3129 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3130 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3131 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 3132 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 3133 reg = TRANS_DP_CTL(pipe);
3134 temp = I915_READ(reg);
3135 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3136 TRANS_DP_SYNC_MASK |
3137 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3138 temp |= (TRANS_DP_OUTPUT_ENABLE |
3139 TRANS_DP_ENH_FRAMING);
9325c9f0 3140 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3141
3142 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3143 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3144 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3145 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3146
3147 switch (intel_trans_dp_port_sel(crtc)) {
3148 case PCH_DP_B:
5eddb70b 3149 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3150 break;
3151 case PCH_DP_C:
5eddb70b 3152 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3153 break;
3154 case PCH_DP_D:
5eddb70b 3155 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3156 break;
3157 default:
e95d41e1 3158 BUG();
32f9d658 3159 }
2c07245f 3160
5eddb70b 3161 I915_WRITE(reg, temp);
6be4a607 3162 }
b52eb4dc 3163
040484af 3164 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 3165}
3166
1507e5bd
PZ		 3167static void lpt_pch_enable(struct drm_crtc *crtc)
3168{
3169 struct drm_device *dev = crtc->dev;
3170 struct drm_i915_private *dev_priv = dev->dev_private;
3171 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3172 int pipe = intel_crtc->pipe;
1507e5bd
PZ		 3173
3174 assert_transcoder_disabled(dev_priv, pipe);
3175
3176 /* Write the TU size bits before fdi link training, so that error
3177 * detection works. */
3178 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3179 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3180
3181 /* For PCH output, training FDI link */
3182 dev_priv->display.fdi_link_train(crtc);
3183
8c52b5e8 3184 lpt_program_iclkip(crtc);
1507e5bd 3185
0540e488 3186 /* Set transcoder timing. */
1507e5bd
PZ		 3187 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3188 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3189 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3190
3191 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3192 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3193 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
3194 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
3195
1507e5bd
PZ		 3196 intel_enable_transcoder(dev_priv, pipe);
3197}
3198
ee7b9f93
JB		 3199static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3200{
3201 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3202
3203 if (pll == NULL)
3204 return;
3205
3206 if (pll->refcount == 0) {
3207 WARN(1, "bad PCH PLL refcount\n");
3208 return;
3209 }
3210
3211 --pll->refcount;
3212 intel_crtc->pch_pll = NULL;
3213}
3214
3215static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3216{
3217 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3218 struct intel_pch_pll *pll;
3219 int i;
3220
3221 pll = intel_crtc->pch_pll;
3222 if (pll) {
3223 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3224 intel_crtc->base.base.id, pll->pll_reg);
3225 goto prepare;
3226 }
3227
98b6bd99
DV		 3228 if (HAS_PCH_IBX(dev_priv->dev)) {
3229 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3230 i = intel_crtc->pipe;
3231 pll = &dev_priv->pch_plls[i];
3232
3233 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3234 intel_crtc->base.base.id, pll->pll_reg);
3235
3236 goto found;
3237 }
3238
ee7b9f93
JB		 3239 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3240 pll = &dev_priv->pch_plls[i];
3241
3242 /* Only want to check enabled timings first */
3243 if (pll->refcount == 0)
3244 continue;
3245
3246 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3247 fp == I915_READ(pll->fp0_reg)) {
3248 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3249 intel_crtc->base.base.id,
3250 pll->pll_reg, pll->refcount, pll->active);
3251
3252 goto found;
3253 }
3254 }
3255
3256 /* Ok no matching timings, maybe there's a free one? */
3257 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3258 pll = &dev_priv->pch_plls[i];
3259 if (pll->refcount == 0) {
3260 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3261 intel_crtc->base.base.id, pll->pll_reg);
3262 goto found;
3263 }
3264 }
3265
3266 return NULL;
3267
3268found:
3269 intel_crtc->pch_pll = pll;
3270 pll->refcount++;
3271 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3272prepare: /* separate function? */
3273 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3274
e04c7350
CW		 3275 /* Wait for the clocks to stabilize before rewriting the regs */
3276 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3277 POSTING_READ(pll->pll_reg);
3278 udelay(150);
e04c7350
CW		 3279
3280 I915_WRITE(pll->fp0_reg, fp);
3281 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3282 pll->on = false;
3283 return pll;
3284}
3285
d4270e57
JB		 3286void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3287{
3288 struct drm_i915_private *dev_priv = dev->dev_private;
3289 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3290 u32 temp;
3291
3292 temp = I915_READ(dslreg);
3293 udelay(500);
3294 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3295 /* Without this, mode sets may fail silently on FDI */
3296 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3297 udelay(250);
3298 I915_WRITE(tc2reg, 0);
3299 if (wait_for(I915_READ(dslreg) != temp, 5))
3300 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3301 }
3302}
3303
f67a559d
JB		 3304static void ironlake_crtc_enable(struct drm_crtc *crtc)
3305{
3306 struct drm_device *dev = crtc->dev;
3307 struct drm_i915_private *dev_priv = dev->dev_private;
3308 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3309 struct intel_encoder *encoder;
f67a559d
JB		 3310 int pipe = intel_crtc->pipe;
3311 int plane = intel_crtc->plane;
3312 u32 temp;
3313 bool is_pch_port;
3314
08a48469
DV		 3315 WARN_ON(!crtc->enabled);
3316
f67a559d
JB		 3317 if (intel_crtc->active)
3318 return;
3319
3320 intel_crtc->active = true;
3321 intel_update_watermarks(dev);
3322
3323 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3324 temp = I915_READ(PCH_LVDS);
3325 if ((temp & LVDS_PORT_EN) == 0)
3326 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3327 }
3328
fc316cbe 3329 is_pch_port = ironlake_crtc_driving_pch(crtc);
f67a559d 3330
46b6f814 3331 if (is_pch_port) {
fff367c7
DV		 3332 /* Note: FDI PLL enabling _must_ be done before we enable the
3333 * cpu pipes, hence this is separate from all the other fdi/pch
3334 * enabling. */
88cefb6c 3335 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3336 } else {
3337 assert_fdi_tx_disabled(dev_priv, pipe);
3338 assert_fdi_rx_disabled(dev_priv, pipe);
3339 }
f67a559d 3340
bf49ec8c
DV		 3341 for_each_encoder_on_crtc(dev, crtc, encoder)
3342 if (encoder->pre_enable)
3343 encoder->pre_enable(encoder);
3344
f67a559d
JB		 3345 /* Enable panel fitting for LVDS */
3346 if (dev_priv->pch_pf_size &&
3347 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3348 /* Force use of hard-coded filter coefficients
3349 * as some pre-programmed values are broken,
3350 * e.g. x201.
3351 */
9db4a9c7
JB		 3352 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3353 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3354 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3355 }
3356
9c54c0dd
JB		 3357 /*
3358 * On ILK+ LUT must be loaded before the pipe is running but with
3359 * clocks enabled
3360 */
3361 intel_crtc_load_lut(crtc);
3362
f67a559d
JB		 3363 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3364 intel_enable_plane(dev_priv, plane, pipe);
3365
3366 if (is_pch_port)
3367 ironlake_pch_enable(crtc);
c98e9dcf 3368
d1ebd816 3369 mutex_lock(&dev->struct_mutex);
bed4a673 3370 intel_update_fbc(dev);
d1ebd816
BW		 3371 mutex_unlock(&dev->struct_mutex);
3372
6b383a7f 3373 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3374
fa5c73b1
DV		 3375 for_each_encoder_on_crtc(dev, crtc, encoder)
3376 encoder->enable(encoder);
61b77ddd
DV		 3377
3378 if (HAS_PCH_CPT(dev))
3379 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3380
3381 /*
3382 * There seems to be a race in PCH platform hw (at least on some
3383 * outputs) where an enabled pipe still completes any pageflip right
3384 * away (as if the pipe is off) instead of waiting for vblank. As soon
3385 * as the first vblank happend, everything works as expected. Hence just
3386 * wait for one vblank before returning to avoid strange things
3387 * happening.
3388 */
3389 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3390}
3391
4f771f10
PZ		 3392static void haswell_crtc_enable(struct drm_crtc *crtc)
3393{
3394 struct drm_device *dev = crtc->dev;
3395 struct drm_i915_private *dev_priv = dev->dev_private;
3396 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3397 struct intel_encoder *encoder;
3398 int pipe = intel_crtc->pipe;
3399 int plane = intel_crtc->plane;
4f771f10
PZ		 3400 bool is_pch_port;
3401
3402 WARN_ON(!crtc->enabled);
3403
3404 if (intel_crtc->active)
3405 return;
3406
3407 intel_crtc->active = true;
3408 intel_update_watermarks(dev);
3409
fc316cbe 3410 is_pch_port = haswell_crtc_driving_pch(crtc);
4f771f10 3411
83616634 3412 if (is_pch_port)
4f771f10 3413 ironlake_fdi_pll_enable(intel_crtc);
4f771f10
PZ		 3414
3415 for_each_encoder_on_crtc(dev, crtc, encoder)
3416 if (encoder->pre_enable)
3417 encoder->pre_enable(encoder);
3418
1f544388 3419 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3420
1f544388
PZ		 3421 /* Enable panel fitting for eDP */
3422 if (dev_priv->pch_pf_size && HAS_eDP) {
4f771f10
PZ		 3423 /* Force use of hard-coded filter coefficients
3424 * as some pre-programmed values are broken,
3425 * e.g. x201.
3426 */
3427 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3428 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3429 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3430 }
3431
3432 /*
3433 * On ILK+ LUT must be loaded before the pipe is running but with
3434 * clocks enabled
3435 */
3436 intel_crtc_load_lut(crtc);
3437
1f544388
PZ		 3438 intel_ddi_set_pipe_settings(crtc);
3439 intel_ddi_enable_pipe_func(crtc);
4f771f10
PZ		 3440
3441 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3442 intel_enable_plane(dev_priv, plane, pipe);
3443
3444 if (is_pch_port)
1507e5bd 3445 lpt_pch_enable(crtc);
4f771f10
PZ		 3446
3447 mutex_lock(&dev->struct_mutex);
3448 intel_update_fbc(dev);
3449 mutex_unlock(&dev->struct_mutex);
3450
3451 intel_crtc_update_cursor(crtc, true);
3452
3453 for_each_encoder_on_crtc(dev, crtc, encoder)
3454 encoder->enable(encoder);
3455
4f771f10
PZ		 3456 /*
3457 * There seems to be a race in PCH platform hw (at least on some
3458 * outputs) where an enabled pipe still completes any pageflip right
3459 * away (as if the pipe is off) instead of waiting for vblank. As soon
3460 * as the first vblank happend, everything works as expected. Hence just
3461 * wait for one vblank before returning to avoid strange things
3462 * happening.
3463 */
3464 intel_wait_for_vblank(dev, intel_crtc->pipe);
3465}
3466
6be4a607
JB		 3467static void ironlake_crtc_disable(struct drm_crtc *crtc)
3468{
3469 struct drm_device *dev = crtc->dev;
3470 struct drm_i915_private *dev_priv = dev->dev_private;
3471 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3472 struct intel_encoder *encoder;
6be4a607
JB		 3473 int pipe = intel_crtc->pipe;
3474 int plane = intel_crtc->plane;
5eddb70b 3475 u32 reg, temp;
b52eb4dc 3476
ef9c3aee 3477
f7abfe8b
CW		 3478 if (!intel_crtc->active)
3479 return;
3480
ea9d758d
DV		 3481 for_each_encoder_on_crtc(dev, crtc, encoder)
3482 encoder->disable(encoder);
3483
e6c3a2a6 3484 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3485 drm_vblank_off(dev, pipe);
6b383a7f 3486 intel_crtc_update_cursor(crtc, false);
5eddb70b 3487
b24e7179 3488 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3489
973d04f9
CW		 3490 if (dev_priv->cfb_plane == plane)
3491 intel_disable_fbc(dev);
2c07245f 3492
b24e7179 3493 intel_disable_pipe(dev_priv, pipe);
32f9d658 3494
6be4a607 3495 /* Disable PF */
9db4a9c7
JB		 3496 I915_WRITE(PF_CTL(pipe), 0);
3497 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3498
bf49ec8c
DV		 3499 for_each_encoder_on_crtc(dev, crtc, encoder)
3500 if (encoder->post_disable)
3501 encoder->post_disable(encoder);
3502
0fc932b8 3503 ironlake_fdi_disable(crtc);
2c07245f 3504
040484af 3505 intel_disable_transcoder(dev_priv, pipe);
913d8d11 3506
6be4a607
JB		 3507 if (HAS_PCH_CPT(dev)) {
3508 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3509 reg = TRANS_DP_CTL(pipe);
3510 temp = I915_READ(reg);
3511 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3512 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3513 I915_WRITE(reg, temp);
6be4a607
JB		 3514
3515 /* disable DPLL_SEL */
3516 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3517 switch (pipe) {
3518 case 0:
d64311ab 3519 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3520 break;
3521 case 1:
6be4a607 3522 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3523 break;
3524 case 2:
4b645f14 3525 /* C shares PLL A or B */
d64311ab 3526 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3527 break;
3528 default:
3529 BUG(); /* wtf */
3530 }
6be4a607 3531 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3532 }
e3421a18 3533
6be4a607 3534 /* disable PCH DPLL */
ee7b9f93 3535 intel_disable_pch_pll(intel_crtc);
8db9d77b 3536
88cefb6c 3537 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3538
f7abfe8b 3539 intel_crtc->active = false;
6b383a7f 3540 intel_update_watermarks(dev);
d1ebd816
BW		 3541
3542 mutex_lock(&dev->struct_mutex);
6b383a7f 3543 intel_update_fbc(dev);
d1ebd816 3544 mutex_unlock(&dev->struct_mutex);
6be4a607 3545}
1b3c7a47 3546
4f771f10
PZ		 3547static void haswell_crtc_disable(struct drm_crtc *crtc)
3548{
3549 struct drm_device *dev = crtc->dev;
3550 struct drm_i915_private *dev_priv = dev->dev_private;
3551 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3552 struct intel_encoder *encoder;
3553 int pipe = intel_crtc->pipe;
3554 int plane = intel_crtc->plane;
ad80a810 3555 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
83616634 3556 bool is_pch_port;
4f771f10
PZ		 3557
3558 if (!intel_crtc->active)
3559 return;
3560
83616634
PZ		 3561 is_pch_port = haswell_crtc_driving_pch(crtc);
3562
4f771f10
PZ		 3563 for_each_encoder_on_crtc(dev, crtc, encoder)
3564 encoder->disable(encoder);
3565
3566 intel_crtc_wait_for_pending_flips(crtc);
3567 drm_vblank_off(dev, pipe);
3568 intel_crtc_update_cursor(crtc, false);
3569
3570 intel_disable_plane(dev_priv, plane, pipe);
3571
3572 if (dev_priv->cfb_plane == plane)
3573 intel_disable_fbc(dev);
3574
3575 intel_disable_pipe(dev_priv, pipe);
3576
ad80a810 3577 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10
PZ		 3578
3579 /* Disable PF */
3580 I915_WRITE(PF_CTL(pipe), 0);
3581 I915_WRITE(PF_WIN_SZ(pipe), 0);
3582
1f544388 3583 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3584
3585 for_each_encoder_on_crtc(dev, crtc, encoder)
3586 if (encoder->post_disable)
3587 encoder->post_disable(encoder);
3588
83616634
PZ		 3589 if (is_pch_port) {
3590 ironlake_fdi_disable(crtc);
3591 intel_disable_transcoder(dev_priv, pipe);
3592 intel_disable_pch_pll(intel_crtc);
3593 ironlake_fdi_pll_disable(intel_crtc);
3594 }
4f771f10
PZ		 3595
3596 intel_crtc->active = false;
3597 intel_update_watermarks(dev);
3598
3599 mutex_lock(&dev->struct_mutex);
3600 intel_update_fbc(dev);
3601 mutex_unlock(&dev->struct_mutex);
3602}
3603
ee7b9f93
JB		 3604static void ironlake_crtc_off(struct drm_crtc *crtc)
3605{
3606 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3607 intel_put_pch_pll(intel_crtc);
3608}
3609
6441ab5f
PZ		 3610static void haswell_crtc_off(struct drm_crtc *crtc)
3611{
a5c961d1
PZ		 3612 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3613
3614 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3615 * start using it. */
3616 intel_crtc->cpu_transcoder = intel_crtc->pipe;
3617
6441ab5f
PZ		 3618 intel_ddi_put_crtc_pll(crtc);
3619}
3620
02e792fb
DV		 3621static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3622{
02e792fb 3623 if (!enable && intel_crtc->overlay) {
23f09ce3 3624 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3625 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3626
23f09ce3 3627 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3628 dev_priv->mm.interruptible = false;
3629 (void) intel_overlay_switch_off(intel_crtc->overlay);
3630 dev_priv->mm.interruptible = true;
23f09ce3 3631 mutex_unlock(&dev->struct_mutex);
02e792fb 3632 }
02e792fb 3633
5dcdbcb0
CW		 3634 /* Let userspace switch the overlay on again. In most cases userspace
3635 * has to recompute where to put it anyway.
3636 */
02e792fb
DV		 3637}
3638
0b8765c6 3639static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3640{
3641 struct drm_device *dev = crtc->dev;
79e53945
JB		 3642 struct drm_i915_private *dev_priv = dev->dev_private;
3643 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3644 struct intel_encoder *encoder;
79e53945 3645 int pipe = intel_crtc->pipe;
80824003 3646 int plane = intel_crtc->plane;
79e53945 3647
08a48469
DV		 3648 WARN_ON(!crtc->enabled);
3649
f7abfe8b
CW		 3650 if (intel_crtc->active)
3651 return;
3652
3653 intel_crtc->active = true;
6b383a7f
CW		 3654 intel_update_watermarks(dev);
3655
63d7bbe9 3656 intel_enable_pll(dev_priv, pipe);
040484af 3657 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3658 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3659
0b8765c6 3660 intel_crtc_load_lut(crtc);
bed4a673 3661 intel_update_fbc(dev);
79e53945 3662
0b8765c6
JB		 3663 /* Give the overlay scaler a chance to enable if it's on this pipe */
3664 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3665 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3666
fa5c73b1
DV		 3667 for_each_encoder_on_crtc(dev, crtc, encoder)
3668 encoder->enable(encoder);
0b8765c6 3669}
79e53945 3670
0b8765c6
JB		 3671static void i9xx_crtc_disable(struct drm_crtc *crtc)
3672{
3673 struct drm_device *dev = crtc->dev;
3674 struct drm_i915_private *dev_priv = dev->dev_private;
3675 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3676 struct intel_encoder *encoder;
0b8765c6
JB		 3677 int pipe = intel_crtc->pipe;
3678 int plane = intel_crtc->plane;
b690e96c 3679
ef9c3aee 3680
f7abfe8b
CW		 3681 if (!intel_crtc->active)
3682 return;
3683
ea9d758d
DV		 3684 for_each_encoder_on_crtc(dev, crtc, encoder)
3685 encoder->disable(encoder);
3686
0b8765c6 3687 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3688 intel_crtc_wait_for_pending_flips(crtc);
3689 drm_vblank_off(dev, pipe);
0b8765c6 3690 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3691 intel_crtc_update_cursor(crtc, false);
0b8765c6 3692
973d04f9
CW		 3693 if (dev_priv->cfb_plane == plane)
3694 intel_disable_fbc(dev);
79e53945 3695
b24e7179 3696 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3697 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3698 intel_disable_pll(dev_priv, pipe);
0b8765c6 3699
f7abfe8b 3700 intel_crtc->active = false;
6b383a7f
CW		 3701 intel_update_fbc(dev);
3702 intel_update_watermarks(dev);
0b8765c6
JB		 3703}
3704
ee7b9f93
JB		 3705static void i9xx_crtc_off(struct drm_crtc *crtc)
3706{
3707}
3708
976f8a20
DV		 3709static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3710 bool enabled)
2c07245f
ZW		 3711{
3712 struct drm_device *dev = crtc->dev;
3713 struct drm_i915_master_private *master_priv;
3714 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3715 int pipe = intel_crtc->pipe;
79e53945
JB		 3716
3717 if (!dev->primary->master)
3718 return;
3719
3720 master_priv = dev->primary->master->driver_priv;
3721 if (!master_priv->sarea_priv)
3722 return;
3723
79e53945
JB		 3724 switch (pipe) {
3725 case 0:
3726 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3727 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3728 break;
3729 case 1:
3730 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3731 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3732 break;
3733 default:
9db4a9c7 3734 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3735 break;
3736 }
79e53945
JB		 3737}
3738
976f8a20
DV		 3739/**
3740 * Sets the power management mode of the pipe and plane.
3741 */
3742void intel_crtc_update_dpms(struct drm_crtc *crtc)
3743{
3744 struct drm_device *dev = crtc->dev;
3745 struct drm_i915_private *dev_priv = dev->dev_private;
3746 struct intel_encoder *intel_encoder;
3747 bool enable = false;
3748
3749 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3750 enable |= intel_encoder->connectors_active;
3751
3752 if (enable)
3753 dev_priv->display.crtc_enable(crtc);
3754 else
3755 dev_priv->display.crtc_disable(crtc);
3756
3757 intel_crtc_update_sarea(crtc, enable);
3758}
3759
3760static void intel_crtc_noop(struct drm_crtc *crtc)
3761{
3762}
3763
cdd59983
CW		 3764static void intel_crtc_disable(struct drm_crtc *crtc)
3765{
cdd59983 3766 struct drm_device *dev = crtc->dev;
976f8a20 3767 struct drm_connector *connector;
ee7b9f93 3768 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 3769
976f8a20
DV		 3770 /* crtc should still be enabled when we disable it. */
3771 WARN_ON(!crtc->enabled);
3772
3773 dev_priv->display.crtc_disable(crtc);
3774 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3775 dev_priv->display.off(crtc);
3776
931872fc
CW		 3777 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3778 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3779
3780 if (crtc->fb) {
3781 mutex_lock(&dev->struct_mutex);
1690e1eb 3782 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3783 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3784 crtc->fb = NULL;
3785 }
3786
3787 /* Update computed state. */
3788 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3789 if (!connector->encoder || !connector->encoder->crtc)
3790 continue;
3791
3792 if (connector->encoder->crtc != crtc)
3793 continue;
3794
3795 connector->dpms = DRM_MODE_DPMS_OFF;
3796 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3797 }
3798}
3799
a261b246 3800void intel_modeset_disable(struct drm_device *dev)
79e53945 3801{
a261b246
DV		 3802 struct drm_crtc *crtc;
3803
3804 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3805 if (crtc->enabled)
3806 intel_crtc_disable(crtc);
3807 }
79e53945
JB		 3808}
3809
1f703855 3810void intel_encoder_noop(struct drm_encoder *encoder)
79e53945 3811{
7e7d76c3
JB		 3812}
3813
ea5b213a 3814void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3815{
4ef69c7a 3816 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3817
ea5b213a
CW		 3818 drm_encoder_cleanup(encoder);
3819 kfree(intel_encoder);
7e7d76c3
JB		 3820}
3821
5ab432ef
DV		 3822/* Simple dpms helper for encodres with just one connector, no cloning and only
3823 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3824 * state of the entire output pipe. */
3825void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3826{
5ab432ef
DV		 3827 if (mode == DRM_MODE_DPMS_ON) {
3828 encoder->connectors_active = true;
3829
b2cabb0e 3830 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3831 } else {
3832 encoder->connectors_active = false;
3833
b2cabb0e 3834 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3835 }
79e53945
JB		 3836}
3837
0a91ca29
DV		 3838/* Cross check the actual hw state with our own modeset state tracking (and it's
3839 * internal consistency). */
b980514c 3840static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3841{
0a91ca29
DV		 3842 if (connector->get_hw_state(connector)) {
3843 struct intel_encoder *encoder = connector->encoder;
3844 struct drm_crtc *crtc;
3845 bool encoder_enabled;
3846 enum pipe pipe;
3847
3848 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3849 connector->base.base.id,
3850 drm_get_connector_name(&connector->base));
3851
3852 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3853 "wrong connector dpms state\n");
3854 WARN(connector->base.encoder != &encoder->base,
3855 "active connector not linked to encoder\n");
3856 WARN(!encoder->connectors_active,
3857 "encoder->connectors_active not set\n");
3858
3859 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3860 WARN(!encoder_enabled, "encoder not enabled\n");
3861 if (WARN_ON(!encoder->base.crtc))
3862 return;
3863
3864 crtc = encoder->base.crtc;
3865
3866 WARN(!crtc->enabled, "crtc not enabled\n");
3867 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3868 WARN(pipe != to_intel_crtc(crtc)->pipe,
3869 "encoder active on the wrong pipe\n");
3870 }
79e53945
JB		 3871}
3872
5ab432ef
DV		 3873/* Even simpler default implementation, if there's really no special case to
3874 * consider. */
3875void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3876{
5ab432ef 3877 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3878
5ab432ef
DV		 3879 /* All the simple cases only support two dpms states. */
3880 if (mode != DRM_MODE_DPMS_ON)
3881 mode = DRM_MODE_DPMS_OFF;
d4270e57 3882
5ab432ef
DV		 3883 if (mode == connector->dpms)
3884 return;
3885
3886 connector->dpms = mode;
3887
3888 /* Only need to change hw state when actually enabled */
3889 if (encoder->base.crtc)
3890 intel_encoder_dpms(encoder, mode);
3891 else
8af6cf88 3892 WARN_ON(encoder->connectors_active != false);
0a91ca29 3893
b980514c 3894 intel_modeset_check_state(connector->dev);
79e53945
JB		 3895}
3896
f0947c37
DV		 3897/* Simple connector->get_hw_state implementation for encoders that support only
3898 * one connector and no cloning and hence the encoder state determines the state
3899 * of the connector. */
3900bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3901{
24929352 3902 enum pipe pipe = 0;
f0947c37 3903 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3904
f0947c37 3905 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3906}
3907
79e53945 3908static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
35313cde 3909 const struct drm_display_mode *mode,
79e53945
JB		 3910 struct drm_display_mode *adjusted_mode)
3911{
2c07245f 3912 struct drm_device *dev = crtc->dev;
89749350 3913
bad720ff 3914 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3915 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3916 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3917 return false;
2c07245f 3918 }
89749350 3919
f9bef081
DV		 3920 /* All interlaced capable intel hw wants timings in frames. Note though
3921 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3922 * timings, so we need to be careful not to clobber these.*/
3923 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3924 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3925
44f46b42
CW		 3926 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3927 * with a hsync front porch of 0.
3928 */
3929 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3930 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3931 return false;
3932
79e53945
JB		 3933 return true;
3934}
3935
25eb05fc
JB		 3936static int valleyview_get_display_clock_speed(struct drm_device *dev)
3937{
3938 return 400000; /* FIXME */
3939}
3940
e70236a8
JB		 3941static int i945_get_display_clock_speed(struct drm_device *dev)
3942{
3943 return 400000;
3944}
79e53945 3945
e70236a8 3946static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3947{
e70236a8
JB		 3948 return 333000;
3949}
79e53945 3950
e70236a8
JB		 3951static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3952{
3953 return 200000;
3954}
79e53945 3955
e70236a8
JB		 3956static int i915gm_get_display_clock_speed(struct drm_device *dev)
3957{
3958 u16 gcfgc = 0;
79e53945 3959
e70236a8
JB		 3960 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3961
3962 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3963 return 133000;
3964 else {
3965 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3966 case GC_DISPLAY_CLOCK_333_MHZ:
3967 return 333000;
3968 default:
3969 case GC_DISPLAY_CLOCK_190_200_MHZ:
3970 return 190000;
79e53945 3971 }
e70236a8
JB		 3972 }
3973}
3974
3975static int i865_get_display_clock_speed(struct drm_device *dev)
3976{
3977 return 266000;
3978}
3979
3980static int i855_get_display_clock_speed(struct drm_device *dev)
3981{
3982 u16 hpllcc = 0;
3983 /* Assume that the hardware is in the high speed state. This
3984 * should be the default.
3985 */
3986 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3987 case GC_CLOCK_133_200:
3988 case GC_CLOCK_100_200:
3989 return 200000;
3990 case GC_CLOCK_166_250:
3991 return 250000;
3992 case GC_CLOCK_100_133:
79e53945 3993 return 133000;
e70236a8 3994 }
79e53945 3995
e70236a8
JB		 3996 /* Shouldn't happen */
3997 return 0;
3998}
79e53945 3999
e70236a8
JB		 4000static int i830_get_display_clock_speed(struct drm_device *dev)
4001{
4002 return 133000;
79e53945
JB		 4003}
4004
2c07245f
ZW		 4005struct fdi_m_n {
4006 u32 tu;
4007 u32 gmch_m;
4008 u32 gmch_n;
4009 u32 link_m;
4010 u32 link_n;
4011};
4012
4013static void
4014fdi_reduce_ratio(u32 *num, u32 *den)
4015{
4016 while (*num > 0xffffff || *den > 0xffffff) {
4017 *num >>= 1;
4018 *den >>= 1;
4019 }
4020}
4021
2c07245f 4022static void
f2b115e6
AJ		 4023ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
4024 int link_clock, struct fdi_m_n *m_n)
2c07245f 4025{
2c07245f
ZW		 4026 m_n->tu = 64; /* default size */
4027
22ed1113
CW		 4028 /* BUG_ON(pixel_clock > INT_MAX / 36); */
4029 m_n->gmch_m = bits_per_pixel * pixel_clock;
4030 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 4031 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4032
22ed1113
CW		 4033 m_n->link_m = pixel_clock;
4034 m_n->link_n = link_clock;
2c07245f
ZW		 4035 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
4036}
4037
a7615030
CW		 4038static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4039{
72bbe58c
KP		 4040 if (i915_panel_use_ssc >= 0)
4041 return i915_panel_use_ssc != 0;
4042 return dev_priv->lvds_use_ssc
435793df 4043 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4044}
4045
5a354204
JB		 4046/**
4047 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4048 * @crtc: CRTC structure
3b5c78a3 4049 * @mode: requested mode
5a354204
JB		 4050 *
4051 * A pipe may be connected to one or more outputs. Based on the depth of the
4052 * attached framebuffer, choose a good color depth to use on the pipe.
4053 *
4054 * If possible, match the pipe depth to the fb depth. In some cases, this
4055 * isn't ideal, because the connected output supports a lesser or restricted
4056 * set of depths. Resolve that here:
4057 * LVDS typically supports only 6bpc, so clamp down in that case
4058 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4059 * Displays may support a restricted set as well, check EDID and clamp as
4060 * appropriate.
3b5c78a3 4061 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 4062 *
4063 * RETURNS:
4064 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4065 * true if they don't match).
4066 */
4067static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
94352cf9 4068 struct drm_framebuffer *fb,
3b5c78a3
AJ		 4069 unsigned int *pipe_bpp,
4070 struct drm_display_mode *mode)
5a354204
JB		 4071{
4072 struct drm_device *dev = crtc->dev;
4073 struct drm_i915_private *dev_priv = dev->dev_private;
5a354204 4074 struct drm_connector *connector;
6c2b7c12 4075 struct intel_encoder *intel_encoder;
5a354204
JB		 4076 unsigned int display_bpc = UINT_MAX, bpc;
4077
4078 /* Walk the encoders & connectors on this crtc, get min bpc */
6c2b7c12 4079 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5a354204
JB		 4080
4081 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4082 unsigned int lvds_bpc;
4083
4084 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4085 LVDS_A3_POWER_UP)
4086 lvds_bpc = 8;
4087 else
4088 lvds_bpc = 6;
4089
4090 if (lvds_bpc < display_bpc) {
82820490 4091 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 4092 display_bpc = lvds_bpc;
4093 }
4094 continue;
4095 }
4096
5a354204
JB		 4097 /* Not one of the known troublemakers, check the EDID */
4098 list_for_each_entry(connector, &dev->mode_config.connector_list,
4099 head) {
6c2b7c12 4100 if (connector->encoder != &intel_encoder->base)
5a354204
JB		 4101 continue;
4102
62ac41a6
JB		 4103 /* Don't use an invalid EDID bpc value */
4104 if (connector->display_info.bpc &&
4105 connector->display_info.bpc < display_bpc) {
82820490 4106 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 4107 display_bpc = connector->display_info.bpc;
4108 }
4109 }
4110
4111 /*
4112 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4113 * through, clamp it down. (Note: >12bpc will be caught below.)
4114 */
4115 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4116 if (display_bpc > 8 && display_bpc < 12) {
82820490 4117 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 4118 display_bpc = 12;
4119 } else {
82820490 4120 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 4121 display_bpc = 8;
4122 }
4123 }
4124 }
4125
3b5c78a3
AJ		 4126 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4127 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4128 display_bpc = 6;
4129 }
4130
5a354204
JB		 4131 /*
4132 * We could just drive the pipe at the highest bpc all the time and
4133 * enable dithering as needed, but that costs bandwidth. So choose
4134 * the minimum value that expresses the full color range of the fb but
4135 * also stays within the max display bpc discovered above.
4136 */
4137
94352cf9 4138 switch (fb->depth) {
5a354204
JB		 4139 case 8:
4140 bpc = 8; /* since we go through a colormap */
4141 break;
4142 case 15:
4143 case 16:
4144 bpc = 6; /* min is 18bpp */
4145 break;
4146 case 24:
578393cd 4147 bpc = 8;
5a354204
JB		 4148 break;
4149 case 30:
578393cd 4150 bpc = 10;
5a354204
JB		 4151 break;
4152 case 48:
578393cd 4153 bpc = 12;
5a354204
JB		 4154 break;
4155 default:
4156 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4157 bpc = min((unsigned int)8, display_bpc);
4158 break;
4159 }
4160
578393cd
KP		 4161 display_bpc = min(display_bpc, bpc);
4162
82820490
AJ		 4163 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4164 bpc, display_bpc);
5a354204 4165
578393cd 4166 *pipe_bpp = display_bpc * 3;
5a354204
JB		 4167
4168 return display_bpc != bpc;
4169}
4170
a0c4da24
JB		 4171static int vlv_get_refclk(struct drm_crtc *crtc)
4172{
4173 struct drm_device *dev = crtc->dev;
4174 struct drm_i915_private *dev_priv = dev->dev_private;
4175 int refclk = 27000; /* for DP & HDMI */
4176
4177 return 100000; /* only one validated so far */
4178
4179 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4180 refclk = 96000;
4181 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4182 if (intel_panel_use_ssc(dev_priv))
4183 refclk = 100000;
4184 else
4185 refclk = 96000;
4186 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4187 refclk = 100000;
4188 }
4189
4190 return refclk;
4191}
4192
c65d77d8
JB		 4193static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4194{
4195 struct drm_device *dev = crtc->dev;
4196 struct drm_i915_private *dev_priv = dev->dev_private;
4197 int refclk;
4198
a0c4da24
JB		 4199 if (IS_VALLEYVIEW(dev)) {
4200 refclk = vlv_get_refclk(crtc);
4201 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4202 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4203 refclk = dev_priv->lvds_ssc_freq * 1000;
4204 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4205 refclk / 1000);
4206 } else if (!IS_GEN2(dev)) {
4207 refclk = 96000;
4208 } else {
4209 refclk = 48000;
4210 }
4211
4212 return refclk;
4213}
4214
4215static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4216 intel_clock_t *clock)
4217{
4218 /* SDVO TV has fixed PLL values depend on its clock range,
4219 this mirrors vbios setting. */
4220 if (adjusted_mode->clock >= 100000
4221 && adjusted_mode->clock < 140500) {
4222 clock->p1 = 2;
4223 clock->p2 = 10;
4224 clock->n = 3;
4225 clock->m1 = 16;
4226 clock->m2 = 8;
4227 } else if (adjusted_mode->clock >= 140500
4228 && adjusted_mode->clock <= 200000) {
4229 clock->p1 = 1;
4230 clock->p2 = 10;
4231 clock->n = 6;
4232 clock->m1 = 12;
4233 clock->m2 = 8;
4234 }
4235}
4236
a7516a05
JB		 4237static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4238 intel_clock_t *clock,
4239 intel_clock_t *reduced_clock)
4240{
4241 struct drm_device *dev = crtc->dev;
4242 struct drm_i915_private *dev_priv = dev->dev_private;
4243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4244 int pipe = intel_crtc->pipe;
4245 u32 fp, fp2 = 0;
4246
4247 if (IS_PINEVIEW(dev)) {
4248 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4249 if (reduced_clock)
4250 fp2 = (1 << reduced_clock->n) << 16 |
4251 reduced_clock->m1 << 8 | reduced_clock->m2;
4252 } else {
4253 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4254 if (reduced_clock)
4255 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4256 reduced_clock->m2;
4257 }
4258
4259 I915_WRITE(FP0(pipe), fp);
4260
4261 intel_crtc->lowfreq_avail = false;
4262 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4263 reduced_clock && i915_powersave) {
4264 I915_WRITE(FP1(pipe), fp2);
4265 intel_crtc->lowfreq_avail = true;
4266 } else {
4267 I915_WRITE(FP1(pipe), fp);
4268 }
4269}
4270
93e537a1
DV		 4271static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4272 struct drm_display_mode *adjusted_mode)
4273{
4274 struct drm_device *dev = crtc->dev;
4275 struct drm_i915_private *dev_priv = dev->dev_private;
4276 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4277 int pipe = intel_crtc->pipe;
284d5df5 4278 u32 temp;
93e537a1
DV		 4279
4280 temp = I915_READ(LVDS);
4281 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4282 if (pipe == 1) {
4283 temp |= LVDS_PIPEB_SELECT;
4284 } else {
4285 temp &= ~LVDS_PIPEB_SELECT;
4286 }
4287 /* set the corresponsding LVDS_BORDER bit */
4288 temp |= dev_priv->lvds_border_bits;
4289 /* Set the B0-B3 data pairs corresponding to whether we're going to
4290 * set the DPLLs for dual-channel mode or not.
4291 */
4292 if (clock->p2 == 7)
4293 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4294 else
4295 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4296
4297 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4298 * appropriately here, but we need to look more thoroughly into how
4299 * panels behave in the two modes.
4300 */
4301 /* set the dithering flag on LVDS as needed */
4302 if (INTEL_INFO(dev)->gen >= 4) {
4303 if (dev_priv->lvds_dither)
4304 temp |= LVDS_ENABLE_DITHER;
4305 else
4306 temp &= ~LVDS_ENABLE_DITHER;
4307 }
284d5df5 4308 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
93e537a1 4309 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 4310 temp |= LVDS_HSYNC_POLARITY;
93e537a1 4311 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 4312 temp |= LVDS_VSYNC_POLARITY;
93e537a1
DV		 4313 I915_WRITE(LVDS, temp);
4314}
4315
a0c4da24
JB		 4316static void vlv_update_pll(struct drm_crtc *crtc,
4317 struct drm_display_mode *mode,
4318 struct drm_display_mode *adjusted_mode,
4319 intel_clock_t *clock, intel_clock_t *reduced_clock,
2a8f64ca 4320 int num_connectors)
a0c4da24
JB		 4321{
4322 struct drm_device *dev = crtc->dev;
4323 struct drm_i915_private *dev_priv = dev->dev_private;
4324 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4325 int pipe = intel_crtc->pipe;
4326 u32 dpll, mdiv, pdiv;
4327 u32 bestn, bestm1, bestm2, bestp1, bestp2;
2a8f64ca
VP		 4328 bool is_sdvo;
4329 u32 temp;
4330
4331 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4332 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
a0c4da24 4333
2a8f64ca
VP		 4334 dpll = DPLL_VGA_MODE_DIS;
4335 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4336 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4337 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4338
4339 I915_WRITE(DPLL(pipe), dpll);
4340 POSTING_READ(DPLL(pipe));
a0c4da24
JB		 4341
4342 bestn = clock->n;
4343 bestm1 = clock->m1;
4344 bestm2 = clock->m2;
4345 bestp1 = clock->p1;
4346 bestp2 = clock->p2;
4347
2a8f64ca
VP		 4348 /*
4349 * In Valleyview PLL and program lane counter registers are exposed
4350 * through DPIO interface
4351 */
a0c4da24
JB		 4352 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4353 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4354 mdiv |= ((bestn << DPIO_N_SHIFT));
4355 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4356 mdiv |= (1 << DPIO_K_SHIFT);
4357 mdiv |= DPIO_ENABLE_CALIBRATION;
4358 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4359
4360 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4361
2a8f64ca 4362 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
a0c4da24 4363 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
2a8f64ca
VP		 4364 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4365 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
a0c4da24
JB		 4366 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4367
2a8f64ca 4368 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
a0c4da24
JB		 4369
4370 dpll |= DPLL_VCO_ENABLE;
4371 I915_WRITE(DPLL(pipe), dpll);
4372 POSTING_READ(DPLL(pipe));
4373 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4374 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4375
2a8f64ca
VP		 4376 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4377
4378 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4379 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4380
4381 I915_WRITE(DPLL(pipe), dpll);
4382
4383 /* Wait for the clocks to stabilize. */
4384 POSTING_READ(DPLL(pipe));
4385 udelay(150);
a0c4da24 4386
2a8f64ca
VP		 4387 temp = 0;
4388 if (is_sdvo) {
4389 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
a0c4da24
JB		 4390 if (temp > 1)
4391 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4392 else
4393 temp = 0;
a0c4da24 4394 }
2a8f64ca
VP		 4395 I915_WRITE(DPLL_MD(pipe), temp);
4396 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4397
2a8f64ca
VP		 4398 /* Now program lane control registers */
4399 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4400 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4401 {
4402 temp = 0x1000C4;
4403 if(pipe == 1)
4404 temp |= (1 << 21);
4405 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4406 }
4407 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4408 {
4409 temp = 0x1000C4;
4410 if(pipe == 1)
4411 temp |= (1 << 21);
4412 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4413 }
a0c4da24
JB		 4414}
4415
eb1cbe48
DV		 4416static void i9xx_update_pll(struct drm_crtc *crtc,
4417 struct drm_display_mode *mode,
4418 struct drm_display_mode *adjusted_mode,
4419 intel_clock_t *clock, intel_clock_t *reduced_clock,
4420 int num_connectors)
4421{
4422 struct drm_device *dev = crtc->dev;
4423 struct drm_i915_private *dev_priv = dev->dev_private;
4424 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4425 int pipe = intel_crtc->pipe;
4426 u32 dpll;
4427 bool is_sdvo;
4428
2a8f64ca
VP		 4429 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4430
eb1cbe48
DV		 4431 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4432 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4433
4434 dpll = DPLL_VGA_MODE_DIS;
4435
4436 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4437 dpll |= DPLLB_MODE_LVDS;
4438 else
4439 dpll |= DPLLB_MODE_DAC_SERIAL;
4440 if (is_sdvo) {
4441 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4442 if (pixel_multiplier > 1) {
4443 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4444 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4445 }
4446 dpll |= DPLL_DVO_HIGH_SPEED;
4447 }
4448 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4449 dpll |= DPLL_DVO_HIGH_SPEED;
4450
4451 /* compute bitmask from p1 value */
4452 if (IS_PINEVIEW(dev))
4453 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4454 else {
4455 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4456 if (IS_G4X(dev) && reduced_clock)
4457 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4458 }
4459 switch (clock->p2) {
4460 case 5:
4461 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4462 break;
4463 case 7:
4464 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4465 break;
4466 case 10:
4467 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4468 break;
4469 case 14:
4470 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4471 break;
4472 }
4473 if (INTEL_INFO(dev)->gen >= 4)
4474 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4475
4476 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4477 dpll |= PLL_REF_INPUT_TVCLKINBC;
4478 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4479 /* XXX: just matching BIOS for now */
4480 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4481 dpll |= 3;
4482 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4483 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4484 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4485 else
4486 dpll |= PLL_REF_INPUT_DREFCLK;
4487
4488 dpll |= DPLL_VCO_ENABLE;
4489 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4490 POSTING_READ(DPLL(pipe));
4491 udelay(150);
4492
4493 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4494 * This is an exception to the general rule that mode_set doesn't turn
4495 * things on.
4496 */
4497 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4498 intel_update_lvds(crtc, clock, adjusted_mode);
4499
4500 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4501 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4502
4503 I915_WRITE(DPLL(pipe), dpll);
4504
4505 /* Wait for the clocks to stabilize. */
4506 POSTING_READ(DPLL(pipe));
4507 udelay(150);
4508
4509 if (INTEL_INFO(dev)->gen >= 4) {
4510 u32 temp = 0;
4511 if (is_sdvo) {
4512 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4513 if (temp > 1)
4514 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4515 else
4516 temp = 0;
4517 }
4518 I915_WRITE(DPLL_MD(pipe), temp);
4519 } else {
4520 /* The pixel multiplier can only be updated once the
4521 * DPLL is enabled and the clocks are stable.
4522 *
4523 * So write it again.
4524 */
4525 I915_WRITE(DPLL(pipe), dpll);
4526 }
4527}
4528
4529static void i8xx_update_pll(struct drm_crtc *crtc,
4530 struct drm_display_mode *adjusted_mode,
2a8f64ca 4531 intel_clock_t *clock, intel_clock_t *reduced_clock,
eb1cbe48
DV		 4532 int num_connectors)
4533{
4534 struct drm_device *dev = crtc->dev;
4535 struct drm_i915_private *dev_priv = dev->dev_private;
4536 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4537 int pipe = intel_crtc->pipe;
4538 u32 dpll;
4539
2a8f64ca
VP		 4540 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4541
eb1cbe48
DV		 4542 dpll = DPLL_VGA_MODE_DIS;
4543
4544 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4545 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4546 } else {
4547 if (clock->p1 == 2)
4548 dpll |= PLL_P1_DIVIDE_BY_TWO;
4549 else
4550 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4551 if (clock->p2 == 4)
4552 dpll |= PLL_P2_DIVIDE_BY_4;
4553 }
4554
4555 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4556 /* XXX: just matching BIOS for now */
4557 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4558 dpll |= 3;
4559 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4560 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4561 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4562 else
4563 dpll |= PLL_REF_INPUT_DREFCLK;
4564
4565 dpll |= DPLL_VCO_ENABLE;
4566 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4567 POSTING_READ(DPLL(pipe));
4568 udelay(150);
4569
eb1cbe48
DV		 4570 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4571 * This is an exception to the general rule that mode_set doesn't turn
4572 * things on.
4573 */
4574 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4575 intel_update_lvds(crtc, clock, adjusted_mode);
4576
5b5896e4
DV		 4577 I915_WRITE(DPLL(pipe), dpll);
4578
4579 /* Wait for the clocks to stabilize. */
4580 POSTING_READ(DPLL(pipe));
4581 udelay(150);
4582
eb1cbe48
DV		 4583 /* The pixel multiplier can only be updated once the
4584 * DPLL is enabled and the clocks are stable.
4585 *
4586 * So write it again.
4587 */
4588 I915_WRITE(DPLL(pipe), dpll);
4589}
4590
b0e77b9c
PZ		 4591static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4592 struct drm_display_mode *mode,
4593 struct drm_display_mode *adjusted_mode)
4594{
4595 struct drm_device *dev = intel_crtc->base.dev;
4596 struct drm_i915_private *dev_priv = dev->dev_private;
4597 enum pipe pipe = intel_crtc->pipe;
fe2b8f9d 4598 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
b0e77b9c
PZ		 4599 uint32_t vsyncshift;
4600
4601 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4602 /* the chip adds 2 halflines automatically */
4603 adjusted_mode->crtc_vtotal -= 1;
4604 adjusted_mode->crtc_vblank_end -= 1;
4605 vsyncshift = adjusted_mode->crtc_hsync_start
4606 - adjusted_mode->crtc_htotal / 2;
4607 } else {
4608 vsyncshift = 0;
4609 }
4610
4611 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4612 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4613
fe2b8f9d 4614 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4615 (adjusted_mode->crtc_hdisplay - 1) |
4616 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4617 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4618 (adjusted_mode->crtc_hblank_start - 1) |
4619 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4620 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4621 (adjusted_mode->crtc_hsync_start - 1) |
4622 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4623
fe2b8f9d 4624 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4625 (adjusted_mode->crtc_vdisplay - 1) |
4626 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4627 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4628 (adjusted_mode->crtc_vblank_start - 1) |
4629 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4630 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4631 (adjusted_mode->crtc_vsync_start - 1) |
4632 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4633
b5e508d4
PZ		 4634 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4635 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4636 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4637 * bits. */
4638 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4639 (pipe == PIPE_B || pipe == PIPE_C))
4640 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4641
b0e77b9c
PZ		 4642 /* pipesrc controls the size that is scaled from, which should
4643 * always be the user's requested size.
4644 */
4645 I915_WRITE(PIPESRC(pipe),
4646 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4647}
4648
f564048e
EA		 4649static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4650 struct drm_display_mode *mode,
4651 struct drm_display_mode *adjusted_mode,
4652 int x, int y,
94352cf9 4653 struct drm_framebuffer *fb)
79e53945
JB		 4654{
4655 struct drm_device *dev = crtc->dev;
4656 struct drm_i915_private *dev_priv = dev->dev_private;
4657 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4658 int pipe = intel_crtc->pipe;
80824003 4659 int plane = intel_crtc->plane;
c751ce4f 4660 int refclk, num_connectors = 0;
652c393a 4661 intel_clock_t clock, reduced_clock;
b0e77b9c 4662 u32 dspcntr, pipeconf;
eb1cbe48
DV		 4663 bool ok, has_reduced_clock = false, is_sdvo = false;
4664 bool is_lvds = false, is_tv = false, is_dp = false;
5eddb70b 4665 struct intel_encoder *encoder;
d4906093 4666 const intel_limit_t *limit;
5c3b82e2 4667 int ret;
79e53945 4668
6c2b7c12 4669 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4670 switch (encoder->type) {
79e53945
JB		 4671 case INTEL_OUTPUT_LVDS:
4672 is_lvds = true;
4673 break;
4674 case INTEL_OUTPUT_SDVO:
7d57382e 4675 case INTEL_OUTPUT_HDMI:
79e53945 4676 is_sdvo = true;
5eddb70b 4677 if (encoder->needs_tv_clock)
e2f0ba97 4678 is_tv = true;
79e53945 4679 break;
79e53945
JB		 4680 case INTEL_OUTPUT_TVOUT:
4681 is_tv = true;
4682 break;
a4fc5ed6
KP		 4683 case INTEL_OUTPUT_DISPLAYPORT:
4684 is_dp = true;
4685 break;
79e53945 4686 }
43565a06 4687
c751ce4f 4688 num_connectors++;
79e53945
JB		 4689 }
4690
c65d77d8 4691 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4692
d4906093
ML		 4693 /*
4694 * Returns a set of divisors for the desired target clock with the given
4695 * refclk, or FALSE. The returned values represent the clock equation:
4696 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4697 */
1b894b59 4698 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4699 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4700 &clock);
79e53945
JB		 4701 if (!ok) {
4702 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4703 return -EINVAL;
79e53945
JB		 4704 }
4705
cda4b7d3 4706 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4707 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4708
ddc9003c 4709 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4710 /*
4711 * Ensure we match the reduced clock's P to the target clock.
4712 * If the clocks don't match, we can't switch the display clock
4713 * by using the FP0/FP1. In such case we will disable the LVDS
4714 * downclock feature.
4715 */
ddc9003c 4716 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4717 dev_priv->lvds_downclock,
4718 refclk,
cec2f356 4719 &clock,
5eddb70b 4720 &reduced_clock);
7026d4ac
ZW		 4721 }
4722
c65d77d8
JB		 4723 if (is_sdvo && is_tv)
4724 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4725
eb1cbe48 4726 if (IS_GEN2(dev))
2a8f64ca
VP		 4727 i8xx_update_pll(crtc, adjusted_mode, &clock,
4728 has_reduced_clock ? &reduced_clock : NULL,
4729 num_connectors);
a0c4da24 4730 else if (IS_VALLEYVIEW(dev))
2a8f64ca
VP		 4731 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4732 has_reduced_clock ? &reduced_clock : NULL,
4733 num_connectors);
79e53945 4734 else
eb1cbe48
DV		 4735 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4736 has_reduced_clock ? &reduced_clock : NULL,
4737 num_connectors);
79e53945
JB		 4738
4739 /* setup pipeconf */
5eddb70b 4740 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4741
4742 /* Set up the display plane register */
4743 dspcntr = DISPPLANE_GAMMA_ENABLE;
4744
929c77fb
EA		 4745 if (pipe == 0)
4746 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4747 else
4748 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4749
a6c45cf0 4750 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4751 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4752 * core speed.
4753 *
4754 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4755 * pipe == 0 check?
4756 */
e70236a8
JB		 4757 if (mode->clock >
4758 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4759 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4760 else
5eddb70b 4761 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4762 }
4763
3b5c78a3
AJ		 4764 /* default to 8bpc */
4765 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4766 if (is_dp) {
0c96c65b 4767 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3b5c78a3
AJ		 4768 pipeconf |= PIPECONF_BPP_6 |
4769 PIPECONF_DITHER_EN |
4770 PIPECONF_DITHER_TYPE_SP;
4771 }
4772 }
4773
19c03924
GB		 4774 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4775 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4776 pipeconf |= PIPECONF_BPP_6 |
4777 PIPECONF_ENABLE |
4778 I965_PIPECONF_ACTIVE;
4779 }
4780 }
4781
28c97730 4782 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4783 drm_mode_debug_printmodeline(mode);
4784
a7516a05
JB		 4785 if (HAS_PIPE_CXSR(dev)) {
4786 if (intel_crtc->lowfreq_avail) {
28c97730 4787 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4788 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4789 } else {
28c97730 4790 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4791 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4792 }
4793 }
4794
617cf884 4795 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575 4796 if (!IS_GEN2(dev) &&
b0e77b9c 4797 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
734b4157 4798 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
b0e77b9c 4799 else
617cf884 4800 pipeconf |= PIPECONF_PROGRESSIVE;
734b4157 4801
b0e77b9c 4802 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4803
4804 /* pipesrc and dspsize control the size that is scaled from,
4805 * which should always be the user's requested size.
79e53945 4806 */
929c77fb
EA		 4807 I915_WRITE(DSPSIZE(plane),
4808 ((mode->vdisplay - 1) << 16) |
4809 (mode->hdisplay - 1));
4810 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4811
f564048e
EA		 4812 I915_WRITE(PIPECONF(pipe), pipeconf);
4813 POSTING_READ(PIPECONF(pipe));
929c77fb 4814 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4815
4816 intel_wait_for_vblank(dev, pipe);
4817
f564048e
EA		 4818 I915_WRITE(DSPCNTR(plane), dspcntr);
4819 POSTING_READ(DSPCNTR(plane));
4820
94352cf9 4821 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4822
4823 intel_update_watermarks(dev);
4824
f564048e
EA		 4825 return ret;
4826}
4827
9fb526db
KP		 4828/*
4829 * Initialize reference clocks when the driver loads
4830 */
4831void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4832{
4833 struct drm_i915_private *dev_priv = dev->dev_private;
4834 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4835 struct intel_encoder *encoder;
13d83a67
JB		 4836 u32 temp;
4837 bool has_lvds = false;
199e5d79
KP		 4838 bool has_cpu_edp = false;
4839 bool has_pch_edp = false;
4840 bool has_panel = false;
99eb6a01
KP		 4841 bool has_ck505 = false;
4842 bool can_ssc = false;
13d83a67
JB		 4843
4844 /* We need to take the global config into account */
199e5d79
KP		 4845 list_for_each_entry(encoder, &mode_config->encoder_list,
4846 base.head) {
4847 switch (encoder->type) {
4848 case INTEL_OUTPUT_LVDS:
4849 has_panel = true;
4850 has_lvds = true;
4851 break;
4852 case INTEL_OUTPUT_EDP:
4853 has_panel = true;
4854 if (intel_encoder_is_pch_edp(&encoder->base))
4855 has_pch_edp = true;
4856 else
4857 has_cpu_edp = true;
4858 break;
13d83a67
JB		 4859 }
4860 }
4861
99eb6a01
KP		 4862 if (HAS_PCH_IBX(dev)) {
4863 has_ck505 = dev_priv->display_clock_mode;
4864 can_ssc = has_ck505;
4865 } else {
4866 has_ck505 = false;
4867 can_ssc = true;
4868 }
4869
4870 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4871 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4872 has_ck505);
13d83a67
JB		 4873
4874 /* Ironlake: try to setup display ref clock before DPLL
4875 * enabling. This is only under driver's control after
4876 * PCH B stepping, previous chipset stepping should be
4877 * ignoring this setting.
4878 */
4879 temp = I915_READ(PCH_DREF_CONTROL);
4880 /* Always enable nonspread source */
4881 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4882
99eb6a01
KP		 4883 if (has_ck505)
4884 temp |= DREF_NONSPREAD_CK505_ENABLE;
4885 else
4886 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4887
199e5d79
KP		 4888 if (has_panel) {
4889 temp &= ~DREF_SSC_SOURCE_MASK;
4890 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4891
199e5d79 4892 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4893 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4894 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4895 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4896 } else
4897 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4898
4899 /* Get SSC going before enabling the outputs */
4900 I915_WRITE(PCH_DREF_CONTROL, temp);
4901 POSTING_READ(PCH_DREF_CONTROL);
4902 udelay(200);
4903
13d83a67
JB		 4904 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4905
4906 /* Enable CPU source on CPU attached eDP */
199e5d79 4907 if (has_cpu_edp) {
99eb6a01 4908 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4909 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4910 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4911 }
13d83a67
JB		 4912 else
4913 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4914 } else
4915 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4916
4917 I915_WRITE(PCH_DREF_CONTROL, temp);
4918 POSTING_READ(PCH_DREF_CONTROL);
4919 udelay(200);
4920 } else {
4921 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4922
4923 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4924
4925 /* Turn off CPU output */
4926 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4927
4928 I915_WRITE(PCH_DREF_CONTROL, temp);
4929 POSTING_READ(PCH_DREF_CONTROL);
4930 udelay(200);
4931
4932 /* Turn off the SSC source */
4933 temp &= ~DREF_SSC_SOURCE_MASK;
4934 temp |= DREF_SSC_SOURCE_DISABLE;
4935
4936 /* Turn off SSC1 */
4937 temp &= ~ DREF_SSC1_ENABLE;
4938
13d83a67
JB		 4939 I915_WRITE(PCH_DREF_CONTROL, temp);
4940 POSTING_READ(PCH_DREF_CONTROL);
4941 udelay(200);
4942 }
4943}
4944
d9d444cb
JB		 4945static int ironlake_get_refclk(struct drm_crtc *crtc)
4946{
4947 struct drm_device *dev = crtc->dev;
4948 struct drm_i915_private *dev_priv = dev->dev_private;
4949 struct intel_encoder *encoder;
d9d444cb
JB		 4950 struct intel_encoder *edp_encoder = NULL;
4951 int num_connectors = 0;
4952 bool is_lvds = false;
4953
6c2b7c12 4954 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 4955 switch (encoder->type) {
4956 case INTEL_OUTPUT_LVDS:
4957 is_lvds = true;
4958 break;
4959 case INTEL_OUTPUT_EDP:
4960 edp_encoder = encoder;
4961 break;
4962 }
4963 num_connectors++;
4964 }
4965
4966 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4967 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4968 dev_priv->lvds_ssc_freq);
4969 return dev_priv->lvds_ssc_freq * 1000;
4970 }
4971
4972 return 120000;
4973}
4974
c8203565
PZ		 4975static void ironlake_set_pipeconf(struct drm_crtc *crtc,
4976 struct drm_display_mode *adjusted_mode,
4977 bool dither)
4978{
4979 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4980 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4981 int pipe = intel_crtc->pipe;
4982 uint32_t val;
4983
4984 val = I915_READ(PIPECONF(pipe));
4985
4986 val &= ~PIPE_BPC_MASK;
4987 switch (intel_crtc->bpp) {
4988 case 18:
4989 val |= PIPE_6BPC;
4990 break;
4991 case 24:
4992 val |= PIPE_8BPC;
4993 break;
4994 case 30:
4995 val |= PIPE_10BPC;
4996 break;
4997 case 36:
4998 val |= PIPE_12BPC;
4999 break;
5000 default:
cc769b62
PZ		 5001 /* Case prevented by intel_choose_pipe_bpp_dither. */
5002 BUG();
c8203565
PZ		 5003 }
5004
5005 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5006 if (dither)
5007 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5008
5009 val &= ~PIPECONF_INTERLACE_MASK;
5010 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5011 val |= PIPECONF_INTERLACED_ILK;
5012 else
5013 val |= PIPECONF_PROGRESSIVE;
5014
5015 I915_WRITE(PIPECONF(pipe), val);
5016 POSTING_READ(PIPECONF(pipe));
5017}
5018
ee2b0b38
PZ		 5019static void haswell_set_pipeconf(struct drm_crtc *crtc,
5020 struct drm_display_mode *adjusted_mode,
5021 bool dither)
5022{
5023 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5024 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
702e7a56 5025 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
ee2b0b38
PZ		 5026 uint32_t val;
5027
702e7a56 5028 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5029
5030 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5031 if (dither)
5032 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5033
5034 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5035 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5036 val |= PIPECONF_INTERLACED_ILK;
5037 else
5038 val |= PIPECONF_PROGRESSIVE;
5039
702e7a56
PZ		 5040 I915_WRITE(PIPECONF(cpu_transcoder), val);
5041 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5042}
5043
6591c6e4
PZ		 5044static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5045 struct drm_display_mode *adjusted_mode,
5046 intel_clock_t *clock,
5047 bool *has_reduced_clock,
5048 intel_clock_t *reduced_clock)
5049{
5050 struct drm_device *dev = crtc->dev;
5051 struct drm_i915_private *dev_priv = dev->dev_private;
5052 struct intel_encoder *intel_encoder;
5053 int refclk;
5054 const intel_limit_t *limit;
5055 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5056
5057 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5058 switch (intel_encoder->type) {
5059 case INTEL_OUTPUT_LVDS:
5060 is_lvds = true;
5061 break;
5062 case INTEL_OUTPUT_SDVO:
5063 case INTEL_OUTPUT_HDMI:
5064 is_sdvo = true;
5065 if (intel_encoder->needs_tv_clock)
5066 is_tv = true;
5067 break;
5068 case INTEL_OUTPUT_TVOUT:
5069 is_tv = true;
5070 break;
5071 }
5072 }
5073
5074 refclk = ironlake_get_refclk(crtc);
5075
5076 /*
5077 * Returns a set of divisors for the desired target clock with the given
5078 * refclk, or FALSE. The returned values represent the clock equation:
5079 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5080 */
5081 limit = intel_limit(crtc, refclk);
5082 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5083 clock);
5084 if (!ret)
5085 return false;
5086
5087 if (is_lvds && dev_priv->lvds_downclock_avail) {
5088 /*
5089 * Ensure we match the reduced clock's P to the target clock.
5090 * If the clocks don't match, we can't switch the display clock
5091 * by using the FP0/FP1. In such case we will disable the LVDS
5092 * downclock feature.
5093 */
5094 *has_reduced_clock = limit->find_pll(limit, crtc,
5095 dev_priv->lvds_downclock,
5096 refclk,
5097 clock,
5098 reduced_clock);
5099 }
5100
5101 if (is_sdvo && is_tv)
5102 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5103
5104 return true;
5105}
5106
01a415fd
DV		 5107static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5108{
5109 struct drm_i915_private *dev_priv = dev->dev_private;
5110 uint32_t temp;
5111
5112 temp = I915_READ(SOUTH_CHICKEN1);
5113 if (temp & FDI_BC_BIFURCATION_SELECT)
5114 return;
5115
5116 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5117 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5118
5119 temp |= FDI_BC_BIFURCATION_SELECT;
5120 DRM_DEBUG_KMS("enabling fdi C rx\n");
5121 I915_WRITE(SOUTH_CHICKEN1, temp);
5122 POSTING_READ(SOUTH_CHICKEN1);
5123}
5124
5125static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5126{
5127 struct drm_device *dev = intel_crtc->base.dev;
5128 struct drm_i915_private *dev_priv = dev->dev_private;
5129 struct intel_crtc *pipe_B_crtc =
5130 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5131
5132 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5133 intel_crtc->pipe, intel_crtc->fdi_lanes);
5134 if (intel_crtc->fdi_lanes > 4) {
5135 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5136 intel_crtc->pipe, intel_crtc->fdi_lanes);
5137 /* Clamp lanes to avoid programming the hw with bogus values. */
5138 intel_crtc->fdi_lanes = 4;
5139
5140 return false;
5141 }
5142
5143 if (dev_priv->num_pipe == 2)
5144 return true;
5145
5146 switch (intel_crtc->pipe) {
5147 case PIPE_A:
5148 return true;
5149 case PIPE_B:
5150 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5151 intel_crtc->fdi_lanes > 2) {
5152 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5153 intel_crtc->pipe, intel_crtc->fdi_lanes);
5154 /* Clamp lanes to avoid programming the hw with bogus values. */
5155 intel_crtc->fdi_lanes = 2;
5156
5157 return false;
5158 }
5159
5160 if (intel_crtc->fdi_lanes > 2)
5161 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5162 else
5163 cpt_enable_fdi_bc_bifurcation(dev);
5164
5165 return true;
5166 case PIPE_C:
5167 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5168 if (intel_crtc->fdi_lanes > 2) {
5169 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5170 intel_crtc->pipe, intel_crtc->fdi_lanes);
5171 /* Clamp lanes to avoid programming the hw with bogus values. */
5172 intel_crtc->fdi_lanes = 2;
5173
5174 return false;
5175 }
5176 } else {
5177 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5178 return false;
5179 }
5180
5181 cpt_enable_fdi_bc_bifurcation(dev);
5182
5183 return true;
5184 default:
5185 BUG();
5186 }
5187}
5188
f48d8f23
PZ		 5189static void ironlake_set_m_n(struct drm_crtc *crtc,
5190 struct drm_display_mode *mode,
5191 struct drm_display_mode *adjusted_mode)
5192{
5193 struct drm_device *dev = crtc->dev;
5194 struct drm_i915_private *dev_priv = dev->dev_private;
5195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
afe2fcf5 5196 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
f48d8f23
PZ		 5197 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5198 struct fdi_m_n m_n = {0};
5199 int target_clock, pixel_multiplier, lane, link_bw;
5200 bool is_dp = false, is_cpu_edp = false;
5201
5202 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5203 switch (intel_encoder->type) {
5204 case INTEL_OUTPUT_DISPLAYPORT:
5205 is_dp = true;
5206 break;
5207 case INTEL_OUTPUT_EDP:
5208 is_dp = true;
5209 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5210 is_cpu_edp = true;
5211 edp_encoder = intel_encoder;
5212 break;
5213 }
5214 }
5215
5216 /* FDI link */
5217 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5218 lane = 0;
5219 /* CPU eDP doesn't require FDI link, so just set DP M/N
5220 according to current link config */
5221 if (is_cpu_edp) {
5222 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5223 } else {
5224 /* FDI is a binary signal running at ~2.7GHz, encoding
5225 * each output octet as 10 bits. The actual frequency
5226 * is stored as a divider into a 100MHz clock, and the
5227 * mode pixel clock is stored in units of 1KHz.
5228 * Hence the bw of each lane in terms of the mode signal
5229 * is:
5230 */
5231 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5232 }
5233
5234 /* [e]DP over FDI requires target mode clock instead of link clock. */
5235 if (edp_encoder)
5236 target_clock = intel_edp_target_clock(edp_encoder, mode);
5237 else if (is_dp)
5238 target_clock = mode->clock;
5239 else
5240 target_clock = adjusted_mode->clock;
5241
5242 if (!lane) {
5243 /*
5244 * Account for spread spectrum to avoid
5245 * oversubscribing the link. Max center spread
5246 * is 2.5%; use 5% for safety's sake.
5247 */
5248 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5249 lane = bps / (link_bw * 8) + 1;
5250 }
5251
5252 intel_crtc->fdi_lanes = lane;
5253
5254 if (pixel_multiplier > 1)
5255 link_bw *= pixel_multiplier;
5256 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5257 &m_n);
5258
afe2fcf5
PZ		 5259 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5260 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5261 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5262 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
f48d8f23
PZ		 5263}
5264
de13a2e3
PZ		 5265static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5266 struct drm_display_mode *adjusted_mode,
5267 intel_clock_t *clock, u32 fp)
79e53945 5268{
de13a2e3 5269 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5270 struct drm_device *dev = crtc->dev;
5271 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5272 struct intel_encoder *intel_encoder;
5273 uint32_t dpll;
5274 int factor, pixel_multiplier, num_connectors = 0;
5275 bool is_lvds = false, is_sdvo = false, is_tv = false;
5276 bool is_dp = false, is_cpu_edp = false;
79e53945 5277
de13a2e3
PZ		 5278 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5279 switch (intel_encoder->type) {
79e53945
JB		 5280 case INTEL_OUTPUT_LVDS:
5281 is_lvds = true;
5282 break;
5283 case INTEL_OUTPUT_SDVO:
7d57382e 5284 case INTEL_OUTPUT_HDMI:
79e53945 5285 is_sdvo = true;
de13a2e3 5286 if (intel_encoder->needs_tv_clock)
e2f0ba97 5287 is_tv = true;
79e53945 5288 break;
79e53945
JB		 5289 case INTEL_OUTPUT_TVOUT:
5290 is_tv = true;
5291 break;
a4fc5ed6
KP		 5292 case INTEL_OUTPUT_DISPLAYPORT:
5293 is_dp = true;
5294 break;
32f9d658 5295 case INTEL_OUTPUT_EDP:
e3aef172 5296 is_dp = true;
de13a2e3 5297 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5298 is_cpu_edp = true;
32f9d658 5299 break;
79e53945 5300 }
43565a06 5301
c751ce4f 5302 num_connectors++;
79e53945
JB		 5303 }
5304
c1858123 5305 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5306 factor = 21;
5307 if (is_lvds) {
5308 if ((intel_panel_use_ssc(dev_priv) &&
5309 dev_priv->lvds_ssc_freq == 100) ||
5310 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5311 factor = 25;
5312 } else if (is_sdvo && is_tv)
5313 factor = 20;
c1858123 5314
de13a2e3 5315 if (clock->m < factor * clock->n)
8febb297 5316 fp |= FP_CB_TUNE;
2c07245f 5317
5eddb70b 5318 dpll = 0;
2c07245f 5319
a07d6787
EA		 5320 if (is_lvds)
5321 dpll |= DPLLB_MODE_LVDS;
5322 else
5323 dpll |= DPLLB_MODE_DAC_SERIAL;
5324 if (is_sdvo) {
de13a2e3 5325 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
a07d6787
EA		 5326 if (pixel_multiplier > 1) {
5327 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5328 }
a07d6787
EA		 5329 dpll |= DPLL_DVO_HIGH_SPEED;
5330 }
e3aef172 5331 if (is_dp && !is_cpu_edp)
a07d6787 5332 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5333
a07d6787 5334 /* compute bitmask from p1 value */
de13a2e3 5335 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5336 /* also FPA1 */
de13a2e3 5337 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5338
de13a2e3 5339 switch (clock->p2) {
a07d6787
EA		 5340 case 5:
5341 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5342 break;
5343 case 7:
5344 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5345 break;
5346 case 10:
5347 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5348 break;
5349 case 14:
5350 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5351 break;
79e53945
JB		 5352 }
5353
43565a06
KH		 5354 if (is_sdvo && is_tv)
5355 dpll |= PLL_REF_INPUT_TVCLKINBC;
5356 else if (is_tv)
79e53945 5357 /* XXX: just matching BIOS for now */
43565a06 5358 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5359 dpll |= 3;
a7615030 5360 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5361 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5362 else
5363 dpll |= PLL_REF_INPUT_DREFCLK;
5364
de13a2e3
PZ		 5365 return dpll;
5366}
5367
5368static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5369 struct drm_display_mode *mode,
5370 struct drm_display_mode *adjusted_mode,
5371 int x, int y,
5372 struct drm_framebuffer *fb)
5373{
5374 struct drm_device *dev = crtc->dev;
5375 struct drm_i915_private *dev_priv = dev->dev_private;
5376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5377 int pipe = intel_crtc->pipe;
5378 int plane = intel_crtc->plane;
5379 int num_connectors = 0;
5380 intel_clock_t clock, reduced_clock;
5381 u32 dpll, fp = 0, fp2 = 0;
e2f12b07
PZ		 5382 bool ok, has_reduced_clock = false;
5383 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
de13a2e3
PZ		 5384 struct intel_encoder *encoder;
5385 u32 temp;
5386 int ret;
01a415fd 5387 bool dither, fdi_config_ok;
de13a2e3
PZ		 5388
5389 for_each_encoder_on_crtc(dev, crtc, encoder) {
5390 switch (encoder->type) {
5391 case INTEL_OUTPUT_LVDS:
5392 is_lvds = true;
5393 break;
de13a2e3
PZ		 5394 case INTEL_OUTPUT_DISPLAYPORT:
5395 is_dp = true;
5396 break;
5397 case INTEL_OUTPUT_EDP:
5398 is_dp = true;
e2f12b07 5399 if (!intel_encoder_is_pch_edp(&encoder->base))
de13a2e3
PZ		 5400 is_cpu_edp = true;
5401 break;
5402 }
5403
5404 num_connectors++;
5405 }
5406
5dc5298b
PZ		 5407 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5408 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5409
de13a2e3
PZ		 5410 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5411 &has_reduced_clock, &reduced_clock);
5412 if (!ok) {
5413 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5414 return -EINVAL;
5415 }
5416
5417 /* Ensure that the cursor is valid for the new mode before changing... */
5418 intel_crtc_update_cursor(crtc, true);
5419
5420 /* determine panel color depth */
c8241969
JN		 5421 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5422 adjusted_mode);
de13a2e3
PZ		 5423 if (is_lvds && dev_priv->lvds_dither)
5424 dither = true;
5425
5426 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5427 if (has_reduced_clock)
5428 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5429 reduced_clock.m2;
5430
5431 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5432
f7cb34d4 5433 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5434 drm_mode_debug_printmodeline(mode);
5435
5dc5298b
PZ		 5436 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5437 if (!is_cpu_edp) {
ee7b9f93 5438 struct intel_pch_pll *pll;
4b645f14 5439
ee7b9f93
JB		 5440 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5441 if (pll == NULL) {
5442 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5443 pipe);
4b645f14
JB		 5444 return -EINVAL;
5445 }
ee7b9f93
JB		 5446 } else
5447 intel_put_pch_pll(intel_crtc);
79e53945
JB		 5448
5449 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5450 * This is an exception to the general rule that mode_set doesn't turn
5451 * things on.
5452 */
5453 if (is_lvds) {
fae14981 5454 temp = I915_READ(PCH_LVDS);
5eddb70b 5455 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
7885d205
JB		 5456 if (HAS_PCH_CPT(dev)) {
5457 temp &= ~PORT_TRANS_SEL_MASK;
4b645f14 5458 temp |= PORT_TRANS_SEL_CPT(pipe);
7885d205
JB		 5459 } else {
5460 if (pipe == 1)
5461 temp |= LVDS_PIPEB_SELECT;
5462 else
5463 temp &= ~LVDS_PIPEB_SELECT;
5464 }
4b645f14 5465
a3e17eb8 5466 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5467 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5468 /* Set the B0-B3 data pairs corresponding to whether we're going to
5469 * set the DPLLs for dual-channel mode or not.
5470 */
5471 if (clock.p2 == 7)
5eddb70b 5472 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5473 else
5eddb70b 5474 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5475
5476 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5477 * appropriately here, but we need to look more thoroughly into how
5478 * panels behave in the two modes.
5479 */
284d5df5 5480 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
aa9b500d 5481 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 5482 temp |= LVDS_HSYNC_POLARITY;
aa9b500d 5483 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 5484 temp |= LVDS_VSYNC_POLARITY;
fae14981 5485 I915_WRITE(PCH_LVDS, temp);
79e53945 5486 }
434ed097 5487
e3aef172 5488 if (is_dp && !is_cpu_edp) {
a4fc5ed6 5489 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 5490 } else {
8db9d77b 5491 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 5492 I915_WRITE(TRANSDATA_M1(pipe), 0);
5493 I915_WRITE(TRANSDATA_N1(pipe), 0);
5494 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5495 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 5496 }
79e53945 5497
ee7b9f93
JB		 5498 if (intel_crtc->pch_pll) {
5499 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5500
32f9d658 5501 /* Wait for the clocks to stabilize. */
ee7b9f93 5502 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5503 udelay(150);
5504
8febb297
EA		 5505 /* The pixel multiplier can only be updated once the
5506 * DPLL is enabled and the clocks are stable.
5507 *
5508 * So write it again.
5509 */
ee7b9f93 5510 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5511 }
79e53945 5512
5eddb70b 5513 intel_crtc->lowfreq_avail = false;
ee7b9f93 5514 if (intel_crtc->pch_pll) {
4b645f14 5515 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5516 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5517 intel_crtc->lowfreq_avail = true;
4b645f14 5518 } else {
ee7b9f93 5519 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5520 }
5521 }
5522
b0e77b9c 5523 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
2c07245f 5524
01a415fd
DV		 5525 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5526 * ironlake_check_fdi_lanes. */
f48d8f23 5527 ironlake_set_m_n(crtc, mode, adjusted_mode);
2c07245f 5528
01a415fd
DV		 5529 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5530
e3aef172 5531 if (is_cpu_edp)
8febb297 5532 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f 5533
c8203565 5534 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5535
9d0498a2 5536 intel_wait_for_vblank(dev, pipe);
79e53945 5537
a1f9e77e
PZ		 5538 /* Set up the display plane register */
5539 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5540 POSTING_READ(DSPCNTR(plane));
79e53945 5541
94352cf9 5542 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5543
5544 intel_update_watermarks(dev);
5545
1f8eeabf
ED		 5546 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5547
01a415fd 5548 return fdi_config_ok ? ret : -EINVAL;
79e53945
JB		 5549}
5550
09b4ddf9
PZ		 5551static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5552 struct drm_display_mode *mode,
5553 struct drm_display_mode *adjusted_mode,
5554 int x, int y,
5555 struct drm_framebuffer *fb)
5556{
5557 struct drm_device *dev = crtc->dev;
5558 struct drm_i915_private *dev_priv = dev->dev_private;
5559 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5560 int pipe = intel_crtc->pipe;
5561 int plane = intel_crtc->plane;
5562 int num_connectors = 0;
5563 intel_clock_t clock, reduced_clock;
5dc5298b 5564 u32 dpll = 0, fp = 0, fp2 = 0;
09b4ddf9
PZ		 5565 bool ok, has_reduced_clock = false;
5566 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5567 struct intel_encoder *encoder;
5568 u32 temp;
5569 int ret;
5570 bool dither;
5571
5572 for_each_encoder_on_crtc(dev, crtc, encoder) {
5573 switch (encoder->type) {
5574 case INTEL_OUTPUT_LVDS:
5575 is_lvds = true;
5576 break;
5577 case INTEL_OUTPUT_DISPLAYPORT:
5578 is_dp = true;
5579 break;
5580 case INTEL_OUTPUT_EDP:
5581 is_dp = true;
5582 if (!intel_encoder_is_pch_edp(&encoder->base))
5583 is_cpu_edp = true;
5584 break;
5585 }
5586
5587 num_connectors++;
5588 }
5589
a5c961d1
PZ		 5590 if (is_cpu_edp)
5591 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5592 else
5593 intel_crtc->cpu_transcoder = pipe;
5594
5dc5298b
PZ		 5595 /* We are not sure yet this won't happen. */
5596 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5597 INTEL_PCH_TYPE(dev));
5598
5599 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5600 num_connectors, pipe_name(pipe));
5601
702e7a56 5602 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
1ce42920
PZ		 5603 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5604
5605 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5606
6441ab5f
PZ		 5607 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5608 return -EINVAL;
5609
5dc5298b
PZ		 5610 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5611 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5612 &has_reduced_clock,
5613 &reduced_clock);
5614 if (!ok) {
5615 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5616 return -EINVAL;
5617 }
09b4ddf9
PZ		 5618 }
5619
5620 /* Ensure that the cursor is valid for the new mode before changing... */
5621 intel_crtc_update_cursor(crtc, true);
5622
5623 /* determine panel color depth */
c8241969
JN		 5624 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5625 adjusted_mode);
09b4ddf9
PZ		 5626 if (is_lvds && dev_priv->lvds_dither)
5627 dither = true;
5628
09b4ddf9
PZ		 5629 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5630 drm_mode_debug_printmodeline(mode);
5631
5dc5298b
PZ		 5632 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5633 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5634 if (has_reduced_clock)
5635 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5636 reduced_clock.m2;
5637
5638 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5639 fp);
5640
5641 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5642 * own on pre-Haswell/LPT generation */
5643 if (!is_cpu_edp) {
5644 struct intel_pch_pll *pll;
5645
5646 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5647 if (pll == NULL) {
5648 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5649 pipe);
5650 return -EINVAL;
5651 }
5652 } else
5653 intel_put_pch_pll(intel_crtc);
09b4ddf9 5654
5dc5298b
PZ		 5655 /* The LVDS pin pair needs to be on before the DPLLs are
5656 * enabled. This is an exception to the general rule that
5657 * mode_set doesn't turn things on.
5658 */
5659 if (is_lvds) {
5660 temp = I915_READ(PCH_LVDS);
5661 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5662 if (HAS_PCH_CPT(dev)) {
5663 temp &= ~PORT_TRANS_SEL_MASK;
5664 temp |= PORT_TRANS_SEL_CPT(pipe);
5665 } else {
5666 if (pipe == 1)
5667 temp |= LVDS_PIPEB_SELECT;
5668 else
5669 temp &= ~LVDS_PIPEB_SELECT;
5670 }
09b4ddf9 5671
5dc5298b
PZ		 5672 /* set the corresponsding LVDS_BORDER bit */
5673 temp |= dev_priv->lvds_border_bits;
5674 /* Set the B0-B3 data pairs corresponding to whether
5675 * we're going to set the DPLLs for dual-channel mode or
5676 * not.
5677 */
5678 if (clock.p2 == 7)
5679 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
09b4ddf9 5680 else
5dc5298b
PZ		 5681 temp &= ~(LVDS_B0B3_POWER_UP |
5682 LVDS_CLKB_POWER_UP);
5683
5684 /* It would be nice to set 24 vs 18-bit mode
5685 * (LVDS_A3_POWER_UP) appropriately here, but we need to
5686 * look more thoroughly into how panels behave in the
5687 * two modes.
5688 */
5689 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5690 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5691 temp |= LVDS_HSYNC_POLARITY;
5692 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5693 temp |= LVDS_VSYNC_POLARITY;
5694 I915_WRITE(PCH_LVDS, temp);
09b4ddf9 5695 }
09b4ddf9
PZ		 5696 }
5697
5698 if (is_dp && !is_cpu_edp) {
5699 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5700 } else {
5dc5298b
PZ		 5701 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5702 /* For non-DP output, clear any trans DP clock recovery
5703 * setting.*/
5704 I915_WRITE(TRANSDATA_M1(pipe), 0);
5705 I915_WRITE(TRANSDATA_N1(pipe), 0);
5706 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5707 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5708 }
09b4ddf9
PZ		 5709 }
5710
5711 intel_crtc->lowfreq_avail = false;
5dc5298b
PZ		 5712 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5713 if (intel_crtc->pch_pll) {
5714 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5715
5716 /* Wait for the clocks to stabilize. */
5717 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5718 udelay(150);
5719
5720 /* The pixel multiplier can only be updated once the
5721 * DPLL is enabled and the clocks are stable.
5722 *
5723 * So write it again.
5724 */
5725 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5726 }
5727
5728 if (intel_crtc->pch_pll) {
5729 if (is_lvds && has_reduced_clock && i915_powersave) {
5730 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5731 intel_crtc->lowfreq_avail = true;
5732 } else {
5733 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5734 }
09b4ddf9
PZ		 5735 }
5736 }
5737
5738 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5739
1eb8dfec
PZ		 5740 if (!is_dp || is_cpu_edp)
5741 ironlake_set_m_n(crtc, mode, adjusted_mode);
09b4ddf9 5742
5dc5298b
PZ		 5743 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5744 if (is_cpu_edp)
5745 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
09b4ddf9 5746
ee2b0b38 5747 haswell_set_pipeconf(crtc, adjusted_mode, dither);
09b4ddf9 5748
09b4ddf9
PZ		 5749 /* Set up the display plane register */
5750 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5751 POSTING_READ(DSPCNTR(plane));
5752
5753 ret = intel_pipe_set_base(crtc, x, y, fb);
5754
5755 intel_update_watermarks(dev);
5756
5757 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5758
5759 return ret;
5760}
5761
f564048e
EA		 5762static int intel_crtc_mode_set(struct drm_crtc *crtc,
5763 struct drm_display_mode *mode,
5764 struct drm_display_mode *adjusted_mode,
5765 int x, int y,
94352cf9 5766 struct drm_framebuffer *fb)
f564048e
EA		 5767{
5768 struct drm_device *dev = crtc->dev;
5769 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5770 struct drm_encoder_helper_funcs *encoder_funcs;
5771 struct intel_encoder *encoder;
0b701d27
EA		 5772 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5773 int pipe = intel_crtc->pipe;
f564048e
EA		 5774 int ret;
5775
0b701d27 5776 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5777
f564048e 5778 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
94352cf9 5779 x, y, fb);
79e53945 5780 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5781
9256aa19
DV		 5782 if (ret != 0)
5783 return ret;
5784
5785 for_each_encoder_on_crtc(dev, crtc, encoder) {
5786 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5787 encoder->base.base.id,
5788 drm_get_encoder_name(&encoder->base),
5789 mode->base.id, mode->name);
5790 encoder_funcs = encoder->base.helper_private;
5791 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5792 }
5793
5794 return 0;
79e53945
JB		 5795}
5796
3a9627f4
WF		 5797static bool intel_eld_uptodate(struct drm_connector *connector,
5798 int reg_eldv, uint32_t bits_eldv,
5799 int reg_elda, uint32_t bits_elda,
5800 int reg_edid)
5801{
5802 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5803 uint8_t *eld = connector->eld;
5804 uint32_t i;
5805
5806 i = I915_READ(reg_eldv);
5807 i &= bits_eldv;
5808
5809 if (!eld[0])
5810 return !i;
5811
5812 if (!i)
5813 return false;
5814
5815 i = I915_READ(reg_elda);
5816 i &= ~bits_elda;
5817 I915_WRITE(reg_elda, i);
5818
5819 for (i = 0; i < eld[2]; i++)
5820 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5821 return false;
5822
5823 return true;
5824}
5825
e0dac65e
WF		 5826static void g4x_write_eld(struct drm_connector *connector,
5827 struct drm_crtc *crtc)
5828{
5829 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5830 uint8_t *eld = connector->eld;
5831 uint32_t eldv;
5832 uint32_t len;
5833 uint32_t i;
5834
5835 i = I915_READ(G4X_AUD_VID_DID);
5836
5837 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5838 eldv = G4X_ELDV_DEVCL_DEVBLC;
5839 else
5840 eldv = G4X_ELDV_DEVCTG;
5841
3a9627f4
WF		 5842 if (intel_eld_uptodate(connector,
5843 G4X_AUD_CNTL_ST, eldv,
5844 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5845 G4X_HDMIW_HDMIEDID))
5846 return;
5847
e0dac65e
WF		 5848 i = I915_READ(G4X_AUD_CNTL_ST);
5849 i &= ~(eldv | G4X_ELD_ADDR);
5850 len = (i >> 9) & 0x1f; /* ELD buffer size */
5851 I915_WRITE(G4X_AUD_CNTL_ST, i);
5852
5853 if (!eld[0])
5854 return;
5855
5856 len = min_t(uint8_t, eld[2], len);
5857 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5858 for (i = 0; i < len; i++)
5859 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5860
5861 i = I915_READ(G4X_AUD_CNTL_ST);
5862 i |= eldv;
5863 I915_WRITE(G4X_AUD_CNTL_ST, i);
5864}
5865
83358c85
WX		 5866static void haswell_write_eld(struct drm_connector *connector,
5867 struct drm_crtc *crtc)
5868{
5869 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5870 uint8_t *eld = connector->eld;
5871 struct drm_device *dev = crtc->dev;
5872 uint32_t eldv;
5873 uint32_t i;
5874 int len;
5875 int pipe = to_intel_crtc(crtc)->pipe;
5876 int tmp;
5877
5878 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5879 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5880 int aud_config = HSW_AUD_CFG(pipe);
5881 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5882
5883
5884 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5885
5886 /* Audio output enable */
5887 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5888 tmp = I915_READ(aud_cntrl_st2);
5889 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5890 I915_WRITE(aud_cntrl_st2, tmp);
5891
5892 /* Wait for 1 vertical blank */
5893 intel_wait_for_vblank(dev, pipe);
5894
5895 /* Set ELD valid state */
5896 tmp = I915_READ(aud_cntrl_st2);
5897 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5898 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5899 I915_WRITE(aud_cntrl_st2, tmp);
5900 tmp = I915_READ(aud_cntrl_st2);
5901 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5902
5903 /* Enable HDMI mode */
5904 tmp = I915_READ(aud_config);
5905 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5906 /* clear N_programing_enable and N_value_index */
5907 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5908 I915_WRITE(aud_config, tmp);
5909
5910 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5911
5912 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5913
5914 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5915 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5916 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5917 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5918 } else
5919 I915_WRITE(aud_config, 0);
5920
5921 if (intel_eld_uptodate(connector,
5922 aud_cntrl_st2, eldv,
5923 aud_cntl_st, IBX_ELD_ADDRESS,
5924 hdmiw_hdmiedid))
5925 return;
5926
5927 i = I915_READ(aud_cntrl_st2);
5928 i &= ~eldv;
5929 I915_WRITE(aud_cntrl_st2, i);
5930
5931 if (!eld[0])
5932 return;
5933
5934 i = I915_READ(aud_cntl_st);
5935 i &= ~IBX_ELD_ADDRESS;
5936 I915_WRITE(aud_cntl_st, i);
5937 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5938 DRM_DEBUG_DRIVER("port num:%d\n", i);
5939
5940 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5941 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5942 for (i = 0; i < len; i++)
5943 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5944
5945 i = I915_READ(aud_cntrl_st2);
5946 i |= eldv;
5947 I915_WRITE(aud_cntrl_st2, i);
5948
5949}
5950
e0dac65e
WF		 5951static void ironlake_write_eld(struct drm_connector *connector,
5952 struct drm_crtc *crtc)
5953{
5954 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5955 uint8_t *eld = connector->eld;
5956 uint32_t eldv;
5957 uint32_t i;
5958 int len;
5959 int hdmiw_hdmiedid;
b6daa025 5960 int aud_config;
e0dac65e
WF		 5961 int aud_cntl_st;
5962 int aud_cntrl_st2;
9b138a83 5963 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 5964
b3f33cbf 5965 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 5966 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5967 aud_config = IBX_AUD_CFG(pipe);
5968 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 5969 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 5970 } else {
9b138a83
WX		 5971 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5972 aud_config = CPT_AUD_CFG(pipe);
5973 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 5974 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 5975 }
5976
9b138a83 5977 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 5978
5979 i = I915_READ(aud_cntl_st);
9b138a83 5980 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 5981 if (!i) {
5982 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5983 /* operate blindly on all ports */
1202b4c6
WF		 5984 eldv = IBX_ELD_VALIDB;
5985 eldv |= IBX_ELD_VALIDB << 4;
5986 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 5987 } else {
5988 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 5989 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 5990 }
5991
3a9627f4
WF		 5992 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5993 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5994 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 5995 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5996 } else
5997 I915_WRITE(aud_config, 0);
e0dac65e 5998
3a9627f4
WF		 5999 if (intel_eld_uptodate(connector,
6000 aud_cntrl_st2, eldv,
6001 aud_cntl_st, IBX_ELD_ADDRESS,
6002 hdmiw_hdmiedid))
6003 return;
6004
e0dac65e
WF		 6005 i = I915_READ(aud_cntrl_st2);
6006 i &= ~eldv;
6007 I915_WRITE(aud_cntrl_st2, i);
6008
6009 if (!eld[0])
6010 return;
6011
e0dac65e 6012 i = I915_READ(aud_cntl_st);
1202b4c6 6013 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6014 I915_WRITE(aud_cntl_st, i);
6015
6016 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6017 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6018 for (i = 0; i < len; i++)
6019 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6020
6021 i = I915_READ(aud_cntrl_st2);
6022 i |= eldv;
6023 I915_WRITE(aud_cntrl_st2, i);
6024}
6025
6026void intel_write_eld(struct drm_encoder *encoder,
6027 struct drm_display_mode *mode)
6028{
6029 struct drm_crtc *crtc = encoder->crtc;
6030 struct drm_connector *connector;
6031 struct drm_device *dev = encoder->dev;
6032 struct drm_i915_private *dev_priv = dev->dev_private;
6033
6034 connector = drm_select_eld(encoder, mode);
6035 if (!connector)
6036 return;
6037
6038 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6039 connector->base.id,
6040 drm_get_connector_name(connector),
6041 connector->encoder->base.id,
6042 drm_get_encoder_name(connector->encoder));
6043
6044 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6045
6046 if (dev_priv->display.write_eld)
6047 dev_priv->display.write_eld(connector, crtc);
6048}
6049
79e53945
JB		 6050/** Loads the palette/gamma unit for the CRTC with the prepared values */
6051void intel_crtc_load_lut(struct drm_crtc *crtc)
6052{
6053 struct drm_device *dev = crtc->dev;
6054 struct drm_i915_private *dev_priv = dev->dev_private;
6055 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6056 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6057 int i;
6058
6059 /* The clocks have to be on to load the palette. */
aed3f09d 6060 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6061 return;
6062
f2b115e6 6063 /* use legacy palette for Ironlake */
bad720ff 6064 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6065 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6066
79e53945
JB		 6067 for (i = 0; i < 256; i++) {
6068 I915_WRITE(palreg + 4 * i,
6069 (intel_crtc->lut_r[i] << 16) |
6070 (intel_crtc->lut_g[i] << 8) |
6071 intel_crtc->lut_b[i]);
6072 }
6073}
6074
560b85bb
CW		 6075static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6076{
6077 struct drm_device *dev = crtc->dev;
6078 struct drm_i915_private *dev_priv = dev->dev_private;
6079 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6080 bool visible = base != 0;
6081 u32 cntl;
6082
6083 if (intel_crtc->cursor_visible == visible)
6084 return;
6085
9db4a9c7 6086 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6087 if (visible) {
6088 /* On these chipsets we can only modify the base whilst
6089 * the cursor is disabled.
6090 */
9db4a9c7 6091 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6092
6093 cntl &= ~(CURSOR_FORMAT_MASK);
6094 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6095 cntl |= CURSOR_ENABLE |
6096 CURSOR_GAMMA_ENABLE |
6097 CURSOR_FORMAT_ARGB;
6098 } else
6099 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6100 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6101
6102 intel_crtc->cursor_visible = visible;
6103}
6104
6105static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6106{
6107 struct drm_device *dev = crtc->dev;
6108 struct drm_i915_private *dev_priv = dev->dev_private;
6109 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6110 int pipe = intel_crtc->pipe;
6111 bool visible = base != 0;
6112
6113 if (intel_crtc->cursor_visible != visible) {
548f245b 6114 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6115 if (base) {
6116 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6117 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6118 cntl |= pipe << 28; /* Connect to correct pipe */
6119 } else {
6120 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6121 cntl |= CURSOR_MODE_DISABLE;
6122 }
9db4a9c7 6123 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6124
6125 intel_crtc->cursor_visible = visible;
6126 }
6127 /* and commit changes on next vblank */
9db4a9c7 6128 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6129}
6130
65a21cd6
JB		 6131static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6132{
6133 struct drm_device *dev = crtc->dev;
6134 struct drm_i915_private *dev_priv = dev->dev_private;
6135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6136 int pipe = intel_crtc->pipe;
6137 bool visible = base != 0;
6138
6139 if (intel_crtc->cursor_visible != visible) {
6140 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6141 if (base) {
6142 cntl &= ~CURSOR_MODE;
6143 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6144 } else {
6145 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6146 cntl |= CURSOR_MODE_DISABLE;
6147 }
6148 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6149
6150 intel_crtc->cursor_visible = visible;
6151 }
6152 /* and commit changes on next vblank */
6153 I915_WRITE(CURBASE_IVB(pipe), base);
6154}
6155
cda4b7d3 6156/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6157static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6158 bool on)
cda4b7d3
CW		 6159{
6160 struct drm_device *dev = crtc->dev;
6161 struct drm_i915_private *dev_priv = dev->dev_private;
6162 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6163 int pipe = intel_crtc->pipe;
6164 int x = intel_crtc->cursor_x;
6165 int y = intel_crtc->cursor_y;
560b85bb 6166 u32 base, pos;
cda4b7d3
CW		 6167 bool visible;
6168
6169 pos = 0;
6170
6b383a7f 6171 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6172 base = intel_crtc->cursor_addr;
6173 if (x > (int) crtc->fb->width)
6174 base = 0;
6175
6176 if (y > (int) crtc->fb->height)
6177 base = 0;
6178 } else
6179 base = 0;
6180
6181 if (x < 0) {
6182 if (x + intel_crtc->cursor_width < 0)
6183 base = 0;
6184
6185 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6186 x = -x;
6187 }
6188 pos |= x << CURSOR_X_SHIFT;
6189
6190 if (y < 0) {
6191 if (y + intel_crtc->cursor_height < 0)
6192 base = 0;
6193
6194 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6195 y = -y;
6196 }
6197 pos |= y << CURSOR_Y_SHIFT;
6198
6199 visible = base != 0;
560b85bb 6200 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6201 return;
6202
0cd83aa9 6203 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6204 I915_WRITE(CURPOS_IVB(pipe), pos);
6205 ivb_update_cursor(crtc, base);
6206 } else {
6207 I915_WRITE(CURPOS(pipe), pos);
6208 if (IS_845G(dev) || IS_I865G(dev))
6209 i845_update_cursor(crtc, base);
6210 else
6211 i9xx_update_cursor(crtc, base);
6212 }
cda4b7d3
CW		 6213}
6214
79e53945 6215static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6216 struct drm_file *file,
79e53945
JB		 6217 uint32_t handle,
6218 uint32_t width, uint32_t height)
6219{
6220 struct drm_device *dev = crtc->dev;
6221 struct drm_i915_private *dev_priv = dev->dev_private;
6222 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6223 struct drm_i915_gem_object *obj;
cda4b7d3 6224 uint32_t addr;
3f8bc370 6225 int ret;
79e53945 6226
79e53945
JB		 6227 /* if we want to turn off the cursor ignore width and height */
6228 if (!handle) {
28c97730 6229 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6230 addr = 0;
05394f39 6231 obj = NULL;
5004417d 6232 mutex_lock(&dev->struct_mutex);
3f8bc370 6233 goto finish;
79e53945
JB		 6234 }
6235
6236 /* Currently we only support 64x64 cursors */
6237 if (width != 64 || height != 64) {
6238 DRM_ERROR("we currently only support 64x64 cursors\n");
6239 return -EINVAL;
6240 }
6241
05394f39 6242 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6243 if (&obj->base == NULL)
79e53945
JB		 6244 return -ENOENT;
6245
05394f39 6246 if (obj->base.size < width * height * 4) {
79e53945 6247 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6248 ret = -ENOMEM;
6249 goto fail;
79e53945
JB		 6250 }
6251
71acb5eb 6252 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6253 mutex_lock(&dev->struct_mutex);
b295d1b6 6254 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 6255 if (obj->tiling_mode) {
6256 DRM_ERROR("cursor cannot be tiled\n");
6257 ret = -EINVAL;
6258 goto fail_locked;
6259 }
6260
2da3b9b9 6261 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 6262 if (ret) {
6263 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6264 goto fail_locked;
e7b526bb
CW		 6265 }
6266
d9e86c0e
CW		 6267 ret = i915_gem_object_put_fence(obj);
6268 if (ret) {
2da3b9b9 6269 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6270 goto fail_unpin;
6271 }
6272
05394f39 6273 addr = obj->gtt_offset;
71acb5eb 6274 } else {
6eeefaf3 6275 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6276 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6277 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6278 align);
71acb5eb
DA		 6279 if (ret) {
6280 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6281 goto fail_locked;
71acb5eb 6282 }
05394f39 6283 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6284 }
6285
a6c45cf0 6286 if (IS_GEN2(dev))
14b60391
JB		 6287 I915_WRITE(CURSIZE, (height << 12) | width);
6288
3f8bc370 6289 finish:
3f8bc370 6290 if (intel_crtc->cursor_bo) {
b295d1b6 6291 if (dev_priv->info->cursor_needs_physical) {
05394f39 6292 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6293 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6294 } else
6295 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6296 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6297 }
80824003 6298
7f9872e0 6299 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6300
6301 intel_crtc->cursor_addr = addr;
05394f39 6302 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6303 intel_crtc->cursor_width = width;
6304 intel_crtc->cursor_height = height;
6305
6b383a7f 6306 intel_crtc_update_cursor(crtc, true);
3f8bc370 6307
79e53945 6308 return 0;
e7b526bb 6309fail_unpin:
05394f39 6310 i915_gem_object_unpin(obj);
7f9872e0 6311fail_locked:
34b8686e 6312 mutex_unlock(&dev->struct_mutex);
bc9025bd 6313fail:
05394f39 6314 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6315 return ret;
79e53945
JB		 6316}
6317
6318static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6319{
79e53945 6320 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6321
cda4b7d3
CW		 6322 intel_crtc->cursor_x = x;
6323 intel_crtc->cursor_y = y;
652c393a 6324
6b383a7f 6325 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6326
6327 return 0;
6328}
6329
6330/** Sets the color ramps on behalf of RandR */
6331void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6332 u16 blue, int regno)
6333{
6334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6335
6336 intel_crtc->lut_r[regno] = red >> 8;
6337 intel_crtc->lut_g[regno] = green >> 8;
6338 intel_crtc->lut_b[regno] = blue >> 8;
6339}
6340
b8c00ac5
DA		 6341void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6342 u16 *blue, int regno)
6343{
6344 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6345
6346 *red = intel_crtc->lut_r[regno] << 8;
6347 *green = intel_crtc->lut_g[regno] << 8;
6348 *blue = intel_crtc->lut_b[regno] << 8;
6349}
6350
79e53945 6351static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6352 u16 *blue, uint32_t start, uint32_t size)
79e53945 6353{
7203425a 6354 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6355 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6356
7203425a 6357 for (i = start; i < end; i++) {
79e53945
JB		 6358 intel_crtc->lut_r[i] = red[i] >> 8;
6359 intel_crtc->lut_g[i] = green[i] >> 8;
6360 intel_crtc->lut_b[i] = blue[i] >> 8;
6361 }
6362
6363 intel_crtc_load_lut(crtc);
6364}
6365
6366/**
6367 * Get a pipe with a simple mode set on it for doing load-based monitor
6368 * detection.
6369 *
6370 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 6371 * its requirements. The pipe will be connected to no other encoders.
79e53945 6372 *
c751ce4f 6373 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 6374 * configured for it. In the future, it could choose to temporarily disable
6375 * some outputs to free up a pipe for its use.
6376 *
6377 * \return crtc, or NULL if no pipes are available.
6378 */
6379
6380/* VESA 640x480x72Hz mode to set on the pipe */
6381static struct drm_display_mode load_detect_mode = {
6382 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6383 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6384};
6385
d2dff872
CW		 6386static struct drm_framebuffer *
6387intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6388 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6389 struct drm_i915_gem_object *obj)
6390{
6391 struct intel_framebuffer *intel_fb;
6392 int ret;
6393
6394 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6395 if (!intel_fb) {
6396 drm_gem_object_unreference_unlocked(&obj->base);
6397 return ERR_PTR(-ENOMEM);
6398 }
6399
6400 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6401 if (ret) {
6402 drm_gem_object_unreference_unlocked(&obj->base);
6403 kfree(intel_fb);
6404 return ERR_PTR(ret);
6405 }
6406
6407 return &intel_fb->base;
6408}
6409
6410static u32
6411intel_framebuffer_pitch_for_width(int width, int bpp)
6412{
6413 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6414 return ALIGN(pitch, 64);
6415}
6416
6417static u32
6418intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6419{
6420 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6421 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6422}
6423
6424static struct drm_framebuffer *
6425intel_framebuffer_create_for_mode(struct drm_device *dev,
6426 struct drm_display_mode *mode,
6427 int depth, int bpp)
6428{
6429 struct drm_i915_gem_object *obj;
308e5bcb 6430 struct drm_mode_fb_cmd2 mode_cmd;
d2dff872
CW		 6431
6432 obj = i915_gem_alloc_object(dev,
6433 intel_framebuffer_size_for_mode(mode, bpp));
6434 if (obj == NULL)
6435 return ERR_PTR(-ENOMEM);
6436
6437 mode_cmd.width = mode->hdisplay;
6438 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6439 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6440 bpp);
5ca0c34a 6441 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6442
6443 return intel_framebuffer_create(dev, &mode_cmd, obj);
6444}
6445
6446static struct drm_framebuffer *
6447mode_fits_in_fbdev(struct drm_device *dev,
6448 struct drm_display_mode *mode)
6449{
6450 struct drm_i915_private *dev_priv = dev->dev_private;
6451 struct drm_i915_gem_object *obj;
6452 struct drm_framebuffer *fb;
6453
6454 if (dev_priv->fbdev == NULL)
6455 return NULL;
6456
6457 obj = dev_priv->fbdev->ifb.obj;
6458 if (obj == NULL)
6459 return NULL;
6460
6461 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6462 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6463 fb->bits_per_pixel))
d2dff872
CW		 6464 return NULL;
6465
01f2c773 6466 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6467 return NULL;
6468
6469 return fb;
6470}
6471
d2434ab7 6472bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6473 struct drm_display_mode *mode,
8261b191 6474 struct intel_load_detect_pipe *old)
79e53945
JB		 6475{
6476 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6477 struct intel_encoder *intel_encoder =
6478 intel_attached_encoder(connector);
79e53945 6479 struct drm_crtc *possible_crtc;
4ef69c7a 6480 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6481 struct drm_crtc *crtc = NULL;
6482 struct drm_device *dev = encoder->dev;
94352cf9 6483 struct drm_framebuffer *fb;
79e53945
JB		 6484 int i = -1;
6485
d2dff872
CW		 6486 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6487 connector->base.id, drm_get_connector_name(connector),
6488 encoder->base.id, drm_get_encoder_name(encoder));
6489
79e53945
JB		 6490 /*
6491 * Algorithm gets a little messy:
7a5e4805 6492 *
79e53945
JB		 6493 * - if the connector already has an assigned crtc, use it (but make
6494 * sure it's on first)
7a5e4805 6495 *
79e53945
JB		 6496 * - try to find the first unused crtc that can drive this connector,
6497 * and use that if we find one
79e53945
JB		 6498 */
6499
6500 /* See if we already have a CRTC for this connector */
6501 if (encoder->crtc) {
6502 crtc = encoder->crtc;
8261b191 6503
24218aac 6504 old->dpms_mode = connector->dpms;
8261b191
CW		 6505 old->load_detect_temp = false;
6506
6507 /* Make sure the crtc and connector are running */
24218aac
DV		 6508 if (connector->dpms != DRM_MODE_DPMS_ON)
6509 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6510
7173188d 6511 return true;
79e53945
JB		 6512 }
6513
6514 /* Find an unused one (if possible) */
6515 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6516 i++;
6517 if (!(encoder->possible_crtcs & (1 << i)))
6518 continue;
6519 if (!possible_crtc->enabled) {
6520 crtc = possible_crtc;
6521 break;
6522 }
79e53945
JB		 6523 }
6524
6525 /*
6526 * If we didn't find an unused CRTC, don't use any.
6527 */
6528 if (!crtc) {
7173188d
CW		 6529 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6530 return false;
79e53945
JB		 6531 }
6532
fc303101
DV		 6533 intel_encoder->new_crtc = to_intel_crtc(crtc);
6534 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6535
6536 intel_crtc = to_intel_crtc(crtc);
24218aac 6537 old->dpms_mode = connector->dpms;
8261b191 6538 old->load_detect_temp = true;
d2dff872 6539 old->release_fb = NULL;
79e53945 6540
6492711d
CW		 6541 if (!mode)
6542 mode = &load_detect_mode;
79e53945 6543
d2dff872
CW		 6544 /* We need a framebuffer large enough to accommodate all accesses
6545 * that the plane may generate whilst we perform load detection.
6546 * We can not rely on the fbcon either being present (we get called
6547 * during its initialisation to detect all boot displays, or it may
6548 * not even exist) or that it is large enough to satisfy the
6549 * requested mode.
6550 */
94352cf9
DV		 6551 fb = mode_fits_in_fbdev(dev, mode);
6552 if (fb == NULL) {
d2dff872 6553 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6554 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6555 old->release_fb = fb;
d2dff872
CW		 6556 } else
6557 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6558 if (IS_ERR(fb)) {
d2dff872 6559 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
24218aac 6560 goto fail;
79e53945 6561 }
79e53945 6562
94352cf9 6563 if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6564 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6565 if (old->release_fb)
6566 old->release_fb->funcs->destroy(old->release_fb);
24218aac 6567 goto fail;
79e53945 6568 }
7173188d 6569
79e53945 6570 /* let the connector get through one full cycle before testing */
9d0498a2 6571 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 6572
7173188d 6573 return true;
24218aac
DV		 6574fail:
6575 connector->encoder = NULL;
6576 encoder->crtc = NULL;
24218aac 6577 return false;
79e53945
JB		 6578}
6579
d2434ab7 6580void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6581 struct intel_load_detect_pipe *old)
79e53945 6582{
d2434ab7
DV		 6583 struct intel_encoder *intel_encoder =
6584 intel_attached_encoder(connector);
4ef69c7a 6585 struct drm_encoder *encoder = &intel_encoder->base;
79e53945 6586
d2dff872
CW		 6587 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6588 connector->base.id, drm_get_connector_name(connector),
6589 encoder->base.id, drm_get_encoder_name(encoder));
6590
8261b191 6591 if (old->load_detect_temp) {
fc303101
DV		 6592 struct drm_crtc *crtc = encoder->crtc;
6593
6594 to_intel_connector(connector)->new_encoder = NULL;
6595 intel_encoder->new_crtc = NULL;
6596 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872
CW		 6597
6598 if (old->release_fb)
6599 old->release_fb->funcs->destroy(old->release_fb);
6600
0622a53c 6601 return;
79e53945
JB		 6602 }
6603
c751ce4f 6604 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6605 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6606 connector->funcs->dpms(connector, old->dpms_mode);
79e53945
JB		 6607}
6608
6609/* Returns the clock of the currently programmed mode of the given pipe. */
6610static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6611{
6612 struct drm_i915_private *dev_priv = dev->dev_private;
6613 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6614 int pipe = intel_crtc->pipe;
548f245b 6615 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6616 u32 fp;
6617 intel_clock_t clock;
6618
6619 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6620 fp = I915_READ(FP0(pipe));
79e53945 6621 else
39adb7a5 6622 fp = I915_READ(FP1(pipe));
79e53945
JB		 6623
6624 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6625 if (IS_PINEVIEW(dev)) {
6626 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6627 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6628 } else {
6629 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6630 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6631 }
6632
a6c45cf0 6633 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6634 if (IS_PINEVIEW(dev))
6635 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6636 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6637 else
6638 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6639 DPLL_FPA01_P1_POST_DIV_SHIFT);
6640
6641 switch (dpll & DPLL_MODE_MASK) {
6642 case DPLLB_MODE_DAC_SERIAL:
6643 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6644 5 : 10;
6645 break;
6646 case DPLLB_MODE_LVDS:
6647 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6648 7 : 14;
6649 break;
6650 default:
28c97730 6651 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6652 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6653 return 0;
6654 }
6655
6656 /* XXX: Handle the 100Mhz refclk */
2177832f 6657 intel_clock(dev, 96000, &clock);
79e53945
JB		 6658 } else {
6659 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6660
6661 if (is_lvds) {
6662 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6663 DPLL_FPA01_P1_POST_DIV_SHIFT);
6664 clock.p2 = 14;
6665
6666 if ((dpll & PLL_REF_INPUT_MASK) ==
6667 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6668 /* XXX: might not be 66MHz */
2177832f 6669 intel_clock(dev, 66000, &clock);
79e53945 6670 } else
2177832f 6671 intel_clock(dev, 48000, &clock);
79e53945
JB		 6672 } else {
6673 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6674 clock.p1 = 2;
6675 else {
6676 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6677 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6678 }
6679 if (dpll & PLL_P2_DIVIDE_BY_4)
6680 clock.p2 = 4;
6681 else
6682 clock.p2 = 2;
6683
2177832f 6684 intel_clock(dev, 48000, &clock);
79e53945
JB		 6685 }
6686 }
6687
6688 /* XXX: It would be nice to validate the clocks, but we can't reuse
6689 * i830PllIsValid() because it relies on the xf86_config connector
6690 * configuration being accurate, which it isn't necessarily.
6691 */
6692
6693 return clock.dot;
6694}
6695
6696/** Returns the currently programmed mode of the given pipe. */
6697struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6698 struct drm_crtc *crtc)
6699{
548f245b 6700 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6701 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fe2b8f9d 6702 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
79e53945 6703 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6704 int htot = I915_READ(HTOTAL(cpu_transcoder));
6705 int hsync = I915_READ(HSYNC(cpu_transcoder));
6706 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6707 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6708
6709 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6710 if (!mode)
6711 return NULL;
6712
6713 mode->clock = intel_crtc_clock_get(dev, crtc);
6714 mode->hdisplay = (htot & 0xffff) + 1;
6715 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6716 mode->hsync_start = (hsync & 0xffff) + 1;
6717 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6718 mode->vdisplay = (vtot & 0xffff) + 1;
6719 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6720 mode->vsync_start = (vsync & 0xffff) + 1;
6721 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6722
6723 drm_mode_set_name(mode);
79e53945
JB		 6724
6725 return mode;
6726}
6727
3dec0095 6728static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6729{
6730 struct drm_device *dev = crtc->dev;
6731 drm_i915_private_t *dev_priv = dev->dev_private;
6732 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6733 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6734 int dpll_reg = DPLL(pipe);
6735 int dpll;
652c393a 6736
bad720ff 6737 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6738 return;
6739
6740 if (!dev_priv->lvds_downclock_avail)
6741 return;
6742
dbdc6479 6743 dpll = I915_READ(dpll_reg);
652c393a 6744 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6745 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6746
8ac5a6d5 6747 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6748
6749 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6750 I915_WRITE(dpll_reg, dpll);
9d0498a2 6751 intel_wait_for_vblank(dev, pipe);
dbdc6479 6752
652c393a
JB		 6753 dpll = I915_READ(dpll_reg);
6754 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6755 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6756 }
652c393a
JB		 6757}
6758
6759static void intel_decrease_pllclock(struct drm_crtc *crtc)
6760{
6761 struct drm_device *dev = crtc->dev;
6762 drm_i915_private_t *dev_priv = dev->dev_private;
6763 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6764
bad720ff 6765 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6766 return;
6767
6768 if (!dev_priv->lvds_downclock_avail)
6769 return;
6770
6771 /*
6772 * Since this is called by a timer, we should never get here in
6773 * the manual case.
6774 */
6775 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6776 int pipe = intel_crtc->pipe;
6777 int dpll_reg = DPLL(pipe);
6778 int dpll;
f6e5b160 6779
44d98a61 6780 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6781
8ac5a6d5 6782 assert_panel_unlocked(dev_priv, pipe);
652c393a 6783
dc257cf1 6784 dpll = I915_READ(dpll_reg);
652c393a
JB		 6785 dpll |= DISPLAY_RATE_SELECT_FPA1;
6786 I915_WRITE(dpll_reg, dpll);
9d0498a2 6787 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6788 dpll = I915_READ(dpll_reg);
6789 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6790 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6791 }
6792
6793}
6794
f047e395
CW		 6795void intel_mark_busy(struct drm_device *dev)
6796{
f047e395
CW		 6797 i915_update_gfx_val(dev->dev_private);
6798}
6799
6800void intel_mark_idle(struct drm_device *dev)
652c393a 6801{
f047e395
CW		 6802}
6803
6804void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6805{
6806 struct drm_device *dev = obj->base.dev;
652c393a 6807 struct drm_crtc *crtc;
652c393a
JB		 6808
6809 if (!i915_powersave)
6810 return;
6811
652c393a 6812 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6813 if (!crtc->fb)
6814 continue;
6815
f047e395
CW		 6816 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6817 intel_increase_pllclock(crtc);
652c393a 6818 }
652c393a
JB		 6819}
6820
f047e395 6821void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
652c393a 6822{
f047e395
CW		 6823 struct drm_device *dev = obj->base.dev;
6824 struct drm_crtc *crtc;
652c393a 6825
f047e395 6826 if (!i915_powersave)
acb87dfb
CW		 6827 return;
6828
652c393a
JB		 6829 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6830 if (!crtc->fb)
6831 continue;
6832
f047e395
CW		 6833 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6834 intel_decrease_pllclock(crtc);
652c393a
JB		 6835 }
6836}
6837
79e53945
JB		 6838static void intel_crtc_destroy(struct drm_crtc *crtc)
6839{
6840 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6841 struct drm_device *dev = crtc->dev;
6842 struct intel_unpin_work *work;
6843 unsigned long flags;
6844
6845 spin_lock_irqsave(&dev->event_lock, flags);
6846 work = intel_crtc->unpin_work;
6847 intel_crtc->unpin_work = NULL;
6848 spin_unlock_irqrestore(&dev->event_lock, flags);
6849
6850 if (work) {
6851 cancel_work_sync(&work->work);
6852 kfree(work);
6853 }
79e53945
JB		 6854
6855 drm_crtc_cleanup(crtc);
67e77c5a 6856
79e53945
JB		 6857 kfree(intel_crtc);
6858}
6859
6b95a207
KH		 6860static void intel_unpin_work_fn(struct work_struct *__work)
6861{
6862 struct intel_unpin_work *work =
6863 container_of(__work, struct intel_unpin_work, work);
6864
6865 mutex_lock(&work->dev->struct_mutex);
1690e1eb 6866 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6867 drm_gem_object_unreference(&work->pending_flip_obj->base);
6868 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6869
7782de3b 6870 intel_update_fbc(work->dev);
6b95a207
KH		 6871 mutex_unlock(&work->dev->struct_mutex);
6872 kfree(work);
6873}
6874
1afe3e9d 6875static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6876 struct drm_crtc *crtc)
6b95a207
KH		 6877{
6878 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6879 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6880 struct intel_unpin_work *work;
05394f39 6881 struct drm_i915_gem_object *obj;
6b95a207 6882 struct drm_pending_vblank_event *e;
95cb1b02 6883 struct timeval tvbl;
6b95a207
KH		 6884 unsigned long flags;
6885
6886 /* Ignore early vblank irqs */
6887 if (intel_crtc == NULL)
6888 return;
6889
6890 spin_lock_irqsave(&dev->event_lock, flags);
6891 work = intel_crtc->unpin_work;
6892 if (work == NULL || !work->pending) {
6893 spin_unlock_irqrestore(&dev->event_lock, flags);
6894 return;
6895 }
6896
6897 intel_crtc->unpin_work = NULL;
6b95a207
KH		 6898
6899 if (work->event) {
6900 e = work->event;
49b14a5c 6901 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df 6902
49b14a5c
MK		 6903 e->event.tv_sec = tvbl.tv_sec;
6904 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 6905
6b95a207
KH		 6906 list_add_tail(&e->base.link,
6907 &e->base.file_priv->event_list);
6908 wake_up_interruptible(&e->base.file_priv->event_wait);
6909 }
6910
0af7e4df
MK		 6911 drm_vblank_put(dev, intel_crtc->pipe);
6912
6b95a207
KH		 6913 spin_unlock_irqrestore(&dev->event_lock, flags);
6914
05394f39 6915 obj = work->old_fb_obj;
d9e86c0e 6916
e59f2bac 6917 atomic_clear_mask(1 << intel_crtc->plane,
05394f39 6918 &obj->pending_flip.counter);
d9e86c0e 6919
5bb61643 6920 wake_up(&dev_priv->pending_flip_queue);
6b95a207 6921 schedule_work(&work->work);
e5510fac
JB		 6922
6923 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6924}
6925
1afe3e9d
JB		 6926void intel_finish_page_flip(struct drm_device *dev, int pipe)
6927{
6928 drm_i915_private_t *dev_priv = dev->dev_private;
6929 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6930
49b14a5c 6931 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6932}
6933
6934void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6935{
6936 drm_i915_private_t *dev_priv = dev->dev_private;
6937 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6938
49b14a5c 6939 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6940}
6941
6b95a207
KH		 6942void intel_prepare_page_flip(struct drm_device *dev, int plane)
6943{
6944 drm_i915_private_t *dev_priv = dev->dev_private;
6945 struct intel_crtc *intel_crtc =
6946 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6947 unsigned long flags;
6948
6949 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 6950 if (intel_crtc->unpin_work) {
4e5359cd
SF		 6951 if ((++intel_crtc->unpin_work->pending) > 1)
6952 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 6953 } else {
6954 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6955 }
6b95a207
KH		 6956 spin_unlock_irqrestore(&dev->event_lock, flags);
6957}
6958
8c9f3aaf
JB		 6959static int intel_gen2_queue_flip(struct drm_device *dev,
6960 struct drm_crtc *crtc,
6961 struct drm_framebuffer *fb,
6962 struct drm_i915_gem_object *obj)
6963{
6964 struct drm_i915_private *dev_priv = dev->dev_private;
6965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6966 u32 flip_mask;
6d90c952 6967 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6968 int ret;
6969
6d90c952 6970 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6971 if (ret)
83d4092b 6972 goto err;
8c9f3aaf 6973
6d90c952 6974 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6975 if (ret)
83d4092b 6976 goto err_unpin;
8c9f3aaf
JB		 6977
6978 /* Can't queue multiple flips, so wait for the previous
6979 * one to finish before executing the next.
6980 */
6981 if (intel_crtc->plane)
6982 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6983 else
6984 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6985 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6986 intel_ring_emit(ring, MI_NOOP);
6987 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6988 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6989 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6990 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 6991 intel_ring_emit(ring, 0); /* aux display base address, unused */
6992 intel_ring_advance(ring);
83d4092b
CW		 6993 return 0;
6994
6995err_unpin:
6996 intel_unpin_fb_obj(obj);
6997err:
8c9f3aaf
JB		 6998 return ret;
6999}
7000
7001static int intel_gen3_queue_flip(struct drm_device *dev,
7002 struct drm_crtc *crtc,
7003 struct drm_framebuffer *fb,
7004 struct drm_i915_gem_object *obj)
7005{
7006 struct drm_i915_private *dev_priv = dev->dev_private;
7007 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7008 u32 flip_mask;
6d90c952 7009 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7010 int ret;
7011
6d90c952 7012 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7013 if (ret)
83d4092b 7014 goto err;
8c9f3aaf 7015
6d90c952 7016 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7017 if (ret)
83d4092b 7018 goto err_unpin;
8c9f3aaf
JB		 7019
7020 if (intel_crtc->plane)
7021 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7022 else
7023 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7024 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7025 intel_ring_emit(ring, MI_NOOP);
7026 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7027 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7028 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7029 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7030 intel_ring_emit(ring, MI_NOOP);
7031
7032 intel_ring_advance(ring);
83d4092b
CW		 7033 return 0;
7034
7035err_unpin:
7036 intel_unpin_fb_obj(obj);
7037err:
8c9f3aaf
JB		 7038 return ret;
7039}
7040
7041static int intel_gen4_queue_flip(struct drm_device *dev,
7042 struct drm_crtc *crtc,
7043 struct drm_framebuffer *fb,
7044 struct drm_i915_gem_object *obj)
7045{
7046 struct drm_i915_private *dev_priv = dev->dev_private;
7047 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7048 uint32_t pf, pipesrc;
6d90c952 7049 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7050 int ret;
7051
6d90c952 7052 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7053 if (ret)
83d4092b 7054 goto err;
8c9f3aaf 7055
6d90c952 7056 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7057 if (ret)
83d4092b 7058 goto err_unpin;
8c9f3aaf
JB		 7059
7060 /* i965+ uses the linear or tiled offsets from the
7061 * Display Registers (which do not change across a page-flip)
7062 * so we need only reprogram the base address.
7063 */
6d90c952
DV		 7064 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7065 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7066 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7067 intel_ring_emit(ring,
7068 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7069 obj->tiling_mode);
8c9f3aaf
JB		 7070
7071 /* XXX Enabling the panel-fitter across page-flip is so far
7072 * untested on non-native modes, so ignore it for now.
7073 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7074 */
7075 pf = 0;
7076 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 7077 intel_ring_emit(ring, pf | pipesrc);
7078 intel_ring_advance(ring);
83d4092b
CW		 7079 return 0;
7080
7081err_unpin:
7082 intel_unpin_fb_obj(obj);
7083err:
8c9f3aaf
JB		 7084 return ret;
7085}
7086
7087static int intel_gen6_queue_flip(struct drm_device *dev,
7088 struct drm_crtc *crtc,
7089 struct drm_framebuffer *fb,
7090 struct drm_i915_gem_object *obj)
7091{
7092 struct drm_i915_private *dev_priv = dev->dev_private;
7093 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7094 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7095 uint32_t pf, pipesrc;
7096 int ret;
7097
6d90c952 7098 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7099 if (ret)
83d4092b 7100 goto err;
8c9f3aaf 7101
6d90c952 7102 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7103 if (ret)
83d4092b 7104 goto err_unpin;
8c9f3aaf 7105
6d90c952
DV		 7106 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7107 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7108 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7109 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7110
dc257cf1
DV		 7111 /* Contrary to the suggestions in the documentation,
7112 * "Enable Panel Fitter" does not seem to be required when page
7113 * flipping with a non-native mode, and worse causes a normal
7114 * modeset to fail.
7115 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7116 */
7117 pf = 0;
8c9f3aaf 7118 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 7119 intel_ring_emit(ring, pf | pipesrc);
7120 intel_ring_advance(ring);
83d4092b
CW		 7121 return 0;
7122
7123err_unpin:
7124 intel_unpin_fb_obj(obj);
7125err:
8c9f3aaf
JB		 7126 return ret;
7127}
7128
7c9017e5
JB		 7129/*
7130 * On gen7 we currently use the blit ring because (in early silicon at least)
7131 * the render ring doesn't give us interrpts for page flip completion, which
7132 * means clients will hang after the first flip is queued. Fortunately the
7133 * blit ring generates interrupts properly, so use it instead.
7134 */
7135static int intel_gen7_queue_flip(struct drm_device *dev,
7136 struct drm_crtc *crtc,
7137 struct drm_framebuffer *fb,
7138 struct drm_i915_gem_object *obj)
7139{
7140 struct drm_i915_private *dev_priv = dev->dev_private;
7141 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7142 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7143 uint32_t plane_bit = 0;
7c9017e5
JB		 7144 int ret;
7145
7146 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7147 if (ret)
83d4092b 7148 goto err;
7c9017e5 7149
cb05d8de
DV		 7150 switch(intel_crtc->plane) {
7151 case PLANE_A:
7152 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7153 break;
7154 case PLANE_B:
7155 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7156 break;
7157 case PLANE_C:
7158 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7159 break;
7160 default:
7161 WARN_ONCE(1, "unknown plane in flip command\n");
7162 ret = -ENODEV;
ab3951eb 7163 goto err_unpin;
cb05d8de
DV		 7164 }
7165
7c9017e5
JB		 7166 ret = intel_ring_begin(ring, 4);
7167 if (ret)
83d4092b 7168 goto err_unpin;
7c9017e5 7169
cb05d8de 7170 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7171 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7172 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5
JB		 7173 intel_ring_emit(ring, (MI_NOOP));
7174 intel_ring_advance(ring);
83d4092b
CW		 7175 return 0;
7176
7177err_unpin:
7178 intel_unpin_fb_obj(obj);
7179err:
7c9017e5
JB		 7180 return ret;
7181}
7182
8c9f3aaf
JB		 7183static int intel_default_queue_flip(struct drm_device *dev,
7184 struct drm_crtc *crtc,
7185 struct drm_framebuffer *fb,
7186 struct drm_i915_gem_object *obj)
7187{
7188 return -ENODEV;
7189}
7190
6b95a207
KH		 7191static int intel_crtc_page_flip(struct drm_crtc *crtc,
7192 struct drm_framebuffer *fb,
7193 struct drm_pending_vblank_event *event)
7194{
7195 struct drm_device *dev = crtc->dev;
7196 struct drm_i915_private *dev_priv = dev->dev_private;
7197 struct intel_framebuffer *intel_fb;
05394f39 7198 struct drm_i915_gem_object *obj;
6b95a207
KH		 7199 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7200 struct intel_unpin_work *work;
8c9f3aaf 7201 unsigned long flags;
52e68630 7202 int ret;
6b95a207 7203
e6a595d2
VS		 7204 /* Can't change pixel format via MI display flips. */
7205 if (fb->pixel_format != crtc->fb->pixel_format)
7206 return -EINVAL;
7207
7208 /*
7209 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7210 * Note that pitch changes could also affect these register.
7211 */
7212 if (INTEL_INFO(dev)->gen > 3 &&
7213 (fb->offsets[0] != crtc->fb->offsets[0] ||
7214 fb->pitches[0] != crtc->fb->pitches[0]))
7215 return -EINVAL;
7216
6b95a207
KH		 7217 work = kzalloc(sizeof *work, GFP_KERNEL);
7218 if (work == NULL)
7219 return -ENOMEM;
7220
6b95a207
KH		 7221 work->event = event;
7222 work->dev = crtc->dev;
7223 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 7224 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 7225 INIT_WORK(&work->work, intel_unpin_work_fn);
7226
7317c75e
JB		 7227 ret = drm_vblank_get(dev, intel_crtc->pipe);
7228 if (ret)
7229 goto free_work;
7230
6b95a207
KH		 7231 /* We borrow the event spin lock for protecting unpin_work */
7232 spin_lock_irqsave(&dev->event_lock, flags);
7233 if (intel_crtc->unpin_work) {
7234 spin_unlock_irqrestore(&dev->event_lock, flags);
7235 kfree(work);
7317c75e 7236 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7237
7238 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7239 return -EBUSY;
7240 }
7241 intel_crtc->unpin_work = work;
7242 spin_unlock_irqrestore(&dev->event_lock, flags);
7243
7244 intel_fb = to_intel_framebuffer(fb);
7245 obj = intel_fb->obj;
7246
79158103
CW		 7247 ret = i915_mutex_lock_interruptible(dev);
7248 if (ret)
7249 goto cleanup;
6b95a207 7250
75dfca80 7251 /* Reference the objects for the scheduled work. */
05394f39
CW		 7252 drm_gem_object_reference(&work->old_fb_obj->base);
7253 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7254
7255 crtc->fb = fb;
96b099fd 7256
e1f99ce6 7257 work->pending_flip_obj = obj;
e1f99ce6 7258
4e5359cd
SF		 7259 work->enable_stall_check = true;
7260
e1f99ce6
CW		 7261 /* Block clients from rendering to the new back buffer until
7262 * the flip occurs and the object is no longer visible.
7263 */
05394f39 7264 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 7265
8c9f3aaf
JB		 7266 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7267 if (ret)
7268 goto cleanup_pending;
6b95a207 7269
7782de3b 7270 intel_disable_fbc(dev);
f047e395 7271 intel_mark_fb_busy(obj);
6b95a207
KH		 7272 mutex_unlock(&dev->struct_mutex);
7273
e5510fac
JB		 7274 trace_i915_flip_request(intel_crtc->plane, obj);
7275
6b95a207 7276 return 0;
96b099fd 7277
8c9f3aaf
JB		 7278cleanup_pending:
7279 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
05394f39
CW		 7280 drm_gem_object_unreference(&work->old_fb_obj->base);
7281 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7282 mutex_unlock(&dev->struct_mutex);
7283
79158103 7284cleanup:
96b099fd
CW		 7285 spin_lock_irqsave(&dev->event_lock, flags);
7286 intel_crtc->unpin_work = NULL;
7287 spin_unlock_irqrestore(&dev->event_lock, flags);
7288
7317c75e
JB		 7289 drm_vblank_put(dev, intel_crtc->pipe);
7290free_work:
96b099fd
CW		 7291 kfree(work);
7292
7293 return ret;
6b95a207
KH		 7294}
7295
f6e5b160 7296static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7297 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7298 .load_lut = intel_crtc_load_lut,
976f8a20 7299 .disable = intel_crtc_noop,
f6e5b160
CW		 7300};
7301
6ed0f796 7302bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7303{
6ed0f796
DV		 7304 struct intel_encoder *other_encoder;
7305 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7306
6ed0f796
DV		 7307 if (WARN_ON(!crtc))
7308 return false;
7309
7310 list_for_each_entry(other_encoder,
7311 &crtc->dev->mode_config.encoder_list,
7312 base.head) {
7313
7314 if (&other_encoder->new_crtc->base != crtc ||
7315 encoder == other_encoder)
7316 continue;
7317 else
7318 return true;
f47166d2
CW		 7319 }
7320
6ed0f796
DV		 7321 return false;
7322}
47f1c6c9 7323
50f56119
DV		 7324static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7325 struct drm_crtc *crtc)
7326{
7327 struct drm_device *dev;
7328 struct drm_crtc *tmp;
7329 int crtc_mask = 1;
47f1c6c9 7330
50f56119 7331 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7332
50f56119 7333 dev = crtc->dev;
47f1c6c9 7334
50f56119
DV		 7335 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7336 if (tmp == crtc)
7337 break;
7338 crtc_mask <<= 1;
7339 }
47f1c6c9 7340
50f56119
DV		 7341 if (encoder->possible_crtcs & crtc_mask)
7342 return true;
7343 return false;
47f1c6c9 7344}
79e53945 7345
9a935856
DV		 7346/**
7347 * intel_modeset_update_staged_output_state
7348 *
7349 * Updates the staged output configuration state, e.g. after we've read out the
7350 * current hw state.
7351 */
7352static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7353{
9a935856
DV		 7354 struct intel_encoder *encoder;
7355 struct intel_connector *connector;
f6e5b160 7356
9a935856
DV		 7357 list_for_each_entry(connector, &dev->mode_config.connector_list,
7358 base.head) {
7359 connector->new_encoder =
7360 to_intel_encoder(connector->base.encoder);
7361 }
f6e5b160 7362
9a935856
DV		 7363 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7364 base.head) {
7365 encoder->new_crtc =
7366 to_intel_crtc(encoder->base.crtc);
7367 }
f6e5b160
CW		 7368}
7369
9a935856
DV		 7370/**
7371 * intel_modeset_commit_output_state
7372 *
7373 * This function copies the stage display pipe configuration to the real one.
7374 */
7375static void intel_modeset_commit_output_state(struct drm_device *dev)
7376{
7377 struct intel_encoder *encoder;
7378 struct intel_connector *connector;
f6e5b160 7379
9a935856
DV		 7380 list_for_each_entry(connector, &dev->mode_config.connector_list,
7381 base.head) {
7382 connector->base.encoder = &connector->new_encoder->base;
7383 }
f6e5b160 7384
9a935856
DV		 7385 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7386 base.head) {
7387 encoder->base.crtc = &encoder->new_crtc->base;
7388 }
7389}
7390
7758a113
DV		 7391static struct drm_display_mode *
7392intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7393 struct drm_display_mode *mode)
ee7b9f93 7394{
7758a113
DV		 7395 struct drm_device *dev = crtc->dev;
7396 struct drm_display_mode *adjusted_mode;
7397 struct drm_encoder_helper_funcs *encoder_funcs;
7398 struct intel_encoder *encoder;
ee7b9f93 7399
7758a113
DV		 7400 adjusted_mode = drm_mode_duplicate(dev, mode);
7401 if (!adjusted_mode)
7402 return ERR_PTR(-ENOMEM);
7403
7404 /* Pass our mode to the connectors and the CRTC to give them a chance to
7405 * adjust it according to limitations or connector properties, and also
7406 * a chance to reject the mode entirely.
7407 */
7408 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7409 base.head) {
7410
7411 if (&encoder->new_crtc->base != crtc)
7412 continue;
7413 encoder_funcs = encoder->base.helper_private;
7414 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7415 adjusted_mode))) {
7416 DRM_DEBUG_KMS("Encoder fixup failed\n");
7417 goto fail;
7418 }
ee7b9f93
JB		 7419 }
7420
7758a113
DV		 7421 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7422 DRM_DEBUG_KMS("CRTC fixup failed\n");
7423 goto fail;
ee7b9f93 7424 }
7758a113
DV		 7425 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7426
7427 return adjusted_mode;
7428fail:
7429 drm_mode_destroy(dev, adjusted_mode);
7430 return ERR_PTR(-EINVAL);
ee7b9f93
JB		 7431}
7432
e2e1ed41
DV		 7433/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7434 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7435static void
7436intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7437 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7438{
7439 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7440 struct drm_device *dev = crtc->dev;
7441 struct intel_encoder *encoder;
7442 struct intel_connector *connector;
7443 struct drm_crtc *tmp_crtc;
79e53945 7444
e2e1ed41 7445 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7446
e2e1ed41
DV		 7447 /* Check which crtcs have changed outputs connected to them, these need
7448 * to be part of the prepare_pipes mask. We don't (yet) support global
7449 * modeset across multiple crtcs, so modeset_pipes will only have one
7450 * bit set at most. */
7451 list_for_each_entry(connector, &dev->mode_config.connector_list,
7452 base.head) {
7453 if (connector->base.encoder == &connector->new_encoder->base)
7454 continue;
79e53945 7455
e2e1ed41
DV		 7456 if (connector->base.encoder) {
7457 tmp_crtc = connector->base.encoder->crtc;
7458
7459 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7460 }
7461
7462 if (connector->new_encoder)
7463 *prepare_pipes |=
7464 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7465 }
7466
e2e1ed41
DV		 7467 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7468 base.head) {
7469 if (encoder->base.crtc == &encoder->new_crtc->base)
7470 continue;
7471
7472 if (encoder->base.crtc) {
7473 tmp_crtc = encoder->base.crtc;
7474
7475 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7476 }
7477
7478 if (encoder->new_crtc)
7479 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7480 }
7481
e2e1ed41
DV		 7482 /* Check for any pipes that will be fully disabled ... */
7483 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7484 base.head) {
7485 bool used = false;
22fd0fab 7486
e2e1ed41
DV		 7487 /* Don't try to disable disabled crtcs. */
7488 if (!intel_crtc->base.enabled)
7489 continue;
7e7d76c3 7490
e2e1ed41
DV		 7491 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7492 base.head) {
7493 if (encoder->new_crtc == intel_crtc)
7494 used = true;
7495 }
7496
7497 if (!used)
7498 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7499 }
7500
e2e1ed41
DV		 7501
7502 /* set_mode is also used to update properties on life display pipes. */
7503 intel_crtc = to_intel_crtc(crtc);
7504 if (crtc->enabled)
7505 *prepare_pipes |= 1 << intel_crtc->pipe;
7506
7507 /* We only support modeset on one single crtc, hence we need to do that
7508 * only for the passed in crtc iff we change anything else than just
7509 * disable crtcs.
7510 *
7511 * This is actually not true, to be fully compatible with the old crtc
7512 * helper we automatically disable _any_ output (i.e. doesn't need to be
7513 * connected to the crtc we're modesetting on) if it's disconnected.
7514 * Which is a rather nutty api (since changed the output configuration
7515 * without userspace's explicit request can lead to confusion), but
7516 * alas. Hence we currently need to modeset on all pipes we prepare. */
7517 if (*prepare_pipes)
7518 *modeset_pipes = *prepare_pipes;
7519
7520 /* ... and mask these out. */
7521 *modeset_pipes &= ~(*disable_pipes);
7522 *prepare_pipes &= ~(*disable_pipes);
7523}
7524
ea9d758d
DV		 7525static bool intel_crtc_in_use(struct drm_crtc *crtc)
7526{
7527 struct drm_encoder *encoder;
7528 struct drm_device *dev = crtc->dev;
7529
7530 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7531 if (encoder->crtc == crtc)
7532 return true;
7533
7534 return false;
7535}
7536
7537static void
7538intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7539{
7540 struct intel_encoder *intel_encoder;
7541 struct intel_crtc *intel_crtc;
7542 struct drm_connector *connector;
7543
7544 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7545 base.head) {
7546 if (!intel_encoder->base.crtc)
7547 continue;
7548
7549 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7550
7551 if (prepare_pipes & (1 << intel_crtc->pipe))
7552 intel_encoder->connectors_active = false;
7553 }
7554
7555 intel_modeset_commit_output_state(dev);
7556
7557 /* Update computed state. */
7558 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7559 base.head) {
7560 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7561 }
7562
7563 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7564 if (!connector->encoder || !connector->encoder->crtc)
7565 continue;
7566
7567 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7568
7569 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7570 struct drm_property *dpms_property =
7571 dev->mode_config.dpms_property;
7572
ea9d758d 7573 connector->dpms = DRM_MODE_DPMS_ON;
68d34720
DV		 7574 drm_connector_property_set_value(connector,
7575 dpms_property,
7576 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7577
7578 intel_encoder = to_intel_encoder(connector->encoder);
7579 intel_encoder->connectors_active = true;
7580 }
7581 }
7582
7583}
7584
25c5b266
DV		 7585#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7586 list_for_each_entry((intel_crtc), \
7587 &(dev)->mode_config.crtc_list, \
7588 base.head) \
7589 if (mask & (1 <<(intel_crtc)->pipe)) \
7590
b980514c 7591void
8af6cf88
DV		 7592intel_modeset_check_state(struct drm_device *dev)
7593{
7594 struct intel_crtc *crtc;
7595 struct intel_encoder *encoder;
7596 struct intel_connector *connector;
7597
7598 list_for_each_entry(connector, &dev->mode_config.connector_list,
7599 base.head) {
7600 /* This also checks the encoder/connector hw state with the
7601 * ->get_hw_state callbacks. */
7602 intel_connector_check_state(connector);
7603
7604 WARN(&connector->new_encoder->base != connector->base.encoder,
7605 "connector's staged encoder doesn't match current encoder\n");
7606 }
7607
7608 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7609 base.head) {
7610 bool enabled = false;
7611 bool active = false;
7612 enum pipe pipe, tracked_pipe;
7613
7614 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7615 encoder->base.base.id,
7616 drm_get_encoder_name(&encoder->base));
7617
7618 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7619 "encoder's stage crtc doesn't match current crtc\n");
7620 WARN(encoder->connectors_active && !encoder->base.crtc,
7621 "encoder's active_connectors set, but no crtc\n");
7622
7623 list_for_each_entry(connector, &dev->mode_config.connector_list,
7624 base.head) {
7625 if (connector->base.encoder != &encoder->base)
7626 continue;
7627 enabled = true;
7628 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7629 active = true;
7630 }
7631 WARN(!!encoder->base.crtc != enabled,
7632 "encoder's enabled state mismatch "
7633 "(expected %i, found %i)\n",
7634 !!encoder->base.crtc, enabled);
7635 WARN(active && !encoder->base.crtc,
7636 "active encoder with no crtc\n");
7637
7638 WARN(encoder->connectors_active != active,
7639 "encoder's computed active state doesn't match tracked active state "
7640 "(expected %i, found %i)\n", active, encoder->connectors_active);
7641
7642 active = encoder->get_hw_state(encoder, &pipe);
7643 WARN(active != encoder->connectors_active,
7644 "encoder's hw state doesn't match sw tracking "
7645 "(expected %i, found %i)\n",
7646 encoder->connectors_active, active);
7647
7648 if (!encoder->base.crtc)
7649 continue;
7650
7651 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7652 WARN(active && pipe != tracked_pipe,
7653 "active encoder's pipe doesn't match"
7654 "(expected %i, found %i)\n",
7655 tracked_pipe, pipe);
7656
7657 }
7658
7659 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7660 base.head) {
7661 bool enabled = false;
7662 bool active = false;
7663
7664 DRM_DEBUG_KMS("[CRTC:%d]\n",
7665 crtc->base.base.id);
7666
7667 WARN(crtc->active && !crtc->base.enabled,
7668 "active crtc, but not enabled in sw tracking\n");
7669
7670 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7671 base.head) {
7672 if (encoder->base.crtc != &crtc->base)
7673 continue;
7674 enabled = true;
7675 if (encoder->connectors_active)
7676 active = true;
7677 }
7678 WARN(active != crtc->active,
7679 "crtc's computed active state doesn't match tracked active state "
7680 "(expected %i, found %i)\n", active, crtc->active);
7681 WARN(enabled != crtc->base.enabled,
7682 "crtc's computed enabled state doesn't match tracked enabled state "
7683 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7684
7685 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7686 }
7687}
7688
a6778b3c
DV		 7689bool intel_set_mode(struct drm_crtc *crtc,
7690 struct drm_display_mode *mode,
94352cf9 7691 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 7692{
7693 struct drm_device *dev = crtc->dev;
dbf2b54e 7694 drm_i915_private_t *dev_priv = dev->dev_private;
a6778b3c 7695 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
25c5b266
DV		 7696 struct intel_crtc *intel_crtc;
7697 unsigned disable_pipes, prepare_pipes, modeset_pipes;
a6778b3c
DV		 7698 bool ret = true;
7699
e2e1ed41 7700 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 7701 &prepare_pipes, &disable_pipes);
7702
7703 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7704 modeset_pipes, prepare_pipes, disable_pipes);
e2e1ed41 7705
976f8a20
DV		 7706 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7707 intel_crtc_disable(&intel_crtc->base);
87f1faa6 7708
a6778b3c
DV		 7709 saved_hwmode = crtc->hwmode;
7710 saved_mode = crtc->mode;
a6778b3c 7711
25c5b266
DV		 7712 /* Hack: Because we don't (yet) support global modeset on multiple
7713 * crtcs, we don't keep track of the new mode for more than one crtc.
7714 * Hence simply check whether any bit is set in modeset_pipes in all the
7715 * pieces of code that are not yet converted to deal with mutliple crtcs
7716 * changing their mode at the same time. */
7717 adjusted_mode = NULL;
7718 if (modeset_pipes) {
7719 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7720 if (IS_ERR(adjusted_mode)) {
7721 return false;
7722 }
25c5b266 7723 }
a6778b3c 7724
ea9d758d
DV		 7725 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7726 if (intel_crtc->base.enabled)
7727 dev_priv->display.crtc_disable(&intel_crtc->base);
7728 }
a6778b3c 7729
6c4c86f5
DV		 7730 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7731 * to set it here already despite that we pass it down the callchain.
7732 */
7733 if (modeset_pipes)
25c5b266 7734 crtc->mode = *mode;
7758a113 7735
ea9d758d
DV		 7736 /* Only after disabling all output pipelines that will be changed can we
7737 * update the the output configuration. */
7738 intel_modeset_update_state(dev, prepare_pipes);
7739
47fab737
DV		 7740 if (dev_priv->display.modeset_global_resources)
7741 dev_priv->display.modeset_global_resources(dev);
7742
a6778b3c
DV		 7743 /* Set up the DPLL and any encoders state that needs to adjust or depend
7744 * on the DPLL.
7745 */
25c5b266
DV		 7746 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7747 ret = !intel_crtc_mode_set(&intel_crtc->base,
7748 mode, adjusted_mode,
7749 x, y, fb);
7750 if (!ret)
7751 goto done;
a6778b3c
DV		 7752 }
7753
7754 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 7755 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7756 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 7757
25c5b266
DV		 7758 if (modeset_pipes) {
7759 /* Store real post-adjustment hardware mode. */
7760 crtc->hwmode = *adjusted_mode;
a6778b3c 7761
25c5b266
DV		 7762 /* Calculate and store various constants which
7763 * are later needed by vblank and swap-completion
7764 * timestamping. They are derived from true hwmode.
7765 */
7766 drm_calc_timestamping_constants(crtc);
7767 }
a6778b3c
DV		 7768
7769 /* FIXME: add subpixel order */
7770done:
7771 drm_mode_destroy(dev, adjusted_mode);
25c5b266 7772 if (!ret && crtc->enabled) {
a6778b3c
DV		 7773 crtc->hwmode = saved_hwmode;
7774 crtc->mode = saved_mode;
8af6cf88
DV		 7775 } else {
7776 intel_modeset_check_state(dev);
a6778b3c
DV		 7777 }
7778
7779 return ret;
7780}
7781
25c5b266
DV		 7782#undef for_each_intel_crtc_masked
7783
d9e55608
DV		 7784static void intel_set_config_free(struct intel_set_config *config)
7785{
7786 if (!config)
7787 return;
7788
1aa4b628
DV		 7789 kfree(config->save_connector_encoders);
7790 kfree(config->save_encoder_crtcs);
d9e55608
DV		 7791 kfree(config);
7792}
7793
85f9eb71
DV		 7794static int intel_set_config_save_state(struct drm_device *dev,
7795 struct intel_set_config *config)
7796{
85f9eb71
DV		 7797 struct drm_encoder *encoder;
7798 struct drm_connector *connector;
7799 int count;
7800
1aa4b628
DV		 7801 config->save_encoder_crtcs =
7802 kcalloc(dev->mode_config.num_encoder,
7803 sizeof(struct drm_crtc *), GFP_KERNEL);
7804 if (!config->save_encoder_crtcs)
85f9eb71
DV		 7805 return -ENOMEM;
7806
1aa4b628
DV		 7807 config->save_connector_encoders =
7808 kcalloc(dev->mode_config.num_connector,
7809 sizeof(struct drm_encoder *), GFP_KERNEL);
7810 if (!config->save_connector_encoders)
85f9eb71
DV		 7811 return -ENOMEM;
7812
7813 /* Copy data. Note that driver private data is not affected.
7814 * Should anything bad happen only the expected state is
7815 * restored, not the drivers personal bookkeeping.
7816 */
85f9eb71
DV		 7817 count = 0;
7818 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 7819 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 7820 }
7821
7822 count = 0;
7823 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 7824 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 7825 }
7826
7827 return 0;
7828}
7829
7830static void intel_set_config_restore_state(struct drm_device *dev,
7831 struct intel_set_config *config)
7832{
9a935856
DV		 7833 struct intel_encoder *encoder;
7834 struct intel_connector *connector;
85f9eb71
DV		 7835 int count;
7836
85f9eb71 7837 count = 0;
9a935856
DV		 7838 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7839 encoder->new_crtc =
7840 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 7841 }
7842
7843 count = 0;
9a935856
DV		 7844 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7845 connector->new_encoder =
7846 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 7847 }
7848}
7849
5e2b584e
DV		 7850static void
7851intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7852 struct intel_set_config *config)
7853{
7854
7855 /* We should be able to check here if the fb has the same properties
7856 * and then just flip_or_move it */
7857 if (set->crtc->fb != set->fb) {
7858 /* If we have no fb then treat it as a full mode set */
7859 if (set->crtc->fb == NULL) {
7860 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7861 config->mode_changed = true;
7862 } else if (set->fb == NULL) {
7863 config->mode_changed = true;
7864 } else if (set->fb->depth != set->crtc->fb->depth) {
7865 config->mode_changed = true;
7866 } else if (set->fb->bits_per_pixel !=
7867 set->crtc->fb->bits_per_pixel) {
7868 config->mode_changed = true;
7869 } else
7870 config->fb_changed = true;
7871 }
7872
835c5873 7873 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 7874 config->fb_changed = true;
7875
7876 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7877 DRM_DEBUG_KMS("modes are different, full mode set\n");
7878 drm_mode_debug_printmodeline(&set->crtc->mode);
7879 drm_mode_debug_printmodeline(set->mode);
7880 config->mode_changed = true;
7881 }
7882}
7883
2e431051 7884static int
9a935856
DV		 7885intel_modeset_stage_output_state(struct drm_device *dev,
7886 struct drm_mode_set *set,
7887 struct intel_set_config *config)
50f56119 7888{
85f9eb71 7889 struct drm_crtc *new_crtc;
9a935856
DV		 7890 struct intel_connector *connector;
7891 struct intel_encoder *encoder;
2e431051 7892 int count, ro;
50f56119 7893
9a935856
DV		 7894 /* The upper layers ensure that we either disabl a crtc or have a list
7895 * of connectors. For paranoia, double-check this. */
7896 WARN_ON(!set->fb && (set->num_connectors != 0));
7897 WARN_ON(set->fb && (set->num_connectors == 0));
7898
50f56119 7899 count = 0;
9a935856
DV		 7900 list_for_each_entry(connector, &dev->mode_config.connector_list,
7901 base.head) {
7902 /* Otherwise traverse passed in connector list and get encoders
7903 * for them. */
50f56119 7904 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 7905 if (set->connectors[ro] == &connector->base) {
7906 connector->new_encoder = connector->encoder;
50f56119
DV		 7907 break;
7908 }
7909 }
7910
9a935856
DV		 7911 /* If we disable the crtc, disable all its connectors. Also, if
7912 * the connector is on the changing crtc but not on the new
7913 * connector list, disable it. */
7914 if ((!set->fb || ro == set->num_connectors) &&
7915 connector->base.encoder &&
7916 connector->base.encoder->crtc == set->crtc) {
7917 connector->new_encoder = NULL;
7918
7919 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7920 connector->base.base.id,
7921 drm_get_connector_name(&connector->base));
7922 }
7923
7924
7925 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 7926 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 7927 config->mode_changed = true;
50f56119 7928 }
9a935856
DV		 7929
7930 /* Disable all disconnected encoders. */
7931 if (connector->base.status == connector_status_disconnected)
7932 connector->new_encoder = NULL;
50f56119 7933 }
9a935856 7934 /* connector->new_encoder is now updated for all connectors. */
50f56119 7935
9a935856 7936 /* Update crtc of enabled connectors. */
50f56119 7937 count = 0;
9a935856
DV		 7938 list_for_each_entry(connector, &dev->mode_config.connector_list,
7939 base.head) {
7940 if (!connector->new_encoder)
50f56119
DV		 7941 continue;
7942
9a935856 7943 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 7944
7945 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 7946 if (set->connectors[ro] == &connector->base)
50f56119
DV		 7947 new_crtc = set->crtc;
7948 }
7949
7950 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 7951 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7952 new_crtc)) {
5e2b584e 7953 return -EINVAL;
50f56119 7954 }
9a935856
DV		 7955 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7956
7957 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7958 connector->base.base.id,
7959 drm_get_connector_name(&connector->base),
7960 new_crtc->base.id);
7961 }
7962
7963 /* Check for any encoders that needs to be disabled. */
7964 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7965 base.head) {
7966 list_for_each_entry(connector,
7967 &dev->mode_config.connector_list,
7968 base.head) {
7969 if (connector->new_encoder == encoder) {
7970 WARN_ON(!connector->new_encoder->new_crtc);
7971
7972 goto next_encoder;
7973 }
7974 }
7975 encoder->new_crtc = NULL;
7976next_encoder:
7977 /* Only now check for crtc changes so we don't miss encoders
7978 * that will be disabled. */
7979 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 7980 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 7981 config->mode_changed = true;
50f56119
DV		 7982 }
7983 }
9a935856 7984 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 7985
2e431051
DV		 7986 return 0;
7987}
7988
7989static int intel_crtc_set_config(struct drm_mode_set *set)
7990{
7991 struct drm_device *dev;
2e431051
DV		 7992 struct drm_mode_set save_set;
7993 struct intel_set_config *config;
7994 int ret;
2e431051 7995
8d3e375e
DV		 7996 BUG_ON(!set);
7997 BUG_ON(!set->crtc);
7998 BUG_ON(!set->crtc->helper_private);
2e431051
DV		 7999
8000 if (!set->mode)
8001 set->fb = NULL;
8002
431e50f7
DV		 8003 /* The fb helper likes to play gross jokes with ->mode_set_config.
8004 * Unfortunately the crtc helper doesn't do much at all for this case,
8005 * so we have to cope with this madness until the fb helper is fixed up. */
8006 if (set->fb && set->num_connectors == 0)
8007 return 0;
8008
2e431051
DV		 8009 if (set->fb) {
8010 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8011 set->crtc->base.id, set->fb->base.id,
8012 (int)set->num_connectors, set->x, set->y);
8013 } else {
8014 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8015 }
8016
8017 dev = set->crtc->dev;
8018
8019 ret = -ENOMEM;
8020 config = kzalloc(sizeof(*config), GFP_KERNEL);
8021 if (!config)
8022 goto out_config;
8023
8024 ret = intel_set_config_save_state(dev, config);
8025 if (ret)
8026 goto out_config;
8027
8028 save_set.crtc = set->crtc;
8029 save_set.mode = &set->crtc->mode;
8030 save_set.x = set->crtc->x;
8031 save_set.y = set->crtc->y;
8032 save_set.fb = set->crtc->fb;
8033
8034 /* Compute whether we need a full modeset, only an fb base update or no
8035 * change at all. In the future we might also check whether only the
8036 * mode changed, e.g. for LVDS where we only change the panel fitter in
8037 * such cases. */
8038 intel_set_config_compute_mode_changes(set, config);
8039
9a935856 8040 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8041 if (ret)
8042 goto fail;
8043
5e2b584e 8044 if (config->mode_changed) {
87f1faa6 8045 if (set->mode) {
50f56119
DV		 8046 DRM_DEBUG_KMS("attempting to set mode from"
8047 " userspace\n");
8048 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 8049 }
8050
8051 if (!intel_set_mode(set->crtc, set->mode,
8052 set->x, set->y, set->fb)) {
8053 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
8054 set->crtc->base.id);
8055 ret = -EINVAL;
8056 goto fail;
8057 }
5e2b584e 8058 } else if (config->fb_changed) {
4f660f49 8059 ret = intel_pipe_set_base(set->crtc,
94352cf9 8060 set->x, set->y, set->fb);
50f56119
DV		 8061 }
8062
d9e55608
DV		 8063 intel_set_config_free(config);
8064
50f56119
DV		 8065 return 0;
8066
8067fail:
85f9eb71 8068 intel_set_config_restore_state(dev, config);
50f56119
DV		 8069
8070 /* Try to restore the config */
5e2b584e 8071 if (config->mode_changed &&
a6778b3c
DV		 8072 !intel_set_mode(save_set.crtc, save_set.mode,
8073 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8074 DRM_ERROR("failed to restore config after modeset failure\n");
8075
d9e55608
DV		 8076out_config:
8077 intel_set_config_free(config);
50f56119
DV		 8078 return ret;
8079}
8080
f6e5b160 8081static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8082 .cursor_set = intel_crtc_cursor_set,
8083 .cursor_move = intel_crtc_cursor_move,
8084 .gamma_set = intel_crtc_gamma_set,
50f56119 8085 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8086 .destroy = intel_crtc_destroy,
8087 .page_flip = intel_crtc_page_flip,
8088};
8089
79f689aa
PZ		 8090static void intel_cpu_pll_init(struct drm_device *dev)
8091{
8092 if (IS_HASWELL(dev))
8093 intel_ddi_pll_init(dev);
8094}
8095
ee7b9f93
JB		 8096static void intel_pch_pll_init(struct drm_device *dev)
8097{
8098 drm_i915_private_t *dev_priv = dev->dev_private;
8099 int i;
8100
8101 if (dev_priv->num_pch_pll == 0) {
8102 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8103 return;
8104 }
8105
8106 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8107 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8108 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8109 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8110 }
8111}
8112
b358d0a6 8113static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8114{
22fd0fab 8115 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8116 struct intel_crtc *intel_crtc;
8117 int i;
8118
8119 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8120 if (intel_crtc == NULL)
8121 return;
8122
8123 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8124
8125 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8126 for (i = 0; i < 256; i++) {
8127 intel_crtc->lut_r[i] = i;
8128 intel_crtc->lut_g[i] = i;
8129 intel_crtc->lut_b[i] = i;
8130 }
8131
80824003
JB		 8132 /* Swap pipes & planes for FBC on pre-965 */
8133 intel_crtc->pipe = pipe;
8134 intel_crtc->plane = pipe;
a5c961d1 8135 intel_crtc->cpu_transcoder = pipe;
e2e767ab 8136 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8137 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8138 intel_crtc->plane = !pipe;
80824003
JB		 8139 }
8140
22fd0fab
JB		 8141 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8142 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8143 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8144 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8145
5a354204 8146 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3 8147
79e53945 8148 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8149}
8150
08d7b3d1 8151int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8152 struct drm_file *file)
08d7b3d1 8153{
08d7b3d1 8154 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8155 struct drm_mode_object *drmmode_obj;
8156 struct intel_crtc *crtc;
08d7b3d1 8157
1cff8f6b
DV		 8158 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8159 return -ENODEV;
08d7b3d1 8160
c05422d5
DV		 8161 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8162 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8163
c05422d5 8164 if (!drmmode_obj) {
08d7b3d1
CW		 8165 DRM_ERROR("no such CRTC id\n");
8166 return -EINVAL;
8167 }
8168
c05422d5
DV		 8169 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8170 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8171
c05422d5 8172 return 0;
08d7b3d1
CW		 8173}
8174
66a9278e 8175static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8176{
66a9278e
DV		 8177 struct drm_device *dev = encoder->base.dev;
8178 struct intel_encoder *source_encoder;
79e53945 8179 int index_mask = 0;
79e53945
JB		 8180 int entry = 0;
8181
66a9278e
DV		 8182 list_for_each_entry(source_encoder,
8183 &dev->mode_config.encoder_list, base.head) {
8184
8185 if (encoder == source_encoder)
79e53945 8186 index_mask |= (1 << entry);
66a9278e
DV		 8187
8188 /* Intel hw has only one MUX where enocoders could be cloned. */
8189 if (encoder->cloneable && source_encoder->cloneable)
8190 index_mask |= (1 << entry);
8191
79e53945
JB		 8192 entry++;
8193 }
4ef69c7a 8194
79e53945
JB		 8195 return index_mask;
8196}
8197
4d302442
CW		 8198static bool has_edp_a(struct drm_device *dev)
8199{
8200 struct drm_i915_private *dev_priv = dev->dev_private;
8201
8202 if (!IS_MOBILE(dev))
8203 return false;
8204
8205 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8206 return false;
8207
8208 if (IS_GEN5(dev) &&
8209 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8210 return false;
8211
8212 return true;
8213}
8214
79e53945
JB		 8215static void intel_setup_outputs(struct drm_device *dev)
8216{
725e30ad 8217 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8218 struct intel_encoder *encoder;
cb0953d7 8219 bool dpd_is_edp = false;
f3cfcba6 8220 bool has_lvds;
79e53945 8221
f3cfcba6 8222 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8223 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8224 /* disable the panel fitter on everything but LVDS */
8225 I915_WRITE(PFIT_CONTROL, 0);
8226 }
79e53945 8227
bad720ff 8228 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8229 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 8230
4d302442 8231 if (has_edp_a(dev))
ab9d7c30 8232 intel_dp_init(dev, DP_A, PORT_A);
32f9d658 8233
cb0953d7 8234 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
ab9d7c30 8235 intel_dp_init(dev, PCH_DP_D, PORT_D);
cb0953d7
AJ		 8236 }
8237
8238 intel_crt_init(dev);
8239
0e72a5b5
ED		 8240 if (IS_HASWELL(dev)) {
8241 int found;
8242
8243 /* Haswell uses DDI functions to detect digital outputs */
8244 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8245 /* DDI A only supports eDP */
8246 if (found)
8247 intel_ddi_init(dev, PORT_A);
8248
8249 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8250 * register */
8251 found = I915_READ(SFUSE_STRAP);
8252
8253 if (found & SFUSE_STRAP_DDIB_DETECTED)
8254 intel_ddi_init(dev, PORT_B);
8255 if (found & SFUSE_STRAP_DDIC_DETECTED)
8256 intel_ddi_init(dev, PORT_C);
8257 if (found & SFUSE_STRAP_DDID_DETECTED)
8258 intel_ddi_init(dev, PORT_D);
8259 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7
AJ		 8260 int found;
8261
30ad48b7 8262 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 8263 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8264 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8265 if (!found)
08d644ad 8266 intel_hdmi_init(dev, HDMIB, PORT_B);
5eb08b69 8267 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8268 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8269 }
8270
8271 if (I915_READ(HDMIC) & PORT_DETECTED)
08d644ad 8272 intel_hdmi_init(dev, HDMIC, PORT_C);
30ad48b7 8273
b708a1d5 8274 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
08d644ad 8275 intel_hdmi_init(dev, HDMID, PORT_D);
30ad48b7 8276
5eb08b69 8277 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8278 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8279
cb0953d7 8280 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
ab9d7c30 8281 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d
JB		 8282 } else if (IS_VALLEYVIEW(dev)) {
8283 int found;
8284
19c03924
GB		 8285 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8286 if (I915_READ(DP_C) & DP_DETECTED)
8287 intel_dp_init(dev, DP_C, PORT_C);
8288
4a87d65d
JB		 8289 if (I915_READ(SDVOB) & PORT_DETECTED) {
8290 /* SDVOB multiplex with HDMIB */
8291 found = intel_sdvo_init(dev, SDVOB, true);
8292 if (!found)
08d644ad 8293 intel_hdmi_init(dev, SDVOB, PORT_B);
4a87d65d 8294 if (!found && (I915_READ(DP_B) & DP_DETECTED))
ab9d7c30 8295 intel_dp_init(dev, DP_B, PORT_B);
4a87d65d
JB		 8296 }
8297
8298 if (I915_READ(SDVOC) & PORT_DETECTED)
08d644ad 8299 intel_hdmi_init(dev, SDVOC, PORT_C);
5eb08b69 8300
103a196f 8301 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8302 bool found = false;
7d57382e 8303
725e30ad 8304 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 8305 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 8306 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 8307 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8308 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
08d644ad 8309 intel_hdmi_init(dev, SDVOB, PORT_B);
b01f2c3a 8310 }
27185ae1 8311
b01f2c3a
JB		 8312 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8313 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8314 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8315 }
725e30ad 8316 }
13520b05
KH		 8317
8318 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8319
b01f2c3a
JB		 8320 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8321 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 8322 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 8323 }
27185ae1
ML		 8324
8325 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8326
b01f2c3a
JB		 8327 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8328 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
08d644ad 8329 intel_hdmi_init(dev, SDVOC, PORT_C);
b01f2c3a
JB		 8330 }
8331 if (SUPPORTS_INTEGRATED_DP(dev)) {
8332 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8333 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8334 }
725e30ad 8335 }
27185ae1 8336
b01f2c3a
JB		 8337 if (SUPPORTS_INTEGRATED_DP(dev) &&
8338 (I915_READ(DP_D) & DP_DETECTED)) {
8339 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8340 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8341 }
bad720ff 8342 } else if (IS_GEN2(dev))
79e53945
JB		 8343 intel_dvo_init(dev);
8344
103a196f 8345 if (SUPPORTS_TV(dev))
79e53945
JB		 8346 intel_tv_init(dev);
8347
4ef69c7a
CW		 8348 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8349 encoder->base.possible_crtcs = encoder->crtc_mask;
8350 encoder->base.possible_clones =
66a9278e 8351 intel_encoder_clones(encoder);
79e53945 8352 }
47356eb6 8353
40579abe 8354 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9fb526db 8355 ironlake_init_pch_refclk(dev);
79e53945
JB		 8356}
8357
8358static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8359{
8360 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8361
8362 drm_framebuffer_cleanup(fb);
05394f39 8363 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8364
8365 kfree(intel_fb);
8366}
8367
8368static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8369 struct drm_file *file,
79e53945
JB		 8370 unsigned int *handle)
8371{
8372 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8373 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8374
05394f39 8375 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8376}
8377
8378static const struct drm_framebuffer_funcs intel_fb_funcs = {
8379 .destroy = intel_user_framebuffer_destroy,
8380 .create_handle = intel_user_framebuffer_create_handle,
8381};
8382
38651674
DA		 8383int intel_framebuffer_init(struct drm_device *dev,
8384 struct intel_framebuffer *intel_fb,
308e5bcb 8385 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8386 struct drm_i915_gem_object *obj)
79e53945 8387{
79e53945
JB		 8388 int ret;
8389
05394f39 8390 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 8391 return -EINVAL;
8392
308e5bcb 8393 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 8394 return -EINVAL;
8395
5d7bd705
VS		 8396 /* FIXME <= Gen4 stride limits are bit unclear */
8397 if (mode_cmd->pitches[0] > 32768)
8398 return -EINVAL;
8399
8400 if (obj->tiling_mode != I915_TILING_NONE &&
8401 mode_cmd->pitches[0] != obj->stride)
8402 return -EINVAL;
8403
57779d06 8404 /* Reject formats not supported by any plane early. */
308e5bcb 8405 switch (mode_cmd->pixel_format) {
57779d06 8406 case DRM_FORMAT_C8:
04b3924d
VS		 8407 case DRM_FORMAT_RGB565:
8408 case DRM_FORMAT_XRGB8888:
8409 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8410 break;
8411 case DRM_FORMAT_XRGB1555:
8412 case DRM_FORMAT_ARGB1555:
8413 if (INTEL_INFO(dev)->gen > 3)
8414 return -EINVAL;
8415 break;
8416 case DRM_FORMAT_XBGR8888:
8417 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8418 case DRM_FORMAT_XRGB2101010:
8419 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8420 case DRM_FORMAT_XBGR2101010:
8421 case DRM_FORMAT_ABGR2101010:
8422 if (INTEL_INFO(dev)->gen < 4)
8423 return -EINVAL;
b5626747 8424 break;
04b3924d
VS		 8425 case DRM_FORMAT_YUYV:
8426 case DRM_FORMAT_UYVY:
8427 case DRM_FORMAT_YVYU:
8428 case DRM_FORMAT_VYUY:
57779d06
VS		 8429 if (INTEL_INFO(dev)->gen < 6)
8430 return -EINVAL;
57cd6508
CW		 8431 break;
8432 default:
57779d06 8433 DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8434 return -EINVAL;
8435 }
8436
90f9a336
VS		 8437 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8438 if (mode_cmd->offsets[0] != 0)
8439 return -EINVAL;
8440
79e53945
JB		 8441 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8442 if (ret) {
8443 DRM_ERROR("framebuffer init failed %d\n", ret);
8444 return ret;
8445 }
8446
8447 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 8448 intel_fb->obj = obj;
79e53945
JB		 8449 return 0;
8450}
8451
79e53945
JB		 8452static struct drm_framebuffer *
8453intel_user_framebuffer_create(struct drm_device *dev,
8454 struct drm_file *filp,
308e5bcb 8455 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8456{
05394f39 8457 struct drm_i915_gem_object *obj;
79e53945 8458
308e5bcb
JB		 8459 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8460 mode_cmd->handles[0]));
c8725226 8461 if (&obj->base == NULL)
cce13ff7 8462 return ERR_PTR(-ENOENT);
79e53945 8463
d2dff872 8464 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8465}
8466
79e53945 8467static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8468 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8469 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8470};
8471
e70236a8
JB		 8472/* Set up chip specific display functions */
8473static void intel_init_display(struct drm_device *dev)
8474{
8475 struct drm_i915_private *dev_priv = dev->dev_private;
8476
8477 /* We always want a DPMS function */
09b4ddf9
PZ		 8478 if (IS_HASWELL(dev)) {
8479 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8480 dev_priv->display.crtc_enable = haswell_crtc_enable;
8481 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8482 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8483 dev_priv->display.update_plane = ironlake_update_plane;
8484 } else if (HAS_PCH_SPLIT(dev)) {
f564048e 8485 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8486 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8487 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8488 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8489 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8490 } else {
f564048e 8491 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8492 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8493 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8494 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8495 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8496 }
e70236a8 8497
e70236a8 8498 /* Returns the core display clock speed */
25eb05fc
JB		 8499 if (IS_VALLEYVIEW(dev))
8500 dev_priv->display.get_display_clock_speed =
8501 valleyview_get_display_clock_speed;
8502 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8503 dev_priv->display.get_display_clock_speed =
8504 i945_get_display_clock_speed;
8505 else if (IS_I915G(dev))
8506 dev_priv->display.get_display_clock_speed =
8507 i915_get_display_clock_speed;
f2b115e6 8508 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8509 dev_priv->display.get_display_clock_speed =
8510 i9xx_misc_get_display_clock_speed;
8511 else if (IS_I915GM(dev))
8512 dev_priv->display.get_display_clock_speed =
8513 i915gm_get_display_clock_speed;
8514 else if (IS_I865G(dev))
8515 dev_priv->display.get_display_clock_speed =
8516 i865_get_display_clock_speed;
f0f8a9ce 8517 else if (IS_I85X(dev))
e70236a8
JB		 8518 dev_priv->display.get_display_clock_speed =
8519 i855_get_display_clock_speed;
8520 else /* 852, 830 */
8521 dev_priv->display.get_display_clock_speed =
8522 i830_get_display_clock_speed;
8523
7f8a8569 8524 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8525 if (IS_GEN5(dev)) {
674cf967 8526 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8527 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8528 } else if (IS_GEN6(dev)) {
674cf967 8529 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8530 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8531 } else if (IS_IVYBRIDGE(dev)) {
8532 /* FIXME: detect B0+ stepping and use auto training */
8533 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8534 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8535 dev_priv->display.modeset_global_resources =
8536 ivb_modeset_global_resources;
c82e4d26
ED		 8537 } else if (IS_HASWELL(dev)) {
8538 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8539 dev_priv->display.write_eld = haswell_write_eld;
7f8a8569
ZW		 8540 } else
8541 dev_priv->display.update_wm = NULL;
6067aaea 8542 } else if (IS_G4X(dev)) {
e0dac65e 8543 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8544 }
8c9f3aaf
JB		 8545
8546 /* Default just returns -ENODEV to indicate unsupported */
8547 dev_priv->display.queue_flip = intel_default_queue_flip;
8548
8549 switch (INTEL_INFO(dev)->gen) {
8550 case 2:
8551 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8552 break;
8553
8554 case 3:
8555 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8556 break;
8557
8558 case 4:
8559 case 5:
8560 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8561 break;
8562
8563 case 6:
8564 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8565 break;
7c9017e5
JB		 8566 case 7:
8567 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8568 break;
8c9f3aaf 8569 }
e70236a8
JB		 8570}
8571
b690e96c
JB		 8572/*
8573 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8574 * resume, or other times. This quirk makes sure that's the case for
8575 * affected systems.
8576 */
0206e353 8577static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8578{
8579 struct drm_i915_private *dev_priv = dev->dev_private;
8580
8581 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 8582 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 8583}
8584
435793df
KP		 8585/*
8586 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8587 */
8588static void quirk_ssc_force_disable(struct drm_device *dev)
8589{
8590 struct drm_i915_private *dev_priv = dev->dev_private;
8591 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 8592 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 8593}
8594
4dca20ef 8595/*
5a15ab5b
CE		 8596 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8597 * brightness value
4dca20ef
CE		 8598 */
8599static void quirk_invert_brightness(struct drm_device *dev)
8600{
8601 struct drm_i915_private *dev_priv = dev->dev_private;
8602 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 8603 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 8604}
8605
b690e96c
JB		 8606struct intel_quirk {
8607 int device;
8608 int subsystem_vendor;
8609 int subsystem_device;
8610 void (*hook)(struct drm_device *dev);
8611};
8612
c43b5634 8613static struct intel_quirk intel_quirks[] = {
b690e96c 8614 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8615 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 8616
b690e96c
JB		 8617 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8618 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8619
b690e96c
JB		 8620 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8621 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8622
ccd0d36e 8623 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 8624 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 8625 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8626
8627 /* Lenovo U160 cannot use SSC on LVDS */
8628 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8629
8630 /* Sony Vaio Y cannot use SSC on LVDS */
8631 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 8632
8633 /* Acer Aspire 5734Z must invert backlight brightness */
8634 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
b690e96c
JB		 8635};
8636
8637static void intel_init_quirks(struct drm_device *dev)
8638{
8639 struct pci_dev *d = dev->pdev;
8640 int i;
8641
8642 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8643 struct intel_quirk *q = &intel_quirks[i];
8644
8645 if (d->device == q->device &&
8646 (d->subsystem_vendor == q->subsystem_vendor ||
8647 q->subsystem_vendor == PCI_ANY_ID) &&
8648 (d->subsystem_device == q->subsystem_device ||
8649 q->subsystem_device == PCI_ANY_ID))
8650 q->hook(dev);
8651 }
8652}
8653
9cce37f4
JB		 8654/* Disable the VGA plane that we never use */
8655static void i915_disable_vga(struct drm_device *dev)
8656{
8657 struct drm_i915_private *dev_priv = dev->dev_private;
8658 u8 sr1;
8659 u32 vga_reg;
8660
8661 if (HAS_PCH_SPLIT(dev))
8662 vga_reg = CPU_VGACNTRL;
8663 else
8664 vga_reg = VGACNTRL;
8665
8666 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 8667 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 8668 sr1 = inb(VGA_SR_DATA);
8669 outb(sr1 | 1<<5, VGA_SR_DATA);
8670 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8671 udelay(300);
8672
8673 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8674 POSTING_READ(vga_reg);
8675}
8676
f817586c
DV		 8677void intel_modeset_init_hw(struct drm_device *dev)
8678{
0232e927
ED		 8679 /* We attempt to init the necessary power wells early in the initialization
8680 * time, so the subsystems that expect power to be enabled can work.
8681 */
8682 intel_init_power_wells(dev);
8683
a8f78b58
ED		 8684 intel_prepare_ddi(dev);
8685
f817586c
DV		 8686 intel_init_clock_gating(dev);
8687
79f5b2c7 8688 mutex_lock(&dev->struct_mutex);
8090c6b9 8689 intel_enable_gt_powersave(dev);
79f5b2c7 8690 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 8691}
8692
79e53945
JB		 8693void intel_modeset_init(struct drm_device *dev)
8694{
652c393a 8695 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 8696 int i, ret;
79e53945
JB		 8697
8698 drm_mode_config_init(dev);
8699
8700 dev->mode_config.min_width = 0;
8701 dev->mode_config.min_height = 0;
8702
019d96cb
DA		 8703 dev->mode_config.preferred_depth = 24;
8704 dev->mode_config.prefer_shadow = 1;
8705
e6ecefaa 8706 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 8707
b690e96c
JB		 8708 intel_init_quirks(dev);
8709
1fa61106
ED		 8710 intel_init_pm(dev);
8711
e70236a8
JB		 8712 intel_init_display(dev);
8713
a6c45cf0
CW		 8714 if (IS_GEN2(dev)) {
8715 dev->mode_config.max_width = 2048;
8716 dev->mode_config.max_height = 2048;
8717 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 8718 dev->mode_config.max_width = 4096;
8719 dev->mode_config.max_height = 4096;
79e53945 8720 } else {
a6c45cf0
CW		 8721 dev->mode_config.max_width = 8192;
8722 dev->mode_config.max_height = 8192;
79e53945 8723 }
dd2757f8 8724 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
79e53945 8725
28c97730 8726 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 8727 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 8728
a3524f1b 8729 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 8730 intel_crtc_init(dev, i);
00c2064b
JB		 8731 ret = intel_plane_init(dev, i);
8732 if (ret)
8733 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 8734 }
8735
79f689aa 8736 intel_cpu_pll_init(dev);
ee7b9f93
JB		 8737 intel_pch_pll_init(dev);
8738
9cce37f4
JB		 8739 /* Just disable it once at startup */
8740 i915_disable_vga(dev);
79e53945 8741 intel_setup_outputs(dev);
2c7111db
CW		 8742}
8743
24929352
DV		 8744static void
8745intel_connector_break_all_links(struct intel_connector *connector)
8746{
8747 connector->base.dpms = DRM_MODE_DPMS_OFF;
8748 connector->base.encoder = NULL;
8749 connector->encoder->connectors_active = false;
8750 connector->encoder->base.crtc = NULL;
8751}
8752
7fad798e
DV		 8753static void intel_enable_pipe_a(struct drm_device *dev)
8754{
8755 struct intel_connector *connector;
8756 struct drm_connector *crt = NULL;
8757 struct intel_load_detect_pipe load_detect_temp;
8758
8759 /* We can't just switch on the pipe A, we need to set things up with a
8760 * proper mode and output configuration. As a gross hack, enable pipe A
8761 * by enabling the load detect pipe once. */
8762 list_for_each_entry(connector,
8763 &dev->mode_config.connector_list,
8764 base.head) {
8765 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8766 crt = &connector->base;
8767 break;
8768 }
8769 }
8770
8771 if (!crt)
8772 return;
8773
8774 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8775 intel_release_load_detect_pipe(crt, &load_detect_temp);
8776
8777
8778}
8779
fa555837
DV		 8780static bool
8781intel_check_plane_mapping(struct intel_crtc *crtc)
8782{
8783 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8784 u32 reg, val;
8785
8786 if (dev_priv->num_pipe == 1)
8787 return true;
8788
8789 reg = DSPCNTR(!crtc->plane);
8790 val = I915_READ(reg);
8791
8792 if ((val & DISPLAY_PLANE_ENABLE) &&
8793 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8794 return false;
8795
8796 return true;
8797}
8798
24929352
DV		 8799static void intel_sanitize_crtc(struct intel_crtc *crtc)
8800{
8801 struct drm_device *dev = crtc->base.dev;
8802 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 8803 u32 reg;
24929352 8804
24929352 8805 /* Clear any frame start delays used for debugging left by the BIOS */
702e7a56 8806 reg = PIPECONF(crtc->cpu_transcoder);
24929352
DV		 8807 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8808
8809 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 8810 * disable the crtc (and hence change the state) if it is wrong. Note
8811 * that gen4+ has a fixed plane -> pipe mapping. */
8812 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 8813 struct intel_connector *connector;
8814 bool plane;
8815
24929352
DV		 8816 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8817 crtc->base.base.id);
8818
8819 /* Pipe has the wrong plane attached and the plane is active.
8820 * Temporarily change the plane mapping and disable everything
8821 * ... */
8822 plane = crtc->plane;
8823 crtc->plane = !plane;
8824 dev_priv->display.crtc_disable(&crtc->base);
8825 crtc->plane = plane;
8826
8827 /* ... and break all links. */
8828 list_for_each_entry(connector, &dev->mode_config.connector_list,
8829 base.head) {
8830 if (connector->encoder->base.crtc != &crtc->base)
8831 continue;
8832
8833 intel_connector_break_all_links(connector);
8834 }
8835
8836 WARN_ON(crtc->active);
8837 crtc->base.enabled = false;
8838 }
24929352 8839
7fad798e
DV		 8840 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8841 crtc->pipe == PIPE_A && !crtc->active) {
8842 /* BIOS forgot to enable pipe A, this mostly happens after
8843 * resume. Force-enable the pipe to fix this, the update_dpms
8844 * call below we restore the pipe to the right state, but leave
8845 * the required bits on. */
8846 intel_enable_pipe_a(dev);
8847 }
8848
24929352
DV		 8849 /* Adjust the state of the output pipe according to whether we
8850 * have active connectors/encoders. */
8851 intel_crtc_update_dpms(&crtc->base);
8852
8853 if (crtc->active != crtc->base.enabled) {
8854 struct intel_encoder *encoder;
8855
8856 /* This can happen either due to bugs in the get_hw_state
8857 * functions or because the pipe is force-enabled due to the
8858 * pipe A quirk. */
8859 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8860 crtc->base.base.id,
8861 crtc->base.enabled ? "enabled" : "disabled",
8862 crtc->active ? "enabled" : "disabled");
8863
8864 crtc->base.enabled = crtc->active;
8865
8866 /* Because we only establish the connector -> encoder ->
8867 * crtc links if something is active, this means the
8868 * crtc is now deactivated. Break the links. connector
8869 * -> encoder links are only establish when things are
8870 * actually up, hence no need to break them. */
8871 WARN_ON(crtc->active);
8872
8873 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8874 WARN_ON(encoder->connectors_active);
8875 encoder->base.crtc = NULL;
8876 }
8877 }
8878}
8879
8880static void intel_sanitize_encoder(struct intel_encoder *encoder)
8881{
8882 struct intel_connector *connector;
8883 struct drm_device *dev = encoder->base.dev;
8884
8885 /* We need to check both for a crtc link (meaning that the
8886 * encoder is active and trying to read from a pipe) and the
8887 * pipe itself being active. */
8888 bool has_active_crtc = encoder->base.crtc &&
8889 to_intel_crtc(encoder->base.crtc)->active;
8890
8891 if (encoder->connectors_active && !has_active_crtc) {
8892 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8893 encoder->base.base.id,
8894 drm_get_encoder_name(&encoder->base));
8895
8896 /* Connector is active, but has no active pipe. This is
8897 * fallout from our resume register restoring. Disable
8898 * the encoder manually again. */
8899 if (encoder->base.crtc) {
8900 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8901 encoder->base.base.id,
8902 drm_get_encoder_name(&encoder->base));
8903 encoder->disable(encoder);
8904 }
8905
8906 /* Inconsistent output/port/pipe state happens presumably due to
8907 * a bug in one of the get_hw_state functions. Or someplace else
8908 * in our code, like the register restore mess on resume. Clamp
8909 * things to off as a safer default. */
8910 list_for_each_entry(connector,
8911 &dev->mode_config.connector_list,
8912 base.head) {
8913 if (connector->encoder != encoder)
8914 continue;
8915
8916 intel_connector_break_all_links(connector);
8917 }
8918 }
8919 /* Enabled encoders without active connectors will be fixed in
8920 * the crtc fixup. */
8921}
8922
8923/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8924 * and i915 state tracking structures. */
8925void intel_modeset_setup_hw_state(struct drm_device *dev)
8926{
8927 struct drm_i915_private *dev_priv = dev->dev_private;
8928 enum pipe pipe;
8929 u32 tmp;
8930 struct intel_crtc *crtc;
8931 struct intel_encoder *encoder;
8932 struct intel_connector *connector;
8933
e28d54cb
PZ		 8934 if (IS_HASWELL(dev)) {
8935 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8936
8937 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8938 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8939 case TRANS_DDI_EDP_INPUT_A_ON:
8940 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8941 pipe = PIPE_A;
8942 break;
8943 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8944 pipe = PIPE_B;
8945 break;
8946 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8947 pipe = PIPE_C;
8948 break;
8949 }
8950
8951 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8952 crtc->cpu_transcoder = TRANSCODER_EDP;
8953
8954 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
8955 pipe_name(pipe));
8956 }
8957 }
8958
24929352
DV		 8959 for_each_pipe(pipe) {
8960 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8961
702e7a56 8962 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
24929352
DV		 8963 if (tmp & PIPECONF_ENABLE)
8964 crtc->active = true;
8965 else
8966 crtc->active = false;
8967
8968 crtc->base.enabled = crtc->active;
8969
8970 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8971 crtc->base.base.id,
8972 crtc->active ? "enabled" : "disabled");
8973 }
8974
6441ab5f
PZ		 8975 if (IS_HASWELL(dev))
8976 intel_ddi_setup_hw_pll_state(dev);
8977
24929352
DV		 8978 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8979 base.head) {
8980 pipe = 0;
8981
8982 if (encoder->get_hw_state(encoder, &pipe)) {
8983 encoder->base.crtc =
8984 dev_priv->pipe_to_crtc_mapping[pipe];
8985 } else {
8986 encoder->base.crtc = NULL;
8987 }
8988
8989 encoder->connectors_active = false;
8990 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8991 encoder->base.base.id,
8992 drm_get_encoder_name(&encoder->base),
8993 encoder->base.crtc ? "enabled" : "disabled",
8994 pipe);
8995 }
8996
8997 list_for_each_entry(connector, &dev->mode_config.connector_list,
8998 base.head) {
8999 if (connector->get_hw_state(connector)) {
9000 connector->base.dpms = DRM_MODE_DPMS_ON;
9001 connector->encoder->connectors_active = true;
9002 connector->base.encoder = &connector->encoder->base;
9003 } else {
9004 connector->base.dpms = DRM_MODE_DPMS_OFF;
9005 connector->base.encoder = NULL;
9006 }
9007 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9008 connector->base.base.id,
9009 drm_get_connector_name(&connector->base),
9010 connector->base.encoder ? "enabled" : "disabled");
9011 }
9012
9013 /* HW state is read out, now we need to sanitize this mess. */
9014 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9015 base.head) {
9016 intel_sanitize_encoder(encoder);
9017 }
9018
9019 for_each_pipe(pipe) {
9020 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9021 intel_sanitize_crtc(crtc);
9022 }
9a935856
DV		 9023
9024 intel_modeset_update_staged_output_state(dev);
8af6cf88
DV		 9025
9026 intel_modeset_check_state(dev);
2e938892
DV		 9027
9028 drm_mode_config_reset(dev);
24929352
DV		 9029}
9030
2c7111db
CW		 9031void intel_modeset_gem_init(struct drm_device *dev)
9032{
1833b134 9033 intel_modeset_init_hw(dev);
02e792fb
DV		 9034
9035 intel_setup_overlay(dev);
24929352
DV		 9036
9037 intel_modeset_setup_hw_state(dev);
79e53945
JB		 9038}
9039
9040void intel_modeset_cleanup(struct drm_device *dev)
9041{
652c393a
JB		 9042 struct drm_i915_private *dev_priv = dev->dev_private;
9043 struct drm_crtc *crtc;
9044 struct intel_crtc *intel_crtc;
9045
f87ea761 9046 drm_kms_helper_poll_fini(dev);
652c393a
JB		 9047 mutex_lock(&dev->struct_mutex);
9048
723bfd70
JB		 9049 intel_unregister_dsm_handler();
9050
9051
652c393a
JB		 9052 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9053 /* Skip inactive CRTCs */
9054 if (!crtc->fb)
9055 continue;
9056
9057 intel_crtc = to_intel_crtc(crtc);
3dec0095 9058 intel_increase_pllclock(crtc);
652c393a
JB		 9059 }
9060
973d04f9 9061 intel_disable_fbc(dev);
e70236a8 9062
8090c6b9 9063 intel_disable_gt_powersave(dev);
0cdab21f 9064
930ebb46
DV		 9065 ironlake_teardown_rc6(dev);
9066
57f350b6
JB		 9067 if (IS_VALLEYVIEW(dev))
9068 vlv_init_dpio(dev);
9069
69341a5e
KH		 9070 mutex_unlock(&dev->struct_mutex);
9071
6c0d9350
DV		 9072 /* Disable the irq before mode object teardown, for the irq might
9073 * enqueue unpin/hotplug work. */
9074 drm_irq_uninstall(dev);
9075 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 9076 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 9077
1630fe75
CW		 9078 /* flush any delayed tasks or pending work */
9079 flush_scheduled_work();
9080
79e53945
JB		 9081 drm_mode_config_cleanup(dev);
9082}
9083
f1c79df3
ZW		 9084/*
9085 * Return which encoder is currently attached for connector.
9086 */
df0e9248 9087struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9088{
df0e9248
CW		 9089 return &intel_attached_encoder(connector)->base;
9090}
f1c79df3 9091
df0e9248
CW		 9092void intel_connector_attach_encoder(struct intel_connector *connector,
9093 struct intel_encoder *encoder)
9094{
9095 connector->encoder = encoder;
9096 drm_mode_connector_attach_encoder(&connector->base,
9097 &encoder->base);
79e53945 9098}
28d52043
DA		 9099
9100/*
9101 * set vga decode state - true == enable VGA decode
9102 */
9103int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9104{
9105 struct drm_i915_private *dev_priv = dev->dev_private;
9106 u16 gmch_ctrl;
9107
9108 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9109 if (state)
9110 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9111 else
9112 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9113 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9114 return 0;
9115}
c4a1d9e4
CW		 9116
9117#ifdef CONFIG_DEBUG_FS
9118#include <linux/seq_file.h>
9119
9120struct intel_display_error_state {
9121 struct intel_cursor_error_state {
9122 u32 control;
9123 u32 position;
9124 u32 base;
9125 u32 size;
52331309 9126 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9127
9128 struct intel_pipe_error_state {
9129 u32 conf;
9130 u32 source;
9131
9132 u32 htotal;
9133 u32 hblank;
9134 u32 hsync;
9135 u32 vtotal;
9136 u32 vblank;
9137 u32 vsync;
52331309 9138 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9139
9140 struct intel_plane_error_state {
9141 u32 control;
9142 u32 stride;
9143 u32 size;
9144 u32 pos;
9145 u32 addr;
9146 u32 surface;
9147 u32 tile_offset;
52331309 9148 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9149};
9150
9151struct intel_display_error_state *
9152intel_display_capture_error_state(struct drm_device *dev)
9153{
0206e353 9154 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9155 struct intel_display_error_state *error;
702e7a56 9156 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9157 int i;
9158
9159 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9160 if (error == NULL)
9161 return NULL;
9162
52331309 9163 for_each_pipe(i) {
702e7a56
PZ		 9164 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9165
c4a1d9e4
CW		 9166 error->cursor[i].control = I915_READ(CURCNTR(i));
9167 error->cursor[i].position = I915_READ(CURPOS(i));
9168 error->cursor[i].base = I915_READ(CURBASE(i));
9169
9170 error->plane[i].control = I915_READ(DSPCNTR(i));
9171 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9172 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 9173 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 9174 error->plane[i].addr = I915_READ(DSPADDR(i));
9175 if (INTEL_INFO(dev)->gen >= 4) {
9176 error->plane[i].surface = I915_READ(DSPSURF(i));
9177 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9178 }
9179
702e7a56 9180 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9181 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9182 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9183 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9184 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9185 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9186 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9187 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9188 }
9189
9190 return error;
9191}
9192
9193void
9194intel_display_print_error_state(struct seq_file *m,
9195 struct drm_device *dev,
9196 struct intel_display_error_state *error)
9197{
52331309 9198 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 9199 int i;
9200
52331309
DL		 9201 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9202 for_each_pipe(i) {
c4a1d9e4
CW		 9203 seq_printf(m, "Pipe [%d]:\n", i);
9204 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9205 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9206 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9207 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9208 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9209 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9210 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9211 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9212
9213 seq_printf(m, "Plane [%d]:\n", i);
9214 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9215 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9216 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9217 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9218 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9219 if (INTEL_INFO(dev)->gen >= 4) {
9220 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9221 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9222 }
9223
9224 seq_printf(m, "Cursor [%d]:\n", i);
9225 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9226 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9227 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9228 }
9229}
9230#endif
Linux kernel - Deliverables
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