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drm/i915: move detaching scalers to begin_crtc_commit, v2.
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c 48/* Primary plane formats for gen <= 3 */
568db4f2 49static const uint32_t i8xx_primary_formats[] = {
67fe7dc5
DL		 50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
465c120c 52 DRM_FORMAT_XRGB1555,
67fe7dc5 53 DRM_FORMAT_XRGB8888,
465c120c
MR		 54};
55
56/* Primary plane formats for gen >= 4 */
568db4f2 57static const uint32_t i965_primary_formats[] = {
6c0fd451
DL		 58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64};
65
66static const uint32_t skl_primary_formats[] = {
67fe7dc5
DL		 67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
465c120c 70 DRM_FORMAT_XBGR8888,
67fe7dc5 71 DRM_FORMAT_ARGB8888,
465c120c
MR		 72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
465c120c 74 DRM_FORMAT_XBGR2101010,
465c120c
MR		 75};
76
3d7d6510
MR		 77/* Cursor formats */
78static const uint32_t intel_cursor_formats[] = {
79 DRM_FORMAT_ARGB8888,
80};
81
6b383a7f 82static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 83
f1f644dc 84static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 85 struct intel_crtc_state *pipe_config);
18442d08 86static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 87 struct intel_crtc_state *pipe_config);
f1f644dc 88
568c634a 89static int intel_set_mode(struct drm_atomic_state *state);
eb1bfe80
JB		 90static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj);
5b18e57c
DV		 94static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
95static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 96static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 97 struct intel_link_m_n *m_n,
98 struct intel_link_m_n *m2_n2);
29407aab 99static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 100static void haswell_set_pipeconf(struct drm_crtc *crtc);
101static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 102static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 103 const struct intel_crtc_state *pipe_config);
d288f65f 104static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 105 const struct intel_crtc_state *pipe_config);
ea2c67bb
MR		 106static void intel_begin_crtc_commit(struct drm_crtc *crtc);
107static void intel_finish_crtc_commit(struct drm_crtc *crtc);
549e2bfb
CK		 108static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
109 struct intel_crtc_state *crtc_state);
5ab7b0b7
ID		 110static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
111 int num_connectors);
ce22dba9
ML		 112static void intel_crtc_enable_planes(struct drm_crtc *crtc);
113static void intel_crtc_disable_planes(struct drm_crtc *crtc);
e7457a9a 114
0e32b39c
DA		 115static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
116{
117 if (!connector->mst_port)
118 return connector->encoder;
119 else
120 return &connector->mst_port->mst_encoders[pipe]->base;
121}
122
79e53945 123typedef struct {
0206e353 124 int min, max;
79e53945
JB		 125} intel_range_t;
126
127typedef struct {
0206e353
AJ		 128 int dot_limit;
129 int p2_slow, p2_fast;
79e53945
JB		 130} intel_p2_t;
131
d4906093
ML		 132typedef struct intel_limit intel_limit_t;
133struct intel_limit {
0206e353
AJ		 134 intel_range_t dot, vco, n, m, m1, m2, p, p1;
135 intel_p2_t p2;
d4906093 136};
79e53945 137
d2acd215
DV		 138int
139intel_pch_rawclk(struct drm_device *dev)
140{
141 struct drm_i915_private *dev_priv = dev->dev_private;
142
143 WARN_ON(!HAS_PCH_SPLIT(dev));
144
145 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
146}
147
021357ac
CW		 148static inline u32 /* units of 100MHz */
149intel_fdi_link_freq(struct drm_device *dev)
150{
8b99e68c
CW		 151 if (IS_GEN5(dev)) {
152 struct drm_i915_private *dev_priv = dev->dev_private;
153 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
154 } else
155 return 27;
021357ac
CW		 156}
157
5d536e28 158static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 159 .dot = { .min = 25000, .max = 350000 },
9c333719 160 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 161 .n = { .min = 2, .max = 16 },
0206e353
AJ		 162 .m = { .min = 96, .max = 140 },
163 .m1 = { .min = 18, .max = 26 },
164 .m2 = { .min = 6, .max = 16 },
165 .p = { .min = 4, .max = 128 },
166 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 167 .p2 = { .dot_limit = 165000,
168 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 169};
170
5d536e28
DV		 171static const intel_limit_t intel_limits_i8xx_dvo = {
172 .dot = { .min = 25000, .max = 350000 },
9c333719 173 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 174 .n = { .min = 2, .max = 16 },
5d536e28
DV		 175 .m = { .min = 96, .max = 140 },
176 .m1 = { .min = 18, .max = 26 },
177 .m2 = { .min = 6, .max = 16 },
178 .p = { .min = 4, .max = 128 },
179 .p1 = { .min = 2, .max = 33 },
180 .p2 = { .dot_limit = 165000,
181 .p2_slow = 4, .p2_fast = 4 },
182};
183
e4b36699 184static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 185 .dot = { .min = 25000, .max = 350000 },
9c333719 186 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 187 .n = { .min = 2, .max = 16 },
0206e353
AJ		 188 .m = { .min = 96, .max = 140 },
189 .m1 = { .min = 18, .max = 26 },
190 .m2 = { .min = 6, .max = 16 },
191 .p = { .min = 4, .max = 128 },
192 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 193 .p2 = { .dot_limit = 165000,
194 .p2_slow = 14, .p2_fast = 7 },
e4b36699 195};
273e27ca 196
e4b36699 197static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 198 .dot = { .min = 20000, .max = 400000 },
199 .vco = { .min = 1400000, .max = 2800000 },
200 .n = { .min = 1, .max = 6 },
201 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 202 .m1 = { .min = 8, .max = 18 },
203 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 204 .p = { .min = 5, .max = 80 },
205 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 206 .p2 = { .dot_limit = 200000,
207 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 208};
209
210static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 211 .dot = { .min = 20000, .max = 400000 },
212 .vco = { .min = 1400000, .max = 2800000 },
213 .n = { .min = 1, .max = 6 },
214 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 215 .m1 = { .min = 8, .max = 18 },
216 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 217 .p = { .min = 7, .max = 98 },
218 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 219 .p2 = { .dot_limit = 112000,
220 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 221};
222
273e27ca 223
e4b36699 224static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 225 .dot = { .min = 25000, .max = 270000 },
226 .vco = { .min = 1750000, .max = 3500000},
227 .n = { .min = 1, .max = 4 },
228 .m = { .min = 104, .max = 138 },
229 .m1 = { .min = 17, .max = 23 },
230 .m2 = { .min = 5, .max = 11 },
231 .p = { .min = 10, .max = 30 },
232 .p1 = { .min = 1, .max = 3},
233 .p2 = { .dot_limit = 270000,
234 .p2_slow = 10,
235 .p2_fast = 10
044c7c41 236 },
e4b36699
KP		 237};
238
239static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 240 .dot = { .min = 22000, .max = 400000 },
241 .vco = { .min = 1750000, .max = 3500000},
242 .n = { .min = 1, .max = 4 },
243 .m = { .min = 104, .max = 138 },
244 .m1 = { .min = 16, .max = 23 },
245 .m2 = { .min = 5, .max = 11 },
246 .p = { .min = 5, .max = 80 },
247 .p1 = { .min = 1, .max = 8},
248 .p2 = { .dot_limit = 165000,
249 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 250};
251
252static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 253 .dot = { .min = 20000, .max = 115000 },
254 .vco = { .min = 1750000, .max = 3500000 },
255 .n = { .min = 1, .max = 3 },
256 .m = { .min = 104, .max = 138 },
257 .m1 = { .min = 17, .max = 23 },
258 .m2 = { .min = 5, .max = 11 },
259 .p = { .min = 28, .max = 112 },
260 .p1 = { .min = 2, .max = 8 },
261 .p2 = { .dot_limit = 0,
262 .p2_slow = 14, .p2_fast = 14
044c7c41 263 },
e4b36699
KP		 264};
265
266static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 267 .dot = { .min = 80000, .max = 224000 },
268 .vco = { .min = 1750000, .max = 3500000 },
269 .n = { .min = 1, .max = 3 },
270 .m = { .min = 104, .max = 138 },
271 .m1 = { .min = 17, .max = 23 },
272 .m2 = { .min = 5, .max = 11 },
273 .p = { .min = 14, .max = 42 },
274 .p1 = { .min = 2, .max = 6 },
275 .p2 = { .dot_limit = 0,
276 .p2_slow = 7, .p2_fast = 7
044c7c41 277 },
e4b36699
KP		 278};
279
f2b115e6 280static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 281 .dot = { .min = 20000, .max = 400000},
282 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 283 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 284 .n = { .min = 3, .max = 6 },
285 .m = { .min = 2, .max = 256 },
273e27ca 286 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 287 .m1 = { .min = 0, .max = 0 },
288 .m2 = { .min = 0, .max = 254 },
289 .p = { .min = 5, .max = 80 },
290 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 291 .p2 = { .dot_limit = 200000,
292 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 293};
294
f2b115e6 295static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 296 .dot = { .min = 20000, .max = 400000 },
297 .vco = { .min = 1700000, .max = 3500000 },
298 .n = { .min = 3, .max = 6 },
299 .m = { .min = 2, .max = 256 },
300 .m1 = { .min = 0, .max = 0 },
301 .m2 = { .min = 0, .max = 254 },
302 .p = { .min = 7, .max = 112 },
303 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 304 .p2 = { .dot_limit = 112000,
305 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 306};
307
273e27ca
EA		 308/* Ironlake / Sandybridge
309 *
310 * We calculate clock using (register_value + 2) for N/M1/M2, so here
311 * the range value for them is (actual_value - 2).
312 */
b91ad0ec 313static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 314 .dot = { .min = 25000, .max = 350000 },
315 .vco = { .min = 1760000, .max = 3510000 },
316 .n = { .min = 1, .max = 5 },
317 .m = { .min = 79, .max = 127 },
318 .m1 = { .min = 12, .max = 22 },
319 .m2 = { .min = 5, .max = 9 },
320 .p = { .min = 5, .max = 80 },
321 .p1 = { .min = 1, .max = 8 },
322 .p2 = { .dot_limit = 225000,
323 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 324};
325
b91ad0ec 326static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 327 .dot = { .min = 25000, .max = 350000 },
328 .vco = { .min = 1760000, .max = 3510000 },
329 .n = { .min = 1, .max = 3 },
330 .m = { .min = 79, .max = 118 },
331 .m1 = { .min = 12, .max = 22 },
332 .m2 = { .min = 5, .max = 9 },
333 .p = { .min = 28, .max = 112 },
334 .p1 = { .min = 2, .max = 8 },
335 .p2 = { .dot_limit = 225000,
336 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 337};
338
339static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 340 .dot = { .min = 25000, .max = 350000 },
341 .vco = { .min = 1760000, .max = 3510000 },
342 .n = { .min = 1, .max = 3 },
343 .m = { .min = 79, .max = 127 },
344 .m1 = { .min = 12, .max = 22 },
345 .m2 = { .min = 5, .max = 9 },
346 .p = { .min = 14, .max = 56 },
347 .p1 = { .min = 2, .max = 8 },
348 .p2 = { .dot_limit = 225000,
349 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 350};
351
273e27ca 352/* LVDS 100mhz refclk limits. */
b91ad0ec 353static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 354 .dot = { .min = 25000, .max = 350000 },
355 .vco = { .min = 1760000, .max = 3510000 },
356 .n = { .min = 1, .max = 2 },
357 .m = { .min = 79, .max = 126 },
358 .m1 = { .min = 12, .max = 22 },
359 .m2 = { .min = 5, .max = 9 },
360 .p = { .min = 28, .max = 112 },
0206e353 361 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 362 .p2 = { .dot_limit = 225000,
363 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 364};
365
366static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 367 .dot = { .min = 25000, .max = 350000 },
368 .vco = { .min = 1760000, .max = 3510000 },
369 .n = { .min = 1, .max = 3 },
370 .m = { .min = 79, .max = 126 },
371 .m1 = { .min = 12, .max = 22 },
372 .m2 = { .min = 5, .max = 9 },
373 .p = { .min = 14, .max = 42 },
0206e353 374 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 375 .p2 = { .dot_limit = 225000,
376 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 377};
378
dc730512 379static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 380 /*
381 * These are the data rate limits (measured in fast clocks)
382 * since those are the strictest limits we have. The fast
383 * clock and actual rate limits are more relaxed, so checking
384 * them would make no difference.
385 */
386 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 387 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 388 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 389 .m1 = { .min = 2, .max = 3 },
390 .m2 = { .min = 11, .max = 156 },
b99ab663 391 .p1 = { .min = 2, .max = 3 },
5fdc9c49 392 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 393};
394
ef9348c8
CML		 395static const intel_limit_t intel_limits_chv = {
396 /*
397 * These are the data rate limits (measured in fast clocks)
398 * since those are the strictest limits we have. The fast
399 * clock and actual rate limits are more relaxed, so checking
400 * them would make no difference.
401 */
402 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 403 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 404 .n = { .min = 1, .max = 1 },
405 .m1 = { .min = 2, .max = 2 },
406 .m2 = { .min = 24 << 22, .max = 175 << 22 },
407 .p1 = { .min = 2, .max = 4 },
408 .p2 = { .p2_slow = 1, .p2_fast = 14 },
409};
410
5ab7b0b7
ID		 411static const intel_limit_t intel_limits_bxt = {
412 /* FIXME: find real dot limits */
413 .dot = { .min = 0, .max = INT_MAX },
414 .vco = { .min = 4800000, .max = 6480000 },
415 .n = { .min = 1, .max = 1 },
416 .m1 = { .min = 2, .max = 2 },
417 /* FIXME: find real m2 limits */
418 .m2 = { .min = 2 << 22, .max = 255 << 22 },
419 .p1 = { .min = 2, .max = 4 },
420 .p2 = { .p2_slow = 1, .p2_fast = 20 },
421};
422
6b4bf1c4
VS		 423static void vlv_clock(int refclk, intel_clock_t *clock)
424{
425 clock->m = clock->m1 * clock->m2;
426 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 427 if (WARN_ON(clock->n == 0 || clock->p == 0))
428 return;
fb03ac01
VS		 429 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
430 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
6b4bf1c4
VS		 431}
432
cdba954e
ACO		 433static bool
434needs_modeset(struct drm_crtc_state *state)
435{
436 return state->mode_changed || state->active_changed;
437}
438
e0638cdf
PZ		 439/**
440 * Returns whether any output on the specified pipe is of the specified type
441 */
4093561b 442bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 443{
409ee761 444 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 445 struct intel_encoder *encoder;
446
409ee761 447 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 448 if (encoder->type == type)
449 return true;
450
451 return false;
452}
453
d0737e1d
ACO		 454/**
455 * Returns whether any output on the specified pipe will have the specified
456 * type after a staged modeset is complete, i.e., the same as
457 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
458 * encoder->crtc.
459 */
a93e255f
ACO		 460static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
461 int type)
d0737e1d 462{
a93e255f 463 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 464 struct drm_connector *connector;
a93e255f 465 struct drm_connector_state *connector_state;
d0737e1d 466 struct intel_encoder *encoder;
a93e255f
ACO		 467 int i, num_connectors = 0;
468
da3ced29 469 for_each_connector_in_state(state, connector, connector_state, i) {
a93e255f
ACO		 470 if (connector_state->crtc != crtc_state->base.crtc)
471 continue;
472
473 num_connectors++;
d0737e1d 474
a93e255f
ACO		 475 encoder = to_intel_encoder(connector_state->best_encoder);
476 if (encoder->type == type)
d0737e1d 477 return true;
a93e255f
ACO		 478 }
479
480 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 481
482 return false;
483}
484
a93e255f
ACO		 485static const intel_limit_t *
486intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 487{
a93e255f 488 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 489 const intel_limit_t *limit;
b91ad0ec 490
a93e255f 491 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 492 if (intel_is_dual_link_lvds(dev)) {
1b894b59 493 if (refclk == 100000)
b91ad0ec
ZW		 494 limit = &intel_limits_ironlake_dual_lvds_100m;
495 else
496 limit = &intel_limits_ironlake_dual_lvds;
497 } else {
1b894b59 498 if (refclk == 100000)
b91ad0ec
ZW		 499 limit = &intel_limits_ironlake_single_lvds_100m;
500 else
501 limit = &intel_limits_ironlake_single_lvds;
502 }
c6bb3538 503 } else
b91ad0ec 504 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 505
506 return limit;
507}
508
a93e255f
ACO		 509static const intel_limit_t *
510intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 511{
a93e255f 512 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 513 const intel_limit_t *limit;
514
a93e255f 515 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 516 if (intel_is_dual_link_lvds(dev))
e4b36699 517 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 518 else
e4b36699 519 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 520 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
521 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 522 limit = &intel_limits_g4x_hdmi;
a93e255f 523 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 524 limit = &intel_limits_g4x_sdvo;
044c7c41 525 } else /* The option is for other outputs */
e4b36699 526 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 527
528 return limit;
529}
530
a93e255f
ACO		 531static const intel_limit_t *
532intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 533{
a93e255f 534 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 535 const intel_limit_t *limit;
536
5ab7b0b7
ID		 537 if (IS_BROXTON(dev))
538 limit = &intel_limits_bxt;
539 else if (HAS_PCH_SPLIT(dev))
a93e255f 540 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 541 else if (IS_G4X(dev)) {
a93e255f 542 limit = intel_g4x_limit(crtc_state);
f2b115e6 543 } else if (IS_PINEVIEW(dev)) {
a93e255f 544 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 545 limit = &intel_limits_pineview_lvds;
2177832f 546 else
f2b115e6 547 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 548 } else if (IS_CHERRYVIEW(dev)) {
549 limit = &intel_limits_chv;
a0c4da24 550 } else if (IS_VALLEYVIEW(dev)) {
dc730512 551 limit = &intel_limits_vlv;
a6c45cf0 552 } else if (!IS_GEN2(dev)) {
a93e255f 553 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 554 limit = &intel_limits_i9xx_lvds;
555 else
556 limit = &intel_limits_i9xx_sdvo;
79e53945 557 } else {
a93e255f 558 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 559 limit = &intel_limits_i8xx_lvds;
a93e255f 560 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 561 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 562 else
563 limit = &intel_limits_i8xx_dac;
79e53945
JB		 564 }
565 return limit;
566}
567
f2b115e6
AJ		 568/* m1 is reserved as 0 in Pineview, n is a ring counter */
569static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 570{
2177832f
SL		 571 clock->m = clock->m2 + 2;
572 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 573 if (WARN_ON(clock->n == 0 || clock->p == 0))
574 return;
fb03ac01
VS		 575 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
576 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
2177832f
SL		 577}
578
7429e9d4
DV		 579static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
580{
581 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
582}
583
ac58c3f0 584static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 585{
7429e9d4 586 clock->m = i9xx_dpll_compute_m(clock);
79e53945 587 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 588 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
589 return;
fb03ac01
VS		 590 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
591 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
79e53945
JB		 592}
593
ef9348c8
CML		 594static void chv_clock(int refclk, intel_clock_t *clock)
595{
596 clock->m = clock->m1 * clock->m2;
597 clock->p = clock->p1 * clock->p2;
598 if (WARN_ON(clock->n == 0 || clock->p == 0))
599 return;
600 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
601 clock->n << 22);
602 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
603}
604
7c04d1d9 605#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 606/**
607 * Returns whether the given set of divisors are valid for a given refclk with
608 * the given connectors.
609 */
610
1b894b59
CW		 611static bool intel_PLL_is_valid(struct drm_device *dev,
612 const intel_limit_t *limit,
613 const intel_clock_t *clock)
79e53945 614{
f01b7962
VS		 615 if (clock->n < limit->n.min || limit->n.max < clock->n)
616 INTELPllInvalid("n out of range\n");
79e53945 617 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 618 INTELPllInvalid("p1 out of range\n");
79e53945 619 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 620 INTELPllInvalid("m2 out of range\n");
79e53945 621 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 622 INTELPllInvalid("m1 out of range\n");
f01b7962 623
5ab7b0b7 624 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
f01b7962
VS		 625 if (clock->m1 <= clock->m2)
626 INTELPllInvalid("m1 <= m2\n");
627
5ab7b0b7 628 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
f01b7962
VS		 629 if (clock->p < limit->p.min || limit->p.max < clock->p)
630 INTELPllInvalid("p out of range\n");
631 if (clock->m < limit->m.min || limit->m.max < clock->m)
632 INTELPllInvalid("m out of range\n");
633 }
634
79e53945 635 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 636 INTELPllInvalid("vco out of range\n");
79e53945
JB		 637 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
638 * connector, etc., rather than just a single range.
639 */
640 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 641 INTELPllInvalid("dot out of range\n");
79e53945
JB		 642
643 return true;
644}
645
d4906093 646static bool
a93e255f
ACO		 647i9xx_find_best_dpll(const intel_limit_t *limit,
648 struct intel_crtc_state *crtc_state,
cec2f356
SP		 649 int target, int refclk, intel_clock_t *match_clock,
650 intel_clock_t *best_clock)
79e53945 651{
a93e255f 652 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 653 struct drm_device *dev = crtc->base.dev;
79e53945 654 intel_clock_t clock;
79e53945
JB		 655 int err = target;
656
a93e255f 657 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 658 /*
a210b028
DV		 659 * For LVDS just rely on its current settings for dual-channel.
660 * We haven't figured out how to reliably set up different
661 * single/dual channel state, if we even can.
79e53945 662 */
1974cad0 663 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 664 clock.p2 = limit->p2.p2_fast;
665 else
666 clock.p2 = limit->p2.p2_slow;
667 } else {
668 if (target < limit->p2.dot_limit)
669 clock.p2 = limit->p2.p2_slow;
670 else
671 clock.p2 = limit->p2.p2_fast;
672 }
673
0206e353 674 memset(best_clock, 0, sizeof(*best_clock));
79e53945 675
42158660
ZY		 676 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
677 clock.m1++) {
678 for (clock.m2 = limit->m2.min;
679 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 680 if (clock.m2 >= clock.m1)
42158660
ZY		 681 break;
682 for (clock.n = limit->n.min;
683 clock.n <= limit->n.max; clock.n++) {
684 for (clock.p1 = limit->p1.min;
685 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 686 int this_err;
687
ac58c3f0
DV		 688 i9xx_clock(refclk, &clock);
689 if (!intel_PLL_is_valid(dev, limit,
690 &clock))
691 continue;
692 if (match_clock &&
693 clock.p != match_clock->p)
694 continue;
695
696 this_err = abs(clock.dot - target);
697 if (this_err < err) {
698 *best_clock = clock;
699 err = this_err;
700 }
701 }
702 }
703 }
704 }
705
706 return (err != target);
707}
708
709static bool
a93e255f
ACO		 710pnv_find_best_dpll(const intel_limit_t *limit,
711 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 712 int target, int refclk, intel_clock_t *match_clock,
713 intel_clock_t *best_clock)
79e53945 714{
a93e255f 715 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 716 struct drm_device *dev = crtc->base.dev;
79e53945 717 intel_clock_t clock;
79e53945
JB		 718 int err = target;
719
a93e255f 720 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 721 /*
a210b028
DV		 722 * For LVDS just rely on its current settings for dual-channel.
723 * We haven't figured out how to reliably set up different
724 * single/dual channel state, if we even can.
79e53945 725 */
1974cad0 726 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 727 clock.p2 = limit->p2.p2_fast;
728 else
729 clock.p2 = limit->p2.p2_slow;
730 } else {
731 if (target < limit->p2.dot_limit)
732 clock.p2 = limit->p2.p2_slow;
733 else
734 clock.p2 = limit->p2.p2_fast;
735 }
736
0206e353 737 memset(best_clock, 0, sizeof(*best_clock));
79e53945 738
42158660
ZY		 739 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
740 clock.m1++) {
741 for (clock.m2 = limit->m2.min;
742 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 743 for (clock.n = limit->n.min;
744 clock.n <= limit->n.max; clock.n++) {
745 for (clock.p1 = limit->p1.min;
746 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 747 int this_err;
748
ac58c3f0 749 pineview_clock(refclk, &clock);
1b894b59
CW		 750 if (!intel_PLL_is_valid(dev, limit,
751 &clock))
79e53945 752 continue;
cec2f356
SP		 753 if (match_clock &&
754 clock.p != match_clock->p)
755 continue;
79e53945
JB		 756
757 this_err = abs(clock.dot - target);
758 if (this_err < err) {
759 *best_clock = clock;
760 err = this_err;
761 }
762 }
763 }
764 }
765 }
766
767 return (err != target);
768}
769
d4906093 770static bool
a93e255f
ACO		 771g4x_find_best_dpll(const intel_limit_t *limit,
772 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 773 int target, int refclk, intel_clock_t *match_clock,
774 intel_clock_t *best_clock)
d4906093 775{
a93e255f 776 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 777 struct drm_device *dev = crtc->base.dev;
d4906093
ML		 778 intel_clock_t clock;
779 int max_n;
780 bool found;
6ba770dc
AJ		 781 /* approximately equals target * 0.00585 */
782 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 783 found = false;
784
a93e255f 785 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 786 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 787 clock.p2 = limit->p2.p2_fast;
788 else
789 clock.p2 = limit->p2.p2_slow;
790 } else {
791 if (target < limit->p2.dot_limit)
792 clock.p2 = limit->p2.p2_slow;
793 else
794 clock.p2 = limit->p2.p2_fast;
795 }
796
797 memset(best_clock, 0, sizeof(*best_clock));
798 max_n = limit->n.max;
f77f13e2 799 /* based on hardware requirement, prefer smaller n to precision */
d4906093 800 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 801 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 802 for (clock.m1 = limit->m1.max;
803 clock.m1 >= limit->m1.min; clock.m1--) {
804 for (clock.m2 = limit->m2.max;
805 clock.m2 >= limit->m2.min; clock.m2--) {
806 for (clock.p1 = limit->p1.max;
807 clock.p1 >= limit->p1.min; clock.p1--) {
808 int this_err;
809
ac58c3f0 810 i9xx_clock(refclk, &clock);
1b894b59
CW		 811 if (!intel_PLL_is_valid(dev, limit,
812 &clock))
d4906093 813 continue;
1b894b59
CW		 814
815 this_err = abs(clock.dot - target);
d4906093
ML		 816 if (this_err < err_most) {
817 *best_clock = clock;
818 err_most = this_err;
819 max_n = clock.n;
820 found = true;
821 }
822 }
823 }
824 }
825 }
2c07245f
ZW		 826 return found;
827}
828
d5dd62bd
ID		 829/*
830 * Check if the calculated PLL configuration is more optimal compared to the
831 * best configuration and error found so far. Return the calculated error.
832 */
833static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
834 const intel_clock_t *calculated_clock,
835 const intel_clock_t *best_clock,
836 unsigned int best_error_ppm,
837 unsigned int *error_ppm)
838{
9ca3ba01
ID		 839 /*
840 * For CHV ignore the error and consider only the P value.
841 * Prefer a bigger P value based on HW requirements.
842 */
843 if (IS_CHERRYVIEW(dev)) {
844 *error_ppm = 0;
845
846 return calculated_clock->p > best_clock->p;
847 }
848
24be4e46
ID		 849 if (WARN_ON_ONCE(!target_freq))
850 return false;
851
d5dd62bd
ID		 852 *error_ppm = div_u64(1000000ULL *
853 abs(target_freq - calculated_clock->dot),
854 target_freq);
855 /*
856 * Prefer a better P value over a better (smaller) error if the error
857 * is small. Ensure this preference for future configurations too by
858 * setting the error to 0.
859 */
860 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
861 *error_ppm = 0;
862
863 return true;
864 }
865
866 return *error_ppm + 10 < best_error_ppm;
867}
868
a0c4da24 869static bool
a93e255f
ACO		 870vlv_find_best_dpll(const intel_limit_t *limit,
871 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 872 int target, int refclk, intel_clock_t *match_clock,
873 intel_clock_t *best_clock)
a0c4da24 874{
a93e255f 875 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 876 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 877 intel_clock_t clock;
69e4f900 878 unsigned int bestppm = 1000000;
27e639bf
VS		 879 /* min update 19.2 MHz */
880 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 881 bool found = false;
a0c4da24 882
6b4bf1c4
VS		 883 target *= 5; /* fast clock */
884
885 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 886
887 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 888 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 889 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 890 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 891 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 892 clock.p = clock.p1 * clock.p2;
a0c4da24 893 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 894 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 895 unsigned int ppm;
69e4f900 896
6b4bf1c4
VS		 897 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
898 refclk * clock.m1);
899
900 vlv_clock(refclk, &clock);
43b0ac53 901
f01b7962
VS		 902 if (!intel_PLL_is_valid(dev, limit,
903 &clock))
43b0ac53
VS		 904 continue;
905
d5dd62bd
ID		 906 if (!vlv_PLL_is_optimal(dev, target,
907 &clock,
908 best_clock,
909 bestppm, &ppm))
910 continue;
6b4bf1c4 911
d5dd62bd
ID		 912 *best_clock = clock;
913 bestppm = ppm;
914 found = true;
a0c4da24
JB		 915 }
916 }
917 }
918 }
a0c4da24 919
49e497ef 920 return found;
a0c4da24 921}
a4fc5ed6 922
ef9348c8 923static bool
a93e255f
ACO		 924chv_find_best_dpll(const intel_limit_t *limit,
925 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 926 int target, int refclk, intel_clock_t *match_clock,
927 intel_clock_t *best_clock)
928{
a93e255f 929 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 930 struct drm_device *dev = crtc->base.dev;
9ca3ba01 931 unsigned int best_error_ppm;
ef9348c8
CML		 932 intel_clock_t clock;
933 uint64_t m2;
934 int found = false;
935
936 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 937 best_error_ppm = 1000000;
ef9348c8
CML		 938
939 /*
940 * Based on hardware doc, the n always set to 1, and m1 always
941 * set to 2. If requires to support 200Mhz refclk, we need to
942 * revisit this because n may not 1 anymore.
943 */
944 clock.n = 1, clock.m1 = 2;
945 target *= 5; /* fast clock */
946
947 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
948 for (clock.p2 = limit->p2.p2_fast;
949 clock.p2 >= limit->p2.p2_slow;
950 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 951 unsigned int error_ppm;
ef9348c8
CML		 952
953 clock.p = clock.p1 * clock.p2;
954
955 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
956 clock.n) << 22, refclk * clock.m1);
957
958 if (m2 > INT_MAX/clock.m1)
959 continue;
960
961 clock.m2 = m2;
962
963 chv_clock(refclk, &clock);
964
965 if (!intel_PLL_is_valid(dev, limit, &clock))
966 continue;
967
9ca3ba01
ID		 968 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
969 best_error_ppm, &error_ppm))
970 continue;
971
972 *best_clock = clock;
973 best_error_ppm = error_ppm;
974 found = true;
ef9348c8
CML		 975 }
976 }
977
978 return found;
979}
980
5ab7b0b7
ID		 981bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
982 intel_clock_t *best_clock)
983{
984 int refclk = i9xx_get_refclk(crtc_state, 0);
985
986 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
987 target_clock, refclk, NULL, best_clock);
988}
989
20ddf665
VS		 990bool intel_crtc_active(struct drm_crtc *crtc)
991{
992 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
993
994 /* Be paranoid as we can arrive here with only partial
995 * state retrieved from the hardware during setup.
996 *
241bfc38 997 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 998 * as Haswell has gained clock readout/fastboot support.
999 *
66e514c1 1000 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 1001 * properly reconstruct framebuffers.
c3d1f436
MR		 1002 *
1003 * FIXME: The intel_crtc->active here should be switched to
1004 * crtc->state->active once we have proper CRTC states wired up
1005 * for atomic.
20ddf665 1006 */
c3d1f436 1007 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 1008 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 1009}
1010
a5c961d1
PZ		 1011enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1012 enum pipe pipe)
1013{
1014 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1015 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1016
6e3c9717 1017 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 1018}
1019
fbf49ea2
VS		 1020static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1021{
1022 struct drm_i915_private *dev_priv = dev->dev_private;
1023 u32 reg = PIPEDSL(pipe);
1024 u32 line1, line2;
1025 u32 line_mask;
1026
1027 if (IS_GEN2(dev))
1028 line_mask = DSL_LINEMASK_GEN2;
1029 else
1030 line_mask = DSL_LINEMASK_GEN3;
1031
1032 line1 = I915_READ(reg) & line_mask;
1033 mdelay(5);
1034 line2 = I915_READ(reg) & line_mask;
1035
1036 return line1 == line2;
1037}
1038
ab7ad7f6
KP		 1039/*
1040 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1041 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1042 *
1043 * After disabling a pipe, we can't wait for vblank in the usual way,
1044 * spinning on the vblank interrupt status bit, since we won't actually
1045 * see an interrupt when the pipe is disabled.
1046 *
ab7ad7f6
KP		 1047 * On Gen4 and above:
1048 * wait for the pipe register state bit to turn off
1049 *
1050 * Otherwise:
1051 * wait for the display line value to settle (it usually
1052 * ends up stopping at the start of the next frame).
58e10eb9 1053 *
9d0498a2 1054 */
575f7ab7 1055static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1056{
575f7ab7 1057 struct drm_device *dev = crtc->base.dev;
9d0498a2 1058 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1059 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1060 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1061
1062 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1063 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1064
1065 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1066 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1067 100))
284637d9 1068 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1069 } else {
ab7ad7f6 1070 /* Wait for the display line to settle */
fbf49ea2 1071 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1072 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1073 }
79e53945
JB		 1074}
1075
b0ea7d37
DL		 1076/*
1077 * ibx_digital_port_connected - is the specified port connected?
1078 * @dev_priv: i915 private structure
1079 * @port: the port to test
1080 *
1081 * Returns true if @port is connected, false otherwise.
1082 */
1083bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1084 struct intel_digital_port *port)
1085{
1086 u32 bit;
1087
c36346e3 1088 if (HAS_PCH_IBX(dev_priv->dev)) {
eba905b2 1089 switch (port->port) {
c36346e3
DL		 1090 case PORT_B:
1091 bit = SDE_PORTB_HOTPLUG;
1092 break;
1093 case PORT_C:
1094 bit = SDE_PORTC_HOTPLUG;
1095 break;
1096 case PORT_D:
1097 bit = SDE_PORTD_HOTPLUG;
1098 break;
1099 default:
1100 return true;
1101 }
1102 } else {
eba905b2 1103 switch (port->port) {
c36346e3
DL		 1104 case PORT_B:
1105 bit = SDE_PORTB_HOTPLUG_CPT;
1106 break;
1107 case PORT_C:
1108 bit = SDE_PORTC_HOTPLUG_CPT;
1109 break;
1110 case PORT_D:
1111 bit = SDE_PORTD_HOTPLUG_CPT;
1112 break;
1113 default:
1114 return true;
1115 }
b0ea7d37
DL		 1116 }
1117
1118 return I915_READ(SDEISR) & bit;
1119}
1120
b24e7179
JB		 1121static const char *state_string(bool enabled)
1122{
1123 return enabled ? "on" : "off";
1124}
1125
1126/* Only for pre-ILK configs */
55607e8a
DV		 1127void assert_pll(struct drm_i915_private *dev_priv,
1128 enum pipe pipe, bool state)
b24e7179
JB		 1129{
1130 int reg;
1131 u32 val;
1132 bool cur_state;
1133
1134 reg = DPLL(pipe);
1135 val = I915_READ(reg);
1136 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1137 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1138 "PLL state assertion failure (expected %s, current %s)\n",
1139 state_string(state), state_string(cur_state));
1140}
b24e7179 1141
23538ef1
JN		 1142/* XXX: the dsi pll is shared between MIPI DSI ports */
1143static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1144{
1145 u32 val;
1146 bool cur_state;
1147
a580516d 1148 mutex_lock(&dev_priv->sb_lock);
23538ef1 1149 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
a580516d 1150 mutex_unlock(&dev_priv->sb_lock);
23538ef1
JN		 1151
1152 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1153 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1154 "DSI PLL state assertion failure (expected %s, current %s)\n",
1155 state_string(state), state_string(cur_state));
1156}
1157#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1158#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1159
55607e8a 1160struct intel_shared_dpll *
e2b78267
DV		 1161intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1162{
1163 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1164
6e3c9717 1165 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1166 return NULL;
1167
6e3c9717 1168 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1169}
1170
040484af 1171/* For ILK+ */
55607e8a
DV		 1172void assert_shared_dpll(struct drm_i915_private *dev_priv,
1173 struct intel_shared_dpll *pll,
1174 bool state)
040484af 1175{
040484af 1176 bool cur_state;
5358901f 1177 struct intel_dpll_hw_state hw_state;
040484af 1178
92b27b08 1179 if (WARN (!pll,
46edb027 1180 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1181 return;
ee7b9f93 1182
5358901f 1183 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1184 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1185 "%s assertion failure (expected %s, current %s)\n",
1186 pll->name, state_string(state), state_string(cur_state));
040484af 1187}
040484af
JB		 1188
1189static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1190 enum pipe pipe, bool state)
1191{
1192 int reg;
1193 u32 val;
1194 bool cur_state;
ad80a810
PZ		 1195 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1196 pipe);
040484af 1197
affa9354
PZ		 1198 if (HAS_DDI(dev_priv->dev)) {
1199 /* DDI does not have a specific FDI_TX register */
ad80a810 1200 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1201 val = I915_READ(reg);
ad80a810 1202 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1203 } else {
1204 reg = FDI_TX_CTL(pipe);
1205 val = I915_READ(reg);
1206 cur_state = !!(val & FDI_TX_ENABLE);
1207 }
e2c719b7 1208 I915_STATE_WARN(cur_state != state,
040484af
JB		 1209 "FDI TX state assertion failure (expected %s, current %s)\n",
1210 state_string(state), state_string(cur_state));
1211}
1212#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1213#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1214
1215static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1216 enum pipe pipe, bool state)
1217{
1218 int reg;
1219 u32 val;
1220 bool cur_state;
1221
d63fa0dc
PZ		 1222 reg = FDI_RX_CTL(pipe);
1223 val = I915_READ(reg);
1224 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1225 I915_STATE_WARN(cur_state != state,
040484af
JB		 1226 "FDI RX state assertion failure (expected %s, current %s)\n",
1227 state_string(state), state_string(cur_state));
1228}
1229#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1230#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1231
1232static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1233 enum pipe pipe)
1234{
1235 int reg;
1236 u32 val;
1237
1238 /* ILK FDI PLL is always enabled */
3d13ef2e 1239 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1240 return;
1241
bf507ef7 1242 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1243 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1244 return;
1245
040484af
JB		 1246 reg = FDI_TX_CTL(pipe);
1247 val = I915_READ(reg);
e2c719b7 1248 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1249}
1250
55607e8a
DV		 1251void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1252 enum pipe pipe, bool state)
040484af
JB		 1253{
1254 int reg;
1255 u32 val;
55607e8a 1256 bool cur_state;
040484af
JB		 1257
1258 reg = FDI_RX_CTL(pipe);
1259 val = I915_READ(reg);
55607e8a 1260 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1261 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1262 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1263 state_string(state), state_string(cur_state));
040484af
JB		 1264}
1265
b680c37a
DV		 1266void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1267 enum pipe pipe)
ea0760cf 1268{
bedd4dba
JN		 1269 struct drm_device *dev = dev_priv->dev;
1270 int pp_reg;
ea0760cf
JB		 1271 u32 val;
1272 enum pipe panel_pipe = PIPE_A;
0de3b485 1273 bool locked = true;
ea0760cf 1274
bedd4dba
JN		 1275 if (WARN_ON(HAS_DDI(dev)))
1276 return;
1277
1278 if (HAS_PCH_SPLIT(dev)) {
1279 u32 port_sel;
1280
ea0760cf 1281 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1282 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1283
1284 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1285 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1286 panel_pipe = PIPE_B;
1287 /* XXX: else fix for eDP */
1288 } else if (IS_VALLEYVIEW(dev)) {
1289 /* presumably write lock depends on pipe, not port select */
1290 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1291 panel_pipe = pipe;
ea0760cf
JB		 1292 } else {
1293 pp_reg = PP_CONTROL;
bedd4dba
JN		 1294 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1295 panel_pipe = PIPE_B;
ea0760cf
JB		 1296 }
1297
1298 val = I915_READ(pp_reg);
1299 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1300 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1301 locked = false;
1302
e2c719b7 1303 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1304 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1305 pipe_name(pipe));
ea0760cf
JB		 1306}
1307
93ce0ba6
JN		 1308static void assert_cursor(struct drm_i915_private *dev_priv,
1309 enum pipe pipe, bool state)
1310{
1311 struct drm_device *dev = dev_priv->dev;
1312 bool cur_state;
1313
d9d82081 1314 if (IS_845G(dev) || IS_I865G(dev))
93ce0ba6 1315 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
d9d82081 1316 else
5efb3e28 1317 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1318
e2c719b7 1319 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1320 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1321 pipe_name(pipe), state_string(state), state_string(cur_state));
1322}
1323#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1324#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1325
b840d907
JB		 1326void assert_pipe(struct drm_i915_private *dev_priv,
1327 enum pipe pipe, bool state)
b24e7179
JB		 1328{
1329 int reg;
1330 u32 val;
63d7bbe9 1331 bool cur_state;
702e7a56
PZ		 1332 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1333 pipe);
b24e7179 1334
b6b5d049
VS		 1335 /* if we need the pipe quirk it must be always on */
1336 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1337 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1338 state = true;
1339
f458ebbc 1340 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1341 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1342 cur_state = false;
1343 } else {
1344 reg = PIPECONF(cpu_transcoder);
1345 val = I915_READ(reg);
1346 cur_state = !!(val & PIPECONF_ENABLE);
1347 }
1348
e2c719b7 1349 I915_STATE_WARN(cur_state != state,
63d7bbe9 1350 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1351 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1352}
1353
931872fc
CW		 1354static void assert_plane(struct drm_i915_private *dev_priv,
1355 enum plane plane, bool state)
b24e7179
JB		 1356{
1357 int reg;
1358 u32 val;
931872fc 1359 bool cur_state;
b24e7179
JB		 1360
1361 reg = DSPCNTR(plane);
1362 val = I915_READ(reg);
931872fc 1363 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1364 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1365 "plane %c assertion failure (expected %s, current %s)\n",
1366 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1367}
1368
931872fc
CW		 1369#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1370#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1371
b24e7179
JB		 1372static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1373 enum pipe pipe)
1374{
653e1026 1375 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1376 int reg, i;
1377 u32 val;
1378 int cur_pipe;
1379
653e1026
VS		 1380 /* Primary planes are fixed to pipes on gen4+ */
1381 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1382 reg = DSPCNTR(pipe);
1383 val = I915_READ(reg);
e2c719b7 1384 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1385 "plane %c assertion failure, should be disabled but not\n",
1386 plane_name(pipe));
19ec1358 1387 return;
28c05794 1388 }
19ec1358 1389
b24e7179 1390 /* Need to check both planes against the pipe */
055e393f 1391 for_each_pipe(dev_priv, i) {
b24e7179
JB		 1392 reg = DSPCNTR(i);
1393 val = I915_READ(reg);
1394 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1395 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1396 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1397 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1398 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1399 }
1400}
1401
19332d7a
JB		 1402static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1403 enum pipe pipe)
1404{
20674eef 1405 struct drm_device *dev = dev_priv->dev;
1fe47785 1406 int reg, sprite;
19332d7a
JB		 1407 u32 val;
1408
7feb8b88 1409 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1410 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1411 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1412 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1413 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1414 sprite, pipe_name(pipe));
1415 }
1416 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1417 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1418 reg = SPCNTR(pipe, sprite);
20674eef 1419 val = I915_READ(reg);
e2c719b7 1420 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1421 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1422 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1423 }
1424 } else if (INTEL_INFO(dev)->gen >= 7) {
1425 reg = SPRCTL(pipe);
19332d7a 1426 val = I915_READ(reg);
e2c719b7 1427 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1428 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1429 plane_name(pipe), pipe_name(pipe));
1430 } else if (INTEL_INFO(dev)->gen >= 5) {
1431 reg = DVSCNTR(pipe);
19332d7a 1432 val = I915_READ(reg);
e2c719b7 1433 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1434 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1435 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1436 }
1437}
1438
08c71e5e
VS		 1439static void assert_vblank_disabled(struct drm_crtc *crtc)
1440{
e2c719b7 1441 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1442 drm_crtc_vblank_put(crtc);
1443}
1444
89eff4be 1445static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1446{
1447 u32 val;
1448 bool enabled;
1449
e2c719b7 1450 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1451
92f2584a
JB		 1452 val = I915_READ(PCH_DREF_CONTROL);
1453 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1454 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1455 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1456}
1457
ab9412ba
DV		 1458static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1459 enum pipe pipe)
92f2584a
JB		 1460{
1461 int reg;
1462 u32 val;
1463 bool enabled;
1464
ab9412ba 1465 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1466 val = I915_READ(reg);
1467 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1468 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1469 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1470 pipe_name(pipe));
92f2584a
JB		 1471}
1472
4e634389
KP		 1473static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1474 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1475{
1476 if ((val & DP_PORT_EN) == 0)
1477 return false;
1478
1479 if (HAS_PCH_CPT(dev_priv->dev)) {
1480 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1481 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1482 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1483 return false;
44f37d1f
CML		 1484 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1485 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1486 return false;
f0575e92
KP		 1487 } else {
1488 if ((val & DP_PIPE_MASK) != (pipe << 30))
1489 return false;
1490 }
1491 return true;
1492}
1493
1519b995
KP		 1494static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1495 enum pipe pipe, u32 val)
1496{
dc0fa718 1497 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1498 return false;
1499
1500 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1501 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1502 return false;
44f37d1f
CML		 1503 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1504 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1505 return false;
1519b995 1506 } else {
dc0fa718 1507 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1508 return false;
1509 }
1510 return true;
1511}
1512
1513static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1514 enum pipe pipe, u32 val)
1515{
1516 if ((val & LVDS_PORT_EN) == 0)
1517 return false;
1518
1519 if (HAS_PCH_CPT(dev_priv->dev)) {
1520 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1521 return false;
1522 } else {
1523 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1524 return false;
1525 }
1526 return true;
1527}
1528
1529static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1530 enum pipe pipe, u32 val)
1531{
1532 if ((val & ADPA_DAC_ENABLE) == 0)
1533 return false;
1534 if (HAS_PCH_CPT(dev_priv->dev)) {
1535 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1536 return false;
1537 } else {
1538 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1539 return false;
1540 }
1541 return true;
1542}
1543
291906f1 1544static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1545 enum pipe pipe, int reg, u32 port_sel)
291906f1 1546{
47a05eca 1547 u32 val = I915_READ(reg);
e2c719b7 1548 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1549 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1550 reg, pipe_name(pipe));
de9a35ab 1551
e2c719b7 1552 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1553 && (val & DP_PIPEB_SELECT),
de9a35ab 1554 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1555}
1556
1557static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1558 enum pipe pipe, int reg)
1559{
47a05eca 1560 u32 val = I915_READ(reg);
e2c719b7 1561 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1562 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1563 reg, pipe_name(pipe));
de9a35ab 1564
e2c719b7 1565 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1566 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1567 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1568}
1569
1570static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1571 enum pipe pipe)
1572{
1573 int reg;
1574 u32 val;
291906f1 1575
f0575e92
KP		 1576 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1577 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1578 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1579
1580 reg = PCH_ADPA;
1581 val = I915_READ(reg);
e2c719b7 1582 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1583 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1584 pipe_name(pipe));
291906f1
JB		 1585
1586 reg = PCH_LVDS;
1587 val = I915_READ(reg);
e2c719b7 1588 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1589 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1590 pipe_name(pipe));
291906f1 1591
e2debe91
PZ		 1592 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1593 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1594 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1595}
1596
40e9cf64
JB		 1597static void intel_init_dpio(struct drm_device *dev)
1598{
1599 struct drm_i915_private *dev_priv = dev->dev_private;
1600
1601 if (!IS_VALLEYVIEW(dev))
1602 return;
1603
a09caddd
CML		 1604 /*
1605 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1606 * CHV x1 PHY (DP/HDMI D)
1607 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1608 */
1609 if (IS_CHERRYVIEW(dev)) {
1610 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1611 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1612 } else {
1613 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1614 }
5382f5f3
JB		 1615}
1616
d288f65f 1617static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1618 const struct intel_crtc_state *pipe_config)
87442f73 1619{
426115cf
DV		 1620 struct drm_device *dev = crtc->base.dev;
1621 struct drm_i915_private *dev_priv = dev->dev_private;
1622 int reg = DPLL(crtc->pipe);
d288f65f 1623 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1624
426115cf 1625 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1626
1627 /* No really, not for ILK+ */
1628 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1629
1630 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1631 if (IS_MOBILE(dev_priv->dev))
426115cf 1632 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1633
426115cf
DV		 1634 I915_WRITE(reg, dpll);
1635 POSTING_READ(reg);
1636 udelay(150);
1637
1638 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1639 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1640
d288f65f 1641 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1642 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1643
1644 /* We do this three times for luck */
426115cf 1645 I915_WRITE(reg, dpll);
87442f73
DV		 1646 POSTING_READ(reg);
1647 udelay(150); /* wait for warmup */
426115cf 1648 I915_WRITE(reg, dpll);
87442f73
DV		 1649 POSTING_READ(reg);
1650 udelay(150); /* wait for warmup */
426115cf 1651 I915_WRITE(reg, dpll);
87442f73
DV		 1652 POSTING_READ(reg);
1653 udelay(150); /* wait for warmup */
1654}
1655
d288f65f 1656static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1657 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1658{
1659 struct drm_device *dev = crtc->base.dev;
1660 struct drm_i915_private *dev_priv = dev->dev_private;
1661 int pipe = crtc->pipe;
1662 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1663 u32 tmp;
1664
1665 assert_pipe_disabled(dev_priv, crtc->pipe);
1666
1667 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1668
a580516d 1669 mutex_lock(&dev_priv->sb_lock);
9d556c99
CML		 1670
1671 /* Enable back the 10bit clock to display controller */
1672 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1673 tmp |= DPIO_DCLKP_EN;
1674 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1675
54433e91
VS		 1676 mutex_unlock(&dev_priv->sb_lock);
1677
9d556c99
CML		 1678 /*
1679 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1680 */
1681 udelay(1);
1682
1683 /* Enable PLL */
d288f65f 1684 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1685
1686 /* Check PLL is locked */
a11b0703 1687 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1688 DRM_ERROR("PLL %d failed to lock\n", pipe);
1689
a11b0703 1690 /* not sure when this should be written */
d288f65f 1691 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703 1692 POSTING_READ(DPLL_MD(pipe));
9d556c99
CML		 1693}
1694
1c4e0274
VS		 1695static int intel_num_dvo_pipes(struct drm_device *dev)
1696{
1697 struct intel_crtc *crtc;
1698 int count = 0;
1699
1700 for_each_intel_crtc(dev, crtc)
3538b9df 1701 count += crtc->base.state->active &&
409ee761 1702 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1703
1704 return count;
1705}
1706
66e3d5c0 1707static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1708{
66e3d5c0
DV		 1709 struct drm_device *dev = crtc->base.dev;
1710 struct drm_i915_private *dev_priv = dev->dev_private;
1711 int reg = DPLL(crtc->pipe);
6e3c9717 1712 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1713
66e3d5c0 1714 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1715
63d7bbe9 1716 /* No really, not for ILK+ */
3d13ef2e 1717 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1718
1719 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1720 if (IS_MOBILE(dev) && !IS_I830(dev))
1721 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1722
1c4e0274
VS		 1723 /* Enable DVO 2x clock on both PLLs if necessary */
1724 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1725 /*
1726 * It appears to be important that we don't enable this
1727 * for the current pipe before otherwise configuring the
1728 * PLL. No idea how this should be handled if multiple
1729 * DVO outputs are enabled simultaneosly.
1730 */
1731 dpll |= DPLL_DVO_2X_MODE;
1732 I915_WRITE(DPLL(!crtc->pipe),
1733 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1734 }
66e3d5c0
DV		 1735
1736 /* Wait for the clocks to stabilize. */
1737 POSTING_READ(reg);
1738 udelay(150);
1739
1740 if (INTEL_INFO(dev)->gen >= 4) {
1741 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1742 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1743 } else {
1744 /* The pixel multiplier can only be updated once the
1745 * DPLL is enabled and the clocks are stable.
1746 *
1747 * So write it again.
1748 */
1749 I915_WRITE(reg, dpll);
1750 }
63d7bbe9
JB		 1751
1752 /* We do this three times for luck */
66e3d5c0 1753 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1754 POSTING_READ(reg);
1755 udelay(150); /* wait for warmup */
66e3d5c0 1756 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1757 POSTING_READ(reg);
1758 udelay(150); /* wait for warmup */
66e3d5c0 1759 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1760 POSTING_READ(reg);
1761 udelay(150); /* wait for warmup */
1762}
1763
1764/**
50b44a44 1765 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1766 * @dev_priv: i915 private structure
1767 * @pipe: pipe PLL to disable
1768 *
1769 * Disable the PLL for @pipe, making sure the pipe is off first.
1770 *
1771 * Note! This is for pre-ILK only.
1772 */
1c4e0274 1773static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1774{
1c4e0274
VS		 1775 struct drm_device *dev = crtc->base.dev;
1776 struct drm_i915_private *dev_priv = dev->dev_private;
1777 enum pipe pipe = crtc->pipe;
1778
1779 /* Disable DVO 2x clock on both PLLs if necessary */
1780 if (IS_I830(dev) &&
409ee761 1781 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
3538b9df 1782 !intel_num_dvo_pipes(dev)) {
1c4e0274
VS		 1783 I915_WRITE(DPLL(PIPE_B),
1784 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1785 I915_WRITE(DPLL(PIPE_A),
1786 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1787 }
1788
b6b5d049
VS		 1789 /* Don't disable pipe or pipe PLLs if needed */
1790 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1791 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1792 return;
1793
1794 /* Make sure the pipe isn't still relying on us */
1795 assert_pipe_disabled(dev_priv, pipe);
1796
50b44a44
DV		 1797 I915_WRITE(DPLL(pipe), 0);
1798 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1799}
1800
f6071166
JB		 1801static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1802{
1803 u32 val = 0;
1804
1805 /* Make sure the pipe isn't still relying on us */
1806 assert_pipe_disabled(dev_priv, pipe);
1807
e5cbfbfb
ID		 1808 /*
1809 * Leave integrated clock source and reference clock enabled for pipe B.
1810 * The latter is needed for VGA hotplug / manual detection.
1811 */
f6071166 1812 if (pipe == PIPE_B)
e5cbfbfb 1813 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
f6071166
JB		 1814 I915_WRITE(DPLL(pipe), val);
1815 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1816
1817}
1818
1819static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1820{
d752048d 1821 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1822 u32 val;
1823
a11b0703
VS		 1824 /* Make sure the pipe isn't still relying on us */
1825 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1826
a11b0703 1827 /* Set PLL en = 0 */
d17ec4ce 1828 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
a11b0703
VS		 1829 if (pipe != PIPE_A)
1830 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1831 I915_WRITE(DPLL(pipe), val);
1832 POSTING_READ(DPLL(pipe));
d752048d 1833
a580516d 1834 mutex_lock(&dev_priv->sb_lock);
d752048d
VS		 1835
1836 /* Disable 10bit clock to display controller */
1837 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1838 val &= ~DPIO_DCLKP_EN;
1839 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1840
61407f6d
VS		 1841 /* disable left/right clock distribution */
1842 if (pipe != PIPE_B) {
1843 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1844 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1845 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1846 } else {
1847 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1848 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1849 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1850 }
1851
a580516d 1852 mutex_unlock(&dev_priv->sb_lock);
f6071166
JB		 1853}
1854
e4607fcf 1855void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
9b6de0a1
VS		 1856 struct intel_digital_port *dport,
1857 unsigned int expected_mask)
89b667f8
JB		 1858{
1859 u32 port_mask;
00fc31b7 1860 int dpll_reg;
89b667f8 1861
e4607fcf
CML		 1862 switch (dport->port) {
1863 case PORT_B:
89b667f8 1864 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1865 dpll_reg = DPLL(0);
e4607fcf
CML		 1866 break;
1867 case PORT_C:
89b667f8 1868 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7 1869 dpll_reg = DPLL(0);
9b6de0a1 1870 expected_mask <<= 4;
00fc31b7
CML		 1871 break;
1872 case PORT_D:
1873 port_mask = DPLL_PORTD_READY_MASK;
1874 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1875 break;
1876 default:
1877 BUG();
1878 }
89b667f8 1879
9b6de0a1
VS		 1880 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1881 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1882 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
89b667f8
JB		 1883}
1884
b14b1055
DV		 1885static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1886{
1887 struct drm_device *dev = crtc->base.dev;
1888 struct drm_i915_private *dev_priv = dev->dev_private;
1889 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1890
be19f0ff
CW		 1891 if (WARN_ON(pll == NULL))
1892 return;
1893
3e369b76 1894 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1895 if (pll->active == 0) {
1896 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1897 WARN_ON(pll->on);
1898 assert_shared_dpll_disabled(dev_priv, pll);
1899
1900 pll->mode_set(dev_priv, pll);
1901 }
1902}
1903
92f2584a 1904/**
85b3894f 1905 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1906 * @dev_priv: i915 private structure
1907 * @pipe: pipe PLL to enable
1908 *
1909 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1910 * drives the transcoder clock.
1911 */
85b3894f 1912static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1913{
3d13ef2e
DL		 1914 struct drm_device *dev = crtc->base.dev;
1915 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1916 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1917
87a875bb 1918 if (WARN_ON(pll == NULL))
48da64a8
CW		 1919 return;
1920
3e369b76 1921 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1922 return;
ee7b9f93 1923
74dd6928 1924 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1925 pll->name, pll->active, pll->on,
e2b78267 1926 crtc->base.base.id);
92f2584a 1927
cdbd2316
DV		 1928 if (pll->active++) {
1929 WARN_ON(!pll->on);
e9d6944e 1930 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1931 return;
1932 }
f4a091c7 1933 WARN_ON(pll->on);
ee7b9f93 1934
bd2bb1b9
PZ		 1935 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1936
46edb027 1937 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1938 pll->enable(dev_priv, pll);
ee7b9f93 1939 pll->on = true;
92f2584a
JB		 1940}
1941
f6daaec2 1942static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1943{
3d13ef2e
DL		 1944 struct drm_device *dev = crtc->base.dev;
1945 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1946 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1947
92f2584a 1948 /* PCH only available on ILK+ */
3d13ef2e 1949 BUG_ON(INTEL_INFO(dev)->gen < 5);
87a875bb 1950 if (WARN_ON(pll == NULL))
ee7b9f93 1951 return;
92f2584a 1952
3e369b76 1953 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1954 return;
7a419866 1955
46edb027
DV		 1956 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1957 pll->name, pll->active, pll->on,
e2b78267 1958 crtc->base.base.id);
7a419866 1959
48da64a8 1960 if (WARN_ON(pll->active == 0)) {
e9d6944e 1961 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1962 return;
1963 }
1964
e9d6944e 1965 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1966 WARN_ON(!pll->on);
cdbd2316 1967 if (--pll->active)
7a419866 1968 return;
ee7b9f93 1969
46edb027 1970 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1971 pll->disable(dev_priv, pll);
ee7b9f93 1972 pll->on = false;
bd2bb1b9
PZ		 1973
1974 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1975}
1976
b8a4f404
PZ		 1977static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1978 enum pipe pipe)
040484af 1979{
23670b32 1980 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1981 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1982 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1983 uint32_t reg, val, pipeconf_val;
040484af
JB		 1984
1985 /* PCH only available on ILK+ */
55522f37 1986 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1987
1988 /* Make sure PCH DPLL is enabled */
e72f9fbf 1989 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1990 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1991
1992 /* FDI must be feeding us bits for PCH ports */
1993 assert_fdi_tx_enabled(dev_priv, pipe);
1994 assert_fdi_rx_enabled(dev_priv, pipe);
1995
23670b32
DV		 1996 if (HAS_PCH_CPT(dev)) {
1997 /* Workaround: Set the timing override bit before enabling the
1998 * pch transcoder. */
1999 reg = TRANS_CHICKEN2(pipe);
2000 val = I915_READ(reg);
2001 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2002 I915_WRITE(reg, val);
59c859d6 2003 }
23670b32 2004
ab9412ba 2005 reg = PCH_TRANSCONF(pipe);
040484af 2006 val = I915_READ(reg);
5f7f726d 2007 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 2008
2009 if (HAS_PCH_IBX(dev_priv->dev)) {
2010 /*
c5de7c6f
VS		 2011 * Make the BPC in transcoder be consistent with
2012 * that in pipeconf reg. For HDMI we must use 8bpc
2013 * here for both 8bpc and 12bpc.
e9bcff5c 2014 */
dfd07d72 2015 val &= ~PIPECONF_BPC_MASK;
c5de7c6f
VS		 2016 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2017 val |= PIPECONF_8BPC;
2018 else
2019 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 2020 }
5f7f726d
PZ		 2021
2022 val &= ~TRANS_INTERLACE_MASK;
2023 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 2024 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 2025 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 2026 val |= TRANS_LEGACY_INTERLACED_ILK;
2027 else
2028 val |= TRANS_INTERLACED;
5f7f726d
PZ		 2029 else
2030 val |= TRANS_PROGRESSIVE;
2031
040484af
JB		 2032 I915_WRITE(reg, val | TRANS_ENABLE);
2033 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 2034 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 2035}
2036
8fb033d7 2037static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 2038 enum transcoder cpu_transcoder)
040484af 2039{
8fb033d7 2040 u32 val, pipeconf_val;
8fb033d7
PZ		 2041
2042 /* PCH only available on ILK+ */
55522f37 2043 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 2044
8fb033d7 2045 /* FDI must be feeding us bits for PCH ports */
1a240d4d 2046 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2047 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2048
223a6fdf
PZ		 2049 /* Workaround: set timing override bit. */
2050 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2051 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 2052 I915_WRITE(_TRANSA_CHICKEN2, val);
2053
25f3ef11 2054 val = TRANS_ENABLE;
937bb610 2055 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2056
9a76b1c6
PZ		 2057 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2058 PIPECONF_INTERLACED_ILK)
a35f2679 2059 val |= TRANS_INTERLACED;
8fb033d7
PZ		 2060 else
2061 val |= TRANS_PROGRESSIVE;
2062
ab9412ba
DV		 2063 I915_WRITE(LPT_TRANSCONF, val);
2064 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2065 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 2066}
2067
b8a4f404
PZ		 2068static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2069 enum pipe pipe)
040484af 2070{
23670b32
DV		 2071 struct drm_device *dev = dev_priv->dev;
2072 uint32_t reg, val;
040484af
JB		 2073
2074 /* FDI relies on the transcoder */
2075 assert_fdi_tx_disabled(dev_priv, pipe);
2076 assert_fdi_rx_disabled(dev_priv, pipe);
2077
291906f1
JB		 2078 /* Ports must be off as well */
2079 assert_pch_ports_disabled(dev_priv, pipe);
2080
ab9412ba 2081 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2082 val = I915_READ(reg);
2083 val &= ~TRANS_ENABLE;
2084 I915_WRITE(reg, val);
2085 /* wait for PCH transcoder off, transcoder state */
2086 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2087 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2088
2089 if (!HAS_PCH_IBX(dev)) {
2090 /* Workaround: Clear the timing override chicken bit again. */
2091 reg = TRANS_CHICKEN2(pipe);
2092 val = I915_READ(reg);
2093 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2094 I915_WRITE(reg, val);
2095 }
040484af
JB		 2096}
2097
ab4d966c 2098static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2099{
8fb033d7
PZ		 2100 u32 val;
2101
ab9412ba 2102 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2103 val &= ~TRANS_ENABLE;
ab9412ba 2104 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2105 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2106 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2107 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2108
2109 /* Workaround: clear timing override bit. */
2110 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2111 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 2112 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 2113}
2114
b24e7179 2115/**
309cfea8 2116 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2117 * @crtc: crtc responsible for the pipe
b24e7179 2118 *
0372264a 2119 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2120 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2121 */
e1fdc473 2122static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2123{
0372264a
PZ		 2124 struct drm_device *dev = crtc->base.dev;
2125 struct drm_i915_private *dev_priv = dev->dev_private;
2126 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2127 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2128 pipe);
1a240d4d 2129 enum pipe pch_transcoder;
b24e7179
JB		 2130 int reg;
2131 u32 val;
2132
58c6eaa2 2133 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2134 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2135 assert_sprites_disabled(dev_priv, pipe);
2136
681e5811 2137 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2138 pch_transcoder = TRANSCODER_A;
2139 else
2140 pch_transcoder = pipe;
2141
b24e7179
JB		 2142 /*
2143 * A pipe without a PLL won't actually be able to drive bits from
2144 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2145 * need the check.
2146 */
50360403 2147 if (HAS_GMCH_DISPLAY(dev_priv->dev))
409ee761 2148 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2149 assert_dsi_pll_enabled(dev_priv);
2150 else
2151 assert_pll_enabled(dev_priv, pipe);
040484af 2152 else {
6e3c9717 2153 if (crtc->config->has_pch_encoder) {
040484af 2154 /* if driving the PCH, we need FDI enabled */
cc391bbb 2155 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2156 assert_fdi_tx_pll_enabled(dev_priv,
2157 (enum pipe) cpu_transcoder);
040484af
JB		 2158 }
2159 /* FIXME: assert CPU port conditions for SNB+ */
2160 }
b24e7179 2161
702e7a56 2162 reg = PIPECONF(cpu_transcoder);
b24e7179 2163 val = I915_READ(reg);
7ad25d48 2164 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2165 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2166 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2167 return;
7ad25d48 2168 }
00d70b15
CW		 2169
2170 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2171 POSTING_READ(reg);
b24e7179
JB		 2172}
2173
2174/**
309cfea8 2175 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2176 * @crtc: crtc whose pipes is to be disabled
b24e7179 2177 *
575f7ab7
VS		 2178 * Disable the pipe of @crtc, making sure that various hardware
2179 * specific requirements are met, if applicable, e.g. plane
2180 * disabled, panel fitter off, etc.
b24e7179
JB		 2181 *
2182 * Will wait until the pipe has shut down before returning.
2183 */
575f7ab7 2184static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2185{
575f7ab7 2186 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2187 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2188 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2189 int reg;
2190 u32 val;
2191
2192 /*
2193 * Make sure planes won't keep trying to pump pixels to us,
2194 * or we might hang the display.
2195 */
2196 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2197 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2198 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2199
702e7a56 2200 reg = PIPECONF(cpu_transcoder);
b24e7179 2201 val = I915_READ(reg);
00d70b15
CW		 2202 if ((val & PIPECONF_ENABLE) == 0)
2203 return;
2204
67adc644
VS		 2205 /*
2206 * Double wide has implications for planes
2207 * so best keep it disabled when not needed.
2208 */
6e3c9717 2209 if (crtc->config->double_wide)
67adc644
VS		 2210 val &= ~PIPECONF_DOUBLE_WIDE;
2211
2212 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2213 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2214 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2215 val &= ~PIPECONF_ENABLE;
2216
2217 I915_WRITE(reg, val);
2218 if ((val & PIPECONF_ENABLE) == 0)
2219 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2220}
2221
2222/**
262ca2b0 2223 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
fdd508a6
VS		 2224 * @plane: plane to be enabled
2225 * @crtc: crtc for the plane
b24e7179 2226 *
fdd508a6 2227 * Enable @plane on @crtc, making sure that the pipe is running first.
b24e7179 2228 */
fdd508a6
VS		 2229static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2230 struct drm_crtc *crtc)
b24e7179 2231{
fdd508a6
VS		 2232 struct drm_device *dev = plane->dev;
2233 struct drm_i915_private *dev_priv = dev->dev_private;
2234 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b24e7179
JB		 2235
2236 /* If the pipe isn't enabled, we can't pump pixels and may hang */
fdd508a6 2237 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
b70709a6 2238 to_intel_plane_state(plane->state)->visible = true;
939c2fe8 2239
fdd508a6
VS		 2240 dev_priv->display.update_primary_plane(crtc, plane->fb,
2241 crtc->x, crtc->y);
b24e7179
JB		 2242}
2243
693db184
CW		 2244static bool need_vtd_wa(struct drm_device *dev)
2245{
2246#ifdef CONFIG_INTEL_IOMMU
2247 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2248 return true;
2249#endif
2250 return false;
2251}
2252
50470bb0 2253unsigned int
6761dd31
TU		 2254intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2255 uint64_t fb_format_modifier)
a57ce0b2 2256{
6761dd31
TU		 2257 unsigned int tile_height;
2258 uint32_t pixel_bytes;
a57ce0b2 2259
b5d0e9bf
DL		 2260 switch (fb_format_modifier) {
2261 case DRM_FORMAT_MOD_NONE:
2262 tile_height = 1;
2263 break;
2264 case I915_FORMAT_MOD_X_TILED:
2265 tile_height = IS_GEN2(dev) ? 16 : 8;
2266 break;
2267 case I915_FORMAT_MOD_Y_TILED:
2268 tile_height = 32;
2269 break;
2270 case I915_FORMAT_MOD_Yf_TILED:
6761dd31
TU		 2271 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2272 switch (pixel_bytes) {
b5d0e9bf 2273 default:
6761dd31 2274 case 1:
b5d0e9bf
DL		 2275 tile_height = 64;
2276 break;
6761dd31
TU		 2277 case 2:
2278 case 4:
b5d0e9bf
DL		 2279 tile_height = 32;
2280 break;
6761dd31 2281 case 8:
b5d0e9bf
DL		 2282 tile_height = 16;
2283 break;
6761dd31 2284 case 16:
b5d0e9bf
DL		 2285 WARN_ONCE(1,
2286 "128-bit pixels are not supported for display!");
2287 tile_height = 16;
2288 break;
2289 }
2290 break;
2291 default:
2292 MISSING_CASE(fb_format_modifier);
2293 tile_height = 1;
2294 break;
2295 }
091df6cb 2296
6761dd31
TU		 2297 return tile_height;
2298}
2299
2300unsigned int
2301intel_fb_align_height(struct drm_device *dev, unsigned int height,
2302 uint32_t pixel_format, uint64_t fb_format_modifier)
2303{
2304 return ALIGN(height, intel_tile_height(dev, pixel_format,
2305 fb_format_modifier));
a57ce0b2
JB		 2306}
2307
f64b98cd
TU		 2308static int
2309intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2310 const struct drm_plane_state *plane_state)
2311{
50470bb0 2312 struct intel_rotation_info *info = &view->rotation_info;
50470bb0 2313
f64b98cd
TU		 2314 *view = i915_ggtt_view_normal;
2315
50470bb0
TU		 2316 if (!plane_state)
2317 return 0;
2318
121920fa 2319 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2320 return 0;
2321
9abc4648 2322 *view = i915_ggtt_view_rotated;
50470bb0
TU		 2323
2324 info->height = fb->height;
2325 info->pixel_format = fb->pixel_format;
2326 info->pitch = fb->pitches[0];
2327 info->fb_modifier = fb->modifier[0];
2328
f64b98cd
TU		 2329 return 0;
2330}
2331
4e9a86b6
VS		 2332static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2333{
2334 if (INTEL_INFO(dev_priv)->gen >= 9)
2335 return 256 * 1024;
985b8bb4
VS		 2336 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2337 IS_VALLEYVIEW(dev_priv))
4e9a86b6
VS		 2338 return 128 * 1024;
2339 else if (INTEL_INFO(dev_priv)->gen >= 4)
2340 return 4 * 1024;
2341 else
44c5905e 2342 return 0;
4e9a86b6
VS		 2343}
2344
127bd2ac 2345int
850c4cdc
TU		 2346intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2347 struct drm_framebuffer *fb,
82bc3b2d 2348 const struct drm_plane_state *plane_state,
a4872ba6 2349 struct intel_engine_cs *pipelined)
6b95a207 2350{
850c4cdc 2351 struct drm_device *dev = fb->dev;
ce453d81 2352 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2353 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2354 struct i915_ggtt_view view;
6b95a207
KH		 2355 u32 alignment;
2356 int ret;
2357
ebcdd39e
MR		 2358 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2359
7b911adc
TU		 2360 switch (fb->modifier[0]) {
2361 case DRM_FORMAT_MOD_NONE:
4e9a86b6 2362 alignment = intel_linear_alignment(dev_priv);
6b95a207 2363 break;
7b911adc 2364 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2365 if (INTEL_INFO(dev)->gen >= 9)
2366 alignment = 256 * 1024;
2367 else {
2368 /* pin() will align the object as required by fence */
2369 alignment = 0;
2370 }
6b95a207 2371 break;
7b911adc 2372 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2373 case I915_FORMAT_MOD_Yf_TILED:
2374 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2375 "Y tiling bo slipped through, driver bug!\n"))
2376 return -EINVAL;
2377 alignment = 1 * 1024 * 1024;
2378 break;
6b95a207 2379 default:
7b911adc
TU		 2380 MISSING_CASE(fb->modifier[0]);
2381 return -EINVAL;
6b95a207
KH		 2382 }
2383
f64b98cd
TU		 2384 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2385 if (ret)
2386 return ret;
2387
693db184
CW		 2388 /* Note that the w/a also requires 64 PTE of padding following the
2389 * bo. We currently fill all unused PTE with the shadow page and so
2390 * we should always have valid PTE following the scanout preventing
2391 * the VT-d warning.
2392 */
2393 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2394 alignment = 256 * 1024;
2395
d6dd6843
PZ		 2396 /*
2397 * Global gtt pte registers are special registers which actually forward
2398 * writes to a chunk of system memory. Which means that there is no risk
2399 * that the register values disappear as soon as we call
2400 * intel_runtime_pm_put(), so it is correct to wrap only the
2401 * pin/unpin/fence and not more.
2402 */
2403 intel_runtime_pm_get(dev_priv);
2404
ce453d81 2405 dev_priv->mm.interruptible = false;
e6617330 2406 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
f64b98cd 2407 &view);
48b956c5 2408 if (ret)
ce453d81 2409 goto err_interruptible;
6b95a207
KH		 2410
2411 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2412 * fence, whereas 965+ only requires a fence if using
2413 * framebuffer compression. For simplicity, we always install
2414 * a fence as the cost is not that onerous.
2415 */
06d98131 2416 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2417 if (ret)
2418 goto err_unpin;
1690e1eb 2419
9a5a53b3 2420 i915_gem_object_pin_fence(obj);
6b95a207 2421
ce453d81 2422 dev_priv->mm.interruptible = true;
d6dd6843 2423 intel_runtime_pm_put(dev_priv);
6b95a207 2424 return 0;
48b956c5
CW		 2425
2426err_unpin:
f64b98cd 2427 i915_gem_object_unpin_from_display_plane(obj, &view);
ce453d81
CW		 2428err_interruptible:
2429 dev_priv->mm.interruptible = true;
d6dd6843 2430 intel_runtime_pm_put(dev_priv);
48b956c5 2431 return ret;
6b95a207
KH		 2432}
2433
82bc3b2d
TU		 2434static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2435 const struct drm_plane_state *plane_state)
1690e1eb 2436{
82bc3b2d 2437 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2438 struct i915_ggtt_view view;
2439 int ret;
82bc3b2d 2440
ebcdd39e
MR		 2441 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2442
f64b98cd
TU		 2443 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2444 WARN_ONCE(ret, "Couldn't get view from plane state!");
2445
1690e1eb 2446 i915_gem_object_unpin_fence(obj);
f64b98cd 2447 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2448}
2449
c2c75131
DV		 2450/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2451 * is assumed to be a power-of-two. */
4e9a86b6
VS		 2452unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2453 int *x, int *y,
bc752862
CW		 2454 unsigned int tiling_mode,
2455 unsigned int cpp,
2456 unsigned int pitch)
c2c75131 2457{
bc752862
CW		 2458 if (tiling_mode != I915_TILING_NONE) {
2459 unsigned int tile_rows, tiles;
c2c75131 2460
bc752862
CW		 2461 tile_rows = *y / 8;
2462 *y %= 8;
c2c75131 2463
bc752862
CW		 2464 tiles = *x / (512/cpp);
2465 *x %= 512/cpp;
2466
2467 return tile_rows * pitch * 8 + tiles * 4096;
2468 } else {
4e9a86b6 2469 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
bc752862
CW		 2470 unsigned int offset;
2471
2472 offset = *y * pitch + *x * cpp;
4e9a86b6
VS		 2473 *y = (offset & alignment) / pitch;
2474 *x = ((offset & alignment) - *y * pitch) / cpp;
2475 return offset & ~alignment;
bc752862 2476 }
c2c75131
DV		 2477}
2478
b35d63fa 2479static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2480{
2481 switch (format) {
2482 case DISPPLANE_8BPP:
2483 return DRM_FORMAT_C8;
2484 case DISPPLANE_BGRX555:
2485 return DRM_FORMAT_XRGB1555;
2486 case DISPPLANE_BGRX565:
2487 return DRM_FORMAT_RGB565;
2488 default:
2489 case DISPPLANE_BGRX888:
2490 return DRM_FORMAT_XRGB8888;
2491 case DISPPLANE_RGBX888:
2492 return DRM_FORMAT_XBGR8888;
2493 case DISPPLANE_BGRX101010:
2494 return DRM_FORMAT_XRGB2101010;
2495 case DISPPLANE_RGBX101010:
2496 return DRM_FORMAT_XBGR2101010;
2497 }
2498}
2499
bc8d7dff
DL		 2500static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2501{
2502 switch (format) {
2503 case PLANE_CTL_FORMAT_RGB_565:
2504 return DRM_FORMAT_RGB565;
2505 default:
2506 case PLANE_CTL_FORMAT_XRGB_8888:
2507 if (rgb_order) {
2508 if (alpha)
2509 return DRM_FORMAT_ABGR8888;
2510 else
2511 return DRM_FORMAT_XBGR8888;
2512 } else {
2513 if (alpha)
2514 return DRM_FORMAT_ARGB8888;
2515 else
2516 return DRM_FORMAT_XRGB8888;
2517 }
2518 case PLANE_CTL_FORMAT_XRGB_2101010:
2519 if (rgb_order)
2520 return DRM_FORMAT_XBGR2101010;
2521 else
2522 return DRM_FORMAT_XRGB2101010;
2523 }
2524}
2525
5724dbd1 2526static bool
f6936e29
DV		 2527intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2528 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2529{
2530 struct drm_device *dev = crtc->base.dev;
2531 struct drm_i915_gem_object *obj = NULL;
2532 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2533 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2534 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2535 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2536 PAGE_SIZE);
2537
2538 size_aligned -= base_aligned;
46f297fb 2539
ff2652ea
CW		 2540 if (plane_config->size == 0)
2541 return false;
2542
f37b5c2b
DV		 2543 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2544 base_aligned,
2545 base_aligned,
2546 size_aligned);
46f297fb 2547 if (!obj)
484b41dd 2548 return false;
46f297fb 2549
49af449b
DL		 2550 obj->tiling_mode = plane_config->tiling;
2551 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2552 obj->stride = fb->pitches[0];
46f297fb 2553
6bf129df
DL		 2554 mode_cmd.pixel_format = fb->pixel_format;
2555 mode_cmd.width = fb->width;
2556 mode_cmd.height = fb->height;
2557 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2558 mode_cmd.modifier[0] = fb->modifier[0];
2559 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2560
2561 mutex_lock(&dev->struct_mutex);
6bf129df 2562 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2563 &mode_cmd, obj)) {
46f297fb
JB		 2564 DRM_DEBUG_KMS("intel fb init failed\n");
2565 goto out_unref_obj;
2566 }
46f297fb 2567 mutex_unlock(&dev->struct_mutex);
484b41dd 2568
f6936e29 2569 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2570 return true;
46f297fb
JB		 2571
2572out_unref_obj:
2573 drm_gem_object_unreference(&obj->base);
2574 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2575 return false;
2576}
2577
afd65eb4
MR		 2578/* Update plane->state->fb to match plane->fb after driver-internal updates */
2579static void
2580update_state_fb(struct drm_plane *plane)
2581{
2582 if (plane->fb == plane->state->fb)
2583 return;
2584
2585 if (plane->state->fb)
2586 drm_framebuffer_unreference(plane->state->fb);
2587 plane->state->fb = plane->fb;
2588 if (plane->state->fb)
2589 drm_framebuffer_reference(plane->state->fb);
2590}
2591
5724dbd1 2592static void
f6936e29
DV		 2593intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2594 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2595{
2596 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2597 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2598 struct drm_crtc *c;
2599 struct intel_crtc *i;
2ff8fde1 2600 struct drm_i915_gem_object *obj;
88595ac9
DV		 2601 struct drm_plane *primary = intel_crtc->base.primary;
2602 struct drm_framebuffer *fb;
484b41dd 2603
2d14030b 2604 if (!plane_config->fb)
484b41dd
JB		 2605 return;
2606
f6936e29 2607 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2608 fb = &plane_config->fb->base;
2609 goto valid_fb;
f55548b5 2610 }
484b41dd 2611
2d14030b 2612 kfree(plane_config->fb);
484b41dd
JB		 2613
2614 /*
2615 * Failed to alloc the obj, check to see if we should share
2616 * an fb with another CRTC instead
2617 */
70e1e0ec 2618 for_each_crtc(dev, c) {
484b41dd
JB		 2619 i = to_intel_crtc(c);
2620
2621 if (c == &intel_crtc->base)
2622 continue;
2623
2ff8fde1
MR		 2624 if (!i->active)
2625 continue;
2626
88595ac9
DV		 2627 fb = c->primary->fb;
2628 if (!fb)
484b41dd
JB		 2629 continue;
2630
88595ac9 2631 obj = intel_fb_obj(fb);
2ff8fde1 2632 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2633 drm_framebuffer_reference(fb);
2634 goto valid_fb;
484b41dd
JB		 2635 }
2636 }
88595ac9
DV		 2637
2638 return;
2639
2640valid_fb:
2641 obj = intel_fb_obj(fb);
2642 if (obj->tiling_mode != I915_TILING_NONE)
2643 dev_priv->preserve_bios_swizzle = true;
2644
2645 primary->fb = fb;
36750f28 2646 primary->crtc = primary->state->crtc = &intel_crtc->base;
88595ac9 2647 update_state_fb(primary);
36750f28 2648 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
88595ac9 2649 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
46f297fb
JB		 2650}
2651
29b9bde6
DV		 2652static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2653 struct drm_framebuffer *fb,
2654 int x, int y)
81255565
JB		 2655{
2656 struct drm_device *dev = crtc->dev;
2657 struct drm_i915_private *dev_priv = dev->dev_private;
2658 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2659 struct drm_plane *primary = crtc->primary;
2660 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2661 struct drm_i915_gem_object *obj;
81255565 2662 int plane = intel_crtc->plane;
e506a0c6 2663 unsigned long linear_offset;
81255565 2664 u32 dspcntr;
f45651ba 2665 u32 reg = DSPCNTR(plane);
48404c1e 2666 int pixel_size;
f45651ba 2667
b70709a6 2668 if (!visible || !fb) {
fdd508a6
VS		 2669 I915_WRITE(reg, 0);
2670 if (INTEL_INFO(dev)->gen >= 4)
2671 I915_WRITE(DSPSURF(plane), 0);
2672 else
2673 I915_WRITE(DSPADDR(plane), 0);
2674 POSTING_READ(reg);
2675 return;
2676 }
2677
c9ba6fad
VS		 2678 obj = intel_fb_obj(fb);
2679 if (WARN_ON(obj == NULL))
2680 return;
2681
2682 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2683
f45651ba
VS		 2684 dspcntr = DISPPLANE_GAMMA_ENABLE;
2685
fdd508a6 2686 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2687
2688 if (INTEL_INFO(dev)->gen < 4) {
2689 if (intel_crtc->pipe == PIPE_B)
2690 dspcntr |= DISPPLANE_SEL_PIPE_B;
2691
2692 /* pipesrc and dspsize control the size that is scaled from,
2693 * which should always be the user's requested size.
2694 */
2695 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2696 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2697 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2698 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2699 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2700 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2701 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2702 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2703 I915_WRITE(PRIMPOS(plane), 0);
2704 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2705 }
81255565 2706
57779d06
VS		 2707 switch (fb->pixel_format) {
2708 case DRM_FORMAT_C8:
81255565
JB		 2709 dspcntr |= DISPPLANE_8BPP;
2710 break;
57779d06 2711 case DRM_FORMAT_XRGB1555:
57779d06 2712 dspcntr |= DISPPLANE_BGRX555;
81255565 2713 break;
57779d06
VS		 2714 case DRM_FORMAT_RGB565:
2715 dspcntr |= DISPPLANE_BGRX565;
2716 break;
2717 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2718 dspcntr |= DISPPLANE_BGRX888;
2719 break;
2720 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2721 dspcntr |= DISPPLANE_RGBX888;
2722 break;
2723 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2724 dspcntr |= DISPPLANE_BGRX101010;
2725 break;
2726 case DRM_FORMAT_XBGR2101010:
57779d06 2727 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2728 break;
2729 default:
baba133a 2730 BUG();
81255565 2731 }
57779d06 2732
f45651ba
VS		 2733 if (INTEL_INFO(dev)->gen >= 4 &&
2734 obj->tiling_mode != I915_TILING_NONE)
2735 dspcntr |= DISPPLANE_TILED;
81255565 2736
de1aa629
VS		 2737 if (IS_G4X(dev))
2738 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2739
b9897127 2740 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2741
c2c75131
DV		 2742 if (INTEL_INFO(dev)->gen >= 4) {
2743 intel_crtc->dspaddr_offset =
4e9a86b6
VS		 2744 intel_gen4_compute_page_offset(dev_priv,
2745 &x, &y, obj->tiling_mode,
b9897127 2746 pixel_size,
bc752862 2747 fb->pitches[0]);
c2c75131
DV		 2748 linear_offset -= intel_crtc->dspaddr_offset;
2749 } else {
e506a0c6 2750 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2751 }
e506a0c6 2752
8e7d688b 2753 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2754 dspcntr |= DISPPLANE_ROTATE_180;
2755
6e3c9717
ACO		 2756 x += (intel_crtc->config->pipe_src_w - 1);
2757 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2758
2759 /* Finding the last pixel of the last line of the display
2760 data and adding to linear_offset*/
2761 linear_offset +=
6e3c9717
ACO		 2762 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2763 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2764 }
2765
2766 I915_WRITE(reg, dspcntr);
2767
01f2c773 2768 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2769 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2770 I915_WRITE(DSPSURF(plane),
2771 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2772 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2773 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2774 } else
f343c5f6 2775 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2776 POSTING_READ(reg);
17638cd6
JB		 2777}
2778
29b9bde6
DV		 2779static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2780 struct drm_framebuffer *fb,
2781 int x, int y)
17638cd6
JB		 2782{
2783 struct drm_device *dev = crtc->dev;
2784 struct drm_i915_private *dev_priv = dev->dev_private;
2785 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2786 struct drm_plane *primary = crtc->primary;
2787 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2788 struct drm_i915_gem_object *obj;
17638cd6 2789 int plane = intel_crtc->plane;
e506a0c6 2790 unsigned long linear_offset;
17638cd6 2791 u32 dspcntr;
f45651ba 2792 u32 reg = DSPCNTR(plane);
48404c1e 2793 int pixel_size;
f45651ba 2794
b70709a6 2795 if (!visible || !fb) {
fdd508a6
VS		 2796 I915_WRITE(reg, 0);
2797 I915_WRITE(DSPSURF(plane), 0);
2798 POSTING_READ(reg);
2799 return;
2800 }
2801
c9ba6fad
VS		 2802 obj = intel_fb_obj(fb);
2803 if (WARN_ON(obj == NULL))
2804 return;
2805
2806 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2807
f45651ba
VS		 2808 dspcntr = DISPPLANE_GAMMA_ENABLE;
2809
fdd508a6 2810 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2811
2812 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2813 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2814
57779d06
VS		 2815 switch (fb->pixel_format) {
2816 case DRM_FORMAT_C8:
17638cd6
JB		 2817 dspcntr |= DISPPLANE_8BPP;
2818 break;
57779d06
VS		 2819 case DRM_FORMAT_RGB565:
2820 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2821 break;
57779d06 2822 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2823 dspcntr |= DISPPLANE_BGRX888;
2824 break;
2825 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2826 dspcntr |= DISPPLANE_RGBX888;
2827 break;
2828 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2829 dspcntr |= DISPPLANE_BGRX101010;
2830 break;
2831 case DRM_FORMAT_XBGR2101010:
57779d06 2832 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2833 break;
2834 default:
baba133a 2835 BUG();
17638cd6
JB		 2836 }
2837
2838 if (obj->tiling_mode != I915_TILING_NONE)
2839 dspcntr |= DISPPLANE_TILED;
17638cd6 2840
f45651ba 2841 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2842 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2843
b9897127 2844 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2845 intel_crtc->dspaddr_offset =
4e9a86b6
VS		 2846 intel_gen4_compute_page_offset(dev_priv,
2847 &x, &y, obj->tiling_mode,
b9897127 2848 pixel_size,
bc752862 2849 fb->pitches[0]);
c2c75131 2850 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2851 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2852 dspcntr |= DISPPLANE_ROTATE_180;
2853
2854 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2855 x += (intel_crtc->config->pipe_src_w - 1);
2856 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2857
2858 /* Finding the last pixel of the last line of the display
2859 data and adding to linear_offset*/
2860 linear_offset +=
6e3c9717
ACO		 2861 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2862 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2863 }
2864 }
2865
2866 I915_WRITE(reg, dspcntr);
17638cd6 2867
01f2c773 2868 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2869 I915_WRITE(DSPSURF(plane),
2870 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2871 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2872 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2873 } else {
2874 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2875 I915_WRITE(DSPLINOFF(plane), linear_offset);
2876 }
17638cd6 2877 POSTING_READ(reg);
17638cd6
JB		 2878}
2879
b321803d
DL		 2880u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2881 uint32_t pixel_format)
2882{
2883 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2884
2885 /*
2886 * The stride is either expressed as a multiple of 64 bytes
2887 * chunks for linear buffers or in number of tiles for tiled
2888 * buffers.
2889 */
2890 switch (fb_modifier) {
2891 case DRM_FORMAT_MOD_NONE:
2892 return 64;
2893 case I915_FORMAT_MOD_X_TILED:
2894 if (INTEL_INFO(dev)->gen == 2)
2895 return 128;
2896 return 512;
2897 case I915_FORMAT_MOD_Y_TILED:
2898 /* No need to check for old gens and Y tiling since this is
2899 * about the display engine and those will be blocked before
2900 * we get here.
2901 */
2902 return 128;
2903 case I915_FORMAT_MOD_Yf_TILED:
2904 if (bits_per_pixel == 8)
2905 return 64;
2906 else
2907 return 128;
2908 default:
2909 MISSING_CASE(fb_modifier);
2910 return 64;
2911 }
2912}
2913
121920fa
TU		 2914unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2915 struct drm_i915_gem_object *obj)
2916{
9abc4648 2917 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
121920fa
TU		 2918
2919 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2920 view = &i915_ggtt_view_rotated;
121920fa
TU		 2921
2922 return i915_gem_obj_ggtt_offset_view(obj, view);
2923}
2924
a1b2278e
CK		 2925/*
2926 * This function detaches (aka. unbinds) unused scalers in hardware
2927 */
0583236e 2928static void skl_detach_scalers(struct intel_crtc *intel_crtc)
a1b2278e
CK		 2929{
2930 struct drm_device *dev;
2931 struct drm_i915_private *dev_priv;
2932 struct intel_crtc_scaler_state *scaler_state;
2933 int i;
2934
a1b2278e
CK		 2935 dev = intel_crtc->base.dev;
2936 dev_priv = dev->dev_private;
2937 scaler_state = &intel_crtc->config->scaler_state;
2938
2939 /* loop through and disable scalers that aren't in use */
2940 for (i = 0; i < intel_crtc->num_scalers; i++) {
2941 if (!scaler_state->scalers[i].in_use) {
2942 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2943 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2944 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2945 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2946 intel_crtc->base.base.id, intel_crtc->pipe, i);
2947 }
2948 }
2949}
2950
6156a456 2951u32 skl_plane_ctl_format(uint32_t pixel_format)
70d21f0e 2952{
6156a456 2953 switch (pixel_format) {
d161cf7a 2954 case DRM_FORMAT_C8:
c34ce3d1 2955 return PLANE_CTL_FORMAT_INDEXED;
70d21f0e 2956 case DRM_FORMAT_RGB565:
c34ce3d1 2957 return PLANE_CTL_FORMAT_RGB_565;
70d21f0e 2958 case DRM_FORMAT_XBGR8888:
c34ce3d1 2959 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
6156a456 2960 case DRM_FORMAT_XRGB8888:
c34ce3d1 2961 return PLANE_CTL_FORMAT_XRGB_8888;
6156a456
CK		 2962 /*
2963 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2964 * to be already pre-multiplied. We need to add a knob (or a different
2965 * DRM_FORMAT) for user-space to configure that.
2966 */
f75fb42a 2967 case DRM_FORMAT_ABGR8888:
c34ce3d1 2968 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
6156a456 2969 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
6156a456 2970 case DRM_FORMAT_ARGB8888:
c34ce3d1 2971 return PLANE_CTL_FORMAT_XRGB_8888 |
6156a456 2972 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
70d21f0e 2973 case DRM_FORMAT_XRGB2101010:
c34ce3d1 2974 return PLANE_CTL_FORMAT_XRGB_2101010;
70d21f0e 2975 case DRM_FORMAT_XBGR2101010:
c34ce3d1 2976 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
6156a456 2977 case DRM_FORMAT_YUYV:
c34ce3d1 2978 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
6156a456 2979 case DRM_FORMAT_YVYU:
c34ce3d1 2980 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
6156a456 2981 case DRM_FORMAT_UYVY:
c34ce3d1 2982 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
6156a456 2983 case DRM_FORMAT_VYUY:
c34ce3d1 2984 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
70d21f0e 2985 default:
4249eeef 2986 MISSING_CASE(pixel_format);
70d21f0e 2987 }
8cfcba41 2988
c34ce3d1 2989 return 0;
6156a456 2990}
70d21f0e 2991
6156a456
CK		 2992u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2993{
6156a456 2994 switch (fb_modifier) {
30af77c4 2995 case DRM_FORMAT_MOD_NONE:
70d21f0e 2996 break;
30af77c4 2997 case I915_FORMAT_MOD_X_TILED:
c34ce3d1 2998 return PLANE_CTL_TILED_X;
b321803d 2999 case I915_FORMAT_MOD_Y_TILED:
c34ce3d1 3000 return PLANE_CTL_TILED_Y;
b321803d 3001 case I915_FORMAT_MOD_Yf_TILED:
c34ce3d1 3002 return PLANE_CTL_TILED_YF;
70d21f0e 3003 default:
6156a456 3004 MISSING_CASE(fb_modifier);
70d21f0e 3005 }
8cfcba41 3006
c34ce3d1 3007 return 0;
6156a456 3008}
70d21f0e 3009
6156a456
CK		 3010u32 skl_plane_ctl_rotation(unsigned int rotation)
3011{
3b7a5119 3012 switch (rotation) {
6156a456
CK		 3013 case BIT(DRM_ROTATE_0):
3014 break;
1e8df167
SJ		 3015 /*
3016 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3017 * while i915 HW rotation is clockwise, thats why this swapping.
3018 */
3b7a5119 3019 case BIT(DRM_ROTATE_90):
1e8df167 3020 return PLANE_CTL_ROTATE_270;
3b7a5119 3021 case BIT(DRM_ROTATE_180):
c34ce3d1 3022 return PLANE_CTL_ROTATE_180;
3b7a5119 3023 case BIT(DRM_ROTATE_270):
1e8df167 3024 return PLANE_CTL_ROTATE_90;
6156a456
CK		 3025 default:
3026 MISSING_CASE(rotation);
3027 }
3028
c34ce3d1 3029 return 0;
6156a456
CK		 3030}
3031
3032static void skylake_update_primary_plane(struct drm_crtc *crtc,
3033 struct drm_framebuffer *fb,
3034 int x, int y)
3035{
3036 struct drm_device *dev = crtc->dev;
3037 struct drm_i915_private *dev_priv = dev->dev_private;
3038 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 3039 struct drm_plane *plane = crtc->primary;
3040 bool visible = to_intel_plane_state(plane->state)->visible;
6156a456
CK		 3041 struct drm_i915_gem_object *obj;
3042 int pipe = intel_crtc->pipe;
3043 u32 plane_ctl, stride_div, stride;
3044 u32 tile_height, plane_offset, plane_size;
3045 unsigned int rotation;
3046 int x_offset, y_offset;
3047 unsigned long surf_addr;
6156a456
CK		 3048 struct intel_crtc_state *crtc_state = intel_crtc->config;
3049 struct intel_plane_state *plane_state;
3050 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3051 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3052 int scaler_id = -1;
3053
6156a456
CK		 3054 plane_state = to_intel_plane_state(plane->state);
3055
b70709a6 3056 if (!visible || !fb) {
6156a456
CK		 3057 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3058 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3059 POSTING_READ(PLANE_CTL(pipe, 0));
3060 return;
3b7a5119 3061 }
70d21f0e 3062
6156a456
CK		 3063 plane_ctl = PLANE_CTL_ENABLE |
3064 PLANE_CTL_PIPE_GAMMA_ENABLE |
3065 PLANE_CTL_PIPE_CSC_ENABLE;
3066
3067 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3068 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3069 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3070
3071 rotation = plane->state->rotation;
3072 plane_ctl |= skl_plane_ctl_rotation(rotation);
3073
b321803d
DL		 3074 obj = intel_fb_obj(fb);
3075 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3076 fb->pixel_format);
3b7a5119
SJ		 3077 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3078
6156a456
CK		 3079 /*
3080 * FIXME: intel_plane_state->src, dst aren't set when transitional
3081 * update_plane helpers are called from legacy paths.
3082 * Once full atomic crtc is available, below check can be avoided.
3083 */
3084 if (drm_rect_width(&plane_state->src)) {
3085 scaler_id = plane_state->scaler_id;
3086 src_x = plane_state->src.x1 >> 16;
3087 src_y = plane_state->src.y1 >> 16;
3088 src_w = drm_rect_width(&plane_state->src) >> 16;
3089 src_h = drm_rect_height(&plane_state->src) >> 16;
3090 dst_x = plane_state->dst.x1;
3091 dst_y = plane_state->dst.y1;
3092 dst_w = drm_rect_width(&plane_state->dst);
3093 dst_h = drm_rect_height(&plane_state->dst);
3094
3095 WARN_ON(x != src_x || y != src_y);
3096 } else {
3097 src_w = intel_crtc->config->pipe_src_w;
3098 src_h = intel_crtc->config->pipe_src_h;
3099 }
3100
3b7a5119
SJ		 3101 if (intel_rotation_90_or_270(rotation)) {
3102 /* stride = Surface height in tiles */
2614f17d 3103 tile_height = intel_tile_height(dev, fb->pixel_format,
3b7a5119
SJ		 3104 fb->modifier[0]);
3105 stride = DIV_ROUND_UP(fb->height, tile_height);
6156a456 3106 x_offset = stride * tile_height - y - src_h;
3b7a5119 3107 y_offset = x;
6156a456 3108 plane_size = (src_w - 1) << 16 | (src_h - 1);
3b7a5119
SJ		 3109 } else {
3110 stride = fb->pitches[0] / stride_div;
3111 x_offset = x;
3112 y_offset = y;
6156a456 3113 plane_size = (src_h - 1) << 16 | (src_w - 1);
3b7a5119
SJ		 3114 }
3115 plane_offset = y_offset << 16 | x_offset;
b321803d 3116
70d21f0e 3117 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3b7a5119
SJ		 3118 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3119 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3120 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
6156a456
CK		 3121
3122 if (scaler_id >= 0) {
3123 uint32_t ps_ctrl = 0;
3124
3125 WARN_ON(!dst_w || !dst_h);
3126 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3127 crtc_state->scaler_state.scalers[scaler_id].mode;
3128 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3129 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3130 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3131 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3132 I915_WRITE(PLANE_POS(pipe, 0), 0);
3133 } else {
3134 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3135 }
3136
121920fa 3137 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3138
3139 POSTING_READ(PLANE_SURF(pipe, 0));
3140}
3141
17638cd6
JB		 3142/* Assume fb object is pinned & idle & fenced and just update base pointers */
3143static int
3144intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3145 int x, int y, enum mode_set_atomic state)
3146{
3147 struct drm_device *dev = crtc->dev;
3148 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3149
6b8e6ed0
CW		 3150 if (dev_priv->display.disable_fbc)
3151 dev_priv->display.disable_fbc(dev);
81255565 3152
29b9bde6
DV		 3153 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3154
3155 return 0;
81255565
JB		 3156}
3157
7514747d 3158static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3159{
96a02917
VS		 3160 struct drm_crtc *crtc;
3161
70e1e0ec 3162 for_each_crtc(dev, crtc) {
96a02917
VS		 3163 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3164 enum plane plane = intel_crtc->plane;
3165
3166 intel_prepare_page_flip(dev, plane);
3167 intel_finish_page_flip_plane(dev, plane);
3168 }
7514747d
VS		 3169}
3170
3171static void intel_update_primary_planes(struct drm_device *dev)
3172{
3173 struct drm_i915_private *dev_priv = dev->dev_private;
3174 struct drm_crtc *crtc;
96a02917 3175
70e1e0ec 3176 for_each_crtc(dev, crtc) {
96a02917
VS		 3177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3178
51fd371b 3179 drm_modeset_lock(&crtc->mutex, NULL);
947fdaad
CW		 3180 /*
3181 * FIXME: Once we have proper support for primary planes (and
3182 * disabling them without disabling the entire crtc) allow again
66e514c1 3183 * a NULL crtc->primary->fb.
947fdaad 3184 */
f4510a27 3185 if (intel_crtc->active && crtc->primary->fb)
262ca2b0 3186 dev_priv->display.update_primary_plane(crtc,
66e514c1 3187 crtc->primary->fb,
262ca2b0
MR		 3188 crtc->x,
3189 crtc->y);
51fd371b 3190 drm_modeset_unlock(&crtc->mutex);
96a02917
VS		 3191 }
3192}
3193
7514747d
VS		 3194void intel_prepare_reset(struct drm_device *dev)
3195{
3196 /* no reset support for gen2 */
3197 if (IS_GEN2(dev))
3198 return;
3199
3200 /* reset doesn't touch the display */
3201 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3202 return;
3203
3204 drm_modeset_lock_all(dev);
f98ce92f
VS		 3205 /*
3206 * Disabling the crtcs gracefully seems nicer. Also the
3207 * g33 docs say we should at least disable all the planes.
3208 */
6b72d486 3209 intel_display_suspend(dev);
7514747d
VS		 3210}
3211
3212void intel_finish_reset(struct drm_device *dev)
3213{
3214 struct drm_i915_private *dev_priv = to_i915(dev);
3215
3216 /*
3217 * Flips in the rings will be nuked by the reset,
3218 * so complete all pending flips so that user space
3219 * will get its events and not get stuck.
3220 */
3221 intel_complete_page_flips(dev);
3222
3223 /* no reset support for gen2 */
3224 if (IS_GEN2(dev))
3225 return;
3226
3227 /* reset doesn't touch the display */
3228 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3229 /*
3230 * Flips in the rings have been nuked by the reset,
3231 * so update the base address of all primary
3232 * planes to the the last fb to make sure we're
3233 * showing the correct fb after a reset.
3234 */
3235 intel_update_primary_planes(dev);
3236 return;
3237 }
3238
3239 /*
3240 * The display has been reset as well,
3241 * so need a full re-initialization.
3242 */
3243 intel_runtime_pm_disable_interrupts(dev_priv);
3244 intel_runtime_pm_enable_interrupts(dev_priv);
3245
3246 intel_modeset_init_hw(dev);
3247
3248 spin_lock_irq(&dev_priv->irq_lock);
3249 if (dev_priv->display.hpd_irq_setup)
3250 dev_priv->display.hpd_irq_setup(dev);
3251 spin_unlock_irq(&dev_priv->irq_lock);
3252
3253 intel_modeset_setup_hw_state(dev, true);
3254
3255 intel_hpd_init(dev_priv);
3256
3257 drm_modeset_unlock_all(dev);
3258}
3259
2e2f351d 3260static void
14667a4b
CW		 3261intel_finish_fb(struct drm_framebuffer *old_fb)
3262{
2ff8fde1 3263 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2e2f351d 3264 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14667a4b
CW		 3265 bool was_interruptible = dev_priv->mm.interruptible;
3266 int ret;
3267
14667a4b
CW		 3268 /* Big Hammer, we also need to ensure that any pending
3269 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3270 * current scanout is retired before unpinning the old
2e2f351d
CW		 3271 * framebuffer. Note that we rely on userspace rendering
3272 * into the buffer attached to the pipe they are waiting
3273 * on. If not, userspace generates a GPU hang with IPEHR
3274 * point to the MI_WAIT_FOR_EVENT.
14667a4b
CW		 3275 *
3276 * This should only fail upon a hung GPU, in which case we
3277 * can safely continue.
3278 */
3279 dev_priv->mm.interruptible = false;
2e2f351d 3280 ret = i915_gem_object_wait_rendering(obj, true);
14667a4b
CW		 3281 dev_priv->mm.interruptible = was_interruptible;
3282
2e2f351d 3283 WARN_ON(ret);
14667a4b
CW		 3284}
3285
7d5e3799
CW		 3286static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3287{
3288 struct drm_device *dev = crtc->dev;
3289 struct drm_i915_private *dev_priv = dev->dev_private;
3290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3291 bool pending;
3292
3293 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3294 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3295 return false;
3296
5e2d7afc 3297 spin_lock_irq(&dev->event_lock);
7d5e3799 3298 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3299 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3300
3301 return pending;
3302}
3303
e30e8f75
GP		 3304static void intel_update_pipe_size(struct intel_crtc *crtc)
3305{
3306 struct drm_device *dev = crtc->base.dev;
3307 struct drm_i915_private *dev_priv = dev->dev_private;
3308 const struct drm_display_mode *adjusted_mode;
3309
3310 if (!i915.fastboot)
3311 return;
3312
3313 /*
3314 * Update pipe size and adjust fitter if needed: the reason for this is
3315 * that in compute_mode_changes we check the native mode (not the pfit
3316 * mode) to see if we can flip rather than do a full mode set. In the
3317 * fastboot case, we'll flip, but if we don't update the pipesrc and
3318 * pfit state, we'll end up with a big fb scanned out into the wrong
3319 * sized surface.
3320 *
3321 * To fix this properly, we need to hoist the checks up into
3322 * compute_mode_changes (or above), check the actual pfit state and
3323 * whether the platform allows pfit disable with pipe active, and only
3324 * then update the pipesrc and pfit state, even on the flip path.
3325 */
3326
6e3c9717 3327 adjusted_mode = &crtc->config->base.adjusted_mode;
e30e8f75
GP		 3328
3329 I915_WRITE(PIPESRC(crtc->pipe),
3330 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3331 (adjusted_mode->crtc_vdisplay - 1));
6e3c9717 3332 if (!crtc->config->pch_pfit.enabled &&
409ee761
ACO		 3333 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3334 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
e30e8f75
GP		 3335 I915_WRITE(PF_CTL(crtc->pipe), 0);
3336 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3337 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3338 }
6e3c9717
ACO		 3339 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3340 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
e30e8f75
GP		 3341}
3342
5e84e1a4
ZW		 3343static void intel_fdi_normal_train(struct drm_crtc *crtc)
3344{
3345 struct drm_device *dev = crtc->dev;
3346 struct drm_i915_private *dev_priv = dev->dev_private;
3347 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3348 int pipe = intel_crtc->pipe;
3349 u32 reg, temp;
3350
3351 /* enable normal train */
3352 reg = FDI_TX_CTL(pipe);
3353 temp = I915_READ(reg);
61e499bf 3354 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3355 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3356 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3357 } else {
3358 temp &= ~FDI_LINK_TRAIN_NONE;
3359 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3360 }
5e84e1a4
ZW		 3361 I915_WRITE(reg, temp);
3362
3363 reg = FDI_RX_CTL(pipe);
3364 temp = I915_READ(reg);
3365 if (HAS_PCH_CPT(dev)) {
3366 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3367 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3368 } else {
3369 temp &= ~FDI_LINK_TRAIN_NONE;
3370 temp |= FDI_LINK_TRAIN_NONE;
3371 }
3372 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3373
3374 /* wait one idle pattern time */
3375 POSTING_READ(reg);
3376 udelay(1000);
357555c0
JB		 3377
3378 /* IVB wants error correction enabled */
3379 if (IS_IVYBRIDGE(dev))
3380 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3381 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3382}
3383
8db9d77b
ZW		 3384/* The FDI link training functions for ILK/Ibexpeak. */
3385static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3386{
3387 struct drm_device *dev = crtc->dev;
3388 struct drm_i915_private *dev_priv = dev->dev_private;
3389 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3390 int pipe = intel_crtc->pipe;
5eddb70b 3391 u32 reg, temp, tries;
8db9d77b 3392
1c8562f6 3393 /* FDI needs bits from pipe first */
0fc932b8 3394 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3395
e1a44743
AJ		 3396 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3397 for train result */
5eddb70b
CW		 3398 reg = FDI_RX_IMR(pipe);
3399 temp = I915_READ(reg);
e1a44743
AJ		 3400 temp &= ~FDI_RX_SYMBOL_LOCK;
3401 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3402 I915_WRITE(reg, temp);
3403 I915_READ(reg);
e1a44743
AJ		 3404 udelay(150);
3405
8db9d77b 3406 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3407 reg = FDI_TX_CTL(pipe);
3408 temp = I915_READ(reg);
627eb5a3 3409 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3410 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3411 temp &= ~FDI_LINK_TRAIN_NONE;
3412 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3413 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3414
5eddb70b
CW		 3415 reg = FDI_RX_CTL(pipe);
3416 temp = I915_READ(reg);
8db9d77b
ZW		 3417 temp &= ~FDI_LINK_TRAIN_NONE;
3418 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3419 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3420
3421 POSTING_READ(reg);
8db9d77b
ZW		 3422 udelay(150);
3423
5b2adf89 3424 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3425 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3426 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3427 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3428
5eddb70b 3429 reg = FDI_RX_IIR(pipe);
e1a44743 3430 for (tries = 0; tries < 5; tries++) {
5eddb70b 3431 temp = I915_READ(reg);
8db9d77b
ZW		 3432 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3433
3434 if ((temp & FDI_RX_BIT_LOCK)) {
3435 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3436 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3437 break;
3438 }
8db9d77b 3439 }
e1a44743 3440 if (tries == 5)
5eddb70b 3441 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3442
3443 /* Train 2 */
5eddb70b
CW		 3444 reg = FDI_TX_CTL(pipe);
3445 temp = I915_READ(reg);
8db9d77b
ZW		 3446 temp &= ~FDI_LINK_TRAIN_NONE;
3447 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3448 I915_WRITE(reg, temp);
8db9d77b 3449
5eddb70b
CW		 3450 reg = FDI_RX_CTL(pipe);
3451 temp = I915_READ(reg);
8db9d77b
ZW		 3452 temp &= ~FDI_LINK_TRAIN_NONE;
3453 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3454 I915_WRITE(reg, temp);
8db9d77b 3455
5eddb70b
CW		 3456 POSTING_READ(reg);
3457 udelay(150);
8db9d77b 3458
5eddb70b 3459 reg = FDI_RX_IIR(pipe);
e1a44743 3460 for (tries = 0; tries < 5; tries++) {
5eddb70b 3461 temp = I915_READ(reg);
8db9d77b
ZW		 3462 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3463
3464 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3465 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3466 DRM_DEBUG_KMS("FDI train 2 done.\n");
3467 break;
3468 }
8db9d77b 3469 }
e1a44743 3470 if (tries == 5)
5eddb70b 3471 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3472
3473 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3474
8db9d77b
ZW		 3475}
3476
0206e353 3477static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3478 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3479 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3480 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3481 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3482};
3483
3484/* The FDI link training functions for SNB/Cougarpoint. */
3485static void gen6_fdi_link_train(struct drm_crtc *crtc)
3486{
3487 struct drm_device *dev = crtc->dev;
3488 struct drm_i915_private *dev_priv = dev->dev_private;
3489 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3490 int pipe = intel_crtc->pipe;
fa37d39e 3491 u32 reg, temp, i, retry;
8db9d77b 3492
e1a44743
AJ		 3493 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3494 for train result */
5eddb70b
CW		 3495 reg = FDI_RX_IMR(pipe);
3496 temp = I915_READ(reg);
e1a44743
AJ		 3497 temp &= ~FDI_RX_SYMBOL_LOCK;
3498 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3499 I915_WRITE(reg, temp);
3500
3501 POSTING_READ(reg);
e1a44743
AJ		 3502 udelay(150);
3503
8db9d77b 3504 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3505 reg = FDI_TX_CTL(pipe);
3506 temp = I915_READ(reg);
627eb5a3 3507 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3508 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3509 temp &= ~FDI_LINK_TRAIN_NONE;
3510 temp |= FDI_LINK_TRAIN_PATTERN_1;
3511 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3512 /* SNB-B */
3513 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3514 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3515
d74cf324
DV		 3516 I915_WRITE(FDI_RX_MISC(pipe),
3517 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3518
5eddb70b
CW		 3519 reg = FDI_RX_CTL(pipe);
3520 temp = I915_READ(reg);
8db9d77b
ZW		 3521 if (HAS_PCH_CPT(dev)) {
3522 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3523 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3524 } else {
3525 temp &= ~FDI_LINK_TRAIN_NONE;
3526 temp |= FDI_LINK_TRAIN_PATTERN_1;
3527 }
5eddb70b
CW		 3528 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3529
3530 POSTING_READ(reg);
8db9d77b
ZW		 3531 udelay(150);
3532
0206e353 3533 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3534 reg = FDI_TX_CTL(pipe);
3535 temp = I915_READ(reg);
8db9d77b
ZW		 3536 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3537 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3538 I915_WRITE(reg, temp);
3539
3540 POSTING_READ(reg);
8db9d77b
ZW		 3541 udelay(500);
3542
fa37d39e
SP		 3543 for (retry = 0; retry < 5; retry++) {
3544 reg = FDI_RX_IIR(pipe);
3545 temp = I915_READ(reg);
3546 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3547 if (temp & FDI_RX_BIT_LOCK) {
3548 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3549 DRM_DEBUG_KMS("FDI train 1 done.\n");
3550 break;
3551 }
3552 udelay(50);
8db9d77b 3553 }
fa37d39e
SP		 3554 if (retry < 5)
3555 break;
8db9d77b
ZW		 3556 }
3557 if (i == 4)
5eddb70b 3558 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3559
3560 /* Train 2 */
5eddb70b
CW		 3561 reg = FDI_TX_CTL(pipe);
3562 temp = I915_READ(reg);
8db9d77b
ZW		 3563 temp &= ~FDI_LINK_TRAIN_NONE;
3564 temp |= FDI_LINK_TRAIN_PATTERN_2;
3565 if (IS_GEN6(dev)) {
3566 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3567 /* SNB-B */
3568 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3569 }
5eddb70b 3570 I915_WRITE(reg, temp);
8db9d77b 3571
5eddb70b
CW		 3572 reg = FDI_RX_CTL(pipe);
3573 temp = I915_READ(reg);
8db9d77b
ZW		 3574 if (HAS_PCH_CPT(dev)) {
3575 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3576 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3577 } else {
3578 temp &= ~FDI_LINK_TRAIN_NONE;
3579 temp |= FDI_LINK_TRAIN_PATTERN_2;
3580 }
5eddb70b
CW		 3581 I915_WRITE(reg, temp);
3582
3583 POSTING_READ(reg);
8db9d77b
ZW		 3584 udelay(150);
3585
0206e353 3586 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3587 reg = FDI_TX_CTL(pipe);
3588 temp = I915_READ(reg);
8db9d77b
ZW		 3589 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3590 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3591 I915_WRITE(reg, temp);
3592
3593 POSTING_READ(reg);
8db9d77b
ZW		 3594 udelay(500);
3595
fa37d39e
SP		 3596 for (retry = 0; retry < 5; retry++) {
3597 reg = FDI_RX_IIR(pipe);
3598 temp = I915_READ(reg);
3599 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3600 if (temp & FDI_RX_SYMBOL_LOCK) {
3601 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3602 DRM_DEBUG_KMS("FDI train 2 done.\n");
3603 break;
3604 }
3605 udelay(50);
8db9d77b 3606 }
fa37d39e
SP		 3607 if (retry < 5)
3608 break;
8db9d77b
ZW		 3609 }
3610 if (i == 4)
5eddb70b 3611 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3612
3613 DRM_DEBUG_KMS("FDI train done.\n");
3614}
3615
357555c0
JB		 3616/* Manual link training for Ivy Bridge A0 parts */
3617static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3618{
3619 struct drm_device *dev = crtc->dev;
3620 struct drm_i915_private *dev_priv = dev->dev_private;
3621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3622 int pipe = intel_crtc->pipe;
139ccd3f 3623 u32 reg, temp, i, j;
357555c0
JB		 3624
3625 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3626 for train result */
3627 reg = FDI_RX_IMR(pipe);
3628 temp = I915_READ(reg);
3629 temp &= ~FDI_RX_SYMBOL_LOCK;
3630 temp &= ~FDI_RX_BIT_LOCK;
3631 I915_WRITE(reg, temp);
3632
3633 POSTING_READ(reg);
3634 udelay(150);
3635
01a415fd
DV		 3636 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3637 I915_READ(FDI_RX_IIR(pipe)));
3638
139ccd3f
JB		 3639 /* Try each vswing and preemphasis setting twice before moving on */
3640 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3641 /* disable first in case we need to retry */
3642 reg = FDI_TX_CTL(pipe);
3643 temp = I915_READ(reg);
3644 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3645 temp &= ~FDI_TX_ENABLE;
3646 I915_WRITE(reg, temp);
357555c0 3647
139ccd3f
JB		 3648 reg = FDI_RX_CTL(pipe);
3649 temp = I915_READ(reg);
3650 temp &= ~FDI_LINK_TRAIN_AUTO;
3651 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3652 temp &= ~FDI_RX_ENABLE;
3653 I915_WRITE(reg, temp);
357555c0 3654
139ccd3f 3655 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3656 reg = FDI_TX_CTL(pipe);
3657 temp = I915_READ(reg);
139ccd3f 3658 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3659 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3660 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3661 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3662 temp |= snb_b_fdi_train_param[j/2];
3663 temp |= FDI_COMPOSITE_SYNC;
3664 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3665
139ccd3f
JB		 3666 I915_WRITE(FDI_RX_MISC(pipe),
3667 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3668
139ccd3f 3669 reg = FDI_RX_CTL(pipe);
357555c0 3670 temp = I915_READ(reg);
139ccd3f
JB		 3671 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3672 temp |= FDI_COMPOSITE_SYNC;
3673 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3674
139ccd3f
JB		 3675 POSTING_READ(reg);
3676 udelay(1); /* should be 0.5us */
357555c0 3677
139ccd3f
JB		 3678 for (i = 0; i < 4; i++) {
3679 reg = FDI_RX_IIR(pipe);
3680 temp = I915_READ(reg);
3681 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3682
139ccd3f
JB		 3683 if (temp & FDI_RX_BIT_LOCK ||
3684 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3685 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3686 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3687 i);
3688 break;
3689 }
3690 udelay(1); /* should be 0.5us */
3691 }
3692 if (i == 4) {
3693 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3694 continue;
3695 }
357555c0 3696
139ccd3f 3697 /* Train 2 */
357555c0
JB		 3698 reg = FDI_TX_CTL(pipe);
3699 temp = I915_READ(reg);
139ccd3f
JB		 3700 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3701 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3702 I915_WRITE(reg, temp);
3703
3704 reg = FDI_RX_CTL(pipe);
3705 temp = I915_READ(reg);
3706 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3707 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3708 I915_WRITE(reg, temp);
3709
3710 POSTING_READ(reg);
139ccd3f 3711 udelay(2); /* should be 1.5us */
357555c0 3712
139ccd3f
JB		 3713 for (i = 0; i < 4; i++) {
3714 reg = FDI_RX_IIR(pipe);
3715 temp = I915_READ(reg);
3716 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3717
139ccd3f
JB		 3718 if (temp & FDI_RX_SYMBOL_LOCK ||
3719 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3720 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3721 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3722 i);
3723 goto train_done;
3724 }
3725 udelay(2); /* should be 1.5us */
357555c0 3726 }
139ccd3f
JB		 3727 if (i == 4)
3728 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3729 }
357555c0 3730
139ccd3f 3731train_done:
357555c0
JB		 3732 DRM_DEBUG_KMS("FDI train done.\n");
3733}
3734
88cefb6c 3735static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3736{
88cefb6c 3737 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3738 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3739 int pipe = intel_crtc->pipe;
5eddb70b 3740 u32 reg, temp;
79e53945 3741
c64e311e 3742
c98e9dcf 3743 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3744 reg = FDI_RX_CTL(pipe);
3745 temp = I915_READ(reg);
627eb5a3 3746 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3747 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3748 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3749 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3750
3751 POSTING_READ(reg);
c98e9dcf
JB		 3752 udelay(200);
3753
3754 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3755 temp = I915_READ(reg);
3756 I915_WRITE(reg, temp | FDI_PCDCLK);
3757
3758 POSTING_READ(reg);
c98e9dcf
JB		 3759 udelay(200);
3760
20749730
PZ		 3761 /* Enable CPU FDI TX PLL, always on for Ironlake */
3762 reg = FDI_TX_CTL(pipe);
3763 temp = I915_READ(reg);
3764 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3765 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3766
20749730
PZ		 3767 POSTING_READ(reg);
3768 udelay(100);
6be4a607 3769 }
0e23b99d
JB		 3770}
3771
88cefb6c
DV		 3772static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3773{
3774 struct drm_device *dev = intel_crtc->base.dev;
3775 struct drm_i915_private *dev_priv = dev->dev_private;
3776 int pipe = intel_crtc->pipe;
3777 u32 reg, temp;
3778
3779 /* Switch from PCDclk to Rawclk */
3780 reg = FDI_RX_CTL(pipe);
3781 temp = I915_READ(reg);
3782 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3783
3784 /* Disable CPU FDI TX PLL */
3785 reg = FDI_TX_CTL(pipe);
3786 temp = I915_READ(reg);
3787 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3788
3789 POSTING_READ(reg);
3790 udelay(100);
3791
3792 reg = FDI_RX_CTL(pipe);
3793 temp = I915_READ(reg);
3794 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3795
3796 /* Wait for the clocks to turn off. */
3797 POSTING_READ(reg);
3798 udelay(100);
3799}
3800
0fc932b8
JB		 3801static void ironlake_fdi_disable(struct drm_crtc *crtc)
3802{
3803 struct drm_device *dev = crtc->dev;
3804 struct drm_i915_private *dev_priv = dev->dev_private;
3805 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3806 int pipe = intel_crtc->pipe;
3807 u32 reg, temp;
3808
3809 /* disable CPU FDI tx and PCH FDI rx */
3810 reg = FDI_TX_CTL(pipe);
3811 temp = I915_READ(reg);
3812 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3813 POSTING_READ(reg);
3814
3815 reg = FDI_RX_CTL(pipe);
3816 temp = I915_READ(reg);
3817 temp &= ~(0x7 << 16);
dfd07d72 3818 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3819 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3820
3821 POSTING_READ(reg);
3822 udelay(100);
3823
3824 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3825 if (HAS_PCH_IBX(dev))
6f06ce18 3826 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3827
3828 /* still set train pattern 1 */
3829 reg = FDI_TX_CTL(pipe);
3830 temp = I915_READ(reg);
3831 temp &= ~FDI_LINK_TRAIN_NONE;
3832 temp |= FDI_LINK_TRAIN_PATTERN_1;
3833 I915_WRITE(reg, temp);
3834
3835 reg = FDI_RX_CTL(pipe);
3836 temp = I915_READ(reg);
3837 if (HAS_PCH_CPT(dev)) {
3838 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3839 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3840 } else {
3841 temp &= ~FDI_LINK_TRAIN_NONE;
3842 temp |= FDI_LINK_TRAIN_PATTERN_1;
3843 }
3844 /* BPC in FDI rx is consistent with that in PIPECONF */
3845 temp &= ~(0x07 << 16);
dfd07d72 3846 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3847 I915_WRITE(reg, temp);
3848
3849 POSTING_READ(reg);
3850 udelay(100);
3851}
3852
5dce5b93
CW		 3853bool intel_has_pending_fb_unpin(struct drm_device *dev)
3854{
3855 struct intel_crtc *crtc;
3856
3857 /* Note that we don't need to be called with mode_config.lock here
3858 * as our list of CRTC objects is static for the lifetime of the
3859 * device and so cannot disappear as we iterate. Similarly, we can
3860 * happily treat the predicates as racy, atomic checks as userspace
3861 * cannot claim and pin a new fb without at least acquring the
3862 * struct_mutex and so serialising with us.
3863 */
d3fcc808 3864 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3865 if (atomic_read(&crtc->unpin_work_count) == 0)
3866 continue;
3867
3868 if (crtc->unpin_work)
3869 intel_wait_for_vblank(dev, crtc->pipe);
3870
3871 return true;
3872 }
3873
3874 return false;
3875}
3876
d6bbafa1
CW		 3877static void page_flip_completed(struct intel_crtc *intel_crtc)
3878{
3879 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3880 struct intel_unpin_work *work = intel_crtc->unpin_work;
3881
3882 /* ensure that the unpin work is consistent wrt ->pending. */
3883 smp_rmb();
3884 intel_crtc->unpin_work = NULL;
3885
3886 if (work->event)
3887 drm_send_vblank_event(intel_crtc->base.dev,
3888 intel_crtc->pipe,
3889 work->event);
3890
3891 drm_crtc_vblank_put(&intel_crtc->base);
3892
3893 wake_up_all(&dev_priv->pending_flip_queue);
3894 queue_work(dev_priv->wq, &work->work);
3895
3896 trace_i915_flip_complete(intel_crtc->plane,
3897 work->pending_flip_obj);
3898}
3899
46a55d30 3900void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3901{
0f91128d 3902 struct drm_device *dev = crtc->dev;
5bb61643 3903 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3904
2c10d571 3905 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW		 3906 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3907 !intel_crtc_has_pending_flip(crtc),
3908 60*HZ) == 0)) {
3909 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3910
5e2d7afc 3911 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3912 if (intel_crtc->unpin_work) {
3913 WARN_ONCE(1, "Removing stuck page flip\n");
3914 page_flip_completed(intel_crtc);
3915 }
5e2d7afc 3916 spin_unlock_irq(&dev->event_lock);
9c787942 3917 }
5bb61643 3918
975d568a
CW		 3919 if (crtc->primary->fb) {
3920 mutex_lock(&dev->struct_mutex);
3921 intel_finish_fb(crtc->primary->fb);
3922 mutex_unlock(&dev->struct_mutex);
3923 }
e6c3a2a6
CW		 3924}
3925
e615efe4
ED		 3926/* Program iCLKIP clock to the desired frequency */
3927static void lpt_program_iclkip(struct drm_crtc *crtc)
3928{
3929 struct drm_device *dev = crtc->dev;
3930 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3931 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3932 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3933 u32 temp;
3934
a580516d 3935 mutex_lock(&dev_priv->sb_lock);
09153000 3936
e615efe4
ED		 3937 /* It is necessary to ungate the pixclk gate prior to programming
3938 * the divisors, and gate it back when it is done.
3939 */
3940 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3941
3942 /* Disable SSCCTL */
3943 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3944 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3945 SBI_SSCCTL_DISABLE,
3946 SBI_ICLK);
e615efe4
ED		 3947
3948 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3949 if (clock == 20000) {
e615efe4
ED		 3950 auxdiv = 1;
3951 divsel = 0x41;
3952 phaseinc = 0x20;
3953 } else {
3954 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3955 * but the adjusted_mode->crtc_clock in in KHz. To get the
3956 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3957 * convert the virtual clock precision to KHz here for higher
3958 * precision.
3959 */
3960 u32 iclk_virtual_root_freq = 172800 * 1000;
3961 u32 iclk_pi_range = 64;
3962 u32 desired_divisor, msb_divisor_value, pi_value;
3963
12d7ceed 3964 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3965 msb_divisor_value = desired_divisor / iclk_pi_range;
3966 pi_value = desired_divisor % iclk_pi_range;
3967
3968 auxdiv = 0;
3969 divsel = msb_divisor_value - 2;
3970 phaseinc = pi_value;
3971 }
3972
3973 /* This should not happen with any sane values */
3974 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3975 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3976 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3977 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3978
3979 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3980 clock,
e615efe4
ED		 3981 auxdiv,
3982 divsel,
3983 phasedir,
3984 phaseinc);
3985
3986 /* Program SSCDIVINTPHASE6 */
988d6ee8 3987 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3988 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3989 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3990 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3991 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3992 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3993 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3994 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3995
3996 /* Program SSCAUXDIV */
988d6ee8 3997 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3998 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3999 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 4000 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 4001
4002 /* Enable modulator and associated divider */
988d6ee8 4003 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 4004 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 4005 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 4006
4007 /* Wait for initialization time */
4008 udelay(24);
4009
4010 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000 4011
a580516d 4012 mutex_unlock(&dev_priv->sb_lock);
e615efe4
ED		 4013}
4014
275f01b2
DV		 4015static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4016 enum pipe pch_transcoder)
4017{
4018 struct drm_device *dev = crtc->base.dev;
4019 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 4020 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 4021
4022 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4023 I915_READ(HTOTAL(cpu_transcoder)));
4024 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4025 I915_READ(HBLANK(cpu_transcoder)));
4026 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4027 I915_READ(HSYNC(cpu_transcoder)));
4028
4029 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4030 I915_READ(VTOTAL(cpu_transcoder)));
4031 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4032 I915_READ(VBLANK(cpu_transcoder)));
4033 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4034 I915_READ(VSYNC(cpu_transcoder)));
4035 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4036 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4037}
4038
003632d9 4039static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 4040{
4041 struct drm_i915_private *dev_priv = dev->dev_private;
4042 uint32_t temp;
4043
4044 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 4045 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 4046 return;
4047
4048 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4049 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4050
003632d9
ACO		 4051 temp &= ~FDI_BC_BIFURCATION_SELECT;
4052 if (enable)
4053 temp |= FDI_BC_BIFURCATION_SELECT;
4054
4055 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 4056 I915_WRITE(SOUTH_CHICKEN1, temp);
4057 POSTING_READ(SOUTH_CHICKEN1);
4058}
4059
4060static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4061{
4062 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 4063
4064 switch (intel_crtc->pipe) {
4065 case PIPE_A:
4066 break;
4067 case PIPE_B:
6e3c9717 4068 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4069 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4070 else
003632d9 4071 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4072
4073 break;
4074 case PIPE_C:
003632d9 4075 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4076
4077 break;
4078 default:
4079 BUG();
4080 }
4081}
4082
f67a559d
JB		 4083/*
4084 * Enable PCH resources required for PCH ports:
4085 * - PCH PLLs
4086 * - FDI training & RX/TX
4087 * - update transcoder timings
4088 * - DP transcoding bits
4089 * - transcoder
4090 */
4091static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 4092{
4093 struct drm_device *dev = crtc->dev;
4094 struct drm_i915_private *dev_priv = dev->dev_private;
4095 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4096 int pipe = intel_crtc->pipe;
ee7b9f93 4097 u32 reg, temp;
2c07245f 4098
ab9412ba 4099 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4100
1fbc0d78
DV		 4101 if (IS_IVYBRIDGE(dev))
4102 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4103
cd986abb
DV		 4104 /* Write the TU size bits before fdi link training, so that error
4105 * detection works. */
4106 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4107 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4108
c98e9dcf 4109 /* For PCH output, training FDI link */
674cf967 4110 dev_priv->display.fdi_link_train(crtc);
2c07245f 4111
3ad8a208
DV		 4112 /* We need to program the right clock selection before writing the pixel
4113 * mutliplier into the DPLL. */
303b81e0 4114 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4115 u32 sel;
4b645f14 4116
c98e9dcf 4117 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4118 temp |= TRANS_DPLL_ENABLE(pipe);
4119 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4120 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4121 temp |= sel;
4122 else
4123 temp &= ~sel;
c98e9dcf 4124 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4125 }
5eddb70b 4126
3ad8a208
DV		 4127 /* XXX: pch pll's can be enabled any time before we enable the PCH
4128 * transcoder, and we actually should do this to not upset any PCH
4129 * transcoder that already use the clock when we share it.
4130 *
4131 * Note that enable_shared_dpll tries to do the right thing, but
4132 * get_shared_dpll unconditionally resets the pll - we need that to have
4133 * the right LVDS enable sequence. */
85b3894f 4134 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4135
d9b6cb56
JB		 4136 /* set transcoder timing, panel must allow it */
4137 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4138 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4139
303b81e0 4140 intel_fdi_normal_train(crtc);
5e84e1a4 4141
c98e9dcf 4142 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4143 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4144 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4145 reg = TRANS_DP_CTL(pipe);
4146 temp = I915_READ(reg);
4147 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4148 TRANS_DP_SYNC_MASK |
4149 TRANS_DP_BPC_MASK);
e3ef4479 4150 temp |= TRANS_DP_OUTPUT_ENABLE;
9325c9f0 4151 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4152
4153 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4154 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4155 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4156 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4157
4158 switch (intel_trans_dp_port_sel(crtc)) {
4159 case PCH_DP_B:
5eddb70b 4160 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4161 break;
4162 case PCH_DP_C:
5eddb70b 4163 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4164 break;
4165 case PCH_DP_D:
5eddb70b 4166 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4167 break;
4168 default:
e95d41e1 4169 BUG();
32f9d658 4170 }
2c07245f 4171
5eddb70b 4172 I915_WRITE(reg, temp);
6be4a607 4173 }
b52eb4dc 4174
b8a4f404 4175 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4176}
4177
1507e5bd
PZ		 4178static void lpt_pch_enable(struct drm_crtc *crtc)
4179{
4180 struct drm_device *dev = crtc->dev;
4181 struct drm_i915_private *dev_priv = dev->dev_private;
4182 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4183 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4184
ab9412ba 4185 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4186
8c52b5e8 4187 lpt_program_iclkip(crtc);
1507e5bd 4188
0540e488 4189 /* Set transcoder timing. */
275f01b2 4190 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4191
937bb610 4192 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4193}
4194
190f68c5
ACO		 4195struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4196 struct intel_crtc_state *crtc_state)
ee7b9f93 4197{
e2b78267 4198 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4199 struct intel_shared_dpll *pll;
de419ab6 4200 struct intel_shared_dpll_config *shared_dpll;
e2b78267 4201 enum intel_dpll_id i;
ee7b9f93 4202
de419ab6
ML		 4203 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4204
98b6bd99
DV		 4205 if (HAS_PCH_IBX(dev_priv->dev)) {
4206 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4207 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4208 pll = &dev_priv->shared_dplls[i];
98b6bd99 4209
46edb027
DV		 4210 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4211 crtc->base.base.id, pll->name);
98b6bd99 4212
de419ab6 4213 WARN_ON(shared_dpll[i].crtc_mask);
f2a69f44 4214
98b6bd99
DV		 4215 goto found;
4216 }
4217
bcddf610
S		 4218 if (IS_BROXTON(dev_priv->dev)) {
4219 /* PLL is attached to port in bxt */
4220 struct intel_encoder *encoder;
4221 struct intel_digital_port *intel_dig_port;
4222
4223 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4224 if (WARN_ON(!encoder))
4225 return NULL;
4226
4227 intel_dig_port = enc_to_dig_port(&encoder->base);
4228 /* 1:1 mapping between ports and PLLs */
4229 i = (enum intel_dpll_id)intel_dig_port->port;
4230 pll = &dev_priv->shared_dplls[i];
4231 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4232 crtc->base.base.id, pll->name);
de419ab6 4233 WARN_ON(shared_dpll[i].crtc_mask);
bcddf610
S		 4234
4235 goto found;
4236 }
4237
e72f9fbf
DV		 4238 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4239 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4240
4241 /* Only want to check enabled timings first */
de419ab6 4242 if (shared_dpll[i].crtc_mask == 0)
ee7b9f93
JB		 4243 continue;
4244
190f68c5 4245 if (memcmp(&crtc_state->dpll_hw_state,
de419ab6
ML		 4246 &shared_dpll[i].hw_state,
4247 sizeof(crtc_state->dpll_hw_state)) == 0) {
8bd31e67 4248 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4249 crtc->base.base.id, pll->name,
de419ab6 4250 shared_dpll[i].crtc_mask,
8bd31e67 4251 pll->active);
ee7b9f93
JB		 4252 goto found;
4253 }
4254 }
4255
4256 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4257 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4258 pll = &dev_priv->shared_dplls[i];
de419ab6 4259 if (shared_dpll[i].crtc_mask == 0) {
46edb027
DV		 4260 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4261 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4262 goto found;
4263 }
4264 }
4265
4266 return NULL;
4267
4268found:
de419ab6
ML		 4269 if (shared_dpll[i].crtc_mask == 0)
4270 shared_dpll[i].hw_state =
4271 crtc_state->dpll_hw_state;
f2a69f44 4272
190f68c5 4273 crtc_state->shared_dpll = i;
46edb027
DV		 4274 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4275 pipe_name(crtc->pipe));
ee7b9f93 4276
de419ab6 4277 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
e04c7350 4278
ee7b9f93
JB		 4279 return pll;
4280}
4281
de419ab6 4282static void intel_shared_dpll_commit(struct drm_atomic_state *state)
8bd31e67 4283{
de419ab6
ML		 4284 struct drm_i915_private *dev_priv = to_i915(state->dev);
4285 struct intel_shared_dpll_config *shared_dpll;
8bd31e67
ACO		 4286 struct intel_shared_dpll *pll;
4287 enum intel_dpll_id i;
4288
de419ab6
ML		 4289 if (!to_intel_atomic_state(state)->dpll_set)
4290 return;
8bd31e67 4291
de419ab6 4292 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
8bd31e67
ACO		 4293 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4294 pll = &dev_priv->shared_dplls[i];
de419ab6 4295 pll->config = shared_dpll[i];
8bd31e67
ACO		 4296 }
4297}
4298
a1520318 4299static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4300{
4301 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4302 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4303 u32 temp;
4304
4305 temp = I915_READ(dslreg);
4306 udelay(500);
4307 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4308 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4309 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4310 }
4311}
4312
86adf9d7
ML		 4313static int
4314skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4315 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4316 int src_w, int src_h, int dst_w, int dst_h)
a1b2278e 4317{
86adf9d7
ML		 4318 struct intel_crtc_scaler_state *scaler_state =
4319 &crtc_state->scaler_state;
4320 struct intel_crtc *intel_crtc =
4321 to_intel_crtc(crtc_state->base.crtc);
a1b2278e 4322 int need_scaling;
6156a456
CK		 4323
4324 need_scaling = intel_rotation_90_or_270(rotation) ?
4325 (src_h != dst_w || src_w != dst_h):
4326 (src_w != dst_w || src_h != dst_h);
a1b2278e
CK		 4327
4328 /*
4329 * if plane is being disabled or scaler is no more required or force detach
4330 * - free scaler binded to this plane/crtc
4331 * - in order to do this, update crtc->scaler_usage
4332 *
4333 * Here scaler state in crtc_state is set free so that
4334 * scaler can be assigned to other user. Actual register
4335 * update to free the scaler is done in plane/panel-fit programming.
4336 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4337 */
86adf9d7 4338 if (force_detach || !need_scaling) {
a1b2278e 4339 if (*scaler_id >= 0) {
86adf9d7 4340 scaler_state->scaler_users &= ~(1 << scaler_user);
a1b2278e
CK		 4341 scaler_state->scalers[*scaler_id].in_use = 0;
4342
86adf9d7
ML		 4343 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4344 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4345 intel_crtc->pipe, scaler_user, *scaler_id,
a1b2278e
CK		 4346 scaler_state->scaler_users);
4347 *scaler_id = -1;
4348 }
4349 return 0;
4350 }
4351
4352 /* range checks */
4353 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4354 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4355
4356 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4357 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
86adf9d7 4358 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
a1b2278e 4359 "size is out of scaler range\n",
86adf9d7 4360 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
a1b2278e
CK		 4361 return -EINVAL;
4362 }
4363
86adf9d7
ML		 4364 /* mark this plane as a scaler user in crtc_state */
4365 scaler_state->scaler_users |= (1 << scaler_user);
4366 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4367 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4368 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4369 scaler_state->scaler_users);
4370
4371 return 0;
4372}
4373
4374/**
4375 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4376 *
4377 * @state: crtc's scaler state
4378 * @force_detach: whether to forcibly disable scaler
4379 *
4380 * Return
4381 * 0 - scaler_usage updated successfully
4382 * error - requested scaling cannot be supported or other error condition
4383 */
4384int skl_update_scaler_crtc(struct intel_crtc_state *state, int force_detach)
4385{
4386 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4387 struct drm_display_mode *adjusted_mode =
4388 &state->base.adjusted_mode;
4389
4390 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4391 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4392
4393 return skl_update_scaler(state, force_detach, SKL_CRTC_INDEX,
4394 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4395 state->pipe_src_w, state->pipe_src_h,
4396 adjusted_mode->hdisplay, adjusted_mode->hdisplay);
4397}
4398
4399/**
4400 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4401 *
4402 * @state: crtc's scaler state
86adf9d7
ML		 4403 * @plane_state: atomic plane state to update
4404 *
4405 * Return
4406 * 0 - scaler_usage updated successfully
4407 * error - requested scaling cannot be supported or other error condition
4408 */
da20eabd
ML		 4409static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4410 struct intel_plane_state *plane_state)
86adf9d7
ML		 4411{
4412
4413 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
da20eabd
ML		 4414 struct intel_plane *intel_plane =
4415 to_intel_plane(plane_state->base.plane);
86adf9d7
ML		 4416 struct drm_framebuffer *fb = plane_state->base.fb;
4417 int ret;
4418
4419 bool force_detach = !fb || !plane_state->visible;
4420
4421 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4422 intel_plane->base.base.id, intel_crtc->pipe,
4423 drm_plane_index(&intel_plane->base));
4424
4425 ret = skl_update_scaler(crtc_state, force_detach,
4426 drm_plane_index(&intel_plane->base),
4427 &plane_state->scaler_id,
4428 plane_state->base.rotation,
4429 drm_rect_width(&plane_state->src) >> 16,
4430 drm_rect_height(&plane_state->src) >> 16,
4431 drm_rect_width(&plane_state->dst),
4432 drm_rect_height(&plane_state->dst));
4433
4434 if (ret || plane_state->scaler_id < 0)
4435 return ret;
4436
a1b2278e 4437 /* check colorkey */
86adf9d7
ML		 4438 if (WARN_ON(intel_plane->ckey.flags != I915_SET_COLORKEY_NONE)) {
4439 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4440 intel_plane->base.base.id);
a1b2278e
CK		 4441 return -EINVAL;
4442 }
4443
4444 /* Check src format */
86adf9d7
ML		 4445 switch (fb->pixel_format) {
4446 case DRM_FORMAT_RGB565:
4447 case DRM_FORMAT_XBGR8888:
4448 case DRM_FORMAT_XRGB8888:
4449 case DRM_FORMAT_ABGR8888:
4450 case DRM_FORMAT_ARGB8888:
4451 case DRM_FORMAT_XRGB2101010:
4452 case DRM_FORMAT_XBGR2101010:
4453 case DRM_FORMAT_YUYV:
4454 case DRM_FORMAT_YVYU:
4455 case DRM_FORMAT_UYVY:
4456 case DRM_FORMAT_VYUY:
4457 break;
4458 default:
4459 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4460 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4461 return -EINVAL;
a1b2278e
CK		 4462 }
4463
a1b2278e
CK		 4464 return 0;
4465}
4466
4467static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
bd2e244f
JB		 4468{
4469 struct drm_device *dev = crtc->base.dev;
4470 struct drm_i915_private *dev_priv = dev->dev_private;
4471 int pipe = crtc->pipe;
a1b2278e
CK		 4472 struct intel_crtc_scaler_state *scaler_state =
4473 &crtc->config->scaler_state;
4474
4475 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4476
4477 /* To update pfit, first update scaler state */
86adf9d7 4478 skl_update_scaler_crtc(crtc->config, !enable);
a1b2278e
CK		 4479 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4480 skl_detach_scalers(crtc);
4481 if (!enable)
4482 return;
bd2e244f 4483
6e3c9717 4484 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK		 4485 int id;
4486
4487 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4488 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4489 return;
4490 }
4491
4492 id = scaler_state->scaler_id;
4493 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4494 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4495 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4496 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4497
4498 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB		 4499 }
4500}
4501
b074cec8
JB		 4502static void ironlake_pfit_enable(struct intel_crtc *crtc)
4503{
4504 struct drm_device *dev = crtc->base.dev;
4505 struct drm_i915_private *dev_priv = dev->dev_private;
4506 int pipe = crtc->pipe;
4507
6e3c9717 4508 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4509 /* Force use of hard-coded filter coefficients
4510 * as some pre-programmed values are broken,
4511 * e.g. x201.
4512 */
4513 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4514 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4515 PF_PIPE_SEL_IVB(pipe));
4516 else
4517 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4518 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4519 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4520 }
4521}
4522
4a3b8769 4523static void intel_enable_sprite_planes(struct drm_crtc *crtc)
bb53d4ae
VS		 4524{
4525 struct drm_device *dev = crtc->dev;
4526 enum pipe pipe = to_intel_crtc(crtc)->pipe;
af2b653b 4527 struct drm_plane *plane;
bb53d4ae
VS		 4528 struct intel_plane *intel_plane;
4529
af2b653b
MR		 4530 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4531 intel_plane = to_intel_plane(plane);
bb53d4ae
VS		 4532 if (intel_plane->pipe == pipe)
4533 intel_plane_restore(&intel_plane->base);
af2b653b 4534 }
bb53d4ae
VS		 4535}
4536
20bc8673 4537void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4538{
cea165c3
VS		 4539 struct drm_device *dev = crtc->base.dev;
4540 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4541
6e3c9717 4542 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4543 return;
4544
cea165c3
VS		 4545 /* We can only enable IPS after we enable a plane and wait for a vblank */
4546 intel_wait_for_vblank(dev, crtc->pipe);
4547
d77e4531 4548 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4549 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4550 mutex_lock(&dev_priv->rps.hw_lock);
4551 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4552 mutex_unlock(&dev_priv->rps.hw_lock);
4553 /* Quoting Art Runyan: "its not safe to expect any particular
4554 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4555 * mailbox." Moreover, the mailbox may return a bogus state,
4556 * so we need to just enable it and continue on.
2a114cc1
BW		 4557 */
4558 } else {
4559 I915_WRITE(IPS_CTL, IPS_ENABLE);
4560 /* The bit only becomes 1 in the next vblank, so this wait here
4561 * is essentially intel_wait_for_vblank. If we don't have this
4562 * and don't wait for vblanks until the end of crtc_enable, then
4563 * the HW state readout code will complain that the expected
4564 * IPS_CTL value is not the one we read. */
4565 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4566 DRM_ERROR("Timed out waiting for IPS enable\n");
4567 }
d77e4531
PZ		 4568}
4569
20bc8673 4570void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4571{
4572 struct drm_device *dev = crtc->base.dev;
4573 struct drm_i915_private *dev_priv = dev->dev_private;
4574
6e3c9717 4575 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4576 return;
4577
4578 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4579 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4580 mutex_lock(&dev_priv->rps.hw_lock);
4581 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4582 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4583 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4584 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4585 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4586 } else {
2a114cc1 4587 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4588 POSTING_READ(IPS_CTL);
4589 }
d77e4531
PZ		 4590
4591 /* We need to wait for a vblank before we can disable the plane. */
4592 intel_wait_for_vblank(dev, crtc->pipe);
4593}
4594
4595/** Loads the palette/gamma unit for the CRTC with the prepared values */
4596static void intel_crtc_load_lut(struct drm_crtc *crtc)
4597{
4598 struct drm_device *dev = crtc->dev;
4599 struct drm_i915_private *dev_priv = dev->dev_private;
4600 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4601 enum pipe pipe = intel_crtc->pipe;
4602 int palreg = PALETTE(pipe);
4603 int i;
4604 bool reenable_ips = false;
4605
4606 /* The clocks have to be on to load the palette. */
53d9f4e9 4607 if (!crtc->state->active)
d77e4531
PZ		 4608 return;
4609
50360403 4610 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
409ee761 4611 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4612 assert_dsi_pll_enabled(dev_priv);
4613 else
4614 assert_pll_enabled(dev_priv, pipe);
4615 }
4616
4617 /* use legacy palette for Ironlake */
7a1db49a 4618 if (!HAS_GMCH_DISPLAY(dev))
d77e4531
PZ		 4619 palreg = LGC_PALETTE(pipe);
4620
4621 /* Workaround : Do not read or write the pipe palette/gamma data while
4622 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4623 */
6e3c9717 4624 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4625 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4626 GAMMA_MODE_MODE_SPLIT)) {
4627 hsw_disable_ips(intel_crtc);
4628 reenable_ips = true;
4629 }
4630
4631 for (i = 0; i < 256; i++) {
4632 I915_WRITE(palreg + 4 * i,
4633 (intel_crtc->lut_r[i] << 16) |
4634 (intel_crtc->lut_g[i] << 8) |
4635 intel_crtc->lut_b[i]);
4636 }
4637
4638 if (reenable_ips)
4639 hsw_enable_ips(intel_crtc);
4640}
4641
7cac945f 4642static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
d3eedb1a 4643{
7cac945f 4644 if (intel_crtc->overlay) {
d3eedb1a
VS		 4645 struct drm_device *dev = intel_crtc->base.dev;
4646 struct drm_i915_private *dev_priv = dev->dev_private;
4647
4648 mutex_lock(&dev->struct_mutex);
4649 dev_priv->mm.interruptible = false;
4650 (void) intel_overlay_switch_off(intel_crtc->overlay);
4651 dev_priv->mm.interruptible = true;
4652 mutex_unlock(&dev->struct_mutex);
4653 }
4654
4655 /* Let userspace switch the overlay on again. In most cases userspace
4656 * has to recompute where to put it anyway.
4657 */
4658}
4659
87d4300a
ML		 4660/**
4661 * intel_post_enable_primary - Perform operations after enabling primary plane
4662 * @crtc: the CRTC whose primary plane was just enabled
4663 *
4664 * Performs potentially sleeping operations that must be done after the primary
4665 * plane is enabled, such as updating FBC and IPS. Note that this may be
4666 * called due to an explicit primary plane update, or due to an implicit
4667 * re-enable that is caused when a sprite plane is updated to no longer
4668 * completely hide the primary plane.
4669 */
4670static void
4671intel_post_enable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4672{
4673 struct drm_device *dev = crtc->dev;
87d4300a 4674 struct drm_i915_private *dev_priv = dev->dev_private;
a5c4d7bc
VS		 4675 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4676 int pipe = intel_crtc->pipe;
a5c4d7bc 4677
87d4300a
ML		 4678 /*
4679 * BDW signals flip done immediately if the plane
4680 * is disabled, even if the plane enable is already
4681 * armed to occur at the next vblank :(
4682 */
4683 if (IS_BROADWELL(dev))
4684 intel_wait_for_vblank(dev, pipe);
a5c4d7bc 4685
87d4300a
ML		 4686 /*
4687 * FIXME IPS should be fine as long as one plane is
4688 * enabled, but in practice it seems to have problems
4689 * when going from primary only to sprite only and vice
4690 * versa.
4691 */
a5c4d7bc
VS		 4692 hsw_enable_ips(intel_crtc);
4693
4694 mutex_lock(&dev->struct_mutex);
7ff0ebcc 4695 intel_fbc_update(dev);
a5c4d7bc 4696 mutex_unlock(&dev->struct_mutex);
f99d7069
DV		 4697
4698 /*
87d4300a
ML		 4699 * Gen2 reports pipe underruns whenever all planes are disabled.
4700 * So don't enable underrun reporting before at least some planes
4701 * are enabled.
4702 * FIXME: Need to fix the logic to work when we turn off all planes
4703 * but leave the pipe running.
f99d7069 4704 */
87d4300a
ML		 4705 if (IS_GEN2(dev))
4706 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4707
4708 /* Underruns don't raise interrupts, so check manually. */
4709 if (HAS_GMCH_DISPLAY(dev))
4710 i9xx_check_fifo_underruns(dev_priv);
a5c4d7bc
VS		 4711}
4712
87d4300a
ML		 4713/**
4714 * intel_pre_disable_primary - Perform operations before disabling primary plane
4715 * @crtc: the CRTC whose primary plane is to be disabled
4716 *
4717 * Performs potentially sleeping operations that must be done before the
4718 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4719 * be called due to an explicit primary plane update, or due to an implicit
4720 * disable that is caused when a sprite plane completely hides the primary
4721 * plane.
4722 */
4723static void
4724intel_pre_disable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4725{
4726 struct drm_device *dev = crtc->dev;
4727 struct drm_i915_private *dev_priv = dev->dev_private;
4728 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4729 int pipe = intel_crtc->pipe;
a5c4d7bc 4730
87d4300a
ML		 4731 /*
4732 * Gen2 reports pipe underruns whenever all planes are disabled.
4733 * So diasble underrun reporting before all the planes get disabled.
4734 * FIXME: Need to fix the logic to work when we turn off all planes
4735 * but leave the pipe running.
4736 */
4737 if (IS_GEN2(dev))
4738 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
a5c4d7bc 4739
87d4300a
ML		 4740 /*
4741 * Vblank time updates from the shadow to live plane control register
4742 * are blocked if the memory self-refresh mode is active at that
4743 * moment. So to make sure the plane gets truly disabled, disable
4744 * first the self-refresh mode. The self-refresh enable bit in turn
4745 * will be checked/applied by the HW only at the next frame start
4746 * event which is after the vblank start event, so we need to have a
4747 * wait-for-vblank between disabling the plane and the pipe.
4748 */
4749 if (HAS_GMCH_DISPLAY(dev))
4750 intel_set_memory_cxsr(dev_priv, false);
4751
4752 mutex_lock(&dev->struct_mutex);
e35fef21 4753 if (dev_priv->fbc.crtc == intel_crtc)
7ff0ebcc 4754 intel_fbc_disable(dev);
87d4300a 4755 mutex_unlock(&dev->struct_mutex);
a5c4d7bc 4756
87d4300a
ML		 4757 /*
4758 * FIXME IPS should be fine as long as one plane is
4759 * enabled, but in practice it seems to have problems
4760 * when going from primary only to sprite only and vice
4761 * versa.
4762 */
a5c4d7bc 4763 hsw_disable_ips(intel_crtc);
87d4300a
ML		 4764}
4765
4766static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4767{
2d847d45
RV		 4768 struct drm_device *dev = crtc->dev;
4769 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4770 int pipe = intel_crtc->pipe;
4771
87d4300a
ML		 4772 intel_enable_primary_hw_plane(crtc->primary, crtc);
4773 intel_enable_sprite_planes(crtc);
c0165304
ML		 4774 if (to_intel_plane_state(crtc->cursor->state)->visible)
4775 intel_crtc_update_cursor(crtc, true);
87d4300a
ML		 4776
4777 intel_post_enable_primary(crtc);
2d847d45
RV		 4778
4779 /*
4780 * FIXME: Once we grow proper nuclear flip support out of this we need
4781 * to compute the mask of flip planes precisely. For the time being
4782 * consider this a flip to a NULL plane.
4783 */
4784 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
87d4300a
ML		 4785}
4786
4787static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4788{
4789 struct drm_device *dev = crtc->dev;
4790 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4791 struct intel_plane *intel_plane;
4792 int pipe = intel_crtc->pipe;
4793
4794 intel_crtc_wait_for_pending_flips(crtc);
4795
4796 intel_pre_disable_primary(crtc);
a5c4d7bc 4797
7cac945f 4798 intel_crtc_dpms_overlay_disable(intel_crtc);
27321ae8
ML		 4799 for_each_intel_plane(dev, intel_plane) {
4800 if (intel_plane->pipe == pipe) {
4801 struct drm_crtc *from = intel_plane->base.crtc;
4802
4803 intel_plane->disable_plane(&intel_plane->base,
7fabf5ef 4804 from ?: crtc);
27321ae8
ML		 4805 }
4806 }
f98551ae 4807
f99d7069
DV		 4808 /*
4809 * FIXME: Once we grow proper nuclear flip support out of this we need
4810 * to compute the mask of flip planes precisely. For the time being
4811 * consider this a flip to a NULL plane.
4812 */
4813 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4814}
4815
f67a559d
JB		 4816static void ironlake_crtc_enable(struct drm_crtc *crtc)
4817{
4818 struct drm_device *dev = crtc->dev;
4819 struct drm_i915_private *dev_priv = dev->dev_private;
4820 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4821 struct intel_encoder *encoder;
f67a559d 4822 int pipe = intel_crtc->pipe;
f67a559d 4823
53d9f4e9 4824 if (WARN_ON(intel_crtc->active))
f67a559d
JB		 4825 return;
4826
6e3c9717 4827 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4828 intel_prepare_shared_dpll(intel_crtc);
4829
6e3c9717 4830 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4831 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4832
4833 intel_set_pipe_timings(intel_crtc);
4834
6e3c9717 4835 if (intel_crtc->config->has_pch_encoder) {
29407aab 4836 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4837 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4838 }
4839
4840 ironlake_set_pipeconf(crtc);
4841
f67a559d 4842 intel_crtc->active = true;
8664281b 4843
a72e4c9f
DV		 4844 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4845 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4846
f6736a1a 4847 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4848 if (encoder->pre_enable)
4849 encoder->pre_enable(encoder);
f67a559d 4850
6e3c9717 4851 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4852 /* Note: FDI PLL enabling _must_ be done before we enable the
4853 * cpu pipes, hence this is separate from all the other fdi/pch
4854 * enabling. */
88cefb6c 4855 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4856 } else {
4857 assert_fdi_tx_disabled(dev_priv, pipe);
4858 assert_fdi_rx_disabled(dev_priv, pipe);
4859 }
f67a559d 4860
b074cec8 4861 ironlake_pfit_enable(intel_crtc);
f67a559d 4862
9c54c0dd
JB		 4863 /*
4864 * On ILK+ LUT must be loaded before the pipe is running but with
4865 * clocks enabled
4866 */
4867 intel_crtc_load_lut(crtc);
4868
f37fcc2a 4869 intel_update_watermarks(crtc);
e1fdc473 4870 intel_enable_pipe(intel_crtc);
f67a559d 4871
6e3c9717 4872 if (intel_crtc->config->has_pch_encoder)
f67a559d 4873 ironlake_pch_enable(crtc);
c98e9dcf 4874
f9b61ff6
DV		 4875 assert_vblank_disabled(crtc);
4876 drm_crtc_vblank_on(crtc);
4877
fa5c73b1
DV		 4878 for_each_encoder_on_crtc(dev, crtc, encoder)
4879 encoder->enable(encoder);
61b77ddd
DV		 4880
4881 if (HAS_PCH_CPT(dev))
a1520318 4882 cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB		 4883}
4884
42db64ef
PZ		 4885/* IPS only exists on ULT machines and is tied to pipe A. */
4886static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4887{
f5adf94e 4888 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4889}
4890
4f771f10
PZ		 4891static void haswell_crtc_enable(struct drm_crtc *crtc)
4892{
4893 struct drm_device *dev = crtc->dev;
4894 struct drm_i915_private *dev_priv = dev->dev_private;
4895 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4896 struct intel_encoder *encoder;
99d736a2
ML		 4897 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4898 struct intel_crtc_state *pipe_config =
4899 to_intel_crtc_state(crtc->state);
4f771f10 4900
53d9f4e9 4901 if (WARN_ON(intel_crtc->active))
4f771f10
PZ		 4902 return;
4903
df8ad70c
DV		 4904 if (intel_crtc_to_shared_dpll(intel_crtc))
4905 intel_enable_shared_dpll(intel_crtc);
4906
6e3c9717 4907 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4908 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 4909
4910 intel_set_pipe_timings(intel_crtc);
4911
6e3c9717
ACO		 4912 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4913 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4914 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 4915 }
4916
6e3c9717 4917 if (intel_crtc->config->has_pch_encoder) {
229fca97 4918 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4919 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 4920 }
4921
4922 haswell_set_pipeconf(crtc);
4923
4924 intel_set_pipe_csc(crtc);
4925
4f771f10 4926 intel_crtc->active = true;
8664281b 4927
a72e4c9f 4928 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ		 4929 for_each_encoder_on_crtc(dev, crtc, encoder)
4930 if (encoder->pre_enable)
4931 encoder->pre_enable(encoder);
4932
6e3c9717 4933 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 4934 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4935 true);
4fe9467d
ID		 4936 dev_priv->display.fdi_link_train(crtc);
4937 }
4938
1f544388 4939 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 4940
ff6d9f55 4941 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 4942 skylake_pfit_update(intel_crtc, 1);
ff6d9f55 4943 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 4944 ironlake_pfit_enable(intel_crtc);
ff6d9f55
JB		 4945 else
4946 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10
PZ		 4947
4948 /*
4949 * On ILK+ LUT must be loaded before the pipe is running but with
4950 * clocks enabled
4951 */
4952 intel_crtc_load_lut(crtc);
4953
1f544388 4954 intel_ddi_set_pipe_settings(crtc);
8228c251 4955 intel_ddi_enable_transcoder_func(crtc);
4f771f10 4956
f37fcc2a 4957 intel_update_watermarks(crtc);
e1fdc473 4958 intel_enable_pipe(intel_crtc);
42db64ef 4959
6e3c9717 4960 if (intel_crtc->config->has_pch_encoder)
1507e5bd 4961 lpt_pch_enable(crtc);
4f771f10 4962
6e3c9717 4963 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA		 4964 intel_ddi_set_vc_payload_alloc(crtc, true);
4965
f9b61ff6
DV		 4966 assert_vblank_disabled(crtc);
4967 drm_crtc_vblank_on(crtc);
4968
8807e55b 4969 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 4970 encoder->enable(encoder);
8807e55b
JN		 4971 intel_opregion_notify_encoder(encoder, true);
4972 }
4f771f10 4973
e4916946
PZ		 4974 /* If we change the relative order between pipe/planes enabling, we need
4975 * to change the workaround. */
99d736a2
ML		 4976 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4977 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4978 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4979 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4980 }
4f771f10
PZ		 4981}
4982
3f8dce3a
DV		 4983static void ironlake_pfit_disable(struct intel_crtc *crtc)
4984{
4985 struct drm_device *dev = crtc->base.dev;
4986 struct drm_i915_private *dev_priv = dev->dev_private;
4987 int pipe = crtc->pipe;
4988
4989 /* To avoid upsetting the power well on haswell only disable the pfit if
4990 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 4991 if (crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 4992 I915_WRITE(PF_CTL(pipe), 0);
4993 I915_WRITE(PF_WIN_POS(pipe), 0);
4994 I915_WRITE(PF_WIN_SZ(pipe), 0);
4995 }
4996}
4997
6be4a607
JB		 4998static void ironlake_crtc_disable(struct drm_crtc *crtc)
4999{
5000 struct drm_device *dev = crtc->dev;
5001 struct drm_i915_private *dev_priv = dev->dev_private;
5002 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5003 struct intel_encoder *encoder;
6be4a607 5004 int pipe = intel_crtc->pipe;
5eddb70b 5005 u32 reg, temp;
b52eb4dc 5006
53d9f4e9 5007 if (WARN_ON(!intel_crtc->active))
f7abfe8b
CW		 5008 return;
5009
ea9d758d
DV		 5010 for_each_encoder_on_crtc(dev, crtc, encoder)
5011 encoder->disable(encoder);
5012
f9b61ff6
DV		 5013 drm_crtc_vblank_off(crtc);
5014 assert_vblank_disabled(crtc);
5015
6e3c9717 5016 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 5017 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 5018
575f7ab7 5019 intel_disable_pipe(intel_crtc);
32f9d658 5020
3f8dce3a 5021 ironlake_pfit_disable(intel_crtc);
2c07245f 5022
5a74f70a
VS		 5023 if (intel_crtc->config->has_pch_encoder)
5024 ironlake_fdi_disable(crtc);
5025
bf49ec8c
DV		 5026 for_each_encoder_on_crtc(dev, crtc, encoder)
5027 if (encoder->post_disable)
5028 encoder->post_disable(encoder);
2c07245f 5029
6e3c9717 5030 if (intel_crtc->config->has_pch_encoder) {
d925c59a 5031 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 5032
d925c59a
DV		 5033 if (HAS_PCH_CPT(dev)) {
5034 /* disable TRANS_DP_CTL */
5035 reg = TRANS_DP_CTL(pipe);
5036 temp = I915_READ(reg);
5037 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5038 TRANS_DP_PORT_SEL_MASK);
5039 temp |= TRANS_DP_PORT_SEL_NONE;
5040 I915_WRITE(reg, temp);
5041
5042 /* disable DPLL_SEL */
5043 temp = I915_READ(PCH_DPLL_SEL);
11887397 5044 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 5045 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 5046 }
e3421a18 5047
d925c59a 5048 /* disable PCH DPLL */
e72f9fbf 5049 intel_disable_shared_dpll(intel_crtc);
8db9d77b 5050
d925c59a
DV		 5051 ironlake_fdi_pll_disable(intel_crtc);
5052 }
6b383a7f 5053
f7abfe8b 5054 intel_crtc->active = false;
46ba614c 5055 intel_update_watermarks(crtc);
d1ebd816
BW		 5056
5057 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5058 intel_fbc_update(dev);
d1ebd816 5059 mutex_unlock(&dev->struct_mutex);
6be4a607 5060}
1b3c7a47 5061
4f771f10 5062static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 5063{
4f771f10
PZ		 5064 struct drm_device *dev = crtc->dev;
5065 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5066 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5067 struct intel_encoder *encoder;
6e3c9717 5068 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 5069
53d9f4e9 5070 if (WARN_ON(!intel_crtc->active))
4f771f10
PZ		 5071 return;
5072
8807e55b
JN		 5073 for_each_encoder_on_crtc(dev, crtc, encoder) {
5074 intel_opregion_notify_encoder(encoder, false);
4f771f10 5075 encoder->disable(encoder);
8807e55b 5076 }
4f771f10 5077
f9b61ff6
DV		 5078 drm_crtc_vblank_off(crtc);
5079 assert_vblank_disabled(crtc);
5080
6e3c9717 5081 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 5082 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5083 false);
575f7ab7 5084 intel_disable_pipe(intel_crtc);
4f771f10 5085
6e3c9717 5086 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 5087 intel_ddi_set_vc_payload_alloc(crtc, false);
5088
ad80a810 5089 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5090
ff6d9f55 5091 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 5092 skylake_pfit_update(intel_crtc, 0);
ff6d9f55 5093 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5094 ironlake_pfit_disable(intel_crtc);
ff6d9f55
JB		 5095 else
5096 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10 5097
1f544388 5098 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5099
6e3c9717 5100 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 5101 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 5102 intel_ddi_fdi_disable(crtc);
83616634 5103 }
4f771f10 5104
97b040aa
ID		 5105 for_each_encoder_on_crtc(dev, crtc, encoder)
5106 if (encoder->post_disable)
5107 encoder->post_disable(encoder);
5108
4f771f10 5109 intel_crtc->active = false;
46ba614c 5110 intel_update_watermarks(crtc);
4f771f10
PZ		 5111
5112 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5113 intel_fbc_update(dev);
4f771f10 5114 mutex_unlock(&dev->struct_mutex);
df8ad70c
DV		 5115
5116 if (intel_crtc_to_shared_dpll(intel_crtc))
5117 intel_disable_shared_dpll(intel_crtc);
4f771f10
PZ		 5118}
5119
2dd24552
JB		 5120static void i9xx_pfit_enable(struct intel_crtc *crtc)
5121{
5122 struct drm_device *dev = crtc->base.dev;
5123 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5124 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5125
681a8504 5126 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 5127 return;
5128
2dd24552 5129 /*
c0b03411
DV		 5130 * The panel fitter should only be adjusted whilst the pipe is disabled,
5131 * according to register description and PRM.
2dd24552 5132 */
c0b03411
DV		 5133 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5134 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5135
b074cec8
JB		 5136 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5137 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 5138
5139 /* Border color in case we don't scale up to the full screen. Black by
5140 * default, change to something else for debugging. */
5141 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 5142}
5143
d05410f9
DA		 5144static enum intel_display_power_domain port_to_power_domain(enum port port)
5145{
5146 switch (port) {
5147 case PORT_A:
5148 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5149 case PORT_B:
5150 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5151 case PORT_C:
5152 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5153 case PORT_D:
5154 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5155 default:
5156 WARN_ON_ONCE(1);
5157 return POWER_DOMAIN_PORT_OTHER;
5158 }
5159}
5160
77d22dca
ID		 5161#define for_each_power_domain(domain, mask) \
5162 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5163 if ((1 << (domain)) & (mask))
5164
319be8ae
ID		 5165enum intel_display_power_domain
5166intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5167{
5168 struct drm_device *dev = intel_encoder->base.dev;
5169 struct intel_digital_port *intel_dig_port;
5170
5171 switch (intel_encoder->type) {
5172 case INTEL_OUTPUT_UNKNOWN:
5173 /* Only DDI platforms should ever use this output type */
5174 WARN_ON_ONCE(!HAS_DDI(dev));
5175 case INTEL_OUTPUT_DISPLAYPORT:
5176 case INTEL_OUTPUT_HDMI:
5177 case INTEL_OUTPUT_EDP:
5178 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5179 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 5180 case INTEL_OUTPUT_DP_MST:
5181 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5182 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 5183 case INTEL_OUTPUT_ANALOG:
5184 return POWER_DOMAIN_PORT_CRT;
5185 case INTEL_OUTPUT_DSI:
5186 return POWER_DOMAIN_PORT_DSI;
5187 default:
5188 return POWER_DOMAIN_PORT_OTHER;
5189 }
5190}
5191
5192static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5193{
319be8ae
ID		 5194 struct drm_device *dev = crtc->dev;
5195 struct intel_encoder *intel_encoder;
5196 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5197 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 5198 unsigned long mask;
5199 enum transcoder transcoder;
5200
5201 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5202
5203 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5204 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 5205 if (intel_crtc->config->pch_pfit.enabled ||
5206 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 5207 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5208
319be8ae
ID		 5209 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5210 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5211
77d22dca
ID		 5212 return mask;
5213}
5214
679dacd4 5215static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
77d22dca 5216{
679dacd4 5217 struct drm_device *dev = state->dev;
77d22dca
ID		 5218 struct drm_i915_private *dev_priv = dev->dev_private;
5219 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5220 struct intel_crtc *crtc;
5221
5222 /*
5223 * First get all needed power domains, then put all unneeded, to avoid
5224 * any unnecessary toggling of the power wells.
5225 */
d3fcc808 5226 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5227 enum intel_display_power_domain domain;
5228
83d65738 5229 if (!crtc->base.state->enable)
77d22dca
ID		 5230 continue;
5231
319be8ae 5232 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
77d22dca
ID		 5233
5234 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5235 intel_display_power_get(dev_priv, domain);
5236 }
5237
50f6e502 5238 if (dev_priv->display.modeset_global_resources)
679dacd4 5239 dev_priv->display.modeset_global_resources(state);
50f6e502 5240
d3fcc808 5241 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5242 enum intel_display_power_domain domain;
5243
5244 for_each_power_domain(domain, crtc->enabled_power_domains)
5245 intel_display_power_put(dev_priv, domain);
5246
5247 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5248 }
5249
5250 intel_display_set_init_power(dev_priv, false);
5251}
5252
560a7ae4
DL		 5253static void intel_update_max_cdclk(struct drm_device *dev)
5254{
5255 struct drm_i915_private *dev_priv = dev->dev_private;
5256
5257 if (IS_SKYLAKE(dev)) {
5258 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5259
5260 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5261 dev_priv->max_cdclk_freq = 675000;
5262 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5263 dev_priv->max_cdclk_freq = 540000;
5264 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5265 dev_priv->max_cdclk_freq = 450000;
5266 else
5267 dev_priv->max_cdclk_freq = 337500;
5268 } else if (IS_BROADWELL(dev)) {
5269 /*
5270 * FIXME with extra cooling we can allow
5271 * 540 MHz for ULX and 675 Mhz for ULT.
5272 * How can we know if extra cooling is
5273 * available? PCI ID, VTB, something else?
5274 */
5275 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5276 dev_priv->max_cdclk_freq = 450000;
5277 else if (IS_BDW_ULX(dev))
5278 dev_priv->max_cdclk_freq = 450000;
5279 else if (IS_BDW_ULT(dev))
5280 dev_priv->max_cdclk_freq = 540000;
5281 else
5282 dev_priv->max_cdclk_freq = 675000;
0904deaf
MK		 5283 } else if (IS_CHERRYVIEW(dev)) {
5284 dev_priv->max_cdclk_freq = 320000;
560a7ae4
DL		 5285 } else if (IS_VALLEYVIEW(dev)) {
5286 dev_priv->max_cdclk_freq = 400000;
5287 } else {
5288 /* otherwise assume cdclk is fixed */
5289 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5290 }
5291
5292 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5293 dev_priv->max_cdclk_freq);
5294}
5295
5296static void intel_update_cdclk(struct drm_device *dev)
5297{
5298 struct drm_i915_private *dev_priv = dev->dev_private;
5299
5300 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5301 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5302 dev_priv->cdclk_freq);
5303
5304 /*
5305 * Program the gmbus_freq based on the cdclk frequency.
5306 * BSpec erroneously claims we should aim for 4MHz, but
5307 * in fact 1MHz is the correct frequency.
5308 */
5309 if (IS_VALLEYVIEW(dev)) {
5310 /*
5311 * Program the gmbus_freq based on the cdclk frequency.
5312 * BSpec erroneously claims we should aim for 4MHz, but
5313 * in fact 1MHz is the correct frequency.
5314 */
5315 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5316 }
5317
5318 if (dev_priv->max_cdclk_freq == 0)
5319 intel_update_max_cdclk(dev);
5320}
5321
70d0c574 5322static void broxton_set_cdclk(struct drm_device *dev, int frequency)
f8437dd1
VK		 5323{
5324 struct drm_i915_private *dev_priv = dev->dev_private;
5325 uint32_t divider;
5326 uint32_t ratio;
5327 uint32_t current_freq;
5328 int ret;
5329
5330 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5331 switch (frequency) {
5332 case 144000:
5333 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5334 ratio = BXT_DE_PLL_RATIO(60);
5335 break;
5336 case 288000:
5337 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5338 ratio = BXT_DE_PLL_RATIO(60);
5339 break;
5340 case 384000:
5341 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5342 ratio = BXT_DE_PLL_RATIO(60);
5343 break;
5344 case 576000:
5345 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5346 ratio = BXT_DE_PLL_RATIO(60);
5347 break;
5348 case 624000:
5349 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5350 ratio = BXT_DE_PLL_RATIO(65);
5351 break;
5352 case 19200:
5353 /*
5354 * Bypass frequency with DE PLL disabled. Init ratio, divider
5355 * to suppress GCC warning.
5356 */
5357 ratio = 0;
5358 divider = 0;
5359 break;
5360 default:
5361 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5362
5363 return;
5364 }
5365
5366 mutex_lock(&dev_priv->rps.hw_lock);
5367 /* Inform power controller of upcoming frequency change */
5368 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5369 0x80000000);
5370 mutex_unlock(&dev_priv->rps.hw_lock);
5371
5372 if (ret) {
5373 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5374 ret, frequency);
5375 return;
5376 }
5377
5378 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5379 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5380 current_freq = current_freq * 500 + 1000;
5381
5382 /*
5383 * DE PLL has to be disabled when
5384 * - setting to 19.2MHz (bypass, PLL isn't used)
5385 * - before setting to 624MHz (PLL needs toggling)
5386 * - before setting to any frequency from 624MHz (PLL needs toggling)
5387 */
5388 if (frequency == 19200 || frequency == 624000 ||
5389 current_freq == 624000) {
5390 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5391 /* Timeout 200us */
5392 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5393 1))
5394 DRM_ERROR("timout waiting for DE PLL unlock\n");
5395 }
5396
5397 if (frequency != 19200) {
5398 uint32_t val;
5399
5400 val = I915_READ(BXT_DE_PLL_CTL);
5401 val &= ~BXT_DE_PLL_RATIO_MASK;
5402 val |= ratio;
5403 I915_WRITE(BXT_DE_PLL_CTL, val);
5404
5405 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5406 /* Timeout 200us */
5407 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5408 DRM_ERROR("timeout waiting for DE PLL lock\n");
5409
5410 val = I915_READ(CDCLK_CTL);
5411 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5412 val |= divider;
5413 /*
5414 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5415 * enable otherwise.
5416 */
5417 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5418 if (frequency >= 500000)
5419 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5420
5421 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5422 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5423 val |= (frequency - 1000) / 500;
5424 I915_WRITE(CDCLK_CTL, val);
5425 }
5426
5427 mutex_lock(&dev_priv->rps.hw_lock);
5428 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5429 DIV_ROUND_UP(frequency, 25000));
5430 mutex_unlock(&dev_priv->rps.hw_lock);
5431
5432 if (ret) {
5433 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5434 ret, frequency);
5435 return;
5436 }
5437
a47871bd 5438 intel_update_cdclk(dev);
f8437dd1
VK		 5439}
5440
5441void broxton_init_cdclk(struct drm_device *dev)
5442{
5443 struct drm_i915_private *dev_priv = dev->dev_private;
5444 uint32_t val;
5445
5446 /*
5447 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5448 * or else the reset will hang because there is no PCH to respond.
5449 * Move the handshake programming to initialization sequence.
5450 * Previously was left up to BIOS.
5451 */
5452 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5453 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5454 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5455
5456 /* Enable PG1 for cdclk */
5457 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5458
5459 /* check if cd clock is enabled */
5460 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5461 DRM_DEBUG_KMS("Display already initialized\n");
5462 return;
5463 }
5464
5465 /*
5466 * FIXME:
5467 * - The initial CDCLK needs to be read from VBT.
5468 * Need to make this change after VBT has changes for BXT.
5469 * - check if setting the max (or any) cdclk freq is really necessary
5470 * here, it belongs to modeset time
5471 */
5472 broxton_set_cdclk(dev, 624000);
5473
5474 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
22e02c0b
VS		 5475 POSTING_READ(DBUF_CTL);
5476
f8437dd1
VK		 5477 udelay(10);
5478
5479 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5480 DRM_ERROR("DBuf power enable timeout!\n");
5481}
5482
5483void broxton_uninit_cdclk(struct drm_device *dev)
5484{
5485 struct drm_i915_private *dev_priv = dev->dev_private;
5486
5487 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
22e02c0b
VS		 5488 POSTING_READ(DBUF_CTL);
5489
f8437dd1
VK		 5490 udelay(10);
5491
5492 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5493 DRM_ERROR("DBuf power disable timeout!\n");
5494
5495 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5496 broxton_set_cdclk(dev, 19200);
5497
5498 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5499}
5500
5d96d8af
DL		 5501static const struct skl_cdclk_entry {
5502 unsigned int freq;
5503 unsigned int vco;
5504} skl_cdclk_frequencies[] = {
5505 { .freq = 308570, .vco = 8640 },
5506 { .freq = 337500, .vco = 8100 },
5507 { .freq = 432000, .vco = 8640 },
5508 { .freq = 450000, .vco = 8100 },
5509 { .freq = 540000, .vco = 8100 },
5510 { .freq = 617140, .vco = 8640 },
5511 { .freq = 675000, .vco = 8100 },
5512};
5513
5514static unsigned int skl_cdclk_decimal(unsigned int freq)
5515{
5516 return (freq - 1000) / 500;
5517}
5518
5519static unsigned int skl_cdclk_get_vco(unsigned int freq)
5520{
5521 unsigned int i;
5522
5523 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5524 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5525
5526 if (e->freq == freq)
5527 return e->vco;
5528 }
5529
5530 return 8100;
5531}
5532
5533static void
5534skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5535{
5536 unsigned int min_freq;
5537 u32 val;
5538
5539 /* select the minimum CDCLK before enabling DPLL 0 */
5540 val = I915_READ(CDCLK_CTL);
5541 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5542 val |= CDCLK_FREQ_337_308;
5543
5544 if (required_vco == 8640)
5545 min_freq = 308570;
5546 else
5547 min_freq = 337500;
5548
5549 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5550
5551 I915_WRITE(CDCLK_CTL, val);
5552 POSTING_READ(CDCLK_CTL);
5553
5554 /*
5555 * We always enable DPLL0 with the lowest link rate possible, but still
5556 * taking into account the VCO required to operate the eDP panel at the
5557 * desired frequency. The usual DP link rates operate with a VCO of
5558 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5559 * The modeset code is responsible for the selection of the exact link
5560 * rate later on, with the constraint of choosing a frequency that
5561 * works with required_vco.
5562 */
5563 val = I915_READ(DPLL_CTRL1);
5564
5565 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5566 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5567 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5568 if (required_vco == 8640)
5569 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5570 SKL_DPLL0);
5571 else
5572 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5573 SKL_DPLL0);
5574
5575 I915_WRITE(DPLL_CTRL1, val);
5576 POSTING_READ(DPLL_CTRL1);
5577
5578 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5579
5580 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5581 DRM_ERROR("DPLL0 not locked\n");
5582}
5583
5584static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5585{
5586 int ret;
5587 u32 val;
5588
5589 /* inform PCU we want to change CDCLK */
5590 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5591 mutex_lock(&dev_priv->rps.hw_lock);
5592 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5593 mutex_unlock(&dev_priv->rps.hw_lock);
5594
5595 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5596}
5597
5598static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5599{
5600 unsigned int i;
5601
5602 for (i = 0; i < 15; i++) {
5603 if (skl_cdclk_pcu_ready(dev_priv))
5604 return true;
5605 udelay(10);
5606 }
5607
5608 return false;
5609}
5610
5611static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5612{
560a7ae4 5613 struct drm_device *dev = dev_priv->dev;
5d96d8af
DL		 5614 u32 freq_select, pcu_ack;
5615
5616 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5617
5618 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5619 DRM_ERROR("failed to inform PCU about cdclk change\n");
5620 return;
5621 }
5622
5623 /* set CDCLK_CTL */
5624 switch(freq) {
5625 case 450000:
5626 case 432000:
5627 freq_select = CDCLK_FREQ_450_432;
5628 pcu_ack = 1;
5629 break;
5630 case 540000:
5631 freq_select = CDCLK_FREQ_540;
5632 pcu_ack = 2;
5633 break;
5634 case 308570:
5635 case 337500:
5636 default:
5637 freq_select = CDCLK_FREQ_337_308;
5638 pcu_ack = 0;
5639 break;
5640 case 617140:
5641 case 675000:
5642 freq_select = CDCLK_FREQ_675_617;
5643 pcu_ack = 3;
5644 break;
5645 }
5646
5647 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5648 POSTING_READ(CDCLK_CTL);
5649
5650 /* inform PCU of the change */
5651 mutex_lock(&dev_priv->rps.hw_lock);
5652 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5653 mutex_unlock(&dev_priv->rps.hw_lock);
560a7ae4
DL		 5654
5655 intel_update_cdclk(dev);
5d96d8af
DL		 5656}
5657
5658void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5659{
5660 /* disable DBUF power */
5661 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5662 POSTING_READ(DBUF_CTL);
5663
5664 udelay(10);
5665
5666 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5667 DRM_ERROR("DBuf power disable timeout\n");
5668
5669 /* disable DPLL0 */
5670 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5671 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5672 DRM_ERROR("Couldn't disable DPLL0\n");
5673
5674 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5675}
5676
5677void skl_init_cdclk(struct drm_i915_private *dev_priv)
5678{
5679 u32 val;
5680 unsigned int required_vco;
5681
5682 /* enable PCH reset handshake */
5683 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5684 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5685
5686 /* enable PG1 and Misc I/O */
5687 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5688
5689 /* DPLL0 already enabed !? */
5690 if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5691 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5692 return;
5693 }
5694
5695 /* enable DPLL0 */
5696 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5697 skl_dpll0_enable(dev_priv, required_vco);
5698
5699 /* set CDCLK to the frequency the BIOS chose */
5700 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5701
5702 /* enable DBUF power */
5703 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5704 POSTING_READ(DBUF_CTL);
5705
5706 udelay(10);
5707
5708 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5709 DRM_ERROR("DBuf power enable timeout\n");
5710}
5711
dfcab17e 5712/* returns HPLL frequency in kHz */
f8bf63fd 5713static int valleyview_get_vco(struct drm_i915_private *dev_priv)
30a970c6 5714{
586f49dc 5715 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
30a970c6 5716
586f49dc 5717 /* Obtain SKU information */
a580516d 5718 mutex_lock(&dev_priv->sb_lock);
586f49dc
JB		 5719 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5720 CCK_FUSE_HPLL_FREQ_MASK;
a580516d 5721 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5722
dfcab17e 5723 return vco_freq[hpll_freq] * 1000;
30a970c6
JB		 5724}
5725
5726/* Adjust CDclk dividers to allow high res or save power if possible */
5727static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5728{
5729 struct drm_i915_private *dev_priv = dev->dev_private;
5730 u32 val, cmd;
5731
164dfd28
VK		 5732 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5733 != dev_priv->cdclk_freq);
d60c4473 5734
dfcab17e 5735 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5736 cmd = 2;
dfcab17e 5737 else if (cdclk == 266667)
30a970c6
JB		 5738 cmd = 1;
5739 else
5740 cmd = 0;
5741
5742 mutex_lock(&dev_priv->rps.hw_lock);
5743 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5744 val &= ~DSPFREQGUAR_MASK;
5745 val |= (cmd << DSPFREQGUAR_SHIFT);
5746 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5747 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5748 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5749 50)) {
5750 DRM_ERROR("timed out waiting for CDclk change\n");
5751 }
5752 mutex_unlock(&dev_priv->rps.hw_lock);
5753
54433e91
VS		 5754 mutex_lock(&dev_priv->sb_lock);
5755
dfcab17e 5756 if (cdclk == 400000) {
6bcda4f0 5757 u32 divider;
30a970c6 5758
6bcda4f0 5759 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6 5760
30a970c6
JB		 5761 /* adjust cdclk divider */
5762 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
9cf33db5 5763 val &= ~DISPLAY_FREQUENCY_VALUES;
30a970c6
JB		 5764 val |= divider;
5765 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5766
5767 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5768 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5769 50))
5770 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5771 }
5772
30a970c6
JB		 5773 /* adjust self-refresh exit latency value */
5774 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5775 val &= ~0x7f;
5776
5777 /*
5778 * For high bandwidth configs, we set a higher latency in the bunit
5779 * so that the core display fetch happens in time to avoid underruns.
5780 */
dfcab17e 5781 if (cdclk == 400000)
30a970c6
JB		 5782 val |= 4500 / 250; /* 4.5 usec */
5783 else
5784 val |= 3000 / 250; /* 3.0 usec */
5785 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
54433e91 5786
a580516d 5787 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5788
b6283055 5789 intel_update_cdclk(dev);
30a970c6
JB		 5790}
5791
383c5a6a
VS		 5792static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5793{
5794 struct drm_i915_private *dev_priv = dev->dev_private;
5795 u32 val, cmd;
5796
164dfd28
VK		 5797 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5798 != dev_priv->cdclk_freq);
383c5a6a
VS		 5799
5800 switch (cdclk) {
383c5a6a
VS		 5801 case 333333:
5802 case 320000:
383c5a6a 5803 case 266667:
383c5a6a 5804 case 200000:
383c5a6a
VS		 5805 break;
5806 default:
5f77eeb0 5807 MISSING_CASE(cdclk);
383c5a6a
VS		 5808 return;
5809 }
5810
9d0d3fda
VS		 5811 /*
5812 * Specs are full of misinformation, but testing on actual
5813 * hardware has shown that we just need to write the desired
5814 * CCK divider into the Punit register.
5815 */
5816 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5817
383c5a6a
VS		 5818 mutex_lock(&dev_priv->rps.hw_lock);
5819 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5820 val &= ~DSPFREQGUAR_MASK_CHV;
5821 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5822 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5823 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5824 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5825 50)) {
5826 DRM_ERROR("timed out waiting for CDclk change\n");
5827 }
5828 mutex_unlock(&dev_priv->rps.hw_lock);
5829
b6283055 5830 intel_update_cdclk(dev);
383c5a6a
VS		 5831}
5832
30a970c6
JB		 5833static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5834 int max_pixclk)
5835{
6bcda4f0 5836 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5837 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5838
30a970c6
JB		 5839 /*
5840 * Really only a few cases to deal with, as only 4 CDclks are supported:
5841 * 200MHz
5842 * 267MHz
29dc7ef3 5843 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5844 * 400MHz (VLV only)
5845 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5846 * of the lower bin and adjust if needed.
e37c67a1
VS		 5847 *
5848 * We seem to get an unstable or solid color picture at 200MHz.
5849 * Not sure what's wrong. For now use 200MHz only when all pipes
5850 * are off.
30a970c6 5851 */
6cca3195
VS		 5852 if (!IS_CHERRYVIEW(dev_priv) &&
5853 max_pixclk > freq_320*limit/100)
dfcab17e 5854 return 400000;
6cca3195 5855 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5856 return freq_320;
e37c67a1 5857 else if (max_pixclk > 0)
dfcab17e 5858 return 266667;
e37c67a1
VS		 5859 else
5860 return 200000;
30a970c6
JB		 5861}
5862
f8437dd1
VK		 5863static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5864 int max_pixclk)
5865{
5866 /*
5867 * FIXME:
5868 * - remove the guardband, it's not needed on BXT
5869 * - set 19.2MHz bypass frequency if there are no active pipes
5870 */
5871 if (max_pixclk > 576000*9/10)
5872 return 624000;
5873 else if (max_pixclk > 384000*9/10)
5874 return 576000;
5875 else if (max_pixclk > 288000*9/10)
5876 return 384000;
5877 else if (max_pixclk > 144000*9/10)
5878 return 288000;
5879 else
5880 return 144000;
5881}
5882
a821fc46
ACO		 5883/* Compute the max pixel clock for new configuration. Uses atomic state if
5884 * that's non-NULL, look at current state otherwise. */
5885static int intel_mode_max_pixclk(struct drm_device *dev,
5886 struct drm_atomic_state *state)
30a970c6 5887{
30a970c6 5888 struct intel_crtc *intel_crtc;
304603f4 5889 struct intel_crtc_state *crtc_state;
30a970c6
JB		 5890 int max_pixclk = 0;
5891
d3fcc808 5892 for_each_intel_crtc(dev, intel_crtc) {
a821fc46
ACO		 5893 if (state)
5894 crtc_state =
5895 intel_atomic_get_crtc_state(state, intel_crtc);
5896 else
5897 crtc_state = intel_crtc->config;
304603f4
ACO		 5898 if (IS_ERR(crtc_state))
5899 return PTR_ERR(crtc_state);
5900
5901 if (!crtc_state->base.enable)
5902 continue;
5903
5904 max_pixclk = max(max_pixclk,
5905 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5906 }
5907
5908 return max_pixclk;
5909}
5910
0a9ab303 5911static int valleyview_modeset_global_pipes(struct drm_atomic_state *state)
30a970c6 5912{
304603f4 5913 struct drm_i915_private *dev_priv = to_i915(state->dev);
0a9ab303
ACO		 5914 struct drm_crtc *crtc;
5915 struct drm_crtc_state *crtc_state;
a821fc46 5916 int max_pixclk = intel_mode_max_pixclk(state->dev, state);
85a96e7a 5917 int cdclk, ret = 0;
30a970c6 5918
304603f4
ACO		 5919 if (max_pixclk < 0)
5920 return max_pixclk;
30a970c6 5921
f8437dd1
VK		 5922 if (IS_VALLEYVIEW(dev_priv))
5923 cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5924 else
5925 cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
5926
5927 if (cdclk == dev_priv->cdclk_freq)
304603f4 5928 return 0;
30a970c6 5929
0a9ab303
ACO		 5930 /* add all active pipes to the state */
5931 for_each_crtc(state->dev, crtc) {
0a9ab303
ACO		 5932 crtc_state = drm_atomic_get_crtc_state(state, crtc);
5933 if (IS_ERR(crtc_state))
5934 return PTR_ERR(crtc_state);
0a9ab303 5935
85a96e7a
ML		 5936 if (!crtc_state->active || needs_modeset(crtc_state))
5937 continue;
304603f4 5938
85a96e7a
ML		 5939 crtc_state->mode_changed = true;
5940
5941 ret = drm_atomic_add_affected_connectors(state, crtc);
5942 if (ret)
5943 break;
5944
5945 ret = drm_atomic_add_affected_planes(state, crtc);
5946 if (ret)
5947 break;
5948 }
5949
5950 return ret;
30a970c6
JB		 5951}
5952
1e69cd74
VS		 5953static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5954{
5955 unsigned int credits, default_credits;
5956
5957 if (IS_CHERRYVIEW(dev_priv))
5958 default_credits = PFI_CREDIT(12);
5959 else
5960 default_credits = PFI_CREDIT(8);
5961
164dfd28 5962 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
1e69cd74
VS		 5963 /* CHV suggested value is 31 or 63 */
5964 if (IS_CHERRYVIEW(dev_priv))
fcc0008f 5965 credits = PFI_CREDIT_63;
1e69cd74
VS		 5966 else
5967 credits = PFI_CREDIT(15);
5968 } else {
5969 credits = default_credits;
5970 }
5971
5972 /*
5973 * WA - write default credits before re-programming
5974 * FIXME: should we also set the resend bit here?
5975 */
5976 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5977 default_credits);
5978
5979 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5980 credits | PFI_CREDIT_RESEND);
5981
5982 /*
5983 * FIXME is this guaranteed to clear
5984 * immediately or should we poll for it?
5985 */
5986 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5987}
5988
a821fc46 5989static void valleyview_modeset_global_resources(struct drm_atomic_state *old_state)
30a970c6 5990{
a821fc46 5991 struct drm_device *dev = old_state->dev;
30a970c6 5992 struct drm_i915_private *dev_priv = dev->dev_private;
a821fc46 5993 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
304603f4
ACO		 5994 int req_cdclk;
5995
a821fc46
ACO		 5996 /* The path in intel_mode_max_pixclk() with a NULL atomic state should
5997 * never fail. */
304603f4
ACO		 5998 if (WARN_ON(max_pixclk < 0))
5999 return;
30a970c6 6000
304603f4 6001 req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
30a970c6 6002
164dfd28 6003 if (req_cdclk != dev_priv->cdclk_freq) {
738c05c0
ID		 6004 /*
6005 * FIXME: We can end up here with all power domains off, yet
6006 * with a CDCLK frequency other than the minimum. To account
6007 * for this take the PIPE-A power domain, which covers the HW
6008 * blocks needed for the following programming. This can be
6009 * removed once it's guaranteed that we get here either with
6010 * the minimum CDCLK set, or the required power domains
6011 * enabled.
6012 */
6013 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6014
383c5a6a
VS		 6015 if (IS_CHERRYVIEW(dev))
6016 cherryview_set_cdclk(dev, req_cdclk);
6017 else
6018 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 6019
1e69cd74
VS		 6020 vlv_program_pfi_credits(dev_priv);
6021
738c05c0 6022 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
383c5a6a 6023 }
30a970c6
JB		 6024}
6025
89b667f8
JB		 6026static void valleyview_crtc_enable(struct drm_crtc *crtc)
6027{
6028 struct drm_device *dev = crtc->dev;
a72e4c9f 6029 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 6030 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6031 struct intel_encoder *encoder;
6032 int pipe = intel_crtc->pipe;
23538ef1 6033 bool is_dsi;
89b667f8 6034
53d9f4e9 6035 if (WARN_ON(intel_crtc->active))
89b667f8
JB		 6036 return;
6037
409ee761 6038 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 6039
1ae0d137
VS		 6040 if (!is_dsi) {
6041 if (IS_CHERRYVIEW(dev))
6e3c9717 6042 chv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 6043 else
6e3c9717 6044 vlv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 6045 }
5b18e57c 6046
6e3c9717 6047 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6048 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6049
6050 intel_set_pipe_timings(intel_crtc);
6051
c14b0485
VS		 6052 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6053 struct drm_i915_private *dev_priv = dev->dev_private;
6054
6055 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6056 I915_WRITE(CHV_CANVAS(pipe), 0);
6057 }
6058
5b18e57c
DV		 6059 i9xx_set_pipeconf(intel_crtc);
6060
89b667f8 6061 intel_crtc->active = true;
89b667f8 6062
a72e4c9f 6063 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6064
89b667f8
JB		 6065 for_each_encoder_on_crtc(dev, crtc, encoder)
6066 if (encoder->pre_pll_enable)
6067 encoder->pre_pll_enable(encoder);
6068
9d556c99
CML		 6069 if (!is_dsi) {
6070 if (IS_CHERRYVIEW(dev))
6e3c9717 6071 chv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6072 else
6e3c9717 6073 vlv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6074 }
89b667f8
JB		 6075
6076 for_each_encoder_on_crtc(dev, crtc, encoder)
6077 if (encoder->pre_enable)
6078 encoder->pre_enable(encoder);
6079
2dd24552
JB		 6080 i9xx_pfit_enable(intel_crtc);
6081
63cbb074
VS		 6082 intel_crtc_load_lut(crtc);
6083
f37fcc2a 6084 intel_update_watermarks(crtc);
e1fdc473 6085 intel_enable_pipe(intel_crtc);
be6a6f8e 6086
4b3a9526
VS		 6087 assert_vblank_disabled(crtc);
6088 drm_crtc_vblank_on(crtc);
6089
f9b61ff6
DV		 6090 for_each_encoder_on_crtc(dev, crtc, encoder)
6091 encoder->enable(encoder);
89b667f8
JB		 6092}
6093
f13c2ef3
DV		 6094static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6095{
6096 struct drm_device *dev = crtc->base.dev;
6097 struct drm_i915_private *dev_priv = dev->dev_private;
6098
6e3c9717
ACO		 6099 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6100 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 6101}
6102
0b8765c6 6103static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 6104{
6105 struct drm_device *dev = crtc->dev;
a72e4c9f 6106 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 6107 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6108 struct intel_encoder *encoder;
79e53945 6109 int pipe = intel_crtc->pipe;
79e53945 6110
53d9f4e9 6111 if (WARN_ON(intel_crtc->active))
f7abfe8b
CW		 6112 return;
6113
f13c2ef3
DV		 6114 i9xx_set_pll_dividers(intel_crtc);
6115
6e3c9717 6116 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6117 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6118
6119 intel_set_pipe_timings(intel_crtc);
6120
5b18e57c
DV		 6121 i9xx_set_pipeconf(intel_crtc);
6122
f7abfe8b 6123 intel_crtc->active = true;
6b383a7f 6124
4a3436e8 6125 if (!IS_GEN2(dev))
a72e4c9f 6126 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6127
9d6d9f19
MK		 6128 for_each_encoder_on_crtc(dev, crtc, encoder)
6129 if (encoder->pre_enable)
6130 encoder->pre_enable(encoder);
6131
f6736a1a
DV		 6132 i9xx_enable_pll(intel_crtc);
6133
2dd24552
JB		 6134 i9xx_pfit_enable(intel_crtc);
6135
63cbb074
VS		 6136 intel_crtc_load_lut(crtc);
6137
f37fcc2a 6138 intel_update_watermarks(crtc);
e1fdc473 6139 intel_enable_pipe(intel_crtc);
be6a6f8e 6140
4b3a9526
VS		 6141 assert_vblank_disabled(crtc);
6142 drm_crtc_vblank_on(crtc);
6143
f9b61ff6
DV		 6144 for_each_encoder_on_crtc(dev, crtc, encoder)
6145 encoder->enable(encoder);
0b8765c6 6146}
79e53945 6147
87476d63
DV		 6148static void i9xx_pfit_disable(struct intel_crtc *crtc)
6149{
6150 struct drm_device *dev = crtc->base.dev;
6151 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 6152
6e3c9717 6153 if (!crtc->config->gmch_pfit.control)
328d8e82 6154 return;
87476d63 6155
328d8e82 6156 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 6157
328d8e82
DV		 6158 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6159 I915_READ(PFIT_CONTROL));
6160 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 6161}
6162
0b8765c6
JB		 6163static void i9xx_crtc_disable(struct drm_crtc *crtc)
6164{
6165 struct drm_device *dev = crtc->dev;
6166 struct drm_i915_private *dev_priv = dev->dev_private;
6167 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6168 struct intel_encoder *encoder;
0b8765c6 6169 int pipe = intel_crtc->pipe;
ef9c3aee 6170
53d9f4e9 6171 if (WARN_ON(!intel_crtc->active))
f7abfe8b
CW		 6172 return;
6173
6304cd91
VS		 6174 /*
6175 * On gen2 planes are double buffered but the pipe isn't, so we must
6176 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 6177 * We also need to wait on all gmch platforms because of the
6178 * self-refresh mode constraint explained above.
6304cd91 6179 */
564ed191 6180 intel_wait_for_vblank(dev, pipe);
6304cd91 6181
4b3a9526
VS		 6182 for_each_encoder_on_crtc(dev, crtc, encoder)
6183 encoder->disable(encoder);
6184
f9b61ff6
DV		 6185 drm_crtc_vblank_off(crtc);
6186 assert_vblank_disabled(crtc);
6187
575f7ab7 6188 intel_disable_pipe(intel_crtc);
24a1f16d 6189
87476d63 6190 i9xx_pfit_disable(intel_crtc);
24a1f16d 6191
89b667f8
JB		 6192 for_each_encoder_on_crtc(dev, crtc, encoder)
6193 if (encoder->post_disable)
6194 encoder->post_disable(encoder);
6195
409ee761 6196 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 6197 if (IS_CHERRYVIEW(dev))
6198 chv_disable_pll(dev_priv, pipe);
6199 else if (IS_VALLEYVIEW(dev))
6200 vlv_disable_pll(dev_priv, pipe);
6201 else
1c4e0274 6202 i9xx_disable_pll(intel_crtc);
076ed3b2 6203 }
0b8765c6 6204
4a3436e8 6205 if (!IS_GEN2(dev))
a72e4c9f 6206 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4a3436e8 6207
f7abfe8b 6208 intel_crtc->active = false;
46ba614c 6209 intel_update_watermarks(crtc);
f37fcc2a 6210
efa9624e 6211 mutex_lock(&dev->struct_mutex);
7ff0ebcc 6212 intel_fbc_update(dev);
efa9624e 6213 mutex_unlock(&dev->struct_mutex);
0b8765c6
JB		 6214}
6215
b17d48e2
ML		 6216static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6217{
6218 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6219 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6220 enum intel_display_power_domain domain;
6221 unsigned long domains;
6222
6223 if (!intel_crtc->active)
6224 return;
6225
6226 intel_crtc_disable_planes(crtc);
6227 dev_priv->display.crtc_disable(crtc);
6228
6229 domains = intel_crtc->enabled_power_domains;
6230 for_each_power_domain(domain, domains)
6231 intel_display_power_put(dev_priv, domain);
6232 intel_crtc->enabled_power_domains = 0;
6233}
6234
6b72d486
ML		 6235/*
6236 * turn all crtc's off, but do not adjust state
6237 * This has to be paired with a call to intel_modeset_setup_hw_state.
6238 */
9716c691 6239void intel_display_suspend(struct drm_device *dev)
ee7b9f93 6240{
6b72d486
ML		 6241 struct drm_crtc *crtc;
6242
b17d48e2
ML		 6243 for_each_crtc(dev, crtc)
6244 intel_crtc_disable_noatomic(crtc);
ee7b9f93
JB		 6245}
6246
b04c5bd6 6247/* Master function to enable/disable CRTC and corresponding power wells */
5da76e94 6248int intel_crtc_control(struct drm_crtc *crtc, bool enable)
976f8a20
DV		 6249{
6250 struct drm_device *dev = crtc->dev;
5da76e94
ML		 6251 struct drm_mode_config *config = &dev->mode_config;
6252 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
0e572fe7 6253 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5da76e94
ML		 6254 struct intel_crtc_state *pipe_config;
6255 struct drm_atomic_state *state;
6256 int ret;
976f8a20 6257
1b509259 6258 if (enable == intel_crtc->active)
5da76e94 6259 return 0;
0e572fe7 6260
1b509259 6261 if (enable && !crtc->state->enable)
5da76e94 6262 return 0;
1b509259 6263
5da76e94
ML		 6264 /* this function should be called with drm_modeset_lock_all for now */
6265 if (WARN_ON(!ctx))
6266 return -EIO;
6267 lockdep_assert_held(&ctx->ww_ctx);
1b509259 6268
5da76e94
ML		 6269 state = drm_atomic_state_alloc(dev);
6270 if (WARN_ON(!state))
6271 return -ENOMEM;
1b509259 6272
5da76e94
ML		 6273 state->acquire_ctx = ctx;
6274 state->allow_modeset = true;
6275
6276 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
6277 if (IS_ERR(pipe_config)) {
6278 ret = PTR_ERR(pipe_config);
6279 goto err;
0e572fe7 6280 }
5da76e94
ML		 6281 pipe_config->base.active = enable;
6282
6283 ret = intel_set_mode(state);
6284 if (!ret)
6285 return ret;
6286
6287err:
6288 DRM_ERROR("Updating crtc active failed with %i\n", ret);
6289 drm_atomic_state_free(state);
6290 return ret;
b04c5bd6
BF		 6291}
6292
6293/**
6294 * Sets the power management mode of the pipe and plane.
6295 */
6296void intel_crtc_update_dpms(struct drm_crtc *crtc)
6297{
6298 struct drm_device *dev = crtc->dev;
6299 struct intel_encoder *intel_encoder;
6300 bool enable = false;
6301
6302 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6303 enable |= intel_encoder->connectors_active;
6304
6305 intel_crtc_control(crtc, enable);
cdd59983
CW		 6306}
6307
ea5b213a 6308void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 6309{
4ef69c7a 6310 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 6311
ea5b213a
CW		 6312 drm_encoder_cleanup(encoder);
6313 kfree(intel_encoder);
7e7d76c3
JB		 6314}
6315
9237329d 6316/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 6317 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6318 * state of the entire output pipe. */
9237329d 6319static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 6320{
5ab432ef
DV		 6321 if (mode == DRM_MODE_DPMS_ON) {
6322 encoder->connectors_active = true;
6323
b2cabb0e 6324 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 6325 } else {
6326 encoder->connectors_active = false;
6327
b2cabb0e 6328 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 6329 }
79e53945
JB		 6330}
6331
0a91ca29
DV		 6332/* Cross check the actual hw state with our own modeset state tracking (and it's
6333 * internal consistency). */
b980514c 6334static void intel_connector_check_state(struct intel_connector *connector)
79e53945 6335{
0a91ca29
DV		 6336 if (connector->get_hw_state(connector)) {
6337 struct intel_encoder *encoder = connector->encoder;
6338 struct drm_crtc *crtc;
6339 bool encoder_enabled;
6340 enum pipe pipe;
6341
6342 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6343 connector->base.base.id,
c23cc417 6344 connector->base.name);
0a91ca29 6345
0e32b39c
DA		 6346 /* there is no real hw state for MST connectors */
6347 if (connector->mst_port)
6348 return;
6349
e2c719b7 6350 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
0a91ca29 6351 "wrong connector dpms state\n");
e2c719b7 6352 I915_STATE_WARN(connector->base.encoder != &encoder->base,
0a91ca29 6353 "active connector not linked to encoder\n");
0a91ca29 6354
36cd7444 6355 if (encoder) {
e2c719b7 6356 I915_STATE_WARN(!encoder->connectors_active,
36cd7444
DA		 6357 "encoder->connectors_active not set\n");
6358
6359 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
e2c719b7
RC		 6360 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6361 if (I915_STATE_WARN_ON(!encoder->base.crtc))
36cd7444 6362 return;
0a91ca29 6363
36cd7444 6364 crtc = encoder->base.crtc;
0a91ca29 6365
83d65738
MR		 6366 I915_STATE_WARN(!crtc->state->enable,
6367 "crtc not enabled\n");
e2c719b7
RC		 6368 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6369 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
36cd7444
DA		 6370 "encoder active on the wrong pipe\n");
6371 }
0a91ca29 6372 }
79e53945
JB		 6373}
6374
08d9bc92
ACO		 6375int intel_connector_init(struct intel_connector *connector)
6376{
6377 struct drm_connector_state *connector_state;
6378
6379 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6380 if (!connector_state)
6381 return -ENOMEM;
6382
6383 connector->base.state = connector_state;
6384 return 0;
6385}
6386
6387struct intel_connector *intel_connector_alloc(void)
6388{
6389 struct intel_connector *connector;
6390
6391 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6392 if (!connector)
6393 return NULL;
6394
6395 if (intel_connector_init(connector) < 0) {
6396 kfree(connector);
6397 return NULL;
6398 }
6399
6400 return connector;
6401}
6402
5ab432ef
DV		 6403/* Even simpler default implementation, if there's really no special case to
6404 * consider. */
6405void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 6406{
5ab432ef
DV		 6407 /* All the simple cases only support two dpms states. */
6408 if (mode != DRM_MODE_DPMS_ON)
6409 mode = DRM_MODE_DPMS_OFF;
d4270e57 6410
5ab432ef
DV		 6411 if (mode == connector->dpms)
6412 return;
6413
6414 connector->dpms = mode;
6415
6416 /* Only need to change hw state when actually enabled */
c9976dcf
CW		 6417 if (connector->encoder)
6418 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
0a91ca29 6419
b980514c 6420 intel_modeset_check_state(connector->dev);
79e53945
JB		 6421}
6422
f0947c37
DV		 6423/* Simple connector->get_hw_state implementation for encoders that support only
6424 * one connector and no cloning and hence the encoder state determines the state
6425 * of the connector. */
6426bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 6427{
24929352 6428 enum pipe pipe = 0;
f0947c37 6429 struct intel_encoder *encoder = connector->encoder;
ea5b213a 6430
f0947c37 6431 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 6432}
6433
6d293983 6434static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 6435{
6d293983
ACO		 6436 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6437 return crtc_state->fdi_lanes;
d272ddfa
VS		 6438
6439 return 0;
6440}
6441
6d293983 6442static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6443 struct intel_crtc_state *pipe_config)
1857e1da 6444{
6d293983
ACO		 6445 struct drm_atomic_state *state = pipe_config->base.state;
6446 struct intel_crtc *other_crtc;
6447 struct intel_crtc_state *other_crtc_state;
6448
1857e1da
DV		 6449 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6450 pipe_name(pipe), pipe_config->fdi_lanes);
6451 if (pipe_config->fdi_lanes > 4) {
6452 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6453 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6454 return -EINVAL;
1857e1da
DV		 6455 }
6456
bafb6553 6457 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 6458 if (pipe_config->fdi_lanes > 2) {
6459 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6460 pipe_config->fdi_lanes);
6d293983 6461 return -EINVAL;
1857e1da 6462 } else {
6d293983 6463 return 0;
1857e1da
DV		 6464 }
6465 }
6466
6467 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 6468 return 0;
1857e1da
DV		 6469
6470 /* Ivybridge 3 pipe is really complicated */
6471 switch (pipe) {
6472 case PIPE_A:
6d293983 6473 return 0;
1857e1da 6474 case PIPE_B:
6d293983
ACO		 6475 if (pipe_config->fdi_lanes <= 2)
6476 return 0;
6477
6478 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6479 other_crtc_state =
6480 intel_atomic_get_crtc_state(state, other_crtc);
6481 if (IS_ERR(other_crtc_state))
6482 return PTR_ERR(other_crtc_state);
6483
6484 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV		 6485 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6486 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6487 return -EINVAL;
1857e1da 6488 }
6d293983 6489 return 0;
1857e1da 6490 case PIPE_C:
251cc67c
VS		 6491 if (pipe_config->fdi_lanes > 2) {
6492 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6493 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6494 return -EINVAL;
251cc67c 6495 }
6d293983
ACO		 6496
6497 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6498 other_crtc_state =
6499 intel_atomic_get_crtc_state(state, other_crtc);
6500 if (IS_ERR(other_crtc_state))
6501 return PTR_ERR(other_crtc_state);
6502
6503 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6504 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6505 return -EINVAL;
1857e1da 6506 }
6d293983 6507 return 0;
1857e1da
DV		 6508 default:
6509 BUG();
6510 }
6511}
6512
e29c22c0
DV		 6513#define RETRY 1
6514static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6515 struct intel_crtc_state *pipe_config)
877d48d5 6516{
1857e1da 6517 struct drm_device *dev = intel_crtc->base.dev;
2d112de7 6518 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 6519 int lane, link_bw, fdi_dotclock, ret;
6520 bool needs_recompute = false;
877d48d5 6521
e29c22c0 6522retry:
877d48d5
DV		 6523 /* FDI is a binary signal running at ~2.7GHz, encoding
6524 * each output octet as 10 bits. The actual frequency
6525 * is stored as a divider into a 100MHz clock, and the
6526 * mode pixel clock is stored in units of 1KHz.
6527 * Hence the bw of each lane in terms of the mode signal
6528 * is:
6529 */
6530 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6531
241bfc38 6532 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6533
2bd89a07 6534 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 6535 pipe_config->pipe_bpp);
6536
6537 pipe_config->fdi_lanes = lane;
6538
2bd89a07 6539 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6540 link_bw, &pipe_config->fdi_m_n);
1857e1da 6541
6d293983
ACO		 6542 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6543 intel_crtc->pipe, pipe_config);
6544 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV		 6545 pipe_config->pipe_bpp -= 2*3;
6546 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6547 pipe_config->pipe_bpp);
6548 needs_recompute = true;
6549 pipe_config->bw_constrained = true;
6550
6551 goto retry;
6552 }
6553
6554 if (needs_recompute)
6555 return RETRY;
6556
6d293983 6557 return ret;
877d48d5
DV		 6558}
6559
8cfb3407
VS		 6560static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6561 struct intel_crtc_state *pipe_config)
6562{
6563 if (pipe_config->pipe_bpp > 24)
6564 return false;
6565
6566 /* HSW can handle pixel rate up to cdclk? */
6567 if (IS_HASWELL(dev_priv->dev))
6568 return true;
6569
6570 /*
b432e5cf
VS		 6571 * We compare against max which means we must take
6572 * the increased cdclk requirement into account when
6573 * calculating the new cdclk.
6574 *
6575 * Should measure whether using a lower cdclk w/o IPS
8cfb3407
VS		 6576 */
6577 return ilk_pipe_pixel_rate(pipe_config) <=
6578 dev_priv->max_cdclk_freq * 95 / 100;
6579}
6580
42db64ef 6581static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6582 struct intel_crtc_state *pipe_config)
42db64ef 6583{
8cfb3407
VS		 6584 struct drm_device *dev = crtc->base.dev;
6585 struct drm_i915_private *dev_priv = dev->dev_private;
6586
d330a953 6587 pipe_config->ips_enabled = i915.enable_ips &&
8cfb3407
VS		 6588 hsw_crtc_supports_ips(crtc) &&
6589 pipe_config_supports_ips(dev_priv, pipe_config);
42db64ef
PZ		 6590}
6591
a43f6e0f 6592static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6593 struct intel_crtc_state *pipe_config)
79e53945 6594{
a43f6e0f 6595 struct drm_device *dev = crtc->base.dev;
8bd31e67 6596 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 6597 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
89749350 6598
ad3a4479 6599 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 6600 if (INTEL_INFO(dev)->gen < 4) {
44913155 6601 int clock_limit = dev_priv->max_cdclk_freq;
cf532bb2
VS		 6602
6603 /*
6604 * Enable pixel doubling when the dot clock
6605 * is > 90% of the (display) core speed.
6606 *
b397c96b
VS		 6607 * GDG double wide on either pipe,
6608 * otherwise pipe A only.
cf532bb2 6609 */
b397c96b 6610 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 6611 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 6612 clock_limit *= 2;
cf532bb2 6613 pipe_config->double_wide = true;
ad3a4479
VS		 6614 }
6615
241bfc38 6616 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 6617 return -EINVAL;
2c07245f 6618 }
89749350 6619
1d1d0e27
VS		 6620 /*
6621 * Pipe horizontal size must be even in:
6622 * - DVO ganged mode
6623 * - LVDS dual channel mode
6624 * - Double wide pipe
6625 */
a93e255f 6626 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 6627 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6628 pipe_config->pipe_src_w &= ~1;
6629
8693a824
DL		 6630 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6631 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 6632 */
6633 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6634 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 6635 return -EINVAL;
44f46b42 6636
f5adf94e 6637 if (HAS_IPS(dev))
a43f6e0f
DV		 6638 hsw_compute_ips_config(crtc, pipe_config);
6639
877d48d5 6640 if (pipe_config->has_pch_encoder)
a43f6e0f 6641 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6642
cf5a15be 6643 return 0;
79e53945
JB		 6644}
6645
1652d19e
VS		 6646static int skylake_get_display_clock_speed(struct drm_device *dev)
6647{
6648 struct drm_i915_private *dev_priv = to_i915(dev);
6649 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6650 uint32_t cdctl = I915_READ(CDCLK_CTL);
6651 uint32_t linkrate;
6652
414355a7 6653 if (!(lcpll1 & LCPLL_PLL_ENABLE))
1652d19e 6654 return 24000; /* 24MHz is the cd freq with NSSC ref */
1652d19e
VS		 6655
6656 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6657 return 540000;
6658
6659 linkrate = (I915_READ(DPLL_CTRL1) &
71cd8423 6660 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1652d19e 6661
71cd8423
DL		 6662 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6663 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
1652d19e
VS		 6664 /* vco 8640 */
6665 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6666 case CDCLK_FREQ_450_432:
6667 return 432000;
6668 case CDCLK_FREQ_337_308:
6669 return 308570;
6670 case CDCLK_FREQ_675_617:
6671 return 617140;
6672 default:
6673 WARN(1, "Unknown cd freq selection\n");
6674 }
6675 } else {
6676 /* vco 8100 */
6677 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6678 case CDCLK_FREQ_450_432:
6679 return 450000;
6680 case CDCLK_FREQ_337_308:
6681 return 337500;
6682 case CDCLK_FREQ_675_617:
6683 return 675000;
6684 default:
6685 WARN(1, "Unknown cd freq selection\n");
6686 }
6687 }
6688
6689 /* error case, do as if DPLL0 isn't enabled */
6690 return 24000;
6691}
6692
6693static int broadwell_get_display_clock_speed(struct drm_device *dev)
6694{
6695 struct drm_i915_private *dev_priv = dev->dev_private;
6696 uint32_t lcpll = I915_READ(LCPLL_CTL);
6697 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6698
6699 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6700 return 800000;
6701 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6702 return 450000;
6703 else if (freq == LCPLL_CLK_FREQ_450)
6704 return 450000;
6705 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6706 return 540000;
6707 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6708 return 337500;
6709 else
6710 return 675000;
6711}
6712
6713static int haswell_get_display_clock_speed(struct drm_device *dev)
6714{
6715 struct drm_i915_private *dev_priv = dev->dev_private;
6716 uint32_t lcpll = I915_READ(LCPLL_CTL);
6717 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6718
6719 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6720 return 800000;
6721 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6722 return 450000;
6723 else if (freq == LCPLL_CLK_FREQ_450)
6724 return 450000;
6725 else if (IS_HSW_ULT(dev))
6726 return 337500;
6727 else
6728 return 540000;
79e53945
JB		 6729}
6730
25eb05fc
JB		 6731static int valleyview_get_display_clock_speed(struct drm_device *dev)
6732{
d197b7d3 6733 struct drm_i915_private *dev_priv = dev->dev_private;
d197b7d3
VS		 6734 u32 val;
6735 int divider;
6736
6bcda4f0
VS		 6737 if (dev_priv->hpll_freq == 0)
6738 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6739
a580516d 6740 mutex_lock(&dev_priv->sb_lock);
d197b7d3 6741 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
a580516d 6742 mutex_unlock(&dev_priv->sb_lock);
d197b7d3
VS		 6743
6744 divider = val & DISPLAY_FREQUENCY_VALUES;
6745
7d007f40
VS		 6746 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6747 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6748 "cdclk change in progress\n");
6749
6bcda4f0 6750 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
25eb05fc
JB		 6751}
6752
b37a6434
VS		 6753static int ilk_get_display_clock_speed(struct drm_device *dev)
6754{
6755 return 450000;
6756}
6757
e70236a8
JB		 6758static int i945_get_display_clock_speed(struct drm_device *dev)
6759{
6760 return 400000;
6761}
79e53945 6762
e70236a8 6763static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6764{
e907f170 6765 return 333333;
e70236a8 6766}
79e53945 6767
e70236a8
JB		 6768static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6769{
6770 return 200000;
6771}
79e53945 6772
257a7ffc
DV		 6773static int pnv_get_display_clock_speed(struct drm_device *dev)
6774{
6775 u16 gcfgc = 0;
6776
6777 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6778
6779 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6780 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6781 return 266667;
257a7ffc 6782 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6783 return 333333;
257a7ffc 6784 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6785 return 444444;
257a7ffc
DV		 6786 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6787 return 200000;
6788 default:
6789 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6790 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6791 return 133333;
257a7ffc 6792 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6793 return 166667;
257a7ffc
DV		 6794 }
6795}
6796
e70236a8
JB		 6797static int i915gm_get_display_clock_speed(struct drm_device *dev)
6798{
6799 u16 gcfgc = 0;
79e53945 6800
e70236a8
JB		 6801 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6802
6803 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6804 return 133333;
e70236a8
JB		 6805 else {
6806 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6807 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6808 return 333333;
e70236a8
JB		 6809 default:
6810 case GC_DISPLAY_CLOCK_190_200_MHZ:
6811 return 190000;
79e53945 6812 }
e70236a8
JB		 6813 }
6814}
6815
6816static int i865_get_display_clock_speed(struct drm_device *dev)
6817{
e907f170 6818 return 266667;
e70236a8
JB		 6819}
6820
1b1d2716 6821static int i85x_get_display_clock_speed(struct drm_device *dev)
e70236a8
JB		 6822{
6823 u16 hpllcc = 0;
1b1d2716 6824
65cd2b3f
VS		 6825 /*
6826 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6827 * encoding is different :(
6828 * FIXME is this the right way to detect 852GM/852GMV?
6829 */
6830 if (dev->pdev->revision == 0x1)
6831 return 133333;
6832
1b1d2716
VS		 6833 pci_bus_read_config_word(dev->pdev->bus,
6834 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6835
e70236a8
JB		 6836 /* Assume that the hardware is in the high speed state. This
6837 * should be the default.
6838 */
6839 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6840 case GC_CLOCK_133_200:
1b1d2716 6841 case GC_CLOCK_133_200_2:
e70236a8
JB		 6842 case GC_CLOCK_100_200:
6843 return 200000;
6844 case GC_CLOCK_166_250:
6845 return 250000;
6846 case GC_CLOCK_100_133:
e907f170 6847 return 133333;
1b1d2716
VS		 6848 case GC_CLOCK_133_266:
6849 case GC_CLOCK_133_266_2:
6850 case GC_CLOCK_166_266:
6851 return 266667;
e70236a8 6852 }
79e53945 6853
e70236a8
JB		 6854 /* Shouldn't happen */
6855 return 0;
6856}
79e53945 6857
e70236a8
JB		 6858static int i830_get_display_clock_speed(struct drm_device *dev)
6859{
e907f170 6860 return 133333;
79e53945
JB		 6861}
6862
34edce2f
VS		 6863static unsigned int intel_hpll_vco(struct drm_device *dev)
6864{
6865 struct drm_i915_private *dev_priv = dev->dev_private;
6866 static const unsigned int blb_vco[8] = {
6867 [0] = 3200000,
6868 [1] = 4000000,
6869 [2] = 5333333,
6870 [3] = 4800000,
6871 [4] = 6400000,
6872 };
6873 static const unsigned int pnv_vco[8] = {
6874 [0] = 3200000,
6875 [1] = 4000000,
6876 [2] = 5333333,
6877 [3] = 4800000,
6878 [4] = 2666667,
6879 };
6880 static const unsigned int cl_vco[8] = {
6881 [0] = 3200000,
6882 [1] = 4000000,
6883 [2] = 5333333,
6884 [3] = 6400000,
6885 [4] = 3333333,
6886 [5] = 3566667,
6887 [6] = 4266667,
6888 };
6889 static const unsigned int elk_vco[8] = {
6890 [0] = 3200000,
6891 [1] = 4000000,
6892 [2] = 5333333,
6893 [3] = 4800000,
6894 };
6895 static const unsigned int ctg_vco[8] = {
6896 [0] = 3200000,
6897 [1] = 4000000,
6898 [2] = 5333333,
6899 [3] = 6400000,
6900 [4] = 2666667,
6901 [5] = 4266667,
6902 };
6903 const unsigned int *vco_table;
6904 unsigned int vco;
6905 uint8_t tmp = 0;
6906
6907 /* FIXME other chipsets? */
6908 if (IS_GM45(dev))
6909 vco_table = ctg_vco;
6910 else if (IS_G4X(dev))
6911 vco_table = elk_vco;
6912 else if (IS_CRESTLINE(dev))
6913 vco_table = cl_vco;
6914 else if (IS_PINEVIEW(dev))
6915 vco_table = pnv_vco;
6916 else if (IS_G33(dev))
6917 vco_table = blb_vco;
6918 else
6919 return 0;
6920
6921 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6922
6923 vco = vco_table[tmp & 0x7];
6924 if (vco == 0)
6925 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6926 else
6927 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6928
6929 return vco;
6930}
6931
6932static int gm45_get_display_clock_speed(struct drm_device *dev)
6933{
6934 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6935 uint16_t tmp = 0;
6936
6937 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6938
6939 cdclk_sel = (tmp >> 12) & 0x1;
6940
6941 switch (vco) {
6942 case 2666667:
6943 case 4000000:
6944 case 5333333:
6945 return cdclk_sel ? 333333 : 222222;
6946 case 3200000:
6947 return cdclk_sel ? 320000 : 228571;
6948 default:
6949 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6950 return 222222;
6951 }
6952}
6953
6954static int i965gm_get_display_clock_speed(struct drm_device *dev)
6955{
6956 static const uint8_t div_3200[] = { 16, 10, 8 };
6957 static const uint8_t div_4000[] = { 20, 12, 10 };
6958 static const uint8_t div_5333[] = { 24, 16, 14 };
6959 const uint8_t *div_table;
6960 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6961 uint16_t tmp = 0;
6962
6963 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6964
6965 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6966
6967 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6968 goto fail;
6969
6970 switch (vco) {
6971 case 3200000:
6972 div_table = div_3200;
6973 break;
6974 case 4000000:
6975 div_table = div_4000;
6976 break;
6977 case 5333333:
6978 div_table = div_5333;
6979 break;
6980 default:
6981 goto fail;
6982 }
6983
6984 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6985
caf4e252 6986fail:
34edce2f
VS		 6987 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6988 return 200000;
6989}
6990
6991static int g33_get_display_clock_speed(struct drm_device *dev)
6992{
6993 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6994 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6995 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6996 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6997 const uint8_t *div_table;
6998 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6999 uint16_t tmp = 0;
7000
7001 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7002
7003 cdclk_sel = (tmp >> 4) & 0x7;
7004
7005 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7006 goto fail;
7007
7008 switch (vco) {
7009 case 3200000:
7010 div_table = div_3200;
7011 break;
7012 case 4000000:
7013 div_table = div_4000;
7014 break;
7015 case 4800000:
7016 div_table = div_4800;
7017 break;
7018 case 5333333:
7019 div_table = div_5333;
7020 break;
7021 default:
7022 goto fail;
7023 }
7024
7025 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7026
caf4e252 7027fail:
34edce2f
VS		 7028 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7029 return 190476;
7030}
7031
2c07245f 7032static void
a65851af 7033intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 7034{
a65851af
VS		 7035 while (*num > DATA_LINK_M_N_MASK ||
7036 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 7037 *num >>= 1;
7038 *den >>= 1;
7039 }
7040}
7041
a65851af
VS		 7042static void compute_m_n(unsigned int m, unsigned int n,
7043 uint32_t *ret_m, uint32_t *ret_n)
7044{
7045 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7046 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7047 intel_reduce_m_n_ratio(ret_m, ret_n);
7048}
7049
e69d0bc1
DV		 7050void
7051intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7052 int pixel_clock, int link_clock,
7053 struct intel_link_m_n *m_n)
2c07245f 7054{
e69d0bc1 7055 m_n->tu = 64;
a65851af
VS		 7056
7057 compute_m_n(bits_per_pixel * pixel_clock,
7058 link_clock * nlanes * 8,
7059 &m_n->gmch_m, &m_n->gmch_n);
7060
7061 compute_m_n(pixel_clock, link_clock,
7062 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 7063}
7064
a7615030
CW		 7065static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7066{
d330a953
JN		 7067 if (i915.panel_use_ssc >= 0)
7068 return i915.panel_use_ssc != 0;
41aa3448 7069 return dev_priv->vbt.lvds_use_ssc
435793df 7070 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 7071}
7072
a93e255f
ACO		 7073static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7074 int num_connectors)
c65d77d8 7075{
a93e255f 7076 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 7077 struct drm_i915_private *dev_priv = dev->dev_private;
7078 int refclk;
7079
a93e255f
ACO		 7080 WARN_ON(!crtc_state->base.state);
7081
5ab7b0b7 7082 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
9a0ea498 7083 refclk = 100000;
a93e255f 7084 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 7085 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 7086 refclk = dev_priv->vbt.lvds_ssc_freq;
7087 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 7088 } else if (!IS_GEN2(dev)) {
7089 refclk = 96000;
7090 } else {
7091 refclk = 48000;
7092 }
7093
7094 return refclk;
7095}
7096
7429e9d4 7097static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 7098{
7df00d7a 7099 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 7100}
f47709a9 7101
7429e9d4
DV		 7102static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7103{
7104 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 7105}
7106
f47709a9 7107static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 7108 struct intel_crtc_state *crtc_state,
a7516a05
JB		 7109 intel_clock_t *reduced_clock)
7110{
f47709a9 7111 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 7112 u32 fp, fp2 = 0;
7113
7114 if (IS_PINEVIEW(dev)) {
190f68c5 7115 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7116 if (reduced_clock)
7429e9d4 7117 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 7118 } else {
190f68c5 7119 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7120 if (reduced_clock)
7429e9d4 7121 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 7122 }
7123
190f68c5 7124 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 7125
f47709a9 7126 crtc->lowfreq_avail = false;
a93e255f 7127 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 7128 reduced_clock) {
190f68c5 7129 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 7130 crtc->lowfreq_avail = true;
a7516a05 7131 } else {
190f68c5 7132 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 7133 }
7134}
7135
5e69f97f
CML		 7136static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7137 pipe)
89b667f8
JB		 7138{
7139 u32 reg_val;
7140
7141 /*
7142 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7143 * and set it to a reasonable value instead.
7144 */
ab3c759a 7145 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 7146 reg_val &= 0xffffff00;
7147 reg_val |= 0x00000030;
ab3c759a 7148 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7149
ab3c759a 7150 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7151 reg_val &= 0x8cffffff;
7152 reg_val = 0x8c000000;
ab3c759a 7153 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 7154
ab3c759a 7155 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 7156 reg_val &= 0xffffff00;
ab3c759a 7157 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7158
ab3c759a 7159 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7160 reg_val &= 0x00ffffff;
7161 reg_val |= 0xb0000000;
ab3c759a 7162 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 7163}
7164
b551842d
DV		 7165static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7166 struct intel_link_m_n *m_n)
7167{
7168 struct drm_device *dev = crtc->base.dev;
7169 struct drm_i915_private *dev_priv = dev->dev_private;
7170 int pipe = crtc->pipe;
7171
e3b95f1e
DV		 7172 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7173 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7174 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7175 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 7176}
7177
7178static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 7179 struct intel_link_m_n *m_n,
7180 struct intel_link_m_n *m2_n2)
b551842d
DV		 7181{
7182 struct drm_device *dev = crtc->base.dev;
7183 struct drm_i915_private *dev_priv = dev->dev_private;
7184 int pipe = crtc->pipe;
6e3c9717 7185 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 7186
7187 if (INTEL_INFO(dev)->gen >= 5) {
7188 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7189 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7190 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7191 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 7192 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7193 * for gen < 8) and if DRRS is supported (to make sure the
7194 * registers are not unnecessarily accessed).
7195 */
44395bfe 7196 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 7197 crtc->config->has_drrs) {
f769cd24
VK		 7198 I915_WRITE(PIPE_DATA_M2(transcoder),
7199 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7200 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7201 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7202 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7203 }
b551842d 7204 } else {
e3b95f1e
DV		 7205 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7206 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7207 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7208 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 7209 }
7210}
7211
fe3cd48d 7212void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 7213{
fe3cd48d
R		 7214 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7215
7216 if (m_n == M1_N1) {
7217 dp_m_n = &crtc->config->dp_m_n;
7218 dp_m2_n2 = &crtc->config->dp_m2_n2;
7219 } else if (m_n == M2_N2) {
7220
7221 /*
7222 * M2_N2 registers are not supported. Hence m2_n2 divider value
7223 * needs to be programmed into M1_N1.
7224 */
7225 dp_m_n = &crtc->config->dp_m2_n2;
7226 } else {
7227 DRM_ERROR("Unsupported divider value\n");
7228 return;
7229 }
7230
6e3c9717
ACO		 7231 if (crtc->config->has_pch_encoder)
7232 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 7233 else
fe3cd48d 7234 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 7235}
7236
d288f65f 7237static void vlv_update_pll(struct intel_crtc *crtc,
5cec258b 7238 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 7239{
7240 u32 dpll, dpll_md;
7241
7242 /*
7243 * Enable DPIO clock input. We should never disable the reference
7244 * clock for pipe B, since VGA hotplug / manual detection depends
7245 * on it.
7246 */
7247 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
7248 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
7249 /* We should never disable this, set it here for state tracking */
7250 if (crtc->pipe == PIPE_B)
7251 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7252 dpll |= DPLL_VCO_ENABLE;
d288f65f 7253 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 7254
d288f65f 7255 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 7256 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 7257 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 7258}
7259
d288f65f 7260static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7261 const struct intel_crtc_state *pipe_config)
a0c4da24 7262{
f47709a9 7263 struct drm_device *dev = crtc->base.dev;
a0c4da24 7264 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 7265 int pipe = crtc->pipe;
bdd4b6a6 7266 u32 mdiv;
a0c4da24 7267 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 7268 u32 coreclk, reg_val;
a0c4da24 7269
a580516d 7270 mutex_lock(&dev_priv->sb_lock);
09153000 7271
d288f65f
VS		 7272 bestn = pipe_config->dpll.n;
7273 bestm1 = pipe_config->dpll.m1;
7274 bestm2 = pipe_config->dpll.m2;
7275 bestp1 = pipe_config->dpll.p1;
7276 bestp2 = pipe_config->dpll.p2;
a0c4da24 7277
89b667f8
JB		 7278 /* See eDP HDMI DPIO driver vbios notes doc */
7279
7280 /* PLL B needs special handling */
bdd4b6a6 7281 if (pipe == PIPE_B)
5e69f97f 7282 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 7283
7284 /* Set up Tx target for periodic Rcomp update */
ab3c759a 7285 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 7286
7287 /* Disable target IRef on PLL */
ab3c759a 7288 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 7289 reg_val &= 0x00ffffff;
ab3c759a 7290 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 7291
7292 /* Disable fast lock */
ab3c759a 7293 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 7294
7295 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 7296 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7297 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7298 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 7299 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 7300
7301 /*
7302 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7303 * but we don't support that).
7304 * Note: don't use the DAC post divider as it seems unstable.
7305 */
7306 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 7307 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7308
a0c4da24 7309 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 7310 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7311
89b667f8 7312 /* Set HBR and RBR LPF coefficients */
d288f65f 7313 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 7314 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7315 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 7316 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 7317 0x009f0003);
89b667f8 7318 else
ab3c759a 7319 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 7320 0x00d0000f);
7321
681a8504 7322 if (pipe_config->has_dp_encoder) {
89b667f8 7323 /* Use SSC source */
bdd4b6a6 7324 if (pipe == PIPE_A)
ab3c759a 7325 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7326 0x0df40000);
7327 else
ab3c759a 7328 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7329 0x0df70000);
7330 } else { /* HDMI or VGA */
7331 /* Use bend source */
bdd4b6a6 7332 if (pipe == PIPE_A)
ab3c759a 7333 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7334 0x0df70000);
7335 else
ab3c759a 7336 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7337 0x0df40000);
7338 }
a0c4da24 7339
ab3c759a 7340 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 7341 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 7342 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7343 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 7344 coreclk |= 0x01000000;
ab3c759a 7345 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 7346
ab3c759a 7347 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
a580516d 7348 mutex_unlock(&dev_priv->sb_lock);
a0c4da24
JB		 7349}
7350
d288f65f 7351static void chv_update_pll(struct intel_crtc *crtc,
5cec258b 7352 struct intel_crtc_state *pipe_config)
1ae0d137 7353{
d288f65f 7354 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
1ae0d137
VS		 7355 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7356 DPLL_VCO_ENABLE;
7357 if (crtc->pipe != PIPE_A)
d288f65f 7358 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 7359
d288f65f
VS		 7360 pipe_config->dpll_hw_state.dpll_md =
7361 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 7362}
7363
d288f65f 7364static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7365 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 7366{
7367 struct drm_device *dev = crtc->base.dev;
7368 struct drm_i915_private *dev_priv = dev->dev_private;
7369 int pipe = crtc->pipe;
7370 int dpll_reg = DPLL(crtc->pipe);
7371 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 7372 u32 loopfilter, tribuf_calcntr;
9d556c99 7373 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 7374 u32 dpio_val;
9cbe40c1 7375 int vco;
9d556c99 7376
d288f65f
VS		 7377 bestn = pipe_config->dpll.n;
7378 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7379 bestm1 = pipe_config->dpll.m1;
7380 bestm2 = pipe_config->dpll.m2 >> 22;
7381 bestp1 = pipe_config->dpll.p1;
7382 bestp2 = pipe_config->dpll.p2;
9cbe40c1 7383 vco = pipe_config->dpll.vco;
a945ce7e 7384 dpio_val = 0;
9cbe40c1 7385 loopfilter = 0;
9d556c99
CML		 7386
7387 /*
7388 * Enable Refclk and SSC
7389 */
a11b0703 7390 I915_WRITE(dpll_reg,
d288f65f 7391 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703 7392
a580516d 7393 mutex_lock(&dev_priv->sb_lock);
9d556c99 7394
9d556c99
CML		 7395 /* p1 and p2 divider */
7396 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7397 5 << DPIO_CHV_S1_DIV_SHIFT |
7398 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7399 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7400 1 << DPIO_CHV_K_DIV_SHIFT);
7401
7402 /* Feedback post-divider - m2 */
7403 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7404
7405 /* Feedback refclk divider - n and m1 */
7406 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7407 DPIO_CHV_M1_DIV_BY_2 |
7408 1 << DPIO_CHV_N_DIV_SHIFT);
7409
7410 /* M2 fraction division */
a945ce7e
VP		 7411 if (bestm2_frac)
7412 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 7413
7414 /* M2 fraction division enable */
a945ce7e
VP		 7415 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7416 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7417 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7418 if (bestm2_frac)
7419 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7420 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 7421
de3a0fde
VP		 7422 /* Program digital lock detect threshold */
7423 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7424 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7425 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7426 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7427 if (!bestm2_frac)
7428 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7429 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7430
9d556c99 7431 /* Loop filter */
9cbe40c1
VP		 7432 if (vco == 5400000) {
7433 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7434 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7435 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7436 tribuf_calcntr = 0x9;
7437 } else if (vco <= 6200000) {
7438 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7439 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7440 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7441 tribuf_calcntr = 0x9;
7442 } else if (vco <= 6480000) {
7443 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7444 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7445 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7446 tribuf_calcntr = 0x8;
7447 } else {
7448 /* Not supported. Apply the same limits as in the max case */
7449 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7450 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7451 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7452 tribuf_calcntr = 0;
7453 }
9d556c99
CML		 7454 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7455
968040b2 7456 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 7457 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7458 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7459 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7460
9d556c99
CML		 7461 /* AFC Recal */
7462 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7463 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7464 DPIO_AFC_RECAL);
7465
a580516d 7466 mutex_unlock(&dev_priv->sb_lock);
9d556c99
CML		 7467}
7468
d288f65f
VS		 7469/**
7470 * vlv_force_pll_on - forcibly enable just the PLL
7471 * @dev_priv: i915 private structure
7472 * @pipe: pipe PLL to enable
7473 * @dpll: PLL configuration
7474 *
7475 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7476 * in cases where we need the PLL enabled even when @pipe is not going to
7477 * be enabled.
7478 */
7479void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7480 const struct dpll *dpll)
7481{
7482 struct intel_crtc *crtc =
7483 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 7484 struct intel_crtc_state pipe_config = {
a93e255f 7485 .base.crtc = &crtc->base,
d288f65f
VS		 7486 .pixel_multiplier = 1,
7487 .dpll = *dpll,
7488 };
7489
7490 if (IS_CHERRYVIEW(dev)) {
7491 chv_update_pll(crtc, &pipe_config);
7492 chv_prepare_pll(crtc, &pipe_config);
7493 chv_enable_pll(crtc, &pipe_config);
7494 } else {
7495 vlv_update_pll(crtc, &pipe_config);
7496 vlv_prepare_pll(crtc, &pipe_config);
7497 vlv_enable_pll(crtc, &pipe_config);
7498 }
7499}
7500
7501/**
7502 * vlv_force_pll_off - forcibly disable just the PLL
7503 * @dev_priv: i915 private structure
7504 * @pipe: pipe PLL to disable
7505 *
7506 * Disable the PLL for @pipe. To be used in cases where we need
7507 * the PLL enabled even when @pipe is not going to be enabled.
7508 */
7509void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7510{
7511 if (IS_CHERRYVIEW(dev))
7512 chv_disable_pll(to_i915(dev), pipe);
7513 else
7514 vlv_disable_pll(to_i915(dev), pipe);
7515}
7516
f47709a9 7517static void i9xx_update_pll(struct intel_crtc *crtc,
190f68c5 7518 struct intel_crtc_state *crtc_state,
f47709a9 7519 intel_clock_t *reduced_clock,
eb1cbe48
DV		 7520 int num_connectors)
7521{
f47709a9 7522 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7523 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 7524 u32 dpll;
7525 bool is_sdvo;
190f68c5 7526 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7527
190f68c5 7528 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7529
a93e255f
ACO		 7530 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7531 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 7532
7533 dpll = DPLL_VGA_MODE_DIS;
7534
a93e255f 7535 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 7536 dpll |= DPLLB_MODE_LVDS;
7537 else
7538 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 7539
ef1b460d 7540 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 7541 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 7542 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 7543 }
198a037f
DV		 7544
7545 if (is_sdvo)
4a33e48d 7546 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 7547
190f68c5 7548 if (crtc_state->has_dp_encoder)
4a33e48d 7549 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 7550
7551 /* compute bitmask from p1 value */
7552 if (IS_PINEVIEW(dev))
7553 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7554 else {
7555 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7556 if (IS_G4X(dev) && reduced_clock)
7557 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7558 }
7559 switch (clock->p2) {
7560 case 5:
7561 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7562 break;
7563 case 7:
7564 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7565 break;
7566 case 10:
7567 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7568 break;
7569 case 14:
7570 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7571 break;
7572 }
7573 if (INTEL_INFO(dev)->gen >= 4)
7574 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7575
190f68c5 7576 if (crtc_state->sdvo_tv_clock)
eb1cbe48 7577 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 7578 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7579 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7580 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7581 else
7582 dpll |= PLL_REF_INPUT_DREFCLK;
7583
7584 dpll |= DPLL_VCO_ENABLE;
190f68c5 7585 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 7586
eb1cbe48 7587 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 7588 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 7589 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 7590 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 7591 }
7592}
7593
f47709a9 7594static void i8xx_update_pll(struct intel_crtc *crtc,
190f68c5 7595 struct intel_crtc_state *crtc_state,
f47709a9 7596 intel_clock_t *reduced_clock,
eb1cbe48
DV		 7597 int num_connectors)
7598{
f47709a9 7599 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7600 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 7601 u32 dpll;
190f68c5 7602 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7603
190f68c5 7604 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7605
eb1cbe48
DV		 7606 dpll = DPLL_VGA_MODE_DIS;
7607
a93e255f 7608 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 7609 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7610 } else {
7611 if (clock->p1 == 2)
7612 dpll |= PLL_P1_DIVIDE_BY_TWO;
7613 else
7614 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7615 if (clock->p2 == 4)
7616 dpll |= PLL_P2_DIVIDE_BY_4;
7617 }
7618
a93e255f 7619 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 7620 dpll |= DPLL_DVO_2X_MODE;
7621
a93e255f 7622 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7623 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7624 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7625 else
7626 dpll |= PLL_REF_INPUT_DREFCLK;
7627
7628 dpll |= DPLL_VCO_ENABLE;
190f68c5 7629 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 7630}
7631
8a654f3b 7632static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 7633{
7634 struct drm_device *dev = intel_crtc->base.dev;
7635 struct drm_i915_private *dev_priv = dev->dev_private;
7636 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7637 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8a654f3b 7638 struct drm_display_mode *adjusted_mode =
6e3c9717 7639 &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 7640 uint32_t crtc_vtotal, crtc_vblank_end;
7641 int vsyncshift = 0;
4d8a62ea
DV		 7642
7643 /* We need to be careful not to changed the adjusted mode, for otherwise
7644 * the hw state checker will get angry at the mismatch. */
7645 crtc_vtotal = adjusted_mode->crtc_vtotal;
7646 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 7647
609aeaca 7648 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 7649 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 7650 crtc_vtotal -= 1;
7651 crtc_vblank_end -= 1;
609aeaca 7652
409ee761 7653 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 7654 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7655 else
7656 vsyncshift = adjusted_mode->crtc_hsync_start -
7657 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 7658 if (vsyncshift < 0)
7659 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 7660 }
7661
7662 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 7663 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 7664
fe2b8f9d 7665 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 7666 (adjusted_mode->crtc_hdisplay - 1) |
7667 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 7668 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 7669 (adjusted_mode->crtc_hblank_start - 1) |
7670 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 7671 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 7672 (adjusted_mode->crtc_hsync_start - 1) |
7673 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7674
fe2b8f9d 7675 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 7676 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 7677 ((crtc_vtotal - 1) << 16));
fe2b8f9d 7678 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 7679 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 7680 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 7681 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 7682 (adjusted_mode->crtc_vsync_start - 1) |
7683 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7684
b5e508d4
PZ		 7685 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7686 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7687 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7688 * bits. */
7689 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7690 (pipe == PIPE_B || pipe == PIPE_C))
7691 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7692
b0e77b9c
PZ		 7693 /* pipesrc controls the size that is scaled from, which should
7694 * always be the user's requested size.
7695 */
7696 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 7697 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7698 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 7699}
7700
1bd1bd80 7701static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7702 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 7703{
7704 struct drm_device *dev = crtc->base.dev;
7705 struct drm_i915_private *dev_priv = dev->dev_private;
7706 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7707 uint32_t tmp;
7708
7709 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 7710 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7711 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7712 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 7713 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7714 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7715 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 7716 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7717 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7718
7719 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 7720 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7721 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7722 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 7723 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7724 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7725 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 7726 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7727 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7728
7729 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 7730 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7731 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7732 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 7733 }
7734
7735 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 7736 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7737 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7738
2d112de7
ACO		 7739 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7740 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 7741}
7742
f6a83288 7743void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7744 struct intel_crtc_state *pipe_config)
babea61d 7745{
2d112de7
ACO		 7746 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7747 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7748 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7749 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7750
2d112de7
ACO		 7751 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7752 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7753 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7754 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7755
2d112de7 7756 mode->flags = pipe_config->base.adjusted_mode.flags;
babea61d 7757
2d112de7
ACO		 7758 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7759 mode->flags |= pipe_config->base.adjusted_mode.flags;
babea61d
JB		 7760}
7761
84b046f3
DV		 7762static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7763{
7764 struct drm_device *dev = intel_crtc->base.dev;
7765 struct drm_i915_private *dev_priv = dev->dev_private;
7766 uint32_t pipeconf;
7767
9f11a9e4 7768 pipeconf = 0;
84b046f3 7769
b6b5d049
VS		 7770 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7771 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7772 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7773
6e3c9717 7774 if (intel_crtc->config->double_wide)
cf532bb2 7775 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7776
ff9ce46e
DV		 7777 /* only g4x and later have fancy bpc/dither controls */
7778 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 7779 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7780 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7781 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7782 PIPECONF_DITHER_TYPE_SP;
84b046f3 7783
6e3c9717 7784 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 7785 case 18:
7786 pipeconf |= PIPECONF_6BPC;
7787 break;
7788 case 24:
7789 pipeconf |= PIPECONF_8BPC;
7790 break;
7791 case 30:
7792 pipeconf |= PIPECONF_10BPC;
7793 break;
7794 default:
7795 /* Case prevented by intel_choose_pipe_bpp_dither. */
7796 BUG();
84b046f3
DV		 7797 }
7798 }
7799
7800 if (HAS_PIPE_CXSR(dev)) {
7801 if (intel_crtc->lowfreq_avail) {
7802 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7803 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7804 } else {
7805 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 7806 }
7807 }
7808
6e3c9717 7809 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7810 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7811 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 7812 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7813 else
7814 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7815 } else
84b046f3
DV		 7816 pipeconf |= PIPECONF_PROGRESSIVE;
7817
6e3c9717 7818 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 7819 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7820
84b046f3
DV		 7821 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7822 POSTING_READ(PIPECONF(intel_crtc->pipe));
7823}
7824
190f68c5
ACO		 7825static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7826 struct intel_crtc_state *crtc_state)
79e53945 7827{
c7653199 7828 struct drm_device *dev = crtc->base.dev;
79e53945 7829 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 7830 int refclk, num_connectors = 0;
652c393a 7831 intel_clock_t clock, reduced_clock;
a16af721 7832 bool ok, has_reduced_clock = false;
e9fd1c02 7833 bool is_lvds = false, is_dsi = false;
5eddb70b 7834 struct intel_encoder *encoder;
d4906093 7835 const intel_limit_t *limit;
55bb9992 7836 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 7837 struct drm_connector *connector;
55bb9992
ACO		 7838 struct drm_connector_state *connector_state;
7839 int i;
79e53945 7840
dd3cd74a
ACO		 7841 memset(&crtc_state->dpll_hw_state, 0,
7842 sizeof(crtc_state->dpll_hw_state));
7843
da3ced29 7844 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 7845 if (connector_state->crtc != &crtc->base)
7846 continue;
7847
7848 encoder = to_intel_encoder(connector_state->best_encoder);
7849
5eddb70b 7850 switch (encoder->type) {
79e53945
JB		 7851 case INTEL_OUTPUT_LVDS:
7852 is_lvds = true;
7853 break;
e9fd1c02
JN		 7854 case INTEL_OUTPUT_DSI:
7855 is_dsi = true;
7856 break;
6847d71b
PZ		 7857 default:
7858 break;
79e53945 7859 }
43565a06 7860
c751ce4f 7861 num_connectors++;
79e53945
JB		 7862 }
7863
f2335330 7864 if (is_dsi)
5b18e57c 7865 return 0;
f2335330 7866
190f68c5 7867 if (!crtc_state->clock_set) {
a93e255f 7868 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 7869
e9fd1c02
JN		 7870 /*
7871 * Returns a set of divisors for the desired target clock with
7872 * the given refclk, or FALSE. The returned values represent
7873 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7874 * 2) / p1 / p2.
7875 */
a93e255f
ACO		 7876 limit = intel_limit(crtc_state, refclk);
7877 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7878 crtc_state->port_clock,
e9fd1c02 7879 refclk, NULL, &clock);
f2335330 7880 if (!ok) {
e9fd1c02
JN		 7881 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7882 return -EINVAL;
7883 }
79e53945 7884
f2335330
JN		 7885 if (is_lvds && dev_priv->lvds_downclock_avail) {
7886 /*
7887 * Ensure we match the reduced clock's P to the target
7888 * clock. If the clocks don't match, we can't switch
7889 * the display clock by using the FP0/FP1. In such case
7890 * we will disable the LVDS downclock feature.
7891 */
7892 has_reduced_clock =
a93e255f 7893 dev_priv->display.find_dpll(limit, crtc_state,
f2335330
JN		 7894 dev_priv->lvds_downclock,
7895 refclk, &clock,
7896 &reduced_clock);
7897 }
7898 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7899 crtc_state->dpll.n = clock.n;
7900 crtc_state->dpll.m1 = clock.m1;
7901 crtc_state->dpll.m2 = clock.m2;
7902 crtc_state->dpll.p1 = clock.p1;
7903 crtc_state->dpll.p2 = clock.p2;
f47709a9 7904 }
7026d4ac 7905
e9fd1c02 7906 if (IS_GEN2(dev)) {
190f68c5 7907 i8xx_update_pll(crtc, crtc_state,
2a8f64ca
VP		 7908 has_reduced_clock ? &reduced_clock : NULL,
7909 num_connectors);
9d556c99 7910 } else if (IS_CHERRYVIEW(dev)) {
190f68c5 7911 chv_update_pll(crtc, crtc_state);
e9fd1c02 7912 } else if (IS_VALLEYVIEW(dev)) {
190f68c5 7913 vlv_update_pll(crtc, crtc_state);
e9fd1c02 7914 } else {
190f68c5 7915 i9xx_update_pll(crtc, crtc_state,
eb1cbe48 7916 has_reduced_clock ? &reduced_clock : NULL,
eba905b2 7917 num_connectors);
e9fd1c02 7918 }
79e53945 7919
c8f7a0db 7920 return 0;
f564048e
EA		 7921}
7922
2fa2fe9a 7923static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7924 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 7925{
7926 struct drm_device *dev = crtc->base.dev;
7927 struct drm_i915_private *dev_priv = dev->dev_private;
7928 uint32_t tmp;
7929
dc9e7dec
VS		 7930 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7931 return;
7932
2fa2fe9a 7933 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 7934 if (!(tmp & PFIT_ENABLE))
7935 return;
2fa2fe9a 7936
06922821 7937 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 7938 if (INTEL_INFO(dev)->gen < 4) {
7939 if (crtc->pipe != PIPE_B)
7940 return;
2fa2fe9a
DV		 7941 } else {
7942 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7943 return;
7944 }
7945
06922821 7946 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 7947 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7948 if (INTEL_INFO(dev)->gen < 5)
7949 pipe_config->gmch_pfit.lvds_border_bits =
7950 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7951}
7952
acbec814 7953static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7954 struct intel_crtc_state *pipe_config)
acbec814
JB		 7955{
7956 struct drm_device *dev = crtc->base.dev;
7957 struct drm_i915_private *dev_priv = dev->dev_private;
7958 int pipe = pipe_config->cpu_transcoder;
7959 intel_clock_t clock;
7960 u32 mdiv;
662c6ecb 7961 int refclk = 100000;
acbec814 7962
f573de5a
SK		 7963 /* In case of MIPI DPLL will not even be used */
7964 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7965 return;
7966
a580516d 7967 mutex_lock(&dev_priv->sb_lock);
ab3c759a 7968 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
a580516d 7969 mutex_unlock(&dev_priv->sb_lock);
acbec814
JB		 7970
7971 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7972 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7973 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7974 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7975 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7976
f646628b 7977 vlv_clock(refclk, &clock);
acbec814 7978
f646628b
VS		 7979 /* clock.dot is the fast clock */
7980 pipe_config->port_clock = clock.dot / 5;
acbec814
JB		 7981}
7982
5724dbd1
DL		 7983static void
7984i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7985 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 7986{
7987 struct drm_device *dev = crtc->base.dev;
7988 struct drm_i915_private *dev_priv = dev->dev_private;
7989 u32 val, base, offset;
7990 int pipe = crtc->pipe, plane = crtc->plane;
7991 int fourcc, pixel_format;
6761dd31 7992 unsigned int aligned_height;
b113d5ee 7993 struct drm_framebuffer *fb;
1b842c89 7994 struct intel_framebuffer *intel_fb;
1ad292b5 7995
42a7b088
DL		 7996 val = I915_READ(DSPCNTR(plane));
7997 if (!(val & DISPLAY_PLANE_ENABLE))
7998 return;
7999
d9806c9f 8000 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8001 if (!intel_fb) {
1ad292b5
JB		 8002 DRM_DEBUG_KMS("failed to alloc fb\n");
8003 return;
8004 }
8005
1b842c89
DL		 8006 fb = &intel_fb->base;
8007
18c5247e
DV		 8008 if (INTEL_INFO(dev)->gen >= 4) {
8009 if (val & DISPPLANE_TILED) {
49af449b 8010 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 8011 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8012 }
8013 }
1ad292b5
JB		 8014
8015 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 8016 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 8017 fb->pixel_format = fourcc;
8018 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 8019
8020 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 8021 if (plane_config->tiling)
1ad292b5
JB		 8022 offset = I915_READ(DSPTILEOFF(plane));
8023 else
8024 offset = I915_READ(DSPLINOFF(plane));
8025 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8026 } else {
8027 base = I915_READ(DSPADDR(plane));
8028 }
8029 plane_config->base = base;
8030
8031 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 8032 fb->width = ((val >> 16) & 0xfff) + 1;
8033 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 8034
8035 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 8036 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 8037
b113d5ee 8038 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8039 fb->pixel_format,
8040 fb->modifier[0]);
1ad292b5 8041
f37b5c2b 8042 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 8043
2844a921
DL		 8044 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8045 pipe_name(pipe), plane, fb->width, fb->height,
8046 fb->bits_per_pixel, base, fb->pitches[0],
8047 plane_config->size);
1ad292b5 8048
2d14030b 8049 plane_config->fb = intel_fb;
1ad292b5
JB		 8050}
8051
70b23a98 8052static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 8053 struct intel_crtc_state *pipe_config)
70b23a98
VS		 8054{
8055 struct drm_device *dev = crtc->base.dev;
8056 struct drm_i915_private *dev_priv = dev->dev_private;
8057 int pipe = pipe_config->cpu_transcoder;
8058 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8059 intel_clock_t clock;
8060 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
8061 int refclk = 100000;
8062
a580516d 8063 mutex_lock(&dev_priv->sb_lock);
70b23a98
VS		 8064 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8065 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8066 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8067 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
a580516d 8068 mutex_unlock(&dev_priv->sb_lock);
70b23a98
VS		 8069
8070 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8071 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
8072 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8073 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8074 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8075
8076 chv_clock(refclk, &clock);
8077
8078 /* clock.dot is the fast clock */
8079 pipe_config->port_clock = clock.dot / 5;
8080}
8081
0e8ffe1b 8082static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8083 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8084{
8085 struct drm_device *dev = crtc->base.dev;
8086 struct drm_i915_private *dev_priv = dev->dev_private;
8087 uint32_t tmp;
8088
f458ebbc
DV		 8089 if (!intel_display_power_is_enabled(dev_priv,
8090 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 8091 return false;
8092
e143a21c 8093 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8094 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8095
0e8ffe1b
DV		 8096 tmp = I915_READ(PIPECONF(crtc->pipe));
8097 if (!(tmp & PIPECONF_ENABLE))
8098 return false;
8099
42571aef
VS		 8100 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8101 switch (tmp & PIPECONF_BPC_MASK) {
8102 case PIPECONF_6BPC:
8103 pipe_config->pipe_bpp = 18;
8104 break;
8105 case PIPECONF_8BPC:
8106 pipe_config->pipe_bpp = 24;
8107 break;
8108 case PIPECONF_10BPC:
8109 pipe_config->pipe_bpp = 30;
8110 break;
8111 default:
8112 break;
8113 }
8114 }
8115
b5a9fa09
DV		 8116 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8117 pipe_config->limited_color_range = true;
8118
282740f7
VS		 8119 if (INTEL_INFO(dev)->gen < 4)
8120 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8121
1bd1bd80
DV		 8122 intel_get_pipe_timings(crtc, pipe_config);
8123
2fa2fe9a
DV		 8124 i9xx_get_pfit_config(crtc, pipe_config);
8125
6c49f241
DV		 8126 if (INTEL_INFO(dev)->gen >= 4) {
8127 tmp = I915_READ(DPLL_MD(crtc->pipe));
8128 pipe_config->pixel_multiplier =
8129 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8130 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 8131 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 8132 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8133 tmp = I915_READ(DPLL(crtc->pipe));
8134 pipe_config->pixel_multiplier =
8135 ((tmp & SDVO_MULTIPLIER_MASK)
8136 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8137 } else {
8138 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8139 * port and will be fixed up in the encoder->get_config
8140 * function. */
8141 pipe_config->pixel_multiplier = 1;
8142 }
8bcc2795
DV		 8143 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8144 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 8145 /*
8146 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8147 * on 830. Filter it out here so that we don't
8148 * report errors due to that.
8149 */
8150 if (IS_I830(dev))
8151 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8152
8bcc2795
DV		 8153 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8154 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 8155 } else {
8156 /* Mask out read-only status bits. */
8157 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8158 DPLL_PORTC_READY_MASK |
8159 DPLL_PORTB_READY_MASK);
8bcc2795 8160 }
6c49f241 8161
70b23a98
VS		 8162 if (IS_CHERRYVIEW(dev))
8163 chv_crtc_clock_get(crtc, pipe_config);
8164 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 8165 vlv_crtc_clock_get(crtc, pipe_config);
8166 else
8167 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 8168
0e8ffe1b
DV		 8169 return true;
8170}
8171
dde86e2d 8172static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 8173{
8174 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 8175 struct intel_encoder *encoder;
74cfd7ac 8176 u32 val, final;
13d83a67 8177 bool has_lvds = false;
199e5d79 8178 bool has_cpu_edp = false;
199e5d79 8179 bool has_panel = false;
99eb6a01
KP		 8180 bool has_ck505 = false;
8181 bool can_ssc = false;
13d83a67
JB		 8182
8183 /* We need to take the global config into account */
b2784e15 8184 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 8185 switch (encoder->type) {
8186 case INTEL_OUTPUT_LVDS:
8187 has_panel = true;
8188 has_lvds = true;
8189 break;
8190 case INTEL_OUTPUT_EDP:
8191 has_panel = true;
2de6905f 8192 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 8193 has_cpu_edp = true;
8194 break;
6847d71b
PZ		 8195 default:
8196 break;
13d83a67
JB		 8197 }
8198 }
8199
99eb6a01 8200 if (HAS_PCH_IBX(dev)) {
41aa3448 8201 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 8202 can_ssc = has_ck505;
8203 } else {
8204 has_ck505 = false;
8205 can_ssc = true;
8206 }
8207
2de6905f
ID		 8208 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8209 has_panel, has_lvds, has_ck505);
13d83a67
JB		 8210
8211 /* Ironlake: try to setup display ref clock before DPLL
8212 * enabling. This is only under driver's control after
8213 * PCH B stepping, previous chipset stepping should be
8214 * ignoring this setting.
8215 */
74cfd7ac
CW		 8216 val = I915_READ(PCH_DREF_CONTROL);
8217
8218 /* As we must carefully and slowly disable/enable each source in turn,
8219 * compute the final state we want first and check if we need to
8220 * make any changes at all.
8221 */
8222 final = val;
8223 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8224 if (has_ck505)
8225 final |= DREF_NONSPREAD_CK505_ENABLE;
8226 else
8227 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8228
8229 final &= ~DREF_SSC_SOURCE_MASK;
8230 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8231 final &= ~DREF_SSC1_ENABLE;
8232
8233 if (has_panel) {
8234 final |= DREF_SSC_SOURCE_ENABLE;
8235
8236 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8237 final |= DREF_SSC1_ENABLE;
8238
8239 if (has_cpu_edp) {
8240 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8241 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8242 else
8243 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8244 } else
8245 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8246 } else {
8247 final |= DREF_SSC_SOURCE_DISABLE;
8248 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8249 }
8250
8251 if (final == val)
8252 return;
8253
13d83a67 8254 /* Always enable nonspread source */
74cfd7ac 8255 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 8256
99eb6a01 8257 if (has_ck505)
74cfd7ac 8258 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 8259 else
74cfd7ac 8260 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 8261
199e5d79 8262 if (has_panel) {
74cfd7ac
CW		 8263 val &= ~DREF_SSC_SOURCE_MASK;
8264 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 8265
199e5d79 8266 /* SSC must be turned on before enabling the CPU output */
99eb6a01 8267 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8268 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 8269 val |= DREF_SSC1_ENABLE;
e77166b5 8270 } else
74cfd7ac 8271 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 8272
8273 /* Get SSC going before enabling the outputs */
74cfd7ac 8274 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8275 POSTING_READ(PCH_DREF_CONTROL);
8276 udelay(200);
8277
74cfd7ac 8278 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 8279
8280 /* Enable CPU source on CPU attached eDP */
199e5d79 8281 if (has_cpu_edp) {
99eb6a01 8282 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8283 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 8284 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 8285 } else
74cfd7ac 8286 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 8287 } else
74cfd7ac 8288 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8289
74cfd7ac 8290 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8291 POSTING_READ(PCH_DREF_CONTROL);
8292 udelay(200);
8293 } else {
8294 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8295
74cfd7ac 8296 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 8297
8298 /* Turn off CPU output */
74cfd7ac 8299 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8300
74cfd7ac 8301 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8302 POSTING_READ(PCH_DREF_CONTROL);
8303 udelay(200);
8304
8305 /* Turn off the SSC source */
74cfd7ac
CW		 8306 val &= ~DREF_SSC_SOURCE_MASK;
8307 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 8308
8309 /* Turn off SSC1 */
74cfd7ac 8310 val &= ~DREF_SSC1_ENABLE;
199e5d79 8311
74cfd7ac 8312 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 8313 POSTING_READ(PCH_DREF_CONTROL);
8314 udelay(200);
8315 }
74cfd7ac
CW		 8316
8317 BUG_ON(val != final);
13d83a67
JB		 8318}
8319
f31f2d55 8320static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 8321{
f31f2d55 8322 uint32_t tmp;
dde86e2d 8323
0ff066a9
PZ		 8324 tmp = I915_READ(SOUTH_CHICKEN2);
8325 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8326 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8327
0ff066a9
PZ		 8328 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8329 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8330 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 8331
0ff066a9
PZ		 8332 tmp = I915_READ(SOUTH_CHICKEN2);
8333 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8334 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8335
0ff066a9
PZ		 8336 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8337 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8338 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 8339}
8340
8341/* WaMPhyProgramming:hsw */
8342static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8343{
8344 uint32_t tmp;
dde86e2d
PZ		 8345
8346 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8347 tmp &= ~(0xFF << 24);
8348 tmp |= (0x12 << 24);
8349 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8350
dde86e2d
PZ		 8351 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8352 tmp |= (1 << 11);
8353 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8354
8355 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8356 tmp |= (1 << 11);
8357 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8358
dde86e2d
PZ		 8359 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8360 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8361 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8362
8363 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8364 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8365 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8366
0ff066a9
PZ		 8367 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8368 tmp &= ~(7 << 13);
8369 tmp |= (5 << 13);
8370 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 8371
0ff066a9
PZ		 8372 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8373 tmp &= ~(7 << 13);
8374 tmp |= (5 << 13);
8375 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 8376
8377 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8378 tmp &= ~0xFF;
8379 tmp |= 0x1C;
8380 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8381
8382 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8383 tmp &= ~0xFF;
8384 tmp |= 0x1C;
8385 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8386
8387 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8388 tmp &= ~(0xFF << 16);
8389 tmp |= (0x1C << 16);
8390 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8391
8392 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8393 tmp &= ~(0xFF << 16);
8394 tmp |= (0x1C << 16);
8395 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8396
0ff066a9
PZ		 8397 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8398 tmp |= (1 << 27);
8399 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 8400
0ff066a9
PZ		 8401 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8402 tmp |= (1 << 27);
8403 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 8404
0ff066a9
PZ		 8405 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8406 tmp &= ~(0xF << 28);
8407 tmp |= (4 << 28);
8408 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 8409
0ff066a9
PZ		 8410 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8411 tmp &= ~(0xF << 28);
8412 tmp |= (4 << 28);
8413 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 8414}
8415
2fa86a1f
PZ		 8416/* Implements 3 different sequences from BSpec chapter "Display iCLK
8417 * Programming" based on the parameters passed:
8418 * - Sequence to enable CLKOUT_DP
8419 * - Sequence to enable CLKOUT_DP without spread
8420 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8421 */
8422static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8423 bool with_fdi)
f31f2d55
PZ		 8424{
8425 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 8426 uint32_t reg, tmp;
8427
8428 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8429 with_spread = true;
8430 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8431 with_fdi, "LP PCH doesn't have FDI\n"))
8432 with_fdi = false;
f31f2d55 8433
a580516d 8434 mutex_lock(&dev_priv->sb_lock);
f31f2d55
PZ		 8435
8436 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8437 tmp &= ~SBI_SSCCTL_DISABLE;
8438 tmp |= SBI_SSCCTL_PATHALT;
8439 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8440
8441 udelay(24);
8442
2fa86a1f
PZ		 8443 if (with_spread) {
8444 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8445 tmp &= ~SBI_SSCCTL_PATHALT;
8446 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 8447
2fa86a1f
PZ		 8448 if (with_fdi) {
8449 lpt_reset_fdi_mphy(dev_priv);
8450 lpt_program_fdi_mphy(dev_priv);
8451 }
8452 }
dde86e2d 8453
2fa86a1f
PZ		 8454 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8455 SBI_GEN0 : SBI_DBUFF0;
8456 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8457 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8458 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246 8459
a580516d 8460 mutex_unlock(&dev_priv->sb_lock);
dde86e2d
PZ		 8461}
8462
47701c3b
PZ		 8463/* Sequence to disable CLKOUT_DP */
8464static void lpt_disable_clkout_dp(struct drm_device *dev)
8465{
8466 struct drm_i915_private *dev_priv = dev->dev_private;
8467 uint32_t reg, tmp;
8468
a580516d 8469 mutex_lock(&dev_priv->sb_lock);
47701c3b
PZ		 8470
8471 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8472 SBI_GEN0 : SBI_DBUFF0;
8473 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8474 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8475 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8476
8477 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8478 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8479 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8480 tmp |= SBI_SSCCTL_PATHALT;
8481 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8482 udelay(32);
8483 }
8484 tmp |= SBI_SSCCTL_DISABLE;
8485 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8486 }
8487
a580516d 8488 mutex_unlock(&dev_priv->sb_lock);
47701c3b
PZ		 8489}
8490
bf8fa3d3
PZ		 8491static void lpt_init_pch_refclk(struct drm_device *dev)
8492{
bf8fa3d3
PZ		 8493 struct intel_encoder *encoder;
8494 bool has_vga = false;
8495
b2784e15 8496 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 8497 switch (encoder->type) {
8498 case INTEL_OUTPUT_ANALOG:
8499 has_vga = true;
8500 break;
6847d71b
PZ		 8501 default:
8502 break;
bf8fa3d3
PZ		 8503 }
8504 }
8505
47701c3b
PZ		 8506 if (has_vga)
8507 lpt_enable_clkout_dp(dev, true, true);
8508 else
8509 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 8510}
8511
dde86e2d
PZ		 8512/*
8513 * Initialize reference clocks when the driver loads
8514 */
8515void intel_init_pch_refclk(struct drm_device *dev)
8516{
8517 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8518 ironlake_init_pch_refclk(dev);
8519 else if (HAS_PCH_LPT(dev))
8520 lpt_init_pch_refclk(dev);
8521}
8522
55bb9992 8523static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 8524{
55bb9992 8525 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 8526 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8527 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8528 struct drm_connector *connector;
55bb9992 8529 struct drm_connector_state *connector_state;
d9d444cb 8530 struct intel_encoder *encoder;
55bb9992 8531 int num_connectors = 0, i;
d9d444cb
JB		 8532 bool is_lvds = false;
8533
da3ced29 8534 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8535 if (connector_state->crtc != crtc_state->base.crtc)
8536 continue;
8537
8538 encoder = to_intel_encoder(connector_state->best_encoder);
8539
d9d444cb
JB		 8540 switch (encoder->type) {
8541 case INTEL_OUTPUT_LVDS:
8542 is_lvds = true;
8543 break;
6847d71b
PZ		 8544 default:
8545 break;
d9d444cb
JB		 8546 }
8547 num_connectors++;
8548 }
8549
8550 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 8551 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 8552 dev_priv->vbt.lvds_ssc_freq);
e91e941b 8553 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 8554 }
8555
8556 return 120000;
8557}
8558
6ff93609 8559static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 8560{
c8203565 8561 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 8562 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8563 int pipe = intel_crtc->pipe;
c8203565
PZ		 8564 uint32_t val;
8565
78114071 8566 val = 0;
c8203565 8567
6e3c9717 8568 switch (intel_crtc->config->pipe_bpp) {
c8203565 8569 case 18:
dfd07d72 8570 val |= PIPECONF_6BPC;
c8203565
PZ		 8571 break;
8572 case 24:
dfd07d72 8573 val |= PIPECONF_8BPC;
c8203565
PZ		 8574 break;
8575 case 30:
dfd07d72 8576 val |= PIPECONF_10BPC;
c8203565
PZ		 8577 break;
8578 case 36:
dfd07d72 8579 val |= PIPECONF_12BPC;
c8203565
PZ		 8580 break;
8581 default:
cc769b62
PZ		 8582 /* Case prevented by intel_choose_pipe_bpp_dither. */
8583 BUG();
c8203565
PZ		 8584 }
8585
6e3c9717 8586 if (intel_crtc->config->dither)
c8203565
PZ		 8587 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8588
6e3c9717 8589 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 8590 val |= PIPECONF_INTERLACED_ILK;
8591 else
8592 val |= PIPECONF_PROGRESSIVE;
8593
6e3c9717 8594 if (intel_crtc->config->limited_color_range)
3685a8f3 8595 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 8596
c8203565
PZ		 8597 I915_WRITE(PIPECONF(pipe), val);
8598 POSTING_READ(PIPECONF(pipe));
8599}
8600
86d3efce
VS		 8601/*
8602 * Set up the pipe CSC unit.
8603 *
8604 * Currently only full range RGB to limited range RGB conversion
8605 * is supported, but eventually this should handle various
8606 * RGB<->YCbCr scenarios as well.
8607 */
50f3b016 8608static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 8609{
8610 struct drm_device *dev = crtc->dev;
8611 struct drm_i915_private *dev_priv = dev->dev_private;
8612 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8613 int pipe = intel_crtc->pipe;
8614 uint16_t coeff = 0x7800; /* 1.0 */
8615
8616 /*
8617 * TODO: Check what kind of values actually come out of the pipe
8618 * with these coeff/postoff values and adjust to get the best
8619 * accuracy. Perhaps we even need to take the bpc value into
8620 * consideration.
8621 */
8622
6e3c9717 8623 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8624 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8625
8626 /*
8627 * GY/GU and RY/RU should be the other way around according
8628 * to BSpec, but reality doesn't agree. Just set them up in
8629 * a way that results in the correct picture.
8630 */
8631 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8632 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8633
8634 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8635 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8636
8637 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8638 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8639
8640 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8641 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8642 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8643
8644 if (INTEL_INFO(dev)->gen > 6) {
8645 uint16_t postoff = 0;
8646
6e3c9717 8647 if (intel_crtc->config->limited_color_range)
32cf0cb0 8648 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 8649
8650 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8651 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8652 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8653
8654 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8655 } else {
8656 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8657
6e3c9717 8658 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8659 mode |= CSC_BLACK_SCREEN_OFFSET;
8660
8661 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8662 }
8663}
8664
6ff93609 8665static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8666{
756f85cf
PZ		 8667 struct drm_device *dev = crtc->dev;
8668 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 8669 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8670 enum pipe pipe = intel_crtc->pipe;
6e3c9717 8671 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 8672 uint32_t val;
8673
3eff4faa 8674 val = 0;
ee2b0b38 8675
6e3c9717 8676 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 8677 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8678
6e3c9717 8679 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 8680 val |= PIPECONF_INTERLACED_ILK;
8681 else
8682 val |= PIPECONF_PROGRESSIVE;
8683
702e7a56
PZ		 8684 I915_WRITE(PIPECONF(cpu_transcoder), val);
8685 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 8686
8687 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8688 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 8689
3cdf122c 8690 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 8691 val = 0;
8692
6e3c9717 8693 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 8694 case 18:
8695 val |= PIPEMISC_DITHER_6_BPC;
8696 break;
8697 case 24:
8698 val |= PIPEMISC_DITHER_8_BPC;
8699 break;
8700 case 30:
8701 val |= PIPEMISC_DITHER_10_BPC;
8702 break;
8703 case 36:
8704 val |= PIPEMISC_DITHER_12_BPC;
8705 break;
8706 default:
8707 /* Case prevented by pipe_config_set_bpp. */
8708 BUG();
8709 }
8710
6e3c9717 8711 if (intel_crtc->config->dither)
756f85cf
PZ		 8712 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8713
8714 I915_WRITE(PIPEMISC(pipe), val);
8715 }
ee2b0b38
PZ		 8716}
8717
6591c6e4 8718static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 8719 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 8720 intel_clock_t *clock,
8721 bool *has_reduced_clock,
8722 intel_clock_t *reduced_clock)
8723{
8724 struct drm_device *dev = crtc->dev;
8725 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 8726 int refclk;
d4906093 8727 const intel_limit_t *limit;
a16af721 8728 bool ret, is_lvds = false;
79e53945 8729
a93e255f 8730 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
79e53945 8731
55bb9992 8732 refclk = ironlake_get_refclk(crtc_state);
79e53945 8733
d4906093
ML		 8734 /*
8735 * Returns a set of divisors for the desired target clock with the given
8736 * refclk, or FALSE. The returned values represent the clock equation:
8737 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8738 */
a93e255f
ACO		 8739 limit = intel_limit(crtc_state, refclk);
8740 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 8741 crtc_state->port_clock,
ee9300bb 8742 refclk, NULL, clock);
6591c6e4
PZ		 8743 if (!ret)
8744 return false;
cda4b7d3 8745
ddc9003c 8746 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 8747 /*
8748 * Ensure we match the reduced clock's P to the target clock.
8749 * If the clocks don't match, we can't switch the display clock
8750 * by using the FP0/FP1. In such case we will disable the LVDS
8751 * downclock feature.
8752 */
ee9300bb 8753 *has_reduced_clock =
a93e255f 8754 dev_priv->display.find_dpll(limit, crtc_state,
ee9300bb
DV		 8755 dev_priv->lvds_downclock,
8756 refclk, clock,
8757 reduced_clock);
652c393a 8758 }
61e9653f 8759
6591c6e4
PZ		 8760 return true;
8761}
8762
d4b1931c
PZ		 8763int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8764{
8765 /*
8766 * Account for spread spectrum to avoid
8767 * oversubscribing the link. Max center spread
8768 * is 2.5%; use 5% for safety's sake.
8769 */
8770 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8771 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 8772}
8773
7429e9d4 8774static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8775{
7429e9d4 8776 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 8777}
8778
de13a2e3 8779static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 8780 struct intel_crtc_state *crtc_state,
7429e9d4 8781 u32 *fp,
9a7c7890 8782 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 8783{
de13a2e3 8784 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 8785 struct drm_device *dev = crtc->dev;
8786 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8787 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8788 struct drm_connector *connector;
55bb9992
ACO		 8789 struct drm_connector_state *connector_state;
8790 struct intel_encoder *encoder;
de13a2e3 8791 uint32_t dpll;
55bb9992 8792 int factor, num_connectors = 0, i;
09ede541 8793 bool is_lvds = false, is_sdvo = false;
79e53945 8794
da3ced29 8795 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8796 if (connector_state->crtc != crtc_state->base.crtc)
8797 continue;
8798
8799 encoder = to_intel_encoder(connector_state->best_encoder);
8800
8801 switch (encoder->type) {
79e53945
JB		 8802 case INTEL_OUTPUT_LVDS:
8803 is_lvds = true;
8804 break;
8805 case INTEL_OUTPUT_SDVO:
7d57382e 8806 case INTEL_OUTPUT_HDMI:
79e53945 8807 is_sdvo = true;
79e53945 8808 break;
6847d71b
PZ		 8809 default:
8810 break;
79e53945 8811 }
43565a06 8812
c751ce4f 8813 num_connectors++;
79e53945 8814 }
79e53945 8815
c1858123 8816 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 8817 factor = 21;
8818 if (is_lvds) {
8819 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8820 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8821 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8822 factor = 25;
190f68c5 8823 } else if (crtc_state->sdvo_tv_clock)
8febb297 8824 factor = 20;
c1858123 8825
190f68c5 8826 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 8827 *fp |= FP_CB_TUNE;
2c07245f 8828
9a7c7890
DV		 8829 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8830 *fp2 |= FP_CB_TUNE;
8831
5eddb70b 8832 dpll = 0;
2c07245f 8833
a07d6787
EA		 8834 if (is_lvds)
8835 dpll |= DPLLB_MODE_LVDS;
8836 else
8837 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8838
190f68c5 8839 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8840 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 8841
8842 if (is_sdvo)
4a33e48d 8843 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8844 if (crtc_state->has_dp_encoder)
4a33e48d 8845 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8846
a07d6787 8847 /* compute bitmask from p1 value */
190f68c5 8848 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8849 /* also FPA1 */
190f68c5 8850 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8851
190f68c5 8852 switch (crtc_state->dpll.p2) {
a07d6787
EA		 8853 case 5:
8854 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8855 break;
8856 case 7:
8857 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8858 break;
8859 case 10:
8860 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8861 break;
8862 case 14:
8863 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8864 break;
79e53945
JB		 8865 }
8866
b4c09f3b 8867 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 8868 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 8869 else
8870 dpll |= PLL_REF_INPUT_DREFCLK;
8871
959e16d6 8872 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 8873}
8874
190f68c5
ACO		 8875static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8876 struct intel_crtc_state *crtc_state)
de13a2e3 8877{
c7653199 8878 struct drm_device *dev = crtc->base.dev;
de13a2e3 8879 intel_clock_t clock, reduced_clock;
cbbab5bd 8880 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 8881 bool ok, has_reduced_clock = false;
8b47047b 8882 bool is_lvds = false;
e2b78267 8883 struct intel_shared_dpll *pll;
de13a2e3 8884
dd3cd74a
ACO		 8885 memset(&crtc_state->dpll_hw_state, 0,
8886 sizeof(crtc_state->dpll_hw_state));
8887
409ee761 8888 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 8889
5dc5298b
PZ		 8890 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8891 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 8892
190f68c5 8893 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 8894 &has_reduced_clock, &reduced_clock);
190f68c5 8895 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 8896 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8897 return -EINVAL;
79e53945 8898 }
f47709a9 8899 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 8900 if (!crtc_state->clock_set) {
8901 crtc_state->dpll.n = clock.n;
8902 crtc_state->dpll.m1 = clock.m1;
8903 crtc_state->dpll.m2 = clock.m2;
8904 crtc_state->dpll.p1 = clock.p1;
8905 crtc_state->dpll.p2 = clock.p2;
f47709a9 8906 }
79e53945 8907
5dc5298b 8908 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 8909 if (crtc_state->has_pch_encoder) {
8910 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 8911 if (has_reduced_clock)
7429e9d4 8912 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 8913
190f68c5 8914 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 8915 &fp, &reduced_clock,
8916 has_reduced_clock ? &fp2 : NULL);
8917
190f68c5
ACO		 8918 crtc_state->dpll_hw_state.dpll = dpll;
8919 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 8920 if (has_reduced_clock)
190f68c5 8921 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 8922 else
190f68c5 8923 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 8924
190f68c5 8925 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 8926 if (pll == NULL) {
84f44ce7 8927 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 8928 pipe_name(crtc->pipe));
4b645f14
JB		 8929 return -EINVAL;
8930 }
3fb37703 8931 }
79e53945 8932
ab585dea 8933 if (is_lvds && has_reduced_clock)
c7653199 8934 crtc->lowfreq_avail = true;
bcd644e0 8935 else
c7653199 8936 crtc->lowfreq_avail = false;
e2b78267 8937
c8f7a0db 8938 return 0;
79e53945
JB		 8939}
8940
eb14cb74
VS		 8941static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8942 struct intel_link_m_n *m_n)
8943{
8944 struct drm_device *dev = crtc->base.dev;
8945 struct drm_i915_private *dev_priv = dev->dev_private;
8946 enum pipe pipe = crtc->pipe;
8947
8948 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8949 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8950 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8951 & ~TU_SIZE_MASK;
8952 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8953 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8954 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8955}
8956
8957static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8958 enum transcoder transcoder,
b95af8be
VK		 8959 struct intel_link_m_n *m_n,
8960 struct intel_link_m_n *m2_n2)
72419203
DV		 8961{
8962 struct drm_device *dev = crtc->base.dev;
8963 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 8964 enum pipe pipe = crtc->pipe;
72419203 8965
eb14cb74
VS		 8966 if (INTEL_INFO(dev)->gen >= 5) {
8967 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8968 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8969 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8970 & ~TU_SIZE_MASK;
8971 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8972 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8973 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 8974 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8975 * gen < 8) and if DRRS is supported (to make sure the
8976 * registers are not unnecessarily read).
8977 */
8978 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 8979 crtc->config->has_drrs) {
b95af8be
VK		 8980 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8981 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8982 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8983 & ~TU_SIZE_MASK;
8984 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8985 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8986 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8987 }
eb14cb74
VS		 8988 } else {
8989 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8990 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8991 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8992 & ~TU_SIZE_MASK;
8993 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8994 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8995 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8996 }
8997}
8998
8999void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 9000 struct intel_crtc_state *pipe_config)
eb14cb74 9001{
681a8504 9002 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 9003 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9004 else
9005 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 9006 &pipe_config->dp_m_n,
9007 &pipe_config->dp_m2_n2);
eb14cb74 9008}
72419203 9009
eb14cb74 9010static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 9011 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 9012{
9013 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 9014 &pipe_config->fdi_m_n, NULL);
72419203
DV		 9015}
9016
bd2e244f 9017static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9018 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 9019{
9020 struct drm_device *dev = crtc->base.dev;
9021 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK		 9022 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9023 uint32_t ps_ctrl = 0;
9024 int id = -1;
9025 int i;
bd2e244f 9026
a1b2278e
CK		 9027 /* find scaler attached to this pipe */
9028 for (i = 0; i < crtc->num_scalers; i++) {
9029 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9030 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9031 id = i;
9032 pipe_config->pch_pfit.enabled = true;
9033 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9034 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9035 break;
9036 }
9037 }
bd2e244f 9038
a1b2278e
CK		 9039 scaler_state->scaler_id = id;
9040 if (id >= 0) {
9041 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9042 } else {
9043 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB		 9044 }
9045}
9046
5724dbd1
DL		 9047static void
9048skylake_get_initial_plane_config(struct intel_crtc *crtc,
9049 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 9050{
9051 struct drm_device *dev = crtc->base.dev;
9052 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 9053 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 9054 int pipe = crtc->pipe;
9055 int fourcc, pixel_format;
6761dd31 9056 unsigned int aligned_height;
bc8d7dff 9057 struct drm_framebuffer *fb;
1b842c89 9058 struct intel_framebuffer *intel_fb;
bc8d7dff 9059
d9806c9f 9060 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9061 if (!intel_fb) {
bc8d7dff
DL		 9062 DRM_DEBUG_KMS("failed to alloc fb\n");
9063 return;
9064 }
9065
1b842c89
DL		 9066 fb = &intel_fb->base;
9067
bc8d7dff 9068 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 9069 if (!(val & PLANE_CTL_ENABLE))
9070 goto error;
9071
bc8d7dff
DL		 9072 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9073 fourcc = skl_format_to_fourcc(pixel_format,
9074 val & PLANE_CTL_ORDER_RGBX,
9075 val & PLANE_CTL_ALPHA_MASK);
9076 fb->pixel_format = fourcc;
9077 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9078
40f46283
DL		 9079 tiling = val & PLANE_CTL_TILED_MASK;
9080 switch (tiling) {
9081 case PLANE_CTL_TILED_LINEAR:
9082 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9083 break;
9084 case PLANE_CTL_TILED_X:
9085 plane_config->tiling = I915_TILING_X;
9086 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9087 break;
9088 case PLANE_CTL_TILED_Y:
9089 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9090 break;
9091 case PLANE_CTL_TILED_YF:
9092 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9093 break;
9094 default:
9095 MISSING_CASE(tiling);
9096 goto error;
9097 }
9098
bc8d7dff
DL		 9099 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9100 plane_config->base = base;
9101
9102 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9103
9104 val = I915_READ(PLANE_SIZE(pipe, 0));
9105 fb->height = ((val >> 16) & 0xfff) + 1;
9106 fb->width = ((val >> 0) & 0x1fff) + 1;
9107
9108 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 9109 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9110 fb->pixel_format);
bc8d7dff
DL		 9111 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9112
9113 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9114 fb->pixel_format,
9115 fb->modifier[0]);
bc8d7dff 9116
f37b5c2b 9117 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 9118
9119 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9120 pipe_name(pipe), fb->width, fb->height,
9121 fb->bits_per_pixel, base, fb->pitches[0],
9122 plane_config->size);
9123
2d14030b 9124 plane_config->fb = intel_fb;
bc8d7dff
DL		 9125 return;
9126
9127error:
9128 kfree(fb);
9129}
9130
2fa2fe9a 9131static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9132 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 9133{
9134 struct drm_device *dev = crtc->base.dev;
9135 struct drm_i915_private *dev_priv = dev->dev_private;
9136 uint32_t tmp;
9137
9138 tmp = I915_READ(PF_CTL(crtc->pipe));
9139
9140 if (tmp & PF_ENABLE) {
fd4daa9c 9141 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 9142 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9143 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 9144
9145 /* We currently do not free assignements of panel fitters on
9146 * ivb/hsw (since we don't use the higher upscaling modes which
9147 * differentiates them) so just WARN about this case for now. */
9148 if (IS_GEN7(dev)) {
9149 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9150 PF_PIPE_SEL_IVB(crtc->pipe));
9151 }
2fa2fe9a 9152 }
79e53945
JB		 9153}
9154
5724dbd1
DL		 9155static void
9156ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9157 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 9158{
9159 struct drm_device *dev = crtc->base.dev;
9160 struct drm_i915_private *dev_priv = dev->dev_private;
9161 u32 val, base, offset;
aeee5a49 9162 int pipe = crtc->pipe;
4c6baa59 9163 int fourcc, pixel_format;
6761dd31 9164 unsigned int aligned_height;
b113d5ee 9165 struct drm_framebuffer *fb;
1b842c89 9166 struct intel_framebuffer *intel_fb;
4c6baa59 9167
42a7b088
DL		 9168 val = I915_READ(DSPCNTR(pipe));
9169 if (!(val & DISPLAY_PLANE_ENABLE))
9170 return;
9171
d9806c9f 9172 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9173 if (!intel_fb) {
4c6baa59
JB		 9174 DRM_DEBUG_KMS("failed to alloc fb\n");
9175 return;
9176 }
9177
1b842c89
DL		 9178 fb = &intel_fb->base;
9179
18c5247e
DV		 9180 if (INTEL_INFO(dev)->gen >= 4) {
9181 if (val & DISPPLANE_TILED) {
49af449b 9182 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 9183 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9184 }
9185 }
4c6baa59
JB		 9186
9187 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 9188 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 9189 fb->pixel_format = fourcc;
9190 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 9191
aeee5a49 9192 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 9193 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 9194 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 9195 } else {
49af449b 9196 if (plane_config->tiling)
aeee5a49 9197 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 9198 else
aeee5a49 9199 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 9200 }
9201 plane_config->base = base;
9202
9203 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 9204 fb->width = ((val >> 16) & 0xfff) + 1;
9205 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 9206
9207 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 9208 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 9209
b113d5ee 9210 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9211 fb->pixel_format,
9212 fb->modifier[0]);
4c6baa59 9213
f37b5c2b 9214 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 9215
2844a921
DL		 9216 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9217 pipe_name(pipe), fb->width, fb->height,
9218 fb->bits_per_pixel, base, fb->pitches[0],
9219 plane_config->size);
b113d5ee 9220
2d14030b 9221 plane_config->fb = intel_fb;
4c6baa59
JB		 9222}
9223
0e8ffe1b 9224static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9225 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9226{
9227 struct drm_device *dev = crtc->base.dev;
9228 struct drm_i915_private *dev_priv = dev->dev_private;
9229 uint32_t tmp;
9230
f458ebbc
DV		 9231 if (!intel_display_power_is_enabled(dev_priv,
9232 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 9233 return false;
9234
e143a21c 9235 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 9236 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 9237
0e8ffe1b
DV		 9238 tmp = I915_READ(PIPECONF(crtc->pipe));
9239 if (!(tmp & PIPECONF_ENABLE))
9240 return false;
9241
42571aef
VS		 9242 switch (tmp & PIPECONF_BPC_MASK) {
9243 case PIPECONF_6BPC:
9244 pipe_config->pipe_bpp = 18;
9245 break;
9246 case PIPECONF_8BPC:
9247 pipe_config->pipe_bpp = 24;
9248 break;
9249 case PIPECONF_10BPC:
9250 pipe_config->pipe_bpp = 30;
9251 break;
9252 case PIPECONF_12BPC:
9253 pipe_config->pipe_bpp = 36;
9254 break;
9255 default:
9256 break;
9257 }
9258
b5a9fa09
DV		 9259 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9260 pipe_config->limited_color_range = true;
9261
ab9412ba 9262 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 9263 struct intel_shared_dpll *pll;
9264
88adfff1
DV		 9265 pipe_config->has_pch_encoder = true;
9266
627eb5a3
DV		 9267 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9268 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9269 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 9270
9271 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 9272
c0d43d62 9273 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 9274 pipe_config->shared_dpll =
9275 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 9276 } else {
9277 tmp = I915_READ(PCH_DPLL_SEL);
9278 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9279 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9280 else
9281 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9282 }
66e985c0
DV		 9283
9284 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9285
9286 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9287 &pipe_config->dpll_hw_state));
c93f54cf
DV		 9288
9289 tmp = pipe_config->dpll_hw_state.dpll;
9290 pipe_config->pixel_multiplier =
9291 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9292 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 9293
9294 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 9295 } else {
9296 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 9297 }
9298
1bd1bd80
DV		 9299 intel_get_pipe_timings(crtc, pipe_config);
9300
2fa2fe9a
DV		 9301 ironlake_get_pfit_config(crtc, pipe_config);
9302
0e8ffe1b
DV		 9303 return true;
9304}
9305
be256dc7
PZ		 9306static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9307{
9308 struct drm_device *dev = dev_priv->dev;
be256dc7 9309 struct intel_crtc *crtc;
be256dc7 9310
d3fcc808 9311 for_each_intel_crtc(dev, crtc)
e2c719b7 9312 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 9313 pipe_name(crtc->pipe));
9314
e2c719b7
RC		 9315 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9316 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9317 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9318 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9319 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9320 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 9321 "CPU PWM1 enabled\n");
c5107b87 9322 if (IS_HASWELL(dev))
e2c719b7 9323 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 9324 "CPU PWM2 enabled\n");
e2c719b7 9325 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 9326 "PCH PWM1 enabled\n");
e2c719b7 9327 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 9328 "Utility pin enabled\n");
e2c719b7 9329 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 9330
9926ada1
PZ		 9331 /*
9332 * In theory we can still leave IRQs enabled, as long as only the HPD
9333 * interrupts remain enabled. We used to check for that, but since it's
9334 * gen-specific and since we only disable LCPLL after we fully disable
9335 * the interrupts, the check below should be enough.
9336 */
e2c719b7 9337 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 9338}
9339
9ccd5aeb
PZ		 9340static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9341{
9342 struct drm_device *dev = dev_priv->dev;
9343
9344 if (IS_HASWELL(dev))
9345 return I915_READ(D_COMP_HSW);
9346 else
9347 return I915_READ(D_COMP_BDW);
9348}
9349
3c4c9b81
PZ		 9350static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9351{
9352 struct drm_device *dev = dev_priv->dev;
9353
9354 if (IS_HASWELL(dev)) {
9355 mutex_lock(&dev_priv->rps.hw_lock);
9356 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9357 val))
f475dadf 9358 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 9359 mutex_unlock(&dev_priv->rps.hw_lock);
9360 } else {
9ccd5aeb
PZ		 9361 I915_WRITE(D_COMP_BDW, val);
9362 POSTING_READ(D_COMP_BDW);
3c4c9b81 9363 }
be256dc7
PZ		 9364}
9365
9366/*
9367 * This function implements pieces of two sequences from BSpec:
9368 * - Sequence for display software to disable LCPLL
9369 * - Sequence for display software to allow package C8+
9370 * The steps implemented here are just the steps that actually touch the LCPLL
9371 * register. Callers should take care of disabling all the display engine
9372 * functions, doing the mode unset, fixing interrupts, etc.
9373 */
6ff58d53
PZ		 9374static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9375 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 9376{
9377 uint32_t val;
9378
9379 assert_can_disable_lcpll(dev_priv);
9380
9381 val = I915_READ(LCPLL_CTL);
9382
9383 if (switch_to_fclk) {
9384 val |= LCPLL_CD_SOURCE_FCLK;
9385 I915_WRITE(LCPLL_CTL, val);
9386
9387 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9388 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9389 DRM_ERROR("Switching to FCLK failed\n");
9390
9391 val = I915_READ(LCPLL_CTL);
9392 }
9393
9394 val |= LCPLL_PLL_DISABLE;
9395 I915_WRITE(LCPLL_CTL, val);
9396 POSTING_READ(LCPLL_CTL);
9397
9398 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9399 DRM_ERROR("LCPLL still locked\n");
9400
9ccd5aeb 9401 val = hsw_read_dcomp(dev_priv);
be256dc7 9402 val |= D_COMP_COMP_DISABLE;
3c4c9b81 9403 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9404 ndelay(100);
9405
9ccd5aeb
PZ		 9406 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9407 1))
be256dc7
PZ		 9408 DRM_ERROR("D_COMP RCOMP still in progress\n");
9409
9410 if (allow_power_down) {
9411 val = I915_READ(LCPLL_CTL);
9412 val |= LCPLL_POWER_DOWN_ALLOW;
9413 I915_WRITE(LCPLL_CTL, val);
9414 POSTING_READ(LCPLL_CTL);
9415 }
9416}
9417
9418/*
9419 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9420 * source.
9421 */
6ff58d53 9422static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 9423{
9424 uint32_t val;
9425
9426 val = I915_READ(LCPLL_CTL);
9427
9428 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9429 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9430 return;
9431
a8a8bd54
PZ		 9432 /*
9433 * Make sure we're not on PC8 state before disabling PC8, otherwise
9434 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 9435 */
59bad947 9436 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 9437
be256dc7
PZ		 9438 if (val & LCPLL_POWER_DOWN_ALLOW) {
9439 val &= ~LCPLL_POWER_DOWN_ALLOW;
9440 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 9441 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 9442 }
9443
9ccd5aeb 9444 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 9445 val |= D_COMP_COMP_FORCE;
9446 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 9447 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9448
9449 val = I915_READ(LCPLL_CTL);
9450 val &= ~LCPLL_PLL_DISABLE;
9451 I915_WRITE(LCPLL_CTL, val);
9452
9453 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9454 DRM_ERROR("LCPLL not locked yet\n");
9455
9456 if (val & LCPLL_CD_SOURCE_FCLK) {
9457 val = I915_READ(LCPLL_CTL);
9458 val &= ~LCPLL_CD_SOURCE_FCLK;
9459 I915_WRITE(LCPLL_CTL, val);
9460
9461 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9462 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9463 DRM_ERROR("Switching back to LCPLL failed\n");
9464 }
215733fa 9465
59bad947 9466 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b6283055 9467 intel_update_cdclk(dev_priv->dev);
be256dc7
PZ		 9468}
9469
765dab67
PZ		 9470/*
9471 * Package states C8 and deeper are really deep PC states that can only be
9472 * reached when all the devices on the system allow it, so even if the graphics
9473 * device allows PC8+, it doesn't mean the system will actually get to these
9474 * states. Our driver only allows PC8+ when going into runtime PM.
9475 *
9476 * The requirements for PC8+ are that all the outputs are disabled, the power
9477 * well is disabled and most interrupts are disabled, and these are also
9478 * requirements for runtime PM. When these conditions are met, we manually do
9479 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9480 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9481 * hang the machine.
9482 *
9483 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9484 * the state of some registers, so when we come back from PC8+ we need to
9485 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9486 * need to take care of the registers kept by RC6. Notice that this happens even
9487 * if we don't put the device in PCI D3 state (which is what currently happens
9488 * because of the runtime PM support).
9489 *
9490 * For more, read "Display Sequences for Package C8" on the hardware
9491 * documentation.
9492 */
a14cb6fc 9493void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 9494{
c67a470b
PZ		 9495 struct drm_device *dev = dev_priv->dev;
9496 uint32_t val;
9497
c67a470b
PZ		 9498 DRM_DEBUG_KMS("Enabling package C8+\n");
9499
c67a470b
PZ		 9500 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9501 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9502 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9503 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9504 }
9505
9506 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 9507 hsw_disable_lcpll(dev_priv, true, true);
9508}
9509
a14cb6fc 9510void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 9511{
9512 struct drm_device *dev = dev_priv->dev;
9513 uint32_t val;
9514
c67a470b
PZ		 9515 DRM_DEBUG_KMS("Disabling package C8+\n");
9516
9517 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 9518 lpt_init_pch_refclk(dev);
9519
9520 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9521 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9522 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9523 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9524 }
9525
9526 intel_prepare_ddi(dev);
c67a470b
PZ		 9527}
9528
a821fc46 9529static void broxton_modeset_global_resources(struct drm_atomic_state *old_state)
f8437dd1 9530{
a821fc46 9531 struct drm_device *dev = old_state->dev;
f8437dd1 9532 struct drm_i915_private *dev_priv = dev->dev_private;
a821fc46 9533 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
f8437dd1
VK		 9534 int req_cdclk;
9535
9536 /* see the comment in valleyview_modeset_global_resources */
9537 if (WARN_ON(max_pixclk < 0))
9538 return;
9539
9540 req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
9541
9542 if (req_cdclk != dev_priv->cdclk_freq)
9543 broxton_set_cdclk(dev, req_cdclk);
9544}
9545
b432e5cf
VS		 9546/* compute the max rate for new configuration */
9547static int ilk_max_pixel_rate(struct drm_i915_private *dev_priv)
9548{
9549 struct drm_device *dev = dev_priv->dev;
9550 struct intel_crtc *intel_crtc;
9551 struct drm_crtc *crtc;
9552 int max_pixel_rate = 0;
9553 int pixel_rate;
9554
9555 for_each_crtc(dev, crtc) {
9556 if (!crtc->state->enable)
9557 continue;
9558
9559 intel_crtc = to_intel_crtc(crtc);
9560 pixel_rate = ilk_pipe_pixel_rate(intel_crtc->config);
9561
9562 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9563 if (IS_BROADWELL(dev) && intel_crtc->config->ips_enabled)
9564 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9565
9566 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9567 }
9568
9569 return max_pixel_rate;
9570}
9571
9572static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9573{
9574 struct drm_i915_private *dev_priv = dev->dev_private;
9575 uint32_t val, data;
9576 int ret;
9577
9578 if (WARN((I915_READ(LCPLL_CTL) &
9579 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9580 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9581 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9582 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9583 "trying to change cdclk frequency with cdclk not enabled\n"))
9584 return;
9585
9586 mutex_lock(&dev_priv->rps.hw_lock);
9587 ret = sandybridge_pcode_write(dev_priv,
9588 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9589 mutex_unlock(&dev_priv->rps.hw_lock);
9590 if (ret) {
9591 DRM_ERROR("failed to inform pcode about cdclk change\n");
9592 return;
9593 }
9594
9595 val = I915_READ(LCPLL_CTL);
9596 val |= LCPLL_CD_SOURCE_FCLK;
9597 I915_WRITE(LCPLL_CTL, val);
9598
9599 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9600 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9601 DRM_ERROR("Switching to FCLK failed\n");
9602
9603 val = I915_READ(LCPLL_CTL);
9604 val &= ~LCPLL_CLK_FREQ_MASK;
9605
9606 switch (cdclk) {
9607 case 450000:
9608 val |= LCPLL_CLK_FREQ_450;
9609 data = 0;
9610 break;
9611 case 540000:
9612 val |= LCPLL_CLK_FREQ_54O_BDW;
9613 data = 1;
9614 break;
9615 case 337500:
9616 val |= LCPLL_CLK_FREQ_337_5_BDW;
9617 data = 2;
9618 break;
9619 case 675000:
9620 val |= LCPLL_CLK_FREQ_675_BDW;
9621 data = 3;
9622 break;
9623 default:
9624 WARN(1, "invalid cdclk frequency\n");
9625 return;
9626 }
9627
9628 I915_WRITE(LCPLL_CTL, val);
9629
9630 val = I915_READ(LCPLL_CTL);
9631 val &= ~LCPLL_CD_SOURCE_FCLK;
9632 I915_WRITE(LCPLL_CTL, val);
9633
9634 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9635 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9636 DRM_ERROR("Switching back to LCPLL failed\n");
9637
9638 mutex_lock(&dev_priv->rps.hw_lock);
9639 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9640 mutex_unlock(&dev_priv->rps.hw_lock);
9641
9642 intel_update_cdclk(dev);
9643
9644 WARN(cdclk != dev_priv->cdclk_freq,
9645 "cdclk requested %d kHz but got %d kHz\n",
9646 cdclk, dev_priv->cdclk_freq);
9647}
9648
9649static int broadwell_calc_cdclk(struct drm_i915_private *dev_priv,
9650 int max_pixel_rate)
9651{
9652 int cdclk;
9653
9654 /*
9655 * FIXME should also account for plane ratio
9656 * once 64bpp pixel formats are supported.
9657 */
9658 if (max_pixel_rate > 540000)
9659 cdclk = 675000;
9660 else if (max_pixel_rate > 450000)
9661 cdclk = 540000;
9662 else if (max_pixel_rate > 337500)
9663 cdclk = 450000;
9664 else
9665 cdclk = 337500;
9666
9667 /*
9668 * FIXME move the cdclk caclulation to
9669 * compute_config() so we can fail gracegully.
9670 */
9671 if (cdclk > dev_priv->max_cdclk_freq) {
9672 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9673 cdclk, dev_priv->max_cdclk_freq);
9674 cdclk = dev_priv->max_cdclk_freq;
9675 }
9676
9677 return cdclk;
9678}
9679
9680static int broadwell_modeset_global_pipes(struct drm_atomic_state *state)
9681{
9682 struct drm_i915_private *dev_priv = to_i915(state->dev);
9683 struct drm_crtc *crtc;
9684 struct drm_crtc_state *crtc_state;
9685 int max_pixclk = ilk_max_pixel_rate(dev_priv);
9686 int cdclk, i;
9687
9688 cdclk = broadwell_calc_cdclk(dev_priv, max_pixclk);
9689
9690 if (cdclk == dev_priv->cdclk_freq)
9691 return 0;
9692
9693 /* add all active pipes to the state */
9694 for_each_crtc(state->dev, crtc) {
9695 if (!crtc->state->enable)
9696 continue;
9697
9698 crtc_state = drm_atomic_get_crtc_state(state, crtc);
9699 if (IS_ERR(crtc_state))
9700 return PTR_ERR(crtc_state);
9701 }
9702
9703 /* disable/enable all currently active pipes while we change cdclk */
9704 for_each_crtc_in_state(state, crtc, crtc_state, i)
9705 if (crtc_state->enable)
9706 crtc_state->mode_changed = true;
9707
9708 return 0;
9709}
9710
9711static void broadwell_modeset_global_resources(struct drm_atomic_state *state)
9712{
9713 struct drm_device *dev = state->dev;
9714 struct drm_i915_private *dev_priv = dev->dev_private;
9715 int max_pixel_rate = ilk_max_pixel_rate(dev_priv);
9716 int req_cdclk = broadwell_calc_cdclk(dev_priv, max_pixel_rate);
9717
9718 if (req_cdclk != dev_priv->cdclk_freq)
9719 broadwell_set_cdclk(dev, req_cdclk);
9720}
9721
190f68c5
ACO		 9722static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9723 struct intel_crtc_state *crtc_state)
09b4ddf9 9724{
190f68c5 9725 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 9726 return -EINVAL;
716c2e55 9727
c7653199 9728 crtc->lowfreq_avail = false;
644cef34 9729
c8f7a0db 9730 return 0;
79e53945
JB		 9731}
9732
3760b59c
S		 9733static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9734 enum port port,
9735 struct intel_crtc_state *pipe_config)
9736{
9737 switch (port) {
9738 case PORT_A:
9739 pipe_config->ddi_pll_sel = SKL_DPLL0;
9740 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9741 break;
9742 case PORT_B:
9743 pipe_config->ddi_pll_sel = SKL_DPLL1;
9744 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9745 break;
9746 case PORT_C:
9747 pipe_config->ddi_pll_sel = SKL_DPLL2;
9748 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9749 break;
9750 default:
9751 DRM_ERROR("Incorrect port type\n");
9752 }
9753}
9754
96b7dfb7
S		 9755static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9756 enum port port,
5cec258b 9757 struct intel_crtc_state *pipe_config)
96b7dfb7 9758{
3148ade7 9759 u32 temp, dpll_ctl1;
96b7dfb7
S		 9760
9761 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9762 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9763
9764 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 9765 case SKL_DPLL0:
9766 /*
9767 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9768 * of the shared DPLL framework and thus needs to be read out
9769 * separately
9770 */
9771 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9772 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9773 break;
96b7dfb7
S		 9774 case SKL_DPLL1:
9775 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9776 break;
9777 case SKL_DPLL2:
9778 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9779 break;
9780 case SKL_DPLL3:
9781 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9782 break;
96b7dfb7
S		 9783 }
9784}
9785
7d2c8175
DL		 9786static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9787 enum port port,
5cec258b 9788 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 9789{
9790 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9791
9792 switch (pipe_config->ddi_pll_sel) {
9793 case PORT_CLK_SEL_WRPLL1:
9794 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9795 break;
9796 case PORT_CLK_SEL_WRPLL2:
9797 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9798 break;
9799 }
9800}
9801
26804afd 9802static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 9803 struct intel_crtc_state *pipe_config)
26804afd
DV		 9804{
9805 struct drm_device *dev = crtc->base.dev;
9806 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 9807 struct intel_shared_dpll *pll;
26804afd
DV		 9808 enum port port;
9809 uint32_t tmp;
9810
9811 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9812
9813 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9814
96b7dfb7
S		 9815 if (IS_SKYLAKE(dev))
9816 skylake_get_ddi_pll(dev_priv, port, pipe_config);
3760b59c
S		 9817 else if (IS_BROXTON(dev))
9818 bxt_get_ddi_pll(dev_priv, port, pipe_config);
96b7dfb7
S		 9819 else
9820 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 9821
d452c5b6
DV		 9822 if (pipe_config->shared_dpll >= 0) {
9823 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9824
9825 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9826 &pipe_config->dpll_hw_state));
9827 }
9828
26804afd
DV		 9829 /*
9830 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9831 * DDI E. So just check whether this pipe is wired to DDI E and whether
9832 * the PCH transcoder is on.
9833 */
ca370455
DL		 9834 if (INTEL_INFO(dev)->gen < 9 &&
9835 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 9836 pipe_config->has_pch_encoder = true;
9837
9838 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9839 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9840 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9841
9842 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9843 }
9844}
9845
0e8ffe1b 9846static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9847 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9848{
9849 struct drm_device *dev = crtc->base.dev;
9850 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 9851 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 9852 uint32_t tmp;
9853
f458ebbc 9854 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 9855 POWER_DOMAIN_PIPE(crtc->pipe)))
9856 return false;
9857
e143a21c 9858 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 9859 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9860
eccb140b
DV		 9861 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9862 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9863 enum pipe trans_edp_pipe;
9864 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9865 default:
9866 WARN(1, "unknown pipe linked to edp transcoder\n");
9867 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9868 case TRANS_DDI_EDP_INPUT_A_ON:
9869 trans_edp_pipe = PIPE_A;
9870 break;
9871 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9872 trans_edp_pipe = PIPE_B;
9873 break;
9874 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9875 trans_edp_pipe = PIPE_C;
9876 break;
9877 }
9878
9879 if (trans_edp_pipe == crtc->pipe)
9880 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9881 }
9882
f458ebbc 9883 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 9884 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 9885 return false;
9886
eccb140b 9887 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 9888 if (!(tmp & PIPECONF_ENABLE))
9889 return false;
9890
26804afd 9891 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 9892
1bd1bd80
DV		 9893 intel_get_pipe_timings(crtc, pipe_config);
9894
a1b2278e
CK		 9895 if (INTEL_INFO(dev)->gen >= 9) {
9896 skl_init_scalers(dev, crtc, pipe_config);
9897 }
9898
2fa2fe9a 9899 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
af99ceda
CK		 9900
9901 if (INTEL_INFO(dev)->gen >= 9) {
9902 pipe_config->scaler_state.scaler_id = -1;
9903 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9904 }
9905
bd2e244f 9906 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
ff6d9f55 9907 if (INTEL_INFO(dev)->gen == 9)
bd2e244f 9908 skylake_get_pfit_config(crtc, pipe_config);
ff6d9f55 9909 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 9910 ironlake_get_pfit_config(crtc, pipe_config);
ff6d9f55
JB		 9911 else
9912 MISSING_CASE(INTEL_INFO(dev)->gen);
bd2e244f 9913 }
88adfff1 9914
e59150dc
JB		 9915 if (IS_HASWELL(dev))
9916 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9917 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 9918
ebb69c95
CT		 9919 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9920 pipe_config->pixel_multiplier =
9921 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9922 } else {
9923 pipe_config->pixel_multiplier = 1;
9924 }
6c49f241 9925
0e8ffe1b
DV		 9926 return true;
9927}
9928
560b85bb
CW		 9929static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9930{
9931 struct drm_device *dev = crtc->dev;
9932 struct drm_i915_private *dev_priv = dev->dev_private;
9933 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 9934 uint32_t cntl = 0, size = 0;
560b85bb 9935
dc41c154 9936 if (base) {
3dd512fb
MR		 9937 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9938 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 9939 unsigned int stride = roundup_pow_of_two(width) * 4;
9940
9941 switch (stride) {
9942 default:
9943 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9944 width, stride);
9945 stride = 256;
9946 /* fallthrough */
9947 case 256:
9948 case 512:
9949 case 1024:
9950 case 2048:
9951 break;
4b0e333e
CW		 9952 }
9953
dc41c154
VS		 9954 cntl |= CURSOR_ENABLE |
9955 CURSOR_GAMMA_ENABLE |
9956 CURSOR_FORMAT_ARGB |
9957 CURSOR_STRIDE(stride);
9958
9959 size = (height << 12) | width;
4b0e333e 9960 }
560b85bb 9961
dc41c154
VS		 9962 if (intel_crtc->cursor_cntl != 0 &&
9963 (intel_crtc->cursor_base != base ||
9964 intel_crtc->cursor_size != size ||
9965 intel_crtc->cursor_cntl != cntl)) {
9966 /* On these chipsets we can only modify the base/size/stride
9967 * whilst the cursor is disabled.
9968 */
9969 I915_WRITE(_CURACNTR, 0);
4b0e333e 9970 POSTING_READ(_CURACNTR);
dc41c154 9971 intel_crtc->cursor_cntl = 0;
4b0e333e 9972 }
560b85bb 9973
99d1f387 9974 if (intel_crtc->cursor_base != base) {
9db4a9c7 9975 I915_WRITE(_CURABASE, base);
99d1f387
VS		 9976 intel_crtc->cursor_base = base;
9977 }
4726e0b0 9978
dc41c154
VS		 9979 if (intel_crtc->cursor_size != size) {
9980 I915_WRITE(CURSIZE, size);
9981 intel_crtc->cursor_size = size;
4b0e333e 9982 }
560b85bb 9983
4b0e333e 9984 if (intel_crtc->cursor_cntl != cntl) {
4b0e333e
CW		 9985 I915_WRITE(_CURACNTR, cntl);
9986 POSTING_READ(_CURACNTR);
4b0e333e 9987 intel_crtc->cursor_cntl = cntl;
560b85bb 9988 }
560b85bb
CW		 9989}
9990
560b85bb 9991static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 9992{
9993 struct drm_device *dev = crtc->dev;
9994 struct drm_i915_private *dev_priv = dev->dev_private;
9995 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9996 int pipe = intel_crtc->pipe;
4b0e333e
CW		 9997 uint32_t cntl;
9998
9999 cntl = 0;
10000 if (base) {
10001 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 10002 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 10003 case 64:
10004 cntl |= CURSOR_MODE_64_ARGB_AX;
10005 break;
10006 case 128:
10007 cntl |= CURSOR_MODE_128_ARGB_AX;
10008 break;
10009 case 256:
10010 cntl |= CURSOR_MODE_256_ARGB_AX;
10011 break;
10012 default:
3dd512fb 10013 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 10014 return;
65a21cd6 10015 }
4b0e333e 10016 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS		 10017
10018 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
10019 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 10020 }
65a21cd6 10021
8e7d688b 10022 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 10023 cntl |= CURSOR_ROTATE_180;
10024
4b0e333e
CW		 10025 if (intel_crtc->cursor_cntl != cntl) {
10026 I915_WRITE(CURCNTR(pipe), cntl);
10027 POSTING_READ(CURCNTR(pipe));
10028 intel_crtc->cursor_cntl = cntl;
65a21cd6 10029 }
4b0e333e 10030
65a21cd6 10031 /* and commit changes on next vblank */
5efb3e28
VS		 10032 I915_WRITE(CURBASE(pipe), base);
10033 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 10034
10035 intel_crtc->cursor_base = base;
65a21cd6
JB		 10036}
10037
cda4b7d3 10038/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 10039static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10040 bool on)
cda4b7d3
CW		 10041{
10042 struct drm_device *dev = crtc->dev;
10043 struct drm_i915_private *dev_priv = dev->dev_private;
10044 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10045 int pipe = intel_crtc->pipe;
3d7d6510
MR		 10046 int x = crtc->cursor_x;
10047 int y = crtc->cursor_y;
d6e4db15 10048 u32 base = 0, pos = 0;
cda4b7d3 10049
d6e4db15 10050 if (on)
cda4b7d3 10051 base = intel_crtc->cursor_addr;
cda4b7d3 10052
6e3c9717 10053 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 10054 base = 0;
10055
6e3c9717 10056 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 10057 base = 0;
10058
10059 if (x < 0) {
3dd512fb 10060 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
cda4b7d3
CW		 10061 base = 0;
10062
10063 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10064 x = -x;
10065 }
10066 pos |= x << CURSOR_X_SHIFT;
10067
10068 if (y < 0) {
3dd512fb 10069 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
cda4b7d3
CW		 10070 base = 0;
10071
10072 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10073 y = -y;
10074 }
10075 pos |= y << CURSOR_Y_SHIFT;
10076
4b0e333e 10077 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 10078 return;
10079
5efb3e28
VS		 10080 I915_WRITE(CURPOS(pipe), pos);
10081
4398ad45
VS		 10082 /* ILK+ do this automagically */
10083 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 10084 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
3dd512fb
MR		 10085 base += (intel_crtc->base.cursor->state->crtc_h *
10086 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
4398ad45
VS		 10087 }
10088
8ac54669 10089 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 10090 i845_update_cursor(crtc, base);
10091 else
10092 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 10093}
10094
dc41c154
VS		 10095static bool cursor_size_ok(struct drm_device *dev,
10096 uint32_t width, uint32_t height)
10097{
10098 if (width == 0 || height == 0)
10099 return false;
10100
10101 /*
10102 * 845g/865g are special in that they are only limited by
10103 * the width of their cursors, the height is arbitrary up to
10104 * the precision of the register. Everything else requires
10105 * square cursors, limited to a few power-of-two sizes.
10106 */
10107 if (IS_845G(dev) || IS_I865G(dev)) {
10108 if ((width & 63) != 0)
10109 return false;
10110
10111 if (width > (IS_845G(dev) ? 64 : 512))
10112 return false;
10113
10114 if (height > 1023)
10115 return false;
10116 } else {
10117 switch (width | height) {
10118 case 256:
10119 case 128:
10120 if (IS_GEN2(dev))
10121 return false;
10122 case 64:
10123 break;
10124 default:
10125 return false;
10126 }
10127 }
10128
10129 return true;
10130}
10131
79e53945 10132static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 10133 u16 *blue, uint32_t start, uint32_t size)
79e53945 10134{
7203425a 10135 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 10136 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 10137
7203425a 10138 for (i = start; i < end; i++) {
79e53945
JB		 10139 intel_crtc->lut_r[i] = red[i] >> 8;
10140 intel_crtc->lut_g[i] = green[i] >> 8;
10141 intel_crtc->lut_b[i] = blue[i] >> 8;
10142 }
10143
10144 intel_crtc_load_lut(crtc);
10145}
10146
79e53945
JB		 10147/* VESA 640x480x72Hz mode to set on the pipe */
10148static struct drm_display_mode load_detect_mode = {
10149 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10150 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10151};
10152
a8bb6818
DV		 10153struct drm_framebuffer *
10154__intel_framebuffer_create(struct drm_device *dev,
10155 struct drm_mode_fb_cmd2 *mode_cmd,
10156 struct drm_i915_gem_object *obj)
d2dff872
CW		 10157{
10158 struct intel_framebuffer *intel_fb;
10159 int ret;
10160
10161 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10162 if (!intel_fb) {
6ccb81f2 10163 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 10164 return ERR_PTR(-ENOMEM);
10165 }
10166
10167 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 10168 if (ret)
10169 goto err;
d2dff872
CW		 10170
10171 return &intel_fb->base;
dd4916c5 10172err:
6ccb81f2 10173 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 10174 kfree(intel_fb);
10175
10176 return ERR_PTR(ret);
d2dff872
CW		 10177}
10178
b5ea642a 10179static struct drm_framebuffer *
a8bb6818
DV		 10180intel_framebuffer_create(struct drm_device *dev,
10181 struct drm_mode_fb_cmd2 *mode_cmd,
10182 struct drm_i915_gem_object *obj)
10183{
10184 struct drm_framebuffer *fb;
10185 int ret;
10186
10187 ret = i915_mutex_lock_interruptible(dev);
10188 if (ret)
10189 return ERR_PTR(ret);
10190 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10191 mutex_unlock(&dev->struct_mutex);
10192
10193 return fb;
10194}
10195
d2dff872
CW		 10196static u32
10197intel_framebuffer_pitch_for_width(int width, int bpp)
10198{
10199 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10200 return ALIGN(pitch, 64);
10201}
10202
10203static u32
10204intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10205{
10206 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 10207 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 10208}
10209
10210static struct drm_framebuffer *
10211intel_framebuffer_create_for_mode(struct drm_device *dev,
10212 struct drm_display_mode *mode,
10213 int depth, int bpp)
10214{
10215 struct drm_i915_gem_object *obj;
0fed39bd 10216 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 10217
10218 obj = i915_gem_alloc_object(dev,
10219 intel_framebuffer_size_for_mode(mode, bpp));
10220 if (obj == NULL)
10221 return ERR_PTR(-ENOMEM);
10222
10223 mode_cmd.width = mode->hdisplay;
10224 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 10225 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10226 bpp);
5ca0c34a 10227 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 10228
10229 return intel_framebuffer_create(dev, &mode_cmd, obj);
10230}
10231
10232static struct drm_framebuffer *
10233mode_fits_in_fbdev(struct drm_device *dev,
10234 struct drm_display_mode *mode)
10235{
4520f53a 10236#ifdef CONFIG_DRM_I915_FBDEV
d2dff872
CW		 10237 struct drm_i915_private *dev_priv = dev->dev_private;
10238 struct drm_i915_gem_object *obj;
10239 struct drm_framebuffer *fb;
10240
4c0e5528 10241 if (!dev_priv->fbdev)
d2dff872
CW		 10242 return NULL;
10243
4c0e5528 10244 if (!dev_priv->fbdev->fb)
d2dff872
CW		 10245 return NULL;
10246
4c0e5528
DV		 10247 obj = dev_priv->fbdev->fb->obj;
10248 BUG_ON(!obj);
10249
8bcd4553 10250 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 10251 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10252 fb->bits_per_pixel))
d2dff872
CW		 10253 return NULL;
10254
01f2c773 10255 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 10256 return NULL;
10257
10258 return fb;
4520f53a
DV		 10259#else
10260 return NULL;
10261#endif
d2dff872
CW		 10262}
10263
d3a40d1b
ACO		 10264static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10265 struct drm_crtc *crtc,
10266 struct drm_display_mode *mode,
10267 struct drm_framebuffer *fb,
10268 int x, int y)
10269{
10270 struct drm_plane_state *plane_state;
10271 int hdisplay, vdisplay;
10272 int ret;
10273
10274 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10275 if (IS_ERR(plane_state))
10276 return PTR_ERR(plane_state);
10277
10278 if (mode)
10279 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10280 else
10281 hdisplay = vdisplay = 0;
10282
10283 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10284 if (ret)
10285 return ret;
10286 drm_atomic_set_fb_for_plane(plane_state, fb);
10287 plane_state->crtc_x = 0;
10288 plane_state->crtc_y = 0;
10289 plane_state->crtc_w = hdisplay;
10290 plane_state->crtc_h = vdisplay;
10291 plane_state->src_x = x << 16;
10292 plane_state->src_y = y << 16;
10293 plane_state->src_w = hdisplay << 16;
10294 plane_state->src_h = vdisplay << 16;
10295
10296 return 0;
10297}
10298
d2434ab7 10299bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 10300 struct drm_display_mode *mode,
51fd371b
RC		 10301 struct intel_load_detect_pipe *old,
10302 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 10303{
10304 struct intel_crtc *intel_crtc;
d2434ab7
DV		 10305 struct intel_encoder *intel_encoder =
10306 intel_attached_encoder(connector);
79e53945 10307 struct drm_crtc *possible_crtc;
4ef69c7a 10308 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 10309 struct drm_crtc *crtc = NULL;
10310 struct drm_device *dev = encoder->dev;
94352cf9 10311 struct drm_framebuffer *fb;
51fd371b 10312 struct drm_mode_config *config = &dev->mode_config;
83a57153 10313 struct drm_atomic_state *state = NULL;
944b0c76 10314 struct drm_connector_state *connector_state;
4be07317 10315 struct intel_crtc_state *crtc_state;
51fd371b 10316 int ret, i = -1;
79e53945 10317
d2dff872 10318 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10319 connector->base.id, connector->name,
8e329a03 10320 encoder->base.id, encoder->name);
d2dff872 10321
51fd371b
RC		 10322retry:
10323 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10324 if (ret)
10325 goto fail_unlock;
6e9f798d 10326
79e53945
JB		 10327 /*
10328 * Algorithm gets a little messy:
7a5e4805 10329 *
79e53945
JB		 10330 * - if the connector already has an assigned crtc, use it (but make
10331 * sure it's on first)
7a5e4805 10332 *
79e53945
JB		 10333 * - try to find the first unused crtc that can drive this connector,
10334 * and use that if we find one
79e53945
JB		 10335 */
10336
10337 /* See if we already have a CRTC for this connector */
10338 if (encoder->crtc) {
10339 crtc = encoder->crtc;
8261b191 10340
51fd371b 10341 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de
DV		 10342 if (ret)
10343 goto fail_unlock;
10344 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b
RC		 10345 if (ret)
10346 goto fail_unlock;
7b24056b 10347
24218aac 10348 old->dpms_mode = connector->dpms;
8261b191
CW		 10349 old->load_detect_temp = false;
10350
10351 /* Make sure the crtc and connector are running */
24218aac
DV		 10352 if (connector->dpms != DRM_MODE_DPMS_ON)
10353 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 10354
7173188d 10355 return true;
79e53945
JB		 10356 }
10357
10358 /* Find an unused one (if possible) */
70e1e0ec 10359 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 10360 i++;
10361 if (!(encoder->possible_crtcs & (1 << i)))
10362 continue;
83d65738 10363 if (possible_crtc->state->enable)
a459249c
VS		 10364 continue;
10365 /* This can occur when applying the pipe A quirk on resume. */
10366 if (to_intel_crtc(possible_crtc)->new_enabled)
10367 continue;
10368
10369 crtc = possible_crtc;
10370 break;
79e53945
JB		 10371 }
10372
10373 /*
10374 * If we didn't find an unused CRTC, don't use any.
10375 */
10376 if (!crtc) {
7173188d 10377 DRM_DEBUG_KMS("no pipe available for load-detect\n");
51fd371b 10378 goto fail_unlock;
79e53945
JB		 10379 }
10380
51fd371b
RC		 10381 ret = drm_modeset_lock(&crtc->mutex, ctx);
10382 if (ret)
4d02e2de
DV		 10383 goto fail_unlock;
10384 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10385 if (ret)
51fd371b 10386 goto fail_unlock;
fc303101
DV		 10387 intel_encoder->new_crtc = to_intel_crtc(crtc);
10388 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 10389
10390 intel_crtc = to_intel_crtc(crtc);
412b61d8 10391 intel_crtc->new_enabled = true;
24218aac 10392 old->dpms_mode = connector->dpms;
8261b191 10393 old->load_detect_temp = true;
d2dff872 10394 old->release_fb = NULL;
79e53945 10395
83a57153
ACO		 10396 state = drm_atomic_state_alloc(dev);
10397 if (!state)
10398 return false;
10399
10400 state->acquire_ctx = ctx;
10401
944b0c76
ACO		 10402 connector_state = drm_atomic_get_connector_state(state, connector);
10403 if (IS_ERR(connector_state)) {
10404 ret = PTR_ERR(connector_state);
10405 goto fail;
10406 }
10407
10408 connector_state->crtc = crtc;
10409 connector_state->best_encoder = &intel_encoder->base;
10410
4be07317
ACO		 10411 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10412 if (IS_ERR(crtc_state)) {
10413 ret = PTR_ERR(crtc_state);
10414 goto fail;
10415 }
10416
49d6fa21 10417 crtc_state->base.active = crtc_state->base.enable = true;
4be07317 10418
6492711d
CW		 10419 if (!mode)
10420 mode = &load_detect_mode;
79e53945 10421
d2dff872
CW		 10422 /* We need a framebuffer large enough to accommodate all accesses
10423 * that the plane may generate whilst we perform load detection.
10424 * We can not rely on the fbcon either being present (we get called
10425 * during its initialisation to detect all boot displays, or it may
10426 * not even exist) or that it is large enough to satisfy the
10427 * requested mode.
10428 */
94352cf9
DV		 10429 fb = mode_fits_in_fbdev(dev, mode);
10430 if (fb == NULL) {
d2dff872 10431 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 10432 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10433 old->release_fb = fb;
d2dff872
CW		 10434 } else
10435 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 10436 if (IS_ERR(fb)) {
d2dff872 10437 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 10438 goto fail;
79e53945 10439 }
79e53945 10440
d3a40d1b
ACO		 10441 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10442 if (ret)
10443 goto fail;
10444
8c7b5ccb
ACO		 10445 drm_mode_copy(&crtc_state->base.mode, mode);
10446
568c634a 10447 if (intel_set_mode(state)) {
6492711d 10448 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 10449 if (old->release_fb)
10450 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 10451 goto fail;
79e53945 10452 }
9128b040 10453 crtc->primary->crtc = crtc;
7173188d 10454
79e53945 10455 /* let the connector get through one full cycle before testing */
9d0498a2 10456 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 10457 return true;
412b61d8
VS		 10458
10459 fail:
83d65738 10460 intel_crtc->new_enabled = crtc->state->enable;
51fd371b 10461fail_unlock:
e5d958ef
ACO		 10462 drm_atomic_state_free(state);
10463 state = NULL;
83a57153 10464
51fd371b
RC		 10465 if (ret == -EDEADLK) {
10466 drm_modeset_backoff(ctx);
10467 goto retry;
10468 }
10469
412b61d8 10470 return false;
79e53945
JB		 10471}
10472
d2434ab7 10473void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 10474 struct intel_load_detect_pipe *old,
10475 struct drm_modeset_acquire_ctx *ctx)
79e53945 10476{
83a57153 10477 struct drm_device *dev = connector->dev;
d2434ab7
DV		 10478 struct intel_encoder *intel_encoder =
10479 intel_attached_encoder(connector);
4ef69c7a 10480 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 10481 struct drm_crtc *crtc = encoder->crtc;
412b61d8 10482 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 10483 struct drm_atomic_state *state;
944b0c76 10484 struct drm_connector_state *connector_state;
4be07317 10485 struct intel_crtc_state *crtc_state;
d3a40d1b 10486 int ret;
79e53945 10487
d2dff872 10488 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10489 connector->base.id, connector->name,
8e329a03 10490 encoder->base.id, encoder->name);
d2dff872 10491
8261b191 10492 if (old->load_detect_temp) {
83a57153 10493 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 10494 if (!state)
10495 goto fail;
83a57153
ACO		 10496
10497 state->acquire_ctx = ctx;
10498
944b0c76
ACO		 10499 connector_state = drm_atomic_get_connector_state(state, connector);
10500 if (IS_ERR(connector_state))
10501 goto fail;
10502
4be07317
ACO		 10503 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10504 if (IS_ERR(crtc_state))
10505 goto fail;
10506
fc303101
DV		 10507 to_intel_connector(connector)->new_encoder = NULL;
10508 intel_encoder->new_crtc = NULL;
412b61d8 10509 intel_crtc->new_enabled = false;
944b0c76
ACO		 10510
10511 connector_state->best_encoder = NULL;
10512 connector_state->crtc = NULL;
10513
49d6fa21 10514 crtc_state->base.enable = crtc_state->base.active = false;
4be07317 10515
d3a40d1b
ACO		 10516 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10517 0, 0);
10518 if (ret)
10519 goto fail;
10520
568c634a 10521 ret = intel_set_mode(state);
2bfb4627
ACO		 10522 if (ret)
10523 goto fail;
d2dff872 10524
36206361
DV		 10525 if (old->release_fb) {
10526 drm_framebuffer_unregister_private(old->release_fb);
10527 drm_framebuffer_unreference(old->release_fb);
10528 }
d2dff872 10529
0622a53c 10530 return;
79e53945
JB		 10531 }
10532
c751ce4f 10533 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 10534 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10535 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 10536
10537 return;
10538fail:
10539 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10540 drm_atomic_state_free(state);
79e53945
JB		 10541}
10542
da4a1efa 10543static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 10544 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 10545{
10546 struct drm_i915_private *dev_priv = dev->dev_private;
10547 u32 dpll = pipe_config->dpll_hw_state.dpll;
10548
10549 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 10550 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 10551 else if (HAS_PCH_SPLIT(dev))
10552 return 120000;
10553 else if (!IS_GEN2(dev))
10554 return 96000;
10555 else
10556 return 48000;
10557}
10558
79e53945 10559/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 10560static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 10561 struct intel_crtc_state *pipe_config)
79e53945 10562{
f1f644dc 10563 struct drm_device *dev = crtc->base.dev;
79e53945 10564 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 10565 int pipe = pipe_config->cpu_transcoder;
293623f7 10566 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 10567 u32 fp;
10568 intel_clock_t clock;
da4a1efa 10569 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 10570
10571 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 10572 fp = pipe_config->dpll_hw_state.fp0;
79e53945 10573 else
293623f7 10574 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 10575
10576 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 10577 if (IS_PINEVIEW(dev)) {
10578 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10579 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 10580 } else {
10581 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10582 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10583 }
10584
a6c45cf0 10585 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 10586 if (IS_PINEVIEW(dev))
10587 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10588 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 10589 else
10590 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 10591 DPLL_FPA01_P1_POST_DIV_SHIFT);
10592
10593 switch (dpll & DPLL_MODE_MASK) {
10594 case DPLLB_MODE_DAC_SERIAL:
10595 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10596 5 : 10;
10597 break;
10598 case DPLLB_MODE_LVDS:
10599 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10600 7 : 14;
10601 break;
10602 default:
28c97730 10603 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 10604 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 10605 return;
79e53945
JB		 10606 }
10607
ac58c3f0 10608 if (IS_PINEVIEW(dev))
da4a1efa 10609 pineview_clock(refclk, &clock);
ac58c3f0 10610 else
da4a1efa 10611 i9xx_clock(refclk, &clock);
79e53945 10612 } else {
0fb58223 10613 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 10614 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 10615
10616 if (is_lvds) {
10617 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10618 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 10619
10620 if (lvds & LVDS_CLKB_POWER_UP)
10621 clock.p2 = 7;
10622 else
10623 clock.p2 = 14;
79e53945
JB		 10624 } else {
10625 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10626 clock.p1 = 2;
10627 else {
10628 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10629 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10630 }
10631 if (dpll & PLL_P2_DIVIDE_BY_4)
10632 clock.p2 = 4;
10633 else
10634 clock.p2 = 2;
79e53945 10635 }
da4a1efa
VS		 10636
10637 i9xx_clock(refclk, &clock);
79e53945
JB		 10638 }
10639
18442d08
VS		 10640 /*
10641 * This value includes pixel_multiplier. We will use
241bfc38 10642 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 10643 * encoder's get_config() function.
10644 */
10645 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 10646}
10647
6878da05
VS		 10648int intel_dotclock_calculate(int link_freq,
10649 const struct intel_link_m_n *m_n)
f1f644dc 10650{
f1f644dc
JB		 10651 /*
10652 * The calculation for the data clock is:
1041a02f 10653 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 10654 * But we want to avoid losing precison if possible, so:
1041a02f 10655 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 10656 *
10657 * and the link clock is simpler:
1041a02f 10658 * link_clock = (m * link_clock) / n
f1f644dc
JB		 10659 */
10660
6878da05
VS		 10661 if (!m_n->link_n)
10662 return 0;
f1f644dc 10663
6878da05
VS		 10664 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10665}
f1f644dc 10666
18442d08 10667static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 10668 struct intel_crtc_state *pipe_config)
6878da05
VS		 10669{
10670 struct drm_device *dev = crtc->base.dev;
79e53945 10671
18442d08
VS		 10672 /* read out port_clock from the DPLL */
10673 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 10674
f1f644dc 10675 /*
18442d08 10676 * This value does not include pixel_multiplier.
241bfc38 10677 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 10678 * agree once we know their relationship in the encoder's
10679 * get_config() function.
79e53945 10680 */
2d112de7 10681 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 10682 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10683 &pipe_config->fdi_m_n);
79e53945
JB		 10684}
10685
10686/** Returns the currently programmed mode of the given pipe. */
10687struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10688 struct drm_crtc *crtc)
10689{
548f245b 10690 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 10691 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 10692 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 10693 struct drm_display_mode *mode;
5cec258b 10694 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 10695 int htot = I915_READ(HTOTAL(cpu_transcoder));
10696 int hsync = I915_READ(HSYNC(cpu_transcoder));
10697 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10698 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 10699 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 10700
10701 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10702 if (!mode)
10703 return NULL;
10704
f1f644dc
JB		 10705 /*
10706 * Construct a pipe_config sufficient for getting the clock info
10707 * back out of crtc_clock_get.
10708 *
10709 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10710 * to use a real value here instead.
10711 */
293623f7 10712 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 10713 pipe_config.pixel_multiplier = 1;
293623f7
VS		 10714 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10715 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10716 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 10717 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10718
773ae034 10719 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 10720 mode->hdisplay = (htot & 0xffff) + 1;
10721 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10722 mode->hsync_start = (hsync & 0xffff) + 1;
10723 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10724 mode->vdisplay = (vtot & 0xffff) + 1;
10725 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10726 mode->vsync_start = (vsync & 0xffff) + 1;
10727 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10728
10729 drm_mode_set_name(mode);
79e53945
JB		 10730
10731 return mode;
10732}
10733
652c393a
JB		 10734static void intel_decrease_pllclock(struct drm_crtc *crtc)
10735{
10736 struct drm_device *dev = crtc->dev;
fbee40df 10737 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10738 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 10739
baff296c 10740 if (!HAS_GMCH_DISPLAY(dev))
652c393a
JB		 10741 return;
10742
10743 if (!dev_priv->lvds_downclock_avail)
10744 return;
10745
10746 /*
10747 * Since this is called by a timer, we should never get here in
10748 * the manual case.
10749 */
10750 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 10751 int pipe = intel_crtc->pipe;
10752 int dpll_reg = DPLL(pipe);
10753 int dpll;
f6e5b160 10754
44d98a61 10755 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 10756
8ac5a6d5 10757 assert_panel_unlocked(dev_priv, pipe);
652c393a 10758
dc257cf1 10759 dpll = I915_READ(dpll_reg);
652c393a
JB		 10760 dpll |= DISPLAY_RATE_SELECT_FPA1;
10761 I915_WRITE(dpll_reg, dpll);
9d0498a2 10762 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 10763 dpll = I915_READ(dpll_reg);
10764 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 10765 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 10766 }
10767
10768}
10769
f047e395
CW		 10770void intel_mark_busy(struct drm_device *dev)
10771{
c67a470b
PZ		 10772 struct drm_i915_private *dev_priv = dev->dev_private;
10773
f62a0076
CW		 10774 if (dev_priv->mm.busy)
10775 return;
10776
43694d69 10777 intel_runtime_pm_get(dev_priv);
c67a470b 10778 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 10779 if (INTEL_INFO(dev)->gen >= 6)
10780 gen6_rps_busy(dev_priv);
f62a0076 10781 dev_priv->mm.busy = true;
f047e395
CW		 10782}
10783
10784void intel_mark_idle(struct drm_device *dev)
652c393a 10785{
c67a470b 10786 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10787 struct drm_crtc *crtc;
652c393a 10788
f62a0076
CW		 10789 if (!dev_priv->mm.busy)
10790 return;
10791
10792 dev_priv->mm.busy = false;
10793
70e1e0ec 10794 for_each_crtc(dev, crtc) {
f4510a27 10795 if (!crtc->primary->fb)
652c393a
JB		 10796 continue;
10797
725a5b54 10798 intel_decrease_pllclock(crtc);
652c393a 10799 }
b29c19b6 10800
3d13ef2e 10801 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 10802 gen6_rps_idle(dev->dev_private);
bb4cdd53 10803
43694d69 10804 intel_runtime_pm_put(dev_priv);
652c393a
JB		 10805}
10806
79e53945
JB		 10807static void intel_crtc_destroy(struct drm_crtc *crtc)
10808{
10809 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 10810 struct drm_device *dev = crtc->dev;
10811 struct intel_unpin_work *work;
67e77c5a 10812
5e2d7afc 10813 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 10814 work = intel_crtc->unpin_work;
10815 intel_crtc->unpin_work = NULL;
5e2d7afc 10816 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 10817
10818 if (work) {
10819 cancel_work_sync(&work->work);
10820 kfree(work);
10821 }
79e53945
JB		 10822
10823 drm_crtc_cleanup(crtc);
67e77c5a 10824
79e53945
JB		 10825 kfree(intel_crtc);
10826}
10827
6b95a207
KH		 10828static void intel_unpin_work_fn(struct work_struct *__work)
10829{
10830 struct intel_unpin_work *work =
10831 container_of(__work, struct intel_unpin_work, work);
b4a98e57 10832 struct drm_device *dev = work->crtc->dev;
f99d7069 10833 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
6b95a207 10834
b4a98e57 10835 mutex_lock(&dev->struct_mutex);
82bc3b2d 10836 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
05394f39 10837 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 10838
7ff0ebcc 10839 intel_fbc_update(dev);
f06cc1b9
JH		 10840
10841 if (work->flip_queued_req)
146d84f0 10842 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 10843 mutex_unlock(&dev->struct_mutex);
10844
f99d7069 10845 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
89ed88ba 10846 drm_framebuffer_unreference(work->old_fb);
f99d7069 10847
b4a98e57
CW		 10848 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10849 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10850
6b95a207
KH		 10851 kfree(work);
10852}
10853
1afe3e9d 10854static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 10855 struct drm_crtc *crtc)
6b95a207 10856{
6b95a207
KH		 10857 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10858 struct intel_unpin_work *work;
6b95a207
KH		 10859 unsigned long flags;
10860
10861 /* Ignore early vblank irqs */
10862 if (intel_crtc == NULL)
10863 return;
10864
f326038a
DV		 10865 /*
10866 * This is called both by irq handlers and the reset code (to complete
10867 * lost pageflips) so needs the full irqsave spinlocks.
10868 */
6b95a207
KH		 10869 spin_lock_irqsave(&dev->event_lock, flags);
10870 work = intel_crtc->unpin_work;
e7d841ca
CW		 10871
10872 /* Ensure we don't miss a work->pending update ... */
10873 smp_rmb();
10874
10875 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 10876 spin_unlock_irqrestore(&dev->event_lock, flags);
10877 return;
10878 }
10879
d6bbafa1 10880 page_flip_completed(intel_crtc);
0af7e4df 10881
6b95a207 10882 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 10883}
10884
1afe3e9d
JB		 10885void intel_finish_page_flip(struct drm_device *dev, int pipe)
10886{
fbee40df 10887 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10888 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10889
49b14a5c 10890 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10891}
10892
10893void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10894{
fbee40df 10895 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10896 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10897
49b14a5c 10898 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10899}
10900
75f7f3ec
VS		 10901/* Is 'a' after or equal to 'b'? */
10902static bool g4x_flip_count_after_eq(u32 a, u32 b)
10903{
10904 return !((a - b) & 0x80000000);
10905}
10906
10907static bool page_flip_finished(struct intel_crtc *crtc)
10908{
10909 struct drm_device *dev = crtc->base.dev;
10910 struct drm_i915_private *dev_priv = dev->dev_private;
10911
bdfa7542
VS		 10912 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10913 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10914 return true;
10915
75f7f3ec
VS		 10916 /*
10917 * The relevant registers doen't exist on pre-ctg.
10918 * As the flip done interrupt doesn't trigger for mmio
10919 * flips on gmch platforms, a flip count check isn't
10920 * really needed there. But since ctg has the registers,
10921 * include it in the check anyway.
10922 */
10923 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10924 return true;
10925
10926 /*
10927 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10928 * used the same base address. In that case the mmio flip might
10929 * have completed, but the CS hasn't even executed the flip yet.
10930 *
10931 * A flip count check isn't enough as the CS might have updated
10932 * the base address just after start of vblank, but before we
10933 * managed to process the interrupt. This means we'd complete the
10934 * CS flip too soon.
10935 *
10936 * Combining both checks should get us a good enough result. It may
10937 * still happen that the CS flip has been executed, but has not
10938 * yet actually completed. But in case the base address is the same
10939 * anyway, we don't really care.
10940 */
10941 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10942 crtc->unpin_work->gtt_offset &&
10943 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10944 crtc->unpin_work->flip_count);
10945}
10946
6b95a207
KH		 10947void intel_prepare_page_flip(struct drm_device *dev, int plane)
10948{
fbee40df 10949 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 10950 struct intel_crtc *intel_crtc =
10951 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10952 unsigned long flags;
10953
f326038a
DV		 10954
10955 /*
10956 * This is called both by irq handlers and the reset code (to complete
10957 * lost pageflips) so needs the full irqsave spinlocks.
10958 *
10959 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 10960 * generate a page-flip completion irq, i.e. every modeset
10961 * is also accompanied by a spurious intel_prepare_page_flip().
10962 */
6b95a207 10963 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 10964 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 10965 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 10966 spin_unlock_irqrestore(&dev->event_lock, flags);
10967}
10968
eba905b2 10969static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW		 10970{
10971 /* Ensure that the work item is consistent when activating it ... */
10972 smp_wmb();
10973 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10974 /* and that it is marked active as soon as the irq could fire. */
10975 smp_wmb();
10976}
10977
8c9f3aaf
JB		 10978static int intel_gen2_queue_flip(struct drm_device *dev,
10979 struct drm_crtc *crtc,
10980 struct drm_framebuffer *fb,
ed8d1975 10981 struct drm_i915_gem_object *obj,
a4872ba6 10982 struct intel_engine_cs *ring,
ed8d1975 10983 uint32_t flags)
8c9f3aaf 10984{
8c9f3aaf 10985 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10986 u32 flip_mask;
10987 int ret;
10988
6d90c952 10989 ret = intel_ring_begin(ring, 6);
8c9f3aaf 10990 if (ret)
4fa62c89 10991 return ret;
8c9f3aaf
JB		 10992
10993 /* Can't queue multiple flips, so wait for the previous
10994 * one to finish before executing the next.
10995 */
10996 if (intel_crtc->plane)
10997 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10998 else
10999 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 11000 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11001 intel_ring_emit(ring, MI_NOOP);
11002 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11003 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11004 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 11005 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 11006 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 11007
11008 intel_mark_page_flip_active(intel_crtc);
09246732 11009 __intel_ring_advance(ring);
83d4092b 11010 return 0;
8c9f3aaf
JB		 11011}
11012
11013static int intel_gen3_queue_flip(struct drm_device *dev,
11014 struct drm_crtc *crtc,
11015 struct drm_framebuffer *fb,
ed8d1975 11016 struct drm_i915_gem_object *obj,
a4872ba6 11017 struct intel_engine_cs *ring,
ed8d1975 11018 uint32_t flags)
8c9f3aaf 11019{
8c9f3aaf 11020 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 11021 u32 flip_mask;
11022 int ret;
11023
6d90c952 11024 ret = intel_ring_begin(ring, 6);
8c9f3aaf 11025 if (ret)
4fa62c89 11026 return ret;
8c9f3aaf
JB		 11027
11028 if (intel_crtc->plane)
11029 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11030 else
11031 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 11032 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11033 intel_ring_emit(ring, MI_NOOP);
11034 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11035 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11036 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 11037 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 11038 intel_ring_emit(ring, MI_NOOP);
11039
e7d841ca 11040 intel_mark_page_flip_active(intel_crtc);
09246732 11041 __intel_ring_advance(ring);
83d4092b 11042 return 0;
8c9f3aaf
JB		 11043}
11044
11045static int intel_gen4_queue_flip(struct drm_device *dev,
11046 struct drm_crtc *crtc,
11047 struct drm_framebuffer *fb,
ed8d1975 11048 struct drm_i915_gem_object *obj,
a4872ba6 11049 struct intel_engine_cs *ring,
ed8d1975 11050 uint32_t flags)
8c9f3aaf
JB		 11051{
11052 struct drm_i915_private *dev_priv = dev->dev_private;
11053 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11054 uint32_t pf, pipesrc;
11055 int ret;
11056
6d90c952 11057 ret = intel_ring_begin(ring, 4);
8c9f3aaf 11058 if (ret)
4fa62c89 11059 return ret;
8c9f3aaf
JB		 11060
11061 /* i965+ uses the linear or tiled offsets from the
11062 * Display Registers (which do not change across a page-flip)
11063 * so we need only reprogram the base address.
11064 */
6d90c952
DV		 11065 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11066 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11067 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 11068 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 11069 obj->tiling_mode);
8c9f3aaf
JB		 11070
11071 /* XXX Enabling the panel-fitter across page-flip is so far
11072 * untested on non-native modes, so ignore it for now.
11073 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11074 */
11075 pf = 0;
11076 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 11077 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 11078
11079 intel_mark_page_flip_active(intel_crtc);
09246732 11080 __intel_ring_advance(ring);
83d4092b 11081 return 0;
8c9f3aaf
JB		 11082}
11083
11084static int intel_gen6_queue_flip(struct drm_device *dev,
11085 struct drm_crtc *crtc,
11086 struct drm_framebuffer *fb,
ed8d1975 11087 struct drm_i915_gem_object *obj,
a4872ba6 11088 struct intel_engine_cs *ring,
ed8d1975 11089 uint32_t flags)
8c9f3aaf
JB		 11090{
11091 struct drm_i915_private *dev_priv = dev->dev_private;
11092 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11093 uint32_t pf, pipesrc;
11094 int ret;
11095
6d90c952 11096 ret = intel_ring_begin(ring, 4);
8c9f3aaf 11097 if (ret)
4fa62c89 11098 return ret;
8c9f3aaf 11099
6d90c952
DV		 11100 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11101 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11102 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 11103 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 11104
dc257cf1
DV		 11105 /* Contrary to the suggestions in the documentation,
11106 * "Enable Panel Fitter" does not seem to be required when page
11107 * flipping with a non-native mode, and worse causes a normal
11108 * modeset to fail.
11109 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11110 */
11111 pf = 0;
8c9f3aaf 11112 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 11113 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 11114
11115 intel_mark_page_flip_active(intel_crtc);
09246732 11116 __intel_ring_advance(ring);
83d4092b 11117 return 0;
8c9f3aaf
JB		 11118}
11119
7c9017e5
JB		 11120static int intel_gen7_queue_flip(struct drm_device *dev,
11121 struct drm_crtc *crtc,
11122 struct drm_framebuffer *fb,
ed8d1975 11123 struct drm_i915_gem_object *obj,
a4872ba6 11124 struct intel_engine_cs *ring,
ed8d1975 11125 uint32_t flags)
7c9017e5 11126{
7c9017e5 11127 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 11128 uint32_t plane_bit = 0;
ffe74d75
CW		 11129 int len, ret;
11130
eba905b2 11131 switch (intel_crtc->plane) {
cb05d8de
DV		 11132 case PLANE_A:
11133 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11134 break;
11135 case PLANE_B:
11136 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11137 break;
11138 case PLANE_C:
11139 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11140 break;
11141 default:
11142 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 11143 return -ENODEV;
cb05d8de
DV		 11144 }
11145
ffe74d75 11146 len = 4;
f476828a 11147 if (ring->id == RCS) {
ffe74d75 11148 len += 6;
f476828a
DL		 11149 /*
11150 * On Gen 8, SRM is now taking an extra dword to accommodate
11151 * 48bits addresses, and we need a NOOP for the batch size to
11152 * stay even.
11153 */
11154 if (IS_GEN8(dev))
11155 len += 2;
11156 }
ffe74d75 11157
f66fab8e
VS		 11158 /*
11159 * BSpec MI_DISPLAY_FLIP for IVB:
11160 * "The full packet must be contained within the same cache line."
11161 *
11162 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11163 * cacheline, if we ever start emitting more commands before
11164 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11165 * then do the cacheline alignment, and finally emit the
11166 * MI_DISPLAY_FLIP.
11167 */
11168 ret = intel_ring_cacheline_align(ring);
11169 if (ret)
4fa62c89 11170 return ret;
f66fab8e 11171
ffe74d75 11172 ret = intel_ring_begin(ring, len);
7c9017e5 11173 if (ret)
4fa62c89 11174 return ret;
7c9017e5 11175
ffe74d75
CW		 11176 /* Unmask the flip-done completion message. Note that the bspec says that
11177 * we should do this for both the BCS and RCS, and that we must not unmask
11178 * more than one flip event at any time (or ensure that one flip message
11179 * can be sent by waiting for flip-done prior to queueing new flips).
11180 * Experimentation says that BCS works despite DERRMR masking all
11181 * flip-done completion events and that unmasking all planes at once
11182 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11183 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11184 */
11185 if (ring->id == RCS) {
11186 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11187 intel_ring_emit(ring, DERRMR);
11188 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11189 DERRMR_PIPEB_PRI_FLIP_DONE |
11190 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a
DL		 11191 if (IS_GEN8(dev))
11192 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11193 MI_SRM_LRM_GLOBAL_GTT);
11194 else
11195 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11196 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 11197 intel_ring_emit(ring, DERRMR);
11198 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 11199 if (IS_GEN8(dev)) {
11200 intel_ring_emit(ring, 0);
11201 intel_ring_emit(ring, MI_NOOP);
11202 }
ffe74d75
CW		 11203 }
11204
cb05d8de 11205 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 11206 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 11207 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 11208 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 11209
11210 intel_mark_page_flip_active(intel_crtc);
09246732 11211 __intel_ring_advance(ring);
83d4092b 11212 return 0;
7c9017e5
JB		 11213}
11214
84c33a64
SG		 11215static bool use_mmio_flip(struct intel_engine_cs *ring,
11216 struct drm_i915_gem_object *obj)
11217{
11218 /*
11219 * This is not being used for older platforms, because
11220 * non-availability of flip done interrupt forces us to use
11221 * CS flips. Older platforms derive flip done using some clever
11222 * tricks involving the flip_pending status bits and vblank irqs.
11223 * So using MMIO flips there would disrupt this mechanism.
11224 */
11225
8e09bf83
CW		 11226 if (ring == NULL)
11227 return true;
11228
84c33a64
SG		 11229 if (INTEL_INFO(ring->dev)->gen < 5)
11230 return false;
11231
11232 if (i915.use_mmio_flip < 0)
11233 return false;
11234 else if (i915.use_mmio_flip > 0)
11235 return true;
14bf993e
OM		 11236 else if (i915.enable_execlists)
11237 return true;
84c33a64 11238 else
b4716185 11239 return ring != i915_gem_request_get_ring(obj->last_write_req);
84c33a64
SG		 11240}
11241
ff944564
DL		 11242static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11243{
11244 struct drm_device *dev = intel_crtc->base.dev;
11245 struct drm_i915_private *dev_priv = dev->dev_private;
11246 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
ff944564
DL		 11247 const enum pipe pipe = intel_crtc->pipe;
11248 u32 ctl, stride;
11249
11250 ctl = I915_READ(PLANE_CTL(pipe, 0));
11251 ctl &= ~PLANE_CTL_TILED_MASK;
2ebef630
TU		 11252 switch (fb->modifier[0]) {
11253 case DRM_FORMAT_MOD_NONE:
11254 break;
11255 case I915_FORMAT_MOD_X_TILED:
ff944564 11256 ctl |= PLANE_CTL_TILED_X;
2ebef630
TU		 11257 break;
11258 case I915_FORMAT_MOD_Y_TILED:
11259 ctl |= PLANE_CTL_TILED_Y;
11260 break;
11261 case I915_FORMAT_MOD_Yf_TILED:
11262 ctl |= PLANE_CTL_TILED_YF;
11263 break;
11264 default:
11265 MISSING_CASE(fb->modifier[0]);
11266 }
ff944564
DL		 11267
11268 /*
11269 * The stride is either expressed as a multiple of 64 bytes chunks for
11270 * linear buffers or in number of tiles for tiled buffers.
11271 */
2ebef630
TU		 11272 stride = fb->pitches[0] /
11273 intel_fb_stride_alignment(dev, fb->modifier[0],
11274 fb->pixel_format);
ff944564
DL		 11275
11276 /*
11277 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11278 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11279 */
11280 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11281 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11282
11283 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11284 POSTING_READ(PLANE_SURF(pipe, 0));
11285}
11286
11287static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG		 11288{
11289 struct drm_device *dev = intel_crtc->base.dev;
11290 struct drm_i915_private *dev_priv = dev->dev_private;
11291 struct intel_framebuffer *intel_fb =
11292 to_intel_framebuffer(intel_crtc->base.primary->fb);
11293 struct drm_i915_gem_object *obj = intel_fb->obj;
11294 u32 dspcntr;
11295 u32 reg;
11296
84c33a64
SG		 11297 reg = DSPCNTR(intel_crtc->plane);
11298 dspcntr = I915_READ(reg);
11299
c5d97472
DL		 11300 if (obj->tiling_mode != I915_TILING_NONE)
11301 dspcntr |= DISPPLANE_TILED;
11302 else
11303 dspcntr &= ~DISPPLANE_TILED;
11304
84c33a64
SG		 11305 I915_WRITE(reg, dspcntr);
11306
11307 I915_WRITE(DSPSURF(intel_crtc->plane),
11308 intel_crtc->unpin_work->gtt_offset);
11309 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 11310
ff944564
DL		 11311}
11312
11313/*
11314 * XXX: This is the temporary way to update the plane registers until we get
11315 * around to using the usual plane update functions for MMIO flips
11316 */
11317static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11318{
11319 struct drm_device *dev = intel_crtc->base.dev;
11320 bool atomic_update;
11321 u32 start_vbl_count;
11322
11323 intel_mark_page_flip_active(intel_crtc);
11324
11325 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
11326
11327 if (INTEL_INFO(dev)->gen >= 9)
11328 skl_do_mmio_flip(intel_crtc);
11329 else
11330 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11331 ilk_do_mmio_flip(intel_crtc);
11332
9362c7c5
ACO		 11333 if (atomic_update)
11334 intel_pipe_update_end(intel_crtc, start_vbl_count);
84c33a64
SG		 11335}
11336
9362c7c5 11337static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 11338{
b2cfe0ab
CW		 11339 struct intel_mmio_flip *mmio_flip =
11340 container_of(work, struct intel_mmio_flip, work);
84c33a64 11341
eed29a5b
DV		 11342 if (mmio_flip->req)
11343 WARN_ON(__i915_wait_request(mmio_flip->req,
b2cfe0ab 11344 mmio_flip->crtc->reset_counter,
bcafc4e3
CW		 11345 false, NULL,
11346 &mmio_flip->i915->rps.mmioflips));
84c33a64 11347
b2cfe0ab
CW		 11348 intel_do_mmio_flip(mmio_flip->crtc);
11349
eed29a5b 11350 i915_gem_request_unreference__unlocked(mmio_flip->req);
b2cfe0ab 11351 kfree(mmio_flip);
84c33a64
SG		 11352}
11353
11354static int intel_queue_mmio_flip(struct drm_device *dev,
11355 struct drm_crtc *crtc,
11356 struct drm_framebuffer *fb,
11357 struct drm_i915_gem_object *obj,
11358 struct intel_engine_cs *ring,
11359 uint32_t flags)
11360{
b2cfe0ab
CW		 11361 struct intel_mmio_flip *mmio_flip;
11362
11363 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11364 if (mmio_flip == NULL)
11365 return -ENOMEM;
84c33a64 11366
bcafc4e3 11367 mmio_flip->i915 = to_i915(dev);
eed29a5b 11368 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
b2cfe0ab 11369 mmio_flip->crtc = to_intel_crtc(crtc);
536f5b5e 11370
b2cfe0ab
CW		 11371 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11372 schedule_work(&mmio_flip->work);
84c33a64 11373
84c33a64
SG		 11374 return 0;
11375}
11376
8c9f3aaf
JB		 11377static int intel_default_queue_flip(struct drm_device *dev,
11378 struct drm_crtc *crtc,
11379 struct drm_framebuffer *fb,
ed8d1975 11380 struct drm_i915_gem_object *obj,
a4872ba6 11381 struct intel_engine_cs *ring,
ed8d1975 11382 uint32_t flags)
8c9f3aaf
JB		 11383{
11384 return -ENODEV;
11385}
11386
d6bbafa1
CW		 11387static bool __intel_pageflip_stall_check(struct drm_device *dev,
11388 struct drm_crtc *crtc)
11389{
11390 struct drm_i915_private *dev_priv = dev->dev_private;
11391 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11392 struct intel_unpin_work *work = intel_crtc->unpin_work;
11393 u32 addr;
11394
11395 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11396 return true;
11397
11398 if (!work->enable_stall_check)
11399 return false;
11400
11401 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 11402 if (work->flip_queued_req &&
11403 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 11404 return false;
11405
1e3feefd 11406 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 11407 }
11408
1e3feefd 11409 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 11410 return false;
11411
11412 /* Potential stall - if we see that the flip has happened,
11413 * assume a missed interrupt. */
11414 if (INTEL_INFO(dev)->gen >= 4)
11415 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11416 else
11417 addr = I915_READ(DSPADDR(intel_crtc->plane));
11418
11419 /* There is a potential issue here with a false positive after a flip
11420 * to the same address. We could address this by checking for a
11421 * non-incrementing frame counter.
11422 */
11423 return addr == work->gtt_offset;
11424}
11425
11426void intel_check_page_flip(struct drm_device *dev, int pipe)
11427{
11428 struct drm_i915_private *dev_priv = dev->dev_private;
11429 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11430 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 11431 struct intel_unpin_work *work;
f326038a 11432
6c51d46f 11433 WARN_ON(!in_interrupt());
d6bbafa1
CW		 11434
11435 if (crtc == NULL)
11436 return;
11437
f326038a 11438 spin_lock(&dev->event_lock);
6ad790c0
CW		 11439 work = intel_crtc->unpin_work;
11440 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 11441 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 11442 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 11443 page_flip_completed(intel_crtc);
6ad790c0 11444 work = NULL;
d6bbafa1 11445 }
6ad790c0
CW		 11446 if (work != NULL &&
11447 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11448 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 11449 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 11450}
11451
6b95a207
KH		 11452static int intel_crtc_page_flip(struct drm_crtc *crtc,
11453 struct drm_framebuffer *fb,
ed8d1975
KP		 11454 struct drm_pending_vblank_event *event,
11455 uint32_t page_flip_flags)
6b95a207
KH		 11456{
11457 struct drm_device *dev = crtc->dev;
11458 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 11459 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 11460 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 11461 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 11462 struct drm_plane *primary = crtc->primary;
a071fa00 11463 enum pipe pipe = intel_crtc->pipe;
6b95a207 11464 struct intel_unpin_work *work;
a4872ba6 11465 struct intel_engine_cs *ring;
cf5d8a46 11466 bool mmio_flip;
52e68630 11467 int ret;
6b95a207 11468
2ff8fde1
MR		 11469 /*
11470 * drm_mode_page_flip_ioctl() should already catch this, but double
11471 * check to be safe. In the future we may enable pageflipping from
11472 * a disabled primary plane.
11473 */
11474 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11475 return -EBUSY;
11476
e6a595d2 11477 /* Can't change pixel format via MI display flips. */
f4510a27 11478 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 11479 return -EINVAL;
11480
11481 /*
11482 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11483 * Note that pitch changes could also affect these register.
11484 */
11485 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 11486 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11487 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 11488 return -EINVAL;
11489
f900db47
CW		 11490 if (i915_terminally_wedged(&dev_priv->gpu_error))
11491 goto out_hang;
11492
b14c5679 11493 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 11494 if (work == NULL)
11495 return -ENOMEM;
11496
6b95a207 11497 work->event = event;
b4a98e57 11498 work->crtc = crtc;
ab8d6675 11499 work->old_fb = old_fb;
6b95a207
KH		 11500 INIT_WORK(&work->work, intel_unpin_work_fn);
11501
87b6b101 11502 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 11503 if (ret)
11504 goto free_work;
11505
6b95a207 11506 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 11507 spin_lock_irq(&dev->event_lock);
6b95a207 11508 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 11509 /* Before declaring the flip queue wedged, check if
11510 * the hardware completed the operation behind our backs.
11511 */
11512 if (__intel_pageflip_stall_check(dev, crtc)) {
11513 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11514 page_flip_completed(intel_crtc);
11515 } else {
11516 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 11517 spin_unlock_irq(&dev->event_lock);
468f0b44 11518
d6bbafa1
CW		 11519 drm_crtc_vblank_put(crtc);
11520 kfree(work);
11521 return -EBUSY;
11522 }
6b95a207
KH		 11523 }
11524 intel_crtc->unpin_work = work;
5e2d7afc 11525 spin_unlock_irq(&dev->event_lock);
6b95a207 11526
b4a98e57
CW		 11527 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11528 flush_workqueue(dev_priv->wq);
11529
75dfca80 11530 /* Reference the objects for the scheduled work. */
ab8d6675 11531 drm_framebuffer_reference(work->old_fb);
05394f39 11532 drm_gem_object_reference(&obj->base);
6b95a207 11533
f4510a27 11534 crtc->primary->fb = fb;
afd65eb4 11535 update_state_fb(crtc->primary);
1ed1f968 11536
e1f99ce6 11537 work->pending_flip_obj = obj;
e1f99ce6 11538
89ed88ba
CW		 11539 ret = i915_mutex_lock_interruptible(dev);
11540 if (ret)
11541 goto cleanup;
11542
b4a98e57 11543 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 11544 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 11545
75f7f3ec 11546 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 11547 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 11548
4fa62c89
VS		 11549 if (IS_VALLEYVIEW(dev)) {
11550 ring = &dev_priv->ring[BCS];
ab8d6675 11551 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 11552 /* vlv: DISPLAY_FLIP fails to change tiling */
11553 ring = NULL;
48bf5b2d 11554 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 11555 ring = &dev_priv->ring[BCS];
4fa62c89 11556 } else if (INTEL_INFO(dev)->gen >= 7) {
b4716185 11557 ring = i915_gem_request_get_ring(obj->last_write_req);
4fa62c89
VS		 11558 if (ring == NULL || ring->id != RCS)
11559 ring = &dev_priv->ring[BCS];
11560 } else {
11561 ring = &dev_priv->ring[RCS];
11562 }
11563
cf5d8a46
CW		 11564 mmio_flip = use_mmio_flip(ring, obj);
11565
11566 /* When using CS flips, we want to emit semaphores between rings.
11567 * However, when using mmio flips we will create a task to do the
11568 * synchronisation, so all we want here is to pin the framebuffer
11569 * into the display plane and skip any waits.
11570 */
82bc3b2d 11571 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
cf5d8a46 11572 crtc->primary->state,
b4716185 11573 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring);
8c9f3aaf
JB		 11574 if (ret)
11575 goto cleanup_pending;
6b95a207 11576
121920fa
TU		 11577 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11578 + intel_crtc->dspaddr_offset;
4fa62c89 11579
cf5d8a46 11580 if (mmio_flip) {
84c33a64
SG		 11581 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11582 page_flip_flags);
d6bbafa1
CW		 11583 if (ret)
11584 goto cleanup_unpin;
11585
f06cc1b9
JH		 11586 i915_gem_request_assign(&work->flip_queued_req,
11587 obj->last_write_req);
d6bbafa1 11588 } else {
d94b5030
CW		 11589 if (obj->last_write_req) {
11590 ret = i915_gem_check_olr(obj->last_write_req);
11591 if (ret)
11592 goto cleanup_unpin;
11593 }
11594
84c33a64 11595 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
d6bbafa1
CW		 11596 page_flip_flags);
11597 if (ret)
11598 goto cleanup_unpin;
11599
f06cc1b9
JH		 11600 i915_gem_request_assign(&work->flip_queued_req,
11601 intel_ring_get_request(ring));
d6bbafa1
CW		 11602 }
11603
1e3feefd 11604 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 11605 work->enable_stall_check = true;
4fa62c89 11606
ab8d6675 11607 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a071fa00
DV		 11608 INTEL_FRONTBUFFER_PRIMARY(pipe));
11609
7ff0ebcc 11610 intel_fbc_disable(dev);
f99d7069 11611 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
6b95a207
KH		 11612 mutex_unlock(&dev->struct_mutex);
11613
e5510fac
JB		 11614 trace_i915_flip_request(intel_crtc->plane, obj);
11615
6b95a207 11616 return 0;
96b099fd 11617
4fa62c89 11618cleanup_unpin:
82bc3b2d 11619 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 11620cleanup_pending:
b4a98e57 11621 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 11622 mutex_unlock(&dev->struct_mutex);
11623cleanup:
f4510a27 11624 crtc->primary->fb = old_fb;
afd65eb4 11625 update_state_fb(crtc->primary);
89ed88ba
CW		 11626
11627 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 11628 drm_framebuffer_unreference(work->old_fb);
96b099fd 11629
5e2d7afc 11630 spin_lock_irq(&dev->event_lock);
96b099fd 11631 intel_crtc->unpin_work = NULL;
5e2d7afc 11632 spin_unlock_irq(&dev->event_lock);
96b099fd 11633
87b6b101 11634 drm_crtc_vblank_put(crtc);
7317c75e 11635free_work:
96b099fd
CW		 11636 kfree(work);
11637
f900db47 11638 if (ret == -EIO) {
02e0efb5
ML		 11639 struct drm_atomic_state *state;
11640 struct drm_plane_state *plane_state;
11641
f900db47 11642out_hang:
02e0efb5
ML		 11643 state = drm_atomic_state_alloc(dev);
11644 if (!state)
11645 return -ENOMEM;
11646 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11647
11648retry:
11649 plane_state = drm_atomic_get_plane_state(state, primary);
11650 ret = PTR_ERR_OR_ZERO(plane_state);
11651 if (!ret) {
11652 drm_atomic_set_fb_for_plane(plane_state, fb);
11653
11654 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11655 if (!ret)
11656 ret = drm_atomic_commit(state);
11657 }
11658
11659 if (ret == -EDEADLK) {
11660 drm_modeset_backoff(state->acquire_ctx);
11661 drm_atomic_state_clear(state);
11662 goto retry;
11663 }
11664
11665 if (ret)
11666 drm_atomic_state_free(state);
11667
f0d3dad3 11668 if (ret == 0 && event) {
5e2d7afc 11669 spin_lock_irq(&dev->event_lock);
a071fa00 11670 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 11671 spin_unlock_irq(&dev->event_lock);
f0d3dad3 11672 }
f900db47 11673 }
96b099fd 11674 return ret;
6b95a207
KH		 11675}
11676
da20eabd
ML		 11677
11678/**
11679 * intel_wm_need_update - Check whether watermarks need updating
11680 * @plane: drm plane
11681 * @state: new plane state
11682 *
11683 * Check current plane state versus the new one to determine whether
11684 * watermarks need to be recalculated.
11685 *
11686 * Returns true or false.
11687 */
11688static bool intel_wm_need_update(struct drm_plane *plane,
11689 struct drm_plane_state *state)
11690{
11691 /* Update watermarks on tiling changes. */
11692 if (!plane->state->fb || !state->fb ||
11693 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11694 plane->state->rotation != state->rotation)
11695 return true;
11696
11697 if (plane->state->crtc_w != state->crtc_w)
11698 return true;
11699
11700 return false;
11701}
11702
11703int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11704 struct drm_plane_state *plane_state)
11705{
11706 struct drm_crtc *crtc = crtc_state->crtc;
11707 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11708 struct drm_plane *plane = plane_state->plane;
11709 struct drm_device *dev = crtc->dev;
11710 struct drm_i915_private *dev_priv = dev->dev_private;
11711 struct intel_plane_state *old_plane_state =
11712 to_intel_plane_state(plane->state);
11713 int idx = intel_crtc->base.base.id, ret;
11714 int i = drm_plane_index(plane);
11715 bool mode_changed = needs_modeset(crtc_state);
11716 bool was_crtc_enabled = crtc->state->active;
11717 bool is_crtc_enabled = crtc_state->active;
11718
11719 bool turn_off, turn_on, visible, was_visible;
11720 struct drm_framebuffer *fb = plane_state->fb;
11721
11722 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11723 plane->type != DRM_PLANE_TYPE_CURSOR) {
11724 ret = skl_update_scaler_plane(
11725 to_intel_crtc_state(crtc_state),
11726 to_intel_plane_state(plane_state));
11727 if (ret)
11728 return ret;
11729 }
11730
11731 /*
11732 * Disabling a plane is always okay; we just need to update
11733 * fb tracking in a special way since cleanup_fb() won't
11734 * get called by the plane helpers.
11735 */
11736 if (old_plane_state->base.fb && !fb)
11737 intel_crtc->atomic.disabled_planes |= 1 << i;
11738
11739 /* don't run rest during modeset yet */
11740 if (!intel_crtc->active || mode_changed)
11741 return 0;
11742
11743 was_visible = old_plane_state->visible;
11744 visible = to_intel_plane_state(plane_state)->visible;
11745
11746 if (!was_crtc_enabled && WARN_ON(was_visible))
11747 was_visible = false;
11748
11749 if (!is_crtc_enabled && WARN_ON(visible))
11750 visible = false;
11751
11752 if (!was_visible && !visible)
11753 return 0;
11754
11755 turn_off = was_visible && (!visible || mode_changed);
11756 turn_on = visible && (!was_visible || mode_changed);
11757
11758 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11759 plane->base.id, fb ? fb->base.id : -1);
11760
11761 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11762 plane->base.id, was_visible, visible,
11763 turn_off, turn_on, mode_changed);
11764
11765 if (intel_wm_need_update(plane, plane_state))
11766 intel_crtc->atomic.update_wm = true;
11767
11768 switch (plane->type) {
11769 case DRM_PLANE_TYPE_PRIMARY:
11770 if (visible)
11771 intel_crtc->atomic.fb_bits |=
11772 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
11773
11774 intel_crtc->atomic.wait_for_flips = true;
11775 intel_crtc->atomic.pre_disable_primary = turn_off;
11776 intel_crtc->atomic.post_enable_primary = turn_on;
11777
11778 if (turn_off)
11779 intel_crtc->atomic.disable_fbc = true;
11780
11781 /*
11782 * FBC does not work on some platforms for rotated
11783 * planes, so disable it when rotation is not 0 and
11784 * update it when rotation is set back to 0.
11785 *
11786 * FIXME: This is redundant with the fbc update done in
11787 * the primary plane enable function except that that
11788 * one is done too late. We eventually need to unify
11789 * this.
11790 */
11791
11792 if (visible &&
11793 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11794 dev_priv->fbc.crtc == intel_crtc &&
11795 plane_state->rotation != BIT(DRM_ROTATE_0))
11796 intel_crtc->atomic.disable_fbc = true;
11797
11798 /*
11799 * BDW signals flip done immediately if the plane
11800 * is disabled, even if the plane enable is already
11801 * armed to occur at the next vblank :(
11802 */
11803 if (turn_on && IS_BROADWELL(dev))
11804 intel_crtc->atomic.wait_vblank = true;
11805
11806 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11807 break;
11808 case DRM_PLANE_TYPE_CURSOR:
11809 if (visible)
11810 intel_crtc->atomic.fb_bits |=
11811 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
11812 break;
11813 case DRM_PLANE_TYPE_OVERLAY:
11814 /*
11815 * 'prepare' is never called when plane is being disabled, so
11816 * we need to handle frontbuffer tracking as a special case
11817 */
11818 if (visible)
11819 intel_crtc->atomic.fb_bits |=
11820 INTEL_FRONTBUFFER_SPRITE(intel_crtc->pipe);
11821
11822 if (turn_off && is_crtc_enabled) {
11823 intel_crtc->atomic.wait_vblank = true;
11824 intel_crtc->atomic.update_sprite_watermarks |=
11825 1 << i;
11826 }
11827 break;
11828 }
11829 return 0;
11830}
11831
6d3a1ce7
ML		 11832static bool encoders_cloneable(const struct intel_encoder *a,
11833 const struct intel_encoder *b)
11834{
11835 /* masks could be asymmetric, so check both ways */
11836 return a == b || (a->cloneable & (1 << b->type) &&
11837 b->cloneable & (1 << a->type));
11838}
11839
11840static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11841 struct intel_crtc *crtc,
11842 struct intel_encoder *encoder)
11843{
11844 struct intel_encoder *source_encoder;
11845 struct drm_connector *connector;
11846 struct drm_connector_state *connector_state;
11847 int i;
11848
11849 for_each_connector_in_state(state, connector, connector_state, i) {
11850 if (connector_state->crtc != &crtc->base)
11851 continue;
11852
11853 source_encoder =
11854 to_intel_encoder(connector_state->best_encoder);
11855 if (!encoders_cloneable(encoder, source_encoder))
11856 return false;
11857 }
11858
11859 return true;
11860}
11861
11862static bool check_encoder_cloning(struct drm_atomic_state *state,
11863 struct intel_crtc *crtc)
11864{
11865 struct intel_encoder *encoder;
11866 struct drm_connector *connector;
11867 struct drm_connector_state *connector_state;
11868 int i;
11869
11870 for_each_connector_in_state(state, connector, connector_state, i) {
11871 if (connector_state->crtc != &crtc->base)
11872 continue;
11873
11874 encoder = to_intel_encoder(connector_state->best_encoder);
11875 if (!check_single_encoder_cloning(state, crtc, encoder))
11876 return false;
11877 }
11878
11879 return true;
11880}
11881
11882static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11883 struct drm_crtc_state *crtc_state)
11884{
cf5a15be 11885 struct drm_device *dev = crtc->dev;
ad421372 11886 struct drm_i915_private *dev_priv = dev->dev_private;
6d3a1ce7 11887 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cf5a15be
ML		 11888 struct intel_crtc_state *pipe_config =
11889 to_intel_crtc_state(crtc_state);
6d3a1ce7 11890 struct drm_atomic_state *state = crtc_state->state;
ad421372 11891 int ret, idx = crtc->base.id;
6d3a1ce7
ML		 11892 bool mode_changed = needs_modeset(crtc_state);
11893
11894 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11895 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11896 return -EINVAL;
11897 }
11898
11899 I915_STATE_WARN(crtc->state->active != intel_crtc->active,
11900 "[CRTC:%i] mismatch between state->active(%i) and crtc->active(%i)\n",
11901 idx, crtc->state->active, intel_crtc->active);
11902
ad421372
ML		 11903 if (mode_changed && crtc_state->enable &&
11904 dev_priv->display.crtc_compute_clock &&
11905 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11906 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11907 pipe_config);
11908 if (ret)
11909 return ret;
11910 }
11911
cf5a15be 11912 return intel_atomic_setup_scalers(dev, intel_crtc, pipe_config);
6d3a1ce7
ML		 11913}
11914
65b38e0d 11915static const struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 11916 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11917 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 11918 .atomic_begin = intel_begin_crtc_commit,
11919 .atomic_flush = intel_finish_crtc_commit,
6d3a1ce7 11920 .atomic_check = intel_crtc_atomic_check,
f6e5b160
CW		 11921};
11922
9a935856
DV		 11923/**
11924 * intel_modeset_update_staged_output_state
11925 *
11926 * Updates the staged output configuration state, e.g. after we've read out the
11927 * current hw state.
11928 */
11929static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 11930{
7668851f 11931 struct intel_crtc *crtc;
9a935856
DV		 11932 struct intel_encoder *encoder;
11933 struct intel_connector *connector;
f6e5b160 11934
3a3371ff 11935 for_each_intel_connector(dev, connector) {
9a935856
DV		 11936 connector->new_encoder =
11937 to_intel_encoder(connector->base.encoder);
11938 }
f6e5b160 11939
b2784e15 11940 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 11941 encoder->new_crtc =
11942 to_intel_crtc(encoder->base.crtc);
11943 }
7668851f 11944
d3fcc808 11945 for_each_intel_crtc(dev, crtc) {
83d65738 11946 crtc->new_enabled = crtc->base.state->enable;
7668851f 11947 }
f6e5b160
CW		 11948}
11949
d29b2f9d
ACO		 11950/* Transitional helper to copy current connector/encoder state to
11951 * connector->state. This is needed so that code that is partially
11952 * converted to atomic does the right thing.
11953 */
11954static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11955{
11956 struct intel_connector *connector;
11957
11958 for_each_intel_connector(dev, connector) {
11959 if (connector->base.encoder) {
11960 connector->base.state->best_encoder =
11961 connector->base.encoder;
11962 connector->base.state->crtc =
11963 connector->base.encoder->crtc;
11964 } else {
11965 connector->base.state->best_encoder = NULL;
11966 connector->base.state->crtc = NULL;
11967 }
11968 }
11969}
11970
050f7aeb 11971static void
eba905b2 11972connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 11973 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 11974{
11975 int bpp = pipe_config->pipe_bpp;
11976
11977 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11978 connector->base.base.id,
c23cc417 11979 connector->base.name);
050f7aeb
DV		 11980
11981 /* Don't use an invalid EDID bpc value */
11982 if (connector->base.display_info.bpc &&
11983 connector->base.display_info.bpc * 3 < bpp) {
11984 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11985 bpp, connector->base.display_info.bpc*3);
11986 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11987 }
11988
11989 /* Clamp bpp to 8 on screens without EDID 1.4 */
11990 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11991 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11992 bpp);
11993 pipe_config->pipe_bpp = 24;
11994 }
11995}
11996
4e53c2e0 11997static int
050f7aeb 11998compute_baseline_pipe_bpp(struct intel_crtc *crtc,
5cec258b 11999 struct intel_crtc_state *pipe_config)
4e53c2e0 12000{
050f7aeb 12001 struct drm_device *dev = crtc->base.dev;
1486017f 12002 struct drm_atomic_state *state;
da3ced29
ACO		 12003 struct drm_connector *connector;
12004 struct drm_connector_state *connector_state;
1486017f 12005 int bpp, i;
4e53c2e0 12006
d328c9d7 12007 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
4e53c2e0 12008 bpp = 10*3;
d328c9d7
DV		 12009 else if (INTEL_INFO(dev)->gen >= 5)
12010 bpp = 12*3;
12011 else
12012 bpp = 8*3;
12013
4e53c2e0 12014
4e53c2e0
DV		 12015 pipe_config->pipe_bpp = bpp;
12016
1486017f
ACO		 12017 state = pipe_config->base.state;
12018
4e53c2e0 12019 /* Clamp display bpp to EDID value */
da3ced29
ACO		 12020 for_each_connector_in_state(state, connector, connector_state, i) {
12021 if (connector_state->crtc != &crtc->base)
4e53c2e0
DV		 12022 continue;
12023
da3ced29
ACO		 12024 connected_sink_compute_bpp(to_intel_connector(connector),
12025 pipe_config);
4e53c2e0
DV		 12026 }
12027
12028 return bpp;
12029}
12030
644db711
DV		 12031static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12032{
12033 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12034 "type: 0x%x flags: 0x%x\n",
1342830c 12035 mode->crtc_clock,
644db711
DV		 12036 mode->crtc_hdisplay, mode->crtc_hsync_start,
12037 mode->crtc_hsync_end, mode->crtc_htotal,
12038 mode->crtc_vdisplay, mode->crtc_vsync_start,
12039 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12040}
12041
c0b03411 12042static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 12043 struct intel_crtc_state *pipe_config,
c0b03411
DV		 12044 const char *context)
12045{
6a60cd87
CK		 12046 struct drm_device *dev = crtc->base.dev;
12047 struct drm_plane *plane;
12048 struct intel_plane *intel_plane;
12049 struct intel_plane_state *state;
12050 struct drm_framebuffer *fb;
12051
12052 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
12053 context, pipe_config, pipe_name(crtc->pipe));
c0b03411
DV		 12054
12055 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
12056 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12057 pipe_config->pipe_bpp, pipe_config->dither);
12058 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12059 pipe_config->has_pch_encoder,
12060 pipe_config->fdi_lanes,
12061 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12062 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12063 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 12064 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12065 pipe_config->has_dp_encoder,
12066 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12067 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12068 pipe_config->dp_m_n.tu);
b95af8be
VK		 12069
12070 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12071 pipe_config->has_dp_encoder,
12072 pipe_config->dp_m2_n2.gmch_m,
12073 pipe_config->dp_m2_n2.gmch_n,
12074 pipe_config->dp_m2_n2.link_m,
12075 pipe_config->dp_m2_n2.link_n,
12076 pipe_config->dp_m2_n2.tu);
12077
55072d19
DV		 12078 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12079 pipe_config->has_audio,
12080 pipe_config->has_infoframe);
12081
c0b03411 12082 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 12083 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 12084 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 12085 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12086 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 12087 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 12088 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12089 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
0ec463d3
TU		 12090 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12091 crtc->num_scalers,
12092 pipe_config->scaler_state.scaler_users,
12093 pipe_config->scaler_state.scaler_id);
c0b03411
DV		 12094 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12095 pipe_config->gmch_pfit.control,
12096 pipe_config->gmch_pfit.pgm_ratios,
12097 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 12098 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 12099 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 12100 pipe_config->pch_pfit.size,
12101 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 12102 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 12103 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87 12104
415ff0f6
TU		 12105 if (IS_BROXTON(dev)) {
12106 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, "
12107 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12108 "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n",
12109 pipe_config->ddi_pll_sel,
12110 pipe_config->dpll_hw_state.ebb0,
12111 pipe_config->dpll_hw_state.pll0,
12112 pipe_config->dpll_hw_state.pll1,
12113 pipe_config->dpll_hw_state.pll2,
12114 pipe_config->dpll_hw_state.pll3,
12115 pipe_config->dpll_hw_state.pll6,
12116 pipe_config->dpll_hw_state.pll8,
12117 pipe_config->dpll_hw_state.pcsdw12);
12118 } else if (IS_SKYLAKE(dev)) {
12119 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12120 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12121 pipe_config->ddi_pll_sel,
12122 pipe_config->dpll_hw_state.ctrl1,
12123 pipe_config->dpll_hw_state.cfgcr1,
12124 pipe_config->dpll_hw_state.cfgcr2);
12125 } else if (HAS_DDI(dev)) {
12126 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
12127 pipe_config->ddi_pll_sel,
12128 pipe_config->dpll_hw_state.wrpll);
12129 } else {
12130 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12131 "fp0: 0x%x, fp1: 0x%x\n",
12132 pipe_config->dpll_hw_state.dpll,
12133 pipe_config->dpll_hw_state.dpll_md,
12134 pipe_config->dpll_hw_state.fp0,
12135 pipe_config->dpll_hw_state.fp1);
12136 }
12137
6a60cd87
CK		 12138 DRM_DEBUG_KMS("planes on this crtc\n");
12139 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12140 intel_plane = to_intel_plane(plane);
12141 if (intel_plane->pipe != crtc->pipe)
12142 continue;
12143
12144 state = to_intel_plane_state(plane->state);
12145 fb = state->base.fb;
12146 if (!fb) {
12147 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12148 "disabled, scaler_id = %d\n",
12149 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12150 plane->base.id, intel_plane->pipe,
12151 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12152 drm_plane_index(plane), state->scaler_id);
12153 continue;
12154 }
12155
12156 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12157 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12158 plane->base.id, intel_plane->pipe,
12159 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12160 drm_plane_index(plane));
12161 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12162 fb->base.id, fb->width, fb->height, fb->pixel_format);
12163 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12164 state->scaler_id,
12165 state->src.x1 >> 16, state->src.y1 >> 16,
12166 drm_rect_width(&state->src) >> 16,
12167 drm_rect_height(&state->src) >> 16,
12168 state->dst.x1, state->dst.y1,
12169 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12170 }
c0b03411
DV		 12171}
12172
5448a00d 12173static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 12174{
5448a00d
ACO		 12175 struct drm_device *dev = state->dev;
12176 struct intel_encoder *encoder;
da3ced29 12177 struct drm_connector *connector;
5448a00d 12178 struct drm_connector_state *connector_state;
00f0b378 12179 unsigned int used_ports = 0;
5448a00d 12180 int i;
00f0b378
VS		 12181
12182 /*
12183 * Walk the connector list instead of the encoder
12184 * list to detect the problem on ddi platforms
12185 * where there's just one encoder per digital port.
12186 */
da3ced29 12187 for_each_connector_in_state(state, connector, connector_state, i) {
5448a00d 12188 if (!connector_state->best_encoder)
00f0b378
VS		 12189 continue;
12190
5448a00d
ACO		 12191 encoder = to_intel_encoder(connector_state->best_encoder);
12192
12193 WARN_ON(!connector_state->crtc);
00f0b378
VS		 12194
12195 switch (encoder->type) {
12196 unsigned int port_mask;
12197 case INTEL_OUTPUT_UNKNOWN:
12198 if (WARN_ON(!HAS_DDI(dev)))
12199 break;
12200 case INTEL_OUTPUT_DISPLAYPORT:
12201 case INTEL_OUTPUT_HDMI:
12202 case INTEL_OUTPUT_EDP:
12203 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12204
12205 /* the same port mustn't appear more than once */
12206 if (used_ports & port_mask)
12207 return false;
12208
12209 used_ports |= port_mask;
12210 default:
12211 break;
12212 }
12213 }
12214
12215 return true;
12216}
12217
83a57153
ACO		 12218static void
12219clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12220{
12221 struct drm_crtc_state tmp_state;
663a3640 12222 struct intel_crtc_scaler_state scaler_state;
4978cc93
ACO		 12223 struct intel_dpll_hw_state dpll_hw_state;
12224 enum intel_dpll_id shared_dpll;
8504c74c 12225 uint32_t ddi_pll_sel;
83a57153 12226
7546a384
ACO		 12227 /* FIXME: before the switch to atomic started, a new pipe_config was
12228 * kzalloc'd. Code that depends on any field being zero should be
12229 * fixed, so that the crtc_state can be safely duplicated. For now,
12230 * only fields that are know to not cause problems are preserved. */
12231
83a57153 12232 tmp_state = crtc_state->base;
663a3640 12233 scaler_state = crtc_state->scaler_state;
4978cc93
ACO		 12234 shared_dpll = crtc_state->shared_dpll;
12235 dpll_hw_state = crtc_state->dpll_hw_state;
8504c74c 12236 ddi_pll_sel = crtc_state->ddi_pll_sel;
4978cc93 12237
83a57153 12238 memset(crtc_state, 0, sizeof *crtc_state);
4978cc93 12239
83a57153 12240 crtc_state->base = tmp_state;
663a3640 12241 crtc_state->scaler_state = scaler_state;
4978cc93
ACO		 12242 crtc_state->shared_dpll = shared_dpll;
12243 crtc_state->dpll_hw_state = dpll_hw_state;
8504c74c 12244 crtc_state->ddi_pll_sel = ddi_pll_sel;
83a57153
ACO		 12245}
12246
548ee15b 12247static int
b8cecdf5 12248intel_modeset_pipe_config(struct drm_crtc *crtc,
b359283a 12249 struct intel_crtc_state *pipe_config)
ee7b9f93 12250{
b359283a 12251 struct drm_atomic_state *state = pipe_config->base.state;
7758a113 12252 struct intel_encoder *encoder;
da3ced29 12253 struct drm_connector *connector;
0b901879 12254 struct drm_connector_state *connector_state;
d328c9d7 12255 int base_bpp, ret = -EINVAL;
0b901879 12256 int i;
e29c22c0 12257 bool retry = true;
ee7b9f93 12258
83a57153 12259 clear_intel_crtc_state(pipe_config);
7758a113 12260
e143a21c
DV		 12261 pipe_config->cpu_transcoder =
12262 (enum transcoder) to_intel_crtc(crtc)->pipe;
b8cecdf5 12263
2960bc9c
ID		 12264 /*
12265 * Sanitize sync polarity flags based on requested ones. If neither
12266 * positive or negative polarity is requested, treat this as meaning
12267 * negative polarity.
12268 */
2d112de7 12269 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12270 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 12271 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 12272
2d112de7 12273 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12274 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 12275 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 12276
050f7aeb
DV		 12277 /* Compute a starting value for pipe_config->pipe_bpp taking the source
12278 * plane pixel format and any sink constraints into account. Returns the
12279 * source plane bpp so that dithering can be selected on mismatches
12280 * after encoders and crtc also have had their say. */
d328c9d7
DV		 12281 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12282 pipe_config);
12283 if (base_bpp < 0)
4e53c2e0
DV		 12284 goto fail;
12285
e41a56be
VS		 12286 /*
12287 * Determine the real pipe dimensions. Note that stereo modes can
12288 * increase the actual pipe size due to the frame doubling and
12289 * insertion of additional space for blanks between the frame. This
12290 * is stored in the crtc timings. We use the requested mode to do this
12291 * computation to clearly distinguish it from the adjusted mode, which
12292 * can be changed by the connectors in the below retry loop.
12293 */
2d112de7 12294 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 12295 &pipe_config->pipe_src_w,
12296 &pipe_config->pipe_src_h);
e41a56be 12297
e29c22c0 12298encoder_retry:
ef1b460d 12299 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 12300 pipe_config->port_clock = 0;
ef1b460d 12301 pipe_config->pixel_multiplier = 1;
ff9a6750 12302
135c81b8 12303 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 12304 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12305 CRTC_STEREO_DOUBLE);
135c81b8 12306
7758a113
DV		 12307 /* Pass our mode to the connectors and the CRTC to give them a chance to
12308 * adjust it according to limitations or connector properties, and also
12309 * a chance to reject the mode entirely.
47f1c6c9 12310 */
da3ced29 12311 for_each_connector_in_state(state, connector, connector_state, i) {
0b901879 12312 if (connector_state->crtc != crtc)
7758a113 12313 continue;
7ae89233 12314
0b901879
ACO		 12315 encoder = to_intel_encoder(connector_state->best_encoder);
12316
efea6e8e
DV		 12317 if (!(encoder->compute_config(encoder, pipe_config))) {
12318 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 12319 goto fail;
12320 }
ee7b9f93 12321 }
47f1c6c9 12322
ff9a6750
DV		 12323 /* Set default port clock if not overwritten by the encoder. Needs to be
12324 * done afterwards in case the encoder adjusts the mode. */
12325 if (!pipe_config->port_clock)
2d112de7 12326 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 12327 * pipe_config->pixel_multiplier;
ff9a6750 12328
a43f6e0f 12329 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 12330 if (ret < 0) {
7758a113
DV		 12331 DRM_DEBUG_KMS("CRTC fixup failed\n");
12332 goto fail;
ee7b9f93 12333 }
e29c22c0
DV		 12334
12335 if (ret == RETRY) {
12336 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12337 ret = -EINVAL;
12338 goto fail;
12339 }
12340
12341 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12342 retry = false;
12343 goto encoder_retry;
12344 }
12345
d328c9d7 12346 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
4e53c2e0 12347 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
d328c9d7 12348 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
4e53c2e0 12349
cdba954e
ACO		 12350 /* Check if we need to force a modeset */
12351 if (pipe_config->has_audio !=
85a96e7a 12352 to_intel_crtc_state(crtc->state)->has_audio) {
cdba954e 12353 pipe_config->base.mode_changed = true;
85a96e7a
ML		 12354 ret = drm_atomic_add_affected_planes(state, crtc);
12355 }
cdba954e
ACO		 12356
12357 /*
12358 * Note we have an issue here with infoframes: current code
12359 * only updates them on the full mode set path per hw
12360 * requirements. So here we should be checking for any
12361 * required changes and forcing a mode set.
12362 */
7758a113 12363fail:
548ee15b 12364 return ret;
ee7b9f93 12365}
47f1c6c9 12366
ea9d758d 12367static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 12368{
ea9d758d 12369 struct drm_encoder *encoder;
f6e5b160 12370 struct drm_device *dev = crtc->dev;
f6e5b160 12371
ea9d758d
DV		 12372 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
12373 if (encoder->crtc == crtc)
12374 return true;
12375
12376 return false;
12377}
12378
12379static void
0a9ab303 12380intel_modeset_update_state(struct drm_atomic_state *state)
ea9d758d 12381{
0a9ab303 12382 struct drm_device *dev = state->dev;
ea9d758d 12383 struct intel_encoder *intel_encoder;
0a9ab303
ACO		 12384 struct drm_crtc *crtc;
12385 struct drm_crtc_state *crtc_state;
ea9d758d
DV		 12386 struct drm_connector *connector;
12387
de419ab6 12388 intel_shared_dpll_commit(state);
ba41c0de 12389
b2784e15 12390 for_each_intel_encoder(dev, intel_encoder) {
ea9d758d
DV		 12391 if (!intel_encoder->base.crtc)
12392 continue;
12393
69024de8
ML		 12394 crtc = intel_encoder->base.crtc;
12395 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12396 if (!crtc_state || !needs_modeset(crtc->state))
12397 continue;
ea9d758d 12398
69024de8 12399 intel_encoder->connectors_active = false;
ea9d758d
DV		 12400 }
12401
3cb480bc 12402 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
f7217905 12403 intel_modeset_update_staged_output_state(state->dev);
ea9d758d 12404
7668851f 12405 /* Double check state. */
0a9ab303
ACO		 12406 for_each_crtc(dev, crtc) {
12407 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
3cb480bc
ML		 12408
12409 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
fc467a22
ML		 12410
12411 /* Update hwmode for vblank functions */
12412 if (crtc->state->active)
12413 crtc->hwmode = crtc->state->adjusted_mode;
12414 else
12415 crtc->hwmode.crtc_clock = 0;
ea9d758d
DV		 12416 }
12417
12418 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12419 if (!connector->encoder || !connector->encoder->crtc)
12420 continue;
12421
69024de8
ML		 12422 crtc = connector->encoder->crtc;
12423 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12424 if (!crtc_state || !needs_modeset(crtc->state))
12425 continue;
ea9d758d 12426
53d9f4e9 12427 if (crtc->state->active) {
69024de8
ML		 12428 struct drm_property *dpms_property =
12429 dev->mode_config.dpms_property;
68d34720 12430
69024de8
ML		 12431 connector->dpms = DRM_MODE_DPMS_ON;
12432 drm_object_property_set_value(&connector->base, dpms_property, DRM_MODE_DPMS_ON);
ea9d758d 12433
69024de8
ML		 12434 intel_encoder = to_intel_encoder(connector->encoder);
12435 intel_encoder->connectors_active = true;
12436 } else
12437 connector->dpms = DRM_MODE_DPMS_OFF;
ea9d758d 12438 }
ea9d758d
DV		 12439}
12440
3bd26263 12441static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 12442{
3bd26263 12443 int diff;
f1f644dc
JB		 12444
12445 if (clock1 == clock2)
12446 return true;
12447
12448 if (!clock1 || !clock2)
12449 return false;
12450
12451 diff = abs(clock1 - clock2);
12452
12453 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12454 return true;
12455
12456 return false;
12457}
12458
25c5b266
DV		 12459#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12460 list_for_each_entry((intel_crtc), \
12461 &(dev)->mode_config.crtc_list, \
12462 base.head) \
0973f18f 12463 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 12464
0e8ffe1b 12465static bool
2fa2fe9a 12466intel_pipe_config_compare(struct drm_device *dev,
5cec258b
ACO		 12467 struct intel_crtc_state *current_config,
12468 struct intel_crtc_state *pipe_config)
0e8ffe1b 12469{
66e985c0
DV		 12470#define PIPE_CONF_CHECK_X(name) \
12471 if (current_config->name != pipe_config->name) { \
12472 DRM_ERROR("mismatch in " #name " " \
12473 "(expected 0x%08x, found 0x%08x)\n", \
12474 current_config->name, \
12475 pipe_config->name); \
12476 return false; \
12477 }
12478
08a24034
DV		 12479#define PIPE_CONF_CHECK_I(name) \
12480 if (current_config->name != pipe_config->name) { \
12481 DRM_ERROR("mismatch in " #name " " \
12482 "(expected %i, found %i)\n", \
12483 current_config->name, \
12484 pipe_config->name); \
12485 return false; \
88adfff1
DV		 12486 }
12487
b95af8be
VK		 12488/* This is required for BDW+ where there is only one set of registers for
12489 * switching between high and low RR.
12490 * This macro can be used whenever a comparison has to be made between one
12491 * hw state and multiple sw state variables.
12492 */
12493#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12494 if ((current_config->name != pipe_config->name) && \
12495 (current_config->alt_name != pipe_config->name)) { \
12496 DRM_ERROR("mismatch in " #name " " \
12497 "(expected %i or %i, found %i)\n", \
12498 current_config->name, \
12499 current_config->alt_name, \
12500 pipe_config->name); \
12501 return false; \
12502 }
12503
1bd1bd80
DV		 12504#define PIPE_CONF_CHECK_FLAGS(name, mask) \
12505 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 12506 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 12507 "(expected %i, found %i)\n", \
12508 current_config->name & (mask), \
12509 pipe_config->name & (mask)); \
12510 return false; \
12511 }
12512
5e550656
VS		 12513#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12514 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12515 DRM_ERROR("mismatch in " #name " " \
12516 "(expected %i, found %i)\n", \
12517 current_config->name, \
12518 pipe_config->name); \
12519 return false; \
12520 }
12521
bb760063
DV		 12522#define PIPE_CONF_QUIRK(quirk) \
12523 ((current_config->quirks | pipe_config->quirks) & (quirk))
12524
eccb140b
DV		 12525 PIPE_CONF_CHECK_I(cpu_transcoder);
12526
08a24034
DV		 12527 PIPE_CONF_CHECK_I(has_pch_encoder);
12528 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 12529 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
12530 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
12531 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
12532 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
12533 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 12534
eb14cb74 12535 PIPE_CONF_CHECK_I(has_dp_encoder);
b95af8be
VK		 12536
12537 if (INTEL_INFO(dev)->gen < 8) {
12538 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
12539 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
12540 PIPE_CONF_CHECK_I(dp_m_n.link_m);
12541 PIPE_CONF_CHECK_I(dp_m_n.link_n);
12542 PIPE_CONF_CHECK_I(dp_m_n.tu);
12543
12544 if (current_config->has_drrs) {
12545 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
12546 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
12547 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
12548 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
12549 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
12550 }
12551 } else {
12552 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
12553 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
12554 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
12555 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
12556 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
12557 }
eb14cb74 12558
2d112de7
ACO		 12559 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12560 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12561 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12562 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12563 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12564 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 12565
2d112de7
ACO		 12566 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12567 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12568 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12569 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12570 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12571 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 12572
c93f54cf 12573 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 12574 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 12575 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12576 IS_VALLEYVIEW(dev))
12577 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 12578 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 12579
9ed109a7
DV		 12580 PIPE_CONF_CHECK_I(has_audio);
12581
2d112de7 12582 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 12583 DRM_MODE_FLAG_INTERLACE);
12584
bb760063 12585 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 12586 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12587 DRM_MODE_FLAG_PHSYNC);
2d112de7 12588 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12589 DRM_MODE_FLAG_NHSYNC);
2d112de7 12590 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12591 DRM_MODE_FLAG_PVSYNC);
2d112de7 12592 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 12593 DRM_MODE_FLAG_NVSYNC);
12594 }
045ac3b5 12595
37327abd
VS		 12596 PIPE_CONF_CHECK_I(pipe_src_w);
12597 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 12598
9953599b
DV		 12599 /*
12600 * FIXME: BIOS likes to set up a cloned config with lvds+external
12601 * screen. Since we don't yet re-compute the pipe config when moving
12602 * just the lvds port away to another pipe the sw tracking won't match.
12603 *
12604 * Proper atomic modesets with recomputed global state will fix this.
12605 * Until then just don't check gmch state for inherited modes.
12606 */
12607 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
12608 PIPE_CONF_CHECK_I(gmch_pfit.control);
12609 /* pfit ratios are autocomputed by the hw on gen4+ */
12610 if (INTEL_INFO(dev)->gen < 4)
12611 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12612 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12613 }
12614
fd4daa9c
CW		 12615 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12616 if (current_config->pch_pfit.enabled) {
12617 PIPE_CONF_CHECK_I(pch_pfit.pos);
12618 PIPE_CONF_CHECK_I(pch_pfit.size);
12619 }
2fa2fe9a 12620
a1b2278e
CK		 12621 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12622
e59150dc
JB		 12623 /* BDW+ don't expose a synchronous way to read the state */
12624 if (IS_HASWELL(dev))
12625 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 12626
282740f7
VS		 12627 PIPE_CONF_CHECK_I(double_wide);
12628
26804afd
DV		 12629 PIPE_CONF_CHECK_X(ddi_pll_sel);
12630
c0d43d62 12631 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 12632 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 12633 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 12634 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12635 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 12636 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 12637 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12638 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12639 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 12640
42571aef
VS		 12641 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12642 PIPE_CONF_CHECK_I(pipe_bpp);
12643
2d112de7 12644 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 12645 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 12646
66e985c0 12647#undef PIPE_CONF_CHECK_X
08a24034 12648#undef PIPE_CONF_CHECK_I
b95af8be 12649#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 12650#undef PIPE_CONF_CHECK_FLAGS
5e550656 12651#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 12652#undef PIPE_CONF_QUIRK
88adfff1 12653
0e8ffe1b
DV		 12654 return true;
12655}
12656
08db6652
DL		 12657static void check_wm_state(struct drm_device *dev)
12658{
12659 struct drm_i915_private *dev_priv = dev->dev_private;
12660 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12661 struct intel_crtc *intel_crtc;
12662 int plane;
12663
12664 if (INTEL_INFO(dev)->gen < 9)
12665 return;
12666
12667 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12668 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12669
12670 for_each_intel_crtc(dev, intel_crtc) {
12671 struct skl_ddb_entry *hw_entry, *sw_entry;
12672 const enum pipe pipe = intel_crtc->pipe;
12673
12674 if (!intel_crtc->active)
12675 continue;
12676
12677 /* planes */
dd740780 12678 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 12679 hw_entry = &hw_ddb.plane[pipe][plane];
12680 sw_entry = &sw_ddb->plane[pipe][plane];
12681
12682 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12683 continue;
12684
12685 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12686 "(expected (%u,%u), found (%u,%u))\n",
12687 pipe_name(pipe), plane + 1,
12688 sw_entry->start, sw_entry->end,
12689 hw_entry->start, hw_entry->end);
12690 }
12691
12692 /* cursor */
12693 hw_entry = &hw_ddb.cursor[pipe];
12694 sw_entry = &sw_ddb->cursor[pipe];
12695
12696 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12697 continue;
12698
12699 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12700 "(expected (%u,%u), found (%u,%u))\n",
12701 pipe_name(pipe),
12702 sw_entry->start, sw_entry->end,
12703 hw_entry->start, hw_entry->end);
12704 }
12705}
12706
91d1b4bd
DV		 12707static void
12708check_connector_state(struct drm_device *dev)
8af6cf88 12709{
8af6cf88
DV		 12710 struct intel_connector *connector;
12711
3a3371ff 12712 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 12713 /* This also checks the encoder/connector hw state with the
12714 * ->get_hw_state callbacks. */
12715 intel_connector_check_state(connector);
12716
e2c719b7 12717 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
8af6cf88
DV		 12718 "connector's staged encoder doesn't match current encoder\n");
12719 }
91d1b4bd
DV		 12720}
12721
12722static void
12723check_encoder_state(struct drm_device *dev)
12724{
12725 struct intel_encoder *encoder;
12726 struct intel_connector *connector;
8af6cf88 12727
b2784e15 12728 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 12729 bool enabled = false;
12730 bool active = false;
12731 enum pipe pipe, tracked_pipe;
12732
12733 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12734 encoder->base.base.id,
8e329a03 12735 encoder->base.name);
8af6cf88 12736
e2c719b7 12737 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
8af6cf88 12738 "encoder's stage crtc doesn't match current crtc\n");
e2c719b7 12739 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
8af6cf88
DV		 12740 "encoder's active_connectors set, but no crtc\n");
12741
3a3371ff 12742 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 12743 if (connector->base.encoder != &encoder->base)
12744 continue;
12745 enabled = true;
12746 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12747 active = true;
12748 }
0e32b39c
DA		 12749 /*
12750 * for MST connectors if we unplug the connector is gone
12751 * away but the encoder is still connected to a crtc
12752 * until a modeset happens in response to the hotplug.
12753 */
12754 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12755 continue;
12756
e2c719b7 12757 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 12758 "encoder's enabled state mismatch "
12759 "(expected %i, found %i)\n",
12760 !!encoder->base.crtc, enabled);
e2c719b7 12761 I915_STATE_WARN(active && !encoder->base.crtc,
8af6cf88
DV		 12762 "active encoder with no crtc\n");
12763
e2c719b7 12764 I915_STATE_WARN(encoder->connectors_active != active,
8af6cf88
DV		 12765 "encoder's computed active state doesn't match tracked active state "
12766 "(expected %i, found %i)\n", active, encoder->connectors_active);
12767
12768 active = encoder->get_hw_state(encoder, &pipe);
e2c719b7 12769 I915_STATE_WARN(active != encoder->connectors_active,
8af6cf88
DV		 12770 "encoder's hw state doesn't match sw tracking "
12771 "(expected %i, found %i)\n",
12772 encoder->connectors_active, active);
12773
12774 if (!encoder->base.crtc)
12775 continue;
12776
12777 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
e2c719b7 12778 I915_STATE_WARN(active && pipe != tracked_pipe,
8af6cf88
DV		 12779 "active encoder's pipe doesn't match"
12780 "(expected %i, found %i)\n",
12781 tracked_pipe, pipe);
12782
12783 }
91d1b4bd
DV		 12784}
12785
12786static void
12787check_crtc_state(struct drm_device *dev)
12788{
fbee40df 12789 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12790 struct intel_crtc *crtc;
12791 struct intel_encoder *encoder;
5cec258b 12792 struct intel_crtc_state pipe_config;
8af6cf88 12793
d3fcc808 12794 for_each_intel_crtc(dev, crtc) {
8af6cf88
DV		 12795 bool enabled = false;
12796 bool active = false;
12797
045ac3b5
JB		 12798 memset(&pipe_config, 0, sizeof(pipe_config));
12799
8af6cf88
DV		 12800 DRM_DEBUG_KMS("[CRTC:%d]\n",
12801 crtc->base.base.id);
12802
83d65738 12803 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
8af6cf88
DV		 12804 "active crtc, but not enabled in sw tracking\n");
12805
b2784e15 12806 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 12807 if (encoder->base.crtc != &crtc->base)
12808 continue;
12809 enabled = true;
12810 if (encoder->connectors_active)
12811 active = true;
12812 }
6c49f241 12813
e2c719b7 12814 I915_STATE_WARN(active != crtc->active,
8af6cf88
DV		 12815 "crtc's computed active state doesn't match tracked active state "
12816 "(expected %i, found %i)\n", active, crtc->active);
83d65738 12817 I915_STATE_WARN(enabled != crtc->base.state->enable,
8af6cf88 12818 "crtc's computed enabled state doesn't match tracked enabled state "
83d65738
MR		 12819 "(expected %i, found %i)\n", enabled,
12820 crtc->base.state->enable);
8af6cf88 12821
0e8ffe1b
DV		 12822 active = dev_priv->display.get_pipe_config(crtc,
12823 &pipe_config);
d62cf62a 12824
b6b5d049
VS		 12825 /* hw state is inconsistent with the pipe quirk */
12826 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12827 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
d62cf62a
DV		 12828 active = crtc->active;
12829
b2784e15 12830 for_each_intel_encoder(dev, encoder) {
3eaba51c 12831 enum pipe pipe;
6c49f241
DV		 12832 if (encoder->base.crtc != &crtc->base)
12833 continue;
1d37b689 12834 if (encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 12835 encoder->get_config(encoder, &pipe_config);
12836 }
12837
e2c719b7 12838 I915_STATE_WARN(crtc->active != active,
0e8ffe1b
DV		 12839 "crtc active state doesn't match with hw state "
12840 "(expected %i, found %i)\n", crtc->active, active);
12841
53d9f4e9
ML		 12842 I915_STATE_WARN(crtc->active != crtc->base.state->active,
12843 "transitional active state does not match atomic hw state "
12844 "(expected %i, found %i)\n", crtc->base.state->active, crtc->active);
12845
c0b03411 12846 if (active &&
6e3c9717 12847 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
e2c719b7 12848 I915_STATE_WARN(1, "pipe state doesn't match!\n");
c0b03411
DV		 12849 intel_dump_pipe_config(crtc, &pipe_config,
12850 "[hw state]");
6e3c9717 12851 intel_dump_pipe_config(crtc, crtc->config,
c0b03411
DV		 12852 "[sw state]");
12853 }
8af6cf88
DV		 12854 }
12855}
12856
91d1b4bd
DV		 12857static void
12858check_shared_dpll_state(struct drm_device *dev)
12859{
fbee40df 12860 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12861 struct intel_crtc *crtc;
12862 struct intel_dpll_hw_state dpll_hw_state;
12863 int i;
5358901f
DV		 12864
12865 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12866 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12867 int enabled_crtcs = 0, active_crtcs = 0;
12868 bool active;
12869
12870 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12871
12872 DRM_DEBUG_KMS("%s\n", pll->name);
12873
12874 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12875
e2c719b7 12876 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 12877 "more active pll users than references: %i vs %i\n",
3e369b76 12878 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 12879 I915_STATE_WARN(pll->active && !pll->on,
5358901f 12880 "pll in active use but not on in sw tracking\n");
e2c719b7 12881 I915_STATE_WARN(pll->on && !pll->active,
35c95375 12882 "pll in on but not on in use in sw tracking\n");
e2c719b7 12883 I915_STATE_WARN(pll->on != active,
5358901f
DV		 12884 "pll on state mismatch (expected %i, found %i)\n",
12885 pll->on, active);
12886
d3fcc808 12887 for_each_intel_crtc(dev, crtc) {
83d65738 12888 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 12889 enabled_crtcs++;
12890 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12891 active_crtcs++;
12892 }
e2c719b7 12893 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 12894 "pll active crtcs mismatch (expected %i, found %i)\n",
12895 pll->active, active_crtcs);
e2c719b7 12896 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 12897 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 12898 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 12899
e2c719b7 12900 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 12901 sizeof(dpll_hw_state)),
12902 "pll hw state mismatch\n");
5358901f 12903 }
8af6cf88
DV		 12904}
12905
91d1b4bd
DV		 12906void
12907intel_modeset_check_state(struct drm_device *dev)
12908{
08db6652 12909 check_wm_state(dev);
91d1b4bd
DV		 12910 check_connector_state(dev);
12911 check_encoder_state(dev);
12912 check_crtc_state(dev);
12913 check_shared_dpll_state(dev);
12914}
12915
5cec258b 12916void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 12917 int dotclock)
12918{
12919 /*
12920 * FDI already provided one idea for the dotclock.
12921 * Yell if the encoder disagrees.
12922 */
2d112de7 12923 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 12924 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 12925 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 12926}
12927
80715b2f
VS		 12928static void update_scanline_offset(struct intel_crtc *crtc)
12929{
12930 struct drm_device *dev = crtc->base.dev;
12931
12932 /*
12933 * The scanline counter increments at the leading edge of hsync.
12934 *
12935 * On most platforms it starts counting from vtotal-1 on the
12936 * first active line. That means the scanline counter value is
12937 * always one less than what we would expect. Ie. just after
12938 * start of vblank, which also occurs at start of hsync (on the
12939 * last active line), the scanline counter will read vblank_start-1.
12940 *
12941 * On gen2 the scanline counter starts counting from 1 instead
12942 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12943 * to keep the value positive), instead of adding one.
12944 *
12945 * On HSW+ the behaviour of the scanline counter depends on the output
12946 * type. For DP ports it behaves like most other platforms, but on HDMI
12947 * there's an extra 1 line difference. So we need to add two instead of
12948 * one to the value.
12949 */
12950 if (IS_GEN2(dev)) {
6e3c9717 12951 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 12952 int vtotal;
12953
12954 vtotal = mode->crtc_vtotal;
12955 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12956 vtotal /= 2;
12957
12958 crtc->scanline_offset = vtotal - 1;
12959 } else if (HAS_DDI(dev) &&
409ee761 12960 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 12961 crtc->scanline_offset = 2;
12962 } else
12963 crtc->scanline_offset = 1;
12964}
12965
ad421372 12966static void intel_modeset_clear_plls(struct drm_atomic_state *state)
ed6739ef 12967{
225da59b 12968 struct drm_device *dev = state->dev;
ed6739ef 12969 struct drm_i915_private *dev_priv = to_i915(dev);
ad421372 12970 struct intel_shared_dpll_config *shared_dpll = NULL;
ed6739ef 12971 struct intel_crtc *intel_crtc;
0a9ab303
ACO		 12972 struct intel_crtc_state *intel_crtc_state;
12973 struct drm_crtc *crtc;
12974 struct drm_crtc_state *crtc_state;
0a9ab303 12975 int i;
ed6739ef
ACO		 12976
12977 if (!dev_priv->display.crtc_compute_clock)
ad421372 12978 return;
ed6739ef 12979
0a9ab303 12980 for_each_crtc_in_state(state, crtc, crtc_state, i) {
ad421372
ML		 12981 int dpll;
12982
0a9ab303 12983 intel_crtc = to_intel_crtc(crtc);
4978cc93 12984 intel_crtc_state = to_intel_crtc_state(crtc_state);
ad421372 12985 dpll = intel_crtc_state->shared_dpll;
0a9ab303 12986
ad421372 12987 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
225da59b
ACO		 12988 continue;
12989
ad421372 12990 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
0a9ab303 12991
ad421372
ML		 12992 if (!shared_dpll)
12993 shared_dpll = intel_atomic_get_shared_dpll_state(state);
ed6739ef 12994
ad421372
ML		 12995 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12996 }
ed6739ef
ACO		 12997}
12998
99d736a2
ML		 12999/*
13000 * This implements the workaround described in the "notes" section of the mode
13001 * set sequence documentation. When going from no pipes or single pipe to
13002 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13003 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13004 */
13005static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13006{
13007 struct drm_crtc_state *crtc_state;
13008 struct intel_crtc *intel_crtc;
13009 struct drm_crtc *crtc;
13010 struct intel_crtc_state *first_crtc_state = NULL;
13011 struct intel_crtc_state *other_crtc_state = NULL;
13012 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13013 int i;
13014
13015 /* look at all crtc's that are going to be enabled in during modeset */
13016 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13017 intel_crtc = to_intel_crtc(crtc);
13018
13019 if (!crtc_state->active || !needs_modeset(crtc_state))
13020 continue;
13021
13022 if (first_crtc_state) {
13023 other_crtc_state = to_intel_crtc_state(crtc_state);
13024 break;
13025 } else {
13026 first_crtc_state = to_intel_crtc_state(crtc_state);
13027 first_pipe = intel_crtc->pipe;
13028 }
13029 }
13030
13031 /* No workaround needed? */
13032 if (!first_crtc_state)
13033 return 0;
13034
13035 /* w/a possibly needed, check how many crtc's are already enabled. */
13036 for_each_intel_crtc(state->dev, intel_crtc) {
13037 struct intel_crtc_state *pipe_config;
13038
13039 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13040 if (IS_ERR(pipe_config))
13041 return PTR_ERR(pipe_config);
13042
13043 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13044
13045 if (!pipe_config->base.active ||
13046 needs_modeset(&pipe_config->base))
13047 continue;
13048
13049 /* 2 or more enabled crtcs means no need for w/a */
13050 if (enabled_pipe != INVALID_PIPE)
13051 return 0;
13052
13053 enabled_pipe = intel_crtc->pipe;
13054 }
13055
13056 if (enabled_pipe != INVALID_PIPE)
13057 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13058 else if (other_crtc_state)
13059 other_crtc_state->hsw_workaround_pipe = first_pipe;
13060
13061 return 0;
13062}
13063
054518dd 13064/* Code that should eventually be part of atomic_check() */
c347a676 13065static int intel_modeset_checks(struct drm_atomic_state *state)
054518dd
ACO		 13066{
13067 struct drm_device *dev = state->dev;
13068 int ret;
13069
b359283a
ML		 13070 if (!check_digital_port_conflicts(state)) {
13071 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13072 return -EINVAL;
13073 }
13074
054518dd
ACO		 13075 /*
13076 * See if the config requires any additional preparation, e.g.
13077 * to adjust global state with pipes off. We need to do this
13078 * here so we can get the modeset_pipe updated config for the new
13079 * mode set on this crtc. For other crtcs we need to use the
13080 * adjusted_mode bits in the crtc directly.
13081 */
b432e5cf
VS		 13082 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev) || IS_BROADWELL(dev)) {
13083 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev))
13084 ret = valleyview_modeset_global_pipes(state);
13085 else
13086 ret = broadwell_modeset_global_pipes(state);
13087
054518dd
ACO		 13088 if (ret)
13089 return ret;
13090 }
13091
ad421372 13092 intel_modeset_clear_plls(state);
054518dd 13093
99d736a2 13094 if (IS_HASWELL(dev))
ad421372 13095 return haswell_mode_set_planes_workaround(state);
99d736a2 13096
ad421372 13097 return 0;
c347a676
ACO		 13098}
13099
13100static int
13101intel_modeset_compute_config(struct drm_atomic_state *state)
13102{
13103 struct drm_crtc *crtc;
13104 struct drm_crtc_state *crtc_state;
13105 int ret, i;
13106
13107 ret = drm_atomic_helper_check_modeset(state->dev, state);
054518dd
ACO		 13108 if (ret)
13109 return ret;
13110
c347a676
ACO		 13111 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13112 if (!crtc_state->enable &&
13113 WARN_ON(crtc_state->active))
13114 crtc_state->active = false;
13115
13116 if (!crtc_state->enable)
13117 continue;
13118
b359283a
ML		 13119 if (!needs_modeset(crtc_state)) {
13120 ret = drm_atomic_add_affected_connectors(state, crtc);
13121 if (ret)
13122 return ret;
13123 }
13124
13125 ret = intel_modeset_pipe_config(crtc,
13126 to_intel_crtc_state(crtc_state));
c347a676
ACO		 13127 if (ret)
13128 return ret;
13129
13130 intel_dump_pipe_config(to_intel_crtc(crtc),
13131 to_intel_crtc_state(crtc_state),
13132 "[modeset]");
13133 }
13134
13135 ret = intel_modeset_checks(state);
13136 if (ret)
13137 return ret;
13138
13139 return drm_atomic_helper_check_planes(state->dev, state);
054518dd
ACO		 13140}
13141
c72d969b 13142static int __intel_set_mode(struct drm_atomic_state *state)
a6778b3c 13143{
c72d969b 13144 struct drm_device *dev = state->dev;
fbee40df 13145 struct drm_i915_private *dev_priv = dev->dev_private;
0a9ab303
ACO		 13146 struct drm_crtc *crtc;
13147 struct drm_crtc_state *crtc_state;
c0c36b94 13148 int ret = 0;
0a9ab303 13149 int i;
a6778b3c 13150
d4afb8cc
ACO		 13151 ret = drm_atomic_helper_prepare_planes(dev, state);
13152 if (ret)
13153 return ret;
13154
1c5e19f8
ML		 13155 drm_atomic_helper_swap_state(dev, state);
13156
0a9ab303 13157 for_each_crtc_in_state(state, crtc, crtc_state, i) {
1c5e19f8 13158 if (!needs_modeset(crtc->state) || !crtc_state->active)
0a9ab303 13159 continue;
460da916 13160
69024de8
ML		 13161 intel_crtc_disable_planes(crtc);
13162 dev_priv->display.crtc_disable(crtc);
b8cecdf5 13163 }
7758a113 13164
ea9d758d
DV		 13165 /* Only after disabling all output pipelines that will be changed can we
13166 * update the the output configuration. */
0a9ab303 13167 intel_modeset_update_state(state);
f6e5b160 13168
a821fc46
ACO		 13169 /* The state has been swaped above, so state actually contains the
13170 * old state now. */
13171
304603f4 13172 modeset_update_crtc_power_domains(state);
47fab737 13173
a6778b3c 13174 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
0a9ab303 13175 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5ac1c4bc
ML		 13176 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13177
53d9f4e9 13178 if (!needs_modeset(crtc->state) || !crtc->state->active)
0a9ab303
ACO		 13179 continue;
13180
13181 update_scanline_offset(to_intel_crtc(crtc));
80715b2f 13182
0a9ab303
ACO		 13183 dev_priv->display.crtc_enable(crtc);
13184 intel_crtc_enable_planes(crtc);
80715b2f 13185 }
a6778b3c 13186
a6778b3c 13187 /* FIXME: add subpixel order */
83a57153 13188
d4afb8cc
ACO		 13189 drm_atomic_helper_cleanup_planes(dev, state);
13190
2bfb4627
ACO		 13191 drm_atomic_state_free(state);
13192
9eb45f22 13193 return 0;
f6e5b160
CW		 13194}
13195
568c634a 13196static int intel_set_mode_checked(struct drm_atomic_state *state)
f30da187 13197{
568c634a 13198 struct drm_device *dev = state->dev;
f30da187
DV		 13199 int ret;
13200
568c634a 13201 ret = __intel_set_mode(state);
f30da187 13202 if (ret == 0)
568c634a 13203 intel_modeset_check_state(dev);
f30da187
DV		 13204
13205 return ret;
13206}
13207
568c634a 13208static int intel_set_mode(struct drm_atomic_state *state)
7f27126e 13209{
568c634a 13210 int ret;
83a57153 13211
568c634a 13212 ret = intel_modeset_compute_config(state);
83a57153 13213 if (ret)
568c634a 13214 return ret;
7f27126e 13215
568c634a 13216 return intel_set_mode_checked(state);
7f27126e
JB		 13217}
13218
c0c36b94
CW		 13219void intel_crtc_restore_mode(struct drm_crtc *crtc)
13220{
83a57153
ACO		 13221 struct drm_device *dev = crtc->dev;
13222 struct drm_atomic_state *state;
4be07317 13223 struct intel_crtc *intel_crtc;
83a57153
ACO		 13224 struct intel_encoder *encoder;
13225 struct intel_connector *connector;
13226 struct drm_connector_state *connector_state;
4be07317 13227 struct intel_crtc_state *crtc_state;
2bfb4627 13228 int ret;
83a57153
ACO		 13229
13230 state = drm_atomic_state_alloc(dev);
13231 if (!state) {
13232 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
13233 crtc->base.id);
13234 return;
13235 }
13236
13237 state->acquire_ctx = dev->mode_config.acquire_ctx;
13238
13239 /* The force restore path in the HW readout code relies on the staged
13240 * config still keeping the user requested config while the actual
13241 * state has been overwritten by the configuration read from HW. We
13242 * need to copy the staged config to the atomic state, otherwise the
13243 * mode set will just reapply the state the HW is already in. */
13244 for_each_intel_encoder(dev, encoder) {
13245 if (&encoder->new_crtc->base != crtc)
13246 continue;
13247
13248 for_each_intel_connector(dev, connector) {
13249 if (connector->new_encoder != encoder)
13250 continue;
13251
13252 connector_state = drm_atomic_get_connector_state(state, &connector->base);
13253 if (IS_ERR(connector_state)) {
13254 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
13255 connector->base.base.id,
13256 connector->base.name,
13257 PTR_ERR(connector_state));
13258 continue;
13259 }
13260
13261 connector_state->crtc = crtc;
13262 connector_state->best_encoder = &encoder->base;
13263 }
13264 }
13265
4be07317
ACO		 13266 for_each_intel_crtc(dev, intel_crtc) {
13267 if (intel_crtc->new_enabled == intel_crtc->base.enabled)
13268 continue;
13269
13270 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
13271 if (IS_ERR(crtc_state)) {
13272 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
13273 intel_crtc->base.base.id,
13274 PTR_ERR(crtc_state));
13275 continue;
13276 }
13277
49d6fa21
ML		 13278 crtc_state->base.active = crtc_state->base.enable =
13279 intel_crtc->new_enabled;
8c7b5ccb
ACO		 13280
13281 if (&intel_crtc->base == crtc)
13282 drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
4be07317
ACO		 13283 }
13284
d3a40d1b
ACO		 13285 intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
13286 crtc->primary->fb, crtc->x, crtc->y);
13287
568c634a 13288 ret = intel_set_mode(state);
2bfb4627
ACO		 13289 if (ret)
13290 drm_atomic_state_free(state);
c0c36b94
CW		 13291}
13292
25c5b266
DV		 13293#undef for_each_intel_crtc_masked
13294
b7885264
ACO		 13295static bool intel_connector_in_mode_set(struct intel_connector *connector,
13296 struct drm_mode_set *set)
13297{
13298 int ro;
13299
13300 for (ro = 0; ro < set->num_connectors; ro++)
13301 if (set->connectors[ro] == &connector->base)
13302 return true;
13303
13304 return false;
13305}
13306
2e431051 13307static int
9a935856
DV		 13308intel_modeset_stage_output_state(struct drm_device *dev,
13309 struct drm_mode_set *set,
944b0c76 13310 struct drm_atomic_state *state)
50f56119 13311{
9a935856 13312 struct intel_connector *connector;
d5432a9d 13313 struct drm_connector *drm_connector;
944b0c76 13314 struct drm_connector_state *connector_state;
d5432a9d
ACO		 13315 struct drm_crtc *crtc;
13316 struct drm_crtc_state *crtc_state;
13317 int i, ret;
50f56119 13318
9abdda74 13319 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 13320 * of connectors. For paranoia, double-check this. */
13321 WARN_ON(!set->fb && (set->num_connectors != 0));
13322 WARN_ON(set->fb && (set->num_connectors == 0));
13323
3a3371ff 13324 for_each_intel_connector(dev, connector) {
b7885264
ACO		 13325 bool in_mode_set = intel_connector_in_mode_set(connector, set);
13326
d5432a9d
ACO		 13327 if (!in_mode_set && connector->base.state->crtc != set->crtc)
13328 continue;
13329
13330 connector_state =
13331 drm_atomic_get_connector_state(state, &connector->base);
13332 if (IS_ERR(connector_state))
13333 return PTR_ERR(connector_state);
13334
b7885264
ACO		 13335 if (in_mode_set) {
13336 int pipe = to_intel_crtc(set->crtc)->pipe;
d5432a9d
ACO		 13337 connector_state->best_encoder =
13338 &intel_find_encoder(connector, pipe)->base;
50f56119
DV		 13339 }
13340
d5432a9d 13341 if (connector->base.state->crtc != set->crtc)
b7885264
ACO		 13342 continue;
13343
9a935856
DV		 13344 /* If we disable the crtc, disable all its connectors. Also, if
13345 * the connector is on the changing crtc but not on the new
13346 * connector list, disable it. */
b7885264 13347 if (!set->fb || !in_mode_set) {
d5432a9d 13348 connector_state->best_encoder = NULL;
9a935856
DV		 13349
13350 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
13351 connector->base.base.id,
c23cc417 13352 connector->base.name);
9a935856 13353 }
50f56119 13354 }
9a935856 13355 /* connector->new_encoder is now updated for all connectors. */
50f56119 13356
d5432a9d
ACO		 13357 for_each_connector_in_state(state, drm_connector, connector_state, i) {
13358 connector = to_intel_connector(drm_connector);
13359
13360 if (!connector_state->best_encoder) {
13361 ret = drm_atomic_set_crtc_for_connector(connector_state,
13362 NULL);
13363 if (ret)
13364 return ret;
7668851f 13365
50f56119 13366 continue;
d5432a9d 13367 }
50f56119 13368
d5432a9d
ACO		 13369 if (intel_connector_in_mode_set(connector, set)) {
13370 struct drm_crtc *crtc = connector->base.state->crtc;
13371
13372 /* If this connector was in a previous crtc, add it
13373 * to the state. We might need to disable it. */
13374 if (crtc) {
13375 crtc_state =
13376 drm_atomic_get_crtc_state(state, crtc);
13377 if (IS_ERR(crtc_state))
13378 return PTR_ERR(crtc_state);
13379 }
13380
13381 ret = drm_atomic_set_crtc_for_connector(connector_state,
13382 set->crtc);
13383 if (ret)
13384 return ret;
13385 }
50f56119
DV		 13386
13387 /* Make sure the new CRTC will work with the encoder */
d5432a9d
ACO		 13388 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
13389 connector_state->crtc)) {
5e2b584e 13390 return -EINVAL;
50f56119 13391 }
944b0c76 13392
9a935856
DV		 13393 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
13394 connector->base.base.id,
c23cc417 13395 connector->base.name,
d5432a9d 13396 connector_state->crtc->base.id);
944b0c76 13397
d5432a9d
ACO		 13398 if (connector_state->best_encoder != &connector->encoder->base)
13399 connector->encoder =
13400 to_intel_encoder(connector_state->best_encoder);
0e32b39c 13401 }
7668851f 13402
d5432a9d 13403 for_each_crtc_in_state(state, crtc, crtc_state, i) {
49d6fa21
ML		 13404 bool has_connectors;
13405
d5432a9d
ACO		 13406 ret = drm_atomic_add_affected_connectors(state, crtc);
13407 if (ret)
13408 return ret;
4be07317 13409
49d6fa21
ML		 13410 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
13411 if (has_connectors != crtc_state->enable)
13412 crtc_state->enable =
13413 crtc_state->active = has_connectors;
7668851f
VS		 13414 }
13415
8c7b5ccb
ACO		 13416 ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
13417 set->fb, set->x, set->y);
13418 if (ret)
13419 return ret;
13420
13421 crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
13422 if (IS_ERR(crtc_state))
13423 return PTR_ERR(crtc_state);
13424
ce52299c
MR		 13425 ret = drm_atomic_set_mode_for_crtc(crtc_state, set->mode);
13426 if (ret)
13427 return ret;
8c7b5ccb
ACO		 13428
13429 if (set->num_connectors)
13430 crtc_state->active = true;
13431
2e431051
DV		 13432 return 0;
13433}
13434
13435static int intel_crtc_set_config(struct drm_mode_set *set)
13436{
13437 struct drm_device *dev;
83a57153 13438 struct drm_atomic_state *state = NULL;
2e431051 13439 int ret;
2e431051 13440
8d3e375e
DV		 13441 BUG_ON(!set);
13442 BUG_ON(!set->crtc);
13443 BUG_ON(!set->crtc->helper_private);
2e431051 13444
7e53f3a4
DV		 13445 /* Enforce sane interface api - has been abused by the fb helper. */
13446 BUG_ON(!set->mode && set->fb);
13447 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 13448
2e431051
DV		 13449 if (set->fb) {
13450 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
13451 set->crtc->base.id, set->fb->base.id,
13452 (int)set->num_connectors, set->x, set->y);
13453 } else {
13454 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 13455 }
13456
13457 dev = set->crtc->dev;
13458
83a57153 13459 state = drm_atomic_state_alloc(dev);
7cbf41d6
ACO		 13460 if (!state)
13461 return -ENOMEM;
83a57153
ACO		 13462
13463 state->acquire_ctx = dev->mode_config.acquire_ctx;
13464
462a425a 13465 ret = intel_modeset_stage_output_state(dev, set, state);
2e431051 13466 if (ret)
7cbf41d6 13467 goto out;
2e431051 13468
568c634a
ACO		 13469 ret = intel_modeset_compute_config(state);
13470 if (ret)
7cbf41d6 13471 goto out;
50f52756 13472
1f9954d0
JB		 13473 intel_update_pipe_size(to_intel_crtc(set->crtc));
13474
568c634a 13475 ret = intel_set_mode_checked(state);
2d05eae1 13476 if (ret) {
bf67dfeb
DV		 13477 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
13478 set->crtc->base.id, ret);
2d05eae1 13479 }
50f56119 13480
7cbf41d6 13481out:
2bfb4627
ACO		 13482 if (ret)
13483 drm_atomic_state_free(state);
50f56119
DV		 13484 return ret;
13485}
f6e5b160
CW		 13486
13487static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 13488 .gamma_set = intel_crtc_gamma_set,
50f56119 13489 .set_config = intel_crtc_set_config,
f6e5b160
CW		 13490 .destroy = intel_crtc_destroy,
13491 .page_flip = intel_crtc_page_flip,
1356837e
MR		 13492 .atomic_duplicate_state = intel_crtc_duplicate_state,
13493 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 13494};
13495
5358901f
DV		 13496static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13497 struct intel_shared_dpll *pll,
13498 struct intel_dpll_hw_state *hw_state)
ee7b9f93 13499{
5358901f 13500 uint32_t val;
ee7b9f93 13501
f458ebbc 13502 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 13503 return false;
13504
5358901f 13505 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 13506 hw_state->dpll = val;
13507 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13508 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 13509
13510 return val & DPLL_VCO_ENABLE;
13511}
13512
15bdd4cf
DV		 13513static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13514 struct intel_shared_dpll *pll)
13515{
3e369b76
ACO		 13516 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13517 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 13518}
13519
e7b903d2
DV		 13520static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13521 struct intel_shared_dpll *pll)
13522{
e7b903d2 13523 /* PCH refclock must be enabled first */
89eff4be 13524 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 13525
3e369b76 13526 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 13527
13528 /* Wait for the clocks to stabilize. */
13529 POSTING_READ(PCH_DPLL(pll->id));
13530 udelay(150);
13531
13532 /* The pixel multiplier can only be updated once the
13533 * DPLL is enabled and the clocks are stable.
13534 *
13535 * So write it again.
13536 */
3e369b76 13537 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 13538 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13539 udelay(200);
13540}
13541
13542static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13543 struct intel_shared_dpll *pll)
13544{
13545 struct drm_device *dev = dev_priv->dev;
13546 struct intel_crtc *crtc;
e7b903d2
DV		 13547
13548 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 13549 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 13550 if (intel_crtc_to_shared_dpll(crtc) == pll)
13551 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 13552 }
13553
15bdd4cf
DV		 13554 I915_WRITE(PCH_DPLL(pll->id), 0);
13555 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13556 udelay(200);
13557}
13558
46edb027
DV		 13559static char *ibx_pch_dpll_names[] = {
13560 "PCH DPLL A",
13561 "PCH DPLL B",
13562};
13563
7c74ade1 13564static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 13565{
e7b903d2 13566 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 13567 int i;
13568
7c74ade1 13569 dev_priv->num_shared_dpll = 2;
ee7b9f93 13570
e72f9fbf 13571 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 13572 dev_priv->shared_dplls[i].id = i;
13573 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 13574 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 13575 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13576 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 13577 dev_priv->shared_dplls[i].get_hw_state =
13578 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 13579 }
13580}
13581
7c74ade1
DV		 13582static void intel_shared_dpll_init(struct drm_device *dev)
13583{
e7b903d2 13584 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 13585
b6283055
VS		 13586 intel_update_cdclk(dev);
13587
9cd86933
DV		 13588 if (HAS_DDI(dev))
13589 intel_ddi_pll_init(dev);
13590 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 13591 ibx_pch_dpll_init(dev);
13592 else
13593 dev_priv->num_shared_dpll = 0;
13594
13595 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 13596}
13597
6beb8c23
MR		 13598/**
13599 * intel_prepare_plane_fb - Prepare fb for usage on plane
13600 * @plane: drm plane to prepare for
13601 * @fb: framebuffer to prepare for presentation
13602 *
13603 * Prepares a framebuffer for usage on a display plane. Generally this
13604 * involves pinning the underlying object and updating the frontbuffer tracking
13605 * bits. Some older platforms need special physical address handling for
13606 * cursor planes.
13607 *
13608 * Returns 0 on success, negative error code on failure.
13609 */
13610int
13611intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13612 struct drm_framebuffer *fb,
13613 const struct drm_plane_state *new_state)
465c120c
MR		 13614{
13615 struct drm_device *dev = plane->dev;
6beb8c23
MR		 13616 struct intel_plane *intel_plane = to_intel_plane(plane);
13617 enum pipe pipe = intel_plane->pipe;
13618 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13619 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13620 unsigned frontbuffer_bits = 0;
13621 int ret = 0;
465c120c 13622
ea2c67bb 13623 if (!obj)
465c120c
MR		 13624 return 0;
13625
6beb8c23
MR		 13626 switch (plane->type) {
13627 case DRM_PLANE_TYPE_PRIMARY:
13628 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
13629 break;
13630 case DRM_PLANE_TYPE_CURSOR:
13631 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
13632 break;
13633 case DRM_PLANE_TYPE_OVERLAY:
13634 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
13635 break;
13636 }
465c120c 13637
6beb8c23 13638 mutex_lock(&dev->struct_mutex);
465c120c 13639
6beb8c23
MR		 13640 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13641 INTEL_INFO(dev)->cursor_needs_physical) {
13642 int align = IS_I830(dev) ? 16 * 1024 : 256;
13643 ret = i915_gem_object_attach_phys(obj, align);
13644 if (ret)
13645 DRM_DEBUG_KMS("failed to attach phys object\n");
13646 } else {
82bc3b2d 13647 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
6beb8c23 13648 }
465c120c 13649
6beb8c23
MR		 13650 if (ret == 0)
13651 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
fdd508a6 13652
4c34574f 13653 mutex_unlock(&dev->struct_mutex);
465c120c 13654
6beb8c23
MR		 13655 return ret;
13656}
13657
38f3ce3a
MR		 13658/**
13659 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13660 * @plane: drm plane to clean up for
13661 * @fb: old framebuffer that was on plane
13662 *
13663 * Cleans up a framebuffer that has just been removed from a plane.
13664 */
13665void
13666intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13667 struct drm_framebuffer *fb,
13668 const struct drm_plane_state *old_state)
38f3ce3a
MR		 13669{
13670 struct drm_device *dev = plane->dev;
13671 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13672
13673 if (WARN_ON(!obj))
13674 return;
13675
13676 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13677 !INTEL_INFO(dev)->cursor_needs_physical) {
13678 mutex_lock(&dev->struct_mutex);
82bc3b2d 13679 intel_unpin_fb_obj(fb, old_state);
38f3ce3a
MR		 13680 mutex_unlock(&dev->struct_mutex);
13681 }
465c120c
MR		 13682}
13683
6156a456
CK		 13684int
13685skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13686{
13687 int max_scale;
13688 struct drm_device *dev;
13689 struct drm_i915_private *dev_priv;
13690 int crtc_clock, cdclk;
13691
13692 if (!intel_crtc || !crtc_state)
13693 return DRM_PLANE_HELPER_NO_SCALING;
13694
13695 dev = intel_crtc->base.dev;
13696 dev_priv = dev->dev_private;
13697 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13698 cdclk = dev_priv->display.get_display_clock_speed(dev);
13699
13700 if (!crtc_clock || !cdclk)
13701 return DRM_PLANE_HELPER_NO_SCALING;
13702
13703 /*
13704 * skl max scale is lower of:
13705 * close to 3 but not 3, -1 is for that purpose
13706 * or
13707 * cdclk/crtc_clock
13708 */
13709 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13710
13711 return max_scale;
13712}
13713
465c120c 13714static int
3c692a41 13715intel_check_primary_plane(struct drm_plane *plane,
061e4b8d 13716 struct intel_crtc_state *crtc_state,
3c692a41
GP		 13717 struct intel_plane_state *state)
13718{
2b875c22
MR		 13719 struct drm_crtc *crtc = state->base.crtc;
13720 struct drm_framebuffer *fb = state->base.fb;
6156a456 13721 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
061e4b8d
ML		 13722 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13723 bool can_position = false;
465c120c 13724
061e4b8d
ML		 13725 /* use scaler when colorkey is not required */
13726 if (INTEL_INFO(plane->dev)->gen >= 9 &&
13727 to_intel_plane(plane)->ckey.flags == I915_SET_COLORKEY_NONE) {
13728 min_scale = 1;
13729 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
d8106366 13730 can_position = true;
6156a456 13731 }
d8106366 13732
061e4b8d
ML		 13733 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13734 &state->dst, &state->clip,
da20eabd
ML		 13735 min_scale, max_scale,
13736 can_position, true,
13737 &state->visible);
14af293f
GP		 13738}
13739
13740static void
13741intel_commit_primary_plane(struct drm_plane *plane,
13742 struct intel_plane_state *state)
13743{
2b875c22
MR		 13744 struct drm_crtc *crtc = state->base.crtc;
13745 struct drm_framebuffer *fb = state->base.fb;
13746 struct drm_device *dev = plane->dev;
14af293f 13747 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 13748 struct intel_crtc *intel_crtc;
14af293f
GP		 13749 struct drm_rect *src = &state->src;
13750
ea2c67bb
MR		 13751 crtc = crtc ? crtc : plane->crtc;
13752 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR		 13753
13754 plane->fb = fb;
9dc806fc
MR		 13755 crtc->x = src->x1 >> 16;
13756 crtc->y = src->y1 >> 16;
ccc759dc 13757
302d19ac
ML		 13758 if (!intel_crtc->active)
13759 return;
465c120c 13760
302d19ac
ML		 13761 if (state->visible)
13762 /* FIXME: kill this fastboot hack */
13763 intel_update_pipe_size(intel_crtc);
13764
13765 dev_priv->display.update_primary_plane(crtc, fb, crtc->x, crtc->y);
465c120c
MR		 13766}
13767
a8ad0d8e
ML		 13768static void
13769intel_disable_primary_plane(struct drm_plane *plane,
7fabf5ef 13770 struct drm_crtc *crtc)
a8ad0d8e
ML		 13771{
13772 struct drm_device *dev = plane->dev;
13773 struct drm_i915_private *dev_priv = dev->dev_private;
13774
a8ad0d8e
ML		 13775 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13776}
13777
32b7eeec 13778static void intel_begin_crtc_commit(struct drm_crtc *crtc)
3c692a41 13779{
32b7eeec 13780 struct drm_device *dev = crtc->dev;
140fd38d 13781 struct drm_i915_private *dev_priv = dev->dev_private;
3c692a41 13782 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5c2db188 13783 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
ea2c67bb
MR		 13784 struct intel_plane *intel_plane;
13785 struct drm_plane *p;
13786 unsigned fb_bits = 0;
13787
13788 /* Track fb's for any planes being disabled */
13789 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
13790 intel_plane = to_intel_plane(p);
13791
13792 if (intel_crtc->atomic.disabled_planes &
13793 (1 << drm_plane_index(p))) {
13794 switch (p->type) {
13795 case DRM_PLANE_TYPE_PRIMARY:
13796 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
13797 break;
13798 case DRM_PLANE_TYPE_CURSOR:
13799 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
13800 break;
13801 case DRM_PLANE_TYPE_OVERLAY:
13802 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
13803 break;
13804 }
3c692a41 13805
ea2c67bb
MR		 13806 mutex_lock(&dev->struct_mutex);
13807 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
13808 mutex_unlock(&dev->struct_mutex);
13809 }
13810 }
3c692a41 13811
32b7eeec
MR		 13812 if (intel_crtc->atomic.wait_for_flips)
13813 intel_crtc_wait_for_pending_flips(crtc);
3c692a41 13814
32b7eeec
MR		 13815 if (intel_crtc->atomic.disable_fbc)
13816 intel_fbc_disable(dev);
3c692a41 13817
32b7eeec
MR		 13818 if (intel_crtc->atomic.pre_disable_primary)
13819 intel_pre_disable_primary(crtc);
3c692a41 13820
32b7eeec
MR		 13821 if (intel_crtc->atomic.update_wm)
13822 intel_update_watermarks(crtc);
3c692a41 13823
32b7eeec 13824 intel_runtime_pm_get(dev_priv);
3c692a41 13825
c34c9ee4 13826 /* Perform vblank evasion around commit operation */
5c2db188 13827 if (crtc_state->active && !needs_modeset(crtc_state))
c34c9ee4
MR		 13828 intel_crtc->atomic.evade =
13829 intel_pipe_update_start(intel_crtc,
13830 &intel_crtc->atomic.start_vbl_count);
0583236e
ML		 13831
13832 if (!needs_modeset(crtc->state) && INTEL_INFO(dev)->gen >= 9)
13833 skl_detach_scalers(intel_crtc);
32b7eeec
MR		 13834}
13835
13836static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13837{
13838 struct drm_device *dev = crtc->dev;
13839 struct drm_i915_private *dev_priv = dev->dev_private;
13840 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13841 struct drm_plane *p;
13842
c34c9ee4
MR		 13843 if (intel_crtc->atomic.evade)
13844 intel_pipe_update_end(intel_crtc,
13845 intel_crtc->atomic.start_vbl_count);
3c692a41 13846
140fd38d 13847 intel_runtime_pm_put(dev_priv);
3c692a41 13848
8a8f7f44 13849 if (intel_crtc->atomic.wait_vblank && intel_crtc->active)
32b7eeec
MR		 13850 intel_wait_for_vblank(dev, intel_crtc->pipe);
13851
13852 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
13853
13854 if (intel_crtc->atomic.update_fbc) {
ccc759dc 13855 mutex_lock(&dev->struct_mutex);
7ff0ebcc 13856 intel_fbc_update(dev);
ccc759dc 13857 mutex_unlock(&dev->struct_mutex);
38f3ce3a 13858 }
3c692a41 13859
32b7eeec
MR		 13860 if (intel_crtc->atomic.post_enable_primary)
13861 intel_post_enable_primary(crtc);
3c692a41 13862
32b7eeec
MR		 13863 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
13864 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
13865 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
13866 false, false);
13867
13868 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
3c692a41
GP		 13869}
13870
cf4c7c12 13871/**
4a3b8769
MR		 13872 * intel_plane_destroy - destroy a plane
13873 * @plane: plane to destroy
cf4c7c12 13874 *
4a3b8769
MR		 13875 * Common destruction function for all types of planes (primary, cursor,
13876 * sprite).
cf4c7c12 13877 */
4a3b8769 13878void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 13879{
13880 struct intel_plane *intel_plane = to_intel_plane(plane);
13881 drm_plane_cleanup(plane);
13882 kfree(intel_plane);
13883}
13884
65a3fea0 13885const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR		 13886 .update_plane = drm_atomic_helper_update_plane,
13887 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13888 .destroy = intel_plane_destroy,
c196e1d6 13889 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 13890 .atomic_get_property = intel_plane_atomic_get_property,
13891 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 13892 .atomic_duplicate_state = intel_plane_duplicate_state,
13893 .atomic_destroy_state = intel_plane_destroy_state,
13894
465c120c
MR		 13895};
13896
13897static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13898 int pipe)
13899{
13900 struct intel_plane *primary;
8e7d688b 13901 struct intel_plane_state *state;
465c120c
MR		 13902 const uint32_t *intel_primary_formats;
13903 int num_formats;
13904
13905 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13906 if (primary == NULL)
13907 return NULL;
13908
8e7d688b
MR		 13909 state = intel_create_plane_state(&primary->base);
13910 if (!state) {
ea2c67bb
MR		 13911 kfree(primary);
13912 return NULL;
13913 }
8e7d688b 13914 primary->base.state = &state->base;
ea2c67bb 13915
465c120c
MR		 13916 primary->can_scale = false;
13917 primary->max_downscale = 1;
6156a456
CK		 13918 if (INTEL_INFO(dev)->gen >= 9) {
13919 primary->can_scale = true;
af99ceda 13920 state->scaler_id = -1;
6156a456 13921 }
465c120c
MR		 13922 primary->pipe = pipe;
13923 primary->plane = pipe;
c59cb179
MR		 13924 primary->check_plane = intel_check_primary_plane;
13925 primary->commit_plane = intel_commit_primary_plane;
a8ad0d8e 13926 primary->disable_plane = intel_disable_primary_plane;
08e221fb 13927 primary->ckey.flags = I915_SET_COLORKEY_NONE;
465c120c
MR		 13928 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13929 primary->plane = !pipe;
13930
6c0fd451
DL		 13931 if (INTEL_INFO(dev)->gen >= 9) {
13932 intel_primary_formats = skl_primary_formats;
13933 num_formats = ARRAY_SIZE(skl_primary_formats);
13934 } else if (INTEL_INFO(dev)->gen >= 4) {
568db4f2
DL		 13935 intel_primary_formats = i965_primary_formats;
13936 num_formats = ARRAY_SIZE(i965_primary_formats);
6c0fd451
DL		 13937 } else {
13938 intel_primary_formats = i8xx_primary_formats;
13939 num_formats = ARRAY_SIZE(i8xx_primary_formats);
465c120c
MR		 13940 }
13941
13942 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 13943 &intel_plane_funcs,
465c120c
MR		 13944 intel_primary_formats, num_formats,
13945 DRM_PLANE_TYPE_PRIMARY);
48404c1e 13946
3b7a5119
SJ		 13947 if (INTEL_INFO(dev)->gen >= 4)
13948 intel_create_rotation_property(dev, primary);
48404c1e 13949
ea2c67bb
MR		 13950 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13951
465c120c
MR		 13952 return &primary->base;
13953}
13954
3b7a5119
SJ		 13955void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13956{
13957 if (!dev->mode_config.rotation_property) {
13958 unsigned long flags = BIT(DRM_ROTATE_0) |
13959 BIT(DRM_ROTATE_180);
13960
13961 if (INTEL_INFO(dev)->gen >= 9)
13962 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13963
13964 dev->mode_config.rotation_property =
13965 drm_mode_create_rotation_property(dev, flags);
13966 }
13967 if (dev->mode_config.rotation_property)
13968 drm_object_attach_property(&plane->base.base,
13969 dev->mode_config.rotation_property,
13970 plane->base.state->rotation);
13971}
13972
3d7d6510 13973static int
852e787c 13974intel_check_cursor_plane(struct drm_plane *plane,
061e4b8d 13975 struct intel_crtc_state *crtc_state,
852e787c 13976 struct intel_plane_state *state)
3d7d6510 13977{
061e4b8d 13978 struct drm_crtc *crtc = crtc_state->base.crtc;
2b875c22 13979 struct drm_framebuffer *fb = state->base.fb;
757f9a3e 13980 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
757f9a3e
GP		 13981 unsigned stride;
13982 int ret;
3d7d6510 13983
061e4b8d
ML		 13984 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13985 &state->dst, &state->clip,
3d7d6510
MR		 13986 DRM_PLANE_HELPER_NO_SCALING,
13987 DRM_PLANE_HELPER_NO_SCALING,
852e787c 13988 true, true, &state->visible);
757f9a3e
GP		 13989 if (ret)
13990 return ret;
13991
757f9a3e
GP		 13992 /* if we want to turn off the cursor ignore width and height */
13993 if (!obj)
da20eabd 13994 return 0;
757f9a3e 13995
757f9a3e 13996 /* Check for which cursor types we support */
061e4b8d 13997 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
ea2c67bb
MR		 13998 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13999 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 14000 return -EINVAL;
14001 }
14002
ea2c67bb
MR		 14003 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14004 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 14005 DRM_DEBUG_KMS("buffer is too small\n");
14006 return -ENOMEM;
14007 }
14008
3a656b54 14009 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e 14010 DRM_DEBUG_KMS("cursor cannot be tiled\n");
da20eabd 14011 return -EINVAL;
32b7eeec
MR		 14012 }
14013
da20eabd 14014 return 0;
852e787c 14015}
3d7d6510 14016
a8ad0d8e
ML		 14017static void
14018intel_disable_cursor_plane(struct drm_plane *plane,
7fabf5ef 14019 struct drm_crtc *crtc)
a8ad0d8e 14020{
a8ad0d8e
ML		 14021 intel_crtc_update_cursor(crtc, false);
14022}
14023
f4a2cf29 14024static void
852e787c
GP		 14025intel_commit_cursor_plane(struct drm_plane *plane,
14026 struct intel_plane_state *state)
14027{
2b875c22 14028 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 14029 struct drm_device *dev = plane->dev;
14030 struct intel_crtc *intel_crtc;
2b875c22 14031 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 14032 uint32_t addr;
852e787c 14033
ea2c67bb
MR		 14034 crtc = crtc ? crtc : plane->crtc;
14035 intel_crtc = to_intel_crtc(crtc);
14036
2b875c22 14037 plane->fb = state->base.fb;
ea2c67bb
MR		 14038 crtc->cursor_x = state->base.crtc_x;
14039 crtc->cursor_y = state->base.crtc_y;
14040
a912f12f
GP		 14041 if (intel_crtc->cursor_bo == obj)
14042 goto update;
4ed91096 14043
f4a2cf29 14044 if (!obj)
a912f12f 14045 addr = 0;
f4a2cf29 14046 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 14047 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 14048 else
a912f12f 14049 addr = obj->phys_handle->busaddr;
852e787c 14050
a912f12f
GP		 14051 intel_crtc->cursor_addr = addr;
14052 intel_crtc->cursor_bo = obj;
852e787c 14053
302d19ac 14054update:
32b7eeec 14055 if (intel_crtc->active)
a912f12f 14056 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 14057}
14058
3d7d6510
MR		 14059static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14060 int pipe)
14061{
14062 struct intel_plane *cursor;
8e7d688b 14063 struct intel_plane_state *state;
3d7d6510
MR		 14064
14065 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14066 if (cursor == NULL)
14067 return NULL;
14068
8e7d688b
MR		 14069 state = intel_create_plane_state(&cursor->base);
14070 if (!state) {
ea2c67bb
MR		 14071 kfree(cursor);
14072 return NULL;
14073 }
8e7d688b 14074 cursor->base.state = &state->base;
ea2c67bb 14075
3d7d6510
MR		 14076 cursor->can_scale = false;
14077 cursor->max_downscale = 1;
14078 cursor->pipe = pipe;
14079 cursor->plane = pipe;
c59cb179
MR		 14080 cursor->check_plane = intel_check_cursor_plane;
14081 cursor->commit_plane = intel_commit_cursor_plane;
a8ad0d8e 14082 cursor->disable_plane = intel_disable_cursor_plane;
3d7d6510
MR		 14083
14084 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 14085 &intel_plane_funcs,
3d7d6510
MR		 14086 intel_cursor_formats,
14087 ARRAY_SIZE(intel_cursor_formats),
14088 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 14089
14090 if (INTEL_INFO(dev)->gen >= 4) {
14091 if (!dev->mode_config.rotation_property)
14092 dev->mode_config.rotation_property =
14093 drm_mode_create_rotation_property(dev,
14094 BIT(DRM_ROTATE_0) |
14095 BIT(DRM_ROTATE_180));
14096 if (dev->mode_config.rotation_property)
14097 drm_object_attach_property(&cursor->base.base,
14098 dev->mode_config.rotation_property,
8e7d688b 14099 state->base.rotation);
4398ad45
VS		 14100 }
14101
af99ceda
CK		 14102 if (INTEL_INFO(dev)->gen >=9)
14103 state->scaler_id = -1;
14104
ea2c67bb
MR		 14105 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14106
3d7d6510
MR		 14107 return &cursor->base;
14108}
14109
549e2bfb
CK		 14110static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14111 struct intel_crtc_state *crtc_state)
14112{
14113 int i;
14114 struct intel_scaler *intel_scaler;
14115 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14116
14117 for (i = 0; i < intel_crtc->num_scalers; i++) {
14118 intel_scaler = &scaler_state->scalers[i];
14119 intel_scaler->in_use = 0;
549e2bfb
CK		 14120 intel_scaler->mode = PS_SCALER_MODE_DYN;
14121 }
14122
14123 scaler_state->scaler_id = -1;
14124}
14125
b358d0a6 14126static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 14127{
fbee40df 14128 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 14129 struct intel_crtc *intel_crtc;
f5de6e07 14130 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 14131 struct drm_plane *primary = NULL;
14132 struct drm_plane *cursor = NULL;
465c120c 14133 int i, ret;
79e53945 14134
955382f3 14135 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 14136 if (intel_crtc == NULL)
14137 return;
14138
f5de6e07
ACO		 14139 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14140 if (!crtc_state)
14141 goto fail;
550acefd
ACO		 14142 intel_crtc->config = crtc_state;
14143 intel_crtc->base.state = &crtc_state->base;
07878248 14144 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 14145
549e2bfb
CK		 14146 /* initialize shared scalers */
14147 if (INTEL_INFO(dev)->gen >= 9) {
14148 if (pipe == PIPE_C)
14149 intel_crtc->num_scalers = 1;
14150 else
14151 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14152
14153 skl_init_scalers(dev, intel_crtc, crtc_state);
14154 }
14155
465c120c 14156 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 14157 if (!primary)
14158 goto fail;
14159
14160 cursor = intel_cursor_plane_create(dev, pipe);
14161 if (!cursor)
14162 goto fail;
14163
465c120c 14164 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 14165 cursor, &intel_crtc_funcs);
14166 if (ret)
14167 goto fail;
79e53945
JB		 14168
14169 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 14170 for (i = 0; i < 256; i++) {
14171 intel_crtc->lut_r[i] = i;
14172 intel_crtc->lut_g[i] = i;
14173 intel_crtc->lut_b[i] = i;
14174 }
14175
1f1c2e24
VS		 14176 /*
14177 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 14178 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 14179 */
80824003
JB		 14180 intel_crtc->pipe = pipe;
14181 intel_crtc->plane = pipe;
3a77c4c4 14182 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 14183 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 14184 intel_crtc->plane = !pipe;
80824003
JB		 14185 }
14186
4b0e333e
CW		 14187 intel_crtc->cursor_base = ~0;
14188 intel_crtc->cursor_cntl = ~0;
dc41c154 14189 intel_crtc->cursor_size = ~0;
8d7849db 14190
22fd0fab
JB		 14191 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14192 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14193 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14194 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14195
79e53945 14196 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 14197
14198 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 14199 return;
14200
14201fail:
14202 if (primary)
14203 drm_plane_cleanup(primary);
14204 if (cursor)
14205 drm_plane_cleanup(cursor);
f5de6e07 14206 kfree(crtc_state);
3d7d6510 14207 kfree(intel_crtc);
79e53945
JB		 14208}
14209
752aa88a
JB		 14210enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14211{
14212 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 14213 struct drm_device *dev = connector->base.dev;
752aa88a 14214
51fd371b 14215 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 14216
d3babd3f 14217 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 14218 return INVALID_PIPE;
14219
14220 return to_intel_crtc(encoder->crtc)->pipe;
14221}
14222
08d7b3d1 14223int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 14224 struct drm_file *file)
08d7b3d1 14225{
08d7b3d1 14226 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 14227 struct drm_crtc *drmmode_crtc;
c05422d5 14228 struct intel_crtc *crtc;
08d7b3d1 14229
7707e653 14230 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 14231
7707e653 14232 if (!drmmode_crtc) {
08d7b3d1 14233 DRM_ERROR("no such CRTC id\n");
3f2c2057 14234 return -ENOENT;
08d7b3d1
CW		 14235 }
14236
7707e653 14237 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 14238 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 14239
c05422d5 14240 return 0;
08d7b3d1
CW		 14241}
14242
66a9278e 14243static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 14244{
66a9278e
DV		 14245 struct drm_device *dev = encoder->base.dev;
14246 struct intel_encoder *source_encoder;
79e53945 14247 int index_mask = 0;
79e53945
JB		 14248 int entry = 0;
14249
b2784e15 14250 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 14251 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 14252 index_mask |= (1 << entry);
14253
79e53945
JB		 14254 entry++;
14255 }
4ef69c7a 14256
79e53945
JB		 14257 return index_mask;
14258}
14259
4d302442
CW		 14260static bool has_edp_a(struct drm_device *dev)
14261{
14262 struct drm_i915_private *dev_priv = dev->dev_private;
14263
14264 if (!IS_MOBILE(dev))
14265 return false;
14266
14267 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14268 return false;
14269
e3589908 14270 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 14271 return false;
14272
14273 return true;
14274}
14275
84b4e042
JB		 14276static bool intel_crt_present(struct drm_device *dev)
14277{
14278 struct drm_i915_private *dev_priv = dev->dev_private;
14279
884497ed
DL		 14280 if (INTEL_INFO(dev)->gen >= 9)
14281 return false;
14282
cf404ce4 14283 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 14284 return false;
14285
14286 if (IS_CHERRYVIEW(dev))
14287 return false;
14288
14289 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14290 return false;
14291
14292 return true;
14293}
14294
79e53945
JB		 14295static void intel_setup_outputs(struct drm_device *dev)
14296{
725e30ad 14297 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 14298 struct intel_encoder *encoder;
cb0953d7 14299 bool dpd_is_edp = false;
79e53945 14300
c9093354 14301 intel_lvds_init(dev);
79e53945 14302
84b4e042 14303 if (intel_crt_present(dev))
79935fca 14304 intel_crt_init(dev);
cb0953d7 14305
c776eb2e
VK		 14306 if (IS_BROXTON(dev)) {
14307 /*
14308 * FIXME: Broxton doesn't support port detection via the
14309 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14310 * detect the ports.
14311 */
14312 intel_ddi_init(dev, PORT_A);
14313 intel_ddi_init(dev, PORT_B);
14314 intel_ddi_init(dev, PORT_C);
14315 } else if (HAS_DDI(dev)) {
0e72a5b5
ED		 14316 int found;
14317
de31facd
JB		 14318 /*
14319 * Haswell uses DDI functions to detect digital outputs.
14320 * On SKL pre-D0 the strap isn't connected, so we assume
14321 * it's there.
14322 */
0e72a5b5 14323 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
de31facd
JB		 14324 /* WaIgnoreDDIAStrap: skl */
14325 if (found ||
14326 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
0e72a5b5
ED		 14327 intel_ddi_init(dev, PORT_A);
14328
14329 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14330 * register */
14331 found = I915_READ(SFUSE_STRAP);
14332
14333 if (found & SFUSE_STRAP_DDIB_DETECTED)
14334 intel_ddi_init(dev, PORT_B);
14335 if (found & SFUSE_STRAP_DDIC_DETECTED)
14336 intel_ddi_init(dev, PORT_C);
14337 if (found & SFUSE_STRAP_DDID_DETECTED)
14338 intel_ddi_init(dev, PORT_D);
14339 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 14340 int found;
5d8a7752 14341 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 14342
14343 if (has_edp_a(dev))
14344 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 14345
dc0fa718 14346 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 14347 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 14348 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 14349 if (!found)
e2debe91 14350 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 14351 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 14352 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 14353 }
14354
dc0fa718 14355 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 14356 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 14357
dc0fa718 14358 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 14359 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 14360
5eb08b69 14361 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 14362 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 14363
270b3042 14364 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 14365 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 14366 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 14367 /*
14368 * The DP_DETECTED bit is the latched state of the DDC
14369 * SDA pin at boot. However since eDP doesn't require DDC
14370 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14371 * eDP ports may have been muxed to an alternate function.
14372 * Thus we can't rely on the DP_DETECTED bit alone to detect
14373 * eDP ports. Consult the VBT as well as DP_DETECTED to
14374 * detect eDP ports.
14375 */
d2182a66
VS		 14376 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14377 !intel_dp_is_edp(dev, PORT_B))
585a94b8
AB		 14378 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14379 PORT_B);
e17ac6db
VS		 14380 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14381 intel_dp_is_edp(dev, PORT_B))
14382 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
585a94b8 14383
d2182a66
VS		 14384 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14385 !intel_dp_is_edp(dev, PORT_C))
6f6005a5
JB		 14386 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14387 PORT_C);
e17ac6db
VS		 14388 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14389 intel_dp_is_edp(dev, PORT_C))
14390 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 14391
9418c1f1 14392 if (IS_CHERRYVIEW(dev)) {
e17ac6db 14393 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
9418c1f1
VS		 14394 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14395 PORT_D);
e17ac6db
VS		 14396 /* eDP not supported on port D, so don't check VBT */
14397 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14398 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
9418c1f1
VS		 14399 }
14400
3cfca973 14401 intel_dsi_init(dev);
103a196f 14402 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 14403 bool found = false;
7d57382e 14404
e2debe91 14405 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14406 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 14407 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 14408 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
14409 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 14410 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 14411 }
27185ae1 14412
e7281eab 14413 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 14414 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 14415 }
13520b05
KH		 14416
14417 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 14418
e2debe91 14419 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14420 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 14421 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 14422 }
27185ae1 14423
e2debe91 14424 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 14425
b01f2c3a
JB		 14426 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
14427 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 14428 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 14429 }
e7281eab 14430 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 14431 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 14432 }
27185ae1 14433
b01f2c3a 14434 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 14435 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 14436 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 14437 } else if (IS_GEN2(dev))
79e53945
JB		 14438 intel_dvo_init(dev);
14439
103a196f 14440 if (SUPPORTS_TV(dev))
79e53945
JB		 14441 intel_tv_init(dev);
14442
0bc12bcb 14443 intel_psr_init(dev);
7c8f8a70 14444
b2784e15 14445 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 14446 encoder->base.possible_crtcs = encoder->crtc_mask;
14447 encoder->base.possible_clones =
66a9278e 14448 intel_encoder_clones(encoder);
79e53945 14449 }
47356eb6 14450
dde86e2d 14451 intel_init_pch_refclk(dev);
270b3042
DV		 14452
14453 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 14454}
14455
14456static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14457{
60a5ca01 14458 struct drm_device *dev = fb->dev;
79e53945 14459 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 14460
ef2d633e 14461 drm_framebuffer_cleanup(fb);
60a5ca01 14462 mutex_lock(&dev->struct_mutex);
ef2d633e 14463 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 14464 drm_gem_object_unreference(&intel_fb->obj->base);
14465 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 14466 kfree(intel_fb);
14467}
14468
14469static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 14470 struct drm_file *file,
79e53945
JB		 14471 unsigned int *handle)
14472{
14473 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 14474 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 14475
05394f39 14476 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 14477}
14478
14479static const struct drm_framebuffer_funcs intel_fb_funcs = {
14480 .destroy = intel_user_framebuffer_destroy,
14481 .create_handle = intel_user_framebuffer_create_handle,
14482};
14483
b321803d
DL		 14484static
14485u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14486 uint32_t pixel_format)
14487{
14488 u32 gen = INTEL_INFO(dev)->gen;
14489
14490 if (gen >= 9) {
14491 /* "The stride in bytes must not exceed the of the size of 8K
14492 * pixels and 32K bytes."
14493 */
14494 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14495 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14496 return 32*1024;
14497 } else if (gen >= 4) {
14498 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14499 return 16*1024;
14500 else
14501 return 32*1024;
14502 } else if (gen >= 3) {
14503 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14504 return 8*1024;
14505 else
14506 return 16*1024;
14507 } else {
14508 /* XXX DSPC is limited to 4k tiled */
14509 return 8*1024;
14510 }
14511}
14512
b5ea642a
DV		 14513static int intel_framebuffer_init(struct drm_device *dev,
14514 struct intel_framebuffer *intel_fb,
14515 struct drm_mode_fb_cmd2 *mode_cmd,
14516 struct drm_i915_gem_object *obj)
79e53945 14517{
6761dd31 14518 unsigned int aligned_height;
79e53945 14519 int ret;
b321803d 14520 u32 pitch_limit, stride_alignment;
79e53945 14521
dd4916c5
DV		 14522 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14523
2a80eada
DV		 14524 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14525 /* Enforce that fb modifier and tiling mode match, but only for
14526 * X-tiled. This is needed for FBC. */
14527 if (!!(obj->tiling_mode == I915_TILING_X) !=
14528 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14529 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14530 return -EINVAL;
14531 }
14532 } else {
14533 if (obj->tiling_mode == I915_TILING_X)
14534 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14535 else if (obj->tiling_mode == I915_TILING_Y) {
14536 DRM_DEBUG("No Y tiling for legacy addfb\n");
14537 return -EINVAL;
14538 }
14539 }
14540
9a8f0a12
TU		 14541 /* Passed in modifier sanity checking. */
14542 switch (mode_cmd->modifier[0]) {
14543 case I915_FORMAT_MOD_Y_TILED:
14544 case I915_FORMAT_MOD_Yf_TILED:
14545 if (INTEL_INFO(dev)->gen < 9) {
14546 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14547 mode_cmd->modifier[0]);
14548 return -EINVAL;
14549 }
14550 case DRM_FORMAT_MOD_NONE:
14551 case I915_FORMAT_MOD_X_TILED:
14552 break;
14553 default:
c0f40428
JB		 14554 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14555 mode_cmd->modifier[0]);
57cd6508 14556 return -EINVAL;
c16ed4be 14557 }
57cd6508 14558
b321803d
DL		 14559 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14560 mode_cmd->pixel_format);
14561 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14562 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14563 mode_cmd->pitches[0], stride_alignment);
57cd6508 14564 return -EINVAL;
c16ed4be 14565 }
57cd6508 14566
b321803d
DL		 14567 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14568 mode_cmd->pixel_format);
a35cdaa0 14569 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 14570 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14571 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 14572 "tiled" : "linear",
a35cdaa0 14573 mode_cmd->pitches[0], pitch_limit);
5d7bd705 14574 return -EINVAL;
c16ed4be 14575 }
5d7bd705 14576
2a80eada 14577 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 14578 mode_cmd->pitches[0] != obj->stride) {
14579 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14580 mode_cmd->pitches[0], obj->stride);
5d7bd705 14581 return -EINVAL;
c16ed4be 14582 }
5d7bd705 14583
57779d06 14584 /* Reject formats not supported by any plane early. */
308e5bcb 14585 switch (mode_cmd->pixel_format) {
57779d06 14586 case DRM_FORMAT_C8:
04b3924d
VS		 14587 case DRM_FORMAT_RGB565:
14588 case DRM_FORMAT_XRGB8888:
14589 case DRM_FORMAT_ARGB8888:
57779d06
VS		 14590 break;
14591 case DRM_FORMAT_XRGB1555:
c16ed4be 14592 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 14593 DRM_DEBUG("unsupported pixel format: %s\n",
14594 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14595 return -EINVAL;
c16ed4be 14596 }
57779d06 14597 break;
57779d06 14598 case DRM_FORMAT_ABGR8888:
6c0fd451
DL		 14599 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14600 DRM_DEBUG("unsupported pixel format: %s\n",
14601 drm_get_format_name(mode_cmd->pixel_format));
14602 return -EINVAL;
14603 }
14604 break;
14605 case DRM_FORMAT_XBGR8888:
04b3924d 14606 case DRM_FORMAT_XRGB2101010:
57779d06 14607 case DRM_FORMAT_XBGR2101010:
c16ed4be 14608 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 14609 DRM_DEBUG("unsupported pixel format: %s\n",
14610 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14611 return -EINVAL;
c16ed4be 14612 }
b5626747 14613 break;
7531208b
DL		 14614 case DRM_FORMAT_ABGR2101010:
14615 if (!IS_VALLEYVIEW(dev)) {
14616 DRM_DEBUG("unsupported pixel format: %s\n",
14617 drm_get_format_name(mode_cmd->pixel_format));
14618 return -EINVAL;
14619 }
14620 break;
04b3924d
VS		 14621 case DRM_FORMAT_YUYV:
14622 case DRM_FORMAT_UYVY:
14623 case DRM_FORMAT_YVYU:
14624 case DRM_FORMAT_VYUY:
c16ed4be 14625 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 14626 DRM_DEBUG("unsupported pixel format: %s\n",
14627 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14628 return -EINVAL;
c16ed4be 14629 }
57cd6508
CW		 14630 break;
14631 default:
4ee62c76
VS		 14632 DRM_DEBUG("unsupported pixel format: %s\n",
14633 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 14634 return -EINVAL;
14635 }
14636
90f9a336
VS		 14637 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14638 if (mode_cmd->offsets[0] != 0)
14639 return -EINVAL;
14640
ec2c981e 14641 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 14642 mode_cmd->pixel_format,
14643 mode_cmd->modifier[0]);
53155c0a
DV		 14644 /* FIXME drm helper for size checks (especially planar formats)? */
14645 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14646 return -EINVAL;
14647
c7d73f6a
DV		 14648 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14649 intel_fb->obj = obj;
80075d49 14650 intel_fb->obj->framebuffer_references++;
c7d73f6a 14651
79e53945
JB		 14652 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14653 if (ret) {
14654 DRM_ERROR("framebuffer init failed %d\n", ret);
14655 return ret;
14656 }
14657
79e53945
JB		 14658 return 0;
14659}
14660
79e53945
JB		 14661static struct drm_framebuffer *
14662intel_user_framebuffer_create(struct drm_device *dev,
14663 struct drm_file *filp,
308e5bcb 14664 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 14665{
05394f39 14666 struct drm_i915_gem_object *obj;
79e53945 14667
308e5bcb
JB		 14668 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14669 mode_cmd->handles[0]));
c8725226 14670 if (&obj->base == NULL)
cce13ff7 14671 return ERR_PTR(-ENOENT);
79e53945 14672
d2dff872 14673 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 14674}
14675
4520f53a 14676#ifndef CONFIG_DRM_I915_FBDEV
0632fef6 14677static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 14678{
14679}
14680#endif
14681
79e53945 14682static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 14683 .fb_create = intel_user_framebuffer_create,
0632fef6 14684 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 14685 .atomic_check = intel_atomic_check,
14686 .atomic_commit = intel_atomic_commit,
de419ab6
ML		 14687 .atomic_state_alloc = intel_atomic_state_alloc,
14688 .atomic_state_clear = intel_atomic_state_clear,
79e53945
JB		 14689};
14690
e70236a8
JB		 14691/* Set up chip specific display functions */
14692static void intel_init_display(struct drm_device *dev)
14693{
14694 struct drm_i915_private *dev_priv = dev->dev_private;
14695
ee9300bb
DV		 14696 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14697 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 14698 else if (IS_CHERRYVIEW(dev))
14699 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 14700 else if (IS_VALLEYVIEW(dev))
14701 dev_priv->display.find_dpll = vlv_find_best_dpll;
14702 else if (IS_PINEVIEW(dev))
14703 dev_priv->display.find_dpll = pnv_find_best_dpll;
14704 else
14705 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14706
bc8d7dff
DL		 14707 if (INTEL_INFO(dev)->gen >= 9) {
14708 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14709 dev_priv->display.get_initial_plane_config =
14710 skylake_get_initial_plane_config;
bc8d7dff
DL		 14711 dev_priv->display.crtc_compute_clock =
14712 haswell_crtc_compute_clock;
14713 dev_priv->display.crtc_enable = haswell_crtc_enable;
14714 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14715 dev_priv->display.update_primary_plane =
14716 skylake_update_primary_plane;
14717 } else if (HAS_DDI(dev)) {
0e8ffe1b 14718 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14719 dev_priv->display.get_initial_plane_config =
14720 ironlake_get_initial_plane_config;
797d0259
ACO		 14721 dev_priv->display.crtc_compute_clock =
14722 haswell_crtc_compute_clock;
4f771f10
PZ		 14723 dev_priv->display.crtc_enable = haswell_crtc_enable;
14724 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14725 dev_priv->display.update_primary_plane =
14726 ironlake_update_primary_plane;
09b4ddf9 14727 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 14728 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 14729 dev_priv->display.get_initial_plane_config =
14730 ironlake_get_initial_plane_config;
3fb37703
ACO		 14731 dev_priv->display.crtc_compute_clock =
14732 ironlake_crtc_compute_clock;
76e5a89c
DV		 14733 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14734 dev_priv->display.crtc_disable = ironlake_crtc_disable;
262ca2b0
MR		 14735 dev_priv->display.update_primary_plane =
14736 ironlake_update_primary_plane;
89b667f8
JB		 14737 } else if (IS_VALLEYVIEW(dev)) {
14738 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14739 dev_priv->display.get_initial_plane_config =
14740 i9xx_get_initial_plane_config;
d6dfee7a 14741 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 14742 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14743 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14744 dev_priv->display.update_primary_plane =
14745 i9xx_update_primary_plane;
f564048e 14746 } else {
0e8ffe1b 14747 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14748 dev_priv->display.get_initial_plane_config =
14749 i9xx_get_initial_plane_config;
d6dfee7a 14750 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 14751 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14752 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14753 dev_priv->display.update_primary_plane =
14754 i9xx_update_primary_plane;
f564048e 14755 }
e70236a8 14756
e70236a8 14757 /* Returns the core display clock speed */
1652d19e
VS		 14758 if (IS_SKYLAKE(dev))
14759 dev_priv->display.get_display_clock_speed =
14760 skylake_get_display_clock_speed;
14761 else if (IS_BROADWELL(dev))
14762 dev_priv->display.get_display_clock_speed =
14763 broadwell_get_display_clock_speed;
14764 else if (IS_HASWELL(dev))
14765 dev_priv->display.get_display_clock_speed =
14766 haswell_get_display_clock_speed;
14767 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB		 14768 dev_priv->display.get_display_clock_speed =
14769 valleyview_get_display_clock_speed;
b37a6434
VS		 14770 else if (IS_GEN5(dev))
14771 dev_priv->display.get_display_clock_speed =
14772 ilk_get_display_clock_speed;
a7c66cd8 14773 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
34edce2f 14774 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
e70236a8
JB		 14775 dev_priv->display.get_display_clock_speed =
14776 i945_get_display_clock_speed;
34edce2f
VS		 14777 else if (IS_GM45(dev))
14778 dev_priv->display.get_display_clock_speed =
14779 gm45_get_display_clock_speed;
14780 else if (IS_CRESTLINE(dev))
14781 dev_priv->display.get_display_clock_speed =
14782 i965gm_get_display_clock_speed;
14783 else if (IS_PINEVIEW(dev))
14784 dev_priv->display.get_display_clock_speed =
14785 pnv_get_display_clock_speed;
14786 else if (IS_G33(dev) || IS_G4X(dev))
14787 dev_priv->display.get_display_clock_speed =
14788 g33_get_display_clock_speed;
e70236a8
JB		 14789 else if (IS_I915G(dev))
14790 dev_priv->display.get_display_clock_speed =
14791 i915_get_display_clock_speed;
257a7ffc 14792 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 14793 dev_priv->display.get_display_clock_speed =
14794 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 14795 else if (IS_PINEVIEW(dev))
14796 dev_priv->display.get_display_clock_speed =
14797 pnv_get_display_clock_speed;
e70236a8
JB		 14798 else if (IS_I915GM(dev))
14799 dev_priv->display.get_display_clock_speed =
14800 i915gm_get_display_clock_speed;
14801 else if (IS_I865G(dev))
14802 dev_priv->display.get_display_clock_speed =
14803 i865_get_display_clock_speed;
f0f8a9ce 14804 else if (IS_I85X(dev))
e70236a8 14805 dev_priv->display.get_display_clock_speed =
1b1d2716 14806 i85x_get_display_clock_speed;
623e01e5
VS		 14807 else { /* 830 */
14808 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
e70236a8
JB		 14809 dev_priv->display.get_display_clock_speed =
14810 i830_get_display_clock_speed;
623e01e5 14811 }
e70236a8 14812
7c10a2b5 14813 if (IS_GEN5(dev)) {
3bb11b53 14814 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 14815 } else if (IS_GEN6(dev)) {
14816 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 14817 } else if (IS_IVYBRIDGE(dev)) {
14818 /* FIXME: detect B0+ stepping and use auto training */
14819 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 14820 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 14821 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
b432e5cf
VS		 14822 if (IS_BROADWELL(dev))
14823 dev_priv->display.modeset_global_resources =
14824 broadwell_modeset_global_resources;
30a970c6
JB		 14825 } else if (IS_VALLEYVIEW(dev)) {
14826 dev_priv->display.modeset_global_resources =
14827 valleyview_modeset_global_resources;
f8437dd1
VK		 14828 } else if (IS_BROXTON(dev)) {
14829 dev_priv->display.modeset_global_resources =
14830 broxton_modeset_global_resources;
e70236a8 14831 }
8c9f3aaf 14832
8c9f3aaf
JB		 14833 switch (INTEL_INFO(dev)->gen) {
14834 case 2:
14835 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14836 break;
14837
14838 case 3:
14839 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14840 break;
14841
14842 case 4:
14843 case 5:
14844 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14845 break;
14846
14847 case 6:
14848 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14849 break;
7c9017e5 14850 case 7:
4e0bbc31 14851 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 14852 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14853 break;
830c81db 14854 case 9:
ba343e02
TU		 14855 /* Drop through - unsupported since execlist only. */
14856 default:
14857 /* Default just returns -ENODEV to indicate unsupported */
14858 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 14859 }
7bd688cd
JN		 14860
14861 intel_panel_init_backlight_funcs(dev);
e39b999a
VS		 14862
14863 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 14864}
14865
b690e96c
JB		 14866/*
14867 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14868 * resume, or other times. This quirk makes sure that's the case for
14869 * affected systems.
14870 */
0206e353 14871static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 14872{
14873 struct drm_i915_private *dev_priv = dev->dev_private;
14874
14875 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 14876 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 14877}
14878
b6b5d049
VS		 14879static void quirk_pipeb_force(struct drm_device *dev)
14880{
14881 struct drm_i915_private *dev_priv = dev->dev_private;
14882
14883 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14884 DRM_INFO("applying pipe b force quirk\n");
14885}
14886
435793df
KP		 14887/*
14888 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14889 */
14890static void quirk_ssc_force_disable(struct drm_device *dev)
14891{
14892 struct drm_i915_private *dev_priv = dev->dev_private;
14893 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 14894 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 14895}
14896
4dca20ef 14897/*
5a15ab5b
CE		 14898 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14899 * brightness value
4dca20ef
CE		 14900 */
14901static void quirk_invert_brightness(struct drm_device *dev)
14902{
14903 struct drm_i915_private *dev_priv = dev->dev_private;
14904 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 14905 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 14906}
14907
9c72cc6f
SD		 14908/* Some VBT's incorrectly indicate no backlight is present */
14909static void quirk_backlight_present(struct drm_device *dev)
14910{
14911 struct drm_i915_private *dev_priv = dev->dev_private;
14912 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14913 DRM_INFO("applying backlight present quirk\n");
14914}
14915
b690e96c
JB		 14916struct intel_quirk {
14917 int device;
14918 int subsystem_vendor;
14919 int subsystem_device;
14920 void (*hook)(struct drm_device *dev);
14921};
14922
5f85f176
EE		 14923/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14924struct intel_dmi_quirk {
14925 void (*hook)(struct drm_device *dev);
14926 const struct dmi_system_id (*dmi_id_list)[];
14927};
14928
14929static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14930{
14931 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14932 return 1;
14933}
14934
14935static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14936 {
14937 .dmi_id_list = &(const struct dmi_system_id[]) {
14938 {
14939 .callback = intel_dmi_reverse_brightness,
14940 .ident = "NCR Corporation",
14941 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14942 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14943 },
14944 },
14945 { } /* terminating entry */
14946 },
14947 .hook = quirk_invert_brightness,
14948 },
14949};
14950
c43b5634 14951static struct intel_quirk intel_quirks[] = {
b690e96c
JB		 14952 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14953 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14954
b690e96c
JB		 14955 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14956 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14957
5f080c0f
VS		 14958 /* 830 needs to leave pipe A & dpll A up */
14959 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14960
b6b5d049
VS		 14961 /* 830 needs to leave pipe B & dpll B up */
14962 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14963
435793df
KP		 14964 /* Lenovo U160 cannot use SSC on LVDS */
14965 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 14966
14967 /* Sony Vaio Y cannot use SSC on LVDS */
14968 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 14969
be505f64
AH		 14970 /* Acer Aspire 5734Z must invert backlight brightness */
14971 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14972
14973 /* Acer/eMachines G725 */
14974 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14975
14976 /* Acer/eMachines e725 */
14977 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14978
14979 /* Acer/Packard Bell NCL20 */
14980 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14981
14982 /* Acer Aspire 4736Z */
14983 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 14984
14985 /* Acer Aspire 5336 */
14986 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 14987
14988 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14989 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 14990
dfb3d47b
SD		 14991 /* Acer C720 Chromebook (Core i3 4005U) */
14992 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14993
b2a9601c 14994 /* Apple Macbook 2,1 (Core 2 T7400) */
14995 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14996
d4967d8c
SD		 14997 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14998 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 14999
15000 /* HP Chromebook 14 (Celeron 2955U) */
15001 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 15002
15003 /* Dell Chromebook 11 */
15004 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 15005};
15006
15007static void intel_init_quirks(struct drm_device *dev)
15008{
15009 struct pci_dev *d = dev->pdev;
15010 int i;
15011
15012 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15013 struct intel_quirk *q = &intel_quirks[i];
15014
15015 if (d->device == q->device &&
15016 (d->subsystem_vendor == q->subsystem_vendor ||
15017 q->subsystem_vendor == PCI_ANY_ID) &&
15018 (d->subsystem_device == q->subsystem_device ||
15019 q->subsystem_device == PCI_ANY_ID))
15020 q->hook(dev);
15021 }
5f85f176
EE		 15022 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15023 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15024 intel_dmi_quirks[i].hook(dev);
15025 }
b690e96c
JB		 15026}
15027
9cce37f4
JB		 15028/* Disable the VGA plane that we never use */
15029static void i915_disable_vga(struct drm_device *dev)
15030{
15031 struct drm_i915_private *dev_priv = dev->dev_private;
15032 u8 sr1;
766aa1c4 15033 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 15034
2b37c616 15035 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 15036 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 15037 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 15038 sr1 = inb(VGA_SR_DATA);
15039 outb(sr1 | 1<<5, VGA_SR_DATA);
15040 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15041 udelay(300);
15042
01f5a626 15043 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 15044 POSTING_READ(vga_reg);
15045}
15046
f817586c
DV		 15047void intel_modeset_init_hw(struct drm_device *dev)
15048{
b6283055 15049 intel_update_cdclk(dev);
a8f78b58 15050 intel_prepare_ddi(dev);
f817586c 15051 intel_init_clock_gating(dev);
8090c6b9 15052 intel_enable_gt_powersave(dev);
f817586c
DV		 15053}
15054
79e53945
JB		 15055void intel_modeset_init(struct drm_device *dev)
15056{
652c393a 15057 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 15058 int sprite, ret;
8cc87b75 15059 enum pipe pipe;
46f297fb 15060 struct intel_crtc *crtc;
79e53945
JB		 15061
15062 drm_mode_config_init(dev);
15063
15064 dev->mode_config.min_width = 0;
15065 dev->mode_config.min_height = 0;
15066
019d96cb
DA		 15067 dev->mode_config.preferred_depth = 24;
15068 dev->mode_config.prefer_shadow = 1;
15069
25bab385
TU		 15070 dev->mode_config.allow_fb_modifiers = true;
15071
e6ecefaa 15072 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 15073
b690e96c
JB		 15074 intel_init_quirks(dev);
15075
1fa61106
ED		 15076 intel_init_pm(dev);
15077
e3c74757
BW		 15078 if (INTEL_INFO(dev)->num_pipes == 0)
15079 return;
15080
e70236a8 15081 intel_init_display(dev);
7c10a2b5 15082 intel_init_audio(dev);
e70236a8 15083
a6c45cf0
CW		 15084 if (IS_GEN2(dev)) {
15085 dev->mode_config.max_width = 2048;
15086 dev->mode_config.max_height = 2048;
15087 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 15088 dev->mode_config.max_width = 4096;
15089 dev->mode_config.max_height = 4096;
79e53945 15090 } else {
a6c45cf0
CW		 15091 dev->mode_config.max_width = 8192;
15092 dev->mode_config.max_height = 8192;
79e53945 15093 }
068be561 15094
dc41c154
VS		 15095 if (IS_845G(dev) || IS_I865G(dev)) {
15096 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15097 dev->mode_config.cursor_height = 1023;
15098 } else if (IS_GEN2(dev)) {
068be561
DL		 15099 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15100 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15101 } else {
15102 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15103 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15104 }
15105
5d4545ae 15106 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 15107
28c97730 15108 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 15109 INTEL_INFO(dev)->num_pipes,
15110 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 15111
055e393f 15112 for_each_pipe(dev_priv, pipe) {
8cc87b75 15113 intel_crtc_init(dev, pipe);
3bdcfc0c 15114 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 15115 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 15116 if (ret)
06da8da2 15117 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 15118 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 15119 }
79e53945
JB		 15120 }
15121
f42bb70d
JB		 15122 intel_init_dpio(dev);
15123
e72f9fbf 15124 intel_shared_dpll_init(dev);
ee7b9f93 15125
9cce37f4
JB		 15126 /* Just disable it once at startup */
15127 i915_disable_vga(dev);
79e53945 15128 intel_setup_outputs(dev);
11be49eb
CW		 15129
15130 /* Just in case the BIOS is doing something questionable. */
7ff0ebcc 15131 intel_fbc_disable(dev);
fa9fa083 15132
6e9f798d 15133 drm_modeset_lock_all(dev);
fa9fa083 15134 intel_modeset_setup_hw_state(dev, false);
6e9f798d 15135 drm_modeset_unlock_all(dev);
46f297fb 15136
d3fcc808 15137 for_each_intel_crtc(dev, crtc) {
46f297fb
JB		 15138 if (!crtc->active)
15139 continue;
15140
46f297fb 15141 /*
46f297fb
JB		 15142 * Note that reserving the BIOS fb up front prevents us
15143 * from stuffing other stolen allocations like the ring
15144 * on top. This prevents some ugliness at boot time, and
15145 * can even allow for smooth boot transitions if the BIOS
15146 * fb is large enough for the active pipe configuration.
15147 */
5724dbd1
DL		 15148 if (dev_priv->display.get_initial_plane_config) {
15149 dev_priv->display.get_initial_plane_config(crtc,
46f297fb
JB		 15150 &crtc->plane_config);
15151 /*
15152 * If the fb is shared between multiple heads, we'll
15153 * just get the first one.
15154 */
f6936e29 15155 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
46f297fb 15156 }
46f297fb 15157 }
2c7111db
CW		 15158}
15159
7fad798e
DV		 15160static void intel_enable_pipe_a(struct drm_device *dev)
15161{
15162 struct intel_connector *connector;
15163 struct drm_connector *crt = NULL;
15164 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 15165 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 15166
15167 /* We can't just switch on the pipe A, we need to set things up with a
15168 * proper mode and output configuration. As a gross hack, enable pipe A
15169 * by enabling the load detect pipe once. */
3a3371ff 15170 for_each_intel_connector(dev, connector) {
7fad798e
DV		 15171 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15172 crt = &connector->base;
15173 break;
15174 }
15175 }
15176
15177 if (!crt)
15178 return;
15179
208bf9fd 15180 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 15181 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 15182}
15183
fa555837
DV		 15184static bool
15185intel_check_plane_mapping(struct intel_crtc *crtc)
15186{
7eb552ae
BW		 15187 struct drm_device *dev = crtc->base.dev;
15188 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 15189 u32 reg, val;
15190
7eb552ae 15191 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 15192 return true;
15193
15194 reg = DSPCNTR(!crtc->plane);
15195 val = I915_READ(reg);
15196
15197 if ((val & DISPLAY_PLANE_ENABLE) &&
15198 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15199 return false;
15200
15201 return true;
15202}
15203
24929352
DV		 15204static void intel_sanitize_crtc(struct intel_crtc *crtc)
15205{
15206 struct drm_device *dev = crtc->base.dev;
15207 struct drm_i915_private *dev_priv = dev->dev_private;
b17d48e2 15208 struct intel_encoder *encoder;
fa555837 15209 u32 reg;
b17d48e2 15210 bool enable;
24929352 15211
24929352 15212 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 15213 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 15214 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15215
d3eaf884 15216 /* restore vblank interrupts to correct state */
9625604c 15217 drm_crtc_vblank_reset(&crtc->base);
d297e103
VS		 15218 if (crtc->active) {
15219 update_scanline_offset(crtc);
9625604c
DV		 15220 drm_crtc_vblank_on(&crtc->base);
15221 }
d3eaf884 15222
24929352 15223 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 15224 * disable the crtc (and hence change the state) if it is wrong. Note
15225 * that gen4+ has a fixed plane -> pipe mapping. */
15226 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 15227 bool plane;
15228
24929352
DV		 15229 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15230 crtc->base.base.id);
15231
15232 /* Pipe has the wrong plane attached and the plane is active.
15233 * Temporarily change the plane mapping and disable everything
15234 * ... */
15235 plane = crtc->plane;
b70709a6 15236 to_intel_plane_state(crtc->base.primary->state)->visible = true;
24929352 15237 crtc->plane = !plane;
b17d48e2 15238 intel_crtc_disable_noatomic(&crtc->base);
24929352 15239 crtc->plane = plane;
24929352 15240 }
24929352 15241
7fad798e
DV		 15242 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15243 crtc->pipe == PIPE_A && !crtc->active) {
15244 /* BIOS forgot to enable pipe A, this mostly happens after
15245 * resume. Force-enable the pipe to fix this, the update_dpms
15246 * call below we restore the pipe to the right state, but leave
15247 * the required bits on. */
15248 intel_enable_pipe_a(dev);
15249 }
15250
24929352
DV		 15251 /* Adjust the state of the output pipe according to whether we
15252 * have active connectors/encoders. */
b17d48e2
ML		 15253 enable = false;
15254 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15255 enable |= encoder->connectors_active;
24929352 15256
b17d48e2
ML		 15257 if (!enable)
15258 intel_crtc_disable_noatomic(&crtc->base);
24929352 15259
53d9f4e9 15260 if (crtc->active != crtc->base.state->active) {
24929352
DV		 15261
15262 /* This can happen either due to bugs in the get_hw_state
b17d48e2
ML		 15263 * functions or because of calls to intel_crtc_disable_noatomic,
15264 * or because the pipe is force-enabled due to the
24929352
DV		 15265 * pipe A quirk. */
15266 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15267 crtc->base.base.id,
83d65738 15268 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 15269 crtc->active ? "enabled" : "disabled");
15270
83d65738 15271 crtc->base.state->enable = crtc->active;
49d6fa21 15272 crtc->base.state->active = crtc->active;
24929352
DV		 15273 crtc->base.enabled = crtc->active;
15274
15275 /* Because we only establish the connector -> encoder ->
15276 * crtc links if something is active, this means the
15277 * crtc is now deactivated. Break the links. connector
15278 * -> encoder links are only establish when things are
15279 * actually up, hence no need to break them. */
15280 WARN_ON(crtc->active);
15281
15282 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
15283 WARN_ON(encoder->connectors_active);
15284 encoder->base.crtc = NULL;
15285 }
15286 }
c5ab3bc0 15287
a3ed6aad 15288 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 15289 /*
15290 * We start out with underrun reporting disabled to avoid races.
15291 * For correct bookkeeping mark this on active crtcs.
15292 *
c5ab3bc0
DV		 15293 * Also on gmch platforms we dont have any hardware bits to
15294 * disable the underrun reporting. Which means we need to start
15295 * out with underrun reporting disabled also on inactive pipes,
15296 * since otherwise we'll complain about the garbage we read when
15297 * e.g. coming up after runtime pm.
15298 *
4cc31489
DV		 15299 * No protection against concurrent access is required - at
15300 * worst a fifo underrun happens which also sets this to false.
15301 */
15302 crtc->cpu_fifo_underrun_disabled = true;
15303 crtc->pch_fifo_underrun_disabled = true;
15304 }
24929352
DV		 15305}
15306
15307static void intel_sanitize_encoder(struct intel_encoder *encoder)
15308{
15309 struct intel_connector *connector;
15310 struct drm_device *dev = encoder->base.dev;
15311
15312 /* We need to check both for a crtc link (meaning that the
15313 * encoder is active and trying to read from a pipe) and the
15314 * pipe itself being active. */
15315 bool has_active_crtc = encoder->base.crtc &&
15316 to_intel_crtc(encoder->base.crtc)->active;
15317
15318 if (encoder->connectors_active && !has_active_crtc) {
15319 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15320 encoder->base.base.id,
8e329a03 15321 encoder->base.name);
24929352
DV		 15322
15323 /* Connector is active, but has no active pipe. This is
15324 * fallout from our resume register restoring. Disable
15325 * the encoder manually again. */
15326 if (encoder->base.crtc) {
15327 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15328 encoder->base.base.id,
8e329a03 15329 encoder->base.name);
24929352 15330 encoder->disable(encoder);
a62d1497
VS		 15331 if (encoder->post_disable)
15332 encoder->post_disable(encoder);
24929352 15333 }
7f1950fb
EE		 15334 encoder->base.crtc = NULL;
15335 encoder->connectors_active = false;
24929352
DV		 15336
15337 /* Inconsistent output/port/pipe state happens presumably due to
15338 * a bug in one of the get_hw_state functions. Or someplace else
15339 * in our code, like the register restore mess on resume. Clamp
15340 * things to off as a safer default. */
3a3371ff 15341 for_each_intel_connector(dev, connector) {
24929352
DV		 15342 if (connector->encoder != encoder)
15343 continue;
7f1950fb
EE		 15344 connector->base.dpms = DRM_MODE_DPMS_OFF;
15345 connector->base.encoder = NULL;
24929352
DV		 15346 }
15347 }
15348 /* Enabled encoders without active connectors will be fixed in
15349 * the crtc fixup. */
15350}
15351
04098753 15352void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 15353{
15354 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 15355 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 15356
04098753
ID		 15357 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15358 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15359 i915_disable_vga(dev);
15360 }
15361}
15362
15363void i915_redisable_vga(struct drm_device *dev)
15364{
15365 struct drm_i915_private *dev_priv = dev->dev_private;
15366
8dc8a27c
PZ		 15367 /* This function can be called both from intel_modeset_setup_hw_state or
15368 * at a very early point in our resume sequence, where the power well
15369 * structures are not yet restored. Since this function is at a very
15370 * paranoid "someone might have enabled VGA while we were not looking"
15371 * level, just check if the power well is enabled instead of trying to
15372 * follow the "don't touch the power well if we don't need it" policy
15373 * the rest of the driver uses. */
f458ebbc 15374 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 15375 return;
15376
04098753 15377 i915_redisable_vga_power_on(dev);
0fde901f
KM		 15378}
15379
98ec7739
VS		 15380static bool primary_get_hw_state(struct intel_crtc *crtc)
15381{
15382 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15383
15384 if (!crtc->active)
15385 return false;
15386
15387 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
15388}
15389
30e984df 15390static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 15391{
15392 struct drm_i915_private *dev_priv = dev->dev_private;
15393 enum pipe pipe;
24929352
DV		 15394 struct intel_crtc *crtc;
15395 struct intel_encoder *encoder;
15396 struct intel_connector *connector;
5358901f 15397 int i;
24929352 15398
d3fcc808 15399 for_each_intel_crtc(dev, crtc) {
b70709a6
ML		 15400 struct drm_plane *primary = crtc->base.primary;
15401 struct intel_plane_state *plane_state;
15402
6e3c9717 15403 memset(crtc->config, 0, sizeof(*crtc->config));
f7217905 15404 crtc->config->base.crtc = &crtc->base;
3b117c8f 15405
6e3c9717 15406 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
9953599b 15407
0e8ffe1b 15408 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 15409 crtc->config);
24929352 15410
83d65738 15411 crtc->base.state->enable = crtc->active;
49d6fa21 15412 crtc->base.state->active = crtc->active;
24929352 15413 crtc->base.enabled = crtc->active;
b8b7fade 15414 crtc->base.hwmode = crtc->config->base.adjusted_mode;
b70709a6
ML		 15415
15416 plane_state = to_intel_plane_state(primary->state);
15417 plane_state->visible = primary_get_hw_state(crtc);
24929352
DV		 15418
15419 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15420 crtc->base.base.id,
15421 crtc->active ? "enabled" : "disabled");
15422 }
15423
5358901f
DV		 15424 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15425 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15426
3e369b76
ACO		 15427 pll->on = pll->get_hw_state(dev_priv, pll,
15428 &pll->config.hw_state);
5358901f 15429 pll->active = 0;
3e369b76 15430 pll->config.crtc_mask = 0;
d3fcc808 15431 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 15432 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 15433 pll->active++;
3e369b76 15434 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 15435 }
5358901f 15436 }
5358901f 15437
1e6f2ddc 15438 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 15439 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 15440
3e369b76 15441 if (pll->config.crtc_mask)
bd2bb1b9 15442 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 15443 }
15444
b2784e15 15445 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15446 pipe = 0;
15447
15448 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 15449 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15450 encoder->base.crtc = &crtc->base;
6e3c9717 15451 encoder->get_config(encoder, crtc->config);
24929352
DV		 15452 } else {
15453 encoder->base.crtc = NULL;
15454 }
15455
15456 encoder->connectors_active = false;
6f2bcceb 15457 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 15458 encoder->base.base.id,
8e329a03 15459 encoder->base.name,
24929352 15460 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 15461 pipe_name(pipe));
24929352
DV		 15462 }
15463
3a3371ff 15464 for_each_intel_connector(dev, connector) {
24929352
DV		 15465 if (connector->get_hw_state(connector)) {
15466 connector->base.dpms = DRM_MODE_DPMS_ON;
15467 connector->encoder->connectors_active = true;
15468 connector->base.encoder = &connector->encoder->base;
15469 } else {
15470 connector->base.dpms = DRM_MODE_DPMS_OFF;
15471 connector->base.encoder = NULL;
15472 }
15473 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15474 connector->base.base.id,
c23cc417 15475 connector->base.name,
24929352
DV		 15476 connector->base.encoder ? "enabled" : "disabled");
15477 }
30e984df
DV		 15478}
15479
15480/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15481 * and i915 state tracking structures. */
15482void intel_modeset_setup_hw_state(struct drm_device *dev,
15483 bool force_restore)
15484{
15485 struct drm_i915_private *dev_priv = dev->dev_private;
15486 enum pipe pipe;
30e984df
DV		 15487 struct intel_crtc *crtc;
15488 struct intel_encoder *encoder;
35c95375 15489 int i;
30e984df
DV		 15490
15491 intel_modeset_readout_hw_state(dev);
24929352 15492
babea61d
JB		 15493 /*
15494 * Now that we have the config, copy it to each CRTC struct
15495 * Note that this could go away if we move to using crtc_config
15496 * checking everywhere.
15497 */
d3fcc808 15498 for_each_intel_crtc(dev, crtc) {
d330a953 15499 if (crtc->active && i915.fastboot) {
6e3c9717
ACO		 15500 intel_mode_from_pipe_config(&crtc->base.mode,
15501 crtc->config);
babea61d
JB		 15502 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15503 crtc->base.base.id);
15504 drm_mode_debug_printmodeline(&crtc->base.mode);
15505 }
15506 }
15507
24929352 15508 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 15509 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15510 intel_sanitize_encoder(encoder);
15511 }
15512
055e393f 15513 for_each_pipe(dev_priv, pipe) {
24929352
DV		 15514 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15515 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 15516 intel_dump_pipe_config(crtc, crtc->config,
15517 "[setup_hw_state]");
24929352 15518 }
9a935856 15519
d29b2f9d
ACO		 15520 intel_modeset_update_connector_atomic_state(dev);
15521
35c95375
DV		 15522 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15523 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15524
15525 if (!pll->on || pll->active)
15526 continue;
15527
15528 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15529
15530 pll->disable(dev_priv, pll);
15531 pll->on = false;
15532 }
15533
3078999f
PB		 15534 if (IS_GEN9(dev))
15535 skl_wm_get_hw_state(dev);
15536 else if (HAS_PCH_SPLIT(dev))
243e6a44
VS		 15537 ilk_wm_get_hw_state(dev);
15538
45e2b5f6 15539 if (force_restore) {
7d0bc1ea
VS		 15540 i915_redisable_vga(dev);
15541
f30da187
DV		 15542 /*
15543 * We need to use raw interfaces for restoring state to avoid
15544 * checking (bogus) intermediate states.
15545 */
055e393f 15546 for_each_pipe(dev_priv, pipe) {
b5644d05
JB		 15547 struct drm_crtc *crtc =
15548 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187 15549
83a57153 15550 intel_crtc_restore_mode(crtc);
45e2b5f6
DV		 15551 }
15552 } else {
15553 intel_modeset_update_staged_output_state(dev);
15554 }
8af6cf88
DV		 15555
15556 intel_modeset_check_state(dev);
2c7111db
CW		 15557}
15558
15559void intel_modeset_gem_init(struct drm_device *dev)
15560{
92122789 15561 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd 15562 struct drm_crtc *c;
2ff8fde1 15563 struct drm_i915_gem_object *obj;
e0d6149b 15564 int ret;
484b41dd 15565
ae48434c
ID		 15566 mutex_lock(&dev->struct_mutex);
15567 intel_init_gt_powersave(dev);
15568 mutex_unlock(&dev->struct_mutex);
15569
92122789
JB		 15570 /*
15571 * There may be no VBT; and if the BIOS enabled SSC we can
15572 * just keep using it to avoid unnecessary flicker. Whereas if the
15573 * BIOS isn't using it, don't assume it will work even if the VBT
15574 * indicates as much.
15575 */
15576 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15577 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15578 DREF_SSC1_ENABLE);
15579
1833b134 15580 intel_modeset_init_hw(dev);
02e792fb
DV		 15581
15582 intel_setup_overlay(dev);
484b41dd
JB		 15583
15584 /*
15585 * Make sure any fbs we allocated at startup are properly
15586 * pinned & fenced. When we do the allocation it's too early
15587 * for this.
15588 */
70e1e0ec 15589 for_each_crtc(dev, c) {
2ff8fde1
MR		 15590 obj = intel_fb_obj(c->primary->fb);
15591 if (obj == NULL)
484b41dd
JB		 15592 continue;
15593
e0d6149b
TU		 15594 mutex_lock(&dev->struct_mutex);
15595 ret = intel_pin_and_fence_fb_obj(c->primary,
15596 c->primary->fb,
15597 c->primary->state,
15598 NULL);
15599 mutex_unlock(&dev->struct_mutex);
15600 if (ret) {
484b41dd
JB		 15601 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15602 to_intel_crtc(c)->pipe);
66e514c1
DA		 15603 drm_framebuffer_unreference(c->primary->fb);
15604 c->primary->fb = NULL;
36750f28 15605 c->primary->crtc = c->primary->state->crtc = NULL;
afd65eb4 15606 update_state_fb(c->primary);
36750f28 15607 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
484b41dd
JB		 15608 }
15609 }
0962c3c9
VS		 15610
15611 intel_backlight_register(dev);
79e53945
JB		 15612}
15613
4932e2c3
ID		 15614void intel_connector_unregister(struct intel_connector *intel_connector)
15615{
15616 struct drm_connector *connector = &intel_connector->base;
15617
15618 intel_panel_destroy_backlight(connector);
34ea3d38 15619 drm_connector_unregister(connector);
4932e2c3
ID		 15620}
15621
79e53945
JB		 15622void intel_modeset_cleanup(struct drm_device *dev)
15623{
652c393a 15624 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 15625 struct drm_connector *connector;
652c393a 15626
2eb5252e
ID		 15627 intel_disable_gt_powersave(dev);
15628
0962c3c9
VS		 15629 intel_backlight_unregister(dev);
15630
fd0c0642
DV		 15631 /*
15632 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 15633 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 15634 * experience fancy races otherwise.
15635 */
2aeb7d3a 15636 intel_irq_uninstall(dev_priv);
eb21b92b 15637
fd0c0642
DV		 15638 /*
15639 * Due to the hpd irq storm handling the hotplug work can re-arm the
15640 * poll handlers. Hence disable polling after hpd handling is shut down.
15641 */
f87ea761 15642 drm_kms_helper_poll_fini(dev);
fd0c0642 15643
652c393a
JB		 15644 mutex_lock(&dev->struct_mutex);
15645
723bfd70
JB		 15646 intel_unregister_dsm_handler();
15647
7ff0ebcc 15648 intel_fbc_disable(dev);
e70236a8 15649
69341a5e
KH		 15650 mutex_unlock(&dev->struct_mutex);
15651
1630fe75
CW		 15652 /* flush any delayed tasks or pending work */
15653 flush_scheduled_work();
15654
db31af1d
JN		 15655 /* destroy the backlight and sysfs files before encoders/connectors */
15656 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 15657 struct intel_connector *intel_connector;
15658
15659 intel_connector = to_intel_connector(connector);
15660 intel_connector->unregister(intel_connector);
db31af1d 15661 }
d9255d57 15662
79e53945 15663 drm_mode_config_cleanup(dev);
4d7bb011
DV		 15664
15665 intel_cleanup_overlay(dev);
ae48434c
ID		 15666
15667 mutex_lock(&dev->struct_mutex);
15668 intel_cleanup_gt_powersave(dev);
15669 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 15670}
15671
f1c79df3
ZW		 15672/*
15673 * Return which encoder is currently attached for connector.
15674 */
df0e9248 15675struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 15676{
df0e9248
CW		 15677 return &intel_attached_encoder(connector)->base;
15678}
f1c79df3 15679
df0e9248
CW		 15680void intel_connector_attach_encoder(struct intel_connector *connector,
15681 struct intel_encoder *encoder)
15682{
15683 connector->encoder = encoder;
15684 drm_mode_connector_attach_encoder(&connector->base,
15685 &encoder->base);
79e53945 15686}
28d52043
DA		 15687
15688/*
15689 * set vga decode state - true == enable VGA decode
15690 */
15691int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15692{
15693 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 15694 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 15695 u16 gmch_ctrl;
15696
75fa041d
CW		 15697 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15698 DRM_ERROR("failed to read control word\n");
15699 return -EIO;
15700 }
15701
c0cc8a55
CW		 15702 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15703 return 0;
15704
28d52043
DA		 15705 if (state)
15706 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15707 else
15708 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 15709
15710 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15711 DRM_ERROR("failed to write control word\n");
15712 return -EIO;
15713 }
15714
28d52043
DA		 15715 return 0;
15716}
c4a1d9e4 15717
c4a1d9e4 15718struct intel_display_error_state {
ff57f1b0
PZ		 15719
15720 u32 power_well_driver;
15721
63b66e5b
CW		 15722 int num_transcoders;
15723
c4a1d9e4
CW		 15724 struct intel_cursor_error_state {
15725 u32 control;
15726 u32 position;
15727 u32 base;
15728 u32 size;
52331309 15729 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 15730
15731 struct intel_pipe_error_state {
ddf9c536 15732 bool power_domain_on;
c4a1d9e4 15733 u32 source;
f301b1e1 15734 u32 stat;
52331309 15735 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 15736
15737 struct intel_plane_error_state {
15738 u32 control;
15739 u32 stride;
15740 u32 size;
15741 u32 pos;
15742 u32 addr;
15743 u32 surface;
15744 u32 tile_offset;
52331309 15745 } plane[I915_MAX_PIPES];
63b66e5b
CW		 15746
15747 struct intel_transcoder_error_state {
ddf9c536 15748 bool power_domain_on;
63b66e5b
CW		 15749 enum transcoder cpu_transcoder;
15750
15751 u32 conf;
15752
15753 u32 htotal;
15754 u32 hblank;
15755 u32 hsync;
15756 u32 vtotal;
15757 u32 vblank;
15758 u32 vsync;
15759 } transcoder[4];
c4a1d9e4
CW		 15760};
15761
15762struct intel_display_error_state *
15763intel_display_capture_error_state(struct drm_device *dev)
15764{
fbee40df 15765 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 15766 struct intel_display_error_state *error;
63b66e5b
CW		 15767 int transcoders[] = {
15768 TRANSCODER_A,
15769 TRANSCODER_B,
15770 TRANSCODER_C,
15771 TRANSCODER_EDP,
15772 };
c4a1d9e4
CW		 15773 int i;
15774
63b66e5b
CW		 15775 if (INTEL_INFO(dev)->num_pipes == 0)
15776 return NULL;
15777
9d1cb914 15778 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 15779 if (error == NULL)
15780 return NULL;
15781
190be112 15782 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 15783 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15784
055e393f 15785 for_each_pipe(dev_priv, i) {
ddf9c536 15786 error->pipe[i].power_domain_on =
f458ebbc
DV		 15787 __intel_display_power_is_enabled(dev_priv,
15788 POWER_DOMAIN_PIPE(i));
ddf9c536 15789 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 15790 continue;
15791
5efb3e28
VS		 15792 error->cursor[i].control = I915_READ(CURCNTR(i));
15793 error->cursor[i].position = I915_READ(CURPOS(i));
15794 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 15795
15796 error->plane[i].control = I915_READ(DSPCNTR(i));
15797 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 15798 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 15799 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 15800 error->plane[i].pos = I915_READ(DSPPOS(i));
15801 }
ca291363
PZ		 15802 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15803 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 15804 if (INTEL_INFO(dev)->gen >= 4) {
15805 error->plane[i].surface = I915_READ(DSPSURF(i));
15806 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15807 }
15808
c4a1d9e4 15809 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 15810
3abfce77 15811 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 15812 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 15813 }
15814
15815 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15816 if (HAS_DDI(dev_priv->dev))
15817 error->num_transcoders++; /* Account for eDP. */
15818
15819 for (i = 0; i < error->num_transcoders; i++) {
15820 enum transcoder cpu_transcoder = transcoders[i];
15821
ddf9c536 15822 error->transcoder[i].power_domain_on =
f458ebbc 15823 __intel_display_power_is_enabled(dev_priv,
38cc1daf 15824 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 15825 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 15826 continue;
15827
63b66e5b
CW		 15828 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15829
15830 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15831 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15832 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15833 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15834 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15835 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15836 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 15837 }
15838
15839 return error;
15840}
15841
edc3d884
MK		 15842#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15843
c4a1d9e4 15844void
edc3d884 15845intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 15846 struct drm_device *dev,
15847 struct intel_display_error_state *error)
15848{
055e393f 15849 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 15850 int i;
15851
63b66e5b
CW		 15852 if (!error)
15853 return;
15854
edc3d884 15855 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 15856 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 15857 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 15858 error->power_well_driver);
055e393f 15859 for_each_pipe(dev_priv, i) {
edc3d884 15860 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 15861 err_printf(m, " Power: %s\n",
15862 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 15863 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 15864 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 15865
15866 err_printf(m, "Plane [%d]:\n", i);
15867 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15868 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 15869 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 15870 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15871 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 15872 }
4b71a570 15873 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 15874 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 15875 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 15876 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15877 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 15878 }
15879
edc3d884
MK		 15880 err_printf(m, "Cursor [%d]:\n", i);
15881 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15882 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15883 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 15884 }
63b66e5b
CW		 15885
15886 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 15887 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 15888 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 15889 err_printf(m, " Power: %s\n",
15890 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 15891 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15892 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15893 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15894 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15895 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15896 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15897 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15898 }
c4a1d9e4 15899}
e2fcdaa9
VS		 15900
15901void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15902{
15903 struct intel_crtc *crtc;
15904
15905 for_each_intel_crtc(dev, crtc) {
15906 struct intel_unpin_work *work;
e2fcdaa9 15907
5e2d7afc 15908 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 15909
15910 work = crtc->unpin_work;
15911
15912 if (work && work->event &&
15913 work->event->base.file_priv == file) {
15914 kfree(work->event);
15915 work->event = NULL;
15916 }
15917
5e2d7afc 15918 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 15919 }
15920}
Linux kernel - Deliverables
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