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drm/i915: Refactor ctg+ trickle feed disable
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
79e53945 48typedef struct {
0206e353 49 int min, max;
79e53945
JB		 50} intel_range_t;
51
52typedef struct {
0206e353
AJ		 53 int dot_limit;
54 int p2_slow, p2_fast;
79e53945
JB		 55} intel_p2_t;
56
57#define INTEL_P2_NUM 2
d4906093
ML		 58typedef struct intel_limit intel_limit_t;
59struct intel_limit {
0206e353
AJ		 60 intel_range_t dot, vco, n, m, m1, m2, p, p1;
61 intel_p2_t p2;
d4906093 62};
79e53945 63
2377b741
JB		 64/* FDI */
65#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
66
d2acd215
DV		 67int
68intel_pch_rawclk(struct drm_device *dev)
69{
70 struct drm_i915_private *dev_priv = dev->dev_private;
71
72 WARN_ON(!HAS_PCH_SPLIT(dev));
73
74 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
75}
76
021357ac
CW		 77static inline u32 /* units of 100MHz */
78intel_fdi_link_freq(struct drm_device *dev)
79{
8b99e68c
CW		 80 if (IS_GEN5(dev)) {
81 struct drm_i915_private *dev_priv = dev->dev_private;
82 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
83 } else
84 return 27;
021357ac
CW		 85}
86
e4b36699 87static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 88 .dot = { .min = 25000, .max = 350000 },
89 .vco = { .min = 930000, .max = 1400000 },
90 .n = { .min = 3, .max = 16 },
91 .m = { .min = 96, .max = 140 },
92 .m1 = { .min = 18, .max = 26 },
93 .m2 = { .min = 6, .max = 16 },
94 .p = { .min = 4, .max = 128 },
95 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 96 .p2 = { .dot_limit = 165000,
97 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 98};
99
100static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 101 .dot = { .min = 25000, .max = 350000 },
102 .vco = { .min = 930000, .max = 1400000 },
103 .n = { .min = 3, .max = 16 },
104 .m = { .min = 96, .max = 140 },
105 .m1 = { .min = 18, .max = 26 },
106 .m2 = { .min = 6, .max = 16 },
107 .p = { .min = 4, .max = 128 },
108 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 109 .p2 = { .dot_limit = 165000,
110 .p2_slow = 14, .p2_fast = 7 },
e4b36699 111};
273e27ca 112
e4b36699 113static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 114 .dot = { .min = 20000, .max = 400000 },
115 .vco = { .min = 1400000, .max = 2800000 },
116 .n = { .min = 1, .max = 6 },
117 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 118 .m1 = { .min = 8, .max = 18 },
119 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 120 .p = { .min = 5, .max = 80 },
121 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 122 .p2 = { .dot_limit = 200000,
123 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 124};
125
126static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 127 .dot = { .min = 20000, .max = 400000 },
128 .vco = { .min = 1400000, .max = 2800000 },
129 .n = { .min = 1, .max = 6 },
130 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 131 .m1 = { .min = 8, .max = 18 },
132 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 133 .p = { .min = 7, .max = 98 },
134 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 135 .p2 = { .dot_limit = 112000,
136 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 137};
138
273e27ca 139
e4b36699 140static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 141 .dot = { .min = 25000, .max = 270000 },
142 .vco = { .min = 1750000, .max = 3500000},
143 .n = { .min = 1, .max = 4 },
144 .m = { .min = 104, .max = 138 },
145 .m1 = { .min = 17, .max = 23 },
146 .m2 = { .min = 5, .max = 11 },
147 .p = { .min = 10, .max = 30 },
148 .p1 = { .min = 1, .max = 3},
149 .p2 = { .dot_limit = 270000,
150 .p2_slow = 10,
151 .p2_fast = 10
044c7c41 152 },
e4b36699
KP		 153};
154
155static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 156 .dot = { .min = 22000, .max = 400000 },
157 .vco = { .min = 1750000, .max = 3500000},
158 .n = { .min = 1, .max = 4 },
159 .m = { .min = 104, .max = 138 },
160 .m1 = { .min = 16, .max = 23 },
161 .m2 = { .min = 5, .max = 11 },
162 .p = { .min = 5, .max = 80 },
163 .p1 = { .min = 1, .max = 8},
164 .p2 = { .dot_limit = 165000,
165 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 166};
167
168static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 169 .dot = { .min = 20000, .max = 115000 },
170 .vco = { .min = 1750000, .max = 3500000 },
171 .n = { .min = 1, .max = 3 },
172 .m = { .min = 104, .max = 138 },
173 .m1 = { .min = 17, .max = 23 },
174 .m2 = { .min = 5, .max = 11 },
175 .p = { .min = 28, .max = 112 },
176 .p1 = { .min = 2, .max = 8 },
177 .p2 = { .dot_limit = 0,
178 .p2_slow = 14, .p2_fast = 14
044c7c41 179 },
e4b36699
KP		 180};
181
182static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 183 .dot = { .min = 80000, .max = 224000 },
184 .vco = { .min = 1750000, .max = 3500000 },
185 .n = { .min = 1, .max = 3 },
186 .m = { .min = 104, .max = 138 },
187 .m1 = { .min = 17, .max = 23 },
188 .m2 = { .min = 5, .max = 11 },
189 .p = { .min = 14, .max = 42 },
190 .p1 = { .min = 2, .max = 6 },
191 .p2 = { .dot_limit = 0,
192 .p2_slow = 7, .p2_fast = 7
044c7c41 193 },
e4b36699
KP		 194};
195
f2b115e6 196static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 197 .dot = { .min = 20000, .max = 400000},
198 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 199 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 200 .n = { .min = 3, .max = 6 },
201 .m = { .min = 2, .max = 256 },
273e27ca 202 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 203 .m1 = { .min = 0, .max = 0 },
204 .m2 = { .min = 0, .max = 254 },
205 .p = { .min = 5, .max = 80 },
206 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 207 .p2 = { .dot_limit = 200000,
208 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 209};
210
f2b115e6 211static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 212 .dot = { .min = 20000, .max = 400000 },
213 .vco = { .min = 1700000, .max = 3500000 },
214 .n = { .min = 3, .max = 6 },
215 .m = { .min = 2, .max = 256 },
216 .m1 = { .min = 0, .max = 0 },
217 .m2 = { .min = 0, .max = 254 },
218 .p = { .min = 7, .max = 112 },
219 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 220 .p2 = { .dot_limit = 112000,
221 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 222};
223
273e27ca
EA		 224/* Ironlake / Sandybridge
225 *
226 * We calculate clock using (register_value + 2) for N/M1/M2, so here
227 * the range value for them is (actual_value - 2).
228 */
b91ad0ec 229static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 230 .dot = { .min = 25000, .max = 350000 },
231 .vco = { .min = 1760000, .max = 3510000 },
232 .n = { .min = 1, .max = 5 },
233 .m = { .min = 79, .max = 127 },
234 .m1 = { .min = 12, .max = 22 },
235 .m2 = { .min = 5, .max = 9 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8 },
238 .p2 = { .dot_limit = 225000,
239 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 240};
241
b91ad0ec 242static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 243 .dot = { .min = 25000, .max = 350000 },
244 .vco = { .min = 1760000, .max = 3510000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 79, .max = 118 },
247 .m1 = { .min = 12, .max = 22 },
248 .m2 = { .min = 5, .max = 9 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 225000,
252 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 253};
254
255static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 256 .dot = { .min = 25000, .max = 350000 },
257 .vco = { .min = 1760000, .max = 3510000 },
258 .n = { .min = 1, .max = 3 },
259 .m = { .min = 79, .max = 127 },
260 .m1 = { .min = 12, .max = 22 },
261 .m2 = { .min = 5, .max = 9 },
262 .p = { .min = 14, .max = 56 },
263 .p1 = { .min = 2, .max = 8 },
264 .p2 = { .dot_limit = 225000,
265 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 266};
267
273e27ca 268/* LVDS 100mhz refclk limits. */
b91ad0ec 269static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 270 .dot = { .min = 25000, .max = 350000 },
271 .vco = { .min = 1760000, .max = 3510000 },
272 .n = { .min = 1, .max = 2 },
273 .m = { .min = 79, .max = 126 },
274 .m1 = { .min = 12, .max = 22 },
275 .m2 = { .min = 5, .max = 9 },
276 .p = { .min = 28, .max = 112 },
0206e353 277 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 278 .p2 = { .dot_limit = 225000,
279 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 280};
281
282static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 1760000, .max = 3510000 },
285 .n = { .min = 1, .max = 3 },
286 .m = { .min = 79, .max = 126 },
287 .m1 = { .min = 12, .max = 22 },
288 .m2 = { .min = 5, .max = 9 },
289 .p = { .min = 14, .max = 42 },
0206e353 290 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 291 .p2 = { .dot_limit = 225000,
292 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 293};
294
a0c4da24
JB		 295static const intel_limit_t intel_limits_vlv_dac = {
296 .dot = { .min = 25000, .max = 270000 },
297 .vco = { .min = 4000000, .max = 6000000 },
298 .n = { .min = 1, .max = 7 },
299 .m = { .min = 22, .max = 450 }, /* guess */
300 .m1 = { .min = 2, .max = 3 },
301 .m2 = { .min = 11, .max = 156 },
302 .p = { .min = 10, .max = 30 },
75e53986 303 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 304 .p2 = { .dot_limit = 270000,
305 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 306};
307
308static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 309 .dot = { .min = 25000, .max = 270000 },
310 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 311 .n = { .min = 1, .max = 7 },
312 .m = { .min = 60, .max = 300 }, /* guess */
313 .m1 = { .min = 2, .max = 3 },
314 .m2 = { .min = 11, .max = 156 },
315 .p = { .min = 10, .max = 30 },
316 .p1 = { .min = 2, .max = 3 },
317 .p2 = { .dot_limit = 270000,
318 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 319};
320
321static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 322 .dot = { .min = 25000, .max = 270000 },
323 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 324 .n = { .min = 1, .max = 7 },
74a4dd2e 325 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 326 .m1 = { .min = 2, .max = 3 },
327 .m2 = { .min = 11, .max = 156 },
328 .p = { .min = 10, .max = 30 },
75e53986 329 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 330 .p2 = { .dot_limit = 270000,
331 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 332};
333
1b894b59
CW		 334static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
335 int refclk)
2c07245f 336{
b91ad0ec 337 struct drm_device *dev = crtc->dev;
2c07245f 338 const intel_limit_t *limit;
b91ad0ec
ZW		 339
340 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 341 if (intel_is_dual_link_lvds(dev)) {
1b894b59 342 if (refclk == 100000)
b91ad0ec
ZW		 343 limit = &intel_limits_ironlake_dual_lvds_100m;
344 else
345 limit = &intel_limits_ironlake_dual_lvds;
346 } else {
1b894b59 347 if (refclk == 100000)
b91ad0ec
ZW		 348 limit = &intel_limits_ironlake_single_lvds_100m;
349 else
350 limit = &intel_limits_ironlake_single_lvds;
351 }
c6bb3538 352 } else
b91ad0ec 353 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 354
355 return limit;
356}
357
044c7c41
ML		 358static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
359{
360 struct drm_device *dev = crtc->dev;
044c7c41
ML		 361 const intel_limit_t *limit;
362
363 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 364 if (intel_is_dual_link_lvds(dev))
e4b36699 365 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 366 else
e4b36699 367 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 368 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
369 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 370 limit = &intel_limits_g4x_hdmi;
044c7c41 371 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 372 limit = &intel_limits_g4x_sdvo;
044c7c41 373 } else /* The option is for other outputs */
e4b36699 374 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 375
376 return limit;
377}
378
1b894b59 379static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 380{
381 struct drm_device *dev = crtc->dev;
382 const intel_limit_t *limit;
383
bad720ff 384 if (HAS_PCH_SPLIT(dev))
1b894b59 385 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 386 else if (IS_G4X(dev)) {
044c7c41 387 limit = intel_g4x_limit(crtc);
f2b115e6 388 } else if (IS_PINEVIEW(dev)) {
2177832f 389 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 390 limit = &intel_limits_pineview_lvds;
2177832f 391 else
f2b115e6 392 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 393 } else if (IS_VALLEYVIEW(dev)) {
394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
395 limit = &intel_limits_vlv_dac;
396 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
397 limit = &intel_limits_vlv_hdmi;
398 else
399 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 400 } else if (!IS_GEN2(dev)) {
401 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
402 limit = &intel_limits_i9xx_lvds;
403 else
404 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 405 } else {
406 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 407 limit = &intel_limits_i8xx_lvds;
79e53945 408 else
e4b36699 409 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 410 }
411 return limit;
412}
413
f2b115e6
AJ		 414/* m1 is reserved as 0 in Pineview, n is a ring counter */
415static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 416{
2177832f
SL		 417 clock->m = clock->m2 + 2;
418 clock->p = clock->p1 * clock->p2;
419 clock->vco = refclk * clock->m / clock->n;
420 clock->dot = clock->vco / clock->p;
421}
422
7429e9d4
DV		 423static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
424{
425 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
426}
427
ac58c3f0 428static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 429{
7429e9d4 430 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 431 clock->p = clock->p1 * clock->p2;
432 clock->vco = refclk * clock->m / (clock->n + 2);
433 clock->dot = clock->vco / clock->p;
434}
435
79e53945
JB		 436/**
437 * Returns whether any output on the specified pipe is of the specified type
438 */
4ef69c7a 439bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 440{
4ef69c7a 441 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 442 struct intel_encoder *encoder;
443
6c2b7c12
DV		 444 for_each_encoder_on_crtc(dev, crtc, encoder)
445 if (encoder->type == type)
4ef69c7a
CW		 446 return true;
447
448 return false;
79e53945
JB		 449}
450
7c04d1d9 451#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 452/**
453 * Returns whether the given set of divisors are valid for a given refclk with
454 * the given connectors.
455 */
456
1b894b59
CW		 457static bool intel_PLL_is_valid(struct drm_device *dev,
458 const intel_limit_t *limit,
459 const intel_clock_t *clock)
79e53945 460{
79e53945 461 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 462 INTELPllInvalid("p1 out of range\n");
79e53945 463 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 464 INTELPllInvalid("p out of range\n");
79e53945 465 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 466 INTELPllInvalid("m2 out of range\n");
79e53945 467 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 468 INTELPllInvalid("m1 out of range\n");
f2b115e6 469 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 470 INTELPllInvalid("m1 <= m2\n");
79e53945 471 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 472 INTELPllInvalid("m out of range\n");
79e53945 473 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 474 INTELPllInvalid("n out of range\n");
79e53945 475 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 476 INTELPllInvalid("vco out of range\n");
79e53945
JB		 477 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
478 * connector, etc., rather than just a single range.
479 */
480 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 481 INTELPllInvalid("dot out of range\n");
79e53945
JB		 482
483 return true;
484}
485
d4906093 486static bool
ee9300bb 487i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 488 int target, int refclk, intel_clock_t *match_clock,
489 intel_clock_t *best_clock)
ac58c3f0
DV		 490{
491 struct drm_device *dev = crtc->dev;
492 intel_clock_t clock;
493 int err = target;
494
495 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
496 /*
497 * For LVDS just rely on its current settings for dual-channel.
498 * We haven't figured out how to reliably set up different
499 * single/dual channel state, if we even can.
500 */
501 if (intel_is_dual_link_lvds(dev))
502 clock.p2 = limit->p2.p2_fast;
503 else
504 clock.p2 = limit->p2.p2_slow;
505 } else {
506 if (target < limit->p2.dot_limit)
507 clock.p2 = limit->p2.p2_slow;
508 else
509 clock.p2 = limit->p2.p2_fast;
510 }
511
512 memset(best_clock, 0, sizeof(*best_clock));
513
514 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
515 clock.m1++) {
516 for (clock.m2 = limit->m2.min;
517 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 518 if (clock.m2 >= clock.m1)
ac58c3f0
DV		 519 break;
520 for (clock.n = limit->n.min;
521 clock.n <= limit->n.max; clock.n++) {
522 for (clock.p1 = limit->p1.min;
523 clock.p1 <= limit->p1.max; clock.p1++) {
524 int this_err;
d4906093 525
ac58c3f0
DV		 526 i9xx_clock(refclk, &clock);
527 if (!intel_PLL_is_valid(dev, limit,
528 &clock))
529 continue;
530 if (match_clock &&
531 clock.p != match_clock->p)
532 continue;
533
534 this_err = abs(clock.dot - target);
535 if (this_err < err) {
536 *best_clock = clock;
537 err = this_err;
538 }
539 }
540 }
541 }
542 }
543
544 return (err != target);
545}
546
547static bool
ee9300bb
DV		 548pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
549 int target, int refclk, intel_clock_t *match_clock,
550 intel_clock_t *best_clock)
79e53945
JB		 551{
552 struct drm_device *dev = crtc->dev;
79e53945 553 intel_clock_t clock;
79e53945
JB		 554 int err = target;
555
a210b028 556 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 557 /*
a210b028
DV		 558 * For LVDS just rely on its current settings for dual-channel.
559 * We haven't figured out how to reliably set up different
560 * single/dual channel state, if we even can.
79e53945 561 */
1974cad0 562 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 563 clock.p2 = limit->p2.p2_fast;
564 else
565 clock.p2 = limit->p2.p2_slow;
566 } else {
567 if (target < limit->p2.dot_limit)
568 clock.p2 = limit->p2.p2_slow;
569 else
570 clock.p2 = limit->p2.p2_fast;
571 }
572
0206e353 573 memset(best_clock, 0, sizeof(*best_clock));
79e53945 574
42158660
ZY		 575 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
576 clock.m1++) {
577 for (clock.m2 = limit->m2.min;
578 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 579 for (clock.n = limit->n.min;
580 clock.n <= limit->n.max; clock.n++) {
581 for (clock.p1 = limit->p1.min;
582 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 583 int this_err;
584
ac58c3f0 585 pineview_clock(refclk, &clock);
1b894b59
CW		 586 if (!intel_PLL_is_valid(dev, limit,
587 &clock))
79e53945 588 continue;
cec2f356
SP		 589 if (match_clock &&
590 clock.p != match_clock->p)
591 continue;
79e53945
JB		 592
593 this_err = abs(clock.dot - target);
594 if (this_err < err) {
595 *best_clock = clock;
596 err = this_err;
597 }
598 }
599 }
600 }
601 }
602
603 return (err != target);
604}
605
d4906093 606static bool
ee9300bb
DV		 607g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
608 int target, int refclk, intel_clock_t *match_clock,
609 intel_clock_t *best_clock)
d4906093
ML		 610{
611 struct drm_device *dev = crtc->dev;
d4906093
ML		 612 intel_clock_t clock;
613 int max_n;
614 bool found;
6ba770dc
AJ		 615 /* approximately equals target * 0.00585 */
616 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 617 found = false;
618
619 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 620 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 621 clock.p2 = limit->p2.p2_fast;
622 else
623 clock.p2 = limit->p2.p2_slow;
624 } else {
625 if (target < limit->p2.dot_limit)
626 clock.p2 = limit->p2.p2_slow;
627 else
628 clock.p2 = limit->p2.p2_fast;
629 }
630
631 memset(best_clock, 0, sizeof(*best_clock));
632 max_n = limit->n.max;
f77f13e2 633 /* based on hardware requirement, prefer smaller n to precision */
d4906093 634 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 635 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 636 for (clock.m1 = limit->m1.max;
637 clock.m1 >= limit->m1.min; clock.m1--) {
638 for (clock.m2 = limit->m2.max;
639 clock.m2 >= limit->m2.min; clock.m2--) {
640 for (clock.p1 = limit->p1.max;
641 clock.p1 >= limit->p1.min; clock.p1--) {
642 int this_err;
643
ac58c3f0 644 i9xx_clock(refclk, &clock);
1b894b59
CW		 645 if (!intel_PLL_is_valid(dev, limit,
646 &clock))
d4906093 647 continue;
1b894b59
CW		 648
649 this_err = abs(clock.dot - target);
d4906093
ML		 650 if (this_err < err_most) {
651 *best_clock = clock;
652 err_most = this_err;
653 max_n = clock.n;
654 found = true;
655 }
656 }
657 }
658 }
659 }
2c07245f
ZW		 660 return found;
661}
662
a0c4da24 663static bool
ee9300bb
DV		 664vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
665 int target, int refclk, intel_clock_t *match_clock,
666 intel_clock_t *best_clock)
a0c4da24
JB		 667{
668 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
669 u32 m, n, fastclk;
670 u32 updrate, minupdate, fracbits, p;
671 unsigned long bestppm, ppm, absppm;
672 int dotclk, flag;
673
af447bd3 674 flag = 0;
a0c4da24
JB		 675 dotclk = target * 1000;
676 bestppm = 1000000;
677 ppm = absppm = 0;
678 fastclk = dotclk / (2*100);
679 updrate = 0;
680 minupdate = 19200;
681 fracbits = 1;
682 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
683 bestm1 = bestm2 = bestp1 = bestp2 = 0;
684
685 /* based on hardware requirement, prefer smaller n to precision */
686 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
687 updrate = refclk / n;
688 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
689 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
690 if (p2 > 10)
691 p2 = p2 - 1;
692 p = p1 * p2;
693 /* based on hardware requirement, prefer bigger m1,m2 values */
694 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
695 m2 = (((2*(fastclk * p * n / m1 )) +
696 refclk) / (2*refclk));
697 m = m1 * m2;
698 vco = updrate * m;
699 if (vco >= limit->vco.min && vco < limit->vco.max) {
700 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
701 absppm = (ppm > 0) ? ppm : (-ppm);
702 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
703 bestppm = 0;
704 flag = 1;
705 }
706 if (absppm < bestppm - 10) {
707 bestppm = absppm;
708 flag = 1;
709 }
710 if (flag) {
711 bestn = n;
712 bestm1 = m1;
713 bestm2 = m2;
714 bestp1 = p1;
715 bestp2 = p2;
716 flag = 0;
717 }
718 }
719 }
720 }
721 }
722 }
723 best_clock->n = bestn;
724 best_clock->m1 = bestm1;
725 best_clock->m2 = bestm2;
726 best_clock->p1 = bestp1;
727 best_clock->p2 = bestp2;
728
729 return true;
730}
a4fc5ed6 731
a5c961d1
PZ		 732enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
733 enum pipe pipe)
734{
735 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
737
3b117c8f 738 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 739}
740
a928d536
PZ		 741static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
742{
743 struct drm_i915_private *dev_priv = dev->dev_private;
744 u32 frame, frame_reg = PIPEFRAME(pipe);
745
746 frame = I915_READ(frame_reg);
747
748 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
749 DRM_DEBUG_KMS("vblank wait timed out\n");
750}
751
9d0498a2
JB		 752/**
753 * intel_wait_for_vblank - wait for vblank on a given pipe
754 * @dev: drm device
755 * @pipe: pipe to wait for
756 *
757 * Wait for vblank to occur on a given pipe. Needed for various bits of
758 * mode setting code.
759 */
760void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 761{
9d0498a2 762 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 763 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 764
a928d536
PZ		 765 if (INTEL_INFO(dev)->gen >= 5) {
766 ironlake_wait_for_vblank(dev, pipe);
767 return;
768 }
769
300387c0
CW		 770 /* Clear existing vblank status. Note this will clear any other
771 * sticky status fields as well.
772 *
773 * This races with i915_driver_irq_handler() with the result
774 * that either function could miss a vblank event. Here it is not
775 * fatal, as we will either wait upon the next vblank interrupt or
776 * timeout. Generally speaking intel_wait_for_vblank() is only
777 * called during modeset at which time the GPU should be idle and
778 * should *not* be performing page flips and thus not waiting on
779 * vblanks...
780 * Currently, the result of us stealing a vblank from the irq
781 * handler is that a single frame will be skipped during swapbuffers.
782 */
783 I915_WRITE(pipestat_reg,
784 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
785
9d0498a2 786 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 787 if (wait_for(I915_READ(pipestat_reg) &
788 PIPE_VBLANK_INTERRUPT_STATUS,
789 50))
9d0498a2
JB		 790 DRM_DEBUG_KMS("vblank wait timed out\n");
791}
792
ab7ad7f6
KP		 793/*
794 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 795 * @dev: drm device
796 * @pipe: pipe to wait for
797 *
798 * After disabling a pipe, we can't wait for vblank in the usual way,
799 * spinning on the vblank interrupt status bit, since we won't actually
800 * see an interrupt when the pipe is disabled.
801 *
ab7ad7f6
KP		 802 * On Gen4 and above:
803 * wait for the pipe register state bit to turn off
804 *
805 * Otherwise:
806 * wait for the display line value to settle (it usually
807 * ends up stopping at the start of the next frame).
58e10eb9 808 *
9d0498a2 809 */
58e10eb9 810void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 811{
812 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 813 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
814 pipe);
ab7ad7f6
KP		 815
816 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 817 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 818
819 /* Wait for the Pipe State to go off */
58e10eb9
CW		 820 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
821 100))
284637d9 822 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 823 } else {
837ba00f 824 u32 last_line, line_mask;
58e10eb9 825 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 826 unsigned long timeout = jiffies + msecs_to_jiffies(100);
827
837ba00f
PZ		 828 if (IS_GEN2(dev))
829 line_mask = DSL_LINEMASK_GEN2;
830 else
831 line_mask = DSL_LINEMASK_GEN3;
832
ab7ad7f6
KP		 833 /* Wait for the display line to settle */
834 do {
837ba00f 835 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 836 mdelay(5);
837ba00f 837 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 838 time_after(timeout, jiffies));
839 if (time_after(jiffies, timeout))
284637d9 840 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 841 }
79e53945
JB		 842}
843
b0ea7d37
DL		 844/*
845 * ibx_digital_port_connected - is the specified port connected?
846 * @dev_priv: i915 private structure
847 * @port: the port to test
848 *
849 * Returns true if @port is connected, false otherwise.
850 */
851bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
852 struct intel_digital_port *port)
853{
854 u32 bit;
855
c36346e3
DL		 856 if (HAS_PCH_IBX(dev_priv->dev)) {
857 switch(port->port) {
858 case PORT_B:
859 bit = SDE_PORTB_HOTPLUG;
860 break;
861 case PORT_C:
862 bit = SDE_PORTC_HOTPLUG;
863 break;
864 case PORT_D:
865 bit = SDE_PORTD_HOTPLUG;
866 break;
867 default:
868 return true;
869 }
870 } else {
871 switch(port->port) {
872 case PORT_B:
873 bit = SDE_PORTB_HOTPLUG_CPT;
874 break;
875 case PORT_C:
876 bit = SDE_PORTC_HOTPLUG_CPT;
877 break;
878 case PORT_D:
879 bit = SDE_PORTD_HOTPLUG_CPT;
880 break;
881 default:
882 return true;
883 }
b0ea7d37
DL		 884 }
885
886 return I915_READ(SDEISR) & bit;
887}
888
b24e7179
JB		 889static const char *state_string(bool enabled)
890{
891 return enabled ? "on" : "off";
892}
893
894/* Only for pre-ILK configs */
895static void assert_pll(struct drm_i915_private *dev_priv,
896 enum pipe pipe, bool state)
897{
898 int reg;
899 u32 val;
900 bool cur_state;
901
902 reg = DPLL(pipe);
903 val = I915_READ(reg);
904 cur_state = !!(val & DPLL_VCO_ENABLE);
905 WARN(cur_state != state,
906 "PLL state assertion failure (expected %s, current %s)\n",
907 state_string(state), state_string(cur_state));
908}
909#define assert_pll_enabled(d, p) assert_pll(d, p, true)
910#define assert_pll_disabled(d, p) assert_pll(d, p, false)
911
040484af
JB		 912/* For ILK+ */
913static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 914 struct intel_pch_pll *pll,
915 struct intel_crtc *crtc,
916 bool state)
040484af 917{
040484af
JB		 918 u32 val;
919 bool cur_state;
920
9d82aa17
ED		 921 if (HAS_PCH_LPT(dev_priv->dev)) {
922 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
923 return;
924 }
925
92b27b08
CW		 926 if (WARN (!pll,
927 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 928 return;
ee7b9f93 929
92b27b08
CW		 930 val = I915_READ(pll->pll_reg);
931 cur_state = !!(val & DPLL_VCO_ENABLE);
932 WARN(cur_state != state,
933 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
934 pll->pll_reg, state_string(state), state_string(cur_state), val);
935
936 /* Make sure the selected PLL is correctly attached to the transcoder */
937 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 938 u32 pch_dpll;
939
940 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 941 cur_state = pll->pll_reg == _PCH_DPLL_B;
942 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
4bb6f1f3
VS		 943 "PLL[%d] not attached to this transcoder %c: %08x\n",
944 cur_state, pipe_name(crtc->pipe), pch_dpll)) {
92b27b08
CW		 945 cur_state = !!(val >> (4*crtc->pipe + 3));
946 WARN(cur_state != state,
4bb6f1f3 947 "PLL[%d] not %s on this transcoder %c: %08x\n",
92b27b08
CW		 948 pll->pll_reg == _PCH_DPLL_B,
949 state_string(state),
4bb6f1f3 950 pipe_name(crtc->pipe),
92b27b08
CW		 951 val);
952 }
d3ccbe86 953 }
040484af 954}
92b27b08
CW		 955#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
956#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 957
958static void assert_fdi_tx(struct drm_i915_private *dev_priv,
959 enum pipe pipe, bool state)
960{
961 int reg;
962 u32 val;
963 bool cur_state;
ad80a810
PZ		 964 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
965 pipe);
040484af 966
affa9354
PZ		 967 if (HAS_DDI(dev_priv->dev)) {
968 /* DDI does not have a specific FDI_TX register */
ad80a810 969 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 970 val = I915_READ(reg);
ad80a810 971 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 972 } else {
973 reg = FDI_TX_CTL(pipe);
974 val = I915_READ(reg);
975 cur_state = !!(val & FDI_TX_ENABLE);
976 }
040484af
JB		 977 WARN(cur_state != state,
978 "FDI TX state assertion failure (expected %s, current %s)\n",
979 state_string(state), state_string(cur_state));
980}
981#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
982#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
983
984static void assert_fdi_rx(struct drm_i915_private *dev_priv,
985 enum pipe pipe, bool state)
986{
987 int reg;
988 u32 val;
989 bool cur_state;
990
d63fa0dc
PZ		 991 reg = FDI_RX_CTL(pipe);
992 val = I915_READ(reg);
993 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 994 WARN(cur_state != state,
995 "FDI RX state assertion failure (expected %s, current %s)\n",
996 state_string(state), state_string(cur_state));
997}
998#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
999#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1000
1001static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1002 enum pipe pipe)
1003{
1004 int reg;
1005 u32 val;
1006
1007 /* ILK FDI PLL is always enabled */
1008 if (dev_priv->info->gen == 5)
1009 return;
1010
bf507ef7 1011 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1012 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1013 return;
1014
040484af
JB		 1015 reg = FDI_TX_CTL(pipe);
1016 val = I915_READ(reg);
1017 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1018}
1019
1020static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1021 enum pipe pipe)
1022{
1023 int reg;
1024 u32 val;
1025
1026 reg = FDI_RX_CTL(pipe);
1027 val = I915_READ(reg);
1028 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1029}
1030
ea0760cf
JB		 1031static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1032 enum pipe pipe)
1033{
1034 int pp_reg, lvds_reg;
1035 u32 val;
1036 enum pipe panel_pipe = PIPE_A;
0de3b485 1037 bool locked = true;
ea0760cf
JB		 1038
1039 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1040 pp_reg = PCH_PP_CONTROL;
1041 lvds_reg = PCH_LVDS;
1042 } else {
1043 pp_reg = PP_CONTROL;
1044 lvds_reg = LVDS;
1045 }
1046
1047 val = I915_READ(pp_reg);
1048 if (!(val & PANEL_POWER_ON) ||
1049 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1050 locked = false;
1051
1052 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1053 panel_pipe = PIPE_B;
1054
1055 WARN(panel_pipe == pipe && locked,
1056 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1057 pipe_name(pipe));
ea0760cf
JB		 1058}
1059
b840d907
JB		 1060void assert_pipe(struct drm_i915_private *dev_priv,
1061 enum pipe pipe, bool state)
b24e7179
JB		 1062{
1063 int reg;
1064 u32 val;
63d7bbe9 1065 bool cur_state;
702e7a56
PZ		 1066 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1067 pipe);
b24e7179 1068
8e636784
DV		 1069 /* if we need the pipe A quirk it must be always on */
1070 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1071 state = true;
1072
b97186f0
PZ		 1073 if (!intel_display_power_enabled(dev_priv->dev,
1074 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1075 cur_state = false;
1076 } else {
1077 reg = PIPECONF(cpu_transcoder);
1078 val = I915_READ(reg);
1079 cur_state = !!(val & PIPECONF_ENABLE);
1080 }
1081
63d7bbe9
JB		 1082 WARN(cur_state != state,
1083 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1084 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1085}
1086
931872fc
CW		 1087static void assert_plane(struct drm_i915_private *dev_priv,
1088 enum plane plane, bool state)
b24e7179
JB		 1089{
1090 int reg;
1091 u32 val;
931872fc 1092 bool cur_state;
b24e7179
JB		 1093
1094 reg = DSPCNTR(plane);
1095 val = I915_READ(reg);
931872fc
CW		 1096 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1097 WARN(cur_state != state,
1098 "plane %c assertion failure (expected %s, current %s)\n",
1099 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1100}
1101
931872fc
CW		 1102#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1103#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1104
b24e7179
JB		 1105static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1106 enum pipe pipe)
1107{
653e1026 1108 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1109 int reg, i;
1110 u32 val;
1111 int cur_pipe;
1112
653e1026
VS		 1113 /* Primary planes are fixed to pipes on gen4+ */
1114 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1115 reg = DSPCNTR(pipe);
1116 val = I915_READ(reg);
1117 WARN((val & DISPLAY_PLANE_ENABLE),
1118 "plane %c assertion failure, should be disabled but not\n",
1119 plane_name(pipe));
19ec1358 1120 return;
28c05794 1121 }
19ec1358 1122
b24e7179 1123 /* Need to check both planes against the pipe */
653e1026 1124 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
b24e7179
JB		 1125 reg = DSPCNTR(i);
1126 val = I915_READ(reg);
1127 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1128 DISPPLANE_SEL_PIPE_SHIFT;
1129 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1130 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1131 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1132 }
1133}
1134
19332d7a
JB		 1135static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1136 enum pipe pipe)
1137{
20674eef 1138 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1139 int reg, i;
1140 u32 val;
1141
20674eef
VS		 1142 if (IS_VALLEYVIEW(dev)) {
1143 for (i = 0; i < dev_priv->num_plane; i++) {
1144 reg = SPCNTR(pipe, i);
1145 val = I915_READ(reg);
1146 WARN((val & SP_ENABLE),
1147 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1148 sprite_name(pipe, i), pipe_name(pipe));
1149 }
1150 } else if (INTEL_INFO(dev)->gen >= 7) {
1151 reg = SPRCTL(pipe);
1152 val = I915_READ(reg);
1153 WARN((val & SPRITE_ENABLE),
1154 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1155 plane_name(pipe), pipe_name(pipe));
1156 } else if (INTEL_INFO(dev)->gen >= 5) {
1157 reg = DVSCNTR(pipe);
19332d7a 1158 val = I915_READ(reg);
20674eef 1159 WARN((val & DVS_ENABLE),
06da8da2 1160 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1161 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1162 }
1163}
1164
92f2584a
JB		 1165static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1166{
1167 u32 val;
1168 bool enabled;
1169
9d82aa17
ED		 1170 if (HAS_PCH_LPT(dev_priv->dev)) {
1171 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1172 return;
1173 }
1174
92f2584a
JB		 1175 val = I915_READ(PCH_DREF_CONTROL);
1176 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1177 DREF_SUPERSPREAD_SOURCE_MASK));
1178 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1179}
1180
ab9412ba
DV		 1181static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1182 enum pipe pipe)
92f2584a
JB		 1183{
1184 int reg;
1185 u32 val;
1186 bool enabled;
1187
ab9412ba 1188 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1189 val = I915_READ(reg);
1190 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1191 WARN(enabled,
1192 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1193 pipe_name(pipe));
92f2584a
JB		 1194}
1195
4e634389
KP		 1196static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1197 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1198{
1199 if ((val & DP_PORT_EN) == 0)
1200 return false;
1201
1202 if (HAS_PCH_CPT(dev_priv->dev)) {
1203 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1204 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1205 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1206 return false;
1207 } else {
1208 if ((val & DP_PIPE_MASK) != (pipe << 30))
1209 return false;
1210 }
1211 return true;
1212}
1213
1519b995
KP		 1214static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1215 enum pipe pipe, u32 val)
1216{
dc0fa718 1217 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1218 return false;
1219
1220 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1221 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1222 return false;
1223 } else {
dc0fa718 1224 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1225 return false;
1226 }
1227 return true;
1228}
1229
1230static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1231 enum pipe pipe, u32 val)
1232{
1233 if ((val & LVDS_PORT_EN) == 0)
1234 return false;
1235
1236 if (HAS_PCH_CPT(dev_priv->dev)) {
1237 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1238 return false;
1239 } else {
1240 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1241 return false;
1242 }
1243 return true;
1244}
1245
1246static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1247 enum pipe pipe, u32 val)
1248{
1249 if ((val & ADPA_DAC_ENABLE) == 0)
1250 return false;
1251 if (HAS_PCH_CPT(dev_priv->dev)) {
1252 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1253 return false;
1254 } else {
1255 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1256 return false;
1257 }
1258 return true;
1259}
1260
291906f1 1261static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1262 enum pipe pipe, int reg, u32 port_sel)
291906f1 1263{
47a05eca 1264 u32 val = I915_READ(reg);
4e634389 1265 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1266 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1267 reg, pipe_name(pipe));
de9a35ab 1268
75c5da27
DV		 1269 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1270 && (val & DP_PIPEB_SELECT),
de9a35ab 1271 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1272}
1273
1274static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1275 enum pipe pipe, int reg)
1276{
47a05eca 1277 u32 val = I915_READ(reg);
b70ad586 1278 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1279 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1280 reg, pipe_name(pipe));
de9a35ab 1281
dc0fa718 1282 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1283 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1284 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1285}
1286
1287static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1288 enum pipe pipe)
1289{
1290 int reg;
1291 u32 val;
291906f1 1292
f0575e92
KP		 1293 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1294 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1295 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1296
1297 reg = PCH_ADPA;
1298 val = I915_READ(reg);
b70ad586 1299 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1300 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1301 pipe_name(pipe));
291906f1
JB		 1302
1303 reg = PCH_LVDS;
1304 val = I915_READ(reg);
b70ad586 1305 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1306 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1307 pipe_name(pipe));
291906f1 1308
e2debe91
PZ		 1309 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1310 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1311 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1312}
1313
63d7bbe9
JB		 1314/**
1315 * intel_enable_pll - enable a PLL
1316 * @dev_priv: i915 private structure
1317 * @pipe: pipe PLL to enable
1318 *
1319 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1320 * make sure the PLL reg is writable first though, since the panel write
1321 * protect mechanism may be enabled.
1322 *
1323 * Note! This is for pre-ILK only.
7434a255
TR		 1324 *
1325 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1326 */
1327static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1328{
1329 int reg;
1330 u32 val;
1331
58c6eaa2
DV		 1332 assert_pipe_disabled(dev_priv, pipe);
1333
63d7bbe9 1334 /* No really, not for ILK+ */
a0c4da24 1335 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1336
1337 /* PLL is protected by panel, make sure we can write it */
1338 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1339 assert_panel_unlocked(dev_priv, pipe);
1340
1341 reg = DPLL(pipe);
1342 val = I915_READ(reg);
1343 val |= DPLL_VCO_ENABLE;
1344
1345 /* We do this three times for luck */
1346 I915_WRITE(reg, val);
1347 POSTING_READ(reg);
1348 udelay(150); /* wait for warmup */
1349 I915_WRITE(reg, val);
1350 POSTING_READ(reg);
1351 udelay(150); /* wait for warmup */
1352 I915_WRITE(reg, val);
1353 POSTING_READ(reg);
1354 udelay(150); /* wait for warmup */
1355}
1356
1357/**
1358 * intel_disable_pll - disable a PLL
1359 * @dev_priv: i915 private structure
1360 * @pipe: pipe PLL to disable
1361 *
1362 * Disable the PLL for @pipe, making sure the pipe is off first.
1363 *
1364 * Note! This is for pre-ILK only.
1365 */
1366static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1367{
1368 int reg;
1369 u32 val;
1370
1371 /* Don't disable pipe A or pipe A PLLs if needed */
1372 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1373 return;
1374
1375 /* Make sure the pipe isn't still relying on us */
1376 assert_pipe_disabled(dev_priv, pipe);
1377
1378 reg = DPLL(pipe);
1379 val = I915_READ(reg);
1380 val &= ~DPLL_VCO_ENABLE;
1381 I915_WRITE(reg, val);
1382 POSTING_READ(reg);
1383}
1384
89b667f8
JB		 1385void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1386{
1387 u32 port_mask;
1388
1389 if (!port)
1390 port_mask = DPLL_PORTB_READY_MASK;
1391 else
1392 port_mask = DPLL_PORTC_READY_MASK;
1393
1394 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1395 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1396 'B' + port, I915_READ(DPLL(0)));
1397}
1398
92f2584a 1399/**
b6b4e185 1400 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1401 * @dev_priv: i915 private structure
1402 * @pipe: pipe PLL to enable
1403 *
1404 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1405 * drives the transcoder clock.
1406 */
b6b4e185 1407static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1408{
ee7b9f93 1409 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1410 struct intel_pch_pll *pll;
92f2584a
JB		 1411 int reg;
1412 u32 val;
1413
48da64a8 1414 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1415 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1416 pll = intel_crtc->pch_pll;
1417 if (pll == NULL)
1418 return;
1419
1420 if (WARN_ON(pll->refcount == 0))
1421 return;
ee7b9f93
JB		 1422
1423 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1424 pll->pll_reg, pll->active, pll->on,
1425 intel_crtc->base.base.id);
92f2584a
JB		 1426
1427 /* PCH refclock must be enabled first */
1428 assert_pch_refclk_enabled(dev_priv);
1429
ee7b9f93 1430 if (pll->active++ && pll->on) {
92b27b08 1431 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1432 return;
1433 }
1434
1435 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1436
1437 reg = pll->pll_reg;
92f2584a
JB		 1438 val = I915_READ(reg);
1439 val |= DPLL_VCO_ENABLE;
1440 I915_WRITE(reg, val);
1441 POSTING_READ(reg);
1442 udelay(200);
ee7b9f93
JB		 1443
1444 pll->on = true;
92f2584a
JB		 1445}
1446
ee7b9f93 1447static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1448{
ee7b9f93
JB		 1449 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1450 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1451 int reg;
ee7b9f93 1452 u32 val;
4c609cb8 1453
92f2584a
JB		 1454 /* PCH only available on ILK+ */
1455 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1456 if (pll == NULL)
1457 return;
92f2584a 1458
48da64a8
CW		 1459 if (WARN_ON(pll->refcount == 0))
1460 return;
7a419866 1461
ee7b9f93
JB		 1462 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1463 pll->pll_reg, pll->active, pll->on,
1464 intel_crtc->base.base.id);
7a419866 1465
48da64a8 1466 if (WARN_ON(pll->active == 0)) {
92b27b08 1467 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1468 return;
1469 }
1470
ee7b9f93 1471 if (--pll->active) {
92b27b08 1472 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1473 return;
ee7b9f93
JB		 1474 }
1475
1476 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1477
1478 /* Make sure transcoder isn't still depending on us */
ab9412ba 1479 assert_pch_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1480
ee7b9f93 1481 reg = pll->pll_reg;
92f2584a
JB		 1482 val = I915_READ(reg);
1483 val &= ~DPLL_VCO_ENABLE;
1484 I915_WRITE(reg, val);
1485 POSTING_READ(reg);
1486 udelay(200);
ee7b9f93
JB		 1487
1488 pll->on = false;
92f2584a
JB		 1489}
1490
b8a4f404
PZ		 1491static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1492 enum pipe pipe)
040484af 1493{
23670b32 1494 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1495 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1496 uint32_t reg, val, pipeconf_val;
040484af
JB		 1497
1498 /* PCH only available on ILK+ */
1499 BUG_ON(dev_priv->info->gen < 5);
1500
1501 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1502 assert_pch_pll_enabled(dev_priv,
1503 to_intel_crtc(crtc)->pch_pll,
1504 to_intel_crtc(crtc));
040484af
JB		 1505
1506 /* FDI must be feeding us bits for PCH ports */
1507 assert_fdi_tx_enabled(dev_priv, pipe);
1508 assert_fdi_rx_enabled(dev_priv, pipe);
1509
23670b32
DV		 1510 if (HAS_PCH_CPT(dev)) {
1511 /* Workaround: Set the timing override bit before enabling the
1512 * pch transcoder. */
1513 reg = TRANS_CHICKEN2(pipe);
1514 val = I915_READ(reg);
1515 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1516 I915_WRITE(reg, val);
59c859d6 1517 }
23670b32 1518
ab9412ba 1519 reg = PCH_TRANSCONF(pipe);
040484af 1520 val = I915_READ(reg);
5f7f726d 1521 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1522
1523 if (HAS_PCH_IBX(dev_priv->dev)) {
1524 /*
1525 * make the BPC in transcoder be consistent with
1526 * that in pipeconf reg.
1527 */
dfd07d72
DV		 1528 val &= ~PIPECONF_BPC_MASK;
1529 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1530 }
5f7f726d
PZ		 1531
1532 val &= ~TRANS_INTERLACE_MASK;
1533 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1534 if (HAS_PCH_IBX(dev_priv->dev) &&
1535 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1536 val |= TRANS_LEGACY_INTERLACED_ILK;
1537 else
1538 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1539 else
1540 val |= TRANS_PROGRESSIVE;
1541
040484af
JB		 1542 I915_WRITE(reg, val | TRANS_ENABLE);
1543 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1544 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1545}
1546
8fb033d7 1547static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1548 enum transcoder cpu_transcoder)
040484af 1549{
8fb033d7 1550 u32 val, pipeconf_val;
8fb033d7
PZ		 1551
1552 /* PCH only available on ILK+ */
1553 BUG_ON(dev_priv->info->gen < 5);
1554
8fb033d7 1555 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1556 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1557 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1558
223a6fdf
PZ		 1559 /* Workaround: set timing override bit. */
1560 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1561 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1562 I915_WRITE(_TRANSA_CHICKEN2, val);
1563
25f3ef11 1564 val = TRANS_ENABLE;
937bb610 1565 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1566
9a76b1c6
PZ		 1567 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1568 PIPECONF_INTERLACED_ILK)
a35f2679 1569 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1570 else
1571 val |= TRANS_PROGRESSIVE;
1572
ab9412ba
DV		 1573 I915_WRITE(LPT_TRANSCONF, val);
1574 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1575 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1576}
1577
b8a4f404
PZ		 1578static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1579 enum pipe pipe)
040484af 1580{
23670b32
DV		 1581 struct drm_device *dev = dev_priv->dev;
1582 uint32_t reg, val;
040484af
JB		 1583
1584 /* FDI relies on the transcoder */
1585 assert_fdi_tx_disabled(dev_priv, pipe);
1586 assert_fdi_rx_disabled(dev_priv, pipe);
1587
291906f1
JB		 1588 /* Ports must be off as well */
1589 assert_pch_ports_disabled(dev_priv, pipe);
1590
ab9412ba 1591 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1592 val = I915_READ(reg);
1593 val &= ~TRANS_ENABLE;
1594 I915_WRITE(reg, val);
1595 /* wait for PCH transcoder off, transcoder state */
1596 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1597 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1598
1599 if (!HAS_PCH_IBX(dev)) {
1600 /* Workaround: Clear the timing override chicken bit again. */
1601 reg = TRANS_CHICKEN2(pipe);
1602 val = I915_READ(reg);
1603 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1604 I915_WRITE(reg, val);
1605 }
040484af
JB		 1606}
1607
ab4d966c 1608static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1609{
8fb033d7
PZ		 1610 u32 val;
1611
ab9412ba 1612 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1613 val &= ~TRANS_ENABLE;
ab9412ba 1614 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1615 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1616 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1617 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1618
1619 /* Workaround: clear timing override bit. */
1620 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1621 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1622 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1623}
1624
b24e7179 1625/**
309cfea8 1626 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1627 * @dev_priv: i915 private structure
1628 * @pipe: pipe to enable
040484af 1629 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1630 *
1631 * Enable @pipe, making sure that various hardware specific requirements
1632 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1633 *
1634 * @pipe should be %PIPE_A or %PIPE_B.
1635 *
1636 * Will wait until the pipe is actually running (i.e. first vblank) before
1637 * returning.
1638 */
040484af
JB		 1639static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1640 bool pch_port)
b24e7179 1641{
702e7a56
PZ		 1642 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1643 pipe);
1a240d4d 1644 enum pipe pch_transcoder;
b24e7179
JB		 1645 int reg;
1646 u32 val;
1647
58c6eaa2
DV		 1648 assert_planes_disabled(dev_priv, pipe);
1649 assert_sprites_disabled(dev_priv, pipe);
1650
681e5811 1651 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1652 pch_transcoder = TRANSCODER_A;
1653 else
1654 pch_transcoder = pipe;
1655
b24e7179
JB		 1656 /*
1657 * A pipe without a PLL won't actually be able to drive bits from
1658 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1659 * need the check.
1660 */
1661 if (!HAS_PCH_SPLIT(dev_priv->dev))
1662 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1663 else {
1664 if (pch_port) {
1665 /* if driving the PCH, we need FDI enabled */
cc391bbb 1666 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1667 assert_fdi_tx_pll_enabled(dev_priv,
1668 (enum pipe) cpu_transcoder);
040484af
JB		 1669 }
1670 /* FIXME: assert CPU port conditions for SNB+ */
1671 }
b24e7179 1672
702e7a56 1673 reg = PIPECONF(cpu_transcoder);
b24e7179 1674 val = I915_READ(reg);
00d70b15
CW		 1675 if (val & PIPECONF_ENABLE)
1676 return;
1677
1678 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1679 intel_wait_for_vblank(dev_priv->dev, pipe);
1680}
1681
1682/**
309cfea8 1683 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1684 * @dev_priv: i915 private structure
1685 * @pipe: pipe to disable
1686 *
1687 * Disable @pipe, making sure that various hardware specific requirements
1688 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1689 *
1690 * @pipe should be %PIPE_A or %PIPE_B.
1691 *
1692 * Will wait until the pipe has shut down before returning.
1693 */
1694static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1695 enum pipe pipe)
1696{
702e7a56
PZ		 1697 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1698 pipe);
b24e7179
JB		 1699 int reg;
1700 u32 val;
1701
1702 /*
1703 * Make sure planes won't keep trying to pump pixels to us,
1704 * or we might hang the display.
1705 */
1706 assert_planes_disabled(dev_priv, pipe);
19332d7a 1707 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1708
1709 /* Don't disable pipe A or pipe A PLLs if needed */
1710 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1711 return;
1712
702e7a56 1713 reg = PIPECONF(cpu_transcoder);
b24e7179 1714 val = I915_READ(reg);
00d70b15
CW		 1715 if ((val & PIPECONF_ENABLE) == 0)
1716 return;
1717
1718 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1719 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1720}
1721
d74362c9
KP		 1722/*
1723 * Plane regs are double buffered, going from enabled->disabled needs a
1724 * trigger in order to latch. The display address reg provides this.
1725 */
6f1d69b0 1726void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1727 enum plane plane)
1728{
14f86147
DL		 1729 if (dev_priv->info->gen >= 4)
1730 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1731 else
1732 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1733}
1734
b24e7179
JB		 1735/**
1736 * intel_enable_plane - enable a display plane on a given pipe
1737 * @dev_priv: i915 private structure
1738 * @plane: plane to enable
1739 * @pipe: pipe being fed
1740 *
1741 * Enable @plane on @pipe, making sure that @pipe is running first.
1742 */
1743static void intel_enable_plane(struct drm_i915_private *dev_priv,
1744 enum plane plane, enum pipe pipe)
1745{
1746 int reg;
1747 u32 val;
1748
1749 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1750 assert_pipe_enabled(dev_priv, pipe);
1751
1752 reg = DSPCNTR(plane);
1753 val = I915_READ(reg);
00d70b15
CW		 1754 if (val & DISPLAY_PLANE_ENABLE)
1755 return;
1756
1757 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1758 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1759 intel_wait_for_vblank(dev_priv->dev, pipe);
1760}
1761
b24e7179
JB		 1762/**
1763 * intel_disable_plane - disable a display plane
1764 * @dev_priv: i915 private structure
1765 * @plane: plane to disable
1766 * @pipe: pipe consuming the data
1767 *
1768 * Disable @plane; should be an independent operation.
1769 */
1770static void intel_disable_plane(struct drm_i915_private *dev_priv,
1771 enum plane plane, enum pipe pipe)
1772{
1773 int reg;
1774 u32 val;
1775
1776 reg = DSPCNTR(plane);
1777 val = I915_READ(reg);
00d70b15
CW		 1778 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1779 return;
1780
1781 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1782 intel_flush_display_plane(dev_priv, plane);
1783 intel_wait_for_vblank(dev_priv->dev, pipe);
1784}
1785
693db184
CW		 1786static bool need_vtd_wa(struct drm_device *dev)
1787{
1788#ifdef CONFIG_INTEL_IOMMU
1789 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1790 return true;
1791#endif
1792 return false;
1793}
1794
127bd2ac 1795int
48b956c5 1796intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1797 struct drm_i915_gem_object *obj,
919926ae 1798 struct intel_ring_buffer *pipelined)
6b95a207 1799{
ce453d81 1800 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1801 u32 alignment;
1802 int ret;
1803
05394f39 1804 switch (obj->tiling_mode) {
6b95a207 1805 case I915_TILING_NONE:
534843da
CW		 1806 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1807 alignment = 128 * 1024;
a6c45cf0 1808 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1809 alignment = 4 * 1024;
1810 else
1811 alignment = 64 * 1024;
6b95a207
KH		 1812 break;
1813 case I915_TILING_X:
1814 /* pin() will align the object as required by fence */
1815 alignment = 0;
1816 break;
1817 case I915_TILING_Y:
8bb6e959
DV		 1818 /* Despite that we check this in framebuffer_init userspace can
1819 * screw us over and change the tiling after the fact. Only
1820 * pinned buffers can't change their tiling. */
1821 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1822 return -EINVAL;
1823 default:
1824 BUG();
1825 }
1826
693db184
CW		 1827 /* Note that the w/a also requires 64 PTE of padding following the
1828 * bo. We currently fill all unused PTE with the shadow page and so
1829 * we should always have valid PTE following the scanout preventing
1830 * the VT-d warning.
1831 */
1832 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1833 alignment = 256 * 1024;
1834
ce453d81 1835 dev_priv->mm.interruptible = false;
2da3b9b9 1836 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1837 if (ret)
ce453d81 1838 goto err_interruptible;
6b95a207
KH		 1839
1840 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1841 * fence, whereas 965+ only requires a fence if using
1842 * framebuffer compression. For simplicity, we always install
1843 * a fence as the cost is not that onerous.
1844 */
06d98131 1845 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1846 if (ret)
1847 goto err_unpin;
1690e1eb 1848
9a5a53b3 1849 i915_gem_object_pin_fence(obj);
6b95a207 1850
ce453d81 1851 dev_priv->mm.interruptible = true;
6b95a207 1852 return 0;
48b956c5
CW		 1853
1854err_unpin:
1855 i915_gem_object_unpin(obj);
ce453d81
CW		 1856err_interruptible:
1857 dev_priv->mm.interruptible = true;
48b956c5 1858 return ret;
6b95a207
KH		 1859}
1860
1690e1eb
CW		 1861void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1862{
1863 i915_gem_object_unpin_fence(obj);
1864 i915_gem_object_unpin(obj);
1865}
1866
c2c75131
DV		 1867/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1868 * is assumed to be a power-of-two. */
bc752862
CW		 1869unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1870 unsigned int tiling_mode,
1871 unsigned int cpp,
1872 unsigned int pitch)
c2c75131 1873{
bc752862
CW		 1874 if (tiling_mode != I915_TILING_NONE) {
1875 unsigned int tile_rows, tiles;
c2c75131 1876
bc752862
CW		 1877 tile_rows = *y / 8;
1878 *y %= 8;
c2c75131 1879
bc752862
CW		 1880 tiles = *x / (512/cpp);
1881 *x %= 512/cpp;
1882
1883 return tile_rows * pitch * 8 + tiles * 4096;
1884 } else {
1885 unsigned int offset;
1886
1887 offset = *y * pitch + *x * cpp;
1888 *y = 0;
1889 *x = (offset & 4095) / cpp;
1890 return offset & -4096;
1891 }
c2c75131
DV		 1892}
1893
17638cd6
JB		 1894static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1895 int x, int y)
81255565
JB		 1896{
1897 struct drm_device *dev = crtc->dev;
1898 struct drm_i915_private *dev_priv = dev->dev_private;
1899 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1900 struct intel_framebuffer *intel_fb;
05394f39 1901 struct drm_i915_gem_object *obj;
81255565 1902 int plane = intel_crtc->plane;
e506a0c6 1903 unsigned long linear_offset;
81255565 1904 u32 dspcntr;
5eddb70b 1905 u32 reg;
81255565
JB		 1906
1907 switch (plane) {
1908 case 0:
1909 case 1:
1910 break;
1911 default:
84f44ce7 1912 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1913 return -EINVAL;
1914 }
1915
1916 intel_fb = to_intel_framebuffer(fb);
1917 obj = intel_fb->obj;
81255565 1918
5eddb70b
CW		 1919 reg = DSPCNTR(plane);
1920 dspcntr = I915_READ(reg);
81255565
JB		 1921 /* Mask out pixel format bits in case we change it */
1922 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1923 switch (fb->pixel_format) {
1924 case DRM_FORMAT_C8:
81255565
JB		 1925 dspcntr |= DISPPLANE_8BPP;
1926 break;
57779d06
VS		 1927 case DRM_FORMAT_XRGB1555:
1928 case DRM_FORMAT_ARGB1555:
1929 dspcntr |= DISPPLANE_BGRX555;
81255565 1930 break;
57779d06
VS		 1931 case DRM_FORMAT_RGB565:
1932 dspcntr |= DISPPLANE_BGRX565;
1933 break;
1934 case DRM_FORMAT_XRGB8888:
1935 case DRM_FORMAT_ARGB8888:
1936 dspcntr |= DISPPLANE_BGRX888;
1937 break;
1938 case DRM_FORMAT_XBGR8888:
1939 case DRM_FORMAT_ABGR8888:
1940 dspcntr |= DISPPLANE_RGBX888;
1941 break;
1942 case DRM_FORMAT_XRGB2101010:
1943 case DRM_FORMAT_ARGB2101010:
1944 dspcntr |= DISPPLANE_BGRX101010;
1945 break;
1946 case DRM_FORMAT_XBGR2101010:
1947 case DRM_FORMAT_ABGR2101010:
1948 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 1949 break;
1950 default:
baba133a 1951 BUG();
81255565 1952 }
57779d06 1953
a6c45cf0 1954 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1955 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1956 dspcntr |= DISPPLANE_TILED;
1957 else
1958 dspcntr &= ~DISPPLANE_TILED;
1959 }
1960
de1aa629
VS		 1961 if (IS_G4X(dev))
1962 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1963
5eddb70b 1964 I915_WRITE(reg, dspcntr);
81255565 1965
e506a0c6 1966 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 1967
c2c75131
DV		 1968 if (INTEL_INFO(dev)->gen >= 4) {
1969 intel_crtc->dspaddr_offset =
bc752862
CW		 1970 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1971 fb->bits_per_pixel / 8,
1972 fb->pitches[0]);
c2c75131
DV		 1973 linear_offset -= intel_crtc->dspaddr_offset;
1974 } else {
e506a0c6 1975 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 1976 }
e506a0c6
DV		 1977
1978 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
1979 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 1980 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 1981 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 1982 I915_MODIFY_DISPBASE(DSPSURF(plane),
1983 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 1984 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 1985 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 1986 } else
e506a0c6 1987 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 1988 POSTING_READ(reg);
81255565 1989
17638cd6
JB		 1990 return 0;
1991}
1992
1993static int ironlake_update_plane(struct drm_crtc *crtc,
1994 struct drm_framebuffer *fb, int x, int y)
1995{
1996 struct drm_device *dev = crtc->dev;
1997 struct drm_i915_private *dev_priv = dev->dev_private;
1998 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1999 struct intel_framebuffer *intel_fb;
2000 struct drm_i915_gem_object *obj;
2001 int plane = intel_crtc->plane;
e506a0c6 2002 unsigned long linear_offset;
17638cd6
JB		 2003 u32 dspcntr;
2004 u32 reg;
2005
2006 switch (plane) {
2007 case 0:
2008 case 1:
27f8227b 2009 case 2:
17638cd6
JB		 2010 break;
2011 default:
84f44ce7 2012 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2013 return -EINVAL;
2014 }
2015
2016 intel_fb = to_intel_framebuffer(fb);
2017 obj = intel_fb->obj;
2018
2019 reg = DSPCNTR(plane);
2020 dspcntr = I915_READ(reg);
2021 /* Mask out pixel format bits in case we change it */
2022 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2023 switch (fb->pixel_format) {
2024 case DRM_FORMAT_C8:
17638cd6
JB		 2025 dspcntr |= DISPPLANE_8BPP;
2026 break;
57779d06
VS		 2027 case DRM_FORMAT_RGB565:
2028 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2029 break;
57779d06
VS		 2030 case DRM_FORMAT_XRGB8888:
2031 case DRM_FORMAT_ARGB8888:
2032 dspcntr |= DISPPLANE_BGRX888;
2033 break;
2034 case DRM_FORMAT_XBGR8888:
2035 case DRM_FORMAT_ABGR8888:
2036 dspcntr |= DISPPLANE_RGBX888;
2037 break;
2038 case DRM_FORMAT_XRGB2101010:
2039 case DRM_FORMAT_ARGB2101010:
2040 dspcntr |= DISPPLANE_BGRX101010;
2041 break;
2042 case DRM_FORMAT_XBGR2101010:
2043 case DRM_FORMAT_ABGR2101010:
2044 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2045 break;
2046 default:
baba133a 2047 BUG();
17638cd6
JB		 2048 }
2049
2050 if (obj->tiling_mode != I915_TILING_NONE)
2051 dspcntr |= DISPPLANE_TILED;
2052 else
2053 dspcntr &= ~DISPPLANE_TILED;
2054
2055 /* must disable */
2056 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2057
2058 I915_WRITE(reg, dspcntr);
2059
e506a0c6 2060 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2061 intel_crtc->dspaddr_offset =
bc752862
CW		 2062 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2063 fb->bits_per_pixel / 8,
2064 fb->pitches[0]);
c2c75131 2065 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2066
e506a0c6
DV		 2067 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2068 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2069 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2070 I915_MODIFY_DISPBASE(DSPSURF(plane),
2071 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2072 if (IS_HASWELL(dev)) {
2073 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2074 } else {
2075 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2076 I915_WRITE(DSPLINOFF(plane), linear_offset);
2077 }
17638cd6
JB		 2078 POSTING_READ(reg);
2079
2080 return 0;
2081}
2082
2083/* Assume fb object is pinned & idle & fenced and just update base pointers */
2084static int
2085intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2086 int x, int y, enum mode_set_atomic state)
2087{
2088 struct drm_device *dev = crtc->dev;
2089 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2090
6b8e6ed0
CW		 2091 if (dev_priv->display.disable_fbc)
2092 dev_priv->display.disable_fbc(dev);
3dec0095 2093 intel_increase_pllclock(crtc);
81255565 2094
6b8e6ed0 2095 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2096}
2097
96a02917
VS		 2098void intel_display_handle_reset(struct drm_device *dev)
2099{
2100 struct drm_i915_private *dev_priv = dev->dev_private;
2101 struct drm_crtc *crtc;
2102
2103 /*
2104 * Flips in the rings have been nuked by the reset,
2105 * so complete all pending flips so that user space
2106 * will get its events and not get stuck.
2107 *
2108 * Also update the base address of all primary
2109 * planes to the the last fb to make sure we're
2110 * showing the correct fb after a reset.
2111 *
2112 * Need to make two loops over the crtcs so that we
2113 * don't try to grab a crtc mutex before the
2114 * pending_flip_queue really got woken up.
2115 */
2116
2117 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2118 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2119 enum plane plane = intel_crtc->plane;
2120
2121 intel_prepare_page_flip(dev, plane);
2122 intel_finish_page_flip_plane(dev, plane);
2123 }
2124
2125 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2126 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2127
2128 mutex_lock(&crtc->mutex);
2129 if (intel_crtc->active)
2130 dev_priv->display.update_plane(crtc, crtc->fb,
2131 crtc->x, crtc->y);
2132 mutex_unlock(&crtc->mutex);
2133 }
2134}
2135
14667a4b
CW		 2136static int
2137intel_finish_fb(struct drm_framebuffer *old_fb)
2138{
2139 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2140 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2141 bool was_interruptible = dev_priv->mm.interruptible;
2142 int ret;
2143
14667a4b
CW		 2144 /* Big Hammer, we also need to ensure that any pending
2145 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2146 * current scanout is retired before unpinning the old
2147 * framebuffer.
2148 *
2149 * This should only fail upon a hung GPU, in which case we
2150 * can safely continue.
2151 */
2152 dev_priv->mm.interruptible = false;
2153 ret = i915_gem_object_finish_gpu(obj);
2154 dev_priv->mm.interruptible = was_interruptible;
2155
2156 return ret;
2157}
2158
198598d0
VS		 2159static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2160{
2161 struct drm_device *dev = crtc->dev;
2162 struct drm_i915_master_private *master_priv;
2163 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2164
2165 if (!dev->primary->master)
2166 return;
2167
2168 master_priv = dev->primary->master->driver_priv;
2169 if (!master_priv->sarea_priv)
2170 return;
2171
2172 switch (intel_crtc->pipe) {
2173 case 0:
2174 master_priv->sarea_priv->pipeA_x = x;
2175 master_priv->sarea_priv->pipeA_y = y;
2176 break;
2177 case 1:
2178 master_priv->sarea_priv->pipeB_x = x;
2179 master_priv->sarea_priv->pipeB_y = y;
2180 break;
2181 default:
2182 break;
2183 }
2184}
2185
5c3b82e2 2186static int
3c4fdcfb 2187intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2188 struct drm_framebuffer *fb)
79e53945
JB		 2189{
2190 struct drm_device *dev = crtc->dev;
6b8e6ed0 2191 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2192 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2193 struct drm_framebuffer *old_fb;
5c3b82e2 2194 int ret;
79e53945
JB		 2195
2196 /* no fb bound */
94352cf9 2197 if (!fb) {
a5071c2f 2198 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2199 return 0;
2200 }
2201
7eb552ae 2202 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2203 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2204 plane_name(intel_crtc->plane),
2205 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2206 return -EINVAL;
79e53945
JB		 2207 }
2208
5c3b82e2 2209 mutex_lock(&dev->struct_mutex);
265db958 2210 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2211 to_intel_framebuffer(fb)->obj,
919926ae 2212 NULL);
5c3b82e2
CW		 2213 if (ret != 0) {
2214 mutex_unlock(&dev->struct_mutex);
a5071c2f 2215 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2216 return ret;
2217 }
79e53945 2218
94352cf9 2219 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2220 if (ret) {
94352cf9 2221 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2222 mutex_unlock(&dev->struct_mutex);
a5071c2f 2223 DRM_ERROR("failed to update base address\n");
4e6cfefc 2224 return ret;
79e53945 2225 }
3c4fdcfb 2226
94352cf9
DV		 2227 old_fb = crtc->fb;
2228 crtc->fb = fb;
6c4c86f5
DV		 2229 crtc->x = x;
2230 crtc->y = y;
94352cf9 2231
b7f1de28 2232 if (old_fb) {
d7697eea
DV		 2233 if (intel_crtc->active && old_fb != fb)
2234 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2235 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2236 }
652c393a 2237
6b8e6ed0 2238 intel_update_fbc(dev);
5c3b82e2 2239 mutex_unlock(&dev->struct_mutex);
79e53945 2240
198598d0 2241 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2242
2243 return 0;
79e53945
JB		 2244}
2245
5e84e1a4
ZW		 2246static void intel_fdi_normal_train(struct drm_crtc *crtc)
2247{
2248 struct drm_device *dev = crtc->dev;
2249 struct drm_i915_private *dev_priv = dev->dev_private;
2250 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2251 int pipe = intel_crtc->pipe;
2252 u32 reg, temp;
2253
2254 /* enable normal train */
2255 reg = FDI_TX_CTL(pipe);
2256 temp = I915_READ(reg);
61e499bf 2257 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2258 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2259 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2260 } else {
2261 temp &= ~FDI_LINK_TRAIN_NONE;
2262 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2263 }
5e84e1a4
ZW		 2264 I915_WRITE(reg, temp);
2265
2266 reg = FDI_RX_CTL(pipe);
2267 temp = I915_READ(reg);
2268 if (HAS_PCH_CPT(dev)) {
2269 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2270 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2271 } else {
2272 temp &= ~FDI_LINK_TRAIN_NONE;
2273 temp |= FDI_LINK_TRAIN_NONE;
2274 }
2275 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2276
2277 /* wait one idle pattern time */
2278 POSTING_READ(reg);
2279 udelay(1000);
357555c0
JB		 2280
2281 /* IVB wants error correction enabled */
2282 if (IS_IVYBRIDGE(dev))
2283 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2284 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2285}
2286
1e833f40
DV		 2287static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2288{
2289 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2290}
2291
01a415fd
DV		 2292static void ivb_modeset_global_resources(struct drm_device *dev)
2293{
2294 struct drm_i915_private *dev_priv = dev->dev_private;
2295 struct intel_crtc *pipe_B_crtc =
2296 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2297 struct intel_crtc *pipe_C_crtc =
2298 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2299 uint32_t temp;
2300
1e833f40
DV		 2301 /*
2302 * When everything is off disable fdi C so that we could enable fdi B
2303 * with all lanes. Note that we don't care about enabled pipes without
2304 * an enabled pch encoder.
2305 */
2306 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2307 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2308 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2309 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2310
2311 temp = I915_READ(SOUTH_CHICKEN1);
2312 temp &= ~FDI_BC_BIFURCATION_SELECT;
2313 DRM_DEBUG_KMS("disabling fdi C rx\n");
2314 I915_WRITE(SOUTH_CHICKEN1, temp);
2315 }
2316}
2317
8db9d77b
ZW		 2318/* The FDI link training functions for ILK/Ibexpeak. */
2319static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2320{
2321 struct drm_device *dev = crtc->dev;
2322 struct drm_i915_private *dev_priv = dev->dev_private;
2323 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2324 int pipe = intel_crtc->pipe;
0fc932b8 2325 int plane = intel_crtc->plane;
5eddb70b 2326 u32 reg, temp, tries;
8db9d77b 2327
0fc932b8
JB		 2328 /* FDI needs bits from pipe & plane first */
2329 assert_pipe_enabled(dev_priv, pipe);
2330 assert_plane_enabled(dev_priv, plane);
2331
e1a44743
AJ		 2332 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2333 for train result */
5eddb70b
CW		 2334 reg = FDI_RX_IMR(pipe);
2335 temp = I915_READ(reg);
e1a44743
AJ		 2336 temp &= ~FDI_RX_SYMBOL_LOCK;
2337 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2338 I915_WRITE(reg, temp);
2339 I915_READ(reg);
e1a44743
AJ		 2340 udelay(150);
2341
8db9d77b 2342 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2343 reg = FDI_TX_CTL(pipe);
2344 temp = I915_READ(reg);
627eb5a3
DV		 2345 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2346 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2347 temp &= ~FDI_LINK_TRAIN_NONE;
2348 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2349 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2350
5eddb70b
CW		 2351 reg = FDI_RX_CTL(pipe);
2352 temp = I915_READ(reg);
8db9d77b
ZW		 2353 temp &= ~FDI_LINK_TRAIN_NONE;
2354 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2355 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2356
2357 POSTING_READ(reg);
8db9d77b
ZW		 2358 udelay(150);
2359
5b2adf89 2360 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2361 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2362 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2363 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2364
5eddb70b 2365 reg = FDI_RX_IIR(pipe);
e1a44743 2366 for (tries = 0; tries < 5; tries++) {
5eddb70b 2367 temp = I915_READ(reg);
8db9d77b
ZW		 2368 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2369
2370 if ((temp & FDI_RX_BIT_LOCK)) {
2371 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2372 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2373 break;
2374 }
8db9d77b 2375 }
e1a44743 2376 if (tries == 5)
5eddb70b 2377 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2378
2379 /* Train 2 */
5eddb70b
CW		 2380 reg = FDI_TX_CTL(pipe);
2381 temp = I915_READ(reg);
8db9d77b
ZW		 2382 temp &= ~FDI_LINK_TRAIN_NONE;
2383 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2384 I915_WRITE(reg, temp);
8db9d77b 2385
5eddb70b
CW		 2386 reg = FDI_RX_CTL(pipe);
2387 temp = I915_READ(reg);
8db9d77b
ZW		 2388 temp &= ~FDI_LINK_TRAIN_NONE;
2389 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2390 I915_WRITE(reg, temp);
8db9d77b 2391
5eddb70b
CW		 2392 POSTING_READ(reg);
2393 udelay(150);
8db9d77b 2394
5eddb70b 2395 reg = FDI_RX_IIR(pipe);
e1a44743 2396 for (tries = 0; tries < 5; tries++) {
5eddb70b 2397 temp = I915_READ(reg);
8db9d77b
ZW		 2398 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2399
2400 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2401 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2402 DRM_DEBUG_KMS("FDI train 2 done.\n");
2403 break;
2404 }
8db9d77b 2405 }
e1a44743 2406 if (tries == 5)
5eddb70b 2407 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2408
2409 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2410
8db9d77b
ZW		 2411}
2412
0206e353 2413static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2414 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2415 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2416 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2417 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2418};
2419
2420/* The FDI link training functions for SNB/Cougarpoint. */
2421static void gen6_fdi_link_train(struct drm_crtc *crtc)
2422{
2423 struct drm_device *dev = crtc->dev;
2424 struct drm_i915_private *dev_priv = dev->dev_private;
2425 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2426 int pipe = intel_crtc->pipe;
fa37d39e 2427 u32 reg, temp, i, retry;
8db9d77b 2428
e1a44743
AJ		 2429 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2430 for train result */
5eddb70b
CW		 2431 reg = FDI_RX_IMR(pipe);
2432 temp = I915_READ(reg);
e1a44743
AJ		 2433 temp &= ~FDI_RX_SYMBOL_LOCK;
2434 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2435 I915_WRITE(reg, temp);
2436
2437 POSTING_READ(reg);
e1a44743
AJ		 2438 udelay(150);
2439
8db9d77b 2440 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2441 reg = FDI_TX_CTL(pipe);
2442 temp = I915_READ(reg);
627eb5a3
DV		 2443 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2444 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2445 temp &= ~FDI_LINK_TRAIN_NONE;
2446 temp |= FDI_LINK_TRAIN_PATTERN_1;
2447 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2448 /* SNB-B */
2449 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2450 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2451
d74cf324
DV		 2452 I915_WRITE(FDI_RX_MISC(pipe),
2453 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2454
5eddb70b
CW		 2455 reg = FDI_RX_CTL(pipe);
2456 temp = I915_READ(reg);
8db9d77b
ZW		 2457 if (HAS_PCH_CPT(dev)) {
2458 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2459 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2460 } else {
2461 temp &= ~FDI_LINK_TRAIN_NONE;
2462 temp |= FDI_LINK_TRAIN_PATTERN_1;
2463 }
5eddb70b
CW		 2464 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2465
2466 POSTING_READ(reg);
8db9d77b
ZW		 2467 udelay(150);
2468
0206e353 2469 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2470 reg = FDI_TX_CTL(pipe);
2471 temp = I915_READ(reg);
8db9d77b
ZW		 2472 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2473 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2474 I915_WRITE(reg, temp);
2475
2476 POSTING_READ(reg);
8db9d77b
ZW		 2477 udelay(500);
2478
fa37d39e
SP		 2479 for (retry = 0; retry < 5; retry++) {
2480 reg = FDI_RX_IIR(pipe);
2481 temp = I915_READ(reg);
2482 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2483 if (temp & FDI_RX_BIT_LOCK) {
2484 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2485 DRM_DEBUG_KMS("FDI train 1 done.\n");
2486 break;
2487 }
2488 udelay(50);
8db9d77b 2489 }
fa37d39e
SP		 2490 if (retry < 5)
2491 break;
8db9d77b
ZW		 2492 }
2493 if (i == 4)
5eddb70b 2494 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2495
2496 /* Train 2 */
5eddb70b
CW		 2497 reg = FDI_TX_CTL(pipe);
2498 temp = I915_READ(reg);
8db9d77b
ZW		 2499 temp &= ~FDI_LINK_TRAIN_NONE;
2500 temp |= FDI_LINK_TRAIN_PATTERN_2;
2501 if (IS_GEN6(dev)) {
2502 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2503 /* SNB-B */
2504 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2505 }
5eddb70b 2506 I915_WRITE(reg, temp);
8db9d77b 2507
5eddb70b
CW		 2508 reg = FDI_RX_CTL(pipe);
2509 temp = I915_READ(reg);
8db9d77b
ZW		 2510 if (HAS_PCH_CPT(dev)) {
2511 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2512 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2513 } else {
2514 temp &= ~FDI_LINK_TRAIN_NONE;
2515 temp |= FDI_LINK_TRAIN_PATTERN_2;
2516 }
5eddb70b
CW		 2517 I915_WRITE(reg, temp);
2518
2519 POSTING_READ(reg);
8db9d77b
ZW		 2520 udelay(150);
2521
0206e353 2522 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2523 reg = FDI_TX_CTL(pipe);
2524 temp = I915_READ(reg);
8db9d77b
ZW		 2525 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2526 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2527 I915_WRITE(reg, temp);
2528
2529 POSTING_READ(reg);
8db9d77b
ZW		 2530 udelay(500);
2531
fa37d39e
SP		 2532 for (retry = 0; retry < 5; retry++) {
2533 reg = FDI_RX_IIR(pipe);
2534 temp = I915_READ(reg);
2535 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2536 if (temp & FDI_RX_SYMBOL_LOCK) {
2537 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2538 DRM_DEBUG_KMS("FDI train 2 done.\n");
2539 break;
2540 }
2541 udelay(50);
8db9d77b 2542 }
fa37d39e
SP		 2543 if (retry < 5)
2544 break;
8db9d77b
ZW		 2545 }
2546 if (i == 4)
5eddb70b 2547 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2548
2549 DRM_DEBUG_KMS("FDI train done.\n");
2550}
2551
357555c0
JB		 2552/* Manual link training for Ivy Bridge A0 parts */
2553static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2554{
2555 struct drm_device *dev = crtc->dev;
2556 struct drm_i915_private *dev_priv = dev->dev_private;
2557 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2558 int pipe = intel_crtc->pipe;
2559 u32 reg, temp, i;
2560
2561 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2562 for train result */
2563 reg = FDI_RX_IMR(pipe);
2564 temp = I915_READ(reg);
2565 temp &= ~FDI_RX_SYMBOL_LOCK;
2566 temp &= ~FDI_RX_BIT_LOCK;
2567 I915_WRITE(reg, temp);
2568
2569 POSTING_READ(reg);
2570 udelay(150);
2571
01a415fd
DV		 2572 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2573 I915_READ(FDI_RX_IIR(pipe)));
2574
357555c0
JB		 2575 /* enable CPU FDI TX and PCH FDI RX */
2576 reg = FDI_TX_CTL(pipe);
2577 temp = I915_READ(reg);
627eb5a3
DV		 2578 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2579 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
357555c0
JB		 2580 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2581 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2582 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2583 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2584 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2585 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2586
d74cf324
DV		 2587 I915_WRITE(FDI_RX_MISC(pipe),
2588 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2589
357555c0
JB		 2590 reg = FDI_RX_CTL(pipe);
2591 temp = I915_READ(reg);
2592 temp &= ~FDI_LINK_TRAIN_AUTO;
2593 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2594 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2595 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2596 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2597
2598 POSTING_READ(reg);
2599 udelay(150);
2600
0206e353 2601 for (i = 0; i < 4; i++) {
357555c0
JB		 2602 reg = FDI_TX_CTL(pipe);
2603 temp = I915_READ(reg);
2604 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2605 temp |= snb_b_fdi_train_param[i];
2606 I915_WRITE(reg, temp);
2607
2608 POSTING_READ(reg);
2609 udelay(500);
2610
2611 reg = FDI_RX_IIR(pipe);
2612 temp = I915_READ(reg);
2613 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2614
2615 if (temp & FDI_RX_BIT_LOCK ||
2616 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2617 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2618 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2619 break;
2620 }
2621 }
2622 if (i == 4)
2623 DRM_ERROR("FDI train 1 fail!\n");
2624
2625 /* Train 2 */
2626 reg = FDI_TX_CTL(pipe);
2627 temp = I915_READ(reg);
2628 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2629 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2630 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2631 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2632 I915_WRITE(reg, temp);
2633
2634 reg = FDI_RX_CTL(pipe);
2635 temp = I915_READ(reg);
2636 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2637 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2638 I915_WRITE(reg, temp);
2639
2640 POSTING_READ(reg);
2641 udelay(150);
2642
0206e353 2643 for (i = 0; i < 4; i++) {
357555c0
JB		 2644 reg = FDI_TX_CTL(pipe);
2645 temp = I915_READ(reg);
2646 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2647 temp |= snb_b_fdi_train_param[i];
2648 I915_WRITE(reg, temp);
2649
2650 POSTING_READ(reg);
2651 udelay(500);
2652
2653 reg = FDI_RX_IIR(pipe);
2654 temp = I915_READ(reg);
2655 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2656
2657 if (temp & FDI_RX_SYMBOL_LOCK) {
2658 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2659 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2660 break;
2661 }
2662 }
2663 if (i == 4)
2664 DRM_ERROR("FDI train 2 fail!\n");
2665
2666 DRM_DEBUG_KMS("FDI train done.\n");
2667}
2668
88cefb6c 2669static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2670{
88cefb6c 2671 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2672 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2673 int pipe = intel_crtc->pipe;
5eddb70b 2674 u32 reg, temp;
79e53945 2675
c64e311e 2676
c98e9dcf 2677 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2678 reg = FDI_RX_CTL(pipe);
2679 temp = I915_READ(reg);
627eb5a3
DV		 2680 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2681 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2682 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2683 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2684
2685 POSTING_READ(reg);
c98e9dcf
JB		 2686 udelay(200);
2687
2688 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2689 temp = I915_READ(reg);
2690 I915_WRITE(reg, temp | FDI_PCDCLK);
2691
2692 POSTING_READ(reg);
c98e9dcf
JB		 2693 udelay(200);
2694
20749730
PZ		 2695 /* Enable CPU FDI TX PLL, always on for Ironlake */
2696 reg = FDI_TX_CTL(pipe);
2697 temp = I915_READ(reg);
2698 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2699 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2700
20749730
PZ		 2701 POSTING_READ(reg);
2702 udelay(100);
6be4a607 2703 }
0e23b99d
JB		 2704}
2705
88cefb6c
DV		 2706static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2707{
2708 struct drm_device *dev = intel_crtc->base.dev;
2709 struct drm_i915_private *dev_priv = dev->dev_private;
2710 int pipe = intel_crtc->pipe;
2711 u32 reg, temp;
2712
2713 /* Switch from PCDclk to Rawclk */
2714 reg = FDI_RX_CTL(pipe);
2715 temp = I915_READ(reg);
2716 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2717
2718 /* Disable CPU FDI TX PLL */
2719 reg = FDI_TX_CTL(pipe);
2720 temp = I915_READ(reg);
2721 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2722
2723 POSTING_READ(reg);
2724 udelay(100);
2725
2726 reg = FDI_RX_CTL(pipe);
2727 temp = I915_READ(reg);
2728 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2729
2730 /* Wait for the clocks to turn off. */
2731 POSTING_READ(reg);
2732 udelay(100);
2733}
2734
0fc932b8
JB		 2735static void ironlake_fdi_disable(struct drm_crtc *crtc)
2736{
2737 struct drm_device *dev = crtc->dev;
2738 struct drm_i915_private *dev_priv = dev->dev_private;
2739 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2740 int pipe = intel_crtc->pipe;
2741 u32 reg, temp;
2742
2743 /* disable CPU FDI tx and PCH FDI rx */
2744 reg = FDI_TX_CTL(pipe);
2745 temp = I915_READ(reg);
2746 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2747 POSTING_READ(reg);
2748
2749 reg = FDI_RX_CTL(pipe);
2750 temp = I915_READ(reg);
2751 temp &= ~(0x7 << 16);
dfd07d72 2752 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2753 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2754
2755 POSTING_READ(reg);
2756 udelay(100);
2757
2758 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2759 if (HAS_PCH_IBX(dev)) {
2760 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2761 }
0fc932b8
JB		 2762
2763 /* still set train pattern 1 */
2764 reg = FDI_TX_CTL(pipe);
2765 temp = I915_READ(reg);
2766 temp &= ~FDI_LINK_TRAIN_NONE;
2767 temp |= FDI_LINK_TRAIN_PATTERN_1;
2768 I915_WRITE(reg, temp);
2769
2770 reg = FDI_RX_CTL(pipe);
2771 temp = I915_READ(reg);
2772 if (HAS_PCH_CPT(dev)) {
2773 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2774 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2775 } else {
2776 temp &= ~FDI_LINK_TRAIN_NONE;
2777 temp |= FDI_LINK_TRAIN_PATTERN_1;
2778 }
2779 /* BPC in FDI rx is consistent with that in PIPECONF */
2780 temp &= ~(0x07 << 16);
dfd07d72 2781 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2782 I915_WRITE(reg, temp);
2783
2784 POSTING_READ(reg);
2785 udelay(100);
2786}
2787
5bb61643
CW		 2788static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2789{
2790 struct drm_device *dev = crtc->dev;
2791 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2792 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2793 unsigned long flags;
2794 bool pending;
2795
10d83730
VS		 2796 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2797 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2798 return false;
2799
2800 spin_lock_irqsave(&dev->event_lock, flags);
2801 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2802 spin_unlock_irqrestore(&dev->event_lock, flags);
2803
2804 return pending;
2805}
2806
e6c3a2a6
CW		 2807static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2808{
0f91128d 2809 struct drm_device *dev = crtc->dev;
5bb61643 2810 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2811
2812 if (crtc->fb == NULL)
2813 return;
2814
2c10d571
DV		 2815 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2816
5bb61643
CW		 2817 wait_event(dev_priv->pending_flip_queue,
2818 !intel_crtc_has_pending_flip(crtc));
2819
0f91128d
CW		 2820 mutex_lock(&dev->struct_mutex);
2821 intel_finish_fb(crtc->fb);
2822 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2823}
2824
e615efe4
ED		 2825/* Program iCLKIP clock to the desired frequency */
2826static void lpt_program_iclkip(struct drm_crtc *crtc)
2827{
2828 struct drm_device *dev = crtc->dev;
2829 struct drm_i915_private *dev_priv = dev->dev_private;
2830 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2831 u32 temp;
2832
09153000
DV		 2833 mutex_lock(&dev_priv->dpio_lock);
2834
e615efe4
ED		 2835 /* It is necessary to ungate the pixclk gate prior to programming
2836 * the divisors, and gate it back when it is done.
2837 */
2838 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2839
2840 /* Disable SSCCTL */
2841 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2842 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2843 SBI_SSCCTL_DISABLE,
2844 SBI_ICLK);
e615efe4
ED		 2845
2846 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2847 if (crtc->mode.clock == 20000) {
2848 auxdiv = 1;
2849 divsel = 0x41;
2850 phaseinc = 0x20;
2851 } else {
2852 /* The iCLK virtual clock root frequency is in MHz,
2853 * but the crtc->mode.clock in in KHz. To get the divisors,
2854 * it is necessary to divide one by another, so we
2855 * convert the virtual clock precision to KHz here for higher
2856 * precision.
2857 */
2858 u32 iclk_virtual_root_freq = 172800 * 1000;
2859 u32 iclk_pi_range = 64;
2860 u32 desired_divisor, msb_divisor_value, pi_value;
2861
2862 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2863 msb_divisor_value = desired_divisor / iclk_pi_range;
2864 pi_value = desired_divisor % iclk_pi_range;
2865
2866 auxdiv = 0;
2867 divsel = msb_divisor_value - 2;
2868 phaseinc = pi_value;
2869 }
2870
2871 /* This should not happen with any sane values */
2872 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2873 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2874 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2875 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2876
2877 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2878 crtc->mode.clock,
2879 auxdiv,
2880 divsel,
2881 phasedir,
2882 phaseinc);
2883
2884 /* Program SSCDIVINTPHASE6 */
988d6ee8 2885 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2886 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2887 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2888 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2889 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2890 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2891 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2892 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2893
2894 /* Program SSCAUXDIV */
988d6ee8 2895 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2896 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2897 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2898 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2899
2900 /* Enable modulator and associated divider */
988d6ee8 2901 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2902 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2903 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2904
2905 /* Wait for initialization time */
2906 udelay(24);
2907
2908 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2909
2910 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2911}
2912
275f01b2
DV		 2913static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2914 enum pipe pch_transcoder)
2915{
2916 struct drm_device *dev = crtc->base.dev;
2917 struct drm_i915_private *dev_priv = dev->dev_private;
2918 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2919
2920 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2921 I915_READ(HTOTAL(cpu_transcoder)));
2922 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2923 I915_READ(HBLANK(cpu_transcoder)));
2924 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2925 I915_READ(HSYNC(cpu_transcoder)));
2926
2927 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2928 I915_READ(VTOTAL(cpu_transcoder)));
2929 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2930 I915_READ(VBLANK(cpu_transcoder)));
2931 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2932 I915_READ(VSYNC(cpu_transcoder)));
2933 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2934 I915_READ(VSYNCSHIFT(cpu_transcoder)));
2935}
2936
f67a559d
JB		 2937/*
2938 * Enable PCH resources required for PCH ports:
2939 * - PCH PLLs
2940 * - FDI training & RX/TX
2941 * - update transcoder timings
2942 * - DP transcoding bits
2943 * - transcoder
2944 */
2945static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2946{
2947 struct drm_device *dev = crtc->dev;
2948 struct drm_i915_private *dev_priv = dev->dev_private;
2949 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2950 int pipe = intel_crtc->pipe;
ee7b9f93 2951 u32 reg, temp;
2c07245f 2952
ab9412ba 2953 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 2954
cd986abb
DV		 2955 /* Write the TU size bits before fdi link training, so that error
2956 * detection works. */
2957 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2958 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2959
c98e9dcf 2960 /* For PCH output, training FDI link */
674cf967 2961 dev_priv->display.fdi_link_train(crtc);
2c07245f 2962
572deb37
DV		 2963 /* XXX: pch pll's can be enabled any time before we enable the PCH
2964 * transcoder, and we actually should do this to not upset any PCH
2965 * transcoder that already use the clock when we share it.
2966 *
2967 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
2968 * unconditionally resets the pll - we need that to have the right LVDS
2969 * enable sequence. */
b6b4e185 2970 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 2971
303b81e0 2972 if (HAS_PCH_CPT(dev)) {
ee7b9f93 2973 u32 sel;
4b645f14 2974
c98e9dcf 2975 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 2976 switch (pipe) {
2977 default:
2978 case 0:
2979 temp |= TRANSA_DPLL_ENABLE;
2980 sel = TRANSA_DPLLB_SEL;
2981 break;
2982 case 1:
2983 temp |= TRANSB_DPLL_ENABLE;
2984 sel = TRANSB_DPLLB_SEL;
2985 break;
2986 case 2:
2987 temp |= TRANSC_DPLL_ENABLE;
2988 sel = TRANSC_DPLLB_SEL;
2989 break;
d64311ab 2990 }
ee7b9f93
JB		 2991 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2992 temp |= sel;
2993 else
2994 temp &= ~sel;
c98e9dcf 2995 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2996 }
5eddb70b 2997
d9b6cb56
JB		 2998 /* set transcoder timing, panel must allow it */
2999 assert_panel_unlocked(dev_priv, pipe);
275f01b2 3000 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 3001
303b81e0 3002 intel_fdi_normal_train(crtc);
5e84e1a4 3003
c98e9dcf
JB		 3004 /* For PCH DP, enable TRANS_DP_CTL */
3005 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3006 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3007 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3008 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3009 reg = TRANS_DP_CTL(pipe);
3010 temp = I915_READ(reg);
3011 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3012 TRANS_DP_SYNC_MASK |
3013 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3014 temp |= (TRANS_DP_OUTPUT_ENABLE |
3015 TRANS_DP_ENH_FRAMING);
9325c9f0 3016 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3017
3018 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3019 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3020 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3021 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3022
3023 switch (intel_trans_dp_port_sel(crtc)) {
3024 case PCH_DP_B:
5eddb70b 3025 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3026 break;
3027 case PCH_DP_C:
5eddb70b 3028 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3029 break;
3030 case PCH_DP_D:
5eddb70b 3031 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3032 break;
3033 default:
e95d41e1 3034 BUG();
32f9d658 3035 }
2c07245f 3036
5eddb70b 3037 I915_WRITE(reg, temp);
6be4a607 3038 }
b52eb4dc 3039
b8a4f404 3040 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3041}
3042
1507e5bd
PZ		 3043static void lpt_pch_enable(struct drm_crtc *crtc)
3044{
3045 struct drm_device *dev = crtc->dev;
3046 struct drm_i915_private *dev_priv = dev->dev_private;
3047 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3048 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3049
ab9412ba 3050 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3051
8c52b5e8 3052 lpt_program_iclkip(crtc);
1507e5bd 3053
0540e488 3054 /* Set transcoder timing. */
275f01b2 3055 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3056
937bb610 3057 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3058}
3059
ee7b9f93
JB		 3060static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3061{
3062 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3063
3064 if (pll == NULL)
3065 return;
3066
3067 if (pll->refcount == 0) {
3068 WARN(1, "bad PCH PLL refcount\n");
3069 return;
3070 }
3071
3072 --pll->refcount;
3073 intel_crtc->pch_pll = NULL;
3074}
3075
3076static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3077{
3078 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3079 struct intel_pch_pll *pll;
3080 int i;
3081
3082 pll = intel_crtc->pch_pll;
3083 if (pll) {
3084 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3085 intel_crtc->base.base.id, pll->pll_reg);
3086 goto prepare;
3087 }
3088
98b6bd99
DV		 3089 if (HAS_PCH_IBX(dev_priv->dev)) {
3090 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3091 i = intel_crtc->pipe;
3092 pll = &dev_priv->pch_plls[i];
3093
3094 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3095 intel_crtc->base.base.id, pll->pll_reg);
3096
3097 goto found;
3098 }
3099
ee7b9f93
JB		 3100 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3101 pll = &dev_priv->pch_plls[i];
3102
3103 /* Only want to check enabled timings first */
3104 if (pll->refcount == 0)
3105 continue;
3106
3107 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3108 fp == I915_READ(pll->fp0_reg)) {
3109 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3110 intel_crtc->base.base.id,
3111 pll->pll_reg, pll->refcount, pll->active);
3112
3113 goto found;
3114 }
3115 }
3116
3117 /* Ok no matching timings, maybe there's a free one? */
3118 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3119 pll = &dev_priv->pch_plls[i];
3120 if (pll->refcount == 0) {
3121 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3122 intel_crtc->base.base.id, pll->pll_reg);
3123 goto found;
3124 }
3125 }
3126
3127 return NULL;
3128
3129found:
3130 intel_crtc->pch_pll = pll;
3131 pll->refcount++;
84f44ce7 3132 DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
ee7b9f93
JB		 3133prepare: /* separate function? */
3134 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3135
e04c7350
CW		 3136 /* Wait for the clocks to stabilize before rewriting the regs */
3137 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3138 POSTING_READ(pll->pll_reg);
3139 udelay(150);
e04c7350
CW		 3140
3141 I915_WRITE(pll->fp0_reg, fp);
3142 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3143 pll->on = false;
3144 return pll;
3145}
3146
a1520318 3147static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3148{
3149 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3150 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3151 u32 temp;
3152
3153 temp = I915_READ(dslreg);
3154 udelay(500);
3155 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3156 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3157 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3158 }
3159}
3160
b074cec8
JB		 3161static void ironlake_pfit_enable(struct intel_crtc *crtc)
3162{
3163 struct drm_device *dev = crtc->base.dev;
3164 struct drm_i915_private *dev_priv = dev->dev_private;
3165 int pipe = crtc->pipe;
3166
0ef37f3f 3167 if (crtc->config.pch_pfit.size) {
b074cec8
JB		 3168 /* Force use of hard-coded filter coefficients
3169 * as some pre-programmed values are broken,
3170 * e.g. x201.
3171 */
3172 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3173 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3174 PF_PIPE_SEL_IVB(pipe));
3175 else
3176 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3177 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3178 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3179 }
3180}
3181
bb53d4ae
VS		 3182static void intel_enable_planes(struct drm_crtc *crtc)
3183{
3184 struct drm_device *dev = crtc->dev;
3185 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3186 struct intel_plane *intel_plane;
3187
3188 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3189 if (intel_plane->pipe == pipe)
3190 intel_plane_restore(&intel_plane->base);
3191}
3192
3193static void intel_disable_planes(struct drm_crtc *crtc)
3194{
3195 struct drm_device *dev = crtc->dev;
3196 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3197 struct intel_plane *intel_plane;
3198
3199 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3200 if (intel_plane->pipe == pipe)
3201 intel_plane_disable(&intel_plane->base);
3202}
3203
f67a559d
JB		 3204static void ironlake_crtc_enable(struct drm_crtc *crtc)
3205{
3206 struct drm_device *dev = crtc->dev;
3207 struct drm_i915_private *dev_priv = dev->dev_private;
3208 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3209 struct intel_encoder *encoder;
f67a559d
JB		 3210 int pipe = intel_crtc->pipe;
3211 int plane = intel_crtc->plane;
3212 u32 temp;
f67a559d 3213
08a48469
DV		 3214 WARN_ON(!crtc->enabled);
3215
f67a559d
JB		 3216 if (intel_crtc->active)
3217 return;
3218
3219 intel_crtc->active = true;
8664281b
PZ		 3220
3221 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3222 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3223
f67a559d
JB		 3224 intel_update_watermarks(dev);
3225
3226 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3227 temp = I915_READ(PCH_LVDS);
3228 if ((temp & LVDS_PORT_EN) == 0)
3229 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3230 }
3231
f67a559d 3232
5bfe2ac0 3233 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3234 /* Note: FDI PLL enabling _must_ be done before we enable the
3235 * cpu pipes, hence this is separate from all the other fdi/pch
3236 * enabling. */
88cefb6c 3237 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3238 } else {
3239 assert_fdi_tx_disabled(dev_priv, pipe);
3240 assert_fdi_rx_disabled(dev_priv, pipe);
3241 }
f67a559d 3242
bf49ec8c
DV		 3243 for_each_encoder_on_crtc(dev, crtc, encoder)
3244 if (encoder->pre_enable)
3245 encoder->pre_enable(encoder);
f67a559d
JB		 3246
3247 /* Enable panel fitting for LVDS */
b074cec8 3248 ironlake_pfit_enable(intel_crtc);
f67a559d 3249
9c54c0dd
JB		 3250 /*
3251 * On ILK+ LUT must be loaded before the pipe is running but with
3252 * clocks enabled
3253 */
3254 intel_crtc_load_lut(crtc);
3255
5bfe2ac0
DV		 3256 intel_enable_pipe(dev_priv, pipe,
3257 intel_crtc->config.has_pch_encoder);
f67a559d 3258 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3259 intel_enable_planes(crtc);
5c38d48c 3260 intel_crtc_update_cursor(crtc, true);
f67a559d 3261
5bfe2ac0 3262 if (intel_crtc->config.has_pch_encoder)
f67a559d 3263 ironlake_pch_enable(crtc);
c98e9dcf 3264
d1ebd816 3265 mutex_lock(&dev->struct_mutex);
bed4a673 3266 intel_update_fbc(dev);
d1ebd816
BW		 3267 mutex_unlock(&dev->struct_mutex);
3268
fa5c73b1
DV		 3269 for_each_encoder_on_crtc(dev, crtc, encoder)
3270 encoder->enable(encoder);
61b77ddd
DV		 3271
3272 if (HAS_PCH_CPT(dev))
a1520318 3273 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3274
3275 /*
3276 * There seems to be a race in PCH platform hw (at least on some
3277 * outputs) where an enabled pipe still completes any pageflip right
3278 * away (as if the pipe is off) instead of waiting for vblank. As soon
3279 * as the first vblank happend, everything works as expected. Hence just
3280 * wait for one vblank before returning to avoid strange things
3281 * happening.
3282 */
3283 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3284}
3285
42db64ef
PZ		 3286/* IPS only exists on ULT machines and is tied to pipe A. */
3287static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3288{
3289 return IS_ULT(crtc->base.dev) && crtc->pipe == PIPE_A;
3290}
3291
3292static void hsw_enable_ips(struct intel_crtc *crtc)
3293{
3294 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3295
3296 if (!crtc->config.ips_enabled)
3297 return;
3298
3299 /* We can only enable IPS after we enable a plane and wait for a vblank.
3300 * We guarantee that the plane is enabled by calling intel_enable_ips
3301 * only after intel_enable_plane. And intel_enable_plane already waits
3302 * for a vblank, so all we need to do here is to enable the IPS bit. */
3303 assert_plane_enabled(dev_priv, crtc->plane);
3304 I915_WRITE(IPS_CTL, IPS_ENABLE);
3305}
3306
3307static void hsw_disable_ips(struct intel_crtc *crtc)
3308{
3309 struct drm_device *dev = crtc->base.dev;
3310 struct drm_i915_private *dev_priv = dev->dev_private;
3311
3312 if (!crtc->config.ips_enabled)
3313 return;
3314
3315 assert_plane_enabled(dev_priv, crtc->plane);
3316 I915_WRITE(IPS_CTL, 0);
3317
3318 /* We need to wait for a vblank before we can disable the plane. */
3319 intel_wait_for_vblank(dev, crtc->pipe);
3320}
3321
4f771f10
PZ		 3322static void haswell_crtc_enable(struct drm_crtc *crtc)
3323{
3324 struct drm_device *dev = crtc->dev;
3325 struct drm_i915_private *dev_priv = dev->dev_private;
3326 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3327 struct intel_encoder *encoder;
3328 int pipe = intel_crtc->pipe;
3329 int plane = intel_crtc->plane;
4f771f10
PZ		 3330
3331 WARN_ON(!crtc->enabled);
3332
3333 if (intel_crtc->active)
3334 return;
3335
3336 intel_crtc->active = true;
8664281b
PZ		 3337
3338 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3339 if (intel_crtc->config.has_pch_encoder)
3340 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3341
4f771f10
PZ		 3342 intel_update_watermarks(dev);
3343
5bfe2ac0 3344 if (intel_crtc->config.has_pch_encoder)
04945641 3345 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3346
3347 for_each_encoder_on_crtc(dev, crtc, encoder)
3348 if (encoder->pre_enable)
3349 encoder->pre_enable(encoder);
3350
1f544388 3351 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3352
1f544388 3353 /* Enable panel fitting for eDP */
b074cec8 3354 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3355
3356 /*
3357 * On ILK+ LUT must be loaded before the pipe is running but with
3358 * clocks enabled
3359 */
3360 intel_crtc_load_lut(crtc);
3361
1f544388 3362 intel_ddi_set_pipe_settings(crtc);
8228c251 3363 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3364
5bfe2ac0
DV		 3365 intel_enable_pipe(dev_priv, pipe,
3366 intel_crtc->config.has_pch_encoder);
4f771f10 3367 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3368 intel_enable_planes(crtc);
5c38d48c 3369 intel_crtc_update_cursor(crtc, true);
4f771f10 3370
42db64ef
PZ		 3371 hsw_enable_ips(intel_crtc);
3372
5bfe2ac0 3373 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3374 lpt_pch_enable(crtc);
4f771f10
PZ		 3375
3376 mutex_lock(&dev->struct_mutex);
3377 intel_update_fbc(dev);
3378 mutex_unlock(&dev->struct_mutex);
3379
4f771f10
PZ		 3380 for_each_encoder_on_crtc(dev, crtc, encoder)
3381 encoder->enable(encoder);
3382
4f771f10
PZ		 3383 /*
3384 * There seems to be a race in PCH platform hw (at least on some
3385 * outputs) where an enabled pipe still completes any pageflip right
3386 * away (as if the pipe is off) instead of waiting for vblank. As soon
3387 * as the first vblank happend, everything works as expected. Hence just
3388 * wait for one vblank before returning to avoid strange things
3389 * happening.
3390 */
3391 intel_wait_for_vblank(dev, intel_crtc->pipe);
3392}
3393
3f8dce3a
DV		 3394static void ironlake_pfit_disable(struct intel_crtc *crtc)
3395{
3396 struct drm_device *dev = crtc->base.dev;
3397 struct drm_i915_private *dev_priv = dev->dev_private;
3398 int pipe = crtc->pipe;
3399
3400 /* To avoid upsetting the power well on haswell only disable the pfit if
3401 * it's in use. The hw state code will make sure we get this right. */
3402 if (crtc->config.pch_pfit.size) {
3403 I915_WRITE(PF_CTL(pipe), 0);
3404 I915_WRITE(PF_WIN_POS(pipe), 0);
3405 I915_WRITE(PF_WIN_SZ(pipe), 0);
3406 }
3407}
3408
6be4a607
JB		 3409static void ironlake_crtc_disable(struct drm_crtc *crtc)
3410{
3411 struct drm_device *dev = crtc->dev;
3412 struct drm_i915_private *dev_priv = dev->dev_private;
3413 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3414 struct intel_encoder *encoder;
6be4a607
JB		 3415 int pipe = intel_crtc->pipe;
3416 int plane = intel_crtc->plane;
5eddb70b 3417 u32 reg, temp;
b52eb4dc 3418
ef9c3aee 3419
f7abfe8b
CW		 3420 if (!intel_crtc->active)
3421 return;
3422
ea9d758d
DV		 3423 for_each_encoder_on_crtc(dev, crtc, encoder)
3424 encoder->disable(encoder);
3425
e6c3a2a6 3426 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3427 drm_vblank_off(dev, pipe);
913d8d11 3428
973d04f9
CW		 3429 if (dev_priv->cfb_plane == plane)
3430 intel_disable_fbc(dev);
2c07245f 3431
0d5b8c61 3432 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3433 intel_disable_planes(crtc);
0d5b8c61
VS		 3434 intel_disable_plane(dev_priv, plane, pipe);
3435
8664281b 3436 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
b24e7179 3437 intel_disable_pipe(dev_priv, pipe);
32f9d658 3438
3f8dce3a 3439 ironlake_pfit_disable(intel_crtc);
2c07245f 3440
bf49ec8c
DV		 3441 for_each_encoder_on_crtc(dev, crtc, encoder)
3442 if (encoder->post_disable)
3443 encoder->post_disable(encoder);
2c07245f 3444
0fc932b8 3445 ironlake_fdi_disable(crtc);
249c0e64 3446
b8a4f404 3447 ironlake_disable_pch_transcoder(dev_priv, pipe);
8664281b 3448 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
913d8d11 3449
6be4a607
JB		 3450 if (HAS_PCH_CPT(dev)) {
3451 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3452 reg = TRANS_DP_CTL(pipe);
3453 temp = I915_READ(reg);
3454 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3455 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3456 I915_WRITE(reg, temp);
6be4a607
JB		 3457
3458 /* disable DPLL_SEL */
3459 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3460 switch (pipe) {
3461 case 0:
d64311ab 3462 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3463 break;
3464 case 1:
6be4a607 3465 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3466 break;
3467 case 2:
4b645f14 3468 /* C shares PLL A or B */
d64311ab 3469 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3470 break;
3471 default:
3472 BUG(); /* wtf */
3473 }
6be4a607 3474 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3475 }
e3421a18 3476
6be4a607 3477 /* disable PCH DPLL */
ee7b9f93 3478 intel_disable_pch_pll(intel_crtc);
8db9d77b 3479
88cefb6c 3480 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3481
f7abfe8b 3482 intel_crtc->active = false;
6b383a7f 3483 intel_update_watermarks(dev);
d1ebd816
BW		 3484
3485 mutex_lock(&dev->struct_mutex);
6b383a7f 3486 intel_update_fbc(dev);
d1ebd816 3487 mutex_unlock(&dev->struct_mutex);
6be4a607 3488}
1b3c7a47 3489
4f771f10 3490static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3491{
4f771f10
PZ		 3492 struct drm_device *dev = crtc->dev;
3493 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3494 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3495 struct intel_encoder *encoder;
3496 int pipe = intel_crtc->pipe;
3497 int plane = intel_crtc->plane;
3b117c8f 3498 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3499
4f771f10
PZ		 3500 if (!intel_crtc->active)
3501 return;
3502
3503 for_each_encoder_on_crtc(dev, crtc, encoder)
3504 encoder->disable(encoder);
3505
3506 intel_crtc_wait_for_pending_flips(crtc);
3507 drm_vblank_off(dev, pipe);
4f771f10 3508
891348b2 3509 /* FBC must be disabled before disabling the plane on HSW. */
4f771f10
PZ		 3510 if (dev_priv->cfb_plane == plane)
3511 intel_disable_fbc(dev);
3512
42db64ef
PZ		 3513 hsw_disable_ips(intel_crtc);
3514
0d5b8c61 3515 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3516 intel_disable_planes(crtc);
891348b2
RV		 3517 intel_disable_plane(dev_priv, plane, pipe);
3518
8664281b
PZ		 3519 if (intel_crtc->config.has_pch_encoder)
3520 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3521 intel_disable_pipe(dev_priv, pipe);
3522
ad80a810 3523 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3524
3f8dce3a 3525 ironlake_pfit_disable(intel_crtc);
4f771f10 3526
1f544388 3527 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3528
3529 for_each_encoder_on_crtc(dev, crtc, encoder)
3530 if (encoder->post_disable)
3531 encoder->post_disable(encoder);
3532
88adfff1 3533 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3534 lpt_disable_pch_transcoder(dev_priv);
8664281b 3535 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3536 intel_ddi_fdi_disable(crtc);
83616634 3537 }
4f771f10
PZ		 3538
3539 intel_crtc->active = false;
3540 intel_update_watermarks(dev);
3541
3542 mutex_lock(&dev->struct_mutex);
3543 intel_update_fbc(dev);
3544 mutex_unlock(&dev->struct_mutex);
3545}
3546
ee7b9f93
JB		 3547static void ironlake_crtc_off(struct drm_crtc *crtc)
3548{
3549 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3550 intel_put_pch_pll(intel_crtc);
3551}
3552
6441ab5f
PZ		 3553static void haswell_crtc_off(struct drm_crtc *crtc)
3554{
3555 intel_ddi_put_crtc_pll(crtc);
3556}
3557
02e792fb
DV		 3558static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3559{
02e792fb 3560 if (!enable && intel_crtc->overlay) {
23f09ce3 3561 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3562 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3563
23f09ce3 3564 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3565 dev_priv->mm.interruptible = false;
3566 (void) intel_overlay_switch_off(intel_crtc->overlay);
3567 dev_priv->mm.interruptible = true;
23f09ce3 3568 mutex_unlock(&dev->struct_mutex);
02e792fb 3569 }
02e792fb 3570
5dcdbcb0
CW		 3571 /* Let userspace switch the overlay on again. In most cases userspace
3572 * has to recompute where to put it anyway.
3573 */
02e792fb
DV		 3574}
3575
61bc95c1
EE		 3576/**
3577 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3578 * cursor plane briefly if not already running after enabling the display
3579 * plane.
3580 * This workaround avoids occasional blank screens when self refresh is
3581 * enabled.
3582 */
3583static void
3584g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3585{
3586 u32 cntl = I915_READ(CURCNTR(pipe));
3587
3588 if ((cntl & CURSOR_MODE) == 0) {
3589 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3590
3591 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3592 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3593 intel_wait_for_vblank(dev_priv->dev, pipe);
3594 I915_WRITE(CURCNTR(pipe), cntl);
3595 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3596 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3597 }
3598}
3599
2dd24552
JB		 3600static void i9xx_pfit_enable(struct intel_crtc *crtc)
3601{
3602 struct drm_device *dev = crtc->base.dev;
3603 struct drm_i915_private *dev_priv = dev->dev_private;
3604 struct intel_crtc_config *pipe_config = &crtc->config;
3605
328d8e82 3606 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3607 return;
3608
2dd24552 3609 /*
c0b03411
DV		 3610 * The panel fitter should only be adjusted whilst the pipe is disabled,
3611 * according to register description and PRM.
2dd24552 3612 */
c0b03411
DV		 3613 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3614 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3615
b074cec8
JB		 3616 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3617 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3618
3619 /* Border color in case we don't scale up to the full screen. Black by
3620 * default, change to something else for debugging. */
3621 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3622}
3623
89b667f8
JB		 3624static void valleyview_crtc_enable(struct drm_crtc *crtc)
3625{
3626 struct drm_device *dev = crtc->dev;
3627 struct drm_i915_private *dev_priv = dev->dev_private;
3628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3629 struct intel_encoder *encoder;
3630 int pipe = intel_crtc->pipe;
3631 int plane = intel_crtc->plane;
3632
3633 WARN_ON(!crtc->enabled);
3634
3635 if (intel_crtc->active)
3636 return;
3637
3638 intel_crtc->active = true;
3639 intel_update_watermarks(dev);
3640
3641 mutex_lock(&dev_priv->dpio_lock);
3642
3643 for_each_encoder_on_crtc(dev, crtc, encoder)
3644 if (encoder->pre_pll_enable)
3645 encoder->pre_pll_enable(encoder);
3646
3647 intel_enable_pll(dev_priv, pipe);
3648
3649 for_each_encoder_on_crtc(dev, crtc, encoder)
3650 if (encoder->pre_enable)
3651 encoder->pre_enable(encoder);
3652
3653 /* VLV wants encoder enabling _before_ the pipe is up. */
3654 for_each_encoder_on_crtc(dev, crtc, encoder)
3655 encoder->enable(encoder);
3656
2dd24552
JB		 3657 /* Enable panel fitting for eDP */
3658 i9xx_pfit_enable(intel_crtc);
3659
63cbb074
VS		 3660 intel_crtc_load_lut(crtc);
3661
89b667f8
JB		 3662 intel_enable_pipe(dev_priv, pipe, false);
3663 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3664 intel_enable_planes(crtc);
5c38d48c 3665 intel_crtc_update_cursor(crtc, true);
89b667f8 3666
f440eb13
VS		 3667 intel_update_fbc(dev);
3668
89b667f8
JB		 3669 mutex_unlock(&dev_priv->dpio_lock);
3670}
3671
0b8765c6 3672static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3673{
3674 struct drm_device *dev = crtc->dev;
79e53945
JB		 3675 struct drm_i915_private *dev_priv = dev->dev_private;
3676 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3677 struct intel_encoder *encoder;
79e53945 3678 int pipe = intel_crtc->pipe;
80824003 3679 int plane = intel_crtc->plane;
79e53945 3680
08a48469
DV		 3681 WARN_ON(!crtc->enabled);
3682
f7abfe8b
CW		 3683 if (intel_crtc->active)
3684 return;
3685
3686 intel_crtc->active = true;
6b383a7f
CW		 3687 intel_update_watermarks(dev);
3688
63d7bbe9 3689 intel_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3690
3691 for_each_encoder_on_crtc(dev, crtc, encoder)
3692 if (encoder->pre_enable)
3693 encoder->pre_enable(encoder);
3694
2dd24552
JB		 3695 /* Enable panel fitting for LVDS */
3696 i9xx_pfit_enable(intel_crtc);
3697
63cbb074
VS		 3698 intel_crtc_load_lut(crtc);
3699
040484af 3700 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3701 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3702 intel_enable_planes(crtc);
5c38d48c 3703 intel_crtc_update_cursor(crtc, true);
61bc95c1
EE		 3704 if (IS_G4X(dev))
3705 g4x_fixup_plane(dev_priv, pipe);
79e53945 3706
0b8765c6
JB		 3707 /* Give the overlay scaler a chance to enable if it's on this pipe */
3708 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3709
f440eb13
VS		 3710 intel_update_fbc(dev);
3711
fa5c73b1
DV		 3712 for_each_encoder_on_crtc(dev, crtc, encoder)
3713 encoder->enable(encoder);
0b8765c6 3714}
79e53945 3715
87476d63
DV		 3716static void i9xx_pfit_disable(struct intel_crtc *crtc)
3717{
3718 struct drm_device *dev = crtc->base.dev;
3719 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3720
328d8e82
DV		 3721 if (!crtc->config.gmch_pfit.control)
3722 return;
87476d63 3723
328d8e82 3724 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3725
328d8e82
DV		 3726 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3727 I915_READ(PFIT_CONTROL));
3728 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3729}
3730
0b8765c6
JB		 3731static void i9xx_crtc_disable(struct drm_crtc *crtc)
3732{
3733 struct drm_device *dev = crtc->dev;
3734 struct drm_i915_private *dev_priv = dev->dev_private;
3735 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3736 struct intel_encoder *encoder;
0b8765c6
JB		 3737 int pipe = intel_crtc->pipe;
3738 int plane = intel_crtc->plane;
ef9c3aee 3739
f7abfe8b
CW		 3740 if (!intel_crtc->active)
3741 return;
3742
ea9d758d
DV		 3743 for_each_encoder_on_crtc(dev, crtc, encoder)
3744 encoder->disable(encoder);
3745
0b8765c6 3746 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3747 intel_crtc_wait_for_pending_flips(crtc);
3748 drm_vblank_off(dev, pipe);
0b8765c6 3749
973d04f9
CW		 3750 if (dev_priv->cfb_plane == plane)
3751 intel_disable_fbc(dev);
79e53945 3752
0d5b8c61
VS		 3753 intel_crtc_dpms_overlay(intel_crtc, false);
3754 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3755 intel_disable_planes(crtc);
b24e7179 3756 intel_disable_plane(dev_priv, plane, pipe);
0d5b8c61 3757
b24e7179 3758 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3759
87476d63 3760 i9xx_pfit_disable(intel_crtc);
24a1f16d 3761
89b667f8
JB		 3762 for_each_encoder_on_crtc(dev, crtc, encoder)
3763 if (encoder->post_disable)
3764 encoder->post_disable(encoder);
3765
63d7bbe9 3766 intel_disable_pll(dev_priv, pipe);
0b8765c6 3767
f7abfe8b 3768 intel_crtc->active = false;
6b383a7f
CW		 3769 intel_update_fbc(dev);
3770 intel_update_watermarks(dev);
0b8765c6
JB		 3771}
3772
ee7b9f93
JB		 3773static void i9xx_crtc_off(struct drm_crtc *crtc)
3774{
3775}
3776
976f8a20
DV		 3777static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3778 bool enabled)
2c07245f
ZW		 3779{
3780 struct drm_device *dev = crtc->dev;
3781 struct drm_i915_master_private *master_priv;
3782 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3783 int pipe = intel_crtc->pipe;
79e53945
JB		 3784
3785 if (!dev->primary->master)
3786 return;
3787
3788 master_priv = dev->primary->master->driver_priv;
3789 if (!master_priv->sarea_priv)
3790 return;
3791
79e53945
JB		 3792 switch (pipe) {
3793 case 0:
3794 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3795 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3796 break;
3797 case 1:
3798 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3799 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3800 break;
3801 default:
9db4a9c7 3802 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3803 break;
3804 }
79e53945
JB		 3805}
3806
976f8a20
DV		 3807/**
3808 * Sets the power management mode of the pipe and plane.
3809 */
3810void intel_crtc_update_dpms(struct drm_crtc *crtc)
3811{
3812 struct drm_device *dev = crtc->dev;
3813 struct drm_i915_private *dev_priv = dev->dev_private;
3814 struct intel_encoder *intel_encoder;
3815 bool enable = false;
3816
3817 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3818 enable |= intel_encoder->connectors_active;
3819
3820 if (enable)
3821 dev_priv->display.crtc_enable(crtc);
3822 else
3823 dev_priv->display.crtc_disable(crtc);
3824
3825 intel_crtc_update_sarea(crtc, enable);
3826}
3827
cdd59983
CW		 3828static void intel_crtc_disable(struct drm_crtc *crtc)
3829{
cdd59983 3830 struct drm_device *dev = crtc->dev;
976f8a20 3831 struct drm_connector *connector;
ee7b9f93 3832 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3833 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3834
976f8a20
DV		 3835 /* crtc should still be enabled when we disable it. */
3836 WARN_ON(!crtc->enabled);
3837
3838 dev_priv->display.crtc_disable(crtc);
c77bf565 3839 intel_crtc->eld_vld = false;
976f8a20 3840 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3841 dev_priv->display.off(crtc);
3842
931872fc
CW		 3843 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3844 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3845
3846 if (crtc->fb) {
3847 mutex_lock(&dev->struct_mutex);
1690e1eb 3848 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3849 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3850 crtc->fb = NULL;
3851 }
3852
3853 /* Update computed state. */
3854 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3855 if (!connector->encoder || !connector->encoder->crtc)
3856 continue;
3857
3858 if (connector->encoder->crtc != crtc)
3859 continue;
3860
3861 connector->dpms = DRM_MODE_DPMS_OFF;
3862 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3863 }
3864}
3865
a261b246 3866void intel_modeset_disable(struct drm_device *dev)
79e53945 3867{
a261b246
DV		 3868 struct drm_crtc *crtc;
3869
3870 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3871 if (crtc->enabled)
3872 intel_crtc_disable(crtc);
3873 }
79e53945
JB		 3874}
3875
ea5b213a 3876void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3877{
4ef69c7a 3878 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3879
ea5b213a
CW		 3880 drm_encoder_cleanup(encoder);
3881 kfree(intel_encoder);
7e7d76c3
JB		 3882}
3883
5ab432ef
DV		 3884/* Simple dpms helper for encodres with just one connector, no cloning and only
3885 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3886 * state of the entire output pipe. */
3887void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3888{
5ab432ef
DV		 3889 if (mode == DRM_MODE_DPMS_ON) {
3890 encoder->connectors_active = true;
3891
b2cabb0e 3892 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3893 } else {
3894 encoder->connectors_active = false;
3895
b2cabb0e 3896 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3897 }
79e53945
JB		 3898}
3899
0a91ca29
DV		 3900/* Cross check the actual hw state with our own modeset state tracking (and it's
3901 * internal consistency). */
b980514c 3902static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3903{
0a91ca29
DV		 3904 if (connector->get_hw_state(connector)) {
3905 struct intel_encoder *encoder = connector->encoder;
3906 struct drm_crtc *crtc;
3907 bool encoder_enabled;
3908 enum pipe pipe;
3909
3910 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3911 connector->base.base.id,
3912 drm_get_connector_name(&connector->base));
3913
3914 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3915 "wrong connector dpms state\n");
3916 WARN(connector->base.encoder != &encoder->base,
3917 "active connector not linked to encoder\n");
3918 WARN(!encoder->connectors_active,
3919 "encoder->connectors_active not set\n");
3920
3921 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3922 WARN(!encoder_enabled, "encoder not enabled\n");
3923 if (WARN_ON(!encoder->base.crtc))
3924 return;
3925
3926 crtc = encoder->base.crtc;
3927
3928 WARN(!crtc->enabled, "crtc not enabled\n");
3929 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3930 WARN(pipe != to_intel_crtc(crtc)->pipe,
3931 "encoder active on the wrong pipe\n");
3932 }
79e53945
JB		 3933}
3934
5ab432ef
DV		 3935/* Even simpler default implementation, if there's really no special case to
3936 * consider. */
3937void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3938{
5ab432ef 3939 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3940
5ab432ef
DV		 3941 /* All the simple cases only support two dpms states. */
3942 if (mode != DRM_MODE_DPMS_ON)
3943 mode = DRM_MODE_DPMS_OFF;
d4270e57 3944
5ab432ef
DV		 3945 if (mode == connector->dpms)
3946 return;
3947
3948 connector->dpms = mode;
3949
3950 /* Only need to change hw state when actually enabled */
3951 if (encoder->base.crtc)
3952 intel_encoder_dpms(encoder, mode);
3953 else
8af6cf88 3954 WARN_ON(encoder->connectors_active != false);
0a91ca29 3955
b980514c 3956 intel_modeset_check_state(connector->dev);
79e53945
JB		 3957}
3958
f0947c37
DV		 3959/* Simple connector->get_hw_state implementation for encoders that support only
3960 * one connector and no cloning and hence the encoder state determines the state
3961 * of the connector. */
3962bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3963{
24929352 3964 enum pipe pipe = 0;
f0947c37 3965 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3966
f0947c37 3967 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3968}
3969
1857e1da
DV		 3970static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3971 struct intel_crtc_config *pipe_config)
3972{
3973 struct drm_i915_private *dev_priv = dev->dev_private;
3974 struct intel_crtc *pipe_B_crtc =
3975 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3976
3977 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3978 pipe_name(pipe), pipe_config->fdi_lanes);
3979 if (pipe_config->fdi_lanes > 4) {
3980 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3981 pipe_name(pipe), pipe_config->fdi_lanes);
3982 return false;
3983 }
3984
3985 if (IS_HASWELL(dev)) {
3986 if (pipe_config->fdi_lanes > 2) {
3987 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3988 pipe_config->fdi_lanes);
3989 return false;
3990 } else {
3991 return true;
3992 }
3993 }
3994
3995 if (INTEL_INFO(dev)->num_pipes == 2)
3996 return true;
3997
3998 /* Ivybridge 3 pipe is really complicated */
3999 switch (pipe) {
4000 case PIPE_A:
4001 return true;
4002 case PIPE_B:
4003 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4004 pipe_config->fdi_lanes > 2) {
4005 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4006 pipe_name(pipe), pipe_config->fdi_lanes);
4007 return false;
4008 }
4009 return true;
4010 case PIPE_C:
1e833f40 4011 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 4012 pipe_B_crtc->config.fdi_lanes <= 2) {
4013 if (pipe_config->fdi_lanes > 2) {
4014 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4015 pipe_name(pipe), pipe_config->fdi_lanes);
4016 return false;
4017 }
4018 } else {
4019 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4020 return false;
4021 }
4022 return true;
4023 default:
4024 BUG();
4025 }
4026}
4027
e29c22c0
DV		 4028#define RETRY 1
4029static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4030 struct intel_crtc_config *pipe_config)
877d48d5 4031{
1857e1da 4032 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 4033 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 4034 int lane, link_bw, fdi_dotclock;
e29c22c0 4035 bool setup_ok, needs_recompute = false;
877d48d5 4036
e29c22c0 4037retry:
877d48d5
DV		 4038 /* FDI is a binary signal running at ~2.7GHz, encoding
4039 * each output octet as 10 bits. The actual frequency
4040 * is stored as a divider into a 100MHz clock, and the
4041 * mode pixel clock is stored in units of 1KHz.
4042 * Hence the bw of each lane in terms of the mode signal
4043 * is:
4044 */
4045 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4046
ff9a6750 4047 fdi_dotclock = adjusted_mode->clock;
ef1b460d 4048 fdi_dotclock /= pipe_config->pixel_multiplier;
2bd89a07
DV		 4049
4050 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4051 pipe_config->pipe_bpp);
4052
4053 pipe_config->fdi_lanes = lane;
4054
2bd89a07 4055 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4056 link_bw, &pipe_config->fdi_m_n);
1857e1da 4057
e29c22c0
DV		 4058 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4059 intel_crtc->pipe, pipe_config);
4060 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4061 pipe_config->pipe_bpp -= 2*3;
4062 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4063 pipe_config->pipe_bpp);
4064 needs_recompute = true;
4065 pipe_config->bw_constrained = true;
4066
4067 goto retry;
4068 }
4069
4070 if (needs_recompute)
4071 return RETRY;
4072
4073 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4074}
4075
42db64ef
PZ		 4076static void hsw_compute_ips_config(struct intel_crtc *crtc,
4077 struct intel_crtc_config *pipe_config)
4078{
3c4ca58c
PZ		 4079 pipe_config->ips_enabled = i915_enable_ips &&
4080 hsw_crtc_supports_ips(crtc) &&
42db64ef
PZ		 4081 pipe_config->pipe_bpp == 24;
4082}
4083
e29c22c0
DV		 4084static int intel_crtc_compute_config(struct drm_crtc *crtc,
4085 struct intel_crtc_config *pipe_config)
79e53945 4086{
2c07245f 4087 struct drm_device *dev = crtc->dev;
b8cecdf5 4088 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
42db64ef 4089 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
89749350 4090
bad720ff 4091 if (HAS_PCH_SPLIT(dev)) {
2c07245f 4092 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 4093 if (pipe_config->requested_mode.clock * 3
4094 > IRONLAKE_FDI_FREQ * 4)
e29c22c0 4095 return -EINVAL;
2c07245f 4096 }
89749350 4097
f9bef081
DV		 4098 /* All interlaced capable intel hw wants timings in frames. Note though
4099 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4100 * timings, so we need to be careful not to clobber these.*/
7ae89233 4101 if (!pipe_config->timings_set)
f9bef081 4102 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 4103
8693a824
DL		 4104 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4105 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4106 */
4107 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4108 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4109 return -EINVAL;
44f46b42 4110
bd080ee5 4111 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4112 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4113 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4114 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4115 * for lvds. */
4116 pipe_config->pipe_bpp = 8*3;
4117 }
4118
42db64ef
PZ		 4119 if (IS_HASWELL(dev))
4120 hsw_compute_ips_config(intel_crtc, pipe_config);
4121
877d48d5 4122 if (pipe_config->has_pch_encoder)
42db64ef 4123 return ironlake_fdi_compute_config(intel_crtc, pipe_config);
877d48d5 4124
e29c22c0 4125 return 0;
79e53945
JB		 4126}
4127
25eb05fc
JB		 4128static int valleyview_get_display_clock_speed(struct drm_device *dev)
4129{
4130 return 400000; /* FIXME */
4131}
4132
e70236a8
JB		 4133static int i945_get_display_clock_speed(struct drm_device *dev)
4134{
4135 return 400000;
4136}
79e53945 4137
e70236a8 4138static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4139{
e70236a8
JB		 4140 return 333000;
4141}
79e53945 4142
e70236a8
JB		 4143static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4144{
4145 return 200000;
4146}
79e53945 4147
e70236a8
JB		 4148static int i915gm_get_display_clock_speed(struct drm_device *dev)
4149{
4150 u16 gcfgc = 0;
79e53945 4151
e70236a8
JB		 4152 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4153
4154 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4155 return 133000;
4156 else {
4157 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4158 case GC_DISPLAY_CLOCK_333_MHZ:
4159 return 333000;
4160 default:
4161 case GC_DISPLAY_CLOCK_190_200_MHZ:
4162 return 190000;
79e53945 4163 }
e70236a8
JB		 4164 }
4165}
4166
4167static int i865_get_display_clock_speed(struct drm_device *dev)
4168{
4169 return 266000;
4170}
4171
4172static int i855_get_display_clock_speed(struct drm_device *dev)
4173{
4174 u16 hpllcc = 0;
4175 /* Assume that the hardware is in the high speed state. This
4176 * should be the default.
4177 */
4178 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4179 case GC_CLOCK_133_200:
4180 case GC_CLOCK_100_200:
4181 return 200000;
4182 case GC_CLOCK_166_250:
4183 return 250000;
4184 case GC_CLOCK_100_133:
79e53945 4185 return 133000;
e70236a8 4186 }
79e53945 4187
e70236a8
JB		 4188 /* Shouldn't happen */
4189 return 0;
4190}
79e53945 4191
e70236a8
JB		 4192static int i830_get_display_clock_speed(struct drm_device *dev)
4193{
4194 return 133000;
79e53945
JB		 4195}
4196
2c07245f 4197static void
a65851af 4198intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4199{
a65851af
VS		 4200 while (*num > DATA_LINK_M_N_MASK ||
4201 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4202 *num >>= 1;
4203 *den >>= 1;
4204 }
4205}
4206
a65851af
VS		 4207static void compute_m_n(unsigned int m, unsigned int n,
4208 uint32_t *ret_m, uint32_t *ret_n)
4209{
4210 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4211 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4212 intel_reduce_m_n_ratio(ret_m, ret_n);
4213}
4214
e69d0bc1
DV		 4215void
4216intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4217 int pixel_clock, int link_clock,
4218 struct intel_link_m_n *m_n)
2c07245f 4219{
e69d0bc1 4220 m_n->tu = 64;
a65851af
VS		 4221
4222 compute_m_n(bits_per_pixel * pixel_clock,
4223 link_clock * nlanes * 8,
4224 &m_n->gmch_m, &m_n->gmch_n);
4225
4226 compute_m_n(pixel_clock, link_clock,
4227 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4228}
4229
a7615030
CW		 4230static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4231{
72bbe58c
KP		 4232 if (i915_panel_use_ssc >= 0)
4233 return i915_panel_use_ssc != 0;
41aa3448 4234 return dev_priv->vbt.lvds_use_ssc
435793df 4235 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4236}
4237
a0c4da24
JB		 4238static int vlv_get_refclk(struct drm_crtc *crtc)
4239{
4240 struct drm_device *dev = crtc->dev;
4241 struct drm_i915_private *dev_priv = dev->dev_private;
4242 int refclk = 27000; /* for DP & HDMI */
4243
4244 return 100000; /* only one validated so far */
4245
4246 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4247 refclk = 96000;
4248 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4249 if (intel_panel_use_ssc(dev_priv))
4250 refclk = 100000;
4251 else
4252 refclk = 96000;
4253 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4254 refclk = 100000;
4255 }
4256
4257 return refclk;
4258}
4259
c65d77d8
JB		 4260static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4261{
4262 struct drm_device *dev = crtc->dev;
4263 struct drm_i915_private *dev_priv = dev->dev_private;
4264 int refclk;
4265
a0c4da24
JB		 4266 if (IS_VALLEYVIEW(dev)) {
4267 refclk = vlv_get_refclk(crtc);
4268 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4269 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4270 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4271 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4272 refclk / 1000);
4273 } else if (!IS_GEN2(dev)) {
4274 refclk = 96000;
4275 } else {
4276 refclk = 48000;
4277 }
4278
4279 return refclk;
4280}
4281
7429e9d4
DV		 4282static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4283{
4284 return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
4285}
4286
4287static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4288{
4289 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4290}
4291
f47709a9 4292static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4293 intel_clock_t *reduced_clock)
4294{
f47709a9 4295 struct drm_device *dev = crtc->base.dev;
a7516a05 4296 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4297 int pipe = crtc->pipe;
a7516a05
JB		 4298 u32 fp, fp2 = 0;
4299
4300 if (IS_PINEVIEW(dev)) {
7429e9d4 4301 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4302 if (reduced_clock)
7429e9d4 4303 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4304 } else {
7429e9d4 4305 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4306 if (reduced_clock)
7429e9d4 4307 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4308 }
4309
4310 I915_WRITE(FP0(pipe), fp);
4311
f47709a9
DV		 4312 crtc->lowfreq_avail = false;
4313 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4314 reduced_clock && i915_powersave) {
4315 I915_WRITE(FP1(pipe), fp2);
f47709a9 4316 crtc->lowfreq_avail = true;
a7516a05
JB		 4317 } else {
4318 I915_WRITE(FP1(pipe), fp);
4319 }
4320}
4321
89b667f8
JB		 4322static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4323{
4324 u32 reg_val;
4325
4326 /*
4327 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4328 * and set it to a reasonable value instead.
4329 */
ae99258f 4330 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8
JB		 4331 reg_val &= 0xffffff00;
4332 reg_val |= 0x00000030;
ae99258f 4333 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4334
ae99258f 4335 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4336 reg_val &= 0x8cffffff;
4337 reg_val = 0x8c000000;
ae99258f 4338 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8 4339
ae99258f 4340 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8 4341 reg_val &= 0xffffff00;
ae99258f 4342 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4343
ae99258f 4344 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4345 reg_val &= 0x00ffffff;
4346 reg_val |= 0xb0000000;
ae99258f 4347 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4348}
4349
b551842d
DV		 4350static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4351 struct intel_link_m_n *m_n)
4352{
4353 struct drm_device *dev = crtc->base.dev;
4354 struct drm_i915_private *dev_priv = dev->dev_private;
4355 int pipe = crtc->pipe;
4356
e3b95f1e
DV		 4357 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4358 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4359 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4360 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4361}
4362
4363static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4364 struct intel_link_m_n *m_n)
4365{
4366 struct drm_device *dev = crtc->base.dev;
4367 struct drm_i915_private *dev_priv = dev->dev_private;
4368 int pipe = crtc->pipe;
4369 enum transcoder transcoder = crtc->config.cpu_transcoder;
4370
4371 if (INTEL_INFO(dev)->gen >= 5) {
4372 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4373 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4374 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4375 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4376 } else {
e3b95f1e
DV		 4377 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4378 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4379 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4380 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4381 }
4382}
4383
03afc4a2
DV		 4384static void intel_dp_set_m_n(struct intel_crtc *crtc)
4385{
4386 if (crtc->config.has_pch_encoder)
4387 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4388 else
4389 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4390}
4391
f47709a9 4392static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4393{
f47709a9 4394 struct drm_device *dev = crtc->base.dev;
a0c4da24 4395 struct drm_i915_private *dev_priv = dev->dev_private;
89b667f8 4396 struct intel_encoder *encoder;
f47709a9 4397 int pipe = crtc->pipe;
89b667f8 4398 u32 dpll, mdiv;
a0c4da24 4399 u32 bestn, bestm1, bestm2, bestp1, bestp2;
89b667f8 4400 bool is_hdmi;
198a037f 4401 u32 coreclk, reg_val, dpll_md;
a0c4da24 4402
09153000
DV		 4403 mutex_lock(&dev_priv->dpio_lock);
4404
89b667f8 4405 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
a0c4da24 4406
f47709a9
DV		 4407 bestn = crtc->config.dpll.n;
4408 bestm1 = crtc->config.dpll.m1;
4409 bestm2 = crtc->config.dpll.m2;
4410 bestp1 = crtc->config.dpll.p1;
4411 bestp2 = crtc->config.dpll.p2;
a0c4da24 4412
89b667f8
JB		 4413 /* See eDP HDMI DPIO driver vbios notes doc */
4414
4415 /* PLL B needs special handling */
4416 if (pipe)
4417 vlv_pllb_recal_opamp(dev_priv);
4418
4419 /* Set up Tx target for periodic Rcomp update */
ae99258f 4420 vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4421
4422 /* Disable target IRef on PLL */
ae99258f 4423 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
89b667f8 4424 reg_val &= 0x00ffffff;
ae99258f 4425 vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4426
4427 /* Disable fast lock */
ae99258f 4428 vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4429
4430 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4431 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4432 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4433 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4434 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4435
4436 /*
4437 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4438 * but we don't support that).
4439 * Note: don't use the DAC post divider as it seems unstable.
4440 */
4441 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ae99258f 4442 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4443
89b667f8 4444 mdiv |= DPIO_ENABLE_CALIBRATION;
ae99258f 4445 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4446
89b667f8 4447 /* Set HBR and RBR LPF coefficients */
ff9a6750 4448 if (crtc->config.port_clock == 162000 ||
89b667f8 4449 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
ae99258f 4450 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
89b667f8
JB		 4451 0x005f0021);
4452 else
ae99258f 4453 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
89b667f8
JB		 4454 0x00d0000f);
4455
4456 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4457 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4458 /* Use SSC source */
4459 if (!pipe)
ae99258f 4460 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4461 0x0df40000);
4462 else
ae99258f 4463 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4464 0x0df70000);
4465 } else { /* HDMI or VGA */
4466 /* Use bend source */
4467 if (!pipe)
ae99258f 4468 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4469 0x0df70000);
4470 else
ae99258f 4471 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4472 0x0df40000);
4473 }
a0c4da24 4474
ae99258f 4475 coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4476 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4477 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4478 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4479 coreclk |= 0x01000000;
ae99258f 4480 vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4481
ae99258f 4482 vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4483
89b667f8
JB		 4484 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4485 if (encoder->pre_pll_enable)
4486 encoder->pre_pll_enable(encoder);
2a8f64ca 4487
89b667f8
JB		 4488 /* Enable DPIO clock input */
4489 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4490 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4491 if (pipe)
4492 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
2a8f64ca 4493
89b667f8 4494 dpll |= DPLL_VCO_ENABLE;
2a8f64ca 4495 I915_WRITE(DPLL(pipe), dpll);
2a8f64ca
VP		 4496 POSTING_READ(DPLL(pipe));
4497 udelay(150);
a0c4da24 4498
89b667f8
JB		 4499 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4500 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4501
ef1b460d
DV		 4502 dpll_md = (crtc->config.pixel_multiplier - 1)
4503 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
198a037f
DV		 4504 I915_WRITE(DPLL_MD(pipe), dpll_md);
4505 POSTING_READ(DPLL_MD(pipe));
f47709a9 4506
89b667f8
JB		 4507 if (crtc->config.has_dp_encoder)
4508 intel_dp_set_m_n(crtc);
09153000
DV		 4509
4510 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4511}
4512
f47709a9
DV		 4513static void i9xx_update_pll(struct intel_crtc *crtc,
4514 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4515 int num_connectors)
4516{
f47709a9 4517 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4518 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4519 struct intel_encoder *encoder;
f47709a9 4520 int pipe = crtc->pipe;
eb1cbe48
DV		 4521 u32 dpll;
4522 bool is_sdvo;
f47709a9 4523 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4524
f47709a9 4525 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4526
f47709a9
DV		 4527 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4528 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4529
4530 dpll = DPLL_VGA_MODE_DIS;
4531
f47709a9 4532 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4533 dpll |= DPLLB_MODE_LVDS;
4534 else
4535 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4536
ef1b460d 4537 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4538 dpll |= (crtc->config.pixel_multiplier - 1)
4539 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4540 }
198a037f
DV		 4541
4542 if (is_sdvo)
4543 dpll |= DPLL_DVO_HIGH_SPEED;
4544
f47709a9 4545 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
eb1cbe48
DV		 4546 dpll |= DPLL_DVO_HIGH_SPEED;
4547
4548 /* compute bitmask from p1 value */
4549 if (IS_PINEVIEW(dev))
4550 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4551 else {
4552 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4553 if (IS_G4X(dev) && reduced_clock)
4554 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4555 }
4556 switch (clock->p2) {
4557 case 5:
4558 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4559 break;
4560 case 7:
4561 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4562 break;
4563 case 10:
4564 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4565 break;
4566 case 14:
4567 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4568 break;
4569 }
4570 if (INTEL_INFO(dev)->gen >= 4)
4571 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4572
09ede541 4573 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4574 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4575 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4576 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4577 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4578 else
4579 dpll |= PLL_REF_INPUT_DREFCLK;
4580
4581 dpll |= DPLL_VCO_ENABLE;
4582 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4583 POSTING_READ(DPLL(pipe));
4584 udelay(150);
4585
f47709a9 4586 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4587 if (encoder->pre_pll_enable)
4588 encoder->pre_pll_enable(encoder);
eb1cbe48 4589
f47709a9
DV		 4590 if (crtc->config.has_dp_encoder)
4591 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4592
4593 I915_WRITE(DPLL(pipe), dpll);
4594
4595 /* Wait for the clocks to stabilize. */
4596 POSTING_READ(DPLL(pipe));
4597 udelay(150);
4598
4599 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4600 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4601 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
198a037f 4602 I915_WRITE(DPLL_MD(pipe), dpll_md);
eb1cbe48
DV		 4603 } else {
4604 /* The pixel multiplier can only be updated once the
4605 * DPLL is enabled and the clocks are stable.
4606 *
4607 * So write it again.
4608 */
4609 I915_WRITE(DPLL(pipe), dpll);
4610 }
4611}
4612
f47709a9 4613static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4614 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4615 int num_connectors)
4616{
f47709a9 4617 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4618 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4619 struct intel_encoder *encoder;
f47709a9 4620 int pipe = crtc->pipe;
eb1cbe48 4621 u32 dpll;
f47709a9 4622 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4623
f47709a9 4624 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4625
eb1cbe48
DV		 4626 dpll = DPLL_VGA_MODE_DIS;
4627
f47709a9 4628 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4629 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4630 } else {
4631 if (clock->p1 == 2)
4632 dpll |= PLL_P1_DIVIDE_BY_TWO;
4633 else
4634 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4635 if (clock->p2 == 4)
4636 dpll |= PLL_P2_DIVIDE_BY_4;
4637 }
4638
f47709a9 4639 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4640 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4641 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4642 else
4643 dpll |= PLL_REF_INPUT_DREFCLK;
4644
4645 dpll |= DPLL_VCO_ENABLE;
4646 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4647 POSTING_READ(DPLL(pipe));
4648 udelay(150);
4649
f47709a9 4650 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4651 if (encoder->pre_pll_enable)
4652 encoder->pre_pll_enable(encoder);
eb1cbe48 4653
5b5896e4
DV		 4654 I915_WRITE(DPLL(pipe), dpll);
4655
4656 /* Wait for the clocks to stabilize. */
4657 POSTING_READ(DPLL(pipe));
4658 udelay(150);
4659
eb1cbe48
DV		 4660 /* The pixel multiplier can only be updated once the
4661 * DPLL is enabled and the clocks are stable.
4662 *
4663 * So write it again.
4664 */
4665 I915_WRITE(DPLL(pipe), dpll);
4666}
4667
8a654f3b 4668static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4669{
4670 struct drm_device *dev = intel_crtc->base.dev;
4671 struct drm_i915_private *dev_priv = dev->dev_private;
4672 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4673 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4674 struct drm_display_mode *adjusted_mode =
4675 &intel_crtc->config.adjusted_mode;
4676 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4d8a62ea
DV		 4677 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4678
4679 /* We need to be careful not to changed the adjusted mode, for otherwise
4680 * the hw state checker will get angry at the mismatch. */
4681 crtc_vtotal = adjusted_mode->crtc_vtotal;
4682 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4683
4684 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4685 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4686 crtc_vtotal -= 1;
4687 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4688 vsyncshift = adjusted_mode->crtc_hsync_start
4689 - adjusted_mode->crtc_htotal / 2;
4690 } else {
4691 vsyncshift = 0;
4692 }
4693
4694 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4695 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4696
fe2b8f9d 4697 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4698 (adjusted_mode->crtc_hdisplay - 1) |
4699 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4700 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4701 (adjusted_mode->crtc_hblank_start - 1) |
4702 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4703 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4704 (adjusted_mode->crtc_hsync_start - 1) |
4705 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4706
fe2b8f9d 4707 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4708 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4709 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4710 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4711 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4712 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4713 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4714 (adjusted_mode->crtc_vsync_start - 1) |
4715 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4716
b5e508d4
PZ		 4717 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4718 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4719 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4720 * bits. */
4721 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4722 (pipe == PIPE_B || pipe == PIPE_C))
4723 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4724
b0e77b9c
PZ		 4725 /* pipesrc controls the size that is scaled from, which should
4726 * always be the user's requested size.
4727 */
4728 I915_WRITE(PIPESRC(pipe),
4729 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4730}
4731
1bd1bd80
DV		 4732static void intel_get_pipe_timings(struct intel_crtc *crtc,
4733 struct intel_crtc_config *pipe_config)
4734{
4735 struct drm_device *dev = crtc->base.dev;
4736 struct drm_i915_private *dev_priv = dev->dev_private;
4737 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4738 uint32_t tmp;
4739
4740 tmp = I915_READ(HTOTAL(cpu_transcoder));
4741 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4742 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4743 tmp = I915_READ(HBLANK(cpu_transcoder));
4744 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4745 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4746 tmp = I915_READ(HSYNC(cpu_transcoder));
4747 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4748 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4749
4750 tmp = I915_READ(VTOTAL(cpu_transcoder));
4751 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4752 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4753 tmp = I915_READ(VBLANK(cpu_transcoder));
4754 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4755 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4756 tmp = I915_READ(VSYNC(cpu_transcoder));
4757 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4758 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4759
4760 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4761 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4762 pipe_config->adjusted_mode.crtc_vtotal += 1;
4763 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4764 }
4765
4766 tmp = I915_READ(PIPESRC(crtc->pipe));
4767 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4768 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4769}
4770
84b046f3
DV		 4771static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4772{
4773 struct drm_device *dev = intel_crtc->base.dev;
4774 struct drm_i915_private *dev_priv = dev->dev_private;
4775 uint32_t pipeconf;
4776
4777 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4778
4779 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4780 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4781 * core speed.
4782 *
4783 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4784 * pipe == 0 check?
4785 */
4786 if (intel_crtc->config.requested_mode.clock >
4787 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4788 pipeconf |= PIPECONF_DOUBLE_WIDE;
4789 else
4790 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4791 }
4792
ff9ce46e
DV		 4793 /* only g4x and later have fancy bpc/dither controls */
4794 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4795 pipeconf &= ~(PIPECONF_BPC_MASK |
4796 PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4797
4798 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4799 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4800 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4801 PIPECONF_DITHER_TYPE_SP;
84b046f3 4802
ff9ce46e
DV		 4803 switch (intel_crtc->config.pipe_bpp) {
4804 case 18:
4805 pipeconf |= PIPECONF_6BPC;
4806 break;
4807 case 24:
4808 pipeconf |= PIPECONF_8BPC;
4809 break;
4810 case 30:
4811 pipeconf |= PIPECONF_10BPC;
4812 break;
4813 default:
4814 /* Case prevented by intel_choose_pipe_bpp_dither. */
4815 BUG();
84b046f3
DV		 4816 }
4817 }
4818
4819 if (HAS_PIPE_CXSR(dev)) {
4820 if (intel_crtc->lowfreq_avail) {
4821 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4822 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4823 } else {
4824 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4825 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4826 }
4827 }
4828
4829 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4830 if (!IS_GEN2(dev) &&
4831 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4832 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4833 else
4834 pipeconf |= PIPECONF_PROGRESSIVE;
4835
9c8e09b7
VS		 4836 if (IS_VALLEYVIEW(dev)) {
4837 if (intel_crtc->config.limited_color_range)
4838 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4839 else
4840 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4841 }
4842
84b046f3
DV		 4843 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4844 POSTING_READ(PIPECONF(intel_crtc->pipe));
4845}
4846
f564048e 4847static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4848 int x, int y,
94352cf9 4849 struct drm_framebuffer *fb)
79e53945
JB		 4850{
4851 struct drm_device *dev = crtc->dev;
4852 struct drm_i915_private *dev_priv = dev->dev_private;
4853 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 4854 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4855 int pipe = intel_crtc->pipe;
80824003 4856 int plane = intel_crtc->plane;
c751ce4f 4857 int refclk, num_connectors = 0;
652c393a 4858 intel_clock_t clock, reduced_clock;
84b046f3 4859 u32 dspcntr;
a16af721
DV		 4860 bool ok, has_reduced_clock = false;
4861 bool is_lvds = false;
5eddb70b 4862 struct intel_encoder *encoder;
d4906093 4863 const intel_limit_t *limit;
5c3b82e2 4864 int ret;
79e53945 4865
6c2b7c12 4866 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4867 switch (encoder->type) {
79e53945
JB		 4868 case INTEL_OUTPUT_LVDS:
4869 is_lvds = true;
4870 break;
79e53945 4871 }
43565a06 4872
c751ce4f 4873 num_connectors++;
79e53945
JB		 4874 }
4875
c65d77d8 4876 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4877
d4906093
ML		 4878 /*
4879 * Returns a set of divisors for the desired target clock with the given
4880 * refclk, or FALSE. The returned values represent the clock equation:
4881 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4882 */
1b894b59 4883 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 4884 ok = dev_priv->display.find_dpll(limit, crtc,
4885 intel_crtc->config.port_clock,
ee9300bb
DV		 4886 refclk, NULL, &clock);
4887 if (!ok && !intel_crtc->config.clock_set) {
79e53945 4888 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4889 return -EINVAL;
79e53945
JB		 4890 }
4891
cda4b7d3 4892 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4893 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4894
ddc9003c 4895 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4896 /*
4897 * Ensure we match the reduced clock's P to the target clock.
4898 * If the clocks don't match, we can't switch the display clock
4899 * by using the FP0/FP1. In such case we will disable the LVDS
4900 * downclock feature.
4901 */
ee9300bb
DV		 4902 has_reduced_clock =
4903 dev_priv->display.find_dpll(limit, crtc,
5eddb70b 4904 dev_priv->lvds_downclock,
ee9300bb 4905 refclk, &clock,
5eddb70b 4906 &reduced_clock);
7026d4ac 4907 }
f47709a9
DV		 4908 /* Compat-code for transition, will disappear. */
4909 if (!intel_crtc->config.clock_set) {
4910 intel_crtc->config.dpll.n = clock.n;
4911 intel_crtc->config.dpll.m1 = clock.m1;
4912 intel_crtc->config.dpll.m2 = clock.m2;
4913 intel_crtc->config.dpll.p1 = clock.p1;
4914 intel_crtc->config.dpll.p2 = clock.p2;
4915 }
7026d4ac 4916
eb1cbe48 4917 if (IS_GEN2(dev))
8a654f3b 4918 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 4919 has_reduced_clock ? &reduced_clock : NULL,
4920 num_connectors);
a0c4da24 4921 else if (IS_VALLEYVIEW(dev))
f47709a9 4922 vlv_update_pll(intel_crtc);
79e53945 4923 else
f47709a9 4924 i9xx_update_pll(intel_crtc,
eb1cbe48 4925 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4926 num_connectors);
79e53945 4927
79e53945
JB		 4928 /* Set up the display plane register */
4929 dspcntr = DISPPLANE_GAMMA_ENABLE;
4930
da6ecc5d
JB		 4931 if (!IS_VALLEYVIEW(dev)) {
4932 if (pipe == 0)
4933 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4934 else
4935 dspcntr |= DISPPLANE_SEL_PIPE_B;
4936 }
79e53945 4937
8a654f3b 4938 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 4939
4940 /* pipesrc and dspsize control the size that is scaled from,
4941 * which should always be the user's requested size.
79e53945 4942 */
929c77fb
EA		 4943 I915_WRITE(DSPSIZE(plane),
4944 ((mode->vdisplay - 1) << 16) |
4945 (mode->hdisplay - 1));
4946 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4947
84b046f3
DV		 4948 i9xx_set_pipeconf(intel_crtc);
4949
f564048e
EA		 4950 I915_WRITE(DSPCNTR(plane), dspcntr);
4951 POSTING_READ(DSPCNTR(plane));
4952
94352cf9 4953 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4954
4955 intel_update_watermarks(dev);
4956
f564048e
EA		 4957 return ret;
4958}
4959
2fa2fe9a
DV		 4960static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4961 struct intel_crtc_config *pipe_config)
4962{
4963 struct drm_device *dev = crtc->base.dev;
4964 struct drm_i915_private *dev_priv = dev->dev_private;
4965 uint32_t tmp;
4966
4967 tmp = I915_READ(PFIT_CONTROL);
4968
4969 if (INTEL_INFO(dev)->gen < 4) {
4970 if (crtc->pipe != PIPE_B)
4971 return;
4972
4973 /* gen2/3 store dither state in pfit control, needs to match */
4974 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4975 } else {
4976 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4977 return;
4978 }
4979
4980 if (!(tmp & PFIT_ENABLE))
4981 return;
4982
4983 pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4984 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4985 if (INTEL_INFO(dev)->gen < 5)
4986 pipe_config->gmch_pfit.lvds_border_bits =
4987 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4988}
4989
0e8ffe1b
DV		 4990static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4991 struct intel_crtc_config *pipe_config)
4992{
4993 struct drm_device *dev = crtc->base.dev;
4994 struct drm_i915_private *dev_priv = dev->dev_private;
4995 uint32_t tmp;
4996
eccb140b
DV		 4997 pipe_config->cpu_transcoder = crtc->pipe;
4998
0e8ffe1b
DV		 4999 tmp = I915_READ(PIPECONF(crtc->pipe));
5000 if (!(tmp & PIPECONF_ENABLE))
5001 return false;
5002
1bd1bd80
DV		 5003 intel_get_pipe_timings(crtc, pipe_config);
5004
2fa2fe9a
DV		 5005 i9xx_get_pfit_config(crtc, pipe_config);
5006
6c49f241
DV		 5007 if (INTEL_INFO(dev)->gen >= 4) {
5008 tmp = I915_READ(DPLL_MD(crtc->pipe));
5009 pipe_config->pixel_multiplier =
5010 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5011 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5012 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5013 tmp = I915_READ(DPLL(crtc->pipe));
5014 pipe_config->pixel_multiplier =
5015 ((tmp & SDVO_MULTIPLIER_MASK)
5016 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5017 } else {
5018 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5019 * port and will be fixed up in the encoder->get_config
5020 * function. */
5021 pipe_config->pixel_multiplier = 1;
5022 }
5023
0e8ffe1b
DV		 5024 return true;
5025}
5026
dde86e2d 5027static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5028{
5029 struct drm_i915_private *dev_priv = dev->dev_private;
5030 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5031 struct intel_encoder *encoder;
74cfd7ac 5032 u32 val, final;
13d83a67 5033 bool has_lvds = false;
199e5d79 5034 bool has_cpu_edp = false;
199e5d79 5035 bool has_panel = false;
99eb6a01
KP		 5036 bool has_ck505 = false;
5037 bool can_ssc = false;
13d83a67
JB		 5038
5039 /* We need to take the global config into account */
199e5d79
KP		 5040 list_for_each_entry(encoder, &mode_config->encoder_list,
5041 base.head) {
5042 switch (encoder->type) {
5043 case INTEL_OUTPUT_LVDS:
5044 has_panel = true;
5045 has_lvds = true;
5046 break;
5047 case INTEL_OUTPUT_EDP:
5048 has_panel = true;
2de6905f 5049 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5050 has_cpu_edp = true;
5051 break;
13d83a67
JB		 5052 }
5053 }
5054
99eb6a01 5055 if (HAS_PCH_IBX(dev)) {
41aa3448 5056 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5057 can_ssc = has_ck505;
5058 } else {
5059 has_ck505 = false;
5060 can_ssc = true;
5061 }
5062
2de6905f
ID		 5063 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5064 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5065
5066 /* Ironlake: try to setup display ref clock before DPLL
5067 * enabling. This is only under driver's control after
5068 * PCH B stepping, previous chipset stepping should be
5069 * ignoring this setting.
5070 */
74cfd7ac
CW		 5071 val = I915_READ(PCH_DREF_CONTROL);
5072
5073 /* As we must carefully and slowly disable/enable each source in turn,
5074 * compute the final state we want first and check if we need to
5075 * make any changes at all.
5076 */
5077 final = val;
5078 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5079 if (has_ck505)
5080 final |= DREF_NONSPREAD_CK505_ENABLE;
5081 else
5082 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5083
5084 final &= ~DREF_SSC_SOURCE_MASK;
5085 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5086 final &= ~DREF_SSC1_ENABLE;
5087
5088 if (has_panel) {
5089 final |= DREF_SSC_SOURCE_ENABLE;
5090
5091 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5092 final |= DREF_SSC1_ENABLE;
5093
5094 if (has_cpu_edp) {
5095 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5096 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5097 else
5098 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5099 } else
5100 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5101 } else {
5102 final |= DREF_SSC_SOURCE_DISABLE;
5103 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5104 }
5105
5106 if (final == val)
5107 return;
5108
13d83a67 5109 /* Always enable nonspread source */
74cfd7ac 5110 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5111
99eb6a01 5112 if (has_ck505)
74cfd7ac 5113 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5114 else
74cfd7ac 5115 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5116
199e5d79 5117 if (has_panel) {
74cfd7ac
CW		 5118 val &= ~DREF_SSC_SOURCE_MASK;
5119 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5120
199e5d79 5121 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5122 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5123 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5124 val |= DREF_SSC1_ENABLE;
e77166b5 5125 } else
74cfd7ac 5126 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5127
5128 /* Get SSC going before enabling the outputs */
74cfd7ac 5129 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5130 POSTING_READ(PCH_DREF_CONTROL);
5131 udelay(200);
5132
74cfd7ac 5133 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5134
5135 /* Enable CPU source on CPU attached eDP */
199e5d79 5136 if (has_cpu_edp) {
99eb6a01 5137 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5138 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5139 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5140 }
13d83a67 5141 else
74cfd7ac 5142 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5143 } else
74cfd7ac 5144 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5145
74cfd7ac 5146 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5147 POSTING_READ(PCH_DREF_CONTROL);
5148 udelay(200);
5149 } else {
5150 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5151
74cfd7ac 5152 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5153
5154 /* Turn off CPU output */
74cfd7ac 5155 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5156
74cfd7ac 5157 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5158 POSTING_READ(PCH_DREF_CONTROL);
5159 udelay(200);
5160
5161 /* Turn off the SSC source */
74cfd7ac
CW		 5162 val &= ~DREF_SSC_SOURCE_MASK;
5163 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5164
5165 /* Turn off SSC1 */
74cfd7ac 5166 val &= ~DREF_SSC1_ENABLE;
199e5d79 5167
74cfd7ac 5168 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5169 POSTING_READ(PCH_DREF_CONTROL);
5170 udelay(200);
5171 }
74cfd7ac
CW		 5172
5173 BUG_ON(val != final);
13d83a67
JB		 5174}
5175
dde86e2d
PZ		 5176/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5177static void lpt_init_pch_refclk(struct drm_device *dev)
5178{
5179 struct drm_i915_private *dev_priv = dev->dev_private;
5180 struct drm_mode_config *mode_config = &dev->mode_config;
5181 struct intel_encoder *encoder;
5182 bool has_vga = false;
5183 bool is_sdv = false;
5184 u32 tmp;
5185
5186 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5187 switch (encoder->type) {
5188 case INTEL_OUTPUT_ANALOG:
5189 has_vga = true;
5190 break;
5191 }
5192 }
5193
5194 if (!has_vga)
5195 return;
5196
c00db246
DV		 5197 mutex_lock(&dev_priv->dpio_lock);
5198
dde86e2d
PZ		 5199 /* XXX: Rip out SDV support once Haswell ships for real. */
5200 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5201 is_sdv = true;
5202
5203 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5204 tmp &= ~SBI_SSCCTL_DISABLE;
5205 tmp |= SBI_SSCCTL_PATHALT;
5206 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5207
5208 udelay(24);
5209
5210 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5211 tmp &= ~SBI_SSCCTL_PATHALT;
5212 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5213
5214 if (!is_sdv) {
5215 tmp = I915_READ(SOUTH_CHICKEN2);
5216 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5217 I915_WRITE(SOUTH_CHICKEN2, tmp);
5218
5219 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5220 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5221 DRM_ERROR("FDI mPHY reset assert timeout\n");
5222
5223 tmp = I915_READ(SOUTH_CHICKEN2);
5224 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5225 I915_WRITE(SOUTH_CHICKEN2, tmp);
5226
5227 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5228 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5229 100))
5230 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5231 }
5232
5233 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5234 tmp &= ~(0xFF << 24);
5235 tmp |= (0x12 << 24);
5236 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5237
dde86e2d
PZ		 5238 if (is_sdv) {
5239 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5240 tmp |= 0x7FFF;
5241 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5242 }
5243
5244 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5245 tmp |= (1 << 11);
5246 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5247
5248 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5249 tmp |= (1 << 11);
5250 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5251
5252 if (is_sdv) {
5253 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5254 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5255 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5256
5257 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5258 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5259 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5260
5261 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5262 tmp |= (0x3F << 8);
5263 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5264
5265 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5266 tmp |= (0x3F << 8);
5267 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5268 }
5269
5270 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5271 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5272 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5273
5274 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5275 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5276 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5277
5278 if (!is_sdv) {
5279 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5280 tmp &= ~(7 << 13);
5281 tmp |= (5 << 13);
5282 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5283
5284 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5285 tmp &= ~(7 << 13);
5286 tmp |= (5 << 13);
5287 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5288 }
5289
5290 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5291 tmp &= ~0xFF;
5292 tmp |= 0x1C;
5293 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5294
5295 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5296 tmp &= ~0xFF;
5297 tmp |= 0x1C;
5298 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5299
5300 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5301 tmp &= ~(0xFF << 16);
5302 tmp |= (0x1C << 16);
5303 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5304
5305 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5306 tmp &= ~(0xFF << 16);
5307 tmp |= (0x1C << 16);
5308 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5309
5310 if (!is_sdv) {
5311 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5312 tmp |= (1 << 27);
5313 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5314
5315 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5316 tmp |= (1 << 27);
5317 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5318
5319 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5320 tmp &= ~(0xF << 28);
5321 tmp |= (4 << 28);
5322 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5323
5324 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5325 tmp &= ~(0xF << 28);
5326 tmp |= (4 << 28);
5327 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5328 }
5329
5330 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5331 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5332 tmp |= SBI_DBUFF0_ENABLE;
5333 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5334
5335 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5336}
5337
5338/*
5339 * Initialize reference clocks when the driver loads
5340 */
5341void intel_init_pch_refclk(struct drm_device *dev)
5342{
5343 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5344 ironlake_init_pch_refclk(dev);
5345 else if (HAS_PCH_LPT(dev))
5346 lpt_init_pch_refclk(dev);
5347}
5348
d9d444cb
JB		 5349static int ironlake_get_refclk(struct drm_crtc *crtc)
5350{
5351 struct drm_device *dev = crtc->dev;
5352 struct drm_i915_private *dev_priv = dev->dev_private;
5353 struct intel_encoder *encoder;
d9d444cb
JB		 5354 int num_connectors = 0;
5355 bool is_lvds = false;
5356
6c2b7c12 5357 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5358 switch (encoder->type) {
5359 case INTEL_OUTPUT_LVDS:
5360 is_lvds = true;
5361 break;
d9d444cb
JB		 5362 }
5363 num_connectors++;
5364 }
5365
5366 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5367 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5368 dev_priv->vbt.lvds_ssc_freq);
5369 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5370 }
5371
5372 return 120000;
5373}
5374
6ff93609 5375static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5376{
c8203565 5377 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5378 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5379 int pipe = intel_crtc->pipe;
c8203565
PZ		 5380 uint32_t val;
5381
5382 val = I915_READ(PIPECONF(pipe));
5383
dfd07d72 5384 val &= ~PIPECONF_BPC_MASK;
965e0c48 5385 switch (intel_crtc->config.pipe_bpp) {
c8203565 5386 case 18:
dfd07d72 5387 val |= PIPECONF_6BPC;
c8203565
PZ		 5388 break;
5389 case 24:
dfd07d72 5390 val |= PIPECONF_8BPC;
c8203565
PZ		 5391 break;
5392 case 30:
dfd07d72 5393 val |= PIPECONF_10BPC;
c8203565
PZ		 5394 break;
5395 case 36:
dfd07d72 5396 val |= PIPECONF_12BPC;
c8203565
PZ		 5397 break;
5398 default:
cc769b62
PZ		 5399 /* Case prevented by intel_choose_pipe_bpp_dither. */
5400 BUG();
c8203565
PZ		 5401 }
5402
5403 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5404 if (intel_crtc->config.dither)
c8203565
PZ		 5405 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5406
5407 val &= ~PIPECONF_INTERLACE_MASK;
6ff93609 5408 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5409 val |= PIPECONF_INTERLACED_ILK;
5410 else
5411 val |= PIPECONF_PROGRESSIVE;
5412
50f3b016 5413 if (intel_crtc->config.limited_color_range)
3685a8f3
VS		 5414 val |= PIPECONF_COLOR_RANGE_SELECT;
5415 else
5416 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5417
c8203565
PZ		 5418 I915_WRITE(PIPECONF(pipe), val);
5419 POSTING_READ(PIPECONF(pipe));
5420}
5421
86d3efce
VS		 5422/*
5423 * Set up the pipe CSC unit.
5424 *
5425 * Currently only full range RGB to limited range RGB conversion
5426 * is supported, but eventually this should handle various
5427 * RGB<->YCbCr scenarios as well.
5428 */
50f3b016 5429static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5430{
5431 struct drm_device *dev = crtc->dev;
5432 struct drm_i915_private *dev_priv = dev->dev_private;
5433 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5434 int pipe = intel_crtc->pipe;
5435 uint16_t coeff = 0x7800; /* 1.0 */
5436
5437 /*
5438 * TODO: Check what kind of values actually come out of the pipe
5439 * with these coeff/postoff values and adjust to get the best
5440 * accuracy. Perhaps we even need to take the bpc value into
5441 * consideration.
5442 */
5443
50f3b016 5444 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5445 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5446
5447 /*
5448 * GY/GU and RY/RU should be the other way around according
5449 * to BSpec, but reality doesn't agree. Just set them up in
5450 * a way that results in the correct picture.
5451 */
5452 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5453 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5454
5455 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5456 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5457
5458 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5459 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5460
5461 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5462 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5463 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5464
5465 if (INTEL_INFO(dev)->gen > 6) {
5466 uint16_t postoff = 0;
5467
50f3b016 5468 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5469 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5470
5471 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5472 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5473 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5474
5475 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5476 } else {
5477 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5478
50f3b016 5479 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5480 mode |= CSC_BLACK_SCREEN_OFFSET;
5481
5482 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5483 }
5484}
5485
6ff93609 5486static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5487{
5488 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5489 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5490 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5491 uint32_t val;
5492
702e7a56 5493 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5494
5495 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5496 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5497 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5498
5499 val &= ~PIPECONF_INTERLACE_MASK_HSW;
6ff93609 5500 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5501 val |= PIPECONF_INTERLACED_ILK;
5502 else
5503 val |= PIPECONF_PROGRESSIVE;
5504
702e7a56
PZ		 5505 I915_WRITE(PIPECONF(cpu_transcoder), val);
5506 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5507}
5508
6591c6e4 5509static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5510 intel_clock_t *clock,
5511 bool *has_reduced_clock,
5512 intel_clock_t *reduced_clock)
5513{
5514 struct drm_device *dev = crtc->dev;
5515 struct drm_i915_private *dev_priv = dev->dev_private;
5516 struct intel_encoder *intel_encoder;
5517 int refclk;
d4906093 5518 const intel_limit_t *limit;
a16af721 5519 bool ret, is_lvds = false;
79e53945 5520
6591c6e4
PZ		 5521 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5522 switch (intel_encoder->type) {
79e53945
JB		 5523 case INTEL_OUTPUT_LVDS:
5524 is_lvds = true;
5525 break;
79e53945
JB		 5526 }
5527 }
5528
d9d444cb 5529 refclk = ironlake_get_refclk(crtc);
79e53945 5530
d4906093
ML		 5531 /*
5532 * Returns a set of divisors for the desired target clock with the given
5533 * refclk, or FALSE. The returned values represent the clock equation:
5534 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5535 */
1b894b59 5536 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5537 ret = dev_priv->display.find_dpll(limit, crtc,
5538 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5539 refclk, NULL, clock);
6591c6e4
PZ		 5540 if (!ret)
5541 return false;
cda4b7d3 5542
ddc9003c 5543 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5544 /*
5545 * Ensure we match the reduced clock's P to the target clock.
5546 * If the clocks don't match, we can't switch the display clock
5547 * by using the FP0/FP1. In such case we will disable the LVDS
5548 * downclock feature.
5549 */
ee9300bb
DV		 5550 *has_reduced_clock =
5551 dev_priv->display.find_dpll(limit, crtc,
5552 dev_priv->lvds_downclock,
5553 refclk, clock,
5554 reduced_clock);
652c393a 5555 }
61e9653f 5556
6591c6e4
PZ		 5557 return true;
5558}
5559
01a415fd
DV		 5560static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5561{
5562 struct drm_i915_private *dev_priv = dev->dev_private;
5563 uint32_t temp;
5564
5565 temp = I915_READ(SOUTH_CHICKEN1);
5566 if (temp & FDI_BC_BIFURCATION_SELECT)
5567 return;
5568
5569 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5570 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5571
5572 temp |= FDI_BC_BIFURCATION_SELECT;
5573 DRM_DEBUG_KMS("enabling fdi C rx\n");
5574 I915_WRITE(SOUTH_CHICKEN1, temp);
5575 POSTING_READ(SOUTH_CHICKEN1);
5576}
5577
ebfd86fd
DV		 5578static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5579{
5580 struct drm_device *dev = intel_crtc->base.dev;
5581 struct drm_i915_private *dev_priv = dev->dev_private;
5582
5583 switch (intel_crtc->pipe) {
5584 case PIPE_A:
5585 break;
5586 case PIPE_B:
5587 if (intel_crtc->config.fdi_lanes > 2)
5588 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5589 else
5590 cpt_enable_fdi_bc_bifurcation(dev);
5591
5592 break;
5593 case PIPE_C:
01a415fd
DV		 5594 cpt_enable_fdi_bc_bifurcation(dev);
5595
ebfd86fd 5596 break;
01a415fd
DV		 5597 default:
5598 BUG();
5599 }
5600}
5601
d4b1931c
PZ		 5602int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5603{
5604 /*
5605 * Account for spread spectrum to avoid
5606 * oversubscribing the link. Max center spread
5607 * is 2.5%; use 5% for safety's sake.
5608 */
5609 u32 bps = target_clock * bpp * 21 / 20;
5610 return bps / (link_bw * 8) + 1;
5611}
5612
7429e9d4
DV		 5613static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5614{
5615 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5616}
5617
de13a2e3 5618static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5619 u32 *fp,
9a7c7890 5620 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5621{
de13a2e3 5622 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5623 struct drm_device *dev = crtc->dev;
5624 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5625 struct intel_encoder *intel_encoder;
5626 uint32_t dpll;
6cc5f341 5627 int factor, num_connectors = 0;
09ede541 5628 bool is_lvds = false, is_sdvo = false;
79e53945 5629
de13a2e3
PZ		 5630 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5631 switch (intel_encoder->type) {
79e53945
JB		 5632 case INTEL_OUTPUT_LVDS:
5633 is_lvds = true;
5634 break;
5635 case INTEL_OUTPUT_SDVO:
7d57382e 5636 case INTEL_OUTPUT_HDMI:
79e53945
JB		 5637 is_sdvo = true;
5638 break;
79e53945 5639 }
43565a06 5640
c751ce4f 5641 num_connectors++;
79e53945 5642 }
79e53945 5643
c1858123 5644 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5645 factor = 21;
5646 if (is_lvds) {
5647 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5648 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5649 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5650 factor = 25;
09ede541 5651 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5652 factor = 20;
c1858123 5653
7429e9d4 5654 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5655 *fp |= FP_CB_TUNE;
2c07245f 5656
9a7c7890
DV		 5657 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5658 *fp2 |= FP_CB_TUNE;
5659
5eddb70b 5660 dpll = 0;
2c07245f 5661
a07d6787
EA		 5662 if (is_lvds)
5663 dpll |= DPLLB_MODE_LVDS;
5664 else
5665 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5666
ef1b460d
DV		 5667 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5668 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5669
5670 if (is_sdvo)
5671 dpll |= DPLL_DVO_HIGH_SPEED;
9566e9af 5672 if (intel_crtc->config.has_dp_encoder)
a07d6787 5673 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5674
a07d6787 5675 /* compute bitmask from p1 value */
7429e9d4 5676 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5677 /* also FPA1 */
7429e9d4 5678 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5679
7429e9d4 5680 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5681 case 5:
5682 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5683 break;
5684 case 7:
5685 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5686 break;
5687 case 10:
5688 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5689 break;
5690 case 14:
5691 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5692 break;
79e53945
JB		 5693 }
5694
b4c09f3b 5695 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5696 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5697 else
5698 dpll |= PLL_REF_INPUT_DREFCLK;
5699
de13a2e3
PZ		 5700 return dpll;
5701}
5702
5703static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5704 int x, int y,
5705 struct drm_framebuffer *fb)
5706{
5707 struct drm_device *dev = crtc->dev;
5708 struct drm_i915_private *dev_priv = dev->dev_private;
5709 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5710 int pipe = intel_crtc->pipe;
5711 int plane = intel_crtc->plane;
5712 int num_connectors = 0;
5713 intel_clock_t clock, reduced_clock;
cbbab5bd 5714 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5715 bool ok, has_reduced_clock = false;
8b47047b 5716 bool is_lvds = false;
de13a2e3 5717 struct intel_encoder *encoder;
de13a2e3 5718 int ret;
de13a2e3
PZ		 5719
5720 for_each_encoder_on_crtc(dev, crtc, encoder) {
5721 switch (encoder->type) {
5722 case INTEL_OUTPUT_LVDS:
5723 is_lvds = true;
5724 break;
de13a2e3
PZ		 5725 }
5726
5727 num_connectors++;
a07d6787 5728 }
79e53945 5729
5dc5298b
PZ		 5730 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5731 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5732
ff9a6750 5733 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 5734 &has_reduced_clock, &reduced_clock);
ee9300bb 5735 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 5736 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5737 return -EINVAL;
79e53945 5738 }
f47709a9
DV		 5739 /* Compat-code for transition, will disappear. */
5740 if (!intel_crtc->config.clock_set) {
5741 intel_crtc->config.dpll.n = clock.n;
5742 intel_crtc->config.dpll.m1 = clock.m1;
5743 intel_crtc->config.dpll.m2 = clock.m2;
5744 intel_crtc->config.dpll.p1 = clock.p1;
5745 intel_crtc->config.dpll.p2 = clock.p2;
5746 }
79e53945 5747
de13a2e3
PZ		 5748 /* Ensure that the cursor is valid for the new mode before changing... */
5749 intel_crtc_update_cursor(crtc, true);
5750
5dc5298b 5751 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5752 if (intel_crtc->config.has_pch_encoder) {
ee7b9f93 5753 struct intel_pch_pll *pll;
4b645f14 5754
7429e9d4 5755 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5756 if (has_reduced_clock)
7429e9d4 5757 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5758
7429e9d4 5759 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5760 &fp, &reduced_clock,
5761 has_reduced_clock ? &fp2 : NULL);
5762
ee7b9f93
JB		 5763 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5764 if (pll == NULL) {
84f44ce7
VS		 5765 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5766 pipe_name(pipe));
4b645f14
JB		 5767 return -EINVAL;
5768 }
ee7b9f93
JB		 5769 } else
5770 intel_put_pch_pll(intel_crtc);
79e53945 5771
03afc4a2
DV		 5772 if (intel_crtc->config.has_dp_encoder)
5773 intel_dp_set_m_n(intel_crtc);
79e53945 5774
dafd226c
DV		 5775 for_each_encoder_on_crtc(dev, crtc, encoder)
5776 if (encoder->pre_pll_enable)
5777 encoder->pre_pll_enable(encoder);
79e53945 5778
ee7b9f93
JB		 5779 if (intel_crtc->pch_pll) {
5780 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5781
32f9d658 5782 /* Wait for the clocks to stabilize. */
ee7b9f93 5783 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5784 udelay(150);
5785
8febb297
EA		 5786 /* The pixel multiplier can only be updated once the
5787 * DPLL is enabled and the clocks are stable.
5788 *
5789 * So write it again.
5790 */
ee7b9f93 5791 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5792 }
79e53945 5793
5eddb70b 5794 intel_crtc->lowfreq_avail = false;
ee7b9f93 5795 if (intel_crtc->pch_pll) {
4b645f14 5796 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5797 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5798 intel_crtc->lowfreq_avail = true;
4b645f14 5799 } else {
ee7b9f93 5800 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5801 }
5802 }
5803
8a654f3b 5804 intel_set_pipe_timings(intel_crtc);
5eddb70b 5805
ca3a0ff8 5806 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5807 intel_cpu_transcoder_set_m_n(intel_crtc,
5808 &intel_crtc->config.fdi_m_n);
5809 }
2c07245f 5810
ebfd86fd
DV		 5811 if (IS_IVYBRIDGE(dev))
5812 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
2c07245f 5813
6ff93609 5814 ironlake_set_pipeconf(crtc);
79e53945 5815
a1f9e77e
PZ		 5816 /* Set up the display plane register */
5817 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5818 POSTING_READ(DSPCNTR(plane));
79e53945 5819
94352cf9 5820 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5821
5822 intel_update_watermarks(dev);
5823
1857e1da 5824 return ret;
79e53945
JB		 5825}
5826
72419203
DV		 5827static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5828 struct intel_crtc_config *pipe_config)
5829{
5830 struct drm_device *dev = crtc->base.dev;
5831 struct drm_i915_private *dev_priv = dev->dev_private;
5832 enum transcoder transcoder = pipe_config->cpu_transcoder;
5833
5834 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5835 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5836 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5837 & ~TU_SIZE_MASK;
5838 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5839 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5840 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5841}
5842
2fa2fe9a
DV		 5843static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5844 struct intel_crtc_config *pipe_config)
5845{
5846 struct drm_device *dev = crtc->base.dev;
5847 struct drm_i915_private *dev_priv = dev->dev_private;
5848 uint32_t tmp;
5849
5850 tmp = I915_READ(PF_CTL(crtc->pipe));
5851
5852 if (tmp & PF_ENABLE) {
5853 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5854 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 5855
5856 /* We currently do not free assignements of panel fitters on
5857 * ivb/hsw (since we don't use the higher upscaling modes which
5858 * differentiates them) so just WARN about this case for now. */
5859 if (IS_GEN7(dev)) {
5860 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5861 PF_PIPE_SEL_IVB(crtc->pipe));
5862 }
2fa2fe9a
DV		 5863 }
5864}
5865
0e8ffe1b
DV		 5866static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5867 struct intel_crtc_config *pipe_config)
5868{
5869 struct drm_device *dev = crtc->base.dev;
5870 struct drm_i915_private *dev_priv = dev->dev_private;
5871 uint32_t tmp;
5872
eccb140b
DV		 5873 pipe_config->cpu_transcoder = crtc->pipe;
5874
0e8ffe1b
DV		 5875 tmp = I915_READ(PIPECONF(crtc->pipe));
5876 if (!(tmp & PIPECONF_ENABLE))
5877 return false;
5878
ab9412ba 5879 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
88adfff1
DV		 5880 pipe_config->has_pch_encoder = true;
5881
627eb5a3
DV		 5882 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5883 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5884 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5885
5886 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241
DV		 5887
5888 /* XXX: Can't properly read out the pch dpll pixel multiplier
5889 * since we don't have state tracking for pch clocks yet. */
5890 pipe_config->pixel_multiplier = 1;
5891 } else {
5892 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 5893 }
5894
1bd1bd80
DV		 5895 intel_get_pipe_timings(crtc, pipe_config);
5896
2fa2fe9a
DV		 5897 ironlake_get_pfit_config(crtc, pipe_config);
5898
0e8ffe1b
DV		 5899 return true;
5900}
5901
d6dd9eb1
DV		 5902static void haswell_modeset_global_resources(struct drm_device *dev)
5903{
d6dd9eb1
DV		 5904 bool enable = false;
5905 struct intel_crtc *crtc;
d6dd9eb1
DV		 5906
5907 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 5908 if (!crtc->base.enabled)
5909 continue;
d6dd9eb1 5910
e7a639c4
DV		 5911 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5912 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 5913 enable = true;
5914 }
5915
d6dd9eb1
DV		 5916 intel_set_power_well(dev, enable);
5917}
5918
09b4ddf9 5919static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5920 int x, int y,
5921 struct drm_framebuffer *fb)
5922{
5923 struct drm_device *dev = crtc->dev;
5924 struct drm_i915_private *dev_priv = dev->dev_private;
5925 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 5926 int plane = intel_crtc->plane;
09b4ddf9 5927 int ret;
09b4ddf9 5928
ff9a6750 5929 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 5930 return -EINVAL;
5931
09b4ddf9
PZ		 5932 /* Ensure that the cursor is valid for the new mode before changing... */
5933 intel_crtc_update_cursor(crtc, true);
5934
03afc4a2
DV		 5935 if (intel_crtc->config.has_dp_encoder)
5936 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 5937
5938 intel_crtc->lowfreq_avail = false;
09b4ddf9 5939
8a654f3b 5940 intel_set_pipe_timings(intel_crtc);
09b4ddf9 5941
ca3a0ff8 5942 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5943 intel_cpu_transcoder_set_m_n(intel_crtc,
5944 &intel_crtc->config.fdi_m_n);
5945 }
09b4ddf9 5946
6ff93609 5947 haswell_set_pipeconf(crtc);
09b4ddf9 5948
50f3b016 5949 intel_set_pipe_csc(crtc);
86d3efce 5950
09b4ddf9 5951 /* Set up the display plane register */
86d3efce 5952 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5953 POSTING_READ(DSPCNTR(plane));
5954
5955 ret = intel_pipe_set_base(crtc, x, y, fb);
5956
5957 intel_update_watermarks(dev);
5958
1f803ee5 5959 return ret;
79e53945
JB		 5960}
5961
0e8ffe1b
DV		 5962static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5963 struct intel_crtc_config *pipe_config)
5964{
5965 struct drm_device *dev = crtc->base.dev;
5966 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 5967 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 5968 uint32_t tmp;
5969
eccb140b
DV		 5970 pipe_config->cpu_transcoder = crtc->pipe;
5971 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5972 if (tmp & TRANS_DDI_FUNC_ENABLE) {
5973 enum pipe trans_edp_pipe;
5974 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5975 default:
5976 WARN(1, "unknown pipe linked to edp transcoder\n");
5977 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5978 case TRANS_DDI_EDP_INPUT_A_ON:
5979 trans_edp_pipe = PIPE_A;
5980 break;
5981 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5982 trans_edp_pipe = PIPE_B;
5983 break;
5984 case TRANS_DDI_EDP_INPUT_C_ONOFF:
5985 trans_edp_pipe = PIPE_C;
5986 break;
5987 }
5988
5989 if (trans_edp_pipe == crtc->pipe)
5990 pipe_config->cpu_transcoder = TRANSCODER_EDP;
5991 }
5992
b97186f0 5993 if (!intel_display_power_enabled(dev,
eccb140b 5994 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 5995 return false;
5996
eccb140b 5997 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 5998 if (!(tmp & PIPECONF_ENABLE))
5999 return false;
6000
88adfff1 6001 /*
f196e6be 6002 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 6003 * DDI E. So just check whether this pipe is wired to DDI E and whether
6004 * the PCH transcoder is on.
6005 */
eccb140b 6006 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 6007 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 6008 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 6009 pipe_config->has_pch_encoder = true;
6010
627eb5a3
DV		 6011 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6012 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6013 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6014
6015 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 6016 }
6017
1bd1bd80
DV		 6018 intel_get_pipe_timings(crtc, pipe_config);
6019
2fa2fe9a
DV		 6020 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6021 if (intel_display_power_enabled(dev, pfit_domain))
6022 ironlake_get_pfit_config(crtc, pipe_config);
6023
42db64ef
PZ		 6024 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6025 (I915_READ(IPS_CTL) & IPS_ENABLE);
6026
6c49f241
DV		 6027 pipe_config->pixel_multiplier = 1;
6028
0e8ffe1b
DV		 6029 return true;
6030}
6031
f564048e 6032static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6033 int x, int y,
94352cf9 6034 struct drm_framebuffer *fb)
f564048e
EA		 6035{
6036 struct drm_device *dev = crtc->dev;
6037 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 6038 struct drm_encoder_helper_funcs *encoder_funcs;
6039 struct intel_encoder *encoder;
0b701d27 6040 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 6041 struct drm_display_mode *adjusted_mode =
6042 &intel_crtc->config.adjusted_mode;
6043 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6044 int pipe = intel_crtc->pipe;
f564048e
EA		 6045 int ret;
6046
0b701d27 6047 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6048
b8cecdf5
DV		 6049 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6050
79e53945 6051 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6052
9256aa19
DV		 6053 if (ret != 0)
6054 return ret;
6055
6056 for_each_encoder_on_crtc(dev, crtc, encoder) {
6057 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6058 encoder->base.base.id,
6059 drm_get_encoder_name(&encoder->base),
6060 mode->base.id, mode->name);
6cc5f341
DV		 6061 if (encoder->mode_set) {
6062 encoder->mode_set(encoder);
6063 } else {
6064 encoder_funcs = encoder->base.helper_private;
6065 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6066 }
9256aa19
DV		 6067 }
6068
6069 return 0;
79e53945
JB		 6070}
6071
3a9627f4
WF		 6072static bool intel_eld_uptodate(struct drm_connector *connector,
6073 int reg_eldv, uint32_t bits_eldv,
6074 int reg_elda, uint32_t bits_elda,
6075 int reg_edid)
6076{
6077 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6078 uint8_t *eld = connector->eld;
6079 uint32_t i;
6080
6081 i = I915_READ(reg_eldv);
6082 i &= bits_eldv;
6083
6084 if (!eld[0])
6085 return !i;
6086
6087 if (!i)
6088 return false;
6089
6090 i = I915_READ(reg_elda);
6091 i &= ~bits_elda;
6092 I915_WRITE(reg_elda, i);
6093
6094 for (i = 0; i < eld[2]; i++)
6095 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6096 return false;
6097
6098 return true;
6099}
6100
e0dac65e
WF		 6101static void g4x_write_eld(struct drm_connector *connector,
6102 struct drm_crtc *crtc)
6103{
6104 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6105 uint8_t *eld = connector->eld;
6106 uint32_t eldv;
6107 uint32_t len;
6108 uint32_t i;
6109
6110 i = I915_READ(G4X_AUD_VID_DID);
6111
6112 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6113 eldv = G4X_ELDV_DEVCL_DEVBLC;
6114 else
6115 eldv = G4X_ELDV_DEVCTG;
6116
3a9627f4
WF		 6117 if (intel_eld_uptodate(connector,
6118 G4X_AUD_CNTL_ST, eldv,
6119 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6120 G4X_HDMIW_HDMIEDID))
6121 return;
6122
e0dac65e
WF		 6123 i = I915_READ(G4X_AUD_CNTL_ST);
6124 i &= ~(eldv | G4X_ELD_ADDR);
6125 len = (i >> 9) & 0x1f; /* ELD buffer size */
6126 I915_WRITE(G4X_AUD_CNTL_ST, i);
6127
6128 if (!eld[0])
6129 return;
6130
6131 len = min_t(uint8_t, eld[2], len);
6132 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6133 for (i = 0; i < len; i++)
6134 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6135
6136 i = I915_READ(G4X_AUD_CNTL_ST);
6137 i |= eldv;
6138 I915_WRITE(G4X_AUD_CNTL_ST, i);
6139}
6140
83358c85
WX		 6141static void haswell_write_eld(struct drm_connector *connector,
6142 struct drm_crtc *crtc)
6143{
6144 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6145 uint8_t *eld = connector->eld;
6146 struct drm_device *dev = crtc->dev;
7b9f35a6 6147 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6148 uint32_t eldv;
6149 uint32_t i;
6150 int len;
6151 int pipe = to_intel_crtc(crtc)->pipe;
6152 int tmp;
6153
6154 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6155 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6156 int aud_config = HSW_AUD_CFG(pipe);
6157 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6158
6159
6160 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6161
6162 /* Audio output enable */
6163 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6164 tmp = I915_READ(aud_cntrl_st2);
6165 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6166 I915_WRITE(aud_cntrl_st2, tmp);
6167
6168 /* Wait for 1 vertical blank */
6169 intel_wait_for_vblank(dev, pipe);
6170
6171 /* Set ELD valid state */
6172 tmp = I915_READ(aud_cntrl_st2);
6173 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6174 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6175 I915_WRITE(aud_cntrl_st2, tmp);
6176 tmp = I915_READ(aud_cntrl_st2);
6177 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6178
6179 /* Enable HDMI mode */
6180 tmp = I915_READ(aud_config);
6181 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6182 /* clear N_programing_enable and N_value_index */
6183 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6184 I915_WRITE(aud_config, tmp);
6185
6186 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6187
6188 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6189 intel_crtc->eld_vld = true;
83358c85
WX		 6190
6191 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6192 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6193 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6194 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6195 } else
6196 I915_WRITE(aud_config, 0);
6197
6198 if (intel_eld_uptodate(connector,
6199 aud_cntrl_st2, eldv,
6200 aud_cntl_st, IBX_ELD_ADDRESS,
6201 hdmiw_hdmiedid))
6202 return;
6203
6204 i = I915_READ(aud_cntrl_st2);
6205 i &= ~eldv;
6206 I915_WRITE(aud_cntrl_st2, i);
6207
6208 if (!eld[0])
6209 return;
6210
6211 i = I915_READ(aud_cntl_st);
6212 i &= ~IBX_ELD_ADDRESS;
6213 I915_WRITE(aud_cntl_st, i);
6214 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6215 DRM_DEBUG_DRIVER("port num:%d\n", i);
6216
6217 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6218 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6219 for (i = 0; i < len; i++)
6220 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6221
6222 i = I915_READ(aud_cntrl_st2);
6223 i |= eldv;
6224 I915_WRITE(aud_cntrl_st2, i);
6225
6226}
6227
e0dac65e
WF		 6228static void ironlake_write_eld(struct drm_connector *connector,
6229 struct drm_crtc *crtc)
6230{
6231 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6232 uint8_t *eld = connector->eld;
6233 uint32_t eldv;
6234 uint32_t i;
6235 int len;
6236 int hdmiw_hdmiedid;
b6daa025 6237 int aud_config;
e0dac65e
WF		 6238 int aud_cntl_st;
6239 int aud_cntrl_st2;
9b138a83 6240 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6241
b3f33cbf 6242 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6243 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6244 aud_config = IBX_AUD_CFG(pipe);
6245 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6246 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6247 } else {
9b138a83
WX		 6248 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6249 aud_config = CPT_AUD_CFG(pipe);
6250 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6251 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6252 }
6253
9b138a83 6254 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6255
6256 i = I915_READ(aud_cntl_st);
9b138a83 6257 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6258 if (!i) {
6259 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6260 /* operate blindly on all ports */
1202b4c6
WF		 6261 eldv = IBX_ELD_VALIDB;
6262 eldv |= IBX_ELD_VALIDB << 4;
6263 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6264 } else {
2582a850 6265 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6266 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6267 }
6268
3a9627f4
WF		 6269 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6270 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6271 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6272 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6273 } else
6274 I915_WRITE(aud_config, 0);
e0dac65e 6275
3a9627f4
WF		 6276 if (intel_eld_uptodate(connector,
6277 aud_cntrl_st2, eldv,
6278 aud_cntl_st, IBX_ELD_ADDRESS,
6279 hdmiw_hdmiedid))
6280 return;
6281
e0dac65e
WF		 6282 i = I915_READ(aud_cntrl_st2);
6283 i &= ~eldv;
6284 I915_WRITE(aud_cntrl_st2, i);
6285
6286 if (!eld[0])
6287 return;
6288
e0dac65e 6289 i = I915_READ(aud_cntl_st);
1202b4c6 6290 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6291 I915_WRITE(aud_cntl_st, i);
6292
6293 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6294 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6295 for (i = 0; i < len; i++)
6296 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6297
6298 i = I915_READ(aud_cntrl_st2);
6299 i |= eldv;
6300 I915_WRITE(aud_cntrl_st2, i);
6301}
6302
6303void intel_write_eld(struct drm_encoder *encoder,
6304 struct drm_display_mode *mode)
6305{
6306 struct drm_crtc *crtc = encoder->crtc;
6307 struct drm_connector *connector;
6308 struct drm_device *dev = encoder->dev;
6309 struct drm_i915_private *dev_priv = dev->dev_private;
6310
6311 connector = drm_select_eld(encoder, mode);
6312 if (!connector)
6313 return;
6314
6315 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6316 connector->base.id,
6317 drm_get_connector_name(connector),
6318 connector->encoder->base.id,
6319 drm_get_encoder_name(connector->encoder));
6320
6321 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6322
6323 if (dev_priv->display.write_eld)
6324 dev_priv->display.write_eld(connector, crtc);
6325}
6326
79e53945
JB		 6327/** Loads the palette/gamma unit for the CRTC with the prepared values */
6328void intel_crtc_load_lut(struct drm_crtc *crtc)
6329{
6330 struct drm_device *dev = crtc->dev;
6331 struct drm_i915_private *dev_priv = dev->dev_private;
6332 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
42db64ef
PZ		 6333 enum pipe pipe = intel_crtc->pipe;
6334 int palreg = PALETTE(pipe);
79e53945 6335 int i;
42db64ef 6336 bool reenable_ips = false;
79e53945
JB		 6337
6338 /* The clocks have to be on to load the palette. */
aed3f09d 6339 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6340 return;
6341
14420bd0
VS		 6342 if (!HAS_PCH_SPLIT(dev_priv->dev))
6343 assert_pll_enabled(dev_priv, pipe);
6344
f2b115e6 6345 /* use legacy palette for Ironlake */
bad720ff 6346 if (HAS_PCH_SPLIT(dev))
42db64ef
PZ		 6347 palreg = LGC_PALETTE(pipe);
6348
6349 /* Workaround : Do not read or write the pipe palette/gamma data while
6350 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6351 */
6352 if (intel_crtc->config.ips_enabled &&
6353 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6354 GAMMA_MODE_MODE_SPLIT)) {
6355 hsw_disable_ips(intel_crtc);
6356 reenable_ips = true;
6357 }
2c07245f 6358
79e53945
JB		 6359 for (i = 0; i < 256; i++) {
6360 I915_WRITE(palreg + 4 * i,
6361 (intel_crtc->lut_r[i] << 16) |
6362 (intel_crtc->lut_g[i] << 8) |
6363 intel_crtc->lut_b[i]);
6364 }
42db64ef
PZ		 6365
6366 if (reenable_ips)
6367 hsw_enable_ips(intel_crtc);
79e53945
JB		 6368}
6369
560b85bb
CW		 6370static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6371{
6372 struct drm_device *dev = crtc->dev;
6373 struct drm_i915_private *dev_priv = dev->dev_private;
6374 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6375 bool visible = base != 0;
6376 u32 cntl;
6377
6378 if (intel_crtc->cursor_visible == visible)
6379 return;
6380
9db4a9c7 6381 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6382 if (visible) {
6383 /* On these chipsets we can only modify the base whilst
6384 * the cursor is disabled.
6385 */
9db4a9c7 6386 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6387
6388 cntl &= ~(CURSOR_FORMAT_MASK);
6389 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6390 cntl |= CURSOR_ENABLE |
6391 CURSOR_GAMMA_ENABLE |
6392 CURSOR_FORMAT_ARGB;
6393 } else
6394 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6395 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6396
6397 intel_crtc->cursor_visible = visible;
6398}
6399
6400static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6401{
6402 struct drm_device *dev = crtc->dev;
6403 struct drm_i915_private *dev_priv = dev->dev_private;
6404 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6405 int pipe = intel_crtc->pipe;
6406 bool visible = base != 0;
6407
6408 if (intel_crtc->cursor_visible != visible) {
548f245b 6409 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6410 if (base) {
6411 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6412 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6413 cntl |= pipe << 28; /* Connect to correct pipe */
6414 } else {
6415 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6416 cntl |= CURSOR_MODE_DISABLE;
6417 }
9db4a9c7 6418 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6419
6420 intel_crtc->cursor_visible = visible;
6421 }
6422 /* and commit changes on next vblank */
9db4a9c7 6423 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6424}
6425
65a21cd6
JB		 6426static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6427{
6428 struct drm_device *dev = crtc->dev;
6429 struct drm_i915_private *dev_priv = dev->dev_private;
6430 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6431 int pipe = intel_crtc->pipe;
6432 bool visible = base != 0;
6433
6434 if (intel_crtc->cursor_visible != visible) {
6435 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6436 if (base) {
6437 cntl &= ~CURSOR_MODE;
6438 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6439 } else {
6440 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6441 cntl |= CURSOR_MODE_DISABLE;
6442 }
86d3efce
VS		 6443 if (IS_HASWELL(dev))
6444 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6445 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6446
6447 intel_crtc->cursor_visible = visible;
6448 }
6449 /* and commit changes on next vblank */
6450 I915_WRITE(CURBASE_IVB(pipe), base);
6451}
6452
cda4b7d3 6453/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6454static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6455 bool on)
cda4b7d3
CW		 6456{
6457 struct drm_device *dev = crtc->dev;
6458 struct drm_i915_private *dev_priv = dev->dev_private;
6459 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6460 int pipe = intel_crtc->pipe;
6461 int x = intel_crtc->cursor_x;
6462 int y = intel_crtc->cursor_y;
560b85bb 6463 u32 base, pos;
cda4b7d3
CW		 6464 bool visible;
6465
6466 pos = 0;
6467
6b383a7f 6468 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6469 base = intel_crtc->cursor_addr;
6470 if (x > (int) crtc->fb->width)
6471 base = 0;
6472
6473 if (y > (int) crtc->fb->height)
6474 base = 0;
6475 } else
6476 base = 0;
6477
6478 if (x < 0) {
6479 if (x + intel_crtc->cursor_width < 0)
6480 base = 0;
6481
6482 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6483 x = -x;
6484 }
6485 pos |= x << CURSOR_X_SHIFT;
6486
6487 if (y < 0) {
6488 if (y + intel_crtc->cursor_height < 0)
6489 base = 0;
6490
6491 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6492 y = -y;
6493 }
6494 pos |= y << CURSOR_Y_SHIFT;
6495
6496 visible = base != 0;
560b85bb 6497 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6498 return;
6499
0cd83aa9 6500 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6501 I915_WRITE(CURPOS_IVB(pipe), pos);
6502 ivb_update_cursor(crtc, base);
6503 } else {
6504 I915_WRITE(CURPOS(pipe), pos);
6505 if (IS_845G(dev) || IS_I865G(dev))
6506 i845_update_cursor(crtc, base);
6507 else
6508 i9xx_update_cursor(crtc, base);
6509 }
cda4b7d3
CW		 6510}
6511
79e53945 6512static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6513 struct drm_file *file,
79e53945
JB		 6514 uint32_t handle,
6515 uint32_t width, uint32_t height)
6516{
6517 struct drm_device *dev = crtc->dev;
6518 struct drm_i915_private *dev_priv = dev->dev_private;
6519 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6520 struct drm_i915_gem_object *obj;
cda4b7d3 6521 uint32_t addr;
3f8bc370 6522 int ret;
79e53945 6523
79e53945
JB		 6524 /* if we want to turn off the cursor ignore width and height */
6525 if (!handle) {
28c97730 6526 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6527 addr = 0;
05394f39 6528 obj = NULL;
5004417d 6529 mutex_lock(&dev->struct_mutex);
3f8bc370 6530 goto finish;
79e53945
JB		 6531 }
6532
6533 /* Currently we only support 64x64 cursors */
6534 if (width != 64 || height != 64) {
6535 DRM_ERROR("we currently only support 64x64 cursors\n");
6536 return -EINVAL;
6537 }
6538
05394f39 6539 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6540 if (&obj->base == NULL)
79e53945
JB		 6541 return -ENOENT;
6542
05394f39 6543 if (obj->base.size < width * height * 4) {
79e53945 6544 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6545 ret = -ENOMEM;
6546 goto fail;
79e53945
JB		 6547 }
6548
71acb5eb 6549 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6550 mutex_lock(&dev->struct_mutex);
b295d1b6 6551 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6552 unsigned alignment;
6553
d9e86c0e
CW		 6554 if (obj->tiling_mode) {
6555 DRM_ERROR("cursor cannot be tiled\n");
6556 ret = -EINVAL;
6557 goto fail_locked;
6558 }
6559
693db184
CW		 6560 /* Note that the w/a also requires 2 PTE of padding following
6561 * the bo. We currently fill all unused PTE with the shadow
6562 * page and so we should always have valid PTE following the
6563 * cursor preventing the VT-d warning.
6564 */
6565 alignment = 0;
6566 if (need_vtd_wa(dev))
6567 alignment = 64*1024;
6568
6569 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6570 if (ret) {
6571 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6572 goto fail_locked;
e7b526bb
CW		 6573 }
6574
d9e86c0e
CW		 6575 ret = i915_gem_object_put_fence(obj);
6576 if (ret) {
2da3b9b9 6577 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6578 goto fail_unpin;
6579 }
6580
05394f39 6581 addr = obj->gtt_offset;
71acb5eb 6582 } else {
6eeefaf3 6583 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6584 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6585 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6586 align);
71acb5eb
DA		 6587 if (ret) {
6588 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6589 goto fail_locked;
71acb5eb 6590 }
05394f39 6591 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6592 }
6593
a6c45cf0 6594 if (IS_GEN2(dev))
14b60391
JB		 6595 I915_WRITE(CURSIZE, (height << 12) | width);
6596
3f8bc370 6597 finish:
3f8bc370 6598 if (intel_crtc->cursor_bo) {
b295d1b6 6599 if (dev_priv->info->cursor_needs_physical) {
05394f39 6600 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6601 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6602 } else
6603 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6604 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6605 }
80824003 6606
7f9872e0 6607 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6608
6609 intel_crtc->cursor_addr = addr;
05394f39 6610 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6611 intel_crtc->cursor_width = width;
6612 intel_crtc->cursor_height = height;
6613
40ccc72b 6614 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 6615
79e53945 6616 return 0;
e7b526bb 6617fail_unpin:
05394f39 6618 i915_gem_object_unpin(obj);
7f9872e0 6619fail_locked:
34b8686e 6620 mutex_unlock(&dev->struct_mutex);
bc9025bd 6621fail:
05394f39 6622 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6623 return ret;
79e53945
JB		 6624}
6625
6626static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6627{
79e53945 6628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6629
cda4b7d3
CW		 6630 intel_crtc->cursor_x = x;
6631 intel_crtc->cursor_y = y;
652c393a 6632
40ccc72b 6633 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 6634
6635 return 0;
6636}
6637
6638/** Sets the color ramps on behalf of RandR */
6639void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6640 u16 blue, int regno)
6641{
6642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6643
6644 intel_crtc->lut_r[regno] = red >> 8;
6645 intel_crtc->lut_g[regno] = green >> 8;
6646 intel_crtc->lut_b[regno] = blue >> 8;
6647}
6648
b8c00ac5
DA		 6649void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6650 u16 *blue, int regno)
6651{
6652 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6653
6654 *red = intel_crtc->lut_r[regno] << 8;
6655 *green = intel_crtc->lut_g[regno] << 8;
6656 *blue = intel_crtc->lut_b[regno] << 8;
6657}
6658
79e53945 6659static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6660 u16 *blue, uint32_t start, uint32_t size)
79e53945 6661{
7203425a 6662 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6663 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6664
7203425a 6665 for (i = start; i < end; i++) {
79e53945
JB		 6666 intel_crtc->lut_r[i] = red[i] >> 8;
6667 intel_crtc->lut_g[i] = green[i] >> 8;
6668 intel_crtc->lut_b[i] = blue[i] >> 8;
6669 }
6670
6671 intel_crtc_load_lut(crtc);
6672}
6673
79e53945
JB		 6674/* VESA 640x480x72Hz mode to set on the pipe */
6675static struct drm_display_mode load_detect_mode = {
6676 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6677 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6678};
6679
d2dff872
CW		 6680static struct drm_framebuffer *
6681intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6682 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6683 struct drm_i915_gem_object *obj)
6684{
6685 struct intel_framebuffer *intel_fb;
6686 int ret;
6687
6688 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6689 if (!intel_fb) {
6690 drm_gem_object_unreference_unlocked(&obj->base);
6691 return ERR_PTR(-ENOMEM);
6692 }
6693
6694 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6695 if (ret) {
6696 drm_gem_object_unreference_unlocked(&obj->base);
6697 kfree(intel_fb);
6698 return ERR_PTR(ret);
6699 }
6700
6701 return &intel_fb->base;
6702}
6703
6704static u32
6705intel_framebuffer_pitch_for_width(int width, int bpp)
6706{
6707 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6708 return ALIGN(pitch, 64);
6709}
6710
6711static u32
6712intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6713{
6714 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6715 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6716}
6717
6718static struct drm_framebuffer *
6719intel_framebuffer_create_for_mode(struct drm_device *dev,
6720 struct drm_display_mode *mode,
6721 int depth, int bpp)
6722{
6723 struct drm_i915_gem_object *obj;
0fed39bd 6724 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6725
6726 obj = i915_gem_alloc_object(dev,
6727 intel_framebuffer_size_for_mode(mode, bpp));
6728 if (obj == NULL)
6729 return ERR_PTR(-ENOMEM);
6730
6731 mode_cmd.width = mode->hdisplay;
6732 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6733 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6734 bpp);
5ca0c34a 6735 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6736
6737 return intel_framebuffer_create(dev, &mode_cmd, obj);
6738}
6739
6740static struct drm_framebuffer *
6741mode_fits_in_fbdev(struct drm_device *dev,
6742 struct drm_display_mode *mode)
6743{
6744 struct drm_i915_private *dev_priv = dev->dev_private;
6745 struct drm_i915_gem_object *obj;
6746 struct drm_framebuffer *fb;
6747
6748 if (dev_priv->fbdev == NULL)
6749 return NULL;
6750
6751 obj = dev_priv->fbdev->ifb.obj;
6752 if (obj == NULL)
6753 return NULL;
6754
6755 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6756 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6757 fb->bits_per_pixel))
d2dff872
CW		 6758 return NULL;
6759
01f2c773 6760 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6761 return NULL;
6762
6763 return fb;
6764}
6765
d2434ab7 6766bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6767 struct drm_display_mode *mode,
8261b191 6768 struct intel_load_detect_pipe *old)
79e53945
JB		 6769{
6770 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6771 struct intel_encoder *intel_encoder =
6772 intel_attached_encoder(connector);
79e53945 6773 struct drm_crtc *possible_crtc;
4ef69c7a 6774 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6775 struct drm_crtc *crtc = NULL;
6776 struct drm_device *dev = encoder->dev;
94352cf9 6777 struct drm_framebuffer *fb;
79e53945
JB		 6778 int i = -1;
6779
d2dff872
CW		 6780 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6781 connector->base.id, drm_get_connector_name(connector),
6782 encoder->base.id, drm_get_encoder_name(encoder));
6783
79e53945
JB		 6784 /*
6785 * Algorithm gets a little messy:
7a5e4805 6786 *
79e53945
JB		 6787 * - if the connector already has an assigned crtc, use it (but make
6788 * sure it's on first)
7a5e4805 6789 *
79e53945
JB		 6790 * - try to find the first unused crtc that can drive this connector,
6791 * and use that if we find one
79e53945
JB		 6792 */
6793
6794 /* See if we already have a CRTC for this connector */
6795 if (encoder->crtc) {
6796 crtc = encoder->crtc;
8261b191 6797
7b24056b
DV		 6798 mutex_lock(&crtc->mutex);
6799
24218aac 6800 old->dpms_mode = connector->dpms;
8261b191
CW		 6801 old->load_detect_temp = false;
6802
6803 /* Make sure the crtc and connector are running */
24218aac
DV		 6804 if (connector->dpms != DRM_MODE_DPMS_ON)
6805 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6806
7173188d 6807 return true;
79e53945
JB		 6808 }
6809
6810 /* Find an unused one (if possible) */
6811 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6812 i++;
6813 if (!(encoder->possible_crtcs & (1 << i)))
6814 continue;
6815 if (!possible_crtc->enabled) {
6816 crtc = possible_crtc;
6817 break;
6818 }
79e53945
JB		 6819 }
6820
6821 /*
6822 * If we didn't find an unused CRTC, don't use any.
6823 */
6824 if (!crtc) {
7173188d
CW		 6825 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6826 return false;
79e53945
JB		 6827 }
6828
7b24056b 6829 mutex_lock(&crtc->mutex);
fc303101
DV		 6830 intel_encoder->new_crtc = to_intel_crtc(crtc);
6831 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6832
6833 intel_crtc = to_intel_crtc(crtc);
24218aac 6834 old->dpms_mode = connector->dpms;
8261b191 6835 old->load_detect_temp = true;
d2dff872 6836 old->release_fb = NULL;
79e53945 6837
6492711d
CW		 6838 if (!mode)
6839 mode = &load_detect_mode;
79e53945 6840
d2dff872
CW		 6841 /* We need a framebuffer large enough to accommodate all accesses
6842 * that the plane may generate whilst we perform load detection.
6843 * We can not rely on the fbcon either being present (we get called
6844 * during its initialisation to detect all boot displays, or it may
6845 * not even exist) or that it is large enough to satisfy the
6846 * requested mode.
6847 */
94352cf9
DV		 6848 fb = mode_fits_in_fbdev(dev, mode);
6849 if (fb == NULL) {
d2dff872 6850 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6851 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6852 old->release_fb = fb;
d2dff872
CW		 6853 } else
6854 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6855 if (IS_ERR(fb)) {
d2dff872 6856 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6857 mutex_unlock(&crtc->mutex);
0e8b3d3e 6858 return false;
79e53945 6859 }
79e53945 6860
c0c36b94 6861 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6862 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6863 if (old->release_fb)
6864 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6865 mutex_unlock(&crtc->mutex);
0e8b3d3e 6866 return false;
79e53945 6867 }
7173188d 6868
79e53945 6869 /* let the connector get through one full cycle before testing */
9d0498a2 6870 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6871 return true;
79e53945
JB		 6872}
6873
d2434ab7 6874void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6875 struct intel_load_detect_pipe *old)
79e53945 6876{
d2434ab7
DV		 6877 struct intel_encoder *intel_encoder =
6878 intel_attached_encoder(connector);
4ef69c7a 6879 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6880 struct drm_crtc *crtc = encoder->crtc;
79e53945 6881
d2dff872
CW		 6882 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6883 connector->base.id, drm_get_connector_name(connector),
6884 encoder->base.id, drm_get_encoder_name(encoder));
6885
8261b191 6886 if (old->load_detect_temp) {
fc303101
DV		 6887 to_intel_connector(connector)->new_encoder = NULL;
6888 intel_encoder->new_crtc = NULL;
6889 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6890
36206361
DV		 6891 if (old->release_fb) {
6892 drm_framebuffer_unregister_private(old->release_fb);
6893 drm_framebuffer_unreference(old->release_fb);
6894 }
d2dff872 6895
67c96400 6896 mutex_unlock(&crtc->mutex);
0622a53c 6897 return;
79e53945
JB		 6898 }
6899
c751ce4f 6900 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6901 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6902 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6903
6904 mutex_unlock(&crtc->mutex);
79e53945
JB		 6905}
6906
6907/* Returns the clock of the currently programmed mode of the given pipe. */
6908static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6909{
6910 struct drm_i915_private *dev_priv = dev->dev_private;
6911 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6912 int pipe = intel_crtc->pipe;
548f245b 6913 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6914 u32 fp;
6915 intel_clock_t clock;
6916
6917 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6918 fp = I915_READ(FP0(pipe));
79e53945 6919 else
39adb7a5 6920 fp = I915_READ(FP1(pipe));
79e53945
JB		 6921
6922 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6923 if (IS_PINEVIEW(dev)) {
6924 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6925 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6926 } else {
6927 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6928 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6929 }
6930
a6c45cf0 6931 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6932 if (IS_PINEVIEW(dev))
6933 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6934 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6935 else
6936 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6937 DPLL_FPA01_P1_POST_DIV_SHIFT);
6938
6939 switch (dpll & DPLL_MODE_MASK) {
6940 case DPLLB_MODE_DAC_SERIAL:
6941 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6942 5 : 10;
6943 break;
6944 case DPLLB_MODE_LVDS:
6945 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6946 7 : 14;
6947 break;
6948 default:
28c97730 6949 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6950 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6951 return 0;
6952 }
6953
ac58c3f0
DV		 6954 if (IS_PINEVIEW(dev))
6955 pineview_clock(96000, &clock);
6956 else
6957 i9xx_clock(96000, &clock);
79e53945
JB		 6958 } else {
6959 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6960
6961 if (is_lvds) {
6962 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6963 DPLL_FPA01_P1_POST_DIV_SHIFT);
6964 clock.p2 = 14;
6965
6966 if ((dpll & PLL_REF_INPUT_MASK) ==
6967 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6968 /* XXX: might not be 66MHz */
ac58c3f0 6969 i9xx_clock(66000, &clock);
79e53945 6970 } else
ac58c3f0 6971 i9xx_clock(48000, &clock);
79e53945
JB		 6972 } else {
6973 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6974 clock.p1 = 2;
6975 else {
6976 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6977 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6978 }
6979 if (dpll & PLL_P2_DIVIDE_BY_4)
6980 clock.p2 = 4;
6981 else
6982 clock.p2 = 2;
6983
ac58c3f0 6984 i9xx_clock(48000, &clock);
79e53945
JB		 6985 }
6986 }
6987
6988 /* XXX: It would be nice to validate the clocks, but we can't reuse
6989 * i830PllIsValid() because it relies on the xf86_config connector
6990 * configuration being accurate, which it isn't necessarily.
6991 */
6992
6993 return clock.dot;
6994}
6995
6996/** Returns the currently programmed mode of the given pipe. */
6997struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6998 struct drm_crtc *crtc)
6999{
548f245b 7000 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 7001 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 7002 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 7003 struct drm_display_mode *mode;
fe2b8f9d
PZ		 7004 int htot = I915_READ(HTOTAL(cpu_transcoder));
7005 int hsync = I915_READ(HSYNC(cpu_transcoder));
7006 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7007 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 7008
7009 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7010 if (!mode)
7011 return NULL;
7012
7013 mode->clock = intel_crtc_clock_get(dev, crtc);
7014 mode->hdisplay = (htot & 0xffff) + 1;
7015 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7016 mode->hsync_start = (hsync & 0xffff) + 1;
7017 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7018 mode->vdisplay = (vtot & 0xffff) + 1;
7019 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7020 mode->vsync_start = (vsync & 0xffff) + 1;
7021 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7022
7023 drm_mode_set_name(mode);
79e53945
JB		 7024
7025 return mode;
7026}
7027
3dec0095 7028static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7029{
7030 struct drm_device *dev = crtc->dev;
7031 drm_i915_private_t *dev_priv = dev->dev_private;
7032 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7033 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7034 int dpll_reg = DPLL(pipe);
7035 int dpll;
652c393a 7036
bad720ff 7037 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7038 return;
7039
7040 if (!dev_priv->lvds_downclock_avail)
7041 return;
7042
dbdc6479 7043 dpll = I915_READ(dpll_reg);
652c393a 7044 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7045 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7046
8ac5a6d5 7047 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7048
7049 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7050 I915_WRITE(dpll_reg, dpll);
9d0498a2 7051 intel_wait_for_vblank(dev, pipe);
dbdc6479 7052
652c393a
JB		 7053 dpll = I915_READ(dpll_reg);
7054 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7055 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7056 }
652c393a
JB		 7057}
7058
7059static void intel_decrease_pllclock(struct drm_crtc *crtc)
7060{
7061 struct drm_device *dev = crtc->dev;
7062 drm_i915_private_t *dev_priv = dev->dev_private;
7063 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7064
bad720ff 7065 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7066 return;
7067
7068 if (!dev_priv->lvds_downclock_avail)
7069 return;
7070
7071 /*
7072 * Since this is called by a timer, we should never get here in
7073 * the manual case.
7074 */
7075 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7076 int pipe = intel_crtc->pipe;
7077 int dpll_reg = DPLL(pipe);
7078 int dpll;
f6e5b160 7079
44d98a61 7080 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7081
8ac5a6d5 7082 assert_panel_unlocked(dev_priv, pipe);
652c393a 7083
dc257cf1 7084 dpll = I915_READ(dpll_reg);
652c393a
JB		 7085 dpll |= DISPLAY_RATE_SELECT_FPA1;
7086 I915_WRITE(dpll_reg, dpll);
9d0498a2 7087 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7088 dpll = I915_READ(dpll_reg);
7089 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7090 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7091 }
7092
7093}
7094
f047e395
CW		 7095void intel_mark_busy(struct drm_device *dev)
7096{
f047e395
CW		 7097 i915_update_gfx_val(dev->dev_private);
7098}
7099
7100void intel_mark_idle(struct drm_device *dev)
652c393a 7101{
652c393a 7102 struct drm_crtc *crtc;
652c393a
JB		 7103
7104 if (!i915_powersave)
7105 return;
7106
652c393a 7107 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7108 if (!crtc->fb)
7109 continue;
7110
725a5b54 7111 intel_decrease_pllclock(crtc);
652c393a 7112 }
652c393a
JB		 7113}
7114
725a5b54 7115void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
652c393a 7116{
f047e395
CW		 7117 struct drm_device *dev = obj->base.dev;
7118 struct drm_crtc *crtc;
652c393a 7119
f047e395 7120 if (!i915_powersave)
acb87dfb
CW		 7121 return;
7122
652c393a
JB		 7123 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7124 if (!crtc->fb)
7125 continue;
7126
f047e395 7127 if (to_intel_framebuffer(crtc->fb)->obj == obj)
725a5b54 7128 intel_increase_pllclock(crtc);
652c393a
JB		 7129 }
7130}
7131
79e53945
JB		 7132static void intel_crtc_destroy(struct drm_crtc *crtc)
7133{
7134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7135 struct drm_device *dev = crtc->dev;
7136 struct intel_unpin_work *work;
7137 unsigned long flags;
7138
7139 spin_lock_irqsave(&dev->event_lock, flags);
7140 work = intel_crtc->unpin_work;
7141 intel_crtc->unpin_work = NULL;
7142 spin_unlock_irqrestore(&dev->event_lock, flags);
7143
7144 if (work) {
7145 cancel_work_sync(&work->work);
7146 kfree(work);
7147 }
79e53945 7148
40ccc72b
MK		 7149 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7150
79e53945 7151 drm_crtc_cleanup(crtc);
67e77c5a 7152
79e53945
JB		 7153 kfree(intel_crtc);
7154}
7155
6b95a207
KH		 7156static void intel_unpin_work_fn(struct work_struct *__work)
7157{
7158 struct intel_unpin_work *work =
7159 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7160 struct drm_device *dev = work->crtc->dev;
6b95a207 7161
b4a98e57 7162 mutex_lock(&dev->struct_mutex);
1690e1eb 7163 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7164 drm_gem_object_unreference(&work->pending_flip_obj->base);
7165 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7166
b4a98e57
CW		 7167 intel_update_fbc(dev);
7168 mutex_unlock(&dev->struct_mutex);
7169
7170 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7171 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7172
6b95a207
KH		 7173 kfree(work);
7174}
7175
1afe3e9d 7176static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7177 struct drm_crtc *crtc)
6b95a207
KH		 7178{
7179 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7180 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7181 struct intel_unpin_work *work;
6b95a207
KH		 7182 unsigned long flags;
7183
7184 /* Ignore early vblank irqs */
7185 if (intel_crtc == NULL)
7186 return;
7187
7188 spin_lock_irqsave(&dev->event_lock, flags);
7189 work = intel_crtc->unpin_work;
e7d841ca
CW		 7190
7191 /* Ensure we don't miss a work->pending update ... */
7192 smp_rmb();
7193
7194 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7195 spin_unlock_irqrestore(&dev->event_lock, flags);
7196 return;
7197 }
7198
e7d841ca
CW		 7199 /* and that the unpin work is consistent wrt ->pending. */
7200 smp_rmb();
7201
6b95a207 7202 intel_crtc->unpin_work = NULL;
6b95a207 7203
45a066eb
RC		 7204 if (work->event)
7205 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7206
0af7e4df
MK		 7207 drm_vblank_put(dev, intel_crtc->pipe);
7208
6b95a207
KH		 7209 spin_unlock_irqrestore(&dev->event_lock, flags);
7210
2c10d571 7211 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7212
7213 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7214
7215 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7216}
7217
1afe3e9d
JB		 7218void intel_finish_page_flip(struct drm_device *dev, int pipe)
7219{
7220 drm_i915_private_t *dev_priv = dev->dev_private;
7221 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7222
49b14a5c 7223 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7224}
7225
7226void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7227{
7228 drm_i915_private_t *dev_priv = dev->dev_private;
7229 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7230
49b14a5c 7231 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7232}
7233
6b95a207
KH		 7234void intel_prepare_page_flip(struct drm_device *dev, int plane)
7235{
7236 drm_i915_private_t *dev_priv = dev->dev_private;
7237 struct intel_crtc *intel_crtc =
7238 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7239 unsigned long flags;
7240
e7d841ca
CW		 7241 /* NB: An MMIO update of the plane base pointer will also
7242 * generate a page-flip completion irq, i.e. every modeset
7243 * is also accompanied by a spurious intel_prepare_page_flip().
7244 */
6b95a207 7245 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7246 if (intel_crtc->unpin_work)
7247 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7248 spin_unlock_irqrestore(&dev->event_lock, flags);
7249}
7250
e7d841ca
CW		 7251inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7252{
7253 /* Ensure that the work item is consistent when activating it ... */
7254 smp_wmb();
7255 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7256 /* and that it is marked active as soon as the irq could fire. */
7257 smp_wmb();
7258}
7259
8c9f3aaf
JB		 7260static int intel_gen2_queue_flip(struct drm_device *dev,
7261 struct drm_crtc *crtc,
7262 struct drm_framebuffer *fb,
7263 struct drm_i915_gem_object *obj)
7264{
7265 struct drm_i915_private *dev_priv = dev->dev_private;
7266 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7267 u32 flip_mask;
6d90c952 7268 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7269 int ret;
7270
6d90c952 7271 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7272 if (ret)
83d4092b 7273 goto err;
8c9f3aaf 7274
6d90c952 7275 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7276 if (ret)
83d4092b 7277 goto err_unpin;
8c9f3aaf
JB		 7278
7279 /* Can't queue multiple flips, so wait for the previous
7280 * one to finish before executing the next.
7281 */
7282 if (intel_crtc->plane)
7283 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7284 else
7285 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7286 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7287 intel_ring_emit(ring, MI_NOOP);
7288 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7289 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7290 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7291 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7292 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7293
7294 intel_mark_page_flip_active(intel_crtc);
6d90c952 7295 intel_ring_advance(ring);
83d4092b
CW		 7296 return 0;
7297
7298err_unpin:
7299 intel_unpin_fb_obj(obj);
7300err:
8c9f3aaf
JB		 7301 return ret;
7302}
7303
7304static int intel_gen3_queue_flip(struct drm_device *dev,
7305 struct drm_crtc *crtc,
7306 struct drm_framebuffer *fb,
7307 struct drm_i915_gem_object *obj)
7308{
7309 struct drm_i915_private *dev_priv = dev->dev_private;
7310 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7311 u32 flip_mask;
6d90c952 7312 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7313 int ret;
7314
6d90c952 7315 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7316 if (ret)
83d4092b 7317 goto err;
8c9f3aaf 7318
6d90c952 7319 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7320 if (ret)
83d4092b 7321 goto err_unpin;
8c9f3aaf
JB		 7322
7323 if (intel_crtc->plane)
7324 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7325 else
7326 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7327 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7328 intel_ring_emit(ring, MI_NOOP);
7329 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7330 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7331 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7332 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7333 intel_ring_emit(ring, MI_NOOP);
7334
e7d841ca 7335 intel_mark_page_flip_active(intel_crtc);
6d90c952 7336 intel_ring_advance(ring);
83d4092b
CW		 7337 return 0;
7338
7339err_unpin:
7340 intel_unpin_fb_obj(obj);
7341err:
8c9f3aaf
JB		 7342 return ret;
7343}
7344
7345static int intel_gen4_queue_flip(struct drm_device *dev,
7346 struct drm_crtc *crtc,
7347 struct drm_framebuffer *fb,
7348 struct drm_i915_gem_object *obj)
7349{
7350 struct drm_i915_private *dev_priv = dev->dev_private;
7351 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7352 uint32_t pf, pipesrc;
6d90c952 7353 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7354 int ret;
7355
6d90c952 7356 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7357 if (ret)
83d4092b 7358 goto err;
8c9f3aaf 7359
6d90c952 7360 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7361 if (ret)
83d4092b 7362 goto err_unpin;
8c9f3aaf
JB		 7363
7364 /* i965+ uses the linear or tiled offsets from the
7365 * Display Registers (which do not change across a page-flip)
7366 * so we need only reprogram the base address.
7367 */
6d90c952
DV		 7368 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7369 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7370 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7371 intel_ring_emit(ring,
7372 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7373 obj->tiling_mode);
8c9f3aaf
JB		 7374
7375 /* XXX Enabling the panel-fitter across page-flip is so far
7376 * untested on non-native modes, so ignore it for now.
7377 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7378 */
7379 pf = 0;
7380 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7381 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7382
7383 intel_mark_page_flip_active(intel_crtc);
6d90c952 7384 intel_ring_advance(ring);
83d4092b
CW		 7385 return 0;
7386
7387err_unpin:
7388 intel_unpin_fb_obj(obj);
7389err:
8c9f3aaf
JB		 7390 return ret;
7391}
7392
7393static int intel_gen6_queue_flip(struct drm_device *dev,
7394 struct drm_crtc *crtc,
7395 struct drm_framebuffer *fb,
7396 struct drm_i915_gem_object *obj)
7397{
7398 struct drm_i915_private *dev_priv = dev->dev_private;
7399 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7400 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7401 uint32_t pf, pipesrc;
7402 int ret;
7403
6d90c952 7404 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7405 if (ret)
83d4092b 7406 goto err;
8c9f3aaf 7407
6d90c952 7408 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7409 if (ret)
83d4092b 7410 goto err_unpin;
8c9f3aaf 7411
6d90c952
DV		 7412 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7413 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7414 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7415 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7416
dc257cf1
DV		 7417 /* Contrary to the suggestions in the documentation,
7418 * "Enable Panel Fitter" does not seem to be required when page
7419 * flipping with a non-native mode, and worse causes a normal
7420 * modeset to fail.
7421 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7422 */
7423 pf = 0;
8c9f3aaf 7424 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7425 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7426
7427 intel_mark_page_flip_active(intel_crtc);
6d90c952 7428 intel_ring_advance(ring);
83d4092b
CW		 7429 return 0;
7430
7431err_unpin:
7432 intel_unpin_fb_obj(obj);
7433err:
8c9f3aaf
JB		 7434 return ret;
7435}
7436
7c9017e5
JB		 7437/*
7438 * On gen7 we currently use the blit ring because (in early silicon at least)
7439 * the render ring doesn't give us interrpts for page flip completion, which
7440 * means clients will hang after the first flip is queued. Fortunately the
7441 * blit ring generates interrupts properly, so use it instead.
7442 */
7443static int intel_gen7_queue_flip(struct drm_device *dev,
7444 struct drm_crtc *crtc,
7445 struct drm_framebuffer *fb,
7446 struct drm_i915_gem_object *obj)
7447{
7448 struct drm_i915_private *dev_priv = dev->dev_private;
7449 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7450 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7451 uint32_t plane_bit = 0;
7c9017e5
JB		 7452 int ret;
7453
7454 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7455 if (ret)
83d4092b 7456 goto err;
7c9017e5 7457
cb05d8de
DV		 7458 switch(intel_crtc->plane) {
7459 case PLANE_A:
7460 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7461 break;
7462 case PLANE_B:
7463 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7464 break;
7465 case PLANE_C:
7466 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7467 break;
7468 default:
7469 WARN_ONCE(1, "unknown plane in flip command\n");
7470 ret = -ENODEV;
ab3951eb 7471 goto err_unpin;
cb05d8de
DV		 7472 }
7473
7c9017e5
JB		 7474 ret = intel_ring_begin(ring, 4);
7475 if (ret)
83d4092b 7476 goto err_unpin;
7c9017e5 7477
cb05d8de 7478 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7479 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7480 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7481 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7482
7483 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7484 intel_ring_advance(ring);
83d4092b
CW		 7485 return 0;
7486
7487err_unpin:
7488 intel_unpin_fb_obj(obj);
7489err:
7c9017e5
JB		 7490 return ret;
7491}
7492
8c9f3aaf
JB		 7493static int intel_default_queue_flip(struct drm_device *dev,
7494 struct drm_crtc *crtc,
7495 struct drm_framebuffer *fb,
7496 struct drm_i915_gem_object *obj)
7497{
7498 return -ENODEV;
7499}
7500
6b95a207
KH		 7501static int intel_crtc_page_flip(struct drm_crtc *crtc,
7502 struct drm_framebuffer *fb,
7503 struct drm_pending_vblank_event *event)
7504{
7505 struct drm_device *dev = crtc->dev;
7506 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7507 struct drm_framebuffer *old_fb = crtc->fb;
7508 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7509 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7510 struct intel_unpin_work *work;
8c9f3aaf 7511 unsigned long flags;
52e68630 7512 int ret;
6b95a207 7513
e6a595d2
VS		 7514 /* Can't change pixel format via MI display flips. */
7515 if (fb->pixel_format != crtc->fb->pixel_format)
7516 return -EINVAL;
7517
7518 /*
7519 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7520 * Note that pitch changes could also affect these register.
7521 */
7522 if (INTEL_INFO(dev)->gen > 3 &&
7523 (fb->offsets[0] != crtc->fb->offsets[0] ||
7524 fb->pitches[0] != crtc->fb->pitches[0]))
7525 return -EINVAL;
7526
6b95a207
KH		 7527 work = kzalloc(sizeof *work, GFP_KERNEL);
7528 if (work == NULL)
7529 return -ENOMEM;
7530
6b95a207 7531 work->event = event;
b4a98e57 7532 work->crtc = crtc;
4a35f83b 7533 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7534 INIT_WORK(&work->work, intel_unpin_work_fn);
7535
7317c75e
JB		 7536 ret = drm_vblank_get(dev, intel_crtc->pipe);
7537 if (ret)
7538 goto free_work;
7539
6b95a207
KH		 7540 /* We borrow the event spin lock for protecting unpin_work */
7541 spin_lock_irqsave(&dev->event_lock, flags);
7542 if (intel_crtc->unpin_work) {
7543 spin_unlock_irqrestore(&dev->event_lock, flags);
7544 kfree(work);
7317c75e 7545 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7546
7547 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7548 return -EBUSY;
7549 }
7550 intel_crtc->unpin_work = work;
7551 spin_unlock_irqrestore(&dev->event_lock, flags);
7552
b4a98e57
CW		 7553 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7554 flush_workqueue(dev_priv->wq);
7555
79158103
CW		 7556 ret = i915_mutex_lock_interruptible(dev);
7557 if (ret)
7558 goto cleanup;
6b95a207 7559
75dfca80 7560 /* Reference the objects for the scheduled work. */
05394f39
CW		 7561 drm_gem_object_reference(&work->old_fb_obj->base);
7562 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7563
7564 crtc->fb = fb;
96b099fd 7565
e1f99ce6 7566 work->pending_flip_obj = obj;
e1f99ce6 7567
4e5359cd
SF		 7568 work->enable_stall_check = true;
7569
b4a98e57 7570 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7571 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7572
8c9f3aaf
JB		 7573 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7574 if (ret)
7575 goto cleanup_pending;
6b95a207 7576
7782de3b 7577 intel_disable_fbc(dev);
f047e395 7578 intel_mark_fb_busy(obj);
6b95a207
KH		 7579 mutex_unlock(&dev->struct_mutex);
7580
e5510fac
JB		 7581 trace_i915_flip_request(intel_crtc->plane, obj);
7582
6b95a207 7583 return 0;
96b099fd 7584
8c9f3aaf 7585cleanup_pending:
b4a98e57 7586 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7587 crtc->fb = old_fb;
05394f39
CW		 7588 drm_gem_object_unreference(&work->old_fb_obj->base);
7589 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7590 mutex_unlock(&dev->struct_mutex);
7591
79158103 7592cleanup:
96b099fd
CW		 7593 spin_lock_irqsave(&dev->event_lock, flags);
7594 intel_crtc->unpin_work = NULL;
7595 spin_unlock_irqrestore(&dev->event_lock, flags);
7596
7317c75e
JB		 7597 drm_vblank_put(dev, intel_crtc->pipe);
7598free_work:
96b099fd
CW		 7599 kfree(work);
7600
7601 return ret;
6b95a207
KH		 7602}
7603
f6e5b160 7604static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7605 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7606 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7607};
7608
50f56119
DV		 7609static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7610 struct drm_crtc *crtc)
7611{
7612 struct drm_device *dev;
7613 struct drm_crtc *tmp;
7614 int crtc_mask = 1;
47f1c6c9 7615
50f56119 7616 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7617
50f56119 7618 dev = crtc->dev;
47f1c6c9 7619
50f56119
DV		 7620 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7621 if (tmp == crtc)
7622 break;
7623 crtc_mask <<= 1;
7624 }
47f1c6c9 7625
50f56119
DV		 7626 if (encoder->possible_crtcs & crtc_mask)
7627 return true;
7628 return false;
47f1c6c9 7629}
79e53945 7630
9a935856
DV		 7631/**
7632 * intel_modeset_update_staged_output_state
7633 *
7634 * Updates the staged output configuration state, e.g. after we've read out the
7635 * current hw state.
7636 */
7637static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7638{
9a935856
DV		 7639 struct intel_encoder *encoder;
7640 struct intel_connector *connector;
f6e5b160 7641
9a935856
DV		 7642 list_for_each_entry(connector, &dev->mode_config.connector_list,
7643 base.head) {
7644 connector->new_encoder =
7645 to_intel_encoder(connector->base.encoder);
7646 }
f6e5b160 7647
9a935856
DV		 7648 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7649 base.head) {
7650 encoder->new_crtc =
7651 to_intel_crtc(encoder->base.crtc);
7652 }
f6e5b160
CW		 7653}
7654
9a935856
DV		 7655/**
7656 * intel_modeset_commit_output_state
7657 *
7658 * This function copies the stage display pipe configuration to the real one.
7659 */
7660static void intel_modeset_commit_output_state(struct drm_device *dev)
7661{
7662 struct intel_encoder *encoder;
7663 struct intel_connector *connector;
f6e5b160 7664
9a935856
DV		 7665 list_for_each_entry(connector, &dev->mode_config.connector_list,
7666 base.head) {
7667 connector->base.encoder = &connector->new_encoder->base;
7668 }
f6e5b160 7669
9a935856
DV		 7670 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7671 base.head) {
7672 encoder->base.crtc = &encoder->new_crtc->base;
7673 }
7674}
7675
050f7aeb
DV		 7676static void
7677connected_sink_compute_bpp(struct intel_connector * connector,
7678 struct intel_crtc_config *pipe_config)
7679{
7680 int bpp = pipe_config->pipe_bpp;
7681
7682 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7683 connector->base.base.id,
7684 drm_get_connector_name(&connector->base));
7685
7686 /* Don't use an invalid EDID bpc value */
7687 if (connector->base.display_info.bpc &&
7688 connector->base.display_info.bpc * 3 < bpp) {
7689 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7690 bpp, connector->base.display_info.bpc*3);
7691 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7692 }
7693
7694 /* Clamp bpp to 8 on screens without EDID 1.4 */
7695 if (connector->base.display_info.bpc == 0 && bpp > 24) {
7696 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7697 bpp);
7698 pipe_config->pipe_bpp = 24;
7699 }
7700}
7701
4e53c2e0 7702static int
050f7aeb
DV		 7703compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7704 struct drm_framebuffer *fb,
7705 struct intel_crtc_config *pipe_config)
4e53c2e0 7706{
050f7aeb
DV		 7707 struct drm_device *dev = crtc->base.dev;
7708 struct intel_connector *connector;
4e53c2e0
DV		 7709 int bpp;
7710
d42264b1
DV		 7711 switch (fb->pixel_format) {
7712 case DRM_FORMAT_C8:
4e53c2e0
DV		 7713 bpp = 8*3; /* since we go through a colormap */
7714 break;
d42264b1
DV		 7715 case DRM_FORMAT_XRGB1555:
7716 case DRM_FORMAT_ARGB1555:
7717 /* checked in intel_framebuffer_init already */
7718 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7719 return -EINVAL;
7720 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 7721 bpp = 6*3; /* min is 18bpp */
7722 break;
d42264b1
DV		 7723 case DRM_FORMAT_XBGR8888:
7724 case DRM_FORMAT_ABGR8888:
7725 /* checked in intel_framebuffer_init already */
7726 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7727 return -EINVAL;
7728 case DRM_FORMAT_XRGB8888:
7729 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 7730 bpp = 8*3;
7731 break;
d42264b1
DV		 7732 case DRM_FORMAT_XRGB2101010:
7733 case DRM_FORMAT_ARGB2101010:
7734 case DRM_FORMAT_XBGR2101010:
7735 case DRM_FORMAT_ABGR2101010:
7736 /* checked in intel_framebuffer_init already */
7737 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 7738 return -EINVAL;
4e53c2e0
DV		 7739 bpp = 10*3;
7740 break;
baba133a 7741 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7742 default:
7743 DRM_DEBUG_KMS("unsupported depth\n");
7744 return -EINVAL;
7745 }
7746
4e53c2e0
DV		 7747 pipe_config->pipe_bpp = bpp;
7748
7749 /* Clamp display bpp to EDID value */
7750 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 7751 base.head) {
1b829e05
DV		 7752 if (!connector->new_encoder ||
7753 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 7754 continue;
7755
050f7aeb 7756 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 7757 }
7758
7759 return bpp;
7760}
7761
c0b03411
DV		 7762static void intel_dump_pipe_config(struct intel_crtc *crtc,
7763 struct intel_crtc_config *pipe_config,
7764 const char *context)
7765{
7766 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7767 context, pipe_name(crtc->pipe));
7768
7769 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7770 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7771 pipe_config->pipe_bpp, pipe_config->dither);
7772 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7773 pipe_config->has_pch_encoder,
7774 pipe_config->fdi_lanes,
7775 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7776 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7777 pipe_config->fdi_m_n.tu);
7778 DRM_DEBUG_KMS("requested mode:\n");
7779 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7780 DRM_DEBUG_KMS("adjusted mode:\n");
7781 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7782 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7783 pipe_config->gmch_pfit.control,
7784 pipe_config->gmch_pfit.pgm_ratios,
7785 pipe_config->gmch_pfit.lvds_border_bits);
7786 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7787 pipe_config->pch_pfit.pos,
7788 pipe_config->pch_pfit.size);
42db64ef 7789 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
c0b03411
DV		 7790}
7791
accfc0c5
DV		 7792static bool check_encoder_cloning(struct drm_crtc *crtc)
7793{
7794 int num_encoders = 0;
7795 bool uncloneable_encoders = false;
7796 struct intel_encoder *encoder;
7797
7798 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
7799 base.head) {
7800 if (&encoder->new_crtc->base != crtc)
7801 continue;
7802
7803 num_encoders++;
7804 if (!encoder->cloneable)
7805 uncloneable_encoders = true;
7806 }
7807
7808 return !(num_encoders > 1 && uncloneable_encoders);
7809}
7810
b8cecdf5
DV		 7811static struct intel_crtc_config *
7812intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7813 struct drm_framebuffer *fb,
b8cecdf5 7814 struct drm_display_mode *mode)
ee7b9f93 7815{
7758a113 7816 struct drm_device *dev = crtc->dev;
7758a113
DV		 7817 struct drm_encoder_helper_funcs *encoder_funcs;
7818 struct intel_encoder *encoder;
b8cecdf5 7819 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 7820 int plane_bpp, ret = -EINVAL;
7821 bool retry = true;
ee7b9f93 7822
accfc0c5
DV		 7823 if (!check_encoder_cloning(crtc)) {
7824 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
7825 return ERR_PTR(-EINVAL);
7826 }
7827
b8cecdf5
DV		 7828 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7829 if (!pipe_config)
7758a113
DV		 7830 return ERR_PTR(-ENOMEM);
7831
b8cecdf5
DV		 7832 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7833 drm_mode_copy(&pipe_config->requested_mode, mode);
eccb140b 7834 pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
b8cecdf5 7835
050f7aeb
DV		 7836 /* Compute a starting value for pipe_config->pipe_bpp taking the source
7837 * plane pixel format and any sink constraints into account. Returns the
7838 * source plane bpp so that dithering can be selected on mismatches
7839 * after encoders and crtc also have had their say. */
7840 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7841 fb, pipe_config);
4e53c2e0
DV		 7842 if (plane_bpp < 0)
7843 goto fail;
7844
e29c22c0 7845encoder_retry:
ef1b460d 7846 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 7847 pipe_config->port_clock = 0;
ef1b460d 7848 pipe_config->pixel_multiplier = 1;
ff9a6750 7849
7758a113
DV		 7850 /* Pass our mode to the connectors and the CRTC to give them a chance to
7851 * adjust it according to limitations or connector properties, and also
7852 * a chance to reject the mode entirely.
47f1c6c9 7853 */
7758a113
DV		 7854 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7855 base.head) {
47f1c6c9 7856
7758a113
DV		 7857 if (&encoder->new_crtc->base != crtc)
7858 continue;
7ae89233
DV		 7859
7860 if (encoder->compute_config) {
7861 if (!(encoder->compute_config(encoder, pipe_config))) {
7862 DRM_DEBUG_KMS("Encoder config failure\n");
7863 goto fail;
7864 }
7865
7866 continue;
7867 }
7868
7758a113 7869 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7870 if (!(encoder_funcs->mode_fixup(&encoder->base,
7871 &pipe_config->requested_mode,
7872 &pipe_config->adjusted_mode))) {
7758a113
DV		 7873 DRM_DEBUG_KMS("Encoder fixup failed\n");
7874 goto fail;
7875 }
ee7b9f93 7876 }
47f1c6c9 7877
ff9a6750
DV		 7878 /* Set default port clock if not overwritten by the encoder. Needs to be
7879 * done afterwards in case the encoder adjusts the mode. */
7880 if (!pipe_config->port_clock)
7881 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
7882
e29c22c0
DV		 7883 ret = intel_crtc_compute_config(crtc, pipe_config);
7884 if (ret < 0) {
7758a113
DV		 7885 DRM_DEBUG_KMS("CRTC fixup failed\n");
7886 goto fail;
ee7b9f93 7887 }
e29c22c0
DV		 7888
7889 if (ret == RETRY) {
7890 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7891 ret = -EINVAL;
7892 goto fail;
7893 }
7894
7895 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7896 retry = false;
7897 goto encoder_retry;
7898 }
7899
4e53c2e0
DV		 7900 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7901 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7902 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7903
b8cecdf5 7904 return pipe_config;
7758a113 7905fail:
b8cecdf5 7906 kfree(pipe_config);
e29c22c0 7907 return ERR_PTR(ret);
ee7b9f93 7908}
47f1c6c9 7909
e2e1ed41
DV		 7910/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7911 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7912static void
7913intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7914 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7915{
7916 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7917 struct drm_device *dev = crtc->dev;
7918 struct intel_encoder *encoder;
7919 struct intel_connector *connector;
7920 struct drm_crtc *tmp_crtc;
79e53945 7921
e2e1ed41 7922 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7923
e2e1ed41
DV		 7924 /* Check which crtcs have changed outputs connected to them, these need
7925 * to be part of the prepare_pipes mask. We don't (yet) support global
7926 * modeset across multiple crtcs, so modeset_pipes will only have one
7927 * bit set at most. */
7928 list_for_each_entry(connector, &dev->mode_config.connector_list,
7929 base.head) {
7930 if (connector->base.encoder == &connector->new_encoder->base)
7931 continue;
79e53945 7932
e2e1ed41
DV		 7933 if (connector->base.encoder) {
7934 tmp_crtc = connector->base.encoder->crtc;
7935
7936 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7937 }
7938
7939 if (connector->new_encoder)
7940 *prepare_pipes |=
7941 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7942 }
7943
e2e1ed41
DV		 7944 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7945 base.head) {
7946 if (encoder->base.crtc == &encoder->new_crtc->base)
7947 continue;
7948
7949 if (encoder->base.crtc) {
7950 tmp_crtc = encoder->base.crtc;
7951
7952 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7953 }
7954
7955 if (encoder->new_crtc)
7956 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7957 }
7958
e2e1ed41
DV		 7959 /* Check for any pipes that will be fully disabled ... */
7960 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7961 base.head) {
7962 bool used = false;
22fd0fab 7963
e2e1ed41
DV		 7964 /* Don't try to disable disabled crtcs. */
7965 if (!intel_crtc->base.enabled)
7966 continue;
7e7d76c3 7967
e2e1ed41
DV		 7968 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7969 base.head) {
7970 if (encoder->new_crtc == intel_crtc)
7971 used = true;
7972 }
7973
7974 if (!used)
7975 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7976 }
7977
e2e1ed41
DV		 7978
7979 /* set_mode is also used to update properties on life display pipes. */
7980 intel_crtc = to_intel_crtc(crtc);
7981 if (crtc->enabled)
7982 *prepare_pipes |= 1 << intel_crtc->pipe;
7983
b6c5164d
DV		 7984 /*
7985 * For simplicity do a full modeset on any pipe where the output routing
7986 * changed. We could be more clever, but that would require us to be
7987 * more careful with calling the relevant encoder->mode_set functions.
7988 */
e2e1ed41
DV		 7989 if (*prepare_pipes)
7990 *modeset_pipes = *prepare_pipes;
7991
7992 /* ... and mask these out. */
7993 *modeset_pipes &= ~(*disable_pipes);
7994 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 7995
7996 /*
7997 * HACK: We don't (yet) fully support global modesets. intel_set_config
7998 * obies this rule, but the modeset restore mode of
7999 * intel_modeset_setup_hw_state does not.
8000 */
8001 *modeset_pipes &= 1 << intel_crtc->pipe;
8002 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 8003
8004 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8005 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 8006}
79e53945 8007
ea9d758d 8008static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 8009{
ea9d758d 8010 struct drm_encoder *encoder;
f6e5b160 8011 struct drm_device *dev = crtc->dev;
f6e5b160 8012
ea9d758d
DV		 8013 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8014 if (encoder->crtc == crtc)
8015 return true;
8016
8017 return false;
8018}
8019
8020static void
8021intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8022{
8023 struct intel_encoder *intel_encoder;
8024 struct intel_crtc *intel_crtc;
8025 struct drm_connector *connector;
8026
8027 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8028 base.head) {
8029 if (!intel_encoder->base.crtc)
8030 continue;
8031
8032 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8033
8034 if (prepare_pipes & (1 << intel_crtc->pipe))
8035 intel_encoder->connectors_active = false;
8036 }
8037
8038 intel_modeset_commit_output_state(dev);
8039
8040 /* Update computed state. */
8041 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8042 base.head) {
8043 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8044 }
8045
8046 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8047 if (!connector->encoder || !connector->encoder->crtc)
8048 continue;
8049
8050 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8051
8052 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8053 struct drm_property *dpms_property =
8054 dev->mode_config.dpms_property;
8055
ea9d758d 8056 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8057 drm_object_property_set_value(&connector->base,
68d34720
DV		 8058 dpms_property,
8059 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8060
8061 intel_encoder = to_intel_encoder(connector->encoder);
8062 intel_encoder->connectors_active = true;
8063 }
8064 }
8065
8066}
8067
25c5b266
DV		 8068#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8069 list_for_each_entry((intel_crtc), \
8070 &(dev)->mode_config.crtc_list, \
8071 base.head) \
0973f18f 8072 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8073
0e8ffe1b 8074static bool
2fa2fe9a
DV		 8075intel_pipe_config_compare(struct drm_device *dev,
8076 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8077 struct intel_crtc_config *pipe_config)
8078{
08a24034
DV		 8079#define PIPE_CONF_CHECK_I(name) \
8080 if (current_config->name != pipe_config->name) { \
8081 DRM_ERROR("mismatch in " #name " " \
8082 "(expected %i, found %i)\n", \
8083 current_config->name, \
8084 pipe_config->name); \
8085 return false; \
88adfff1
DV		 8086 }
8087
1bd1bd80
DV		 8088#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8089 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8090 DRM_ERROR("mismatch in " #name " " \
8091 "(expected %i, found %i)\n", \
8092 current_config->name & (mask), \
8093 pipe_config->name & (mask)); \
8094 return false; \
8095 }
8096
bb760063
DV		 8097#define PIPE_CONF_QUIRK(quirk) \
8098 ((current_config->quirks | pipe_config->quirks) & (quirk))
8099
eccb140b
DV		 8100 PIPE_CONF_CHECK_I(cpu_transcoder);
8101
08a24034
DV		 8102 PIPE_CONF_CHECK_I(has_pch_encoder);
8103 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8104 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8105 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8106 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8107 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8108 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8109
1bd1bd80
DV		 8110 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8111 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8112 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8113 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8114 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8115 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8116
8117 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8118 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8119 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8120 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8121 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8122 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8123
6c49f241
DV		 8124 if (!HAS_PCH_SPLIT(dev))
8125 PIPE_CONF_CHECK_I(pixel_multiplier);
8126
1bd1bd80
DV		 8127 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8128 DRM_MODE_FLAG_INTERLACE);
8129
bb760063
DV		 8130 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8131 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8132 DRM_MODE_FLAG_PHSYNC);
8133 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8134 DRM_MODE_FLAG_NHSYNC);
8135 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8136 DRM_MODE_FLAG_PVSYNC);
8137 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8138 DRM_MODE_FLAG_NVSYNC);
8139 }
045ac3b5 8140
1bd1bd80
DV		 8141 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8142 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8143
2fa2fe9a
DV		 8144 PIPE_CONF_CHECK_I(gmch_pfit.control);
8145 /* pfit ratios are autocomputed by the hw on gen4+ */
8146 if (INTEL_INFO(dev)->gen < 4)
8147 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8148 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8149 PIPE_CONF_CHECK_I(pch_pfit.pos);
8150 PIPE_CONF_CHECK_I(pch_pfit.size);
8151
42db64ef
PZ		 8152 PIPE_CONF_CHECK_I(ips_enabled);
8153
08a24034 8154#undef PIPE_CONF_CHECK_I
1bd1bd80 8155#undef PIPE_CONF_CHECK_FLAGS
bb760063 8156#undef PIPE_CONF_QUIRK
627eb5a3 8157
0e8ffe1b
DV		 8158 return true;
8159}
8160
b980514c 8161void
8af6cf88
DV		 8162intel_modeset_check_state(struct drm_device *dev)
8163{
0e8ffe1b 8164 drm_i915_private_t *dev_priv = dev->dev_private;
8af6cf88
DV		 8165 struct intel_crtc *crtc;
8166 struct intel_encoder *encoder;
8167 struct intel_connector *connector;
0e8ffe1b 8168 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8169
8170 list_for_each_entry(connector, &dev->mode_config.connector_list,
8171 base.head) {
8172 /* This also checks the encoder/connector hw state with the
8173 * ->get_hw_state callbacks. */
8174 intel_connector_check_state(connector);
8175
8176 WARN(&connector->new_encoder->base != connector->base.encoder,
8177 "connector's staged encoder doesn't match current encoder\n");
8178 }
8179
8180 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8181 base.head) {
8182 bool enabled = false;
8183 bool active = false;
8184 enum pipe pipe, tracked_pipe;
8185
8186 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8187 encoder->base.base.id,
8188 drm_get_encoder_name(&encoder->base));
8189
8190 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8191 "encoder's stage crtc doesn't match current crtc\n");
8192 WARN(encoder->connectors_active && !encoder->base.crtc,
8193 "encoder's active_connectors set, but no crtc\n");
8194
8195 list_for_each_entry(connector, &dev->mode_config.connector_list,
8196 base.head) {
8197 if (connector->base.encoder != &encoder->base)
8198 continue;
8199 enabled = true;
8200 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8201 active = true;
8202 }
8203 WARN(!!encoder->base.crtc != enabled,
8204 "encoder's enabled state mismatch "
8205 "(expected %i, found %i)\n",
8206 !!encoder->base.crtc, enabled);
8207 WARN(active && !encoder->base.crtc,
8208 "active encoder with no crtc\n");
8209
8210 WARN(encoder->connectors_active != active,
8211 "encoder's computed active state doesn't match tracked active state "
8212 "(expected %i, found %i)\n", active, encoder->connectors_active);
8213
8214 active = encoder->get_hw_state(encoder, &pipe);
8215 WARN(active != encoder->connectors_active,
8216 "encoder's hw state doesn't match sw tracking "
8217 "(expected %i, found %i)\n",
8218 encoder->connectors_active, active);
8219
8220 if (!encoder->base.crtc)
8221 continue;
8222
8223 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8224 WARN(active && pipe != tracked_pipe,
8225 "active encoder's pipe doesn't match"
8226 "(expected %i, found %i)\n",
8227 tracked_pipe, pipe);
8228
8229 }
8230
8231 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8232 base.head) {
8233 bool enabled = false;
8234 bool active = false;
8235
045ac3b5
JB		 8236 memset(&pipe_config, 0, sizeof(pipe_config));
8237
8af6cf88
DV		 8238 DRM_DEBUG_KMS("[CRTC:%d]\n",
8239 crtc->base.base.id);
8240
8241 WARN(crtc->active && !crtc->base.enabled,
8242 "active crtc, but not enabled in sw tracking\n");
8243
8244 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8245 base.head) {
8246 if (encoder->base.crtc != &crtc->base)
8247 continue;
8248 enabled = true;
8249 if (encoder->connectors_active)
8250 active = true;
8251 }
6c49f241 8252
8af6cf88
DV		 8253 WARN(active != crtc->active,
8254 "crtc's computed active state doesn't match tracked active state "
8255 "(expected %i, found %i)\n", active, crtc->active);
8256 WARN(enabled != crtc->base.enabled,
8257 "crtc's computed enabled state doesn't match tracked enabled state "
8258 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8259
0e8ffe1b
DV		 8260 active = dev_priv->display.get_pipe_config(crtc,
8261 &pipe_config);
6c49f241
DV		 8262 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8263 base.head) {
8264 if (encoder->base.crtc != &crtc->base)
8265 continue;
8266 if (encoder->get_config)
8267 encoder->get_config(encoder, &pipe_config);
8268 }
8269
0e8ffe1b
DV		 8270 WARN(crtc->active != active,
8271 "crtc active state doesn't match with hw state "
8272 "(expected %i, found %i)\n", crtc->active, active);
8273
c0b03411
DV		 8274 if (active &&
8275 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8276 WARN(1, "pipe state doesn't match!\n");
8277 intel_dump_pipe_config(crtc, &pipe_config,
8278 "[hw state]");
8279 intel_dump_pipe_config(crtc, &crtc->config,
8280 "[sw state]");
8281 }
8af6cf88
DV		 8282 }
8283}
8284
f30da187
DV		 8285static int __intel_set_mode(struct drm_crtc *crtc,
8286 struct drm_display_mode *mode,
8287 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 8288{
8289 struct drm_device *dev = crtc->dev;
dbf2b54e 8290 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 8291 struct drm_display_mode *saved_mode, *saved_hwmode;
8292 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 8293 struct intel_crtc *intel_crtc;
8294 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 8295 int ret = 0;
a6778b3c 8296
3ac18232 8297 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 8298 if (!saved_mode)
8299 return -ENOMEM;
3ac18232 8300 saved_hwmode = saved_mode + 1;
a6778b3c 8301
e2e1ed41 8302 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 8303 &prepare_pipes, &disable_pipes);
8304
3ac18232
TG		 8305 *saved_hwmode = crtc->hwmode;
8306 *saved_mode = crtc->mode;
a6778b3c 8307
25c5b266
DV		 8308 /* Hack: Because we don't (yet) support global modeset on multiple
8309 * crtcs, we don't keep track of the new mode for more than one crtc.
8310 * Hence simply check whether any bit is set in modeset_pipes in all the
8311 * pieces of code that are not yet converted to deal with mutliple crtcs
8312 * changing their mode at the same time. */
25c5b266 8313 if (modeset_pipes) {
4e53c2e0 8314 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 8315 if (IS_ERR(pipe_config)) {
8316 ret = PTR_ERR(pipe_config);
8317 pipe_config = NULL;
8318
3ac18232 8319 goto out;
25c5b266 8320 }
c0b03411
DV		 8321 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8322 "[modeset]");
25c5b266 8323 }
a6778b3c 8324
460da916
DV		 8325 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8326 intel_crtc_disable(&intel_crtc->base);
8327
ea9d758d
DV		 8328 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8329 if (intel_crtc->base.enabled)
8330 dev_priv->display.crtc_disable(&intel_crtc->base);
8331 }
a6778b3c 8332
6c4c86f5
DV		 8333 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8334 * to set it here already despite that we pass it down the callchain.
f6e5b160 8335 */
b8cecdf5 8336 if (modeset_pipes) {
25c5b266 8337 crtc->mode = *mode;
b8cecdf5
DV		 8338 /* mode_set/enable/disable functions rely on a correct pipe
8339 * config. */
8340 to_intel_crtc(crtc)->config = *pipe_config;
8341 }
7758a113 8342
ea9d758d
DV		 8343 /* Only after disabling all output pipelines that will be changed can we
8344 * update the the output configuration. */
8345 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8346
47fab737
DV		 8347 if (dev_priv->display.modeset_global_resources)
8348 dev_priv->display.modeset_global_resources(dev);
8349
a6778b3c
DV		 8350 /* Set up the DPLL and any encoders state that needs to adjust or depend
8351 * on the DPLL.
f6e5b160 8352 */
25c5b266 8353 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8354 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8355 x, y, fb);
8356 if (ret)
8357 goto done;
a6778b3c
DV		 8358 }
8359
8360 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8361 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8362 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8363
25c5b266
DV		 8364 if (modeset_pipes) {
8365 /* Store real post-adjustment hardware mode. */
b8cecdf5 8366 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8367
25c5b266
DV		 8368 /* Calculate and store various constants which
8369 * are later needed by vblank and swap-completion
8370 * timestamping. They are derived from true hwmode.
8371 */
8372 drm_calc_timestamping_constants(crtc);
8373 }
a6778b3c
DV		 8374
8375 /* FIXME: add subpixel order */
8376done:
c0c36b94 8377 if (ret && crtc->enabled) {
3ac18232
TG		 8378 crtc->hwmode = *saved_hwmode;
8379 crtc->mode = *saved_mode;
a6778b3c
DV		 8380 }
8381
3ac18232 8382out:
b8cecdf5 8383 kfree(pipe_config);
3ac18232 8384 kfree(saved_mode);
a6778b3c 8385 return ret;
f6e5b160
CW		 8386}
8387
f30da187
DV		 8388int intel_set_mode(struct drm_crtc *crtc,
8389 struct drm_display_mode *mode,
8390 int x, int y, struct drm_framebuffer *fb)
8391{
8392 int ret;
8393
8394 ret = __intel_set_mode(crtc, mode, x, y, fb);
8395
8396 if (ret == 0)
8397 intel_modeset_check_state(crtc->dev);
8398
8399 return ret;
8400}
8401
c0c36b94
CW		 8402void intel_crtc_restore_mode(struct drm_crtc *crtc)
8403{
8404 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8405}
8406
25c5b266
DV		 8407#undef for_each_intel_crtc_masked
8408
d9e55608
DV		 8409static void intel_set_config_free(struct intel_set_config *config)
8410{
8411 if (!config)
8412 return;
8413
1aa4b628
DV		 8414 kfree(config->save_connector_encoders);
8415 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8416 kfree(config);
8417}
8418
85f9eb71
DV		 8419static int intel_set_config_save_state(struct drm_device *dev,
8420 struct intel_set_config *config)
8421{
85f9eb71
DV		 8422 struct drm_encoder *encoder;
8423 struct drm_connector *connector;
8424 int count;
8425
1aa4b628
DV		 8426 config->save_encoder_crtcs =
8427 kcalloc(dev->mode_config.num_encoder,
8428 sizeof(struct drm_crtc *), GFP_KERNEL);
8429 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8430 return -ENOMEM;
8431
1aa4b628
DV		 8432 config->save_connector_encoders =
8433 kcalloc(dev->mode_config.num_connector,
8434 sizeof(struct drm_encoder *), GFP_KERNEL);
8435 if (!config->save_connector_encoders)
85f9eb71
DV		 8436 return -ENOMEM;
8437
8438 /* Copy data. Note that driver private data is not affected.
8439 * Should anything bad happen only the expected state is
8440 * restored, not the drivers personal bookkeeping.
8441 */
85f9eb71
DV		 8442 count = 0;
8443 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 8444 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 8445 }
8446
8447 count = 0;
8448 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 8449 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 8450 }
8451
8452 return 0;
8453}
8454
8455static void intel_set_config_restore_state(struct drm_device *dev,
8456 struct intel_set_config *config)
8457{
9a935856
DV		 8458 struct intel_encoder *encoder;
8459 struct intel_connector *connector;
85f9eb71
DV		 8460 int count;
8461
85f9eb71 8462 count = 0;
9a935856
DV		 8463 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8464 encoder->new_crtc =
8465 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 8466 }
8467
8468 count = 0;
9a935856
DV		 8469 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8470 connector->new_encoder =
8471 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8472 }
8473}
8474
5e2b584e
DV		 8475static void
8476intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8477 struct intel_set_config *config)
8478{
8479
8480 /* We should be able to check here if the fb has the same properties
8481 * and then just flip_or_move it */
8482 if (set->crtc->fb != set->fb) {
8483 /* If we have no fb then treat it as a full mode set */
8484 if (set->crtc->fb == NULL) {
8485 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8486 config->mode_changed = true;
8487 } else if (set->fb == NULL) {
8488 config->mode_changed = true;
72f4901e
DV		 8489 } else if (set->fb->pixel_format !=
8490 set->crtc->fb->pixel_format) {
5e2b584e
DV		 8491 config->mode_changed = true;
8492 } else
8493 config->fb_changed = true;
8494 }
8495
835c5873 8496 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8497 config->fb_changed = true;
8498
8499 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8500 DRM_DEBUG_KMS("modes are different, full mode set\n");
8501 drm_mode_debug_printmodeline(&set->crtc->mode);
8502 drm_mode_debug_printmodeline(set->mode);
8503 config->mode_changed = true;
8504 }
8505}
8506
2e431051 8507static int
9a935856
DV		 8508intel_modeset_stage_output_state(struct drm_device *dev,
8509 struct drm_mode_set *set,
8510 struct intel_set_config *config)
50f56119 8511{
85f9eb71 8512 struct drm_crtc *new_crtc;
9a935856
DV		 8513 struct intel_connector *connector;
8514 struct intel_encoder *encoder;
2e431051 8515 int count, ro;
50f56119 8516
9abdda74 8517 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8518 * of connectors. For paranoia, double-check this. */
8519 WARN_ON(!set->fb && (set->num_connectors != 0));
8520 WARN_ON(set->fb && (set->num_connectors == 0));
8521
50f56119 8522 count = 0;
9a935856
DV		 8523 list_for_each_entry(connector, &dev->mode_config.connector_list,
8524 base.head) {
8525 /* Otherwise traverse passed in connector list and get encoders
8526 * for them. */
50f56119 8527 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8528 if (set->connectors[ro] == &connector->base) {
8529 connector->new_encoder = connector->encoder;
50f56119
DV		 8530 break;
8531 }
8532 }
8533
9a935856
DV		 8534 /* If we disable the crtc, disable all its connectors. Also, if
8535 * the connector is on the changing crtc but not on the new
8536 * connector list, disable it. */
8537 if ((!set->fb || ro == set->num_connectors) &&
8538 connector->base.encoder &&
8539 connector->base.encoder->crtc == set->crtc) {
8540 connector->new_encoder = NULL;
8541
8542 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8543 connector->base.base.id,
8544 drm_get_connector_name(&connector->base));
8545 }
8546
8547
8548 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8549 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8550 config->mode_changed = true;
50f56119
DV		 8551 }
8552 }
9a935856 8553 /* connector->new_encoder is now updated for all connectors. */
50f56119 8554
9a935856 8555 /* Update crtc of enabled connectors. */
50f56119 8556 count = 0;
9a935856
DV		 8557 list_for_each_entry(connector, &dev->mode_config.connector_list,
8558 base.head) {
8559 if (!connector->new_encoder)
50f56119
DV		 8560 continue;
8561
9a935856 8562 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8563
8564 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8565 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8566 new_crtc = set->crtc;
8567 }
8568
8569 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8570 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8571 new_crtc)) {
5e2b584e 8572 return -EINVAL;
50f56119 8573 }
9a935856
DV		 8574 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8575
8576 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8577 connector->base.base.id,
8578 drm_get_connector_name(&connector->base),
8579 new_crtc->base.id);
8580 }
8581
8582 /* Check for any encoders that needs to be disabled. */
8583 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8584 base.head) {
8585 list_for_each_entry(connector,
8586 &dev->mode_config.connector_list,
8587 base.head) {
8588 if (connector->new_encoder == encoder) {
8589 WARN_ON(!connector->new_encoder->new_crtc);
8590
8591 goto next_encoder;
8592 }
8593 }
8594 encoder->new_crtc = NULL;
8595next_encoder:
8596 /* Only now check for crtc changes so we don't miss encoders
8597 * that will be disabled. */
8598 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8599 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8600 config->mode_changed = true;
50f56119
DV		 8601 }
8602 }
9a935856 8603 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8604
2e431051
DV		 8605 return 0;
8606}
8607
8608static int intel_crtc_set_config(struct drm_mode_set *set)
8609{
8610 struct drm_device *dev;
2e431051
DV		 8611 struct drm_mode_set save_set;
8612 struct intel_set_config *config;
8613 int ret;
2e431051 8614
8d3e375e
DV		 8615 BUG_ON(!set);
8616 BUG_ON(!set->crtc);
8617 BUG_ON(!set->crtc->helper_private);
2e431051 8618
7e53f3a4
DV		 8619 /* Enforce sane interface api - has been abused by the fb helper. */
8620 BUG_ON(!set->mode && set->fb);
8621 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8622
2e431051
DV		 8623 if (set->fb) {
8624 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8625 set->crtc->base.id, set->fb->base.id,
8626 (int)set->num_connectors, set->x, set->y);
8627 } else {
8628 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8629 }
8630
8631 dev = set->crtc->dev;
8632
8633 ret = -ENOMEM;
8634 config = kzalloc(sizeof(*config), GFP_KERNEL);
8635 if (!config)
8636 goto out_config;
8637
8638 ret = intel_set_config_save_state(dev, config);
8639 if (ret)
8640 goto out_config;
8641
8642 save_set.crtc = set->crtc;
8643 save_set.mode = &set->crtc->mode;
8644 save_set.x = set->crtc->x;
8645 save_set.y = set->crtc->y;
8646 save_set.fb = set->crtc->fb;
8647
8648 /* Compute whether we need a full modeset, only an fb base update or no
8649 * change at all. In the future we might also check whether only the
8650 * mode changed, e.g. for LVDS where we only change the panel fitter in
8651 * such cases. */
8652 intel_set_config_compute_mode_changes(set, config);
8653
9a935856 8654 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8655 if (ret)
8656 goto fail;
8657
5e2b584e 8658 if (config->mode_changed) {
c0c36b94
CW		 8659 ret = intel_set_mode(set->crtc, set->mode,
8660 set->x, set->y, set->fb);
8661 if (ret) {
8662 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8663 set->crtc->base.id, ret);
87f1faa6
DV		 8664 goto fail;
8665 }
5e2b584e 8666 } else if (config->fb_changed) {
4878cae2
VS		 8667 intel_crtc_wait_for_pending_flips(set->crtc);
8668
4f660f49 8669 ret = intel_pipe_set_base(set->crtc,
94352cf9 8670 set->x, set->y, set->fb);
50f56119
DV		 8671 }
8672
d9e55608
DV		 8673 intel_set_config_free(config);
8674
50f56119
DV		 8675 return 0;
8676
8677fail:
85f9eb71 8678 intel_set_config_restore_state(dev, config);
50f56119
DV		 8679
8680 /* Try to restore the config */
5e2b584e 8681 if (config->mode_changed &&
c0c36b94
CW		 8682 intel_set_mode(save_set.crtc, save_set.mode,
8683 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8684 DRM_ERROR("failed to restore config after modeset failure\n");
8685
d9e55608
DV		 8686out_config:
8687 intel_set_config_free(config);
50f56119
DV		 8688 return ret;
8689}
f6e5b160
CW		 8690
8691static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8692 .cursor_set = intel_crtc_cursor_set,
8693 .cursor_move = intel_crtc_cursor_move,
8694 .gamma_set = intel_crtc_gamma_set,
50f56119 8695 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8696 .destroy = intel_crtc_destroy,
8697 .page_flip = intel_crtc_page_flip,
8698};
8699
79f689aa
PZ		 8700static void intel_cpu_pll_init(struct drm_device *dev)
8701{
affa9354 8702 if (HAS_DDI(dev))
79f689aa
PZ		 8703 intel_ddi_pll_init(dev);
8704}
8705
ee7b9f93
JB		 8706static void intel_pch_pll_init(struct drm_device *dev)
8707{
8708 drm_i915_private_t *dev_priv = dev->dev_private;
8709 int i;
8710
8711 if (dev_priv->num_pch_pll == 0) {
8712 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8713 return;
8714 }
8715
8716 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8717 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8718 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8719 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8720 }
8721}
8722
b358d0a6 8723static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8724{
22fd0fab 8725 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8726 struct intel_crtc *intel_crtc;
8727 int i;
8728
8729 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8730 if (intel_crtc == NULL)
8731 return;
8732
8733 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8734
8735 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8736 for (i = 0; i < 256; i++) {
8737 intel_crtc->lut_r[i] = i;
8738 intel_crtc->lut_g[i] = i;
8739 intel_crtc->lut_b[i] = i;
8740 }
8741
80824003
JB		 8742 /* Swap pipes & planes for FBC on pre-965 */
8743 intel_crtc->pipe = pipe;
8744 intel_crtc->plane = pipe;
e2e767ab 8745 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8746 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8747 intel_crtc->plane = !pipe;
80824003
JB		 8748 }
8749
22fd0fab
JB		 8750 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8751 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8752 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8753 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8754
79e53945 8755 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8756}
8757
08d7b3d1 8758int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8759 struct drm_file *file)
08d7b3d1 8760{
08d7b3d1 8761 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8762 struct drm_mode_object *drmmode_obj;
8763 struct intel_crtc *crtc;
08d7b3d1 8764
1cff8f6b
DV		 8765 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8766 return -ENODEV;
08d7b3d1 8767
c05422d5
DV		 8768 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8769 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8770
c05422d5 8771 if (!drmmode_obj) {
08d7b3d1
CW		 8772 DRM_ERROR("no such CRTC id\n");
8773 return -EINVAL;
8774 }
8775
c05422d5
DV		 8776 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8777 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8778
c05422d5 8779 return 0;
08d7b3d1
CW		 8780}
8781
66a9278e 8782static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8783{
66a9278e
DV		 8784 struct drm_device *dev = encoder->base.dev;
8785 struct intel_encoder *source_encoder;
79e53945 8786 int index_mask = 0;
79e53945
JB		 8787 int entry = 0;
8788
66a9278e
DV		 8789 list_for_each_entry(source_encoder,
8790 &dev->mode_config.encoder_list, base.head) {
8791
8792 if (encoder == source_encoder)
79e53945 8793 index_mask |= (1 << entry);
66a9278e
DV		 8794
8795 /* Intel hw has only one MUX where enocoders could be cloned. */
8796 if (encoder->cloneable && source_encoder->cloneable)
8797 index_mask |= (1 << entry);
8798
79e53945
JB		 8799 entry++;
8800 }
4ef69c7a 8801
79e53945
JB		 8802 return index_mask;
8803}
8804
4d302442
CW		 8805static bool has_edp_a(struct drm_device *dev)
8806{
8807 struct drm_i915_private *dev_priv = dev->dev_private;
8808
8809 if (!IS_MOBILE(dev))
8810 return false;
8811
8812 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8813 return false;
8814
8815 if (IS_GEN5(dev) &&
8816 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8817 return false;
8818
8819 return true;
8820}
8821
79e53945
JB		 8822static void intel_setup_outputs(struct drm_device *dev)
8823{
725e30ad 8824 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8825 struct intel_encoder *encoder;
cb0953d7 8826 bool dpd_is_edp = false;
f3cfcba6 8827 bool has_lvds;
79e53945 8828
f3cfcba6 8829 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8830 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8831 /* disable the panel fitter on everything but LVDS */
8832 I915_WRITE(PFIT_CONTROL, 0);
8833 }
79e53945 8834
c40c0f5b 8835 if (!IS_ULT(dev))
79935fca 8836 intel_crt_init(dev);
cb0953d7 8837
affa9354 8838 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8839 int found;
8840
8841 /* Haswell uses DDI functions to detect digital outputs */
8842 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8843 /* DDI A only supports eDP */
8844 if (found)
8845 intel_ddi_init(dev, PORT_A);
8846
8847 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8848 * register */
8849 found = I915_READ(SFUSE_STRAP);
8850
8851 if (found & SFUSE_STRAP_DDIB_DETECTED)
8852 intel_ddi_init(dev, PORT_B);
8853 if (found & SFUSE_STRAP_DDIC_DETECTED)
8854 intel_ddi_init(dev, PORT_C);
8855 if (found & SFUSE_STRAP_DDID_DETECTED)
8856 intel_ddi_init(dev, PORT_D);
8857 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8858 int found;
270b3042
DV		 8859 dpd_is_edp = intel_dpd_is_edp(dev);
8860
8861 if (has_edp_a(dev))
8862 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8863
dc0fa718 8864 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 8865 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8866 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8867 if (!found)
e2debe91 8868 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 8869 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8870 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8871 }
8872
dc0fa718 8873 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 8874 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 8875
dc0fa718 8876 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 8877 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 8878
5eb08b69 8879 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8880 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8881
270b3042 8882 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8883 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 8884 } else if (IS_VALLEYVIEW(dev)) {
19c03924 8885 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 8886 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8887 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 8888
dc0fa718 8889 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 8890 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8891 PORT_B);
67cfc203
VS		 8892 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8893 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 8894 }
103a196f 8895 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8896 bool found = false;
7d57382e 8897
e2debe91 8898 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8899 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 8900 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 8901 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8902 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 8903 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 8904 }
27185ae1 8905
e7281eab 8906 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 8907 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 8908 }
13520b05
KH		 8909
8910 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8911
e2debe91 8912 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8913 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 8914 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 8915 }
27185ae1 8916
e2debe91 8917 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 8918
b01f2c3a
JB		 8919 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8920 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 8921 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 8922 }
e7281eab 8923 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 8924 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 8925 }
27185ae1 8926
b01f2c3a 8927 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 8928 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 8929 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 8930 } else if (IS_GEN2(dev))
79e53945
JB		 8931 intel_dvo_init(dev);
8932
103a196f 8933 if (SUPPORTS_TV(dev))
79e53945
JB		 8934 intel_tv_init(dev);
8935
4ef69c7a
CW		 8936 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8937 encoder->base.possible_crtcs = encoder->crtc_mask;
8938 encoder->base.possible_clones =
66a9278e 8939 intel_encoder_clones(encoder);
79e53945 8940 }
47356eb6 8941
dde86e2d 8942 intel_init_pch_refclk(dev);
270b3042
DV		 8943
8944 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8945}
8946
8947static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8948{
8949 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8950
8951 drm_framebuffer_cleanup(fb);
05394f39 8952 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8953
8954 kfree(intel_fb);
8955}
8956
8957static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8958 struct drm_file *file,
79e53945
JB		 8959 unsigned int *handle)
8960{
8961 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8962 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8963
05394f39 8964 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8965}
8966
8967static const struct drm_framebuffer_funcs intel_fb_funcs = {
8968 .destroy = intel_user_framebuffer_destroy,
8969 .create_handle = intel_user_framebuffer_create_handle,
8970};
8971
38651674
DA		 8972int intel_framebuffer_init(struct drm_device *dev,
8973 struct intel_framebuffer *intel_fb,
308e5bcb 8974 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8975 struct drm_i915_gem_object *obj)
79e53945 8976{
79e53945
JB		 8977 int ret;
8978
c16ed4be
CW		 8979 if (obj->tiling_mode == I915_TILING_Y) {
8980 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 8981 return -EINVAL;
c16ed4be 8982 }
57cd6508 8983
c16ed4be
CW		 8984 if (mode_cmd->pitches[0] & 63) {
8985 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8986 mode_cmd->pitches[0]);
57cd6508 8987 return -EINVAL;
c16ed4be 8988 }
57cd6508 8989
5d7bd705 8990 /* FIXME <= Gen4 stride limits are bit unclear */
c16ed4be
CW		 8991 if (mode_cmd->pitches[0] > 32768) {
8992 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8993 mode_cmd->pitches[0]);
5d7bd705 8994 return -EINVAL;
c16ed4be 8995 }
5d7bd705
VS		 8996
8997 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 8998 mode_cmd->pitches[0] != obj->stride) {
8999 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9000 mode_cmd->pitches[0], obj->stride);
5d7bd705 9001 return -EINVAL;
c16ed4be 9002 }
5d7bd705 9003
57779d06 9004 /* Reject formats not supported by any plane early. */
308e5bcb 9005 switch (mode_cmd->pixel_format) {
57779d06 9006 case DRM_FORMAT_C8:
04b3924d
VS		 9007 case DRM_FORMAT_RGB565:
9008 case DRM_FORMAT_XRGB8888:
9009 case DRM_FORMAT_ARGB8888:
57779d06
VS		 9010 break;
9011 case DRM_FORMAT_XRGB1555:
9012 case DRM_FORMAT_ARGB1555:
c16ed4be
CW		 9013 if (INTEL_INFO(dev)->gen > 3) {
9014 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 9015 return -EINVAL;
c16ed4be 9016 }
57779d06
VS		 9017 break;
9018 case DRM_FORMAT_XBGR8888:
9019 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 9020 case DRM_FORMAT_XRGB2101010:
9021 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 9022 case DRM_FORMAT_XBGR2101010:
9023 case DRM_FORMAT_ABGR2101010:
c16ed4be
CW		 9024 if (INTEL_INFO(dev)->gen < 4) {
9025 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 9026 return -EINVAL;
c16ed4be 9027 }
b5626747 9028 break;
04b3924d
VS		 9029 case DRM_FORMAT_YUYV:
9030 case DRM_FORMAT_UYVY:
9031 case DRM_FORMAT_YVYU:
9032 case DRM_FORMAT_VYUY:
c16ed4be
CW		 9033 if (INTEL_INFO(dev)->gen < 5) {
9034 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 9035 return -EINVAL;
c16ed4be 9036 }
57cd6508
CW		 9037 break;
9038 default:
c16ed4be 9039 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 9040 return -EINVAL;
9041 }
9042
90f9a336
VS		 9043 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9044 if (mode_cmd->offsets[0] != 0)
9045 return -EINVAL;
9046
c7d73f6a
DV		 9047 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9048 intel_fb->obj = obj;
9049
79e53945
JB		 9050 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9051 if (ret) {
9052 DRM_ERROR("framebuffer init failed %d\n", ret);
9053 return ret;
9054 }
9055
79e53945
JB		 9056 return 0;
9057}
9058
79e53945
JB		 9059static struct drm_framebuffer *
9060intel_user_framebuffer_create(struct drm_device *dev,
9061 struct drm_file *filp,
308e5bcb 9062 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 9063{
05394f39 9064 struct drm_i915_gem_object *obj;
79e53945 9065
308e5bcb
JB		 9066 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9067 mode_cmd->handles[0]));
c8725226 9068 if (&obj->base == NULL)
cce13ff7 9069 return ERR_PTR(-ENOENT);
79e53945 9070
d2dff872 9071 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 9072}
9073
79e53945 9074static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 9075 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 9076 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 9077};
9078
e70236a8
JB		 9079/* Set up chip specific display functions */
9080static void intel_init_display(struct drm_device *dev)
9081{
9082 struct drm_i915_private *dev_priv = dev->dev_private;
9083
ee9300bb
DV		 9084 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9085 dev_priv->display.find_dpll = g4x_find_best_dpll;
9086 else if (IS_VALLEYVIEW(dev))
9087 dev_priv->display.find_dpll = vlv_find_best_dpll;
9088 else if (IS_PINEVIEW(dev))
9089 dev_priv->display.find_dpll = pnv_find_best_dpll;
9090 else
9091 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9092
affa9354 9093 if (HAS_DDI(dev)) {
0e8ffe1b 9094 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 9095 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 9096 dev_priv->display.crtc_enable = haswell_crtc_enable;
9097 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 9098 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 9099 dev_priv->display.update_plane = ironlake_update_plane;
9100 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 9101 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 9102 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 9103 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9104 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 9105 dev_priv->display.off = ironlake_crtc_off;
17638cd6 9106 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 9107 } else if (IS_VALLEYVIEW(dev)) {
9108 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9109 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9110 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9111 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9112 dev_priv->display.off = i9xx_crtc_off;
9113 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9114 } else {
0e8ffe1b 9115 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 9116 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 9117 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9118 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 9119 dev_priv->display.off = i9xx_crtc_off;
17638cd6 9120 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9121 }
e70236a8 9122
e70236a8 9123 /* Returns the core display clock speed */
25eb05fc
JB		 9124 if (IS_VALLEYVIEW(dev))
9125 dev_priv->display.get_display_clock_speed =
9126 valleyview_get_display_clock_speed;
9127 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 9128 dev_priv->display.get_display_clock_speed =
9129 i945_get_display_clock_speed;
9130 else if (IS_I915G(dev))
9131 dev_priv->display.get_display_clock_speed =
9132 i915_get_display_clock_speed;
f2b115e6 9133 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 9134 dev_priv->display.get_display_clock_speed =
9135 i9xx_misc_get_display_clock_speed;
9136 else if (IS_I915GM(dev))
9137 dev_priv->display.get_display_clock_speed =
9138 i915gm_get_display_clock_speed;
9139 else if (IS_I865G(dev))
9140 dev_priv->display.get_display_clock_speed =
9141 i865_get_display_clock_speed;
f0f8a9ce 9142 else if (IS_I85X(dev))
e70236a8
JB		 9143 dev_priv->display.get_display_clock_speed =
9144 i855_get_display_clock_speed;
9145 else /* 852, 830 */
9146 dev_priv->display.get_display_clock_speed =
9147 i830_get_display_clock_speed;
9148
7f8a8569 9149 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 9150 if (IS_GEN5(dev)) {
674cf967 9151 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 9152 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 9153 } else if (IS_GEN6(dev)) {
674cf967 9154 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 9155 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 9156 } else if (IS_IVYBRIDGE(dev)) {
9157 /* FIXME: detect B0+ stepping and use auto training */
9158 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 9159 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 9160 dev_priv->display.modeset_global_resources =
9161 ivb_modeset_global_resources;
c82e4d26
ED		 9162 } else if (IS_HASWELL(dev)) {
9163 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 9164 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 9165 dev_priv->display.modeset_global_resources =
9166 haswell_modeset_global_resources;
a0e63c22 9167 }
6067aaea 9168 } else if (IS_G4X(dev)) {
e0dac65e 9169 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 9170 }
8c9f3aaf
JB		 9171
9172 /* Default just returns -ENODEV to indicate unsupported */
9173 dev_priv->display.queue_flip = intel_default_queue_flip;
9174
9175 switch (INTEL_INFO(dev)->gen) {
9176 case 2:
9177 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9178 break;
9179
9180 case 3:
9181 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9182 break;
9183
9184 case 4:
9185 case 5:
9186 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9187 break;
9188
9189 case 6:
9190 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9191 break;
7c9017e5
JB		 9192 case 7:
9193 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9194 break;
8c9f3aaf 9195 }
e70236a8
JB		 9196}
9197
b690e96c
JB		 9198/*
9199 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9200 * resume, or other times. This quirk makes sure that's the case for
9201 * affected systems.
9202 */
0206e353 9203static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 9204{
9205 struct drm_i915_private *dev_priv = dev->dev_private;
9206
9207 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 9208 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 9209}
9210
435793df
KP		 9211/*
9212 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9213 */
9214static void quirk_ssc_force_disable(struct drm_device *dev)
9215{
9216 struct drm_i915_private *dev_priv = dev->dev_private;
9217 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 9218 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 9219}
9220
4dca20ef 9221/*
5a15ab5b
CE		 9222 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9223 * brightness value
4dca20ef
CE		 9224 */
9225static void quirk_invert_brightness(struct drm_device *dev)
9226{
9227 struct drm_i915_private *dev_priv = dev->dev_private;
9228 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 9229 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 9230}
9231
b690e96c
JB		 9232struct intel_quirk {
9233 int device;
9234 int subsystem_vendor;
9235 int subsystem_device;
9236 void (*hook)(struct drm_device *dev);
9237};
9238
5f85f176
EE		 9239/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9240struct intel_dmi_quirk {
9241 void (*hook)(struct drm_device *dev);
9242 const struct dmi_system_id (*dmi_id_list)[];
9243};
9244
9245static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9246{
9247 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9248 return 1;
9249}
9250
9251static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9252 {
9253 .dmi_id_list = &(const struct dmi_system_id[]) {
9254 {
9255 .callback = intel_dmi_reverse_brightness,
9256 .ident = "NCR Corporation",
9257 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9258 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9259 },
9260 },
9261 { } /* terminating entry */
9262 },
9263 .hook = quirk_invert_brightness,
9264 },
9265};
9266
c43b5634 9267static struct intel_quirk intel_quirks[] = {
b690e96c 9268 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 9269 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 9270
b690e96c
JB		 9271 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9272 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9273
b690e96c
JB		 9274 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9275 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9276
ccd0d36e 9277 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 9278 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 9279 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 9280
9281 /* Lenovo U160 cannot use SSC on LVDS */
9282 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 9283
9284 /* Sony Vaio Y cannot use SSC on LVDS */
9285 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 9286
9287 /* Acer Aspire 5734Z must invert backlight brightness */
9288 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 9289
9290 /* Acer/eMachines G725 */
9291 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 9292
9293 /* Acer/eMachines e725 */
9294 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 9295
9296 /* Acer/Packard Bell NCL20 */
9297 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 9298
9299 /* Acer Aspire 4736Z */
9300 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 9301};
9302
9303static void intel_init_quirks(struct drm_device *dev)
9304{
9305 struct pci_dev *d = dev->pdev;
9306 int i;
9307
9308 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9309 struct intel_quirk *q = &intel_quirks[i];
9310
9311 if (d->device == q->device &&
9312 (d->subsystem_vendor == q->subsystem_vendor ||
9313 q->subsystem_vendor == PCI_ANY_ID) &&
9314 (d->subsystem_device == q->subsystem_device ||
9315 q->subsystem_device == PCI_ANY_ID))
9316 q->hook(dev);
9317 }
5f85f176
EE		 9318 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9319 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9320 intel_dmi_quirks[i].hook(dev);
9321 }
b690e96c
JB		 9322}
9323
9cce37f4
JB		 9324/* Disable the VGA plane that we never use */
9325static void i915_disable_vga(struct drm_device *dev)
9326{
9327 struct drm_i915_private *dev_priv = dev->dev_private;
9328 u8 sr1;
766aa1c4 9329 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 9330
9331 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 9332 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 9333 sr1 = inb(VGA_SR_DATA);
9334 outb(sr1 | 1<<5, VGA_SR_DATA);
9335 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9336 udelay(300);
9337
9338 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9339 POSTING_READ(vga_reg);
9340}
9341
f817586c
DV		 9342void intel_modeset_init_hw(struct drm_device *dev)
9343{
fa42e23c 9344 intel_init_power_well(dev);
0232e927 9345
a8f78b58
ED		 9346 intel_prepare_ddi(dev);
9347
f817586c
DV		 9348 intel_init_clock_gating(dev);
9349
79f5b2c7 9350 mutex_lock(&dev->struct_mutex);
8090c6b9 9351 intel_enable_gt_powersave(dev);
79f5b2c7 9352 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 9353}
9354
7d708ee4
ID		 9355void intel_modeset_suspend_hw(struct drm_device *dev)
9356{
9357 intel_suspend_hw(dev);
9358}
9359
79e53945
JB		 9360void intel_modeset_init(struct drm_device *dev)
9361{
652c393a 9362 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 9363 int i, j, ret;
79e53945
JB		 9364
9365 drm_mode_config_init(dev);
9366
9367 dev->mode_config.min_width = 0;
9368 dev->mode_config.min_height = 0;
9369
019d96cb
DA		 9370 dev->mode_config.preferred_depth = 24;
9371 dev->mode_config.prefer_shadow = 1;
9372
e6ecefaa 9373 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 9374
b690e96c
JB		 9375 intel_init_quirks(dev);
9376
1fa61106
ED		 9377 intel_init_pm(dev);
9378
e3c74757
BW		 9379 if (INTEL_INFO(dev)->num_pipes == 0)
9380 return;
9381
e70236a8
JB		 9382 intel_init_display(dev);
9383
a6c45cf0
CW		 9384 if (IS_GEN2(dev)) {
9385 dev->mode_config.max_width = 2048;
9386 dev->mode_config.max_height = 2048;
9387 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9388 dev->mode_config.max_width = 4096;
9389 dev->mode_config.max_height = 4096;
79e53945 9390 } else {
a6c45cf0
CW		 9391 dev->mode_config.max_width = 8192;
9392 dev->mode_config.max_height = 8192;
79e53945 9393 }
5d4545ae 9394 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 9395
28c97730 9396 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 9397 INTEL_INFO(dev)->num_pipes,
9398 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 9399
7eb552ae 9400 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 9401 intel_crtc_init(dev, i);
7f1f3851
JB		 9402 for (j = 0; j < dev_priv->num_plane; j++) {
9403 ret = intel_plane_init(dev, i, j);
9404 if (ret)
06da8da2
VS		 9405 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9406 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 9407 }
79e53945
JB		 9408 }
9409
79f689aa 9410 intel_cpu_pll_init(dev);
ee7b9f93
JB		 9411 intel_pch_pll_init(dev);
9412
9cce37f4
JB		 9413 /* Just disable it once at startup */
9414 i915_disable_vga(dev);
79e53945 9415 intel_setup_outputs(dev);
11be49eb
CW		 9416
9417 /* Just in case the BIOS is doing something questionable. */
9418 intel_disable_fbc(dev);
2c7111db
CW		 9419}
9420
24929352
DV		 9421static void
9422intel_connector_break_all_links(struct intel_connector *connector)
9423{
9424 connector->base.dpms = DRM_MODE_DPMS_OFF;
9425 connector->base.encoder = NULL;
9426 connector->encoder->connectors_active = false;
9427 connector->encoder->base.crtc = NULL;
9428}
9429
7fad798e
DV		 9430static void intel_enable_pipe_a(struct drm_device *dev)
9431{
9432 struct intel_connector *connector;
9433 struct drm_connector *crt = NULL;
9434 struct intel_load_detect_pipe load_detect_temp;
9435
9436 /* We can't just switch on the pipe A, we need to set things up with a
9437 * proper mode and output configuration. As a gross hack, enable pipe A
9438 * by enabling the load detect pipe once. */
9439 list_for_each_entry(connector,
9440 &dev->mode_config.connector_list,
9441 base.head) {
9442 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9443 crt = &connector->base;
9444 break;
9445 }
9446 }
9447
9448 if (!crt)
9449 return;
9450
9451 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9452 intel_release_load_detect_pipe(crt, &load_detect_temp);
9453
652c393a 9454
7fad798e
DV		 9455}
9456
fa555837
DV		 9457static bool
9458intel_check_plane_mapping(struct intel_crtc *crtc)
9459{
7eb552ae
BW		 9460 struct drm_device *dev = crtc->base.dev;
9461 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 9462 u32 reg, val;
9463
7eb552ae 9464 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 9465 return true;
9466
9467 reg = DSPCNTR(!crtc->plane);
9468 val = I915_READ(reg);
9469
9470 if ((val & DISPLAY_PLANE_ENABLE) &&
9471 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9472 return false;
9473
9474 return true;
9475}
9476
24929352
DV		 9477static void intel_sanitize_crtc(struct intel_crtc *crtc)
9478{
9479 struct drm_device *dev = crtc->base.dev;
9480 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 9481 u32 reg;
24929352 9482
24929352 9483 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 9484 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 9485 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9486
9487 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 9488 * disable the crtc (and hence change the state) if it is wrong. Note
9489 * that gen4+ has a fixed plane -> pipe mapping. */
9490 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 9491 struct intel_connector *connector;
9492 bool plane;
9493
24929352
DV		 9494 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9495 crtc->base.base.id);
9496
9497 /* Pipe has the wrong plane attached and the plane is active.
9498 * Temporarily change the plane mapping and disable everything
9499 * ... */
9500 plane = crtc->plane;
9501 crtc->plane = !plane;
9502 dev_priv->display.crtc_disable(&crtc->base);
9503 crtc->plane = plane;
9504
9505 /* ... and break all links. */
9506 list_for_each_entry(connector, &dev->mode_config.connector_list,
9507 base.head) {
9508 if (connector->encoder->base.crtc != &crtc->base)
9509 continue;
9510
9511 intel_connector_break_all_links(connector);
9512 }
9513
9514 WARN_ON(crtc->active);
9515 crtc->base.enabled = false;
9516 }
24929352 9517
7fad798e
DV		 9518 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9519 crtc->pipe == PIPE_A && !crtc->active) {
9520 /* BIOS forgot to enable pipe A, this mostly happens after
9521 * resume. Force-enable the pipe to fix this, the update_dpms
9522 * call below we restore the pipe to the right state, but leave
9523 * the required bits on. */
9524 intel_enable_pipe_a(dev);
9525 }
9526
24929352
DV		 9527 /* Adjust the state of the output pipe according to whether we
9528 * have active connectors/encoders. */
9529 intel_crtc_update_dpms(&crtc->base);
9530
9531 if (crtc->active != crtc->base.enabled) {
9532 struct intel_encoder *encoder;
9533
9534 /* This can happen either due to bugs in the get_hw_state
9535 * functions or because the pipe is force-enabled due to the
9536 * pipe A quirk. */
9537 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9538 crtc->base.base.id,
9539 crtc->base.enabled ? "enabled" : "disabled",
9540 crtc->active ? "enabled" : "disabled");
9541
9542 crtc->base.enabled = crtc->active;
9543
9544 /* Because we only establish the connector -> encoder ->
9545 * crtc links if something is active, this means the
9546 * crtc is now deactivated. Break the links. connector
9547 * -> encoder links are only establish when things are
9548 * actually up, hence no need to break them. */
9549 WARN_ON(crtc->active);
9550
9551 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9552 WARN_ON(encoder->connectors_active);
9553 encoder->base.crtc = NULL;
9554 }
9555 }
9556}
9557
9558static void intel_sanitize_encoder(struct intel_encoder *encoder)
9559{
9560 struct intel_connector *connector;
9561 struct drm_device *dev = encoder->base.dev;
9562
9563 /* We need to check both for a crtc link (meaning that the
9564 * encoder is active and trying to read from a pipe) and the
9565 * pipe itself being active. */
9566 bool has_active_crtc = encoder->base.crtc &&
9567 to_intel_crtc(encoder->base.crtc)->active;
9568
9569 if (encoder->connectors_active && !has_active_crtc) {
9570 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9571 encoder->base.base.id,
9572 drm_get_encoder_name(&encoder->base));
9573
9574 /* Connector is active, but has no active pipe. This is
9575 * fallout from our resume register restoring. Disable
9576 * the encoder manually again. */
9577 if (encoder->base.crtc) {
9578 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9579 encoder->base.base.id,
9580 drm_get_encoder_name(&encoder->base));
9581 encoder->disable(encoder);
9582 }
9583
9584 /* Inconsistent output/port/pipe state happens presumably due to
9585 * a bug in one of the get_hw_state functions. Or someplace else
9586 * in our code, like the register restore mess on resume. Clamp
9587 * things to off as a safer default. */
9588 list_for_each_entry(connector,
9589 &dev->mode_config.connector_list,
9590 base.head) {
9591 if (connector->encoder != encoder)
9592 continue;
9593
9594 intel_connector_break_all_links(connector);
9595 }
9596 }
9597 /* Enabled encoders without active connectors will be fixed in
9598 * the crtc fixup. */
9599}
9600
44cec740 9601void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9602{
9603 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9604 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9605
9606 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9607 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9608 i915_disable_vga(dev);
0fde901f
KM		 9609 }
9610}
9611
24929352
DV		 9612/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9613 * and i915 state tracking structures. */
45e2b5f6
DV		 9614void intel_modeset_setup_hw_state(struct drm_device *dev,
9615 bool force_restore)
24929352
DV		 9616{
9617 struct drm_i915_private *dev_priv = dev->dev_private;
9618 enum pipe pipe;
b5644d05 9619 struct drm_plane *plane;
24929352
DV		 9620 struct intel_crtc *crtc;
9621 struct intel_encoder *encoder;
9622 struct intel_connector *connector;
9623
0e8ffe1b
DV		 9624 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9625 base.head) {
88adfff1 9626 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 9627
0e8ffe1b
DV		 9628 crtc->active = dev_priv->display.get_pipe_config(crtc,
9629 &crtc->config);
24929352
DV		 9630
9631 crtc->base.enabled = crtc->active;
9632
9633 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9634 crtc->base.base.id,
9635 crtc->active ? "enabled" : "disabled");
9636 }
9637
affa9354 9638 if (HAS_DDI(dev))
6441ab5f
PZ		 9639 intel_ddi_setup_hw_pll_state(dev);
9640
24929352
DV		 9641 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9642 base.head) {
9643 pipe = 0;
9644
9645 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 9646 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9647 encoder->base.crtc = &crtc->base;
9648 if (encoder->get_config)
9649 encoder->get_config(encoder, &crtc->config);
24929352
DV		 9650 } else {
9651 encoder->base.crtc = NULL;
9652 }
9653
9654 encoder->connectors_active = false;
9655 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9656 encoder->base.base.id,
9657 drm_get_encoder_name(&encoder->base),
9658 encoder->base.crtc ? "enabled" : "disabled",
9659 pipe);
9660 }
9661
9662 list_for_each_entry(connector, &dev->mode_config.connector_list,
9663 base.head) {
9664 if (connector->get_hw_state(connector)) {
9665 connector->base.dpms = DRM_MODE_DPMS_ON;
9666 connector->encoder->connectors_active = true;
9667 connector->base.encoder = &connector->encoder->base;
9668 } else {
9669 connector->base.dpms = DRM_MODE_DPMS_OFF;
9670 connector->base.encoder = NULL;
9671 }
9672 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9673 connector->base.base.id,
9674 drm_get_connector_name(&connector->base),
9675 connector->base.encoder ? "enabled" : "disabled");
9676 }
9677
9678 /* HW state is read out, now we need to sanitize this mess. */
9679 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9680 base.head) {
9681 intel_sanitize_encoder(encoder);
9682 }
9683
9684 for_each_pipe(pipe) {
9685 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9686 intel_sanitize_crtc(crtc);
c0b03411 9687 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 9688 }
9a935856 9689
45e2b5f6 9690 if (force_restore) {
f30da187
DV		 9691 /*
9692 * We need to use raw interfaces for restoring state to avoid
9693 * checking (bogus) intermediate states.
9694 */
45e2b5f6 9695 for_each_pipe(pipe) {
b5644d05
JB		 9696 struct drm_crtc *crtc =
9697 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 9698
9699 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9700 crtc->fb);
45e2b5f6 9701 }
b5644d05
JB		 9702 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9703 intel_plane_restore(plane);
0fde901f
KM		 9704
9705 i915_redisable_vga(dev);
45e2b5f6
DV		 9706 } else {
9707 intel_modeset_update_staged_output_state(dev);
9708 }
8af6cf88
DV		 9709
9710 intel_modeset_check_state(dev);
2e938892
DV		 9711
9712 drm_mode_config_reset(dev);
2c7111db
CW		 9713}
9714
9715void intel_modeset_gem_init(struct drm_device *dev)
9716{
1833b134 9717 intel_modeset_init_hw(dev);
02e792fb
DV		 9718
9719 intel_setup_overlay(dev);
24929352 9720
45e2b5f6 9721 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9722}
9723
9724void intel_modeset_cleanup(struct drm_device *dev)
9725{
652c393a
JB		 9726 struct drm_i915_private *dev_priv = dev->dev_private;
9727 struct drm_crtc *crtc;
9728 struct intel_crtc *intel_crtc;
9729
fd0c0642
DV		 9730 /*
9731 * Interrupts and polling as the first thing to avoid creating havoc.
9732 * Too much stuff here (turning of rps, connectors, ...) would
9733 * experience fancy races otherwise.
9734 */
9735 drm_irq_uninstall(dev);
9736 cancel_work_sync(&dev_priv->hotplug_work);
9737 /*
9738 * Due to the hpd irq storm handling the hotplug work can re-arm the
9739 * poll handlers. Hence disable polling after hpd handling is shut down.
9740 */
f87ea761 9741 drm_kms_helper_poll_fini(dev);
fd0c0642 9742
652c393a
JB		 9743 mutex_lock(&dev->struct_mutex);
9744
723bfd70
JB		 9745 intel_unregister_dsm_handler();
9746
652c393a
JB		 9747 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9748 /* Skip inactive CRTCs */
9749 if (!crtc->fb)
9750 continue;
9751
9752 intel_crtc = to_intel_crtc(crtc);
3dec0095 9753 intel_increase_pllclock(crtc);
652c393a
JB		 9754 }
9755
973d04f9 9756 intel_disable_fbc(dev);
e70236a8 9757
8090c6b9 9758 intel_disable_gt_powersave(dev);
0cdab21f 9759
930ebb46
DV		 9760 ironlake_teardown_rc6(dev);
9761
69341a5e
KH		 9762 mutex_unlock(&dev->struct_mutex);
9763
1630fe75
CW		 9764 /* flush any delayed tasks or pending work */
9765 flush_scheduled_work();
9766
dc652f90
JN		 9767 /* destroy backlight, if any, before the connectors */
9768 intel_panel_destroy_backlight(dev);
9769
79e53945 9770 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9771
9772 intel_cleanup_overlay(dev);
79e53945
JB		 9773}
9774
f1c79df3
ZW		 9775/*
9776 * Return which encoder is currently attached for connector.
9777 */
df0e9248 9778struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9779{
df0e9248
CW		 9780 return &intel_attached_encoder(connector)->base;
9781}
f1c79df3 9782
df0e9248
CW		 9783void intel_connector_attach_encoder(struct intel_connector *connector,
9784 struct intel_encoder *encoder)
9785{
9786 connector->encoder = encoder;
9787 drm_mode_connector_attach_encoder(&connector->base,
9788 &encoder->base);
79e53945 9789}
28d52043
DA		 9790
9791/*
9792 * set vga decode state - true == enable VGA decode
9793 */
9794int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9795{
9796 struct drm_i915_private *dev_priv = dev->dev_private;
9797 u16 gmch_ctrl;
9798
9799 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9800 if (state)
9801 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9802 else
9803 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9804 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9805 return 0;
9806}
c4a1d9e4
CW		 9807
9808#ifdef CONFIG_DEBUG_FS
9809#include <linux/seq_file.h>
9810
9811struct intel_display_error_state {
ff57f1b0
PZ		 9812
9813 u32 power_well_driver;
9814
c4a1d9e4
CW		 9815 struct intel_cursor_error_state {
9816 u32 control;
9817 u32 position;
9818 u32 base;
9819 u32 size;
52331309 9820 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9821
9822 struct intel_pipe_error_state {
ff57f1b0 9823 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9824 u32 conf;
9825 u32 source;
9826
9827 u32 htotal;
9828 u32 hblank;
9829 u32 hsync;
9830 u32 vtotal;
9831 u32 vblank;
9832 u32 vsync;
52331309 9833 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9834
9835 struct intel_plane_error_state {
9836 u32 control;
9837 u32 stride;
9838 u32 size;
9839 u32 pos;
9840 u32 addr;
9841 u32 surface;
9842 u32 tile_offset;
52331309 9843 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9844};
9845
9846struct intel_display_error_state *
9847intel_display_capture_error_state(struct drm_device *dev)
9848{
0206e353 9849 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9850 struct intel_display_error_state *error;
702e7a56 9851 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9852 int i;
9853
9854 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9855 if (error == NULL)
9856 return NULL;
9857
ff57f1b0
PZ		 9858 if (HAS_POWER_WELL(dev))
9859 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
9860
52331309 9861 for_each_pipe(i) {
702e7a56 9862 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
ff57f1b0 9863 error->pipe[i].cpu_transcoder = cpu_transcoder;
702e7a56 9864
a18c4c3d
PZ		 9865 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9866 error->cursor[i].control = I915_READ(CURCNTR(i));
9867 error->cursor[i].position = I915_READ(CURPOS(i));
9868 error->cursor[i].base = I915_READ(CURBASE(i));
9869 } else {
9870 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9871 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9872 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9873 }
c4a1d9e4
CW		 9874
9875 error->plane[i].control = I915_READ(DSPCNTR(i));
9876 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 9877 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9878 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 9879 error->plane[i].pos = I915_READ(DSPPOS(i));
9880 }
ca291363
PZ		 9881 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9882 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 9883 if (INTEL_INFO(dev)->gen >= 4) {
9884 error->plane[i].surface = I915_READ(DSPSURF(i));
9885 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9886 }
9887
702e7a56 9888 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9889 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9890 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9891 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9892 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9893 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9894 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9895 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9896 }
9897
12d217c7
PZ		 9898 /* In the code above we read the registers without checking if the power
9899 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
9900 * prevent the next I915_WRITE from detecting it and printing an error
9901 * message. */
9902 if (HAS_POWER_WELL(dev))
9903 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
9904
c4a1d9e4
CW		 9905 return error;
9906}
9907
edc3d884
MK		 9908#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
9909
c4a1d9e4 9910void
edc3d884 9911intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 9912 struct drm_device *dev,
9913 struct intel_display_error_state *error)
9914{
9915 int i;
9916
edc3d884 9917 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 9918 if (HAS_POWER_WELL(dev))
edc3d884 9919 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 9920 error->power_well_driver);
52331309 9921 for_each_pipe(i) {
edc3d884
MK		 9922 err_printf(m, "Pipe [%d]:\n", i);
9923 err_printf(m, " CPU transcoder: %c\n",
ff57f1b0 9924 transcoder_name(error->pipe[i].cpu_transcoder));
edc3d884
MK		 9925 err_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9926 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
9927 err_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9928 err_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9929 err_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9930 err_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9931 err_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9932 err_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9933
9934 err_printf(m, "Plane [%d]:\n", i);
9935 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
9936 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 9937 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 9938 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
9939 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 9940 }
4b71a570 9941 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 9942 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 9943 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 9944 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
9945 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 9946 }
9947
edc3d884
MK		 9948 err_printf(m, "Cursor [%d]:\n", i);
9949 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9950 err_printf(m, " POS: %08x\n", error->cursor[i].position);
9951 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4
CW		 9952 }
9953}
9954#endif
Linux kernel - Deliverables
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