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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
760285e7 DH |
40 | #include <drm/drm_dp_helper.h> |
41 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
42 | #include <drm/drm_plane_helper.h> |
43 | #include <drm/drm_rect.h> | |
c0f372b3 | 44 | #include <linux/dma_remapping.h> |
79e53945 | 45 | |
465c120c MR |
46 | /* Primary plane formats supported by all gen */ |
47 | #define COMMON_PRIMARY_FORMATS \ | |
48 | DRM_FORMAT_C8, \ | |
49 | DRM_FORMAT_RGB565, \ | |
50 | DRM_FORMAT_XRGB8888, \ | |
51 | DRM_FORMAT_ARGB8888 | |
52 | ||
53 | /* Primary plane formats for gen <= 3 */ | |
54 | static const uint32_t intel_primary_formats_gen2[] = { | |
55 | COMMON_PRIMARY_FORMATS, | |
56 | DRM_FORMAT_XRGB1555, | |
57 | DRM_FORMAT_ARGB1555, | |
58 | }; | |
59 | ||
60 | /* Primary plane formats for gen >= 4 */ | |
61 | static const uint32_t intel_primary_formats_gen4[] = { | |
62 | COMMON_PRIMARY_FORMATS, \ | |
63 | DRM_FORMAT_XBGR8888, | |
64 | DRM_FORMAT_ABGR8888, | |
65 | DRM_FORMAT_XRGB2101010, | |
66 | DRM_FORMAT_ARGB2101010, | |
67 | DRM_FORMAT_XBGR2101010, | |
68 | DRM_FORMAT_ABGR2101010, | |
69 | }; | |
70 | ||
3d7d6510 MR |
71 | /* Cursor formats */ |
72 | static const uint32_t intel_cursor_formats[] = { | |
73 | DRM_FORMAT_ARGB8888, | |
74 | }; | |
75 | ||
ef9348c8 | 76 | #define DIV_ROUND_CLOSEST_ULL(ll, d) \ |
465c120c | 77 | ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; }) |
ef9348c8 | 78 | |
cc36513c DV |
79 | static void intel_increase_pllclock(struct drm_device *dev, |
80 | enum pipe pipe); | |
6b383a7f | 81 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 82 | |
f1f644dc JB |
83 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
84 | struct intel_crtc_config *pipe_config); | |
18442d08 VS |
85 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
86 | struct intel_crtc_config *pipe_config); | |
f1f644dc | 87 | |
e7457a9a DL |
88 | static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
89 | int x, int y, struct drm_framebuffer *old_fb); | |
eb1bfe80 JB |
90 | static int intel_framebuffer_init(struct drm_device *dev, |
91 | struct intel_framebuffer *ifb, | |
92 | struct drm_mode_fb_cmd2 *mode_cmd, | |
93 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
94 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
95 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
29407aab | 96 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
97 | struct intel_link_m_n *m_n, |
98 | struct intel_link_m_n *m2_n2); | |
29407aab | 99 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 DV |
100 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
101 | static void intel_set_pipe_csc(struct drm_crtc *crtc); | |
bdd4b6a6 | 102 | static void vlv_prepare_pll(struct intel_crtc *crtc); |
1ae0d137 | 103 | static void chv_prepare_pll(struct intel_crtc *crtc); |
e7457a9a | 104 | |
0e32b39c DA |
105 | static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe) |
106 | { | |
107 | if (!connector->mst_port) | |
108 | return connector->encoder; | |
109 | else | |
110 | return &connector->mst_port->mst_encoders[pipe]->base; | |
111 | } | |
112 | ||
79e53945 | 113 | typedef struct { |
0206e353 | 114 | int min, max; |
79e53945 JB |
115 | } intel_range_t; |
116 | ||
117 | typedef struct { | |
0206e353 AJ |
118 | int dot_limit; |
119 | int p2_slow, p2_fast; | |
79e53945 JB |
120 | } intel_p2_t; |
121 | ||
d4906093 ML |
122 | typedef struct intel_limit intel_limit_t; |
123 | struct intel_limit { | |
0206e353 AJ |
124 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
125 | intel_p2_t p2; | |
d4906093 | 126 | }; |
79e53945 | 127 | |
d2acd215 DV |
128 | int |
129 | intel_pch_rawclk(struct drm_device *dev) | |
130 | { | |
131 | struct drm_i915_private *dev_priv = dev->dev_private; | |
132 | ||
133 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
134 | ||
135 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
136 | } | |
137 | ||
021357ac CW |
138 | static inline u32 /* units of 100MHz */ |
139 | intel_fdi_link_freq(struct drm_device *dev) | |
140 | { | |
8b99e68c CW |
141 | if (IS_GEN5(dev)) { |
142 | struct drm_i915_private *dev_priv = dev->dev_private; | |
143 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
144 | } else | |
145 | return 27; | |
021357ac CW |
146 | } |
147 | ||
5d536e28 | 148 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 149 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 150 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 151 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
152 | .m = { .min = 96, .max = 140 }, |
153 | .m1 = { .min = 18, .max = 26 }, | |
154 | .m2 = { .min = 6, .max = 16 }, | |
155 | .p = { .min = 4, .max = 128 }, | |
156 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
157 | .p2 = { .dot_limit = 165000, |
158 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
159 | }; |
160 | ||
5d536e28 DV |
161 | static const intel_limit_t intel_limits_i8xx_dvo = { |
162 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 163 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 164 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
165 | .m = { .min = 96, .max = 140 }, |
166 | .m1 = { .min = 18, .max = 26 }, | |
167 | .m2 = { .min = 6, .max = 16 }, | |
168 | .p = { .min = 4, .max = 128 }, | |
169 | .p1 = { .min = 2, .max = 33 }, | |
170 | .p2 = { .dot_limit = 165000, | |
171 | .p2_slow = 4, .p2_fast = 4 }, | |
172 | }; | |
173 | ||
e4b36699 | 174 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 175 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 176 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 177 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
178 | .m = { .min = 96, .max = 140 }, |
179 | .m1 = { .min = 18, .max = 26 }, | |
180 | .m2 = { .min = 6, .max = 16 }, | |
181 | .p = { .min = 4, .max = 128 }, | |
182 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
183 | .p2 = { .dot_limit = 165000, |
184 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 185 | }; |
273e27ca | 186 | |
e4b36699 | 187 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
188 | .dot = { .min = 20000, .max = 400000 }, |
189 | .vco = { .min = 1400000, .max = 2800000 }, | |
190 | .n = { .min = 1, .max = 6 }, | |
191 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
192 | .m1 = { .min = 8, .max = 18 }, |
193 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
194 | .p = { .min = 5, .max = 80 }, |
195 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
196 | .p2 = { .dot_limit = 200000, |
197 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
198 | }; |
199 | ||
200 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
201 | .dot = { .min = 20000, .max = 400000 }, |
202 | .vco = { .min = 1400000, .max = 2800000 }, | |
203 | .n = { .min = 1, .max = 6 }, | |
204 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
205 | .m1 = { .min = 8, .max = 18 }, |
206 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
207 | .p = { .min = 7, .max = 98 }, |
208 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
209 | .p2 = { .dot_limit = 112000, |
210 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
211 | }; |
212 | ||
273e27ca | 213 | |
e4b36699 | 214 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
215 | .dot = { .min = 25000, .max = 270000 }, |
216 | .vco = { .min = 1750000, .max = 3500000}, | |
217 | .n = { .min = 1, .max = 4 }, | |
218 | .m = { .min = 104, .max = 138 }, | |
219 | .m1 = { .min = 17, .max = 23 }, | |
220 | .m2 = { .min = 5, .max = 11 }, | |
221 | .p = { .min = 10, .max = 30 }, | |
222 | .p1 = { .min = 1, .max = 3}, | |
223 | .p2 = { .dot_limit = 270000, | |
224 | .p2_slow = 10, | |
225 | .p2_fast = 10 | |
044c7c41 | 226 | }, |
e4b36699 KP |
227 | }; |
228 | ||
229 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
230 | .dot = { .min = 22000, .max = 400000 }, |
231 | .vco = { .min = 1750000, .max = 3500000}, | |
232 | .n = { .min = 1, .max = 4 }, | |
233 | .m = { .min = 104, .max = 138 }, | |
234 | .m1 = { .min = 16, .max = 23 }, | |
235 | .m2 = { .min = 5, .max = 11 }, | |
236 | .p = { .min = 5, .max = 80 }, | |
237 | .p1 = { .min = 1, .max = 8}, | |
238 | .p2 = { .dot_limit = 165000, | |
239 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
240 | }; |
241 | ||
242 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
243 | .dot = { .min = 20000, .max = 115000 }, |
244 | .vco = { .min = 1750000, .max = 3500000 }, | |
245 | .n = { .min = 1, .max = 3 }, | |
246 | .m = { .min = 104, .max = 138 }, | |
247 | .m1 = { .min = 17, .max = 23 }, | |
248 | .m2 = { .min = 5, .max = 11 }, | |
249 | .p = { .min = 28, .max = 112 }, | |
250 | .p1 = { .min = 2, .max = 8 }, | |
251 | .p2 = { .dot_limit = 0, | |
252 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 253 | }, |
e4b36699 KP |
254 | }; |
255 | ||
256 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
257 | .dot = { .min = 80000, .max = 224000 }, |
258 | .vco = { .min = 1750000, .max = 3500000 }, | |
259 | .n = { .min = 1, .max = 3 }, | |
260 | .m = { .min = 104, .max = 138 }, | |
261 | .m1 = { .min = 17, .max = 23 }, | |
262 | .m2 = { .min = 5, .max = 11 }, | |
263 | .p = { .min = 14, .max = 42 }, | |
264 | .p1 = { .min = 2, .max = 6 }, | |
265 | .p2 = { .dot_limit = 0, | |
266 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 267 | }, |
e4b36699 KP |
268 | }; |
269 | ||
f2b115e6 | 270 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
271 | .dot = { .min = 20000, .max = 400000}, |
272 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 273 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
274 | .n = { .min = 3, .max = 6 }, |
275 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 276 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
277 | .m1 = { .min = 0, .max = 0 }, |
278 | .m2 = { .min = 0, .max = 254 }, | |
279 | .p = { .min = 5, .max = 80 }, | |
280 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
281 | .p2 = { .dot_limit = 200000, |
282 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
283 | }; |
284 | ||
f2b115e6 | 285 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
286 | .dot = { .min = 20000, .max = 400000 }, |
287 | .vco = { .min = 1700000, .max = 3500000 }, | |
288 | .n = { .min = 3, .max = 6 }, | |
289 | .m = { .min = 2, .max = 256 }, | |
290 | .m1 = { .min = 0, .max = 0 }, | |
291 | .m2 = { .min = 0, .max = 254 }, | |
292 | .p = { .min = 7, .max = 112 }, | |
293 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
294 | .p2 = { .dot_limit = 112000, |
295 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
296 | }; |
297 | ||
273e27ca EA |
298 | /* Ironlake / Sandybridge |
299 | * | |
300 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
301 | * the range value for them is (actual_value - 2). | |
302 | */ | |
b91ad0ec | 303 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
304 | .dot = { .min = 25000, .max = 350000 }, |
305 | .vco = { .min = 1760000, .max = 3510000 }, | |
306 | .n = { .min = 1, .max = 5 }, | |
307 | .m = { .min = 79, .max = 127 }, | |
308 | .m1 = { .min = 12, .max = 22 }, | |
309 | .m2 = { .min = 5, .max = 9 }, | |
310 | .p = { .min = 5, .max = 80 }, | |
311 | .p1 = { .min = 1, .max = 8 }, | |
312 | .p2 = { .dot_limit = 225000, | |
313 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
314 | }; |
315 | ||
b91ad0ec | 316 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
317 | .dot = { .min = 25000, .max = 350000 }, |
318 | .vco = { .min = 1760000, .max = 3510000 }, | |
319 | .n = { .min = 1, .max = 3 }, | |
320 | .m = { .min = 79, .max = 118 }, | |
321 | .m1 = { .min = 12, .max = 22 }, | |
322 | .m2 = { .min = 5, .max = 9 }, | |
323 | .p = { .min = 28, .max = 112 }, | |
324 | .p1 = { .min = 2, .max = 8 }, | |
325 | .p2 = { .dot_limit = 225000, | |
326 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
327 | }; |
328 | ||
329 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
330 | .dot = { .min = 25000, .max = 350000 }, |
331 | .vco = { .min = 1760000, .max = 3510000 }, | |
332 | .n = { .min = 1, .max = 3 }, | |
333 | .m = { .min = 79, .max = 127 }, | |
334 | .m1 = { .min = 12, .max = 22 }, | |
335 | .m2 = { .min = 5, .max = 9 }, | |
336 | .p = { .min = 14, .max = 56 }, | |
337 | .p1 = { .min = 2, .max = 8 }, | |
338 | .p2 = { .dot_limit = 225000, | |
339 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
340 | }; |
341 | ||
273e27ca | 342 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 343 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
344 | .dot = { .min = 25000, .max = 350000 }, |
345 | .vco = { .min = 1760000, .max = 3510000 }, | |
346 | .n = { .min = 1, .max = 2 }, | |
347 | .m = { .min = 79, .max = 126 }, | |
348 | .m1 = { .min = 12, .max = 22 }, | |
349 | .m2 = { .min = 5, .max = 9 }, | |
350 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 351 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
352 | .p2 = { .dot_limit = 225000, |
353 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
354 | }; |
355 | ||
356 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
357 | .dot = { .min = 25000, .max = 350000 }, |
358 | .vco = { .min = 1760000, .max = 3510000 }, | |
359 | .n = { .min = 1, .max = 3 }, | |
360 | .m = { .min = 79, .max = 126 }, | |
361 | .m1 = { .min = 12, .max = 22 }, | |
362 | .m2 = { .min = 5, .max = 9 }, | |
363 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 364 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
365 | .p2 = { .dot_limit = 225000, |
366 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
367 | }; |
368 | ||
dc730512 | 369 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
370 | /* |
371 | * These are the data rate limits (measured in fast clocks) | |
372 | * since those are the strictest limits we have. The fast | |
373 | * clock and actual rate limits are more relaxed, so checking | |
374 | * them would make no difference. | |
375 | */ | |
376 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 377 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 378 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
379 | .m1 = { .min = 2, .max = 3 }, |
380 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 381 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 382 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
383 | }; |
384 | ||
ef9348c8 CML |
385 | static const intel_limit_t intel_limits_chv = { |
386 | /* | |
387 | * These are the data rate limits (measured in fast clocks) | |
388 | * since those are the strictest limits we have. The fast | |
389 | * clock and actual rate limits are more relaxed, so checking | |
390 | * them would make no difference. | |
391 | */ | |
392 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
393 | .vco = { .min = 4860000, .max = 6700000 }, | |
394 | .n = { .min = 1, .max = 1 }, | |
395 | .m1 = { .min = 2, .max = 2 }, | |
396 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
397 | .p1 = { .min = 2, .max = 4 }, | |
398 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
399 | }; | |
400 | ||
6b4bf1c4 VS |
401 | static void vlv_clock(int refclk, intel_clock_t *clock) |
402 | { | |
403 | clock->m = clock->m1 * clock->m2; | |
404 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
405 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
406 | return; | |
fb03ac01 VS |
407 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
408 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
6b4bf1c4 VS |
409 | } |
410 | ||
e0638cdf PZ |
411 | /** |
412 | * Returns whether any output on the specified pipe is of the specified type | |
413 | */ | |
414 | static bool intel_pipe_has_type(struct drm_crtc *crtc, int type) | |
415 | { | |
416 | struct drm_device *dev = crtc->dev; | |
417 | struct intel_encoder *encoder; | |
418 | ||
419 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
420 | if (encoder->type == type) | |
421 | return true; | |
422 | ||
423 | return false; | |
424 | } | |
425 | ||
1b894b59 CW |
426 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
427 | int refclk) | |
2c07245f | 428 | { |
b91ad0ec | 429 | struct drm_device *dev = crtc->dev; |
2c07245f | 430 | const intel_limit_t *limit; |
b91ad0ec ZW |
431 | |
432 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 433 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 434 | if (refclk == 100000) |
b91ad0ec ZW |
435 | limit = &intel_limits_ironlake_dual_lvds_100m; |
436 | else | |
437 | limit = &intel_limits_ironlake_dual_lvds; | |
438 | } else { | |
1b894b59 | 439 | if (refclk == 100000) |
b91ad0ec ZW |
440 | limit = &intel_limits_ironlake_single_lvds_100m; |
441 | else | |
442 | limit = &intel_limits_ironlake_single_lvds; | |
443 | } | |
c6bb3538 | 444 | } else |
b91ad0ec | 445 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
446 | |
447 | return limit; | |
448 | } | |
449 | ||
044c7c41 ML |
450 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
451 | { | |
452 | struct drm_device *dev = crtc->dev; | |
044c7c41 ML |
453 | const intel_limit_t *limit; |
454 | ||
455 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 456 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 457 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 458 | else |
e4b36699 | 459 | limit = &intel_limits_g4x_single_channel_lvds; |
044c7c41 ML |
460 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
461 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 462 | limit = &intel_limits_g4x_hdmi; |
044c7c41 | 463 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 464 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 465 | } else /* The option is for other outputs */ |
e4b36699 | 466 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
467 | |
468 | return limit; | |
469 | } | |
470 | ||
1b894b59 | 471 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
79e53945 JB |
472 | { |
473 | struct drm_device *dev = crtc->dev; | |
474 | const intel_limit_t *limit; | |
475 | ||
bad720ff | 476 | if (HAS_PCH_SPLIT(dev)) |
1b894b59 | 477 | limit = intel_ironlake_limit(crtc, refclk); |
2c07245f | 478 | else if (IS_G4X(dev)) { |
044c7c41 | 479 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 480 | } else if (IS_PINEVIEW(dev)) { |
2177832f | 481 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 482 | limit = &intel_limits_pineview_lvds; |
2177832f | 483 | else |
f2b115e6 | 484 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
485 | } else if (IS_CHERRYVIEW(dev)) { |
486 | limit = &intel_limits_chv; | |
a0c4da24 | 487 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 488 | limit = &intel_limits_vlv; |
a6c45cf0 CW |
489 | } else if (!IS_GEN2(dev)) { |
490 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
491 | limit = &intel_limits_i9xx_lvds; | |
492 | else | |
493 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 JB |
494 | } else { |
495 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 496 | limit = &intel_limits_i8xx_lvds; |
5d536e28 | 497 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO)) |
e4b36699 | 498 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
499 | else |
500 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
501 | } |
502 | return limit; | |
503 | } | |
504 | ||
f2b115e6 AJ |
505 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
506 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 507 | { |
2177832f SL |
508 | clock->m = clock->m2 + 2; |
509 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
510 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
511 | return; | |
fb03ac01 VS |
512 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
513 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
2177832f SL |
514 | } |
515 | ||
7429e9d4 DV |
516 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
517 | { | |
518 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
519 | } | |
520 | ||
ac58c3f0 | 521 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
2177832f | 522 | { |
7429e9d4 | 523 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 524 | clock->p = clock->p1 * clock->p2; |
ed5ca77e VS |
525 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
526 | return; | |
fb03ac01 VS |
527 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
528 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
79e53945 JB |
529 | } |
530 | ||
ef9348c8 CML |
531 | static void chv_clock(int refclk, intel_clock_t *clock) |
532 | { | |
533 | clock->m = clock->m1 * clock->m2; | |
534 | clock->p = clock->p1 * clock->p2; | |
535 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
536 | return; | |
537 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, | |
538 | clock->n << 22); | |
539 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
540 | } | |
541 | ||
7c04d1d9 | 542 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
543 | /** |
544 | * Returns whether the given set of divisors are valid for a given refclk with | |
545 | * the given connectors. | |
546 | */ | |
547 | ||
1b894b59 CW |
548 | static bool intel_PLL_is_valid(struct drm_device *dev, |
549 | const intel_limit_t *limit, | |
550 | const intel_clock_t *clock) | |
79e53945 | 551 | { |
f01b7962 VS |
552 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
553 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 554 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 555 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 556 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 557 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 558 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 559 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 VS |
560 | |
561 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev)) | |
562 | if (clock->m1 <= clock->m2) | |
563 | INTELPllInvalid("m1 <= m2\n"); | |
564 | ||
565 | if (!IS_VALLEYVIEW(dev)) { | |
566 | if (clock->p < limit->p.min || limit->p.max < clock->p) | |
567 | INTELPllInvalid("p out of range\n"); | |
568 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
569 | INTELPllInvalid("m out of range\n"); | |
570 | } | |
571 | ||
79e53945 | 572 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 573 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
574 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
575 | * connector, etc., rather than just a single range. | |
576 | */ | |
577 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 578 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
579 | |
580 | return true; | |
581 | } | |
582 | ||
d4906093 | 583 | static bool |
ee9300bb | 584 | i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
cec2f356 SP |
585 | int target, int refclk, intel_clock_t *match_clock, |
586 | intel_clock_t *best_clock) | |
79e53945 JB |
587 | { |
588 | struct drm_device *dev = crtc->dev; | |
79e53945 | 589 | intel_clock_t clock; |
79e53945 JB |
590 | int err = target; |
591 | ||
a210b028 | 592 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 593 | /* |
a210b028 DV |
594 | * For LVDS just rely on its current settings for dual-channel. |
595 | * We haven't figured out how to reliably set up different | |
596 | * single/dual channel state, if we even can. | |
79e53945 | 597 | */ |
1974cad0 | 598 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
599 | clock.p2 = limit->p2.p2_fast; |
600 | else | |
601 | clock.p2 = limit->p2.p2_slow; | |
602 | } else { | |
603 | if (target < limit->p2.dot_limit) | |
604 | clock.p2 = limit->p2.p2_slow; | |
605 | else | |
606 | clock.p2 = limit->p2.p2_fast; | |
607 | } | |
608 | ||
0206e353 | 609 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 610 | |
42158660 ZY |
611 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
612 | clock.m1++) { | |
613 | for (clock.m2 = limit->m2.min; | |
614 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 615 | if (clock.m2 >= clock.m1) |
42158660 ZY |
616 | break; |
617 | for (clock.n = limit->n.min; | |
618 | clock.n <= limit->n.max; clock.n++) { | |
619 | for (clock.p1 = limit->p1.min; | |
620 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
621 | int this_err; |
622 | ||
ac58c3f0 DV |
623 | i9xx_clock(refclk, &clock); |
624 | if (!intel_PLL_is_valid(dev, limit, | |
625 | &clock)) | |
626 | continue; | |
627 | if (match_clock && | |
628 | clock.p != match_clock->p) | |
629 | continue; | |
630 | ||
631 | this_err = abs(clock.dot - target); | |
632 | if (this_err < err) { | |
633 | *best_clock = clock; | |
634 | err = this_err; | |
635 | } | |
636 | } | |
637 | } | |
638 | } | |
639 | } | |
640 | ||
641 | return (err != target); | |
642 | } | |
643 | ||
644 | static bool | |
ee9300bb DV |
645 | pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
646 | int target, int refclk, intel_clock_t *match_clock, | |
647 | intel_clock_t *best_clock) | |
79e53945 JB |
648 | { |
649 | struct drm_device *dev = crtc->dev; | |
79e53945 | 650 | intel_clock_t clock; |
79e53945 JB |
651 | int err = target; |
652 | ||
a210b028 | 653 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 654 | /* |
a210b028 DV |
655 | * For LVDS just rely on its current settings for dual-channel. |
656 | * We haven't figured out how to reliably set up different | |
657 | * single/dual channel state, if we even can. | |
79e53945 | 658 | */ |
1974cad0 | 659 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
660 | clock.p2 = limit->p2.p2_fast; |
661 | else | |
662 | clock.p2 = limit->p2.p2_slow; | |
663 | } else { | |
664 | if (target < limit->p2.dot_limit) | |
665 | clock.p2 = limit->p2.p2_slow; | |
666 | else | |
667 | clock.p2 = limit->p2.p2_fast; | |
668 | } | |
669 | ||
0206e353 | 670 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 671 | |
42158660 ZY |
672 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
673 | clock.m1++) { | |
674 | for (clock.m2 = limit->m2.min; | |
675 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
676 | for (clock.n = limit->n.min; |
677 | clock.n <= limit->n.max; clock.n++) { | |
678 | for (clock.p1 = limit->p1.min; | |
679 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
680 | int this_err; |
681 | ||
ac58c3f0 | 682 | pineview_clock(refclk, &clock); |
1b894b59 CW |
683 | if (!intel_PLL_is_valid(dev, limit, |
684 | &clock)) | |
79e53945 | 685 | continue; |
cec2f356 SP |
686 | if (match_clock && |
687 | clock.p != match_clock->p) | |
688 | continue; | |
79e53945 JB |
689 | |
690 | this_err = abs(clock.dot - target); | |
691 | if (this_err < err) { | |
692 | *best_clock = clock; | |
693 | err = this_err; | |
694 | } | |
695 | } | |
696 | } | |
697 | } | |
698 | } | |
699 | ||
700 | return (err != target); | |
701 | } | |
702 | ||
d4906093 | 703 | static bool |
ee9300bb DV |
704 | g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
705 | int target, int refclk, intel_clock_t *match_clock, | |
706 | intel_clock_t *best_clock) | |
d4906093 ML |
707 | { |
708 | struct drm_device *dev = crtc->dev; | |
d4906093 ML |
709 | intel_clock_t clock; |
710 | int max_n; | |
711 | bool found; | |
6ba770dc AJ |
712 | /* approximately equals target * 0.00585 */ |
713 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
714 | found = false; |
715 | ||
716 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 717 | if (intel_is_dual_link_lvds(dev)) |
d4906093 ML |
718 | clock.p2 = limit->p2.p2_fast; |
719 | else | |
720 | clock.p2 = limit->p2.p2_slow; | |
721 | } else { | |
722 | if (target < limit->p2.dot_limit) | |
723 | clock.p2 = limit->p2.p2_slow; | |
724 | else | |
725 | clock.p2 = limit->p2.p2_fast; | |
726 | } | |
727 | ||
728 | memset(best_clock, 0, sizeof(*best_clock)); | |
729 | max_n = limit->n.max; | |
f77f13e2 | 730 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 731 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 732 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
733 | for (clock.m1 = limit->m1.max; |
734 | clock.m1 >= limit->m1.min; clock.m1--) { | |
735 | for (clock.m2 = limit->m2.max; | |
736 | clock.m2 >= limit->m2.min; clock.m2--) { | |
737 | for (clock.p1 = limit->p1.max; | |
738 | clock.p1 >= limit->p1.min; clock.p1--) { | |
739 | int this_err; | |
740 | ||
ac58c3f0 | 741 | i9xx_clock(refclk, &clock); |
1b894b59 CW |
742 | if (!intel_PLL_is_valid(dev, limit, |
743 | &clock)) | |
d4906093 | 744 | continue; |
1b894b59 CW |
745 | |
746 | this_err = abs(clock.dot - target); | |
d4906093 ML |
747 | if (this_err < err_most) { |
748 | *best_clock = clock; | |
749 | err_most = this_err; | |
750 | max_n = clock.n; | |
751 | found = true; | |
752 | } | |
753 | } | |
754 | } | |
755 | } | |
756 | } | |
2c07245f ZW |
757 | return found; |
758 | } | |
759 | ||
a0c4da24 | 760 | static bool |
ee9300bb DV |
761 | vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
762 | int target, int refclk, intel_clock_t *match_clock, | |
763 | intel_clock_t *best_clock) | |
a0c4da24 | 764 | { |
f01b7962 | 765 | struct drm_device *dev = crtc->dev; |
6b4bf1c4 | 766 | intel_clock_t clock; |
69e4f900 | 767 | unsigned int bestppm = 1000000; |
27e639bf VS |
768 | /* min update 19.2 MHz */ |
769 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 770 | bool found = false; |
a0c4da24 | 771 | |
6b4bf1c4 VS |
772 | target *= 5; /* fast clock */ |
773 | ||
774 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
775 | |
776 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 777 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 778 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 779 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 780 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 781 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 782 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 783 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
69e4f900 VS |
784 | unsigned int ppm, diff; |
785 | ||
6b4bf1c4 VS |
786 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
787 | refclk * clock.m1); | |
788 | ||
789 | vlv_clock(refclk, &clock); | |
43b0ac53 | 790 | |
f01b7962 VS |
791 | if (!intel_PLL_is_valid(dev, limit, |
792 | &clock)) | |
43b0ac53 VS |
793 | continue; |
794 | ||
6b4bf1c4 VS |
795 | diff = abs(clock.dot - target); |
796 | ppm = div_u64(1000000ULL * diff, target); | |
797 | ||
798 | if (ppm < 100 && clock.p > best_clock->p) { | |
43b0ac53 | 799 | bestppm = 0; |
6b4bf1c4 | 800 | *best_clock = clock; |
49e497ef | 801 | found = true; |
43b0ac53 | 802 | } |
6b4bf1c4 | 803 | |
c686122c | 804 | if (bestppm >= 10 && ppm < bestppm - 10) { |
69e4f900 | 805 | bestppm = ppm; |
6b4bf1c4 | 806 | *best_clock = clock; |
49e497ef | 807 | found = true; |
a0c4da24 JB |
808 | } |
809 | } | |
810 | } | |
811 | } | |
812 | } | |
a0c4da24 | 813 | |
49e497ef | 814 | return found; |
a0c4da24 | 815 | } |
a4fc5ed6 | 816 | |
ef9348c8 CML |
817 | static bool |
818 | chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, | |
819 | int target, int refclk, intel_clock_t *match_clock, | |
820 | intel_clock_t *best_clock) | |
821 | { | |
822 | struct drm_device *dev = crtc->dev; | |
823 | intel_clock_t clock; | |
824 | uint64_t m2; | |
825 | int found = false; | |
826 | ||
827 | memset(best_clock, 0, sizeof(*best_clock)); | |
828 | ||
829 | /* | |
830 | * Based on hardware doc, the n always set to 1, and m1 always | |
831 | * set to 2. If requires to support 200Mhz refclk, we need to | |
832 | * revisit this because n may not 1 anymore. | |
833 | */ | |
834 | clock.n = 1, clock.m1 = 2; | |
835 | target *= 5; /* fast clock */ | |
836 | ||
837 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
838 | for (clock.p2 = limit->p2.p2_fast; | |
839 | clock.p2 >= limit->p2.p2_slow; | |
840 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
841 | ||
842 | clock.p = clock.p1 * clock.p2; | |
843 | ||
844 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
845 | clock.n) << 22, refclk * clock.m1); | |
846 | ||
847 | if (m2 > INT_MAX/clock.m1) | |
848 | continue; | |
849 | ||
850 | clock.m2 = m2; | |
851 | ||
852 | chv_clock(refclk, &clock); | |
853 | ||
854 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
855 | continue; | |
856 | ||
857 | /* based on hardware requirement, prefer bigger p | |
858 | */ | |
859 | if (clock.p > best_clock->p) { | |
860 | *best_clock = clock; | |
861 | found = true; | |
862 | } | |
863 | } | |
864 | } | |
865 | ||
866 | return found; | |
867 | } | |
868 | ||
20ddf665 VS |
869 | bool intel_crtc_active(struct drm_crtc *crtc) |
870 | { | |
871 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
872 | ||
873 | /* Be paranoid as we can arrive here with only partial | |
874 | * state retrieved from the hardware during setup. | |
875 | * | |
241bfc38 | 876 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
877 | * as Haswell has gained clock readout/fastboot support. |
878 | * | |
66e514c1 | 879 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 VS |
880 | * properly reconstruct framebuffers. |
881 | */ | |
f4510a27 | 882 | return intel_crtc->active && crtc->primary->fb && |
241bfc38 | 883 | intel_crtc->config.adjusted_mode.crtc_clock; |
20ddf665 VS |
884 | } |
885 | ||
a5c961d1 PZ |
886 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
887 | enum pipe pipe) | |
888 | { | |
889 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
890 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
891 | ||
3b117c8f | 892 | return intel_crtc->config.cpu_transcoder; |
a5c961d1 PZ |
893 | } |
894 | ||
57e22f4a | 895 | static void g4x_wait_for_vblank(struct drm_device *dev, int pipe) |
a928d536 PZ |
896 | { |
897 | struct drm_i915_private *dev_priv = dev->dev_private; | |
57e22f4a | 898 | u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe); |
a928d536 PZ |
899 | |
900 | frame = I915_READ(frame_reg); | |
901 | ||
902 | if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) | |
31e4b89a DL |
903 | WARN(1, "vblank wait on pipe %c timed out\n", |
904 | pipe_name(pipe)); | |
a928d536 PZ |
905 | } |
906 | ||
9d0498a2 JB |
907 | /** |
908 | * intel_wait_for_vblank - wait for vblank on a given pipe | |
909 | * @dev: drm device | |
910 | * @pipe: pipe to wait for | |
911 | * | |
912 | * Wait for vblank to occur on a given pipe. Needed for various bits of | |
913 | * mode setting code. | |
914 | */ | |
915 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) | |
79e53945 | 916 | { |
9d0498a2 | 917 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 918 | int pipestat_reg = PIPESTAT(pipe); |
9d0498a2 | 919 | |
57e22f4a VS |
920 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
921 | g4x_wait_for_vblank(dev, pipe); | |
a928d536 PZ |
922 | return; |
923 | } | |
924 | ||
300387c0 CW |
925 | /* Clear existing vblank status. Note this will clear any other |
926 | * sticky status fields as well. | |
927 | * | |
928 | * This races with i915_driver_irq_handler() with the result | |
929 | * that either function could miss a vblank event. Here it is not | |
930 | * fatal, as we will either wait upon the next vblank interrupt or | |
931 | * timeout. Generally speaking intel_wait_for_vblank() is only | |
932 | * called during modeset at which time the GPU should be idle and | |
933 | * should *not* be performing page flips and thus not waiting on | |
934 | * vblanks... | |
935 | * Currently, the result of us stealing a vblank from the irq | |
936 | * handler is that a single frame will be skipped during swapbuffers. | |
937 | */ | |
938 | I915_WRITE(pipestat_reg, | |
939 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); | |
940 | ||
9d0498a2 | 941 | /* Wait for vblank interrupt bit to set */ |
481b6af3 CW |
942 | if (wait_for(I915_READ(pipestat_reg) & |
943 | PIPE_VBLANK_INTERRUPT_STATUS, | |
944 | 50)) | |
31e4b89a DL |
945 | DRM_DEBUG_KMS("vblank wait on pipe %c timed out\n", |
946 | pipe_name(pipe)); | |
9d0498a2 JB |
947 | } |
948 | ||
fbf49ea2 VS |
949 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
950 | { | |
951 | struct drm_i915_private *dev_priv = dev->dev_private; | |
952 | u32 reg = PIPEDSL(pipe); | |
953 | u32 line1, line2; | |
954 | u32 line_mask; | |
955 | ||
956 | if (IS_GEN2(dev)) | |
957 | line_mask = DSL_LINEMASK_GEN2; | |
958 | else | |
959 | line_mask = DSL_LINEMASK_GEN3; | |
960 | ||
961 | line1 = I915_READ(reg) & line_mask; | |
962 | mdelay(5); | |
963 | line2 = I915_READ(reg) & line_mask; | |
964 | ||
965 | return line1 == line2; | |
966 | } | |
967 | ||
ab7ad7f6 KP |
968 | /* |
969 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
9d0498a2 JB |
970 | * @dev: drm device |
971 | * @pipe: pipe to wait for | |
972 | * | |
973 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
974 | * spinning on the vblank interrupt status bit, since we won't actually | |
975 | * see an interrupt when the pipe is disabled. | |
976 | * | |
ab7ad7f6 KP |
977 | * On Gen4 and above: |
978 | * wait for the pipe register state bit to turn off | |
979 | * | |
980 | * Otherwise: | |
981 | * wait for the display line value to settle (it usually | |
982 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 983 | * |
9d0498a2 | 984 | */ |
58e10eb9 | 985 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
9d0498a2 JB |
986 | { |
987 | struct drm_i915_private *dev_priv = dev->dev_private; | |
702e7a56 PZ |
988 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
989 | pipe); | |
ab7ad7f6 KP |
990 | |
991 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 992 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
993 | |
994 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
995 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
996 | 100)) | |
284637d9 | 997 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 998 | } else { |
ab7ad7f6 | 999 | /* Wait for the display line to settle */ |
fbf49ea2 | 1000 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1001 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1002 | } |
79e53945 JB |
1003 | } |
1004 | ||
b0ea7d37 DL |
1005 | /* |
1006 | * ibx_digital_port_connected - is the specified port connected? | |
1007 | * @dev_priv: i915 private structure | |
1008 | * @port: the port to test | |
1009 | * | |
1010 | * Returns true if @port is connected, false otherwise. | |
1011 | */ | |
1012 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, | |
1013 | struct intel_digital_port *port) | |
1014 | { | |
1015 | u32 bit; | |
1016 | ||
c36346e3 | 1017 | if (HAS_PCH_IBX(dev_priv->dev)) { |
eba905b2 | 1018 | switch (port->port) { |
c36346e3 DL |
1019 | case PORT_B: |
1020 | bit = SDE_PORTB_HOTPLUG; | |
1021 | break; | |
1022 | case PORT_C: | |
1023 | bit = SDE_PORTC_HOTPLUG; | |
1024 | break; | |
1025 | case PORT_D: | |
1026 | bit = SDE_PORTD_HOTPLUG; | |
1027 | break; | |
1028 | default: | |
1029 | return true; | |
1030 | } | |
1031 | } else { | |
eba905b2 | 1032 | switch (port->port) { |
c36346e3 DL |
1033 | case PORT_B: |
1034 | bit = SDE_PORTB_HOTPLUG_CPT; | |
1035 | break; | |
1036 | case PORT_C: | |
1037 | bit = SDE_PORTC_HOTPLUG_CPT; | |
1038 | break; | |
1039 | case PORT_D: | |
1040 | bit = SDE_PORTD_HOTPLUG_CPT; | |
1041 | break; | |
1042 | default: | |
1043 | return true; | |
1044 | } | |
b0ea7d37 DL |
1045 | } |
1046 | ||
1047 | return I915_READ(SDEISR) & bit; | |
1048 | } | |
1049 | ||
b24e7179 JB |
1050 | static const char *state_string(bool enabled) |
1051 | { | |
1052 | return enabled ? "on" : "off"; | |
1053 | } | |
1054 | ||
1055 | /* Only for pre-ILK configs */ | |
55607e8a DV |
1056 | void assert_pll(struct drm_i915_private *dev_priv, |
1057 | enum pipe pipe, bool state) | |
b24e7179 JB |
1058 | { |
1059 | int reg; | |
1060 | u32 val; | |
1061 | bool cur_state; | |
1062 | ||
1063 | reg = DPLL(pipe); | |
1064 | val = I915_READ(reg); | |
1065 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
1066 | WARN(cur_state != state, | |
1067 | "PLL state assertion failure (expected %s, current %s)\n", | |
1068 | state_string(state), state_string(cur_state)); | |
1069 | } | |
b24e7179 | 1070 | |
23538ef1 JN |
1071 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
1072 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
1073 | { | |
1074 | u32 val; | |
1075 | bool cur_state; | |
1076 | ||
1077 | mutex_lock(&dev_priv->dpio_lock); | |
1078 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); | |
1079 | mutex_unlock(&dev_priv->dpio_lock); | |
1080 | ||
1081 | cur_state = val & DSI_PLL_VCO_EN; | |
1082 | WARN(cur_state != state, | |
1083 | "DSI PLL state assertion failure (expected %s, current %s)\n", | |
1084 | state_string(state), state_string(cur_state)); | |
1085 | } | |
1086 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1087 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
1088 | ||
55607e8a | 1089 | struct intel_shared_dpll * |
e2b78267 DV |
1090 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
1091 | { | |
1092 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1093 | ||
a43f6e0f | 1094 | if (crtc->config.shared_dpll < 0) |
e2b78267 DV |
1095 | return NULL; |
1096 | ||
a43f6e0f | 1097 | return &dev_priv->shared_dplls[crtc->config.shared_dpll]; |
e2b78267 DV |
1098 | } |
1099 | ||
040484af | 1100 | /* For ILK+ */ |
55607e8a DV |
1101 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1102 | struct intel_shared_dpll *pll, | |
1103 | bool state) | |
040484af | 1104 | { |
040484af | 1105 | bool cur_state; |
5358901f | 1106 | struct intel_dpll_hw_state hw_state; |
040484af | 1107 | |
92b27b08 | 1108 | if (WARN (!pll, |
46edb027 | 1109 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 1110 | return; |
ee7b9f93 | 1111 | |
5358901f | 1112 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
92b27b08 | 1113 | WARN(cur_state != state, |
5358901f DV |
1114 | "%s assertion failure (expected %s, current %s)\n", |
1115 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 1116 | } |
040484af JB |
1117 | |
1118 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1119 | enum pipe pipe, bool state) | |
1120 | { | |
1121 | int reg; | |
1122 | u32 val; | |
1123 | bool cur_state; | |
ad80a810 PZ |
1124 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1125 | pipe); | |
040484af | 1126 | |
affa9354 PZ |
1127 | if (HAS_DDI(dev_priv->dev)) { |
1128 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 1129 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 1130 | val = I915_READ(reg); |
ad80a810 | 1131 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
1132 | } else { |
1133 | reg = FDI_TX_CTL(pipe); | |
1134 | val = I915_READ(reg); | |
1135 | cur_state = !!(val & FDI_TX_ENABLE); | |
1136 | } | |
040484af JB |
1137 | WARN(cur_state != state, |
1138 | "FDI TX state assertion failure (expected %s, current %s)\n", | |
1139 | state_string(state), state_string(cur_state)); | |
1140 | } | |
1141 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1142 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1143 | ||
1144 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1145 | enum pipe pipe, bool state) | |
1146 | { | |
1147 | int reg; | |
1148 | u32 val; | |
1149 | bool cur_state; | |
1150 | ||
d63fa0dc PZ |
1151 | reg = FDI_RX_CTL(pipe); |
1152 | val = I915_READ(reg); | |
1153 | cur_state = !!(val & FDI_RX_ENABLE); | |
040484af JB |
1154 | WARN(cur_state != state, |
1155 | "FDI RX state assertion failure (expected %s, current %s)\n", | |
1156 | state_string(state), state_string(cur_state)); | |
1157 | } | |
1158 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1159 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1160 | ||
1161 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1162 | enum pipe pipe) | |
1163 | { | |
1164 | int reg; | |
1165 | u32 val; | |
1166 | ||
1167 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1168 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1169 | return; |
1170 | ||
bf507ef7 | 1171 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1172 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1173 | return; |
1174 | ||
040484af JB |
1175 | reg = FDI_TX_CTL(pipe); |
1176 | val = I915_READ(reg); | |
1177 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); | |
1178 | } | |
1179 | ||
55607e8a DV |
1180 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1181 | enum pipe pipe, bool state) | |
040484af JB |
1182 | { |
1183 | int reg; | |
1184 | u32 val; | |
55607e8a | 1185 | bool cur_state; |
040484af JB |
1186 | |
1187 | reg = FDI_RX_CTL(pipe); | |
1188 | val = I915_READ(reg); | |
55607e8a DV |
1189 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
1190 | WARN(cur_state != state, | |
1191 | "FDI RX PLL assertion failure (expected %s, current %s)\n", | |
1192 | state_string(state), state_string(cur_state)); | |
040484af JB |
1193 | } |
1194 | ||
ea0760cf JB |
1195 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1196 | enum pipe pipe) | |
1197 | { | |
bedd4dba JN |
1198 | struct drm_device *dev = dev_priv->dev; |
1199 | int pp_reg; | |
ea0760cf JB |
1200 | u32 val; |
1201 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1202 | bool locked = true; |
ea0760cf | 1203 | |
bedd4dba JN |
1204 | if (WARN_ON(HAS_DDI(dev))) |
1205 | return; | |
1206 | ||
1207 | if (HAS_PCH_SPLIT(dev)) { | |
1208 | u32 port_sel; | |
1209 | ||
ea0760cf | 1210 | pp_reg = PCH_PP_CONTROL; |
bedd4dba JN |
1211 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
1212 | ||
1213 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1214 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1215 | panel_pipe = PIPE_B; | |
1216 | /* XXX: else fix for eDP */ | |
1217 | } else if (IS_VALLEYVIEW(dev)) { | |
1218 | /* presumably write lock depends on pipe, not port select */ | |
1219 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1220 | panel_pipe = pipe; | |
ea0760cf JB |
1221 | } else { |
1222 | pp_reg = PP_CONTROL; | |
bedd4dba JN |
1223 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1224 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1225 | } |
1226 | ||
1227 | val = I915_READ(pp_reg); | |
1228 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1229 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1230 | locked = false; |
1231 | ||
ea0760cf JB |
1232 | WARN(panel_pipe == pipe && locked, |
1233 | "panel assertion failure, pipe %c regs locked\n", | |
9db4a9c7 | 1234 | pipe_name(pipe)); |
ea0760cf JB |
1235 | } |
1236 | ||
93ce0ba6 JN |
1237 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1238 | enum pipe pipe, bool state) | |
1239 | { | |
1240 | struct drm_device *dev = dev_priv->dev; | |
1241 | bool cur_state; | |
1242 | ||
d9d82081 | 1243 | if (IS_845G(dev) || IS_I865G(dev)) |
93ce0ba6 | 1244 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; |
d9d82081 | 1245 | else |
5efb3e28 | 1246 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 JN |
1247 | |
1248 | WARN(cur_state != state, | |
1249 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", | |
1250 | pipe_name(pipe), state_string(state), state_string(cur_state)); | |
1251 | } | |
1252 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1253 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1254 | ||
b840d907 JB |
1255 | void assert_pipe(struct drm_i915_private *dev_priv, |
1256 | enum pipe pipe, bool state) | |
b24e7179 JB |
1257 | { |
1258 | int reg; | |
1259 | u32 val; | |
63d7bbe9 | 1260 | bool cur_state; |
702e7a56 PZ |
1261 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1262 | pipe); | |
b24e7179 | 1263 | |
8e636784 DV |
1264 | /* if we need the pipe A quirk it must be always on */ |
1265 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
1266 | state = true; | |
1267 | ||
da7e29bd | 1268 | if (!intel_display_power_enabled(dev_priv, |
b97186f0 | 1269 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
69310161 PZ |
1270 | cur_state = false; |
1271 | } else { | |
1272 | reg = PIPECONF(cpu_transcoder); | |
1273 | val = I915_READ(reg); | |
1274 | cur_state = !!(val & PIPECONF_ENABLE); | |
1275 | } | |
1276 | ||
63d7bbe9 JB |
1277 | WARN(cur_state != state, |
1278 | "pipe %c assertion failure (expected %s, current %s)\n", | |
9db4a9c7 | 1279 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1280 | } |
1281 | ||
931872fc CW |
1282 | static void assert_plane(struct drm_i915_private *dev_priv, |
1283 | enum plane plane, bool state) | |
b24e7179 JB |
1284 | { |
1285 | int reg; | |
1286 | u32 val; | |
931872fc | 1287 | bool cur_state; |
b24e7179 JB |
1288 | |
1289 | reg = DSPCNTR(plane); | |
1290 | val = I915_READ(reg); | |
931872fc CW |
1291 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
1292 | WARN(cur_state != state, | |
1293 | "plane %c assertion failure (expected %s, current %s)\n", | |
1294 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1295 | } |
1296 | ||
931872fc CW |
1297 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1298 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1299 | ||
b24e7179 JB |
1300 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1301 | enum pipe pipe) | |
1302 | { | |
653e1026 | 1303 | struct drm_device *dev = dev_priv->dev; |
b24e7179 JB |
1304 | int reg, i; |
1305 | u32 val; | |
1306 | int cur_pipe; | |
1307 | ||
653e1026 VS |
1308 | /* Primary planes are fixed to pipes on gen4+ */ |
1309 | if (INTEL_INFO(dev)->gen >= 4) { | |
28c05794 AJ |
1310 | reg = DSPCNTR(pipe); |
1311 | val = I915_READ(reg); | |
83f26f16 | 1312 | WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1313 | "plane %c assertion failure, should be disabled but not\n", |
1314 | plane_name(pipe)); | |
19ec1358 | 1315 | return; |
28c05794 | 1316 | } |
19ec1358 | 1317 | |
b24e7179 | 1318 | /* Need to check both planes against the pipe */ |
055e393f | 1319 | for_each_pipe(dev_priv, i) { |
b24e7179 JB |
1320 | reg = DSPCNTR(i); |
1321 | val = I915_READ(reg); | |
1322 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1323 | DISPPLANE_SEL_PIPE_SHIFT; | |
1324 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, | |
9db4a9c7 JB |
1325 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1326 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1327 | } |
1328 | } | |
1329 | ||
19332d7a JB |
1330 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1331 | enum pipe pipe) | |
1332 | { | |
20674eef | 1333 | struct drm_device *dev = dev_priv->dev; |
1fe47785 | 1334 | int reg, sprite; |
19332d7a JB |
1335 | u32 val; |
1336 | ||
20674eef | 1337 | if (IS_VALLEYVIEW(dev)) { |
1fe47785 DL |
1338 | for_each_sprite(pipe, sprite) { |
1339 | reg = SPCNTR(pipe, sprite); | |
20674eef | 1340 | val = I915_READ(reg); |
83f26f16 | 1341 | WARN(val & SP_ENABLE, |
20674eef | 1342 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1343 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1344 | } |
1345 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
1346 | reg = SPRCTL(pipe); | |
19332d7a | 1347 | val = I915_READ(reg); |
83f26f16 | 1348 | WARN(val & SPRITE_ENABLE, |
06da8da2 | 1349 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1350 | plane_name(pipe), pipe_name(pipe)); |
1351 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
1352 | reg = DVSCNTR(pipe); | |
19332d7a | 1353 | val = I915_READ(reg); |
83f26f16 | 1354 | WARN(val & DVS_ENABLE, |
06da8da2 | 1355 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1356 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1357 | } |
1358 | } | |
1359 | ||
89eff4be | 1360 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1361 | { |
1362 | u32 val; | |
1363 | bool enabled; | |
1364 | ||
89eff4be | 1365 | WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1366 | |
92f2584a JB |
1367 | val = I915_READ(PCH_DREF_CONTROL); |
1368 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1369 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
1370 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); | |
1371 | } | |
1372 | ||
ab9412ba DV |
1373 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1374 | enum pipe pipe) | |
92f2584a JB |
1375 | { |
1376 | int reg; | |
1377 | u32 val; | |
1378 | bool enabled; | |
1379 | ||
ab9412ba | 1380 | reg = PCH_TRANSCONF(pipe); |
92f2584a JB |
1381 | val = I915_READ(reg); |
1382 | enabled = !!(val & TRANS_ENABLE); | |
9db4a9c7 JB |
1383 | WARN(enabled, |
1384 | "transcoder assertion failed, should be off on pipe %c but is still active\n", | |
1385 | pipe_name(pipe)); | |
92f2584a JB |
1386 | } |
1387 | ||
4e634389 KP |
1388 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1389 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1390 | { |
1391 | if ((val & DP_PORT_EN) == 0) | |
1392 | return false; | |
1393 | ||
1394 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1395 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1396 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1397 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1398 | return false; | |
44f37d1f CML |
1399 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1400 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1401 | return false; | |
f0575e92 KP |
1402 | } else { |
1403 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1404 | return false; | |
1405 | } | |
1406 | return true; | |
1407 | } | |
1408 | ||
1519b995 KP |
1409 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1410 | enum pipe pipe, u32 val) | |
1411 | { | |
dc0fa718 | 1412 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1413 | return false; |
1414 | ||
1415 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1416 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1417 | return false; |
44f37d1f CML |
1418 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1419 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1420 | return false; | |
1519b995 | 1421 | } else { |
dc0fa718 | 1422 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1423 | return false; |
1424 | } | |
1425 | return true; | |
1426 | } | |
1427 | ||
1428 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1429 | enum pipe pipe, u32 val) | |
1430 | { | |
1431 | if ((val & LVDS_PORT_EN) == 0) | |
1432 | return false; | |
1433 | ||
1434 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1435 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1436 | return false; | |
1437 | } else { | |
1438 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1439 | return false; | |
1440 | } | |
1441 | return true; | |
1442 | } | |
1443 | ||
1444 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1445 | enum pipe pipe, u32 val) | |
1446 | { | |
1447 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1448 | return false; | |
1449 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1450 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1451 | return false; | |
1452 | } else { | |
1453 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1454 | return false; | |
1455 | } | |
1456 | return true; | |
1457 | } | |
1458 | ||
291906f1 | 1459 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1460 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1461 | { |
47a05eca | 1462 | u32 val = I915_READ(reg); |
4e634389 | 1463 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1464 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1465 | reg, pipe_name(pipe)); |
de9a35ab | 1466 | |
75c5da27 DV |
1467 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
1468 | && (val & DP_PIPEB_SELECT), | |
de9a35ab | 1469 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1470 | } |
1471 | ||
1472 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1473 | enum pipe pipe, int reg) | |
1474 | { | |
47a05eca | 1475 | u32 val = I915_READ(reg); |
b70ad586 | 1476 | WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1477 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1478 | reg, pipe_name(pipe)); |
de9a35ab | 1479 | |
dc0fa718 | 1480 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1481 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1482 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1483 | } |
1484 | ||
1485 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1486 | enum pipe pipe) | |
1487 | { | |
1488 | int reg; | |
1489 | u32 val; | |
291906f1 | 1490 | |
f0575e92 KP |
1491 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1492 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1493 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1494 | |
1495 | reg = PCH_ADPA; | |
1496 | val = I915_READ(reg); | |
b70ad586 | 1497 | WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1498 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1499 | pipe_name(pipe)); |
291906f1 JB |
1500 | |
1501 | reg = PCH_LVDS; | |
1502 | val = I915_READ(reg); | |
b70ad586 | 1503 | WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1504 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1505 | pipe_name(pipe)); |
291906f1 | 1506 | |
e2debe91 PZ |
1507 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1508 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1509 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1510 | } |
1511 | ||
40e9cf64 JB |
1512 | static void intel_init_dpio(struct drm_device *dev) |
1513 | { | |
1514 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1515 | ||
1516 | if (!IS_VALLEYVIEW(dev)) | |
1517 | return; | |
1518 | ||
a09caddd CML |
1519 | /* |
1520 | * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C), | |
1521 | * CHV x1 PHY (DP/HDMI D) | |
1522 | * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C) | |
1523 | */ | |
1524 | if (IS_CHERRYVIEW(dev)) { | |
1525 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2; | |
1526 | DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO; | |
1527 | } else { | |
1528 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; | |
1529 | } | |
5382f5f3 JB |
1530 | } |
1531 | ||
426115cf | 1532 | static void vlv_enable_pll(struct intel_crtc *crtc) |
87442f73 | 1533 | { |
426115cf DV |
1534 | struct drm_device *dev = crtc->base.dev; |
1535 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1536 | int reg = DPLL(crtc->pipe); | |
1537 | u32 dpll = crtc->config.dpll_hw_state.dpll; | |
87442f73 | 1538 | |
426115cf | 1539 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 DV |
1540 | |
1541 | /* No really, not for ILK+ */ | |
1542 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); | |
1543 | ||
1544 | /* PLL is protected by panel, make sure we can write it */ | |
6a9e7363 | 1545 | if (IS_MOBILE(dev_priv->dev)) |
426115cf | 1546 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1547 | |
426115cf DV |
1548 | I915_WRITE(reg, dpll); |
1549 | POSTING_READ(reg); | |
1550 | udelay(150); | |
1551 | ||
1552 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1553 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1554 | ||
1555 | I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md); | |
1556 | POSTING_READ(DPLL_MD(crtc->pipe)); | |
87442f73 DV |
1557 | |
1558 | /* We do this three times for luck */ | |
426115cf | 1559 | I915_WRITE(reg, dpll); |
87442f73 DV |
1560 | POSTING_READ(reg); |
1561 | udelay(150); /* wait for warmup */ | |
426115cf | 1562 | I915_WRITE(reg, dpll); |
87442f73 DV |
1563 | POSTING_READ(reg); |
1564 | udelay(150); /* wait for warmup */ | |
426115cf | 1565 | I915_WRITE(reg, dpll); |
87442f73 DV |
1566 | POSTING_READ(reg); |
1567 | udelay(150); /* wait for warmup */ | |
1568 | } | |
1569 | ||
9d556c99 CML |
1570 | static void chv_enable_pll(struct intel_crtc *crtc) |
1571 | { | |
1572 | struct drm_device *dev = crtc->base.dev; | |
1573 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1574 | int pipe = crtc->pipe; | |
1575 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9d556c99 CML |
1576 | u32 tmp; |
1577 | ||
1578 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1579 | ||
1580 | BUG_ON(!IS_CHERRYVIEW(dev_priv->dev)); | |
1581 | ||
1582 | mutex_lock(&dev_priv->dpio_lock); | |
1583 | ||
1584 | /* Enable back the 10bit clock to display controller */ | |
1585 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1586 | tmp |= DPIO_DCLKP_EN; | |
1587 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1588 | ||
1589 | /* | |
1590 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1591 | */ | |
1592 | udelay(1); | |
1593 | ||
1594 | /* Enable PLL */ | |
a11b0703 | 1595 | I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll); |
9d556c99 CML |
1596 | |
1597 | /* Check PLL is locked */ | |
a11b0703 | 1598 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1599 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1600 | ||
a11b0703 VS |
1601 | /* not sure when this should be written */ |
1602 | I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md); | |
1603 | POSTING_READ(DPLL_MD(pipe)); | |
1604 | ||
9d556c99 CML |
1605 | mutex_unlock(&dev_priv->dpio_lock); |
1606 | } | |
1607 | ||
66e3d5c0 | 1608 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1609 | { |
66e3d5c0 DV |
1610 | struct drm_device *dev = crtc->base.dev; |
1611 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1612 | int reg = DPLL(crtc->pipe); | |
1613 | u32 dpll = crtc->config.dpll_hw_state.dpll; | |
63d7bbe9 | 1614 | |
66e3d5c0 | 1615 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1616 | |
63d7bbe9 | 1617 | /* No really, not for ILK+ */ |
3d13ef2e | 1618 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1619 | |
1620 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1621 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1622 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1623 | |
66e3d5c0 DV |
1624 | I915_WRITE(reg, dpll); |
1625 | ||
1626 | /* Wait for the clocks to stabilize. */ | |
1627 | POSTING_READ(reg); | |
1628 | udelay(150); | |
1629 | ||
1630 | if (INTEL_INFO(dev)->gen >= 4) { | |
1631 | I915_WRITE(DPLL_MD(crtc->pipe), | |
1632 | crtc->config.dpll_hw_state.dpll_md); | |
1633 | } else { | |
1634 | /* The pixel multiplier can only be updated once the | |
1635 | * DPLL is enabled and the clocks are stable. | |
1636 | * | |
1637 | * So write it again. | |
1638 | */ | |
1639 | I915_WRITE(reg, dpll); | |
1640 | } | |
63d7bbe9 JB |
1641 | |
1642 | /* We do this three times for luck */ | |
66e3d5c0 | 1643 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1644 | POSTING_READ(reg); |
1645 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1646 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1647 | POSTING_READ(reg); |
1648 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1649 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1650 | POSTING_READ(reg); |
1651 | udelay(150); /* wait for warmup */ | |
1652 | } | |
1653 | ||
1654 | /** | |
50b44a44 | 1655 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1656 | * @dev_priv: i915 private structure |
1657 | * @pipe: pipe PLL to disable | |
1658 | * | |
1659 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1660 | * | |
1661 | * Note! This is for pre-ILK only. | |
1662 | */ | |
50b44a44 | 1663 | static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
63d7bbe9 | 1664 | { |
63d7bbe9 JB |
1665 | /* Don't disable pipe A or pipe A PLLs if needed */ |
1666 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1667 | return; | |
1668 | ||
1669 | /* Make sure the pipe isn't still relying on us */ | |
1670 | assert_pipe_disabled(dev_priv, pipe); | |
1671 | ||
50b44a44 DV |
1672 | I915_WRITE(DPLL(pipe), 0); |
1673 | POSTING_READ(DPLL(pipe)); | |
63d7bbe9 JB |
1674 | } |
1675 | ||
f6071166 JB |
1676 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1677 | { | |
1678 | u32 val = 0; | |
1679 | ||
1680 | /* Make sure the pipe isn't still relying on us */ | |
1681 | assert_pipe_disabled(dev_priv, pipe); | |
1682 | ||
e5cbfbfb ID |
1683 | /* |
1684 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1685 | * The latter is needed for VGA hotplug / manual detection. | |
1686 | */ | |
f6071166 | 1687 | if (pipe == PIPE_B) |
e5cbfbfb | 1688 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV; |
f6071166 JB |
1689 | I915_WRITE(DPLL(pipe), val); |
1690 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1691 | |
1692 | } | |
1693 | ||
1694 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1695 | { | |
d752048d | 1696 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1697 | u32 val; |
1698 | ||
a11b0703 VS |
1699 | /* Make sure the pipe isn't still relying on us */ |
1700 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1701 | |
a11b0703 | 1702 | /* Set PLL en = 0 */ |
d17ec4ce | 1703 | val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV; |
a11b0703 VS |
1704 | if (pipe != PIPE_A) |
1705 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1706 | I915_WRITE(DPLL(pipe), val); | |
1707 | POSTING_READ(DPLL(pipe)); | |
d752048d VS |
1708 | |
1709 | mutex_lock(&dev_priv->dpio_lock); | |
1710 | ||
1711 | /* Disable 10bit clock to display controller */ | |
1712 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1713 | val &= ~DPIO_DCLKP_EN; | |
1714 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1715 | ||
61407f6d VS |
1716 | /* disable left/right clock distribution */ |
1717 | if (pipe != PIPE_B) { | |
1718 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); | |
1719 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); | |
1720 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); | |
1721 | } else { | |
1722 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); | |
1723 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); | |
1724 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); | |
1725 | } | |
1726 | ||
d752048d | 1727 | mutex_unlock(&dev_priv->dpio_lock); |
f6071166 JB |
1728 | } |
1729 | ||
e4607fcf CML |
1730 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
1731 | struct intel_digital_port *dport) | |
89b667f8 JB |
1732 | { |
1733 | u32 port_mask; | |
00fc31b7 | 1734 | int dpll_reg; |
89b667f8 | 1735 | |
e4607fcf CML |
1736 | switch (dport->port) { |
1737 | case PORT_B: | |
89b667f8 | 1738 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1739 | dpll_reg = DPLL(0); |
e4607fcf CML |
1740 | break; |
1741 | case PORT_C: | |
89b667f8 | 1742 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 CML |
1743 | dpll_reg = DPLL(0); |
1744 | break; | |
1745 | case PORT_D: | |
1746 | port_mask = DPLL_PORTD_READY_MASK; | |
1747 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1748 | break; |
1749 | default: | |
1750 | BUG(); | |
1751 | } | |
89b667f8 | 1752 | |
00fc31b7 | 1753 | if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000)) |
89b667f8 | 1754 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", |
00fc31b7 | 1755 | port_name(dport->port), I915_READ(dpll_reg)); |
89b667f8 JB |
1756 | } |
1757 | ||
b14b1055 DV |
1758 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
1759 | { | |
1760 | struct drm_device *dev = crtc->base.dev; | |
1761 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1762 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
1763 | ||
be19f0ff CW |
1764 | if (WARN_ON(pll == NULL)) |
1765 | return; | |
1766 | ||
b14b1055 DV |
1767 | WARN_ON(!pll->refcount); |
1768 | if (pll->active == 0) { | |
1769 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); | |
1770 | WARN_ON(pll->on); | |
1771 | assert_shared_dpll_disabled(dev_priv, pll); | |
1772 | ||
1773 | pll->mode_set(dev_priv, pll); | |
1774 | } | |
1775 | } | |
1776 | ||
92f2584a | 1777 | /** |
85b3894f | 1778 | * intel_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1779 | * @dev_priv: i915 private structure |
1780 | * @pipe: pipe PLL to enable | |
1781 | * | |
1782 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1783 | * drives the transcoder clock. | |
1784 | */ | |
85b3894f | 1785 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1786 | { |
3d13ef2e DL |
1787 | struct drm_device *dev = crtc->base.dev; |
1788 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1789 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1790 | |
87a875bb | 1791 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1792 | return; |
1793 | ||
1794 | if (WARN_ON(pll->refcount == 0)) | |
1795 | return; | |
ee7b9f93 | 1796 | |
74dd6928 | 1797 | DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n", |
46edb027 | 1798 | pll->name, pll->active, pll->on, |
e2b78267 | 1799 | crtc->base.base.id); |
92f2584a | 1800 | |
cdbd2316 DV |
1801 | if (pll->active++) { |
1802 | WARN_ON(!pll->on); | |
e9d6944e | 1803 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1804 | return; |
1805 | } | |
f4a091c7 | 1806 | WARN_ON(pll->on); |
ee7b9f93 | 1807 | |
bd2bb1b9 PZ |
1808 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
1809 | ||
46edb027 | 1810 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1811 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1812 | pll->on = true; |
92f2584a JB |
1813 | } |
1814 | ||
f6daaec2 | 1815 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1816 | { |
3d13ef2e DL |
1817 | struct drm_device *dev = crtc->base.dev; |
1818 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1819 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1820 | |
92f2584a | 1821 | /* PCH only available on ILK+ */ |
3d13ef2e | 1822 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
87a875bb | 1823 | if (WARN_ON(pll == NULL)) |
ee7b9f93 | 1824 | return; |
92f2584a | 1825 | |
48da64a8 CW |
1826 | if (WARN_ON(pll->refcount == 0)) |
1827 | return; | |
7a419866 | 1828 | |
46edb027 DV |
1829 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1830 | pll->name, pll->active, pll->on, | |
e2b78267 | 1831 | crtc->base.base.id); |
7a419866 | 1832 | |
48da64a8 | 1833 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1834 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1835 | return; |
1836 | } | |
1837 | ||
e9d6944e | 1838 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1839 | WARN_ON(!pll->on); |
cdbd2316 | 1840 | if (--pll->active) |
7a419866 | 1841 | return; |
ee7b9f93 | 1842 | |
46edb027 | 1843 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1844 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1845 | pll->on = false; |
bd2bb1b9 PZ |
1846 | |
1847 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
92f2584a JB |
1848 | } |
1849 | ||
b8a4f404 PZ |
1850 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1851 | enum pipe pipe) | |
040484af | 1852 | { |
23670b32 | 1853 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1854 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1855 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
23670b32 | 1856 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1857 | |
1858 | /* PCH only available on ILK+ */ | |
3d13ef2e | 1859 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
040484af JB |
1860 | |
1861 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1862 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1863 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1864 | |
1865 | /* FDI must be feeding us bits for PCH ports */ | |
1866 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1867 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1868 | ||
23670b32 DV |
1869 | if (HAS_PCH_CPT(dev)) { |
1870 | /* Workaround: Set the timing override bit before enabling the | |
1871 | * pch transcoder. */ | |
1872 | reg = TRANS_CHICKEN2(pipe); | |
1873 | val = I915_READ(reg); | |
1874 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1875 | I915_WRITE(reg, val); | |
59c859d6 | 1876 | } |
23670b32 | 1877 | |
ab9412ba | 1878 | reg = PCH_TRANSCONF(pipe); |
040484af | 1879 | val = I915_READ(reg); |
5f7f726d | 1880 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1881 | |
1882 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1883 | /* | |
1884 | * make the BPC in transcoder be consistent with | |
1885 | * that in pipeconf reg. | |
1886 | */ | |
dfd07d72 DV |
1887 | val &= ~PIPECONF_BPC_MASK; |
1888 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1889 | } |
5f7f726d PZ |
1890 | |
1891 | val &= ~TRANS_INTERLACE_MASK; | |
1892 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 PZ |
1893 | if (HAS_PCH_IBX(dev_priv->dev) && |
1894 | intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) | |
1895 | val |= TRANS_LEGACY_INTERLACED_ILK; | |
1896 | else | |
1897 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1898 | else |
1899 | val |= TRANS_PROGRESSIVE; | |
1900 | ||
040484af JB |
1901 | I915_WRITE(reg, val | TRANS_ENABLE); |
1902 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 1903 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1904 | } |
1905 | ||
8fb033d7 | 1906 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1907 | enum transcoder cpu_transcoder) |
040484af | 1908 | { |
8fb033d7 | 1909 | u32 val, pipeconf_val; |
8fb033d7 PZ |
1910 | |
1911 | /* PCH only available on ILK+ */ | |
3d13ef2e | 1912 | BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5); |
8fb033d7 | 1913 | |
8fb033d7 | 1914 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1915 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1916 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1917 | |
223a6fdf PZ |
1918 | /* Workaround: set timing override bit. */ |
1919 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1920 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf PZ |
1921 | I915_WRITE(_TRANSA_CHICKEN2, val); |
1922 | ||
25f3ef11 | 1923 | val = TRANS_ENABLE; |
937bb610 | 1924 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1925 | |
9a76b1c6 PZ |
1926 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1927 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1928 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1929 | else |
1930 | val |= TRANS_PROGRESSIVE; | |
1931 | ||
ab9412ba DV |
1932 | I915_WRITE(LPT_TRANSCONF, val); |
1933 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 1934 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1935 | } |
1936 | ||
b8a4f404 PZ |
1937 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1938 | enum pipe pipe) | |
040484af | 1939 | { |
23670b32 DV |
1940 | struct drm_device *dev = dev_priv->dev; |
1941 | uint32_t reg, val; | |
040484af JB |
1942 | |
1943 | /* FDI relies on the transcoder */ | |
1944 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1945 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1946 | ||
291906f1 JB |
1947 | /* Ports must be off as well */ |
1948 | assert_pch_ports_disabled(dev_priv, pipe); | |
1949 | ||
ab9412ba | 1950 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1951 | val = I915_READ(reg); |
1952 | val &= ~TRANS_ENABLE; | |
1953 | I915_WRITE(reg, val); | |
1954 | /* wait for PCH transcoder off, transcoder state */ | |
1955 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 1956 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 DV |
1957 | |
1958 | if (!HAS_PCH_IBX(dev)) { | |
1959 | /* Workaround: Clear the timing override chicken bit again. */ | |
1960 | reg = TRANS_CHICKEN2(pipe); | |
1961 | val = I915_READ(reg); | |
1962 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1963 | I915_WRITE(reg, val); | |
1964 | } | |
040484af JB |
1965 | } |
1966 | ||
ab4d966c | 1967 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1968 | { |
8fb033d7 PZ |
1969 | u32 val; |
1970 | ||
ab9412ba | 1971 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1972 | val &= ~TRANS_ENABLE; |
ab9412ba | 1973 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1974 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 1975 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 1976 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1977 | |
1978 | /* Workaround: clear timing override bit. */ | |
1979 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1980 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf | 1981 | I915_WRITE(_TRANSA_CHICKEN2, val); |
040484af JB |
1982 | } |
1983 | ||
b24e7179 | 1984 | /** |
309cfea8 | 1985 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 1986 | * @crtc: crtc responsible for the pipe |
b24e7179 | 1987 | * |
0372264a | 1988 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 1989 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 1990 | */ |
e1fdc473 | 1991 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1992 | { |
0372264a PZ |
1993 | struct drm_device *dev = crtc->base.dev; |
1994 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1995 | enum pipe pipe = crtc->pipe; | |
702e7a56 PZ |
1996 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1997 | pipe); | |
1a240d4d | 1998 | enum pipe pch_transcoder; |
b24e7179 JB |
1999 | int reg; |
2000 | u32 val; | |
2001 | ||
58c6eaa2 | 2002 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 2003 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
2004 | assert_sprites_disabled(dev_priv, pipe); |
2005 | ||
681e5811 | 2006 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
2007 | pch_transcoder = TRANSCODER_A; |
2008 | else | |
2009 | pch_transcoder = pipe; | |
2010 | ||
b24e7179 JB |
2011 | /* |
2012 | * A pipe without a PLL won't actually be able to drive bits from | |
2013 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
2014 | * need the check. | |
2015 | */ | |
2016 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
fbf3218a | 2017 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
2018 | assert_dsi_pll_enabled(dev_priv); |
2019 | else | |
2020 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 2021 | else { |
30421c4f | 2022 | if (crtc->config.has_pch_encoder) { |
040484af | 2023 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 2024 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
2025 | assert_fdi_tx_pll_enabled(dev_priv, |
2026 | (enum pipe) cpu_transcoder); | |
040484af JB |
2027 | } |
2028 | /* FIXME: assert CPU port conditions for SNB+ */ | |
2029 | } | |
b24e7179 | 2030 | |
702e7a56 | 2031 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2032 | val = I915_READ(reg); |
7ad25d48 PZ |
2033 | if (val & PIPECONF_ENABLE) { |
2034 | WARN_ON(!(pipe == PIPE_A && | |
2035 | dev_priv->quirks & QUIRK_PIPEA_FORCE)); | |
00d70b15 | 2036 | return; |
7ad25d48 | 2037 | } |
00d70b15 CW |
2038 | |
2039 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2040 | POSTING_READ(reg); |
b24e7179 JB |
2041 | } |
2042 | ||
2043 | /** | |
309cfea8 | 2044 | * intel_disable_pipe - disable a pipe, asserting requirements |
b24e7179 JB |
2045 | * @dev_priv: i915 private structure |
2046 | * @pipe: pipe to disable | |
2047 | * | |
2048 | * Disable @pipe, making sure that various hardware specific requirements | |
2049 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. | |
2050 | * | |
2051 | * @pipe should be %PIPE_A or %PIPE_B. | |
2052 | * | |
2053 | * Will wait until the pipe has shut down before returning. | |
2054 | */ | |
2055 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, | |
2056 | enum pipe pipe) | |
2057 | { | |
702e7a56 PZ |
2058 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
2059 | pipe); | |
b24e7179 JB |
2060 | int reg; |
2061 | u32 val; | |
2062 | ||
2063 | /* | |
2064 | * Make sure planes won't keep trying to pump pixels to us, | |
2065 | * or we might hang the display. | |
2066 | */ | |
2067 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2068 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2069 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 JB |
2070 | |
2071 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
2072 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
2073 | return; | |
2074 | ||
702e7a56 | 2075 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2076 | val = I915_READ(reg); |
00d70b15 CW |
2077 | if ((val & PIPECONF_ENABLE) == 0) |
2078 | return; | |
2079 | ||
2080 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); | |
b24e7179 JB |
2081 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
2082 | } | |
2083 | ||
d74362c9 KP |
2084 | /* |
2085 | * Plane regs are double buffered, going from enabled->disabled needs a | |
2086 | * trigger in order to latch. The display address reg provides this. | |
2087 | */ | |
1dba99f4 VS |
2088 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
2089 | enum plane plane) | |
d74362c9 | 2090 | { |
3d13ef2e DL |
2091 | struct drm_device *dev = dev_priv->dev; |
2092 | u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); | |
1dba99f4 VS |
2093 | |
2094 | I915_WRITE(reg, I915_READ(reg)); | |
2095 | POSTING_READ(reg); | |
d74362c9 KP |
2096 | } |
2097 | ||
b24e7179 | 2098 | /** |
262ca2b0 | 2099 | * intel_enable_primary_hw_plane - enable the primary plane on a given pipe |
fdd508a6 VS |
2100 | * @plane: plane to be enabled |
2101 | * @crtc: crtc for the plane | |
b24e7179 | 2102 | * |
fdd508a6 | 2103 | * Enable @plane on @crtc, making sure that the pipe is running first. |
b24e7179 | 2104 | */ |
fdd508a6 VS |
2105 | static void intel_enable_primary_hw_plane(struct drm_plane *plane, |
2106 | struct drm_crtc *crtc) | |
b24e7179 | 2107 | { |
fdd508a6 VS |
2108 | struct drm_device *dev = plane->dev; |
2109 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2110 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b24e7179 JB |
2111 | |
2112 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
fdd508a6 | 2113 | assert_pipe_enabled(dev_priv, intel_crtc->pipe); |
b24e7179 | 2114 | |
98ec7739 VS |
2115 | if (intel_crtc->primary_enabled) |
2116 | return; | |
0037f71c | 2117 | |
4c445e0e | 2118 | intel_crtc->primary_enabled = true; |
939c2fe8 | 2119 | |
fdd508a6 VS |
2120 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
2121 | crtc->x, crtc->y); | |
33c3b0d1 VS |
2122 | |
2123 | /* | |
2124 | * BDW signals flip done immediately if the plane | |
2125 | * is disabled, even if the plane enable is already | |
2126 | * armed to occur at the next vblank :( | |
2127 | */ | |
2128 | if (IS_BROADWELL(dev)) | |
2129 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
b24e7179 JB |
2130 | } |
2131 | ||
b24e7179 | 2132 | /** |
262ca2b0 | 2133 | * intel_disable_primary_hw_plane - disable the primary hardware plane |
fdd508a6 VS |
2134 | * @plane: plane to be disabled |
2135 | * @crtc: crtc for the plane | |
b24e7179 | 2136 | * |
fdd508a6 | 2137 | * Disable @plane on @crtc, making sure that the pipe is running first. |
b24e7179 | 2138 | */ |
fdd508a6 VS |
2139 | static void intel_disable_primary_hw_plane(struct drm_plane *plane, |
2140 | struct drm_crtc *crtc) | |
b24e7179 | 2141 | { |
fdd508a6 VS |
2142 | struct drm_device *dev = plane->dev; |
2143 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2144 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2145 | ||
2146 | assert_pipe_enabled(dev_priv, intel_crtc->pipe); | |
b24e7179 | 2147 | |
98ec7739 VS |
2148 | if (!intel_crtc->primary_enabled) |
2149 | return; | |
0037f71c | 2150 | |
4c445e0e | 2151 | intel_crtc->primary_enabled = false; |
939c2fe8 | 2152 | |
fdd508a6 VS |
2153 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
2154 | crtc->x, crtc->y); | |
b24e7179 JB |
2155 | } |
2156 | ||
693db184 CW |
2157 | static bool need_vtd_wa(struct drm_device *dev) |
2158 | { | |
2159 | #ifdef CONFIG_INTEL_IOMMU | |
2160 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2161 | return true; | |
2162 | #endif | |
2163 | return false; | |
2164 | } | |
2165 | ||
a57ce0b2 JB |
2166 | static int intel_align_height(struct drm_device *dev, int height, bool tiled) |
2167 | { | |
2168 | int tile_height; | |
2169 | ||
2170 | tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1; | |
2171 | return ALIGN(height, tile_height); | |
2172 | } | |
2173 | ||
127bd2ac | 2174 | int |
48b956c5 | 2175 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
05394f39 | 2176 | struct drm_i915_gem_object *obj, |
a4872ba6 | 2177 | struct intel_engine_cs *pipelined) |
6b95a207 | 2178 | { |
ce453d81 | 2179 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
2180 | u32 alignment; |
2181 | int ret; | |
2182 | ||
ebcdd39e MR |
2183 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2184 | ||
05394f39 | 2185 | switch (obj->tiling_mode) { |
6b95a207 | 2186 | case I915_TILING_NONE: |
534843da CW |
2187 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
2188 | alignment = 128 * 1024; | |
a6c45cf0 | 2189 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
2190 | alignment = 4 * 1024; |
2191 | else | |
2192 | alignment = 64 * 1024; | |
6b95a207 KH |
2193 | break; |
2194 | case I915_TILING_X: | |
2195 | /* pin() will align the object as required by fence */ | |
2196 | alignment = 0; | |
2197 | break; | |
2198 | case I915_TILING_Y: | |
80075d49 | 2199 | WARN(1, "Y tiled bo slipped through, driver bug!\n"); |
6b95a207 KH |
2200 | return -EINVAL; |
2201 | default: | |
2202 | BUG(); | |
2203 | } | |
2204 | ||
693db184 CW |
2205 | /* Note that the w/a also requires 64 PTE of padding following the |
2206 | * bo. We currently fill all unused PTE with the shadow page and so | |
2207 | * we should always have valid PTE following the scanout preventing | |
2208 | * the VT-d warning. | |
2209 | */ | |
2210 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2211 | alignment = 256 * 1024; | |
2212 | ||
ce453d81 | 2213 | dev_priv->mm.interruptible = false; |
2da3b9b9 | 2214 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
48b956c5 | 2215 | if (ret) |
ce453d81 | 2216 | goto err_interruptible; |
6b95a207 KH |
2217 | |
2218 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2219 | * fence, whereas 965+ only requires a fence if using | |
2220 | * framebuffer compression. For simplicity, we always install | |
2221 | * a fence as the cost is not that onerous. | |
2222 | */ | |
06d98131 | 2223 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
2224 | if (ret) |
2225 | goto err_unpin; | |
1690e1eb | 2226 | |
9a5a53b3 | 2227 | i915_gem_object_pin_fence(obj); |
6b95a207 | 2228 | |
ce453d81 | 2229 | dev_priv->mm.interruptible = true; |
6b95a207 | 2230 | return 0; |
48b956c5 CW |
2231 | |
2232 | err_unpin: | |
cc98b413 | 2233 | i915_gem_object_unpin_from_display_plane(obj); |
ce453d81 CW |
2234 | err_interruptible: |
2235 | dev_priv->mm.interruptible = true; | |
48b956c5 | 2236 | return ret; |
6b95a207 KH |
2237 | } |
2238 | ||
1690e1eb CW |
2239 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
2240 | { | |
ebcdd39e MR |
2241 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2242 | ||
1690e1eb | 2243 | i915_gem_object_unpin_fence(obj); |
cc98b413 | 2244 | i915_gem_object_unpin_from_display_plane(obj); |
1690e1eb CW |
2245 | } |
2246 | ||
c2c75131 DV |
2247 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2248 | * is assumed to be a power-of-two. */ | |
bc752862 CW |
2249 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
2250 | unsigned int tiling_mode, | |
2251 | unsigned int cpp, | |
2252 | unsigned int pitch) | |
c2c75131 | 2253 | { |
bc752862 CW |
2254 | if (tiling_mode != I915_TILING_NONE) { |
2255 | unsigned int tile_rows, tiles; | |
c2c75131 | 2256 | |
bc752862 CW |
2257 | tile_rows = *y / 8; |
2258 | *y %= 8; | |
c2c75131 | 2259 | |
bc752862 CW |
2260 | tiles = *x / (512/cpp); |
2261 | *x %= 512/cpp; | |
2262 | ||
2263 | return tile_rows * pitch * 8 + tiles * 4096; | |
2264 | } else { | |
2265 | unsigned int offset; | |
2266 | ||
2267 | offset = *y * pitch + *x * cpp; | |
2268 | *y = 0; | |
2269 | *x = (offset & 4095) / cpp; | |
2270 | return offset & -4096; | |
2271 | } | |
c2c75131 DV |
2272 | } |
2273 | ||
46f297fb JB |
2274 | int intel_format_to_fourcc(int format) |
2275 | { | |
2276 | switch (format) { | |
2277 | case DISPPLANE_8BPP: | |
2278 | return DRM_FORMAT_C8; | |
2279 | case DISPPLANE_BGRX555: | |
2280 | return DRM_FORMAT_XRGB1555; | |
2281 | case DISPPLANE_BGRX565: | |
2282 | return DRM_FORMAT_RGB565; | |
2283 | default: | |
2284 | case DISPPLANE_BGRX888: | |
2285 | return DRM_FORMAT_XRGB8888; | |
2286 | case DISPPLANE_RGBX888: | |
2287 | return DRM_FORMAT_XBGR8888; | |
2288 | case DISPPLANE_BGRX101010: | |
2289 | return DRM_FORMAT_XRGB2101010; | |
2290 | case DISPPLANE_RGBX101010: | |
2291 | return DRM_FORMAT_XBGR2101010; | |
2292 | } | |
2293 | } | |
2294 | ||
484b41dd | 2295 | static bool intel_alloc_plane_obj(struct intel_crtc *crtc, |
46f297fb JB |
2296 | struct intel_plane_config *plane_config) |
2297 | { | |
2298 | struct drm_device *dev = crtc->base.dev; | |
2299 | struct drm_i915_gem_object *obj = NULL; | |
2300 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2301 | u32 base = plane_config->base; | |
2302 | ||
ff2652ea CW |
2303 | if (plane_config->size == 0) |
2304 | return false; | |
2305 | ||
46f297fb JB |
2306 | obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base, |
2307 | plane_config->size); | |
2308 | if (!obj) | |
484b41dd | 2309 | return false; |
46f297fb JB |
2310 | |
2311 | if (plane_config->tiled) { | |
2312 | obj->tiling_mode = I915_TILING_X; | |
66e514c1 | 2313 | obj->stride = crtc->base.primary->fb->pitches[0]; |
46f297fb JB |
2314 | } |
2315 | ||
66e514c1 DA |
2316 | mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format; |
2317 | mode_cmd.width = crtc->base.primary->fb->width; | |
2318 | mode_cmd.height = crtc->base.primary->fb->height; | |
2319 | mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0]; | |
46f297fb JB |
2320 | |
2321 | mutex_lock(&dev->struct_mutex); | |
2322 | ||
66e514c1 | 2323 | if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb), |
484b41dd | 2324 | &mode_cmd, obj)) { |
46f297fb JB |
2325 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2326 | goto out_unref_obj; | |
2327 | } | |
2328 | ||
a071fa00 | 2329 | obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe); |
46f297fb | 2330 | mutex_unlock(&dev->struct_mutex); |
484b41dd JB |
2331 | |
2332 | DRM_DEBUG_KMS("plane fb obj %p\n", obj); | |
2333 | return true; | |
46f297fb JB |
2334 | |
2335 | out_unref_obj: | |
2336 | drm_gem_object_unreference(&obj->base); | |
2337 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2338 | return false; |
2339 | } | |
2340 | ||
2341 | static void intel_find_plane_obj(struct intel_crtc *intel_crtc, | |
2342 | struct intel_plane_config *plane_config) | |
2343 | { | |
2344 | struct drm_device *dev = intel_crtc->base.dev; | |
2345 | struct drm_crtc *c; | |
2346 | struct intel_crtc *i; | |
2ff8fde1 | 2347 | struct drm_i915_gem_object *obj; |
484b41dd | 2348 | |
66e514c1 | 2349 | if (!intel_crtc->base.primary->fb) |
484b41dd JB |
2350 | return; |
2351 | ||
2352 | if (intel_alloc_plane_obj(intel_crtc, plane_config)) | |
2353 | return; | |
2354 | ||
66e514c1 DA |
2355 | kfree(intel_crtc->base.primary->fb); |
2356 | intel_crtc->base.primary->fb = NULL; | |
484b41dd JB |
2357 | |
2358 | /* | |
2359 | * Failed to alloc the obj, check to see if we should share | |
2360 | * an fb with another CRTC instead | |
2361 | */ | |
70e1e0ec | 2362 | for_each_crtc(dev, c) { |
484b41dd JB |
2363 | i = to_intel_crtc(c); |
2364 | ||
2365 | if (c == &intel_crtc->base) | |
2366 | continue; | |
2367 | ||
2ff8fde1 MR |
2368 | if (!i->active) |
2369 | continue; | |
2370 | ||
2371 | obj = intel_fb_obj(c->primary->fb); | |
2372 | if (obj == NULL) | |
484b41dd JB |
2373 | continue; |
2374 | ||
2ff8fde1 | 2375 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
66e514c1 DA |
2376 | drm_framebuffer_reference(c->primary->fb); |
2377 | intel_crtc->base.primary->fb = c->primary->fb; | |
2ff8fde1 | 2378 | obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); |
484b41dd JB |
2379 | break; |
2380 | } | |
2381 | } | |
46f297fb JB |
2382 | } |
2383 | ||
29b9bde6 DV |
2384 | static void i9xx_update_primary_plane(struct drm_crtc *crtc, |
2385 | struct drm_framebuffer *fb, | |
2386 | int x, int y) | |
81255565 JB |
2387 | { |
2388 | struct drm_device *dev = crtc->dev; | |
2389 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2390 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2ff8fde1 | 2391 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
81255565 | 2392 | int plane = intel_crtc->plane; |
e506a0c6 | 2393 | unsigned long linear_offset; |
81255565 | 2394 | u32 dspcntr; |
f45651ba | 2395 | u32 reg = DSPCNTR(plane); |
48404c1e SJ |
2396 | int pixel_size; |
2397 | ||
2398 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
f45651ba | 2399 | |
fdd508a6 VS |
2400 | if (!intel_crtc->primary_enabled) { |
2401 | I915_WRITE(reg, 0); | |
2402 | if (INTEL_INFO(dev)->gen >= 4) | |
2403 | I915_WRITE(DSPSURF(plane), 0); | |
2404 | else | |
2405 | I915_WRITE(DSPADDR(plane), 0); | |
2406 | POSTING_READ(reg); | |
2407 | return; | |
2408 | } | |
2409 | ||
f45651ba VS |
2410 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2411 | ||
fdd508a6 | 2412 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2413 | |
2414 | if (INTEL_INFO(dev)->gen < 4) { | |
2415 | if (intel_crtc->pipe == PIPE_B) | |
2416 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2417 | ||
2418 | /* pipesrc and dspsize control the size that is scaled from, | |
2419 | * which should always be the user's requested size. | |
2420 | */ | |
2421 | I915_WRITE(DSPSIZE(plane), | |
2422 | ((intel_crtc->config.pipe_src_h - 1) << 16) | | |
2423 | (intel_crtc->config.pipe_src_w - 1)); | |
2424 | I915_WRITE(DSPPOS(plane), 0); | |
2425 | } | |
81255565 | 2426 | |
57779d06 VS |
2427 | switch (fb->pixel_format) { |
2428 | case DRM_FORMAT_C8: | |
81255565 JB |
2429 | dspcntr |= DISPPLANE_8BPP; |
2430 | break; | |
57779d06 VS |
2431 | case DRM_FORMAT_XRGB1555: |
2432 | case DRM_FORMAT_ARGB1555: | |
2433 | dspcntr |= DISPPLANE_BGRX555; | |
81255565 | 2434 | break; |
57779d06 VS |
2435 | case DRM_FORMAT_RGB565: |
2436 | dspcntr |= DISPPLANE_BGRX565; | |
2437 | break; | |
2438 | case DRM_FORMAT_XRGB8888: | |
2439 | case DRM_FORMAT_ARGB8888: | |
2440 | dspcntr |= DISPPLANE_BGRX888; | |
2441 | break; | |
2442 | case DRM_FORMAT_XBGR8888: | |
2443 | case DRM_FORMAT_ABGR8888: | |
2444 | dspcntr |= DISPPLANE_RGBX888; | |
2445 | break; | |
2446 | case DRM_FORMAT_XRGB2101010: | |
2447 | case DRM_FORMAT_ARGB2101010: | |
2448 | dspcntr |= DISPPLANE_BGRX101010; | |
2449 | break; | |
2450 | case DRM_FORMAT_XBGR2101010: | |
2451 | case DRM_FORMAT_ABGR2101010: | |
2452 | dspcntr |= DISPPLANE_RGBX101010; | |
81255565 JB |
2453 | break; |
2454 | default: | |
baba133a | 2455 | BUG(); |
81255565 | 2456 | } |
57779d06 | 2457 | |
f45651ba VS |
2458 | if (INTEL_INFO(dev)->gen >= 4 && |
2459 | obj->tiling_mode != I915_TILING_NONE) | |
2460 | dspcntr |= DISPPLANE_TILED; | |
81255565 | 2461 | |
de1aa629 VS |
2462 | if (IS_G4X(dev)) |
2463 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2464 | ||
e506a0c6 | 2465 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
81255565 | 2466 | |
c2c75131 DV |
2467 | if (INTEL_INFO(dev)->gen >= 4) { |
2468 | intel_crtc->dspaddr_offset = | |
bc752862 CW |
2469 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2470 | fb->bits_per_pixel / 8, | |
2471 | fb->pitches[0]); | |
c2c75131 DV |
2472 | linear_offset -= intel_crtc->dspaddr_offset; |
2473 | } else { | |
e506a0c6 | 2474 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2475 | } |
e506a0c6 | 2476 | |
48404c1e SJ |
2477 | if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) { |
2478 | dspcntr |= DISPPLANE_ROTATE_180; | |
2479 | ||
2480 | x += (intel_crtc->config.pipe_src_w - 1); | |
2481 | y += (intel_crtc->config.pipe_src_h - 1); | |
2482 | ||
2483 | /* Finding the last pixel of the last line of the display | |
2484 | data and adding to linear_offset*/ | |
2485 | linear_offset += | |
2486 | (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] + | |
2487 | (intel_crtc->config.pipe_src_w - 1) * pixel_size; | |
2488 | } | |
2489 | ||
2490 | I915_WRITE(reg, dspcntr); | |
2491 | ||
f343c5f6 BW |
2492 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2493 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2494 | fb->pitches[0]); | |
01f2c773 | 2495 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2496 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2497 | I915_WRITE(DSPSURF(plane), |
2498 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2499 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2500 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2501 | } else |
f343c5f6 | 2502 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2503 | POSTING_READ(reg); |
17638cd6 JB |
2504 | } |
2505 | ||
29b9bde6 DV |
2506 | static void ironlake_update_primary_plane(struct drm_crtc *crtc, |
2507 | struct drm_framebuffer *fb, | |
2508 | int x, int y) | |
17638cd6 JB |
2509 | { |
2510 | struct drm_device *dev = crtc->dev; | |
2511 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2512 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2ff8fde1 | 2513 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
17638cd6 | 2514 | int plane = intel_crtc->plane; |
e506a0c6 | 2515 | unsigned long linear_offset; |
17638cd6 | 2516 | u32 dspcntr; |
f45651ba | 2517 | u32 reg = DSPCNTR(plane); |
48404c1e SJ |
2518 | int pixel_size; |
2519 | ||
2520 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
f45651ba | 2521 | |
fdd508a6 VS |
2522 | if (!intel_crtc->primary_enabled) { |
2523 | I915_WRITE(reg, 0); | |
2524 | I915_WRITE(DSPSURF(plane), 0); | |
2525 | POSTING_READ(reg); | |
2526 | return; | |
2527 | } | |
2528 | ||
f45651ba VS |
2529 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2530 | ||
fdd508a6 | 2531 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2532 | |
2533 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2534 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2535 | |
57779d06 VS |
2536 | switch (fb->pixel_format) { |
2537 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2538 | dspcntr |= DISPPLANE_8BPP; |
2539 | break; | |
57779d06 VS |
2540 | case DRM_FORMAT_RGB565: |
2541 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2542 | break; |
57779d06 VS |
2543 | case DRM_FORMAT_XRGB8888: |
2544 | case DRM_FORMAT_ARGB8888: | |
2545 | dspcntr |= DISPPLANE_BGRX888; | |
2546 | break; | |
2547 | case DRM_FORMAT_XBGR8888: | |
2548 | case DRM_FORMAT_ABGR8888: | |
2549 | dspcntr |= DISPPLANE_RGBX888; | |
2550 | break; | |
2551 | case DRM_FORMAT_XRGB2101010: | |
2552 | case DRM_FORMAT_ARGB2101010: | |
2553 | dspcntr |= DISPPLANE_BGRX101010; | |
2554 | break; | |
2555 | case DRM_FORMAT_XBGR2101010: | |
2556 | case DRM_FORMAT_ABGR2101010: | |
2557 | dspcntr |= DISPPLANE_RGBX101010; | |
17638cd6 JB |
2558 | break; |
2559 | default: | |
baba133a | 2560 | BUG(); |
17638cd6 JB |
2561 | } |
2562 | ||
2563 | if (obj->tiling_mode != I915_TILING_NONE) | |
2564 | dspcntr |= DISPPLANE_TILED; | |
17638cd6 | 2565 | |
f45651ba | 2566 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2567 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2568 | |
e506a0c6 | 2569 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
c2c75131 | 2570 | intel_crtc->dspaddr_offset = |
bc752862 CW |
2571 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2572 | fb->bits_per_pixel / 8, | |
2573 | fb->pitches[0]); | |
c2c75131 | 2574 | linear_offset -= intel_crtc->dspaddr_offset; |
48404c1e SJ |
2575 | if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) { |
2576 | dspcntr |= DISPPLANE_ROTATE_180; | |
2577 | ||
2578 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
2579 | x += (intel_crtc->config.pipe_src_w - 1); | |
2580 | y += (intel_crtc->config.pipe_src_h - 1); | |
2581 | ||
2582 | /* Finding the last pixel of the last line of the display | |
2583 | data and adding to linear_offset*/ | |
2584 | linear_offset += | |
2585 | (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] + | |
2586 | (intel_crtc->config.pipe_src_w - 1) * pixel_size; | |
2587 | } | |
2588 | } | |
2589 | ||
2590 | I915_WRITE(reg, dspcntr); | |
17638cd6 | 2591 | |
f343c5f6 BW |
2592 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2593 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2594 | fb->pitches[0]); | |
01f2c773 | 2595 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2596 | I915_WRITE(DSPSURF(plane), |
2597 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2598 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2599 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2600 | } else { | |
2601 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2602 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2603 | } | |
17638cd6 | 2604 | POSTING_READ(reg); |
17638cd6 JB |
2605 | } |
2606 | ||
2607 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ | |
2608 | static int | |
2609 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
2610 | int x, int y, enum mode_set_atomic state) | |
2611 | { | |
2612 | struct drm_device *dev = crtc->dev; | |
2613 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 2614 | |
6b8e6ed0 CW |
2615 | if (dev_priv->display.disable_fbc) |
2616 | dev_priv->display.disable_fbc(dev); | |
cc36513c | 2617 | intel_increase_pllclock(dev, to_intel_crtc(crtc)->pipe); |
81255565 | 2618 | |
29b9bde6 DV |
2619 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
2620 | ||
2621 | return 0; | |
81255565 JB |
2622 | } |
2623 | ||
96a02917 VS |
2624 | void intel_display_handle_reset(struct drm_device *dev) |
2625 | { | |
2626 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2627 | struct drm_crtc *crtc; | |
2628 | ||
2629 | /* | |
2630 | * Flips in the rings have been nuked by the reset, | |
2631 | * so complete all pending flips so that user space | |
2632 | * will get its events and not get stuck. | |
2633 | * | |
2634 | * Also update the base address of all primary | |
2635 | * planes to the the last fb to make sure we're | |
2636 | * showing the correct fb after a reset. | |
2637 | * | |
2638 | * Need to make two loops over the crtcs so that we | |
2639 | * don't try to grab a crtc mutex before the | |
2640 | * pending_flip_queue really got woken up. | |
2641 | */ | |
2642 | ||
70e1e0ec | 2643 | for_each_crtc(dev, crtc) { |
96a02917 VS |
2644 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2645 | enum plane plane = intel_crtc->plane; | |
2646 | ||
2647 | intel_prepare_page_flip(dev, plane); | |
2648 | intel_finish_page_flip_plane(dev, plane); | |
2649 | } | |
2650 | ||
70e1e0ec | 2651 | for_each_crtc(dev, crtc) { |
96a02917 VS |
2652 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2653 | ||
51fd371b | 2654 | drm_modeset_lock(&crtc->mutex, NULL); |
947fdaad CW |
2655 | /* |
2656 | * FIXME: Once we have proper support for primary planes (and | |
2657 | * disabling them without disabling the entire crtc) allow again | |
66e514c1 | 2658 | * a NULL crtc->primary->fb. |
947fdaad | 2659 | */ |
f4510a27 | 2660 | if (intel_crtc->active && crtc->primary->fb) |
262ca2b0 | 2661 | dev_priv->display.update_primary_plane(crtc, |
66e514c1 | 2662 | crtc->primary->fb, |
262ca2b0 MR |
2663 | crtc->x, |
2664 | crtc->y); | |
51fd371b | 2665 | drm_modeset_unlock(&crtc->mutex); |
96a02917 VS |
2666 | } |
2667 | } | |
2668 | ||
14667a4b CW |
2669 | static int |
2670 | intel_finish_fb(struct drm_framebuffer *old_fb) | |
2671 | { | |
2ff8fde1 | 2672 | struct drm_i915_gem_object *obj = intel_fb_obj(old_fb); |
14667a4b CW |
2673 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
2674 | bool was_interruptible = dev_priv->mm.interruptible; | |
2675 | int ret; | |
2676 | ||
14667a4b CW |
2677 | /* Big Hammer, we also need to ensure that any pending |
2678 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
2679 | * current scanout is retired before unpinning the old | |
2680 | * framebuffer. | |
2681 | * | |
2682 | * This should only fail upon a hung GPU, in which case we | |
2683 | * can safely continue. | |
2684 | */ | |
2685 | dev_priv->mm.interruptible = false; | |
2686 | ret = i915_gem_object_finish_gpu(obj); | |
2687 | dev_priv->mm.interruptible = was_interruptible; | |
2688 | ||
2689 | return ret; | |
2690 | } | |
2691 | ||
7d5e3799 CW |
2692 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
2693 | { | |
2694 | struct drm_device *dev = crtc->dev; | |
2695 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2696 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2697 | unsigned long flags; | |
2698 | bool pending; | |
2699 | ||
2700 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
2701 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
2702 | return false; | |
2703 | ||
2704 | spin_lock_irqsave(&dev->event_lock, flags); | |
2705 | pending = to_intel_crtc(crtc)->unpin_work != NULL; | |
2706 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
2707 | ||
2708 | return pending; | |
2709 | } | |
2710 | ||
5c3b82e2 | 2711 | static int |
3c4fdcfb | 2712 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
94352cf9 | 2713 | struct drm_framebuffer *fb) |
79e53945 JB |
2714 | { |
2715 | struct drm_device *dev = crtc->dev; | |
6b8e6ed0 | 2716 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 2717 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
a071fa00 | 2718 | enum pipe pipe = intel_crtc->pipe; |
2ff8fde1 MR |
2719 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2720 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
2721 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb); | |
5c3b82e2 | 2722 | int ret; |
79e53945 | 2723 | |
7d5e3799 CW |
2724 | if (intel_crtc_has_pending_flip(crtc)) { |
2725 | DRM_ERROR("pipe is still busy with an old pageflip\n"); | |
2726 | return -EBUSY; | |
2727 | } | |
2728 | ||
79e53945 | 2729 | /* no fb bound */ |
94352cf9 | 2730 | if (!fb) { |
a5071c2f | 2731 | DRM_ERROR("No FB bound\n"); |
5c3b82e2 CW |
2732 | return 0; |
2733 | } | |
2734 | ||
7eb552ae | 2735 | if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) { |
84f44ce7 VS |
2736 | DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n", |
2737 | plane_name(intel_crtc->plane), | |
2738 | INTEL_INFO(dev)->num_pipes); | |
5c3b82e2 | 2739 | return -EINVAL; |
79e53945 JB |
2740 | } |
2741 | ||
5c3b82e2 | 2742 | mutex_lock(&dev->struct_mutex); |
a071fa00 DV |
2743 | ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); |
2744 | if (ret == 0) | |
91565c85 | 2745 | i915_gem_track_fb(old_obj, obj, |
a071fa00 | 2746 | INTEL_FRONTBUFFER_PRIMARY(pipe)); |
8ac36ec1 | 2747 | mutex_unlock(&dev->struct_mutex); |
5c3b82e2 | 2748 | if (ret != 0) { |
a5071c2f | 2749 | DRM_ERROR("pin & fence failed\n"); |
5c3b82e2 CW |
2750 | return ret; |
2751 | } | |
79e53945 | 2752 | |
bb2043de DL |
2753 | /* |
2754 | * Update pipe size and adjust fitter if needed: the reason for this is | |
2755 | * that in compute_mode_changes we check the native mode (not the pfit | |
2756 | * mode) to see if we can flip rather than do a full mode set. In the | |
2757 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
2758 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
2759 | * sized surface. | |
2760 | * | |
2761 | * To fix this properly, we need to hoist the checks up into | |
2762 | * compute_mode_changes (or above), check the actual pfit state and | |
2763 | * whether the platform allows pfit disable with pipe active, and only | |
2764 | * then update the pipesrc and pfit state, even on the flip path. | |
2765 | */ | |
d330a953 | 2766 | if (i915.fastboot) { |
d7bf63f2 DL |
2767 | const struct drm_display_mode *adjusted_mode = |
2768 | &intel_crtc->config.adjusted_mode; | |
2769 | ||
4d6a3e63 | 2770 | I915_WRITE(PIPESRC(intel_crtc->pipe), |
d7bf63f2 DL |
2771 | ((adjusted_mode->crtc_hdisplay - 1) << 16) | |
2772 | (adjusted_mode->crtc_vdisplay - 1)); | |
fd4daa9c | 2773 | if (!intel_crtc->config.pch_pfit.enabled && |
4d6a3e63 JB |
2774 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
2775 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
2776 | I915_WRITE(PF_CTL(intel_crtc->pipe), 0); | |
2777 | I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0); | |
2778 | I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0); | |
2779 | } | |
0637d60d JB |
2780 | intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay; |
2781 | intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay; | |
4d6a3e63 JB |
2782 | } |
2783 | ||
29b9bde6 | 2784 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
3c4fdcfb | 2785 | |
f99d7069 DV |
2786 | if (intel_crtc->active) |
2787 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); | |
2788 | ||
f4510a27 | 2789 | crtc->primary->fb = fb; |
6c4c86f5 DV |
2790 | crtc->x = x; |
2791 | crtc->y = y; | |
94352cf9 | 2792 | |
b7f1de28 | 2793 | if (old_fb) { |
d7697eea DV |
2794 | if (intel_crtc->active && old_fb != fb) |
2795 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
8ac36ec1 | 2796 | mutex_lock(&dev->struct_mutex); |
2ff8fde1 | 2797 | intel_unpin_fb_obj(old_obj); |
8ac36ec1 | 2798 | mutex_unlock(&dev->struct_mutex); |
b7f1de28 | 2799 | } |
652c393a | 2800 | |
8ac36ec1 | 2801 | mutex_lock(&dev->struct_mutex); |
6b8e6ed0 | 2802 | intel_update_fbc(dev); |
5c3b82e2 | 2803 | mutex_unlock(&dev->struct_mutex); |
79e53945 | 2804 | |
5c3b82e2 | 2805 | return 0; |
79e53945 JB |
2806 | } |
2807 | ||
5e84e1a4 ZW |
2808 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
2809 | { | |
2810 | struct drm_device *dev = crtc->dev; | |
2811 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2812 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2813 | int pipe = intel_crtc->pipe; | |
2814 | u32 reg, temp; | |
2815 | ||
2816 | /* enable normal train */ | |
2817 | reg = FDI_TX_CTL(pipe); | |
2818 | temp = I915_READ(reg); | |
61e499bf | 2819 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
2820 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2821 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
2822 | } else { |
2823 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2824 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 2825 | } |
5e84e1a4 ZW |
2826 | I915_WRITE(reg, temp); |
2827 | ||
2828 | reg = FDI_RX_CTL(pipe); | |
2829 | temp = I915_READ(reg); | |
2830 | if (HAS_PCH_CPT(dev)) { | |
2831 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2832 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
2833 | } else { | |
2834 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2835 | temp |= FDI_LINK_TRAIN_NONE; | |
2836 | } | |
2837 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
2838 | ||
2839 | /* wait one idle pattern time */ | |
2840 | POSTING_READ(reg); | |
2841 | udelay(1000); | |
357555c0 JB |
2842 | |
2843 | /* IVB wants error correction enabled */ | |
2844 | if (IS_IVYBRIDGE(dev)) | |
2845 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
2846 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
2847 | } |
2848 | ||
1fbc0d78 | 2849 | static bool pipe_has_enabled_pch(struct intel_crtc *crtc) |
1e833f40 | 2850 | { |
1fbc0d78 DV |
2851 | return crtc->base.enabled && crtc->active && |
2852 | crtc->config.has_pch_encoder; | |
1e833f40 DV |
2853 | } |
2854 | ||
01a415fd DV |
2855 | static void ivb_modeset_global_resources(struct drm_device *dev) |
2856 | { | |
2857 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2858 | struct intel_crtc *pipe_B_crtc = | |
2859 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
2860 | struct intel_crtc *pipe_C_crtc = | |
2861 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]); | |
2862 | uint32_t temp; | |
2863 | ||
1e833f40 DV |
2864 | /* |
2865 | * When everything is off disable fdi C so that we could enable fdi B | |
2866 | * with all lanes. Note that we don't care about enabled pipes without | |
2867 | * an enabled pch encoder. | |
2868 | */ | |
2869 | if (!pipe_has_enabled_pch(pipe_B_crtc) && | |
2870 | !pipe_has_enabled_pch(pipe_C_crtc)) { | |
01a415fd DV |
2871 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
2872 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
2873 | ||
2874 | temp = I915_READ(SOUTH_CHICKEN1); | |
2875 | temp &= ~FDI_BC_BIFURCATION_SELECT; | |
2876 | DRM_DEBUG_KMS("disabling fdi C rx\n"); | |
2877 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
2878 | } | |
2879 | } | |
2880 | ||
8db9d77b ZW |
2881 | /* The FDI link training functions for ILK/Ibexpeak. */ |
2882 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
2883 | { | |
2884 | struct drm_device *dev = crtc->dev; | |
2885 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2886 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2887 | int pipe = intel_crtc->pipe; | |
5eddb70b | 2888 | u32 reg, temp, tries; |
8db9d77b | 2889 | |
1c8562f6 | 2890 | /* FDI needs bits from pipe first */ |
0fc932b8 | 2891 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 2892 | |
e1a44743 AJ |
2893 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2894 | for train result */ | |
5eddb70b CW |
2895 | reg = FDI_RX_IMR(pipe); |
2896 | temp = I915_READ(reg); | |
e1a44743 AJ |
2897 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2898 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2899 | I915_WRITE(reg, temp); |
2900 | I915_READ(reg); | |
e1a44743 AJ |
2901 | udelay(150); |
2902 | ||
8db9d77b | 2903 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2904 | reg = FDI_TX_CTL(pipe); |
2905 | temp = I915_READ(reg); | |
627eb5a3 DV |
2906 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2907 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
2908 | temp &= ~FDI_LINK_TRAIN_NONE; |
2909 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 2910 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2911 | |
5eddb70b CW |
2912 | reg = FDI_RX_CTL(pipe); |
2913 | temp = I915_READ(reg); | |
8db9d77b ZW |
2914 | temp &= ~FDI_LINK_TRAIN_NONE; |
2915 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
2916 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2917 | ||
2918 | POSTING_READ(reg); | |
8db9d77b ZW |
2919 | udelay(150); |
2920 | ||
5b2adf89 | 2921 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
2922 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
2923 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
2924 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 2925 | |
5eddb70b | 2926 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2927 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2928 | temp = I915_READ(reg); |
8db9d77b ZW |
2929 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2930 | ||
2931 | if ((temp & FDI_RX_BIT_LOCK)) { | |
2932 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 2933 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
2934 | break; |
2935 | } | |
8db9d77b | 2936 | } |
e1a44743 | 2937 | if (tries == 5) |
5eddb70b | 2938 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2939 | |
2940 | /* Train 2 */ | |
5eddb70b CW |
2941 | reg = FDI_TX_CTL(pipe); |
2942 | temp = I915_READ(reg); | |
8db9d77b ZW |
2943 | temp &= ~FDI_LINK_TRAIN_NONE; |
2944 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2945 | I915_WRITE(reg, temp); |
8db9d77b | 2946 | |
5eddb70b CW |
2947 | reg = FDI_RX_CTL(pipe); |
2948 | temp = I915_READ(reg); | |
8db9d77b ZW |
2949 | temp &= ~FDI_LINK_TRAIN_NONE; |
2950 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2951 | I915_WRITE(reg, temp); |
8db9d77b | 2952 | |
5eddb70b CW |
2953 | POSTING_READ(reg); |
2954 | udelay(150); | |
8db9d77b | 2955 | |
5eddb70b | 2956 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2957 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2958 | temp = I915_READ(reg); |
8db9d77b ZW |
2959 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2960 | ||
2961 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 2962 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
2963 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2964 | break; | |
2965 | } | |
8db9d77b | 2966 | } |
e1a44743 | 2967 | if (tries == 5) |
5eddb70b | 2968 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2969 | |
2970 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 2971 | |
8db9d77b ZW |
2972 | } |
2973 | ||
0206e353 | 2974 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
2975 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
2976 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
2977 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
2978 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
2979 | }; | |
2980 | ||
2981 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
2982 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
2983 | { | |
2984 | struct drm_device *dev = crtc->dev; | |
2985 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2986 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2987 | int pipe = intel_crtc->pipe; | |
fa37d39e | 2988 | u32 reg, temp, i, retry; |
8db9d77b | 2989 | |
e1a44743 AJ |
2990 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2991 | for train result */ | |
5eddb70b CW |
2992 | reg = FDI_RX_IMR(pipe); |
2993 | temp = I915_READ(reg); | |
e1a44743 AJ |
2994 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2995 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2996 | I915_WRITE(reg, temp); |
2997 | ||
2998 | POSTING_READ(reg); | |
e1a44743 AJ |
2999 | udelay(150); |
3000 | ||
8db9d77b | 3001 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3002 | reg = FDI_TX_CTL(pipe); |
3003 | temp = I915_READ(reg); | |
627eb5a3 DV |
3004 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
3005 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
3006 | temp &= ~FDI_LINK_TRAIN_NONE; |
3007 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3008 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3009 | /* SNB-B */ | |
3010 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3011 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3012 | |
d74cf324 DV |
3013 | I915_WRITE(FDI_RX_MISC(pipe), |
3014 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3015 | ||
5eddb70b CW |
3016 | reg = FDI_RX_CTL(pipe); |
3017 | temp = I915_READ(reg); | |
8db9d77b ZW |
3018 | if (HAS_PCH_CPT(dev)) { |
3019 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3020 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3021 | } else { | |
3022 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3023 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3024 | } | |
5eddb70b CW |
3025 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3026 | ||
3027 | POSTING_READ(reg); | |
8db9d77b ZW |
3028 | udelay(150); |
3029 | ||
0206e353 | 3030 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3031 | reg = FDI_TX_CTL(pipe); |
3032 | temp = I915_READ(reg); | |
8db9d77b ZW |
3033 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3034 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3035 | I915_WRITE(reg, temp); |
3036 | ||
3037 | POSTING_READ(reg); | |
8db9d77b ZW |
3038 | udelay(500); |
3039 | ||
fa37d39e SP |
3040 | for (retry = 0; retry < 5; retry++) { |
3041 | reg = FDI_RX_IIR(pipe); | |
3042 | temp = I915_READ(reg); | |
3043 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3044 | if (temp & FDI_RX_BIT_LOCK) { | |
3045 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3046 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3047 | break; | |
3048 | } | |
3049 | udelay(50); | |
8db9d77b | 3050 | } |
fa37d39e SP |
3051 | if (retry < 5) |
3052 | break; | |
8db9d77b ZW |
3053 | } |
3054 | if (i == 4) | |
5eddb70b | 3055 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3056 | |
3057 | /* Train 2 */ | |
5eddb70b CW |
3058 | reg = FDI_TX_CTL(pipe); |
3059 | temp = I915_READ(reg); | |
8db9d77b ZW |
3060 | temp &= ~FDI_LINK_TRAIN_NONE; |
3061 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3062 | if (IS_GEN6(dev)) { | |
3063 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3064 | /* SNB-B */ | |
3065 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3066 | } | |
5eddb70b | 3067 | I915_WRITE(reg, temp); |
8db9d77b | 3068 | |
5eddb70b CW |
3069 | reg = FDI_RX_CTL(pipe); |
3070 | temp = I915_READ(reg); | |
8db9d77b ZW |
3071 | if (HAS_PCH_CPT(dev)) { |
3072 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3073 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3074 | } else { | |
3075 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3076 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3077 | } | |
5eddb70b CW |
3078 | I915_WRITE(reg, temp); |
3079 | ||
3080 | POSTING_READ(reg); | |
8db9d77b ZW |
3081 | udelay(150); |
3082 | ||
0206e353 | 3083 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3084 | reg = FDI_TX_CTL(pipe); |
3085 | temp = I915_READ(reg); | |
8db9d77b ZW |
3086 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3087 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3088 | I915_WRITE(reg, temp); |
3089 | ||
3090 | POSTING_READ(reg); | |
8db9d77b ZW |
3091 | udelay(500); |
3092 | ||
fa37d39e SP |
3093 | for (retry = 0; retry < 5; retry++) { |
3094 | reg = FDI_RX_IIR(pipe); | |
3095 | temp = I915_READ(reg); | |
3096 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3097 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3098 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3099 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3100 | break; | |
3101 | } | |
3102 | udelay(50); | |
8db9d77b | 3103 | } |
fa37d39e SP |
3104 | if (retry < 5) |
3105 | break; | |
8db9d77b ZW |
3106 | } |
3107 | if (i == 4) | |
5eddb70b | 3108 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3109 | |
3110 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3111 | } | |
3112 | ||
357555c0 JB |
3113 | /* Manual link training for Ivy Bridge A0 parts */ |
3114 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3115 | { | |
3116 | struct drm_device *dev = crtc->dev; | |
3117 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3118 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3119 | int pipe = intel_crtc->pipe; | |
139ccd3f | 3120 | u32 reg, temp, i, j; |
357555c0 JB |
3121 | |
3122 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3123 | for train result */ | |
3124 | reg = FDI_RX_IMR(pipe); | |
3125 | temp = I915_READ(reg); | |
3126 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3127 | temp &= ~FDI_RX_BIT_LOCK; | |
3128 | I915_WRITE(reg, temp); | |
3129 | ||
3130 | POSTING_READ(reg); | |
3131 | udelay(150); | |
3132 | ||
01a415fd DV |
3133 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3134 | I915_READ(FDI_RX_IIR(pipe))); | |
3135 | ||
139ccd3f JB |
3136 | /* Try each vswing and preemphasis setting twice before moving on */ |
3137 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3138 | /* disable first in case we need to retry */ | |
3139 | reg = FDI_TX_CTL(pipe); | |
3140 | temp = I915_READ(reg); | |
3141 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3142 | temp &= ~FDI_TX_ENABLE; | |
3143 | I915_WRITE(reg, temp); | |
357555c0 | 3144 | |
139ccd3f JB |
3145 | reg = FDI_RX_CTL(pipe); |
3146 | temp = I915_READ(reg); | |
3147 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3148 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3149 | temp &= ~FDI_RX_ENABLE; | |
3150 | I915_WRITE(reg, temp); | |
357555c0 | 3151 | |
139ccd3f | 3152 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3153 | reg = FDI_TX_CTL(pipe); |
3154 | temp = I915_READ(reg); | |
139ccd3f JB |
3155 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
3156 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
3157 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; | |
357555c0 | 3158 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3159 | temp |= snb_b_fdi_train_param[j/2]; |
3160 | temp |= FDI_COMPOSITE_SYNC; | |
3161 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3162 | |
139ccd3f JB |
3163 | I915_WRITE(FDI_RX_MISC(pipe), |
3164 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3165 | |
139ccd3f | 3166 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3167 | temp = I915_READ(reg); |
139ccd3f JB |
3168 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3169 | temp |= FDI_COMPOSITE_SYNC; | |
3170 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3171 | |
139ccd3f JB |
3172 | POSTING_READ(reg); |
3173 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3174 | |
139ccd3f JB |
3175 | for (i = 0; i < 4; i++) { |
3176 | reg = FDI_RX_IIR(pipe); | |
3177 | temp = I915_READ(reg); | |
3178 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3179 | |
139ccd3f JB |
3180 | if (temp & FDI_RX_BIT_LOCK || |
3181 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3182 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3183 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3184 | i); | |
3185 | break; | |
3186 | } | |
3187 | udelay(1); /* should be 0.5us */ | |
3188 | } | |
3189 | if (i == 4) { | |
3190 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3191 | continue; | |
3192 | } | |
357555c0 | 3193 | |
139ccd3f | 3194 | /* Train 2 */ |
357555c0 JB |
3195 | reg = FDI_TX_CTL(pipe); |
3196 | temp = I915_READ(reg); | |
139ccd3f JB |
3197 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3198 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3199 | I915_WRITE(reg, temp); | |
3200 | ||
3201 | reg = FDI_RX_CTL(pipe); | |
3202 | temp = I915_READ(reg); | |
3203 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3204 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3205 | I915_WRITE(reg, temp); |
3206 | ||
3207 | POSTING_READ(reg); | |
139ccd3f | 3208 | udelay(2); /* should be 1.5us */ |
357555c0 | 3209 | |
139ccd3f JB |
3210 | for (i = 0; i < 4; i++) { |
3211 | reg = FDI_RX_IIR(pipe); | |
3212 | temp = I915_READ(reg); | |
3213 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3214 | |
139ccd3f JB |
3215 | if (temp & FDI_RX_SYMBOL_LOCK || |
3216 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3217 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3218 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3219 | i); | |
3220 | goto train_done; | |
3221 | } | |
3222 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3223 | } |
139ccd3f JB |
3224 | if (i == 4) |
3225 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3226 | } |
357555c0 | 3227 | |
139ccd3f | 3228 | train_done: |
357555c0 JB |
3229 | DRM_DEBUG_KMS("FDI train done.\n"); |
3230 | } | |
3231 | ||
88cefb6c | 3232 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3233 | { |
88cefb6c | 3234 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3235 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3236 | int pipe = intel_crtc->pipe; |
5eddb70b | 3237 | u32 reg, temp; |
79e53945 | 3238 | |
c64e311e | 3239 | |
c98e9dcf | 3240 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3241 | reg = FDI_RX_CTL(pipe); |
3242 | temp = I915_READ(reg); | |
627eb5a3 DV |
3243 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
3244 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
dfd07d72 | 3245 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3246 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3247 | ||
3248 | POSTING_READ(reg); | |
c98e9dcf JB |
3249 | udelay(200); |
3250 | ||
3251 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3252 | temp = I915_READ(reg); |
3253 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3254 | ||
3255 | POSTING_READ(reg); | |
c98e9dcf JB |
3256 | udelay(200); |
3257 | ||
20749730 PZ |
3258 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3259 | reg = FDI_TX_CTL(pipe); | |
3260 | temp = I915_READ(reg); | |
3261 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3262 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3263 | |
20749730 PZ |
3264 | POSTING_READ(reg); |
3265 | udelay(100); | |
6be4a607 | 3266 | } |
0e23b99d JB |
3267 | } |
3268 | ||
88cefb6c DV |
3269 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3270 | { | |
3271 | struct drm_device *dev = intel_crtc->base.dev; | |
3272 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3273 | int pipe = intel_crtc->pipe; | |
3274 | u32 reg, temp; | |
3275 | ||
3276 | /* Switch from PCDclk to Rawclk */ | |
3277 | reg = FDI_RX_CTL(pipe); | |
3278 | temp = I915_READ(reg); | |
3279 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3280 | ||
3281 | /* Disable CPU FDI TX PLL */ | |
3282 | reg = FDI_TX_CTL(pipe); | |
3283 | temp = I915_READ(reg); | |
3284 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3285 | ||
3286 | POSTING_READ(reg); | |
3287 | udelay(100); | |
3288 | ||
3289 | reg = FDI_RX_CTL(pipe); | |
3290 | temp = I915_READ(reg); | |
3291 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3292 | ||
3293 | /* Wait for the clocks to turn off. */ | |
3294 | POSTING_READ(reg); | |
3295 | udelay(100); | |
3296 | } | |
3297 | ||
0fc932b8 JB |
3298 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3299 | { | |
3300 | struct drm_device *dev = crtc->dev; | |
3301 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3302 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3303 | int pipe = intel_crtc->pipe; | |
3304 | u32 reg, temp; | |
3305 | ||
3306 | /* disable CPU FDI tx and PCH FDI rx */ | |
3307 | reg = FDI_TX_CTL(pipe); | |
3308 | temp = I915_READ(reg); | |
3309 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3310 | POSTING_READ(reg); | |
3311 | ||
3312 | reg = FDI_RX_CTL(pipe); | |
3313 | temp = I915_READ(reg); | |
3314 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3315 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3316 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3317 | ||
3318 | POSTING_READ(reg); | |
3319 | udelay(100); | |
3320 | ||
3321 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3322 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3323 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3324 | |
3325 | /* still set train pattern 1 */ | |
3326 | reg = FDI_TX_CTL(pipe); | |
3327 | temp = I915_READ(reg); | |
3328 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3329 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3330 | I915_WRITE(reg, temp); | |
3331 | ||
3332 | reg = FDI_RX_CTL(pipe); | |
3333 | temp = I915_READ(reg); | |
3334 | if (HAS_PCH_CPT(dev)) { | |
3335 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3336 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3337 | } else { | |
3338 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3339 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3340 | } | |
3341 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3342 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3343 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3344 | I915_WRITE(reg, temp); |
3345 | ||
3346 | POSTING_READ(reg); | |
3347 | udelay(100); | |
3348 | } | |
3349 | ||
5dce5b93 CW |
3350 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3351 | { | |
3352 | struct intel_crtc *crtc; | |
3353 | ||
3354 | /* Note that we don't need to be called with mode_config.lock here | |
3355 | * as our list of CRTC objects is static for the lifetime of the | |
3356 | * device and so cannot disappear as we iterate. Similarly, we can | |
3357 | * happily treat the predicates as racy, atomic checks as userspace | |
3358 | * cannot claim and pin a new fb without at least acquring the | |
3359 | * struct_mutex and so serialising with us. | |
3360 | */ | |
d3fcc808 | 3361 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3362 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3363 | continue; | |
3364 | ||
3365 | if (crtc->unpin_work) | |
3366 | intel_wait_for_vblank(dev, crtc->pipe); | |
3367 | ||
3368 | return true; | |
3369 | } | |
3370 | ||
3371 | return false; | |
3372 | } | |
3373 | ||
46a55d30 | 3374 | void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3375 | { |
0f91128d | 3376 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3377 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 | 3378 | |
2c10d571 | 3379 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
eed6d67d DV |
3380 | WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue, |
3381 | !intel_crtc_has_pending_flip(crtc), | |
3382 | 60*HZ) == 0); | |
5bb61643 | 3383 | |
975d568a CW |
3384 | if (crtc->primary->fb) { |
3385 | mutex_lock(&dev->struct_mutex); | |
3386 | intel_finish_fb(crtc->primary->fb); | |
3387 | mutex_unlock(&dev->struct_mutex); | |
3388 | } | |
e6c3a2a6 CW |
3389 | } |
3390 | ||
e615efe4 ED |
3391 | /* Program iCLKIP clock to the desired frequency */ |
3392 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3393 | { | |
3394 | struct drm_device *dev = crtc->dev; | |
3395 | struct drm_i915_private *dev_priv = dev->dev_private; | |
241bfc38 | 3396 | int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock; |
e615efe4 ED |
3397 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3398 | u32 temp; | |
3399 | ||
09153000 DV |
3400 | mutex_lock(&dev_priv->dpio_lock); |
3401 | ||
e615efe4 ED |
3402 | /* It is necessary to ungate the pixclk gate prior to programming |
3403 | * the divisors, and gate it back when it is done. | |
3404 | */ | |
3405 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3406 | ||
3407 | /* Disable SSCCTL */ | |
3408 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
3409 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
3410 | SBI_SSCCTL_DISABLE, | |
3411 | SBI_ICLK); | |
e615efe4 ED |
3412 | |
3413 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3414 | if (clock == 20000) { |
e615efe4 ED |
3415 | auxdiv = 1; |
3416 | divsel = 0x41; | |
3417 | phaseinc = 0x20; | |
3418 | } else { | |
3419 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3420 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3421 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3422 | * convert the virtual clock precision to KHz here for higher |
3423 | * precision. | |
3424 | */ | |
3425 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3426 | u32 iclk_pi_range = 64; | |
3427 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3428 | ||
12d7ceed | 3429 | desired_divisor = (iclk_virtual_root_freq / clock); |
e615efe4 ED |
3430 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3431 | pi_value = desired_divisor % iclk_pi_range; | |
3432 | ||
3433 | auxdiv = 0; | |
3434 | divsel = msb_divisor_value - 2; | |
3435 | phaseinc = pi_value; | |
3436 | } | |
3437 | ||
3438 | /* This should not happen with any sane values */ | |
3439 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3440 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3441 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3442 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3443 | ||
3444 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3445 | clock, |
e615efe4 ED |
3446 | auxdiv, |
3447 | divsel, | |
3448 | phasedir, | |
3449 | phaseinc); | |
3450 | ||
3451 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 3452 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
3453 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3454 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
3455 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
3456 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
3457 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
3458 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 3459 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
3460 | |
3461 | /* Program SSCAUXDIV */ | |
988d6ee8 | 3462 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
3463 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3464 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 3465 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
3466 | |
3467 | /* Enable modulator and associated divider */ | |
988d6ee8 | 3468 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 3469 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 3470 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
3471 | |
3472 | /* Wait for initialization time */ | |
3473 | udelay(24); | |
3474 | ||
3475 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 DV |
3476 | |
3477 | mutex_unlock(&dev_priv->dpio_lock); | |
e615efe4 ED |
3478 | } |
3479 | ||
275f01b2 DV |
3480 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
3481 | enum pipe pch_transcoder) | |
3482 | { | |
3483 | struct drm_device *dev = crtc->base.dev; | |
3484 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3485 | enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; | |
3486 | ||
3487 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
3488 | I915_READ(HTOTAL(cpu_transcoder))); | |
3489 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
3490 | I915_READ(HBLANK(cpu_transcoder))); | |
3491 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
3492 | I915_READ(HSYNC(cpu_transcoder))); | |
3493 | ||
3494 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
3495 | I915_READ(VTOTAL(cpu_transcoder))); | |
3496 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
3497 | I915_READ(VBLANK(cpu_transcoder))); | |
3498 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
3499 | I915_READ(VSYNC(cpu_transcoder))); | |
3500 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
3501 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
3502 | } | |
3503 | ||
1fbc0d78 DV |
3504 | static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev) |
3505 | { | |
3506 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3507 | uint32_t temp; | |
3508 | ||
3509 | temp = I915_READ(SOUTH_CHICKEN1); | |
3510 | if (temp & FDI_BC_BIFURCATION_SELECT) | |
3511 | return; | |
3512 | ||
3513 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
3514 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
3515 | ||
3516 | temp |= FDI_BC_BIFURCATION_SELECT; | |
3517 | DRM_DEBUG_KMS("enabling fdi C rx\n"); | |
3518 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
3519 | POSTING_READ(SOUTH_CHICKEN1); | |
3520 | } | |
3521 | ||
3522 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
3523 | { | |
3524 | struct drm_device *dev = intel_crtc->base.dev; | |
3525 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3526 | ||
3527 | switch (intel_crtc->pipe) { | |
3528 | case PIPE_A: | |
3529 | break; | |
3530 | case PIPE_B: | |
3531 | if (intel_crtc->config.fdi_lanes > 2) | |
3532 | WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); | |
3533 | else | |
3534 | cpt_enable_fdi_bc_bifurcation(dev); | |
3535 | ||
3536 | break; | |
3537 | case PIPE_C: | |
3538 | cpt_enable_fdi_bc_bifurcation(dev); | |
3539 | ||
3540 | break; | |
3541 | default: | |
3542 | BUG(); | |
3543 | } | |
3544 | } | |
3545 | ||
f67a559d JB |
3546 | /* |
3547 | * Enable PCH resources required for PCH ports: | |
3548 | * - PCH PLLs | |
3549 | * - FDI training & RX/TX | |
3550 | * - update transcoder timings | |
3551 | * - DP transcoding bits | |
3552 | * - transcoder | |
3553 | */ | |
3554 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
3555 | { |
3556 | struct drm_device *dev = crtc->dev; | |
3557 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3558 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3559 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 3560 | u32 reg, temp; |
2c07245f | 3561 | |
ab9412ba | 3562 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 3563 | |
1fbc0d78 DV |
3564 | if (IS_IVYBRIDGE(dev)) |
3565 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
3566 | ||
cd986abb DV |
3567 | /* Write the TU size bits before fdi link training, so that error |
3568 | * detection works. */ | |
3569 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
3570 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
3571 | ||
c98e9dcf | 3572 | /* For PCH output, training FDI link */ |
674cf967 | 3573 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 3574 | |
3ad8a208 DV |
3575 | /* We need to program the right clock selection before writing the pixel |
3576 | * mutliplier into the DPLL. */ | |
303b81e0 | 3577 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 3578 | u32 sel; |
4b645f14 | 3579 | |
c98e9dcf | 3580 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
3581 | temp |= TRANS_DPLL_ENABLE(pipe); |
3582 | sel = TRANS_DPLLB_SEL(pipe); | |
a43f6e0f | 3583 | if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
3584 | temp |= sel; |
3585 | else | |
3586 | temp &= ~sel; | |
c98e9dcf | 3587 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 3588 | } |
5eddb70b | 3589 | |
3ad8a208 DV |
3590 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
3591 | * transcoder, and we actually should do this to not upset any PCH | |
3592 | * transcoder that already use the clock when we share it. | |
3593 | * | |
3594 | * Note that enable_shared_dpll tries to do the right thing, but | |
3595 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
3596 | * the right LVDS enable sequence. */ | |
85b3894f | 3597 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 3598 | |
d9b6cb56 JB |
3599 | /* set transcoder timing, panel must allow it */ |
3600 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 3601 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 3602 | |
303b81e0 | 3603 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 3604 | |
c98e9dcf JB |
3605 | /* For PCH DP, enable TRANS_DP_CTL */ |
3606 | if (HAS_PCH_CPT(dev) && | |
417e822d KP |
3607 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
3608 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
dfd07d72 | 3609 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
5eddb70b CW |
3610 | reg = TRANS_DP_CTL(pipe); |
3611 | temp = I915_READ(reg); | |
3612 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
3613 | TRANS_DP_SYNC_MASK | |
3614 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
3615 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
3616 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 3617 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
3618 | |
3619 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 3620 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 3621 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 3622 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
3623 | |
3624 | switch (intel_trans_dp_port_sel(crtc)) { | |
3625 | case PCH_DP_B: | |
5eddb70b | 3626 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
3627 | break; |
3628 | case PCH_DP_C: | |
5eddb70b | 3629 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
3630 | break; |
3631 | case PCH_DP_D: | |
5eddb70b | 3632 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
3633 | break; |
3634 | default: | |
e95d41e1 | 3635 | BUG(); |
32f9d658 | 3636 | } |
2c07245f | 3637 | |
5eddb70b | 3638 | I915_WRITE(reg, temp); |
6be4a607 | 3639 | } |
b52eb4dc | 3640 | |
b8a4f404 | 3641 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
3642 | } |
3643 | ||
1507e5bd PZ |
3644 | static void lpt_pch_enable(struct drm_crtc *crtc) |
3645 | { | |
3646 | struct drm_device *dev = crtc->dev; | |
3647 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3648 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3b117c8f | 3649 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
1507e5bd | 3650 | |
ab9412ba | 3651 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 3652 | |
8c52b5e8 | 3653 | lpt_program_iclkip(crtc); |
1507e5bd | 3654 | |
0540e488 | 3655 | /* Set transcoder timing. */ |
275f01b2 | 3656 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 3657 | |
937bb610 | 3658 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
3659 | } |
3660 | ||
716c2e55 | 3661 | void intel_put_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3662 | { |
e2b78267 | 3663 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
ee7b9f93 JB |
3664 | |
3665 | if (pll == NULL) | |
3666 | return; | |
3667 | ||
3668 | if (pll->refcount == 0) { | |
46edb027 | 3669 | WARN(1, "bad %s refcount\n", pll->name); |
ee7b9f93 JB |
3670 | return; |
3671 | } | |
3672 | ||
f4a091c7 DV |
3673 | if (--pll->refcount == 0) { |
3674 | WARN_ON(pll->on); | |
3675 | WARN_ON(pll->active); | |
3676 | } | |
3677 | ||
a43f6e0f | 3678 | crtc->config.shared_dpll = DPLL_ID_PRIVATE; |
ee7b9f93 JB |
3679 | } |
3680 | ||
716c2e55 | 3681 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3682 | { |
e2b78267 DV |
3683 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
3684 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
3685 | enum intel_dpll_id i; | |
ee7b9f93 | 3686 | |
ee7b9f93 | 3687 | if (pll) { |
46edb027 DV |
3688 | DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n", |
3689 | crtc->base.base.id, pll->name); | |
e2b78267 | 3690 | intel_put_shared_dpll(crtc); |
ee7b9f93 JB |
3691 | } |
3692 | ||
98b6bd99 DV |
3693 | if (HAS_PCH_IBX(dev_priv->dev)) { |
3694 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 3695 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 3696 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 3697 | |
46edb027 DV |
3698 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
3699 | crtc->base.base.id, pll->name); | |
98b6bd99 | 3700 | |
f2a69f44 DV |
3701 | WARN_ON(pll->refcount); |
3702 | ||
98b6bd99 DV |
3703 | goto found; |
3704 | } | |
3705 | ||
e72f9fbf DV |
3706 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3707 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 JB |
3708 | |
3709 | /* Only want to check enabled timings first */ | |
3710 | if (pll->refcount == 0) | |
3711 | continue; | |
3712 | ||
b89a1d39 DV |
3713 | if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state, |
3714 | sizeof(pll->hw_state)) == 0) { | |
46edb027 | 3715 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n", |
e2b78267 | 3716 | crtc->base.base.id, |
46edb027 | 3717 | pll->name, pll->refcount, pll->active); |
ee7b9f93 JB |
3718 | |
3719 | goto found; | |
3720 | } | |
3721 | } | |
3722 | ||
3723 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
3724 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3725 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 | 3726 | if (pll->refcount == 0) { |
46edb027 DV |
3727 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
3728 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
3729 | goto found; |
3730 | } | |
3731 | } | |
3732 | ||
3733 | return NULL; | |
3734 | ||
3735 | found: | |
f2a69f44 DV |
3736 | if (pll->refcount == 0) |
3737 | pll->hw_state = crtc->config.dpll_hw_state; | |
3738 | ||
a43f6e0f | 3739 | crtc->config.shared_dpll = i; |
46edb027 DV |
3740 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
3741 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 3742 | |
cdbd2316 | 3743 | pll->refcount++; |
e04c7350 | 3744 | |
ee7b9f93 JB |
3745 | return pll; |
3746 | } | |
3747 | ||
a1520318 | 3748 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
3749 | { |
3750 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 3751 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
3752 | u32 temp; |
3753 | ||
3754 | temp = I915_READ(dslreg); | |
3755 | udelay(500); | |
3756 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 3757 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 3758 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
3759 | } |
3760 | } | |
3761 | ||
b074cec8 JB |
3762 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
3763 | { | |
3764 | struct drm_device *dev = crtc->base.dev; | |
3765 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3766 | int pipe = crtc->pipe; | |
3767 | ||
fd4daa9c | 3768 | if (crtc->config.pch_pfit.enabled) { |
b074cec8 JB |
3769 | /* Force use of hard-coded filter coefficients |
3770 | * as some pre-programmed values are broken, | |
3771 | * e.g. x201. | |
3772 | */ | |
3773 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
3774 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
3775 | PF_PIPE_SEL_IVB(pipe)); | |
3776 | else | |
3777 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
3778 | I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos); | |
3779 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size); | |
d4270e57 JB |
3780 | } |
3781 | } | |
3782 | ||
bb53d4ae VS |
3783 | static void intel_enable_planes(struct drm_crtc *crtc) |
3784 | { | |
3785 | struct drm_device *dev = crtc->dev; | |
3786 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 3787 | struct drm_plane *plane; |
bb53d4ae VS |
3788 | struct intel_plane *intel_plane; |
3789 | ||
af2b653b MR |
3790 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
3791 | intel_plane = to_intel_plane(plane); | |
bb53d4ae VS |
3792 | if (intel_plane->pipe == pipe) |
3793 | intel_plane_restore(&intel_plane->base); | |
af2b653b | 3794 | } |
bb53d4ae VS |
3795 | } |
3796 | ||
3797 | static void intel_disable_planes(struct drm_crtc *crtc) | |
3798 | { | |
3799 | struct drm_device *dev = crtc->dev; | |
3800 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 3801 | struct drm_plane *plane; |
bb53d4ae VS |
3802 | struct intel_plane *intel_plane; |
3803 | ||
af2b653b MR |
3804 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
3805 | intel_plane = to_intel_plane(plane); | |
bb53d4ae VS |
3806 | if (intel_plane->pipe == pipe) |
3807 | intel_plane_disable(&intel_plane->base); | |
af2b653b | 3808 | } |
bb53d4ae VS |
3809 | } |
3810 | ||
20bc8673 | 3811 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 3812 | { |
cea165c3 VS |
3813 | struct drm_device *dev = crtc->base.dev; |
3814 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 PZ |
3815 | |
3816 | if (!crtc->config.ips_enabled) | |
3817 | return; | |
3818 | ||
cea165c3 VS |
3819 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
3820 | intel_wait_for_vblank(dev, crtc->pipe); | |
3821 | ||
d77e4531 | 3822 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 3823 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
3824 | mutex_lock(&dev_priv->rps.hw_lock); |
3825 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
3826 | mutex_unlock(&dev_priv->rps.hw_lock); | |
3827 | /* Quoting Art Runyan: "its not safe to expect any particular | |
3828 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
3829 | * mailbox." Moreover, the mailbox may return a bogus state, |
3830 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
3831 | */ |
3832 | } else { | |
3833 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
3834 | /* The bit only becomes 1 in the next vblank, so this wait here | |
3835 | * is essentially intel_wait_for_vblank. If we don't have this | |
3836 | * and don't wait for vblanks until the end of crtc_enable, then | |
3837 | * the HW state readout code will complain that the expected | |
3838 | * IPS_CTL value is not the one we read. */ | |
3839 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
3840 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
3841 | } | |
d77e4531 PZ |
3842 | } |
3843 | ||
20bc8673 | 3844 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
3845 | { |
3846 | struct drm_device *dev = crtc->base.dev; | |
3847 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3848 | ||
3849 | if (!crtc->config.ips_enabled) | |
3850 | return; | |
3851 | ||
3852 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 3853 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
3854 | mutex_lock(&dev_priv->rps.hw_lock); |
3855 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
3856 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
3857 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
3858 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
3859 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 3860 | } else { |
2a114cc1 | 3861 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
3862 | POSTING_READ(IPS_CTL); |
3863 | } | |
d77e4531 PZ |
3864 | |
3865 | /* We need to wait for a vblank before we can disable the plane. */ | |
3866 | intel_wait_for_vblank(dev, crtc->pipe); | |
3867 | } | |
3868 | ||
3869 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
3870 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
3871 | { | |
3872 | struct drm_device *dev = crtc->dev; | |
3873 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3874 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3875 | enum pipe pipe = intel_crtc->pipe; | |
3876 | int palreg = PALETTE(pipe); | |
3877 | int i; | |
3878 | bool reenable_ips = false; | |
3879 | ||
3880 | /* The clocks have to be on to load the palette. */ | |
3881 | if (!crtc->enabled || !intel_crtc->active) | |
3882 | return; | |
3883 | ||
3884 | if (!HAS_PCH_SPLIT(dev_priv->dev)) { | |
3885 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) | |
3886 | assert_dsi_pll_enabled(dev_priv); | |
3887 | else | |
3888 | assert_pll_enabled(dev_priv, pipe); | |
3889 | } | |
3890 | ||
3891 | /* use legacy palette for Ironlake */ | |
7a1db49a | 3892 | if (!HAS_GMCH_DISPLAY(dev)) |
d77e4531 PZ |
3893 | palreg = LGC_PALETTE(pipe); |
3894 | ||
3895 | /* Workaround : Do not read or write the pipe palette/gamma data while | |
3896 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
3897 | */ | |
41e6fc4c | 3898 | if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled && |
d77e4531 PZ |
3899 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
3900 | GAMMA_MODE_MODE_SPLIT)) { | |
3901 | hsw_disable_ips(intel_crtc); | |
3902 | reenable_ips = true; | |
3903 | } | |
3904 | ||
3905 | for (i = 0; i < 256; i++) { | |
3906 | I915_WRITE(palreg + 4 * i, | |
3907 | (intel_crtc->lut_r[i] << 16) | | |
3908 | (intel_crtc->lut_g[i] << 8) | | |
3909 | intel_crtc->lut_b[i]); | |
3910 | } | |
3911 | ||
3912 | if (reenable_ips) | |
3913 | hsw_enable_ips(intel_crtc); | |
3914 | } | |
3915 | ||
d3eedb1a VS |
3916 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
3917 | { | |
3918 | if (!enable && intel_crtc->overlay) { | |
3919 | struct drm_device *dev = intel_crtc->base.dev; | |
3920 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3921 | ||
3922 | mutex_lock(&dev->struct_mutex); | |
3923 | dev_priv->mm.interruptible = false; | |
3924 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
3925 | dev_priv->mm.interruptible = true; | |
3926 | mutex_unlock(&dev->struct_mutex); | |
3927 | } | |
3928 | ||
3929 | /* Let userspace switch the overlay on again. In most cases userspace | |
3930 | * has to recompute where to put it anyway. | |
3931 | */ | |
3932 | } | |
3933 | ||
d3eedb1a | 3934 | static void intel_crtc_enable_planes(struct drm_crtc *crtc) |
a5c4d7bc VS |
3935 | { |
3936 | struct drm_device *dev = crtc->dev; | |
a5c4d7bc VS |
3937 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3938 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 3939 | |
f98551ae VS |
3940 | drm_vblank_on(dev, pipe); |
3941 | ||
fdd508a6 | 3942 | intel_enable_primary_hw_plane(crtc->primary, crtc); |
a5c4d7bc VS |
3943 | intel_enable_planes(crtc); |
3944 | intel_crtc_update_cursor(crtc, true); | |
d3eedb1a | 3945 | intel_crtc_dpms_overlay(intel_crtc, true); |
a5c4d7bc VS |
3946 | |
3947 | hsw_enable_ips(intel_crtc); | |
3948 | ||
3949 | mutex_lock(&dev->struct_mutex); | |
3950 | intel_update_fbc(dev); | |
3951 | mutex_unlock(&dev->struct_mutex); | |
f99d7069 DV |
3952 | |
3953 | /* | |
3954 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
3955 | * to compute the mask of flip planes precisely. For the time being | |
3956 | * consider this a flip from a NULL plane. | |
3957 | */ | |
3958 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
3959 | } |
3960 | ||
d3eedb1a | 3961 | static void intel_crtc_disable_planes(struct drm_crtc *crtc) |
a5c4d7bc VS |
3962 | { |
3963 | struct drm_device *dev = crtc->dev; | |
3964 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3965 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3966 | int pipe = intel_crtc->pipe; | |
3967 | int plane = intel_crtc->plane; | |
3968 | ||
3969 | intel_crtc_wait_for_pending_flips(crtc); | |
a5c4d7bc VS |
3970 | |
3971 | if (dev_priv->fbc.plane == plane) | |
3972 | intel_disable_fbc(dev); | |
3973 | ||
3974 | hsw_disable_ips(intel_crtc); | |
3975 | ||
d3eedb1a | 3976 | intel_crtc_dpms_overlay(intel_crtc, false); |
a5c4d7bc VS |
3977 | intel_crtc_update_cursor(crtc, false); |
3978 | intel_disable_planes(crtc); | |
fdd508a6 | 3979 | intel_disable_primary_hw_plane(crtc->primary, crtc); |
f98551ae | 3980 | |
f99d7069 DV |
3981 | /* |
3982 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
3983 | * to compute the mask of flip planes precisely. For the time being | |
3984 | * consider this a flip to a NULL plane. | |
3985 | */ | |
3986 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
3987 | ||
f98551ae | 3988 | drm_vblank_off(dev, pipe); |
a5c4d7bc VS |
3989 | } |
3990 | ||
f67a559d JB |
3991 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
3992 | { | |
3993 | struct drm_device *dev = crtc->dev; | |
3994 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3995 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3996 | struct intel_encoder *encoder; |
f67a559d | 3997 | int pipe = intel_crtc->pipe; |
f67a559d | 3998 | |
08a48469 DV |
3999 | WARN_ON(!crtc->enabled); |
4000 | ||
f67a559d JB |
4001 | if (intel_crtc->active) |
4002 | return; | |
4003 | ||
b14b1055 DV |
4004 | if (intel_crtc->config.has_pch_encoder) |
4005 | intel_prepare_shared_dpll(intel_crtc); | |
4006 | ||
29407aab DV |
4007 | if (intel_crtc->config.has_dp_encoder) |
4008 | intel_dp_set_m_n(intel_crtc); | |
4009 | ||
4010 | intel_set_pipe_timings(intel_crtc); | |
4011 | ||
4012 | if (intel_crtc->config.has_pch_encoder) { | |
4013 | intel_cpu_transcoder_set_m_n(intel_crtc, | |
f769cd24 | 4014 | &intel_crtc->config.fdi_m_n, NULL); |
29407aab DV |
4015 | } |
4016 | ||
4017 | ironlake_set_pipeconf(crtc); | |
4018 | ||
f67a559d | 4019 | intel_crtc->active = true; |
8664281b PZ |
4020 | |
4021 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
4022 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); | |
4023 | ||
f6736a1a | 4024 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4025 | if (encoder->pre_enable) |
4026 | encoder->pre_enable(encoder); | |
f67a559d | 4027 | |
5bfe2ac0 | 4028 | if (intel_crtc->config.has_pch_encoder) { |
fff367c7 DV |
4029 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4030 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4031 | * enabling. */ | |
88cefb6c | 4032 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4033 | } else { |
4034 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4035 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4036 | } | |
f67a559d | 4037 | |
b074cec8 | 4038 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4039 | |
9c54c0dd JB |
4040 | /* |
4041 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4042 | * clocks enabled | |
4043 | */ | |
4044 | intel_crtc_load_lut(crtc); | |
4045 | ||
f37fcc2a | 4046 | intel_update_watermarks(crtc); |
e1fdc473 | 4047 | intel_enable_pipe(intel_crtc); |
f67a559d | 4048 | |
5bfe2ac0 | 4049 | if (intel_crtc->config.has_pch_encoder) |
f67a559d | 4050 | ironlake_pch_enable(crtc); |
c98e9dcf | 4051 | |
fa5c73b1 DV |
4052 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4053 | encoder->enable(encoder); | |
61b77ddd DV |
4054 | |
4055 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4056 | cpt_verify_modeset(dev, intel_crtc->pipe); |
6ce94100 | 4057 | |
d3eedb1a | 4058 | intel_crtc_enable_planes(crtc); |
6be4a607 JB |
4059 | } |
4060 | ||
42db64ef PZ |
4061 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4062 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4063 | { | |
f5adf94e | 4064 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4065 | } |
4066 | ||
e4916946 PZ |
4067 | /* |
4068 | * This implements the workaround described in the "notes" section of the mode | |
4069 | * set sequence documentation. When going from no pipes or single pipe to | |
4070 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
4071 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
4072 | */ | |
4073 | static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) | |
4074 | { | |
4075 | struct drm_device *dev = crtc->base.dev; | |
4076 | struct intel_crtc *crtc_it, *other_active_crtc = NULL; | |
4077 | ||
4078 | /* We want to get the other_active_crtc only if there's only 1 other | |
4079 | * active crtc. */ | |
d3fcc808 | 4080 | for_each_intel_crtc(dev, crtc_it) { |
e4916946 PZ |
4081 | if (!crtc_it->active || crtc_it == crtc) |
4082 | continue; | |
4083 | ||
4084 | if (other_active_crtc) | |
4085 | return; | |
4086 | ||
4087 | other_active_crtc = crtc_it; | |
4088 | } | |
4089 | if (!other_active_crtc) | |
4090 | return; | |
4091 | ||
4092 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4093 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4094 | } | |
4095 | ||
4f771f10 PZ |
4096 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4097 | { | |
4098 | struct drm_device *dev = crtc->dev; | |
4099 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4100 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4101 | struct intel_encoder *encoder; | |
4102 | int pipe = intel_crtc->pipe; | |
4f771f10 PZ |
4103 | |
4104 | WARN_ON(!crtc->enabled); | |
4105 | ||
4106 | if (intel_crtc->active) | |
4107 | return; | |
4108 | ||
df8ad70c DV |
4109 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
4110 | intel_enable_shared_dpll(intel_crtc); | |
4111 | ||
229fca97 DV |
4112 | if (intel_crtc->config.has_dp_encoder) |
4113 | intel_dp_set_m_n(intel_crtc); | |
4114 | ||
4115 | intel_set_pipe_timings(intel_crtc); | |
4116 | ||
4117 | if (intel_crtc->config.has_pch_encoder) { | |
4118 | intel_cpu_transcoder_set_m_n(intel_crtc, | |
f769cd24 | 4119 | &intel_crtc->config.fdi_m_n, NULL); |
229fca97 DV |
4120 | } |
4121 | ||
4122 | haswell_set_pipeconf(crtc); | |
4123 | ||
4124 | intel_set_pipe_csc(crtc); | |
4125 | ||
4f771f10 | 4126 | intel_crtc->active = true; |
8664281b PZ |
4127 | |
4128 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
4f771f10 PZ |
4129 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4130 | if (encoder->pre_enable) | |
4131 | encoder->pre_enable(encoder); | |
4132 | ||
4fe9467d ID |
4133 | if (intel_crtc->config.has_pch_encoder) { |
4134 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); | |
4135 | dev_priv->display.fdi_link_train(crtc); | |
4136 | } | |
4137 | ||
1f544388 | 4138 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 4139 | |
b074cec8 | 4140 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
4141 | |
4142 | /* | |
4143 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4144 | * clocks enabled | |
4145 | */ | |
4146 | intel_crtc_load_lut(crtc); | |
4147 | ||
1f544388 | 4148 | intel_ddi_set_pipe_settings(crtc); |
8228c251 | 4149 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 4150 | |
f37fcc2a | 4151 | intel_update_watermarks(crtc); |
e1fdc473 | 4152 | intel_enable_pipe(intel_crtc); |
42db64ef | 4153 | |
5bfe2ac0 | 4154 | if (intel_crtc->config.has_pch_encoder) |
1507e5bd | 4155 | lpt_pch_enable(crtc); |
4f771f10 | 4156 | |
0e32b39c DA |
4157 | if (intel_crtc->config.dp_encoder_is_mst) |
4158 | intel_ddi_set_vc_payload_alloc(crtc, true); | |
4159 | ||
8807e55b | 4160 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 4161 | encoder->enable(encoder); |
8807e55b JN |
4162 | intel_opregion_notify_encoder(encoder, true); |
4163 | } | |
4f771f10 | 4164 | |
e4916946 PZ |
4165 | /* If we change the relative order between pipe/planes enabling, we need |
4166 | * to change the workaround. */ | |
4167 | haswell_mode_set_planes_workaround(intel_crtc); | |
d3eedb1a | 4168 | intel_crtc_enable_planes(crtc); |
4f771f10 PZ |
4169 | } |
4170 | ||
3f8dce3a DV |
4171 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
4172 | { | |
4173 | struct drm_device *dev = crtc->base.dev; | |
4174 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4175 | int pipe = crtc->pipe; | |
4176 | ||
4177 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
4178 | * it's in use. The hw state code will make sure we get this right. */ | |
fd4daa9c | 4179 | if (crtc->config.pch_pfit.enabled) { |
3f8dce3a DV |
4180 | I915_WRITE(PF_CTL(pipe), 0); |
4181 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
4182 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
4183 | } | |
4184 | } | |
4185 | ||
6be4a607 JB |
4186 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
4187 | { | |
4188 | struct drm_device *dev = crtc->dev; | |
4189 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4190 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4191 | struct intel_encoder *encoder; |
6be4a607 | 4192 | int pipe = intel_crtc->pipe; |
5eddb70b | 4193 | u32 reg, temp; |
b52eb4dc | 4194 | |
f7abfe8b CW |
4195 | if (!intel_crtc->active) |
4196 | return; | |
4197 | ||
d3eedb1a | 4198 | intel_crtc_disable_planes(crtc); |
a5c4d7bc | 4199 | |
ea9d758d DV |
4200 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4201 | encoder->disable(encoder); | |
4202 | ||
d925c59a DV |
4203 | if (intel_crtc->config.has_pch_encoder) |
4204 | intel_set_pch_fifo_underrun_reporting(dev, pipe, false); | |
4205 | ||
b24e7179 | 4206 | intel_disable_pipe(dev_priv, pipe); |
32f9d658 | 4207 | |
0e32b39c DA |
4208 | if (intel_crtc->config.dp_encoder_is_mst) |
4209 | intel_ddi_set_vc_payload_alloc(crtc, false); | |
4210 | ||
3f8dce3a | 4211 | ironlake_pfit_disable(intel_crtc); |
2c07245f | 4212 | |
bf49ec8c DV |
4213 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4214 | if (encoder->post_disable) | |
4215 | encoder->post_disable(encoder); | |
2c07245f | 4216 | |
d925c59a DV |
4217 | if (intel_crtc->config.has_pch_encoder) { |
4218 | ironlake_fdi_disable(crtc); | |
913d8d11 | 4219 | |
d925c59a DV |
4220 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
4221 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); | |
6be4a607 | 4222 | |
d925c59a DV |
4223 | if (HAS_PCH_CPT(dev)) { |
4224 | /* disable TRANS_DP_CTL */ | |
4225 | reg = TRANS_DP_CTL(pipe); | |
4226 | temp = I915_READ(reg); | |
4227 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
4228 | TRANS_DP_PORT_SEL_MASK); | |
4229 | temp |= TRANS_DP_PORT_SEL_NONE; | |
4230 | I915_WRITE(reg, temp); | |
4231 | ||
4232 | /* disable DPLL_SEL */ | |
4233 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 4234 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 4235 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 4236 | } |
e3421a18 | 4237 | |
d925c59a | 4238 | /* disable PCH DPLL */ |
e72f9fbf | 4239 | intel_disable_shared_dpll(intel_crtc); |
8db9d77b | 4240 | |
d925c59a DV |
4241 | ironlake_fdi_pll_disable(intel_crtc); |
4242 | } | |
6b383a7f | 4243 | |
f7abfe8b | 4244 | intel_crtc->active = false; |
46ba614c | 4245 | intel_update_watermarks(crtc); |
d1ebd816 BW |
4246 | |
4247 | mutex_lock(&dev->struct_mutex); | |
6b383a7f | 4248 | intel_update_fbc(dev); |
d1ebd816 | 4249 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 4250 | } |
1b3c7a47 | 4251 | |
4f771f10 | 4252 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 4253 | { |
4f771f10 PZ |
4254 | struct drm_device *dev = crtc->dev; |
4255 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 4256 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 PZ |
4257 | struct intel_encoder *encoder; |
4258 | int pipe = intel_crtc->pipe; | |
3b117c8f | 4259 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee7b9f93 | 4260 | |
4f771f10 PZ |
4261 | if (!intel_crtc->active) |
4262 | return; | |
4263 | ||
d3eedb1a | 4264 | intel_crtc_disable_planes(crtc); |
dda9a66a | 4265 | |
8807e55b JN |
4266 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4267 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 4268 | encoder->disable(encoder); |
8807e55b | 4269 | } |
4f771f10 | 4270 | |
8664281b PZ |
4271 | if (intel_crtc->config.has_pch_encoder) |
4272 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false); | |
4f771f10 PZ |
4273 | intel_disable_pipe(dev_priv, pipe); |
4274 | ||
ad80a810 | 4275 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 4276 | |
3f8dce3a | 4277 | ironlake_pfit_disable(intel_crtc); |
4f771f10 | 4278 | |
1f544388 | 4279 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 4280 | |
88adfff1 | 4281 | if (intel_crtc->config.has_pch_encoder) { |
ab4d966c | 4282 | lpt_disable_pch_transcoder(dev_priv); |
8664281b | 4283 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
1ad960f2 | 4284 | intel_ddi_fdi_disable(crtc); |
83616634 | 4285 | } |
4f771f10 | 4286 | |
97b040aa ID |
4287 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4288 | if (encoder->post_disable) | |
4289 | encoder->post_disable(encoder); | |
4290 | ||
4f771f10 | 4291 | intel_crtc->active = false; |
46ba614c | 4292 | intel_update_watermarks(crtc); |
4f771f10 PZ |
4293 | |
4294 | mutex_lock(&dev->struct_mutex); | |
4295 | intel_update_fbc(dev); | |
4296 | mutex_unlock(&dev->struct_mutex); | |
df8ad70c DV |
4297 | |
4298 | if (intel_crtc_to_shared_dpll(intel_crtc)) | |
4299 | intel_disable_shared_dpll(intel_crtc); | |
4f771f10 PZ |
4300 | } |
4301 | ||
ee7b9f93 JB |
4302 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
4303 | { | |
4304 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e72f9fbf | 4305 | intel_put_shared_dpll(intel_crtc); |
ee7b9f93 JB |
4306 | } |
4307 | ||
6441ab5f | 4308 | |
2dd24552 JB |
4309 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
4310 | { | |
4311 | struct drm_device *dev = crtc->base.dev; | |
4312 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4313 | struct intel_crtc_config *pipe_config = &crtc->config; | |
4314 | ||
328d8e82 | 4315 | if (!crtc->config.gmch_pfit.control) |
2dd24552 JB |
4316 | return; |
4317 | ||
2dd24552 | 4318 | /* |
c0b03411 DV |
4319 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
4320 | * according to register description and PRM. | |
2dd24552 | 4321 | */ |
c0b03411 DV |
4322 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
4323 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 4324 | |
b074cec8 JB |
4325 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
4326 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
4327 | |
4328 | /* Border color in case we don't scale up to the full screen. Black by | |
4329 | * default, change to something else for debugging. */ | |
4330 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
4331 | } |
4332 | ||
d05410f9 DA |
4333 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
4334 | { | |
4335 | switch (port) { | |
4336 | case PORT_A: | |
4337 | return POWER_DOMAIN_PORT_DDI_A_4_LANES; | |
4338 | case PORT_B: | |
4339 | return POWER_DOMAIN_PORT_DDI_B_4_LANES; | |
4340 | case PORT_C: | |
4341 | return POWER_DOMAIN_PORT_DDI_C_4_LANES; | |
4342 | case PORT_D: | |
4343 | return POWER_DOMAIN_PORT_DDI_D_4_LANES; | |
4344 | default: | |
4345 | WARN_ON_ONCE(1); | |
4346 | return POWER_DOMAIN_PORT_OTHER; | |
4347 | } | |
4348 | } | |
4349 | ||
77d22dca ID |
4350 | #define for_each_power_domain(domain, mask) \ |
4351 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
4352 | if ((1 << (domain)) & (mask)) | |
4353 | ||
319be8ae ID |
4354 | enum intel_display_power_domain |
4355 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
4356 | { | |
4357 | struct drm_device *dev = intel_encoder->base.dev; | |
4358 | struct intel_digital_port *intel_dig_port; | |
4359 | ||
4360 | switch (intel_encoder->type) { | |
4361 | case INTEL_OUTPUT_UNKNOWN: | |
4362 | /* Only DDI platforms should ever use this output type */ | |
4363 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
4364 | case INTEL_OUTPUT_DISPLAYPORT: | |
4365 | case INTEL_OUTPUT_HDMI: | |
4366 | case INTEL_OUTPUT_EDP: | |
4367 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 4368 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
4369 | case INTEL_OUTPUT_DP_MST: |
4370 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
4371 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
4372 | case INTEL_OUTPUT_ANALOG: |
4373 | return POWER_DOMAIN_PORT_CRT; | |
4374 | case INTEL_OUTPUT_DSI: | |
4375 | return POWER_DOMAIN_PORT_DSI; | |
4376 | default: | |
4377 | return POWER_DOMAIN_PORT_OTHER; | |
4378 | } | |
4379 | } | |
4380 | ||
4381 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) | |
77d22dca | 4382 | { |
319be8ae ID |
4383 | struct drm_device *dev = crtc->dev; |
4384 | struct intel_encoder *intel_encoder; | |
4385 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4386 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca ID |
4387 | unsigned long mask; |
4388 | enum transcoder transcoder; | |
4389 | ||
4390 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); | |
4391 | ||
4392 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); | |
4393 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
fabf6e51 DV |
4394 | if (intel_crtc->config.pch_pfit.enabled || |
4395 | intel_crtc->config.pch_pfit.force_thru) | |
77d22dca ID |
4396 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
4397 | ||
319be8ae ID |
4398 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
4399 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); | |
4400 | ||
77d22dca ID |
4401 | return mask; |
4402 | } | |
4403 | ||
4404 | void intel_display_set_init_power(struct drm_i915_private *dev_priv, | |
4405 | bool enable) | |
4406 | { | |
4407 | if (dev_priv->power_domains.init_power_on == enable) | |
4408 | return; | |
4409 | ||
4410 | if (enable) | |
4411 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); | |
4412 | else | |
4413 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); | |
4414 | ||
4415 | dev_priv->power_domains.init_power_on = enable; | |
4416 | } | |
4417 | ||
4418 | static void modeset_update_crtc_power_domains(struct drm_device *dev) | |
4419 | { | |
4420 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4421 | unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; | |
4422 | struct intel_crtc *crtc; | |
4423 | ||
4424 | /* | |
4425 | * First get all needed power domains, then put all unneeded, to avoid | |
4426 | * any unnecessary toggling of the power wells. | |
4427 | */ | |
d3fcc808 | 4428 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
4429 | enum intel_display_power_domain domain; |
4430 | ||
4431 | if (!crtc->base.enabled) | |
4432 | continue; | |
4433 | ||
319be8ae | 4434 | pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base); |
77d22dca ID |
4435 | |
4436 | for_each_power_domain(domain, pipe_domains[crtc->pipe]) | |
4437 | intel_display_power_get(dev_priv, domain); | |
4438 | } | |
4439 | ||
d3fcc808 | 4440 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
4441 | enum intel_display_power_domain domain; |
4442 | ||
4443 | for_each_power_domain(domain, crtc->enabled_power_domains) | |
4444 | intel_display_power_put(dev_priv, domain); | |
4445 | ||
4446 | crtc->enabled_power_domains = pipe_domains[crtc->pipe]; | |
4447 | } | |
4448 | ||
4449 | intel_display_set_init_power(dev_priv, false); | |
4450 | } | |
4451 | ||
dfcab17e | 4452 | /* returns HPLL frequency in kHz */ |
f8bf63fd | 4453 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) |
30a970c6 | 4454 | { |
586f49dc | 4455 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
30a970c6 | 4456 | |
586f49dc JB |
4457 | /* Obtain SKU information */ |
4458 | mutex_lock(&dev_priv->dpio_lock); | |
4459 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
4460 | CCK_FUSE_HPLL_FREQ_MASK; | |
4461 | mutex_unlock(&dev_priv->dpio_lock); | |
30a970c6 | 4462 | |
dfcab17e | 4463 | return vco_freq[hpll_freq] * 1000; |
30a970c6 JB |
4464 | } |
4465 | ||
f8bf63fd VS |
4466 | static void vlv_update_cdclk(struct drm_device *dev) |
4467 | { | |
4468 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4469 | ||
4470 | dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
4471 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz", | |
4472 | dev_priv->vlv_cdclk_freq); | |
4473 | ||
4474 | /* | |
4475 | * Program the gmbus_freq based on the cdclk frequency. | |
4476 | * BSpec erroneously claims we should aim for 4MHz, but | |
4477 | * in fact 1MHz is the correct frequency. | |
4478 | */ | |
4479 | I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq); | |
4480 | } | |
4481 | ||
30a970c6 JB |
4482 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
4483 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
4484 | { | |
4485 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4486 | u32 val, cmd; | |
4487 | ||
d197b7d3 | 4488 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq); |
d60c4473 | 4489 | |
dfcab17e | 4490 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 4491 | cmd = 2; |
dfcab17e | 4492 | else if (cdclk == 266667) |
30a970c6 JB |
4493 | cmd = 1; |
4494 | else | |
4495 | cmd = 0; | |
4496 | ||
4497 | mutex_lock(&dev_priv->rps.hw_lock); | |
4498 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
4499 | val &= ~DSPFREQGUAR_MASK; | |
4500 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
4501 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
4502 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
4503 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
4504 | 50)) { | |
4505 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
4506 | } | |
4507 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4508 | ||
dfcab17e | 4509 | if (cdclk == 400000) { |
30a970c6 JB |
4510 | u32 divider, vco; |
4511 | ||
4512 | vco = valleyview_get_vco(dev_priv); | |
dfcab17e | 4513 | divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1; |
30a970c6 JB |
4514 | |
4515 | mutex_lock(&dev_priv->dpio_lock); | |
4516 | /* adjust cdclk divider */ | |
4517 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
9cf33db5 | 4518 | val &= ~DISPLAY_FREQUENCY_VALUES; |
30a970c6 JB |
4519 | val |= divider; |
4520 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
4521 | |
4522 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
4523 | DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
4524 | 50)) | |
4525 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
4526 | mutex_unlock(&dev_priv->dpio_lock); |
4527 | } | |
4528 | ||
4529 | mutex_lock(&dev_priv->dpio_lock); | |
4530 | /* adjust self-refresh exit latency value */ | |
4531 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
4532 | val &= ~0x7f; | |
4533 | ||
4534 | /* | |
4535 | * For high bandwidth configs, we set a higher latency in the bunit | |
4536 | * so that the core display fetch happens in time to avoid underruns. | |
4537 | */ | |
dfcab17e | 4538 | if (cdclk == 400000) |
30a970c6 JB |
4539 | val |= 4500 / 250; /* 4.5 usec */ |
4540 | else | |
4541 | val |= 3000 / 250; /* 3.0 usec */ | |
4542 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
4543 | mutex_unlock(&dev_priv->dpio_lock); | |
4544 | ||
f8bf63fd | 4545 | vlv_update_cdclk(dev); |
30a970c6 JB |
4546 | } |
4547 | ||
383c5a6a VS |
4548 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
4549 | { | |
4550 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4551 | u32 val, cmd; | |
4552 | ||
4553 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq); | |
4554 | ||
4555 | switch (cdclk) { | |
4556 | case 400000: | |
4557 | cmd = 3; | |
4558 | break; | |
4559 | case 333333: | |
4560 | case 320000: | |
4561 | cmd = 2; | |
4562 | break; | |
4563 | case 266667: | |
4564 | cmd = 1; | |
4565 | break; | |
4566 | case 200000: | |
4567 | cmd = 0; | |
4568 | break; | |
4569 | default: | |
4570 | WARN_ON(1); | |
4571 | return; | |
4572 | } | |
4573 | ||
4574 | mutex_lock(&dev_priv->rps.hw_lock); | |
4575 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
4576 | val &= ~DSPFREQGUAR_MASK_CHV; | |
4577 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
4578 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
4579 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
4580 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
4581 | 50)) { | |
4582 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
4583 | } | |
4584 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4585 | ||
4586 | vlv_update_cdclk(dev); | |
4587 | } | |
4588 | ||
30a970c6 JB |
4589 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
4590 | int max_pixclk) | |
4591 | { | |
29dc7ef3 VS |
4592 | int vco = valleyview_get_vco(dev_priv); |
4593 | int freq_320 = (vco << 1) % 320000 != 0 ? 333333 : 320000; | |
4594 | ||
d49a340d VS |
4595 | /* FIXME: Punit isn't quite ready yet */ |
4596 | if (IS_CHERRYVIEW(dev_priv->dev)) | |
4597 | return 400000; | |
4598 | ||
30a970c6 JB |
4599 | /* |
4600 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
4601 | * 200MHz | |
4602 | * 267MHz | |
29dc7ef3 | 4603 | * 320/333MHz (depends on HPLL freq) |
30a970c6 JB |
4604 | * 400MHz |
4605 | * So we check to see whether we're above 90% of the lower bin and | |
4606 | * adjust if needed. | |
e37c67a1 VS |
4607 | * |
4608 | * We seem to get an unstable or solid color picture at 200MHz. | |
4609 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
4610 | * are off. | |
30a970c6 | 4611 | */ |
29dc7ef3 | 4612 | if (max_pixclk > freq_320*9/10) |
dfcab17e VS |
4613 | return 400000; |
4614 | else if (max_pixclk > 266667*9/10) | |
29dc7ef3 | 4615 | return freq_320; |
e37c67a1 | 4616 | else if (max_pixclk > 0) |
dfcab17e | 4617 | return 266667; |
e37c67a1 VS |
4618 | else |
4619 | return 200000; | |
30a970c6 JB |
4620 | } |
4621 | ||
2f2d7aa1 VS |
4622 | /* compute the max pixel clock for new configuration */ |
4623 | static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv) | |
30a970c6 JB |
4624 | { |
4625 | struct drm_device *dev = dev_priv->dev; | |
4626 | struct intel_crtc *intel_crtc; | |
4627 | int max_pixclk = 0; | |
4628 | ||
d3fcc808 | 4629 | for_each_intel_crtc(dev, intel_crtc) { |
2f2d7aa1 | 4630 | if (intel_crtc->new_enabled) |
30a970c6 | 4631 | max_pixclk = max(max_pixclk, |
2f2d7aa1 | 4632 | intel_crtc->new_config->adjusted_mode.crtc_clock); |
30a970c6 JB |
4633 | } |
4634 | ||
4635 | return max_pixclk; | |
4636 | } | |
4637 | ||
4638 | static void valleyview_modeset_global_pipes(struct drm_device *dev, | |
2f2d7aa1 | 4639 | unsigned *prepare_pipes) |
30a970c6 JB |
4640 | { |
4641 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4642 | struct intel_crtc *intel_crtc; | |
2f2d7aa1 | 4643 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
30a970c6 | 4644 | |
d60c4473 ID |
4645 | if (valleyview_calc_cdclk(dev_priv, max_pixclk) == |
4646 | dev_priv->vlv_cdclk_freq) | |
30a970c6 JB |
4647 | return; |
4648 | ||
2f2d7aa1 | 4649 | /* disable/enable all currently active pipes while we change cdclk */ |
d3fcc808 | 4650 | for_each_intel_crtc(dev, intel_crtc) |
30a970c6 JB |
4651 | if (intel_crtc->base.enabled) |
4652 | *prepare_pipes |= (1 << intel_crtc->pipe); | |
4653 | } | |
4654 | ||
4655 | static void valleyview_modeset_global_resources(struct drm_device *dev) | |
4656 | { | |
4657 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2f2d7aa1 | 4658 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
30a970c6 JB |
4659 | int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); |
4660 | ||
383c5a6a VS |
4661 | if (req_cdclk != dev_priv->vlv_cdclk_freq) { |
4662 | if (IS_CHERRYVIEW(dev)) | |
4663 | cherryview_set_cdclk(dev, req_cdclk); | |
4664 | else | |
4665 | valleyview_set_cdclk(dev, req_cdclk); | |
4666 | } | |
4667 | ||
77961eb9 | 4668 | modeset_update_crtc_power_domains(dev); |
30a970c6 JB |
4669 | } |
4670 | ||
89b667f8 JB |
4671 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
4672 | { | |
4673 | struct drm_device *dev = crtc->dev; | |
89b667f8 JB |
4674 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4675 | struct intel_encoder *encoder; | |
4676 | int pipe = intel_crtc->pipe; | |
23538ef1 | 4677 | bool is_dsi; |
89b667f8 JB |
4678 | |
4679 | WARN_ON(!crtc->enabled); | |
4680 | ||
4681 | if (intel_crtc->active) | |
4682 | return; | |
4683 | ||
8525a235 SK |
4684 | is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI); |
4685 | ||
1ae0d137 VS |
4686 | if (!is_dsi) { |
4687 | if (IS_CHERRYVIEW(dev)) | |
4688 | chv_prepare_pll(intel_crtc); | |
4689 | else | |
4690 | vlv_prepare_pll(intel_crtc); | |
4691 | } | |
bdd4b6a6 | 4692 | |
5b18e57c DV |
4693 | if (intel_crtc->config.has_dp_encoder) |
4694 | intel_dp_set_m_n(intel_crtc); | |
4695 | ||
4696 | intel_set_pipe_timings(intel_crtc); | |
4697 | ||
5b18e57c DV |
4698 | i9xx_set_pipeconf(intel_crtc); |
4699 | ||
89b667f8 | 4700 | intel_crtc->active = true; |
89b667f8 | 4701 | |
4a3436e8 VS |
4702 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
4703 | ||
89b667f8 JB |
4704 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4705 | if (encoder->pre_pll_enable) | |
4706 | encoder->pre_pll_enable(encoder); | |
4707 | ||
9d556c99 CML |
4708 | if (!is_dsi) { |
4709 | if (IS_CHERRYVIEW(dev)) | |
4710 | chv_enable_pll(intel_crtc); | |
4711 | else | |
4712 | vlv_enable_pll(intel_crtc); | |
4713 | } | |
89b667f8 JB |
4714 | |
4715 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
4716 | if (encoder->pre_enable) | |
4717 | encoder->pre_enable(encoder); | |
4718 | ||
2dd24552 JB |
4719 | i9xx_pfit_enable(intel_crtc); |
4720 | ||
63cbb074 VS |
4721 | intel_crtc_load_lut(crtc); |
4722 | ||
f37fcc2a | 4723 | intel_update_watermarks(crtc); |
e1fdc473 | 4724 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 4725 | |
5004945f JN |
4726 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4727 | encoder->enable(encoder); | |
9ab0460b VS |
4728 | |
4729 | intel_crtc_enable_planes(crtc); | |
d40d9187 | 4730 | |
56b80e1f VS |
4731 | /* Underruns don't raise interrupts, so check manually. */ |
4732 | i9xx_check_fifo_underruns(dev); | |
89b667f8 JB |
4733 | } |
4734 | ||
f13c2ef3 DV |
4735 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
4736 | { | |
4737 | struct drm_device *dev = crtc->base.dev; | |
4738 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4739 | ||
4740 | I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0); | |
4741 | I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1); | |
4742 | } | |
4743 | ||
0b8765c6 | 4744 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
4745 | { |
4746 | struct drm_device *dev = crtc->dev; | |
79e53945 | 4747 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 4748 | struct intel_encoder *encoder; |
79e53945 | 4749 | int pipe = intel_crtc->pipe; |
79e53945 | 4750 | |
08a48469 DV |
4751 | WARN_ON(!crtc->enabled); |
4752 | ||
f7abfe8b CW |
4753 | if (intel_crtc->active) |
4754 | return; | |
4755 | ||
f13c2ef3 DV |
4756 | i9xx_set_pll_dividers(intel_crtc); |
4757 | ||
5b18e57c DV |
4758 | if (intel_crtc->config.has_dp_encoder) |
4759 | intel_dp_set_m_n(intel_crtc); | |
4760 | ||
4761 | intel_set_pipe_timings(intel_crtc); | |
4762 | ||
5b18e57c DV |
4763 | i9xx_set_pipeconf(intel_crtc); |
4764 | ||
f7abfe8b | 4765 | intel_crtc->active = true; |
6b383a7f | 4766 | |
4a3436e8 VS |
4767 | if (!IS_GEN2(dev)) |
4768 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
4769 | ||
9d6d9f19 MK |
4770 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4771 | if (encoder->pre_enable) | |
4772 | encoder->pre_enable(encoder); | |
4773 | ||
f6736a1a DV |
4774 | i9xx_enable_pll(intel_crtc); |
4775 | ||
2dd24552 JB |
4776 | i9xx_pfit_enable(intel_crtc); |
4777 | ||
63cbb074 VS |
4778 | intel_crtc_load_lut(crtc); |
4779 | ||
f37fcc2a | 4780 | intel_update_watermarks(crtc); |
e1fdc473 | 4781 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 4782 | |
fa5c73b1 DV |
4783 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4784 | encoder->enable(encoder); | |
9ab0460b VS |
4785 | |
4786 | intel_crtc_enable_planes(crtc); | |
d40d9187 | 4787 | |
4a3436e8 VS |
4788 | /* |
4789 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4790 | * So don't enable underrun reporting before at least some planes | |
4791 | * are enabled. | |
4792 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4793 | * but leave the pipe running. | |
4794 | */ | |
4795 | if (IS_GEN2(dev)) | |
4796 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
4797 | ||
56b80e1f VS |
4798 | /* Underruns don't raise interrupts, so check manually. */ |
4799 | i9xx_check_fifo_underruns(dev); | |
0b8765c6 | 4800 | } |
79e53945 | 4801 | |
87476d63 DV |
4802 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
4803 | { | |
4804 | struct drm_device *dev = crtc->base.dev; | |
4805 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 4806 | |
328d8e82 DV |
4807 | if (!crtc->config.gmch_pfit.control) |
4808 | return; | |
87476d63 | 4809 | |
328d8e82 | 4810 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 4811 | |
328d8e82 DV |
4812 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
4813 | I915_READ(PFIT_CONTROL)); | |
4814 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
4815 | } |
4816 | ||
0b8765c6 JB |
4817 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
4818 | { | |
4819 | struct drm_device *dev = crtc->dev; | |
4820 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4821 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4822 | struct intel_encoder *encoder; |
0b8765c6 | 4823 | int pipe = intel_crtc->pipe; |
ef9c3aee | 4824 | |
f7abfe8b CW |
4825 | if (!intel_crtc->active) |
4826 | return; | |
4827 | ||
4a3436e8 VS |
4828 | /* |
4829 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4830 | * So diasble underrun reporting before all the planes get disabled. | |
4831 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4832 | * but leave the pipe running. | |
4833 | */ | |
4834 | if (IS_GEN2(dev)) | |
4835 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false); | |
4836 | ||
564ed191 ID |
4837 | /* |
4838 | * Vblank time updates from the shadow to live plane control register | |
4839 | * are blocked if the memory self-refresh mode is active at that | |
4840 | * moment. So to make sure the plane gets truly disabled, disable | |
4841 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4842 | * will be checked/applied by the HW only at the next frame start | |
4843 | * event which is after the vblank start event, so we need to have a | |
4844 | * wait-for-vblank between disabling the plane and the pipe. | |
4845 | */ | |
4846 | intel_set_memory_cxsr(dev_priv, false); | |
9ab0460b VS |
4847 | intel_crtc_disable_planes(crtc); |
4848 | ||
ea9d758d DV |
4849 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4850 | encoder->disable(encoder); | |
4851 | ||
6304cd91 VS |
4852 | /* |
4853 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
4854 | * wait for planes to fully turn off before disabling the pipe. | |
564ed191 ID |
4855 | * We also need to wait on all gmch platforms because of the |
4856 | * self-refresh mode constraint explained above. | |
6304cd91 | 4857 | */ |
564ed191 | 4858 | intel_wait_for_vblank(dev, pipe); |
6304cd91 | 4859 | |
b24e7179 | 4860 | intel_disable_pipe(dev_priv, pipe); |
24a1f16d | 4861 | |
87476d63 | 4862 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 4863 | |
89b667f8 JB |
4864 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4865 | if (encoder->post_disable) | |
4866 | encoder->post_disable(encoder); | |
4867 | ||
076ed3b2 CML |
4868 | if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) { |
4869 | if (IS_CHERRYVIEW(dev)) | |
4870 | chv_disable_pll(dev_priv, pipe); | |
4871 | else if (IS_VALLEYVIEW(dev)) | |
4872 | vlv_disable_pll(dev_priv, pipe); | |
4873 | else | |
4874 | i9xx_disable_pll(dev_priv, pipe); | |
4875 | } | |
0b8765c6 | 4876 | |
4a3436e8 VS |
4877 | if (!IS_GEN2(dev)) |
4878 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false); | |
4879 | ||
f7abfe8b | 4880 | intel_crtc->active = false; |
46ba614c | 4881 | intel_update_watermarks(crtc); |
f37fcc2a | 4882 | |
efa9624e | 4883 | mutex_lock(&dev->struct_mutex); |
6b383a7f | 4884 | intel_update_fbc(dev); |
efa9624e | 4885 | mutex_unlock(&dev->struct_mutex); |
0b8765c6 JB |
4886 | } |
4887 | ||
ee7b9f93 JB |
4888 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
4889 | { | |
4890 | } | |
4891 | ||
976f8a20 DV |
4892 | static void intel_crtc_update_sarea(struct drm_crtc *crtc, |
4893 | bool enabled) | |
2c07245f ZW |
4894 | { |
4895 | struct drm_device *dev = crtc->dev; | |
4896 | struct drm_i915_master_private *master_priv; | |
4897 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4898 | int pipe = intel_crtc->pipe; | |
79e53945 JB |
4899 | |
4900 | if (!dev->primary->master) | |
4901 | return; | |
4902 | ||
4903 | master_priv = dev->primary->master->driver_priv; | |
4904 | if (!master_priv->sarea_priv) | |
4905 | return; | |
4906 | ||
79e53945 JB |
4907 | switch (pipe) { |
4908 | case 0: | |
4909 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; | |
4910 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; | |
4911 | break; | |
4912 | case 1: | |
4913 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; | |
4914 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; | |
4915 | break; | |
4916 | default: | |
9db4a9c7 | 4917 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
79e53945 JB |
4918 | break; |
4919 | } | |
79e53945 JB |
4920 | } |
4921 | ||
b04c5bd6 BF |
4922 | /* Master function to enable/disable CRTC and corresponding power wells */ |
4923 | void intel_crtc_control(struct drm_crtc *crtc, bool enable) | |
976f8a20 DV |
4924 | { |
4925 | struct drm_device *dev = crtc->dev; | |
4926 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0e572fe7 | 4927 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
0e572fe7 DV |
4928 | enum intel_display_power_domain domain; |
4929 | unsigned long domains; | |
976f8a20 | 4930 | |
0e572fe7 DV |
4931 | if (enable) { |
4932 | if (!intel_crtc->active) { | |
e1e9fb84 DV |
4933 | domains = get_crtc_power_domains(crtc); |
4934 | for_each_power_domain(domain, domains) | |
4935 | intel_display_power_get(dev_priv, domain); | |
4936 | intel_crtc->enabled_power_domains = domains; | |
0e572fe7 DV |
4937 | |
4938 | dev_priv->display.crtc_enable(crtc); | |
4939 | } | |
4940 | } else { | |
4941 | if (intel_crtc->active) { | |
4942 | dev_priv->display.crtc_disable(crtc); | |
4943 | ||
e1e9fb84 DV |
4944 | domains = intel_crtc->enabled_power_domains; |
4945 | for_each_power_domain(domain, domains) | |
4946 | intel_display_power_put(dev_priv, domain); | |
4947 | intel_crtc->enabled_power_domains = 0; | |
0e572fe7 DV |
4948 | } |
4949 | } | |
b04c5bd6 BF |
4950 | } |
4951 | ||
4952 | /** | |
4953 | * Sets the power management mode of the pipe and plane. | |
4954 | */ | |
4955 | void intel_crtc_update_dpms(struct drm_crtc *crtc) | |
4956 | { | |
4957 | struct drm_device *dev = crtc->dev; | |
4958 | struct intel_encoder *intel_encoder; | |
4959 | bool enable = false; | |
4960 | ||
4961 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) | |
4962 | enable |= intel_encoder->connectors_active; | |
4963 | ||
4964 | intel_crtc_control(crtc, enable); | |
976f8a20 DV |
4965 | |
4966 | intel_crtc_update_sarea(crtc, enable); | |
4967 | } | |
4968 | ||
cdd59983 CW |
4969 | static void intel_crtc_disable(struct drm_crtc *crtc) |
4970 | { | |
cdd59983 | 4971 | struct drm_device *dev = crtc->dev; |
976f8a20 | 4972 | struct drm_connector *connector; |
ee7b9f93 | 4973 | struct drm_i915_private *dev_priv = dev->dev_private; |
2ff8fde1 | 4974 | struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb); |
a071fa00 | 4975 | enum pipe pipe = to_intel_crtc(crtc)->pipe; |
cdd59983 | 4976 | |
976f8a20 DV |
4977 | /* crtc should still be enabled when we disable it. */ |
4978 | WARN_ON(!crtc->enabled); | |
4979 | ||
4980 | dev_priv->display.crtc_disable(crtc); | |
4981 | intel_crtc_update_sarea(crtc, false); | |
ee7b9f93 JB |
4982 | dev_priv->display.off(crtc); |
4983 | ||
f4510a27 | 4984 | if (crtc->primary->fb) { |
cdd59983 | 4985 | mutex_lock(&dev->struct_mutex); |
a071fa00 DV |
4986 | intel_unpin_fb_obj(old_obj); |
4987 | i915_gem_track_fb(old_obj, NULL, | |
4988 | INTEL_FRONTBUFFER_PRIMARY(pipe)); | |
cdd59983 | 4989 | mutex_unlock(&dev->struct_mutex); |
f4510a27 | 4990 | crtc->primary->fb = NULL; |
976f8a20 DV |
4991 | } |
4992 | ||
4993 | /* Update computed state. */ | |
4994 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4995 | if (!connector->encoder || !connector->encoder->crtc) | |
4996 | continue; | |
4997 | ||
4998 | if (connector->encoder->crtc != crtc) | |
4999 | continue; | |
5000 | ||
5001 | connector->dpms = DRM_MODE_DPMS_OFF; | |
5002 | to_intel_encoder(connector->encoder)->connectors_active = false; | |
cdd59983 CW |
5003 | } |
5004 | } | |
5005 | ||
ea5b213a | 5006 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 5007 | { |
4ef69c7a | 5008 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 5009 | |
ea5b213a CW |
5010 | drm_encoder_cleanup(encoder); |
5011 | kfree(intel_encoder); | |
7e7d76c3 JB |
5012 | } |
5013 | ||
9237329d | 5014 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
5ab432ef DV |
5015 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
5016 | * state of the entire output pipe. */ | |
9237329d | 5017 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
7e7d76c3 | 5018 | { |
5ab432ef DV |
5019 | if (mode == DRM_MODE_DPMS_ON) { |
5020 | encoder->connectors_active = true; | |
5021 | ||
b2cabb0e | 5022 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef DV |
5023 | } else { |
5024 | encoder->connectors_active = false; | |
5025 | ||
b2cabb0e | 5026 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef | 5027 | } |
79e53945 JB |
5028 | } |
5029 | ||
0a91ca29 DV |
5030 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
5031 | * internal consistency). */ | |
b980514c | 5032 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 5033 | { |
0a91ca29 DV |
5034 | if (connector->get_hw_state(connector)) { |
5035 | struct intel_encoder *encoder = connector->encoder; | |
5036 | struct drm_crtc *crtc; | |
5037 | bool encoder_enabled; | |
5038 | enum pipe pipe; | |
5039 | ||
5040 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
5041 | connector->base.base.id, | |
c23cc417 | 5042 | connector->base.name); |
0a91ca29 | 5043 | |
0e32b39c DA |
5044 | /* there is no real hw state for MST connectors */ |
5045 | if (connector->mst_port) | |
5046 | return; | |
5047 | ||
0a91ca29 DV |
5048 | WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, |
5049 | "wrong connector dpms state\n"); | |
5050 | WARN(connector->base.encoder != &encoder->base, | |
5051 | "active connector not linked to encoder\n"); | |
0a91ca29 | 5052 | |
36cd7444 DA |
5053 | if (encoder) { |
5054 | WARN(!encoder->connectors_active, | |
5055 | "encoder->connectors_active not set\n"); | |
5056 | ||
5057 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); | |
5058 | WARN(!encoder_enabled, "encoder not enabled\n"); | |
5059 | if (WARN_ON(!encoder->base.crtc)) | |
5060 | return; | |
0a91ca29 | 5061 | |
36cd7444 | 5062 | crtc = encoder->base.crtc; |
0a91ca29 | 5063 | |
36cd7444 DA |
5064 | WARN(!crtc->enabled, "crtc not enabled\n"); |
5065 | WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); | |
5066 | WARN(pipe != to_intel_crtc(crtc)->pipe, | |
5067 | "encoder active on the wrong pipe\n"); | |
5068 | } | |
0a91ca29 | 5069 | } |
79e53945 JB |
5070 | } |
5071 | ||
5ab432ef DV |
5072 | /* Even simpler default implementation, if there's really no special case to |
5073 | * consider. */ | |
5074 | void intel_connector_dpms(struct drm_connector *connector, int mode) | |
79e53945 | 5075 | { |
5ab432ef DV |
5076 | /* All the simple cases only support two dpms states. */ |
5077 | if (mode != DRM_MODE_DPMS_ON) | |
5078 | mode = DRM_MODE_DPMS_OFF; | |
d4270e57 | 5079 | |
5ab432ef DV |
5080 | if (mode == connector->dpms) |
5081 | return; | |
5082 | ||
5083 | connector->dpms = mode; | |
5084 | ||
5085 | /* Only need to change hw state when actually enabled */ | |
c9976dcf CW |
5086 | if (connector->encoder) |
5087 | intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); | |
0a91ca29 | 5088 | |
b980514c | 5089 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
5090 | } |
5091 | ||
f0947c37 DV |
5092 | /* Simple connector->get_hw_state implementation for encoders that support only |
5093 | * one connector and no cloning and hence the encoder state determines the state | |
5094 | * of the connector. */ | |
5095 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 5096 | { |
24929352 | 5097 | enum pipe pipe = 0; |
f0947c37 | 5098 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 5099 | |
f0947c37 | 5100 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
5101 | } |
5102 | ||
1857e1da DV |
5103 | static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5104 | struct intel_crtc_config *pipe_config) | |
5105 | { | |
5106 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5107 | struct intel_crtc *pipe_B_crtc = | |
5108 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
5109 | ||
5110 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", | |
5111 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5112 | if (pipe_config->fdi_lanes > 4) { | |
5113 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
5114 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5115 | return false; | |
5116 | } | |
5117 | ||
bafb6553 | 5118 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
5119 | if (pipe_config->fdi_lanes > 2) { |
5120 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
5121 | pipe_config->fdi_lanes); | |
5122 | return false; | |
5123 | } else { | |
5124 | return true; | |
5125 | } | |
5126 | } | |
5127 | ||
5128 | if (INTEL_INFO(dev)->num_pipes == 2) | |
5129 | return true; | |
5130 | ||
5131 | /* Ivybridge 3 pipe is really complicated */ | |
5132 | switch (pipe) { | |
5133 | case PIPE_A: | |
5134 | return true; | |
5135 | case PIPE_B: | |
5136 | if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled && | |
5137 | pipe_config->fdi_lanes > 2) { | |
5138 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
5139 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5140 | return false; | |
5141 | } | |
5142 | return true; | |
5143 | case PIPE_C: | |
1e833f40 | 5144 | if (!pipe_has_enabled_pch(pipe_B_crtc) || |
1857e1da DV |
5145 | pipe_B_crtc->config.fdi_lanes <= 2) { |
5146 | if (pipe_config->fdi_lanes > 2) { | |
5147 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
5148 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5149 | return false; | |
5150 | } | |
5151 | } else { | |
5152 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); | |
5153 | return false; | |
5154 | } | |
5155 | return true; | |
5156 | default: | |
5157 | BUG(); | |
5158 | } | |
5159 | } | |
5160 | ||
e29c22c0 DV |
5161 | #define RETRY 1 |
5162 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5163 | struct intel_crtc_config *pipe_config) | |
877d48d5 | 5164 | { |
1857e1da | 5165 | struct drm_device *dev = intel_crtc->base.dev; |
877d48d5 | 5166 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
ff9a6750 | 5167 | int lane, link_bw, fdi_dotclock; |
e29c22c0 | 5168 | bool setup_ok, needs_recompute = false; |
877d48d5 | 5169 | |
e29c22c0 | 5170 | retry: |
877d48d5 DV |
5171 | /* FDI is a binary signal running at ~2.7GHz, encoding |
5172 | * each output octet as 10 bits. The actual frequency | |
5173 | * is stored as a divider into a 100MHz clock, and the | |
5174 | * mode pixel clock is stored in units of 1KHz. | |
5175 | * Hence the bw of each lane in terms of the mode signal | |
5176 | * is: | |
5177 | */ | |
5178 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
5179 | ||
241bfc38 | 5180 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 5181 | |
2bd89a07 | 5182 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
5183 | pipe_config->pipe_bpp); |
5184 | ||
5185 | pipe_config->fdi_lanes = lane; | |
5186 | ||
2bd89a07 | 5187 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 5188 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 5189 | |
e29c22c0 DV |
5190 | setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
5191 | intel_crtc->pipe, pipe_config); | |
5192 | if (!setup_ok && pipe_config->pipe_bpp > 6*3) { | |
5193 | pipe_config->pipe_bpp -= 2*3; | |
5194 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
5195 | pipe_config->pipe_bpp); | |
5196 | needs_recompute = true; | |
5197 | pipe_config->bw_constrained = true; | |
5198 | ||
5199 | goto retry; | |
5200 | } | |
5201 | ||
5202 | if (needs_recompute) | |
5203 | return RETRY; | |
5204 | ||
5205 | return setup_ok ? 0 : -EINVAL; | |
877d48d5 DV |
5206 | } |
5207 | ||
42db64ef PZ |
5208 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5209 | struct intel_crtc_config *pipe_config) | |
5210 | { | |
d330a953 | 5211 | pipe_config->ips_enabled = i915.enable_ips && |
3c4ca58c | 5212 | hsw_crtc_supports_ips(crtc) && |
b6dfdc9b | 5213 | pipe_config->pipe_bpp <= 24; |
42db64ef PZ |
5214 | } |
5215 | ||
a43f6e0f | 5216 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
e29c22c0 | 5217 | struct intel_crtc_config *pipe_config) |
79e53945 | 5218 | { |
a43f6e0f | 5219 | struct drm_device *dev = crtc->base.dev; |
b8cecdf5 | 5220 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
89749350 | 5221 | |
ad3a4479 | 5222 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 VS |
5223 | if (INTEL_INFO(dev)->gen < 4) { |
5224 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5225 | int clock_limit = | |
5226 | dev_priv->display.get_display_clock_speed(dev); | |
5227 | ||
5228 | /* | |
5229 | * Enable pixel doubling when the dot clock | |
5230 | * is > 90% of the (display) core speed. | |
5231 | * | |
b397c96b VS |
5232 | * GDG double wide on either pipe, |
5233 | * otherwise pipe A only. | |
cf532bb2 | 5234 | */ |
b397c96b | 5235 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
241bfc38 | 5236 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
ad3a4479 | 5237 | clock_limit *= 2; |
cf532bb2 | 5238 | pipe_config->double_wide = true; |
ad3a4479 VS |
5239 | } |
5240 | ||
241bfc38 | 5241 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
e29c22c0 | 5242 | return -EINVAL; |
2c07245f | 5243 | } |
89749350 | 5244 | |
1d1d0e27 VS |
5245 | /* |
5246 | * Pipe horizontal size must be even in: | |
5247 | * - DVO ganged mode | |
5248 | * - LVDS dual channel mode | |
5249 | * - Double wide pipe | |
5250 | */ | |
5251 | if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && | |
5252 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) | |
5253 | pipe_config->pipe_src_w &= ~1; | |
5254 | ||
8693a824 DL |
5255 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
5256 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
5257 | */ |
5258 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
5259 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | |
e29c22c0 | 5260 | return -EINVAL; |
44f46b42 | 5261 | |
bd080ee5 | 5262 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { |
5d2d38dd | 5263 | pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ |
bd080ee5 | 5264 | } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { |
5d2d38dd DV |
5265 | /* only a 8bpc pipe, with 6bpc dither through the panel fitter |
5266 | * for lvds. */ | |
5267 | pipe_config->pipe_bpp = 8*3; | |
5268 | } | |
5269 | ||
f5adf94e | 5270 | if (HAS_IPS(dev)) |
a43f6e0f DV |
5271 | hsw_compute_ips_config(crtc, pipe_config); |
5272 | ||
12030431 DV |
5273 | /* |
5274 | * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the | |
5275 | * old clock survives for now. | |
5276 | */ | |
5277 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev)) | |
a43f6e0f | 5278 | pipe_config->shared_dpll = crtc->config.shared_dpll; |
42db64ef | 5279 | |
877d48d5 | 5280 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 5281 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 5282 | |
e29c22c0 | 5283 | return 0; |
79e53945 JB |
5284 | } |
5285 | ||
25eb05fc JB |
5286 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
5287 | { | |
d197b7d3 VS |
5288 | struct drm_i915_private *dev_priv = dev->dev_private; |
5289 | int vco = valleyview_get_vco(dev_priv); | |
5290 | u32 val; | |
5291 | int divider; | |
5292 | ||
d49a340d VS |
5293 | /* FIXME: Punit isn't quite ready yet */ |
5294 | if (IS_CHERRYVIEW(dev)) | |
5295 | return 400000; | |
5296 | ||
d197b7d3 VS |
5297 | mutex_lock(&dev_priv->dpio_lock); |
5298 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
5299 | mutex_unlock(&dev_priv->dpio_lock); | |
5300 | ||
5301 | divider = val & DISPLAY_FREQUENCY_VALUES; | |
5302 | ||
7d007f40 VS |
5303 | WARN((val & DISPLAY_FREQUENCY_STATUS) != |
5304 | (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
5305 | "cdclk change in progress\n"); | |
5306 | ||
d197b7d3 | 5307 | return DIV_ROUND_CLOSEST(vco << 1, divider + 1); |
25eb05fc JB |
5308 | } |
5309 | ||
e70236a8 JB |
5310 | static int i945_get_display_clock_speed(struct drm_device *dev) |
5311 | { | |
5312 | return 400000; | |
5313 | } | |
79e53945 | 5314 | |
e70236a8 | 5315 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 5316 | { |
e70236a8 JB |
5317 | return 333000; |
5318 | } | |
79e53945 | 5319 | |
e70236a8 JB |
5320 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
5321 | { | |
5322 | return 200000; | |
5323 | } | |
79e53945 | 5324 | |
257a7ffc DV |
5325 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
5326 | { | |
5327 | u16 gcfgc = 0; | |
5328 | ||
5329 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
5330 | ||
5331 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
5332 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
5333 | return 267000; | |
5334 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: | |
5335 | return 333000; | |
5336 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: | |
5337 | return 444000; | |
5338 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: | |
5339 | return 200000; | |
5340 | default: | |
5341 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
5342 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
5343 | return 133000; | |
5344 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: | |
5345 | return 167000; | |
5346 | } | |
5347 | } | |
5348 | ||
e70236a8 JB |
5349 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
5350 | { | |
5351 | u16 gcfgc = 0; | |
79e53945 | 5352 | |
e70236a8 JB |
5353 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
5354 | ||
5355 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
5356 | return 133000; | |
5357 | else { | |
5358 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
5359 | case GC_DISPLAY_CLOCK_333_MHZ: | |
5360 | return 333000; | |
5361 | default: | |
5362 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
5363 | return 190000; | |
79e53945 | 5364 | } |
e70236a8 JB |
5365 | } |
5366 | } | |
5367 | ||
5368 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
5369 | { | |
5370 | return 266000; | |
5371 | } | |
5372 | ||
5373 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
5374 | { | |
5375 | u16 hpllcc = 0; | |
5376 | /* Assume that the hardware is in the high speed state. This | |
5377 | * should be the default. | |
5378 | */ | |
5379 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
5380 | case GC_CLOCK_133_200: | |
5381 | case GC_CLOCK_100_200: | |
5382 | return 200000; | |
5383 | case GC_CLOCK_166_250: | |
5384 | return 250000; | |
5385 | case GC_CLOCK_100_133: | |
79e53945 | 5386 | return 133000; |
e70236a8 | 5387 | } |
79e53945 | 5388 | |
e70236a8 JB |
5389 | /* Shouldn't happen */ |
5390 | return 0; | |
5391 | } | |
79e53945 | 5392 | |
e70236a8 JB |
5393 | static int i830_get_display_clock_speed(struct drm_device *dev) |
5394 | { | |
5395 | return 133000; | |
79e53945 JB |
5396 | } |
5397 | ||
2c07245f | 5398 | static void |
a65851af | 5399 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 5400 | { |
a65851af VS |
5401 | while (*num > DATA_LINK_M_N_MASK || |
5402 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
5403 | *num >>= 1; |
5404 | *den >>= 1; | |
5405 | } | |
5406 | } | |
5407 | ||
a65851af VS |
5408 | static void compute_m_n(unsigned int m, unsigned int n, |
5409 | uint32_t *ret_m, uint32_t *ret_n) | |
5410 | { | |
5411 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
5412 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
5413 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
5414 | } | |
5415 | ||
e69d0bc1 DV |
5416 | void |
5417 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
5418 | int pixel_clock, int link_clock, | |
5419 | struct intel_link_m_n *m_n) | |
2c07245f | 5420 | { |
e69d0bc1 | 5421 | m_n->tu = 64; |
a65851af VS |
5422 | |
5423 | compute_m_n(bits_per_pixel * pixel_clock, | |
5424 | link_clock * nlanes * 8, | |
5425 | &m_n->gmch_m, &m_n->gmch_n); | |
5426 | ||
5427 | compute_m_n(pixel_clock, link_clock, | |
5428 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
5429 | } |
5430 | ||
a7615030 CW |
5431 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
5432 | { | |
d330a953 JN |
5433 | if (i915.panel_use_ssc >= 0) |
5434 | return i915.panel_use_ssc != 0; | |
41aa3448 | 5435 | return dev_priv->vbt.lvds_use_ssc |
435793df | 5436 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
5437 | } |
5438 | ||
c65d77d8 JB |
5439 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
5440 | { | |
5441 | struct drm_device *dev = crtc->dev; | |
5442 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5443 | int refclk; | |
5444 | ||
a0c4da24 | 5445 | if (IS_VALLEYVIEW(dev)) { |
9a0ea498 | 5446 | refclk = 100000; |
a0c4da24 | 5447 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 5448 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
5449 | refclk = dev_priv->vbt.lvds_ssc_freq; |
5450 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
5451 | } else if (!IS_GEN2(dev)) { |
5452 | refclk = 96000; | |
5453 | } else { | |
5454 | refclk = 48000; | |
5455 | } | |
5456 | ||
5457 | return refclk; | |
5458 | } | |
5459 | ||
7429e9d4 | 5460 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 5461 | { |
7df00d7a | 5462 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 5463 | } |
f47709a9 | 5464 | |
7429e9d4 DV |
5465 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
5466 | { | |
5467 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
5468 | } |
5469 | ||
f47709a9 | 5470 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
a7516a05 JB |
5471 | intel_clock_t *reduced_clock) |
5472 | { | |
f47709a9 | 5473 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
5474 | u32 fp, fp2 = 0; |
5475 | ||
5476 | if (IS_PINEVIEW(dev)) { | |
7429e9d4 | 5477 | fp = pnv_dpll_compute_fp(&crtc->config.dpll); |
a7516a05 | 5478 | if (reduced_clock) |
7429e9d4 | 5479 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 5480 | } else { |
7429e9d4 | 5481 | fp = i9xx_dpll_compute_fp(&crtc->config.dpll); |
a7516a05 | 5482 | if (reduced_clock) |
7429e9d4 | 5483 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
5484 | } |
5485 | ||
8bcc2795 | 5486 | crtc->config.dpll_hw_state.fp0 = fp; |
a7516a05 | 5487 | |
f47709a9 DV |
5488 | crtc->lowfreq_avail = false; |
5489 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && | |
d330a953 | 5490 | reduced_clock && i915.powersave) { |
8bcc2795 | 5491 | crtc->config.dpll_hw_state.fp1 = fp2; |
f47709a9 | 5492 | crtc->lowfreq_avail = true; |
a7516a05 | 5493 | } else { |
8bcc2795 | 5494 | crtc->config.dpll_hw_state.fp1 = fp; |
a7516a05 JB |
5495 | } |
5496 | } | |
5497 | ||
5e69f97f CML |
5498 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
5499 | pipe) | |
89b667f8 JB |
5500 | { |
5501 | u32 reg_val; | |
5502 | ||
5503 | /* | |
5504 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
5505 | * and set it to a reasonable value instead. | |
5506 | */ | |
ab3c759a | 5507 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
5508 | reg_val &= 0xffffff00; |
5509 | reg_val |= 0x00000030; | |
ab3c759a | 5510 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 5511 | |
ab3c759a | 5512 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
5513 | reg_val &= 0x8cffffff; |
5514 | reg_val = 0x8c000000; | |
ab3c759a | 5515 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 5516 | |
ab3c759a | 5517 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 5518 | reg_val &= 0xffffff00; |
ab3c759a | 5519 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 5520 | |
ab3c759a | 5521 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
5522 | reg_val &= 0x00ffffff; |
5523 | reg_val |= 0xb0000000; | |
ab3c759a | 5524 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
5525 | } |
5526 | ||
b551842d DV |
5527 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
5528 | struct intel_link_m_n *m_n) | |
5529 | { | |
5530 | struct drm_device *dev = crtc->base.dev; | |
5531 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5532 | int pipe = crtc->pipe; | |
5533 | ||
e3b95f1e DV |
5534 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
5535 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
5536 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
5537 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
5538 | } |
5539 | ||
5540 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
5541 | struct intel_link_m_n *m_n, |
5542 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
5543 | { |
5544 | struct drm_device *dev = crtc->base.dev; | |
5545 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5546 | int pipe = crtc->pipe; | |
5547 | enum transcoder transcoder = crtc->config.cpu_transcoder; | |
5548 | ||
5549 | if (INTEL_INFO(dev)->gen >= 5) { | |
5550 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
5551 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
5552 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
5553 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
5554 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
5555 | * for gen < 8) and if DRRS is supported (to make sure the | |
5556 | * registers are not unnecessarily accessed). | |
5557 | */ | |
5558 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
5559 | crtc->config.has_drrs) { | |
5560 | I915_WRITE(PIPE_DATA_M2(transcoder), | |
5561 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
5562 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
5563 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
5564 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
5565 | } | |
b551842d | 5566 | } else { |
e3b95f1e DV |
5567 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
5568 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
5569 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
5570 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
5571 | } |
5572 | } | |
5573 | ||
f769cd24 | 5574 | void intel_dp_set_m_n(struct intel_crtc *crtc) |
03afc4a2 DV |
5575 | { |
5576 | if (crtc->config.has_pch_encoder) | |
5577 | intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); | |
5578 | else | |
f769cd24 VK |
5579 | intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n, |
5580 | &crtc->config.dp_m2_n2); | |
03afc4a2 DV |
5581 | } |
5582 | ||
f47709a9 | 5583 | static void vlv_update_pll(struct intel_crtc *crtc) |
bdd4b6a6 DV |
5584 | { |
5585 | u32 dpll, dpll_md; | |
5586 | ||
5587 | /* | |
5588 | * Enable DPIO clock input. We should never disable the reference | |
5589 | * clock for pipe B, since VGA hotplug / manual detection depends | |
5590 | * on it. | |
5591 | */ | |
5592 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | | |
5593 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; | |
5594 | /* We should never disable this, set it here for state tracking */ | |
5595 | if (crtc->pipe == PIPE_B) | |
5596 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
5597 | dpll |= DPLL_VCO_ENABLE; | |
5598 | crtc->config.dpll_hw_state.dpll = dpll; | |
5599 | ||
5600 | dpll_md = (crtc->config.pixel_multiplier - 1) | |
5601 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
5602 | crtc->config.dpll_hw_state.dpll_md = dpll_md; | |
5603 | } | |
5604 | ||
5605 | static void vlv_prepare_pll(struct intel_crtc *crtc) | |
a0c4da24 | 5606 | { |
f47709a9 | 5607 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 5608 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 5609 | int pipe = crtc->pipe; |
bdd4b6a6 | 5610 | u32 mdiv; |
a0c4da24 | 5611 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 5612 | u32 coreclk, reg_val; |
a0c4da24 | 5613 | |
09153000 DV |
5614 | mutex_lock(&dev_priv->dpio_lock); |
5615 | ||
f47709a9 DV |
5616 | bestn = crtc->config.dpll.n; |
5617 | bestm1 = crtc->config.dpll.m1; | |
5618 | bestm2 = crtc->config.dpll.m2; | |
5619 | bestp1 = crtc->config.dpll.p1; | |
5620 | bestp2 = crtc->config.dpll.p2; | |
a0c4da24 | 5621 | |
89b667f8 JB |
5622 | /* See eDP HDMI DPIO driver vbios notes doc */ |
5623 | ||
5624 | /* PLL B needs special handling */ | |
bdd4b6a6 | 5625 | if (pipe == PIPE_B) |
5e69f97f | 5626 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
5627 | |
5628 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 5629 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
5630 | |
5631 | /* Disable target IRef on PLL */ | |
ab3c759a | 5632 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 5633 | reg_val &= 0x00ffffff; |
ab3c759a | 5634 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
5635 | |
5636 | /* Disable fast lock */ | |
ab3c759a | 5637 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
5638 | |
5639 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
5640 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
5641 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
5642 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 5643 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
5644 | |
5645 | /* | |
5646 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
5647 | * but we don't support that). | |
5648 | * Note: don't use the DAC post divider as it seems unstable. | |
5649 | */ | |
5650 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 5651 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 5652 | |
a0c4da24 | 5653 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 5654 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 5655 | |
89b667f8 | 5656 | /* Set HBR and RBR LPF coefficients */ |
ff9a6750 | 5657 | if (crtc->config.port_clock == 162000 || |
99750bd4 | 5658 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) || |
89b667f8 | 5659 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) |
ab3c759a | 5660 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 5661 | 0x009f0003); |
89b667f8 | 5662 | else |
ab3c759a | 5663 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
5664 | 0x00d0000f); |
5665 | ||
5666 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) || | |
5667 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) { | |
5668 | /* Use SSC source */ | |
bdd4b6a6 | 5669 | if (pipe == PIPE_A) |
ab3c759a | 5670 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5671 | 0x0df40000); |
5672 | else | |
ab3c759a | 5673 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5674 | 0x0df70000); |
5675 | } else { /* HDMI or VGA */ | |
5676 | /* Use bend source */ | |
bdd4b6a6 | 5677 | if (pipe == PIPE_A) |
ab3c759a | 5678 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5679 | 0x0df70000); |
5680 | else | |
ab3c759a | 5681 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5682 | 0x0df40000); |
5683 | } | |
a0c4da24 | 5684 | |
ab3c759a | 5685 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 JB |
5686 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
5687 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) || | |
5688 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) | |
5689 | coreclk |= 0x01000000; | |
ab3c759a | 5690 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 5691 | |
ab3c759a | 5692 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
09153000 | 5693 | mutex_unlock(&dev_priv->dpio_lock); |
a0c4da24 JB |
5694 | } |
5695 | ||
9d556c99 | 5696 | static void chv_update_pll(struct intel_crtc *crtc) |
1ae0d137 VS |
5697 | { |
5698 | crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV | | |
5699 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | | |
5700 | DPLL_VCO_ENABLE; | |
5701 | if (crtc->pipe != PIPE_A) | |
5702 | crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
5703 | ||
5704 | crtc->config.dpll_hw_state.dpll_md = | |
5705 | (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
5706 | } | |
5707 | ||
5708 | static void chv_prepare_pll(struct intel_crtc *crtc) | |
9d556c99 CML |
5709 | { |
5710 | struct drm_device *dev = crtc->base.dev; | |
5711 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5712 | int pipe = crtc->pipe; | |
5713 | int dpll_reg = DPLL(crtc->pipe); | |
5714 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
580d3811 | 5715 | u32 loopfilter, intcoeff; |
9d556c99 CML |
5716 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
5717 | int refclk; | |
5718 | ||
9d556c99 CML |
5719 | bestn = crtc->config.dpll.n; |
5720 | bestm2_frac = crtc->config.dpll.m2 & 0x3fffff; | |
5721 | bestm1 = crtc->config.dpll.m1; | |
5722 | bestm2 = crtc->config.dpll.m2 >> 22; | |
5723 | bestp1 = crtc->config.dpll.p1; | |
5724 | bestp2 = crtc->config.dpll.p2; | |
5725 | ||
5726 | /* | |
5727 | * Enable Refclk and SSC | |
5728 | */ | |
a11b0703 VS |
5729 | I915_WRITE(dpll_reg, |
5730 | crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); | |
5731 | ||
5732 | mutex_lock(&dev_priv->dpio_lock); | |
9d556c99 | 5733 | |
9d556c99 CML |
5734 | /* p1 and p2 divider */ |
5735 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
5736 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
5737 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
5738 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
5739 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
5740 | ||
5741 | /* Feedback post-divider - m2 */ | |
5742 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
5743 | ||
5744 | /* Feedback refclk divider - n and m1 */ | |
5745 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
5746 | DPIO_CHV_M1_DIV_BY_2 | | |
5747 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
5748 | ||
5749 | /* M2 fraction division */ | |
5750 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); | |
5751 | ||
5752 | /* M2 fraction division enable */ | |
5753 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), | |
5754 | DPIO_CHV_FRAC_DIV_EN | | |
5755 | (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT)); | |
5756 | ||
5757 | /* Loop filter */ | |
5758 | refclk = i9xx_get_refclk(&crtc->base, 0); | |
5759 | loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT | | |
5760 | 2 << DPIO_CHV_GAIN_CTRL_SHIFT; | |
5761 | if (refclk == 100000) | |
5762 | intcoeff = 11; | |
5763 | else if (refclk == 38400) | |
5764 | intcoeff = 10; | |
5765 | else | |
5766 | intcoeff = 9; | |
5767 | loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT; | |
5768 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); | |
5769 | ||
5770 | /* AFC Recal */ | |
5771 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
5772 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
5773 | DPIO_AFC_RECAL); | |
5774 | ||
5775 | mutex_unlock(&dev_priv->dpio_lock); | |
5776 | } | |
5777 | ||
f47709a9 DV |
5778 | static void i9xx_update_pll(struct intel_crtc *crtc, |
5779 | intel_clock_t *reduced_clock, | |
eb1cbe48 DV |
5780 | int num_connectors) |
5781 | { | |
f47709a9 | 5782 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 5783 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
5784 | u32 dpll; |
5785 | bool is_sdvo; | |
f47709a9 | 5786 | struct dpll *clock = &crtc->config.dpll; |
eb1cbe48 | 5787 | |
f47709a9 | 5788 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 5789 | |
f47709a9 DV |
5790 | is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) || |
5791 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
5792 | |
5793 | dpll = DPLL_VGA_MODE_DIS; | |
5794 | ||
f47709a9 | 5795 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
5796 | dpll |= DPLLB_MODE_LVDS; |
5797 | else | |
5798 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 5799 | |
ef1b460d | 5800 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
198a037f DV |
5801 | dpll |= (crtc->config.pixel_multiplier - 1) |
5802 | << SDVO_MULTIPLIER_SHIFT_HIRES; | |
eb1cbe48 | 5803 | } |
198a037f DV |
5804 | |
5805 | if (is_sdvo) | |
4a33e48d | 5806 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 5807 | |
f47709a9 | 5808 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) |
4a33e48d | 5809 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
5810 | |
5811 | /* compute bitmask from p1 value */ | |
5812 | if (IS_PINEVIEW(dev)) | |
5813 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
5814 | else { | |
5815 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5816 | if (IS_G4X(dev) && reduced_clock) | |
5817 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
5818 | } | |
5819 | switch (clock->p2) { | |
5820 | case 5: | |
5821 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
5822 | break; | |
5823 | case 7: | |
5824 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
5825 | break; | |
5826 | case 10: | |
5827 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
5828 | break; | |
5829 | case 14: | |
5830 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
5831 | break; | |
5832 | } | |
5833 | if (INTEL_INFO(dev)->gen >= 4) | |
5834 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
5835 | ||
09ede541 | 5836 | if (crtc->config.sdvo_tv_clock) |
eb1cbe48 | 5837 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
f47709a9 | 5838 | else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
5839 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
5840 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
5841 | else | |
5842 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5843 | ||
5844 | dpll |= DPLL_VCO_ENABLE; | |
8bcc2795 DV |
5845 | crtc->config.dpll_hw_state.dpll = dpll; |
5846 | ||
eb1cbe48 | 5847 | if (INTEL_INFO(dev)->gen >= 4) { |
ef1b460d DV |
5848 | u32 dpll_md = (crtc->config.pixel_multiplier - 1) |
5849 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
8bcc2795 | 5850 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
5851 | } |
5852 | } | |
5853 | ||
f47709a9 | 5854 | static void i8xx_update_pll(struct intel_crtc *crtc, |
f47709a9 | 5855 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
5856 | int num_connectors) |
5857 | { | |
f47709a9 | 5858 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 5859 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 5860 | u32 dpll; |
f47709a9 | 5861 | struct dpll *clock = &crtc->config.dpll; |
eb1cbe48 | 5862 | |
f47709a9 | 5863 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 5864 | |
eb1cbe48 DV |
5865 | dpll = DPLL_VGA_MODE_DIS; |
5866 | ||
f47709a9 | 5867 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
5868 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
5869 | } else { | |
5870 | if (clock->p1 == 2) | |
5871 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
5872 | else | |
5873 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5874 | if (clock->p2 == 4) | |
5875 | dpll |= PLL_P2_DIVIDE_BY_4; | |
5876 | } | |
5877 | ||
4a33e48d DV |
5878 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO)) |
5879 | dpll |= DPLL_DVO_2X_MODE; | |
5880 | ||
f47709a9 | 5881 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
5882 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
5883 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
5884 | else | |
5885 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5886 | ||
5887 | dpll |= DPLL_VCO_ENABLE; | |
8bcc2795 | 5888 | crtc->config.dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
5889 | } |
5890 | ||
8a654f3b | 5891 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
5892 | { |
5893 | struct drm_device *dev = intel_crtc->base.dev; | |
5894 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5895 | enum pipe pipe = intel_crtc->pipe; | |
3b117c8f | 5896 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
8a654f3b DV |
5897 | struct drm_display_mode *adjusted_mode = |
5898 | &intel_crtc->config.adjusted_mode; | |
1caea6e9 VS |
5899 | uint32_t crtc_vtotal, crtc_vblank_end; |
5900 | int vsyncshift = 0; | |
4d8a62ea DV |
5901 | |
5902 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
5903 | * the hw state checker will get angry at the mismatch. */ | |
5904 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
5905 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 5906 | |
609aeaca | 5907 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 5908 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
5909 | crtc_vtotal -= 1; |
5910 | crtc_vblank_end -= 1; | |
609aeaca VS |
5911 | |
5912 | if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO)) | |
5913 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; | |
5914 | else | |
5915 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
5916 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
5917 | if (vsyncshift < 0) |
5918 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
5919 | } |
5920 | ||
5921 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 5922 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 5923 | |
fe2b8f9d | 5924 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
5925 | (adjusted_mode->crtc_hdisplay - 1) | |
5926 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 5927 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
5928 | (adjusted_mode->crtc_hblank_start - 1) | |
5929 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 5930 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
5931 | (adjusted_mode->crtc_hsync_start - 1) | |
5932 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
5933 | ||
fe2b8f9d | 5934 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 5935 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 5936 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 5937 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 5938 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 5939 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 5940 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
5941 | (adjusted_mode->crtc_vsync_start - 1) | |
5942 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
5943 | ||
b5e508d4 PZ |
5944 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
5945 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
5946 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
5947 | * bits. */ | |
5948 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
5949 | (pipe == PIPE_B || pipe == PIPE_C)) | |
5950 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
5951 | ||
b0e77b9c PZ |
5952 | /* pipesrc controls the size that is scaled from, which should |
5953 | * always be the user's requested size. | |
5954 | */ | |
5955 | I915_WRITE(PIPESRC(pipe), | |
37327abd VS |
5956 | ((intel_crtc->config.pipe_src_w - 1) << 16) | |
5957 | (intel_crtc->config.pipe_src_h - 1)); | |
b0e77b9c PZ |
5958 | } |
5959 | ||
1bd1bd80 DV |
5960 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5961 | struct intel_crtc_config *pipe_config) | |
5962 | { | |
5963 | struct drm_device *dev = crtc->base.dev; | |
5964 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5965 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
5966 | uint32_t tmp; | |
5967 | ||
5968 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
5969 | pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; | |
5970 | pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
5971 | tmp = I915_READ(HBLANK(cpu_transcoder)); | |
5972 | pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; | |
5973 | pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
5974 | tmp = I915_READ(HSYNC(cpu_transcoder)); | |
5975 | pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; | |
5976 | pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
5977 | ||
5978 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
5979 | pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; | |
5980 | pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
5981 | tmp = I915_READ(VBLANK(cpu_transcoder)); | |
5982 | pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; | |
5983 | pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
5984 | tmp = I915_READ(VSYNC(cpu_transcoder)); | |
5985 | pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; | |
5986 | pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
5987 | ||
5988 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
5989 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; | |
5990 | pipe_config->adjusted_mode.crtc_vtotal += 1; | |
5991 | pipe_config->adjusted_mode.crtc_vblank_end += 1; | |
5992 | } | |
5993 | ||
5994 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
5995 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
5996 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
5997 | ||
5998 | pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h; | |
5999 | pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
6000 | } |
6001 | ||
f6a83288 DV |
6002 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
6003 | struct intel_crtc_config *pipe_config) | |
babea61d | 6004 | { |
f6a83288 DV |
6005 | mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay; |
6006 | mode->htotal = pipe_config->adjusted_mode.crtc_htotal; | |
6007 | mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start; | |
6008 | mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end; | |
babea61d | 6009 | |
f6a83288 DV |
6010 | mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay; |
6011 | mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal; | |
6012 | mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start; | |
6013 | mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end; | |
babea61d | 6014 | |
f6a83288 | 6015 | mode->flags = pipe_config->adjusted_mode.flags; |
babea61d | 6016 | |
f6a83288 DV |
6017 | mode->clock = pipe_config->adjusted_mode.crtc_clock; |
6018 | mode->flags |= pipe_config->adjusted_mode.flags; | |
babea61d JB |
6019 | } |
6020 | ||
84b046f3 DV |
6021 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
6022 | { | |
6023 | struct drm_device *dev = intel_crtc->base.dev; | |
6024 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6025 | uint32_t pipeconf; | |
6026 | ||
9f11a9e4 | 6027 | pipeconf = 0; |
84b046f3 | 6028 | |
67c72a12 DV |
6029 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
6030 | I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE) | |
6031 | pipeconf |= PIPECONF_ENABLE; | |
6032 | ||
cf532bb2 VS |
6033 | if (intel_crtc->config.double_wide) |
6034 | pipeconf |= PIPECONF_DOUBLE_WIDE; | |
84b046f3 | 6035 | |
ff9ce46e DV |
6036 | /* only g4x and later have fancy bpc/dither controls */ |
6037 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { | |
ff9ce46e DV |
6038 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6039 | if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30) | |
6040 | pipeconf |= PIPECONF_DITHER_EN | | |
84b046f3 | 6041 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 6042 | |
ff9ce46e DV |
6043 | switch (intel_crtc->config.pipe_bpp) { |
6044 | case 18: | |
6045 | pipeconf |= PIPECONF_6BPC; | |
6046 | break; | |
6047 | case 24: | |
6048 | pipeconf |= PIPECONF_8BPC; | |
6049 | break; | |
6050 | case 30: | |
6051 | pipeconf |= PIPECONF_10BPC; | |
6052 | break; | |
6053 | default: | |
6054 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
6055 | BUG(); | |
84b046f3 DV |
6056 | } |
6057 | } | |
6058 | ||
6059 | if (HAS_PIPE_CXSR(dev)) { | |
6060 | if (intel_crtc->lowfreq_avail) { | |
6061 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
6062 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
6063 | } else { | |
6064 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
6065 | } |
6066 | } | |
6067 | ||
efc2cfff VS |
6068 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
6069 | if (INTEL_INFO(dev)->gen < 4 || | |
6070 | intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO)) | |
6071 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; | |
6072 | else | |
6073 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
6074 | } else | |
84b046f3 DV |
6075 | pipeconf |= PIPECONF_PROGRESSIVE; |
6076 | ||
9f11a9e4 DV |
6077 | if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range) |
6078 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; | |
9c8e09b7 | 6079 | |
84b046f3 DV |
6080 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
6081 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
6082 | } | |
6083 | ||
f564048e | 6084 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
f564048e | 6085 | int x, int y, |
94352cf9 | 6086 | struct drm_framebuffer *fb) |
79e53945 JB |
6087 | { |
6088 | struct drm_device *dev = crtc->dev; | |
6089 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6090 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
c751ce4f | 6091 | int refclk, num_connectors = 0; |
652c393a | 6092 | intel_clock_t clock, reduced_clock; |
a16af721 | 6093 | bool ok, has_reduced_clock = false; |
e9fd1c02 | 6094 | bool is_lvds = false, is_dsi = false; |
5eddb70b | 6095 | struct intel_encoder *encoder; |
d4906093 | 6096 | const intel_limit_t *limit; |
79e53945 | 6097 | |
6c2b7c12 | 6098 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5eddb70b | 6099 | switch (encoder->type) { |
79e53945 JB |
6100 | case INTEL_OUTPUT_LVDS: |
6101 | is_lvds = true; | |
6102 | break; | |
e9fd1c02 JN |
6103 | case INTEL_OUTPUT_DSI: |
6104 | is_dsi = true; | |
6105 | break; | |
79e53945 | 6106 | } |
43565a06 | 6107 | |
c751ce4f | 6108 | num_connectors++; |
79e53945 JB |
6109 | } |
6110 | ||
f2335330 | 6111 | if (is_dsi) |
5b18e57c | 6112 | return 0; |
f2335330 JN |
6113 | |
6114 | if (!intel_crtc->config.clock_set) { | |
6115 | refclk = i9xx_get_refclk(crtc, num_connectors); | |
79e53945 | 6116 | |
e9fd1c02 JN |
6117 | /* |
6118 | * Returns a set of divisors for the desired target clock with | |
6119 | * the given refclk, or FALSE. The returned values represent | |
6120 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
6121 | * 2) / p1 / p2. | |
6122 | */ | |
6123 | limit = intel_limit(crtc, refclk); | |
6124 | ok = dev_priv->display.find_dpll(limit, crtc, | |
6125 | intel_crtc->config.port_clock, | |
6126 | refclk, NULL, &clock); | |
f2335330 | 6127 | if (!ok) { |
e9fd1c02 JN |
6128 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
6129 | return -EINVAL; | |
6130 | } | |
79e53945 | 6131 | |
f2335330 JN |
6132 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
6133 | /* | |
6134 | * Ensure we match the reduced clock's P to the target | |
6135 | * clock. If the clocks don't match, we can't switch | |
6136 | * the display clock by using the FP0/FP1. In such case | |
6137 | * we will disable the LVDS downclock feature. | |
6138 | */ | |
6139 | has_reduced_clock = | |
6140 | dev_priv->display.find_dpll(limit, crtc, | |
6141 | dev_priv->lvds_downclock, | |
6142 | refclk, &clock, | |
6143 | &reduced_clock); | |
6144 | } | |
6145 | /* Compat-code for transition, will disappear. */ | |
f47709a9 DV |
6146 | intel_crtc->config.dpll.n = clock.n; |
6147 | intel_crtc->config.dpll.m1 = clock.m1; | |
6148 | intel_crtc->config.dpll.m2 = clock.m2; | |
6149 | intel_crtc->config.dpll.p1 = clock.p1; | |
6150 | intel_crtc->config.dpll.p2 = clock.p2; | |
6151 | } | |
7026d4ac | 6152 | |
e9fd1c02 | 6153 | if (IS_GEN2(dev)) { |
8a654f3b | 6154 | i8xx_update_pll(intel_crtc, |
2a8f64ca VP |
6155 | has_reduced_clock ? &reduced_clock : NULL, |
6156 | num_connectors); | |
9d556c99 CML |
6157 | } else if (IS_CHERRYVIEW(dev)) { |
6158 | chv_update_pll(intel_crtc); | |
e9fd1c02 | 6159 | } else if (IS_VALLEYVIEW(dev)) { |
f2335330 | 6160 | vlv_update_pll(intel_crtc); |
e9fd1c02 | 6161 | } else { |
f47709a9 | 6162 | i9xx_update_pll(intel_crtc, |
eb1cbe48 | 6163 | has_reduced_clock ? &reduced_clock : NULL, |
eba905b2 | 6164 | num_connectors); |
e9fd1c02 | 6165 | } |
79e53945 | 6166 | |
c8f7a0db | 6167 | return 0; |
f564048e EA |
6168 | } |
6169 | ||
2fa2fe9a DV |
6170 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
6171 | struct intel_crtc_config *pipe_config) | |
6172 | { | |
6173 | struct drm_device *dev = crtc->base.dev; | |
6174 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6175 | uint32_t tmp; | |
6176 | ||
dc9e7dec VS |
6177 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
6178 | return; | |
6179 | ||
2fa2fe9a | 6180 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
6181 | if (!(tmp & PFIT_ENABLE)) |
6182 | return; | |
2fa2fe9a | 6183 | |
06922821 | 6184 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
6185 | if (INTEL_INFO(dev)->gen < 4) { |
6186 | if (crtc->pipe != PIPE_B) | |
6187 | return; | |
2fa2fe9a DV |
6188 | } else { |
6189 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
6190 | return; | |
6191 | } | |
6192 | ||
06922821 | 6193 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
6194 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
6195 | if (INTEL_INFO(dev)->gen < 5) | |
6196 | pipe_config->gmch_pfit.lvds_border_bits = | |
6197 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
6198 | } | |
6199 | ||
acbec814 JB |
6200 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
6201 | struct intel_crtc_config *pipe_config) | |
6202 | { | |
6203 | struct drm_device *dev = crtc->base.dev; | |
6204 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6205 | int pipe = pipe_config->cpu_transcoder; | |
6206 | intel_clock_t clock; | |
6207 | u32 mdiv; | |
662c6ecb | 6208 | int refclk = 100000; |
acbec814 | 6209 | |
f573de5a SK |
6210 | /* In case of MIPI DPLL will not even be used */ |
6211 | if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) | |
6212 | return; | |
6213 | ||
acbec814 | 6214 | mutex_lock(&dev_priv->dpio_lock); |
ab3c759a | 6215 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
acbec814 JB |
6216 | mutex_unlock(&dev_priv->dpio_lock); |
6217 | ||
6218 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
6219 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
6220 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
6221 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
6222 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
6223 | ||
f646628b | 6224 | vlv_clock(refclk, &clock); |
acbec814 | 6225 | |
f646628b VS |
6226 | /* clock.dot is the fast clock */ |
6227 | pipe_config->port_clock = clock.dot / 5; | |
acbec814 JB |
6228 | } |
6229 | ||
1ad292b5 JB |
6230 | static void i9xx_get_plane_config(struct intel_crtc *crtc, |
6231 | struct intel_plane_config *plane_config) | |
6232 | { | |
6233 | struct drm_device *dev = crtc->base.dev; | |
6234 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6235 | u32 val, base, offset; | |
6236 | int pipe = crtc->pipe, plane = crtc->plane; | |
6237 | int fourcc, pixel_format; | |
6238 | int aligned_height; | |
6239 | ||
66e514c1 DA |
6240 | crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL); |
6241 | if (!crtc->base.primary->fb) { | |
1ad292b5 JB |
6242 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
6243 | return; | |
6244 | } | |
6245 | ||
6246 | val = I915_READ(DSPCNTR(plane)); | |
6247 | ||
6248 | if (INTEL_INFO(dev)->gen >= 4) | |
6249 | if (val & DISPPLANE_TILED) | |
6250 | plane_config->tiled = true; | |
6251 | ||
6252 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
6253 | fourcc = intel_format_to_fourcc(pixel_format); | |
66e514c1 DA |
6254 | crtc->base.primary->fb->pixel_format = fourcc; |
6255 | crtc->base.primary->fb->bits_per_pixel = | |
1ad292b5 JB |
6256 | drm_format_plane_cpp(fourcc, 0) * 8; |
6257 | ||
6258 | if (INTEL_INFO(dev)->gen >= 4) { | |
6259 | if (plane_config->tiled) | |
6260 | offset = I915_READ(DSPTILEOFF(plane)); | |
6261 | else | |
6262 | offset = I915_READ(DSPLINOFF(plane)); | |
6263 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
6264 | } else { | |
6265 | base = I915_READ(DSPADDR(plane)); | |
6266 | } | |
6267 | plane_config->base = base; | |
6268 | ||
6269 | val = I915_READ(PIPESRC(pipe)); | |
66e514c1 DA |
6270 | crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1; |
6271 | crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
6272 | |
6273 | val = I915_READ(DSPSTRIDE(pipe)); | |
026b96e2 | 6274 | crtc->base.primary->fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 6275 | |
66e514c1 | 6276 | aligned_height = intel_align_height(dev, crtc->base.primary->fb->height, |
1ad292b5 JB |
6277 | plane_config->tiled); |
6278 | ||
1267a26b FF |
6279 | plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] * |
6280 | aligned_height); | |
1ad292b5 JB |
6281 | |
6282 | DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
66e514c1 DA |
6283 | pipe, plane, crtc->base.primary->fb->width, |
6284 | crtc->base.primary->fb->height, | |
6285 | crtc->base.primary->fb->bits_per_pixel, base, | |
6286 | crtc->base.primary->fb->pitches[0], | |
1ad292b5 JB |
6287 | plane_config->size); |
6288 | ||
6289 | } | |
6290 | ||
70b23a98 VS |
6291 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
6292 | struct intel_crtc_config *pipe_config) | |
6293 | { | |
6294 | struct drm_device *dev = crtc->base.dev; | |
6295 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6296 | int pipe = pipe_config->cpu_transcoder; | |
6297 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
6298 | intel_clock_t clock; | |
6299 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2; | |
6300 | int refclk = 100000; | |
6301 | ||
6302 | mutex_lock(&dev_priv->dpio_lock); | |
6303 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); | |
6304 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
6305 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
6306 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
6307 | mutex_unlock(&dev_priv->dpio_lock); | |
6308 | ||
6309 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
6310 | clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff); | |
6311 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; | |
6312 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
6313 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
6314 | ||
6315 | chv_clock(refclk, &clock); | |
6316 | ||
6317 | /* clock.dot is the fast clock */ | |
6318 | pipe_config->port_clock = clock.dot / 5; | |
6319 | } | |
6320 | ||
0e8ffe1b DV |
6321 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
6322 | struct intel_crtc_config *pipe_config) | |
6323 | { | |
6324 | struct drm_device *dev = crtc->base.dev; | |
6325 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6326 | uint32_t tmp; | |
6327 | ||
b5482bd0 ID |
6328 | if (!intel_display_power_enabled(dev_priv, |
6329 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
6330 | return false; | |
6331 | ||
e143a21c | 6332 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 6333 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 6334 | |
0e8ffe1b DV |
6335 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
6336 | if (!(tmp & PIPECONF_ENABLE)) | |
6337 | return false; | |
6338 | ||
42571aef VS |
6339 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
6340 | switch (tmp & PIPECONF_BPC_MASK) { | |
6341 | case PIPECONF_6BPC: | |
6342 | pipe_config->pipe_bpp = 18; | |
6343 | break; | |
6344 | case PIPECONF_8BPC: | |
6345 | pipe_config->pipe_bpp = 24; | |
6346 | break; | |
6347 | case PIPECONF_10BPC: | |
6348 | pipe_config->pipe_bpp = 30; | |
6349 | break; | |
6350 | default: | |
6351 | break; | |
6352 | } | |
6353 | } | |
6354 | ||
b5a9fa09 DV |
6355 | if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
6356 | pipe_config->limited_color_range = true; | |
6357 | ||
282740f7 VS |
6358 | if (INTEL_INFO(dev)->gen < 4) |
6359 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
6360 | ||
1bd1bd80 DV |
6361 | intel_get_pipe_timings(crtc, pipe_config); |
6362 | ||
2fa2fe9a DV |
6363 | i9xx_get_pfit_config(crtc, pipe_config); |
6364 | ||
6c49f241 DV |
6365 | if (INTEL_INFO(dev)->gen >= 4) { |
6366 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
6367 | pipe_config->pixel_multiplier = | |
6368 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
6369 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 6370 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
6371 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
6372 | tmp = I915_READ(DPLL(crtc->pipe)); | |
6373 | pipe_config->pixel_multiplier = | |
6374 | ((tmp & SDVO_MULTIPLIER_MASK) | |
6375 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
6376 | } else { | |
6377 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
6378 | * port and will be fixed up in the encoder->get_config | |
6379 | * function. */ | |
6380 | pipe_config->pixel_multiplier = 1; | |
6381 | } | |
8bcc2795 DV |
6382 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
6383 | if (!IS_VALLEYVIEW(dev)) { | |
6384 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); | |
6385 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
6386 | } else { |
6387 | /* Mask out read-only status bits. */ | |
6388 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
6389 | DPLL_PORTC_READY_MASK | | |
6390 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 6391 | } |
6c49f241 | 6392 | |
70b23a98 VS |
6393 | if (IS_CHERRYVIEW(dev)) |
6394 | chv_crtc_clock_get(crtc, pipe_config); | |
6395 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
6396 | vlv_crtc_clock_get(crtc, pipe_config); |
6397 | else | |
6398 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 6399 | |
0e8ffe1b DV |
6400 | return true; |
6401 | } | |
6402 | ||
dde86e2d | 6403 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
6404 | { |
6405 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13d83a67 | 6406 | struct intel_encoder *encoder; |
74cfd7ac | 6407 | u32 val, final; |
13d83a67 | 6408 | bool has_lvds = false; |
199e5d79 | 6409 | bool has_cpu_edp = false; |
199e5d79 | 6410 | bool has_panel = false; |
99eb6a01 KP |
6411 | bool has_ck505 = false; |
6412 | bool can_ssc = false; | |
13d83a67 JB |
6413 | |
6414 | /* We need to take the global config into account */ | |
b2784e15 | 6415 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
6416 | switch (encoder->type) { |
6417 | case INTEL_OUTPUT_LVDS: | |
6418 | has_panel = true; | |
6419 | has_lvds = true; | |
6420 | break; | |
6421 | case INTEL_OUTPUT_EDP: | |
6422 | has_panel = true; | |
2de6905f | 6423 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
6424 | has_cpu_edp = true; |
6425 | break; | |
13d83a67 JB |
6426 | } |
6427 | } | |
6428 | ||
99eb6a01 | 6429 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 6430 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
6431 | can_ssc = has_ck505; |
6432 | } else { | |
6433 | has_ck505 = false; | |
6434 | can_ssc = true; | |
6435 | } | |
6436 | ||
2de6905f ID |
6437 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
6438 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
6439 | |
6440 | /* Ironlake: try to setup display ref clock before DPLL | |
6441 | * enabling. This is only under driver's control after | |
6442 | * PCH B stepping, previous chipset stepping should be | |
6443 | * ignoring this setting. | |
6444 | */ | |
74cfd7ac CW |
6445 | val = I915_READ(PCH_DREF_CONTROL); |
6446 | ||
6447 | /* As we must carefully and slowly disable/enable each source in turn, | |
6448 | * compute the final state we want first and check if we need to | |
6449 | * make any changes at all. | |
6450 | */ | |
6451 | final = val; | |
6452 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
6453 | if (has_ck505) | |
6454 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
6455 | else | |
6456 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
6457 | ||
6458 | final &= ~DREF_SSC_SOURCE_MASK; | |
6459 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
6460 | final &= ~DREF_SSC1_ENABLE; | |
6461 | ||
6462 | if (has_panel) { | |
6463 | final |= DREF_SSC_SOURCE_ENABLE; | |
6464 | ||
6465 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
6466 | final |= DREF_SSC1_ENABLE; | |
6467 | ||
6468 | if (has_cpu_edp) { | |
6469 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
6470 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
6471 | else | |
6472 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
6473 | } else | |
6474 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
6475 | } else { | |
6476 | final |= DREF_SSC_SOURCE_DISABLE; | |
6477 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
6478 | } | |
6479 | ||
6480 | if (final == val) | |
6481 | return; | |
6482 | ||
13d83a67 | 6483 | /* Always enable nonspread source */ |
74cfd7ac | 6484 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 6485 | |
99eb6a01 | 6486 | if (has_ck505) |
74cfd7ac | 6487 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 6488 | else |
74cfd7ac | 6489 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 6490 | |
199e5d79 | 6491 | if (has_panel) { |
74cfd7ac CW |
6492 | val &= ~DREF_SSC_SOURCE_MASK; |
6493 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 6494 | |
199e5d79 | 6495 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 6496 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 6497 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 6498 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 6499 | } else |
74cfd7ac | 6500 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
6501 | |
6502 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 6503 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
6504 | POSTING_READ(PCH_DREF_CONTROL); |
6505 | udelay(200); | |
6506 | ||
74cfd7ac | 6507 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
6508 | |
6509 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 6510 | if (has_cpu_edp) { |
99eb6a01 | 6511 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 6512 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 6513 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 6514 | } else |
74cfd7ac | 6515 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 6516 | } else |
74cfd7ac | 6517 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 6518 | |
74cfd7ac | 6519 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
6520 | POSTING_READ(PCH_DREF_CONTROL); |
6521 | udelay(200); | |
6522 | } else { | |
6523 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
6524 | ||
74cfd7ac | 6525 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
6526 | |
6527 | /* Turn off CPU output */ | |
74cfd7ac | 6528 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 6529 | |
74cfd7ac | 6530 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
6531 | POSTING_READ(PCH_DREF_CONTROL); |
6532 | udelay(200); | |
6533 | ||
6534 | /* Turn off the SSC source */ | |
74cfd7ac CW |
6535 | val &= ~DREF_SSC_SOURCE_MASK; |
6536 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
6537 | |
6538 | /* Turn off SSC1 */ | |
74cfd7ac | 6539 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 6540 | |
74cfd7ac | 6541 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
6542 | POSTING_READ(PCH_DREF_CONTROL); |
6543 | udelay(200); | |
6544 | } | |
74cfd7ac CW |
6545 | |
6546 | BUG_ON(val != final); | |
13d83a67 JB |
6547 | } |
6548 | ||
f31f2d55 | 6549 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 6550 | { |
f31f2d55 | 6551 | uint32_t tmp; |
dde86e2d | 6552 | |
0ff066a9 PZ |
6553 | tmp = I915_READ(SOUTH_CHICKEN2); |
6554 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
6555 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 6556 | |
0ff066a9 PZ |
6557 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
6558 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
6559 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 6560 | |
0ff066a9 PZ |
6561 | tmp = I915_READ(SOUTH_CHICKEN2); |
6562 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
6563 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 6564 | |
0ff066a9 PZ |
6565 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
6566 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
6567 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
6568 | } |
6569 | ||
6570 | /* WaMPhyProgramming:hsw */ | |
6571 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
6572 | { | |
6573 | uint32_t tmp; | |
dde86e2d PZ |
6574 | |
6575 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
6576 | tmp &= ~(0xFF << 24); | |
6577 | tmp |= (0x12 << 24); | |
6578 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
6579 | ||
dde86e2d PZ |
6580 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
6581 | tmp |= (1 << 11); | |
6582 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
6583 | ||
6584 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
6585 | tmp |= (1 << 11); | |
6586 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
6587 | ||
dde86e2d PZ |
6588 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
6589 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
6590 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
6591 | ||
6592 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
6593 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
6594 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
6595 | ||
0ff066a9 PZ |
6596 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
6597 | tmp &= ~(7 << 13); | |
6598 | tmp |= (5 << 13); | |
6599 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 6600 | |
0ff066a9 PZ |
6601 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
6602 | tmp &= ~(7 << 13); | |
6603 | tmp |= (5 << 13); | |
6604 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
6605 | |
6606 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
6607 | tmp &= ~0xFF; | |
6608 | tmp |= 0x1C; | |
6609 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
6610 | ||
6611 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
6612 | tmp &= ~0xFF; | |
6613 | tmp |= 0x1C; | |
6614 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
6615 | ||
6616 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
6617 | tmp &= ~(0xFF << 16); | |
6618 | tmp |= (0x1C << 16); | |
6619 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
6620 | ||
6621 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
6622 | tmp &= ~(0xFF << 16); | |
6623 | tmp |= (0x1C << 16); | |
6624 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
6625 | ||
0ff066a9 PZ |
6626 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
6627 | tmp |= (1 << 27); | |
6628 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 6629 | |
0ff066a9 PZ |
6630 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
6631 | tmp |= (1 << 27); | |
6632 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 6633 | |
0ff066a9 PZ |
6634 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
6635 | tmp &= ~(0xF << 28); | |
6636 | tmp |= (4 << 28); | |
6637 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 6638 | |
0ff066a9 PZ |
6639 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
6640 | tmp &= ~(0xF << 28); | |
6641 | tmp |= (4 << 28); | |
6642 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
6643 | } |
6644 | ||
2fa86a1f PZ |
6645 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
6646 | * Programming" based on the parameters passed: | |
6647 | * - Sequence to enable CLKOUT_DP | |
6648 | * - Sequence to enable CLKOUT_DP without spread | |
6649 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
6650 | */ | |
6651 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
6652 | bool with_fdi) | |
f31f2d55 PZ |
6653 | { |
6654 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
6655 | uint32_t reg, tmp; |
6656 | ||
6657 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
6658 | with_spread = true; | |
6659 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && | |
6660 | with_fdi, "LP PCH doesn't have FDI\n")) | |
6661 | with_fdi = false; | |
f31f2d55 PZ |
6662 | |
6663 | mutex_lock(&dev_priv->dpio_lock); | |
6664 | ||
6665 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
6666 | tmp &= ~SBI_SSCCTL_DISABLE; | |
6667 | tmp |= SBI_SSCCTL_PATHALT; | |
6668 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
6669 | ||
6670 | udelay(24); | |
6671 | ||
2fa86a1f PZ |
6672 | if (with_spread) { |
6673 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
6674 | tmp &= ~SBI_SSCCTL_PATHALT; | |
6675 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 6676 | |
2fa86a1f PZ |
6677 | if (with_fdi) { |
6678 | lpt_reset_fdi_mphy(dev_priv); | |
6679 | lpt_program_fdi_mphy(dev_priv); | |
6680 | } | |
6681 | } | |
dde86e2d | 6682 | |
2fa86a1f PZ |
6683 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
6684 | SBI_GEN0 : SBI_DBUFF0; | |
6685 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
6686 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
6687 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 DV |
6688 | |
6689 | mutex_unlock(&dev_priv->dpio_lock); | |
dde86e2d PZ |
6690 | } |
6691 | ||
47701c3b PZ |
6692 | /* Sequence to disable CLKOUT_DP */ |
6693 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
6694 | { | |
6695 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6696 | uint32_t reg, tmp; | |
6697 | ||
6698 | mutex_lock(&dev_priv->dpio_lock); | |
6699 | ||
6700 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? | |
6701 | SBI_GEN0 : SBI_DBUFF0; | |
6702 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
6703 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
6704 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
6705 | ||
6706 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
6707 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
6708 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
6709 | tmp |= SBI_SSCCTL_PATHALT; | |
6710 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
6711 | udelay(32); | |
6712 | } | |
6713 | tmp |= SBI_SSCCTL_DISABLE; | |
6714 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
6715 | } | |
6716 | ||
6717 | mutex_unlock(&dev_priv->dpio_lock); | |
6718 | } | |
6719 | ||
bf8fa3d3 PZ |
6720 | static void lpt_init_pch_refclk(struct drm_device *dev) |
6721 | { | |
bf8fa3d3 PZ |
6722 | struct intel_encoder *encoder; |
6723 | bool has_vga = false; | |
6724 | ||
b2784e15 | 6725 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
6726 | switch (encoder->type) { |
6727 | case INTEL_OUTPUT_ANALOG: | |
6728 | has_vga = true; | |
6729 | break; | |
6730 | } | |
6731 | } | |
6732 | ||
47701c3b PZ |
6733 | if (has_vga) |
6734 | lpt_enable_clkout_dp(dev, true, true); | |
6735 | else | |
6736 | lpt_disable_clkout_dp(dev); | |
bf8fa3d3 PZ |
6737 | } |
6738 | ||
dde86e2d PZ |
6739 | /* |
6740 | * Initialize reference clocks when the driver loads | |
6741 | */ | |
6742 | void intel_init_pch_refclk(struct drm_device *dev) | |
6743 | { | |
6744 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
6745 | ironlake_init_pch_refclk(dev); | |
6746 | else if (HAS_PCH_LPT(dev)) | |
6747 | lpt_init_pch_refclk(dev); | |
6748 | } | |
6749 | ||
d9d444cb JB |
6750 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
6751 | { | |
6752 | struct drm_device *dev = crtc->dev; | |
6753 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6754 | struct intel_encoder *encoder; | |
d9d444cb JB |
6755 | int num_connectors = 0; |
6756 | bool is_lvds = false; | |
6757 | ||
6c2b7c12 | 6758 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
d9d444cb JB |
6759 | switch (encoder->type) { |
6760 | case INTEL_OUTPUT_LVDS: | |
6761 | is_lvds = true; | |
6762 | break; | |
d9d444cb JB |
6763 | } |
6764 | num_connectors++; | |
6765 | } | |
6766 | ||
6767 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 6768 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 6769 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 6770 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
6771 | } |
6772 | ||
6773 | return 120000; | |
6774 | } | |
6775 | ||
6ff93609 | 6776 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 6777 | { |
c8203565 | 6778 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
6779 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6780 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
6781 | uint32_t val; |
6782 | ||
78114071 | 6783 | val = 0; |
c8203565 | 6784 | |
965e0c48 | 6785 | switch (intel_crtc->config.pipe_bpp) { |
c8203565 | 6786 | case 18: |
dfd07d72 | 6787 | val |= PIPECONF_6BPC; |
c8203565 PZ |
6788 | break; |
6789 | case 24: | |
dfd07d72 | 6790 | val |= PIPECONF_8BPC; |
c8203565 PZ |
6791 | break; |
6792 | case 30: | |
dfd07d72 | 6793 | val |= PIPECONF_10BPC; |
c8203565 PZ |
6794 | break; |
6795 | case 36: | |
dfd07d72 | 6796 | val |= PIPECONF_12BPC; |
c8203565 PZ |
6797 | break; |
6798 | default: | |
cc769b62 PZ |
6799 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
6800 | BUG(); | |
c8203565 PZ |
6801 | } |
6802 | ||
d8b32247 | 6803 | if (intel_crtc->config.dither) |
c8203565 PZ |
6804 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
6805 | ||
6ff93609 | 6806 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
6807 | val |= PIPECONF_INTERLACED_ILK; |
6808 | else | |
6809 | val |= PIPECONF_PROGRESSIVE; | |
6810 | ||
50f3b016 | 6811 | if (intel_crtc->config.limited_color_range) |
3685a8f3 | 6812 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 6813 | |
c8203565 PZ |
6814 | I915_WRITE(PIPECONF(pipe), val); |
6815 | POSTING_READ(PIPECONF(pipe)); | |
6816 | } | |
6817 | ||
86d3efce VS |
6818 | /* |
6819 | * Set up the pipe CSC unit. | |
6820 | * | |
6821 | * Currently only full range RGB to limited range RGB conversion | |
6822 | * is supported, but eventually this should handle various | |
6823 | * RGB<->YCbCr scenarios as well. | |
6824 | */ | |
50f3b016 | 6825 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
6826 | { |
6827 | struct drm_device *dev = crtc->dev; | |
6828 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6829 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6830 | int pipe = intel_crtc->pipe; | |
6831 | uint16_t coeff = 0x7800; /* 1.0 */ | |
6832 | ||
6833 | /* | |
6834 | * TODO: Check what kind of values actually come out of the pipe | |
6835 | * with these coeff/postoff values and adjust to get the best | |
6836 | * accuracy. Perhaps we even need to take the bpc value into | |
6837 | * consideration. | |
6838 | */ | |
6839 | ||
50f3b016 | 6840 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
6841 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
6842 | ||
6843 | /* | |
6844 | * GY/GU and RY/RU should be the other way around according | |
6845 | * to BSpec, but reality doesn't agree. Just set them up in | |
6846 | * a way that results in the correct picture. | |
6847 | */ | |
6848 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
6849 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
6850 | ||
6851 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
6852 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
6853 | ||
6854 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
6855 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
6856 | ||
6857 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
6858 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
6859 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
6860 | ||
6861 | if (INTEL_INFO(dev)->gen > 6) { | |
6862 | uint16_t postoff = 0; | |
6863 | ||
50f3b016 | 6864 | if (intel_crtc->config.limited_color_range) |
32cf0cb0 | 6865 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
6866 | |
6867 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
6868 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
6869 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
6870 | ||
6871 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
6872 | } else { | |
6873 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
6874 | ||
50f3b016 | 6875 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
6876 | mode |= CSC_BLACK_SCREEN_OFFSET; |
6877 | ||
6878 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
6879 | } | |
6880 | } | |
6881 | ||
6ff93609 | 6882 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 6883 | { |
756f85cf PZ |
6884 | struct drm_device *dev = crtc->dev; |
6885 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 6886 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 6887 | enum pipe pipe = intel_crtc->pipe; |
3b117c8f | 6888 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee2b0b38 PZ |
6889 | uint32_t val; |
6890 | ||
3eff4faa | 6891 | val = 0; |
ee2b0b38 | 6892 | |
756f85cf | 6893 | if (IS_HASWELL(dev) && intel_crtc->config.dither) |
ee2b0b38 PZ |
6894 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
6895 | ||
6ff93609 | 6896 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
6897 | val |= PIPECONF_INTERLACED_ILK; |
6898 | else | |
6899 | val |= PIPECONF_PROGRESSIVE; | |
6900 | ||
702e7a56 PZ |
6901 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
6902 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
6903 | |
6904 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
6905 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf PZ |
6906 | |
6907 | if (IS_BROADWELL(dev)) { | |
6908 | val = 0; | |
6909 | ||
6910 | switch (intel_crtc->config.pipe_bpp) { | |
6911 | case 18: | |
6912 | val |= PIPEMISC_DITHER_6_BPC; | |
6913 | break; | |
6914 | case 24: | |
6915 | val |= PIPEMISC_DITHER_8_BPC; | |
6916 | break; | |
6917 | case 30: | |
6918 | val |= PIPEMISC_DITHER_10_BPC; | |
6919 | break; | |
6920 | case 36: | |
6921 | val |= PIPEMISC_DITHER_12_BPC; | |
6922 | break; | |
6923 | default: | |
6924 | /* Case prevented by pipe_config_set_bpp. */ | |
6925 | BUG(); | |
6926 | } | |
6927 | ||
6928 | if (intel_crtc->config.dither) | |
6929 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; | |
6930 | ||
6931 | I915_WRITE(PIPEMISC(pipe), val); | |
6932 | } | |
ee2b0b38 PZ |
6933 | } |
6934 | ||
6591c6e4 | 6935 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
6591c6e4 PZ |
6936 | intel_clock_t *clock, |
6937 | bool *has_reduced_clock, | |
6938 | intel_clock_t *reduced_clock) | |
6939 | { | |
6940 | struct drm_device *dev = crtc->dev; | |
6941 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6942 | struct intel_encoder *intel_encoder; | |
6943 | int refclk; | |
d4906093 | 6944 | const intel_limit_t *limit; |
a16af721 | 6945 | bool ret, is_lvds = false; |
79e53945 | 6946 | |
6591c6e4 PZ |
6947 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
6948 | switch (intel_encoder->type) { | |
79e53945 JB |
6949 | case INTEL_OUTPUT_LVDS: |
6950 | is_lvds = true; | |
6951 | break; | |
79e53945 JB |
6952 | } |
6953 | } | |
6954 | ||
d9d444cb | 6955 | refclk = ironlake_get_refclk(crtc); |
79e53945 | 6956 | |
d4906093 ML |
6957 | /* |
6958 | * Returns a set of divisors for the desired target clock with the given | |
6959 | * refclk, or FALSE. The returned values represent the clock equation: | |
6960 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
6961 | */ | |
1b894b59 | 6962 | limit = intel_limit(crtc, refclk); |
ff9a6750 DV |
6963 | ret = dev_priv->display.find_dpll(limit, crtc, |
6964 | to_intel_crtc(crtc)->config.port_clock, | |
ee9300bb | 6965 | refclk, NULL, clock); |
6591c6e4 PZ |
6966 | if (!ret) |
6967 | return false; | |
cda4b7d3 | 6968 | |
ddc9003c | 6969 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
6970 | /* |
6971 | * Ensure we match the reduced clock's P to the target clock. | |
6972 | * If the clocks don't match, we can't switch the display clock | |
6973 | * by using the FP0/FP1. In such case we will disable the LVDS | |
6974 | * downclock feature. | |
6975 | */ | |
ee9300bb DV |
6976 | *has_reduced_clock = |
6977 | dev_priv->display.find_dpll(limit, crtc, | |
6978 | dev_priv->lvds_downclock, | |
6979 | refclk, clock, | |
6980 | reduced_clock); | |
652c393a | 6981 | } |
61e9653f | 6982 | |
6591c6e4 PZ |
6983 | return true; |
6984 | } | |
6985 | ||
d4b1931c PZ |
6986 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
6987 | { | |
6988 | /* | |
6989 | * Account for spread spectrum to avoid | |
6990 | * oversubscribing the link. Max center spread | |
6991 | * is 2.5%; use 5% for safety's sake. | |
6992 | */ | |
6993 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 6994 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
6995 | } |
6996 | ||
7429e9d4 | 6997 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 6998 | { |
7429e9d4 | 6999 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
7000 | } |
7001 | ||
de13a2e3 | 7002 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
7429e9d4 | 7003 | u32 *fp, |
9a7c7890 | 7004 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 7005 | { |
de13a2e3 | 7006 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
7007 | struct drm_device *dev = crtc->dev; |
7008 | struct drm_i915_private *dev_priv = dev->dev_private; | |
de13a2e3 PZ |
7009 | struct intel_encoder *intel_encoder; |
7010 | uint32_t dpll; | |
6cc5f341 | 7011 | int factor, num_connectors = 0; |
09ede541 | 7012 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 7013 | |
de13a2e3 PZ |
7014 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
7015 | switch (intel_encoder->type) { | |
79e53945 JB |
7016 | case INTEL_OUTPUT_LVDS: |
7017 | is_lvds = true; | |
7018 | break; | |
7019 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 7020 | case INTEL_OUTPUT_HDMI: |
79e53945 | 7021 | is_sdvo = true; |
79e53945 | 7022 | break; |
79e53945 | 7023 | } |
43565a06 | 7024 | |
c751ce4f | 7025 | num_connectors++; |
79e53945 | 7026 | } |
79e53945 | 7027 | |
c1858123 | 7028 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
7029 | factor = 21; |
7030 | if (is_lvds) { | |
7031 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 7032 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 7033 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 7034 | factor = 25; |
09ede541 | 7035 | } else if (intel_crtc->config.sdvo_tv_clock) |
8febb297 | 7036 | factor = 20; |
c1858123 | 7037 | |
7429e9d4 | 7038 | if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor)) |
7d0ac5b7 | 7039 | *fp |= FP_CB_TUNE; |
2c07245f | 7040 | |
9a7c7890 DV |
7041 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
7042 | *fp2 |= FP_CB_TUNE; | |
7043 | ||
5eddb70b | 7044 | dpll = 0; |
2c07245f | 7045 | |
a07d6787 EA |
7046 | if (is_lvds) |
7047 | dpll |= DPLLB_MODE_LVDS; | |
7048 | else | |
7049 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 7050 | |
ef1b460d DV |
7051 | dpll |= (intel_crtc->config.pixel_multiplier - 1) |
7052 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | |
198a037f DV |
7053 | |
7054 | if (is_sdvo) | |
4a33e48d | 7055 | dpll |= DPLL_SDVO_HIGH_SPEED; |
9566e9af | 7056 | if (intel_crtc->config.has_dp_encoder) |
4a33e48d | 7057 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 7058 | |
a07d6787 | 7059 | /* compute bitmask from p1 value */ |
7429e9d4 | 7060 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 7061 | /* also FPA1 */ |
7429e9d4 | 7062 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 7063 | |
7429e9d4 | 7064 | switch (intel_crtc->config.dpll.p2) { |
a07d6787 EA |
7065 | case 5: |
7066 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7067 | break; | |
7068 | case 7: | |
7069 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7070 | break; | |
7071 | case 10: | |
7072 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7073 | break; | |
7074 | case 14: | |
7075 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7076 | break; | |
79e53945 JB |
7077 | } |
7078 | ||
b4c09f3b | 7079 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 7080 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
7081 | else |
7082 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7083 | ||
959e16d6 | 7084 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
7085 | } |
7086 | ||
7087 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, | |
de13a2e3 PZ |
7088 | int x, int y, |
7089 | struct drm_framebuffer *fb) | |
7090 | { | |
7091 | struct drm_device *dev = crtc->dev; | |
de13a2e3 | 7092 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
de13a2e3 PZ |
7093 | int num_connectors = 0; |
7094 | intel_clock_t clock, reduced_clock; | |
cbbab5bd | 7095 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 7096 | bool ok, has_reduced_clock = false; |
8b47047b | 7097 | bool is_lvds = false; |
de13a2e3 | 7098 | struct intel_encoder *encoder; |
e2b78267 | 7099 | struct intel_shared_dpll *pll; |
de13a2e3 PZ |
7100 | |
7101 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
7102 | switch (encoder->type) { | |
7103 | case INTEL_OUTPUT_LVDS: | |
7104 | is_lvds = true; | |
7105 | break; | |
de13a2e3 PZ |
7106 | } |
7107 | ||
7108 | num_connectors++; | |
a07d6787 | 7109 | } |
79e53945 | 7110 | |
5dc5298b PZ |
7111 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
7112 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 7113 | |
ff9a6750 | 7114 | ok = ironlake_compute_clocks(crtc, &clock, |
de13a2e3 | 7115 | &has_reduced_clock, &reduced_clock); |
ee9300bb | 7116 | if (!ok && !intel_crtc->config.clock_set) { |
de13a2e3 PZ |
7117 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
7118 | return -EINVAL; | |
79e53945 | 7119 | } |
f47709a9 DV |
7120 | /* Compat-code for transition, will disappear. */ |
7121 | if (!intel_crtc->config.clock_set) { | |
7122 | intel_crtc->config.dpll.n = clock.n; | |
7123 | intel_crtc->config.dpll.m1 = clock.m1; | |
7124 | intel_crtc->config.dpll.m2 = clock.m2; | |
7125 | intel_crtc->config.dpll.p1 = clock.p1; | |
7126 | intel_crtc->config.dpll.p2 = clock.p2; | |
7127 | } | |
79e53945 | 7128 | |
5dc5298b | 7129 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
8b47047b | 7130 | if (intel_crtc->config.has_pch_encoder) { |
7429e9d4 | 7131 | fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll); |
cbbab5bd | 7132 | if (has_reduced_clock) |
7429e9d4 | 7133 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 7134 | |
7429e9d4 | 7135 | dpll = ironlake_compute_dpll(intel_crtc, |
cbbab5bd DV |
7136 | &fp, &reduced_clock, |
7137 | has_reduced_clock ? &fp2 : NULL); | |
7138 | ||
959e16d6 | 7139 | intel_crtc->config.dpll_hw_state.dpll = dpll; |
66e985c0 DV |
7140 | intel_crtc->config.dpll_hw_state.fp0 = fp; |
7141 | if (has_reduced_clock) | |
7142 | intel_crtc->config.dpll_hw_state.fp1 = fp2; | |
7143 | else | |
7144 | intel_crtc->config.dpll_hw_state.fp1 = fp; | |
7145 | ||
b89a1d39 | 7146 | pll = intel_get_shared_dpll(intel_crtc); |
ee7b9f93 | 7147 | if (pll == NULL) { |
84f44ce7 | 7148 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
29407aab | 7149 | pipe_name(intel_crtc->pipe)); |
4b645f14 JB |
7150 | return -EINVAL; |
7151 | } | |
ee7b9f93 | 7152 | } else |
e72f9fbf | 7153 | intel_put_shared_dpll(intel_crtc); |
79e53945 | 7154 | |
d330a953 | 7155 | if (is_lvds && has_reduced_clock && i915.powersave) |
bcd644e0 DV |
7156 | intel_crtc->lowfreq_avail = true; |
7157 | else | |
7158 | intel_crtc->lowfreq_avail = false; | |
e2b78267 | 7159 | |
c8f7a0db | 7160 | return 0; |
79e53945 JB |
7161 | } |
7162 | ||
eb14cb74 VS |
7163 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
7164 | struct intel_link_m_n *m_n) | |
7165 | { | |
7166 | struct drm_device *dev = crtc->base.dev; | |
7167 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7168 | enum pipe pipe = crtc->pipe; | |
7169 | ||
7170 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
7171 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
7172 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
7173 | & ~TU_SIZE_MASK; | |
7174 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
7175 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
7176 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7177 | } | |
7178 | ||
7179 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
7180 | enum transcoder transcoder, | |
b95af8be VK |
7181 | struct intel_link_m_n *m_n, |
7182 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
7183 | { |
7184 | struct drm_device *dev = crtc->base.dev; | |
7185 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 7186 | enum pipe pipe = crtc->pipe; |
72419203 | 7187 | |
eb14cb74 VS |
7188 | if (INTEL_INFO(dev)->gen >= 5) { |
7189 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
7190 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
7191 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
7192 | & ~TU_SIZE_MASK; | |
7193 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
7194 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
7195 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
7196 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
7197 | * gen < 8) and if DRRS is supported (to make sure the | |
7198 | * registers are not unnecessarily read). | |
7199 | */ | |
7200 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
7201 | crtc->config.has_drrs) { | |
7202 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); | |
7203 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
7204 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
7205 | & ~TU_SIZE_MASK; | |
7206 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
7207 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
7208 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7209 | } | |
eb14cb74 VS |
7210 | } else { |
7211 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
7212 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
7213 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
7214 | & ~TU_SIZE_MASK; | |
7215 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
7216 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
7217 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7218 | } | |
7219 | } | |
7220 | ||
7221 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
7222 | struct intel_crtc_config *pipe_config) | |
7223 | { | |
7224 | if (crtc->config.has_pch_encoder) | |
7225 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); | |
7226 | else | |
7227 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
7228 | &pipe_config->dp_m_n, |
7229 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 7230 | } |
72419203 | 7231 | |
eb14cb74 VS |
7232 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
7233 | struct intel_crtc_config *pipe_config) | |
7234 | { | |
7235 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 7236 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
7237 | } |
7238 | ||
2fa2fe9a DV |
7239 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
7240 | struct intel_crtc_config *pipe_config) | |
7241 | { | |
7242 | struct drm_device *dev = crtc->base.dev; | |
7243 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7244 | uint32_t tmp; | |
7245 | ||
7246 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
7247 | ||
7248 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 7249 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
7250 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
7251 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
7252 | |
7253 | /* We currently do not free assignements of panel fitters on | |
7254 | * ivb/hsw (since we don't use the higher upscaling modes which | |
7255 | * differentiates them) so just WARN about this case for now. */ | |
7256 | if (IS_GEN7(dev)) { | |
7257 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
7258 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
7259 | } | |
2fa2fe9a | 7260 | } |
79e53945 JB |
7261 | } |
7262 | ||
4c6baa59 JB |
7263 | static void ironlake_get_plane_config(struct intel_crtc *crtc, |
7264 | struct intel_plane_config *plane_config) | |
7265 | { | |
7266 | struct drm_device *dev = crtc->base.dev; | |
7267 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7268 | u32 val, base, offset; | |
7269 | int pipe = crtc->pipe, plane = crtc->plane; | |
7270 | int fourcc, pixel_format; | |
7271 | int aligned_height; | |
7272 | ||
66e514c1 DA |
7273 | crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL); |
7274 | if (!crtc->base.primary->fb) { | |
4c6baa59 JB |
7275 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
7276 | return; | |
7277 | } | |
7278 | ||
7279 | val = I915_READ(DSPCNTR(plane)); | |
7280 | ||
7281 | if (INTEL_INFO(dev)->gen >= 4) | |
7282 | if (val & DISPPLANE_TILED) | |
7283 | plane_config->tiled = true; | |
7284 | ||
7285 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
7286 | fourcc = intel_format_to_fourcc(pixel_format); | |
66e514c1 DA |
7287 | crtc->base.primary->fb->pixel_format = fourcc; |
7288 | crtc->base.primary->fb->bits_per_pixel = | |
4c6baa59 JB |
7289 | drm_format_plane_cpp(fourcc, 0) * 8; |
7290 | ||
7291 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
7292 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
7293 | offset = I915_READ(DSPOFFSET(plane)); | |
7294 | } else { | |
7295 | if (plane_config->tiled) | |
7296 | offset = I915_READ(DSPTILEOFF(plane)); | |
7297 | else | |
7298 | offset = I915_READ(DSPLINOFF(plane)); | |
7299 | } | |
7300 | plane_config->base = base; | |
7301 | ||
7302 | val = I915_READ(PIPESRC(pipe)); | |
66e514c1 DA |
7303 | crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1; |
7304 | crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
7305 | |
7306 | val = I915_READ(DSPSTRIDE(pipe)); | |
026b96e2 | 7307 | crtc->base.primary->fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 7308 | |
66e514c1 | 7309 | aligned_height = intel_align_height(dev, crtc->base.primary->fb->height, |
4c6baa59 JB |
7310 | plane_config->tiled); |
7311 | ||
1267a26b FF |
7312 | plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] * |
7313 | aligned_height); | |
4c6baa59 JB |
7314 | |
7315 | DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
66e514c1 DA |
7316 | pipe, plane, crtc->base.primary->fb->width, |
7317 | crtc->base.primary->fb->height, | |
7318 | crtc->base.primary->fb->bits_per_pixel, base, | |
7319 | crtc->base.primary->fb->pitches[0], | |
4c6baa59 JB |
7320 | plane_config->size); |
7321 | } | |
7322 | ||
0e8ffe1b DV |
7323 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
7324 | struct intel_crtc_config *pipe_config) | |
7325 | { | |
7326 | struct drm_device *dev = crtc->base.dev; | |
7327 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7328 | uint32_t tmp; | |
7329 | ||
930e8c9e PZ |
7330 | if (!intel_display_power_enabled(dev_priv, |
7331 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
7332 | return false; | |
7333 | ||
e143a21c | 7334 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 7335 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 7336 | |
0e8ffe1b DV |
7337 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
7338 | if (!(tmp & PIPECONF_ENABLE)) | |
7339 | return false; | |
7340 | ||
42571aef VS |
7341 | switch (tmp & PIPECONF_BPC_MASK) { |
7342 | case PIPECONF_6BPC: | |
7343 | pipe_config->pipe_bpp = 18; | |
7344 | break; | |
7345 | case PIPECONF_8BPC: | |
7346 | pipe_config->pipe_bpp = 24; | |
7347 | break; | |
7348 | case PIPECONF_10BPC: | |
7349 | pipe_config->pipe_bpp = 30; | |
7350 | break; | |
7351 | case PIPECONF_12BPC: | |
7352 | pipe_config->pipe_bpp = 36; | |
7353 | break; | |
7354 | default: | |
7355 | break; | |
7356 | } | |
7357 | ||
b5a9fa09 DV |
7358 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
7359 | pipe_config->limited_color_range = true; | |
7360 | ||
ab9412ba | 7361 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
7362 | struct intel_shared_dpll *pll; |
7363 | ||
88adfff1 DV |
7364 | pipe_config->has_pch_encoder = true; |
7365 | ||
627eb5a3 DV |
7366 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
7367 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
7368 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
7369 | |
7370 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 7371 | |
c0d43d62 | 7372 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
7373 | pipe_config->shared_dpll = |
7374 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
7375 | } else { |
7376 | tmp = I915_READ(PCH_DPLL_SEL); | |
7377 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
7378 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
7379 | else | |
7380 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
7381 | } | |
66e985c0 DV |
7382 | |
7383 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
7384 | ||
7385 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
7386 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
7387 | |
7388 | tmp = pipe_config->dpll_hw_state.dpll; | |
7389 | pipe_config->pixel_multiplier = | |
7390 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
7391 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
7392 | |
7393 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
7394 | } else { |
7395 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
7396 | } |
7397 | ||
1bd1bd80 DV |
7398 | intel_get_pipe_timings(crtc, pipe_config); |
7399 | ||
2fa2fe9a DV |
7400 | ironlake_get_pfit_config(crtc, pipe_config); |
7401 | ||
0e8ffe1b DV |
7402 | return true; |
7403 | } | |
7404 | ||
be256dc7 PZ |
7405 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
7406 | { | |
7407 | struct drm_device *dev = dev_priv->dev; | |
be256dc7 | 7408 | struct intel_crtc *crtc; |
be256dc7 | 7409 | |
d3fcc808 | 7410 | for_each_intel_crtc(dev, crtc) |
798183c5 | 7411 | WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
7412 | pipe_name(crtc->pipe)); |
7413 | ||
7414 | WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); | |
8cc3e169 DV |
7415 | WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); |
7416 | WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); | |
7417 | WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
be256dc7 PZ |
7418 | WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); |
7419 | WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
7420 | "CPU PWM1 enabled\n"); | |
c5107b87 PZ |
7421 | if (IS_HASWELL(dev)) |
7422 | WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, | |
7423 | "CPU PWM2 enabled\n"); | |
be256dc7 PZ |
7424 | WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
7425 | "PCH PWM1 enabled\n"); | |
7426 | WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, | |
7427 | "Utility pin enabled\n"); | |
7428 | WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); | |
7429 | ||
9926ada1 PZ |
7430 | /* |
7431 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
7432 | * interrupts remain enabled. We used to check for that, but since it's | |
7433 | * gen-specific and since we only disable LCPLL after we fully disable | |
7434 | * the interrupts, the check below should be enough. | |
7435 | */ | |
9df7575f | 7436 | WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
7437 | } |
7438 | ||
9ccd5aeb PZ |
7439 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
7440 | { | |
7441 | struct drm_device *dev = dev_priv->dev; | |
7442 | ||
7443 | if (IS_HASWELL(dev)) | |
7444 | return I915_READ(D_COMP_HSW); | |
7445 | else | |
7446 | return I915_READ(D_COMP_BDW); | |
7447 | } | |
7448 | ||
3c4c9b81 PZ |
7449 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
7450 | { | |
7451 | struct drm_device *dev = dev_priv->dev; | |
7452 | ||
7453 | if (IS_HASWELL(dev)) { | |
7454 | mutex_lock(&dev_priv->rps.hw_lock); | |
7455 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
7456 | val)) | |
f475dadf | 7457 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
7458 | mutex_unlock(&dev_priv->rps.hw_lock); |
7459 | } else { | |
9ccd5aeb PZ |
7460 | I915_WRITE(D_COMP_BDW, val); |
7461 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 7462 | } |
be256dc7 PZ |
7463 | } |
7464 | ||
7465 | /* | |
7466 | * This function implements pieces of two sequences from BSpec: | |
7467 | * - Sequence for display software to disable LCPLL | |
7468 | * - Sequence for display software to allow package C8+ | |
7469 | * The steps implemented here are just the steps that actually touch the LCPLL | |
7470 | * register. Callers should take care of disabling all the display engine | |
7471 | * functions, doing the mode unset, fixing interrupts, etc. | |
7472 | */ | |
6ff58d53 PZ |
7473 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
7474 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
7475 | { |
7476 | uint32_t val; | |
7477 | ||
7478 | assert_can_disable_lcpll(dev_priv); | |
7479 | ||
7480 | val = I915_READ(LCPLL_CTL); | |
7481 | ||
7482 | if (switch_to_fclk) { | |
7483 | val |= LCPLL_CD_SOURCE_FCLK; | |
7484 | I915_WRITE(LCPLL_CTL, val); | |
7485 | ||
7486 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
7487 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
7488 | DRM_ERROR("Switching to FCLK failed\n"); | |
7489 | ||
7490 | val = I915_READ(LCPLL_CTL); | |
7491 | } | |
7492 | ||
7493 | val |= LCPLL_PLL_DISABLE; | |
7494 | I915_WRITE(LCPLL_CTL, val); | |
7495 | POSTING_READ(LCPLL_CTL); | |
7496 | ||
7497 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
7498 | DRM_ERROR("LCPLL still locked\n"); | |
7499 | ||
9ccd5aeb | 7500 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 7501 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 7502 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
7503 | ndelay(100); |
7504 | ||
9ccd5aeb PZ |
7505 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
7506 | 1)) | |
be256dc7 PZ |
7507 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
7508 | ||
7509 | if (allow_power_down) { | |
7510 | val = I915_READ(LCPLL_CTL); | |
7511 | val |= LCPLL_POWER_DOWN_ALLOW; | |
7512 | I915_WRITE(LCPLL_CTL, val); | |
7513 | POSTING_READ(LCPLL_CTL); | |
7514 | } | |
7515 | } | |
7516 | ||
7517 | /* | |
7518 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
7519 | * source. | |
7520 | */ | |
6ff58d53 | 7521 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
7522 | { |
7523 | uint32_t val; | |
a8a8bd54 | 7524 | unsigned long irqflags; |
be256dc7 PZ |
7525 | |
7526 | val = I915_READ(LCPLL_CTL); | |
7527 | ||
7528 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
7529 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
7530 | return; | |
7531 | ||
a8a8bd54 PZ |
7532 | /* |
7533 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
7534 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
7535 | * | |
7536 | * The other problem is that hsw_restore_lcpll() is called as part of | |
7537 | * the runtime PM resume sequence, so we can't just call | |
7538 | * gen6_gt_force_wake_get() because that function calls | |
7539 | * intel_runtime_pm_get(), and we can't change the runtime PM refcount | |
7540 | * while we are on the resume sequence. So to solve this problem we have | |
7541 | * to call special forcewake code that doesn't touch runtime PM and | |
7542 | * doesn't enable the forcewake delayed work. | |
7543 | */ | |
7544 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
7545 | if (dev_priv->uncore.forcewake_count++ == 0) | |
7546 | dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL); | |
7547 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
215733fa | 7548 | |
be256dc7 PZ |
7549 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
7550 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
7551 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 7552 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
7553 | } |
7554 | ||
9ccd5aeb | 7555 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
7556 | val |= D_COMP_COMP_FORCE; |
7557 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 7558 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
7559 | |
7560 | val = I915_READ(LCPLL_CTL); | |
7561 | val &= ~LCPLL_PLL_DISABLE; | |
7562 | I915_WRITE(LCPLL_CTL, val); | |
7563 | ||
7564 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
7565 | DRM_ERROR("LCPLL not locked yet\n"); | |
7566 | ||
7567 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
7568 | val = I915_READ(LCPLL_CTL); | |
7569 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
7570 | I915_WRITE(LCPLL_CTL, val); | |
7571 | ||
7572 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
7573 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
7574 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
7575 | } | |
215733fa | 7576 | |
a8a8bd54 PZ |
7577 | /* See the big comment above. */ |
7578 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
7579 | if (--dev_priv->uncore.forcewake_count == 0) | |
7580 | dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL); | |
7581 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
be256dc7 PZ |
7582 | } |
7583 | ||
765dab67 PZ |
7584 | /* |
7585 | * Package states C8 and deeper are really deep PC states that can only be | |
7586 | * reached when all the devices on the system allow it, so even if the graphics | |
7587 | * device allows PC8+, it doesn't mean the system will actually get to these | |
7588 | * states. Our driver only allows PC8+ when going into runtime PM. | |
7589 | * | |
7590 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
7591 | * well is disabled and most interrupts are disabled, and these are also | |
7592 | * requirements for runtime PM. When these conditions are met, we manually do | |
7593 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
7594 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
7595 | * hang the machine. | |
7596 | * | |
7597 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
7598 | * the state of some registers, so when we come back from PC8+ we need to | |
7599 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
7600 | * need to take care of the registers kept by RC6. Notice that this happens even | |
7601 | * if we don't put the device in PCI D3 state (which is what currently happens | |
7602 | * because of the runtime PM support). | |
7603 | * | |
7604 | * For more, read "Display Sequences for Package C8" on the hardware | |
7605 | * documentation. | |
7606 | */ | |
a14cb6fc | 7607 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 7608 | { |
c67a470b PZ |
7609 | struct drm_device *dev = dev_priv->dev; |
7610 | uint32_t val; | |
7611 | ||
c67a470b PZ |
7612 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
7613 | ||
c67a470b PZ |
7614 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
7615 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
7616 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
7617 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
7618 | } | |
7619 | ||
7620 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
7621 | hsw_disable_lcpll(dev_priv, true, true); |
7622 | } | |
7623 | ||
a14cb6fc | 7624 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
7625 | { |
7626 | struct drm_device *dev = dev_priv->dev; | |
7627 | uint32_t val; | |
7628 | ||
c67a470b PZ |
7629 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
7630 | ||
7631 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
7632 | lpt_init_pch_refclk(dev); |
7633 | ||
7634 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
7635 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
7636 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
7637 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
7638 | } | |
7639 | ||
7640 | intel_prepare_ddi(dev); | |
c67a470b PZ |
7641 | } |
7642 | ||
9a952a0d PZ |
7643 | static void snb_modeset_global_resources(struct drm_device *dev) |
7644 | { | |
7645 | modeset_update_crtc_power_domains(dev); | |
7646 | } | |
7647 | ||
4f074129 ID |
7648 | static void haswell_modeset_global_resources(struct drm_device *dev) |
7649 | { | |
da723569 | 7650 | modeset_update_crtc_power_domains(dev); |
d6dd9eb1 DV |
7651 | } |
7652 | ||
09b4ddf9 | 7653 | static int haswell_crtc_mode_set(struct drm_crtc *crtc, |
09b4ddf9 PZ |
7654 | int x, int y, |
7655 | struct drm_framebuffer *fb) | |
7656 | { | |
09b4ddf9 | 7657 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
09b4ddf9 | 7658 | |
566b734a | 7659 | if (!intel_ddi_pll_select(intel_crtc)) |
6441ab5f | 7660 | return -EINVAL; |
716c2e55 | 7661 | |
644cef34 DV |
7662 | intel_crtc->lowfreq_avail = false; |
7663 | ||
c8f7a0db | 7664 | return 0; |
79e53945 JB |
7665 | } |
7666 | ||
7d2c8175 DL |
7667 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
7668 | enum port port, | |
7669 | struct intel_crtc_config *pipe_config) | |
7670 | { | |
7671 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); | |
7672 | ||
7673 | switch (pipe_config->ddi_pll_sel) { | |
7674 | case PORT_CLK_SEL_WRPLL1: | |
7675 | pipe_config->shared_dpll = DPLL_ID_WRPLL1; | |
7676 | break; | |
7677 | case PORT_CLK_SEL_WRPLL2: | |
7678 | pipe_config->shared_dpll = DPLL_ID_WRPLL2; | |
7679 | break; | |
7680 | } | |
7681 | } | |
7682 | ||
26804afd DV |
7683 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
7684 | struct intel_crtc_config *pipe_config) | |
7685 | { | |
7686 | struct drm_device *dev = crtc->base.dev; | |
7687 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d452c5b6 | 7688 | struct intel_shared_dpll *pll; |
26804afd DV |
7689 | enum port port; |
7690 | uint32_t tmp; | |
7691 | ||
7692 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
7693 | ||
7694 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
7695 | ||
7d2c8175 | 7696 | haswell_get_ddi_pll(dev_priv, port, pipe_config); |
9cd86933 | 7697 | |
d452c5b6 DV |
7698 | if (pipe_config->shared_dpll >= 0) { |
7699 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
7700 | ||
7701 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
7702 | &pipe_config->dpll_hw_state)); | |
7703 | } | |
7704 | ||
26804afd DV |
7705 | /* |
7706 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
7707 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
7708 | * the PCH transcoder is on. | |
7709 | */ | |
7710 | if ((port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
7711 | pipe_config->has_pch_encoder = true; | |
7712 | ||
7713 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
7714 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
7715 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
7716 | ||
7717 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
7718 | } | |
7719 | } | |
7720 | ||
0e8ffe1b DV |
7721 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
7722 | struct intel_crtc_config *pipe_config) | |
7723 | { | |
7724 | struct drm_device *dev = crtc->base.dev; | |
7725 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 7726 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
7727 | uint32_t tmp; |
7728 | ||
b5482bd0 ID |
7729 | if (!intel_display_power_enabled(dev_priv, |
7730 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
7731 | return false; | |
7732 | ||
e143a21c | 7733 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
7734 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
7735 | ||
eccb140b DV |
7736 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
7737 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
7738 | enum pipe trans_edp_pipe; | |
7739 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
7740 | default: | |
7741 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
7742 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
7743 | case TRANS_DDI_EDP_INPUT_A_ON: | |
7744 | trans_edp_pipe = PIPE_A; | |
7745 | break; | |
7746 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
7747 | trans_edp_pipe = PIPE_B; | |
7748 | break; | |
7749 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
7750 | trans_edp_pipe = PIPE_C; | |
7751 | break; | |
7752 | } | |
7753 | ||
7754 | if (trans_edp_pipe == crtc->pipe) | |
7755 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
7756 | } | |
7757 | ||
da7e29bd | 7758 | if (!intel_display_power_enabled(dev_priv, |
eccb140b | 7759 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
7760 | return false; |
7761 | ||
eccb140b | 7762 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
7763 | if (!(tmp & PIPECONF_ENABLE)) |
7764 | return false; | |
7765 | ||
26804afd | 7766 | haswell_get_ddi_port_state(crtc, pipe_config); |
627eb5a3 | 7767 | |
1bd1bd80 DV |
7768 | intel_get_pipe_timings(crtc, pipe_config); |
7769 | ||
2fa2fe9a | 7770 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
da7e29bd | 7771 | if (intel_display_power_enabled(dev_priv, pfit_domain)) |
2fa2fe9a | 7772 | ironlake_get_pfit_config(crtc, pipe_config); |
88adfff1 | 7773 | |
e59150dc JB |
7774 | if (IS_HASWELL(dev)) |
7775 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
7776 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 7777 | |
6c49f241 DV |
7778 | pipe_config->pixel_multiplier = 1; |
7779 | ||
0e8ffe1b DV |
7780 | return true; |
7781 | } | |
7782 | ||
1a91510d JN |
7783 | static struct { |
7784 | int clock; | |
7785 | u32 config; | |
7786 | } hdmi_audio_clock[] = { | |
7787 | { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, | |
7788 | { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ | |
7789 | { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, | |
7790 | { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, | |
7791 | { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, | |
7792 | { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, | |
7793 | { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, | |
7794 | { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, | |
7795 | { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, | |
7796 | { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, | |
7797 | }; | |
7798 | ||
7799 | /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ | |
7800 | static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode) | |
7801 | { | |
7802 | int i; | |
7803 | ||
7804 | for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { | |
7805 | if (mode->clock == hdmi_audio_clock[i].clock) | |
7806 | break; | |
7807 | } | |
7808 | ||
7809 | if (i == ARRAY_SIZE(hdmi_audio_clock)) { | |
7810 | DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock); | |
7811 | i = 1; | |
7812 | } | |
7813 | ||
7814 | DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n", | |
7815 | hdmi_audio_clock[i].clock, | |
7816 | hdmi_audio_clock[i].config); | |
7817 | ||
7818 | return hdmi_audio_clock[i].config; | |
7819 | } | |
7820 | ||
3a9627f4 WF |
7821 | static bool intel_eld_uptodate(struct drm_connector *connector, |
7822 | int reg_eldv, uint32_t bits_eldv, | |
7823 | int reg_elda, uint32_t bits_elda, | |
7824 | int reg_edid) | |
7825 | { | |
7826 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7827 | uint8_t *eld = connector->eld; | |
7828 | uint32_t i; | |
7829 | ||
7830 | i = I915_READ(reg_eldv); | |
7831 | i &= bits_eldv; | |
7832 | ||
7833 | if (!eld[0]) | |
7834 | return !i; | |
7835 | ||
7836 | if (!i) | |
7837 | return false; | |
7838 | ||
7839 | i = I915_READ(reg_elda); | |
7840 | i &= ~bits_elda; | |
7841 | I915_WRITE(reg_elda, i); | |
7842 | ||
7843 | for (i = 0; i < eld[2]; i++) | |
7844 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) | |
7845 | return false; | |
7846 | ||
7847 | return true; | |
7848 | } | |
7849 | ||
e0dac65e | 7850 | static void g4x_write_eld(struct drm_connector *connector, |
34427052 JN |
7851 | struct drm_crtc *crtc, |
7852 | struct drm_display_mode *mode) | |
e0dac65e WF |
7853 | { |
7854 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7855 | uint8_t *eld = connector->eld; | |
7856 | uint32_t eldv; | |
7857 | uint32_t len; | |
7858 | uint32_t i; | |
7859 | ||
7860 | i = I915_READ(G4X_AUD_VID_DID); | |
7861 | ||
7862 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) | |
7863 | eldv = G4X_ELDV_DEVCL_DEVBLC; | |
7864 | else | |
7865 | eldv = G4X_ELDV_DEVCTG; | |
7866 | ||
3a9627f4 WF |
7867 | if (intel_eld_uptodate(connector, |
7868 | G4X_AUD_CNTL_ST, eldv, | |
7869 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, | |
7870 | G4X_HDMIW_HDMIEDID)) | |
7871 | return; | |
7872 | ||
e0dac65e WF |
7873 | i = I915_READ(G4X_AUD_CNTL_ST); |
7874 | i &= ~(eldv | G4X_ELD_ADDR); | |
7875 | len = (i >> 9) & 0x1f; /* ELD buffer size */ | |
7876 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
7877 | ||
7878 | if (!eld[0]) | |
7879 | return; | |
7880 | ||
7881 | len = min_t(uint8_t, eld[2], len); | |
7882 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7883 | for (i = 0; i < len; i++) | |
7884 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); | |
7885 | ||
7886 | i = I915_READ(G4X_AUD_CNTL_ST); | |
7887 | i |= eldv; | |
7888 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
7889 | } | |
7890 | ||
83358c85 | 7891 | static void haswell_write_eld(struct drm_connector *connector, |
34427052 JN |
7892 | struct drm_crtc *crtc, |
7893 | struct drm_display_mode *mode) | |
83358c85 WX |
7894 | { |
7895 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7896 | uint8_t *eld = connector->eld; | |
83358c85 WX |
7897 | uint32_t eldv; |
7898 | uint32_t i; | |
7899 | int len; | |
7900 | int pipe = to_intel_crtc(crtc)->pipe; | |
7901 | int tmp; | |
7902 | ||
7903 | int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe); | |
7904 | int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe); | |
7905 | int aud_config = HSW_AUD_CFG(pipe); | |
7906 | int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD; | |
7907 | ||
83358c85 WX |
7908 | /* Audio output enable */ |
7909 | DRM_DEBUG_DRIVER("HDMI audio: enable codec\n"); | |
7910 | tmp = I915_READ(aud_cntrl_st2); | |
7911 | tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4)); | |
7912 | I915_WRITE(aud_cntrl_st2, tmp); | |
c7905792 | 7913 | POSTING_READ(aud_cntrl_st2); |
83358c85 | 7914 | |
c7905792 | 7915 | assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe); |
83358c85 WX |
7916 | |
7917 | /* Set ELD valid state */ | |
7918 | tmp = I915_READ(aud_cntrl_st2); | |
7e7cb34f | 7919 | DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp); |
83358c85 WX |
7920 | tmp |= (AUDIO_ELD_VALID_A << (pipe * 4)); |
7921 | I915_WRITE(aud_cntrl_st2, tmp); | |
7922 | tmp = I915_READ(aud_cntrl_st2); | |
7e7cb34f | 7923 | DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp); |
83358c85 WX |
7924 | |
7925 | /* Enable HDMI mode */ | |
7926 | tmp = I915_READ(aud_config); | |
7e7cb34f | 7927 | DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp); |
83358c85 WX |
7928 | /* clear N_programing_enable and N_value_index */ |
7929 | tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE); | |
7930 | I915_WRITE(aud_config, tmp); | |
7931 | ||
7932 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); | |
7933 | ||
7934 | eldv = AUDIO_ELD_VALID_A << (pipe * 4); | |
7935 | ||
7936 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { | |
7937 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
7938 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
7939 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ | |
1a91510d JN |
7940 | } else { |
7941 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); | |
7942 | } | |
83358c85 WX |
7943 | |
7944 | if (intel_eld_uptodate(connector, | |
7945 | aud_cntrl_st2, eldv, | |
7946 | aud_cntl_st, IBX_ELD_ADDRESS, | |
7947 | hdmiw_hdmiedid)) | |
7948 | return; | |
7949 | ||
7950 | i = I915_READ(aud_cntrl_st2); | |
7951 | i &= ~eldv; | |
7952 | I915_WRITE(aud_cntrl_st2, i); | |
7953 | ||
7954 | if (!eld[0]) | |
7955 | return; | |
7956 | ||
7957 | i = I915_READ(aud_cntl_st); | |
7958 | i &= ~IBX_ELD_ADDRESS; | |
7959 | I915_WRITE(aud_cntl_st, i); | |
7960 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ | |
7961 | DRM_DEBUG_DRIVER("port num:%d\n", i); | |
7962 | ||
7963 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
7964 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7965 | for (i = 0; i < len; i++) | |
7966 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
7967 | ||
7968 | i = I915_READ(aud_cntrl_st2); | |
7969 | i |= eldv; | |
7970 | I915_WRITE(aud_cntrl_st2, i); | |
7971 | ||
7972 | } | |
7973 | ||
e0dac65e | 7974 | static void ironlake_write_eld(struct drm_connector *connector, |
34427052 JN |
7975 | struct drm_crtc *crtc, |
7976 | struct drm_display_mode *mode) | |
e0dac65e WF |
7977 | { |
7978 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7979 | uint8_t *eld = connector->eld; | |
7980 | uint32_t eldv; | |
7981 | uint32_t i; | |
7982 | int len; | |
7983 | int hdmiw_hdmiedid; | |
b6daa025 | 7984 | int aud_config; |
e0dac65e WF |
7985 | int aud_cntl_st; |
7986 | int aud_cntrl_st2; | |
9b138a83 | 7987 | int pipe = to_intel_crtc(crtc)->pipe; |
e0dac65e | 7988 | |
b3f33cbf | 7989 | if (HAS_PCH_IBX(connector->dev)) { |
9b138a83 WX |
7990 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); |
7991 | aud_config = IBX_AUD_CFG(pipe); | |
7992 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); | |
1202b4c6 | 7993 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
9ca2fe73 ML |
7994 | } else if (IS_VALLEYVIEW(connector->dev)) { |
7995 | hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); | |
7996 | aud_config = VLV_AUD_CFG(pipe); | |
7997 | aud_cntl_st = VLV_AUD_CNTL_ST(pipe); | |
7998 | aud_cntrl_st2 = VLV_AUD_CNTL_ST2; | |
e0dac65e | 7999 | } else { |
9b138a83 WX |
8000 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); |
8001 | aud_config = CPT_AUD_CFG(pipe); | |
8002 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); | |
1202b4c6 | 8003 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
e0dac65e WF |
8004 | } |
8005 | ||
9b138a83 | 8006 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
e0dac65e | 8007 | |
9ca2fe73 ML |
8008 | if (IS_VALLEYVIEW(connector->dev)) { |
8009 | struct intel_encoder *intel_encoder; | |
8010 | struct intel_digital_port *intel_dig_port; | |
8011 | ||
8012 | intel_encoder = intel_attached_encoder(connector); | |
8013 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
8014 | i = intel_dig_port->port; | |
8015 | } else { | |
8016 | i = I915_READ(aud_cntl_st); | |
8017 | i = (i >> 29) & DIP_PORT_SEL_MASK; | |
8018 | /* DIP_Port_Select, 0x1 = PortB */ | |
8019 | } | |
8020 | ||
e0dac65e WF |
8021 | if (!i) { |
8022 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); | |
8023 | /* operate blindly on all ports */ | |
1202b4c6 WF |
8024 | eldv = IBX_ELD_VALIDB; |
8025 | eldv |= IBX_ELD_VALIDB << 4; | |
8026 | eldv |= IBX_ELD_VALIDB << 8; | |
e0dac65e | 8027 | } else { |
2582a850 | 8028 | DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i)); |
1202b4c6 | 8029 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
e0dac65e WF |
8030 | } |
8031 | ||
3a9627f4 WF |
8032 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
8033 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
8034 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
b6daa025 | 8035 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
1a91510d JN |
8036 | } else { |
8037 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); | |
8038 | } | |
e0dac65e | 8039 | |
3a9627f4 WF |
8040 | if (intel_eld_uptodate(connector, |
8041 | aud_cntrl_st2, eldv, | |
8042 | aud_cntl_st, IBX_ELD_ADDRESS, | |
8043 | hdmiw_hdmiedid)) | |
8044 | return; | |
8045 | ||
e0dac65e WF |
8046 | i = I915_READ(aud_cntrl_st2); |
8047 | i &= ~eldv; | |
8048 | I915_WRITE(aud_cntrl_st2, i); | |
8049 | ||
8050 | if (!eld[0]) | |
8051 | return; | |
8052 | ||
e0dac65e | 8053 | i = I915_READ(aud_cntl_st); |
1202b4c6 | 8054 | i &= ~IBX_ELD_ADDRESS; |
e0dac65e WF |
8055 | I915_WRITE(aud_cntl_st, i); |
8056 | ||
8057 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
8058 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
8059 | for (i = 0; i < len; i++) | |
8060 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
8061 | ||
8062 | i = I915_READ(aud_cntrl_st2); | |
8063 | i |= eldv; | |
8064 | I915_WRITE(aud_cntrl_st2, i); | |
8065 | } | |
8066 | ||
8067 | void intel_write_eld(struct drm_encoder *encoder, | |
8068 | struct drm_display_mode *mode) | |
8069 | { | |
8070 | struct drm_crtc *crtc = encoder->crtc; | |
8071 | struct drm_connector *connector; | |
8072 | struct drm_device *dev = encoder->dev; | |
8073 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8074 | ||
8075 | connector = drm_select_eld(encoder, mode); | |
8076 | if (!connector) | |
8077 | return; | |
8078 | ||
8079 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", | |
8080 | connector->base.id, | |
c23cc417 | 8081 | connector->name, |
e0dac65e | 8082 | connector->encoder->base.id, |
8e329a03 | 8083 | connector->encoder->name); |
e0dac65e WF |
8084 | |
8085 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; | |
8086 | ||
8087 | if (dev_priv->display.write_eld) | |
34427052 | 8088 | dev_priv->display.write_eld(connector, crtc, mode); |
e0dac65e WF |
8089 | } |
8090 | ||
560b85bb CW |
8091 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
8092 | { | |
8093 | struct drm_device *dev = crtc->dev; | |
8094 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8095 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dc41c154 | 8096 | uint32_t cntl = 0, size = 0; |
560b85bb | 8097 | |
dc41c154 VS |
8098 | if (base) { |
8099 | unsigned int width = intel_crtc->cursor_width; | |
8100 | unsigned int height = intel_crtc->cursor_height; | |
8101 | unsigned int stride = roundup_pow_of_two(width) * 4; | |
8102 | ||
8103 | switch (stride) { | |
8104 | default: | |
8105 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
8106 | width, stride); | |
8107 | stride = 256; | |
8108 | /* fallthrough */ | |
8109 | case 256: | |
8110 | case 512: | |
8111 | case 1024: | |
8112 | case 2048: | |
8113 | break; | |
4b0e333e CW |
8114 | } |
8115 | ||
dc41c154 VS |
8116 | cntl |= CURSOR_ENABLE | |
8117 | CURSOR_GAMMA_ENABLE | | |
8118 | CURSOR_FORMAT_ARGB | | |
8119 | CURSOR_STRIDE(stride); | |
8120 | ||
8121 | size = (height << 12) | width; | |
4b0e333e | 8122 | } |
560b85bb | 8123 | |
dc41c154 VS |
8124 | if (intel_crtc->cursor_cntl != 0 && |
8125 | (intel_crtc->cursor_base != base || | |
8126 | intel_crtc->cursor_size != size || | |
8127 | intel_crtc->cursor_cntl != cntl)) { | |
8128 | /* On these chipsets we can only modify the base/size/stride | |
8129 | * whilst the cursor is disabled. | |
8130 | */ | |
8131 | I915_WRITE(_CURACNTR, 0); | |
4b0e333e | 8132 | POSTING_READ(_CURACNTR); |
dc41c154 | 8133 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 8134 | } |
560b85bb | 8135 | |
dc41c154 | 8136 | if (intel_crtc->cursor_base != base) |
9db4a9c7 | 8137 | I915_WRITE(_CURABASE, base); |
4726e0b0 | 8138 | |
dc41c154 VS |
8139 | if (intel_crtc->cursor_size != size) { |
8140 | I915_WRITE(CURSIZE, size); | |
8141 | intel_crtc->cursor_size = size; | |
4b0e333e | 8142 | } |
560b85bb | 8143 | |
4b0e333e | 8144 | if (intel_crtc->cursor_cntl != cntl) { |
4b0e333e CW |
8145 | I915_WRITE(_CURACNTR, cntl); |
8146 | POSTING_READ(_CURACNTR); | |
4b0e333e | 8147 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 8148 | } |
560b85bb CW |
8149 | } |
8150 | ||
560b85bb | 8151 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) |
65a21cd6 JB |
8152 | { |
8153 | struct drm_device *dev = crtc->dev; | |
8154 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8155 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8156 | int pipe = intel_crtc->pipe; | |
4b0e333e CW |
8157 | uint32_t cntl; |
8158 | ||
8159 | cntl = 0; | |
8160 | if (base) { | |
8161 | cntl = MCURSOR_GAMMA_ENABLE; | |
8162 | switch (intel_crtc->cursor_width) { | |
4726e0b0 SK |
8163 | case 64: |
8164 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
8165 | break; | |
8166 | case 128: | |
8167 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
8168 | break; | |
8169 | case 256: | |
8170 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
8171 | break; | |
8172 | default: | |
8173 | WARN_ON(1); | |
8174 | return; | |
65a21cd6 | 8175 | } |
4b0e333e | 8176 | cntl |= pipe << 28; /* Connect to correct pipe */ |
4b0e333e CW |
8177 | } |
8178 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
8179 | cntl |= CURSOR_PIPE_CSC_ENABLE; | |
65a21cd6 | 8180 | |
4b0e333e CW |
8181 | if (intel_crtc->cursor_cntl != cntl) { |
8182 | I915_WRITE(CURCNTR(pipe), cntl); | |
8183 | POSTING_READ(CURCNTR(pipe)); | |
8184 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 8185 | } |
4b0e333e | 8186 | |
65a21cd6 | 8187 | /* and commit changes on next vblank */ |
5efb3e28 VS |
8188 | I915_WRITE(CURBASE(pipe), base); |
8189 | POSTING_READ(CURBASE(pipe)); | |
65a21cd6 JB |
8190 | } |
8191 | ||
cda4b7d3 | 8192 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
8193 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
8194 | bool on) | |
cda4b7d3 CW |
8195 | { |
8196 | struct drm_device *dev = crtc->dev; | |
8197 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8198 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8199 | int pipe = intel_crtc->pipe; | |
3d7d6510 MR |
8200 | int x = crtc->cursor_x; |
8201 | int y = crtc->cursor_y; | |
d6e4db15 | 8202 | u32 base = 0, pos = 0; |
cda4b7d3 | 8203 | |
d6e4db15 | 8204 | if (on) |
cda4b7d3 | 8205 | base = intel_crtc->cursor_addr; |
cda4b7d3 | 8206 | |
d6e4db15 VS |
8207 | if (x >= intel_crtc->config.pipe_src_w) |
8208 | base = 0; | |
8209 | ||
8210 | if (y >= intel_crtc->config.pipe_src_h) | |
cda4b7d3 CW |
8211 | base = 0; |
8212 | ||
8213 | if (x < 0) { | |
efc9064e | 8214 | if (x + intel_crtc->cursor_width <= 0) |
cda4b7d3 CW |
8215 | base = 0; |
8216 | ||
8217 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
8218 | x = -x; | |
8219 | } | |
8220 | pos |= x << CURSOR_X_SHIFT; | |
8221 | ||
8222 | if (y < 0) { | |
efc9064e | 8223 | if (y + intel_crtc->cursor_height <= 0) |
cda4b7d3 CW |
8224 | base = 0; |
8225 | ||
8226 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
8227 | y = -y; | |
8228 | } | |
8229 | pos |= y << CURSOR_Y_SHIFT; | |
8230 | ||
4b0e333e | 8231 | if (base == 0 && intel_crtc->cursor_base == 0) |
cda4b7d3 CW |
8232 | return; |
8233 | ||
5efb3e28 VS |
8234 | I915_WRITE(CURPOS(pipe), pos); |
8235 | ||
8ac54669 | 8236 | if (IS_845G(dev) || IS_I865G(dev)) |
5efb3e28 VS |
8237 | i845_update_cursor(crtc, base); |
8238 | else | |
8239 | i9xx_update_cursor(crtc, base); | |
4b0e333e | 8240 | intel_crtc->cursor_base = base; |
cda4b7d3 CW |
8241 | } |
8242 | ||
dc41c154 VS |
8243 | static bool cursor_size_ok(struct drm_device *dev, |
8244 | uint32_t width, uint32_t height) | |
8245 | { | |
8246 | if (width == 0 || height == 0) | |
8247 | return false; | |
8248 | ||
8249 | /* | |
8250 | * 845g/865g are special in that they are only limited by | |
8251 | * the width of their cursors, the height is arbitrary up to | |
8252 | * the precision of the register. Everything else requires | |
8253 | * square cursors, limited to a few power-of-two sizes. | |
8254 | */ | |
8255 | if (IS_845G(dev) || IS_I865G(dev)) { | |
8256 | if ((width & 63) != 0) | |
8257 | return false; | |
8258 | ||
8259 | if (width > (IS_845G(dev) ? 64 : 512)) | |
8260 | return false; | |
8261 | ||
8262 | if (height > 1023) | |
8263 | return false; | |
8264 | } else { | |
8265 | switch (width | height) { | |
8266 | case 256: | |
8267 | case 128: | |
8268 | if (IS_GEN2(dev)) | |
8269 | return false; | |
8270 | case 64: | |
8271 | break; | |
8272 | default: | |
8273 | return false; | |
8274 | } | |
8275 | } | |
8276 | ||
8277 | return true; | |
8278 | } | |
8279 | ||
e3287951 MR |
8280 | /* |
8281 | * intel_crtc_cursor_set_obj - Set cursor to specified GEM object | |
8282 | * | |
8283 | * Note that the object's reference will be consumed if the update fails. If | |
8284 | * the update succeeds, the reference of the old object (if any) will be | |
8285 | * consumed. | |
8286 | */ | |
8287 | static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc, | |
8288 | struct drm_i915_gem_object *obj, | |
8289 | uint32_t width, uint32_t height) | |
79e53945 JB |
8290 | { |
8291 | struct drm_device *dev = crtc->dev; | |
79e53945 | 8292 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
a071fa00 | 8293 | enum pipe pipe = intel_crtc->pipe; |
dc41c154 | 8294 | unsigned old_width, stride; |
cda4b7d3 | 8295 | uint32_t addr; |
3f8bc370 | 8296 | int ret; |
79e53945 | 8297 | |
79e53945 | 8298 | /* if we want to turn off the cursor ignore width and height */ |
e3287951 | 8299 | if (!obj) { |
28c97730 | 8300 | DRM_DEBUG_KMS("cursor off\n"); |
3f8bc370 | 8301 | addr = 0; |
05394f39 | 8302 | obj = NULL; |
5004417d | 8303 | mutex_lock(&dev->struct_mutex); |
3f8bc370 | 8304 | goto finish; |
79e53945 JB |
8305 | } |
8306 | ||
4726e0b0 | 8307 | /* Check for which cursor types we support */ |
dc41c154 | 8308 | if (!cursor_size_ok(dev, width, height)) { |
4726e0b0 | 8309 | DRM_DEBUG("Cursor dimension not supported\n"); |
79e53945 JB |
8310 | return -EINVAL; |
8311 | } | |
8312 | ||
dc41c154 VS |
8313 | stride = roundup_pow_of_two(width) * 4; |
8314 | if (obj->base.size < stride * height) { | |
e3287951 | 8315 | DRM_DEBUG_KMS("buffer is too small\n"); |
34b8686e DA |
8316 | ret = -ENOMEM; |
8317 | goto fail; | |
79e53945 JB |
8318 | } |
8319 | ||
71acb5eb | 8320 | /* we only need to pin inside GTT if cursor is non-phy */ |
7f9872e0 | 8321 | mutex_lock(&dev->struct_mutex); |
3d13ef2e | 8322 | if (!INTEL_INFO(dev)->cursor_needs_physical) { |
693db184 CW |
8323 | unsigned alignment; |
8324 | ||
d9e86c0e | 8325 | if (obj->tiling_mode) { |
3b25b31f | 8326 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
d9e86c0e CW |
8327 | ret = -EINVAL; |
8328 | goto fail_locked; | |
8329 | } | |
8330 | ||
693db184 CW |
8331 | /* Note that the w/a also requires 2 PTE of padding following |
8332 | * the bo. We currently fill all unused PTE with the shadow | |
8333 | * page and so we should always have valid PTE following the | |
8334 | * cursor preventing the VT-d warning. | |
8335 | */ | |
8336 | alignment = 0; | |
8337 | if (need_vtd_wa(dev)) | |
8338 | alignment = 64*1024; | |
8339 | ||
8340 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL); | |
e7b526bb | 8341 | if (ret) { |
3b25b31f | 8342 | DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n"); |
2da3b9b9 | 8343 | goto fail_locked; |
e7b526bb CW |
8344 | } |
8345 | ||
d9e86c0e CW |
8346 | ret = i915_gem_object_put_fence(obj); |
8347 | if (ret) { | |
3b25b31f | 8348 | DRM_DEBUG_KMS("failed to release fence for cursor"); |
d9e86c0e CW |
8349 | goto fail_unpin; |
8350 | } | |
8351 | ||
f343c5f6 | 8352 | addr = i915_gem_obj_ggtt_offset(obj); |
71acb5eb | 8353 | } else { |
6eeefaf3 | 8354 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
00731155 | 8355 | ret = i915_gem_object_attach_phys(obj, align); |
71acb5eb | 8356 | if (ret) { |
3b25b31f | 8357 | DRM_DEBUG_KMS("failed to attach phys object\n"); |
7f9872e0 | 8358 | goto fail_locked; |
71acb5eb | 8359 | } |
00731155 | 8360 | addr = obj->phys_handle->busaddr; |
3f8bc370 KH |
8361 | } |
8362 | ||
3f8bc370 | 8363 | finish: |
3f8bc370 | 8364 | if (intel_crtc->cursor_bo) { |
00731155 | 8365 | if (!INTEL_INFO(dev)->cursor_needs_physical) |
cc98b413 | 8366 | i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo); |
3f8bc370 | 8367 | } |
80824003 | 8368 | |
a071fa00 DV |
8369 | i915_gem_track_fb(intel_crtc->cursor_bo, obj, |
8370 | INTEL_FRONTBUFFER_CURSOR(pipe)); | |
7f9872e0 | 8371 | mutex_unlock(&dev->struct_mutex); |
3f8bc370 | 8372 | |
64f962e3 CW |
8373 | old_width = intel_crtc->cursor_width; |
8374 | ||
3f8bc370 | 8375 | intel_crtc->cursor_addr = addr; |
05394f39 | 8376 | intel_crtc->cursor_bo = obj; |
cda4b7d3 CW |
8377 | intel_crtc->cursor_width = width; |
8378 | intel_crtc->cursor_height = height; | |
8379 | ||
64f962e3 CW |
8380 | if (intel_crtc->active) { |
8381 | if (old_width != width) | |
8382 | intel_update_watermarks(crtc); | |
f2f5f771 | 8383 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); |
64f962e3 | 8384 | } |
3f8bc370 | 8385 | |
f99d7069 DV |
8386 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe)); |
8387 | ||
79e53945 | 8388 | return 0; |
e7b526bb | 8389 | fail_unpin: |
cc98b413 | 8390 | i915_gem_object_unpin_from_display_plane(obj); |
7f9872e0 | 8391 | fail_locked: |
34b8686e | 8392 | mutex_unlock(&dev->struct_mutex); |
bc9025bd | 8393 | fail: |
05394f39 | 8394 | drm_gem_object_unreference_unlocked(&obj->base); |
34b8686e | 8395 | return ret; |
79e53945 JB |
8396 | } |
8397 | ||
79e53945 | 8398 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 8399 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 8400 | { |
7203425a | 8401 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 8402 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 8403 | |
7203425a | 8404 | for (i = start; i < end; i++) { |
79e53945 JB |
8405 | intel_crtc->lut_r[i] = red[i] >> 8; |
8406 | intel_crtc->lut_g[i] = green[i] >> 8; | |
8407 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
8408 | } | |
8409 | ||
8410 | intel_crtc_load_lut(crtc); | |
8411 | } | |
8412 | ||
79e53945 JB |
8413 | /* VESA 640x480x72Hz mode to set on the pipe */ |
8414 | static struct drm_display_mode load_detect_mode = { | |
8415 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
8416 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
8417 | }; | |
8418 | ||
a8bb6818 DV |
8419 | struct drm_framebuffer * |
8420 | __intel_framebuffer_create(struct drm_device *dev, | |
8421 | struct drm_mode_fb_cmd2 *mode_cmd, | |
8422 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
8423 | { |
8424 | struct intel_framebuffer *intel_fb; | |
8425 | int ret; | |
8426 | ||
8427 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
8428 | if (!intel_fb) { | |
8429 | drm_gem_object_unreference_unlocked(&obj->base); | |
8430 | return ERR_PTR(-ENOMEM); | |
8431 | } | |
8432 | ||
8433 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
8434 | if (ret) |
8435 | goto err; | |
d2dff872 CW |
8436 | |
8437 | return &intel_fb->base; | |
dd4916c5 DV |
8438 | err: |
8439 | drm_gem_object_unreference_unlocked(&obj->base); | |
8440 | kfree(intel_fb); | |
8441 | ||
8442 | return ERR_PTR(ret); | |
d2dff872 CW |
8443 | } |
8444 | ||
b5ea642a | 8445 | static struct drm_framebuffer * |
a8bb6818 DV |
8446 | intel_framebuffer_create(struct drm_device *dev, |
8447 | struct drm_mode_fb_cmd2 *mode_cmd, | |
8448 | struct drm_i915_gem_object *obj) | |
8449 | { | |
8450 | struct drm_framebuffer *fb; | |
8451 | int ret; | |
8452 | ||
8453 | ret = i915_mutex_lock_interruptible(dev); | |
8454 | if (ret) | |
8455 | return ERR_PTR(ret); | |
8456 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
8457 | mutex_unlock(&dev->struct_mutex); | |
8458 | ||
8459 | return fb; | |
8460 | } | |
8461 | ||
d2dff872 CW |
8462 | static u32 |
8463 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
8464 | { | |
8465 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
8466 | return ALIGN(pitch, 64); | |
8467 | } | |
8468 | ||
8469 | static u32 | |
8470 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
8471 | { | |
8472 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 8473 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
8474 | } |
8475 | ||
8476 | static struct drm_framebuffer * | |
8477 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
8478 | struct drm_display_mode *mode, | |
8479 | int depth, int bpp) | |
8480 | { | |
8481 | struct drm_i915_gem_object *obj; | |
0fed39bd | 8482 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
8483 | |
8484 | obj = i915_gem_alloc_object(dev, | |
8485 | intel_framebuffer_size_for_mode(mode, bpp)); | |
8486 | if (obj == NULL) | |
8487 | return ERR_PTR(-ENOMEM); | |
8488 | ||
8489 | mode_cmd.width = mode->hdisplay; | |
8490 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
8491 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
8492 | bpp); | |
5ca0c34a | 8493 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
8494 | |
8495 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
8496 | } | |
8497 | ||
8498 | static struct drm_framebuffer * | |
8499 | mode_fits_in_fbdev(struct drm_device *dev, | |
8500 | struct drm_display_mode *mode) | |
8501 | { | |
4520f53a | 8502 | #ifdef CONFIG_DRM_I915_FBDEV |
d2dff872 CW |
8503 | struct drm_i915_private *dev_priv = dev->dev_private; |
8504 | struct drm_i915_gem_object *obj; | |
8505 | struct drm_framebuffer *fb; | |
8506 | ||
4c0e5528 | 8507 | if (!dev_priv->fbdev) |
d2dff872 CW |
8508 | return NULL; |
8509 | ||
4c0e5528 | 8510 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
8511 | return NULL; |
8512 | ||
4c0e5528 DV |
8513 | obj = dev_priv->fbdev->fb->obj; |
8514 | BUG_ON(!obj); | |
8515 | ||
8bcd4553 | 8516 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
8517 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
8518 | fb->bits_per_pixel)) | |
d2dff872 CW |
8519 | return NULL; |
8520 | ||
01f2c773 | 8521 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
8522 | return NULL; |
8523 | ||
8524 | return fb; | |
4520f53a DV |
8525 | #else |
8526 | return NULL; | |
8527 | #endif | |
d2dff872 CW |
8528 | } |
8529 | ||
d2434ab7 | 8530 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 8531 | struct drm_display_mode *mode, |
51fd371b RC |
8532 | struct intel_load_detect_pipe *old, |
8533 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
8534 | { |
8535 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
8536 | struct intel_encoder *intel_encoder = |
8537 | intel_attached_encoder(connector); | |
79e53945 | 8538 | struct drm_crtc *possible_crtc; |
4ef69c7a | 8539 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
8540 | struct drm_crtc *crtc = NULL; |
8541 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 8542 | struct drm_framebuffer *fb; |
51fd371b RC |
8543 | struct drm_mode_config *config = &dev->mode_config; |
8544 | int ret, i = -1; | |
79e53945 | 8545 | |
d2dff872 | 8546 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 8547 | connector->base.id, connector->name, |
8e329a03 | 8548 | encoder->base.id, encoder->name); |
d2dff872 | 8549 | |
51fd371b RC |
8550 | retry: |
8551 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
8552 | if (ret) | |
8553 | goto fail_unlock; | |
6e9f798d | 8554 | |
79e53945 JB |
8555 | /* |
8556 | * Algorithm gets a little messy: | |
7a5e4805 | 8557 | * |
79e53945 JB |
8558 | * - if the connector already has an assigned crtc, use it (but make |
8559 | * sure it's on first) | |
7a5e4805 | 8560 | * |
79e53945 JB |
8561 | * - try to find the first unused crtc that can drive this connector, |
8562 | * and use that if we find one | |
79e53945 JB |
8563 | */ |
8564 | ||
8565 | /* See if we already have a CRTC for this connector */ | |
8566 | if (encoder->crtc) { | |
8567 | crtc = encoder->crtc; | |
8261b191 | 8568 | |
51fd371b RC |
8569 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
8570 | if (ret) | |
8571 | goto fail_unlock; | |
7b24056b | 8572 | |
24218aac | 8573 | old->dpms_mode = connector->dpms; |
8261b191 CW |
8574 | old->load_detect_temp = false; |
8575 | ||
8576 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
8577 | if (connector->dpms != DRM_MODE_DPMS_ON) |
8578 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 8579 | |
7173188d | 8580 | return true; |
79e53945 JB |
8581 | } |
8582 | ||
8583 | /* Find an unused one (if possible) */ | |
70e1e0ec | 8584 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
8585 | i++; |
8586 | if (!(encoder->possible_crtcs & (1 << i))) | |
8587 | continue; | |
a459249c VS |
8588 | if (possible_crtc->enabled) |
8589 | continue; | |
8590 | /* This can occur when applying the pipe A quirk on resume. */ | |
8591 | if (to_intel_crtc(possible_crtc)->new_enabled) | |
8592 | continue; | |
8593 | ||
8594 | crtc = possible_crtc; | |
8595 | break; | |
79e53945 JB |
8596 | } |
8597 | ||
8598 | /* | |
8599 | * If we didn't find an unused CRTC, don't use any. | |
8600 | */ | |
8601 | if (!crtc) { | |
7173188d | 8602 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
51fd371b | 8603 | goto fail_unlock; |
79e53945 JB |
8604 | } |
8605 | ||
51fd371b RC |
8606 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
8607 | if (ret) | |
8608 | goto fail_unlock; | |
fc303101 DV |
8609 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
8610 | to_intel_connector(connector)->new_encoder = intel_encoder; | |
79e53945 JB |
8611 | |
8612 | intel_crtc = to_intel_crtc(crtc); | |
412b61d8 VS |
8613 | intel_crtc->new_enabled = true; |
8614 | intel_crtc->new_config = &intel_crtc->config; | |
24218aac | 8615 | old->dpms_mode = connector->dpms; |
8261b191 | 8616 | old->load_detect_temp = true; |
d2dff872 | 8617 | old->release_fb = NULL; |
79e53945 | 8618 | |
6492711d CW |
8619 | if (!mode) |
8620 | mode = &load_detect_mode; | |
79e53945 | 8621 | |
d2dff872 CW |
8622 | /* We need a framebuffer large enough to accommodate all accesses |
8623 | * that the plane may generate whilst we perform load detection. | |
8624 | * We can not rely on the fbcon either being present (we get called | |
8625 | * during its initialisation to detect all boot displays, or it may | |
8626 | * not even exist) or that it is large enough to satisfy the | |
8627 | * requested mode. | |
8628 | */ | |
94352cf9 DV |
8629 | fb = mode_fits_in_fbdev(dev, mode); |
8630 | if (fb == NULL) { | |
d2dff872 | 8631 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
8632 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
8633 | old->release_fb = fb; | |
d2dff872 CW |
8634 | } else |
8635 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 8636 | if (IS_ERR(fb)) { |
d2dff872 | 8637 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 8638 | goto fail; |
79e53945 | 8639 | } |
79e53945 | 8640 | |
c0c36b94 | 8641 | if (intel_set_mode(crtc, mode, 0, 0, fb)) { |
6492711d | 8642 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
8643 | if (old->release_fb) |
8644 | old->release_fb->funcs->destroy(old->release_fb); | |
412b61d8 | 8645 | goto fail; |
79e53945 | 8646 | } |
7173188d | 8647 | |
79e53945 | 8648 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 8649 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 8650 | return true; |
412b61d8 VS |
8651 | |
8652 | fail: | |
8653 | intel_crtc->new_enabled = crtc->enabled; | |
8654 | if (intel_crtc->new_enabled) | |
8655 | intel_crtc->new_config = &intel_crtc->config; | |
8656 | else | |
8657 | intel_crtc->new_config = NULL; | |
51fd371b RC |
8658 | fail_unlock: |
8659 | if (ret == -EDEADLK) { | |
8660 | drm_modeset_backoff(ctx); | |
8661 | goto retry; | |
8662 | } | |
8663 | ||
412b61d8 | 8664 | return false; |
79e53945 JB |
8665 | } |
8666 | ||
d2434ab7 | 8667 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
208bf9fd | 8668 | struct intel_load_detect_pipe *old) |
79e53945 | 8669 | { |
d2434ab7 DV |
8670 | struct intel_encoder *intel_encoder = |
8671 | intel_attached_encoder(connector); | |
4ef69c7a | 8672 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 8673 | struct drm_crtc *crtc = encoder->crtc; |
412b61d8 | 8674 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 8675 | |
d2dff872 | 8676 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 8677 | connector->base.id, connector->name, |
8e329a03 | 8678 | encoder->base.id, encoder->name); |
d2dff872 | 8679 | |
8261b191 | 8680 | if (old->load_detect_temp) { |
fc303101 DV |
8681 | to_intel_connector(connector)->new_encoder = NULL; |
8682 | intel_encoder->new_crtc = NULL; | |
412b61d8 VS |
8683 | intel_crtc->new_enabled = false; |
8684 | intel_crtc->new_config = NULL; | |
fc303101 | 8685 | intel_set_mode(crtc, NULL, 0, 0, NULL); |
d2dff872 | 8686 | |
36206361 DV |
8687 | if (old->release_fb) { |
8688 | drm_framebuffer_unregister_private(old->release_fb); | |
8689 | drm_framebuffer_unreference(old->release_fb); | |
8690 | } | |
d2dff872 | 8691 | |
0622a53c | 8692 | return; |
79e53945 JB |
8693 | } |
8694 | ||
c751ce4f | 8695 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
8696 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
8697 | connector->funcs->dpms(connector, old->dpms_mode); | |
79e53945 JB |
8698 | } |
8699 | ||
da4a1efa VS |
8700 | static int i9xx_pll_refclk(struct drm_device *dev, |
8701 | const struct intel_crtc_config *pipe_config) | |
8702 | { | |
8703 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8704 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
8705 | ||
8706 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 8707 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
8708 | else if (HAS_PCH_SPLIT(dev)) |
8709 | return 120000; | |
8710 | else if (!IS_GEN2(dev)) | |
8711 | return 96000; | |
8712 | else | |
8713 | return 48000; | |
8714 | } | |
8715 | ||
79e53945 | 8716 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc JB |
8717 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
8718 | struct intel_crtc_config *pipe_config) | |
79e53945 | 8719 | { |
f1f644dc | 8720 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 8721 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 8722 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 8723 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
8724 | u32 fp; |
8725 | intel_clock_t clock; | |
da4a1efa | 8726 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
8727 | |
8728 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 8729 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 8730 | else |
293623f7 | 8731 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
8732 | |
8733 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
8734 | if (IS_PINEVIEW(dev)) { |
8735 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
8736 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
8737 | } else { |
8738 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
8739 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
8740 | } | |
8741 | ||
a6c45cf0 | 8742 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
8743 | if (IS_PINEVIEW(dev)) |
8744 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
8745 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
8746 | else |
8747 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
8748 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
8749 | ||
8750 | switch (dpll & DPLL_MODE_MASK) { | |
8751 | case DPLLB_MODE_DAC_SERIAL: | |
8752 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
8753 | 5 : 10; | |
8754 | break; | |
8755 | case DPLLB_MODE_LVDS: | |
8756 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
8757 | 7 : 14; | |
8758 | break; | |
8759 | default: | |
28c97730 | 8760 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 8761 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 8762 | return; |
79e53945 JB |
8763 | } |
8764 | ||
ac58c3f0 | 8765 | if (IS_PINEVIEW(dev)) |
da4a1efa | 8766 | pineview_clock(refclk, &clock); |
ac58c3f0 | 8767 | else |
da4a1efa | 8768 | i9xx_clock(refclk, &clock); |
79e53945 | 8769 | } else { |
0fb58223 | 8770 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 8771 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
8772 | |
8773 | if (is_lvds) { | |
8774 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
8775 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
8776 | |
8777 | if (lvds & LVDS_CLKB_POWER_UP) | |
8778 | clock.p2 = 7; | |
8779 | else | |
8780 | clock.p2 = 14; | |
79e53945 JB |
8781 | } else { |
8782 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
8783 | clock.p1 = 2; | |
8784 | else { | |
8785 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
8786 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
8787 | } | |
8788 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
8789 | clock.p2 = 4; | |
8790 | else | |
8791 | clock.p2 = 2; | |
79e53945 | 8792 | } |
da4a1efa VS |
8793 | |
8794 | i9xx_clock(refclk, &clock); | |
79e53945 JB |
8795 | } |
8796 | ||
18442d08 VS |
8797 | /* |
8798 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 8799 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
8800 | * encoder's get_config() function. |
8801 | */ | |
8802 | pipe_config->port_clock = clock.dot; | |
f1f644dc JB |
8803 | } |
8804 | ||
6878da05 VS |
8805 | int intel_dotclock_calculate(int link_freq, |
8806 | const struct intel_link_m_n *m_n) | |
f1f644dc | 8807 | { |
f1f644dc JB |
8808 | /* |
8809 | * The calculation for the data clock is: | |
1041a02f | 8810 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 8811 | * But we want to avoid losing precison if possible, so: |
1041a02f | 8812 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
8813 | * |
8814 | * and the link clock is simpler: | |
1041a02f | 8815 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
8816 | */ |
8817 | ||
6878da05 VS |
8818 | if (!m_n->link_n) |
8819 | return 0; | |
f1f644dc | 8820 | |
6878da05 VS |
8821 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
8822 | } | |
f1f644dc | 8823 | |
18442d08 VS |
8824 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
8825 | struct intel_crtc_config *pipe_config) | |
6878da05 VS |
8826 | { |
8827 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 8828 | |
18442d08 VS |
8829 | /* read out port_clock from the DPLL */ |
8830 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 8831 | |
f1f644dc | 8832 | /* |
18442d08 | 8833 | * This value does not include pixel_multiplier. |
241bfc38 | 8834 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
8835 | * agree once we know their relationship in the encoder's |
8836 | * get_config() function. | |
79e53945 | 8837 | */ |
241bfc38 | 8838 | pipe_config->adjusted_mode.crtc_clock = |
18442d08 VS |
8839 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
8840 | &pipe_config->fdi_m_n); | |
79e53945 JB |
8841 | } |
8842 | ||
8843 | /** Returns the currently programmed mode of the given pipe. */ | |
8844 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
8845 | struct drm_crtc *crtc) | |
8846 | { | |
548f245b | 8847 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 8848 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3b117c8f | 8849 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
79e53945 | 8850 | struct drm_display_mode *mode; |
f1f644dc | 8851 | struct intel_crtc_config pipe_config; |
fe2b8f9d PZ |
8852 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
8853 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
8854 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
8855 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 8856 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
8857 | |
8858 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
8859 | if (!mode) | |
8860 | return NULL; | |
8861 | ||
f1f644dc JB |
8862 | /* |
8863 | * Construct a pipe_config sufficient for getting the clock info | |
8864 | * back out of crtc_clock_get. | |
8865 | * | |
8866 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
8867 | * to use a real value here instead. | |
8868 | */ | |
293623f7 | 8869 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 8870 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
8871 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
8872 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
8873 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
8874 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
8875 | ||
773ae034 | 8876 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
79e53945 JB |
8877 | mode->hdisplay = (htot & 0xffff) + 1; |
8878 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
8879 | mode->hsync_start = (hsync & 0xffff) + 1; | |
8880 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
8881 | mode->vdisplay = (vtot & 0xffff) + 1; | |
8882 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
8883 | mode->vsync_start = (vsync & 0xffff) + 1; | |
8884 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
8885 | ||
8886 | drm_mode_set_name(mode); | |
79e53945 JB |
8887 | |
8888 | return mode; | |
8889 | } | |
8890 | ||
cc36513c DV |
8891 | static void intel_increase_pllclock(struct drm_device *dev, |
8892 | enum pipe pipe) | |
652c393a | 8893 | { |
fbee40df | 8894 | struct drm_i915_private *dev_priv = dev->dev_private; |
dbdc6479 JB |
8895 | int dpll_reg = DPLL(pipe); |
8896 | int dpll; | |
652c393a | 8897 | |
baff296c | 8898 | if (!HAS_GMCH_DISPLAY(dev)) |
652c393a JB |
8899 | return; |
8900 | ||
8901 | if (!dev_priv->lvds_downclock_avail) | |
8902 | return; | |
8903 | ||
dbdc6479 | 8904 | dpll = I915_READ(dpll_reg); |
652c393a | 8905 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
44d98a61 | 8906 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
652c393a | 8907 | |
8ac5a6d5 | 8908 | assert_panel_unlocked(dev_priv, pipe); |
652c393a JB |
8909 | |
8910 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; | |
8911 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 8912 | intel_wait_for_vblank(dev, pipe); |
dbdc6479 | 8913 | |
652c393a JB |
8914 | dpll = I915_READ(dpll_reg); |
8915 | if (dpll & DISPLAY_RATE_SELECT_FPA1) | |
44d98a61 | 8916 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
652c393a | 8917 | } |
652c393a JB |
8918 | } |
8919 | ||
8920 | static void intel_decrease_pllclock(struct drm_crtc *crtc) | |
8921 | { | |
8922 | struct drm_device *dev = crtc->dev; | |
fbee40df | 8923 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 8924 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
652c393a | 8925 | |
baff296c | 8926 | if (!HAS_GMCH_DISPLAY(dev)) |
652c393a JB |
8927 | return; |
8928 | ||
8929 | if (!dev_priv->lvds_downclock_avail) | |
8930 | return; | |
8931 | ||
8932 | /* | |
8933 | * Since this is called by a timer, we should never get here in | |
8934 | * the manual case. | |
8935 | */ | |
8936 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
dc257cf1 DV |
8937 | int pipe = intel_crtc->pipe; |
8938 | int dpll_reg = DPLL(pipe); | |
8939 | int dpll; | |
f6e5b160 | 8940 | |
44d98a61 | 8941 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 8942 | |
8ac5a6d5 | 8943 | assert_panel_unlocked(dev_priv, pipe); |
652c393a | 8944 | |
dc257cf1 | 8945 | dpll = I915_READ(dpll_reg); |
652c393a JB |
8946 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
8947 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 8948 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
8949 | dpll = I915_READ(dpll_reg); |
8950 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 8951 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
8952 | } |
8953 | ||
8954 | } | |
8955 | ||
f047e395 CW |
8956 | void intel_mark_busy(struct drm_device *dev) |
8957 | { | |
c67a470b PZ |
8958 | struct drm_i915_private *dev_priv = dev->dev_private; |
8959 | ||
f62a0076 CW |
8960 | if (dev_priv->mm.busy) |
8961 | return; | |
8962 | ||
43694d69 | 8963 | intel_runtime_pm_get(dev_priv); |
c67a470b | 8964 | i915_update_gfx_val(dev_priv); |
f62a0076 | 8965 | dev_priv->mm.busy = true; |
f047e395 CW |
8966 | } |
8967 | ||
8968 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 8969 | { |
c67a470b | 8970 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 8971 | struct drm_crtc *crtc; |
652c393a | 8972 | |
f62a0076 CW |
8973 | if (!dev_priv->mm.busy) |
8974 | return; | |
8975 | ||
8976 | dev_priv->mm.busy = false; | |
8977 | ||
d330a953 | 8978 | if (!i915.powersave) |
bb4cdd53 | 8979 | goto out; |
652c393a | 8980 | |
70e1e0ec | 8981 | for_each_crtc(dev, crtc) { |
f4510a27 | 8982 | if (!crtc->primary->fb) |
652c393a JB |
8983 | continue; |
8984 | ||
725a5b54 | 8985 | intel_decrease_pllclock(crtc); |
652c393a | 8986 | } |
b29c19b6 | 8987 | |
3d13ef2e | 8988 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 8989 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 PZ |
8990 | |
8991 | out: | |
43694d69 | 8992 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
8993 | } |
8994 | ||
7c8f8a70 | 8995 | |
f99d7069 DV |
8996 | /** |
8997 | * intel_mark_fb_busy - mark given planes as busy | |
8998 | * @dev: DRM device | |
8999 | * @frontbuffer_bits: bits for the affected planes | |
9000 | * @ring: optional ring for asynchronous commands | |
9001 | * | |
9002 | * This function gets called every time the screen contents change. It can be | |
9003 | * used to keep e.g. the update rate at the nominal refresh rate with DRRS. | |
9004 | */ | |
9005 | static void intel_mark_fb_busy(struct drm_device *dev, | |
9006 | unsigned frontbuffer_bits, | |
9007 | struct intel_engine_cs *ring) | |
652c393a | 9008 | { |
055e393f | 9009 | struct drm_i915_private *dev_priv = dev->dev_private; |
cc36513c | 9010 | enum pipe pipe; |
652c393a | 9011 | |
d330a953 | 9012 | if (!i915.powersave) |
acb87dfb CW |
9013 | return; |
9014 | ||
055e393f | 9015 | for_each_pipe(dev_priv, pipe) { |
f99d7069 | 9016 | if (!(frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe))) |
c65355bb CW |
9017 | continue; |
9018 | ||
cc36513c | 9019 | intel_increase_pllclock(dev, pipe); |
c65355bb CW |
9020 | if (ring && intel_fbc_enabled(dev)) |
9021 | ring->fbc_dirty = true; | |
652c393a JB |
9022 | } |
9023 | } | |
9024 | ||
f99d7069 DV |
9025 | /** |
9026 | * intel_fb_obj_invalidate - invalidate frontbuffer object | |
9027 | * @obj: GEM object to invalidate | |
9028 | * @ring: set for asynchronous rendering | |
9029 | * | |
9030 | * This function gets called every time rendering on the given object starts and | |
9031 | * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must | |
9032 | * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed | |
9033 | * until the rendering completes or a flip on this frontbuffer plane is | |
9034 | * scheduled. | |
9035 | */ | |
9036 | void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj, | |
9037 | struct intel_engine_cs *ring) | |
9038 | { | |
9039 | struct drm_device *dev = obj->base.dev; | |
9040 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9041 | ||
9042 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); | |
9043 | ||
9044 | if (!obj->frontbuffer_bits) | |
9045 | return; | |
9046 | ||
9047 | if (ring) { | |
9048 | mutex_lock(&dev_priv->fb_tracking.lock); | |
9049 | dev_priv->fb_tracking.busy_bits | |
9050 | |= obj->frontbuffer_bits; | |
9051 | dev_priv->fb_tracking.flip_bits | |
9052 | &= ~obj->frontbuffer_bits; | |
9053 | mutex_unlock(&dev_priv->fb_tracking.lock); | |
9054 | } | |
9055 | ||
9056 | intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring); | |
9057 | ||
9ca15301 | 9058 | intel_edp_psr_invalidate(dev, obj->frontbuffer_bits); |
f99d7069 DV |
9059 | } |
9060 | ||
9061 | /** | |
9062 | * intel_frontbuffer_flush - flush frontbuffer | |
9063 | * @dev: DRM device | |
9064 | * @frontbuffer_bits: frontbuffer plane tracking bits | |
9065 | * | |
9066 | * This function gets called every time rendering on the given planes has | |
9067 | * completed and frontbuffer caching can be started again. Flushes will get | |
9068 | * delayed if they're blocked by some oustanding asynchronous rendering. | |
9069 | * | |
9070 | * Can be called without any locks held. | |
9071 | */ | |
9072 | void intel_frontbuffer_flush(struct drm_device *dev, | |
9073 | unsigned frontbuffer_bits) | |
9074 | { | |
9075 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9076 | ||
9077 | /* Delay flushing when rings are still busy.*/ | |
9078 | mutex_lock(&dev_priv->fb_tracking.lock); | |
9079 | frontbuffer_bits &= ~dev_priv->fb_tracking.busy_bits; | |
9080 | mutex_unlock(&dev_priv->fb_tracking.lock); | |
9081 | ||
9082 | intel_mark_fb_busy(dev, frontbuffer_bits, NULL); | |
9083 | ||
9ca15301 | 9084 | intel_edp_psr_flush(dev, frontbuffer_bits); |
f99d7069 DV |
9085 | } |
9086 | ||
9087 | /** | |
9088 | * intel_fb_obj_flush - flush frontbuffer object | |
9089 | * @obj: GEM object to flush | |
9090 | * @retire: set when retiring asynchronous rendering | |
9091 | * | |
9092 | * This function gets called every time rendering on the given object has | |
9093 | * completed and frontbuffer caching can be started again. If @retire is true | |
9094 | * then any delayed flushes will be unblocked. | |
9095 | */ | |
9096 | void intel_fb_obj_flush(struct drm_i915_gem_object *obj, | |
9097 | bool retire) | |
9098 | { | |
9099 | struct drm_device *dev = obj->base.dev; | |
9100 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9101 | unsigned frontbuffer_bits; | |
9102 | ||
9103 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); | |
9104 | ||
9105 | if (!obj->frontbuffer_bits) | |
9106 | return; | |
9107 | ||
9108 | frontbuffer_bits = obj->frontbuffer_bits; | |
9109 | ||
9110 | if (retire) { | |
9111 | mutex_lock(&dev_priv->fb_tracking.lock); | |
9112 | /* Filter out new bits since rendering started. */ | |
9113 | frontbuffer_bits &= dev_priv->fb_tracking.busy_bits; | |
9114 | ||
9115 | dev_priv->fb_tracking.busy_bits &= ~frontbuffer_bits; | |
9116 | mutex_unlock(&dev_priv->fb_tracking.lock); | |
9117 | } | |
9118 | ||
9119 | intel_frontbuffer_flush(dev, frontbuffer_bits); | |
9120 | } | |
9121 | ||
9122 | /** | |
9123 | * intel_frontbuffer_flip_prepare - prepare asnychronous frontbuffer flip | |
9124 | * @dev: DRM device | |
9125 | * @frontbuffer_bits: frontbuffer plane tracking bits | |
9126 | * | |
9127 | * This function gets called after scheduling a flip on @obj. The actual | |
9128 | * frontbuffer flushing will be delayed until completion is signalled with | |
9129 | * intel_frontbuffer_flip_complete. If an invalidate happens in between this | |
9130 | * flush will be cancelled. | |
9131 | * | |
9132 | * Can be called without any locks held. | |
9133 | */ | |
9134 | void intel_frontbuffer_flip_prepare(struct drm_device *dev, | |
9135 | unsigned frontbuffer_bits) | |
9136 | { | |
9137 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9138 | ||
9139 | mutex_lock(&dev_priv->fb_tracking.lock); | |
9140 | dev_priv->fb_tracking.flip_bits | |
9141 | |= frontbuffer_bits; | |
9142 | mutex_unlock(&dev_priv->fb_tracking.lock); | |
9143 | } | |
9144 | ||
9145 | /** | |
9146 | * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flush | |
9147 | * @dev: DRM device | |
9148 | * @frontbuffer_bits: frontbuffer plane tracking bits | |
9149 | * | |
9150 | * This function gets called after the flip has been latched and will complete | |
9151 | * on the next vblank. It will execute the fush if it hasn't been cancalled yet. | |
9152 | * | |
9153 | * Can be called without any locks held. | |
9154 | */ | |
9155 | void intel_frontbuffer_flip_complete(struct drm_device *dev, | |
9156 | unsigned frontbuffer_bits) | |
9157 | { | |
9158 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9159 | ||
9160 | mutex_lock(&dev_priv->fb_tracking.lock); | |
9161 | /* Mask any cancelled flips. */ | |
9162 | frontbuffer_bits &= dev_priv->fb_tracking.flip_bits; | |
9163 | dev_priv->fb_tracking.flip_bits &= ~frontbuffer_bits; | |
9164 | mutex_unlock(&dev_priv->fb_tracking.lock); | |
9165 | ||
9166 | intel_frontbuffer_flush(dev, frontbuffer_bits); | |
9167 | } | |
9168 | ||
79e53945 JB |
9169 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
9170 | { | |
9171 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
9172 | struct drm_device *dev = crtc->dev; |
9173 | struct intel_unpin_work *work; | |
9174 | unsigned long flags; | |
9175 | ||
9176 | spin_lock_irqsave(&dev->event_lock, flags); | |
9177 | work = intel_crtc->unpin_work; | |
9178 | intel_crtc->unpin_work = NULL; | |
9179 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
9180 | ||
9181 | if (work) { | |
9182 | cancel_work_sync(&work->work); | |
9183 | kfree(work); | |
9184 | } | |
79e53945 JB |
9185 | |
9186 | drm_crtc_cleanup(crtc); | |
67e77c5a | 9187 | |
79e53945 JB |
9188 | kfree(intel_crtc); |
9189 | } | |
9190 | ||
6b95a207 KH |
9191 | static void intel_unpin_work_fn(struct work_struct *__work) |
9192 | { | |
9193 | struct intel_unpin_work *work = | |
9194 | container_of(__work, struct intel_unpin_work, work); | |
b4a98e57 | 9195 | struct drm_device *dev = work->crtc->dev; |
f99d7069 | 9196 | enum pipe pipe = to_intel_crtc(work->crtc)->pipe; |
6b95a207 | 9197 | |
b4a98e57 | 9198 | mutex_lock(&dev->struct_mutex); |
1690e1eb | 9199 | intel_unpin_fb_obj(work->old_fb_obj); |
05394f39 CW |
9200 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
9201 | drm_gem_object_unreference(&work->old_fb_obj->base); | |
d9e86c0e | 9202 | |
b4a98e57 CW |
9203 | intel_update_fbc(dev); |
9204 | mutex_unlock(&dev->struct_mutex); | |
9205 | ||
f99d7069 DV |
9206 | intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
9207 | ||
b4a98e57 CW |
9208 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); |
9209 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); | |
9210 | ||
6b95a207 KH |
9211 | kfree(work); |
9212 | } | |
9213 | ||
1afe3e9d | 9214 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 9215 | struct drm_crtc *crtc) |
6b95a207 | 9216 | { |
fbee40df | 9217 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
9218 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
9219 | struct intel_unpin_work *work; | |
6b95a207 KH |
9220 | unsigned long flags; |
9221 | ||
9222 | /* Ignore early vblank irqs */ | |
9223 | if (intel_crtc == NULL) | |
9224 | return; | |
9225 | ||
9226 | spin_lock_irqsave(&dev->event_lock, flags); | |
9227 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
9228 | |
9229 | /* Ensure we don't miss a work->pending update ... */ | |
9230 | smp_rmb(); | |
9231 | ||
9232 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
9233 | spin_unlock_irqrestore(&dev->event_lock, flags); |
9234 | return; | |
9235 | } | |
9236 | ||
e7d841ca CW |
9237 | /* and that the unpin work is consistent wrt ->pending. */ |
9238 | smp_rmb(); | |
9239 | ||
6b95a207 | 9240 | intel_crtc->unpin_work = NULL; |
6b95a207 | 9241 | |
45a066eb RC |
9242 | if (work->event) |
9243 | drm_send_vblank_event(dev, intel_crtc->pipe, work->event); | |
6b95a207 | 9244 | |
87b6b101 | 9245 | drm_crtc_vblank_put(crtc); |
0af7e4df | 9246 | |
6b95a207 KH |
9247 | spin_unlock_irqrestore(&dev->event_lock, flags); |
9248 | ||
2c10d571 | 9249 | wake_up_all(&dev_priv->pending_flip_queue); |
b4a98e57 CW |
9250 | |
9251 | queue_work(dev_priv->wq, &work->work); | |
e5510fac JB |
9252 | |
9253 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); | |
6b95a207 KH |
9254 | } |
9255 | ||
1afe3e9d JB |
9256 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
9257 | { | |
fbee40df | 9258 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
9259 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
9260 | ||
49b14a5c | 9261 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
9262 | } |
9263 | ||
9264 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
9265 | { | |
fbee40df | 9266 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
9267 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
9268 | ||
49b14a5c | 9269 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
9270 | } |
9271 | ||
75f7f3ec VS |
9272 | /* Is 'a' after or equal to 'b'? */ |
9273 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
9274 | { | |
9275 | return !((a - b) & 0x80000000); | |
9276 | } | |
9277 | ||
9278 | static bool page_flip_finished(struct intel_crtc *crtc) | |
9279 | { | |
9280 | struct drm_device *dev = crtc->base.dev; | |
9281 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9282 | ||
9283 | /* | |
9284 | * The relevant registers doen't exist on pre-ctg. | |
9285 | * As the flip done interrupt doesn't trigger for mmio | |
9286 | * flips on gmch platforms, a flip count check isn't | |
9287 | * really needed there. But since ctg has the registers, | |
9288 | * include it in the check anyway. | |
9289 | */ | |
9290 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
9291 | return true; | |
9292 | ||
9293 | /* | |
9294 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
9295 | * used the same base address. In that case the mmio flip might | |
9296 | * have completed, but the CS hasn't even executed the flip yet. | |
9297 | * | |
9298 | * A flip count check isn't enough as the CS might have updated | |
9299 | * the base address just after start of vblank, but before we | |
9300 | * managed to process the interrupt. This means we'd complete the | |
9301 | * CS flip too soon. | |
9302 | * | |
9303 | * Combining both checks should get us a good enough result. It may | |
9304 | * still happen that the CS flip has been executed, but has not | |
9305 | * yet actually completed. But in case the base address is the same | |
9306 | * anyway, we don't really care. | |
9307 | */ | |
9308 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
9309 | crtc->unpin_work->gtt_offset && | |
9310 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)), | |
9311 | crtc->unpin_work->flip_count); | |
9312 | } | |
9313 | ||
6b95a207 KH |
9314 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
9315 | { | |
fbee40df | 9316 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
9317 | struct intel_crtc *intel_crtc = |
9318 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
9319 | unsigned long flags; | |
9320 | ||
e7d841ca CW |
9321 | /* NB: An MMIO update of the plane base pointer will also |
9322 | * generate a page-flip completion irq, i.e. every modeset | |
9323 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
9324 | */ | |
6b95a207 | 9325 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 9326 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 9327 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
9328 | spin_unlock_irqrestore(&dev->event_lock, flags); |
9329 | } | |
9330 | ||
eba905b2 | 9331 | static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
e7d841ca CW |
9332 | { |
9333 | /* Ensure that the work item is consistent when activating it ... */ | |
9334 | smp_wmb(); | |
9335 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); | |
9336 | /* and that it is marked active as soon as the irq could fire. */ | |
9337 | smp_wmb(); | |
9338 | } | |
9339 | ||
8c9f3aaf JB |
9340 | static int intel_gen2_queue_flip(struct drm_device *dev, |
9341 | struct drm_crtc *crtc, | |
9342 | struct drm_framebuffer *fb, | |
ed8d1975 | 9343 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9344 | struct intel_engine_cs *ring, |
ed8d1975 | 9345 | uint32_t flags) |
8c9f3aaf | 9346 | { |
8c9f3aaf | 9347 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
9348 | u32 flip_mask; |
9349 | int ret; | |
9350 | ||
6d90c952 | 9351 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 9352 | if (ret) |
4fa62c89 | 9353 | return ret; |
8c9f3aaf JB |
9354 | |
9355 | /* Can't queue multiple flips, so wait for the previous | |
9356 | * one to finish before executing the next. | |
9357 | */ | |
9358 | if (intel_crtc->plane) | |
9359 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
9360 | else | |
9361 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
9362 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
9363 | intel_ring_emit(ring, MI_NOOP); | |
9364 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
9365 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9366 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9367 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 | 9368 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca CW |
9369 | |
9370 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9371 | __intel_ring_advance(ring); |
83d4092b | 9372 | return 0; |
8c9f3aaf JB |
9373 | } |
9374 | ||
9375 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
9376 | struct drm_crtc *crtc, | |
9377 | struct drm_framebuffer *fb, | |
ed8d1975 | 9378 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9379 | struct intel_engine_cs *ring, |
ed8d1975 | 9380 | uint32_t flags) |
8c9f3aaf | 9381 | { |
8c9f3aaf | 9382 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
9383 | u32 flip_mask; |
9384 | int ret; | |
9385 | ||
6d90c952 | 9386 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 9387 | if (ret) |
4fa62c89 | 9388 | return ret; |
8c9f3aaf JB |
9389 | |
9390 | if (intel_crtc->plane) | |
9391 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
9392 | else | |
9393 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
9394 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
9395 | intel_ring_emit(ring, MI_NOOP); | |
9396 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
9397 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9398 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9399 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 DV |
9400 | intel_ring_emit(ring, MI_NOOP); |
9401 | ||
e7d841ca | 9402 | intel_mark_page_flip_active(intel_crtc); |
09246732 | 9403 | __intel_ring_advance(ring); |
83d4092b | 9404 | return 0; |
8c9f3aaf JB |
9405 | } |
9406 | ||
9407 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
9408 | struct drm_crtc *crtc, | |
9409 | struct drm_framebuffer *fb, | |
ed8d1975 | 9410 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9411 | struct intel_engine_cs *ring, |
ed8d1975 | 9412 | uint32_t flags) |
8c9f3aaf JB |
9413 | { |
9414 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9415 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9416 | uint32_t pf, pipesrc; | |
9417 | int ret; | |
9418 | ||
6d90c952 | 9419 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 9420 | if (ret) |
4fa62c89 | 9421 | return ret; |
8c9f3aaf JB |
9422 | |
9423 | /* i965+ uses the linear or tiled offsets from the | |
9424 | * Display Registers (which do not change across a page-flip) | |
9425 | * so we need only reprogram the base address. | |
9426 | */ | |
6d90c952 DV |
9427 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
9428 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9429 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9430 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | |
c2c75131 | 9431 | obj->tiling_mode); |
8c9f3aaf JB |
9432 | |
9433 | /* XXX Enabling the panel-fitter across page-flip is so far | |
9434 | * untested on non-native modes, so ignore it for now. | |
9435 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
9436 | */ | |
9437 | pf = 0; | |
9438 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 9439 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
9440 | |
9441 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9442 | __intel_ring_advance(ring); |
83d4092b | 9443 | return 0; |
8c9f3aaf JB |
9444 | } |
9445 | ||
9446 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
9447 | struct drm_crtc *crtc, | |
9448 | struct drm_framebuffer *fb, | |
ed8d1975 | 9449 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9450 | struct intel_engine_cs *ring, |
ed8d1975 | 9451 | uint32_t flags) |
8c9f3aaf JB |
9452 | { |
9453 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9454 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9455 | uint32_t pf, pipesrc; | |
9456 | int ret; | |
9457 | ||
6d90c952 | 9458 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 9459 | if (ret) |
4fa62c89 | 9460 | return ret; |
8c9f3aaf | 9461 | |
6d90c952 DV |
9462 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
9463 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9464 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
75f7f3ec | 9465 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8c9f3aaf | 9466 | |
dc257cf1 DV |
9467 | /* Contrary to the suggestions in the documentation, |
9468 | * "Enable Panel Fitter" does not seem to be required when page | |
9469 | * flipping with a non-native mode, and worse causes a normal | |
9470 | * modeset to fail. | |
9471 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
9472 | */ | |
9473 | pf = 0; | |
8c9f3aaf | 9474 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 9475 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
9476 | |
9477 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9478 | __intel_ring_advance(ring); |
83d4092b | 9479 | return 0; |
8c9f3aaf JB |
9480 | } |
9481 | ||
7c9017e5 JB |
9482 | static int intel_gen7_queue_flip(struct drm_device *dev, |
9483 | struct drm_crtc *crtc, | |
9484 | struct drm_framebuffer *fb, | |
ed8d1975 | 9485 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9486 | struct intel_engine_cs *ring, |
ed8d1975 | 9487 | uint32_t flags) |
7c9017e5 | 9488 | { |
7c9017e5 | 9489 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 9490 | uint32_t plane_bit = 0; |
ffe74d75 CW |
9491 | int len, ret; |
9492 | ||
eba905b2 | 9493 | switch (intel_crtc->plane) { |
cb05d8de DV |
9494 | case PLANE_A: |
9495 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
9496 | break; | |
9497 | case PLANE_B: | |
9498 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
9499 | break; | |
9500 | case PLANE_C: | |
9501 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
9502 | break; | |
9503 | default: | |
9504 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 9505 | return -ENODEV; |
cb05d8de DV |
9506 | } |
9507 | ||
ffe74d75 | 9508 | len = 4; |
f476828a | 9509 | if (ring->id == RCS) { |
ffe74d75 | 9510 | len += 6; |
f476828a DL |
9511 | /* |
9512 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
9513 | * 48bits addresses, and we need a NOOP for the batch size to | |
9514 | * stay even. | |
9515 | */ | |
9516 | if (IS_GEN8(dev)) | |
9517 | len += 2; | |
9518 | } | |
ffe74d75 | 9519 | |
f66fab8e VS |
9520 | /* |
9521 | * BSpec MI_DISPLAY_FLIP for IVB: | |
9522 | * "The full packet must be contained within the same cache line." | |
9523 | * | |
9524 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
9525 | * cacheline, if we ever start emitting more commands before | |
9526 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
9527 | * then do the cacheline alignment, and finally emit the | |
9528 | * MI_DISPLAY_FLIP. | |
9529 | */ | |
9530 | ret = intel_ring_cacheline_align(ring); | |
9531 | if (ret) | |
4fa62c89 | 9532 | return ret; |
f66fab8e | 9533 | |
ffe74d75 | 9534 | ret = intel_ring_begin(ring, len); |
7c9017e5 | 9535 | if (ret) |
4fa62c89 | 9536 | return ret; |
7c9017e5 | 9537 | |
ffe74d75 CW |
9538 | /* Unmask the flip-done completion message. Note that the bspec says that |
9539 | * we should do this for both the BCS and RCS, and that we must not unmask | |
9540 | * more than one flip event at any time (or ensure that one flip message | |
9541 | * can be sent by waiting for flip-done prior to queueing new flips). | |
9542 | * Experimentation says that BCS works despite DERRMR masking all | |
9543 | * flip-done completion events and that unmasking all planes at once | |
9544 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
9545 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
9546 | */ | |
9547 | if (ring->id == RCS) { | |
9548 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
9549 | intel_ring_emit(ring, DERRMR); | |
9550 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
9551 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
9552 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a DL |
9553 | if (IS_GEN8(dev)) |
9554 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) | | |
9555 | MI_SRM_LRM_GLOBAL_GTT); | |
9556 | else | |
9557 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | | |
9558 | MI_SRM_LRM_GLOBAL_GTT); | |
ffe74d75 CW |
9559 | intel_ring_emit(ring, DERRMR); |
9560 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
f476828a DL |
9561 | if (IS_GEN8(dev)) { |
9562 | intel_ring_emit(ring, 0); | |
9563 | intel_ring_emit(ring, MI_NOOP); | |
9564 | } | |
ffe74d75 CW |
9565 | } |
9566 | ||
cb05d8de | 9567 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 9568 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
75f7f3ec | 9569 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
7c9017e5 | 9570 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca CW |
9571 | |
9572 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9573 | __intel_ring_advance(ring); |
83d4092b | 9574 | return 0; |
7c9017e5 JB |
9575 | } |
9576 | ||
84c33a64 SG |
9577 | static bool use_mmio_flip(struct intel_engine_cs *ring, |
9578 | struct drm_i915_gem_object *obj) | |
9579 | { | |
9580 | /* | |
9581 | * This is not being used for older platforms, because | |
9582 | * non-availability of flip done interrupt forces us to use | |
9583 | * CS flips. Older platforms derive flip done using some clever | |
9584 | * tricks involving the flip_pending status bits and vblank irqs. | |
9585 | * So using MMIO flips there would disrupt this mechanism. | |
9586 | */ | |
9587 | ||
8e09bf83 CW |
9588 | if (ring == NULL) |
9589 | return true; | |
9590 | ||
84c33a64 SG |
9591 | if (INTEL_INFO(ring->dev)->gen < 5) |
9592 | return false; | |
9593 | ||
9594 | if (i915.use_mmio_flip < 0) | |
9595 | return false; | |
9596 | else if (i915.use_mmio_flip > 0) | |
9597 | return true; | |
14bf993e OM |
9598 | else if (i915.enable_execlists) |
9599 | return true; | |
84c33a64 SG |
9600 | else |
9601 | return ring != obj->ring; | |
9602 | } | |
9603 | ||
9604 | static void intel_do_mmio_flip(struct intel_crtc *intel_crtc) | |
9605 | { | |
9606 | struct drm_device *dev = intel_crtc->base.dev; | |
9607 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9608 | struct intel_framebuffer *intel_fb = | |
9609 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
9610 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
9611 | u32 dspcntr; | |
9612 | u32 reg; | |
9613 | ||
9614 | intel_mark_page_flip_active(intel_crtc); | |
9615 | ||
9616 | reg = DSPCNTR(intel_crtc->plane); | |
9617 | dspcntr = I915_READ(reg); | |
9618 | ||
9619 | if (INTEL_INFO(dev)->gen >= 4) { | |
9620 | if (obj->tiling_mode != I915_TILING_NONE) | |
9621 | dspcntr |= DISPPLANE_TILED; | |
9622 | else | |
9623 | dspcntr &= ~DISPPLANE_TILED; | |
9624 | } | |
9625 | I915_WRITE(reg, dspcntr); | |
9626 | ||
9627 | I915_WRITE(DSPSURF(intel_crtc->plane), | |
9628 | intel_crtc->unpin_work->gtt_offset); | |
9629 | POSTING_READ(DSPSURF(intel_crtc->plane)); | |
9630 | } | |
9631 | ||
9632 | static int intel_postpone_flip(struct drm_i915_gem_object *obj) | |
9633 | { | |
9634 | struct intel_engine_cs *ring; | |
9635 | int ret; | |
9636 | ||
9637 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
9638 | ||
9639 | if (!obj->last_write_seqno) | |
9640 | return 0; | |
9641 | ||
9642 | ring = obj->ring; | |
9643 | ||
9644 | if (i915_seqno_passed(ring->get_seqno(ring, true), | |
9645 | obj->last_write_seqno)) | |
9646 | return 0; | |
9647 | ||
9648 | ret = i915_gem_check_olr(ring, obj->last_write_seqno); | |
9649 | if (ret) | |
9650 | return ret; | |
9651 | ||
9652 | if (WARN_ON(!ring->irq_get(ring))) | |
9653 | return 0; | |
9654 | ||
9655 | return 1; | |
9656 | } | |
9657 | ||
9658 | void intel_notify_mmio_flip(struct intel_engine_cs *ring) | |
9659 | { | |
9660 | struct drm_i915_private *dev_priv = to_i915(ring->dev); | |
9661 | struct intel_crtc *intel_crtc; | |
9662 | unsigned long irq_flags; | |
9663 | u32 seqno; | |
9664 | ||
9665 | seqno = ring->get_seqno(ring, false); | |
9666 | ||
9667 | spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags); | |
9668 | for_each_intel_crtc(ring->dev, intel_crtc) { | |
9669 | struct intel_mmio_flip *mmio_flip; | |
9670 | ||
9671 | mmio_flip = &intel_crtc->mmio_flip; | |
9672 | if (mmio_flip->seqno == 0) | |
9673 | continue; | |
9674 | ||
9675 | if (ring->id != mmio_flip->ring_id) | |
9676 | continue; | |
9677 | ||
9678 | if (i915_seqno_passed(seqno, mmio_flip->seqno)) { | |
9679 | intel_do_mmio_flip(intel_crtc); | |
9680 | mmio_flip->seqno = 0; | |
9681 | ring->irq_put(ring); | |
9682 | } | |
9683 | } | |
9684 | spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags); | |
9685 | } | |
9686 | ||
9687 | static int intel_queue_mmio_flip(struct drm_device *dev, | |
9688 | struct drm_crtc *crtc, | |
9689 | struct drm_framebuffer *fb, | |
9690 | struct drm_i915_gem_object *obj, | |
9691 | struct intel_engine_cs *ring, | |
9692 | uint32_t flags) | |
9693 | { | |
9694 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9695 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9696 | unsigned long irq_flags; | |
9697 | int ret; | |
9698 | ||
9699 | if (WARN_ON(intel_crtc->mmio_flip.seqno)) | |
9700 | return -EBUSY; | |
9701 | ||
9702 | ret = intel_postpone_flip(obj); | |
9703 | if (ret < 0) | |
9704 | return ret; | |
9705 | if (ret == 0) { | |
9706 | intel_do_mmio_flip(intel_crtc); | |
9707 | return 0; | |
9708 | } | |
9709 | ||
9710 | spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags); | |
9711 | intel_crtc->mmio_flip.seqno = obj->last_write_seqno; | |
9712 | intel_crtc->mmio_flip.ring_id = obj->ring->id; | |
9713 | spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags); | |
9714 | ||
9715 | /* | |
9716 | * Double check to catch cases where irq fired before | |
9717 | * mmio flip data was ready | |
9718 | */ | |
9719 | intel_notify_mmio_flip(obj->ring); | |
9720 | return 0; | |
9721 | } | |
9722 | ||
8c9f3aaf JB |
9723 | static int intel_default_queue_flip(struct drm_device *dev, |
9724 | struct drm_crtc *crtc, | |
9725 | struct drm_framebuffer *fb, | |
ed8d1975 | 9726 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9727 | struct intel_engine_cs *ring, |
ed8d1975 | 9728 | uint32_t flags) |
8c9f3aaf JB |
9729 | { |
9730 | return -ENODEV; | |
9731 | } | |
9732 | ||
6b95a207 KH |
9733 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
9734 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
9735 | struct drm_pending_vblank_event *event, |
9736 | uint32_t page_flip_flags) | |
6b95a207 KH |
9737 | { |
9738 | struct drm_device *dev = crtc->dev; | |
9739 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 9740 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2ff8fde1 | 9741 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 | 9742 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
a071fa00 | 9743 | enum pipe pipe = intel_crtc->pipe; |
6b95a207 | 9744 | struct intel_unpin_work *work; |
a4872ba6 | 9745 | struct intel_engine_cs *ring; |
8c9f3aaf | 9746 | unsigned long flags; |
52e68630 | 9747 | int ret; |
6b95a207 | 9748 | |
2ff8fde1 MR |
9749 | /* |
9750 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
9751 | * check to be safe. In the future we may enable pageflipping from | |
9752 | * a disabled primary plane. | |
9753 | */ | |
9754 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
9755 | return -EBUSY; | |
9756 | ||
e6a595d2 | 9757 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 9758 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
9759 | return -EINVAL; |
9760 | ||
9761 | /* | |
9762 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
9763 | * Note that pitch changes could also affect these register. | |
9764 | */ | |
9765 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
9766 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
9767 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
9768 | return -EINVAL; |
9769 | ||
f900db47 CW |
9770 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
9771 | goto out_hang; | |
9772 | ||
b14c5679 | 9773 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
9774 | if (work == NULL) |
9775 | return -ENOMEM; | |
9776 | ||
6b95a207 | 9777 | work->event = event; |
b4a98e57 | 9778 | work->crtc = crtc; |
2ff8fde1 | 9779 | work->old_fb_obj = intel_fb_obj(old_fb); |
6b95a207 KH |
9780 | INIT_WORK(&work->work, intel_unpin_work_fn); |
9781 | ||
87b6b101 | 9782 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
9783 | if (ret) |
9784 | goto free_work; | |
9785 | ||
6b95a207 KH |
9786 | /* We borrow the event spin lock for protecting unpin_work */ |
9787 | spin_lock_irqsave(&dev->event_lock, flags); | |
9788 | if (intel_crtc->unpin_work) { | |
9789 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
9790 | kfree(work); | |
87b6b101 | 9791 | drm_crtc_vblank_put(crtc); |
468f0b44 CW |
9792 | |
9793 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
6b95a207 KH |
9794 | return -EBUSY; |
9795 | } | |
9796 | intel_crtc->unpin_work = work; | |
9797 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
9798 | ||
b4a98e57 CW |
9799 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
9800 | flush_workqueue(dev_priv->wq); | |
9801 | ||
79158103 CW |
9802 | ret = i915_mutex_lock_interruptible(dev); |
9803 | if (ret) | |
9804 | goto cleanup; | |
6b95a207 | 9805 | |
75dfca80 | 9806 | /* Reference the objects for the scheduled work. */ |
05394f39 CW |
9807 | drm_gem_object_reference(&work->old_fb_obj->base); |
9808 | drm_gem_object_reference(&obj->base); | |
6b95a207 | 9809 | |
f4510a27 | 9810 | crtc->primary->fb = fb; |
96b099fd | 9811 | |
e1f99ce6 | 9812 | work->pending_flip_obj = obj; |
e1f99ce6 | 9813 | |
4e5359cd SF |
9814 | work->enable_stall_check = true; |
9815 | ||
b4a98e57 | 9816 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 9817 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 9818 | |
75f7f3ec | 9819 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
a071fa00 | 9820 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1; |
75f7f3ec | 9821 | |
4fa62c89 VS |
9822 | if (IS_VALLEYVIEW(dev)) { |
9823 | ring = &dev_priv->ring[BCS]; | |
8e09bf83 CW |
9824 | if (obj->tiling_mode != work->old_fb_obj->tiling_mode) |
9825 | /* vlv: DISPLAY_FLIP fails to change tiling */ | |
9826 | ring = NULL; | |
2a92d5bc CW |
9827 | } else if (IS_IVYBRIDGE(dev)) { |
9828 | ring = &dev_priv->ring[BCS]; | |
4fa62c89 VS |
9829 | } else if (INTEL_INFO(dev)->gen >= 7) { |
9830 | ring = obj->ring; | |
9831 | if (ring == NULL || ring->id != RCS) | |
9832 | ring = &dev_priv->ring[BCS]; | |
9833 | } else { | |
9834 | ring = &dev_priv->ring[RCS]; | |
9835 | } | |
9836 | ||
9837 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); | |
8c9f3aaf JB |
9838 | if (ret) |
9839 | goto cleanup_pending; | |
6b95a207 | 9840 | |
4fa62c89 VS |
9841 | work->gtt_offset = |
9842 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset; | |
9843 | ||
84c33a64 SG |
9844 | if (use_mmio_flip(ring, obj)) |
9845 | ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring, | |
9846 | page_flip_flags); | |
9847 | else | |
9848 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring, | |
9849 | page_flip_flags); | |
4fa62c89 VS |
9850 | if (ret) |
9851 | goto cleanup_unpin; | |
9852 | ||
a071fa00 DV |
9853 | i915_gem_track_fb(work->old_fb_obj, obj, |
9854 | INTEL_FRONTBUFFER_PRIMARY(pipe)); | |
9855 | ||
7782de3b | 9856 | intel_disable_fbc(dev); |
f99d7069 | 9857 | intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
6b95a207 KH |
9858 | mutex_unlock(&dev->struct_mutex); |
9859 | ||
e5510fac JB |
9860 | trace_i915_flip_request(intel_crtc->plane, obj); |
9861 | ||
6b95a207 | 9862 | return 0; |
96b099fd | 9863 | |
4fa62c89 VS |
9864 | cleanup_unpin: |
9865 | intel_unpin_fb_obj(obj); | |
8c9f3aaf | 9866 | cleanup_pending: |
b4a98e57 | 9867 | atomic_dec(&intel_crtc->unpin_work_count); |
f4510a27 | 9868 | crtc->primary->fb = old_fb; |
05394f39 CW |
9869 | drm_gem_object_unreference(&work->old_fb_obj->base); |
9870 | drm_gem_object_unreference(&obj->base); | |
96b099fd CW |
9871 | mutex_unlock(&dev->struct_mutex); |
9872 | ||
79158103 | 9873 | cleanup: |
96b099fd CW |
9874 | spin_lock_irqsave(&dev->event_lock, flags); |
9875 | intel_crtc->unpin_work = NULL; | |
9876 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
9877 | ||
87b6b101 | 9878 | drm_crtc_vblank_put(crtc); |
7317c75e | 9879 | free_work: |
96b099fd CW |
9880 | kfree(work); |
9881 | ||
f900db47 CW |
9882 | if (ret == -EIO) { |
9883 | out_hang: | |
9884 | intel_crtc_wait_for_pending_flips(crtc); | |
9885 | ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb); | |
9886 | if (ret == 0 && event) | |
a071fa00 | 9887 | drm_send_vblank_event(dev, pipe, event); |
f900db47 | 9888 | } |
96b099fd | 9889 | return ret; |
6b95a207 KH |
9890 | } |
9891 | ||
f6e5b160 | 9892 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
9893 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
9894 | .load_lut = intel_crtc_load_lut, | |
f6e5b160 CW |
9895 | }; |
9896 | ||
9a935856 DV |
9897 | /** |
9898 | * intel_modeset_update_staged_output_state | |
9899 | * | |
9900 | * Updates the staged output configuration state, e.g. after we've read out the | |
9901 | * current hw state. | |
9902 | */ | |
9903 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) | |
f6e5b160 | 9904 | { |
7668851f | 9905 | struct intel_crtc *crtc; |
9a935856 DV |
9906 | struct intel_encoder *encoder; |
9907 | struct intel_connector *connector; | |
f6e5b160 | 9908 | |
9a935856 DV |
9909 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9910 | base.head) { | |
9911 | connector->new_encoder = | |
9912 | to_intel_encoder(connector->base.encoder); | |
9913 | } | |
f6e5b160 | 9914 | |
b2784e15 | 9915 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
9916 | encoder->new_crtc = |
9917 | to_intel_crtc(encoder->base.crtc); | |
9918 | } | |
7668851f | 9919 | |
d3fcc808 | 9920 | for_each_intel_crtc(dev, crtc) { |
7668851f | 9921 | crtc->new_enabled = crtc->base.enabled; |
7bd0a8e7 VS |
9922 | |
9923 | if (crtc->new_enabled) | |
9924 | crtc->new_config = &crtc->config; | |
9925 | else | |
9926 | crtc->new_config = NULL; | |
7668851f | 9927 | } |
f6e5b160 CW |
9928 | } |
9929 | ||
9a935856 DV |
9930 | /** |
9931 | * intel_modeset_commit_output_state | |
9932 | * | |
9933 | * This function copies the stage display pipe configuration to the real one. | |
9934 | */ | |
9935 | static void intel_modeset_commit_output_state(struct drm_device *dev) | |
9936 | { | |
7668851f | 9937 | struct intel_crtc *crtc; |
9a935856 DV |
9938 | struct intel_encoder *encoder; |
9939 | struct intel_connector *connector; | |
f6e5b160 | 9940 | |
9a935856 DV |
9941 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9942 | base.head) { | |
9943 | connector->base.encoder = &connector->new_encoder->base; | |
9944 | } | |
f6e5b160 | 9945 | |
b2784e15 | 9946 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
9947 | encoder->base.crtc = &encoder->new_crtc->base; |
9948 | } | |
7668851f | 9949 | |
d3fcc808 | 9950 | for_each_intel_crtc(dev, crtc) { |
7668851f VS |
9951 | crtc->base.enabled = crtc->new_enabled; |
9952 | } | |
9a935856 DV |
9953 | } |
9954 | ||
050f7aeb | 9955 | static void |
eba905b2 | 9956 | connected_sink_compute_bpp(struct intel_connector *connector, |
050f7aeb DV |
9957 | struct intel_crtc_config *pipe_config) |
9958 | { | |
9959 | int bpp = pipe_config->pipe_bpp; | |
9960 | ||
9961 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
9962 | connector->base.base.id, | |
c23cc417 | 9963 | connector->base.name); |
050f7aeb DV |
9964 | |
9965 | /* Don't use an invalid EDID bpc value */ | |
9966 | if (connector->base.display_info.bpc && | |
9967 | connector->base.display_info.bpc * 3 < bpp) { | |
9968 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
9969 | bpp, connector->base.display_info.bpc*3); | |
9970 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
9971 | } | |
9972 | ||
9973 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
9974 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
9975 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
9976 | bpp); | |
9977 | pipe_config->pipe_bpp = 24; | |
9978 | } | |
9979 | } | |
9980 | ||
4e53c2e0 | 9981 | static int |
050f7aeb DV |
9982 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
9983 | struct drm_framebuffer *fb, | |
9984 | struct intel_crtc_config *pipe_config) | |
4e53c2e0 | 9985 | { |
050f7aeb DV |
9986 | struct drm_device *dev = crtc->base.dev; |
9987 | struct intel_connector *connector; | |
4e53c2e0 DV |
9988 | int bpp; |
9989 | ||
d42264b1 DV |
9990 | switch (fb->pixel_format) { |
9991 | case DRM_FORMAT_C8: | |
4e53c2e0 DV |
9992 | bpp = 8*3; /* since we go through a colormap */ |
9993 | break; | |
d42264b1 DV |
9994 | case DRM_FORMAT_XRGB1555: |
9995 | case DRM_FORMAT_ARGB1555: | |
9996 | /* checked in intel_framebuffer_init already */ | |
9997 | if (WARN_ON(INTEL_INFO(dev)->gen > 3)) | |
9998 | return -EINVAL; | |
9999 | case DRM_FORMAT_RGB565: | |
4e53c2e0 DV |
10000 | bpp = 6*3; /* min is 18bpp */ |
10001 | break; | |
d42264b1 DV |
10002 | case DRM_FORMAT_XBGR8888: |
10003 | case DRM_FORMAT_ABGR8888: | |
10004 | /* checked in intel_framebuffer_init already */ | |
10005 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
10006 | return -EINVAL; | |
10007 | case DRM_FORMAT_XRGB8888: | |
10008 | case DRM_FORMAT_ARGB8888: | |
4e53c2e0 DV |
10009 | bpp = 8*3; |
10010 | break; | |
d42264b1 DV |
10011 | case DRM_FORMAT_XRGB2101010: |
10012 | case DRM_FORMAT_ARGB2101010: | |
10013 | case DRM_FORMAT_XBGR2101010: | |
10014 | case DRM_FORMAT_ABGR2101010: | |
10015 | /* checked in intel_framebuffer_init already */ | |
10016 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
baba133a | 10017 | return -EINVAL; |
4e53c2e0 DV |
10018 | bpp = 10*3; |
10019 | break; | |
baba133a | 10020 | /* TODO: gen4+ supports 16 bpc floating point, too. */ |
4e53c2e0 DV |
10021 | default: |
10022 | DRM_DEBUG_KMS("unsupported depth\n"); | |
10023 | return -EINVAL; | |
10024 | } | |
10025 | ||
4e53c2e0 DV |
10026 | pipe_config->pipe_bpp = bpp; |
10027 | ||
10028 | /* Clamp display bpp to EDID value */ | |
10029 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
050f7aeb | 10030 | base.head) { |
1b829e05 DV |
10031 | if (!connector->new_encoder || |
10032 | connector->new_encoder->new_crtc != crtc) | |
4e53c2e0 DV |
10033 | continue; |
10034 | ||
050f7aeb | 10035 | connected_sink_compute_bpp(connector, pipe_config); |
4e53c2e0 DV |
10036 | } |
10037 | ||
10038 | return bpp; | |
10039 | } | |
10040 | ||
644db711 DV |
10041 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
10042 | { | |
10043 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
10044 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 10045 | mode->crtc_clock, |
644db711 DV |
10046 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
10047 | mode->crtc_hsync_end, mode->crtc_htotal, | |
10048 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
10049 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
10050 | } | |
10051 | ||
c0b03411 DV |
10052 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
10053 | struct intel_crtc_config *pipe_config, | |
10054 | const char *context) | |
10055 | { | |
10056 | DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id, | |
10057 | context, pipe_name(crtc->pipe)); | |
10058 | ||
10059 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
10060 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
10061 | pipe_config->pipe_bpp, pipe_config->dither); | |
10062 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
10063 | pipe_config->has_pch_encoder, | |
10064 | pipe_config->fdi_lanes, | |
10065 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
10066 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
10067 | pipe_config->fdi_m_n.tu); | |
eb14cb74 VS |
10068 | DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
10069 | pipe_config->has_dp_encoder, | |
10070 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, | |
10071 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
10072 | pipe_config->dp_m_n.tu); | |
b95af8be VK |
10073 | |
10074 | DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", | |
10075 | pipe_config->has_dp_encoder, | |
10076 | pipe_config->dp_m2_n2.gmch_m, | |
10077 | pipe_config->dp_m2_n2.gmch_n, | |
10078 | pipe_config->dp_m2_n2.link_m, | |
10079 | pipe_config->dp_m2_n2.link_n, | |
10080 | pipe_config->dp_m2_n2.tu); | |
10081 | ||
c0b03411 DV |
10082 | DRM_DEBUG_KMS("requested mode:\n"); |
10083 | drm_mode_debug_printmodeline(&pipe_config->requested_mode); | |
10084 | DRM_DEBUG_KMS("adjusted mode:\n"); | |
10085 | drm_mode_debug_printmodeline(&pipe_config->adjusted_mode); | |
644db711 | 10086 | intel_dump_crtc_timings(&pipe_config->adjusted_mode); |
d71b8d4a | 10087 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
10088 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
10089 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
c0b03411 DV |
10090 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
10091 | pipe_config->gmch_pfit.control, | |
10092 | pipe_config->gmch_pfit.pgm_ratios, | |
10093 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 10094 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 10095 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
10096 | pipe_config->pch_pfit.size, |
10097 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 10098 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 10099 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
c0b03411 DV |
10100 | } |
10101 | ||
bc079e8b VS |
10102 | static bool encoders_cloneable(const struct intel_encoder *a, |
10103 | const struct intel_encoder *b) | |
accfc0c5 | 10104 | { |
bc079e8b VS |
10105 | /* masks could be asymmetric, so check both ways */ |
10106 | return a == b || (a->cloneable & (1 << b->type) && | |
10107 | b->cloneable & (1 << a->type)); | |
10108 | } | |
10109 | ||
10110 | static bool check_single_encoder_cloning(struct intel_crtc *crtc, | |
10111 | struct intel_encoder *encoder) | |
10112 | { | |
10113 | struct drm_device *dev = crtc->base.dev; | |
10114 | struct intel_encoder *source_encoder; | |
10115 | ||
b2784e15 | 10116 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b VS |
10117 | if (source_encoder->new_crtc != crtc) |
10118 | continue; | |
10119 | ||
10120 | if (!encoders_cloneable(encoder, source_encoder)) | |
10121 | return false; | |
10122 | } | |
10123 | ||
10124 | return true; | |
10125 | } | |
10126 | ||
10127 | static bool check_encoder_cloning(struct intel_crtc *crtc) | |
10128 | { | |
10129 | struct drm_device *dev = crtc->base.dev; | |
accfc0c5 DV |
10130 | struct intel_encoder *encoder; |
10131 | ||
b2784e15 | 10132 | for_each_intel_encoder(dev, encoder) { |
bc079e8b | 10133 | if (encoder->new_crtc != crtc) |
accfc0c5 DV |
10134 | continue; |
10135 | ||
bc079e8b VS |
10136 | if (!check_single_encoder_cloning(crtc, encoder)) |
10137 | return false; | |
accfc0c5 DV |
10138 | } |
10139 | ||
bc079e8b | 10140 | return true; |
accfc0c5 DV |
10141 | } |
10142 | ||
b8cecdf5 DV |
10143 | static struct intel_crtc_config * |
10144 | intel_modeset_pipe_config(struct drm_crtc *crtc, | |
4e53c2e0 | 10145 | struct drm_framebuffer *fb, |
b8cecdf5 | 10146 | struct drm_display_mode *mode) |
ee7b9f93 | 10147 | { |
7758a113 | 10148 | struct drm_device *dev = crtc->dev; |
7758a113 | 10149 | struct intel_encoder *encoder; |
b8cecdf5 | 10150 | struct intel_crtc_config *pipe_config; |
e29c22c0 DV |
10151 | int plane_bpp, ret = -EINVAL; |
10152 | bool retry = true; | |
ee7b9f93 | 10153 | |
bc079e8b | 10154 | if (!check_encoder_cloning(to_intel_crtc(crtc))) { |
accfc0c5 DV |
10155 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); |
10156 | return ERR_PTR(-EINVAL); | |
10157 | } | |
10158 | ||
b8cecdf5 DV |
10159 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
10160 | if (!pipe_config) | |
7758a113 DV |
10161 | return ERR_PTR(-ENOMEM); |
10162 | ||
b8cecdf5 DV |
10163 | drm_mode_copy(&pipe_config->adjusted_mode, mode); |
10164 | drm_mode_copy(&pipe_config->requested_mode, mode); | |
37327abd | 10165 | |
e143a21c DV |
10166 | pipe_config->cpu_transcoder = |
10167 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
c0d43d62 | 10168 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
b8cecdf5 | 10169 | |
2960bc9c ID |
10170 | /* |
10171 | * Sanitize sync polarity flags based on requested ones. If neither | |
10172 | * positive or negative polarity is requested, treat this as meaning | |
10173 | * negative polarity. | |
10174 | */ | |
10175 | if (!(pipe_config->adjusted_mode.flags & | |
10176 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) | |
10177 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; | |
10178 | ||
10179 | if (!(pipe_config->adjusted_mode.flags & | |
10180 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) | |
10181 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; | |
10182 | ||
050f7aeb DV |
10183 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
10184 | * plane pixel format and any sink constraints into account. Returns the | |
10185 | * source plane bpp so that dithering can be selected on mismatches | |
10186 | * after encoders and crtc also have had their say. */ | |
10187 | plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), | |
10188 | fb, pipe_config); | |
4e53c2e0 DV |
10189 | if (plane_bpp < 0) |
10190 | goto fail; | |
10191 | ||
e41a56be VS |
10192 | /* |
10193 | * Determine the real pipe dimensions. Note that stereo modes can | |
10194 | * increase the actual pipe size due to the frame doubling and | |
10195 | * insertion of additional space for blanks between the frame. This | |
10196 | * is stored in the crtc timings. We use the requested mode to do this | |
10197 | * computation to clearly distinguish it from the adjusted mode, which | |
10198 | * can be changed by the connectors in the below retry loop. | |
10199 | */ | |
10200 | drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE); | |
10201 | pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay; | |
10202 | pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay; | |
10203 | ||
e29c22c0 | 10204 | encoder_retry: |
ef1b460d | 10205 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 10206 | pipe_config->port_clock = 0; |
ef1b460d | 10207 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 10208 | |
135c81b8 | 10209 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
6ce70f5e | 10210 | drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE); |
135c81b8 | 10211 | |
7758a113 DV |
10212 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
10213 | * adjust it according to limitations or connector properties, and also | |
10214 | * a chance to reject the mode entirely. | |
47f1c6c9 | 10215 | */ |
b2784e15 | 10216 | for_each_intel_encoder(dev, encoder) { |
47f1c6c9 | 10217 | |
7758a113 DV |
10218 | if (&encoder->new_crtc->base != crtc) |
10219 | continue; | |
7ae89233 | 10220 | |
efea6e8e DV |
10221 | if (!(encoder->compute_config(encoder, pipe_config))) { |
10222 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
10223 | goto fail; |
10224 | } | |
ee7b9f93 | 10225 | } |
47f1c6c9 | 10226 | |
ff9a6750 DV |
10227 | /* Set default port clock if not overwritten by the encoder. Needs to be |
10228 | * done afterwards in case the encoder adjusts the mode. */ | |
10229 | if (!pipe_config->port_clock) | |
241bfc38 DL |
10230 | pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock |
10231 | * pipe_config->pixel_multiplier; | |
ff9a6750 | 10232 | |
a43f6e0f | 10233 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 10234 | if (ret < 0) { |
7758a113 DV |
10235 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
10236 | goto fail; | |
ee7b9f93 | 10237 | } |
e29c22c0 DV |
10238 | |
10239 | if (ret == RETRY) { | |
10240 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
10241 | ret = -EINVAL; | |
10242 | goto fail; | |
10243 | } | |
10244 | ||
10245 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
10246 | retry = false; | |
10247 | goto encoder_retry; | |
10248 | } | |
10249 | ||
4e53c2e0 DV |
10250 | pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; |
10251 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", | |
10252 | plane_bpp, pipe_config->pipe_bpp, pipe_config->dither); | |
10253 | ||
b8cecdf5 | 10254 | return pipe_config; |
7758a113 | 10255 | fail: |
b8cecdf5 | 10256 | kfree(pipe_config); |
e29c22c0 | 10257 | return ERR_PTR(ret); |
ee7b9f93 | 10258 | } |
47f1c6c9 | 10259 | |
e2e1ed41 DV |
10260 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
10261 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ | |
10262 | static void | |
10263 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, | |
10264 | unsigned *prepare_pipes, unsigned *disable_pipes) | |
79e53945 JB |
10265 | { |
10266 | struct intel_crtc *intel_crtc; | |
e2e1ed41 DV |
10267 | struct drm_device *dev = crtc->dev; |
10268 | struct intel_encoder *encoder; | |
10269 | struct intel_connector *connector; | |
10270 | struct drm_crtc *tmp_crtc; | |
79e53945 | 10271 | |
e2e1ed41 | 10272 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
79e53945 | 10273 | |
e2e1ed41 DV |
10274 | /* Check which crtcs have changed outputs connected to them, these need |
10275 | * to be part of the prepare_pipes mask. We don't (yet) support global | |
10276 | * modeset across multiple crtcs, so modeset_pipes will only have one | |
10277 | * bit set at most. */ | |
10278 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
10279 | base.head) { | |
10280 | if (connector->base.encoder == &connector->new_encoder->base) | |
10281 | continue; | |
79e53945 | 10282 | |
e2e1ed41 DV |
10283 | if (connector->base.encoder) { |
10284 | tmp_crtc = connector->base.encoder->crtc; | |
10285 | ||
10286 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
10287 | } | |
10288 | ||
10289 | if (connector->new_encoder) | |
10290 | *prepare_pipes |= | |
10291 | 1 << connector->new_encoder->new_crtc->pipe; | |
79e53945 JB |
10292 | } |
10293 | ||
b2784e15 | 10294 | for_each_intel_encoder(dev, encoder) { |
e2e1ed41 DV |
10295 | if (encoder->base.crtc == &encoder->new_crtc->base) |
10296 | continue; | |
10297 | ||
10298 | if (encoder->base.crtc) { | |
10299 | tmp_crtc = encoder->base.crtc; | |
10300 | ||
10301 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
10302 | } | |
10303 | ||
10304 | if (encoder->new_crtc) | |
10305 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; | |
80824003 JB |
10306 | } |
10307 | ||
7668851f | 10308 | /* Check for pipes that will be enabled/disabled ... */ |
d3fcc808 | 10309 | for_each_intel_crtc(dev, intel_crtc) { |
7668851f | 10310 | if (intel_crtc->base.enabled == intel_crtc->new_enabled) |
e2e1ed41 | 10311 | continue; |
7e7d76c3 | 10312 | |
7668851f | 10313 | if (!intel_crtc->new_enabled) |
e2e1ed41 | 10314 | *disable_pipes |= 1 << intel_crtc->pipe; |
7668851f VS |
10315 | else |
10316 | *prepare_pipes |= 1 << intel_crtc->pipe; | |
7e7d76c3 JB |
10317 | } |
10318 | ||
e2e1ed41 DV |
10319 | |
10320 | /* set_mode is also used to update properties on life display pipes. */ | |
10321 | intel_crtc = to_intel_crtc(crtc); | |
7668851f | 10322 | if (intel_crtc->new_enabled) |
e2e1ed41 DV |
10323 | *prepare_pipes |= 1 << intel_crtc->pipe; |
10324 | ||
b6c5164d DV |
10325 | /* |
10326 | * For simplicity do a full modeset on any pipe where the output routing | |
10327 | * changed. We could be more clever, but that would require us to be | |
10328 | * more careful with calling the relevant encoder->mode_set functions. | |
10329 | */ | |
e2e1ed41 DV |
10330 | if (*prepare_pipes) |
10331 | *modeset_pipes = *prepare_pipes; | |
10332 | ||
10333 | /* ... and mask these out. */ | |
10334 | *modeset_pipes &= ~(*disable_pipes); | |
10335 | *prepare_pipes &= ~(*disable_pipes); | |
b6c5164d DV |
10336 | |
10337 | /* | |
10338 | * HACK: We don't (yet) fully support global modesets. intel_set_config | |
10339 | * obies this rule, but the modeset restore mode of | |
10340 | * intel_modeset_setup_hw_state does not. | |
10341 | */ | |
10342 | *modeset_pipes &= 1 << intel_crtc->pipe; | |
10343 | *prepare_pipes &= 1 << intel_crtc->pipe; | |
e3641d3f DV |
10344 | |
10345 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", | |
10346 | *modeset_pipes, *prepare_pipes, *disable_pipes); | |
47f1c6c9 | 10347 | } |
79e53945 | 10348 | |
ea9d758d | 10349 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
f6e5b160 | 10350 | { |
ea9d758d | 10351 | struct drm_encoder *encoder; |
f6e5b160 | 10352 | struct drm_device *dev = crtc->dev; |
f6e5b160 | 10353 | |
ea9d758d DV |
10354 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
10355 | if (encoder->crtc == crtc) | |
10356 | return true; | |
10357 | ||
10358 | return false; | |
10359 | } | |
10360 | ||
10361 | static void | |
10362 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) | |
10363 | { | |
10364 | struct intel_encoder *intel_encoder; | |
10365 | struct intel_crtc *intel_crtc; | |
10366 | struct drm_connector *connector; | |
10367 | ||
b2784e15 | 10368 | for_each_intel_encoder(dev, intel_encoder) { |
ea9d758d DV |
10369 | if (!intel_encoder->base.crtc) |
10370 | continue; | |
10371 | ||
10372 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
10373 | ||
10374 | if (prepare_pipes & (1 << intel_crtc->pipe)) | |
10375 | intel_encoder->connectors_active = false; | |
10376 | } | |
10377 | ||
10378 | intel_modeset_commit_output_state(dev); | |
10379 | ||
7668851f | 10380 | /* Double check state. */ |
d3fcc808 | 10381 | for_each_intel_crtc(dev, intel_crtc) { |
7668851f | 10382 | WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base)); |
7bd0a8e7 VS |
10383 | WARN_ON(intel_crtc->new_config && |
10384 | intel_crtc->new_config != &intel_crtc->config); | |
10385 | WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config); | |
ea9d758d DV |
10386 | } |
10387 | ||
10388 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
10389 | if (!connector->encoder || !connector->encoder->crtc) | |
10390 | continue; | |
10391 | ||
10392 | intel_crtc = to_intel_crtc(connector->encoder->crtc); | |
10393 | ||
10394 | if (prepare_pipes & (1 << intel_crtc->pipe)) { | |
68d34720 DV |
10395 | struct drm_property *dpms_property = |
10396 | dev->mode_config.dpms_property; | |
10397 | ||
ea9d758d | 10398 | connector->dpms = DRM_MODE_DPMS_ON; |
662595df | 10399 | drm_object_property_set_value(&connector->base, |
68d34720 DV |
10400 | dpms_property, |
10401 | DRM_MODE_DPMS_ON); | |
ea9d758d DV |
10402 | |
10403 | intel_encoder = to_intel_encoder(connector->encoder); | |
10404 | intel_encoder->connectors_active = true; | |
10405 | } | |
10406 | } | |
10407 | ||
10408 | } | |
10409 | ||
3bd26263 | 10410 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 10411 | { |
3bd26263 | 10412 | int diff; |
f1f644dc JB |
10413 | |
10414 | if (clock1 == clock2) | |
10415 | return true; | |
10416 | ||
10417 | if (!clock1 || !clock2) | |
10418 | return false; | |
10419 | ||
10420 | diff = abs(clock1 - clock2); | |
10421 | ||
10422 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
10423 | return true; | |
10424 | ||
10425 | return false; | |
10426 | } | |
10427 | ||
25c5b266 DV |
10428 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
10429 | list_for_each_entry((intel_crtc), \ | |
10430 | &(dev)->mode_config.crtc_list, \ | |
10431 | base.head) \ | |
0973f18f | 10432 | if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 10433 | |
0e8ffe1b | 10434 | static bool |
2fa2fe9a DV |
10435 | intel_pipe_config_compare(struct drm_device *dev, |
10436 | struct intel_crtc_config *current_config, | |
0e8ffe1b DV |
10437 | struct intel_crtc_config *pipe_config) |
10438 | { | |
66e985c0 DV |
10439 | #define PIPE_CONF_CHECK_X(name) \ |
10440 | if (current_config->name != pipe_config->name) { \ | |
10441 | DRM_ERROR("mismatch in " #name " " \ | |
10442 | "(expected 0x%08x, found 0x%08x)\n", \ | |
10443 | current_config->name, \ | |
10444 | pipe_config->name); \ | |
10445 | return false; \ | |
10446 | } | |
10447 | ||
08a24034 DV |
10448 | #define PIPE_CONF_CHECK_I(name) \ |
10449 | if (current_config->name != pipe_config->name) { \ | |
10450 | DRM_ERROR("mismatch in " #name " " \ | |
10451 | "(expected %i, found %i)\n", \ | |
10452 | current_config->name, \ | |
10453 | pipe_config->name); \ | |
10454 | return false; \ | |
88adfff1 DV |
10455 | } |
10456 | ||
b95af8be VK |
10457 | /* This is required for BDW+ where there is only one set of registers for |
10458 | * switching between high and low RR. | |
10459 | * This macro can be used whenever a comparison has to be made between one | |
10460 | * hw state and multiple sw state variables. | |
10461 | */ | |
10462 | #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \ | |
10463 | if ((current_config->name != pipe_config->name) && \ | |
10464 | (current_config->alt_name != pipe_config->name)) { \ | |
10465 | DRM_ERROR("mismatch in " #name " " \ | |
10466 | "(expected %i or %i, found %i)\n", \ | |
10467 | current_config->name, \ | |
10468 | current_config->alt_name, \ | |
10469 | pipe_config->name); \ | |
10470 | return false; \ | |
10471 | } | |
10472 | ||
1bd1bd80 DV |
10473 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
10474 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
6f02488e | 10475 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
10476 | "(expected %i, found %i)\n", \ |
10477 | current_config->name & (mask), \ | |
10478 | pipe_config->name & (mask)); \ | |
10479 | return false; \ | |
10480 | } | |
10481 | ||
5e550656 VS |
10482 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
10483 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
10484 | DRM_ERROR("mismatch in " #name " " \ | |
10485 | "(expected %i, found %i)\n", \ | |
10486 | current_config->name, \ | |
10487 | pipe_config->name); \ | |
10488 | return false; \ | |
10489 | } | |
10490 | ||
bb760063 DV |
10491 | #define PIPE_CONF_QUIRK(quirk) \ |
10492 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
10493 | ||
eccb140b DV |
10494 | PIPE_CONF_CHECK_I(cpu_transcoder); |
10495 | ||
08a24034 DV |
10496 | PIPE_CONF_CHECK_I(has_pch_encoder); |
10497 | PIPE_CONF_CHECK_I(fdi_lanes); | |
72419203 DV |
10498 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
10499 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); | |
10500 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); | |
10501 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); | |
10502 | PIPE_CONF_CHECK_I(fdi_m_n.tu); | |
08a24034 | 10503 | |
eb14cb74 | 10504 | PIPE_CONF_CHECK_I(has_dp_encoder); |
b95af8be VK |
10505 | |
10506 | if (INTEL_INFO(dev)->gen < 8) { | |
10507 | PIPE_CONF_CHECK_I(dp_m_n.gmch_m); | |
10508 | PIPE_CONF_CHECK_I(dp_m_n.gmch_n); | |
10509 | PIPE_CONF_CHECK_I(dp_m_n.link_m); | |
10510 | PIPE_CONF_CHECK_I(dp_m_n.link_n); | |
10511 | PIPE_CONF_CHECK_I(dp_m_n.tu); | |
10512 | ||
10513 | if (current_config->has_drrs) { | |
10514 | PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m); | |
10515 | PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n); | |
10516 | PIPE_CONF_CHECK_I(dp_m2_n2.link_m); | |
10517 | PIPE_CONF_CHECK_I(dp_m2_n2.link_n); | |
10518 | PIPE_CONF_CHECK_I(dp_m2_n2.tu); | |
10519 | } | |
10520 | } else { | |
10521 | PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m); | |
10522 | PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n); | |
10523 | PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m); | |
10524 | PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n); | |
10525 | PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu); | |
10526 | } | |
eb14cb74 | 10527 | |
1bd1bd80 DV |
10528 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay); |
10529 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal); | |
10530 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start); | |
10531 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end); | |
10532 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start); | |
10533 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end); | |
10534 | ||
10535 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay); | |
10536 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal); | |
10537 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start); | |
10538 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end); | |
10539 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start); | |
10540 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end); | |
10541 | ||
c93f54cf | 10542 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 10543 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 DV |
10544 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
10545 | IS_VALLEYVIEW(dev)) | |
10546 | PIPE_CONF_CHECK_I(limited_color_range); | |
6c49f241 | 10547 | |
9ed109a7 DV |
10548 | PIPE_CONF_CHECK_I(has_audio); |
10549 | ||
1bd1bd80 DV |
10550 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
10551 | DRM_MODE_FLAG_INTERLACE); | |
10552 | ||
bb760063 DV |
10553 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
10554 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
10555 | DRM_MODE_FLAG_PHSYNC); | |
10556 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
10557 | DRM_MODE_FLAG_NHSYNC); | |
10558 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
10559 | DRM_MODE_FLAG_PVSYNC); | |
10560 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
10561 | DRM_MODE_FLAG_NVSYNC); | |
10562 | } | |
045ac3b5 | 10563 | |
37327abd VS |
10564 | PIPE_CONF_CHECK_I(pipe_src_w); |
10565 | PIPE_CONF_CHECK_I(pipe_src_h); | |
1bd1bd80 | 10566 | |
9953599b DV |
10567 | /* |
10568 | * FIXME: BIOS likes to set up a cloned config with lvds+external | |
10569 | * screen. Since we don't yet re-compute the pipe config when moving | |
10570 | * just the lvds port away to another pipe the sw tracking won't match. | |
10571 | * | |
10572 | * Proper atomic modesets with recomputed global state will fix this. | |
10573 | * Until then just don't check gmch state for inherited modes. | |
10574 | */ | |
10575 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) { | |
10576 | PIPE_CONF_CHECK_I(gmch_pfit.control); | |
10577 | /* pfit ratios are autocomputed by the hw on gen4+ */ | |
10578 | if (INTEL_INFO(dev)->gen < 4) | |
10579 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
10580 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); | |
10581 | } | |
10582 | ||
fd4daa9c CW |
10583 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
10584 | if (current_config->pch_pfit.enabled) { | |
10585 | PIPE_CONF_CHECK_I(pch_pfit.pos); | |
10586 | PIPE_CONF_CHECK_I(pch_pfit.size); | |
10587 | } | |
2fa2fe9a | 10588 | |
e59150dc JB |
10589 | /* BDW+ don't expose a synchronous way to read the state */ |
10590 | if (IS_HASWELL(dev)) | |
10591 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 10592 | |
282740f7 VS |
10593 | PIPE_CONF_CHECK_I(double_wide); |
10594 | ||
26804afd DV |
10595 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
10596 | ||
c0d43d62 | 10597 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 10598 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 10599 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
10600 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
10601 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 10602 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
c0d43d62 | 10603 | |
42571aef VS |
10604 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
10605 | PIPE_CONF_CHECK_I(pipe_bpp); | |
10606 | ||
a9a7e98a JB |
10607 | PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock); |
10608 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); | |
5e550656 | 10609 | |
66e985c0 | 10610 | #undef PIPE_CONF_CHECK_X |
08a24034 | 10611 | #undef PIPE_CONF_CHECK_I |
b95af8be | 10612 | #undef PIPE_CONF_CHECK_I_ALT |
1bd1bd80 | 10613 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 10614 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 10615 | #undef PIPE_CONF_QUIRK |
88adfff1 | 10616 | |
0e8ffe1b DV |
10617 | return true; |
10618 | } | |
10619 | ||
91d1b4bd DV |
10620 | static void |
10621 | check_connector_state(struct drm_device *dev) | |
8af6cf88 | 10622 | { |
8af6cf88 DV |
10623 | struct intel_connector *connector; |
10624 | ||
10625 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
10626 | base.head) { | |
10627 | /* This also checks the encoder/connector hw state with the | |
10628 | * ->get_hw_state callbacks. */ | |
10629 | intel_connector_check_state(connector); | |
10630 | ||
10631 | WARN(&connector->new_encoder->base != connector->base.encoder, | |
10632 | "connector's staged encoder doesn't match current encoder\n"); | |
10633 | } | |
91d1b4bd DV |
10634 | } |
10635 | ||
10636 | static void | |
10637 | check_encoder_state(struct drm_device *dev) | |
10638 | { | |
10639 | struct intel_encoder *encoder; | |
10640 | struct intel_connector *connector; | |
8af6cf88 | 10641 | |
b2784e15 | 10642 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 DV |
10643 | bool enabled = false; |
10644 | bool active = false; | |
10645 | enum pipe pipe, tracked_pipe; | |
10646 | ||
10647 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
10648 | encoder->base.base.id, | |
8e329a03 | 10649 | encoder->base.name); |
8af6cf88 DV |
10650 | |
10651 | WARN(&encoder->new_crtc->base != encoder->base.crtc, | |
10652 | "encoder's stage crtc doesn't match current crtc\n"); | |
10653 | WARN(encoder->connectors_active && !encoder->base.crtc, | |
10654 | "encoder's active_connectors set, but no crtc\n"); | |
10655 | ||
10656 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
10657 | base.head) { | |
10658 | if (connector->base.encoder != &encoder->base) | |
10659 | continue; | |
10660 | enabled = true; | |
10661 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) | |
10662 | active = true; | |
10663 | } | |
0e32b39c DA |
10664 | /* |
10665 | * for MST connectors if we unplug the connector is gone | |
10666 | * away but the encoder is still connected to a crtc | |
10667 | * until a modeset happens in response to the hotplug. | |
10668 | */ | |
10669 | if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST) | |
10670 | continue; | |
10671 | ||
8af6cf88 DV |
10672 | WARN(!!encoder->base.crtc != enabled, |
10673 | "encoder's enabled state mismatch " | |
10674 | "(expected %i, found %i)\n", | |
10675 | !!encoder->base.crtc, enabled); | |
10676 | WARN(active && !encoder->base.crtc, | |
10677 | "active encoder with no crtc\n"); | |
10678 | ||
10679 | WARN(encoder->connectors_active != active, | |
10680 | "encoder's computed active state doesn't match tracked active state " | |
10681 | "(expected %i, found %i)\n", active, encoder->connectors_active); | |
10682 | ||
10683 | active = encoder->get_hw_state(encoder, &pipe); | |
10684 | WARN(active != encoder->connectors_active, | |
10685 | "encoder's hw state doesn't match sw tracking " | |
10686 | "(expected %i, found %i)\n", | |
10687 | encoder->connectors_active, active); | |
10688 | ||
10689 | if (!encoder->base.crtc) | |
10690 | continue; | |
10691 | ||
10692 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
10693 | WARN(active && pipe != tracked_pipe, | |
10694 | "active encoder's pipe doesn't match" | |
10695 | "(expected %i, found %i)\n", | |
10696 | tracked_pipe, pipe); | |
10697 | ||
10698 | } | |
91d1b4bd DV |
10699 | } |
10700 | ||
10701 | static void | |
10702 | check_crtc_state(struct drm_device *dev) | |
10703 | { | |
fbee40df | 10704 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
10705 | struct intel_crtc *crtc; |
10706 | struct intel_encoder *encoder; | |
10707 | struct intel_crtc_config pipe_config; | |
8af6cf88 | 10708 | |
d3fcc808 | 10709 | for_each_intel_crtc(dev, crtc) { |
8af6cf88 DV |
10710 | bool enabled = false; |
10711 | bool active = false; | |
10712 | ||
045ac3b5 JB |
10713 | memset(&pipe_config, 0, sizeof(pipe_config)); |
10714 | ||
8af6cf88 DV |
10715 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
10716 | crtc->base.base.id); | |
10717 | ||
10718 | WARN(crtc->active && !crtc->base.enabled, | |
10719 | "active crtc, but not enabled in sw tracking\n"); | |
10720 | ||
b2784e15 | 10721 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 DV |
10722 | if (encoder->base.crtc != &crtc->base) |
10723 | continue; | |
10724 | enabled = true; | |
10725 | if (encoder->connectors_active) | |
10726 | active = true; | |
10727 | } | |
6c49f241 | 10728 | |
8af6cf88 DV |
10729 | WARN(active != crtc->active, |
10730 | "crtc's computed active state doesn't match tracked active state " | |
10731 | "(expected %i, found %i)\n", active, crtc->active); | |
10732 | WARN(enabled != crtc->base.enabled, | |
10733 | "crtc's computed enabled state doesn't match tracked enabled state " | |
10734 | "(expected %i, found %i)\n", enabled, crtc->base.enabled); | |
10735 | ||
0e8ffe1b DV |
10736 | active = dev_priv->display.get_pipe_config(crtc, |
10737 | &pipe_config); | |
d62cf62a DV |
10738 | |
10739 | /* hw state is inconsistent with the pipe A quirk */ | |
10740 | if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
10741 | active = crtc->active; | |
10742 | ||
b2784e15 | 10743 | for_each_intel_encoder(dev, encoder) { |
3eaba51c | 10744 | enum pipe pipe; |
6c49f241 DV |
10745 | if (encoder->base.crtc != &crtc->base) |
10746 | continue; | |
1d37b689 | 10747 | if (encoder->get_hw_state(encoder, &pipe)) |
6c49f241 DV |
10748 | encoder->get_config(encoder, &pipe_config); |
10749 | } | |
10750 | ||
0e8ffe1b DV |
10751 | WARN(crtc->active != active, |
10752 | "crtc active state doesn't match with hw state " | |
10753 | "(expected %i, found %i)\n", crtc->active, active); | |
10754 | ||
c0b03411 DV |
10755 | if (active && |
10756 | !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) { | |
10757 | WARN(1, "pipe state doesn't match!\n"); | |
10758 | intel_dump_pipe_config(crtc, &pipe_config, | |
10759 | "[hw state]"); | |
10760 | intel_dump_pipe_config(crtc, &crtc->config, | |
10761 | "[sw state]"); | |
10762 | } | |
8af6cf88 DV |
10763 | } |
10764 | } | |
10765 | ||
91d1b4bd DV |
10766 | static void |
10767 | check_shared_dpll_state(struct drm_device *dev) | |
10768 | { | |
fbee40df | 10769 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
10770 | struct intel_crtc *crtc; |
10771 | struct intel_dpll_hw_state dpll_hw_state; | |
10772 | int i; | |
5358901f DV |
10773 | |
10774 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
10775 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
10776 | int enabled_crtcs = 0, active_crtcs = 0; | |
10777 | bool active; | |
10778 | ||
10779 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
10780 | ||
10781 | DRM_DEBUG_KMS("%s\n", pll->name); | |
10782 | ||
10783 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
10784 | ||
10785 | WARN(pll->active > pll->refcount, | |
10786 | "more active pll users than references: %i vs %i\n", | |
10787 | pll->active, pll->refcount); | |
10788 | WARN(pll->active && !pll->on, | |
10789 | "pll in active use but not on in sw tracking\n"); | |
35c95375 DV |
10790 | WARN(pll->on && !pll->active, |
10791 | "pll in on but not on in use in sw tracking\n"); | |
5358901f DV |
10792 | WARN(pll->on != active, |
10793 | "pll on state mismatch (expected %i, found %i)\n", | |
10794 | pll->on, active); | |
10795 | ||
d3fcc808 | 10796 | for_each_intel_crtc(dev, crtc) { |
5358901f DV |
10797 | if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll) |
10798 | enabled_crtcs++; | |
10799 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
10800 | active_crtcs++; | |
10801 | } | |
10802 | WARN(pll->active != active_crtcs, | |
10803 | "pll active crtcs mismatch (expected %i, found %i)\n", | |
10804 | pll->active, active_crtcs); | |
10805 | WARN(pll->refcount != enabled_crtcs, | |
10806 | "pll enabled crtcs mismatch (expected %i, found %i)\n", | |
10807 | pll->refcount, enabled_crtcs); | |
66e985c0 DV |
10808 | |
10809 | WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state, | |
10810 | sizeof(dpll_hw_state)), | |
10811 | "pll hw state mismatch\n"); | |
5358901f | 10812 | } |
8af6cf88 DV |
10813 | } |
10814 | ||
91d1b4bd DV |
10815 | void |
10816 | intel_modeset_check_state(struct drm_device *dev) | |
10817 | { | |
10818 | check_connector_state(dev); | |
10819 | check_encoder_state(dev); | |
10820 | check_crtc_state(dev); | |
10821 | check_shared_dpll_state(dev); | |
10822 | } | |
10823 | ||
18442d08 VS |
10824 | void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, |
10825 | int dotclock) | |
10826 | { | |
10827 | /* | |
10828 | * FDI already provided one idea for the dotclock. | |
10829 | * Yell if the encoder disagrees. | |
10830 | */ | |
241bfc38 | 10831 | WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock), |
18442d08 | 10832 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
241bfc38 | 10833 | pipe_config->adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
10834 | } |
10835 | ||
80715b2f VS |
10836 | static void update_scanline_offset(struct intel_crtc *crtc) |
10837 | { | |
10838 | struct drm_device *dev = crtc->base.dev; | |
10839 | ||
10840 | /* | |
10841 | * The scanline counter increments at the leading edge of hsync. | |
10842 | * | |
10843 | * On most platforms it starts counting from vtotal-1 on the | |
10844 | * first active line. That means the scanline counter value is | |
10845 | * always one less than what we would expect. Ie. just after | |
10846 | * start of vblank, which also occurs at start of hsync (on the | |
10847 | * last active line), the scanline counter will read vblank_start-1. | |
10848 | * | |
10849 | * On gen2 the scanline counter starts counting from 1 instead | |
10850 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
10851 | * to keep the value positive), instead of adding one. | |
10852 | * | |
10853 | * On HSW+ the behaviour of the scanline counter depends on the output | |
10854 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
10855 | * there's an extra 1 line difference. So we need to add two instead of | |
10856 | * one to the value. | |
10857 | */ | |
10858 | if (IS_GEN2(dev)) { | |
10859 | const struct drm_display_mode *mode = &crtc->config.adjusted_mode; | |
10860 | int vtotal; | |
10861 | ||
10862 | vtotal = mode->crtc_vtotal; | |
10863 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
10864 | vtotal /= 2; | |
10865 | ||
10866 | crtc->scanline_offset = vtotal - 1; | |
10867 | } else if (HAS_DDI(dev) && | |
10868 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) { | |
10869 | crtc->scanline_offset = 2; | |
10870 | } else | |
10871 | crtc->scanline_offset = 1; | |
10872 | } | |
10873 | ||
f30da187 DV |
10874 | static int __intel_set_mode(struct drm_crtc *crtc, |
10875 | struct drm_display_mode *mode, | |
10876 | int x, int y, struct drm_framebuffer *fb) | |
a6778b3c DV |
10877 | { |
10878 | struct drm_device *dev = crtc->dev; | |
fbee40df | 10879 | struct drm_i915_private *dev_priv = dev->dev_private; |
4b4b9238 | 10880 | struct drm_display_mode *saved_mode; |
b8cecdf5 | 10881 | struct intel_crtc_config *pipe_config = NULL; |
25c5b266 DV |
10882 | struct intel_crtc *intel_crtc; |
10883 | unsigned disable_pipes, prepare_pipes, modeset_pipes; | |
c0c36b94 | 10884 | int ret = 0; |
a6778b3c | 10885 | |
4b4b9238 | 10886 | saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL); |
c0c36b94 CW |
10887 | if (!saved_mode) |
10888 | return -ENOMEM; | |
a6778b3c | 10889 | |
e2e1ed41 | 10890 | intel_modeset_affected_pipes(crtc, &modeset_pipes, |
25c5b266 DV |
10891 | &prepare_pipes, &disable_pipes); |
10892 | ||
3ac18232 | 10893 | *saved_mode = crtc->mode; |
a6778b3c | 10894 | |
25c5b266 DV |
10895 | /* Hack: Because we don't (yet) support global modeset on multiple |
10896 | * crtcs, we don't keep track of the new mode for more than one crtc. | |
10897 | * Hence simply check whether any bit is set in modeset_pipes in all the | |
10898 | * pieces of code that are not yet converted to deal with mutliple crtcs | |
10899 | * changing their mode at the same time. */ | |
25c5b266 | 10900 | if (modeset_pipes) { |
4e53c2e0 | 10901 | pipe_config = intel_modeset_pipe_config(crtc, fb, mode); |
b8cecdf5 DV |
10902 | if (IS_ERR(pipe_config)) { |
10903 | ret = PTR_ERR(pipe_config); | |
10904 | pipe_config = NULL; | |
10905 | ||
3ac18232 | 10906 | goto out; |
25c5b266 | 10907 | } |
c0b03411 DV |
10908 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
10909 | "[modeset]"); | |
50741abc | 10910 | to_intel_crtc(crtc)->new_config = pipe_config; |
25c5b266 | 10911 | } |
a6778b3c | 10912 | |
30a970c6 JB |
10913 | /* |
10914 | * See if the config requires any additional preparation, e.g. | |
10915 | * to adjust global state with pipes off. We need to do this | |
10916 | * here so we can get the modeset_pipe updated config for the new | |
10917 | * mode set on this crtc. For other crtcs we need to use the | |
10918 | * adjusted_mode bits in the crtc directly. | |
10919 | */ | |
c164f833 | 10920 | if (IS_VALLEYVIEW(dev)) { |
2f2d7aa1 | 10921 | valleyview_modeset_global_pipes(dev, &prepare_pipes); |
30a970c6 | 10922 | |
c164f833 VS |
10923 | /* may have added more to prepare_pipes than we should */ |
10924 | prepare_pipes &= ~disable_pipes; | |
10925 | } | |
10926 | ||
460da916 DV |
10927 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
10928 | intel_crtc_disable(&intel_crtc->base); | |
10929 | ||
ea9d758d DV |
10930 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
10931 | if (intel_crtc->base.enabled) | |
10932 | dev_priv->display.crtc_disable(&intel_crtc->base); | |
10933 | } | |
a6778b3c | 10934 | |
6c4c86f5 DV |
10935 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
10936 | * to set it here already despite that we pass it down the callchain. | |
f6e5b160 | 10937 | */ |
b8cecdf5 | 10938 | if (modeset_pipes) { |
25c5b266 | 10939 | crtc->mode = *mode; |
b8cecdf5 DV |
10940 | /* mode_set/enable/disable functions rely on a correct pipe |
10941 | * config. */ | |
10942 | to_intel_crtc(crtc)->config = *pipe_config; | |
50741abc | 10943 | to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config; |
c326c0a9 VS |
10944 | |
10945 | /* | |
10946 | * Calculate and store various constants which | |
10947 | * are later needed by vblank and swap-completion | |
10948 | * timestamping. They are derived from true hwmode. | |
10949 | */ | |
10950 | drm_calc_timestamping_constants(crtc, | |
10951 | &pipe_config->adjusted_mode); | |
b8cecdf5 | 10952 | } |
7758a113 | 10953 | |
ea9d758d DV |
10954 | /* Only after disabling all output pipelines that will be changed can we |
10955 | * update the the output configuration. */ | |
10956 | intel_modeset_update_state(dev, prepare_pipes); | |
f6e5b160 | 10957 | |
47fab737 DV |
10958 | if (dev_priv->display.modeset_global_resources) |
10959 | dev_priv->display.modeset_global_resources(dev); | |
10960 | ||
a6778b3c DV |
10961 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
10962 | * on the DPLL. | |
f6e5b160 | 10963 | */ |
25c5b266 | 10964 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
2ff8fde1 MR |
10965 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
10966 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb); | |
10967 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
4c10794f DV |
10968 | |
10969 | mutex_lock(&dev->struct_mutex); | |
10970 | ret = intel_pin_and_fence_fb_obj(dev, | |
a071fa00 | 10971 | obj, |
4c10794f DV |
10972 | NULL); |
10973 | if (ret != 0) { | |
10974 | DRM_ERROR("pin & fence failed\n"); | |
10975 | mutex_unlock(&dev->struct_mutex); | |
10976 | goto done; | |
10977 | } | |
2ff8fde1 | 10978 | if (old_fb) |
a071fa00 | 10979 | intel_unpin_fb_obj(old_obj); |
a071fa00 DV |
10980 | i915_gem_track_fb(old_obj, obj, |
10981 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe)); | |
4c10794f DV |
10982 | mutex_unlock(&dev->struct_mutex); |
10983 | ||
10984 | crtc->primary->fb = fb; | |
10985 | crtc->x = x; | |
10986 | crtc->y = y; | |
10987 | ||
4271b753 DV |
10988 | ret = dev_priv->display.crtc_mode_set(&intel_crtc->base, |
10989 | x, y, fb); | |
c0c36b94 CW |
10990 | if (ret) |
10991 | goto done; | |
a6778b3c DV |
10992 | } |
10993 | ||
10994 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ | |
80715b2f VS |
10995 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
10996 | update_scanline_offset(intel_crtc); | |
10997 | ||
25c5b266 | 10998 | dev_priv->display.crtc_enable(&intel_crtc->base); |
80715b2f | 10999 | } |
a6778b3c | 11000 | |
a6778b3c DV |
11001 | /* FIXME: add subpixel order */ |
11002 | done: | |
4b4b9238 | 11003 | if (ret && crtc->enabled) |
3ac18232 | 11004 | crtc->mode = *saved_mode; |
a6778b3c | 11005 | |
3ac18232 | 11006 | out: |
b8cecdf5 | 11007 | kfree(pipe_config); |
3ac18232 | 11008 | kfree(saved_mode); |
a6778b3c | 11009 | return ret; |
f6e5b160 CW |
11010 | } |
11011 | ||
e7457a9a DL |
11012 | static int intel_set_mode(struct drm_crtc *crtc, |
11013 | struct drm_display_mode *mode, | |
11014 | int x, int y, struct drm_framebuffer *fb) | |
f30da187 DV |
11015 | { |
11016 | int ret; | |
11017 | ||
11018 | ret = __intel_set_mode(crtc, mode, x, y, fb); | |
11019 | ||
11020 | if (ret == 0) | |
11021 | intel_modeset_check_state(crtc->dev); | |
11022 | ||
11023 | return ret; | |
11024 | } | |
11025 | ||
c0c36b94 CW |
11026 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
11027 | { | |
f4510a27 | 11028 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb); |
c0c36b94 CW |
11029 | } |
11030 | ||
25c5b266 DV |
11031 | #undef for_each_intel_crtc_masked |
11032 | ||
d9e55608 DV |
11033 | static void intel_set_config_free(struct intel_set_config *config) |
11034 | { | |
11035 | if (!config) | |
11036 | return; | |
11037 | ||
1aa4b628 DV |
11038 | kfree(config->save_connector_encoders); |
11039 | kfree(config->save_encoder_crtcs); | |
7668851f | 11040 | kfree(config->save_crtc_enabled); |
d9e55608 DV |
11041 | kfree(config); |
11042 | } | |
11043 | ||
85f9eb71 DV |
11044 | static int intel_set_config_save_state(struct drm_device *dev, |
11045 | struct intel_set_config *config) | |
11046 | { | |
7668851f | 11047 | struct drm_crtc *crtc; |
85f9eb71 DV |
11048 | struct drm_encoder *encoder; |
11049 | struct drm_connector *connector; | |
11050 | int count; | |
11051 | ||
7668851f VS |
11052 | config->save_crtc_enabled = |
11053 | kcalloc(dev->mode_config.num_crtc, | |
11054 | sizeof(bool), GFP_KERNEL); | |
11055 | if (!config->save_crtc_enabled) | |
11056 | return -ENOMEM; | |
11057 | ||
1aa4b628 DV |
11058 | config->save_encoder_crtcs = |
11059 | kcalloc(dev->mode_config.num_encoder, | |
11060 | sizeof(struct drm_crtc *), GFP_KERNEL); | |
11061 | if (!config->save_encoder_crtcs) | |
85f9eb71 DV |
11062 | return -ENOMEM; |
11063 | ||
1aa4b628 DV |
11064 | config->save_connector_encoders = |
11065 | kcalloc(dev->mode_config.num_connector, | |
11066 | sizeof(struct drm_encoder *), GFP_KERNEL); | |
11067 | if (!config->save_connector_encoders) | |
85f9eb71 DV |
11068 | return -ENOMEM; |
11069 | ||
11070 | /* Copy data. Note that driver private data is not affected. | |
11071 | * Should anything bad happen only the expected state is | |
11072 | * restored, not the drivers personal bookkeeping. | |
11073 | */ | |
7668851f | 11074 | count = 0; |
70e1e0ec | 11075 | for_each_crtc(dev, crtc) { |
7668851f VS |
11076 | config->save_crtc_enabled[count++] = crtc->enabled; |
11077 | } | |
11078 | ||
85f9eb71 DV |
11079 | count = 0; |
11080 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1aa4b628 | 11081 | config->save_encoder_crtcs[count++] = encoder->crtc; |
85f9eb71 DV |
11082 | } |
11083 | ||
11084 | count = 0; | |
11085 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1aa4b628 | 11086 | config->save_connector_encoders[count++] = connector->encoder; |
85f9eb71 DV |
11087 | } |
11088 | ||
11089 | return 0; | |
11090 | } | |
11091 | ||
11092 | static void intel_set_config_restore_state(struct drm_device *dev, | |
11093 | struct intel_set_config *config) | |
11094 | { | |
7668851f | 11095 | struct intel_crtc *crtc; |
9a935856 DV |
11096 | struct intel_encoder *encoder; |
11097 | struct intel_connector *connector; | |
85f9eb71 DV |
11098 | int count; |
11099 | ||
7668851f | 11100 | count = 0; |
d3fcc808 | 11101 | for_each_intel_crtc(dev, crtc) { |
7668851f | 11102 | crtc->new_enabled = config->save_crtc_enabled[count++]; |
7bd0a8e7 VS |
11103 | |
11104 | if (crtc->new_enabled) | |
11105 | crtc->new_config = &crtc->config; | |
11106 | else | |
11107 | crtc->new_config = NULL; | |
7668851f VS |
11108 | } |
11109 | ||
85f9eb71 | 11110 | count = 0; |
b2784e15 | 11111 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
11112 | encoder->new_crtc = |
11113 | to_intel_crtc(config->save_encoder_crtcs[count++]); | |
85f9eb71 DV |
11114 | } |
11115 | ||
11116 | count = 0; | |
9a935856 DV |
11117 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
11118 | connector->new_encoder = | |
11119 | to_intel_encoder(config->save_connector_encoders[count++]); | |
85f9eb71 DV |
11120 | } |
11121 | } | |
11122 | ||
e3de42b6 | 11123 | static bool |
2e57f47d | 11124 | is_crtc_connector_off(struct drm_mode_set *set) |
e3de42b6 ID |
11125 | { |
11126 | int i; | |
11127 | ||
2e57f47d CW |
11128 | if (set->num_connectors == 0) |
11129 | return false; | |
11130 | ||
11131 | if (WARN_ON(set->connectors == NULL)) | |
11132 | return false; | |
11133 | ||
11134 | for (i = 0; i < set->num_connectors; i++) | |
11135 | if (set->connectors[i]->encoder && | |
11136 | set->connectors[i]->encoder->crtc == set->crtc && | |
11137 | set->connectors[i]->dpms != DRM_MODE_DPMS_ON) | |
e3de42b6 ID |
11138 | return true; |
11139 | ||
11140 | return false; | |
11141 | } | |
11142 | ||
5e2b584e DV |
11143 | static void |
11144 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, | |
11145 | struct intel_set_config *config) | |
11146 | { | |
11147 | ||
11148 | /* We should be able to check here if the fb has the same properties | |
11149 | * and then just flip_or_move it */ | |
2e57f47d CW |
11150 | if (is_crtc_connector_off(set)) { |
11151 | config->mode_changed = true; | |
f4510a27 | 11152 | } else if (set->crtc->primary->fb != set->fb) { |
3b150f08 MR |
11153 | /* |
11154 | * If we have no fb, we can only flip as long as the crtc is | |
11155 | * active, otherwise we need a full mode set. The crtc may | |
11156 | * be active if we've only disabled the primary plane, or | |
11157 | * in fastboot situations. | |
11158 | */ | |
f4510a27 | 11159 | if (set->crtc->primary->fb == NULL) { |
319d9827 JB |
11160 | struct intel_crtc *intel_crtc = |
11161 | to_intel_crtc(set->crtc); | |
11162 | ||
3b150f08 | 11163 | if (intel_crtc->active) { |
319d9827 JB |
11164 | DRM_DEBUG_KMS("crtc has no fb, will flip\n"); |
11165 | config->fb_changed = true; | |
11166 | } else { | |
11167 | DRM_DEBUG_KMS("inactive crtc, full mode set\n"); | |
11168 | config->mode_changed = true; | |
11169 | } | |
5e2b584e DV |
11170 | } else if (set->fb == NULL) { |
11171 | config->mode_changed = true; | |
72f4901e | 11172 | } else if (set->fb->pixel_format != |
f4510a27 | 11173 | set->crtc->primary->fb->pixel_format) { |
5e2b584e | 11174 | config->mode_changed = true; |
e3de42b6 | 11175 | } else { |
5e2b584e | 11176 | config->fb_changed = true; |
e3de42b6 | 11177 | } |
5e2b584e DV |
11178 | } |
11179 | ||
835c5873 | 11180 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
5e2b584e DV |
11181 | config->fb_changed = true; |
11182 | ||
11183 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { | |
11184 | DRM_DEBUG_KMS("modes are different, full mode set\n"); | |
11185 | drm_mode_debug_printmodeline(&set->crtc->mode); | |
11186 | drm_mode_debug_printmodeline(set->mode); | |
11187 | config->mode_changed = true; | |
11188 | } | |
a1d95703 CW |
11189 | |
11190 | DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n", | |
11191 | set->crtc->base.id, config->mode_changed, config->fb_changed); | |
5e2b584e DV |
11192 | } |
11193 | ||
2e431051 | 11194 | static int |
9a935856 DV |
11195 | intel_modeset_stage_output_state(struct drm_device *dev, |
11196 | struct drm_mode_set *set, | |
11197 | struct intel_set_config *config) | |
50f56119 | 11198 | { |
9a935856 DV |
11199 | struct intel_connector *connector; |
11200 | struct intel_encoder *encoder; | |
7668851f | 11201 | struct intel_crtc *crtc; |
f3f08572 | 11202 | int ro; |
50f56119 | 11203 | |
9abdda74 | 11204 | /* The upper layers ensure that we either disable a crtc or have a list |
9a935856 DV |
11205 | * of connectors. For paranoia, double-check this. */ |
11206 | WARN_ON(!set->fb && (set->num_connectors != 0)); | |
11207 | WARN_ON(set->fb && (set->num_connectors == 0)); | |
11208 | ||
9a935856 DV |
11209 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
11210 | base.head) { | |
11211 | /* Otherwise traverse passed in connector list and get encoders | |
11212 | * for them. */ | |
50f56119 | 11213 | for (ro = 0; ro < set->num_connectors; ro++) { |
9a935856 | 11214 | if (set->connectors[ro] == &connector->base) { |
0e32b39c | 11215 | connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe); |
50f56119 DV |
11216 | break; |
11217 | } | |
11218 | } | |
11219 | ||
9a935856 DV |
11220 | /* If we disable the crtc, disable all its connectors. Also, if |
11221 | * the connector is on the changing crtc but not on the new | |
11222 | * connector list, disable it. */ | |
11223 | if ((!set->fb || ro == set->num_connectors) && | |
11224 | connector->base.encoder && | |
11225 | connector->base.encoder->crtc == set->crtc) { | |
11226 | connector->new_encoder = NULL; | |
11227 | ||
11228 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", | |
11229 | connector->base.base.id, | |
c23cc417 | 11230 | connector->base.name); |
9a935856 DV |
11231 | } |
11232 | ||
11233 | ||
11234 | if (&connector->new_encoder->base != connector->base.encoder) { | |
50f56119 | 11235 | DRM_DEBUG_KMS("encoder changed, full mode switch\n"); |
5e2b584e | 11236 | config->mode_changed = true; |
50f56119 DV |
11237 | } |
11238 | } | |
9a935856 | 11239 | /* connector->new_encoder is now updated for all connectors. */ |
50f56119 | 11240 | |
9a935856 | 11241 | /* Update crtc of enabled connectors. */ |
9a935856 DV |
11242 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
11243 | base.head) { | |
7668851f VS |
11244 | struct drm_crtc *new_crtc; |
11245 | ||
9a935856 | 11246 | if (!connector->new_encoder) |
50f56119 DV |
11247 | continue; |
11248 | ||
9a935856 | 11249 | new_crtc = connector->new_encoder->base.crtc; |
50f56119 DV |
11250 | |
11251 | for (ro = 0; ro < set->num_connectors; ro++) { | |
9a935856 | 11252 | if (set->connectors[ro] == &connector->base) |
50f56119 DV |
11253 | new_crtc = set->crtc; |
11254 | } | |
11255 | ||
11256 | /* Make sure the new CRTC will work with the encoder */ | |
14509916 TR |
11257 | if (!drm_encoder_crtc_ok(&connector->new_encoder->base, |
11258 | new_crtc)) { | |
5e2b584e | 11259 | return -EINVAL; |
50f56119 | 11260 | } |
0e32b39c | 11261 | connector->new_encoder->new_crtc = to_intel_crtc(new_crtc); |
9a935856 DV |
11262 | |
11263 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", | |
11264 | connector->base.base.id, | |
c23cc417 | 11265 | connector->base.name, |
9a935856 DV |
11266 | new_crtc->base.id); |
11267 | } | |
11268 | ||
11269 | /* Check for any encoders that needs to be disabled. */ | |
b2784e15 | 11270 | for_each_intel_encoder(dev, encoder) { |
5a65f358 | 11271 | int num_connectors = 0; |
9a935856 DV |
11272 | list_for_each_entry(connector, |
11273 | &dev->mode_config.connector_list, | |
11274 | base.head) { | |
11275 | if (connector->new_encoder == encoder) { | |
11276 | WARN_ON(!connector->new_encoder->new_crtc); | |
5a65f358 | 11277 | num_connectors++; |
9a935856 DV |
11278 | } |
11279 | } | |
5a65f358 PZ |
11280 | |
11281 | if (num_connectors == 0) | |
11282 | encoder->new_crtc = NULL; | |
11283 | else if (num_connectors > 1) | |
11284 | return -EINVAL; | |
11285 | ||
9a935856 DV |
11286 | /* Only now check for crtc changes so we don't miss encoders |
11287 | * that will be disabled. */ | |
11288 | if (&encoder->new_crtc->base != encoder->base.crtc) { | |
50f56119 | 11289 | DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
5e2b584e | 11290 | config->mode_changed = true; |
50f56119 DV |
11291 | } |
11292 | } | |
9a935856 | 11293 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
0e32b39c DA |
11294 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
11295 | base.head) { | |
11296 | if (connector->new_encoder) | |
11297 | if (connector->new_encoder != connector->encoder) | |
11298 | connector->encoder = connector->new_encoder; | |
11299 | } | |
d3fcc808 | 11300 | for_each_intel_crtc(dev, crtc) { |
7668851f VS |
11301 | crtc->new_enabled = false; |
11302 | ||
b2784e15 | 11303 | for_each_intel_encoder(dev, encoder) { |
7668851f VS |
11304 | if (encoder->new_crtc == crtc) { |
11305 | crtc->new_enabled = true; | |
11306 | break; | |
11307 | } | |
11308 | } | |
11309 | ||
11310 | if (crtc->new_enabled != crtc->base.enabled) { | |
11311 | DRM_DEBUG_KMS("crtc %sabled, full mode switch\n", | |
11312 | crtc->new_enabled ? "en" : "dis"); | |
11313 | config->mode_changed = true; | |
11314 | } | |
7bd0a8e7 VS |
11315 | |
11316 | if (crtc->new_enabled) | |
11317 | crtc->new_config = &crtc->config; | |
11318 | else | |
11319 | crtc->new_config = NULL; | |
7668851f VS |
11320 | } |
11321 | ||
2e431051 DV |
11322 | return 0; |
11323 | } | |
11324 | ||
7d00a1f5 VS |
11325 | static void disable_crtc_nofb(struct intel_crtc *crtc) |
11326 | { | |
11327 | struct drm_device *dev = crtc->base.dev; | |
11328 | struct intel_encoder *encoder; | |
11329 | struct intel_connector *connector; | |
11330 | ||
11331 | DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n", | |
11332 | pipe_name(crtc->pipe)); | |
11333 | ||
11334 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { | |
11335 | if (connector->new_encoder && | |
11336 | connector->new_encoder->new_crtc == crtc) | |
11337 | connector->new_encoder = NULL; | |
11338 | } | |
11339 | ||
b2784e15 | 11340 | for_each_intel_encoder(dev, encoder) { |
7d00a1f5 VS |
11341 | if (encoder->new_crtc == crtc) |
11342 | encoder->new_crtc = NULL; | |
11343 | } | |
11344 | ||
11345 | crtc->new_enabled = false; | |
7bd0a8e7 | 11346 | crtc->new_config = NULL; |
7d00a1f5 VS |
11347 | } |
11348 | ||
2e431051 DV |
11349 | static int intel_crtc_set_config(struct drm_mode_set *set) |
11350 | { | |
11351 | struct drm_device *dev; | |
2e431051 DV |
11352 | struct drm_mode_set save_set; |
11353 | struct intel_set_config *config; | |
11354 | int ret; | |
2e431051 | 11355 | |
8d3e375e DV |
11356 | BUG_ON(!set); |
11357 | BUG_ON(!set->crtc); | |
11358 | BUG_ON(!set->crtc->helper_private); | |
2e431051 | 11359 | |
7e53f3a4 DV |
11360 | /* Enforce sane interface api - has been abused by the fb helper. */ |
11361 | BUG_ON(!set->mode && set->fb); | |
11362 | BUG_ON(set->fb && set->num_connectors == 0); | |
431e50f7 | 11363 | |
2e431051 DV |
11364 | if (set->fb) { |
11365 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", | |
11366 | set->crtc->base.id, set->fb->base.id, | |
11367 | (int)set->num_connectors, set->x, set->y); | |
11368 | } else { | |
11369 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); | |
2e431051 DV |
11370 | } |
11371 | ||
11372 | dev = set->crtc->dev; | |
11373 | ||
11374 | ret = -ENOMEM; | |
11375 | config = kzalloc(sizeof(*config), GFP_KERNEL); | |
11376 | if (!config) | |
11377 | goto out_config; | |
11378 | ||
11379 | ret = intel_set_config_save_state(dev, config); | |
11380 | if (ret) | |
11381 | goto out_config; | |
11382 | ||
11383 | save_set.crtc = set->crtc; | |
11384 | save_set.mode = &set->crtc->mode; | |
11385 | save_set.x = set->crtc->x; | |
11386 | save_set.y = set->crtc->y; | |
f4510a27 | 11387 | save_set.fb = set->crtc->primary->fb; |
2e431051 DV |
11388 | |
11389 | /* Compute whether we need a full modeset, only an fb base update or no | |
11390 | * change at all. In the future we might also check whether only the | |
11391 | * mode changed, e.g. for LVDS where we only change the panel fitter in | |
11392 | * such cases. */ | |
11393 | intel_set_config_compute_mode_changes(set, config); | |
11394 | ||
9a935856 | 11395 | ret = intel_modeset_stage_output_state(dev, set, config); |
2e431051 DV |
11396 | if (ret) |
11397 | goto fail; | |
11398 | ||
5e2b584e | 11399 | if (config->mode_changed) { |
c0c36b94 CW |
11400 | ret = intel_set_mode(set->crtc, set->mode, |
11401 | set->x, set->y, set->fb); | |
5e2b584e | 11402 | } else if (config->fb_changed) { |
3b150f08 MR |
11403 | struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc); |
11404 | ||
4878cae2 VS |
11405 | intel_crtc_wait_for_pending_flips(set->crtc); |
11406 | ||
4f660f49 | 11407 | ret = intel_pipe_set_base(set->crtc, |
94352cf9 | 11408 | set->x, set->y, set->fb); |
3b150f08 MR |
11409 | |
11410 | /* | |
11411 | * We need to make sure the primary plane is re-enabled if it | |
11412 | * has previously been turned off. | |
11413 | */ | |
11414 | if (!intel_crtc->primary_enabled && ret == 0) { | |
11415 | WARN_ON(!intel_crtc->active); | |
fdd508a6 | 11416 | intel_enable_primary_hw_plane(set->crtc->primary, set->crtc); |
3b150f08 MR |
11417 | } |
11418 | ||
7ca51a3a JB |
11419 | /* |
11420 | * In the fastboot case this may be our only check of the | |
11421 | * state after boot. It would be better to only do it on | |
11422 | * the first update, but we don't have a nice way of doing that | |
11423 | * (and really, set_config isn't used much for high freq page | |
11424 | * flipping, so increasing its cost here shouldn't be a big | |
11425 | * deal). | |
11426 | */ | |
d330a953 | 11427 | if (i915.fastboot && ret == 0) |
7ca51a3a | 11428 | intel_modeset_check_state(set->crtc->dev); |
50f56119 DV |
11429 | } |
11430 | ||
2d05eae1 | 11431 | if (ret) { |
bf67dfeb DV |
11432 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
11433 | set->crtc->base.id, ret); | |
50f56119 | 11434 | fail: |
2d05eae1 | 11435 | intel_set_config_restore_state(dev, config); |
50f56119 | 11436 | |
7d00a1f5 VS |
11437 | /* |
11438 | * HACK: if the pipe was on, but we didn't have a framebuffer, | |
11439 | * force the pipe off to avoid oopsing in the modeset code | |
11440 | * due to fb==NULL. This should only happen during boot since | |
11441 | * we don't yet reconstruct the FB from the hardware state. | |
11442 | */ | |
11443 | if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb) | |
11444 | disable_crtc_nofb(to_intel_crtc(save_set.crtc)); | |
11445 | ||
2d05eae1 CW |
11446 | /* Try to restore the config */ |
11447 | if (config->mode_changed && | |
11448 | intel_set_mode(save_set.crtc, save_set.mode, | |
11449 | save_set.x, save_set.y, save_set.fb)) | |
11450 | DRM_ERROR("failed to restore config after modeset failure\n"); | |
11451 | } | |
50f56119 | 11452 | |
d9e55608 DV |
11453 | out_config: |
11454 | intel_set_config_free(config); | |
50f56119 DV |
11455 | return ret; |
11456 | } | |
f6e5b160 CW |
11457 | |
11458 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
f6e5b160 | 11459 | .gamma_set = intel_crtc_gamma_set, |
50f56119 | 11460 | .set_config = intel_crtc_set_config, |
f6e5b160 CW |
11461 | .destroy = intel_crtc_destroy, |
11462 | .page_flip = intel_crtc_page_flip, | |
11463 | }; | |
11464 | ||
5358901f DV |
11465 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
11466 | struct intel_shared_dpll *pll, | |
11467 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 11468 | { |
5358901f | 11469 | uint32_t val; |
ee7b9f93 | 11470 | |
bd2bb1b9 PZ |
11471 | if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
11472 | return false; | |
11473 | ||
5358901f | 11474 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
11475 | hw_state->dpll = val; |
11476 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
11477 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
11478 | |
11479 | return val & DPLL_VCO_ENABLE; | |
11480 | } | |
11481 | ||
15bdd4cf DV |
11482 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
11483 | struct intel_shared_dpll *pll) | |
11484 | { | |
11485 | I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0); | |
11486 | I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1); | |
11487 | } | |
11488 | ||
e7b903d2 DV |
11489 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
11490 | struct intel_shared_dpll *pll) | |
11491 | { | |
e7b903d2 | 11492 | /* PCH refclock must be enabled first */ |
89eff4be | 11493 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 11494 | |
15bdd4cf DV |
11495 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); |
11496 | ||
11497 | /* Wait for the clocks to stabilize. */ | |
11498 | POSTING_READ(PCH_DPLL(pll->id)); | |
11499 | udelay(150); | |
11500 | ||
11501 | /* The pixel multiplier can only be updated once the | |
11502 | * DPLL is enabled and the clocks are stable. | |
11503 | * | |
11504 | * So write it again. | |
11505 | */ | |
11506 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); | |
11507 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
11508 | udelay(200); |
11509 | } | |
11510 | ||
11511 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
11512 | struct intel_shared_dpll *pll) | |
11513 | { | |
11514 | struct drm_device *dev = dev_priv->dev; | |
11515 | struct intel_crtc *crtc; | |
e7b903d2 DV |
11516 | |
11517 | /* Make sure no transcoder isn't still depending on us. */ | |
d3fcc808 | 11518 | for_each_intel_crtc(dev, crtc) { |
e7b903d2 DV |
11519 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
11520 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
11521 | } |
11522 | ||
15bdd4cf DV |
11523 | I915_WRITE(PCH_DPLL(pll->id), 0); |
11524 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
11525 | udelay(200); |
11526 | } | |
11527 | ||
46edb027 DV |
11528 | static char *ibx_pch_dpll_names[] = { |
11529 | "PCH DPLL A", | |
11530 | "PCH DPLL B", | |
11531 | }; | |
11532 | ||
7c74ade1 | 11533 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 11534 | { |
e7b903d2 | 11535 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
11536 | int i; |
11537 | ||
7c74ade1 | 11538 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 11539 | |
e72f9fbf | 11540 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
11541 | dev_priv->shared_dplls[i].id = i; |
11542 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 11543 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
11544 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
11545 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
11546 | dev_priv->shared_dplls[i].get_hw_state = |
11547 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
11548 | } |
11549 | } | |
11550 | ||
7c74ade1 DV |
11551 | static void intel_shared_dpll_init(struct drm_device *dev) |
11552 | { | |
e7b903d2 | 11553 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 | 11554 | |
9cd86933 DV |
11555 | if (HAS_DDI(dev)) |
11556 | intel_ddi_pll_init(dev); | |
11557 | else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
7c74ade1 DV |
11558 | ibx_pch_dpll_init(dev); |
11559 | else | |
11560 | dev_priv->num_shared_dpll = 0; | |
11561 | ||
11562 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
11563 | } |
11564 | ||
465c120c MR |
11565 | static int |
11566 | intel_primary_plane_disable(struct drm_plane *plane) | |
11567 | { | |
11568 | struct drm_device *dev = plane->dev; | |
465c120c MR |
11569 | struct intel_crtc *intel_crtc; |
11570 | ||
11571 | if (!plane->fb) | |
11572 | return 0; | |
11573 | ||
11574 | BUG_ON(!plane->crtc); | |
11575 | ||
11576 | intel_crtc = to_intel_crtc(plane->crtc); | |
11577 | ||
11578 | /* | |
11579 | * Even though we checked plane->fb above, it's still possible that | |
11580 | * the primary plane has been implicitly disabled because the crtc | |
11581 | * coordinates given weren't visible, or because we detected | |
11582 | * that it was 100% covered by a sprite plane. Or, the CRTC may be | |
11583 | * off and we've set a fb, but haven't actually turned on the CRTC yet. | |
11584 | * In either case, we need to unpin the FB and let the fb pointer get | |
11585 | * updated, but otherwise we don't need to touch the hardware. | |
11586 | */ | |
11587 | if (!intel_crtc->primary_enabled) | |
11588 | goto disable_unpin; | |
11589 | ||
11590 | intel_crtc_wait_for_pending_flips(plane->crtc); | |
fdd508a6 VS |
11591 | intel_disable_primary_hw_plane(plane, plane->crtc); |
11592 | ||
465c120c | 11593 | disable_unpin: |
4c34574f | 11594 | mutex_lock(&dev->struct_mutex); |
2ff8fde1 | 11595 | i915_gem_track_fb(intel_fb_obj(plane->fb), NULL, |
a071fa00 | 11596 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe)); |
2ff8fde1 | 11597 | intel_unpin_fb_obj(intel_fb_obj(plane->fb)); |
4c34574f | 11598 | mutex_unlock(&dev->struct_mutex); |
465c120c MR |
11599 | plane->fb = NULL; |
11600 | ||
11601 | return 0; | |
11602 | } | |
11603 | ||
11604 | static int | |
11605 | intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc, | |
11606 | struct drm_framebuffer *fb, int crtc_x, int crtc_y, | |
11607 | unsigned int crtc_w, unsigned int crtc_h, | |
11608 | uint32_t src_x, uint32_t src_y, | |
11609 | uint32_t src_w, uint32_t src_h) | |
11610 | { | |
11611 | struct drm_device *dev = crtc->dev; | |
48404c1e | 11612 | struct drm_i915_private *dev_priv = dev->dev_private; |
465c120c | 11613 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2ff8fde1 MR |
11614 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
11615 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb); | |
465c120c MR |
11616 | struct drm_rect dest = { |
11617 | /* integer pixels */ | |
11618 | .x1 = crtc_x, | |
11619 | .y1 = crtc_y, | |
11620 | .x2 = crtc_x + crtc_w, | |
11621 | .y2 = crtc_y + crtc_h, | |
11622 | }; | |
11623 | struct drm_rect src = { | |
11624 | /* 16.16 fixed point */ | |
11625 | .x1 = src_x, | |
11626 | .y1 = src_y, | |
11627 | .x2 = src_x + src_w, | |
11628 | .y2 = src_y + src_h, | |
11629 | }; | |
11630 | const struct drm_rect clip = { | |
11631 | /* integer pixels */ | |
11632 | .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0, | |
11633 | .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0, | |
11634 | }; | |
ce54d85a SJ |
11635 | const struct { |
11636 | int crtc_x, crtc_y; | |
11637 | unsigned int crtc_w, crtc_h; | |
11638 | uint32_t src_x, src_y, src_w, src_h; | |
11639 | } orig = { | |
11640 | .crtc_x = crtc_x, | |
11641 | .crtc_y = crtc_y, | |
11642 | .crtc_w = crtc_w, | |
11643 | .crtc_h = crtc_h, | |
11644 | .src_x = src_x, | |
11645 | .src_y = src_y, | |
11646 | .src_w = src_w, | |
11647 | .src_h = src_h, | |
11648 | }; | |
11649 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
465c120c MR |
11650 | bool visible; |
11651 | int ret; | |
11652 | ||
11653 | ret = drm_plane_helper_check_update(plane, crtc, fb, | |
11654 | &src, &dest, &clip, | |
11655 | DRM_PLANE_HELPER_NO_SCALING, | |
11656 | DRM_PLANE_HELPER_NO_SCALING, | |
11657 | false, true, &visible); | |
11658 | ||
11659 | if (ret) | |
11660 | return ret; | |
11661 | ||
11662 | /* | |
11663 | * If the CRTC isn't enabled, we're just pinning the framebuffer, | |
11664 | * updating the fb pointer, and returning without touching the | |
11665 | * hardware. This allows us to later do a drmModeSetCrtc with fb=-1 to | |
11666 | * turn on the display with all planes setup as desired. | |
11667 | */ | |
11668 | if (!crtc->enabled) { | |
4c34574f MR |
11669 | mutex_lock(&dev->struct_mutex); |
11670 | ||
465c120c MR |
11671 | /* |
11672 | * If we already called setplane while the crtc was disabled, | |
11673 | * we may have an fb pinned; unpin it. | |
11674 | */ | |
11675 | if (plane->fb) | |
a071fa00 DV |
11676 | intel_unpin_fb_obj(old_obj); |
11677 | ||
11678 | i915_gem_track_fb(old_obj, obj, | |
11679 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe)); | |
465c120c MR |
11680 | |
11681 | /* Pin and return without programming hardware */ | |
4c34574f MR |
11682 | ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); |
11683 | mutex_unlock(&dev->struct_mutex); | |
11684 | ||
11685 | return ret; | |
465c120c MR |
11686 | } |
11687 | ||
11688 | intel_crtc_wait_for_pending_flips(crtc); | |
11689 | ||
11690 | /* | |
11691 | * If clipping results in a non-visible primary plane, we'll disable | |
11692 | * the primary plane. Note that this is a bit different than what | |
11693 | * happens if userspace explicitly disables the plane by passing fb=0 | |
11694 | * because plane->fb still gets set and pinned. | |
11695 | */ | |
11696 | if (!visible) { | |
4c34574f MR |
11697 | mutex_lock(&dev->struct_mutex); |
11698 | ||
465c120c MR |
11699 | /* |
11700 | * Try to pin the new fb first so that we can bail out if we | |
11701 | * fail. | |
11702 | */ | |
11703 | if (plane->fb != fb) { | |
a071fa00 | 11704 | ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); |
4c34574f MR |
11705 | if (ret) { |
11706 | mutex_unlock(&dev->struct_mutex); | |
465c120c | 11707 | return ret; |
4c34574f | 11708 | } |
465c120c MR |
11709 | } |
11710 | ||
a071fa00 DV |
11711 | i915_gem_track_fb(old_obj, obj, |
11712 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe)); | |
11713 | ||
465c120c | 11714 | if (intel_crtc->primary_enabled) |
fdd508a6 | 11715 | intel_disable_primary_hw_plane(plane, crtc); |
465c120c MR |
11716 | |
11717 | ||
11718 | if (plane->fb != fb) | |
11719 | if (plane->fb) | |
a071fa00 | 11720 | intel_unpin_fb_obj(old_obj); |
465c120c | 11721 | |
4c34574f MR |
11722 | mutex_unlock(&dev->struct_mutex); |
11723 | ||
ce54d85a | 11724 | } else { |
48404c1e SJ |
11725 | if (intel_crtc && intel_crtc->active && |
11726 | intel_crtc->primary_enabled) { | |
11727 | /* | |
11728 | * FBC does not work on some platforms for rotated | |
11729 | * planes, so disable it when rotation is not 0 and | |
11730 | * update it when rotation is set back to 0. | |
11731 | * | |
11732 | * FIXME: This is redundant with the fbc update done in | |
11733 | * the primary plane enable function except that that | |
11734 | * one is done too late. We eventually need to unify | |
11735 | * this. | |
11736 | */ | |
11737 | if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && | |
11738 | dev_priv->fbc.plane == intel_crtc->plane && | |
11739 | intel_plane->rotation != BIT(DRM_ROTATE_0)) { | |
11740 | intel_disable_fbc(dev); | |
11741 | } | |
11742 | } | |
ce54d85a SJ |
11743 | ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb); |
11744 | if (ret) | |
11745 | return ret; | |
465c120c | 11746 | |
ce54d85a SJ |
11747 | if (!intel_crtc->primary_enabled) |
11748 | intel_enable_primary_hw_plane(plane, crtc); | |
11749 | } | |
465c120c | 11750 | |
ce54d85a SJ |
11751 | intel_plane->crtc_x = orig.crtc_x; |
11752 | intel_plane->crtc_y = orig.crtc_y; | |
11753 | intel_plane->crtc_w = orig.crtc_w; | |
11754 | intel_plane->crtc_h = orig.crtc_h; | |
11755 | intel_plane->src_x = orig.src_x; | |
11756 | intel_plane->src_y = orig.src_y; | |
11757 | intel_plane->src_w = orig.src_w; | |
11758 | intel_plane->src_h = orig.src_h; | |
11759 | intel_plane->obj = obj; | |
465c120c MR |
11760 | |
11761 | return 0; | |
11762 | } | |
11763 | ||
3d7d6510 MR |
11764 | /* Common destruction function for both primary and cursor planes */ |
11765 | static void intel_plane_destroy(struct drm_plane *plane) | |
465c120c MR |
11766 | { |
11767 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
11768 | drm_plane_cleanup(plane); | |
11769 | kfree(intel_plane); | |
11770 | } | |
11771 | ||
11772 | static const struct drm_plane_funcs intel_primary_plane_funcs = { | |
11773 | .update_plane = intel_primary_plane_setplane, | |
11774 | .disable_plane = intel_primary_plane_disable, | |
3d7d6510 | 11775 | .destroy = intel_plane_destroy, |
48404c1e | 11776 | .set_property = intel_plane_set_property |
465c120c MR |
11777 | }; |
11778 | ||
11779 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
11780 | int pipe) | |
11781 | { | |
11782 | struct intel_plane *primary; | |
11783 | const uint32_t *intel_primary_formats; | |
11784 | int num_formats; | |
11785 | ||
11786 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
11787 | if (primary == NULL) | |
11788 | return NULL; | |
11789 | ||
11790 | primary->can_scale = false; | |
11791 | primary->max_downscale = 1; | |
11792 | primary->pipe = pipe; | |
11793 | primary->plane = pipe; | |
48404c1e | 11794 | primary->rotation = BIT(DRM_ROTATE_0); |
465c120c MR |
11795 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
11796 | primary->plane = !pipe; | |
11797 | ||
11798 | if (INTEL_INFO(dev)->gen <= 3) { | |
11799 | intel_primary_formats = intel_primary_formats_gen2; | |
11800 | num_formats = ARRAY_SIZE(intel_primary_formats_gen2); | |
11801 | } else { | |
11802 | intel_primary_formats = intel_primary_formats_gen4; | |
11803 | num_formats = ARRAY_SIZE(intel_primary_formats_gen4); | |
11804 | } | |
11805 | ||
11806 | drm_universal_plane_init(dev, &primary->base, 0, | |
11807 | &intel_primary_plane_funcs, | |
11808 | intel_primary_formats, num_formats, | |
11809 | DRM_PLANE_TYPE_PRIMARY); | |
48404c1e SJ |
11810 | |
11811 | if (INTEL_INFO(dev)->gen >= 4) { | |
11812 | if (!dev->mode_config.rotation_property) | |
11813 | dev->mode_config.rotation_property = | |
11814 | drm_mode_create_rotation_property(dev, | |
11815 | BIT(DRM_ROTATE_0) | | |
11816 | BIT(DRM_ROTATE_180)); | |
11817 | if (dev->mode_config.rotation_property) | |
11818 | drm_object_attach_property(&primary->base.base, | |
11819 | dev->mode_config.rotation_property, | |
11820 | primary->rotation); | |
11821 | } | |
11822 | ||
465c120c MR |
11823 | return &primary->base; |
11824 | } | |
11825 | ||
3d7d6510 MR |
11826 | static int |
11827 | intel_cursor_plane_disable(struct drm_plane *plane) | |
11828 | { | |
11829 | if (!plane->fb) | |
11830 | return 0; | |
11831 | ||
11832 | BUG_ON(!plane->crtc); | |
11833 | ||
11834 | return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0); | |
11835 | } | |
11836 | ||
11837 | static int | |
11838 | intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, | |
11839 | struct drm_framebuffer *fb, int crtc_x, int crtc_y, | |
11840 | unsigned int crtc_w, unsigned int crtc_h, | |
11841 | uint32_t src_x, uint32_t src_y, | |
11842 | uint32_t src_w, uint32_t src_h) | |
11843 | { | |
11844 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11845 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
11846 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
11847 | struct drm_rect dest = { | |
11848 | /* integer pixels */ | |
11849 | .x1 = crtc_x, | |
11850 | .y1 = crtc_y, | |
11851 | .x2 = crtc_x + crtc_w, | |
11852 | .y2 = crtc_y + crtc_h, | |
11853 | }; | |
11854 | struct drm_rect src = { | |
11855 | /* 16.16 fixed point */ | |
11856 | .x1 = src_x, | |
11857 | .y1 = src_y, | |
11858 | .x2 = src_x + src_w, | |
11859 | .y2 = src_y + src_h, | |
11860 | }; | |
11861 | const struct drm_rect clip = { | |
11862 | /* integer pixels */ | |
1add143c VS |
11863 | .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0, |
11864 | .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0, | |
3d7d6510 MR |
11865 | }; |
11866 | bool visible; | |
11867 | int ret; | |
11868 | ||
11869 | ret = drm_plane_helper_check_update(plane, crtc, fb, | |
11870 | &src, &dest, &clip, | |
11871 | DRM_PLANE_HELPER_NO_SCALING, | |
11872 | DRM_PLANE_HELPER_NO_SCALING, | |
11873 | true, true, &visible); | |
11874 | if (ret) | |
11875 | return ret; | |
11876 | ||
11877 | crtc->cursor_x = crtc_x; | |
11878 | crtc->cursor_y = crtc_y; | |
11879 | if (fb != crtc->cursor->fb) { | |
11880 | return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h); | |
11881 | } else { | |
11882 | intel_crtc_update_cursor(crtc, visible); | |
4ed91096 DV |
11883 | |
11884 | intel_frontbuffer_flip(crtc->dev, | |
11885 | INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe)); | |
11886 | ||
3d7d6510 MR |
11887 | return 0; |
11888 | } | |
11889 | } | |
11890 | static const struct drm_plane_funcs intel_cursor_plane_funcs = { | |
11891 | .update_plane = intel_cursor_plane_update, | |
11892 | .disable_plane = intel_cursor_plane_disable, | |
11893 | .destroy = intel_plane_destroy, | |
11894 | }; | |
11895 | ||
11896 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, | |
11897 | int pipe) | |
11898 | { | |
11899 | struct intel_plane *cursor; | |
11900 | ||
11901 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
11902 | if (cursor == NULL) | |
11903 | return NULL; | |
11904 | ||
11905 | cursor->can_scale = false; | |
11906 | cursor->max_downscale = 1; | |
11907 | cursor->pipe = pipe; | |
11908 | cursor->plane = pipe; | |
11909 | ||
11910 | drm_universal_plane_init(dev, &cursor->base, 0, | |
11911 | &intel_cursor_plane_funcs, | |
11912 | intel_cursor_formats, | |
11913 | ARRAY_SIZE(intel_cursor_formats), | |
11914 | DRM_PLANE_TYPE_CURSOR); | |
11915 | return &cursor->base; | |
11916 | } | |
11917 | ||
b358d0a6 | 11918 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 11919 | { |
fbee40df | 11920 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 11921 | struct intel_crtc *intel_crtc; |
3d7d6510 MR |
11922 | struct drm_plane *primary = NULL; |
11923 | struct drm_plane *cursor = NULL; | |
465c120c | 11924 | int i, ret; |
79e53945 | 11925 | |
955382f3 | 11926 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
11927 | if (intel_crtc == NULL) |
11928 | return; | |
11929 | ||
465c120c | 11930 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
11931 | if (!primary) |
11932 | goto fail; | |
11933 | ||
11934 | cursor = intel_cursor_plane_create(dev, pipe); | |
11935 | if (!cursor) | |
11936 | goto fail; | |
11937 | ||
465c120c | 11938 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
3d7d6510 MR |
11939 | cursor, &intel_crtc_funcs); |
11940 | if (ret) | |
11941 | goto fail; | |
79e53945 JB |
11942 | |
11943 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
11944 | for (i = 0; i < 256; i++) { |
11945 | intel_crtc->lut_r[i] = i; | |
11946 | intel_crtc->lut_g[i] = i; | |
11947 | intel_crtc->lut_b[i] = i; | |
11948 | } | |
11949 | ||
1f1c2e24 VS |
11950 | /* |
11951 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 11952 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 11953 | */ |
80824003 JB |
11954 | intel_crtc->pipe = pipe; |
11955 | intel_crtc->plane = pipe; | |
3a77c4c4 | 11956 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 11957 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 11958 | intel_crtc->plane = !pipe; |
80824003 JB |
11959 | } |
11960 | ||
4b0e333e CW |
11961 | intel_crtc->cursor_base = ~0; |
11962 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 11963 | intel_crtc->cursor_size = ~0; |
4b0e333e | 11964 | |
22fd0fab JB |
11965 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
11966 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
11967 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
11968 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
11969 | ||
79e53945 | 11970 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 DV |
11971 | |
11972 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); | |
3d7d6510 MR |
11973 | return; |
11974 | ||
11975 | fail: | |
11976 | if (primary) | |
11977 | drm_plane_cleanup(primary); | |
11978 | if (cursor) | |
11979 | drm_plane_cleanup(cursor); | |
11980 | kfree(intel_crtc); | |
79e53945 JB |
11981 | } |
11982 | ||
752aa88a JB |
11983 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
11984 | { | |
11985 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 11986 | struct drm_device *dev = connector->base.dev; |
752aa88a | 11987 | |
51fd371b | 11988 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a JB |
11989 | |
11990 | if (!encoder) | |
11991 | return INVALID_PIPE; | |
11992 | ||
11993 | return to_intel_crtc(encoder->crtc)->pipe; | |
11994 | } | |
11995 | ||
08d7b3d1 | 11996 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 11997 | struct drm_file *file) |
08d7b3d1 | 11998 | { |
08d7b3d1 | 11999 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 12000 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 12001 | struct intel_crtc *crtc; |
08d7b3d1 | 12002 | |
1cff8f6b DV |
12003 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
12004 | return -ENODEV; | |
08d7b3d1 | 12005 | |
7707e653 | 12006 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
08d7b3d1 | 12007 | |
7707e653 | 12008 | if (!drmmode_crtc) { |
08d7b3d1 | 12009 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 12010 | return -ENOENT; |
08d7b3d1 CW |
12011 | } |
12012 | ||
7707e653 | 12013 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 12014 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 12015 | |
c05422d5 | 12016 | return 0; |
08d7b3d1 CW |
12017 | } |
12018 | ||
66a9278e | 12019 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 12020 | { |
66a9278e DV |
12021 | struct drm_device *dev = encoder->base.dev; |
12022 | struct intel_encoder *source_encoder; | |
79e53945 | 12023 | int index_mask = 0; |
79e53945 JB |
12024 | int entry = 0; |
12025 | ||
b2784e15 | 12026 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 12027 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
12028 | index_mask |= (1 << entry); |
12029 | ||
79e53945 JB |
12030 | entry++; |
12031 | } | |
4ef69c7a | 12032 | |
79e53945 JB |
12033 | return index_mask; |
12034 | } | |
12035 | ||
4d302442 CW |
12036 | static bool has_edp_a(struct drm_device *dev) |
12037 | { | |
12038 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12039 | ||
12040 | if (!IS_MOBILE(dev)) | |
12041 | return false; | |
12042 | ||
12043 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
12044 | return false; | |
12045 | ||
e3589908 | 12046 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
12047 | return false; |
12048 | ||
12049 | return true; | |
12050 | } | |
12051 | ||
ba0fbca4 DL |
12052 | const char *intel_output_name(int output) |
12053 | { | |
12054 | static const char *names[] = { | |
12055 | [INTEL_OUTPUT_UNUSED] = "Unused", | |
12056 | [INTEL_OUTPUT_ANALOG] = "Analog", | |
12057 | [INTEL_OUTPUT_DVO] = "DVO", | |
12058 | [INTEL_OUTPUT_SDVO] = "SDVO", | |
12059 | [INTEL_OUTPUT_LVDS] = "LVDS", | |
12060 | [INTEL_OUTPUT_TVOUT] = "TV", | |
12061 | [INTEL_OUTPUT_HDMI] = "HDMI", | |
12062 | [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort", | |
12063 | [INTEL_OUTPUT_EDP] = "eDP", | |
12064 | [INTEL_OUTPUT_DSI] = "DSI", | |
12065 | [INTEL_OUTPUT_UNKNOWN] = "Unknown", | |
12066 | }; | |
12067 | ||
12068 | if (output < 0 || output >= ARRAY_SIZE(names) || !names[output]) | |
12069 | return "Invalid"; | |
12070 | ||
12071 | return names[output]; | |
12072 | } | |
12073 | ||
84b4e042 JB |
12074 | static bool intel_crt_present(struct drm_device *dev) |
12075 | { | |
12076 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12077 | ||
12078 | if (IS_ULT(dev)) | |
12079 | return false; | |
12080 | ||
12081 | if (IS_CHERRYVIEW(dev)) | |
12082 | return false; | |
12083 | ||
12084 | if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support) | |
12085 | return false; | |
12086 | ||
12087 | return true; | |
12088 | } | |
12089 | ||
79e53945 JB |
12090 | static void intel_setup_outputs(struct drm_device *dev) |
12091 | { | |
725e30ad | 12092 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 12093 | struct intel_encoder *encoder; |
cb0953d7 | 12094 | bool dpd_is_edp = false; |
79e53945 | 12095 | |
c9093354 | 12096 | intel_lvds_init(dev); |
79e53945 | 12097 | |
84b4e042 | 12098 | if (intel_crt_present(dev)) |
79935fca | 12099 | intel_crt_init(dev); |
cb0953d7 | 12100 | |
affa9354 | 12101 | if (HAS_DDI(dev)) { |
0e72a5b5 ED |
12102 | int found; |
12103 | ||
12104 | /* Haswell uses DDI functions to detect digital outputs */ | |
12105 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; | |
12106 | /* DDI A only supports eDP */ | |
12107 | if (found) | |
12108 | intel_ddi_init(dev, PORT_A); | |
12109 | ||
12110 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
12111 | * register */ | |
12112 | found = I915_READ(SFUSE_STRAP); | |
12113 | ||
12114 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
12115 | intel_ddi_init(dev, PORT_B); | |
12116 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
12117 | intel_ddi_init(dev, PORT_C); | |
12118 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
12119 | intel_ddi_init(dev, PORT_D); | |
12120 | } else if (HAS_PCH_SPLIT(dev)) { | |
cb0953d7 | 12121 | int found; |
5d8a7752 | 12122 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
12123 | |
12124 | if (has_edp_a(dev)) | |
12125 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 12126 | |
dc0fa718 | 12127 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 12128 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 12129 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 12130 | if (!found) |
e2debe91 | 12131 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 12132 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 12133 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
12134 | } |
12135 | ||
dc0fa718 | 12136 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 12137 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 12138 | |
dc0fa718 | 12139 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 12140 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 12141 | |
5eb08b69 | 12142 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 12143 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 12144 | |
270b3042 | 12145 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 12146 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d | 12147 | } else if (IS_VALLEYVIEW(dev)) { |
585a94b8 AB |
12148 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) { |
12149 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, | |
12150 | PORT_B); | |
12151 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED) | |
12152 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); | |
12153 | } | |
12154 | ||
6f6005a5 JB |
12155 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) { |
12156 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, | |
12157 | PORT_C); | |
12158 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) | |
5d8a7752 | 12159 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); |
6f6005a5 | 12160 | } |
19c03924 | 12161 | |
9418c1f1 VS |
12162 | if (IS_CHERRYVIEW(dev)) { |
12163 | if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) { | |
12164 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID, | |
12165 | PORT_D); | |
12166 | if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED) | |
12167 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D); | |
12168 | } | |
12169 | } | |
12170 | ||
3cfca973 | 12171 | intel_dsi_init(dev); |
103a196f | 12172 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 12173 | bool found = false; |
7d57382e | 12174 | |
e2debe91 | 12175 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 12176 | DRM_DEBUG_KMS("probing SDVOB\n"); |
e2debe91 | 12177 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
b01f2c3a JB |
12178 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
12179 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
e2debe91 | 12180 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 12181 | } |
27185ae1 | 12182 | |
e7281eab | 12183 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 12184 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 12185 | } |
13520b05 KH |
12186 | |
12187 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 12188 | |
e2debe91 | 12189 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 12190 | DRM_DEBUG_KMS("probing SDVOC\n"); |
e2debe91 | 12191 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
b01f2c3a | 12192 | } |
27185ae1 | 12193 | |
e2debe91 | 12194 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 12195 | |
b01f2c3a JB |
12196 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
12197 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
e2debe91 | 12198 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 12199 | } |
e7281eab | 12200 | if (SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 12201 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 12202 | } |
27185ae1 | 12203 | |
b01f2c3a | 12204 | if (SUPPORTS_INTEGRATED_DP(dev) && |
e7281eab | 12205 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 12206 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 12207 | } else if (IS_GEN2(dev)) |
79e53945 JB |
12208 | intel_dvo_init(dev); |
12209 | ||
103a196f | 12210 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
12211 | intel_tv_init(dev); |
12212 | ||
7c8f8a70 RV |
12213 | intel_edp_psr_init(dev); |
12214 | ||
b2784e15 | 12215 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
12216 | encoder->base.possible_crtcs = encoder->crtc_mask; |
12217 | encoder->base.possible_clones = | |
66a9278e | 12218 | intel_encoder_clones(encoder); |
79e53945 | 12219 | } |
47356eb6 | 12220 | |
dde86e2d | 12221 | intel_init_pch_refclk(dev); |
270b3042 DV |
12222 | |
12223 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
12224 | } |
12225 | ||
12226 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
12227 | { | |
60a5ca01 | 12228 | struct drm_device *dev = fb->dev; |
79e53945 | 12229 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 12230 | |
ef2d633e | 12231 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 12232 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 12233 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
12234 | drm_gem_object_unreference(&intel_fb->obj->base); |
12235 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
12236 | kfree(intel_fb); |
12237 | } | |
12238 | ||
12239 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 12240 | struct drm_file *file, |
79e53945 JB |
12241 | unsigned int *handle) |
12242 | { | |
12243 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 12244 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 12245 | |
05394f39 | 12246 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
12247 | } |
12248 | ||
12249 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
12250 | .destroy = intel_user_framebuffer_destroy, | |
12251 | .create_handle = intel_user_framebuffer_create_handle, | |
12252 | }; | |
12253 | ||
b5ea642a DV |
12254 | static int intel_framebuffer_init(struct drm_device *dev, |
12255 | struct intel_framebuffer *intel_fb, | |
12256 | struct drm_mode_fb_cmd2 *mode_cmd, | |
12257 | struct drm_i915_gem_object *obj) | |
79e53945 | 12258 | { |
a57ce0b2 | 12259 | int aligned_height; |
a35cdaa0 | 12260 | int pitch_limit; |
79e53945 JB |
12261 | int ret; |
12262 | ||
dd4916c5 DV |
12263 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
12264 | ||
c16ed4be CW |
12265 | if (obj->tiling_mode == I915_TILING_Y) { |
12266 | DRM_DEBUG("hardware does not support tiling Y\n"); | |
57cd6508 | 12267 | return -EINVAL; |
c16ed4be | 12268 | } |
57cd6508 | 12269 | |
c16ed4be CW |
12270 | if (mode_cmd->pitches[0] & 63) { |
12271 | DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n", | |
12272 | mode_cmd->pitches[0]); | |
57cd6508 | 12273 | return -EINVAL; |
c16ed4be | 12274 | } |
57cd6508 | 12275 | |
a35cdaa0 CW |
12276 | if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) { |
12277 | pitch_limit = 32*1024; | |
12278 | } else if (INTEL_INFO(dev)->gen >= 4) { | |
12279 | if (obj->tiling_mode) | |
12280 | pitch_limit = 16*1024; | |
12281 | else | |
12282 | pitch_limit = 32*1024; | |
12283 | } else if (INTEL_INFO(dev)->gen >= 3) { | |
12284 | if (obj->tiling_mode) | |
12285 | pitch_limit = 8*1024; | |
12286 | else | |
12287 | pitch_limit = 16*1024; | |
12288 | } else | |
12289 | /* XXX DSPC is limited to 4k tiled */ | |
12290 | pitch_limit = 8*1024; | |
12291 | ||
12292 | if (mode_cmd->pitches[0] > pitch_limit) { | |
12293 | DRM_DEBUG("%s pitch (%d) must be at less than %d\n", | |
12294 | obj->tiling_mode ? "tiled" : "linear", | |
12295 | mode_cmd->pitches[0], pitch_limit); | |
5d7bd705 | 12296 | return -EINVAL; |
c16ed4be | 12297 | } |
5d7bd705 VS |
12298 | |
12299 | if (obj->tiling_mode != I915_TILING_NONE && | |
c16ed4be CW |
12300 | mode_cmd->pitches[0] != obj->stride) { |
12301 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
12302 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 12303 | return -EINVAL; |
c16ed4be | 12304 | } |
5d7bd705 | 12305 | |
57779d06 | 12306 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 12307 | switch (mode_cmd->pixel_format) { |
57779d06 | 12308 | case DRM_FORMAT_C8: |
04b3924d VS |
12309 | case DRM_FORMAT_RGB565: |
12310 | case DRM_FORMAT_XRGB8888: | |
12311 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
12312 | break; |
12313 | case DRM_FORMAT_XRGB1555: | |
12314 | case DRM_FORMAT_ARGB1555: | |
c16ed4be | 12315 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
12316 | DRM_DEBUG("unsupported pixel format: %s\n", |
12317 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 12318 | return -EINVAL; |
c16ed4be | 12319 | } |
57779d06 VS |
12320 | break; |
12321 | case DRM_FORMAT_XBGR8888: | |
12322 | case DRM_FORMAT_ABGR8888: | |
04b3924d VS |
12323 | case DRM_FORMAT_XRGB2101010: |
12324 | case DRM_FORMAT_ARGB2101010: | |
57779d06 VS |
12325 | case DRM_FORMAT_XBGR2101010: |
12326 | case DRM_FORMAT_ABGR2101010: | |
c16ed4be | 12327 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
12328 | DRM_DEBUG("unsupported pixel format: %s\n", |
12329 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 12330 | return -EINVAL; |
c16ed4be | 12331 | } |
b5626747 | 12332 | break; |
04b3924d VS |
12333 | case DRM_FORMAT_YUYV: |
12334 | case DRM_FORMAT_UYVY: | |
12335 | case DRM_FORMAT_YVYU: | |
12336 | case DRM_FORMAT_VYUY: | |
c16ed4be | 12337 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
12338 | DRM_DEBUG("unsupported pixel format: %s\n", |
12339 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 12340 | return -EINVAL; |
c16ed4be | 12341 | } |
57cd6508 CW |
12342 | break; |
12343 | default: | |
4ee62c76 VS |
12344 | DRM_DEBUG("unsupported pixel format: %s\n", |
12345 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
12346 | return -EINVAL; |
12347 | } | |
12348 | ||
90f9a336 VS |
12349 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
12350 | if (mode_cmd->offsets[0] != 0) | |
12351 | return -EINVAL; | |
12352 | ||
a57ce0b2 JB |
12353 | aligned_height = intel_align_height(dev, mode_cmd->height, |
12354 | obj->tiling_mode); | |
53155c0a DV |
12355 | /* FIXME drm helper for size checks (especially planar formats)? */ |
12356 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
12357 | return -EINVAL; | |
12358 | ||
c7d73f6a DV |
12359 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
12360 | intel_fb->obj = obj; | |
80075d49 | 12361 | intel_fb->obj->framebuffer_references++; |
c7d73f6a | 12362 | |
79e53945 JB |
12363 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
12364 | if (ret) { | |
12365 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
12366 | return ret; | |
12367 | } | |
12368 | ||
79e53945 JB |
12369 | return 0; |
12370 | } | |
12371 | ||
79e53945 JB |
12372 | static struct drm_framebuffer * |
12373 | intel_user_framebuffer_create(struct drm_device *dev, | |
12374 | struct drm_file *filp, | |
308e5bcb | 12375 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 12376 | { |
05394f39 | 12377 | struct drm_i915_gem_object *obj; |
79e53945 | 12378 | |
308e5bcb JB |
12379 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
12380 | mode_cmd->handles[0])); | |
c8725226 | 12381 | if (&obj->base == NULL) |
cce13ff7 | 12382 | return ERR_PTR(-ENOENT); |
79e53945 | 12383 | |
d2dff872 | 12384 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
12385 | } |
12386 | ||
4520f53a | 12387 | #ifndef CONFIG_DRM_I915_FBDEV |
0632fef6 | 12388 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
12389 | { |
12390 | } | |
12391 | #endif | |
12392 | ||
79e53945 | 12393 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 12394 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 12395 | .output_poll_changed = intel_fbdev_output_poll_changed, |
79e53945 JB |
12396 | }; |
12397 | ||
e70236a8 JB |
12398 | /* Set up chip specific display functions */ |
12399 | static void intel_init_display(struct drm_device *dev) | |
12400 | { | |
12401 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12402 | ||
ee9300bb DV |
12403 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
12404 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
ef9348c8 CML |
12405 | else if (IS_CHERRYVIEW(dev)) |
12406 | dev_priv->display.find_dpll = chv_find_best_dpll; | |
ee9300bb DV |
12407 | else if (IS_VALLEYVIEW(dev)) |
12408 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
12409 | else if (IS_PINEVIEW(dev)) | |
12410 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
12411 | else | |
12412 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
12413 | ||
affa9354 | 12414 | if (HAS_DDI(dev)) { |
0e8ffe1b | 12415 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
4c6baa59 | 12416 | dev_priv->display.get_plane_config = ironlake_get_plane_config; |
09b4ddf9 | 12417 | dev_priv->display.crtc_mode_set = haswell_crtc_mode_set; |
4f771f10 PZ |
12418 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
12419 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
df8ad70c | 12420 | dev_priv->display.off = ironlake_crtc_off; |
262ca2b0 MR |
12421 | dev_priv->display.update_primary_plane = |
12422 | ironlake_update_primary_plane; | |
09b4ddf9 | 12423 | } else if (HAS_PCH_SPLIT(dev)) { |
0e8ffe1b | 12424 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
4c6baa59 | 12425 | dev_priv->display.get_plane_config = ironlake_get_plane_config; |
f564048e | 12426 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
76e5a89c DV |
12427 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
12428 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
ee7b9f93 | 12429 | dev_priv->display.off = ironlake_crtc_off; |
262ca2b0 MR |
12430 | dev_priv->display.update_primary_plane = |
12431 | ironlake_update_primary_plane; | |
89b667f8 JB |
12432 | } else if (IS_VALLEYVIEW(dev)) { |
12433 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
1ad292b5 | 12434 | dev_priv->display.get_plane_config = i9xx_get_plane_config; |
89b667f8 JB |
12435 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
12436 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
12437 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
12438 | dev_priv->display.off = i9xx_crtc_off; | |
262ca2b0 MR |
12439 | dev_priv->display.update_primary_plane = |
12440 | i9xx_update_primary_plane; | |
f564048e | 12441 | } else { |
0e8ffe1b | 12442 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
1ad292b5 | 12443 | dev_priv->display.get_plane_config = i9xx_get_plane_config; |
f564048e | 12444 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
76e5a89c DV |
12445 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
12446 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
ee7b9f93 | 12447 | dev_priv->display.off = i9xx_crtc_off; |
262ca2b0 MR |
12448 | dev_priv->display.update_primary_plane = |
12449 | i9xx_update_primary_plane; | |
f564048e | 12450 | } |
e70236a8 | 12451 | |
e70236a8 | 12452 | /* Returns the core display clock speed */ |
25eb05fc JB |
12453 | if (IS_VALLEYVIEW(dev)) |
12454 | dev_priv->display.get_display_clock_speed = | |
12455 | valleyview_get_display_clock_speed; | |
12456 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) | |
e70236a8 JB |
12457 | dev_priv->display.get_display_clock_speed = |
12458 | i945_get_display_clock_speed; | |
12459 | else if (IS_I915G(dev)) | |
12460 | dev_priv->display.get_display_clock_speed = | |
12461 | i915_get_display_clock_speed; | |
257a7ffc | 12462 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
12463 | dev_priv->display.get_display_clock_speed = |
12464 | i9xx_misc_get_display_clock_speed; | |
257a7ffc DV |
12465 | else if (IS_PINEVIEW(dev)) |
12466 | dev_priv->display.get_display_clock_speed = | |
12467 | pnv_get_display_clock_speed; | |
e70236a8 JB |
12468 | else if (IS_I915GM(dev)) |
12469 | dev_priv->display.get_display_clock_speed = | |
12470 | i915gm_get_display_clock_speed; | |
12471 | else if (IS_I865G(dev)) | |
12472 | dev_priv->display.get_display_clock_speed = | |
12473 | i865_get_display_clock_speed; | |
f0f8a9ce | 12474 | else if (IS_I85X(dev)) |
e70236a8 JB |
12475 | dev_priv->display.get_display_clock_speed = |
12476 | i855_get_display_clock_speed; | |
12477 | else /* 852, 830 */ | |
12478 | dev_priv->display.get_display_clock_speed = | |
12479 | i830_get_display_clock_speed; | |
12480 | ||
3bb11b53 | 12481 | if (IS_G4X(dev)) { |
e0dac65e | 12482 | dev_priv->display.write_eld = g4x_write_eld; |
3bb11b53 SJ |
12483 | } else if (IS_GEN5(dev)) { |
12484 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; | |
12485 | dev_priv->display.write_eld = ironlake_write_eld; | |
12486 | } else if (IS_GEN6(dev)) { | |
12487 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; | |
12488 | dev_priv->display.write_eld = ironlake_write_eld; | |
12489 | dev_priv->display.modeset_global_resources = | |
12490 | snb_modeset_global_resources; | |
12491 | } else if (IS_IVYBRIDGE(dev)) { | |
12492 | /* FIXME: detect B0+ stepping and use auto training */ | |
12493 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
12494 | dev_priv->display.write_eld = ironlake_write_eld; | |
12495 | dev_priv->display.modeset_global_resources = | |
12496 | ivb_modeset_global_resources; | |
12497 | } else if (IS_HASWELL(dev) || IS_GEN8(dev)) { | |
12498 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; | |
12499 | dev_priv->display.write_eld = haswell_write_eld; | |
12500 | dev_priv->display.modeset_global_resources = | |
12501 | haswell_modeset_global_resources; | |
30a970c6 JB |
12502 | } else if (IS_VALLEYVIEW(dev)) { |
12503 | dev_priv->display.modeset_global_resources = | |
12504 | valleyview_modeset_global_resources; | |
9ca2fe73 | 12505 | dev_priv->display.write_eld = ironlake_write_eld; |
e70236a8 | 12506 | } |
8c9f3aaf JB |
12507 | |
12508 | /* Default just returns -ENODEV to indicate unsupported */ | |
12509 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
12510 | ||
12511 | switch (INTEL_INFO(dev)->gen) { | |
12512 | case 2: | |
12513 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
12514 | break; | |
12515 | ||
12516 | case 3: | |
12517 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
12518 | break; | |
12519 | ||
12520 | case 4: | |
12521 | case 5: | |
12522 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
12523 | break; | |
12524 | ||
12525 | case 6: | |
12526 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
12527 | break; | |
7c9017e5 | 12528 | case 7: |
4e0bbc31 | 12529 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
12530 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
12531 | break; | |
8c9f3aaf | 12532 | } |
7bd688cd JN |
12533 | |
12534 | intel_panel_init_backlight_funcs(dev); | |
e70236a8 JB |
12535 | } |
12536 | ||
b690e96c JB |
12537 | /* |
12538 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
12539 | * resume, or other times. This quirk makes sure that's the case for | |
12540 | * affected systems. | |
12541 | */ | |
0206e353 | 12542 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
12543 | { |
12544 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12545 | ||
12546 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 12547 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
12548 | } |
12549 | ||
435793df KP |
12550 | /* |
12551 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
12552 | */ | |
12553 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
12554 | { | |
12555 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12556 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 12557 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
12558 | } |
12559 | ||
4dca20ef | 12560 | /* |
5a15ab5b CE |
12561 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
12562 | * brightness value | |
4dca20ef CE |
12563 | */ |
12564 | static void quirk_invert_brightness(struct drm_device *dev) | |
12565 | { | |
12566 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12567 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 12568 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
12569 | } |
12570 | ||
9c72cc6f SD |
12571 | /* Some VBT's incorrectly indicate no backlight is present */ |
12572 | static void quirk_backlight_present(struct drm_device *dev) | |
12573 | { | |
12574 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12575 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; | |
12576 | DRM_INFO("applying backlight present quirk\n"); | |
12577 | } | |
12578 | ||
b690e96c JB |
12579 | struct intel_quirk { |
12580 | int device; | |
12581 | int subsystem_vendor; | |
12582 | int subsystem_device; | |
12583 | void (*hook)(struct drm_device *dev); | |
12584 | }; | |
12585 | ||
5f85f176 EE |
12586 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
12587 | struct intel_dmi_quirk { | |
12588 | void (*hook)(struct drm_device *dev); | |
12589 | const struct dmi_system_id (*dmi_id_list)[]; | |
12590 | }; | |
12591 | ||
12592 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
12593 | { | |
12594 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
12595 | return 1; | |
12596 | } | |
12597 | ||
12598 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
12599 | { | |
12600 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
12601 | { | |
12602 | .callback = intel_dmi_reverse_brightness, | |
12603 | .ident = "NCR Corporation", | |
12604 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
12605 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
12606 | }, | |
12607 | }, | |
12608 | { } /* terminating entry */ | |
12609 | }, | |
12610 | .hook = quirk_invert_brightness, | |
12611 | }, | |
12612 | }; | |
12613 | ||
c43b5634 | 12614 | static struct intel_quirk intel_quirks[] = { |
b690e96c | 12615 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
0206e353 | 12616 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c | 12617 | |
b690e96c JB |
12618 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
12619 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
12620 | ||
b690e96c JB |
12621 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
12622 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
12623 | ||
435793df KP |
12624 | /* Lenovo U160 cannot use SSC on LVDS */ |
12625 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
12626 | |
12627 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
12628 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 12629 | |
be505f64 AH |
12630 | /* Acer Aspire 5734Z must invert backlight brightness */ |
12631 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
12632 | ||
12633 | /* Acer/eMachines G725 */ | |
12634 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
12635 | ||
12636 | /* Acer/eMachines e725 */ | |
12637 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
12638 | ||
12639 | /* Acer/Packard Bell NCL20 */ | |
12640 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
12641 | ||
12642 | /* Acer Aspire 4736Z */ | |
12643 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
12644 | |
12645 | /* Acer Aspire 5336 */ | |
12646 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
12647 | |
12648 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
12649 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c SD |
12650 | |
12651 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ | |
12652 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
12653 | |
12654 | /* HP Chromebook 14 (Celeron 2955U) */ | |
12655 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
b690e96c JB |
12656 | }; |
12657 | ||
12658 | static void intel_init_quirks(struct drm_device *dev) | |
12659 | { | |
12660 | struct pci_dev *d = dev->pdev; | |
12661 | int i; | |
12662 | ||
12663 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
12664 | struct intel_quirk *q = &intel_quirks[i]; | |
12665 | ||
12666 | if (d->device == q->device && | |
12667 | (d->subsystem_vendor == q->subsystem_vendor || | |
12668 | q->subsystem_vendor == PCI_ANY_ID) && | |
12669 | (d->subsystem_device == q->subsystem_device || | |
12670 | q->subsystem_device == PCI_ANY_ID)) | |
12671 | q->hook(dev); | |
12672 | } | |
5f85f176 EE |
12673 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
12674 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
12675 | intel_dmi_quirks[i].hook(dev); | |
12676 | } | |
b690e96c JB |
12677 | } |
12678 | ||
9cce37f4 JB |
12679 | /* Disable the VGA plane that we never use */ |
12680 | static void i915_disable_vga(struct drm_device *dev) | |
12681 | { | |
12682 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12683 | u8 sr1; | |
766aa1c4 | 12684 | u32 vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 12685 | |
2b37c616 | 12686 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 12687 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 12688 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
12689 | sr1 = inb(VGA_SR_DATA); |
12690 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
12691 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
12692 | udelay(300); | |
12693 | ||
12694 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); | |
12695 | POSTING_READ(vga_reg); | |
12696 | } | |
12697 | ||
f817586c DV |
12698 | void intel_modeset_init_hw(struct drm_device *dev) |
12699 | { | |
a8f78b58 ED |
12700 | intel_prepare_ddi(dev); |
12701 | ||
f8bf63fd VS |
12702 | if (IS_VALLEYVIEW(dev)) |
12703 | vlv_update_cdclk(dev); | |
12704 | ||
f817586c DV |
12705 | intel_init_clock_gating(dev); |
12706 | ||
8090c6b9 | 12707 | intel_enable_gt_powersave(dev); |
f817586c DV |
12708 | } |
12709 | ||
7d708ee4 ID |
12710 | void intel_modeset_suspend_hw(struct drm_device *dev) |
12711 | { | |
12712 | intel_suspend_hw(dev); | |
12713 | } | |
12714 | ||
79e53945 JB |
12715 | void intel_modeset_init(struct drm_device *dev) |
12716 | { | |
652c393a | 12717 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 12718 | int sprite, ret; |
8cc87b75 | 12719 | enum pipe pipe; |
46f297fb | 12720 | struct intel_crtc *crtc; |
79e53945 JB |
12721 | |
12722 | drm_mode_config_init(dev); | |
12723 | ||
12724 | dev->mode_config.min_width = 0; | |
12725 | dev->mode_config.min_height = 0; | |
12726 | ||
019d96cb DA |
12727 | dev->mode_config.preferred_depth = 24; |
12728 | dev->mode_config.prefer_shadow = 1; | |
12729 | ||
e6ecefaa | 12730 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 12731 | |
b690e96c JB |
12732 | intel_init_quirks(dev); |
12733 | ||
1fa61106 ED |
12734 | intel_init_pm(dev); |
12735 | ||
e3c74757 BW |
12736 | if (INTEL_INFO(dev)->num_pipes == 0) |
12737 | return; | |
12738 | ||
e70236a8 JB |
12739 | intel_init_display(dev); |
12740 | ||
a6c45cf0 CW |
12741 | if (IS_GEN2(dev)) { |
12742 | dev->mode_config.max_width = 2048; | |
12743 | dev->mode_config.max_height = 2048; | |
12744 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
12745 | dev->mode_config.max_width = 4096; |
12746 | dev->mode_config.max_height = 4096; | |
79e53945 | 12747 | } else { |
a6c45cf0 CW |
12748 | dev->mode_config.max_width = 8192; |
12749 | dev->mode_config.max_height = 8192; | |
79e53945 | 12750 | } |
068be561 | 12751 | |
dc41c154 VS |
12752 | if (IS_845G(dev) || IS_I865G(dev)) { |
12753 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
12754 | dev->mode_config.cursor_height = 1023; | |
12755 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
12756 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
12757 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
12758 | } else { | |
12759 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
12760 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
12761 | } | |
12762 | ||
5d4545ae | 12763 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 12764 | |
28c97730 | 12765 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
12766 | INTEL_INFO(dev)->num_pipes, |
12767 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 12768 | |
055e393f | 12769 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 12770 | intel_crtc_init(dev, pipe); |
1fe47785 DL |
12771 | for_each_sprite(pipe, sprite) { |
12772 | ret = intel_plane_init(dev, pipe, sprite); | |
7f1f3851 | 12773 | if (ret) |
06da8da2 | 12774 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 12775 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 12776 | } |
79e53945 JB |
12777 | } |
12778 | ||
f42bb70d JB |
12779 | intel_init_dpio(dev); |
12780 | ||
e72f9fbf | 12781 | intel_shared_dpll_init(dev); |
ee7b9f93 | 12782 | |
9cce37f4 JB |
12783 | /* Just disable it once at startup */ |
12784 | i915_disable_vga(dev); | |
79e53945 | 12785 | intel_setup_outputs(dev); |
11be49eb CW |
12786 | |
12787 | /* Just in case the BIOS is doing something questionable. */ | |
12788 | intel_disable_fbc(dev); | |
fa9fa083 | 12789 | |
6e9f798d | 12790 | drm_modeset_lock_all(dev); |
fa9fa083 | 12791 | intel_modeset_setup_hw_state(dev, false); |
6e9f798d | 12792 | drm_modeset_unlock_all(dev); |
46f297fb | 12793 | |
d3fcc808 | 12794 | for_each_intel_crtc(dev, crtc) { |
46f297fb JB |
12795 | if (!crtc->active) |
12796 | continue; | |
12797 | ||
46f297fb | 12798 | /* |
46f297fb JB |
12799 | * Note that reserving the BIOS fb up front prevents us |
12800 | * from stuffing other stolen allocations like the ring | |
12801 | * on top. This prevents some ugliness at boot time, and | |
12802 | * can even allow for smooth boot transitions if the BIOS | |
12803 | * fb is large enough for the active pipe configuration. | |
12804 | */ | |
12805 | if (dev_priv->display.get_plane_config) { | |
12806 | dev_priv->display.get_plane_config(crtc, | |
12807 | &crtc->plane_config); | |
12808 | /* | |
12809 | * If the fb is shared between multiple heads, we'll | |
12810 | * just get the first one. | |
12811 | */ | |
484b41dd | 12812 | intel_find_plane_obj(crtc, &crtc->plane_config); |
46f297fb | 12813 | } |
46f297fb | 12814 | } |
2c7111db CW |
12815 | } |
12816 | ||
7fad798e DV |
12817 | static void intel_enable_pipe_a(struct drm_device *dev) |
12818 | { | |
12819 | struct intel_connector *connector; | |
12820 | struct drm_connector *crt = NULL; | |
12821 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 12822 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
12823 | |
12824 | /* We can't just switch on the pipe A, we need to set things up with a | |
12825 | * proper mode and output configuration. As a gross hack, enable pipe A | |
12826 | * by enabling the load detect pipe once. */ | |
12827 | list_for_each_entry(connector, | |
12828 | &dev->mode_config.connector_list, | |
12829 | base.head) { | |
12830 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { | |
12831 | crt = &connector->base; | |
12832 | break; | |
12833 | } | |
12834 | } | |
12835 | ||
12836 | if (!crt) | |
12837 | return; | |
12838 | ||
208bf9fd VS |
12839 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
12840 | intel_release_load_detect_pipe(crt, &load_detect_temp); | |
7fad798e DV |
12841 | } |
12842 | ||
fa555837 DV |
12843 | static bool |
12844 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
12845 | { | |
7eb552ae BW |
12846 | struct drm_device *dev = crtc->base.dev; |
12847 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 DV |
12848 | u32 reg, val; |
12849 | ||
7eb552ae | 12850 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
12851 | return true; |
12852 | ||
12853 | reg = DSPCNTR(!crtc->plane); | |
12854 | val = I915_READ(reg); | |
12855 | ||
12856 | if ((val & DISPLAY_PLANE_ENABLE) && | |
12857 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
12858 | return false; | |
12859 | ||
12860 | return true; | |
12861 | } | |
12862 | ||
24929352 DV |
12863 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
12864 | { | |
12865 | struct drm_device *dev = crtc->base.dev; | |
12866 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 | 12867 | u32 reg; |
24929352 | 12868 | |
24929352 | 12869 | /* Clear any frame start delays used for debugging left by the BIOS */ |
3b117c8f | 12870 | reg = PIPECONF(crtc->config.cpu_transcoder); |
24929352 DV |
12871 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
12872 | ||
d3eaf884 VS |
12873 | /* restore vblank interrupts to correct state */ |
12874 | if (crtc->active) | |
12875 | drm_vblank_on(dev, crtc->pipe); | |
12876 | else | |
12877 | drm_vblank_off(dev, crtc->pipe); | |
12878 | ||
24929352 | 12879 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
12880 | * disable the crtc (and hence change the state) if it is wrong. Note |
12881 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
12882 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
12883 | struct intel_connector *connector; |
12884 | bool plane; | |
12885 | ||
24929352 DV |
12886 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
12887 | crtc->base.base.id); | |
12888 | ||
12889 | /* Pipe has the wrong plane attached and the plane is active. | |
12890 | * Temporarily change the plane mapping and disable everything | |
12891 | * ... */ | |
12892 | plane = crtc->plane; | |
12893 | crtc->plane = !plane; | |
9c8958bc | 12894 | crtc->primary_enabled = true; |
24929352 DV |
12895 | dev_priv->display.crtc_disable(&crtc->base); |
12896 | crtc->plane = plane; | |
12897 | ||
12898 | /* ... and break all links. */ | |
12899 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
12900 | base.head) { | |
12901 | if (connector->encoder->base.crtc != &crtc->base) | |
12902 | continue; | |
12903 | ||
7f1950fb EE |
12904 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
12905 | connector->base.encoder = NULL; | |
24929352 | 12906 | } |
7f1950fb EE |
12907 | /* multiple connectors may have the same encoder: |
12908 | * handle them and break crtc link separately */ | |
12909 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
12910 | base.head) | |
12911 | if (connector->encoder->base.crtc == &crtc->base) { | |
12912 | connector->encoder->base.crtc = NULL; | |
12913 | connector->encoder->connectors_active = false; | |
12914 | } | |
24929352 DV |
12915 | |
12916 | WARN_ON(crtc->active); | |
12917 | crtc->base.enabled = false; | |
12918 | } | |
24929352 | 12919 | |
7fad798e DV |
12920 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
12921 | crtc->pipe == PIPE_A && !crtc->active) { | |
12922 | /* BIOS forgot to enable pipe A, this mostly happens after | |
12923 | * resume. Force-enable the pipe to fix this, the update_dpms | |
12924 | * call below we restore the pipe to the right state, but leave | |
12925 | * the required bits on. */ | |
12926 | intel_enable_pipe_a(dev); | |
12927 | } | |
12928 | ||
24929352 DV |
12929 | /* Adjust the state of the output pipe according to whether we |
12930 | * have active connectors/encoders. */ | |
12931 | intel_crtc_update_dpms(&crtc->base); | |
12932 | ||
12933 | if (crtc->active != crtc->base.enabled) { | |
12934 | struct intel_encoder *encoder; | |
12935 | ||
12936 | /* This can happen either due to bugs in the get_hw_state | |
12937 | * functions or because the pipe is force-enabled due to the | |
12938 | * pipe A quirk. */ | |
12939 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
12940 | crtc->base.base.id, | |
12941 | crtc->base.enabled ? "enabled" : "disabled", | |
12942 | crtc->active ? "enabled" : "disabled"); | |
12943 | ||
12944 | crtc->base.enabled = crtc->active; | |
12945 | ||
12946 | /* Because we only establish the connector -> encoder -> | |
12947 | * crtc links if something is active, this means the | |
12948 | * crtc is now deactivated. Break the links. connector | |
12949 | * -> encoder links are only establish when things are | |
12950 | * actually up, hence no need to break them. */ | |
12951 | WARN_ON(crtc->active); | |
12952 | ||
12953 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { | |
12954 | WARN_ON(encoder->connectors_active); | |
12955 | encoder->base.crtc = NULL; | |
12956 | } | |
12957 | } | |
c5ab3bc0 DV |
12958 | |
12959 | if (crtc->active || IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen < 5) { | |
4cc31489 DV |
12960 | /* |
12961 | * We start out with underrun reporting disabled to avoid races. | |
12962 | * For correct bookkeeping mark this on active crtcs. | |
12963 | * | |
c5ab3bc0 DV |
12964 | * Also on gmch platforms we dont have any hardware bits to |
12965 | * disable the underrun reporting. Which means we need to start | |
12966 | * out with underrun reporting disabled also on inactive pipes, | |
12967 | * since otherwise we'll complain about the garbage we read when | |
12968 | * e.g. coming up after runtime pm. | |
12969 | * | |
4cc31489 DV |
12970 | * No protection against concurrent access is required - at |
12971 | * worst a fifo underrun happens which also sets this to false. | |
12972 | */ | |
12973 | crtc->cpu_fifo_underrun_disabled = true; | |
12974 | crtc->pch_fifo_underrun_disabled = true; | |
80715b2f VS |
12975 | |
12976 | update_scanline_offset(crtc); | |
4cc31489 | 12977 | } |
24929352 DV |
12978 | } |
12979 | ||
12980 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
12981 | { | |
12982 | struct intel_connector *connector; | |
12983 | struct drm_device *dev = encoder->base.dev; | |
12984 | ||
12985 | /* We need to check both for a crtc link (meaning that the | |
12986 | * encoder is active and trying to read from a pipe) and the | |
12987 | * pipe itself being active. */ | |
12988 | bool has_active_crtc = encoder->base.crtc && | |
12989 | to_intel_crtc(encoder->base.crtc)->active; | |
12990 | ||
12991 | if (encoder->connectors_active && !has_active_crtc) { | |
12992 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
12993 | encoder->base.base.id, | |
8e329a03 | 12994 | encoder->base.name); |
24929352 DV |
12995 | |
12996 | /* Connector is active, but has no active pipe. This is | |
12997 | * fallout from our resume register restoring. Disable | |
12998 | * the encoder manually again. */ | |
12999 | if (encoder->base.crtc) { | |
13000 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
13001 | encoder->base.base.id, | |
8e329a03 | 13002 | encoder->base.name); |
24929352 | 13003 | encoder->disable(encoder); |
a62d1497 VS |
13004 | if (encoder->post_disable) |
13005 | encoder->post_disable(encoder); | |
24929352 | 13006 | } |
7f1950fb EE |
13007 | encoder->base.crtc = NULL; |
13008 | encoder->connectors_active = false; | |
24929352 DV |
13009 | |
13010 | /* Inconsistent output/port/pipe state happens presumably due to | |
13011 | * a bug in one of the get_hw_state functions. Or someplace else | |
13012 | * in our code, like the register restore mess on resume. Clamp | |
13013 | * things to off as a safer default. */ | |
13014 | list_for_each_entry(connector, | |
13015 | &dev->mode_config.connector_list, | |
13016 | base.head) { | |
13017 | if (connector->encoder != encoder) | |
13018 | continue; | |
7f1950fb EE |
13019 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
13020 | connector->base.encoder = NULL; | |
24929352 DV |
13021 | } |
13022 | } | |
13023 | /* Enabled encoders without active connectors will be fixed in | |
13024 | * the crtc fixup. */ | |
13025 | } | |
13026 | ||
04098753 | 13027 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
13028 | { |
13029 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766aa1c4 | 13030 | u32 vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 13031 | |
04098753 ID |
13032 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
13033 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
13034 | i915_disable_vga(dev); | |
13035 | } | |
13036 | } | |
13037 | ||
13038 | void i915_redisable_vga(struct drm_device *dev) | |
13039 | { | |
13040 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13041 | ||
8dc8a27c PZ |
13042 | /* This function can be called both from intel_modeset_setup_hw_state or |
13043 | * at a very early point in our resume sequence, where the power well | |
13044 | * structures are not yet restored. Since this function is at a very | |
13045 | * paranoid "someone might have enabled VGA while we were not looking" | |
13046 | * level, just check if the power well is enabled instead of trying to | |
13047 | * follow the "don't touch the power well if we don't need it" policy | |
13048 | * the rest of the driver uses. */ | |
04098753 | 13049 | if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
13050 | return; |
13051 | ||
04098753 | 13052 | i915_redisable_vga_power_on(dev); |
0fde901f KM |
13053 | } |
13054 | ||
98ec7739 VS |
13055 | static bool primary_get_hw_state(struct intel_crtc *crtc) |
13056 | { | |
13057 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
13058 | ||
13059 | if (!crtc->active) | |
13060 | return false; | |
13061 | ||
13062 | return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE; | |
13063 | } | |
13064 | ||
30e984df | 13065 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
13066 | { |
13067 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13068 | enum pipe pipe; | |
24929352 DV |
13069 | struct intel_crtc *crtc; |
13070 | struct intel_encoder *encoder; | |
13071 | struct intel_connector *connector; | |
5358901f | 13072 | int i; |
24929352 | 13073 | |
d3fcc808 | 13074 | for_each_intel_crtc(dev, crtc) { |
88adfff1 | 13075 | memset(&crtc->config, 0, sizeof(crtc->config)); |
3b117c8f | 13076 | |
9953599b DV |
13077 | crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE; |
13078 | ||
0e8ffe1b DV |
13079 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
13080 | &crtc->config); | |
24929352 DV |
13081 | |
13082 | crtc->base.enabled = crtc->active; | |
98ec7739 | 13083 | crtc->primary_enabled = primary_get_hw_state(crtc); |
24929352 DV |
13084 | |
13085 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
13086 | crtc->base.base.id, | |
13087 | crtc->active ? "enabled" : "disabled"); | |
13088 | } | |
13089 | ||
5358901f DV |
13090 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
13091 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
13092 | ||
13093 | pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state); | |
13094 | pll->active = 0; | |
d3fcc808 | 13095 | for_each_intel_crtc(dev, crtc) { |
5358901f DV |
13096 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) |
13097 | pll->active++; | |
13098 | } | |
13099 | pll->refcount = pll->active; | |
13100 | ||
35c95375 DV |
13101 | DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n", |
13102 | pll->name, pll->refcount, pll->on); | |
bd2bb1b9 PZ |
13103 | |
13104 | if (pll->refcount) | |
13105 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); | |
5358901f DV |
13106 | } |
13107 | ||
b2784e15 | 13108 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
13109 | pipe = 0; |
13110 | ||
13111 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
13112 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
13113 | encoder->base.crtc = &crtc->base; | |
1d37b689 | 13114 | encoder->get_config(encoder, &crtc->config); |
24929352 DV |
13115 | } else { |
13116 | encoder->base.crtc = NULL; | |
13117 | } | |
13118 | ||
13119 | encoder->connectors_active = false; | |
6f2bcceb | 13120 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 13121 | encoder->base.base.id, |
8e329a03 | 13122 | encoder->base.name, |
24929352 | 13123 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 13124 | pipe_name(pipe)); |
24929352 DV |
13125 | } |
13126 | ||
13127 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
13128 | base.head) { | |
13129 | if (connector->get_hw_state(connector)) { | |
13130 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
13131 | connector->encoder->connectors_active = true; | |
13132 | connector->base.encoder = &connector->encoder->base; | |
13133 | } else { | |
13134 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
13135 | connector->base.encoder = NULL; | |
13136 | } | |
13137 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
13138 | connector->base.base.id, | |
c23cc417 | 13139 | connector->base.name, |
24929352 DV |
13140 | connector->base.encoder ? "enabled" : "disabled"); |
13141 | } | |
30e984df DV |
13142 | } |
13143 | ||
13144 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm | |
13145 | * and i915 state tracking structures. */ | |
13146 | void intel_modeset_setup_hw_state(struct drm_device *dev, | |
13147 | bool force_restore) | |
13148 | { | |
13149 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13150 | enum pipe pipe; | |
30e984df DV |
13151 | struct intel_crtc *crtc; |
13152 | struct intel_encoder *encoder; | |
35c95375 | 13153 | int i; |
30e984df DV |
13154 | |
13155 | intel_modeset_readout_hw_state(dev); | |
24929352 | 13156 | |
babea61d JB |
13157 | /* |
13158 | * Now that we have the config, copy it to each CRTC struct | |
13159 | * Note that this could go away if we move to using crtc_config | |
13160 | * checking everywhere. | |
13161 | */ | |
d3fcc808 | 13162 | for_each_intel_crtc(dev, crtc) { |
d330a953 | 13163 | if (crtc->active && i915.fastboot) { |
f6a83288 | 13164 | intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config); |
babea61d JB |
13165 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", |
13166 | crtc->base.base.id); | |
13167 | drm_mode_debug_printmodeline(&crtc->base.mode); | |
13168 | } | |
13169 | } | |
13170 | ||
24929352 | 13171 | /* HW state is read out, now we need to sanitize this mess. */ |
b2784e15 | 13172 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
13173 | intel_sanitize_encoder(encoder); |
13174 | } | |
13175 | ||
055e393f | 13176 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
13177 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
13178 | intel_sanitize_crtc(crtc); | |
c0b03411 | 13179 | intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]"); |
24929352 | 13180 | } |
9a935856 | 13181 | |
35c95375 DV |
13182 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
13183 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
13184 | ||
13185 | if (!pll->on || pll->active) | |
13186 | continue; | |
13187 | ||
13188 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
13189 | ||
13190 | pll->disable(dev_priv, pll); | |
13191 | pll->on = false; | |
13192 | } | |
13193 | ||
96f90c54 | 13194 | if (HAS_PCH_SPLIT(dev)) |
243e6a44 VS |
13195 | ilk_wm_get_hw_state(dev); |
13196 | ||
45e2b5f6 | 13197 | if (force_restore) { |
7d0bc1ea VS |
13198 | i915_redisable_vga(dev); |
13199 | ||
f30da187 DV |
13200 | /* |
13201 | * We need to use raw interfaces for restoring state to avoid | |
13202 | * checking (bogus) intermediate states. | |
13203 | */ | |
055e393f | 13204 | for_each_pipe(dev_priv, pipe) { |
b5644d05 JB |
13205 | struct drm_crtc *crtc = |
13206 | dev_priv->pipe_to_crtc_mapping[pipe]; | |
f30da187 DV |
13207 | |
13208 | __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, | |
f4510a27 | 13209 | crtc->primary->fb); |
45e2b5f6 DV |
13210 | } |
13211 | } else { | |
13212 | intel_modeset_update_staged_output_state(dev); | |
13213 | } | |
8af6cf88 DV |
13214 | |
13215 | intel_modeset_check_state(dev); | |
2c7111db CW |
13216 | } |
13217 | ||
13218 | void intel_modeset_gem_init(struct drm_device *dev) | |
13219 | { | |
484b41dd | 13220 | struct drm_crtc *c; |
2ff8fde1 | 13221 | struct drm_i915_gem_object *obj; |
484b41dd | 13222 | |
ae48434c ID |
13223 | mutex_lock(&dev->struct_mutex); |
13224 | intel_init_gt_powersave(dev); | |
13225 | mutex_unlock(&dev->struct_mutex); | |
13226 | ||
1833b134 | 13227 | intel_modeset_init_hw(dev); |
02e792fb DV |
13228 | |
13229 | intel_setup_overlay(dev); | |
484b41dd JB |
13230 | |
13231 | /* | |
13232 | * Make sure any fbs we allocated at startup are properly | |
13233 | * pinned & fenced. When we do the allocation it's too early | |
13234 | * for this. | |
13235 | */ | |
13236 | mutex_lock(&dev->struct_mutex); | |
70e1e0ec | 13237 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
13238 | obj = intel_fb_obj(c->primary->fb); |
13239 | if (obj == NULL) | |
484b41dd JB |
13240 | continue; |
13241 | ||
2ff8fde1 | 13242 | if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) { |
484b41dd JB |
13243 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
13244 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
13245 | drm_framebuffer_unreference(c->primary->fb); |
13246 | c->primary->fb = NULL; | |
484b41dd JB |
13247 | } |
13248 | } | |
13249 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
13250 | } |
13251 | ||
4932e2c3 ID |
13252 | void intel_connector_unregister(struct intel_connector *intel_connector) |
13253 | { | |
13254 | struct drm_connector *connector = &intel_connector->base; | |
13255 | ||
13256 | intel_panel_destroy_backlight(connector); | |
34ea3d38 | 13257 | drm_connector_unregister(connector); |
4932e2c3 ID |
13258 | } |
13259 | ||
79e53945 JB |
13260 | void intel_modeset_cleanup(struct drm_device *dev) |
13261 | { | |
652c393a | 13262 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9255d57 | 13263 | struct drm_connector *connector; |
652c393a | 13264 | |
fd0c0642 DV |
13265 | /* |
13266 | * Interrupts and polling as the first thing to avoid creating havoc. | |
13267 | * Too much stuff here (turning of rps, connectors, ...) would | |
13268 | * experience fancy races otherwise. | |
13269 | */ | |
13270 | drm_irq_uninstall(dev); | |
1d0d343a | 13271 | intel_hpd_cancel_work(dev_priv); |
eb21b92b JB |
13272 | dev_priv->pm._irqs_disabled = true; |
13273 | ||
fd0c0642 DV |
13274 | /* |
13275 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
13276 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
13277 | */ | |
f87ea761 | 13278 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 13279 | |
652c393a JB |
13280 | mutex_lock(&dev->struct_mutex); |
13281 | ||
723bfd70 JB |
13282 | intel_unregister_dsm_handler(); |
13283 | ||
973d04f9 | 13284 | intel_disable_fbc(dev); |
e70236a8 | 13285 | |
8090c6b9 | 13286 | intel_disable_gt_powersave(dev); |
0cdab21f | 13287 | |
930ebb46 DV |
13288 | ironlake_teardown_rc6(dev); |
13289 | ||
69341a5e KH |
13290 | mutex_unlock(&dev->struct_mutex); |
13291 | ||
1630fe75 CW |
13292 | /* flush any delayed tasks or pending work */ |
13293 | flush_scheduled_work(); | |
13294 | ||
db31af1d JN |
13295 | /* destroy the backlight and sysfs files before encoders/connectors */ |
13296 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4932e2c3 ID |
13297 | struct intel_connector *intel_connector; |
13298 | ||
13299 | intel_connector = to_intel_connector(connector); | |
13300 | intel_connector->unregister(intel_connector); | |
db31af1d | 13301 | } |
d9255d57 | 13302 | |
79e53945 | 13303 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
13304 | |
13305 | intel_cleanup_overlay(dev); | |
ae48434c ID |
13306 | |
13307 | mutex_lock(&dev->struct_mutex); | |
13308 | intel_cleanup_gt_powersave(dev); | |
13309 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
13310 | } |
13311 | ||
f1c79df3 ZW |
13312 | /* |
13313 | * Return which encoder is currently attached for connector. | |
13314 | */ | |
df0e9248 | 13315 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 13316 | { |
df0e9248 CW |
13317 | return &intel_attached_encoder(connector)->base; |
13318 | } | |
f1c79df3 | 13319 | |
df0e9248 CW |
13320 | void intel_connector_attach_encoder(struct intel_connector *connector, |
13321 | struct intel_encoder *encoder) | |
13322 | { | |
13323 | connector->encoder = encoder; | |
13324 | drm_mode_connector_attach_encoder(&connector->base, | |
13325 | &encoder->base); | |
79e53945 | 13326 | } |
28d52043 DA |
13327 | |
13328 | /* | |
13329 | * set vga decode state - true == enable VGA decode | |
13330 | */ | |
13331 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
13332 | { | |
13333 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 13334 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
13335 | u16 gmch_ctrl; |
13336 | ||
75fa041d CW |
13337 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
13338 | DRM_ERROR("failed to read control word\n"); | |
13339 | return -EIO; | |
13340 | } | |
13341 | ||
c0cc8a55 CW |
13342 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
13343 | return 0; | |
13344 | ||
28d52043 DA |
13345 | if (state) |
13346 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
13347 | else | |
13348 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
13349 | |
13350 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
13351 | DRM_ERROR("failed to write control word\n"); | |
13352 | return -EIO; | |
13353 | } | |
13354 | ||
28d52043 DA |
13355 | return 0; |
13356 | } | |
c4a1d9e4 | 13357 | |
c4a1d9e4 | 13358 | struct intel_display_error_state { |
ff57f1b0 PZ |
13359 | |
13360 | u32 power_well_driver; | |
13361 | ||
63b66e5b CW |
13362 | int num_transcoders; |
13363 | ||
c4a1d9e4 CW |
13364 | struct intel_cursor_error_state { |
13365 | u32 control; | |
13366 | u32 position; | |
13367 | u32 base; | |
13368 | u32 size; | |
52331309 | 13369 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
13370 | |
13371 | struct intel_pipe_error_state { | |
ddf9c536 | 13372 | bool power_domain_on; |
c4a1d9e4 | 13373 | u32 source; |
f301b1e1 | 13374 | u32 stat; |
52331309 | 13375 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
13376 | |
13377 | struct intel_plane_error_state { | |
13378 | u32 control; | |
13379 | u32 stride; | |
13380 | u32 size; | |
13381 | u32 pos; | |
13382 | u32 addr; | |
13383 | u32 surface; | |
13384 | u32 tile_offset; | |
52331309 | 13385 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
13386 | |
13387 | struct intel_transcoder_error_state { | |
ddf9c536 | 13388 | bool power_domain_on; |
63b66e5b CW |
13389 | enum transcoder cpu_transcoder; |
13390 | ||
13391 | u32 conf; | |
13392 | ||
13393 | u32 htotal; | |
13394 | u32 hblank; | |
13395 | u32 hsync; | |
13396 | u32 vtotal; | |
13397 | u32 vblank; | |
13398 | u32 vsync; | |
13399 | } transcoder[4]; | |
c4a1d9e4 CW |
13400 | }; |
13401 | ||
13402 | struct intel_display_error_state * | |
13403 | intel_display_capture_error_state(struct drm_device *dev) | |
13404 | { | |
fbee40df | 13405 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 13406 | struct intel_display_error_state *error; |
63b66e5b CW |
13407 | int transcoders[] = { |
13408 | TRANSCODER_A, | |
13409 | TRANSCODER_B, | |
13410 | TRANSCODER_C, | |
13411 | TRANSCODER_EDP, | |
13412 | }; | |
c4a1d9e4 CW |
13413 | int i; |
13414 | ||
63b66e5b CW |
13415 | if (INTEL_INFO(dev)->num_pipes == 0) |
13416 | return NULL; | |
13417 | ||
9d1cb914 | 13418 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
13419 | if (error == NULL) |
13420 | return NULL; | |
13421 | ||
190be112 | 13422 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
13423 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
13424 | ||
055e393f | 13425 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 13426 | error->pipe[i].power_domain_on = |
bfafe93a ID |
13427 | intel_display_power_enabled_unlocked(dev_priv, |
13428 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 13429 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
13430 | continue; |
13431 | ||
5efb3e28 VS |
13432 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
13433 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
13434 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
13435 | |
13436 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
13437 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 13438 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 13439 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
13440 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
13441 | } | |
ca291363 PZ |
13442 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
13443 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
13444 | if (INTEL_INFO(dev)->gen >= 4) { |
13445 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
13446 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
13447 | } | |
13448 | ||
c4a1d9e4 | 13449 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 13450 | |
3abfce77 | 13451 | if (HAS_GMCH_DISPLAY(dev)) |
f301b1e1 | 13452 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
13453 | } |
13454 | ||
13455 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
13456 | if (HAS_DDI(dev_priv->dev)) | |
13457 | error->num_transcoders++; /* Account for eDP. */ | |
13458 | ||
13459 | for (i = 0; i < error->num_transcoders; i++) { | |
13460 | enum transcoder cpu_transcoder = transcoders[i]; | |
13461 | ||
ddf9c536 | 13462 | error->transcoder[i].power_domain_on = |
bfafe93a | 13463 | intel_display_power_enabled_unlocked(dev_priv, |
38cc1daf | 13464 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 13465 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
13466 | continue; |
13467 | ||
63b66e5b CW |
13468 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
13469 | ||
13470 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
13471 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
13472 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
13473 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
13474 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
13475 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
13476 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
13477 | } |
13478 | ||
13479 | return error; | |
13480 | } | |
13481 | ||
edc3d884 MK |
13482 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
13483 | ||
c4a1d9e4 | 13484 | void |
edc3d884 | 13485 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
13486 | struct drm_device *dev, |
13487 | struct intel_display_error_state *error) | |
13488 | { | |
055e393f | 13489 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
13490 | int i; |
13491 | ||
63b66e5b CW |
13492 | if (!error) |
13493 | return; | |
13494 | ||
edc3d884 | 13495 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 13496 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 13497 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 13498 | error->power_well_driver); |
055e393f | 13499 | for_each_pipe(dev_priv, i) { |
edc3d884 | 13500 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 ID |
13501 | err_printf(m, " Power: %s\n", |
13502 | error->pipe[i].power_domain_on ? "on" : "off"); | |
edc3d884 | 13503 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 13504 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
13505 | |
13506 | err_printf(m, "Plane [%d]:\n", i); | |
13507 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
13508 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 13509 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
13510 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
13511 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 13512 | } |
4b71a570 | 13513 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 13514 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 13515 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
13516 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
13517 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
13518 | } |
13519 | ||
edc3d884 MK |
13520 | err_printf(m, "Cursor [%d]:\n", i); |
13521 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
13522 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
13523 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 13524 | } |
63b66e5b CW |
13525 | |
13526 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 13527 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 13528 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 ID |
13529 | err_printf(m, " Power: %s\n", |
13530 | error->transcoder[i].power_domain_on ? "on" : "off"); | |
63b66e5b CW |
13531 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
13532 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
13533 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
13534 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
13535 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
13536 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
13537 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
13538 | } | |
c4a1d9e4 | 13539 | } |
e2fcdaa9 VS |
13540 | |
13541 | void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file) | |
13542 | { | |
13543 | struct intel_crtc *crtc; | |
13544 | ||
13545 | for_each_intel_crtc(dev, crtc) { | |
13546 | struct intel_unpin_work *work; | |
13547 | unsigned long irqflags; | |
13548 | ||
13549 | spin_lock_irqsave(&dev->event_lock, irqflags); | |
13550 | ||
13551 | work = crtc->unpin_work; | |
13552 | ||
13553 | if (work && work->event && | |
13554 | work->event->base.file_priv == file) { | |
13555 | kfree(work->event); | |
13556 | work->event = NULL; | |
13557 | } | |
13558 | ||
13559 | spin_unlock_irqrestore(&dev->event_lock, irqflags); | |
13560 | } | |
13561 | } |