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drm/i915: Don't factor in pixel multplier when deriving dotclock from link clock...
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
f1f644dc
JB		 48static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
49 struct intel_crtc_config *pipe_config);
50static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
51 struct intel_crtc_config *pipe_config);
52
e7457a9a
DL		 53static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
54 int x, int y, struct drm_framebuffer *old_fb);
55
56
79e53945 57typedef struct {
0206e353 58 int min, max;
79e53945
JB		 59} intel_range_t;
60
61typedef struct {
0206e353
AJ		 62 int dot_limit;
63 int p2_slow, p2_fast;
79e53945
JB		 64} intel_p2_t;
65
d4906093
ML		 66typedef struct intel_limit intel_limit_t;
67struct intel_limit {
0206e353
AJ		 68 intel_range_t dot, vco, n, m, m1, m2, p, p1;
69 intel_p2_t p2;
d4906093 70};
79e53945 71
d2acd215
DV		 72int
73intel_pch_rawclk(struct drm_device *dev)
74{
75 struct drm_i915_private *dev_priv = dev->dev_private;
76
77 WARN_ON(!HAS_PCH_SPLIT(dev));
78
79 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
80}
81
021357ac
CW		 82static inline u32 /* units of 100MHz */
83intel_fdi_link_freq(struct drm_device *dev)
84{
8b99e68c
CW		 85 if (IS_GEN5(dev)) {
86 struct drm_i915_private *dev_priv = dev->dev_private;
87 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
88 } else
89 return 27;
021357ac
CW		 90}
91
5d536e28 92static const intel_limit_t intel_limits_i8xx_dac = {
0206e353
AJ		 93 .dot = { .min = 25000, .max = 350000 },
94 .vco = { .min = 930000, .max = 1400000 },
95 .n = { .min = 3, .max = 16 },
96 .m = { .min = 96, .max = 140 },
97 .m1 = { .min = 18, .max = 26 },
98 .m2 = { .min = 6, .max = 16 },
99 .p = { .min = 4, .max = 128 },
100 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 101 .p2 = { .dot_limit = 165000,
102 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 103};
104
5d536e28
DV		 105static const intel_limit_t intel_limits_i8xx_dvo = {
106 .dot = { .min = 25000, .max = 350000 },
107 .vco = { .min = 930000, .max = 1400000 },
108 .n = { .min = 3, .max = 16 },
109 .m = { .min = 96, .max = 140 },
110 .m1 = { .min = 18, .max = 26 },
111 .m2 = { .min = 6, .max = 16 },
112 .p = { .min = 4, .max = 128 },
113 .p1 = { .min = 2, .max = 33 },
114 .p2 = { .dot_limit = 165000,
115 .p2_slow = 4, .p2_fast = 4 },
116};
117
e4b36699 118static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 119 .dot = { .min = 25000, .max = 350000 },
120 .vco = { .min = 930000, .max = 1400000 },
121 .n = { .min = 3, .max = 16 },
122 .m = { .min = 96, .max = 140 },
123 .m1 = { .min = 18, .max = 26 },
124 .m2 = { .min = 6, .max = 16 },
125 .p = { .min = 4, .max = 128 },
126 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 127 .p2 = { .dot_limit = 165000,
128 .p2_slow = 14, .p2_fast = 7 },
e4b36699 129};
273e27ca 130
e4b36699 131static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 132 .dot = { .min = 20000, .max = 400000 },
133 .vco = { .min = 1400000, .max = 2800000 },
134 .n = { .min = 1, .max = 6 },
135 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 136 .m1 = { .min = 8, .max = 18 },
137 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 138 .p = { .min = 5, .max = 80 },
139 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 140 .p2 = { .dot_limit = 200000,
141 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 142};
143
144static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 145 .dot = { .min = 20000, .max = 400000 },
146 .vco = { .min = 1400000, .max = 2800000 },
147 .n = { .min = 1, .max = 6 },
148 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 149 .m1 = { .min = 8, .max = 18 },
150 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 151 .p = { .min = 7, .max = 98 },
152 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 153 .p2 = { .dot_limit = 112000,
154 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 155};
156
273e27ca 157
e4b36699 158static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 159 .dot = { .min = 25000, .max = 270000 },
160 .vco = { .min = 1750000, .max = 3500000},
161 .n = { .min = 1, .max = 4 },
162 .m = { .min = 104, .max = 138 },
163 .m1 = { .min = 17, .max = 23 },
164 .m2 = { .min = 5, .max = 11 },
165 .p = { .min = 10, .max = 30 },
166 .p1 = { .min = 1, .max = 3},
167 .p2 = { .dot_limit = 270000,
168 .p2_slow = 10,
169 .p2_fast = 10
044c7c41 170 },
e4b36699
KP		 171};
172
173static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 174 .dot = { .min = 22000, .max = 400000 },
175 .vco = { .min = 1750000, .max = 3500000},
176 .n = { .min = 1, .max = 4 },
177 .m = { .min = 104, .max = 138 },
178 .m1 = { .min = 16, .max = 23 },
179 .m2 = { .min = 5, .max = 11 },
180 .p = { .min = 5, .max = 80 },
181 .p1 = { .min = 1, .max = 8},
182 .p2 = { .dot_limit = 165000,
183 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 184};
185
186static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 187 .dot = { .min = 20000, .max = 115000 },
188 .vco = { .min = 1750000, .max = 3500000 },
189 .n = { .min = 1, .max = 3 },
190 .m = { .min = 104, .max = 138 },
191 .m1 = { .min = 17, .max = 23 },
192 .m2 = { .min = 5, .max = 11 },
193 .p = { .min = 28, .max = 112 },
194 .p1 = { .min = 2, .max = 8 },
195 .p2 = { .dot_limit = 0,
196 .p2_slow = 14, .p2_fast = 14
044c7c41 197 },
e4b36699
KP		 198};
199
200static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 201 .dot = { .min = 80000, .max = 224000 },
202 .vco = { .min = 1750000, .max = 3500000 },
203 .n = { .min = 1, .max = 3 },
204 .m = { .min = 104, .max = 138 },
205 .m1 = { .min = 17, .max = 23 },
206 .m2 = { .min = 5, .max = 11 },
207 .p = { .min = 14, .max = 42 },
208 .p1 = { .min = 2, .max = 6 },
209 .p2 = { .dot_limit = 0,
210 .p2_slow = 7, .p2_fast = 7
044c7c41 211 },
e4b36699
KP		 212};
213
f2b115e6 214static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 215 .dot = { .min = 20000, .max = 400000},
216 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 217 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 218 .n = { .min = 3, .max = 6 },
219 .m = { .min = 2, .max = 256 },
273e27ca 220 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 221 .m1 = { .min = 0, .max = 0 },
222 .m2 = { .min = 0, .max = 254 },
223 .p = { .min = 5, .max = 80 },
224 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 225 .p2 = { .dot_limit = 200000,
226 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 227};
228
f2b115e6 229static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 230 .dot = { .min = 20000, .max = 400000 },
231 .vco = { .min = 1700000, .max = 3500000 },
232 .n = { .min = 3, .max = 6 },
233 .m = { .min = 2, .max = 256 },
234 .m1 = { .min = 0, .max = 0 },
235 .m2 = { .min = 0, .max = 254 },
236 .p = { .min = 7, .max = 112 },
237 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 238 .p2 = { .dot_limit = 112000,
239 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 240};
241
273e27ca
EA		 242/* Ironlake / Sandybridge
243 *
244 * We calculate clock using (register_value + 2) for N/M1/M2, so here
245 * the range value for them is (actual_value - 2).
246 */
b91ad0ec 247static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 248 .dot = { .min = 25000, .max = 350000 },
249 .vco = { .min = 1760000, .max = 3510000 },
250 .n = { .min = 1, .max = 5 },
251 .m = { .min = 79, .max = 127 },
252 .m1 = { .min = 12, .max = 22 },
253 .m2 = { .min = 5, .max = 9 },
254 .p = { .min = 5, .max = 80 },
255 .p1 = { .min = 1, .max = 8 },
256 .p2 = { .dot_limit = 225000,
257 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 258};
259
b91ad0ec 260static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 261 .dot = { .min = 25000, .max = 350000 },
262 .vco = { .min = 1760000, .max = 3510000 },
263 .n = { .min = 1, .max = 3 },
264 .m = { .min = 79, .max = 118 },
265 .m1 = { .min = 12, .max = 22 },
266 .m2 = { .min = 5, .max = 9 },
267 .p = { .min = 28, .max = 112 },
268 .p1 = { .min = 2, .max = 8 },
269 .p2 = { .dot_limit = 225000,
270 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 271};
272
273static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 274 .dot = { .min = 25000, .max = 350000 },
275 .vco = { .min = 1760000, .max = 3510000 },
276 .n = { .min = 1, .max = 3 },
277 .m = { .min = 79, .max = 127 },
278 .m1 = { .min = 12, .max = 22 },
279 .m2 = { .min = 5, .max = 9 },
280 .p = { .min = 14, .max = 56 },
281 .p1 = { .min = 2, .max = 8 },
282 .p2 = { .dot_limit = 225000,
283 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 284};
285
273e27ca 286/* LVDS 100mhz refclk limits. */
b91ad0ec 287static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 288 .dot = { .min = 25000, .max = 350000 },
289 .vco = { .min = 1760000, .max = 3510000 },
290 .n = { .min = 1, .max = 2 },
291 .m = { .min = 79, .max = 126 },
292 .m1 = { .min = 12, .max = 22 },
293 .m2 = { .min = 5, .max = 9 },
294 .p = { .min = 28, .max = 112 },
0206e353 295 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 296 .p2 = { .dot_limit = 225000,
297 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 298};
299
300static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 301 .dot = { .min = 25000, .max = 350000 },
302 .vco = { .min = 1760000, .max = 3510000 },
303 .n = { .min = 1, .max = 3 },
304 .m = { .min = 79, .max = 126 },
305 .m1 = { .min = 12, .max = 22 },
306 .m2 = { .min = 5, .max = 9 },
307 .p = { .min = 14, .max = 42 },
0206e353 308 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 309 .p2 = { .dot_limit = 225000,
310 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 311};
312
a0c4da24
JB		 313static const intel_limit_t intel_limits_vlv_dac = {
314 .dot = { .min = 25000, .max = 270000 },
315 .vco = { .min = 4000000, .max = 6000000 },
316 .n = { .min = 1, .max = 7 },
317 .m = { .min = 22, .max = 450 }, /* guess */
318 .m1 = { .min = 2, .max = 3 },
319 .m2 = { .min = 11, .max = 156 },
320 .p = { .min = 10, .max = 30 },
75e53986 321 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 322 .p2 = { .dot_limit = 270000,
323 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 324};
325
326static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 327 .dot = { .min = 25000, .max = 270000 },
328 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 329 .n = { .min = 1, .max = 7 },
330 .m = { .min = 60, .max = 300 }, /* guess */
331 .m1 = { .min = 2, .max = 3 },
332 .m2 = { .min = 11, .max = 156 },
333 .p = { .min = 10, .max = 30 },
334 .p1 = { .min = 2, .max = 3 },
335 .p2 = { .dot_limit = 270000,
336 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 337};
338
1b894b59
CW		 339static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
340 int refclk)
2c07245f 341{
b91ad0ec 342 struct drm_device *dev = crtc->dev;
2c07245f 343 const intel_limit_t *limit;
b91ad0ec
ZW		 344
345 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 346 if (intel_is_dual_link_lvds(dev)) {
1b894b59 347 if (refclk == 100000)
b91ad0ec
ZW		 348 limit = &intel_limits_ironlake_dual_lvds_100m;
349 else
350 limit = &intel_limits_ironlake_dual_lvds;
351 } else {
1b894b59 352 if (refclk == 100000)
b91ad0ec
ZW		 353 limit = &intel_limits_ironlake_single_lvds_100m;
354 else
355 limit = &intel_limits_ironlake_single_lvds;
356 }
c6bb3538 357 } else
b91ad0ec 358 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 359
360 return limit;
361}
362
044c7c41
ML		 363static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
364{
365 struct drm_device *dev = crtc->dev;
044c7c41
ML		 366 const intel_limit_t *limit;
367
368 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 369 if (intel_is_dual_link_lvds(dev))
e4b36699 370 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 371 else
e4b36699 372 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 373 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
374 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 375 limit = &intel_limits_g4x_hdmi;
044c7c41 376 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 377 limit = &intel_limits_g4x_sdvo;
044c7c41 378 } else /* The option is for other outputs */
e4b36699 379 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 380
381 return limit;
382}
383
1b894b59 384static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 385{
386 struct drm_device *dev = crtc->dev;
387 const intel_limit_t *limit;
388
bad720ff 389 if (HAS_PCH_SPLIT(dev))
1b894b59 390 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 391 else if (IS_G4X(dev)) {
044c7c41 392 limit = intel_g4x_limit(crtc);
f2b115e6 393 } else if (IS_PINEVIEW(dev)) {
2177832f 394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 395 limit = &intel_limits_pineview_lvds;
2177832f 396 else
f2b115e6 397 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 398 } else if (IS_VALLEYVIEW(dev)) {
399 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
400 limit = &intel_limits_vlv_dac;
a0c4da24 401 else
65ce4bf5 402 limit = &intel_limits_vlv_hdmi;
a6c45cf0
CW		 403 } else if (!IS_GEN2(dev)) {
404 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
405 limit = &intel_limits_i9xx_lvds;
406 else
407 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 408 } else {
409 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 410 limit = &intel_limits_i8xx_lvds;
5d536e28 411 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
e4b36699 412 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 413 else
414 limit = &intel_limits_i8xx_dac;
79e53945
JB		 415 }
416 return limit;
417}
418
f2b115e6
AJ		 419/* m1 is reserved as 0 in Pineview, n is a ring counter */
420static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 421{
2177832f
SL		 422 clock->m = clock->m2 + 2;
423 clock->p = clock->p1 * clock->p2;
424 clock->vco = refclk * clock->m / clock->n;
425 clock->dot = clock->vco / clock->p;
426}
427
7429e9d4
DV		 428static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
429{
430 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
431}
432
ac58c3f0 433static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 434{
7429e9d4 435 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 436 clock->p = clock->p1 * clock->p2;
437 clock->vco = refclk * clock->m / (clock->n + 2);
438 clock->dot = clock->vco / clock->p;
439}
440
79e53945
JB		 441/**
442 * Returns whether any output on the specified pipe is of the specified type
443 */
4ef69c7a 444bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 445{
4ef69c7a 446 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 447 struct intel_encoder *encoder;
448
6c2b7c12
DV		 449 for_each_encoder_on_crtc(dev, crtc, encoder)
450 if (encoder->type == type)
4ef69c7a
CW		 451 return true;
452
453 return false;
79e53945
JB		 454}
455
7c04d1d9 456#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 457/**
458 * Returns whether the given set of divisors are valid for a given refclk with
459 * the given connectors.
460 */
461
1b894b59
CW		 462static bool intel_PLL_is_valid(struct drm_device *dev,
463 const intel_limit_t *limit,
464 const intel_clock_t *clock)
79e53945 465{
79e53945 466 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 467 INTELPllInvalid("p1 out of range\n");
79e53945 468 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 469 INTELPllInvalid("p out of range\n");
79e53945 470 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 471 INTELPllInvalid("m2 out of range\n");
79e53945 472 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 473 INTELPllInvalid("m1 out of range\n");
f2b115e6 474 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 475 INTELPllInvalid("m1 <= m2\n");
79e53945 476 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 477 INTELPllInvalid("m out of range\n");
79e53945 478 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 479 INTELPllInvalid("n out of range\n");
79e53945 480 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 481 INTELPllInvalid("vco out of range\n");
79e53945
JB		 482 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
483 * connector, etc., rather than just a single range.
484 */
485 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 486 INTELPllInvalid("dot out of range\n");
79e53945
JB		 487
488 return true;
489}
490
d4906093 491static bool
ee9300bb 492i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 493 int target, int refclk, intel_clock_t *match_clock,
494 intel_clock_t *best_clock)
79e53945
JB		 495{
496 struct drm_device *dev = crtc->dev;
79e53945 497 intel_clock_t clock;
79e53945
JB		 498 int err = target;
499
a210b028 500 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 501 /*
a210b028
DV		 502 * For LVDS just rely on its current settings for dual-channel.
503 * We haven't figured out how to reliably set up different
504 * single/dual channel state, if we even can.
79e53945 505 */
1974cad0 506 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 507 clock.p2 = limit->p2.p2_fast;
508 else
509 clock.p2 = limit->p2.p2_slow;
510 } else {
511 if (target < limit->p2.dot_limit)
512 clock.p2 = limit->p2.p2_slow;
513 else
514 clock.p2 = limit->p2.p2_fast;
515 }
516
0206e353 517 memset(best_clock, 0, sizeof(*best_clock));
79e53945 518
42158660
ZY		 519 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
520 clock.m1++) {
521 for (clock.m2 = limit->m2.min;
522 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 523 if (clock.m2 >= clock.m1)
42158660
ZY		 524 break;
525 for (clock.n = limit->n.min;
526 clock.n <= limit->n.max; clock.n++) {
527 for (clock.p1 = limit->p1.min;
528 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 529 int this_err;
530
ac58c3f0
DV		 531 i9xx_clock(refclk, &clock);
532 if (!intel_PLL_is_valid(dev, limit,
533 &clock))
534 continue;
535 if (match_clock &&
536 clock.p != match_clock->p)
537 continue;
538
539 this_err = abs(clock.dot - target);
540 if (this_err < err) {
541 *best_clock = clock;
542 err = this_err;
543 }
544 }
545 }
546 }
547 }
548
549 return (err != target);
550}
551
552static bool
ee9300bb
DV		 553pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
554 int target, int refclk, intel_clock_t *match_clock,
555 intel_clock_t *best_clock)
79e53945
JB		 556{
557 struct drm_device *dev = crtc->dev;
79e53945 558 intel_clock_t clock;
79e53945
JB		 559 int err = target;
560
a210b028 561 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 562 /*
a210b028
DV		 563 * For LVDS just rely on its current settings for dual-channel.
564 * We haven't figured out how to reliably set up different
565 * single/dual channel state, if we even can.
79e53945 566 */
1974cad0 567 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 568 clock.p2 = limit->p2.p2_fast;
569 else
570 clock.p2 = limit->p2.p2_slow;
571 } else {
572 if (target < limit->p2.dot_limit)
573 clock.p2 = limit->p2.p2_slow;
574 else
575 clock.p2 = limit->p2.p2_fast;
576 }
577
0206e353 578 memset(best_clock, 0, sizeof(*best_clock));
79e53945 579
42158660
ZY		 580 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
581 clock.m1++) {
582 for (clock.m2 = limit->m2.min;
583 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 584 for (clock.n = limit->n.min;
585 clock.n <= limit->n.max; clock.n++) {
586 for (clock.p1 = limit->p1.min;
587 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 588 int this_err;
589
ac58c3f0 590 pineview_clock(refclk, &clock);
1b894b59
CW		 591 if (!intel_PLL_is_valid(dev, limit,
592 &clock))
79e53945 593 continue;
cec2f356
SP		 594 if (match_clock &&
595 clock.p != match_clock->p)
596 continue;
79e53945
JB		 597
598 this_err = abs(clock.dot - target);
599 if (this_err < err) {
600 *best_clock = clock;
601 err = this_err;
602 }
603 }
604 }
605 }
606 }
607
608 return (err != target);
609}
610
d4906093 611static bool
ee9300bb
DV		 612g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
613 int target, int refclk, intel_clock_t *match_clock,
614 intel_clock_t *best_clock)
d4906093
ML		 615{
616 struct drm_device *dev = crtc->dev;
d4906093
ML		 617 intel_clock_t clock;
618 int max_n;
619 bool found;
6ba770dc
AJ		 620 /* approximately equals target * 0.00585 */
621 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 622 found = false;
623
624 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 625 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 626 clock.p2 = limit->p2.p2_fast;
627 else
628 clock.p2 = limit->p2.p2_slow;
629 } else {
630 if (target < limit->p2.dot_limit)
631 clock.p2 = limit->p2.p2_slow;
632 else
633 clock.p2 = limit->p2.p2_fast;
634 }
635
636 memset(best_clock, 0, sizeof(*best_clock));
637 max_n = limit->n.max;
f77f13e2 638 /* based on hardware requirement, prefer smaller n to precision */
d4906093 639 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 640 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 641 for (clock.m1 = limit->m1.max;
642 clock.m1 >= limit->m1.min; clock.m1--) {
643 for (clock.m2 = limit->m2.max;
644 clock.m2 >= limit->m2.min; clock.m2--) {
645 for (clock.p1 = limit->p1.max;
646 clock.p1 >= limit->p1.min; clock.p1--) {
647 int this_err;
648
ac58c3f0 649 i9xx_clock(refclk, &clock);
1b894b59
CW		 650 if (!intel_PLL_is_valid(dev, limit,
651 &clock))
d4906093 652 continue;
1b894b59
CW		 653
654 this_err = abs(clock.dot - target);
d4906093
ML		 655 if (this_err < err_most) {
656 *best_clock = clock;
657 err_most = this_err;
658 max_n = clock.n;
659 found = true;
660 }
661 }
662 }
663 }
664 }
2c07245f
ZW		 665 return found;
666}
667
a0c4da24 668static bool
ee9300bb
DV		 669vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
670 int target, int refclk, intel_clock_t *match_clock,
671 intel_clock_t *best_clock)
a0c4da24
JB		 672{
673 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
674 u32 m, n, fastclk;
f3f08572 675 u32 updrate, minupdate, p;
a0c4da24
JB		 676 unsigned long bestppm, ppm, absppm;
677 int dotclk, flag;
678
af447bd3 679 flag = 0;
a0c4da24
JB		 680 dotclk = target * 1000;
681 bestppm = 1000000;
682 ppm = absppm = 0;
683 fastclk = dotclk / (2*100);
684 updrate = 0;
685 minupdate = 19200;
a0c4da24
JB		 686 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
687 bestm1 = bestm2 = bestp1 = bestp2 = 0;
688
689 /* based on hardware requirement, prefer smaller n to precision */
690 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
691 updrate = refclk / n;
692 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
693 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
694 if (p2 > 10)
695 p2 = p2 - 1;
696 p = p1 * p2;
697 /* based on hardware requirement, prefer bigger m1,m2 values */
698 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
699 m2 = (((2*(fastclk * p * n / m1 )) +
700 refclk) / (2*refclk));
701 m = m1 * m2;
702 vco = updrate * m;
703 if (vco >= limit->vco.min && vco < limit->vco.max) {
704 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
705 absppm = (ppm > 0) ? ppm : (-ppm);
706 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
707 bestppm = 0;
708 flag = 1;
709 }
710 if (absppm < bestppm - 10) {
711 bestppm = absppm;
712 flag = 1;
713 }
714 if (flag) {
715 bestn = n;
716 bestm1 = m1;
717 bestm2 = m2;
718 bestp1 = p1;
719 bestp2 = p2;
720 flag = 0;
721 }
722 }
723 }
724 }
725 }
726 }
727 best_clock->n = bestn;
728 best_clock->m1 = bestm1;
729 best_clock->m2 = bestm2;
730 best_clock->p1 = bestp1;
731 best_clock->p2 = bestp2;
732
733 return true;
734}
a4fc5ed6 735
a5c961d1
PZ		 736enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
737 enum pipe pipe)
738{
739 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
740 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
741
3b117c8f 742 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 743}
744
a928d536
PZ		 745static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
746{
747 struct drm_i915_private *dev_priv = dev->dev_private;
748 u32 frame, frame_reg = PIPEFRAME(pipe);
749
750 frame = I915_READ(frame_reg);
751
752 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
753 DRM_DEBUG_KMS("vblank wait timed out\n");
754}
755
9d0498a2
JB		 756/**
757 * intel_wait_for_vblank - wait for vblank on a given pipe
758 * @dev: drm device
759 * @pipe: pipe to wait for
760 *
761 * Wait for vblank to occur on a given pipe. Needed for various bits of
762 * mode setting code.
763 */
764void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 765{
9d0498a2 766 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 767 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 768
a928d536
PZ		 769 if (INTEL_INFO(dev)->gen >= 5) {
770 ironlake_wait_for_vblank(dev, pipe);
771 return;
772 }
773
300387c0
CW		 774 /* Clear existing vblank status. Note this will clear any other
775 * sticky status fields as well.
776 *
777 * This races with i915_driver_irq_handler() with the result
778 * that either function could miss a vblank event. Here it is not
779 * fatal, as we will either wait upon the next vblank interrupt or
780 * timeout. Generally speaking intel_wait_for_vblank() is only
781 * called during modeset at which time the GPU should be idle and
782 * should *not* be performing page flips and thus not waiting on
783 * vblanks...
784 * Currently, the result of us stealing a vblank from the irq
785 * handler is that a single frame will be skipped during swapbuffers.
786 */
787 I915_WRITE(pipestat_reg,
788 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
789
9d0498a2 790 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 791 if (wait_for(I915_READ(pipestat_reg) &
792 PIPE_VBLANK_INTERRUPT_STATUS,
793 50))
9d0498a2
JB		 794 DRM_DEBUG_KMS("vblank wait timed out\n");
795}
796
ab7ad7f6
KP		 797/*
798 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 799 * @dev: drm device
800 * @pipe: pipe to wait for
801 *
802 * After disabling a pipe, we can't wait for vblank in the usual way,
803 * spinning on the vblank interrupt status bit, since we won't actually
804 * see an interrupt when the pipe is disabled.
805 *
ab7ad7f6
KP		 806 * On Gen4 and above:
807 * wait for the pipe register state bit to turn off
808 *
809 * Otherwise:
810 * wait for the display line value to settle (it usually
811 * ends up stopping at the start of the next frame).
58e10eb9 812 *
9d0498a2 813 */
58e10eb9 814void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 815{
816 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 817 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
818 pipe);
ab7ad7f6
KP		 819
820 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 821 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 822
823 /* Wait for the Pipe State to go off */
58e10eb9
CW		 824 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
825 100))
284637d9 826 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 827 } else {
837ba00f 828 u32 last_line, line_mask;
58e10eb9 829 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 830 unsigned long timeout = jiffies + msecs_to_jiffies(100);
831
837ba00f
PZ		 832 if (IS_GEN2(dev))
833 line_mask = DSL_LINEMASK_GEN2;
834 else
835 line_mask = DSL_LINEMASK_GEN3;
836
ab7ad7f6
KP		 837 /* Wait for the display line to settle */
838 do {
837ba00f 839 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 840 mdelay(5);
837ba00f 841 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 842 time_after(timeout, jiffies));
843 if (time_after(jiffies, timeout))
284637d9 844 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 845 }
79e53945
JB		 846}
847
b0ea7d37
DL		 848/*
849 * ibx_digital_port_connected - is the specified port connected?
850 * @dev_priv: i915 private structure
851 * @port: the port to test
852 *
853 * Returns true if @port is connected, false otherwise.
854 */
855bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
856 struct intel_digital_port *port)
857{
858 u32 bit;
859
c36346e3
DL		 860 if (HAS_PCH_IBX(dev_priv->dev)) {
861 switch(port->port) {
862 case PORT_B:
863 bit = SDE_PORTB_HOTPLUG;
864 break;
865 case PORT_C:
866 bit = SDE_PORTC_HOTPLUG;
867 break;
868 case PORT_D:
869 bit = SDE_PORTD_HOTPLUG;
870 break;
871 default:
872 return true;
873 }
874 } else {
875 switch(port->port) {
876 case PORT_B:
877 bit = SDE_PORTB_HOTPLUG_CPT;
878 break;
879 case PORT_C:
880 bit = SDE_PORTC_HOTPLUG_CPT;
881 break;
882 case PORT_D:
883 bit = SDE_PORTD_HOTPLUG_CPT;
884 break;
885 default:
886 return true;
887 }
b0ea7d37
DL		 888 }
889
890 return I915_READ(SDEISR) & bit;
891}
892
b24e7179
JB		 893static const char *state_string(bool enabled)
894{
895 return enabled ? "on" : "off";
896}
897
898/* Only for pre-ILK configs */
55607e8a
DV		 899void assert_pll(struct drm_i915_private *dev_priv,
900 enum pipe pipe, bool state)
b24e7179
JB		 901{
902 int reg;
903 u32 val;
904 bool cur_state;
905
906 reg = DPLL(pipe);
907 val = I915_READ(reg);
908 cur_state = !!(val & DPLL_VCO_ENABLE);
909 WARN(cur_state != state,
910 "PLL state assertion failure (expected %s, current %s)\n",
911 state_string(state), state_string(cur_state));
912}
b24e7179 913
23538ef1
JN		 914/* XXX: the dsi pll is shared between MIPI DSI ports */
915static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
916{
917 u32 val;
918 bool cur_state;
919
920 mutex_lock(&dev_priv->dpio_lock);
921 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
922 mutex_unlock(&dev_priv->dpio_lock);
923
924 cur_state = val & DSI_PLL_VCO_EN;
925 WARN(cur_state != state,
926 "DSI PLL state assertion failure (expected %s, current %s)\n",
927 state_string(state), state_string(cur_state));
928}
929#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
930#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
931
55607e8a 932struct intel_shared_dpll *
e2b78267
DV		 933intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
934{
935 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
936
a43f6e0f 937 if (crtc->config.shared_dpll < 0)
e2b78267
DV		 938 return NULL;
939
a43f6e0f 940 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
e2b78267
DV		 941}
942
040484af 943/* For ILK+ */
55607e8a
DV		 944void assert_shared_dpll(struct drm_i915_private *dev_priv,
945 struct intel_shared_dpll *pll,
946 bool state)
040484af 947{
040484af 948 bool cur_state;
5358901f 949 struct intel_dpll_hw_state hw_state;
040484af 950
9d82aa17
ED		 951 if (HAS_PCH_LPT(dev_priv->dev)) {
952 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
953 return;
954 }
955
92b27b08 956 if (WARN (!pll,
46edb027 957 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 958 return;
ee7b9f93 959
5358901f 960 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
92b27b08 961 WARN(cur_state != state,
5358901f
DV		 962 "%s assertion failure (expected %s, current %s)\n",
963 pll->name, state_string(state), state_string(cur_state));
040484af 964}
040484af
JB		 965
966static void assert_fdi_tx(struct drm_i915_private *dev_priv,
967 enum pipe pipe, bool state)
968{
969 int reg;
970 u32 val;
971 bool cur_state;
ad80a810
PZ		 972 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
973 pipe);
040484af 974
affa9354
PZ		 975 if (HAS_DDI(dev_priv->dev)) {
976 /* DDI does not have a specific FDI_TX register */
ad80a810 977 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 978 val = I915_READ(reg);
ad80a810 979 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 980 } else {
981 reg = FDI_TX_CTL(pipe);
982 val = I915_READ(reg);
983 cur_state = !!(val & FDI_TX_ENABLE);
984 }
040484af
JB		 985 WARN(cur_state != state,
986 "FDI TX state assertion failure (expected %s, current %s)\n",
987 state_string(state), state_string(cur_state));
988}
989#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
990#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
991
992static void assert_fdi_rx(struct drm_i915_private *dev_priv,
993 enum pipe pipe, bool state)
994{
995 int reg;
996 u32 val;
997 bool cur_state;
998
d63fa0dc
PZ		 999 reg = FDI_RX_CTL(pipe);
1000 val = I915_READ(reg);
1001 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1002 WARN(cur_state != state,
1003 "FDI RX state assertion failure (expected %s, current %s)\n",
1004 state_string(state), state_string(cur_state));
1005}
1006#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1007#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1008
1009static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1010 enum pipe pipe)
1011{
1012 int reg;
1013 u32 val;
1014
1015 /* ILK FDI PLL is always enabled */
1016 if (dev_priv->info->gen == 5)
1017 return;
1018
bf507ef7 1019 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1020 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1021 return;
1022
040484af
JB		 1023 reg = FDI_TX_CTL(pipe);
1024 val = I915_READ(reg);
1025 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1026}
1027
55607e8a
DV		 1028void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1029 enum pipe pipe, bool state)
040484af
JB		 1030{
1031 int reg;
1032 u32 val;
55607e8a 1033 bool cur_state;
040484af
JB		 1034
1035 reg = FDI_RX_CTL(pipe);
1036 val = I915_READ(reg);
55607e8a
DV		 1037 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1038 WARN(cur_state != state,
1039 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1040 state_string(state), state_string(cur_state));
040484af
JB		 1041}
1042
ea0760cf
JB		 1043static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1044 enum pipe pipe)
1045{
1046 int pp_reg, lvds_reg;
1047 u32 val;
1048 enum pipe panel_pipe = PIPE_A;
0de3b485 1049 bool locked = true;
ea0760cf
JB		 1050
1051 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1052 pp_reg = PCH_PP_CONTROL;
1053 lvds_reg = PCH_LVDS;
1054 } else {
1055 pp_reg = PP_CONTROL;
1056 lvds_reg = LVDS;
1057 }
1058
1059 val = I915_READ(pp_reg);
1060 if (!(val & PANEL_POWER_ON) ||
1061 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1062 locked = false;
1063
1064 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1065 panel_pipe = PIPE_B;
1066
1067 WARN(panel_pipe == pipe && locked,
1068 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1069 pipe_name(pipe));
ea0760cf
JB		 1070}
1071
b840d907
JB		 1072void assert_pipe(struct drm_i915_private *dev_priv,
1073 enum pipe pipe, bool state)
b24e7179
JB		 1074{
1075 int reg;
1076 u32 val;
63d7bbe9 1077 bool cur_state;
702e7a56
PZ		 1078 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1079 pipe);
b24e7179 1080
8e636784
DV		 1081 /* if we need the pipe A quirk it must be always on */
1082 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1083 state = true;
1084
b97186f0
PZ		 1085 if (!intel_display_power_enabled(dev_priv->dev,
1086 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1087 cur_state = false;
1088 } else {
1089 reg = PIPECONF(cpu_transcoder);
1090 val = I915_READ(reg);
1091 cur_state = !!(val & PIPECONF_ENABLE);
1092 }
1093
63d7bbe9
JB		 1094 WARN(cur_state != state,
1095 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1096 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1097}
1098
931872fc
CW		 1099static void assert_plane(struct drm_i915_private *dev_priv,
1100 enum plane plane, bool state)
b24e7179
JB		 1101{
1102 int reg;
1103 u32 val;
931872fc 1104 bool cur_state;
b24e7179
JB		 1105
1106 reg = DSPCNTR(plane);
1107 val = I915_READ(reg);
931872fc
CW		 1108 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1109 WARN(cur_state != state,
1110 "plane %c assertion failure (expected %s, current %s)\n",
1111 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1112}
1113
931872fc
CW		 1114#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1115#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1116
b24e7179
JB		 1117static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1118 enum pipe pipe)
1119{
653e1026 1120 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1121 int reg, i;
1122 u32 val;
1123 int cur_pipe;
1124
653e1026
VS		 1125 /* Primary planes are fixed to pipes on gen4+ */
1126 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1127 reg = DSPCNTR(pipe);
1128 val = I915_READ(reg);
1129 WARN((val & DISPLAY_PLANE_ENABLE),
1130 "plane %c assertion failure, should be disabled but not\n",
1131 plane_name(pipe));
19ec1358 1132 return;
28c05794 1133 }
19ec1358 1134
b24e7179 1135 /* Need to check both planes against the pipe */
08e2a7de 1136 for_each_pipe(i) {
b24e7179
JB		 1137 reg = DSPCNTR(i);
1138 val = I915_READ(reg);
1139 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1140 DISPPLANE_SEL_PIPE_SHIFT;
1141 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1142 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1143 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1144 }
1145}
1146
19332d7a
JB		 1147static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1148 enum pipe pipe)
1149{
20674eef 1150 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1151 int reg, i;
1152 u32 val;
1153
20674eef
VS		 1154 if (IS_VALLEYVIEW(dev)) {
1155 for (i = 0; i < dev_priv->num_plane; i++) {
1156 reg = SPCNTR(pipe, i);
1157 val = I915_READ(reg);
1158 WARN((val & SP_ENABLE),
1159 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1160 sprite_name(pipe, i), pipe_name(pipe));
1161 }
1162 } else if (INTEL_INFO(dev)->gen >= 7) {
1163 reg = SPRCTL(pipe);
19332d7a 1164 val = I915_READ(reg);
20674eef 1165 WARN((val & SPRITE_ENABLE),
06da8da2 1166 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1167 plane_name(pipe), pipe_name(pipe));
1168 } else if (INTEL_INFO(dev)->gen >= 5) {
1169 reg = DVSCNTR(pipe);
19332d7a 1170 val = I915_READ(reg);
20674eef 1171 WARN((val & DVS_ENABLE),
06da8da2 1172 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1173 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1174 }
1175}
1176
92f2584a
JB		 1177static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1178{
1179 u32 val;
1180 bool enabled;
1181
9d82aa17
ED		 1182 if (HAS_PCH_LPT(dev_priv->dev)) {
1183 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1184 return;
1185 }
1186
92f2584a
JB		 1187 val = I915_READ(PCH_DREF_CONTROL);
1188 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1189 DREF_SUPERSPREAD_SOURCE_MASK));
1190 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1191}
1192
ab9412ba
DV		 1193static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1194 enum pipe pipe)
92f2584a
JB		 1195{
1196 int reg;
1197 u32 val;
1198 bool enabled;
1199
ab9412ba 1200 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1201 val = I915_READ(reg);
1202 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1203 WARN(enabled,
1204 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1205 pipe_name(pipe));
92f2584a
JB		 1206}
1207
4e634389
KP		 1208static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1209 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1210{
1211 if ((val & DP_PORT_EN) == 0)
1212 return false;
1213
1214 if (HAS_PCH_CPT(dev_priv->dev)) {
1215 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1216 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1217 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1218 return false;
1219 } else {
1220 if ((val & DP_PIPE_MASK) != (pipe << 30))
1221 return false;
1222 }
1223 return true;
1224}
1225
1519b995
KP		 1226static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1227 enum pipe pipe, u32 val)
1228{
dc0fa718 1229 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1230 return false;
1231
1232 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1233 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1234 return false;
1235 } else {
dc0fa718 1236 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1237 return false;
1238 }
1239 return true;
1240}
1241
1242static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1243 enum pipe pipe, u32 val)
1244{
1245 if ((val & LVDS_PORT_EN) == 0)
1246 return false;
1247
1248 if (HAS_PCH_CPT(dev_priv->dev)) {
1249 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1250 return false;
1251 } else {
1252 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1253 return false;
1254 }
1255 return true;
1256}
1257
1258static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1259 enum pipe pipe, u32 val)
1260{
1261 if ((val & ADPA_DAC_ENABLE) == 0)
1262 return false;
1263 if (HAS_PCH_CPT(dev_priv->dev)) {
1264 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1265 return false;
1266 } else {
1267 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1268 return false;
1269 }
1270 return true;
1271}
1272
291906f1 1273static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1274 enum pipe pipe, int reg, u32 port_sel)
291906f1 1275{
47a05eca 1276 u32 val = I915_READ(reg);
4e634389 1277 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1278 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1279 reg, pipe_name(pipe));
de9a35ab 1280
75c5da27
DV		 1281 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1282 && (val & DP_PIPEB_SELECT),
de9a35ab 1283 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1284}
1285
1286static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1287 enum pipe pipe, int reg)
1288{
47a05eca 1289 u32 val = I915_READ(reg);
b70ad586 1290 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1291 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1292 reg, pipe_name(pipe));
de9a35ab 1293
dc0fa718 1294 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1295 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1296 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1297}
1298
1299static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1300 enum pipe pipe)
1301{
1302 int reg;
1303 u32 val;
291906f1 1304
f0575e92
KP		 1305 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1306 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1307 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1308
1309 reg = PCH_ADPA;
1310 val = I915_READ(reg);
b70ad586 1311 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1312 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1313 pipe_name(pipe));
291906f1
JB		 1314
1315 reg = PCH_LVDS;
1316 val = I915_READ(reg);
b70ad586 1317 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1318 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1319 pipe_name(pipe));
291906f1 1320
e2debe91
PZ		 1321 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1322 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1323 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1324}
1325
426115cf 1326static void vlv_enable_pll(struct intel_crtc *crtc)
87442f73 1327{
426115cf
DV		 1328 struct drm_device *dev = crtc->base.dev;
1329 struct drm_i915_private *dev_priv = dev->dev_private;
1330 int reg = DPLL(crtc->pipe);
1331 u32 dpll = crtc->config.dpll_hw_state.dpll;
87442f73 1332
426115cf 1333 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1334
1335 /* No really, not for ILK+ */
1336 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1337
1338 /* PLL is protected by panel, make sure we can write it */
1339 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
426115cf 1340 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1341
426115cf
DV		 1342 I915_WRITE(reg, dpll);
1343 POSTING_READ(reg);
1344 udelay(150);
1345
1346 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1347 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1348
1349 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1350 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1351
1352 /* We do this three times for luck */
426115cf 1353 I915_WRITE(reg, dpll);
87442f73
DV		 1354 POSTING_READ(reg);
1355 udelay(150); /* wait for warmup */
426115cf 1356 I915_WRITE(reg, dpll);
87442f73
DV		 1357 POSTING_READ(reg);
1358 udelay(150); /* wait for warmup */
426115cf 1359 I915_WRITE(reg, dpll);
87442f73
DV		 1360 POSTING_READ(reg);
1361 udelay(150); /* wait for warmup */
1362}
1363
66e3d5c0 1364static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1365{
66e3d5c0
DV		 1366 struct drm_device *dev = crtc->base.dev;
1367 struct drm_i915_private *dev_priv = dev->dev_private;
1368 int reg = DPLL(crtc->pipe);
1369 u32 dpll = crtc->config.dpll_hw_state.dpll;
63d7bbe9 1370
66e3d5c0 1371 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1372
63d7bbe9 1373 /* No really, not for ILK+ */
87442f73 1374 BUG_ON(dev_priv->info->gen >= 5);
63d7bbe9
JB		 1375
1376 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1377 if (IS_MOBILE(dev) && !IS_I830(dev))
1378 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1379
66e3d5c0
DV		 1380 I915_WRITE(reg, dpll);
1381
1382 /* Wait for the clocks to stabilize. */
1383 POSTING_READ(reg);
1384 udelay(150);
1385
1386 if (INTEL_INFO(dev)->gen >= 4) {
1387 I915_WRITE(DPLL_MD(crtc->pipe),
1388 crtc->config.dpll_hw_state.dpll_md);
1389 } else {
1390 /* The pixel multiplier can only be updated once the
1391 * DPLL is enabled and the clocks are stable.
1392 *
1393 * So write it again.
1394 */
1395 I915_WRITE(reg, dpll);
1396 }
63d7bbe9
JB		 1397
1398 /* We do this three times for luck */
66e3d5c0 1399 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1400 POSTING_READ(reg);
1401 udelay(150); /* wait for warmup */
66e3d5c0 1402 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1403 POSTING_READ(reg);
1404 udelay(150); /* wait for warmup */
66e3d5c0 1405 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1406 POSTING_READ(reg);
1407 udelay(150); /* wait for warmup */
1408}
1409
1410/**
50b44a44 1411 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1412 * @dev_priv: i915 private structure
1413 * @pipe: pipe PLL to disable
1414 *
1415 * Disable the PLL for @pipe, making sure the pipe is off first.
1416 *
1417 * Note! This is for pre-ILK only.
1418 */
50b44a44 1419static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9 1420{
63d7bbe9
JB		 1421 /* Don't disable pipe A or pipe A PLLs if needed */
1422 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1423 return;
1424
1425 /* Make sure the pipe isn't still relying on us */
1426 assert_pipe_disabled(dev_priv, pipe);
1427
50b44a44
DV		 1428 I915_WRITE(DPLL(pipe), 0);
1429 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1430}
1431
89b667f8
JB		 1432void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1433{
1434 u32 port_mask;
1435
1436 if (!port)
1437 port_mask = DPLL_PORTB_READY_MASK;
1438 else
1439 port_mask = DPLL_PORTC_READY_MASK;
1440
1441 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1442 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1443 'B' + port, I915_READ(DPLL(0)));
1444}
1445
92f2584a 1446/**
e72f9fbf 1447 * ironlake_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1448 * @dev_priv: i915 private structure
1449 * @pipe: pipe PLL to enable
1450 *
1451 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1452 * drives the transcoder clock.
1453 */
e2b78267 1454static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1455{
e2b78267
DV		 1456 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1457 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1458
48da64a8 1459 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1460 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1461 if (WARN_ON(pll == NULL))
48da64a8
CW		 1462 return;
1463
1464 if (WARN_ON(pll->refcount == 0))
1465 return;
ee7b9f93 1466
46edb027
DV		 1467 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1468 pll->name, pll->active, pll->on,
e2b78267 1469 crtc->base.base.id);
92f2584a 1470
cdbd2316
DV		 1471 if (pll->active++) {
1472 WARN_ON(!pll->on);
e9d6944e 1473 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1474 return;
1475 }
f4a091c7 1476 WARN_ON(pll->on);
ee7b9f93 1477
46edb027 1478 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1479 pll->enable(dev_priv, pll);
ee7b9f93 1480 pll->on = true;
92f2584a
JB		 1481}
1482
e2b78267 1483static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1484{
e2b78267
DV		 1485 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1486 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1487
92f2584a
JB		 1488 /* PCH only available on ILK+ */
1489 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1490 if (WARN_ON(pll == NULL))
ee7b9f93 1491 return;
92f2584a 1492
48da64a8
CW		 1493 if (WARN_ON(pll->refcount == 0))
1494 return;
7a419866 1495
46edb027
DV		 1496 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1497 pll->name, pll->active, pll->on,
e2b78267 1498 crtc->base.base.id);
7a419866 1499
48da64a8 1500 if (WARN_ON(pll->active == 0)) {
e9d6944e 1501 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1502 return;
1503 }
1504
e9d6944e 1505 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1506 WARN_ON(!pll->on);
cdbd2316 1507 if (--pll->active)
7a419866 1508 return;
ee7b9f93 1509
46edb027 1510 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1511 pll->disable(dev_priv, pll);
ee7b9f93 1512 pll->on = false;
92f2584a
JB		 1513}
1514
b8a4f404
PZ		 1515static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1516 enum pipe pipe)
040484af 1517{
23670b32 1518 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1519 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1520 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1521 uint32_t reg, val, pipeconf_val;
040484af
JB		 1522
1523 /* PCH only available on ILK+ */
1524 BUG_ON(dev_priv->info->gen < 5);
1525
1526 /* Make sure PCH DPLL is enabled */
e72f9fbf 1527 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1528 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1529
1530 /* FDI must be feeding us bits for PCH ports */
1531 assert_fdi_tx_enabled(dev_priv, pipe);
1532 assert_fdi_rx_enabled(dev_priv, pipe);
1533
23670b32
DV		 1534 if (HAS_PCH_CPT(dev)) {
1535 /* Workaround: Set the timing override bit before enabling the
1536 * pch transcoder. */
1537 reg = TRANS_CHICKEN2(pipe);
1538 val = I915_READ(reg);
1539 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1540 I915_WRITE(reg, val);
59c859d6 1541 }
23670b32 1542
ab9412ba 1543 reg = PCH_TRANSCONF(pipe);
040484af 1544 val = I915_READ(reg);
5f7f726d 1545 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1546
1547 if (HAS_PCH_IBX(dev_priv->dev)) {
1548 /*
1549 * make the BPC in transcoder be consistent with
1550 * that in pipeconf reg.
1551 */
dfd07d72
DV		 1552 val &= ~PIPECONF_BPC_MASK;
1553 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1554 }
5f7f726d
PZ		 1555
1556 val &= ~TRANS_INTERLACE_MASK;
1557 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1558 if (HAS_PCH_IBX(dev_priv->dev) &&
1559 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1560 val |= TRANS_LEGACY_INTERLACED_ILK;
1561 else
1562 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1563 else
1564 val |= TRANS_PROGRESSIVE;
1565
040484af
JB		 1566 I915_WRITE(reg, val | TRANS_ENABLE);
1567 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1568 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1569}
1570
8fb033d7 1571static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1572 enum transcoder cpu_transcoder)
040484af 1573{
8fb033d7 1574 u32 val, pipeconf_val;
8fb033d7
PZ		 1575
1576 /* PCH only available on ILK+ */
1577 BUG_ON(dev_priv->info->gen < 5);
1578
8fb033d7 1579 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1580 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1581 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1582
223a6fdf
PZ		 1583 /* Workaround: set timing override bit. */
1584 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1585 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1586 I915_WRITE(_TRANSA_CHICKEN2, val);
1587
25f3ef11 1588 val = TRANS_ENABLE;
937bb610 1589 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1590
9a76b1c6
PZ		 1591 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1592 PIPECONF_INTERLACED_ILK)
a35f2679 1593 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1594 else
1595 val |= TRANS_PROGRESSIVE;
1596
ab9412ba
DV		 1597 I915_WRITE(LPT_TRANSCONF, val);
1598 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1599 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1600}
1601
b8a4f404
PZ		 1602static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1603 enum pipe pipe)
040484af 1604{
23670b32
DV		 1605 struct drm_device *dev = dev_priv->dev;
1606 uint32_t reg, val;
040484af
JB		 1607
1608 /* FDI relies on the transcoder */
1609 assert_fdi_tx_disabled(dev_priv, pipe);
1610 assert_fdi_rx_disabled(dev_priv, pipe);
1611
291906f1
JB		 1612 /* Ports must be off as well */
1613 assert_pch_ports_disabled(dev_priv, pipe);
1614
ab9412ba 1615 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1616 val = I915_READ(reg);
1617 val &= ~TRANS_ENABLE;
1618 I915_WRITE(reg, val);
1619 /* wait for PCH transcoder off, transcoder state */
1620 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1621 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1622
1623 if (!HAS_PCH_IBX(dev)) {
1624 /* Workaround: Clear the timing override chicken bit again. */
1625 reg = TRANS_CHICKEN2(pipe);
1626 val = I915_READ(reg);
1627 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1628 I915_WRITE(reg, val);
1629 }
040484af
JB		 1630}
1631
ab4d966c 1632static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1633{
8fb033d7
PZ		 1634 u32 val;
1635
ab9412ba 1636 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1637 val &= ~TRANS_ENABLE;
ab9412ba 1638 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1639 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1640 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1641 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1642
1643 /* Workaround: clear timing override bit. */
1644 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1645 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1646 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1647}
1648
b24e7179 1649/**
309cfea8 1650 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1651 * @dev_priv: i915 private structure
1652 * @pipe: pipe to enable
040484af 1653 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1654 *
1655 * Enable @pipe, making sure that various hardware specific requirements
1656 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1657 *
1658 * @pipe should be %PIPE_A or %PIPE_B.
1659 *
1660 * Will wait until the pipe is actually running (i.e. first vblank) before
1661 * returning.
1662 */
040484af 1663static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
23538ef1 1664 bool pch_port, bool dsi)
b24e7179 1665{
702e7a56
PZ		 1666 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1667 pipe);
1a240d4d 1668 enum pipe pch_transcoder;
b24e7179
JB		 1669 int reg;
1670 u32 val;
1671
58c6eaa2
DV		 1672 assert_planes_disabled(dev_priv, pipe);
1673 assert_sprites_disabled(dev_priv, pipe);
1674
681e5811 1675 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1676 pch_transcoder = TRANSCODER_A;
1677 else
1678 pch_transcoder = pipe;
1679
b24e7179
JB		 1680 /*
1681 * A pipe without a PLL won't actually be able to drive bits from
1682 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1683 * need the check.
1684 */
1685 if (!HAS_PCH_SPLIT(dev_priv->dev))
23538ef1
JN		 1686 if (dsi)
1687 assert_dsi_pll_enabled(dev_priv);
1688 else
1689 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1690 else {
1691 if (pch_port) {
1692 /* if driving the PCH, we need FDI enabled */
cc391bbb 1693 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1694 assert_fdi_tx_pll_enabled(dev_priv,
1695 (enum pipe) cpu_transcoder);
040484af
JB		 1696 }
1697 /* FIXME: assert CPU port conditions for SNB+ */
1698 }
b24e7179 1699
702e7a56 1700 reg = PIPECONF(cpu_transcoder);
b24e7179 1701 val = I915_READ(reg);
00d70b15
CW		 1702 if (val & PIPECONF_ENABLE)
1703 return;
1704
1705 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1706 intel_wait_for_vblank(dev_priv->dev, pipe);
1707}
1708
1709/**
309cfea8 1710 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1711 * @dev_priv: i915 private structure
1712 * @pipe: pipe to disable
1713 *
1714 * Disable @pipe, making sure that various hardware specific requirements
1715 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1716 *
1717 * @pipe should be %PIPE_A or %PIPE_B.
1718 *
1719 * Will wait until the pipe has shut down before returning.
1720 */
1721static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1722 enum pipe pipe)
1723{
702e7a56
PZ		 1724 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1725 pipe);
b24e7179
JB		 1726 int reg;
1727 u32 val;
1728
1729 /*
1730 * Make sure planes won't keep trying to pump pixels to us,
1731 * or we might hang the display.
1732 */
1733 assert_planes_disabled(dev_priv, pipe);
19332d7a 1734 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1735
1736 /* Don't disable pipe A or pipe A PLLs if needed */
1737 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1738 return;
1739
702e7a56 1740 reg = PIPECONF(cpu_transcoder);
b24e7179 1741 val = I915_READ(reg);
00d70b15
CW		 1742 if ((val & PIPECONF_ENABLE) == 0)
1743 return;
1744
1745 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1746 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1747}
1748
d74362c9
KP		 1749/*
1750 * Plane regs are double buffered, going from enabled->disabled needs a
1751 * trigger in order to latch. The display address reg provides this.
1752 */
6f1d69b0 1753void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1754 enum plane plane)
1755{
14f86147
DL		 1756 if (dev_priv->info->gen >= 4)
1757 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1758 else
1759 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1760}
1761
b24e7179
JB		 1762/**
1763 * intel_enable_plane - enable a display plane on a given pipe
1764 * @dev_priv: i915 private structure
1765 * @plane: plane to enable
1766 * @pipe: pipe being fed
1767 *
1768 * Enable @plane on @pipe, making sure that @pipe is running first.
1769 */
1770static void intel_enable_plane(struct drm_i915_private *dev_priv,
1771 enum plane plane, enum pipe pipe)
1772{
1773 int reg;
1774 u32 val;
1775
1776 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1777 assert_pipe_enabled(dev_priv, pipe);
1778
1779 reg = DSPCNTR(plane);
1780 val = I915_READ(reg);
00d70b15
CW		 1781 if (val & DISPLAY_PLANE_ENABLE)
1782 return;
1783
1784 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1785 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1786 intel_wait_for_vblank(dev_priv->dev, pipe);
1787}
1788
b24e7179
JB		 1789/**
1790 * intel_disable_plane - disable a display plane
1791 * @dev_priv: i915 private structure
1792 * @plane: plane to disable
1793 * @pipe: pipe consuming the data
1794 *
1795 * Disable @plane; should be an independent operation.
1796 */
1797static void intel_disable_plane(struct drm_i915_private *dev_priv,
1798 enum plane plane, enum pipe pipe)
1799{
1800 int reg;
1801 u32 val;
1802
1803 reg = DSPCNTR(plane);
1804 val = I915_READ(reg);
00d70b15
CW		 1805 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1806 return;
1807
1808 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1809 intel_flush_display_plane(dev_priv, plane);
1810 intel_wait_for_vblank(dev_priv->dev, pipe);
1811}
1812
693db184
CW		 1813static bool need_vtd_wa(struct drm_device *dev)
1814{
1815#ifdef CONFIG_INTEL_IOMMU
1816 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1817 return true;
1818#endif
1819 return false;
1820}
1821
127bd2ac 1822int
48b956c5 1823intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1824 struct drm_i915_gem_object *obj,
919926ae 1825 struct intel_ring_buffer *pipelined)
6b95a207 1826{
ce453d81 1827 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1828 u32 alignment;
1829 int ret;
1830
05394f39 1831 switch (obj->tiling_mode) {
6b95a207 1832 case I915_TILING_NONE:
534843da
CW		 1833 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1834 alignment = 128 * 1024;
a6c45cf0 1835 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1836 alignment = 4 * 1024;
1837 else
1838 alignment = 64 * 1024;
6b95a207
KH		 1839 break;
1840 case I915_TILING_X:
1841 /* pin() will align the object as required by fence */
1842 alignment = 0;
1843 break;
1844 case I915_TILING_Y:
8bb6e959
DV		 1845 /* Despite that we check this in framebuffer_init userspace can
1846 * screw us over and change the tiling after the fact. Only
1847 * pinned buffers can't change their tiling. */
1848 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1849 return -EINVAL;
1850 default:
1851 BUG();
1852 }
1853
693db184
CW		 1854 /* Note that the w/a also requires 64 PTE of padding following the
1855 * bo. We currently fill all unused PTE with the shadow page and so
1856 * we should always have valid PTE following the scanout preventing
1857 * the VT-d warning.
1858 */
1859 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1860 alignment = 256 * 1024;
1861
ce453d81 1862 dev_priv->mm.interruptible = false;
2da3b9b9 1863 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1864 if (ret)
ce453d81 1865 goto err_interruptible;
6b95a207
KH		 1866
1867 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1868 * fence, whereas 965+ only requires a fence if using
1869 * framebuffer compression. For simplicity, we always install
1870 * a fence as the cost is not that onerous.
1871 */
06d98131 1872 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1873 if (ret)
1874 goto err_unpin;
1690e1eb 1875
9a5a53b3 1876 i915_gem_object_pin_fence(obj);
6b95a207 1877
ce453d81 1878 dev_priv->mm.interruptible = true;
6b95a207 1879 return 0;
48b956c5
CW		 1880
1881err_unpin:
cc98b413 1882 i915_gem_object_unpin_from_display_plane(obj);
ce453d81
CW		 1883err_interruptible:
1884 dev_priv->mm.interruptible = true;
48b956c5 1885 return ret;
6b95a207
KH		 1886}
1887
1690e1eb
CW		 1888void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1889{
1890 i915_gem_object_unpin_fence(obj);
cc98b413 1891 i915_gem_object_unpin_from_display_plane(obj);
1690e1eb
CW		 1892}
1893
c2c75131
DV		 1894/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1895 * is assumed to be a power-of-two. */
bc752862
CW		 1896unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1897 unsigned int tiling_mode,
1898 unsigned int cpp,
1899 unsigned int pitch)
c2c75131 1900{
bc752862
CW		 1901 if (tiling_mode != I915_TILING_NONE) {
1902 unsigned int tile_rows, tiles;
c2c75131 1903
bc752862
CW		 1904 tile_rows = *y / 8;
1905 *y %= 8;
c2c75131 1906
bc752862
CW		 1907 tiles = *x / (512/cpp);
1908 *x %= 512/cpp;
1909
1910 return tile_rows * pitch * 8 + tiles * 4096;
1911 } else {
1912 unsigned int offset;
1913
1914 offset = *y * pitch + *x * cpp;
1915 *y = 0;
1916 *x = (offset & 4095) / cpp;
1917 return offset & -4096;
1918 }
c2c75131
DV		 1919}
1920
17638cd6
JB		 1921static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1922 int x, int y)
81255565
JB		 1923{
1924 struct drm_device *dev = crtc->dev;
1925 struct drm_i915_private *dev_priv = dev->dev_private;
1926 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1927 struct intel_framebuffer *intel_fb;
05394f39 1928 struct drm_i915_gem_object *obj;
81255565 1929 int plane = intel_crtc->plane;
e506a0c6 1930 unsigned long linear_offset;
81255565 1931 u32 dspcntr;
5eddb70b 1932 u32 reg;
81255565
JB		 1933
1934 switch (plane) {
1935 case 0:
1936 case 1:
1937 break;
1938 default:
84f44ce7 1939 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1940 return -EINVAL;
1941 }
1942
1943 intel_fb = to_intel_framebuffer(fb);
1944 obj = intel_fb->obj;
81255565 1945
5eddb70b
CW		 1946 reg = DSPCNTR(plane);
1947 dspcntr = I915_READ(reg);
81255565
JB		 1948 /* Mask out pixel format bits in case we change it */
1949 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1950 switch (fb->pixel_format) {
1951 case DRM_FORMAT_C8:
81255565
JB		 1952 dspcntr |= DISPPLANE_8BPP;
1953 break;
57779d06
VS		 1954 case DRM_FORMAT_XRGB1555:
1955 case DRM_FORMAT_ARGB1555:
1956 dspcntr |= DISPPLANE_BGRX555;
81255565 1957 break;
57779d06
VS		 1958 case DRM_FORMAT_RGB565:
1959 dspcntr |= DISPPLANE_BGRX565;
1960 break;
1961 case DRM_FORMAT_XRGB8888:
1962 case DRM_FORMAT_ARGB8888:
1963 dspcntr |= DISPPLANE_BGRX888;
1964 break;
1965 case DRM_FORMAT_XBGR8888:
1966 case DRM_FORMAT_ABGR8888:
1967 dspcntr |= DISPPLANE_RGBX888;
1968 break;
1969 case DRM_FORMAT_XRGB2101010:
1970 case DRM_FORMAT_ARGB2101010:
1971 dspcntr |= DISPPLANE_BGRX101010;
1972 break;
1973 case DRM_FORMAT_XBGR2101010:
1974 case DRM_FORMAT_ABGR2101010:
1975 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 1976 break;
1977 default:
baba133a 1978 BUG();
81255565 1979 }
57779d06 1980
a6c45cf0 1981 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1982 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1983 dspcntr |= DISPPLANE_TILED;
1984 else
1985 dspcntr &= ~DISPPLANE_TILED;
1986 }
1987
de1aa629
VS		 1988 if (IS_G4X(dev))
1989 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1990
5eddb70b 1991 I915_WRITE(reg, dspcntr);
81255565 1992
e506a0c6 1993 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 1994
c2c75131
DV		 1995 if (INTEL_INFO(dev)->gen >= 4) {
1996 intel_crtc->dspaddr_offset =
bc752862
CW		 1997 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1998 fb->bits_per_pixel / 8,
1999 fb->pitches[0]);
c2c75131
DV		 2000 linear_offset -= intel_crtc->dspaddr_offset;
2001 } else {
e506a0c6 2002 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2003 }
e506a0c6 2004
f343c5f6
BW		 2005 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2006 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2007 fb->pitches[0]);
01f2c773 2008 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2009 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131 2010 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2011 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2012 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2013 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2014 } else
f343c5f6 2015 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2016 POSTING_READ(reg);
81255565 2017
17638cd6
JB		 2018 return 0;
2019}
2020
2021static int ironlake_update_plane(struct drm_crtc *crtc,
2022 struct drm_framebuffer *fb, int x, int y)
2023{
2024 struct drm_device *dev = crtc->dev;
2025 struct drm_i915_private *dev_priv = dev->dev_private;
2026 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2027 struct intel_framebuffer *intel_fb;
2028 struct drm_i915_gem_object *obj;
2029 int plane = intel_crtc->plane;
e506a0c6 2030 unsigned long linear_offset;
17638cd6
JB		 2031 u32 dspcntr;
2032 u32 reg;
2033
2034 switch (plane) {
2035 case 0:
2036 case 1:
27f8227b 2037 case 2:
17638cd6
JB		 2038 break;
2039 default:
84f44ce7 2040 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2041 return -EINVAL;
2042 }
2043
2044 intel_fb = to_intel_framebuffer(fb);
2045 obj = intel_fb->obj;
2046
2047 reg = DSPCNTR(plane);
2048 dspcntr = I915_READ(reg);
2049 /* Mask out pixel format bits in case we change it */
2050 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2051 switch (fb->pixel_format) {
2052 case DRM_FORMAT_C8:
17638cd6
JB		 2053 dspcntr |= DISPPLANE_8BPP;
2054 break;
57779d06
VS		 2055 case DRM_FORMAT_RGB565:
2056 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2057 break;
57779d06
VS		 2058 case DRM_FORMAT_XRGB8888:
2059 case DRM_FORMAT_ARGB8888:
2060 dspcntr |= DISPPLANE_BGRX888;
2061 break;
2062 case DRM_FORMAT_XBGR8888:
2063 case DRM_FORMAT_ABGR8888:
2064 dspcntr |= DISPPLANE_RGBX888;
2065 break;
2066 case DRM_FORMAT_XRGB2101010:
2067 case DRM_FORMAT_ARGB2101010:
2068 dspcntr |= DISPPLANE_BGRX101010;
2069 break;
2070 case DRM_FORMAT_XBGR2101010:
2071 case DRM_FORMAT_ABGR2101010:
2072 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2073 break;
2074 default:
baba133a 2075 BUG();
17638cd6
JB		 2076 }
2077
2078 if (obj->tiling_mode != I915_TILING_NONE)
2079 dspcntr |= DISPPLANE_TILED;
2080 else
2081 dspcntr &= ~DISPPLANE_TILED;
2082
1f5d76db
PZ		 2083 if (IS_HASWELL(dev))
2084 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2085 else
2086 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6
JB		 2087
2088 I915_WRITE(reg, dspcntr);
2089
e506a0c6 2090 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2091 intel_crtc->dspaddr_offset =
bc752862
CW		 2092 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2093 fb->bits_per_pixel / 8,
2094 fb->pitches[0]);
c2c75131 2095 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2096
f343c5f6
BW		 2097 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2098 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2099 fb->pitches[0]);
01f2c773 2100 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131 2101 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2102 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2103 if (IS_HASWELL(dev)) {
2104 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2105 } else {
2106 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2107 I915_WRITE(DSPLINOFF(plane), linear_offset);
2108 }
17638cd6
JB		 2109 POSTING_READ(reg);
2110
2111 return 0;
2112}
2113
2114/* Assume fb object is pinned & idle & fenced and just update base pointers */
2115static int
2116intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2117 int x, int y, enum mode_set_atomic state)
2118{
2119 struct drm_device *dev = crtc->dev;
2120 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2121
6b8e6ed0
CW		 2122 if (dev_priv->display.disable_fbc)
2123 dev_priv->display.disable_fbc(dev);
3dec0095 2124 intel_increase_pllclock(crtc);
81255565 2125
6b8e6ed0 2126 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2127}
2128
96a02917
VS		 2129void intel_display_handle_reset(struct drm_device *dev)
2130{
2131 struct drm_i915_private *dev_priv = dev->dev_private;
2132 struct drm_crtc *crtc;
2133
2134 /*
2135 * Flips in the rings have been nuked by the reset,
2136 * so complete all pending flips so that user space
2137 * will get its events and not get stuck.
2138 *
2139 * Also update the base address of all primary
2140 * planes to the the last fb to make sure we're
2141 * showing the correct fb after a reset.
2142 *
2143 * Need to make two loops over the crtcs so that we
2144 * don't try to grab a crtc mutex before the
2145 * pending_flip_queue really got woken up.
2146 */
2147
2148 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2149 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2150 enum plane plane = intel_crtc->plane;
2151
2152 intel_prepare_page_flip(dev, plane);
2153 intel_finish_page_flip_plane(dev, plane);
2154 }
2155
2156 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2157 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2158
2159 mutex_lock(&crtc->mutex);
2160 if (intel_crtc->active)
2161 dev_priv->display.update_plane(crtc, crtc->fb,
2162 crtc->x, crtc->y);
2163 mutex_unlock(&crtc->mutex);
2164 }
2165}
2166
14667a4b
CW		 2167static int
2168intel_finish_fb(struct drm_framebuffer *old_fb)
2169{
2170 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2171 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2172 bool was_interruptible = dev_priv->mm.interruptible;
2173 int ret;
2174
14667a4b
CW		 2175 /* Big Hammer, we also need to ensure that any pending
2176 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2177 * current scanout is retired before unpinning the old
2178 * framebuffer.
2179 *
2180 * This should only fail upon a hung GPU, in which case we
2181 * can safely continue.
2182 */
2183 dev_priv->mm.interruptible = false;
2184 ret = i915_gem_object_finish_gpu(obj);
2185 dev_priv->mm.interruptible = was_interruptible;
2186
2187 return ret;
2188}
2189
198598d0
VS		 2190static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2191{
2192 struct drm_device *dev = crtc->dev;
2193 struct drm_i915_master_private *master_priv;
2194 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2195
2196 if (!dev->primary->master)
2197 return;
2198
2199 master_priv = dev->primary->master->driver_priv;
2200 if (!master_priv->sarea_priv)
2201 return;
2202
2203 switch (intel_crtc->pipe) {
2204 case 0:
2205 master_priv->sarea_priv->pipeA_x = x;
2206 master_priv->sarea_priv->pipeA_y = y;
2207 break;
2208 case 1:
2209 master_priv->sarea_priv->pipeB_x = x;
2210 master_priv->sarea_priv->pipeB_y = y;
2211 break;
2212 default:
2213 break;
2214 }
2215}
2216
5c3b82e2 2217static int
3c4fdcfb 2218intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2219 struct drm_framebuffer *fb)
79e53945
JB		 2220{
2221 struct drm_device *dev = crtc->dev;
6b8e6ed0 2222 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2223 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2224 struct drm_framebuffer *old_fb;
5c3b82e2 2225 int ret;
79e53945
JB		 2226
2227 /* no fb bound */
94352cf9 2228 if (!fb) {
a5071c2f 2229 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2230 return 0;
2231 }
2232
7eb552ae 2233 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2234 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2235 plane_name(intel_crtc->plane),
2236 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2237 return -EINVAL;
79e53945
JB		 2238 }
2239
5c3b82e2 2240 mutex_lock(&dev->struct_mutex);
265db958 2241 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2242 to_intel_framebuffer(fb)->obj,
919926ae 2243 NULL);
5c3b82e2
CW		 2244 if (ret != 0) {
2245 mutex_unlock(&dev->struct_mutex);
a5071c2f 2246 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2247 return ret;
2248 }
79e53945 2249
4d6a3e63
JB		 2250 /* Update pipe size and adjust fitter if needed */
2251 if (i915_fastboot) {
2252 I915_WRITE(PIPESRC(intel_crtc->pipe),
2253 ((crtc->mode.hdisplay - 1) << 16) |
2254 (crtc->mode.vdisplay - 1));
2255 if (!intel_crtc->config.pch_pfit.size &&
2256 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2257 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2258 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2259 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2260 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2261 }
2262 }
2263
94352cf9 2264 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2265 if (ret) {
94352cf9 2266 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2267 mutex_unlock(&dev->struct_mutex);
a5071c2f 2268 DRM_ERROR("failed to update base address\n");
4e6cfefc 2269 return ret;
79e53945 2270 }
3c4fdcfb 2271
94352cf9
DV		 2272 old_fb = crtc->fb;
2273 crtc->fb = fb;
6c4c86f5
DV		 2274 crtc->x = x;
2275 crtc->y = y;
94352cf9 2276
b7f1de28 2277 if (old_fb) {
d7697eea
DV		 2278 if (intel_crtc->active && old_fb != fb)
2279 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2280 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2281 }
652c393a 2282
6b8e6ed0 2283 intel_update_fbc(dev);
4906557e 2284 intel_edp_psr_update(dev);
5c3b82e2 2285 mutex_unlock(&dev->struct_mutex);
79e53945 2286
198598d0 2287 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2288
2289 return 0;
79e53945
JB		 2290}
2291
5e84e1a4
ZW		 2292static void intel_fdi_normal_train(struct drm_crtc *crtc)
2293{
2294 struct drm_device *dev = crtc->dev;
2295 struct drm_i915_private *dev_priv = dev->dev_private;
2296 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2297 int pipe = intel_crtc->pipe;
2298 u32 reg, temp;
2299
2300 /* enable normal train */
2301 reg = FDI_TX_CTL(pipe);
2302 temp = I915_READ(reg);
61e499bf 2303 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2304 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2305 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2306 } else {
2307 temp &= ~FDI_LINK_TRAIN_NONE;
2308 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2309 }
5e84e1a4
ZW		 2310 I915_WRITE(reg, temp);
2311
2312 reg = FDI_RX_CTL(pipe);
2313 temp = I915_READ(reg);
2314 if (HAS_PCH_CPT(dev)) {
2315 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2316 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2317 } else {
2318 temp &= ~FDI_LINK_TRAIN_NONE;
2319 temp |= FDI_LINK_TRAIN_NONE;
2320 }
2321 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2322
2323 /* wait one idle pattern time */
2324 POSTING_READ(reg);
2325 udelay(1000);
357555c0
JB		 2326
2327 /* IVB wants error correction enabled */
2328 if (IS_IVYBRIDGE(dev))
2329 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2330 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2331}
2332
1e833f40
DV		 2333static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2334{
2335 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2336}
2337
01a415fd
DV		 2338static void ivb_modeset_global_resources(struct drm_device *dev)
2339{
2340 struct drm_i915_private *dev_priv = dev->dev_private;
2341 struct intel_crtc *pipe_B_crtc =
2342 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2343 struct intel_crtc *pipe_C_crtc =
2344 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2345 uint32_t temp;
2346
1e833f40
DV		 2347 /*
2348 * When everything is off disable fdi C so that we could enable fdi B
2349 * with all lanes. Note that we don't care about enabled pipes without
2350 * an enabled pch encoder.
2351 */
2352 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2353 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2354 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2355 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2356
2357 temp = I915_READ(SOUTH_CHICKEN1);
2358 temp &= ~FDI_BC_BIFURCATION_SELECT;
2359 DRM_DEBUG_KMS("disabling fdi C rx\n");
2360 I915_WRITE(SOUTH_CHICKEN1, temp);
2361 }
2362}
2363
8db9d77b
ZW		 2364/* The FDI link training functions for ILK/Ibexpeak. */
2365static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2366{
2367 struct drm_device *dev = crtc->dev;
2368 struct drm_i915_private *dev_priv = dev->dev_private;
2369 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2370 int pipe = intel_crtc->pipe;
0fc932b8 2371 int plane = intel_crtc->plane;
5eddb70b 2372 u32 reg, temp, tries;
8db9d77b 2373
0fc932b8
JB		 2374 /* FDI needs bits from pipe & plane first */
2375 assert_pipe_enabled(dev_priv, pipe);
2376 assert_plane_enabled(dev_priv, plane);
2377
e1a44743
AJ		 2378 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2379 for train result */
5eddb70b
CW		 2380 reg = FDI_RX_IMR(pipe);
2381 temp = I915_READ(reg);
e1a44743
AJ		 2382 temp &= ~FDI_RX_SYMBOL_LOCK;
2383 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2384 I915_WRITE(reg, temp);
2385 I915_READ(reg);
e1a44743
AJ		 2386 udelay(150);
2387
8db9d77b 2388 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2389 reg = FDI_TX_CTL(pipe);
2390 temp = I915_READ(reg);
627eb5a3
DV		 2391 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2392 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2393 temp &= ~FDI_LINK_TRAIN_NONE;
2394 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2395 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2396
5eddb70b
CW		 2397 reg = FDI_RX_CTL(pipe);
2398 temp = I915_READ(reg);
8db9d77b
ZW		 2399 temp &= ~FDI_LINK_TRAIN_NONE;
2400 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2401 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2402
2403 POSTING_READ(reg);
8db9d77b
ZW		 2404 udelay(150);
2405
5b2adf89 2406 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2407 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2408 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2409 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2410
5eddb70b 2411 reg = FDI_RX_IIR(pipe);
e1a44743 2412 for (tries = 0; tries < 5; tries++) {
5eddb70b 2413 temp = I915_READ(reg);
8db9d77b
ZW		 2414 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2415
2416 if ((temp & FDI_RX_BIT_LOCK)) {
2417 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2418 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2419 break;
2420 }
8db9d77b 2421 }
e1a44743 2422 if (tries == 5)
5eddb70b 2423 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2424
2425 /* Train 2 */
5eddb70b
CW		 2426 reg = FDI_TX_CTL(pipe);
2427 temp = I915_READ(reg);
8db9d77b
ZW		 2428 temp &= ~FDI_LINK_TRAIN_NONE;
2429 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2430 I915_WRITE(reg, temp);
8db9d77b 2431
5eddb70b
CW		 2432 reg = FDI_RX_CTL(pipe);
2433 temp = I915_READ(reg);
8db9d77b
ZW		 2434 temp &= ~FDI_LINK_TRAIN_NONE;
2435 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2436 I915_WRITE(reg, temp);
8db9d77b 2437
5eddb70b
CW		 2438 POSTING_READ(reg);
2439 udelay(150);
8db9d77b 2440
5eddb70b 2441 reg = FDI_RX_IIR(pipe);
e1a44743 2442 for (tries = 0; tries < 5; tries++) {
5eddb70b 2443 temp = I915_READ(reg);
8db9d77b
ZW		 2444 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2445
2446 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2447 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2448 DRM_DEBUG_KMS("FDI train 2 done.\n");
2449 break;
2450 }
8db9d77b 2451 }
e1a44743 2452 if (tries == 5)
5eddb70b 2453 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2454
2455 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2456
8db9d77b
ZW		 2457}
2458
0206e353 2459static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2460 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2461 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2462 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2463 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2464};
2465
2466/* The FDI link training functions for SNB/Cougarpoint. */
2467static void gen6_fdi_link_train(struct drm_crtc *crtc)
2468{
2469 struct drm_device *dev = crtc->dev;
2470 struct drm_i915_private *dev_priv = dev->dev_private;
2471 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2472 int pipe = intel_crtc->pipe;
fa37d39e 2473 u32 reg, temp, i, retry;
8db9d77b 2474
e1a44743
AJ		 2475 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2476 for train result */
5eddb70b
CW		 2477 reg = FDI_RX_IMR(pipe);
2478 temp = I915_READ(reg);
e1a44743
AJ		 2479 temp &= ~FDI_RX_SYMBOL_LOCK;
2480 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2481 I915_WRITE(reg, temp);
2482
2483 POSTING_READ(reg);
e1a44743
AJ		 2484 udelay(150);
2485
8db9d77b 2486 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2487 reg = FDI_TX_CTL(pipe);
2488 temp = I915_READ(reg);
627eb5a3
DV		 2489 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2490 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2491 temp &= ~FDI_LINK_TRAIN_NONE;
2492 temp |= FDI_LINK_TRAIN_PATTERN_1;
2493 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2494 /* SNB-B */
2495 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2496 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2497
d74cf324
DV		 2498 I915_WRITE(FDI_RX_MISC(pipe),
2499 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2500
5eddb70b
CW		 2501 reg = FDI_RX_CTL(pipe);
2502 temp = I915_READ(reg);
8db9d77b
ZW		 2503 if (HAS_PCH_CPT(dev)) {
2504 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2505 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2506 } else {
2507 temp &= ~FDI_LINK_TRAIN_NONE;
2508 temp |= FDI_LINK_TRAIN_PATTERN_1;
2509 }
5eddb70b
CW		 2510 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2511
2512 POSTING_READ(reg);
8db9d77b
ZW		 2513 udelay(150);
2514
0206e353 2515 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2516 reg = FDI_TX_CTL(pipe);
2517 temp = I915_READ(reg);
8db9d77b
ZW		 2518 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2519 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2520 I915_WRITE(reg, temp);
2521
2522 POSTING_READ(reg);
8db9d77b
ZW		 2523 udelay(500);
2524
fa37d39e
SP		 2525 for (retry = 0; retry < 5; retry++) {
2526 reg = FDI_RX_IIR(pipe);
2527 temp = I915_READ(reg);
2528 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2529 if (temp & FDI_RX_BIT_LOCK) {
2530 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2531 DRM_DEBUG_KMS("FDI train 1 done.\n");
2532 break;
2533 }
2534 udelay(50);
8db9d77b 2535 }
fa37d39e
SP		 2536 if (retry < 5)
2537 break;
8db9d77b
ZW		 2538 }
2539 if (i == 4)
5eddb70b 2540 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2541
2542 /* Train 2 */
5eddb70b
CW		 2543 reg = FDI_TX_CTL(pipe);
2544 temp = I915_READ(reg);
8db9d77b
ZW		 2545 temp &= ~FDI_LINK_TRAIN_NONE;
2546 temp |= FDI_LINK_TRAIN_PATTERN_2;
2547 if (IS_GEN6(dev)) {
2548 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2549 /* SNB-B */
2550 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2551 }
5eddb70b 2552 I915_WRITE(reg, temp);
8db9d77b 2553
5eddb70b
CW		 2554 reg = FDI_RX_CTL(pipe);
2555 temp = I915_READ(reg);
8db9d77b
ZW		 2556 if (HAS_PCH_CPT(dev)) {
2557 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2558 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2559 } else {
2560 temp &= ~FDI_LINK_TRAIN_NONE;
2561 temp |= FDI_LINK_TRAIN_PATTERN_2;
2562 }
5eddb70b
CW		 2563 I915_WRITE(reg, temp);
2564
2565 POSTING_READ(reg);
8db9d77b
ZW		 2566 udelay(150);
2567
0206e353 2568 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2569 reg = FDI_TX_CTL(pipe);
2570 temp = I915_READ(reg);
8db9d77b
ZW		 2571 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2572 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2573 I915_WRITE(reg, temp);
2574
2575 POSTING_READ(reg);
8db9d77b
ZW		 2576 udelay(500);
2577
fa37d39e
SP		 2578 for (retry = 0; retry < 5; retry++) {
2579 reg = FDI_RX_IIR(pipe);
2580 temp = I915_READ(reg);
2581 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2582 if (temp & FDI_RX_SYMBOL_LOCK) {
2583 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2584 DRM_DEBUG_KMS("FDI train 2 done.\n");
2585 break;
2586 }
2587 udelay(50);
8db9d77b 2588 }
fa37d39e
SP		 2589 if (retry < 5)
2590 break;
8db9d77b
ZW		 2591 }
2592 if (i == 4)
5eddb70b 2593 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2594
2595 DRM_DEBUG_KMS("FDI train done.\n");
2596}
2597
357555c0
JB		 2598/* Manual link training for Ivy Bridge A0 parts */
2599static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2600{
2601 struct drm_device *dev = crtc->dev;
2602 struct drm_i915_private *dev_priv = dev->dev_private;
2603 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2604 int pipe = intel_crtc->pipe;
139ccd3f 2605 u32 reg, temp, i, j;
357555c0
JB		 2606
2607 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2608 for train result */
2609 reg = FDI_RX_IMR(pipe);
2610 temp = I915_READ(reg);
2611 temp &= ~FDI_RX_SYMBOL_LOCK;
2612 temp &= ~FDI_RX_BIT_LOCK;
2613 I915_WRITE(reg, temp);
2614
2615 POSTING_READ(reg);
2616 udelay(150);
2617
01a415fd
DV		 2618 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2619 I915_READ(FDI_RX_IIR(pipe)));
2620
139ccd3f
JB		 2621 /* Try each vswing and preemphasis setting twice before moving on */
2622 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2623 /* disable first in case we need to retry */
2624 reg = FDI_TX_CTL(pipe);
2625 temp = I915_READ(reg);
2626 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2627 temp &= ~FDI_TX_ENABLE;
2628 I915_WRITE(reg, temp);
357555c0 2629
139ccd3f
JB		 2630 reg = FDI_RX_CTL(pipe);
2631 temp = I915_READ(reg);
2632 temp &= ~FDI_LINK_TRAIN_AUTO;
2633 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2634 temp &= ~FDI_RX_ENABLE;
2635 I915_WRITE(reg, temp);
357555c0 2636
139ccd3f 2637 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 2638 reg = FDI_TX_CTL(pipe);
2639 temp = I915_READ(reg);
139ccd3f
JB		 2640 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2641 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2642 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 2643 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 2644 temp |= snb_b_fdi_train_param[j/2];
2645 temp |= FDI_COMPOSITE_SYNC;
2646 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 2647
139ccd3f
JB		 2648 I915_WRITE(FDI_RX_MISC(pipe),
2649 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 2650
139ccd3f 2651 reg = FDI_RX_CTL(pipe);
357555c0 2652 temp = I915_READ(reg);
139ccd3f
JB		 2653 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2654 temp |= FDI_COMPOSITE_SYNC;
2655 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 2656
139ccd3f
JB		 2657 POSTING_READ(reg);
2658 udelay(1); /* should be 0.5us */
357555c0 2659
139ccd3f
JB		 2660 for (i = 0; i < 4; i++) {
2661 reg = FDI_RX_IIR(pipe);
2662 temp = I915_READ(reg);
2663 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2664
139ccd3f
JB		 2665 if (temp & FDI_RX_BIT_LOCK ||
2666 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2667 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2668 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2669 i);
2670 break;
2671 }
2672 udelay(1); /* should be 0.5us */
2673 }
2674 if (i == 4) {
2675 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2676 continue;
2677 }
357555c0 2678
139ccd3f 2679 /* Train 2 */
357555c0
JB		 2680 reg = FDI_TX_CTL(pipe);
2681 temp = I915_READ(reg);
139ccd3f
JB		 2682 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2683 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2684 I915_WRITE(reg, temp);
2685
2686 reg = FDI_RX_CTL(pipe);
2687 temp = I915_READ(reg);
2688 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2689 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 2690 I915_WRITE(reg, temp);
2691
2692 POSTING_READ(reg);
139ccd3f 2693 udelay(2); /* should be 1.5us */
357555c0 2694
139ccd3f
JB		 2695 for (i = 0; i < 4; i++) {
2696 reg = FDI_RX_IIR(pipe);
2697 temp = I915_READ(reg);
2698 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2699
139ccd3f
JB		 2700 if (temp & FDI_RX_SYMBOL_LOCK ||
2701 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2702 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2703 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2704 i);
2705 goto train_done;
2706 }
2707 udelay(2); /* should be 1.5us */
357555c0 2708 }
139ccd3f
JB		 2709 if (i == 4)
2710 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 2711 }
357555c0 2712
139ccd3f 2713train_done:
357555c0
JB		 2714 DRM_DEBUG_KMS("FDI train done.\n");
2715}
2716
88cefb6c 2717static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2718{
88cefb6c 2719 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2720 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2721 int pipe = intel_crtc->pipe;
5eddb70b 2722 u32 reg, temp;
79e53945 2723
c64e311e 2724
c98e9dcf 2725 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2726 reg = FDI_RX_CTL(pipe);
2727 temp = I915_READ(reg);
627eb5a3
DV		 2728 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2729 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2730 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2731 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2732
2733 POSTING_READ(reg);
c98e9dcf
JB		 2734 udelay(200);
2735
2736 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2737 temp = I915_READ(reg);
2738 I915_WRITE(reg, temp | FDI_PCDCLK);
2739
2740 POSTING_READ(reg);
c98e9dcf
JB		 2741 udelay(200);
2742
20749730
PZ		 2743 /* Enable CPU FDI TX PLL, always on for Ironlake */
2744 reg = FDI_TX_CTL(pipe);
2745 temp = I915_READ(reg);
2746 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2747 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2748
20749730
PZ		 2749 POSTING_READ(reg);
2750 udelay(100);
6be4a607 2751 }
0e23b99d
JB		 2752}
2753
88cefb6c
DV		 2754static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2755{
2756 struct drm_device *dev = intel_crtc->base.dev;
2757 struct drm_i915_private *dev_priv = dev->dev_private;
2758 int pipe = intel_crtc->pipe;
2759 u32 reg, temp;
2760
2761 /* Switch from PCDclk to Rawclk */
2762 reg = FDI_RX_CTL(pipe);
2763 temp = I915_READ(reg);
2764 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2765
2766 /* Disable CPU FDI TX PLL */
2767 reg = FDI_TX_CTL(pipe);
2768 temp = I915_READ(reg);
2769 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2770
2771 POSTING_READ(reg);
2772 udelay(100);
2773
2774 reg = FDI_RX_CTL(pipe);
2775 temp = I915_READ(reg);
2776 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2777
2778 /* Wait for the clocks to turn off. */
2779 POSTING_READ(reg);
2780 udelay(100);
2781}
2782
0fc932b8
JB		 2783static void ironlake_fdi_disable(struct drm_crtc *crtc)
2784{
2785 struct drm_device *dev = crtc->dev;
2786 struct drm_i915_private *dev_priv = dev->dev_private;
2787 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2788 int pipe = intel_crtc->pipe;
2789 u32 reg, temp;
2790
2791 /* disable CPU FDI tx and PCH FDI rx */
2792 reg = FDI_TX_CTL(pipe);
2793 temp = I915_READ(reg);
2794 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2795 POSTING_READ(reg);
2796
2797 reg = FDI_RX_CTL(pipe);
2798 temp = I915_READ(reg);
2799 temp &= ~(0x7 << 16);
dfd07d72 2800 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2801 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2802
2803 POSTING_READ(reg);
2804 udelay(100);
2805
2806 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2807 if (HAS_PCH_IBX(dev)) {
2808 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2809 }
0fc932b8
JB		 2810
2811 /* still set train pattern 1 */
2812 reg = FDI_TX_CTL(pipe);
2813 temp = I915_READ(reg);
2814 temp &= ~FDI_LINK_TRAIN_NONE;
2815 temp |= FDI_LINK_TRAIN_PATTERN_1;
2816 I915_WRITE(reg, temp);
2817
2818 reg = FDI_RX_CTL(pipe);
2819 temp = I915_READ(reg);
2820 if (HAS_PCH_CPT(dev)) {
2821 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2822 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2823 } else {
2824 temp &= ~FDI_LINK_TRAIN_NONE;
2825 temp |= FDI_LINK_TRAIN_PATTERN_1;
2826 }
2827 /* BPC in FDI rx is consistent with that in PIPECONF */
2828 temp &= ~(0x07 << 16);
dfd07d72 2829 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2830 I915_WRITE(reg, temp);
2831
2832 POSTING_READ(reg);
2833 udelay(100);
2834}
2835
5bb61643
CW		 2836static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2837{
2838 struct drm_device *dev = crtc->dev;
2839 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2840 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2841 unsigned long flags;
2842 bool pending;
2843
10d83730
VS		 2844 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2845 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2846 return false;
2847
2848 spin_lock_irqsave(&dev->event_lock, flags);
2849 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2850 spin_unlock_irqrestore(&dev->event_lock, flags);
2851
2852 return pending;
2853}
2854
e6c3a2a6
CW		 2855static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2856{
0f91128d 2857 struct drm_device *dev = crtc->dev;
5bb61643 2858 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2859
2860 if (crtc->fb == NULL)
2861 return;
2862
2c10d571
DV		 2863 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2864
5bb61643
CW		 2865 wait_event(dev_priv->pending_flip_queue,
2866 !intel_crtc_has_pending_flip(crtc));
2867
0f91128d
CW		 2868 mutex_lock(&dev->struct_mutex);
2869 intel_finish_fb(crtc->fb);
2870 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2871}
2872
e615efe4
ED		 2873/* Program iCLKIP clock to the desired frequency */
2874static void lpt_program_iclkip(struct drm_crtc *crtc)
2875{
2876 struct drm_device *dev = crtc->dev;
2877 struct drm_i915_private *dev_priv = dev->dev_private;
2878 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2879 u32 temp;
2880
09153000
DV		 2881 mutex_lock(&dev_priv->dpio_lock);
2882
e615efe4
ED		 2883 /* It is necessary to ungate the pixclk gate prior to programming
2884 * the divisors, and gate it back when it is done.
2885 */
2886 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2887
2888 /* Disable SSCCTL */
2889 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2890 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2891 SBI_SSCCTL_DISABLE,
2892 SBI_ICLK);
e615efe4
ED		 2893
2894 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2895 if (crtc->mode.clock == 20000) {
2896 auxdiv = 1;
2897 divsel = 0x41;
2898 phaseinc = 0x20;
2899 } else {
2900 /* The iCLK virtual clock root frequency is in MHz,
2901 * but the crtc->mode.clock in in KHz. To get the divisors,
2902 * it is necessary to divide one by another, so we
2903 * convert the virtual clock precision to KHz here for higher
2904 * precision.
2905 */
2906 u32 iclk_virtual_root_freq = 172800 * 1000;
2907 u32 iclk_pi_range = 64;
2908 u32 desired_divisor, msb_divisor_value, pi_value;
2909
2910 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2911 msb_divisor_value = desired_divisor / iclk_pi_range;
2912 pi_value = desired_divisor % iclk_pi_range;
2913
2914 auxdiv = 0;
2915 divsel = msb_divisor_value - 2;
2916 phaseinc = pi_value;
2917 }
2918
2919 /* This should not happen with any sane values */
2920 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2921 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2922 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2923 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2924
2925 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2926 crtc->mode.clock,
2927 auxdiv,
2928 divsel,
2929 phasedir,
2930 phaseinc);
2931
2932 /* Program SSCDIVINTPHASE6 */
988d6ee8 2933 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2934 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2935 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2936 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2937 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2938 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2939 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2940 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2941
2942 /* Program SSCAUXDIV */
988d6ee8 2943 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2944 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2945 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2946 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2947
2948 /* Enable modulator and associated divider */
988d6ee8 2949 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2950 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2951 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2952
2953 /* Wait for initialization time */
2954 udelay(24);
2955
2956 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2957
2958 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2959}
2960
275f01b2
DV		 2961static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2962 enum pipe pch_transcoder)
2963{
2964 struct drm_device *dev = crtc->base.dev;
2965 struct drm_i915_private *dev_priv = dev->dev_private;
2966 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2967
2968 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2969 I915_READ(HTOTAL(cpu_transcoder)));
2970 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2971 I915_READ(HBLANK(cpu_transcoder)));
2972 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2973 I915_READ(HSYNC(cpu_transcoder)));
2974
2975 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2976 I915_READ(VTOTAL(cpu_transcoder)));
2977 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2978 I915_READ(VBLANK(cpu_transcoder)));
2979 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2980 I915_READ(VSYNC(cpu_transcoder)));
2981 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2982 I915_READ(VSYNCSHIFT(cpu_transcoder)));
2983}
2984
f67a559d
JB		 2985/*
2986 * Enable PCH resources required for PCH ports:
2987 * - PCH PLLs
2988 * - FDI training & RX/TX
2989 * - update transcoder timings
2990 * - DP transcoding bits
2991 * - transcoder
2992 */
2993static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2994{
2995 struct drm_device *dev = crtc->dev;
2996 struct drm_i915_private *dev_priv = dev->dev_private;
2997 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2998 int pipe = intel_crtc->pipe;
ee7b9f93 2999 u32 reg, temp;
2c07245f 3000
ab9412ba 3001 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 3002
cd986abb
DV		 3003 /* Write the TU size bits before fdi link training, so that error
3004 * detection works. */
3005 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3006 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3007
c98e9dcf 3008 /* For PCH output, training FDI link */
674cf967 3009 dev_priv->display.fdi_link_train(crtc);
2c07245f 3010
3ad8a208
DV		 3011 /* We need to program the right clock selection before writing the pixel
3012 * mutliplier into the DPLL. */
303b81e0 3013 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3014 u32 sel;
4b645f14 3015
c98e9dcf 3016 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 3017 temp |= TRANS_DPLL_ENABLE(pipe);
3018 sel = TRANS_DPLLB_SEL(pipe);
a43f6e0f 3019 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 3020 temp |= sel;
3021 else
3022 temp &= ~sel;
c98e9dcf 3023 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3024 }
5eddb70b 3025
3ad8a208
DV		 3026 /* XXX: pch pll's can be enabled any time before we enable the PCH
3027 * transcoder, and we actually should do this to not upset any PCH
3028 * transcoder that already use the clock when we share it.
3029 *
3030 * Note that enable_shared_dpll tries to do the right thing, but
3031 * get_shared_dpll unconditionally resets the pll - we need that to have
3032 * the right LVDS enable sequence. */
3033 ironlake_enable_shared_dpll(intel_crtc);
3034
d9b6cb56
JB		 3035 /* set transcoder timing, panel must allow it */
3036 assert_panel_unlocked(dev_priv, pipe);
275f01b2 3037 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 3038
303b81e0 3039 intel_fdi_normal_train(crtc);
5e84e1a4 3040
c98e9dcf
JB		 3041 /* For PCH DP, enable TRANS_DP_CTL */
3042 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3043 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3044 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3045 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3046 reg = TRANS_DP_CTL(pipe);
3047 temp = I915_READ(reg);
3048 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3049 TRANS_DP_SYNC_MASK |
3050 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3051 temp |= (TRANS_DP_OUTPUT_ENABLE |
3052 TRANS_DP_ENH_FRAMING);
9325c9f0 3053 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3054
3055 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3056 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3057 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3058 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3059
3060 switch (intel_trans_dp_port_sel(crtc)) {
3061 case PCH_DP_B:
5eddb70b 3062 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3063 break;
3064 case PCH_DP_C:
5eddb70b 3065 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3066 break;
3067 case PCH_DP_D:
5eddb70b 3068 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3069 break;
3070 default:
e95d41e1 3071 BUG();
32f9d658 3072 }
2c07245f 3073
5eddb70b 3074 I915_WRITE(reg, temp);
6be4a607 3075 }
b52eb4dc 3076
b8a4f404 3077 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3078}
3079
1507e5bd
PZ		 3080static void lpt_pch_enable(struct drm_crtc *crtc)
3081{
3082 struct drm_device *dev = crtc->dev;
3083 struct drm_i915_private *dev_priv = dev->dev_private;
3084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3085 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3086
ab9412ba 3087 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3088
8c52b5e8 3089 lpt_program_iclkip(crtc);
1507e5bd 3090
0540e488 3091 /* Set transcoder timing. */
275f01b2 3092 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3093
937bb610 3094 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3095}
3096
e2b78267 3097static void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3098{
e2b78267 3099 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 3100
3101 if (pll == NULL)
3102 return;
3103
3104 if (pll->refcount == 0) {
46edb027 3105 WARN(1, "bad %s refcount\n", pll->name);
ee7b9f93
JB		 3106 return;
3107 }
3108
f4a091c7
DV		 3109 if (--pll->refcount == 0) {
3110 WARN_ON(pll->on);
3111 WARN_ON(pll->active);
3112 }
3113
a43f6e0f 3114 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 3115}
3116
b89a1d39 3117static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3118{
e2b78267
DV		 3119 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3120 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3121 enum intel_dpll_id i;
ee7b9f93 3122
ee7b9f93 3123 if (pll) {
46edb027
DV		 3124 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3125 crtc->base.base.id, pll->name);
e2b78267 3126 intel_put_shared_dpll(crtc);
ee7b9f93
JB		 3127 }
3128
98b6bd99
DV		 3129 if (HAS_PCH_IBX(dev_priv->dev)) {
3130 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 3131 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 3132 pll = &dev_priv->shared_dplls[i];
98b6bd99 3133
46edb027
DV		 3134 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3135 crtc->base.base.id, pll->name);
98b6bd99
DV		 3136
3137 goto found;
3138 }
3139
e72f9fbf
DV		 3140 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3141 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 3142
3143 /* Only want to check enabled timings first */
3144 if (pll->refcount == 0)
3145 continue;
3146
b89a1d39
DV		 3147 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3148 sizeof(pll->hw_state)) == 0) {
46edb027 3149 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
e2b78267 3150 crtc->base.base.id,
46edb027 3151 pll->name, pll->refcount, pll->active);
ee7b9f93
JB		 3152
3153 goto found;
3154 }
3155 }
3156
3157 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 3158 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3159 pll = &dev_priv->shared_dplls[i];
ee7b9f93 3160 if (pll->refcount == 0) {
46edb027
DV		 3161 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3162 crtc->base.base.id, pll->name);
ee7b9f93
JB		 3163 goto found;
3164 }
3165 }
3166
3167 return NULL;
3168
3169found:
a43f6e0f 3170 crtc->config.shared_dpll = i;
46edb027
DV		 3171 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3172 pipe_name(crtc->pipe));
ee7b9f93 3173
cdbd2316 3174 if (pll->active == 0) {
66e985c0
DV		 3175 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3176 sizeof(pll->hw_state));
3177
46edb027 3178 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
cdbd2316 3179 WARN_ON(pll->on);
e9d6944e 3180 assert_shared_dpll_disabled(dev_priv, pll);
ee7b9f93 3181
15bdd4cf 3182 pll->mode_set(dev_priv, pll);
cdbd2316
DV		 3183 }
3184 pll->refcount++;
e04c7350 3185
ee7b9f93
JB		 3186 return pll;
3187}
3188
a1520318 3189static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3190{
3191 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3192 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3193 u32 temp;
3194
3195 temp = I915_READ(dslreg);
3196 udelay(500);
3197 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3198 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3199 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3200 }
3201}
3202
b074cec8
JB		 3203static void ironlake_pfit_enable(struct intel_crtc *crtc)
3204{
3205 struct drm_device *dev = crtc->base.dev;
3206 struct drm_i915_private *dev_priv = dev->dev_private;
3207 int pipe = crtc->pipe;
3208
0ef37f3f 3209 if (crtc->config.pch_pfit.size) {
b074cec8
JB		 3210 /* Force use of hard-coded filter coefficients
3211 * as some pre-programmed values are broken,
3212 * e.g. x201.
3213 */
3214 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3215 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3216 PF_PIPE_SEL_IVB(pipe));
3217 else
3218 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3219 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3220 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
d4270e57
JB		 3221 }
3222}
3223
bb53d4ae
VS		 3224static void intel_enable_planes(struct drm_crtc *crtc)
3225{
3226 struct drm_device *dev = crtc->dev;
3227 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3228 struct intel_plane *intel_plane;
3229
3230 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3231 if (intel_plane->pipe == pipe)
3232 intel_plane_restore(&intel_plane->base);
3233}
3234
3235static void intel_disable_planes(struct drm_crtc *crtc)
3236{
3237 struct drm_device *dev = crtc->dev;
3238 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3239 struct intel_plane *intel_plane;
3240
3241 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3242 if (intel_plane->pipe == pipe)
3243 intel_plane_disable(&intel_plane->base);
3244}
3245
f67a559d
JB		 3246static void ironlake_crtc_enable(struct drm_crtc *crtc)
3247{
3248 struct drm_device *dev = crtc->dev;
3249 struct drm_i915_private *dev_priv = dev->dev_private;
3250 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3251 struct intel_encoder *encoder;
f67a559d
JB		 3252 int pipe = intel_crtc->pipe;
3253 int plane = intel_crtc->plane;
f67a559d 3254
08a48469
DV		 3255 WARN_ON(!crtc->enabled);
3256
f67a559d
JB		 3257 if (intel_crtc->active)
3258 return;
3259
3260 intel_crtc->active = true;
8664281b
PZ		 3261
3262 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3263 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3264
f6736a1a 3265 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 3266 if (encoder->pre_enable)
3267 encoder->pre_enable(encoder);
f67a559d 3268
5bfe2ac0 3269 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3270 /* Note: FDI PLL enabling _must_ be done before we enable the
3271 * cpu pipes, hence this is separate from all the other fdi/pch
3272 * enabling. */
88cefb6c 3273 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3274 } else {
3275 assert_fdi_tx_disabled(dev_priv, pipe);
3276 assert_fdi_rx_disabled(dev_priv, pipe);
3277 }
f67a559d 3278
b074cec8 3279 ironlake_pfit_enable(intel_crtc);
f67a559d 3280
9c54c0dd
JB		 3281 /*
3282 * On ILK+ LUT must be loaded before the pipe is running but with
3283 * clocks enabled
3284 */
3285 intel_crtc_load_lut(crtc);
3286
f37fcc2a 3287 intel_update_watermarks(crtc);
5bfe2ac0 3288 intel_enable_pipe(dev_priv, pipe,
23538ef1 3289 intel_crtc->config.has_pch_encoder, false);
f67a559d 3290 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3291 intel_enable_planes(crtc);
5c38d48c 3292 intel_crtc_update_cursor(crtc, true);
f67a559d 3293
5bfe2ac0 3294 if (intel_crtc->config.has_pch_encoder)
f67a559d 3295 ironlake_pch_enable(crtc);
c98e9dcf 3296
d1ebd816 3297 mutex_lock(&dev->struct_mutex);
bed4a673 3298 intel_update_fbc(dev);
d1ebd816
BW		 3299 mutex_unlock(&dev->struct_mutex);
3300
fa5c73b1
DV		 3301 for_each_encoder_on_crtc(dev, crtc, encoder)
3302 encoder->enable(encoder);
61b77ddd
DV		 3303
3304 if (HAS_PCH_CPT(dev))
a1520318 3305 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3306
3307 /*
3308 * There seems to be a race in PCH platform hw (at least on some
3309 * outputs) where an enabled pipe still completes any pageflip right
3310 * away (as if the pipe is off) instead of waiting for vblank. As soon
3311 * as the first vblank happend, everything works as expected. Hence just
3312 * wait for one vblank before returning to avoid strange things
3313 * happening.
3314 */
3315 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3316}
3317
42db64ef
PZ		 3318/* IPS only exists on ULT machines and is tied to pipe A. */
3319static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3320{
f5adf94e 3321 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 3322}
3323
3324static void hsw_enable_ips(struct intel_crtc *crtc)
3325{
3326 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3327
3328 if (!crtc->config.ips_enabled)
3329 return;
3330
3331 /* We can only enable IPS after we enable a plane and wait for a vblank.
3332 * We guarantee that the plane is enabled by calling intel_enable_ips
3333 * only after intel_enable_plane. And intel_enable_plane already waits
3334 * for a vblank, so all we need to do here is to enable the IPS bit. */
3335 assert_plane_enabled(dev_priv, crtc->plane);
3336 I915_WRITE(IPS_CTL, IPS_ENABLE);
3337}
3338
3339static void hsw_disable_ips(struct intel_crtc *crtc)
3340{
3341 struct drm_device *dev = crtc->base.dev;
3342 struct drm_i915_private *dev_priv = dev->dev_private;
3343
3344 if (!crtc->config.ips_enabled)
3345 return;
3346
3347 assert_plane_enabled(dev_priv, crtc->plane);
3348 I915_WRITE(IPS_CTL, 0);
3349
3350 /* We need to wait for a vblank before we can disable the plane. */
3351 intel_wait_for_vblank(dev, crtc->pipe);
3352}
3353
4f771f10
PZ		 3354static void haswell_crtc_enable(struct drm_crtc *crtc)
3355{
3356 struct drm_device *dev = crtc->dev;
3357 struct drm_i915_private *dev_priv = dev->dev_private;
3358 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3359 struct intel_encoder *encoder;
3360 int pipe = intel_crtc->pipe;
3361 int plane = intel_crtc->plane;
4f771f10
PZ		 3362
3363 WARN_ON(!crtc->enabled);
3364
3365 if (intel_crtc->active)
3366 return;
3367
3368 intel_crtc->active = true;
8664281b
PZ		 3369
3370 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3371 if (intel_crtc->config.has_pch_encoder)
3372 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3373
5bfe2ac0 3374 if (intel_crtc->config.has_pch_encoder)
04945641 3375 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3376
3377 for_each_encoder_on_crtc(dev, crtc, encoder)
3378 if (encoder->pre_enable)
3379 encoder->pre_enable(encoder);
3380
1f544388 3381 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3382
b074cec8 3383 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3384
3385 /*
3386 * On ILK+ LUT must be loaded before the pipe is running but with
3387 * clocks enabled
3388 */
3389 intel_crtc_load_lut(crtc);
3390
1f544388 3391 intel_ddi_set_pipe_settings(crtc);
8228c251 3392 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3393
f37fcc2a 3394 intel_update_watermarks(crtc);
5bfe2ac0 3395 intel_enable_pipe(dev_priv, pipe,
23538ef1 3396 intel_crtc->config.has_pch_encoder, false);
4f771f10 3397 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3398 intel_enable_planes(crtc);
5c38d48c 3399 intel_crtc_update_cursor(crtc, true);
4f771f10 3400
42db64ef
PZ		 3401 hsw_enable_ips(intel_crtc);
3402
5bfe2ac0 3403 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3404 lpt_pch_enable(crtc);
4f771f10
PZ		 3405
3406 mutex_lock(&dev->struct_mutex);
3407 intel_update_fbc(dev);
3408 mutex_unlock(&dev->struct_mutex);
3409
8807e55b 3410 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 3411 encoder->enable(encoder);
8807e55b
JN		 3412 intel_opregion_notify_encoder(encoder, true);
3413 }
4f771f10 3414
4f771f10
PZ		 3415 /*
3416 * There seems to be a race in PCH platform hw (at least on some
3417 * outputs) where an enabled pipe still completes any pageflip right
3418 * away (as if the pipe is off) instead of waiting for vblank. As soon
3419 * as the first vblank happend, everything works as expected. Hence just
3420 * wait for one vblank before returning to avoid strange things
3421 * happening.
3422 */
3423 intel_wait_for_vblank(dev, intel_crtc->pipe);
3424}
3425
3f8dce3a
DV		 3426static void ironlake_pfit_disable(struct intel_crtc *crtc)
3427{
3428 struct drm_device *dev = crtc->base.dev;
3429 struct drm_i915_private *dev_priv = dev->dev_private;
3430 int pipe = crtc->pipe;
3431
3432 /* To avoid upsetting the power well on haswell only disable the pfit if
3433 * it's in use. The hw state code will make sure we get this right. */
3434 if (crtc->config.pch_pfit.size) {
3435 I915_WRITE(PF_CTL(pipe), 0);
3436 I915_WRITE(PF_WIN_POS(pipe), 0);
3437 I915_WRITE(PF_WIN_SZ(pipe), 0);
3438 }
3439}
3440
6be4a607
JB		 3441static void ironlake_crtc_disable(struct drm_crtc *crtc)
3442{
3443 struct drm_device *dev = crtc->dev;
3444 struct drm_i915_private *dev_priv = dev->dev_private;
3445 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3446 struct intel_encoder *encoder;
6be4a607
JB		 3447 int pipe = intel_crtc->pipe;
3448 int plane = intel_crtc->plane;
5eddb70b 3449 u32 reg, temp;
b52eb4dc 3450
ef9c3aee 3451
f7abfe8b
CW		 3452 if (!intel_crtc->active)
3453 return;
3454
ea9d758d
DV		 3455 for_each_encoder_on_crtc(dev, crtc, encoder)
3456 encoder->disable(encoder);
3457
e6c3a2a6 3458 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3459 drm_vblank_off(dev, pipe);
913d8d11 3460
5c3fe8b0 3461 if (dev_priv->fbc.plane == plane)
973d04f9 3462 intel_disable_fbc(dev);
2c07245f 3463
0d5b8c61 3464 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3465 intel_disable_planes(crtc);
0d5b8c61
VS		 3466 intel_disable_plane(dev_priv, plane, pipe);
3467
d925c59a
DV		 3468 if (intel_crtc->config.has_pch_encoder)
3469 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3470
b24e7179 3471 intel_disable_pipe(dev_priv, pipe);
32f9d658 3472
3f8dce3a 3473 ironlake_pfit_disable(intel_crtc);
2c07245f 3474
bf49ec8c
DV		 3475 for_each_encoder_on_crtc(dev, crtc, encoder)
3476 if (encoder->post_disable)
3477 encoder->post_disable(encoder);
2c07245f 3478
d925c59a
DV		 3479 if (intel_crtc->config.has_pch_encoder) {
3480 ironlake_fdi_disable(crtc);
913d8d11 3481
d925c59a
DV		 3482 ironlake_disable_pch_transcoder(dev_priv, pipe);
3483 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
6be4a607 3484
d925c59a
DV		 3485 if (HAS_PCH_CPT(dev)) {
3486 /* disable TRANS_DP_CTL */
3487 reg = TRANS_DP_CTL(pipe);
3488 temp = I915_READ(reg);
3489 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3490 TRANS_DP_PORT_SEL_MASK);
3491 temp |= TRANS_DP_PORT_SEL_NONE;
3492 I915_WRITE(reg, temp);
3493
3494 /* disable DPLL_SEL */
3495 temp = I915_READ(PCH_DPLL_SEL);
11887397 3496 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 3497 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 3498 }
e3421a18 3499
d925c59a 3500 /* disable PCH DPLL */
e72f9fbf 3501 intel_disable_shared_dpll(intel_crtc);
8db9d77b 3502
d925c59a
DV		 3503 ironlake_fdi_pll_disable(intel_crtc);
3504 }
6b383a7f 3505
f7abfe8b 3506 intel_crtc->active = false;
46ba614c 3507 intel_update_watermarks(crtc);
d1ebd816
BW		 3508
3509 mutex_lock(&dev->struct_mutex);
6b383a7f 3510 intel_update_fbc(dev);
d1ebd816 3511 mutex_unlock(&dev->struct_mutex);
6be4a607 3512}
1b3c7a47 3513
4f771f10 3514static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3515{
4f771f10
PZ		 3516 struct drm_device *dev = crtc->dev;
3517 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3518 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3519 struct intel_encoder *encoder;
3520 int pipe = intel_crtc->pipe;
3521 int plane = intel_crtc->plane;
3b117c8f 3522 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3523
4f771f10
PZ		 3524 if (!intel_crtc->active)
3525 return;
3526
8807e55b
JN		 3527 for_each_encoder_on_crtc(dev, crtc, encoder) {
3528 intel_opregion_notify_encoder(encoder, false);
4f771f10 3529 encoder->disable(encoder);
8807e55b 3530 }
4f771f10
PZ		 3531
3532 intel_crtc_wait_for_pending_flips(crtc);
3533 drm_vblank_off(dev, pipe);
4f771f10 3534
891348b2 3535 /* FBC must be disabled before disabling the plane on HSW. */
5c3fe8b0 3536 if (dev_priv->fbc.plane == plane)
4f771f10
PZ		 3537 intel_disable_fbc(dev);
3538
42db64ef
PZ		 3539 hsw_disable_ips(intel_crtc);
3540
0d5b8c61 3541 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3542 intel_disable_planes(crtc);
891348b2
RV		 3543 intel_disable_plane(dev_priv, plane, pipe);
3544
8664281b
PZ		 3545 if (intel_crtc->config.has_pch_encoder)
3546 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3547 intel_disable_pipe(dev_priv, pipe);
3548
ad80a810 3549 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3550
3f8dce3a 3551 ironlake_pfit_disable(intel_crtc);
4f771f10 3552
1f544388 3553 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3554
3555 for_each_encoder_on_crtc(dev, crtc, encoder)
3556 if (encoder->post_disable)
3557 encoder->post_disable(encoder);
3558
88adfff1 3559 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3560 lpt_disable_pch_transcoder(dev_priv);
8664281b 3561 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3562 intel_ddi_fdi_disable(crtc);
83616634 3563 }
4f771f10
PZ		 3564
3565 intel_crtc->active = false;
46ba614c 3566 intel_update_watermarks(crtc);
4f771f10
PZ		 3567
3568 mutex_lock(&dev->struct_mutex);
3569 intel_update_fbc(dev);
3570 mutex_unlock(&dev->struct_mutex);
3571}
3572
ee7b9f93
JB		 3573static void ironlake_crtc_off(struct drm_crtc *crtc)
3574{
3575 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 3576 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 3577}
3578
6441ab5f
PZ		 3579static void haswell_crtc_off(struct drm_crtc *crtc)
3580{
3581 intel_ddi_put_crtc_pll(crtc);
3582}
3583
02e792fb
DV		 3584static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3585{
02e792fb 3586 if (!enable && intel_crtc->overlay) {
23f09ce3 3587 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3588 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3589
23f09ce3 3590 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3591 dev_priv->mm.interruptible = false;
3592 (void) intel_overlay_switch_off(intel_crtc->overlay);
3593 dev_priv->mm.interruptible = true;
23f09ce3 3594 mutex_unlock(&dev->struct_mutex);
02e792fb 3595 }
02e792fb 3596
5dcdbcb0
CW		 3597 /* Let userspace switch the overlay on again. In most cases userspace
3598 * has to recompute where to put it anyway.
3599 */
02e792fb
DV		 3600}
3601
61bc95c1
EE		 3602/**
3603 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3604 * cursor plane briefly if not already running after enabling the display
3605 * plane.
3606 * This workaround avoids occasional blank screens when self refresh is
3607 * enabled.
3608 */
3609static void
3610g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3611{
3612 u32 cntl = I915_READ(CURCNTR(pipe));
3613
3614 if ((cntl & CURSOR_MODE) == 0) {
3615 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3616
3617 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3618 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3619 intel_wait_for_vblank(dev_priv->dev, pipe);
3620 I915_WRITE(CURCNTR(pipe), cntl);
3621 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3622 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3623 }
3624}
3625
2dd24552
JB		 3626static void i9xx_pfit_enable(struct intel_crtc *crtc)
3627{
3628 struct drm_device *dev = crtc->base.dev;
3629 struct drm_i915_private *dev_priv = dev->dev_private;
3630 struct intel_crtc_config *pipe_config = &crtc->config;
3631
328d8e82 3632 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3633 return;
3634
2dd24552 3635 /*
c0b03411
DV		 3636 * The panel fitter should only be adjusted whilst the pipe is disabled,
3637 * according to register description and PRM.
2dd24552 3638 */
c0b03411
DV		 3639 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3640 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3641
b074cec8
JB		 3642 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3643 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3644
3645 /* Border color in case we don't scale up to the full screen. Black by
3646 * default, change to something else for debugging. */
3647 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3648}
3649
89b667f8
JB		 3650static void valleyview_crtc_enable(struct drm_crtc *crtc)
3651{
3652 struct drm_device *dev = crtc->dev;
3653 struct drm_i915_private *dev_priv = dev->dev_private;
3654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3655 struct intel_encoder *encoder;
3656 int pipe = intel_crtc->pipe;
3657 int plane = intel_crtc->plane;
23538ef1 3658 bool is_dsi;
89b667f8
JB		 3659
3660 WARN_ON(!crtc->enabled);
3661
3662 if (intel_crtc->active)
3663 return;
3664
3665 intel_crtc->active = true;
89b667f8 3666
89b667f8
JB		 3667 for_each_encoder_on_crtc(dev, crtc, encoder)
3668 if (encoder->pre_pll_enable)
3669 encoder->pre_pll_enable(encoder);
3670
23538ef1
JN		 3671 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
3672
e9fd1c02
JN		 3673 if (!is_dsi)
3674 vlv_enable_pll(intel_crtc);
89b667f8
JB		 3675
3676 for_each_encoder_on_crtc(dev, crtc, encoder)
3677 if (encoder->pre_enable)
3678 encoder->pre_enable(encoder);
3679
2dd24552
JB		 3680 i9xx_pfit_enable(intel_crtc);
3681
63cbb074
VS		 3682 intel_crtc_load_lut(crtc);
3683
f37fcc2a 3684 intel_update_watermarks(crtc);
23538ef1 3685 intel_enable_pipe(dev_priv, pipe, false, is_dsi);
89b667f8 3686 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3687 intel_enable_planes(crtc);
5c38d48c 3688 intel_crtc_update_cursor(crtc, true);
89b667f8 3689
89b667f8 3690 intel_update_fbc(dev);
5004945f
JN		 3691
3692 for_each_encoder_on_crtc(dev, crtc, encoder)
3693 encoder->enable(encoder);
89b667f8
JB		 3694}
3695
0b8765c6 3696static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3697{
3698 struct drm_device *dev = crtc->dev;
79e53945
JB		 3699 struct drm_i915_private *dev_priv = dev->dev_private;
3700 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3701 struct intel_encoder *encoder;
79e53945 3702 int pipe = intel_crtc->pipe;
80824003 3703 int plane = intel_crtc->plane;
79e53945 3704
08a48469
DV		 3705 WARN_ON(!crtc->enabled);
3706
f7abfe8b
CW		 3707 if (intel_crtc->active)
3708 return;
3709
3710 intel_crtc->active = true;
6b383a7f 3711
9d6d9f19
MK		 3712 for_each_encoder_on_crtc(dev, crtc, encoder)
3713 if (encoder->pre_enable)
3714 encoder->pre_enable(encoder);
3715
f6736a1a
DV		 3716 i9xx_enable_pll(intel_crtc);
3717
2dd24552
JB		 3718 i9xx_pfit_enable(intel_crtc);
3719
63cbb074
VS		 3720 intel_crtc_load_lut(crtc);
3721
f37fcc2a 3722 intel_update_watermarks(crtc);
23538ef1 3723 intel_enable_pipe(dev_priv, pipe, false, false);
b24e7179 3724 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3725 intel_enable_planes(crtc);
22e407d7 3726 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE		 3727 if (IS_G4X(dev))
3728 g4x_fixup_plane(dev_priv, pipe);
22e407d7 3729 intel_crtc_update_cursor(crtc, true);
79e53945 3730
0b8765c6
JB		 3731 /* Give the overlay scaler a chance to enable if it's on this pipe */
3732 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3733
f440eb13 3734 intel_update_fbc(dev);
ef9c3aee 3735
fa5c73b1
DV		 3736 for_each_encoder_on_crtc(dev, crtc, encoder)
3737 encoder->enable(encoder);
0b8765c6 3738}
79e53945 3739
87476d63
DV		 3740static void i9xx_pfit_disable(struct intel_crtc *crtc)
3741{
3742 struct drm_device *dev = crtc->base.dev;
3743 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3744
328d8e82
DV		 3745 if (!crtc->config.gmch_pfit.control)
3746 return;
87476d63 3747
328d8e82 3748 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3749
328d8e82
DV		 3750 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3751 I915_READ(PFIT_CONTROL));
3752 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3753}
3754
0b8765c6
JB		 3755static void i9xx_crtc_disable(struct drm_crtc *crtc)
3756{
3757 struct drm_device *dev = crtc->dev;
3758 struct drm_i915_private *dev_priv = dev->dev_private;
3759 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3760 struct intel_encoder *encoder;
0b8765c6
JB		 3761 int pipe = intel_crtc->pipe;
3762 int plane = intel_crtc->plane;
ef9c3aee 3763
f7abfe8b
CW		 3764 if (!intel_crtc->active)
3765 return;
3766
ea9d758d
DV		 3767 for_each_encoder_on_crtc(dev, crtc, encoder)
3768 encoder->disable(encoder);
3769
0b8765c6 3770 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3771 intel_crtc_wait_for_pending_flips(crtc);
3772 drm_vblank_off(dev, pipe);
0b8765c6 3773
5c3fe8b0 3774 if (dev_priv->fbc.plane == plane)
973d04f9 3775 intel_disable_fbc(dev);
79e53945 3776
0d5b8c61
VS		 3777 intel_crtc_dpms_overlay(intel_crtc, false);
3778 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3779 intel_disable_planes(crtc);
b24e7179 3780 intel_disable_plane(dev_priv, plane, pipe);
0d5b8c61 3781
b24e7179 3782 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3783
87476d63 3784 i9xx_pfit_disable(intel_crtc);
24a1f16d 3785
89b667f8
JB		 3786 for_each_encoder_on_crtc(dev, crtc, encoder)
3787 if (encoder->post_disable)
3788 encoder->post_disable(encoder);
3789
e9fd1c02
JN		 3790 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3791 i9xx_disable_pll(dev_priv, pipe);
0b8765c6 3792
f7abfe8b 3793 intel_crtc->active = false;
46ba614c 3794 intel_update_watermarks(crtc);
f37fcc2a
VS		 3795
3796 intel_update_fbc(dev);
0b8765c6
JB		 3797}
3798
ee7b9f93
JB		 3799static void i9xx_crtc_off(struct drm_crtc *crtc)
3800{
3801}
3802
976f8a20
DV		 3803static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3804 bool enabled)
2c07245f
ZW		 3805{
3806 struct drm_device *dev = crtc->dev;
3807 struct drm_i915_master_private *master_priv;
3808 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3809 int pipe = intel_crtc->pipe;
79e53945
JB		 3810
3811 if (!dev->primary->master)
3812 return;
3813
3814 master_priv = dev->primary->master->driver_priv;
3815 if (!master_priv->sarea_priv)
3816 return;
3817
79e53945
JB		 3818 switch (pipe) {
3819 case 0:
3820 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3821 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3822 break;
3823 case 1:
3824 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3825 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3826 break;
3827 default:
9db4a9c7 3828 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3829 break;
3830 }
79e53945
JB		 3831}
3832
976f8a20
DV		 3833/**
3834 * Sets the power management mode of the pipe and plane.
3835 */
3836void intel_crtc_update_dpms(struct drm_crtc *crtc)
3837{
3838 struct drm_device *dev = crtc->dev;
3839 struct drm_i915_private *dev_priv = dev->dev_private;
3840 struct intel_encoder *intel_encoder;
3841 bool enable = false;
3842
3843 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3844 enable |= intel_encoder->connectors_active;
3845
3846 if (enable)
3847 dev_priv->display.crtc_enable(crtc);
3848 else
3849 dev_priv->display.crtc_disable(crtc);
3850
3851 intel_crtc_update_sarea(crtc, enable);
3852}
3853
cdd59983
CW		 3854static void intel_crtc_disable(struct drm_crtc *crtc)
3855{
cdd59983 3856 struct drm_device *dev = crtc->dev;
976f8a20 3857 struct drm_connector *connector;
ee7b9f93 3858 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3859 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3860
976f8a20
DV		 3861 /* crtc should still be enabled when we disable it. */
3862 WARN_ON(!crtc->enabled);
3863
3864 dev_priv->display.crtc_disable(crtc);
c77bf565 3865 intel_crtc->eld_vld = false;
976f8a20 3866 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3867 dev_priv->display.off(crtc);
3868
931872fc
CW		 3869 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3870 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3871
3872 if (crtc->fb) {
3873 mutex_lock(&dev->struct_mutex);
1690e1eb 3874 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3875 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3876 crtc->fb = NULL;
3877 }
3878
3879 /* Update computed state. */
3880 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3881 if (!connector->encoder || !connector->encoder->crtc)
3882 continue;
3883
3884 if (connector->encoder->crtc != crtc)
3885 continue;
3886
3887 connector->dpms = DRM_MODE_DPMS_OFF;
3888 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3889 }
3890}
3891
ea5b213a 3892void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3893{
4ef69c7a 3894 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3895
ea5b213a
CW		 3896 drm_encoder_cleanup(encoder);
3897 kfree(intel_encoder);
7e7d76c3
JB		 3898}
3899
9237329d 3900/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 3901 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3902 * state of the entire output pipe. */
9237329d 3903static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3904{
5ab432ef
DV		 3905 if (mode == DRM_MODE_DPMS_ON) {
3906 encoder->connectors_active = true;
3907
b2cabb0e 3908 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3909 } else {
3910 encoder->connectors_active = false;
3911
b2cabb0e 3912 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3913 }
79e53945
JB		 3914}
3915
0a91ca29
DV		 3916/* Cross check the actual hw state with our own modeset state tracking (and it's
3917 * internal consistency). */
b980514c 3918static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3919{
0a91ca29
DV		 3920 if (connector->get_hw_state(connector)) {
3921 struct intel_encoder *encoder = connector->encoder;
3922 struct drm_crtc *crtc;
3923 bool encoder_enabled;
3924 enum pipe pipe;
3925
3926 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3927 connector->base.base.id,
3928 drm_get_connector_name(&connector->base));
3929
3930 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3931 "wrong connector dpms state\n");
3932 WARN(connector->base.encoder != &encoder->base,
3933 "active connector not linked to encoder\n");
3934 WARN(!encoder->connectors_active,
3935 "encoder->connectors_active not set\n");
3936
3937 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3938 WARN(!encoder_enabled, "encoder not enabled\n");
3939 if (WARN_ON(!encoder->base.crtc))
3940 return;
3941
3942 crtc = encoder->base.crtc;
3943
3944 WARN(!crtc->enabled, "crtc not enabled\n");
3945 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3946 WARN(pipe != to_intel_crtc(crtc)->pipe,
3947 "encoder active on the wrong pipe\n");
3948 }
79e53945
JB		 3949}
3950
5ab432ef
DV		 3951/* Even simpler default implementation, if there's really no special case to
3952 * consider. */
3953void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3954{
5ab432ef 3955 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3956
5ab432ef
DV		 3957 /* All the simple cases only support two dpms states. */
3958 if (mode != DRM_MODE_DPMS_ON)
3959 mode = DRM_MODE_DPMS_OFF;
d4270e57 3960
5ab432ef
DV		 3961 if (mode == connector->dpms)
3962 return;
3963
3964 connector->dpms = mode;
3965
3966 /* Only need to change hw state when actually enabled */
3967 if (encoder->base.crtc)
3968 intel_encoder_dpms(encoder, mode);
3969 else
8af6cf88 3970 WARN_ON(encoder->connectors_active != false);
0a91ca29 3971
b980514c 3972 intel_modeset_check_state(connector->dev);
79e53945
JB		 3973}
3974
f0947c37
DV		 3975/* Simple connector->get_hw_state implementation for encoders that support only
3976 * one connector and no cloning and hence the encoder state determines the state
3977 * of the connector. */
3978bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3979{
24929352 3980 enum pipe pipe = 0;
f0947c37 3981 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3982
f0947c37 3983 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3984}
3985
1857e1da
DV		 3986static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3987 struct intel_crtc_config *pipe_config)
3988{
3989 struct drm_i915_private *dev_priv = dev->dev_private;
3990 struct intel_crtc *pipe_B_crtc =
3991 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3992
3993 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3994 pipe_name(pipe), pipe_config->fdi_lanes);
3995 if (pipe_config->fdi_lanes > 4) {
3996 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3997 pipe_name(pipe), pipe_config->fdi_lanes);
3998 return false;
3999 }
4000
4001 if (IS_HASWELL(dev)) {
4002 if (pipe_config->fdi_lanes > 2) {
4003 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4004 pipe_config->fdi_lanes);
4005 return false;
4006 } else {
4007 return true;
4008 }
4009 }
4010
4011 if (INTEL_INFO(dev)->num_pipes == 2)
4012 return true;
4013
4014 /* Ivybridge 3 pipe is really complicated */
4015 switch (pipe) {
4016 case PIPE_A:
4017 return true;
4018 case PIPE_B:
4019 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4020 pipe_config->fdi_lanes > 2) {
4021 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4022 pipe_name(pipe), pipe_config->fdi_lanes);
4023 return false;
4024 }
4025 return true;
4026 case PIPE_C:
1e833f40 4027 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 4028 pipe_B_crtc->config.fdi_lanes <= 2) {
4029 if (pipe_config->fdi_lanes > 2) {
4030 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4031 pipe_name(pipe), pipe_config->fdi_lanes);
4032 return false;
4033 }
4034 } else {
4035 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4036 return false;
4037 }
4038 return true;
4039 default:
4040 BUG();
4041 }
4042}
4043
e29c22c0
DV		 4044#define RETRY 1
4045static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4046 struct intel_crtc_config *pipe_config)
877d48d5 4047{
1857e1da 4048 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 4049 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 4050 int lane, link_bw, fdi_dotclock;
e29c22c0 4051 bool setup_ok, needs_recompute = false;
877d48d5 4052
e29c22c0 4053retry:
877d48d5
DV		 4054 /* FDI is a binary signal running at ~2.7GHz, encoding
4055 * each output octet as 10 bits. The actual frequency
4056 * is stored as a divider into a 100MHz clock, and the
4057 * mode pixel clock is stored in units of 1KHz.
4058 * Hence the bw of each lane in terms of the mode signal
4059 * is:
4060 */
4061 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4062
ff9a6750 4063 fdi_dotclock = adjusted_mode->clock;
ef1b460d 4064 fdi_dotclock /= pipe_config->pixel_multiplier;
877d48d5 4065
2bd89a07 4066 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4067 pipe_config->pipe_bpp);
4068
4069 pipe_config->fdi_lanes = lane;
4070
2bd89a07 4071 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4072 link_bw, &pipe_config->fdi_m_n);
1857e1da 4073
e29c22c0
DV		 4074 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4075 intel_crtc->pipe, pipe_config);
4076 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4077 pipe_config->pipe_bpp -= 2*3;
4078 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4079 pipe_config->pipe_bpp);
4080 needs_recompute = true;
4081 pipe_config->bw_constrained = true;
4082
4083 goto retry;
4084 }
4085
4086 if (needs_recompute)
4087 return RETRY;
4088
4089 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4090}
4091
42db64ef
PZ		 4092static void hsw_compute_ips_config(struct intel_crtc *crtc,
4093 struct intel_crtc_config *pipe_config)
4094{
3c4ca58c
PZ		 4095 pipe_config->ips_enabled = i915_enable_ips &&
4096 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 4097 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 4098}
4099
a43f6e0f 4100static int intel_crtc_compute_config(struct intel_crtc *crtc,
e29c22c0 4101 struct intel_crtc_config *pipe_config)
79e53945 4102{
a43f6e0f 4103 struct drm_device *dev = crtc->base.dev;
b8cecdf5 4104 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4105
8693a824
DL		 4106 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4107 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4108 */
4109 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4110 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4111 return -EINVAL;
44f46b42 4112
bd080ee5 4113 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4114 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4115 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4116 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4117 * for lvds. */
4118 pipe_config->pipe_bpp = 8*3;
4119 }
4120
f5adf94e 4121 if (HAS_IPS(dev))
a43f6e0f
DV		 4122 hsw_compute_ips_config(crtc, pipe_config);
4123
4124 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4125 * clock survives for now. */
4126 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4127 pipe_config->shared_dpll = crtc->config.shared_dpll;
42db64ef 4128
877d48d5 4129 if (pipe_config->has_pch_encoder)
a43f6e0f 4130 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 4131
e29c22c0 4132 return 0;
79e53945
JB		 4133}
4134
25eb05fc
JB		 4135static int valleyview_get_display_clock_speed(struct drm_device *dev)
4136{
4137 return 400000; /* FIXME */
4138}
4139
e70236a8
JB		 4140static int i945_get_display_clock_speed(struct drm_device *dev)
4141{
4142 return 400000;
4143}
79e53945 4144
e70236a8 4145static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4146{
e70236a8
JB		 4147 return 333000;
4148}
79e53945 4149
e70236a8
JB		 4150static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4151{
4152 return 200000;
4153}
79e53945 4154
257a7ffc
DV		 4155static int pnv_get_display_clock_speed(struct drm_device *dev)
4156{
4157 u16 gcfgc = 0;
4158
4159 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4160
4161 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4162 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4163 return 267000;
4164 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4165 return 333000;
4166 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4167 return 444000;
4168 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4169 return 200000;
4170 default:
4171 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4172 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4173 return 133000;
4174 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4175 return 167000;
4176 }
4177}
4178
e70236a8
JB		 4179static int i915gm_get_display_clock_speed(struct drm_device *dev)
4180{
4181 u16 gcfgc = 0;
79e53945 4182
e70236a8
JB		 4183 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4184
4185 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4186 return 133000;
4187 else {
4188 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4189 case GC_DISPLAY_CLOCK_333_MHZ:
4190 return 333000;
4191 default:
4192 case GC_DISPLAY_CLOCK_190_200_MHZ:
4193 return 190000;
79e53945 4194 }
e70236a8
JB		 4195 }
4196}
4197
4198static int i865_get_display_clock_speed(struct drm_device *dev)
4199{
4200 return 266000;
4201}
4202
4203static int i855_get_display_clock_speed(struct drm_device *dev)
4204{
4205 u16 hpllcc = 0;
4206 /* Assume that the hardware is in the high speed state. This
4207 * should be the default.
4208 */
4209 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4210 case GC_CLOCK_133_200:
4211 case GC_CLOCK_100_200:
4212 return 200000;
4213 case GC_CLOCK_166_250:
4214 return 250000;
4215 case GC_CLOCK_100_133:
79e53945 4216 return 133000;
e70236a8 4217 }
79e53945 4218
e70236a8
JB		 4219 /* Shouldn't happen */
4220 return 0;
4221}
79e53945 4222
e70236a8
JB		 4223static int i830_get_display_clock_speed(struct drm_device *dev)
4224{
4225 return 133000;
79e53945
JB		 4226}
4227
2c07245f 4228static void
a65851af 4229intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4230{
a65851af
VS		 4231 while (*num > DATA_LINK_M_N_MASK ||
4232 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4233 *num >>= 1;
4234 *den >>= 1;
4235 }
4236}
4237
a65851af
VS		 4238static void compute_m_n(unsigned int m, unsigned int n,
4239 uint32_t *ret_m, uint32_t *ret_n)
4240{
4241 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4242 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4243 intel_reduce_m_n_ratio(ret_m, ret_n);
4244}
4245
e69d0bc1
DV		 4246void
4247intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4248 int pixel_clock, int link_clock,
4249 struct intel_link_m_n *m_n)
2c07245f 4250{
e69d0bc1 4251 m_n->tu = 64;
a65851af
VS		 4252
4253 compute_m_n(bits_per_pixel * pixel_clock,
4254 link_clock * nlanes * 8,
4255 &m_n->gmch_m, &m_n->gmch_n);
4256
4257 compute_m_n(pixel_clock, link_clock,
4258 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4259}
4260
a7615030
CW		 4261static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4262{
72bbe58c
KP		 4263 if (i915_panel_use_ssc >= 0)
4264 return i915_panel_use_ssc != 0;
41aa3448 4265 return dev_priv->vbt.lvds_use_ssc
435793df 4266 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4267}
4268
a0c4da24
JB		 4269static int vlv_get_refclk(struct drm_crtc *crtc)
4270{
4271 struct drm_device *dev = crtc->dev;
4272 struct drm_i915_private *dev_priv = dev->dev_private;
4273 int refclk = 27000; /* for DP & HDMI */
4274
4275 return 100000; /* only one validated so far */
4276
4277 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4278 refclk = 96000;
4279 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4280 if (intel_panel_use_ssc(dev_priv))
4281 refclk = 100000;
4282 else
4283 refclk = 96000;
4284 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4285 refclk = 100000;
4286 }
4287
4288 return refclk;
4289}
4290
c65d77d8
JB		 4291static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4292{
4293 struct drm_device *dev = crtc->dev;
4294 struct drm_i915_private *dev_priv = dev->dev_private;
4295 int refclk;
4296
a0c4da24
JB		 4297 if (IS_VALLEYVIEW(dev)) {
4298 refclk = vlv_get_refclk(crtc);
4299 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4300 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4301 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4302 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4303 refclk / 1000);
4304 } else if (!IS_GEN2(dev)) {
4305 refclk = 96000;
4306 } else {
4307 refclk = 48000;
4308 }
4309
4310 return refclk;
4311}
4312
7429e9d4 4313static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 4314{
7df00d7a 4315 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 4316}
f47709a9 4317
7429e9d4
DV		 4318static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4319{
4320 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 4321}
4322
f47709a9 4323static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4324 intel_clock_t *reduced_clock)
4325{
f47709a9 4326 struct drm_device *dev = crtc->base.dev;
a7516a05 4327 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4328 int pipe = crtc->pipe;
a7516a05
JB		 4329 u32 fp, fp2 = 0;
4330
4331 if (IS_PINEVIEW(dev)) {
7429e9d4 4332 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4333 if (reduced_clock)
7429e9d4 4334 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4335 } else {
7429e9d4 4336 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4337 if (reduced_clock)
7429e9d4 4338 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4339 }
4340
4341 I915_WRITE(FP0(pipe), fp);
8bcc2795 4342 crtc->config.dpll_hw_state.fp0 = fp;
a7516a05 4343
f47709a9
DV		 4344 crtc->lowfreq_avail = false;
4345 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4346 reduced_clock && i915_powersave) {
4347 I915_WRITE(FP1(pipe), fp2);
8bcc2795 4348 crtc->config.dpll_hw_state.fp1 = fp2;
f47709a9 4349 crtc->lowfreq_avail = true;
a7516a05
JB		 4350 } else {
4351 I915_WRITE(FP1(pipe), fp);
8bcc2795 4352 crtc->config.dpll_hw_state.fp1 = fp;
a7516a05
JB		 4353 }
4354}
4355
5e69f97f
CML		 4356static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4357 pipe)
89b667f8
JB		 4358{
4359 u32 reg_val;
4360
4361 /*
4362 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4363 * and set it to a reasonable value instead.
4364 */
5e69f97f 4365 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8
JB		 4366 reg_val &= 0xffffff00;
4367 reg_val |= 0x00000030;
5e69f97f 4368 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4369
5e69f97f 4370 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4371 reg_val &= 0x8cffffff;
4372 reg_val = 0x8c000000;
5e69f97f 4373 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8 4374
5e69f97f 4375 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8 4376 reg_val &= 0xffffff00;
5e69f97f 4377 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4378
5e69f97f 4379 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4380 reg_val &= 0x00ffffff;
4381 reg_val |= 0xb0000000;
5e69f97f 4382 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4383}
4384
b551842d
DV		 4385static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4386 struct intel_link_m_n *m_n)
4387{
4388 struct drm_device *dev = crtc->base.dev;
4389 struct drm_i915_private *dev_priv = dev->dev_private;
4390 int pipe = crtc->pipe;
4391
e3b95f1e
DV		 4392 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4393 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4394 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4395 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4396}
4397
4398static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4399 struct intel_link_m_n *m_n)
4400{
4401 struct drm_device *dev = crtc->base.dev;
4402 struct drm_i915_private *dev_priv = dev->dev_private;
4403 int pipe = crtc->pipe;
4404 enum transcoder transcoder = crtc->config.cpu_transcoder;
4405
4406 if (INTEL_INFO(dev)->gen >= 5) {
4407 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4408 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4409 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4410 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4411 } else {
e3b95f1e
DV		 4412 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4413 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4414 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4415 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4416 }
4417}
4418
03afc4a2
DV		 4419static void intel_dp_set_m_n(struct intel_crtc *crtc)
4420{
4421 if (crtc->config.has_pch_encoder)
4422 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4423 else
4424 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4425}
4426
f47709a9 4427static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4428{
f47709a9 4429 struct drm_device *dev = crtc->base.dev;
a0c4da24 4430 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4431 int pipe = crtc->pipe;
89b667f8 4432 u32 dpll, mdiv;
a0c4da24 4433 u32 bestn, bestm1, bestm2, bestp1, bestp2;
198a037f 4434 u32 coreclk, reg_val, dpll_md;
a0c4da24 4435
09153000
DV		 4436 mutex_lock(&dev_priv->dpio_lock);
4437
f47709a9
DV		 4438 bestn = crtc->config.dpll.n;
4439 bestm1 = crtc->config.dpll.m1;
4440 bestm2 = crtc->config.dpll.m2;
4441 bestp1 = crtc->config.dpll.p1;
4442 bestp2 = crtc->config.dpll.p2;
a0c4da24 4443
89b667f8
JB		 4444 /* See eDP HDMI DPIO driver vbios notes doc */
4445
4446 /* PLL B needs special handling */
4447 if (pipe)
5e69f97f 4448 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 4449
4450 /* Set up Tx target for periodic Rcomp update */
5e69f97f 4451 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4452
4453 /* Disable target IRef on PLL */
5e69f97f 4454 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
89b667f8 4455 reg_val &= 0x00ffffff;
5e69f97f 4456 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4457
4458 /* Disable fast lock */
5e69f97f 4459 vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4460
4461 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4462 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4463 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4464 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4465 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4466
4467 /*
4468 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4469 * but we don't support that).
4470 * Note: don't use the DAC post divider as it seems unstable.
4471 */
4472 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5e69f97f 4473 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4474
a0c4da24 4475 mdiv |= DPIO_ENABLE_CALIBRATION;
5e69f97f 4476 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4477
89b667f8 4478 /* Set HBR and RBR LPF coefficients */
ff9a6750 4479 if (crtc->config.port_clock == 162000 ||
99750bd4 4480 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
89b667f8 4481 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5e69f97f 4482 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
885b0120 4483 0x009f0003);
89b667f8 4484 else
5e69f97f 4485 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
89b667f8
JB		 4486 0x00d0000f);
4487
4488 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4489 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4490 /* Use SSC source */
4491 if (!pipe)
5e69f97f 4492 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4493 0x0df40000);
4494 else
5e69f97f 4495 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4496 0x0df70000);
4497 } else { /* HDMI or VGA */
4498 /* Use bend source */
4499 if (!pipe)
5e69f97f 4500 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4501 0x0df70000);
4502 else
5e69f97f 4503 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4504 0x0df40000);
4505 }
a0c4da24 4506
5e69f97f 4507 coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4508 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4509 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4510 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4511 coreclk |= 0x01000000;
5e69f97f 4512 vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4513
5e69f97f 4514 vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4515
89b667f8
JB		 4516 /* Enable DPIO clock input */
4517 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4518 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4519 if (pipe)
4520 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
a0c4da24
JB		 4521
4522 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4523 crtc->config.dpll_hw_state.dpll = dpll;
4524
ef1b460d
DV		 4525 dpll_md = (crtc->config.pixel_multiplier - 1)
4526 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795
DV		 4527 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4528
89b667f8
JB		 4529 if (crtc->config.has_dp_encoder)
4530 intel_dp_set_m_n(crtc);
09153000
DV		 4531
4532 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4533}
4534
f47709a9
DV		 4535static void i9xx_update_pll(struct intel_crtc *crtc,
4536 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4537 int num_connectors)
4538{
f47709a9 4539 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4540 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 4541 u32 dpll;
4542 bool is_sdvo;
f47709a9 4543 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4544
f47709a9 4545 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4546
f47709a9
DV		 4547 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4548 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4549
4550 dpll = DPLL_VGA_MODE_DIS;
4551
f47709a9 4552 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4553 dpll |= DPLLB_MODE_LVDS;
4554 else
4555 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4556
ef1b460d 4557 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4558 dpll |= (crtc->config.pixel_multiplier - 1)
4559 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4560 }
198a037f
DV		 4561
4562 if (is_sdvo)
4a33e48d 4563 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 4564
f47709a9 4565 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4a33e48d 4566 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 4567
4568 /* compute bitmask from p1 value */
4569 if (IS_PINEVIEW(dev))
4570 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4571 else {
4572 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4573 if (IS_G4X(dev) && reduced_clock)
4574 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4575 }
4576 switch (clock->p2) {
4577 case 5:
4578 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4579 break;
4580 case 7:
4581 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4582 break;
4583 case 10:
4584 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4585 break;
4586 case 14:
4587 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4588 break;
4589 }
4590 if (INTEL_INFO(dev)->gen >= 4)
4591 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4592
09ede541 4593 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4594 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4595 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4596 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4597 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4598 else
4599 dpll |= PLL_REF_INPUT_DREFCLK;
4600
4601 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4602 crtc->config.dpll_hw_state.dpll = dpll;
4603
eb1cbe48 4604 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4605 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4606 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795 4607 crtc->config.dpll_hw_state.dpll_md = dpll_md;
eb1cbe48 4608 }
66e3d5c0
DV		 4609
4610 if (crtc->config.has_dp_encoder)
4611 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4612}
4613
f47709a9 4614static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4615 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4616 int num_connectors)
4617{
f47709a9 4618 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4619 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 4620 u32 dpll;
f47709a9 4621 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4622
f47709a9 4623 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4624
eb1cbe48
DV		 4625 dpll = DPLL_VGA_MODE_DIS;
4626
f47709a9 4627 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4628 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4629 } else {
4630 if (clock->p1 == 2)
4631 dpll |= PLL_P1_DIVIDE_BY_TWO;
4632 else
4633 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4634 if (clock->p2 == 4)
4635 dpll |= PLL_P2_DIVIDE_BY_4;
4636 }
4637
4a33e48d
DV		 4638 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4639 dpll |= DPLL_DVO_2X_MODE;
4640
f47709a9 4641 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4642 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4643 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4644 else
4645 dpll |= PLL_REF_INPUT_DREFCLK;
4646
4647 dpll |= DPLL_VCO_ENABLE;
8bcc2795 4648 crtc->config.dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 4649}
4650
8a654f3b 4651static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4652{
4653 struct drm_device *dev = intel_crtc->base.dev;
4654 struct drm_i915_private *dev_priv = dev->dev_private;
4655 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4656 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4657 struct drm_display_mode *adjusted_mode =
4658 &intel_crtc->config.adjusted_mode;
4659 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4d8a62ea
DV		 4660 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4661
4662 /* We need to be careful not to changed the adjusted mode, for otherwise
4663 * the hw state checker will get angry at the mismatch. */
4664 crtc_vtotal = adjusted_mode->crtc_vtotal;
4665 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4666
4667 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4668 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4669 crtc_vtotal -= 1;
4670 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4671 vsyncshift = adjusted_mode->crtc_hsync_start
4672 - adjusted_mode->crtc_htotal / 2;
4673 } else {
4674 vsyncshift = 0;
4675 }
4676
4677 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4678 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4679
fe2b8f9d 4680 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4681 (adjusted_mode->crtc_hdisplay - 1) |
4682 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4683 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4684 (adjusted_mode->crtc_hblank_start - 1) |
4685 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4686 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4687 (adjusted_mode->crtc_hsync_start - 1) |
4688 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4689
fe2b8f9d 4690 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4691 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4692 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4693 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4694 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4695 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4696 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4697 (adjusted_mode->crtc_vsync_start - 1) |
4698 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4699
b5e508d4
PZ		 4700 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4701 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4702 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4703 * bits. */
4704 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4705 (pipe == PIPE_B || pipe == PIPE_C))
4706 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4707
b0e77b9c
PZ		 4708 /* pipesrc controls the size that is scaled from, which should
4709 * always be the user's requested size.
4710 */
4711 I915_WRITE(PIPESRC(pipe),
4712 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4713}
4714
1bd1bd80
DV		 4715static void intel_get_pipe_timings(struct intel_crtc *crtc,
4716 struct intel_crtc_config *pipe_config)
4717{
4718 struct drm_device *dev = crtc->base.dev;
4719 struct drm_i915_private *dev_priv = dev->dev_private;
4720 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4721 uint32_t tmp;
4722
4723 tmp = I915_READ(HTOTAL(cpu_transcoder));
4724 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4725 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4726 tmp = I915_READ(HBLANK(cpu_transcoder));
4727 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4728 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4729 tmp = I915_READ(HSYNC(cpu_transcoder));
4730 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4731 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4732
4733 tmp = I915_READ(VTOTAL(cpu_transcoder));
4734 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4735 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4736 tmp = I915_READ(VBLANK(cpu_transcoder));
4737 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4738 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4739 tmp = I915_READ(VSYNC(cpu_transcoder));
4740 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4741 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4742
4743 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4744 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4745 pipe_config->adjusted_mode.crtc_vtotal += 1;
4746 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4747 }
4748
4749 tmp = I915_READ(PIPESRC(crtc->pipe));
4750 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4751 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4752}
4753
babea61d
JB		 4754static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4755 struct intel_crtc_config *pipe_config)
4756{
4757 struct drm_crtc *crtc = &intel_crtc->base;
4758
4759 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4760 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4761 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4762 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4763
4764 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4765 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4766 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4767 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4768
4769 crtc->mode.flags = pipe_config->adjusted_mode.flags;
4770
4771 crtc->mode.clock = pipe_config->adjusted_mode.clock;
4772 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4773}
4774
84b046f3
DV		 4775static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4776{
4777 struct drm_device *dev = intel_crtc->base.dev;
4778 struct drm_i915_private *dev_priv = dev->dev_private;
4779 uint32_t pipeconf;
4780
9f11a9e4 4781 pipeconf = 0;
84b046f3
DV		 4782
4783 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4784 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4785 * core speed.
4786 *
4787 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4788 * pipe == 0 check?
4789 */
4790 if (intel_crtc->config.requested_mode.clock >
4791 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4792 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3
DV		 4793 }
4794
ff9ce46e
DV		 4795 /* only g4x and later have fancy bpc/dither controls */
4796 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e
DV		 4797 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4798 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4799 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4800 PIPECONF_DITHER_TYPE_SP;
84b046f3 4801
ff9ce46e
DV		 4802 switch (intel_crtc->config.pipe_bpp) {
4803 case 18:
4804 pipeconf |= PIPECONF_6BPC;
4805 break;
4806 case 24:
4807 pipeconf |= PIPECONF_8BPC;
4808 break;
4809 case 30:
4810 pipeconf |= PIPECONF_10BPC;
4811 break;
4812 default:
4813 /* Case prevented by intel_choose_pipe_bpp_dither. */
4814 BUG();
84b046f3
DV		 4815 }
4816 }
4817
4818 if (HAS_PIPE_CXSR(dev)) {
4819 if (intel_crtc->lowfreq_avail) {
4820 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4821 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4822 } else {
4823 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 4824 }
4825 }
4826
84b046f3
DV		 4827 if (!IS_GEN2(dev) &&
4828 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4829 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4830 else
4831 pipeconf |= PIPECONF_PROGRESSIVE;
4832
9f11a9e4
DV		 4833 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4834 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 4835
84b046f3
DV		 4836 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4837 POSTING_READ(PIPECONF(intel_crtc->pipe));
4838}
4839
f564048e 4840static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4841 int x, int y,
94352cf9 4842 struct drm_framebuffer *fb)
79e53945
JB		 4843{
4844 struct drm_device *dev = crtc->dev;
4845 struct drm_i915_private *dev_priv = dev->dev_private;
4846 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 4847 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4848 int pipe = intel_crtc->pipe;
80824003 4849 int plane = intel_crtc->plane;
c751ce4f 4850 int refclk, num_connectors = 0;
652c393a 4851 intel_clock_t clock, reduced_clock;
84b046f3 4852 u32 dspcntr;
a16af721 4853 bool ok, has_reduced_clock = false;
e9fd1c02 4854 bool is_lvds = false, is_dsi = false;
5eddb70b 4855 struct intel_encoder *encoder;
d4906093 4856 const intel_limit_t *limit;
5c3b82e2 4857 int ret;
79e53945 4858
6c2b7c12 4859 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4860 switch (encoder->type) {
79e53945
JB		 4861 case INTEL_OUTPUT_LVDS:
4862 is_lvds = true;
4863 break;
e9fd1c02
JN		 4864 case INTEL_OUTPUT_DSI:
4865 is_dsi = true;
4866 break;
79e53945 4867 }
43565a06 4868
c751ce4f 4869 num_connectors++;
79e53945
JB		 4870 }
4871
c65d77d8 4872 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4873
65ce4bf5 4874 if (!is_dsi && !intel_crtc->config.clock_set) {
e9fd1c02
JN		 4875 /*
4876 * Returns a set of divisors for the desired target clock with
4877 * the given refclk, or FALSE. The returned values represent
4878 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
4879 * 2) / p1 / p2.
4880 */
4881 limit = intel_limit(crtc, refclk);
4882 ok = dev_priv->display.find_dpll(limit, crtc,
4883 intel_crtc->config.port_clock,
4884 refclk, NULL, &clock);
4885 if (!ok && !intel_crtc->config.clock_set) {
4886 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4887 return -EINVAL;
4888 }
79e53945
JB		 4889 }
4890
cda4b7d3 4891 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4892 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4893
e9fd1c02 4894 if (!is_dsi && is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4895 /*
4896 * Ensure we match the reduced clock's P to the target clock.
4897 * If the clocks don't match, we can't switch the display clock
4898 * by using the FP0/FP1. In such case we will disable the LVDS
4899 * downclock feature.
4900 */
65ce4bf5 4901 limit = intel_limit(crtc, refclk);
ee9300bb
DV		 4902 has_reduced_clock =
4903 dev_priv->display.find_dpll(limit, crtc,
5eddb70b 4904 dev_priv->lvds_downclock,
ee9300bb 4905 refclk, &clock,
5eddb70b 4906 &reduced_clock);
7026d4ac 4907 }
f47709a9
DV		 4908 /* Compat-code for transition, will disappear. */
4909 if (!intel_crtc->config.clock_set) {
4910 intel_crtc->config.dpll.n = clock.n;
4911 intel_crtc->config.dpll.m1 = clock.m1;
4912 intel_crtc->config.dpll.m2 = clock.m2;
4913 intel_crtc->config.dpll.p1 = clock.p1;
4914 intel_crtc->config.dpll.p2 = clock.p2;
4915 }
7026d4ac 4916
e9fd1c02 4917 if (IS_GEN2(dev)) {
8a654f3b 4918 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 4919 has_reduced_clock ? &reduced_clock : NULL,
4920 num_connectors);
e9fd1c02
JN		 4921 } else if (IS_VALLEYVIEW(dev)) {
4922 if (!is_dsi)
4923 vlv_update_pll(intel_crtc);
4924 } else {
f47709a9 4925 i9xx_update_pll(intel_crtc,
eb1cbe48 4926 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4927 num_connectors);
e9fd1c02 4928 }
79e53945 4929
79e53945
JB		 4930 /* Set up the display plane register */
4931 dspcntr = DISPPLANE_GAMMA_ENABLE;
4932
da6ecc5d
JB		 4933 if (!IS_VALLEYVIEW(dev)) {
4934 if (pipe == 0)
4935 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4936 else
4937 dspcntr |= DISPPLANE_SEL_PIPE_B;
4938 }
79e53945 4939
8a654f3b 4940 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 4941
4942 /* pipesrc and dspsize control the size that is scaled from,
4943 * which should always be the user's requested size.
79e53945 4944 */
929c77fb
EA		 4945 I915_WRITE(DSPSIZE(plane),
4946 ((mode->vdisplay - 1) << 16) |
4947 (mode->hdisplay - 1));
4948 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4949
84b046f3
DV		 4950 i9xx_set_pipeconf(intel_crtc);
4951
f564048e
EA		 4952 I915_WRITE(DSPCNTR(plane), dspcntr);
4953 POSTING_READ(DSPCNTR(plane));
4954
94352cf9 4955 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e 4956
f564048e
EA		 4957 return ret;
4958}
4959
2fa2fe9a
DV		 4960static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4961 struct intel_crtc_config *pipe_config)
4962{
4963 struct drm_device *dev = crtc->base.dev;
4964 struct drm_i915_private *dev_priv = dev->dev_private;
4965 uint32_t tmp;
4966
4967 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 4968 if (!(tmp & PFIT_ENABLE))
4969 return;
2fa2fe9a 4970
06922821 4971 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 4972 if (INTEL_INFO(dev)->gen < 4) {
4973 if (crtc->pipe != PIPE_B)
4974 return;
2fa2fe9a
DV		 4975 } else {
4976 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4977 return;
4978 }
4979
06922821 4980 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 4981 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4982 if (INTEL_INFO(dev)->gen < 5)
4983 pipe_config->gmch_pfit.lvds_border_bits =
4984 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4985}
4986
0e8ffe1b
DV		 4987static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4988 struct intel_crtc_config *pipe_config)
4989{
4990 struct drm_device *dev = crtc->base.dev;
4991 struct drm_i915_private *dev_priv = dev->dev_private;
4992 uint32_t tmp;
4993
e143a21c 4994 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 4995 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 4996
0e8ffe1b
DV		 4997 tmp = I915_READ(PIPECONF(crtc->pipe));
4998 if (!(tmp & PIPECONF_ENABLE))
4999 return false;
5000
1bd1bd80
DV		 5001 intel_get_pipe_timings(crtc, pipe_config);
5002
2fa2fe9a
DV		 5003 i9xx_get_pfit_config(crtc, pipe_config);
5004
6c49f241
DV		 5005 if (INTEL_INFO(dev)->gen >= 4) {
5006 tmp = I915_READ(DPLL_MD(crtc->pipe));
5007 pipe_config->pixel_multiplier =
5008 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5009 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 5010 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 5011 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5012 tmp = I915_READ(DPLL(crtc->pipe));
5013 pipe_config->pixel_multiplier =
5014 ((tmp & SDVO_MULTIPLIER_MASK)
5015 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5016 } else {
5017 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5018 * port and will be fixed up in the encoder->get_config
5019 * function. */
5020 pipe_config->pixel_multiplier = 1;
5021 }
8bcc2795
DV		 5022 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5023 if (!IS_VALLEYVIEW(dev)) {
5024 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5025 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 5026 } else {
5027 /* Mask out read-only status bits. */
5028 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5029 DPLL_PORTC_READY_MASK |
5030 DPLL_PORTB_READY_MASK);
8bcc2795 5031 }
6c49f241 5032
0e8ffe1b
DV		 5033 return true;
5034}
5035
dde86e2d 5036static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5037{
5038 struct drm_i915_private *dev_priv = dev->dev_private;
5039 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5040 struct intel_encoder *encoder;
74cfd7ac 5041 u32 val, final;
13d83a67 5042 bool has_lvds = false;
199e5d79 5043 bool has_cpu_edp = false;
199e5d79 5044 bool has_panel = false;
99eb6a01
KP		 5045 bool has_ck505 = false;
5046 bool can_ssc = false;
13d83a67
JB		 5047
5048 /* We need to take the global config into account */
199e5d79
KP		 5049 list_for_each_entry(encoder, &mode_config->encoder_list,
5050 base.head) {
5051 switch (encoder->type) {
5052 case INTEL_OUTPUT_LVDS:
5053 has_panel = true;
5054 has_lvds = true;
5055 break;
5056 case INTEL_OUTPUT_EDP:
5057 has_panel = true;
2de6905f 5058 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5059 has_cpu_edp = true;
5060 break;
13d83a67
JB		 5061 }
5062 }
5063
99eb6a01 5064 if (HAS_PCH_IBX(dev)) {
41aa3448 5065 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5066 can_ssc = has_ck505;
5067 } else {
5068 has_ck505 = false;
5069 can_ssc = true;
5070 }
5071
2de6905f
ID		 5072 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5073 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5074
5075 /* Ironlake: try to setup display ref clock before DPLL
5076 * enabling. This is only under driver's control after
5077 * PCH B stepping, previous chipset stepping should be
5078 * ignoring this setting.
5079 */
74cfd7ac
CW		 5080 val = I915_READ(PCH_DREF_CONTROL);
5081
5082 /* As we must carefully and slowly disable/enable each source in turn,
5083 * compute the final state we want first and check if we need to
5084 * make any changes at all.
5085 */
5086 final = val;
5087 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5088 if (has_ck505)
5089 final |= DREF_NONSPREAD_CK505_ENABLE;
5090 else
5091 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5092
5093 final &= ~DREF_SSC_SOURCE_MASK;
5094 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5095 final &= ~DREF_SSC1_ENABLE;
5096
5097 if (has_panel) {
5098 final |= DREF_SSC_SOURCE_ENABLE;
5099
5100 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5101 final |= DREF_SSC1_ENABLE;
5102
5103 if (has_cpu_edp) {
5104 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5105 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5106 else
5107 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5108 } else
5109 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5110 } else {
5111 final |= DREF_SSC_SOURCE_DISABLE;
5112 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5113 }
5114
5115 if (final == val)
5116 return;
5117
13d83a67 5118 /* Always enable nonspread source */
74cfd7ac 5119 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5120
99eb6a01 5121 if (has_ck505)
74cfd7ac 5122 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5123 else
74cfd7ac 5124 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5125
199e5d79 5126 if (has_panel) {
74cfd7ac
CW		 5127 val &= ~DREF_SSC_SOURCE_MASK;
5128 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5129
199e5d79 5130 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5131 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5132 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5133 val |= DREF_SSC1_ENABLE;
e77166b5 5134 } else
74cfd7ac 5135 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5136
5137 /* Get SSC going before enabling the outputs */
74cfd7ac 5138 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5139 POSTING_READ(PCH_DREF_CONTROL);
5140 udelay(200);
5141
74cfd7ac 5142 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5143
5144 /* Enable CPU source on CPU attached eDP */
199e5d79 5145 if (has_cpu_edp) {
99eb6a01 5146 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5147 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5148 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5149 }
13d83a67 5150 else
74cfd7ac 5151 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5152 } else
74cfd7ac 5153 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5154
74cfd7ac 5155 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5156 POSTING_READ(PCH_DREF_CONTROL);
5157 udelay(200);
5158 } else {
5159 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5160
74cfd7ac 5161 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5162
5163 /* Turn off CPU output */
74cfd7ac 5164 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5165
74cfd7ac 5166 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5167 POSTING_READ(PCH_DREF_CONTROL);
5168 udelay(200);
5169
5170 /* Turn off the SSC source */
74cfd7ac
CW		 5171 val &= ~DREF_SSC_SOURCE_MASK;
5172 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5173
5174 /* Turn off SSC1 */
74cfd7ac 5175 val &= ~DREF_SSC1_ENABLE;
199e5d79 5176
74cfd7ac 5177 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5178 POSTING_READ(PCH_DREF_CONTROL);
5179 udelay(200);
5180 }
74cfd7ac
CW		 5181
5182 BUG_ON(val != final);
13d83a67
JB		 5183}
5184
f31f2d55 5185static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 5186{
f31f2d55 5187 uint32_t tmp;
dde86e2d 5188
0ff066a9
PZ		 5189 tmp = I915_READ(SOUTH_CHICKEN2);
5190 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5191 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5192
0ff066a9
PZ		 5193 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5194 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5195 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 5196
0ff066a9
PZ		 5197 tmp = I915_READ(SOUTH_CHICKEN2);
5198 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5199 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5200
0ff066a9
PZ		 5201 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5202 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5203 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 5204}
5205
5206/* WaMPhyProgramming:hsw */
5207static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5208{
5209 uint32_t tmp;
dde86e2d
PZ		 5210
5211 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5212 tmp &= ~(0xFF << 24);
5213 tmp |= (0x12 << 24);
5214 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5215
dde86e2d
PZ		 5216 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5217 tmp |= (1 << 11);
5218 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5219
5220 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5221 tmp |= (1 << 11);
5222 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5223
dde86e2d
PZ		 5224 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5225 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5226 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5227
5228 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5229 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5230 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5231
0ff066a9
PZ		 5232 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5233 tmp &= ~(7 << 13);
5234 tmp |= (5 << 13);
5235 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 5236
0ff066a9
PZ		 5237 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5238 tmp &= ~(7 << 13);
5239 tmp |= (5 << 13);
5240 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 5241
5242 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5243 tmp &= ~0xFF;
5244 tmp |= 0x1C;
5245 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5246
5247 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5248 tmp &= ~0xFF;
5249 tmp |= 0x1C;
5250 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5251
5252 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5253 tmp &= ~(0xFF << 16);
5254 tmp |= (0x1C << 16);
5255 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5256
5257 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5258 tmp &= ~(0xFF << 16);
5259 tmp |= (0x1C << 16);
5260 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5261
0ff066a9
PZ		 5262 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5263 tmp |= (1 << 27);
5264 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 5265
0ff066a9
PZ		 5266 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5267 tmp |= (1 << 27);
5268 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 5269
0ff066a9
PZ		 5270 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5271 tmp &= ~(0xF << 28);
5272 tmp |= (4 << 28);
5273 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 5274
0ff066a9
PZ		 5275 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5276 tmp &= ~(0xF << 28);
5277 tmp |= (4 << 28);
5278 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 5279}
5280
2fa86a1f
PZ		 5281/* Implements 3 different sequences from BSpec chapter "Display iCLK
5282 * Programming" based on the parameters passed:
5283 * - Sequence to enable CLKOUT_DP
5284 * - Sequence to enable CLKOUT_DP without spread
5285 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5286 */
5287static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5288 bool with_fdi)
f31f2d55
PZ		 5289{
5290 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 5291 uint32_t reg, tmp;
5292
5293 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5294 with_spread = true;
5295 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5296 with_fdi, "LP PCH doesn't have FDI\n"))
5297 with_fdi = false;
f31f2d55
PZ		 5298
5299 mutex_lock(&dev_priv->dpio_lock);
5300
5301 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5302 tmp &= ~SBI_SSCCTL_DISABLE;
5303 tmp |= SBI_SSCCTL_PATHALT;
5304 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5305
5306 udelay(24);
5307
2fa86a1f
PZ		 5308 if (with_spread) {
5309 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5310 tmp &= ~SBI_SSCCTL_PATHALT;
5311 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 5312
2fa86a1f
PZ		 5313 if (with_fdi) {
5314 lpt_reset_fdi_mphy(dev_priv);
5315 lpt_program_fdi_mphy(dev_priv);
5316 }
5317 }
dde86e2d 5318
2fa86a1f
PZ		 5319 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5320 SBI_GEN0 : SBI_DBUFF0;
5321 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5322 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5323 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 5324
5325 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5326}
5327
47701c3b
PZ		 5328/* Sequence to disable CLKOUT_DP */
5329static void lpt_disable_clkout_dp(struct drm_device *dev)
5330{
5331 struct drm_i915_private *dev_priv = dev->dev_private;
5332 uint32_t reg, tmp;
5333
5334 mutex_lock(&dev_priv->dpio_lock);
5335
5336 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5337 SBI_GEN0 : SBI_DBUFF0;
5338 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5339 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5340 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5341
5342 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5343 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5344 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5345 tmp |= SBI_SSCCTL_PATHALT;
5346 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5347 udelay(32);
5348 }
5349 tmp |= SBI_SSCCTL_DISABLE;
5350 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5351 }
5352
5353 mutex_unlock(&dev_priv->dpio_lock);
5354}
5355
bf8fa3d3
PZ		 5356static void lpt_init_pch_refclk(struct drm_device *dev)
5357{
5358 struct drm_mode_config *mode_config = &dev->mode_config;
5359 struct intel_encoder *encoder;
5360 bool has_vga = false;
5361
5362 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5363 switch (encoder->type) {
5364 case INTEL_OUTPUT_ANALOG:
5365 has_vga = true;
5366 break;
5367 }
5368 }
5369
47701c3b
PZ		 5370 if (has_vga)
5371 lpt_enable_clkout_dp(dev, true, true);
5372 else
5373 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 5374}
5375
dde86e2d
PZ		 5376/*
5377 * Initialize reference clocks when the driver loads
5378 */
5379void intel_init_pch_refclk(struct drm_device *dev)
5380{
5381 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5382 ironlake_init_pch_refclk(dev);
5383 else if (HAS_PCH_LPT(dev))
5384 lpt_init_pch_refclk(dev);
5385}
5386
d9d444cb
JB		 5387static int ironlake_get_refclk(struct drm_crtc *crtc)
5388{
5389 struct drm_device *dev = crtc->dev;
5390 struct drm_i915_private *dev_priv = dev->dev_private;
5391 struct intel_encoder *encoder;
d9d444cb
JB		 5392 int num_connectors = 0;
5393 bool is_lvds = false;
5394
6c2b7c12 5395 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5396 switch (encoder->type) {
5397 case INTEL_OUTPUT_LVDS:
5398 is_lvds = true;
5399 break;
d9d444cb
JB		 5400 }
5401 num_connectors++;
5402 }
5403
5404 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5405 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5406 dev_priv->vbt.lvds_ssc_freq);
5407 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5408 }
5409
5410 return 120000;
5411}
5412
6ff93609 5413static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5414{
c8203565 5415 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5416 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5417 int pipe = intel_crtc->pipe;
c8203565
PZ		 5418 uint32_t val;
5419
78114071 5420 val = 0;
c8203565 5421
965e0c48 5422 switch (intel_crtc->config.pipe_bpp) {
c8203565 5423 case 18:
dfd07d72 5424 val |= PIPECONF_6BPC;
c8203565
PZ		 5425 break;
5426 case 24:
dfd07d72 5427 val |= PIPECONF_8BPC;
c8203565
PZ		 5428 break;
5429 case 30:
dfd07d72 5430 val |= PIPECONF_10BPC;
c8203565
PZ		 5431 break;
5432 case 36:
dfd07d72 5433 val |= PIPECONF_12BPC;
c8203565
PZ		 5434 break;
5435 default:
cc769b62
PZ		 5436 /* Case prevented by intel_choose_pipe_bpp_dither. */
5437 BUG();
c8203565
PZ		 5438 }
5439
d8b32247 5440 if (intel_crtc->config.dither)
c8203565
PZ		 5441 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5442
6ff93609 5443 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5444 val |= PIPECONF_INTERLACED_ILK;
5445 else
5446 val |= PIPECONF_PROGRESSIVE;
5447
50f3b016 5448 if (intel_crtc->config.limited_color_range)
3685a8f3 5449 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 5450
c8203565
PZ		 5451 I915_WRITE(PIPECONF(pipe), val);
5452 POSTING_READ(PIPECONF(pipe));
5453}
5454
86d3efce
VS		 5455/*
5456 * Set up the pipe CSC unit.
5457 *
5458 * Currently only full range RGB to limited range RGB conversion
5459 * is supported, but eventually this should handle various
5460 * RGB<->YCbCr scenarios as well.
5461 */
50f3b016 5462static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5463{
5464 struct drm_device *dev = crtc->dev;
5465 struct drm_i915_private *dev_priv = dev->dev_private;
5466 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5467 int pipe = intel_crtc->pipe;
5468 uint16_t coeff = 0x7800; /* 1.0 */
5469
5470 /*
5471 * TODO: Check what kind of values actually come out of the pipe
5472 * with these coeff/postoff values and adjust to get the best
5473 * accuracy. Perhaps we even need to take the bpc value into
5474 * consideration.
5475 */
5476
50f3b016 5477 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5478 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5479
5480 /*
5481 * GY/GU and RY/RU should be the other way around according
5482 * to BSpec, but reality doesn't agree. Just set them up in
5483 * a way that results in the correct picture.
5484 */
5485 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5486 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5487
5488 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5489 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5490
5491 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5492 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5493
5494 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5495 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5496 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5497
5498 if (INTEL_INFO(dev)->gen > 6) {
5499 uint16_t postoff = 0;
5500
50f3b016 5501 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5502 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5503
5504 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5505 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5506 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5507
5508 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5509 } else {
5510 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5511
50f3b016 5512 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5513 mode |= CSC_BLACK_SCREEN_OFFSET;
5514
5515 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5516 }
5517}
5518
6ff93609 5519static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5520{
5521 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5522 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5523 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5524 uint32_t val;
5525
3eff4faa 5526 val = 0;
ee2b0b38 5527
d8b32247 5528 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5529 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5530
6ff93609 5531 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5532 val |= PIPECONF_INTERLACED_ILK;
5533 else
5534 val |= PIPECONF_PROGRESSIVE;
5535
702e7a56
PZ		 5536 I915_WRITE(PIPECONF(cpu_transcoder), val);
5537 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 5538
5539 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5540 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
ee2b0b38
PZ		 5541}
5542
6591c6e4 5543static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5544 intel_clock_t *clock,
5545 bool *has_reduced_clock,
5546 intel_clock_t *reduced_clock)
5547{
5548 struct drm_device *dev = crtc->dev;
5549 struct drm_i915_private *dev_priv = dev->dev_private;
5550 struct intel_encoder *intel_encoder;
5551 int refclk;
d4906093 5552 const intel_limit_t *limit;
a16af721 5553 bool ret, is_lvds = false;
79e53945 5554
6591c6e4
PZ		 5555 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5556 switch (intel_encoder->type) {
79e53945
JB		 5557 case INTEL_OUTPUT_LVDS:
5558 is_lvds = true;
5559 break;
79e53945
JB		 5560 }
5561 }
5562
d9d444cb 5563 refclk = ironlake_get_refclk(crtc);
79e53945 5564
d4906093
ML		 5565 /*
5566 * Returns a set of divisors for the desired target clock with the given
5567 * refclk, or FALSE. The returned values represent the clock equation:
5568 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5569 */
1b894b59 5570 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5571 ret = dev_priv->display.find_dpll(limit, crtc,
5572 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5573 refclk, NULL, clock);
6591c6e4
PZ		 5574 if (!ret)
5575 return false;
cda4b7d3 5576
ddc9003c 5577 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5578 /*
5579 * Ensure we match the reduced clock's P to the target clock.
5580 * If the clocks don't match, we can't switch the display clock
5581 * by using the FP0/FP1. In such case we will disable the LVDS
5582 * downclock feature.
5583 */
ee9300bb
DV		 5584 *has_reduced_clock =
5585 dev_priv->display.find_dpll(limit, crtc,
5586 dev_priv->lvds_downclock,
5587 refclk, clock,
5588 reduced_clock);
652c393a 5589 }
61e9653f 5590
6591c6e4
PZ		 5591 return true;
5592}
5593
01a415fd
DV		 5594static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5595{
5596 struct drm_i915_private *dev_priv = dev->dev_private;
5597 uint32_t temp;
5598
5599 temp = I915_READ(SOUTH_CHICKEN1);
5600 if (temp & FDI_BC_BIFURCATION_SELECT)
5601 return;
5602
5603 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5604 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5605
5606 temp |= FDI_BC_BIFURCATION_SELECT;
5607 DRM_DEBUG_KMS("enabling fdi C rx\n");
5608 I915_WRITE(SOUTH_CHICKEN1, temp);
5609 POSTING_READ(SOUTH_CHICKEN1);
5610}
5611
ebfd86fd 5612static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
01a415fd
DV		 5613{
5614 struct drm_device *dev = intel_crtc->base.dev;
5615 struct drm_i915_private *dev_priv = dev->dev_private;
01a415fd
DV		 5616
5617 switch (intel_crtc->pipe) {
5618 case PIPE_A:
ebfd86fd 5619 break;
01a415fd 5620 case PIPE_B:
ebfd86fd 5621 if (intel_crtc->config.fdi_lanes > 2)
01a415fd
DV		 5622 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5623 else
5624 cpt_enable_fdi_bc_bifurcation(dev);
5625
ebfd86fd 5626 break;
01a415fd 5627 case PIPE_C:
01a415fd
DV		 5628 cpt_enable_fdi_bc_bifurcation(dev);
5629
ebfd86fd 5630 break;
01a415fd
DV		 5631 default:
5632 BUG();
5633 }
5634}
5635
d4b1931c
PZ		 5636int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5637{
5638 /*
5639 * Account for spread spectrum to avoid
5640 * oversubscribing the link. Max center spread
5641 * is 2.5%; use 5% for safety's sake.
5642 */
5643 u32 bps = target_clock * bpp * 21 / 20;
5644 return bps / (link_bw * 8) + 1;
5645}
5646
7429e9d4 5647static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 5648{
7429e9d4 5649 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 5650}
5651
de13a2e3 5652static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5653 u32 *fp,
9a7c7890 5654 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5655{
de13a2e3 5656 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5657 struct drm_device *dev = crtc->dev;
5658 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5659 struct intel_encoder *intel_encoder;
5660 uint32_t dpll;
6cc5f341 5661 int factor, num_connectors = 0;
09ede541 5662 bool is_lvds = false, is_sdvo = false;
79e53945 5663
de13a2e3
PZ		 5664 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5665 switch (intel_encoder->type) {
79e53945
JB		 5666 case INTEL_OUTPUT_LVDS:
5667 is_lvds = true;
5668 break;
5669 case INTEL_OUTPUT_SDVO:
7d57382e 5670 case INTEL_OUTPUT_HDMI:
79e53945 5671 is_sdvo = true;
79e53945 5672 break;
79e53945 5673 }
43565a06 5674
c751ce4f 5675 num_connectors++;
79e53945 5676 }
79e53945 5677
c1858123 5678 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5679 factor = 21;
5680 if (is_lvds) {
5681 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5682 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5683 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5684 factor = 25;
09ede541 5685 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5686 factor = 20;
c1858123 5687
7429e9d4 5688 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5689 *fp |= FP_CB_TUNE;
2c07245f 5690
9a7c7890
DV		 5691 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5692 *fp2 |= FP_CB_TUNE;
5693
5eddb70b 5694 dpll = 0;
2c07245f 5695
a07d6787
EA		 5696 if (is_lvds)
5697 dpll |= DPLLB_MODE_LVDS;
5698 else
5699 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5700
ef1b460d
DV		 5701 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5702 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5703
5704 if (is_sdvo)
4a33e48d 5705 dpll |= DPLL_SDVO_HIGH_SPEED;
9566e9af 5706 if (intel_crtc->config.has_dp_encoder)
4a33e48d 5707 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 5708
a07d6787 5709 /* compute bitmask from p1 value */
7429e9d4 5710 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5711 /* also FPA1 */
7429e9d4 5712 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5713
7429e9d4 5714 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5715 case 5:
5716 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5717 break;
5718 case 7:
5719 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5720 break;
5721 case 10:
5722 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5723 break;
5724 case 14:
5725 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5726 break;
79e53945
JB		 5727 }
5728
b4c09f3b 5729 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5730 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5731 else
5732 dpll |= PLL_REF_INPUT_DREFCLK;
5733
959e16d6 5734 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 5735}
5736
5737static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5738 int x, int y,
5739 struct drm_framebuffer *fb)
5740{
5741 struct drm_device *dev = crtc->dev;
5742 struct drm_i915_private *dev_priv = dev->dev_private;
5743 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5744 int pipe = intel_crtc->pipe;
5745 int plane = intel_crtc->plane;
5746 int num_connectors = 0;
5747 intel_clock_t clock, reduced_clock;
cbbab5bd 5748 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5749 bool ok, has_reduced_clock = false;
8b47047b 5750 bool is_lvds = false;
de13a2e3 5751 struct intel_encoder *encoder;
e2b78267 5752 struct intel_shared_dpll *pll;
de13a2e3 5753 int ret;
de13a2e3
PZ		 5754
5755 for_each_encoder_on_crtc(dev, crtc, encoder) {
5756 switch (encoder->type) {
5757 case INTEL_OUTPUT_LVDS:
5758 is_lvds = true;
5759 break;
de13a2e3
PZ		 5760 }
5761
5762 num_connectors++;
a07d6787 5763 }
79e53945 5764
5dc5298b
PZ		 5765 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5766 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5767
ff9a6750 5768 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 5769 &has_reduced_clock, &reduced_clock);
ee9300bb 5770 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 5771 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5772 return -EINVAL;
79e53945 5773 }
f47709a9
DV		 5774 /* Compat-code for transition, will disappear. */
5775 if (!intel_crtc->config.clock_set) {
5776 intel_crtc->config.dpll.n = clock.n;
5777 intel_crtc->config.dpll.m1 = clock.m1;
5778 intel_crtc->config.dpll.m2 = clock.m2;
5779 intel_crtc->config.dpll.p1 = clock.p1;
5780 intel_crtc->config.dpll.p2 = clock.p2;
5781 }
79e53945 5782
de13a2e3
PZ		 5783 /* Ensure that the cursor is valid for the new mode before changing... */
5784 intel_crtc_update_cursor(crtc, true);
5785
5dc5298b 5786 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5787 if (intel_crtc->config.has_pch_encoder) {
7429e9d4 5788 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5789 if (has_reduced_clock)
7429e9d4 5790 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5791
7429e9d4 5792 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5793 &fp, &reduced_clock,
5794 has_reduced_clock ? &fp2 : NULL);
5795
959e16d6 5796 intel_crtc->config.dpll_hw_state.dpll = dpll;
66e985c0
DV		 5797 intel_crtc->config.dpll_hw_state.fp0 = fp;
5798 if (has_reduced_clock)
5799 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5800 else
5801 intel_crtc->config.dpll_hw_state.fp1 = fp;
5802
b89a1d39 5803 pll = intel_get_shared_dpll(intel_crtc);
ee7b9f93 5804 if (pll == NULL) {
84f44ce7
VS		 5805 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5806 pipe_name(pipe));
4b645f14
JB		 5807 return -EINVAL;
5808 }
ee7b9f93 5809 } else
e72f9fbf 5810 intel_put_shared_dpll(intel_crtc);
79e53945 5811
03afc4a2
DV		 5812 if (intel_crtc->config.has_dp_encoder)
5813 intel_dp_set_m_n(intel_crtc);
79e53945 5814
bcd644e0
DV		 5815 if (is_lvds && has_reduced_clock && i915_powersave)
5816 intel_crtc->lowfreq_avail = true;
5817 else
5818 intel_crtc->lowfreq_avail = false;
e2b78267
DV		 5819
5820 if (intel_crtc->config.has_pch_encoder) {
5821 pll = intel_crtc_to_shared_dpll(intel_crtc);
5822
652c393a
JB		 5823 }
5824
8a654f3b 5825 intel_set_pipe_timings(intel_crtc);
5eddb70b 5826
ca3a0ff8 5827 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5828 intel_cpu_transcoder_set_m_n(intel_crtc,
5829 &intel_crtc->config.fdi_m_n);
5830 }
2c07245f 5831
ebfd86fd
DV		 5832 if (IS_IVYBRIDGE(dev))
5833 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
79e53945 5834
6ff93609 5835 ironlake_set_pipeconf(crtc);
79e53945 5836
a1f9e77e
PZ		 5837 /* Set up the display plane register */
5838 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5839 POSTING_READ(DSPCNTR(plane));
79e53945 5840
94352cf9 5841 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd 5842
1857e1da 5843 return ret;
79e53945
JB		 5844}
5845
72419203
DV		 5846static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5847 struct intel_crtc_config *pipe_config)
5848{
5849 struct drm_device *dev = crtc->base.dev;
5850 struct drm_i915_private *dev_priv = dev->dev_private;
5851 enum transcoder transcoder = pipe_config->cpu_transcoder;
5852
5853 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5854 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5855 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5856 & ~TU_SIZE_MASK;
5857 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5858 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5859 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5860}
5861
2fa2fe9a
DV		 5862static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5863 struct intel_crtc_config *pipe_config)
5864{
5865 struct drm_device *dev = crtc->base.dev;
5866 struct drm_i915_private *dev_priv = dev->dev_private;
5867 uint32_t tmp;
5868
5869 tmp = I915_READ(PF_CTL(crtc->pipe));
5870
5871 if (tmp & PF_ENABLE) {
5872 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5873 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 5874
5875 /* We currently do not free assignements of panel fitters on
5876 * ivb/hsw (since we don't use the higher upscaling modes which
5877 * differentiates them) so just WARN about this case for now. */
5878 if (IS_GEN7(dev)) {
5879 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5880 PF_PIPE_SEL_IVB(crtc->pipe));
5881 }
2fa2fe9a 5882 }
79e53945
JB		 5883}
5884
0e8ffe1b
DV		 5885static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5886 struct intel_crtc_config *pipe_config)
5887{
5888 struct drm_device *dev = crtc->base.dev;
5889 struct drm_i915_private *dev_priv = dev->dev_private;
5890 uint32_t tmp;
5891
e143a21c 5892 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 5893 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5894
0e8ffe1b
DV		 5895 tmp = I915_READ(PIPECONF(crtc->pipe));
5896 if (!(tmp & PIPECONF_ENABLE))
5897 return false;
5898
ab9412ba 5899 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 5900 struct intel_shared_dpll *pll;
5901
88adfff1
DV		 5902 pipe_config->has_pch_encoder = true;
5903
627eb5a3
DV		 5904 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5905 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5906 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5907
5908 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 5909
c0d43d62 5910 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 5911 pipe_config->shared_dpll =
5912 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 5913 } else {
5914 tmp = I915_READ(PCH_DPLL_SEL);
5915 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5916 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5917 else
5918 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5919 }
66e985c0
DV		 5920
5921 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5922
5923 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5924 &pipe_config->dpll_hw_state));
c93f54cf
DV		 5925
5926 tmp = pipe_config->dpll_hw_state.dpll;
5927 pipe_config->pixel_multiplier =
5928 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
5929 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6c49f241
DV		 5930 } else {
5931 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 5932 }
5933
1bd1bd80
DV		 5934 intel_get_pipe_timings(crtc, pipe_config);
5935
2fa2fe9a
DV		 5936 ironlake_get_pfit_config(crtc, pipe_config);
5937
0e8ffe1b
DV		 5938 return true;
5939}
5940
be256dc7
PZ		 5941static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
5942{
5943 struct drm_device *dev = dev_priv->dev;
5944 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
5945 struct intel_crtc *crtc;
5946 unsigned long irqflags;
bd633a7c 5947 uint32_t val;
be256dc7
PZ		 5948
5949 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
5950 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
5951 pipe_name(crtc->pipe));
5952
5953 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
5954 WARN(plls->spll_refcount, "SPLL enabled\n");
5955 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
5956 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
5957 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
5958 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
5959 "CPU PWM1 enabled\n");
5960 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
5961 "CPU PWM2 enabled\n");
5962 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
5963 "PCH PWM1 enabled\n");
5964 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
5965 "Utility pin enabled\n");
5966 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
5967
5968 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5969 val = I915_READ(DEIMR);
5970 WARN((val & ~DE_PCH_EVENT_IVB) != val,
5971 "Unexpected DEIMR bits enabled: 0x%x\n", val);
5972 val = I915_READ(SDEIMR);
bd633a7c 5973 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
be256dc7
PZ		 5974 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
5975 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5976}
5977
5978/*
5979 * This function implements pieces of two sequences from BSpec:
5980 * - Sequence for display software to disable LCPLL
5981 * - Sequence for display software to allow package C8+
5982 * The steps implemented here are just the steps that actually touch the LCPLL
5983 * register. Callers should take care of disabling all the display engine
5984 * functions, doing the mode unset, fixing interrupts, etc.
5985 */
5986void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
5987 bool switch_to_fclk, bool allow_power_down)
5988{
5989 uint32_t val;
5990
5991 assert_can_disable_lcpll(dev_priv);
5992
5993 val = I915_READ(LCPLL_CTL);
5994
5995 if (switch_to_fclk) {
5996 val |= LCPLL_CD_SOURCE_FCLK;
5997 I915_WRITE(LCPLL_CTL, val);
5998
5999 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6000 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6001 DRM_ERROR("Switching to FCLK failed\n");
6002
6003 val = I915_READ(LCPLL_CTL);
6004 }
6005
6006 val |= LCPLL_PLL_DISABLE;
6007 I915_WRITE(LCPLL_CTL, val);
6008 POSTING_READ(LCPLL_CTL);
6009
6010 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6011 DRM_ERROR("LCPLL still locked\n");
6012
6013 val = I915_READ(D_COMP);
6014 val |= D_COMP_COMP_DISABLE;
6015 I915_WRITE(D_COMP, val);
6016 POSTING_READ(D_COMP);
6017 ndelay(100);
6018
6019 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6020 DRM_ERROR("D_COMP RCOMP still in progress\n");
6021
6022 if (allow_power_down) {
6023 val = I915_READ(LCPLL_CTL);
6024 val |= LCPLL_POWER_DOWN_ALLOW;
6025 I915_WRITE(LCPLL_CTL, val);
6026 POSTING_READ(LCPLL_CTL);
6027 }
6028}
6029
6030/*
6031 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6032 * source.
6033 */
6034void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6035{
6036 uint32_t val;
6037
6038 val = I915_READ(LCPLL_CTL);
6039
6040 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6041 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6042 return;
6043
215733fa
PZ		 6044 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6045 * we'll hang the machine! */
6046 dev_priv->uncore.funcs.force_wake_get(dev_priv);
6047
be256dc7
PZ		 6048 if (val & LCPLL_POWER_DOWN_ALLOW) {
6049 val &= ~LCPLL_POWER_DOWN_ALLOW;
6050 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 6051 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 6052 }
6053
6054 val = I915_READ(D_COMP);
6055 val |= D_COMP_COMP_FORCE;
6056 val &= ~D_COMP_COMP_DISABLE;
6057 I915_WRITE(D_COMP, val);
35d8f2eb 6058 POSTING_READ(D_COMP);
be256dc7
PZ		 6059
6060 val = I915_READ(LCPLL_CTL);
6061 val &= ~LCPLL_PLL_DISABLE;
6062 I915_WRITE(LCPLL_CTL, val);
6063
6064 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6065 DRM_ERROR("LCPLL not locked yet\n");
6066
6067 if (val & LCPLL_CD_SOURCE_FCLK) {
6068 val = I915_READ(LCPLL_CTL);
6069 val &= ~LCPLL_CD_SOURCE_FCLK;
6070 I915_WRITE(LCPLL_CTL, val);
6071
6072 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6073 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6074 DRM_ERROR("Switching back to LCPLL failed\n");
6075 }
215733fa
PZ		 6076
6077 dev_priv->uncore.funcs.force_wake_put(dev_priv);
be256dc7
PZ		 6078}
6079
c67a470b
PZ		 6080void hsw_enable_pc8_work(struct work_struct *__work)
6081{
6082 struct drm_i915_private *dev_priv =
6083 container_of(to_delayed_work(__work), struct drm_i915_private,
6084 pc8.enable_work);
6085 struct drm_device *dev = dev_priv->dev;
6086 uint32_t val;
6087
6088 if (dev_priv->pc8.enabled)
6089 return;
6090
6091 DRM_DEBUG_KMS("Enabling package C8+\n");
6092
6093 dev_priv->pc8.enabled = true;
6094
6095 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6096 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6097 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6098 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6099 }
6100
6101 lpt_disable_clkout_dp(dev);
6102 hsw_pc8_disable_interrupts(dev);
6103 hsw_disable_lcpll(dev_priv, true, true);
6104}
6105
6106static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6107{
6108 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6109 WARN(dev_priv->pc8.disable_count < 1,
6110 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6111
6112 dev_priv->pc8.disable_count--;
6113 if (dev_priv->pc8.disable_count != 0)
6114 return;
6115
6116 schedule_delayed_work(&dev_priv->pc8.enable_work,
90058745 6117 msecs_to_jiffies(i915_pc8_timeout));
c67a470b
PZ		 6118}
6119
6120static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6121{
6122 struct drm_device *dev = dev_priv->dev;
6123 uint32_t val;
6124
6125 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6126 WARN(dev_priv->pc8.disable_count < 0,
6127 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6128
6129 dev_priv->pc8.disable_count++;
6130 if (dev_priv->pc8.disable_count != 1)
6131 return;
6132
6133 cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6134 if (!dev_priv->pc8.enabled)
6135 return;
6136
6137 DRM_DEBUG_KMS("Disabling package C8+\n");
6138
6139 hsw_restore_lcpll(dev_priv);
6140 hsw_pc8_restore_interrupts(dev);
6141 lpt_init_pch_refclk(dev);
6142
6143 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6144 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6145 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6146 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6147 }
6148
6149 intel_prepare_ddi(dev);
6150 i915_gem_init_swizzling(dev);
6151 mutex_lock(&dev_priv->rps.hw_lock);
6152 gen6_update_ring_freq(dev);
6153 mutex_unlock(&dev_priv->rps.hw_lock);
6154 dev_priv->pc8.enabled = false;
6155}
6156
6157void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6158{
6159 mutex_lock(&dev_priv->pc8.lock);
6160 __hsw_enable_package_c8(dev_priv);
6161 mutex_unlock(&dev_priv->pc8.lock);
6162}
6163
6164void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6165{
6166 mutex_lock(&dev_priv->pc8.lock);
6167 __hsw_disable_package_c8(dev_priv);
6168 mutex_unlock(&dev_priv->pc8.lock);
6169}
6170
6171static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6172{
6173 struct drm_device *dev = dev_priv->dev;
6174 struct intel_crtc *crtc;
6175 uint32_t val;
6176
6177 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6178 if (crtc->base.enabled)
6179 return false;
6180
6181 /* This case is still possible since we have the i915.disable_power_well
6182 * parameter and also the KVMr or something else might be requesting the
6183 * power well. */
6184 val = I915_READ(HSW_PWR_WELL_DRIVER);
6185 if (val != 0) {
6186 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6187 return false;
6188 }
6189
6190 return true;
6191}
6192
6193/* Since we're called from modeset_global_resources there's no way to
6194 * symmetrically increase and decrease the refcount, so we use
6195 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6196 * or not.
6197 */
6198static void hsw_update_package_c8(struct drm_device *dev)
6199{
6200 struct drm_i915_private *dev_priv = dev->dev_private;
6201 bool allow;
6202
6203 if (!i915_enable_pc8)
6204 return;
6205
6206 mutex_lock(&dev_priv->pc8.lock);
6207
6208 allow = hsw_can_enable_package_c8(dev_priv);
6209
6210 if (allow == dev_priv->pc8.requirements_met)
6211 goto done;
6212
6213 dev_priv->pc8.requirements_met = allow;
6214
6215 if (allow)
6216 __hsw_enable_package_c8(dev_priv);
6217 else
6218 __hsw_disable_package_c8(dev_priv);
6219
6220done:
6221 mutex_unlock(&dev_priv->pc8.lock);
6222}
6223
6224static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6225{
6226 if (!dev_priv->pc8.gpu_idle) {
6227 dev_priv->pc8.gpu_idle = true;
6228 hsw_enable_package_c8(dev_priv);
6229 }
6230}
6231
6232static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6233{
6234 if (dev_priv->pc8.gpu_idle) {
6235 dev_priv->pc8.gpu_idle = false;
6236 hsw_disable_package_c8(dev_priv);
6237 }
be256dc7
PZ		 6238}
6239
d6dd9eb1
DV		 6240static void haswell_modeset_global_resources(struct drm_device *dev)
6241{
d6dd9eb1
DV		 6242 bool enable = false;
6243 struct intel_crtc *crtc;
d6dd9eb1
DV		 6244
6245 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 6246 if (!crtc->base.enabled)
6247 continue;
d6dd9eb1 6248
e7a639c4
DV		 6249 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
6250 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 6251 enable = true;
6252 }
6253
d6dd9eb1 6254 intel_set_power_well(dev, enable);
c67a470b
PZ		 6255
6256 hsw_update_package_c8(dev);
d6dd9eb1
DV		 6257}
6258
09b4ddf9 6259static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 6260 int x, int y,
6261 struct drm_framebuffer *fb)
6262{
6263 struct drm_device *dev = crtc->dev;
6264 struct drm_i915_private *dev_priv = dev->dev_private;
6265 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 6266 int plane = intel_crtc->plane;
09b4ddf9 6267 int ret;
09b4ddf9 6268
ff9a6750 6269 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 6270 return -EINVAL;
6271
09b4ddf9
PZ		 6272 /* Ensure that the cursor is valid for the new mode before changing... */
6273 intel_crtc_update_cursor(crtc, true);
6274
03afc4a2
DV		 6275 if (intel_crtc->config.has_dp_encoder)
6276 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 6277
6278 intel_crtc->lowfreq_avail = false;
09b4ddf9 6279
8a654f3b 6280 intel_set_pipe_timings(intel_crtc);
09b4ddf9 6281
ca3a0ff8 6282 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 6283 intel_cpu_transcoder_set_m_n(intel_crtc,
6284 &intel_crtc->config.fdi_m_n);
6285 }
09b4ddf9 6286
6ff93609 6287 haswell_set_pipeconf(crtc);
09b4ddf9 6288
50f3b016 6289 intel_set_pipe_csc(crtc);
86d3efce 6290
09b4ddf9 6291 /* Set up the display plane register */
86d3efce 6292 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 6293 POSTING_READ(DSPCNTR(plane));
6294
6295 ret = intel_pipe_set_base(crtc, x, y, fb);
6296
1f803ee5 6297 return ret;
79e53945
JB		 6298}
6299
0e8ffe1b
DV		 6300static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6301 struct intel_crtc_config *pipe_config)
6302{
6303 struct drm_device *dev = crtc->base.dev;
6304 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 6305 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 6306 uint32_t tmp;
6307
e143a21c 6308 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 6309 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6310
eccb140b
DV		 6311 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6312 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6313 enum pipe trans_edp_pipe;
6314 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6315 default:
6316 WARN(1, "unknown pipe linked to edp transcoder\n");
6317 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6318 case TRANS_DDI_EDP_INPUT_A_ON:
6319 trans_edp_pipe = PIPE_A;
6320 break;
6321 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6322 trans_edp_pipe = PIPE_B;
6323 break;
6324 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6325 trans_edp_pipe = PIPE_C;
6326 break;
6327 }
6328
6329 if (trans_edp_pipe == crtc->pipe)
6330 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6331 }
6332
b97186f0 6333 if (!intel_display_power_enabled(dev,
eccb140b 6334 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 6335 return false;
6336
eccb140b 6337 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 6338 if (!(tmp & PIPECONF_ENABLE))
6339 return false;
6340
88adfff1 6341 /*
f196e6be 6342 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 6343 * DDI E. So just check whether this pipe is wired to DDI E and whether
6344 * the PCH transcoder is on.
6345 */
eccb140b 6346 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 6347 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 6348 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 6349 pipe_config->has_pch_encoder = true;
6350
627eb5a3
DV		 6351 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6352 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6353 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6354
6355 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 6356 }
6357
1bd1bd80
DV		 6358 intel_get_pipe_timings(crtc, pipe_config);
6359
2fa2fe9a
DV		 6360 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6361 if (intel_display_power_enabled(dev, pfit_domain))
6362 ironlake_get_pfit_config(crtc, pipe_config);
88adfff1 6363
42db64ef
PZ		 6364 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6365 (I915_READ(IPS_CTL) & IPS_ENABLE);
6366
6c49f241
DV		 6367 pipe_config->pixel_multiplier = 1;
6368
0e8ffe1b
DV		 6369 return true;
6370}
6371
f564048e 6372static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6373 int x, int y,
94352cf9 6374 struct drm_framebuffer *fb)
f564048e
EA		 6375{
6376 struct drm_device *dev = crtc->dev;
6377 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19 6378 struct intel_encoder *encoder;
0b701d27 6379 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 6380 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6381 int pipe = intel_crtc->pipe;
f564048e
EA		 6382 int ret;
6383
0b701d27 6384 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6385
b8cecdf5
DV		 6386 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6387
79e53945 6388 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6389
9256aa19
DV		 6390 if (ret != 0)
6391 return ret;
6392
6393 for_each_encoder_on_crtc(dev, crtc, encoder) {
6394 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6395 encoder->base.base.id,
6396 drm_get_encoder_name(&encoder->base),
6397 mode->base.id, mode->name);
36f2d1f1 6398 encoder->mode_set(encoder);
9256aa19
DV		 6399 }
6400
6401 return 0;
79e53945
JB		 6402}
6403
3a9627f4
WF		 6404static bool intel_eld_uptodate(struct drm_connector *connector,
6405 int reg_eldv, uint32_t bits_eldv,
6406 int reg_elda, uint32_t bits_elda,
6407 int reg_edid)
6408{
6409 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6410 uint8_t *eld = connector->eld;
6411 uint32_t i;
6412
6413 i = I915_READ(reg_eldv);
6414 i &= bits_eldv;
6415
6416 if (!eld[0])
6417 return !i;
6418
6419 if (!i)
6420 return false;
6421
6422 i = I915_READ(reg_elda);
6423 i &= ~bits_elda;
6424 I915_WRITE(reg_elda, i);
6425
6426 for (i = 0; i < eld[2]; i++)
6427 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6428 return false;
6429
6430 return true;
6431}
6432
e0dac65e
WF		 6433static void g4x_write_eld(struct drm_connector *connector,
6434 struct drm_crtc *crtc)
6435{
6436 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6437 uint8_t *eld = connector->eld;
6438 uint32_t eldv;
6439 uint32_t len;
6440 uint32_t i;
6441
6442 i = I915_READ(G4X_AUD_VID_DID);
6443
6444 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6445 eldv = G4X_ELDV_DEVCL_DEVBLC;
6446 else
6447 eldv = G4X_ELDV_DEVCTG;
6448
3a9627f4
WF		 6449 if (intel_eld_uptodate(connector,
6450 G4X_AUD_CNTL_ST, eldv,
6451 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6452 G4X_HDMIW_HDMIEDID))
6453 return;
6454
e0dac65e
WF		 6455 i = I915_READ(G4X_AUD_CNTL_ST);
6456 i &= ~(eldv | G4X_ELD_ADDR);
6457 len = (i >> 9) & 0x1f; /* ELD buffer size */
6458 I915_WRITE(G4X_AUD_CNTL_ST, i);
6459
6460 if (!eld[0])
6461 return;
6462
6463 len = min_t(uint8_t, eld[2], len);
6464 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6465 for (i = 0; i < len; i++)
6466 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6467
6468 i = I915_READ(G4X_AUD_CNTL_ST);
6469 i |= eldv;
6470 I915_WRITE(G4X_AUD_CNTL_ST, i);
6471}
6472
83358c85
WX		 6473static void haswell_write_eld(struct drm_connector *connector,
6474 struct drm_crtc *crtc)
6475{
6476 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6477 uint8_t *eld = connector->eld;
6478 struct drm_device *dev = crtc->dev;
7b9f35a6 6479 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6480 uint32_t eldv;
6481 uint32_t i;
6482 int len;
6483 int pipe = to_intel_crtc(crtc)->pipe;
6484 int tmp;
6485
6486 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6487 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6488 int aud_config = HSW_AUD_CFG(pipe);
6489 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6490
6491
6492 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6493
6494 /* Audio output enable */
6495 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6496 tmp = I915_READ(aud_cntrl_st2);
6497 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6498 I915_WRITE(aud_cntrl_st2, tmp);
6499
6500 /* Wait for 1 vertical blank */
6501 intel_wait_for_vblank(dev, pipe);
6502
6503 /* Set ELD valid state */
6504 tmp = I915_READ(aud_cntrl_st2);
6505 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6506 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6507 I915_WRITE(aud_cntrl_st2, tmp);
6508 tmp = I915_READ(aud_cntrl_st2);
6509 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6510
6511 /* Enable HDMI mode */
6512 tmp = I915_READ(aud_config);
6513 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6514 /* clear N_programing_enable and N_value_index */
6515 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6516 I915_WRITE(aud_config, tmp);
6517
6518 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6519
6520 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6521 intel_crtc->eld_vld = true;
83358c85
WX		 6522
6523 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6524 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6525 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6526 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6527 } else
6528 I915_WRITE(aud_config, 0);
6529
6530 if (intel_eld_uptodate(connector,
6531 aud_cntrl_st2, eldv,
6532 aud_cntl_st, IBX_ELD_ADDRESS,
6533 hdmiw_hdmiedid))
6534 return;
6535
6536 i = I915_READ(aud_cntrl_st2);
6537 i &= ~eldv;
6538 I915_WRITE(aud_cntrl_st2, i);
6539
6540 if (!eld[0])
6541 return;
6542
6543 i = I915_READ(aud_cntl_st);
6544 i &= ~IBX_ELD_ADDRESS;
6545 I915_WRITE(aud_cntl_st, i);
6546 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6547 DRM_DEBUG_DRIVER("port num:%d\n", i);
6548
6549 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6550 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6551 for (i = 0; i < len; i++)
6552 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6553
6554 i = I915_READ(aud_cntrl_st2);
6555 i |= eldv;
6556 I915_WRITE(aud_cntrl_st2, i);
6557
6558}
6559
e0dac65e
WF		 6560static void ironlake_write_eld(struct drm_connector *connector,
6561 struct drm_crtc *crtc)
6562{
6563 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6564 uint8_t *eld = connector->eld;
6565 uint32_t eldv;
6566 uint32_t i;
6567 int len;
6568 int hdmiw_hdmiedid;
b6daa025 6569 int aud_config;
e0dac65e
WF		 6570 int aud_cntl_st;
6571 int aud_cntrl_st2;
9b138a83 6572 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6573
b3f33cbf 6574 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6575 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6576 aud_config = IBX_AUD_CFG(pipe);
6577 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6578 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6579 } else {
9b138a83
WX		 6580 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6581 aud_config = CPT_AUD_CFG(pipe);
6582 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6583 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6584 }
6585
9b138a83 6586 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6587
6588 i = I915_READ(aud_cntl_st);
9b138a83 6589 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6590 if (!i) {
6591 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6592 /* operate blindly on all ports */
1202b4c6
WF		 6593 eldv = IBX_ELD_VALIDB;
6594 eldv |= IBX_ELD_VALIDB << 4;
6595 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6596 } else {
2582a850 6597 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6598 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6599 }
6600
3a9627f4
WF		 6601 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6602 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6603 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6604 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6605 } else
6606 I915_WRITE(aud_config, 0);
e0dac65e 6607
3a9627f4
WF		 6608 if (intel_eld_uptodate(connector,
6609 aud_cntrl_st2, eldv,
6610 aud_cntl_st, IBX_ELD_ADDRESS,
6611 hdmiw_hdmiedid))
6612 return;
6613
e0dac65e
WF		 6614 i = I915_READ(aud_cntrl_st2);
6615 i &= ~eldv;
6616 I915_WRITE(aud_cntrl_st2, i);
6617
6618 if (!eld[0])
6619 return;
6620
e0dac65e 6621 i = I915_READ(aud_cntl_st);
1202b4c6 6622 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6623 I915_WRITE(aud_cntl_st, i);
6624
6625 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6626 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6627 for (i = 0; i < len; i++)
6628 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6629
6630 i = I915_READ(aud_cntrl_st2);
6631 i |= eldv;
6632 I915_WRITE(aud_cntrl_st2, i);
6633}
6634
6635void intel_write_eld(struct drm_encoder *encoder,
6636 struct drm_display_mode *mode)
6637{
6638 struct drm_crtc *crtc = encoder->crtc;
6639 struct drm_connector *connector;
6640 struct drm_device *dev = encoder->dev;
6641 struct drm_i915_private *dev_priv = dev->dev_private;
6642
6643 connector = drm_select_eld(encoder, mode);
6644 if (!connector)
6645 return;
6646
6647 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6648 connector->base.id,
6649 drm_get_connector_name(connector),
6650 connector->encoder->base.id,
6651 drm_get_encoder_name(connector->encoder));
6652
6653 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6654
6655 if (dev_priv->display.write_eld)
6656 dev_priv->display.write_eld(connector, crtc);
6657}
6658
79e53945
JB		 6659/** Loads the palette/gamma unit for the CRTC with the prepared values */
6660void intel_crtc_load_lut(struct drm_crtc *crtc)
6661{
6662 struct drm_device *dev = crtc->dev;
6663 struct drm_i915_private *dev_priv = dev->dev_private;
6664 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
42db64ef
PZ		 6665 enum pipe pipe = intel_crtc->pipe;
6666 int palreg = PALETTE(pipe);
79e53945 6667 int i;
42db64ef 6668 bool reenable_ips = false;
79e53945
JB		 6669
6670 /* The clocks have to be on to load the palette. */
aed3f09d 6671 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6672 return;
6673
23538ef1
JN		 6674 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
6675 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
6676 assert_dsi_pll_enabled(dev_priv);
6677 else
6678 assert_pll_enabled(dev_priv, pipe);
6679 }
14420bd0 6680
f2b115e6 6681 /* use legacy palette for Ironlake */
bad720ff 6682 if (HAS_PCH_SPLIT(dev))
42db64ef
PZ		 6683 palreg = LGC_PALETTE(pipe);
6684
6685 /* Workaround : Do not read or write the pipe palette/gamma data while
6686 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6687 */
6688 if (intel_crtc->config.ips_enabled &&
6689 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6690 GAMMA_MODE_MODE_SPLIT)) {
6691 hsw_disable_ips(intel_crtc);
6692 reenable_ips = true;
6693 }
2c07245f 6694
79e53945
JB		 6695 for (i = 0; i < 256; i++) {
6696 I915_WRITE(palreg + 4 * i,
6697 (intel_crtc->lut_r[i] << 16) |
6698 (intel_crtc->lut_g[i] << 8) |
6699 intel_crtc->lut_b[i]);
6700 }
42db64ef
PZ		 6701
6702 if (reenable_ips)
6703 hsw_enable_ips(intel_crtc);
79e53945
JB		 6704}
6705
560b85bb
CW		 6706static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6707{
6708 struct drm_device *dev = crtc->dev;
6709 struct drm_i915_private *dev_priv = dev->dev_private;
6710 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6711 bool visible = base != 0;
6712 u32 cntl;
6713
6714 if (intel_crtc->cursor_visible == visible)
6715 return;
6716
9db4a9c7 6717 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6718 if (visible) {
6719 /* On these chipsets we can only modify the base whilst
6720 * the cursor is disabled.
6721 */
9db4a9c7 6722 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6723
6724 cntl &= ~(CURSOR_FORMAT_MASK);
6725 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6726 cntl |= CURSOR_ENABLE |
6727 CURSOR_GAMMA_ENABLE |
6728 CURSOR_FORMAT_ARGB;
6729 } else
6730 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6731 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6732
6733 intel_crtc->cursor_visible = visible;
6734}
6735
6736static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6737{
6738 struct drm_device *dev = crtc->dev;
6739 struct drm_i915_private *dev_priv = dev->dev_private;
6740 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6741 int pipe = intel_crtc->pipe;
6742 bool visible = base != 0;
6743
6744 if (intel_crtc->cursor_visible != visible) {
548f245b 6745 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6746 if (base) {
6747 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6748 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6749 cntl |= pipe << 28; /* Connect to correct pipe */
6750 } else {
6751 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6752 cntl |= CURSOR_MODE_DISABLE;
6753 }
9db4a9c7 6754 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6755
6756 intel_crtc->cursor_visible = visible;
6757 }
6758 /* and commit changes on next vblank */
9db4a9c7 6759 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6760}
6761
65a21cd6
JB		 6762static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6763{
6764 struct drm_device *dev = crtc->dev;
6765 struct drm_i915_private *dev_priv = dev->dev_private;
6766 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6767 int pipe = intel_crtc->pipe;
6768 bool visible = base != 0;
6769
6770 if (intel_crtc->cursor_visible != visible) {
6771 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6772 if (base) {
6773 cntl &= ~CURSOR_MODE;
6774 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6775 } else {
6776 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6777 cntl |= CURSOR_MODE_DISABLE;
6778 }
1f5d76db 6779 if (IS_HASWELL(dev)) {
86d3efce 6780 cntl |= CURSOR_PIPE_CSC_ENABLE;
1f5d76db
PZ		 6781 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
6782 }
65a21cd6
JB		 6783 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6784
6785 intel_crtc->cursor_visible = visible;
6786 }
6787 /* and commit changes on next vblank */
6788 I915_WRITE(CURBASE_IVB(pipe), base);
6789}
6790
cda4b7d3 6791/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6792static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6793 bool on)
cda4b7d3
CW		 6794{
6795 struct drm_device *dev = crtc->dev;
6796 struct drm_i915_private *dev_priv = dev->dev_private;
6797 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6798 int pipe = intel_crtc->pipe;
6799 int x = intel_crtc->cursor_x;
6800 int y = intel_crtc->cursor_y;
560b85bb 6801 u32 base, pos;
cda4b7d3
CW		 6802 bool visible;
6803
6804 pos = 0;
6805
6b383a7f 6806 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6807 base = intel_crtc->cursor_addr;
6808 if (x > (int) crtc->fb->width)
6809 base = 0;
6810
6811 if (y > (int) crtc->fb->height)
6812 base = 0;
6813 } else
6814 base = 0;
6815
6816 if (x < 0) {
6817 if (x + intel_crtc->cursor_width < 0)
6818 base = 0;
6819
6820 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6821 x = -x;
6822 }
6823 pos |= x << CURSOR_X_SHIFT;
6824
6825 if (y < 0) {
6826 if (y + intel_crtc->cursor_height < 0)
6827 base = 0;
6828
6829 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6830 y = -y;
6831 }
6832 pos |= y << CURSOR_Y_SHIFT;
6833
6834 visible = base != 0;
560b85bb 6835 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6836 return;
6837
0cd83aa9 6838 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6839 I915_WRITE(CURPOS_IVB(pipe), pos);
6840 ivb_update_cursor(crtc, base);
6841 } else {
6842 I915_WRITE(CURPOS(pipe), pos);
6843 if (IS_845G(dev) || IS_I865G(dev))
6844 i845_update_cursor(crtc, base);
6845 else
6846 i9xx_update_cursor(crtc, base);
6847 }
cda4b7d3
CW		 6848}
6849
79e53945 6850static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6851 struct drm_file *file,
79e53945
JB		 6852 uint32_t handle,
6853 uint32_t width, uint32_t height)
6854{
6855 struct drm_device *dev = crtc->dev;
6856 struct drm_i915_private *dev_priv = dev->dev_private;
6857 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6858 struct drm_i915_gem_object *obj;
cda4b7d3 6859 uint32_t addr;
3f8bc370 6860 int ret;
79e53945 6861
79e53945
JB		 6862 /* if we want to turn off the cursor ignore width and height */
6863 if (!handle) {
28c97730 6864 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6865 addr = 0;
05394f39 6866 obj = NULL;
5004417d 6867 mutex_lock(&dev->struct_mutex);
3f8bc370 6868 goto finish;
79e53945
JB		 6869 }
6870
6871 /* Currently we only support 64x64 cursors */
6872 if (width != 64 || height != 64) {
6873 DRM_ERROR("we currently only support 64x64 cursors\n");
6874 return -EINVAL;
6875 }
6876
05394f39 6877 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6878 if (&obj->base == NULL)
79e53945
JB		 6879 return -ENOENT;
6880
05394f39 6881 if (obj->base.size < width * height * 4) {
79e53945 6882 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6883 ret = -ENOMEM;
6884 goto fail;
79e53945
JB		 6885 }
6886
71acb5eb 6887 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6888 mutex_lock(&dev->struct_mutex);
b295d1b6 6889 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6890 unsigned alignment;
6891
d9e86c0e
CW		 6892 if (obj->tiling_mode) {
6893 DRM_ERROR("cursor cannot be tiled\n");
6894 ret = -EINVAL;
6895 goto fail_locked;
6896 }
6897
693db184
CW		 6898 /* Note that the w/a also requires 2 PTE of padding following
6899 * the bo. We currently fill all unused PTE with the shadow
6900 * page and so we should always have valid PTE following the
6901 * cursor preventing the VT-d warning.
6902 */
6903 alignment = 0;
6904 if (need_vtd_wa(dev))
6905 alignment = 64*1024;
6906
6907 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6908 if (ret) {
6909 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6910 goto fail_locked;
e7b526bb
CW		 6911 }
6912
d9e86c0e
CW		 6913 ret = i915_gem_object_put_fence(obj);
6914 if (ret) {
2da3b9b9 6915 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6916 goto fail_unpin;
6917 }
6918
f343c5f6 6919 addr = i915_gem_obj_ggtt_offset(obj);
71acb5eb 6920 } else {
6eeefaf3 6921 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6922 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6923 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6924 align);
71acb5eb
DA		 6925 if (ret) {
6926 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6927 goto fail_locked;
71acb5eb 6928 }
05394f39 6929 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6930 }
6931
a6c45cf0 6932 if (IS_GEN2(dev))
14b60391
JB		 6933 I915_WRITE(CURSIZE, (height << 12) | width);
6934
3f8bc370 6935 finish:
3f8bc370 6936 if (intel_crtc->cursor_bo) {
b295d1b6 6937 if (dev_priv->info->cursor_needs_physical) {
05394f39 6938 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6939 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6940 } else
cc98b413 6941 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
05394f39 6942 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6943 }
80824003 6944
7f9872e0 6945 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6946
6947 intel_crtc->cursor_addr = addr;
05394f39 6948 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6949 intel_crtc->cursor_width = width;
6950 intel_crtc->cursor_height = height;
6951
40ccc72b 6952 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 6953
79e53945 6954 return 0;
e7b526bb 6955fail_unpin:
cc98b413 6956 i915_gem_object_unpin_from_display_plane(obj);
7f9872e0 6957fail_locked:
34b8686e 6958 mutex_unlock(&dev->struct_mutex);
bc9025bd 6959fail:
05394f39 6960 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6961 return ret;
79e53945
JB		 6962}
6963
6964static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6965{
79e53945 6966 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6967
cda4b7d3
CW		 6968 intel_crtc->cursor_x = x;
6969 intel_crtc->cursor_y = y;
652c393a 6970
40ccc72b 6971 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 6972
6973 return 0;
6974}
6975
6976/** Sets the color ramps on behalf of RandR */
6977void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6978 u16 blue, int regno)
6979{
6980 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6981
6982 intel_crtc->lut_r[regno] = red >> 8;
6983 intel_crtc->lut_g[regno] = green >> 8;
6984 intel_crtc->lut_b[regno] = blue >> 8;
6985}
6986
b8c00ac5
DA		 6987void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6988 u16 *blue, int regno)
6989{
6990 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6991
6992 *red = intel_crtc->lut_r[regno] << 8;
6993 *green = intel_crtc->lut_g[regno] << 8;
6994 *blue = intel_crtc->lut_b[regno] << 8;
6995}
6996
79e53945 6997static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6998 u16 *blue, uint32_t start, uint32_t size)
79e53945 6999{
7203425a 7000 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 7001 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7002
7203425a 7003 for (i = start; i < end; i++) {
79e53945
JB		 7004 intel_crtc->lut_r[i] = red[i] >> 8;
7005 intel_crtc->lut_g[i] = green[i] >> 8;
7006 intel_crtc->lut_b[i] = blue[i] >> 8;
7007 }
7008
7009 intel_crtc_load_lut(crtc);
7010}
7011
79e53945
JB		 7012/* VESA 640x480x72Hz mode to set on the pipe */
7013static struct drm_display_mode load_detect_mode = {
7014 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7015 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7016};
7017
d2dff872
CW		 7018static struct drm_framebuffer *
7019intel_framebuffer_create(struct drm_device *dev,
308e5bcb 7020 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 7021 struct drm_i915_gem_object *obj)
7022{
7023 struct intel_framebuffer *intel_fb;
7024 int ret;
7025
7026 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7027 if (!intel_fb) {
7028 drm_gem_object_unreference_unlocked(&obj->base);
7029 return ERR_PTR(-ENOMEM);
7030 }
7031
7032 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7033 if (ret) {
7034 drm_gem_object_unreference_unlocked(&obj->base);
7035 kfree(intel_fb);
7036 return ERR_PTR(ret);
7037 }
7038
7039 return &intel_fb->base;
7040}
7041
7042static u32
7043intel_framebuffer_pitch_for_width(int width, int bpp)
7044{
7045 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7046 return ALIGN(pitch, 64);
7047}
7048
7049static u32
7050intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7051{
7052 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7053 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7054}
7055
7056static struct drm_framebuffer *
7057intel_framebuffer_create_for_mode(struct drm_device *dev,
7058 struct drm_display_mode *mode,
7059 int depth, int bpp)
7060{
7061 struct drm_i915_gem_object *obj;
0fed39bd 7062 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 7063
7064 obj = i915_gem_alloc_object(dev,
7065 intel_framebuffer_size_for_mode(mode, bpp));
7066 if (obj == NULL)
7067 return ERR_PTR(-ENOMEM);
7068
7069 mode_cmd.width = mode->hdisplay;
7070 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 7071 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7072 bpp);
5ca0c34a 7073 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 7074
7075 return intel_framebuffer_create(dev, &mode_cmd, obj);
7076}
7077
7078static struct drm_framebuffer *
7079mode_fits_in_fbdev(struct drm_device *dev,
7080 struct drm_display_mode *mode)
7081{
7082 struct drm_i915_private *dev_priv = dev->dev_private;
7083 struct drm_i915_gem_object *obj;
7084 struct drm_framebuffer *fb;
7085
7086 if (dev_priv->fbdev == NULL)
7087 return NULL;
7088
7089 obj = dev_priv->fbdev->ifb.obj;
7090 if (obj == NULL)
7091 return NULL;
7092
7093 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 7094 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7095 fb->bits_per_pixel))
d2dff872
CW		 7096 return NULL;
7097
01f2c773 7098 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 7099 return NULL;
7100
7101 return fb;
7102}
7103
d2434ab7 7104bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 7105 struct drm_display_mode *mode,
8261b191 7106 struct intel_load_detect_pipe *old)
79e53945
JB		 7107{
7108 struct intel_crtc *intel_crtc;
d2434ab7
DV		 7109 struct intel_encoder *intel_encoder =
7110 intel_attached_encoder(connector);
79e53945 7111 struct drm_crtc *possible_crtc;
4ef69c7a 7112 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 7113 struct drm_crtc *crtc = NULL;
7114 struct drm_device *dev = encoder->dev;
94352cf9 7115 struct drm_framebuffer *fb;
79e53945
JB		 7116 int i = -1;
7117
d2dff872
CW		 7118 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7119 connector->base.id, drm_get_connector_name(connector),
7120 encoder->base.id, drm_get_encoder_name(encoder));
7121
79e53945
JB		 7122 /*
7123 * Algorithm gets a little messy:
7a5e4805 7124 *
79e53945
JB		 7125 * - if the connector already has an assigned crtc, use it (but make
7126 * sure it's on first)
7a5e4805 7127 *
79e53945
JB		 7128 * - try to find the first unused crtc that can drive this connector,
7129 * and use that if we find one
79e53945
JB		 7130 */
7131
7132 /* See if we already have a CRTC for this connector */
7133 if (encoder->crtc) {
7134 crtc = encoder->crtc;
8261b191 7135
7b24056b
DV		 7136 mutex_lock(&crtc->mutex);
7137
24218aac 7138 old->dpms_mode = connector->dpms;
8261b191
CW		 7139 old->load_detect_temp = false;
7140
7141 /* Make sure the crtc and connector are running */
24218aac
DV		 7142 if (connector->dpms != DRM_MODE_DPMS_ON)
7143 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 7144
7173188d 7145 return true;
79e53945
JB		 7146 }
7147
7148 /* Find an unused one (if possible) */
7149 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7150 i++;
7151 if (!(encoder->possible_crtcs & (1 << i)))
7152 continue;
7153 if (!possible_crtc->enabled) {
7154 crtc = possible_crtc;
7155 break;
7156 }
79e53945
JB		 7157 }
7158
7159 /*
7160 * If we didn't find an unused CRTC, don't use any.
7161 */
7162 if (!crtc) {
7173188d
CW		 7163 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7164 return false;
79e53945
JB		 7165 }
7166
7b24056b 7167 mutex_lock(&crtc->mutex);
fc303101
DV		 7168 intel_encoder->new_crtc = to_intel_crtc(crtc);
7169 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 7170
7171 intel_crtc = to_intel_crtc(crtc);
24218aac 7172 old->dpms_mode = connector->dpms;
8261b191 7173 old->load_detect_temp = true;
d2dff872 7174 old->release_fb = NULL;
79e53945 7175
6492711d
CW		 7176 if (!mode)
7177 mode = &load_detect_mode;
79e53945 7178
d2dff872
CW		 7179 /* We need a framebuffer large enough to accommodate all accesses
7180 * that the plane may generate whilst we perform load detection.
7181 * We can not rely on the fbcon either being present (we get called
7182 * during its initialisation to detect all boot displays, or it may
7183 * not even exist) or that it is large enough to satisfy the
7184 * requested mode.
7185 */
94352cf9
DV		 7186 fb = mode_fits_in_fbdev(dev, mode);
7187 if (fb == NULL) {
d2dff872 7188 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 7189 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7190 old->release_fb = fb;
d2dff872
CW		 7191 } else
7192 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 7193 if (IS_ERR(fb)) {
d2dff872 7194 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 7195 mutex_unlock(&crtc->mutex);
0e8b3d3e 7196 return false;
79e53945 7197 }
79e53945 7198
c0c36b94 7199 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 7200 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 7201 if (old->release_fb)
7202 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 7203 mutex_unlock(&crtc->mutex);
0e8b3d3e 7204 return false;
79e53945 7205 }
7173188d 7206
79e53945 7207 /* let the connector get through one full cycle before testing */
9d0498a2 7208 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 7209 return true;
79e53945
JB		 7210}
7211
d2434ab7 7212void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 7213 struct intel_load_detect_pipe *old)
79e53945 7214{
d2434ab7
DV		 7215 struct intel_encoder *intel_encoder =
7216 intel_attached_encoder(connector);
4ef69c7a 7217 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 7218 struct drm_crtc *crtc = encoder->crtc;
79e53945 7219
d2dff872
CW		 7220 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7221 connector->base.id, drm_get_connector_name(connector),
7222 encoder->base.id, drm_get_encoder_name(encoder));
7223
8261b191 7224 if (old->load_detect_temp) {
fc303101
DV		 7225 to_intel_connector(connector)->new_encoder = NULL;
7226 intel_encoder->new_crtc = NULL;
7227 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 7228
36206361
DV		 7229 if (old->release_fb) {
7230 drm_framebuffer_unregister_private(old->release_fb);
7231 drm_framebuffer_unreference(old->release_fb);
7232 }
d2dff872 7233
67c96400 7234 mutex_unlock(&crtc->mutex);
0622a53c 7235 return;
79e53945
JB		 7236 }
7237
c751ce4f 7238 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 7239 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7240 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 7241
7242 mutex_unlock(&crtc->mutex);
79e53945
JB		 7243}
7244
7245/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc
JB		 7246static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7247 struct intel_crtc_config *pipe_config)
79e53945 7248{
f1f644dc 7249 struct drm_device *dev = crtc->base.dev;
79e53945 7250 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 7251 int pipe = pipe_config->cpu_transcoder;
548f245b 7252 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 7253 u32 fp;
7254 intel_clock_t clock;
7255
7256 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 7257 fp = I915_READ(FP0(pipe));
79e53945 7258 else
39adb7a5 7259 fp = I915_READ(FP1(pipe));
79e53945
JB		 7260
7261 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 7262 if (IS_PINEVIEW(dev)) {
7263 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7264 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 7265 } else {
7266 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7267 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7268 }
7269
a6c45cf0 7270 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 7271 if (IS_PINEVIEW(dev))
7272 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7273 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 7274 else
7275 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 7276 DPLL_FPA01_P1_POST_DIV_SHIFT);
7277
7278 switch (dpll & DPLL_MODE_MASK) {
7279 case DPLLB_MODE_DAC_SERIAL:
7280 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7281 5 : 10;
7282 break;
7283 case DPLLB_MODE_LVDS:
7284 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7285 7 : 14;
7286 break;
7287 default:
28c97730 7288 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 7289 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc
JB		 7290 pipe_config->adjusted_mode.clock = 0;
7291 return;
79e53945
JB		 7292 }
7293
ac58c3f0
DV		 7294 if (IS_PINEVIEW(dev))
7295 pineview_clock(96000, &clock);
7296 else
7297 i9xx_clock(96000, &clock);
79e53945
JB		 7298 } else {
7299 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7300
7301 if (is_lvds) {
7302 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7303 DPLL_FPA01_P1_POST_DIV_SHIFT);
7304 clock.p2 = 14;
7305
7306 if ((dpll & PLL_REF_INPUT_MASK) ==
7307 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7308 /* XXX: might not be 66MHz */
ac58c3f0 7309 i9xx_clock(66000, &clock);
79e53945 7310 } else
ac58c3f0 7311 i9xx_clock(48000, &clock);
79e53945
JB		 7312 } else {
7313 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7314 clock.p1 = 2;
7315 else {
7316 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7317 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7318 }
7319 if (dpll & PLL_P2_DIVIDE_BY_4)
7320 clock.p2 = 4;
7321 else
7322 clock.p2 = 2;
7323
ac58c3f0 7324 i9xx_clock(48000, &clock);
79e53945
JB		 7325 }
7326 }
7327
a2dc53e7 7328 pipe_config->adjusted_mode.clock = clock.dot;
f1f644dc
JB		 7329}
7330
7331static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
7332 struct intel_crtc_config *pipe_config)
7333{
7334 struct drm_device *dev = crtc->base.dev;
7335 struct drm_i915_private *dev_priv = dev->dev_private;
7336 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
1041a02f 7337 int link_freq;
f1f644dc
JB		 7338 u64 clock;
7339 u32 link_m, link_n;
7340
f1f644dc
JB		 7341 /*
7342 * The calculation for the data clock is:
1041a02f 7343 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 7344 * But we want to avoid losing precison if possible, so:
1041a02f 7345 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 7346 *
7347 * and the link clock is simpler:
1041a02f 7348 * link_clock = (m * link_clock) / n
f1f644dc
JB		 7349 */
7350
7351 /*
7352 * We need to get the FDI or DP link clock here to derive
7353 * the M/N dividers.
7354 *
7355 * For FDI, we read it from the BIOS or use a fixed 2.7GHz.
7356 * For DP, it's either 1.62GHz or 2.7GHz.
7357 * We do our calculations in 10*MHz since we don't need much precison.
79e53945 7358 */
f1f644dc
JB		 7359 if (pipe_config->has_pch_encoder)
7360 link_freq = intel_fdi_link_freq(dev) * 10000;
7361 else
7362 link_freq = pipe_config->port_clock;
7363
7364 link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
7365 link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
7366
7367 if (!link_m || !link_n)
7368 return;
79e53945 7369
1041a02f 7370 clock = ((u64)link_m * (u64)link_freq);
f1f644dc
JB		 7371 do_div(clock, link_n);
7372
1041a02f
VS		 7373 pipe_config->adjusted_mode.clock = clock *
7374 pipe_config->pixel_multiplier;
79e53945
JB		 7375}
7376
7377/** Returns the currently programmed mode of the given pipe. */
7378struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7379 struct drm_crtc *crtc)
7380{
548f245b 7381 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 7382 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 7383 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 7384 struct drm_display_mode *mode;
f1f644dc 7385 struct intel_crtc_config pipe_config;
fe2b8f9d
PZ		 7386 int htot = I915_READ(HTOTAL(cpu_transcoder));
7387 int hsync = I915_READ(HSYNC(cpu_transcoder));
7388 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7389 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 7390
7391 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7392 if (!mode)
7393 return NULL;
7394
f1f644dc
JB		 7395 /*
7396 * Construct a pipe_config sufficient for getting the clock info
7397 * back out of crtc_clock_get.
7398 *
7399 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7400 * to use a real value here instead.
7401 */
e143a21c 7402 pipe_config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
f1f644dc
JB		 7403 pipe_config.pixel_multiplier = 1;
7404 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7405
7406 mode->clock = pipe_config.adjusted_mode.clock;
79e53945
JB		 7407 mode->hdisplay = (htot & 0xffff) + 1;
7408 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7409 mode->hsync_start = (hsync & 0xffff) + 1;
7410 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7411 mode->vdisplay = (vtot & 0xffff) + 1;
7412 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7413 mode->vsync_start = (vsync & 0xffff) + 1;
7414 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7415
7416 drm_mode_set_name(mode);
79e53945
JB		 7417
7418 return mode;
7419}
7420
3dec0095 7421static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7422{
7423 struct drm_device *dev = crtc->dev;
7424 drm_i915_private_t *dev_priv = dev->dev_private;
7425 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7426 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7427 int dpll_reg = DPLL(pipe);
7428 int dpll;
652c393a 7429
bad720ff 7430 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7431 return;
7432
7433 if (!dev_priv->lvds_downclock_avail)
7434 return;
7435
dbdc6479 7436 dpll = I915_READ(dpll_reg);
652c393a 7437 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7438 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7439
8ac5a6d5 7440 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7441
7442 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7443 I915_WRITE(dpll_reg, dpll);
9d0498a2 7444 intel_wait_for_vblank(dev, pipe);
dbdc6479 7445
652c393a
JB		 7446 dpll = I915_READ(dpll_reg);
7447 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7448 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7449 }
652c393a
JB		 7450}
7451
7452static void intel_decrease_pllclock(struct drm_crtc *crtc)
7453{
7454 struct drm_device *dev = crtc->dev;
7455 drm_i915_private_t *dev_priv = dev->dev_private;
7456 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7457
bad720ff 7458 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7459 return;
7460
7461 if (!dev_priv->lvds_downclock_avail)
7462 return;
7463
7464 /*
7465 * Since this is called by a timer, we should never get here in
7466 * the manual case.
7467 */
7468 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7469 int pipe = intel_crtc->pipe;
7470 int dpll_reg = DPLL(pipe);
7471 int dpll;
f6e5b160 7472
44d98a61 7473 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7474
8ac5a6d5 7475 assert_panel_unlocked(dev_priv, pipe);
652c393a 7476
dc257cf1 7477 dpll = I915_READ(dpll_reg);
652c393a
JB		 7478 dpll |= DISPLAY_RATE_SELECT_FPA1;
7479 I915_WRITE(dpll_reg, dpll);
9d0498a2 7480 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7481 dpll = I915_READ(dpll_reg);
7482 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7483 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7484 }
7485
7486}
7487
f047e395
CW		 7488void intel_mark_busy(struct drm_device *dev)
7489{
c67a470b
PZ		 7490 struct drm_i915_private *dev_priv = dev->dev_private;
7491
7492 hsw_package_c8_gpu_busy(dev_priv);
7493 i915_update_gfx_val(dev_priv);
f047e395
CW		 7494}
7495
7496void intel_mark_idle(struct drm_device *dev)
652c393a 7497{
c67a470b 7498 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 7499 struct drm_crtc *crtc;
652c393a 7500
c67a470b
PZ		 7501 hsw_package_c8_gpu_idle(dev_priv);
7502
652c393a
JB		 7503 if (!i915_powersave)
7504 return;
7505
652c393a 7506 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7507 if (!crtc->fb)
7508 continue;
7509
725a5b54 7510 intel_decrease_pllclock(crtc);
652c393a 7511 }
652c393a
JB		 7512}
7513
c65355bb
CW		 7514void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7515 struct intel_ring_buffer *ring)
652c393a 7516{
f047e395
CW		 7517 struct drm_device *dev = obj->base.dev;
7518 struct drm_crtc *crtc;
652c393a 7519
f047e395 7520 if (!i915_powersave)
acb87dfb
CW		 7521 return;
7522
652c393a
JB		 7523 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7524 if (!crtc->fb)
7525 continue;
7526
c65355bb
CW		 7527 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7528 continue;
7529
7530 intel_increase_pllclock(crtc);
7531 if (ring && intel_fbc_enabled(dev))
7532 ring->fbc_dirty = true;
652c393a
JB		 7533 }
7534}
7535
79e53945
JB		 7536static void intel_crtc_destroy(struct drm_crtc *crtc)
7537{
7538 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7539 struct drm_device *dev = crtc->dev;
7540 struct intel_unpin_work *work;
7541 unsigned long flags;
7542
7543 spin_lock_irqsave(&dev->event_lock, flags);
7544 work = intel_crtc->unpin_work;
7545 intel_crtc->unpin_work = NULL;
7546 spin_unlock_irqrestore(&dev->event_lock, flags);
7547
7548 if (work) {
7549 cancel_work_sync(&work->work);
7550 kfree(work);
7551 }
79e53945 7552
40ccc72b
MK		 7553 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7554
79e53945 7555 drm_crtc_cleanup(crtc);
67e77c5a 7556
79e53945
JB		 7557 kfree(intel_crtc);
7558}
7559
6b95a207
KH		 7560static void intel_unpin_work_fn(struct work_struct *__work)
7561{
7562 struct intel_unpin_work *work =
7563 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7564 struct drm_device *dev = work->crtc->dev;
6b95a207 7565
b4a98e57 7566 mutex_lock(&dev->struct_mutex);
1690e1eb 7567 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7568 drm_gem_object_unreference(&work->pending_flip_obj->base);
7569 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7570
b4a98e57
CW		 7571 intel_update_fbc(dev);
7572 mutex_unlock(&dev->struct_mutex);
7573
7574 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7575 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7576
6b95a207
KH		 7577 kfree(work);
7578}
7579
1afe3e9d 7580static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7581 struct drm_crtc *crtc)
6b95a207
KH		 7582{
7583 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7584 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7585 struct intel_unpin_work *work;
6b95a207
KH		 7586 unsigned long flags;
7587
7588 /* Ignore early vblank irqs */
7589 if (intel_crtc == NULL)
7590 return;
7591
7592 spin_lock_irqsave(&dev->event_lock, flags);
7593 work = intel_crtc->unpin_work;
e7d841ca
CW		 7594
7595 /* Ensure we don't miss a work->pending update ... */
7596 smp_rmb();
7597
7598 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7599 spin_unlock_irqrestore(&dev->event_lock, flags);
7600 return;
7601 }
7602
e7d841ca
CW		 7603 /* and that the unpin work is consistent wrt ->pending. */
7604 smp_rmb();
7605
6b95a207 7606 intel_crtc->unpin_work = NULL;
6b95a207 7607
45a066eb
RC		 7608 if (work->event)
7609 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7610
0af7e4df
MK		 7611 drm_vblank_put(dev, intel_crtc->pipe);
7612
6b95a207
KH		 7613 spin_unlock_irqrestore(&dev->event_lock, flags);
7614
2c10d571 7615 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7616
7617 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7618
7619 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7620}
7621
1afe3e9d
JB		 7622void intel_finish_page_flip(struct drm_device *dev, int pipe)
7623{
7624 drm_i915_private_t *dev_priv = dev->dev_private;
7625 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7626
49b14a5c 7627 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7628}
7629
7630void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7631{
7632 drm_i915_private_t *dev_priv = dev->dev_private;
7633 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7634
49b14a5c 7635 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7636}
7637
6b95a207
KH		 7638void intel_prepare_page_flip(struct drm_device *dev, int plane)
7639{
7640 drm_i915_private_t *dev_priv = dev->dev_private;
7641 struct intel_crtc *intel_crtc =
7642 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7643 unsigned long flags;
7644
e7d841ca
CW		 7645 /* NB: An MMIO update of the plane base pointer will also
7646 * generate a page-flip completion irq, i.e. every modeset
7647 * is also accompanied by a spurious intel_prepare_page_flip().
7648 */
6b95a207 7649 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7650 if (intel_crtc->unpin_work)
7651 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7652 spin_unlock_irqrestore(&dev->event_lock, flags);
7653}
7654
e7d841ca
CW		 7655inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7656{
7657 /* Ensure that the work item is consistent when activating it ... */
7658 smp_wmb();
7659 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7660 /* and that it is marked active as soon as the irq could fire. */
7661 smp_wmb();
7662}
7663
8c9f3aaf
JB		 7664static int intel_gen2_queue_flip(struct drm_device *dev,
7665 struct drm_crtc *crtc,
7666 struct drm_framebuffer *fb,
ed8d1975
KP		 7667 struct drm_i915_gem_object *obj,
7668 uint32_t flags)
8c9f3aaf
JB		 7669{
7670 struct drm_i915_private *dev_priv = dev->dev_private;
7671 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7672 u32 flip_mask;
6d90c952 7673 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7674 int ret;
7675
6d90c952 7676 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7677 if (ret)
83d4092b 7678 goto err;
8c9f3aaf 7679
6d90c952 7680 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7681 if (ret)
83d4092b 7682 goto err_unpin;
8c9f3aaf
JB		 7683
7684 /* Can't queue multiple flips, so wait for the previous
7685 * one to finish before executing the next.
7686 */
7687 if (intel_crtc->plane)
7688 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7689 else
7690 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7691 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7692 intel_ring_emit(ring, MI_NOOP);
7693 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7694 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7695 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7696 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952 7697 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7698
7699 intel_mark_page_flip_active(intel_crtc);
09246732 7700 __intel_ring_advance(ring);
83d4092b
CW		 7701 return 0;
7702
7703err_unpin:
7704 intel_unpin_fb_obj(obj);
7705err:
8c9f3aaf
JB		 7706 return ret;
7707}
7708
7709static int intel_gen3_queue_flip(struct drm_device *dev,
7710 struct drm_crtc *crtc,
7711 struct drm_framebuffer *fb,
ed8d1975
KP		 7712 struct drm_i915_gem_object *obj,
7713 uint32_t flags)
8c9f3aaf
JB		 7714{
7715 struct drm_i915_private *dev_priv = dev->dev_private;
7716 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7717 u32 flip_mask;
6d90c952 7718 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7719 int ret;
7720
6d90c952 7721 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7722 if (ret)
83d4092b 7723 goto err;
8c9f3aaf 7724
6d90c952 7725 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7726 if (ret)
83d4092b 7727 goto err_unpin;
8c9f3aaf
JB		 7728
7729 if (intel_crtc->plane)
7730 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7731 else
7732 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7733 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7734 intel_ring_emit(ring, MI_NOOP);
7735 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7736 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7737 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7738 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952
DV		 7739 intel_ring_emit(ring, MI_NOOP);
7740
e7d841ca 7741 intel_mark_page_flip_active(intel_crtc);
09246732 7742 __intel_ring_advance(ring);
83d4092b
CW		 7743 return 0;
7744
7745err_unpin:
7746 intel_unpin_fb_obj(obj);
7747err:
8c9f3aaf
JB		 7748 return ret;
7749}
7750
7751static int intel_gen4_queue_flip(struct drm_device *dev,
7752 struct drm_crtc *crtc,
7753 struct drm_framebuffer *fb,
ed8d1975
KP		 7754 struct drm_i915_gem_object *obj,
7755 uint32_t flags)
8c9f3aaf
JB		 7756{
7757 struct drm_i915_private *dev_priv = dev->dev_private;
7758 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7759 uint32_t pf, pipesrc;
6d90c952 7760 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7761 int ret;
7762
6d90c952 7763 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7764 if (ret)
83d4092b 7765 goto err;
8c9f3aaf 7766
6d90c952 7767 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7768 if (ret)
83d4092b 7769 goto err_unpin;
8c9f3aaf
JB		 7770
7771 /* i965+ uses the linear or tiled offsets from the
7772 * Display Registers (which do not change across a page-flip)
7773 * so we need only reprogram the base address.
7774 */
6d90c952
DV		 7775 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7776 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7777 intel_ring_emit(ring, fb->pitches[0]);
c2c75131 7778 intel_ring_emit(ring,
f343c5f6 7779 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
c2c75131 7780 obj->tiling_mode);
8c9f3aaf
JB		 7781
7782 /* XXX Enabling the panel-fitter across page-flip is so far
7783 * untested on non-native modes, so ignore it for now.
7784 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7785 */
7786 pf = 0;
7787 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7788 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7789
7790 intel_mark_page_flip_active(intel_crtc);
09246732 7791 __intel_ring_advance(ring);
83d4092b
CW		 7792 return 0;
7793
7794err_unpin:
7795 intel_unpin_fb_obj(obj);
7796err:
8c9f3aaf
JB		 7797 return ret;
7798}
7799
7800static int intel_gen6_queue_flip(struct drm_device *dev,
7801 struct drm_crtc *crtc,
7802 struct drm_framebuffer *fb,
ed8d1975
KP		 7803 struct drm_i915_gem_object *obj,
7804 uint32_t flags)
8c9f3aaf
JB		 7805{
7806 struct drm_i915_private *dev_priv = dev->dev_private;
7807 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7808 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7809 uint32_t pf, pipesrc;
7810 int ret;
7811
6d90c952 7812 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7813 if (ret)
83d4092b 7814 goto err;
8c9f3aaf 7815
6d90c952 7816 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7817 if (ret)
83d4092b 7818 goto err_unpin;
8c9f3aaf 7819
6d90c952
DV		 7820 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7821 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7822 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
f343c5f6 7823 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8c9f3aaf 7824
dc257cf1
DV		 7825 /* Contrary to the suggestions in the documentation,
7826 * "Enable Panel Fitter" does not seem to be required when page
7827 * flipping with a non-native mode, and worse causes a normal
7828 * modeset to fail.
7829 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7830 */
7831 pf = 0;
8c9f3aaf 7832 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7833 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7834
7835 intel_mark_page_flip_active(intel_crtc);
09246732 7836 __intel_ring_advance(ring);
83d4092b
CW		 7837 return 0;
7838
7839err_unpin:
7840 intel_unpin_fb_obj(obj);
7841err:
8c9f3aaf
JB		 7842 return ret;
7843}
7844
7c9017e5
JB		 7845static int intel_gen7_queue_flip(struct drm_device *dev,
7846 struct drm_crtc *crtc,
7847 struct drm_framebuffer *fb,
ed8d1975
KP		 7848 struct drm_i915_gem_object *obj,
7849 uint32_t flags)
7c9017e5
JB		 7850{
7851 struct drm_i915_private *dev_priv = dev->dev_private;
7852 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ffe74d75 7853 struct intel_ring_buffer *ring;
cb05d8de 7854 uint32_t plane_bit = 0;
ffe74d75
CW		 7855 int len, ret;
7856
7857 ring = obj->ring;
7858 if (ring == NULL || ring->id != RCS)
7859 ring = &dev_priv->ring[BCS];
7c9017e5
JB		 7860
7861 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7862 if (ret)
83d4092b 7863 goto err;
7c9017e5 7864
cb05d8de
DV		 7865 switch(intel_crtc->plane) {
7866 case PLANE_A:
7867 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7868 break;
7869 case PLANE_B:
7870 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7871 break;
7872 case PLANE_C:
7873 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7874 break;
7875 default:
7876 WARN_ONCE(1, "unknown plane in flip command\n");
7877 ret = -ENODEV;
ab3951eb 7878 goto err_unpin;
cb05d8de
DV		 7879 }
7880
ffe74d75
CW		 7881 len = 4;
7882 if (ring->id == RCS)
7883 len += 6;
7884
7885 ret = intel_ring_begin(ring, len);
7c9017e5 7886 if (ret)
83d4092b 7887 goto err_unpin;
7c9017e5 7888
ffe74d75
CW		 7889 /* Unmask the flip-done completion message. Note that the bspec says that
7890 * we should do this for both the BCS and RCS, and that we must not unmask
7891 * more than one flip event at any time (or ensure that one flip message
7892 * can be sent by waiting for flip-done prior to queueing new flips).
7893 * Experimentation says that BCS works despite DERRMR masking all
7894 * flip-done completion events and that unmasking all planes at once
7895 * for the RCS also doesn't appear to drop events. Setting the DERRMR
7896 * to zero does lead to lockups within MI_DISPLAY_FLIP.
7897 */
7898 if (ring->id == RCS) {
7899 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
7900 intel_ring_emit(ring, DERRMR);
7901 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
7902 DERRMR_PIPEB_PRI_FLIP_DONE |
7903 DERRMR_PIPEC_PRI_FLIP_DONE));
7904 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
7905 intel_ring_emit(ring, DERRMR);
7906 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
7907 }
7908
cb05d8de 7909 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7910 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
f343c5f6 7911 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7c9017e5 7912 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7913
7914 intel_mark_page_flip_active(intel_crtc);
09246732 7915 __intel_ring_advance(ring);
83d4092b
CW		 7916 return 0;
7917
7918err_unpin:
7919 intel_unpin_fb_obj(obj);
7920err:
7c9017e5
JB		 7921 return ret;
7922}
7923
8c9f3aaf
JB		 7924static int intel_default_queue_flip(struct drm_device *dev,
7925 struct drm_crtc *crtc,
7926 struct drm_framebuffer *fb,
ed8d1975
KP		 7927 struct drm_i915_gem_object *obj,
7928 uint32_t flags)
8c9f3aaf
JB		 7929{
7930 return -ENODEV;
7931}
7932
6b95a207
KH		 7933static int intel_crtc_page_flip(struct drm_crtc *crtc,
7934 struct drm_framebuffer *fb,
ed8d1975
KP		 7935 struct drm_pending_vblank_event *event,
7936 uint32_t page_flip_flags)
6b95a207
KH		 7937{
7938 struct drm_device *dev = crtc->dev;
7939 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7940 struct drm_framebuffer *old_fb = crtc->fb;
7941 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7942 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7943 struct intel_unpin_work *work;
8c9f3aaf 7944 unsigned long flags;
52e68630 7945 int ret;
6b95a207 7946
e6a595d2
VS		 7947 /* Can't change pixel format via MI display flips. */
7948 if (fb->pixel_format != crtc->fb->pixel_format)
7949 return -EINVAL;
7950
7951 /*
7952 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7953 * Note that pitch changes could also affect these register.
7954 */
7955 if (INTEL_INFO(dev)->gen > 3 &&
7956 (fb->offsets[0] != crtc->fb->offsets[0] ||
7957 fb->pitches[0] != crtc->fb->pitches[0]))
7958 return -EINVAL;
7959
6b95a207
KH		 7960 work = kzalloc(sizeof *work, GFP_KERNEL);
7961 if (work == NULL)
7962 return -ENOMEM;
7963
6b95a207 7964 work->event = event;
b4a98e57 7965 work->crtc = crtc;
4a35f83b 7966 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7967 INIT_WORK(&work->work, intel_unpin_work_fn);
7968
7317c75e
JB		 7969 ret = drm_vblank_get(dev, intel_crtc->pipe);
7970 if (ret)
7971 goto free_work;
7972
6b95a207
KH		 7973 /* We borrow the event spin lock for protecting unpin_work */
7974 spin_lock_irqsave(&dev->event_lock, flags);
7975 if (intel_crtc->unpin_work) {
7976 spin_unlock_irqrestore(&dev->event_lock, flags);
7977 kfree(work);
7317c75e 7978 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7979
7980 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7981 return -EBUSY;
7982 }
7983 intel_crtc->unpin_work = work;
7984 spin_unlock_irqrestore(&dev->event_lock, flags);
7985
b4a98e57
CW		 7986 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7987 flush_workqueue(dev_priv->wq);
7988
79158103
CW		 7989 ret = i915_mutex_lock_interruptible(dev);
7990 if (ret)
7991 goto cleanup;
6b95a207 7992
75dfca80 7993 /* Reference the objects for the scheduled work. */
05394f39
CW		 7994 drm_gem_object_reference(&work->old_fb_obj->base);
7995 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7996
7997 crtc->fb = fb;
96b099fd 7998
e1f99ce6 7999 work->pending_flip_obj = obj;
e1f99ce6 8000
4e5359cd
SF		 8001 work->enable_stall_check = true;
8002
b4a98e57 8003 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 8004 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 8005
ed8d1975 8006 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8c9f3aaf
JB		 8007 if (ret)
8008 goto cleanup_pending;
6b95a207 8009
7782de3b 8010 intel_disable_fbc(dev);
c65355bb 8011 intel_mark_fb_busy(obj, NULL);
6b95a207
KH		 8012 mutex_unlock(&dev->struct_mutex);
8013
e5510fac
JB		 8014 trace_i915_flip_request(intel_crtc->plane, obj);
8015
6b95a207 8016 return 0;
96b099fd 8017
8c9f3aaf 8018cleanup_pending:
b4a98e57 8019 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 8020 crtc->fb = old_fb;
05394f39
CW		 8021 drm_gem_object_unreference(&work->old_fb_obj->base);
8022 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 8023 mutex_unlock(&dev->struct_mutex);
8024
79158103 8025cleanup:
96b099fd
CW		 8026 spin_lock_irqsave(&dev->event_lock, flags);
8027 intel_crtc->unpin_work = NULL;
8028 spin_unlock_irqrestore(&dev->event_lock, flags);
8029
7317c75e
JB		 8030 drm_vblank_put(dev, intel_crtc->pipe);
8031free_work:
96b099fd
CW		 8032 kfree(work);
8033
8034 return ret;
6b95a207
KH		 8035}
8036
f6e5b160 8037static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 8038 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8039 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 8040};
8041
50f56119
DV		 8042static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8043 struct drm_crtc *crtc)
8044{
8045 struct drm_device *dev;
8046 struct drm_crtc *tmp;
8047 int crtc_mask = 1;
47f1c6c9 8048
50f56119 8049 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 8050
50f56119 8051 dev = crtc->dev;
47f1c6c9 8052
50f56119
DV		 8053 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8054 if (tmp == crtc)
8055 break;
8056 crtc_mask <<= 1;
8057 }
47f1c6c9 8058
50f56119
DV		 8059 if (encoder->possible_crtcs & crtc_mask)
8060 return true;
8061 return false;
47f1c6c9 8062}
79e53945 8063
9a935856
DV		 8064/**
8065 * intel_modeset_update_staged_output_state
8066 *
8067 * Updates the staged output configuration state, e.g. after we've read out the
8068 * current hw state.
8069 */
8070static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 8071{
9a935856
DV		 8072 struct intel_encoder *encoder;
8073 struct intel_connector *connector;
f6e5b160 8074
9a935856
DV		 8075 list_for_each_entry(connector, &dev->mode_config.connector_list,
8076 base.head) {
8077 connector->new_encoder =
8078 to_intel_encoder(connector->base.encoder);
8079 }
f6e5b160 8080
9a935856
DV		 8081 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8082 base.head) {
8083 encoder->new_crtc =
8084 to_intel_crtc(encoder->base.crtc);
8085 }
f6e5b160
CW		 8086}
8087
9a935856
DV		 8088/**
8089 * intel_modeset_commit_output_state
8090 *
8091 * This function copies the stage display pipe configuration to the real one.
8092 */
8093static void intel_modeset_commit_output_state(struct drm_device *dev)
8094{
8095 struct intel_encoder *encoder;
8096 struct intel_connector *connector;
f6e5b160 8097
9a935856
DV		 8098 list_for_each_entry(connector, &dev->mode_config.connector_list,
8099 base.head) {
8100 connector->base.encoder = &connector->new_encoder->base;
8101 }
f6e5b160 8102
9a935856
DV		 8103 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8104 base.head) {
8105 encoder->base.crtc = &encoder->new_crtc->base;
8106 }
8107}
8108
050f7aeb
DV		 8109static void
8110connected_sink_compute_bpp(struct intel_connector * connector,
8111 struct intel_crtc_config *pipe_config)
8112{
8113 int bpp = pipe_config->pipe_bpp;
8114
8115 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8116 connector->base.base.id,
8117 drm_get_connector_name(&connector->base));
8118
8119 /* Don't use an invalid EDID bpc value */
8120 if (connector->base.display_info.bpc &&
8121 connector->base.display_info.bpc * 3 < bpp) {
8122 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8123 bpp, connector->base.display_info.bpc*3);
8124 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8125 }
8126
8127 /* Clamp bpp to 8 on screens without EDID 1.4 */
8128 if (connector->base.display_info.bpc == 0 && bpp > 24) {
8129 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8130 bpp);
8131 pipe_config->pipe_bpp = 24;
8132 }
8133}
8134
4e53c2e0 8135static int
050f7aeb
DV		 8136compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8137 struct drm_framebuffer *fb,
8138 struct intel_crtc_config *pipe_config)
4e53c2e0 8139{
050f7aeb
DV		 8140 struct drm_device *dev = crtc->base.dev;
8141 struct intel_connector *connector;
4e53c2e0
DV		 8142 int bpp;
8143
d42264b1
DV		 8144 switch (fb->pixel_format) {
8145 case DRM_FORMAT_C8:
4e53c2e0
DV		 8146 bpp = 8*3; /* since we go through a colormap */
8147 break;
d42264b1
DV		 8148 case DRM_FORMAT_XRGB1555:
8149 case DRM_FORMAT_ARGB1555:
8150 /* checked in intel_framebuffer_init already */
8151 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8152 return -EINVAL;
8153 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 8154 bpp = 6*3; /* min is 18bpp */
8155 break;
d42264b1
DV		 8156 case DRM_FORMAT_XBGR8888:
8157 case DRM_FORMAT_ABGR8888:
8158 /* checked in intel_framebuffer_init already */
8159 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8160 return -EINVAL;
8161 case DRM_FORMAT_XRGB8888:
8162 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 8163 bpp = 8*3;
8164 break;
d42264b1
DV		 8165 case DRM_FORMAT_XRGB2101010:
8166 case DRM_FORMAT_ARGB2101010:
8167 case DRM_FORMAT_XBGR2101010:
8168 case DRM_FORMAT_ABGR2101010:
8169 /* checked in intel_framebuffer_init already */
8170 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 8171 return -EINVAL;
4e53c2e0
DV		 8172 bpp = 10*3;
8173 break;
baba133a 8174 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 8175 default:
8176 DRM_DEBUG_KMS("unsupported depth\n");
8177 return -EINVAL;
8178 }
8179
4e53c2e0
DV		 8180 pipe_config->pipe_bpp = bpp;
8181
8182 /* Clamp display bpp to EDID value */
8183 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 8184 base.head) {
1b829e05
DV		 8185 if (!connector->new_encoder ||
8186 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 8187 continue;
8188
050f7aeb 8189 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 8190 }
8191
8192 return bpp;
8193}
8194
c0b03411
DV		 8195static void intel_dump_pipe_config(struct intel_crtc *crtc,
8196 struct intel_crtc_config *pipe_config,
8197 const char *context)
8198{
8199 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8200 context, pipe_name(crtc->pipe));
8201
8202 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8203 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8204 pipe_config->pipe_bpp, pipe_config->dither);
8205 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8206 pipe_config->has_pch_encoder,
8207 pipe_config->fdi_lanes,
8208 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8209 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8210 pipe_config->fdi_m_n.tu);
8211 DRM_DEBUG_KMS("requested mode:\n");
8212 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8213 DRM_DEBUG_KMS("adjusted mode:\n");
8214 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8215 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8216 pipe_config->gmch_pfit.control,
8217 pipe_config->gmch_pfit.pgm_ratios,
8218 pipe_config->gmch_pfit.lvds_border_bits);
8219 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
8220 pipe_config->pch_pfit.pos,
8221 pipe_config->pch_pfit.size);
42db64ef 8222 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
c0b03411
DV		 8223}
8224
accfc0c5
DV		 8225static bool check_encoder_cloning(struct drm_crtc *crtc)
8226{
8227 int num_encoders = 0;
8228 bool uncloneable_encoders = false;
8229 struct intel_encoder *encoder;
8230
8231 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8232 base.head) {
8233 if (&encoder->new_crtc->base != crtc)
8234 continue;
8235
8236 num_encoders++;
8237 if (!encoder->cloneable)
8238 uncloneable_encoders = true;
8239 }
8240
8241 return !(num_encoders > 1 && uncloneable_encoders);
8242}
8243
b8cecdf5
DV		 8244static struct intel_crtc_config *
8245intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 8246 struct drm_framebuffer *fb,
b8cecdf5 8247 struct drm_display_mode *mode)
ee7b9f93 8248{
7758a113 8249 struct drm_device *dev = crtc->dev;
7758a113 8250 struct intel_encoder *encoder;
b8cecdf5 8251 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 8252 int plane_bpp, ret = -EINVAL;
8253 bool retry = true;
ee7b9f93 8254
accfc0c5
DV		 8255 if (!check_encoder_cloning(crtc)) {
8256 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8257 return ERR_PTR(-EINVAL);
8258 }
8259
b8cecdf5
DV		 8260 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8261 if (!pipe_config)
7758a113
DV		 8262 return ERR_PTR(-ENOMEM);
8263
b8cecdf5
DV		 8264 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8265 drm_mode_copy(&pipe_config->requested_mode, mode);
e143a21c
DV		 8266 pipe_config->cpu_transcoder =
8267 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 8268 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 8269
2960bc9c
ID		 8270 /*
8271 * Sanitize sync polarity flags based on requested ones. If neither
8272 * positive or negative polarity is requested, treat this as meaning
8273 * negative polarity.
8274 */
8275 if (!(pipe_config->adjusted_mode.flags &
8276 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8277 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8278
8279 if (!(pipe_config->adjusted_mode.flags &
8280 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8281 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8282
050f7aeb
DV		 8283 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8284 * plane pixel format and any sink constraints into account. Returns the
8285 * source plane bpp so that dithering can be selected on mismatches
8286 * after encoders and crtc also have had their say. */
8287 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8288 fb, pipe_config);
4e53c2e0
DV		 8289 if (plane_bpp < 0)
8290 goto fail;
8291
e29c22c0 8292encoder_retry:
ef1b460d 8293 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 8294 pipe_config->port_clock = 0;
ef1b460d 8295 pipe_config->pixel_multiplier = 1;
ff9a6750 8296
135c81b8
DV		 8297 /* Fill in default crtc timings, allow encoders to overwrite them. */
8298 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0);
8299
7758a113
DV		 8300 /* Pass our mode to the connectors and the CRTC to give them a chance to
8301 * adjust it according to limitations or connector properties, and also
8302 * a chance to reject the mode entirely.
47f1c6c9 8303 */
7758a113
DV		 8304 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8305 base.head) {
47f1c6c9 8306
7758a113
DV		 8307 if (&encoder->new_crtc->base != crtc)
8308 continue;
7ae89233 8309
efea6e8e
DV		 8310 if (!(encoder->compute_config(encoder, pipe_config))) {
8311 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 8312 goto fail;
8313 }
ee7b9f93 8314 }
47f1c6c9 8315
ff9a6750
DV		 8316 /* Set default port clock if not overwritten by the encoder. Needs to be
8317 * done afterwards in case the encoder adjusts the mode. */
8318 if (!pipe_config->port_clock)
8319 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
8320
a43f6e0f 8321 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 8322 if (ret < 0) {
7758a113
DV		 8323 DRM_DEBUG_KMS("CRTC fixup failed\n");
8324 goto fail;
ee7b9f93 8325 }
e29c22c0
DV		 8326
8327 if (ret == RETRY) {
8328 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8329 ret = -EINVAL;
8330 goto fail;
8331 }
8332
8333 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8334 retry = false;
8335 goto encoder_retry;
8336 }
8337
4e53c2e0
DV		 8338 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8339 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8340 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8341
b8cecdf5 8342 return pipe_config;
7758a113 8343fail:
b8cecdf5 8344 kfree(pipe_config);
e29c22c0 8345 return ERR_PTR(ret);
ee7b9f93 8346}
47f1c6c9 8347
e2e1ed41
DV		 8348/* Computes which crtcs are affected and sets the relevant bits in the mask. For
8349 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8350static void
8351intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8352 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 8353{
8354 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 8355 struct drm_device *dev = crtc->dev;
8356 struct intel_encoder *encoder;
8357 struct intel_connector *connector;
8358 struct drm_crtc *tmp_crtc;
79e53945 8359
e2e1ed41 8360 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 8361
e2e1ed41
DV		 8362 /* Check which crtcs have changed outputs connected to them, these need
8363 * to be part of the prepare_pipes mask. We don't (yet) support global
8364 * modeset across multiple crtcs, so modeset_pipes will only have one
8365 * bit set at most. */
8366 list_for_each_entry(connector, &dev->mode_config.connector_list,
8367 base.head) {
8368 if (connector->base.encoder == &connector->new_encoder->base)
8369 continue;
79e53945 8370
e2e1ed41
DV		 8371 if (connector->base.encoder) {
8372 tmp_crtc = connector->base.encoder->crtc;
8373
8374 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8375 }
8376
8377 if (connector->new_encoder)
8378 *prepare_pipes |=
8379 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 8380 }
8381
e2e1ed41
DV		 8382 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8383 base.head) {
8384 if (encoder->base.crtc == &encoder->new_crtc->base)
8385 continue;
8386
8387 if (encoder->base.crtc) {
8388 tmp_crtc = encoder->base.crtc;
8389
8390 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8391 }
8392
8393 if (encoder->new_crtc)
8394 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 8395 }
8396
e2e1ed41
DV		 8397 /* Check for any pipes that will be fully disabled ... */
8398 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8399 base.head) {
8400 bool used = false;
22fd0fab 8401
e2e1ed41
DV		 8402 /* Don't try to disable disabled crtcs. */
8403 if (!intel_crtc->base.enabled)
8404 continue;
7e7d76c3 8405
e2e1ed41
DV		 8406 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8407 base.head) {
8408 if (encoder->new_crtc == intel_crtc)
8409 used = true;
8410 }
8411
8412 if (!used)
8413 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 8414 }
8415
e2e1ed41
DV		 8416
8417 /* set_mode is also used to update properties on life display pipes. */
8418 intel_crtc = to_intel_crtc(crtc);
8419 if (crtc->enabled)
8420 *prepare_pipes |= 1 << intel_crtc->pipe;
8421
b6c5164d
DV		 8422 /*
8423 * For simplicity do a full modeset on any pipe where the output routing
8424 * changed. We could be more clever, but that would require us to be
8425 * more careful with calling the relevant encoder->mode_set functions.
8426 */
e2e1ed41
DV		 8427 if (*prepare_pipes)
8428 *modeset_pipes = *prepare_pipes;
8429
8430 /* ... and mask these out. */
8431 *modeset_pipes &= ~(*disable_pipes);
8432 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 8433
8434 /*
8435 * HACK: We don't (yet) fully support global modesets. intel_set_config
8436 * obies this rule, but the modeset restore mode of
8437 * intel_modeset_setup_hw_state does not.
8438 */
8439 *modeset_pipes &= 1 << intel_crtc->pipe;
8440 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 8441
8442 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8443 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 8444}
79e53945 8445
ea9d758d 8446static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 8447{
ea9d758d 8448 struct drm_encoder *encoder;
f6e5b160 8449 struct drm_device *dev = crtc->dev;
f6e5b160 8450
ea9d758d
DV		 8451 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8452 if (encoder->crtc == crtc)
8453 return true;
8454
8455 return false;
8456}
8457
8458static void
8459intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8460{
8461 struct intel_encoder *intel_encoder;
8462 struct intel_crtc *intel_crtc;
8463 struct drm_connector *connector;
8464
8465 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8466 base.head) {
8467 if (!intel_encoder->base.crtc)
8468 continue;
8469
8470 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8471
8472 if (prepare_pipes & (1 << intel_crtc->pipe))
8473 intel_encoder->connectors_active = false;
8474 }
8475
8476 intel_modeset_commit_output_state(dev);
8477
8478 /* Update computed state. */
8479 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8480 base.head) {
8481 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8482 }
8483
8484 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8485 if (!connector->encoder || !connector->encoder->crtc)
8486 continue;
8487
8488 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8489
8490 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8491 struct drm_property *dpms_property =
8492 dev->mode_config.dpms_property;
8493
ea9d758d 8494 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8495 drm_object_property_set_value(&connector->base,
68d34720
DV		 8496 dpms_property,
8497 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8498
8499 intel_encoder = to_intel_encoder(connector->encoder);
8500 intel_encoder->connectors_active = true;
8501 }
8502 }
8503
8504}
8505
f1f644dc
JB		 8506static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur,
8507 struct intel_crtc_config *new)
8508{
8509 int clock1, clock2, diff;
8510
8511 clock1 = cur->adjusted_mode.clock;
8512 clock2 = new->adjusted_mode.clock;
8513
8514 if (clock1 == clock2)
8515 return true;
8516
8517 if (!clock1 || !clock2)
8518 return false;
8519
8520 diff = abs(clock1 - clock2);
8521
8522 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8523 return true;
8524
8525 return false;
8526}
8527
25c5b266
DV		 8528#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8529 list_for_each_entry((intel_crtc), \
8530 &(dev)->mode_config.crtc_list, \
8531 base.head) \
0973f18f 8532 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8533
0e8ffe1b 8534static bool
2fa2fe9a
DV		 8535intel_pipe_config_compare(struct drm_device *dev,
8536 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8537 struct intel_crtc_config *pipe_config)
8538{
66e985c0
DV		 8539#define PIPE_CONF_CHECK_X(name) \
8540 if (current_config->name != pipe_config->name) { \
8541 DRM_ERROR("mismatch in " #name " " \
8542 "(expected 0x%08x, found 0x%08x)\n", \
8543 current_config->name, \
8544 pipe_config->name); \
8545 return false; \
8546 }
8547
08a24034
DV		 8548#define PIPE_CONF_CHECK_I(name) \
8549 if (current_config->name != pipe_config->name) { \
8550 DRM_ERROR("mismatch in " #name " " \
8551 "(expected %i, found %i)\n", \
8552 current_config->name, \
8553 pipe_config->name); \
8554 return false; \
88adfff1
DV		 8555 }
8556
1bd1bd80
DV		 8557#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8558 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 8559 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 8560 "(expected %i, found %i)\n", \
8561 current_config->name & (mask), \
8562 pipe_config->name & (mask)); \
8563 return false; \
8564 }
8565
bb760063
DV		 8566#define PIPE_CONF_QUIRK(quirk) \
8567 ((current_config->quirks | pipe_config->quirks) & (quirk))
8568
eccb140b
DV		 8569 PIPE_CONF_CHECK_I(cpu_transcoder);
8570
08a24034
DV		 8571 PIPE_CONF_CHECK_I(has_pch_encoder);
8572 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8573 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8574 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8575 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8576 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8577 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8578
1bd1bd80
DV		 8579 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8580 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8581 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8582 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8583 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8584 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8585
8586 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8587 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8588 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8589 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8590 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8591 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8592
c93f54cf 8593 PIPE_CONF_CHECK_I(pixel_multiplier);
6c49f241 8594
1bd1bd80
DV		 8595 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8596 DRM_MODE_FLAG_INTERLACE);
8597
bb760063
DV		 8598 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8599 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8600 DRM_MODE_FLAG_PHSYNC);
8601 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8602 DRM_MODE_FLAG_NHSYNC);
8603 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8604 DRM_MODE_FLAG_PVSYNC);
8605 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8606 DRM_MODE_FLAG_NVSYNC);
8607 }
045ac3b5 8608
1bd1bd80
DV		 8609 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8610 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8611
2fa2fe9a
DV		 8612 PIPE_CONF_CHECK_I(gmch_pfit.control);
8613 /* pfit ratios are autocomputed by the hw on gen4+ */
8614 if (INTEL_INFO(dev)->gen < 4)
8615 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8616 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8617 PIPE_CONF_CHECK_I(pch_pfit.pos);
8618 PIPE_CONF_CHECK_I(pch_pfit.size);
8619
42db64ef
PZ		 8620 PIPE_CONF_CHECK_I(ips_enabled);
8621
c0d43d62 8622 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 8623 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 8624 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 8625 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8626 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
c0d43d62 8627
66e985c0 8628#undef PIPE_CONF_CHECK_X
08a24034 8629#undef PIPE_CONF_CHECK_I
1bd1bd80 8630#undef PIPE_CONF_CHECK_FLAGS
bb760063 8631#undef PIPE_CONF_QUIRK
88adfff1 8632
f1f644dc
JB		 8633 if (!IS_HASWELL(dev)) {
8634 if (!intel_fuzzy_clock_check(current_config, pipe_config)) {
6f02488e 8635 DRM_ERROR("mismatch in clock (expected %d, found %d)\n",
f1f644dc
JB		 8636 current_config->adjusted_mode.clock,
8637 pipe_config->adjusted_mode.clock);
8638 return false;
8639 }
8640 }
8641
0e8ffe1b
DV		 8642 return true;
8643}
8644
91d1b4bd
DV		 8645static void
8646check_connector_state(struct drm_device *dev)
8af6cf88 8647{
8af6cf88
DV		 8648 struct intel_connector *connector;
8649
8650 list_for_each_entry(connector, &dev->mode_config.connector_list,
8651 base.head) {
8652 /* This also checks the encoder/connector hw state with the
8653 * ->get_hw_state callbacks. */
8654 intel_connector_check_state(connector);
8655
8656 WARN(&connector->new_encoder->base != connector->base.encoder,
8657 "connector's staged encoder doesn't match current encoder\n");
8658 }
91d1b4bd
DV		 8659}
8660
8661static void
8662check_encoder_state(struct drm_device *dev)
8663{
8664 struct intel_encoder *encoder;
8665 struct intel_connector *connector;
8af6cf88
DV		 8666
8667 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8668 base.head) {
8669 bool enabled = false;
8670 bool active = false;
8671 enum pipe pipe, tracked_pipe;
8672
8673 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8674 encoder->base.base.id,
8675 drm_get_encoder_name(&encoder->base));
8676
8677 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8678 "encoder's stage crtc doesn't match current crtc\n");
8679 WARN(encoder->connectors_active && !encoder->base.crtc,
8680 "encoder's active_connectors set, but no crtc\n");
8681
8682 list_for_each_entry(connector, &dev->mode_config.connector_list,
8683 base.head) {
8684 if (connector->base.encoder != &encoder->base)
8685 continue;
8686 enabled = true;
8687 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8688 active = true;
8689 }
8690 WARN(!!encoder->base.crtc != enabled,
8691 "encoder's enabled state mismatch "
8692 "(expected %i, found %i)\n",
8693 !!encoder->base.crtc, enabled);
8694 WARN(active && !encoder->base.crtc,
8695 "active encoder with no crtc\n");
8696
8697 WARN(encoder->connectors_active != active,
8698 "encoder's computed active state doesn't match tracked active state "
8699 "(expected %i, found %i)\n", active, encoder->connectors_active);
8700
8701 active = encoder->get_hw_state(encoder, &pipe);
8702 WARN(active != encoder->connectors_active,
8703 "encoder's hw state doesn't match sw tracking "
8704 "(expected %i, found %i)\n",
8705 encoder->connectors_active, active);
8706
8707 if (!encoder->base.crtc)
8708 continue;
8709
8710 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8711 WARN(active && pipe != tracked_pipe,
8712 "active encoder's pipe doesn't match"
8713 "(expected %i, found %i)\n",
8714 tracked_pipe, pipe);
8715
8716 }
91d1b4bd
DV		 8717}
8718
8719static void
8720check_crtc_state(struct drm_device *dev)
8721{
8722 drm_i915_private_t *dev_priv = dev->dev_private;
8723 struct intel_crtc *crtc;
8724 struct intel_encoder *encoder;
8725 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8726
8727 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8728 base.head) {
8729 bool enabled = false;
8730 bool active = false;
8731
045ac3b5
JB		 8732 memset(&pipe_config, 0, sizeof(pipe_config));
8733
8af6cf88
DV		 8734 DRM_DEBUG_KMS("[CRTC:%d]\n",
8735 crtc->base.base.id);
8736
8737 WARN(crtc->active && !crtc->base.enabled,
8738 "active crtc, but not enabled in sw tracking\n");
8739
8740 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8741 base.head) {
8742 if (encoder->base.crtc != &crtc->base)
8743 continue;
8744 enabled = true;
8745 if (encoder->connectors_active)
8746 active = true;
8747 }
6c49f241 8748
8af6cf88
DV		 8749 WARN(active != crtc->active,
8750 "crtc's computed active state doesn't match tracked active state "
8751 "(expected %i, found %i)\n", active, crtc->active);
8752 WARN(enabled != crtc->base.enabled,
8753 "crtc's computed enabled state doesn't match tracked enabled state "
8754 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8755
0e8ffe1b
DV		 8756 active = dev_priv->display.get_pipe_config(crtc,
8757 &pipe_config);
d62cf62a
DV		 8758
8759 /* hw state is inconsistent with the pipe A quirk */
8760 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8761 active = crtc->active;
8762
6c49f241
DV		 8763 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8764 base.head) {
3eaba51c 8765 enum pipe pipe;
6c49f241
DV		 8766 if (encoder->base.crtc != &crtc->base)
8767 continue;
3eaba51c
VS		 8768 if (encoder->get_config &&
8769 encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 8770 encoder->get_config(encoder, &pipe_config);
8771 }
8772
510d5f2f
JB		 8773 if (dev_priv->display.get_clock)
8774 dev_priv->display.get_clock(crtc, &pipe_config);
8775
0e8ffe1b
DV		 8776 WARN(crtc->active != active,
8777 "crtc active state doesn't match with hw state "
8778 "(expected %i, found %i)\n", crtc->active, active);
8779
c0b03411
DV		 8780 if (active &&
8781 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8782 WARN(1, "pipe state doesn't match!\n");
8783 intel_dump_pipe_config(crtc, &pipe_config,
8784 "[hw state]");
8785 intel_dump_pipe_config(crtc, &crtc->config,
8786 "[sw state]");
8787 }
8af6cf88
DV		 8788 }
8789}
8790
91d1b4bd
DV		 8791static void
8792check_shared_dpll_state(struct drm_device *dev)
8793{
8794 drm_i915_private_t *dev_priv = dev->dev_private;
8795 struct intel_crtc *crtc;
8796 struct intel_dpll_hw_state dpll_hw_state;
8797 int i;
5358901f
DV		 8798
8799 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8800 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8801 int enabled_crtcs = 0, active_crtcs = 0;
8802 bool active;
8803
8804 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8805
8806 DRM_DEBUG_KMS("%s\n", pll->name);
8807
8808 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8809
8810 WARN(pll->active > pll->refcount,
8811 "more active pll users than references: %i vs %i\n",
8812 pll->active, pll->refcount);
8813 WARN(pll->active && !pll->on,
8814 "pll in active use but not on in sw tracking\n");
35c95375
DV		 8815 WARN(pll->on && !pll->active,
8816 "pll in on but not on in use in sw tracking\n");
5358901f
DV		 8817 WARN(pll->on != active,
8818 "pll on state mismatch (expected %i, found %i)\n",
8819 pll->on, active);
8820
8821 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8822 base.head) {
8823 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8824 enabled_crtcs++;
8825 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8826 active_crtcs++;
8827 }
8828 WARN(pll->active != active_crtcs,
8829 "pll active crtcs mismatch (expected %i, found %i)\n",
8830 pll->active, active_crtcs);
8831 WARN(pll->refcount != enabled_crtcs,
8832 "pll enabled crtcs mismatch (expected %i, found %i)\n",
8833 pll->refcount, enabled_crtcs);
66e985c0
DV		 8834
8835 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8836 sizeof(dpll_hw_state)),
8837 "pll hw state mismatch\n");
5358901f 8838 }
8af6cf88
DV		 8839}
8840
91d1b4bd
DV		 8841void
8842intel_modeset_check_state(struct drm_device *dev)
8843{
8844 check_connector_state(dev);
8845 check_encoder_state(dev);
8846 check_crtc_state(dev);
8847 check_shared_dpll_state(dev);
8848}
8849
f30da187
DV		 8850static int __intel_set_mode(struct drm_crtc *crtc,
8851 struct drm_display_mode *mode,
8852 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 8853{
8854 struct drm_device *dev = crtc->dev;
dbf2b54e 8855 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 8856 struct drm_display_mode *saved_mode, *saved_hwmode;
8857 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 8858 struct intel_crtc *intel_crtc;
8859 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 8860 int ret = 0;
a6778b3c 8861
3ac18232 8862 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 8863 if (!saved_mode)
8864 return -ENOMEM;
3ac18232 8865 saved_hwmode = saved_mode + 1;
a6778b3c 8866
e2e1ed41 8867 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 8868 &prepare_pipes, &disable_pipes);
8869
3ac18232
TG		 8870 *saved_hwmode = crtc->hwmode;
8871 *saved_mode = crtc->mode;
a6778b3c 8872
25c5b266
DV		 8873 /* Hack: Because we don't (yet) support global modeset on multiple
8874 * crtcs, we don't keep track of the new mode for more than one crtc.
8875 * Hence simply check whether any bit is set in modeset_pipes in all the
8876 * pieces of code that are not yet converted to deal with mutliple crtcs
8877 * changing their mode at the same time. */
25c5b266 8878 if (modeset_pipes) {
4e53c2e0 8879 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 8880 if (IS_ERR(pipe_config)) {
8881 ret = PTR_ERR(pipe_config);
8882 pipe_config = NULL;
8883
3ac18232 8884 goto out;
25c5b266 8885 }
c0b03411
DV		 8886 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8887 "[modeset]");
25c5b266 8888 }
a6778b3c 8889
460da916
DV		 8890 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8891 intel_crtc_disable(&intel_crtc->base);
8892
ea9d758d
DV		 8893 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8894 if (intel_crtc->base.enabled)
8895 dev_priv->display.crtc_disable(&intel_crtc->base);
8896 }
a6778b3c 8897
6c4c86f5
DV		 8898 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8899 * to set it here already despite that we pass it down the callchain.
f6e5b160 8900 */
b8cecdf5 8901 if (modeset_pipes) {
25c5b266 8902 crtc->mode = *mode;
b8cecdf5
DV		 8903 /* mode_set/enable/disable functions rely on a correct pipe
8904 * config. */
8905 to_intel_crtc(crtc)->config = *pipe_config;
8906 }
7758a113 8907
ea9d758d
DV		 8908 /* Only after disabling all output pipelines that will be changed can we
8909 * update the the output configuration. */
8910 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8911
47fab737
DV		 8912 if (dev_priv->display.modeset_global_resources)
8913 dev_priv->display.modeset_global_resources(dev);
8914
a6778b3c
DV		 8915 /* Set up the DPLL and any encoders state that needs to adjust or depend
8916 * on the DPLL.
f6e5b160 8917 */
25c5b266 8918 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8919 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8920 x, y, fb);
8921 if (ret)
8922 goto done;
a6778b3c
DV		 8923 }
8924
8925 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8926 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8927 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8928
25c5b266
DV		 8929 if (modeset_pipes) {
8930 /* Store real post-adjustment hardware mode. */
b8cecdf5 8931 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8932
25c5b266
DV		 8933 /* Calculate and store various constants which
8934 * are later needed by vblank and swap-completion
8935 * timestamping. They are derived from true hwmode.
8936 */
8937 drm_calc_timestamping_constants(crtc);
8938 }
a6778b3c
DV		 8939
8940 /* FIXME: add subpixel order */
8941done:
c0c36b94 8942 if (ret && crtc->enabled) {
3ac18232
TG		 8943 crtc->hwmode = *saved_hwmode;
8944 crtc->mode = *saved_mode;
a6778b3c
DV		 8945 }
8946
3ac18232 8947out:
b8cecdf5 8948 kfree(pipe_config);
3ac18232 8949 kfree(saved_mode);
a6778b3c 8950 return ret;
f6e5b160
CW		 8951}
8952
e7457a9a
DL		 8953static int intel_set_mode(struct drm_crtc *crtc,
8954 struct drm_display_mode *mode,
8955 int x, int y, struct drm_framebuffer *fb)
f30da187
DV		 8956{
8957 int ret;
8958
8959 ret = __intel_set_mode(crtc, mode, x, y, fb);
8960
8961 if (ret == 0)
8962 intel_modeset_check_state(crtc->dev);
8963
8964 return ret;
8965}
8966
c0c36b94
CW		 8967void intel_crtc_restore_mode(struct drm_crtc *crtc)
8968{
8969 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8970}
8971
25c5b266
DV		 8972#undef for_each_intel_crtc_masked
8973
d9e55608
DV		 8974static void intel_set_config_free(struct intel_set_config *config)
8975{
8976 if (!config)
8977 return;
8978
1aa4b628
DV		 8979 kfree(config->save_connector_encoders);
8980 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8981 kfree(config);
8982}
8983
85f9eb71
DV		 8984static int intel_set_config_save_state(struct drm_device *dev,
8985 struct intel_set_config *config)
8986{
85f9eb71
DV		 8987 struct drm_encoder *encoder;
8988 struct drm_connector *connector;
8989 int count;
8990
1aa4b628
DV		 8991 config->save_encoder_crtcs =
8992 kcalloc(dev->mode_config.num_encoder,
8993 sizeof(struct drm_crtc *), GFP_KERNEL);
8994 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8995 return -ENOMEM;
8996
1aa4b628
DV		 8997 config->save_connector_encoders =
8998 kcalloc(dev->mode_config.num_connector,
8999 sizeof(struct drm_encoder *), GFP_KERNEL);
9000 if (!config->save_connector_encoders)
85f9eb71
DV		 9001 return -ENOMEM;
9002
9003 /* Copy data. Note that driver private data is not affected.
9004 * Should anything bad happen only the expected state is
9005 * restored, not the drivers personal bookkeeping.
9006 */
85f9eb71
DV		 9007 count = 0;
9008 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 9009 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 9010 }
9011
9012 count = 0;
9013 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 9014 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 9015 }
9016
9017 return 0;
9018}
9019
9020static void intel_set_config_restore_state(struct drm_device *dev,
9021 struct intel_set_config *config)
9022{
9a935856
DV		 9023 struct intel_encoder *encoder;
9024 struct intel_connector *connector;
85f9eb71
DV		 9025 int count;
9026
85f9eb71 9027 count = 0;
9a935856
DV		 9028 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9029 encoder->new_crtc =
9030 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 9031 }
9032
9033 count = 0;
9a935856
DV		 9034 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9035 connector->new_encoder =
9036 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 9037 }
9038}
9039
e3de42b6 9040static bool
2e57f47d 9041is_crtc_connector_off(struct drm_mode_set *set)
e3de42b6
ID		 9042{
9043 int i;
9044
2e57f47d
CW		 9045 if (set->num_connectors == 0)
9046 return false;
9047
9048 if (WARN_ON(set->connectors == NULL))
9049 return false;
9050
9051 for (i = 0; i < set->num_connectors; i++)
9052 if (set->connectors[i]->encoder &&
9053 set->connectors[i]->encoder->crtc == set->crtc &&
9054 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
e3de42b6
ID		 9055 return true;
9056
9057 return false;
9058}
9059
5e2b584e
DV		 9060static void
9061intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9062 struct intel_set_config *config)
9063{
9064
9065 /* We should be able to check here if the fb has the same properties
9066 * and then just flip_or_move it */
2e57f47d
CW		 9067 if (is_crtc_connector_off(set)) {
9068 config->mode_changed = true;
e3de42b6 9069 } else if (set->crtc->fb != set->fb) {
5e2b584e
DV		 9070 /* If we have no fb then treat it as a full mode set */
9071 if (set->crtc->fb == NULL) {
319d9827
JB		 9072 struct intel_crtc *intel_crtc =
9073 to_intel_crtc(set->crtc);
9074
9075 if (intel_crtc->active && i915_fastboot) {
9076 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9077 config->fb_changed = true;
9078 } else {
9079 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9080 config->mode_changed = true;
9081 }
5e2b584e
DV		 9082 } else if (set->fb == NULL) {
9083 config->mode_changed = true;
72f4901e
DV		 9084 } else if (set->fb->pixel_format !=
9085 set->crtc->fb->pixel_format) {
5e2b584e 9086 config->mode_changed = true;
e3de42b6 9087 } else {
5e2b584e 9088 config->fb_changed = true;
e3de42b6 9089 }
5e2b584e
DV		 9090 }
9091
835c5873 9092 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 9093 config->fb_changed = true;
9094
9095 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9096 DRM_DEBUG_KMS("modes are different, full mode set\n");
9097 drm_mode_debug_printmodeline(&set->crtc->mode);
9098 drm_mode_debug_printmodeline(set->mode);
9099 config->mode_changed = true;
9100 }
a1d95703
CW		 9101
9102 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9103 set->crtc->base.id, config->mode_changed, config->fb_changed);
5e2b584e
DV		 9104}
9105
2e431051 9106static int
9a935856
DV		 9107intel_modeset_stage_output_state(struct drm_device *dev,
9108 struct drm_mode_set *set,
9109 struct intel_set_config *config)
50f56119 9110{
85f9eb71 9111 struct drm_crtc *new_crtc;
9a935856
DV		 9112 struct intel_connector *connector;
9113 struct intel_encoder *encoder;
f3f08572 9114 int ro;
50f56119 9115
9abdda74 9116 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 9117 * of connectors. For paranoia, double-check this. */
9118 WARN_ON(!set->fb && (set->num_connectors != 0));
9119 WARN_ON(set->fb && (set->num_connectors == 0));
9120
9a935856
DV		 9121 list_for_each_entry(connector, &dev->mode_config.connector_list,
9122 base.head) {
9123 /* Otherwise traverse passed in connector list and get encoders
9124 * for them. */
50f56119 9125 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 9126 if (set->connectors[ro] == &connector->base) {
9127 connector->new_encoder = connector->encoder;
50f56119
DV		 9128 break;
9129 }
9130 }
9131
9a935856
DV		 9132 /* If we disable the crtc, disable all its connectors. Also, if
9133 * the connector is on the changing crtc but not on the new
9134 * connector list, disable it. */
9135 if ((!set->fb || ro == set->num_connectors) &&
9136 connector->base.encoder &&
9137 connector->base.encoder->crtc == set->crtc) {
9138 connector->new_encoder = NULL;
9139
9140 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9141 connector->base.base.id,
9142 drm_get_connector_name(&connector->base));
9143 }
9144
9145
9146 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 9147 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 9148 config->mode_changed = true;
50f56119
DV		 9149 }
9150 }
9a935856 9151 /* connector->new_encoder is now updated for all connectors. */
50f56119 9152
9a935856 9153 /* Update crtc of enabled connectors. */
9a935856
DV		 9154 list_for_each_entry(connector, &dev->mode_config.connector_list,
9155 base.head) {
9156 if (!connector->new_encoder)
50f56119
DV		 9157 continue;
9158
9a935856 9159 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 9160
9161 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 9162 if (set->connectors[ro] == &connector->base)
50f56119
DV		 9163 new_crtc = set->crtc;
9164 }
9165
9166 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 9167 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9168 new_crtc)) {
5e2b584e 9169 return -EINVAL;
50f56119 9170 }
9a935856
DV		 9171 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9172
9173 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9174 connector->base.base.id,
9175 drm_get_connector_name(&connector->base),
9176 new_crtc->base.id);
9177 }
9178
9179 /* Check for any encoders that needs to be disabled. */
9180 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9181 base.head) {
9182 list_for_each_entry(connector,
9183 &dev->mode_config.connector_list,
9184 base.head) {
9185 if (connector->new_encoder == encoder) {
9186 WARN_ON(!connector->new_encoder->new_crtc);
9187
9188 goto next_encoder;
9189 }
9190 }
9191 encoder->new_crtc = NULL;
9192next_encoder:
9193 /* Only now check for crtc changes so we don't miss encoders
9194 * that will be disabled. */
9195 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 9196 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 9197 config->mode_changed = true;
50f56119
DV		 9198 }
9199 }
9a935856 9200 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 9201
2e431051
DV		 9202 return 0;
9203}
9204
9205static int intel_crtc_set_config(struct drm_mode_set *set)
9206{
9207 struct drm_device *dev;
2e431051
DV		 9208 struct drm_mode_set save_set;
9209 struct intel_set_config *config;
9210 int ret;
2e431051 9211
8d3e375e
DV		 9212 BUG_ON(!set);
9213 BUG_ON(!set->crtc);
9214 BUG_ON(!set->crtc->helper_private);
2e431051 9215
7e53f3a4
DV		 9216 /* Enforce sane interface api - has been abused by the fb helper. */
9217 BUG_ON(!set->mode && set->fb);
9218 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 9219
2e431051
DV		 9220 if (set->fb) {
9221 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9222 set->crtc->base.id, set->fb->base.id,
9223 (int)set->num_connectors, set->x, set->y);
9224 } else {
9225 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 9226 }
9227
9228 dev = set->crtc->dev;
9229
9230 ret = -ENOMEM;
9231 config = kzalloc(sizeof(*config), GFP_KERNEL);
9232 if (!config)
9233 goto out_config;
9234
9235 ret = intel_set_config_save_state(dev, config);
9236 if (ret)
9237 goto out_config;
9238
9239 save_set.crtc = set->crtc;
9240 save_set.mode = &set->crtc->mode;
9241 save_set.x = set->crtc->x;
9242 save_set.y = set->crtc->y;
9243 save_set.fb = set->crtc->fb;
9244
9245 /* Compute whether we need a full modeset, only an fb base update or no
9246 * change at all. In the future we might also check whether only the
9247 * mode changed, e.g. for LVDS where we only change the panel fitter in
9248 * such cases. */
9249 intel_set_config_compute_mode_changes(set, config);
9250
9a935856 9251 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 9252 if (ret)
9253 goto fail;
9254
5e2b584e 9255 if (config->mode_changed) {
c0c36b94
CW		 9256 ret = intel_set_mode(set->crtc, set->mode,
9257 set->x, set->y, set->fb);
5e2b584e 9258 } else if (config->fb_changed) {
4878cae2
VS		 9259 intel_crtc_wait_for_pending_flips(set->crtc);
9260
4f660f49 9261 ret = intel_pipe_set_base(set->crtc,
94352cf9 9262 set->x, set->y, set->fb);
50f56119
DV		 9263 }
9264
2d05eae1 9265 if (ret) {
bf67dfeb
DV		 9266 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9267 set->crtc->base.id, ret);
50f56119 9268fail:
2d05eae1 9269 intel_set_config_restore_state(dev, config);
50f56119 9270
2d05eae1
CW		 9271 /* Try to restore the config */
9272 if (config->mode_changed &&
9273 intel_set_mode(save_set.crtc, save_set.mode,
9274 save_set.x, save_set.y, save_set.fb))
9275 DRM_ERROR("failed to restore config after modeset failure\n");
9276 }
50f56119 9277
d9e55608
DV		 9278out_config:
9279 intel_set_config_free(config);
50f56119
DV		 9280 return ret;
9281}
f6e5b160
CW		 9282
9283static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 9284 .cursor_set = intel_crtc_cursor_set,
9285 .cursor_move = intel_crtc_cursor_move,
9286 .gamma_set = intel_crtc_gamma_set,
50f56119 9287 .set_config = intel_crtc_set_config,
f6e5b160
CW		 9288 .destroy = intel_crtc_destroy,
9289 .page_flip = intel_crtc_page_flip,
9290};
9291
79f689aa
PZ		 9292static void intel_cpu_pll_init(struct drm_device *dev)
9293{
affa9354 9294 if (HAS_DDI(dev))
79f689aa
PZ		 9295 intel_ddi_pll_init(dev);
9296}
9297
5358901f
DV		 9298static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9299 struct intel_shared_dpll *pll,
9300 struct intel_dpll_hw_state *hw_state)
ee7b9f93 9301{
5358901f 9302 uint32_t val;
ee7b9f93 9303
5358901f 9304 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 9305 hw_state->dpll = val;
9306 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9307 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 9308
9309 return val & DPLL_VCO_ENABLE;
9310}
9311
15bdd4cf
DV		 9312static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9313 struct intel_shared_dpll *pll)
9314{
9315 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9316 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9317}
9318
e7b903d2
DV		 9319static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9320 struct intel_shared_dpll *pll)
9321{
e7b903d2
DV		 9322 /* PCH refclock must be enabled first */
9323 assert_pch_refclk_enabled(dev_priv);
9324
15bdd4cf
DV		 9325 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9326
9327 /* Wait for the clocks to stabilize. */
9328 POSTING_READ(PCH_DPLL(pll->id));
9329 udelay(150);
9330
9331 /* The pixel multiplier can only be updated once the
9332 * DPLL is enabled and the clocks are stable.
9333 *
9334 * So write it again.
9335 */
9336 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9337 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9338 udelay(200);
9339}
9340
9341static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9342 struct intel_shared_dpll *pll)
9343{
9344 struct drm_device *dev = dev_priv->dev;
9345 struct intel_crtc *crtc;
e7b903d2
DV		 9346
9347 /* Make sure no transcoder isn't still depending on us. */
9348 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9349 if (intel_crtc_to_shared_dpll(crtc) == pll)
9350 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 9351 }
9352
15bdd4cf
DV		 9353 I915_WRITE(PCH_DPLL(pll->id), 0);
9354 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9355 udelay(200);
9356}
9357
46edb027
DV		 9358static char *ibx_pch_dpll_names[] = {
9359 "PCH DPLL A",
9360 "PCH DPLL B",
9361};
9362
7c74ade1 9363static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 9364{
e7b903d2 9365 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 9366 int i;
9367
7c74ade1 9368 dev_priv->num_shared_dpll = 2;
ee7b9f93 9369
e72f9fbf 9370 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 9371 dev_priv->shared_dplls[i].id = i;
9372 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 9373 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 9374 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9375 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 9376 dev_priv->shared_dplls[i].get_hw_state =
9377 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 9378 }
9379}
9380
7c74ade1
DV		 9381static void intel_shared_dpll_init(struct drm_device *dev)
9382{
e7b903d2 9383 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1
DV		 9384
9385 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9386 ibx_pch_dpll_init(dev);
9387 else
9388 dev_priv->num_shared_dpll = 0;
9389
9390 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9391 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9392 dev_priv->num_shared_dpll);
9393}
9394
b358d0a6 9395static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 9396{
22fd0fab 9397 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 9398 struct intel_crtc *intel_crtc;
9399 int i;
9400
9401 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
9402 if (intel_crtc == NULL)
9403 return;
9404
9405 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9406
9407 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 9408 for (i = 0; i < 256; i++) {
9409 intel_crtc->lut_r[i] = i;
9410 intel_crtc->lut_g[i] = i;
9411 intel_crtc->lut_b[i] = i;
9412 }
9413
80824003
JB		 9414 /* Swap pipes & planes for FBC on pre-965 */
9415 intel_crtc->pipe = pipe;
9416 intel_crtc->plane = pipe;
e2e767ab 9417 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 9418 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 9419 intel_crtc->plane = !pipe;
80824003
JB		 9420 }
9421
22fd0fab
JB		 9422 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9423 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9424 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9425 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9426
79e53945 9427 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 9428}
9429
08d7b3d1 9430int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 9431 struct drm_file *file)
08d7b3d1 9432{
08d7b3d1 9433 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 9434 struct drm_mode_object *drmmode_obj;
9435 struct intel_crtc *crtc;
08d7b3d1 9436
1cff8f6b
DV		 9437 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9438 return -ENODEV;
08d7b3d1 9439
c05422d5
DV		 9440 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9441 DRM_MODE_OBJECT_CRTC);
08d7b3d1 9442
c05422d5 9443 if (!drmmode_obj) {
08d7b3d1
CW		 9444 DRM_ERROR("no such CRTC id\n");
9445 return -EINVAL;
9446 }
9447
c05422d5
DV		 9448 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9449 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 9450
c05422d5 9451 return 0;
08d7b3d1
CW		 9452}
9453
66a9278e 9454static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 9455{
66a9278e
DV		 9456 struct drm_device *dev = encoder->base.dev;
9457 struct intel_encoder *source_encoder;
79e53945 9458 int index_mask = 0;
79e53945
JB		 9459 int entry = 0;
9460
66a9278e
DV		 9461 list_for_each_entry(source_encoder,
9462 &dev->mode_config.encoder_list, base.head) {
9463
9464 if (encoder == source_encoder)
79e53945 9465 index_mask |= (1 << entry);
66a9278e
DV		 9466
9467 /* Intel hw has only one MUX where enocoders could be cloned. */
9468 if (encoder->cloneable && source_encoder->cloneable)
9469 index_mask |= (1 << entry);
9470
79e53945
JB		 9471 entry++;
9472 }
4ef69c7a 9473
79e53945
JB		 9474 return index_mask;
9475}
9476
4d302442
CW		 9477static bool has_edp_a(struct drm_device *dev)
9478{
9479 struct drm_i915_private *dev_priv = dev->dev_private;
9480
9481 if (!IS_MOBILE(dev))
9482 return false;
9483
9484 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9485 return false;
9486
9487 if (IS_GEN5(dev) &&
9488 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9489 return false;
9490
9491 return true;
9492}
9493
79e53945
JB		 9494static void intel_setup_outputs(struct drm_device *dev)
9495{
725e30ad 9496 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 9497 struct intel_encoder *encoder;
cb0953d7 9498 bool dpd_is_edp = false;
79e53945 9499
c9093354 9500 intel_lvds_init(dev);
79e53945 9501
c40c0f5b 9502 if (!IS_ULT(dev))
79935fca 9503 intel_crt_init(dev);
cb0953d7 9504
affa9354 9505 if (HAS_DDI(dev)) {
0e72a5b5
ED		 9506 int found;
9507
9508 /* Haswell uses DDI functions to detect digital outputs */
9509 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9510 /* DDI A only supports eDP */
9511 if (found)
9512 intel_ddi_init(dev, PORT_A);
9513
9514 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9515 * register */
9516 found = I915_READ(SFUSE_STRAP);
9517
9518 if (found & SFUSE_STRAP_DDIB_DETECTED)
9519 intel_ddi_init(dev, PORT_B);
9520 if (found & SFUSE_STRAP_DDIC_DETECTED)
9521 intel_ddi_init(dev, PORT_C);
9522 if (found & SFUSE_STRAP_DDID_DETECTED)
9523 intel_ddi_init(dev, PORT_D);
9524 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 9525 int found;
270b3042
DV		 9526 dpd_is_edp = intel_dpd_is_edp(dev);
9527
9528 if (has_edp_a(dev))
9529 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 9530
dc0fa718 9531 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 9532 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 9533 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 9534 if (!found)
e2debe91 9535 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 9536 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 9537 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 9538 }
9539
dc0fa718 9540 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 9541 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 9542
dc0fa718 9543 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 9544 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 9545
5eb08b69 9546 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 9547 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 9548
270b3042 9549 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 9550 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 9551 } else if (IS_VALLEYVIEW(dev)) {
19c03924 9552 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
6f6005a5
JB		 9553 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9554 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9555 PORT_C);
9556 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9557 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9558 PORT_C);
9559 }
19c03924 9560
dc0fa718 9561 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 9562 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9563 PORT_B);
67cfc203
VS		 9564 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9565 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 9566 }
3cfca973
JN		 9567
9568 intel_dsi_init(dev);
103a196f 9569 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 9570 bool found = false;
7d57382e 9571
e2debe91 9572 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9573 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 9574 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 9575 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9576 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 9577 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 9578 }
27185ae1 9579
e7281eab 9580 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9581 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 9582 }
13520b05
KH		 9583
9584 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 9585
e2debe91 9586 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9587 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 9588 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 9589 }
27185ae1 9590
e2debe91 9591 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 9592
b01f2c3a
JB		 9593 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9594 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 9595 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 9596 }
e7281eab 9597 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9598 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 9599 }
27185ae1 9600
b01f2c3a 9601 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 9602 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 9603 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 9604 } else if (IS_GEN2(dev))
79e53945
JB		 9605 intel_dvo_init(dev);
9606
103a196f 9607 if (SUPPORTS_TV(dev))
79e53945
JB		 9608 intel_tv_init(dev);
9609
4ef69c7a
CW		 9610 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9611 encoder->base.possible_crtcs = encoder->crtc_mask;
9612 encoder->base.possible_clones =
66a9278e 9613 intel_encoder_clones(encoder);
79e53945 9614 }
47356eb6 9615
dde86e2d 9616 intel_init_pch_refclk(dev);
270b3042
DV		 9617
9618 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 9619}
9620
ddfe1567
CW		 9621void intel_framebuffer_fini(struct intel_framebuffer *fb)
9622{
9623 drm_framebuffer_cleanup(&fb->base);
9624 drm_gem_object_unreference_unlocked(&fb->obj->base);
9625}
9626
79e53945
JB		 9627static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9628{
9629 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 9630
ddfe1567 9631 intel_framebuffer_fini(intel_fb);
79e53945
JB		 9632 kfree(intel_fb);
9633}
9634
9635static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 9636 struct drm_file *file,
79e53945
JB		 9637 unsigned int *handle)
9638{
9639 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 9640 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 9641
05394f39 9642 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 9643}
9644
9645static const struct drm_framebuffer_funcs intel_fb_funcs = {
9646 .destroy = intel_user_framebuffer_destroy,
9647 .create_handle = intel_user_framebuffer_create_handle,
9648};
9649
38651674
DA		 9650int intel_framebuffer_init(struct drm_device *dev,
9651 struct intel_framebuffer *intel_fb,
308e5bcb 9652 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 9653 struct drm_i915_gem_object *obj)
79e53945 9654{
a35cdaa0 9655 int pitch_limit;
79e53945
JB		 9656 int ret;
9657
c16ed4be
CW		 9658 if (obj->tiling_mode == I915_TILING_Y) {
9659 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 9660 return -EINVAL;
c16ed4be 9661 }
57cd6508 9662
c16ed4be
CW		 9663 if (mode_cmd->pitches[0] & 63) {
9664 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9665 mode_cmd->pitches[0]);
57cd6508 9666 return -EINVAL;
c16ed4be 9667 }
57cd6508 9668
a35cdaa0
CW		 9669 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9670 pitch_limit = 32*1024;
9671 } else if (INTEL_INFO(dev)->gen >= 4) {
9672 if (obj->tiling_mode)
9673 pitch_limit = 16*1024;
9674 else
9675 pitch_limit = 32*1024;
9676 } else if (INTEL_INFO(dev)->gen >= 3) {
9677 if (obj->tiling_mode)
9678 pitch_limit = 8*1024;
9679 else
9680 pitch_limit = 16*1024;
9681 } else
9682 /* XXX DSPC is limited to 4k tiled */
9683 pitch_limit = 8*1024;
9684
9685 if (mode_cmd->pitches[0] > pitch_limit) {
9686 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9687 obj->tiling_mode ? "tiled" : "linear",
9688 mode_cmd->pitches[0], pitch_limit);
5d7bd705 9689 return -EINVAL;
c16ed4be 9690 }
5d7bd705
VS		 9691
9692 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 9693 mode_cmd->pitches[0] != obj->stride) {
9694 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9695 mode_cmd->pitches[0], obj->stride);
5d7bd705 9696 return -EINVAL;
c16ed4be 9697 }
5d7bd705 9698
57779d06 9699 /* Reject formats not supported by any plane early. */
308e5bcb 9700 switch (mode_cmd->pixel_format) {
57779d06 9701 case DRM_FORMAT_C8:
04b3924d
VS		 9702 case DRM_FORMAT_RGB565:
9703 case DRM_FORMAT_XRGB8888:
9704 case DRM_FORMAT_ARGB8888:
57779d06
VS		 9705 break;
9706 case DRM_FORMAT_XRGB1555:
9707 case DRM_FORMAT_ARGB1555:
c16ed4be 9708 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 9709 DRM_DEBUG("unsupported pixel format: %s\n",
9710 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9711 return -EINVAL;
c16ed4be 9712 }
57779d06
VS		 9713 break;
9714 case DRM_FORMAT_XBGR8888:
9715 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 9716 case DRM_FORMAT_XRGB2101010:
9717 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 9718 case DRM_FORMAT_XBGR2101010:
9719 case DRM_FORMAT_ABGR2101010:
c16ed4be 9720 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 9721 DRM_DEBUG("unsupported pixel format: %s\n",
9722 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9723 return -EINVAL;
c16ed4be 9724 }
b5626747 9725 break;
04b3924d
VS		 9726 case DRM_FORMAT_YUYV:
9727 case DRM_FORMAT_UYVY:
9728 case DRM_FORMAT_YVYU:
9729 case DRM_FORMAT_VYUY:
c16ed4be 9730 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 9731 DRM_DEBUG("unsupported pixel format: %s\n",
9732 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9733 return -EINVAL;
c16ed4be 9734 }
57cd6508
CW		 9735 break;
9736 default:
4ee62c76
VS		 9737 DRM_DEBUG("unsupported pixel format: %s\n",
9738 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 9739 return -EINVAL;
9740 }
9741
90f9a336
VS		 9742 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9743 if (mode_cmd->offsets[0] != 0)
9744 return -EINVAL;
9745
c7d73f6a
DV		 9746 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9747 intel_fb->obj = obj;
9748
79e53945
JB		 9749 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9750 if (ret) {
9751 DRM_ERROR("framebuffer init failed %d\n", ret);
9752 return ret;
9753 }
9754
79e53945
JB		 9755 return 0;
9756}
9757
79e53945
JB		 9758static struct drm_framebuffer *
9759intel_user_framebuffer_create(struct drm_device *dev,
9760 struct drm_file *filp,
308e5bcb 9761 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 9762{
05394f39 9763 struct drm_i915_gem_object *obj;
79e53945 9764
308e5bcb
JB		 9765 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9766 mode_cmd->handles[0]));
c8725226 9767 if (&obj->base == NULL)
cce13ff7 9768 return ERR_PTR(-ENOENT);
79e53945 9769
d2dff872 9770 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 9771}
9772
79e53945 9773static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 9774 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 9775 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 9776};
9777
e70236a8
JB		 9778/* Set up chip specific display functions */
9779static void intel_init_display(struct drm_device *dev)
9780{
9781 struct drm_i915_private *dev_priv = dev->dev_private;
9782
ee9300bb
DV		 9783 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9784 dev_priv->display.find_dpll = g4x_find_best_dpll;
9785 else if (IS_VALLEYVIEW(dev))
9786 dev_priv->display.find_dpll = vlv_find_best_dpll;
9787 else if (IS_PINEVIEW(dev))
9788 dev_priv->display.find_dpll = pnv_find_best_dpll;
9789 else
9790 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9791
affa9354 9792 if (HAS_DDI(dev)) {
0e8ffe1b 9793 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 9794 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 9795 dev_priv->display.crtc_enable = haswell_crtc_enable;
9796 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 9797 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 9798 dev_priv->display.update_plane = ironlake_update_plane;
9799 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 9800 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f1f644dc 9801 dev_priv->display.get_clock = ironlake_crtc_clock_get;
f564048e 9802 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 9803 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9804 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 9805 dev_priv->display.off = ironlake_crtc_off;
17638cd6 9806 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 9807 } else if (IS_VALLEYVIEW(dev)) {
9808 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f1f644dc 9809 dev_priv->display.get_clock = i9xx_crtc_clock_get;
89b667f8
JB		 9810 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9811 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9812 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9813 dev_priv->display.off = i9xx_crtc_off;
9814 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9815 } else {
0e8ffe1b 9816 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f1f644dc 9817 dev_priv->display.get_clock = i9xx_crtc_clock_get;
f564048e 9818 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 9819 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9820 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 9821 dev_priv->display.off = i9xx_crtc_off;
17638cd6 9822 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9823 }
e70236a8 9824
e70236a8 9825 /* Returns the core display clock speed */
25eb05fc
JB		 9826 if (IS_VALLEYVIEW(dev))
9827 dev_priv->display.get_display_clock_speed =
9828 valleyview_get_display_clock_speed;
9829 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 9830 dev_priv->display.get_display_clock_speed =
9831 i945_get_display_clock_speed;
9832 else if (IS_I915G(dev))
9833 dev_priv->display.get_display_clock_speed =
9834 i915_get_display_clock_speed;
257a7ffc 9835 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 9836 dev_priv->display.get_display_clock_speed =
9837 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 9838 else if (IS_PINEVIEW(dev))
9839 dev_priv->display.get_display_clock_speed =
9840 pnv_get_display_clock_speed;
e70236a8
JB		 9841 else if (IS_I915GM(dev))
9842 dev_priv->display.get_display_clock_speed =
9843 i915gm_get_display_clock_speed;
9844 else if (IS_I865G(dev))
9845 dev_priv->display.get_display_clock_speed =
9846 i865_get_display_clock_speed;
f0f8a9ce 9847 else if (IS_I85X(dev))
e70236a8
JB		 9848 dev_priv->display.get_display_clock_speed =
9849 i855_get_display_clock_speed;
9850 else /* 852, 830 */
9851 dev_priv->display.get_display_clock_speed =
9852 i830_get_display_clock_speed;
9853
7f8a8569 9854 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 9855 if (IS_GEN5(dev)) {
674cf967 9856 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 9857 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 9858 } else if (IS_GEN6(dev)) {
674cf967 9859 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 9860 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 9861 } else if (IS_IVYBRIDGE(dev)) {
9862 /* FIXME: detect B0+ stepping and use auto training */
9863 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 9864 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 9865 dev_priv->display.modeset_global_resources =
9866 ivb_modeset_global_resources;
c82e4d26
ED		 9867 } else if (IS_HASWELL(dev)) {
9868 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 9869 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 9870 dev_priv->display.modeset_global_resources =
9871 haswell_modeset_global_resources;
a0e63c22 9872 }
6067aaea 9873 } else if (IS_G4X(dev)) {
e0dac65e 9874 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 9875 }
8c9f3aaf
JB		 9876
9877 /* Default just returns -ENODEV to indicate unsupported */
9878 dev_priv->display.queue_flip = intel_default_queue_flip;
9879
9880 switch (INTEL_INFO(dev)->gen) {
9881 case 2:
9882 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9883 break;
9884
9885 case 3:
9886 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9887 break;
9888
9889 case 4:
9890 case 5:
9891 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9892 break;
9893
9894 case 6:
9895 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9896 break;
7c9017e5
JB		 9897 case 7:
9898 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9899 break;
8c9f3aaf 9900 }
e70236a8
JB		 9901}
9902
b690e96c
JB		 9903/*
9904 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9905 * resume, or other times. This quirk makes sure that's the case for
9906 * affected systems.
9907 */
0206e353 9908static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 9909{
9910 struct drm_i915_private *dev_priv = dev->dev_private;
9911
9912 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 9913 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 9914}
9915
435793df
KP		 9916/*
9917 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9918 */
9919static void quirk_ssc_force_disable(struct drm_device *dev)
9920{
9921 struct drm_i915_private *dev_priv = dev->dev_private;
9922 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 9923 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 9924}
9925
4dca20ef 9926/*
5a15ab5b
CE		 9927 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9928 * brightness value
4dca20ef
CE		 9929 */
9930static void quirk_invert_brightness(struct drm_device *dev)
9931{
9932 struct drm_i915_private *dev_priv = dev->dev_private;
9933 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 9934 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 9935}
9936
e85843be
KM		 9937/*
9938 * Some machines (Dell XPS13) suffer broken backlight controls if
9939 * BLM_PCH_PWM_ENABLE is set.
9940 */
9941static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
9942{
9943 struct drm_i915_private *dev_priv = dev->dev_private;
9944 dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
9945 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
9946}
9947
b690e96c
JB		 9948struct intel_quirk {
9949 int device;
9950 int subsystem_vendor;
9951 int subsystem_device;
9952 void (*hook)(struct drm_device *dev);
9953};
9954
5f85f176
EE		 9955/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9956struct intel_dmi_quirk {
9957 void (*hook)(struct drm_device *dev);
9958 const struct dmi_system_id (*dmi_id_list)[];
9959};
9960
9961static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9962{
9963 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9964 return 1;
9965}
9966
9967static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9968 {
9969 .dmi_id_list = &(const struct dmi_system_id[]) {
9970 {
9971 .callback = intel_dmi_reverse_brightness,
9972 .ident = "NCR Corporation",
9973 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9974 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9975 },
9976 },
9977 { } /* terminating entry */
9978 },
9979 .hook = quirk_invert_brightness,
9980 },
9981};
9982
c43b5634 9983static struct intel_quirk intel_quirks[] = {
b690e96c 9984 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 9985 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 9986
b690e96c
JB		 9987 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9988 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9989
b690e96c
JB		 9990 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9991 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9992
ccd0d36e 9993 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 9994 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 9995 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 9996
9997 /* Lenovo U160 cannot use SSC on LVDS */
9998 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 9999
10000 /* Sony Vaio Y cannot use SSC on LVDS */
10001 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 10002
10003 /* Acer Aspire 5734Z must invert backlight brightness */
10004 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 10005
10006 /* Acer/eMachines G725 */
10007 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 10008
10009 /* Acer/eMachines e725 */
10010 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 10011
10012 /* Acer/Packard Bell NCL20 */
10013 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 10014
10015 /* Acer Aspire 4736Z */
10016 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
e85843be
KM		 10017
10018 /* Dell XPS13 HD Sandy Bridge */
10019 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10020 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10021 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
b690e96c
JB		 10022};
10023
10024static void intel_init_quirks(struct drm_device *dev)
10025{
10026 struct pci_dev *d = dev->pdev;
10027 int i;
10028
10029 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10030 struct intel_quirk *q = &intel_quirks[i];
10031
10032 if (d->device == q->device &&
10033 (d->subsystem_vendor == q->subsystem_vendor ||
10034 q->subsystem_vendor == PCI_ANY_ID) &&
10035 (d->subsystem_device == q->subsystem_device ||
10036 q->subsystem_device == PCI_ANY_ID))
10037 q->hook(dev);
10038 }
5f85f176
EE		 10039 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10040 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10041 intel_dmi_quirks[i].hook(dev);
10042 }
b690e96c
JB		 10043}
10044
9cce37f4
JB		 10045/* Disable the VGA plane that we never use */
10046static void i915_disable_vga(struct drm_device *dev)
10047{
10048 struct drm_i915_private *dev_priv = dev->dev_private;
10049 u8 sr1;
766aa1c4 10050 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 10051
10052 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 10053 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 10054 sr1 = inb(VGA_SR_DATA);
10055 outb(sr1 | 1<<5, VGA_SR_DATA);
81b5c7bc
AW		 10056
10057 /* Disable VGA memory on Intel HD */
10058 if (HAS_PCH_SPLIT(dev)) {
10059 outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10060 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10061 VGA_RSRC_NORMAL_IO |
10062 VGA_RSRC_NORMAL_MEM);
10063 }
10064
9cce37f4
JB		 10065 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10066 udelay(300);
10067
10068 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10069 POSTING_READ(vga_reg);
10070}
10071
81b5c7bc
AW		 10072static void i915_enable_vga(struct drm_device *dev)
10073{
10074 /* Enable VGA memory on Intel HD */
10075 if (HAS_PCH_SPLIT(dev)) {
10076 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10077 outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10078 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10079 VGA_RSRC_LEGACY_MEM |
10080 VGA_RSRC_NORMAL_IO |
10081 VGA_RSRC_NORMAL_MEM);
10082 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10083 }
10084}
10085
f817586c
DV		 10086void intel_modeset_init_hw(struct drm_device *dev)
10087{
fa42e23c 10088 intel_init_power_well(dev);
0232e927 10089
a8f78b58
ED		 10090 intel_prepare_ddi(dev);
10091
f817586c
DV		 10092 intel_init_clock_gating(dev);
10093
79f5b2c7 10094 mutex_lock(&dev->struct_mutex);
8090c6b9 10095 intel_enable_gt_powersave(dev);
79f5b2c7 10096 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 10097}
10098
7d708ee4
ID		 10099void intel_modeset_suspend_hw(struct drm_device *dev)
10100{
10101 intel_suspend_hw(dev);
10102}
10103
79e53945
JB		 10104void intel_modeset_init(struct drm_device *dev)
10105{
652c393a 10106 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 10107 int i, j, ret;
79e53945
JB		 10108
10109 drm_mode_config_init(dev);
10110
10111 dev->mode_config.min_width = 0;
10112 dev->mode_config.min_height = 0;
10113
019d96cb
DA		 10114 dev->mode_config.preferred_depth = 24;
10115 dev->mode_config.prefer_shadow = 1;
10116
e6ecefaa 10117 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 10118
b690e96c
JB		 10119 intel_init_quirks(dev);
10120
1fa61106
ED		 10121 intel_init_pm(dev);
10122
e3c74757
BW		 10123 if (INTEL_INFO(dev)->num_pipes == 0)
10124 return;
10125
e70236a8
JB		 10126 intel_init_display(dev);
10127
a6c45cf0
CW		 10128 if (IS_GEN2(dev)) {
10129 dev->mode_config.max_width = 2048;
10130 dev->mode_config.max_height = 2048;
10131 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 10132 dev->mode_config.max_width = 4096;
10133 dev->mode_config.max_height = 4096;
79e53945 10134 } else {
a6c45cf0
CW		 10135 dev->mode_config.max_width = 8192;
10136 dev->mode_config.max_height = 8192;
79e53945 10137 }
5d4545ae 10138 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 10139
28c97730 10140 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 10141 INTEL_INFO(dev)->num_pipes,
10142 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 10143
08e2a7de 10144 for_each_pipe(i) {
79e53945 10145 intel_crtc_init(dev, i);
7f1f3851
JB		 10146 for (j = 0; j < dev_priv->num_plane; j++) {
10147 ret = intel_plane_init(dev, i, j);
10148 if (ret)
06da8da2
VS		 10149 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10150 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 10151 }
79e53945
JB		 10152 }
10153
79f689aa 10154 intel_cpu_pll_init(dev);
e72f9fbf 10155 intel_shared_dpll_init(dev);
ee7b9f93 10156
9cce37f4
JB		 10157 /* Just disable it once at startup */
10158 i915_disable_vga(dev);
79e53945 10159 intel_setup_outputs(dev);
11be49eb
CW		 10160
10161 /* Just in case the BIOS is doing something questionable. */
10162 intel_disable_fbc(dev);
2c7111db
CW		 10163}
10164
24929352
DV		 10165static void
10166intel_connector_break_all_links(struct intel_connector *connector)
10167{
10168 connector->base.dpms = DRM_MODE_DPMS_OFF;
10169 connector->base.encoder = NULL;
10170 connector->encoder->connectors_active = false;
10171 connector->encoder->base.crtc = NULL;
10172}
10173
7fad798e
DV		 10174static void intel_enable_pipe_a(struct drm_device *dev)
10175{
10176 struct intel_connector *connector;
10177 struct drm_connector *crt = NULL;
10178 struct intel_load_detect_pipe load_detect_temp;
10179
10180 /* We can't just switch on the pipe A, we need to set things up with a
10181 * proper mode and output configuration. As a gross hack, enable pipe A
10182 * by enabling the load detect pipe once. */
10183 list_for_each_entry(connector,
10184 &dev->mode_config.connector_list,
10185 base.head) {
10186 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10187 crt = &connector->base;
10188 break;
10189 }
10190 }
10191
10192 if (!crt)
10193 return;
10194
10195 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10196 intel_release_load_detect_pipe(crt, &load_detect_temp);
10197
652c393a 10198
7fad798e
DV		 10199}
10200
fa555837
DV		 10201static bool
10202intel_check_plane_mapping(struct intel_crtc *crtc)
10203{
7eb552ae
BW		 10204 struct drm_device *dev = crtc->base.dev;
10205 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 10206 u32 reg, val;
10207
7eb552ae 10208 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 10209 return true;
10210
10211 reg = DSPCNTR(!crtc->plane);
10212 val = I915_READ(reg);
10213
10214 if ((val & DISPLAY_PLANE_ENABLE) &&
10215 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10216 return false;
10217
10218 return true;
10219}
10220
24929352
DV		 10221static void intel_sanitize_crtc(struct intel_crtc *crtc)
10222{
10223 struct drm_device *dev = crtc->base.dev;
10224 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 10225 u32 reg;
24929352 10226
24929352 10227 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 10228 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 10229 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10230
10231 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 10232 * disable the crtc (and hence change the state) if it is wrong. Note
10233 * that gen4+ has a fixed plane -> pipe mapping. */
10234 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 10235 struct intel_connector *connector;
10236 bool plane;
10237
24929352
DV		 10238 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10239 crtc->base.base.id);
10240
10241 /* Pipe has the wrong plane attached and the plane is active.
10242 * Temporarily change the plane mapping and disable everything
10243 * ... */
10244 plane = crtc->plane;
10245 crtc->plane = !plane;
10246 dev_priv->display.crtc_disable(&crtc->base);
10247 crtc->plane = plane;
10248
10249 /* ... and break all links. */
10250 list_for_each_entry(connector, &dev->mode_config.connector_list,
10251 base.head) {
10252 if (connector->encoder->base.crtc != &crtc->base)
10253 continue;
10254
10255 intel_connector_break_all_links(connector);
10256 }
10257
10258 WARN_ON(crtc->active);
10259 crtc->base.enabled = false;
10260 }
24929352 10261
7fad798e
DV		 10262 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10263 crtc->pipe == PIPE_A && !crtc->active) {
10264 /* BIOS forgot to enable pipe A, this mostly happens after
10265 * resume. Force-enable the pipe to fix this, the update_dpms
10266 * call below we restore the pipe to the right state, but leave
10267 * the required bits on. */
10268 intel_enable_pipe_a(dev);
10269 }
10270
24929352
DV		 10271 /* Adjust the state of the output pipe according to whether we
10272 * have active connectors/encoders. */
10273 intel_crtc_update_dpms(&crtc->base);
10274
10275 if (crtc->active != crtc->base.enabled) {
10276 struct intel_encoder *encoder;
10277
10278 /* This can happen either due to bugs in the get_hw_state
10279 * functions or because the pipe is force-enabled due to the
10280 * pipe A quirk. */
10281 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10282 crtc->base.base.id,
10283 crtc->base.enabled ? "enabled" : "disabled",
10284 crtc->active ? "enabled" : "disabled");
10285
10286 crtc->base.enabled = crtc->active;
10287
10288 /* Because we only establish the connector -> encoder ->
10289 * crtc links if something is active, this means the
10290 * crtc is now deactivated. Break the links. connector
10291 * -> encoder links are only establish when things are
10292 * actually up, hence no need to break them. */
10293 WARN_ON(crtc->active);
10294
10295 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10296 WARN_ON(encoder->connectors_active);
10297 encoder->base.crtc = NULL;
10298 }
10299 }
10300}
10301
10302static void intel_sanitize_encoder(struct intel_encoder *encoder)
10303{
10304 struct intel_connector *connector;
10305 struct drm_device *dev = encoder->base.dev;
10306
10307 /* We need to check both for a crtc link (meaning that the
10308 * encoder is active and trying to read from a pipe) and the
10309 * pipe itself being active. */
10310 bool has_active_crtc = encoder->base.crtc &&
10311 to_intel_crtc(encoder->base.crtc)->active;
10312
10313 if (encoder->connectors_active && !has_active_crtc) {
10314 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10315 encoder->base.base.id,
10316 drm_get_encoder_name(&encoder->base));
10317
10318 /* Connector is active, but has no active pipe. This is
10319 * fallout from our resume register restoring. Disable
10320 * the encoder manually again. */
10321 if (encoder->base.crtc) {
10322 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10323 encoder->base.base.id,
10324 drm_get_encoder_name(&encoder->base));
10325 encoder->disable(encoder);
10326 }
10327
10328 /* Inconsistent output/port/pipe state happens presumably due to
10329 * a bug in one of the get_hw_state functions. Or someplace else
10330 * in our code, like the register restore mess on resume. Clamp
10331 * things to off as a safer default. */
10332 list_for_each_entry(connector,
10333 &dev->mode_config.connector_list,
10334 base.head) {
10335 if (connector->encoder != encoder)
10336 continue;
10337
10338 intel_connector_break_all_links(connector);
10339 }
10340 }
10341 /* Enabled encoders without active connectors will be fixed in
10342 * the crtc fixup. */
10343}
10344
44cec740 10345void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 10346{
10347 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 10348 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 10349
8dc8a27c
PZ		 10350 /* This function can be called both from intel_modeset_setup_hw_state or
10351 * at a very early point in our resume sequence, where the power well
10352 * structures are not yet restored. Since this function is at a very
10353 * paranoid "someone might have enabled VGA while we were not looking"
10354 * level, just check if the power well is enabled instead of trying to
10355 * follow the "don't touch the power well if we don't need it" policy
10356 * the rest of the driver uses. */
10357 if (HAS_POWER_WELL(dev) &&
6aedd1f5 10358 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
8dc8a27c
PZ		 10359 return;
10360
0fde901f
KM		 10361 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
10362 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 10363 i915_disable_vga(dev);
0fde901f
KM		 10364 }
10365}
10366
30e984df 10367static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 10368{
10369 struct drm_i915_private *dev_priv = dev->dev_private;
10370 enum pipe pipe;
24929352
DV		 10371 struct intel_crtc *crtc;
10372 struct intel_encoder *encoder;
10373 struct intel_connector *connector;
5358901f 10374 int i;
24929352 10375
0e8ffe1b
DV		 10376 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10377 base.head) {
88adfff1 10378 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 10379
0e8ffe1b
DV		 10380 crtc->active = dev_priv->display.get_pipe_config(crtc,
10381 &crtc->config);
24929352
DV		 10382
10383 crtc->base.enabled = crtc->active;
10384
10385 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10386 crtc->base.base.id,
10387 crtc->active ? "enabled" : "disabled");
10388 }
10389
5358901f 10390 /* FIXME: Smash this into the new shared dpll infrastructure. */
affa9354 10391 if (HAS_DDI(dev))
6441ab5f
PZ		 10392 intel_ddi_setup_hw_pll_state(dev);
10393
5358901f
DV		 10394 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10395 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10396
10397 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10398 pll->active = 0;
10399 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10400 base.head) {
10401 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10402 pll->active++;
10403 }
10404 pll->refcount = pll->active;
10405
35c95375
DV		 10406 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10407 pll->name, pll->refcount, pll->on);
5358901f
DV		 10408 }
10409
24929352
DV		 10410 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10411 base.head) {
10412 pipe = 0;
10413
10414 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 10415 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10416 encoder->base.crtc = &crtc->base;
510d5f2f 10417 if (encoder->get_config)
045ac3b5 10418 encoder->get_config(encoder, &crtc->config);
24929352
DV		 10419 } else {
10420 encoder->base.crtc = NULL;
10421 }
10422
10423 encoder->connectors_active = false;
10424 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10425 encoder->base.base.id,
10426 drm_get_encoder_name(&encoder->base),
10427 encoder->base.crtc ? "enabled" : "disabled",
10428 pipe);
10429 }
10430
510d5f2f
JB		 10431 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10432 base.head) {
10433 if (!crtc->active)
10434 continue;
10435 if (dev_priv->display.get_clock)
10436 dev_priv->display.get_clock(crtc,
10437 &crtc->config);
10438 }
10439
24929352
DV		 10440 list_for_each_entry(connector, &dev->mode_config.connector_list,
10441 base.head) {
10442 if (connector->get_hw_state(connector)) {
10443 connector->base.dpms = DRM_MODE_DPMS_ON;
10444 connector->encoder->connectors_active = true;
10445 connector->base.encoder = &connector->encoder->base;
10446 } else {
10447 connector->base.dpms = DRM_MODE_DPMS_OFF;
10448 connector->base.encoder = NULL;
10449 }
10450 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10451 connector->base.base.id,
10452 drm_get_connector_name(&connector->base),
10453 connector->base.encoder ? "enabled" : "disabled");
10454 }
30e984df
DV		 10455}
10456
10457/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10458 * and i915 state tracking structures. */
10459void intel_modeset_setup_hw_state(struct drm_device *dev,
10460 bool force_restore)
10461{
10462 struct drm_i915_private *dev_priv = dev->dev_private;
10463 enum pipe pipe;
10464 struct drm_plane *plane;
10465 struct intel_crtc *crtc;
10466 struct intel_encoder *encoder;
35c95375 10467 int i;
30e984df
DV		 10468
10469 intel_modeset_readout_hw_state(dev);
24929352 10470
babea61d
JB		 10471 /*
10472 * Now that we have the config, copy it to each CRTC struct
10473 * Note that this could go away if we move to using crtc_config
10474 * checking everywhere.
10475 */
10476 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10477 base.head) {
10478 if (crtc->active && i915_fastboot) {
10479 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10480
10481 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10482 crtc->base.base.id);
10483 drm_mode_debug_printmodeline(&crtc->base.mode);
10484 }
10485 }
10486
24929352
DV		 10487 /* HW state is read out, now we need to sanitize this mess. */
10488 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10489 base.head) {
10490 intel_sanitize_encoder(encoder);
10491 }
10492
10493 for_each_pipe(pipe) {
10494 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10495 intel_sanitize_crtc(crtc);
c0b03411 10496 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 10497 }
9a935856 10498
35c95375
DV		 10499 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10500 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10501
10502 if (!pll->on || pll->active)
10503 continue;
10504
10505 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10506
10507 pll->disable(dev_priv, pll);
10508 pll->on = false;
10509 }
10510
45e2b5f6 10511 if (force_restore) {
f30da187
DV		 10512 /*
10513 * We need to use raw interfaces for restoring state to avoid
10514 * checking (bogus) intermediate states.
10515 */
45e2b5f6 10516 for_each_pipe(pipe) {
b5644d05
JB		 10517 struct drm_crtc *crtc =
10518 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 10519
10520 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10521 crtc->fb);
45e2b5f6 10522 }
b5644d05
JB		 10523 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
10524 intel_plane_restore(plane);
0fde901f
KM		 10525
10526 i915_redisable_vga(dev);
45e2b5f6
DV		 10527 } else {
10528 intel_modeset_update_staged_output_state(dev);
10529 }
8af6cf88
DV		 10530
10531 intel_modeset_check_state(dev);
2e938892
DV		 10532
10533 drm_mode_config_reset(dev);
2c7111db
CW		 10534}
10535
10536void intel_modeset_gem_init(struct drm_device *dev)
10537{
1833b134 10538 intel_modeset_init_hw(dev);
02e792fb
DV		 10539
10540 intel_setup_overlay(dev);
24929352 10541
45e2b5f6 10542 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 10543}
10544
10545void intel_modeset_cleanup(struct drm_device *dev)
10546{
652c393a
JB		 10547 struct drm_i915_private *dev_priv = dev->dev_private;
10548 struct drm_crtc *crtc;
652c393a 10549
fd0c0642
DV		 10550 /*
10551 * Interrupts and polling as the first thing to avoid creating havoc.
10552 * Too much stuff here (turning of rps, connectors, ...) would
10553 * experience fancy races otherwise.
10554 */
10555 drm_irq_uninstall(dev);
10556 cancel_work_sync(&dev_priv->hotplug_work);
10557 /*
10558 * Due to the hpd irq storm handling the hotplug work can re-arm the
10559 * poll handlers. Hence disable polling after hpd handling is shut down.
10560 */
f87ea761 10561 drm_kms_helper_poll_fini(dev);
fd0c0642 10562
652c393a
JB		 10563 mutex_lock(&dev->struct_mutex);
10564
723bfd70
JB		 10565 intel_unregister_dsm_handler();
10566
652c393a
JB		 10567 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10568 /* Skip inactive CRTCs */
10569 if (!crtc->fb)
10570 continue;
10571
3dec0095 10572 intel_increase_pllclock(crtc);
652c393a
JB		 10573 }
10574
973d04f9 10575 intel_disable_fbc(dev);
e70236a8 10576
81b5c7bc
AW		 10577 i915_enable_vga(dev);
10578
8090c6b9 10579 intel_disable_gt_powersave(dev);
0cdab21f 10580
930ebb46
DV		 10581 ironlake_teardown_rc6(dev);
10582
69341a5e
KH		 10583 mutex_unlock(&dev->struct_mutex);
10584
1630fe75
CW		 10585 /* flush any delayed tasks or pending work */
10586 flush_scheduled_work();
10587
dc652f90
JN		 10588 /* destroy backlight, if any, before the connectors */
10589 intel_panel_destroy_backlight(dev);
10590
79e53945 10591 drm_mode_config_cleanup(dev);
4d7bb011
DV		 10592
10593 intel_cleanup_overlay(dev);
79e53945
JB		 10594}
10595
f1c79df3
ZW		 10596/*
10597 * Return which encoder is currently attached for connector.
10598 */
df0e9248 10599struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 10600{
df0e9248
CW		 10601 return &intel_attached_encoder(connector)->base;
10602}
f1c79df3 10603
df0e9248
CW		 10604void intel_connector_attach_encoder(struct intel_connector *connector,
10605 struct intel_encoder *encoder)
10606{
10607 connector->encoder = encoder;
10608 drm_mode_connector_attach_encoder(&connector->base,
10609 &encoder->base);
79e53945 10610}
28d52043
DA		 10611
10612/*
10613 * set vga decode state - true == enable VGA decode
10614 */
10615int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10616{
10617 struct drm_i915_private *dev_priv = dev->dev_private;
10618 u16 gmch_ctrl;
10619
10620 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10621 if (state)
10622 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10623 else
10624 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10625 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10626 return 0;
10627}
c4a1d9e4 10628
c4a1d9e4 10629struct intel_display_error_state {
ff57f1b0
PZ		 10630
10631 u32 power_well_driver;
10632
63b66e5b
CW		 10633 int num_transcoders;
10634
c4a1d9e4
CW		 10635 struct intel_cursor_error_state {
10636 u32 control;
10637 u32 position;
10638 u32 base;
10639 u32 size;
52331309 10640 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 10641
10642 struct intel_pipe_error_state {
c4a1d9e4 10643 u32 source;
52331309 10644 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 10645
10646 struct intel_plane_error_state {
10647 u32 control;
10648 u32 stride;
10649 u32 size;
10650 u32 pos;
10651 u32 addr;
10652 u32 surface;
10653 u32 tile_offset;
52331309 10654 } plane[I915_MAX_PIPES];
63b66e5b
CW		 10655
10656 struct intel_transcoder_error_state {
10657 enum transcoder cpu_transcoder;
10658
10659 u32 conf;
10660
10661 u32 htotal;
10662 u32 hblank;
10663 u32 hsync;
10664 u32 vtotal;
10665 u32 vblank;
10666 u32 vsync;
10667 } transcoder[4];
c4a1d9e4
CW		 10668};
10669
10670struct intel_display_error_state *
10671intel_display_capture_error_state(struct drm_device *dev)
10672{
0206e353 10673 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 10674 struct intel_display_error_state *error;
63b66e5b
CW		 10675 int transcoders[] = {
10676 TRANSCODER_A,
10677 TRANSCODER_B,
10678 TRANSCODER_C,
10679 TRANSCODER_EDP,
10680 };
c4a1d9e4
CW		 10681 int i;
10682
63b66e5b
CW		 10683 if (INTEL_INFO(dev)->num_pipes == 0)
10684 return NULL;
10685
c4a1d9e4
CW		 10686 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10687 if (error == NULL)
10688 return NULL;
10689
ff57f1b0
PZ		 10690 if (HAS_POWER_WELL(dev))
10691 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10692
52331309 10693 for_each_pipe(i) {
a18c4c3d
PZ		 10694 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10695 error->cursor[i].control = I915_READ(CURCNTR(i));
10696 error->cursor[i].position = I915_READ(CURPOS(i));
10697 error->cursor[i].base = I915_READ(CURBASE(i));
10698 } else {
10699 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10700 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10701 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10702 }
c4a1d9e4
CW		 10703
10704 error->plane[i].control = I915_READ(DSPCNTR(i));
10705 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 10706 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 10707 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 10708 error->plane[i].pos = I915_READ(DSPPOS(i));
10709 }
ca291363
PZ		 10710 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10711 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 10712 if (INTEL_INFO(dev)->gen >= 4) {
10713 error->plane[i].surface = I915_READ(DSPSURF(i));
10714 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10715 }
10716
c4a1d9e4 10717 error->pipe[i].source = I915_READ(PIPESRC(i));
63b66e5b
CW		 10718 }
10719
10720 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
10721 if (HAS_DDI(dev_priv->dev))
10722 error->num_transcoders++; /* Account for eDP. */
10723
10724 for (i = 0; i < error->num_transcoders; i++) {
10725 enum transcoder cpu_transcoder = transcoders[i];
10726
10727 error->transcoder[i].cpu_transcoder = cpu_transcoder;
10728
10729 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10730 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10731 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10732 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10733 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10734 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10735 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 10736 }
10737
12d217c7
PZ		 10738 /* In the code above we read the registers without checking if the power
10739 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10740 * prevent the next I915_WRITE from detecting it and printing an error
10741 * message. */
907b28c5 10742 intel_uncore_clear_errors(dev);
12d217c7 10743
c4a1d9e4
CW		 10744 return error;
10745}
10746
edc3d884
MK		 10747#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10748
c4a1d9e4 10749void
edc3d884 10750intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 10751 struct drm_device *dev,
10752 struct intel_display_error_state *error)
10753{
10754 int i;
10755
63b66e5b
CW		 10756 if (!error)
10757 return;
10758
edc3d884 10759 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 10760 if (HAS_POWER_WELL(dev))
edc3d884 10761 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 10762 error->power_well_driver);
52331309 10763 for_each_pipe(i) {
edc3d884 10764 err_printf(m, "Pipe [%d]:\n", i);
edc3d884 10765 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
edc3d884
MK		 10766
10767 err_printf(m, "Plane [%d]:\n", i);
10768 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10769 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 10770 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 10771 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
10772 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 10773 }
4b71a570 10774 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 10775 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 10776 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 10777 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
10778 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 10779 }
10780
edc3d884
MK		 10781 err_printf(m, "Cursor [%d]:\n", i);
10782 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
10783 err_printf(m, " POS: %08x\n", error->cursor[i].position);
10784 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 10785 }
63b66e5b
CW		 10786
10787 for (i = 0; i < error->num_transcoders; i++) {
10788 err_printf(m, " CPU transcoder: %c\n",
10789 transcoder_name(error->transcoder[i].cpu_transcoder));
10790 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
10791 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
10792 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
10793 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
10794 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
10795 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
10796 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
10797 }
c4a1d9e4 10798}
Linux kernel - Deliverables
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