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drm/i915: Perform intel_enable_fbc() from a delayed task
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
23b2f8bb 27#include <linux/cpufreq.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
79e53945
JB		 34#include "drmP.h"
35#include "intel_drv.h"
36#include "i915_drm.h"
37#include "i915_drv.h"
e5510fac 38#include "i915_trace.h"
ab2c0672 39#include "drm_dp_helper.h"
79e53945
JB		 40
41#include "drm_crtc_helper.h"
42
32f9d658
ZW		 43#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
44
79e53945 45bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
7662c8bd 46static void intel_update_watermarks(struct drm_device *dev);
3dec0095 47static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 48static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 49
50typedef struct {
51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
60} intel_clock_t;
61
62typedef struct {
63 int min, max;
64} intel_range_t;
65
66typedef struct {
67 int dot_limit;
68 int p2_slow, p2_fast;
69} intel_p2_t;
70
71#define INTEL_P2_NUM 2
d4906093
ML		 72typedef struct intel_limit intel_limit_t;
73struct intel_limit {
79e53945
JB		 74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
d4906093
ML		 76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
77 int, int, intel_clock_t *);
78};
79e53945 79
2377b741
JB		 80/* FDI */
81#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
d4906093
ML		 83static bool
84intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
85 int target, int refclk, intel_clock_t *best_clock);
86static bool
87intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
88 int target, int refclk, intel_clock_t *best_clock);
79e53945 89
a4fc5ed6
KP		 90static bool
91intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
92 int target, int refclk, intel_clock_t *best_clock);
5eb08b69 93static bool
f2b115e6
AJ		 94intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
95 int target, int refclk, intel_clock_t *best_clock);
a4fc5ed6 96
021357ac
CW		 97static inline u32 /* units of 100MHz */
98intel_fdi_link_freq(struct drm_device *dev)
99{
8b99e68c
CW		 100 if (IS_GEN5(dev)) {
101 struct drm_i915_private *dev_priv = dev->dev_private;
102 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
103 } else
104 return 27;
021357ac
CW		 105}
106
e4b36699 107static const intel_limit_t intel_limits_i8xx_dvo = {
273e27ca
EA		 108 .dot = { .min = 25000, .max = 350000 },
109 .vco = { .min = 930000, .max = 1400000 },
110 .n = { .min = 3, .max = 16 },
111 .m = { .min = 96, .max = 140 },
112 .m1 = { .min = 18, .max = 26 },
113 .m2 = { .min = 6, .max = 16 },
114 .p = { .min = 4, .max = 128 },
115 .p1 = { .min = 2, .max = 33 },
116 .p2 = { .dot_limit = 165000,
117 .p2_slow = 4, .p2_fast = 2 },
d4906093 118 .find_pll = intel_find_best_PLL,
e4b36699
KP		 119};
120
121static const intel_limit_t intel_limits_i8xx_lvds = {
273e27ca
EA		 122 .dot = { .min = 25000, .max = 350000 },
123 .vco = { .min = 930000, .max = 1400000 },
124 .n = { .min = 3, .max = 16 },
125 .m = { .min = 96, .max = 140 },
126 .m1 = { .min = 18, .max = 26 },
127 .m2 = { .min = 6, .max = 16 },
128 .p = { .min = 4, .max = 128 },
129 .p1 = { .min = 1, .max = 6 },
130 .p2 = { .dot_limit = 165000,
131 .p2_slow = 14, .p2_fast = 7 },
d4906093 132 .find_pll = intel_find_best_PLL,
e4b36699 133};
273e27ca 134
e4b36699 135static const intel_limit_t intel_limits_i9xx_sdvo = {
273e27ca
EA		 136 .dot = { .min = 20000, .max = 400000 },
137 .vco = { .min = 1400000, .max = 2800000 },
138 .n = { .min = 1, .max = 6 },
139 .m = { .min = 70, .max = 120 },
140 .m1 = { .min = 10, .max = 22 },
141 .m2 = { .min = 5, .max = 9 },
142 .p = { .min = 5, .max = 80 },
143 .p1 = { .min = 1, .max = 8 },
144 .p2 = { .dot_limit = 200000,
145 .p2_slow = 10, .p2_fast = 5 },
d4906093 146 .find_pll = intel_find_best_PLL,
e4b36699
KP		 147};
148
149static const intel_limit_t intel_limits_i9xx_lvds = {
273e27ca
EA		 150 .dot = { .min = 20000, .max = 400000 },
151 .vco = { .min = 1400000, .max = 2800000 },
152 .n = { .min = 1, .max = 6 },
153 .m = { .min = 70, .max = 120 },
154 .m1 = { .min = 10, .max = 22 },
155 .m2 = { .min = 5, .max = 9 },
156 .p = { .min = 7, .max = 98 },
157 .p1 = { .min = 1, .max = 8 },
158 .p2 = { .dot_limit = 112000,
159 .p2_slow = 14, .p2_fast = 7 },
d4906093 160 .find_pll = intel_find_best_PLL,
e4b36699
KP		 161};
162
273e27ca 163
e4b36699 164static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 165 .dot = { .min = 25000, .max = 270000 },
166 .vco = { .min = 1750000, .max = 3500000},
167 .n = { .min = 1, .max = 4 },
168 .m = { .min = 104, .max = 138 },
169 .m1 = { .min = 17, .max = 23 },
170 .m2 = { .min = 5, .max = 11 },
171 .p = { .min = 10, .max = 30 },
172 .p1 = { .min = 1, .max = 3},
173 .p2 = { .dot_limit = 270000,
174 .p2_slow = 10,
175 .p2_fast = 10
044c7c41 176 },
d4906093 177 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 178};
179
180static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 181 .dot = { .min = 22000, .max = 400000 },
182 .vco = { .min = 1750000, .max = 3500000},
183 .n = { .min = 1, .max = 4 },
184 .m = { .min = 104, .max = 138 },
185 .m1 = { .min = 16, .max = 23 },
186 .m2 = { .min = 5, .max = 11 },
187 .p = { .min = 5, .max = 80 },
188 .p1 = { .min = 1, .max = 8},
189 .p2 = { .dot_limit = 165000,
190 .p2_slow = 10, .p2_fast = 5 },
d4906093 191 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 192};
193
194static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 195 .dot = { .min = 20000, .max = 115000 },
196 .vco = { .min = 1750000, .max = 3500000 },
197 .n = { .min = 1, .max = 3 },
198 .m = { .min = 104, .max = 138 },
199 .m1 = { .min = 17, .max = 23 },
200 .m2 = { .min = 5, .max = 11 },
201 .p = { .min = 28, .max = 112 },
202 .p1 = { .min = 2, .max = 8 },
203 .p2 = { .dot_limit = 0,
204 .p2_slow = 14, .p2_fast = 14
044c7c41 205 },
d4906093 206 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 207};
208
209static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 210 .dot = { .min = 80000, .max = 224000 },
211 .vco = { .min = 1750000, .max = 3500000 },
212 .n = { .min = 1, .max = 3 },
213 .m = { .min = 104, .max = 138 },
214 .m1 = { .min = 17, .max = 23 },
215 .m2 = { .min = 5, .max = 11 },
216 .p = { .min = 14, .max = 42 },
217 .p1 = { .min = 2, .max = 6 },
218 .p2 = { .dot_limit = 0,
219 .p2_slow = 7, .p2_fast = 7
044c7c41 220 },
d4906093 221 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 222};
223
224static const intel_limit_t intel_limits_g4x_display_port = {
273e27ca
EA		 225 .dot = { .min = 161670, .max = 227000 },
226 .vco = { .min = 1750000, .max = 3500000},
227 .n = { .min = 1, .max = 2 },
228 .m = { .min = 97, .max = 108 },
229 .m1 = { .min = 0x10, .max = 0x12 },
230 .m2 = { .min = 0x05, .max = 0x06 },
231 .p = { .min = 10, .max = 20 },
232 .p1 = { .min = 1, .max = 2},
233 .p2 = { .dot_limit = 0,
234 .p2_slow = 10, .p2_fast = 10 },
a4fc5ed6 235 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 236};
237
f2b115e6 238static const intel_limit_t intel_limits_pineview_sdvo = {
273e27ca
EA		 239 .dot = { .min = 20000, .max = 400000},
240 .vco = { .min = 1700000, .max = 3500000 },
241 /* Pineview's Ncounter is a ring counter */
242 .n = { .min = 3, .max = 6 },
243 .m = { .min = 2, .max = 256 },
244 /* Pineview only has one combined m divider, which we treat as m2. */
245 .m1 = { .min = 0, .max = 0 },
246 .m2 = { .min = 0, .max = 254 },
247 .p = { .min = 5, .max = 80 },
248 .p1 = { .min = 1, .max = 8 },
249 .p2 = { .dot_limit = 200000,
250 .p2_slow = 10, .p2_fast = 5 },
6115707b 251 .find_pll = intel_find_best_PLL,
e4b36699
KP		 252};
253
f2b115e6 254static const intel_limit_t intel_limits_pineview_lvds = {
273e27ca
EA		 255 .dot = { .min = 20000, .max = 400000 },
256 .vco = { .min = 1700000, .max = 3500000 },
257 .n = { .min = 3, .max = 6 },
258 .m = { .min = 2, .max = 256 },
259 .m1 = { .min = 0, .max = 0 },
260 .m2 = { .min = 0, .max = 254 },
261 .p = { .min = 7, .max = 112 },
262 .p1 = { .min = 1, .max = 8 },
263 .p2 = { .dot_limit = 112000,
264 .p2_slow = 14, .p2_fast = 14 },
6115707b 265 .find_pll = intel_find_best_PLL,
e4b36699
KP		 266};
267
273e27ca
EA		 268/* Ironlake / Sandybridge
269 *
270 * We calculate clock using (register_value + 2) for N/M1/M2, so here
271 * the range value for them is (actual_value - 2).
272 */
b91ad0ec 273static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 274 .dot = { .min = 25000, .max = 350000 },
275 .vco = { .min = 1760000, .max = 3510000 },
276 .n = { .min = 1, .max = 5 },
277 .m = { .min = 79, .max = 127 },
278 .m1 = { .min = 12, .max = 22 },
279 .m2 = { .min = 5, .max = 9 },
280 .p = { .min = 5, .max = 80 },
281 .p1 = { .min = 1, .max = 8 },
282 .p2 = { .dot_limit = 225000,
283 .p2_slow = 10, .p2_fast = 5 },
4547668a 284 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 285};
286
b91ad0ec 287static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 288 .dot = { .min = 25000, .max = 350000 },
289 .vco = { .min = 1760000, .max = 3510000 },
290 .n = { .min = 1, .max = 3 },
291 .m = { .min = 79, .max = 118 },
292 .m1 = { .min = 12, .max = 22 },
293 .m2 = { .min = 5, .max = 9 },
294 .p = { .min = 28, .max = 112 },
295 .p1 = { .min = 2, .max = 8 },
296 .p2 = { .dot_limit = 225000,
297 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 298 .find_pll = intel_g4x_find_best_PLL,
299};
300
301static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 302 .dot = { .min = 25000, .max = 350000 },
303 .vco = { .min = 1760000, .max = 3510000 },
304 .n = { .min = 1, .max = 3 },
305 .m = { .min = 79, .max = 127 },
306 .m1 = { .min = 12, .max = 22 },
307 .m2 = { .min = 5, .max = 9 },
308 .p = { .min = 14, .max = 56 },
309 .p1 = { .min = 2, .max = 8 },
310 .p2 = { .dot_limit = 225000,
311 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 312 .find_pll = intel_g4x_find_best_PLL,
313};
314
273e27ca 315/* LVDS 100mhz refclk limits. */
b91ad0ec 316static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 2 },
320 .m = { .min = 79, .max = 126 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2,.max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 327 .find_pll = intel_g4x_find_best_PLL,
328};
329
330static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 331 .dot = { .min = 25000, .max = 350000 },
332 .vco = { .min = 1760000, .max = 3510000 },
333 .n = { .min = 1, .max = 3 },
334 .m = { .min = 79, .max = 126 },
335 .m1 = { .min = 12, .max = 22 },
336 .m2 = { .min = 5, .max = 9 },
337 .p = { .min = 14, .max = 42 },
338 .p1 = { .min = 2,.max = 6 },
339 .p2 = { .dot_limit = 225000,
340 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 341 .find_pll = intel_g4x_find_best_PLL,
342};
343
344static const intel_limit_t intel_limits_ironlake_display_port = {
273e27ca
EA		 345 .dot = { .min = 25000, .max = 350000 },
346 .vco = { .min = 1760000, .max = 3510000},
347 .n = { .min = 1, .max = 2 },
348 .m = { .min = 81, .max = 90 },
349 .m1 = { .min = 12, .max = 22 },
350 .m2 = { .min = 5, .max = 9 },
351 .p = { .min = 10, .max = 20 },
352 .p1 = { .min = 1, .max = 2},
353 .p2 = { .dot_limit = 0,
354 .p2_slow = 10, .p2_fast = 10 },
4547668a 355 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 356};
357
1b894b59
CW		 358static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
359 int refclk)
2c07245f 360{
b91ad0ec
ZW		 361 struct drm_device *dev = crtc->dev;
362 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 363 const intel_limit_t *limit;
b91ad0ec
ZW		 364
365 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b91ad0ec
ZW		 366 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
367 LVDS_CLKB_POWER_UP) {
368 /* LVDS dual channel */
1b894b59 369 if (refclk == 100000)
b91ad0ec
ZW		 370 limit = &intel_limits_ironlake_dual_lvds_100m;
371 else
372 limit = &intel_limits_ironlake_dual_lvds;
373 } else {
1b894b59 374 if (refclk == 100000)
b91ad0ec
ZW		 375 limit = &intel_limits_ironlake_single_lvds_100m;
376 else
377 limit = &intel_limits_ironlake_single_lvds;
378 }
379 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 380 HAS_eDP)
381 limit = &intel_limits_ironlake_display_port;
2c07245f 382 else
b91ad0ec 383 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 384
385 return limit;
386}
387
044c7c41
ML		 388static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
389{
390 struct drm_device *dev = crtc->dev;
391 struct drm_i915_private *dev_priv = dev->dev_private;
392 const intel_limit_t *limit;
393
394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
395 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
396 LVDS_CLKB_POWER_UP)
397 /* LVDS with dual channel */
e4b36699 398 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 399 else
400 /* LVDS with dual channel */
e4b36699 401 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 402 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
403 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 404 limit = &intel_limits_g4x_hdmi;
044c7c41 405 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 406 limit = &intel_limits_g4x_sdvo;
a4fc5ed6 407 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 408 limit = &intel_limits_g4x_display_port;
044c7c41 409 } else /* The option is for other outputs */
e4b36699 410 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 411
412 return limit;
413}
414
1b894b59 415static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 416{
417 struct drm_device *dev = crtc->dev;
418 const intel_limit_t *limit;
419
bad720ff 420 if (HAS_PCH_SPLIT(dev))
1b894b59 421 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 422 else if (IS_G4X(dev)) {
044c7c41 423 limit = intel_g4x_limit(crtc);
f2b115e6 424 } else if (IS_PINEVIEW(dev)) {
2177832f 425 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 426 limit = &intel_limits_pineview_lvds;
2177832f 427 else
f2b115e6 428 limit = &intel_limits_pineview_sdvo;
a6c45cf0
CW		 429 } else if (!IS_GEN2(dev)) {
430 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
431 limit = &intel_limits_i9xx_lvds;
432 else
433 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 434 } else {
435 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 436 limit = &intel_limits_i8xx_lvds;
79e53945 437 else
e4b36699 438 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 439 }
440 return limit;
441}
442
f2b115e6
AJ		 443/* m1 is reserved as 0 in Pineview, n is a ring counter */
444static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 445{
2177832f
SL		 446 clock->m = clock->m2 + 2;
447 clock->p = clock->p1 * clock->p2;
448 clock->vco = refclk * clock->m / clock->n;
449 clock->dot = clock->vco / clock->p;
450}
451
452static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
453{
f2b115e6
AJ		 454 if (IS_PINEVIEW(dev)) {
455 pineview_clock(refclk, clock);
2177832f
SL		 456 return;
457 }
79e53945
JB		 458 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
459 clock->p = clock->p1 * clock->p2;
460 clock->vco = refclk * clock->m / (clock->n + 2);
461 clock->dot = clock->vco / clock->p;
462}
463
79e53945
JB		 464/**
465 * Returns whether any output on the specified pipe is of the specified type
466 */
4ef69c7a 467bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 468{
4ef69c7a
CW		 469 struct drm_device *dev = crtc->dev;
470 struct drm_mode_config *mode_config = &dev->mode_config;
471 struct intel_encoder *encoder;
472
473 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
474 if (encoder->base.crtc == crtc && encoder->type == type)
475 return true;
476
477 return false;
79e53945
JB		 478}
479
7c04d1d9 480#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 481/**
482 * Returns whether the given set of divisors are valid for a given refclk with
483 * the given connectors.
484 */
485
1b894b59
CW		 486static bool intel_PLL_is_valid(struct drm_device *dev,
487 const intel_limit_t *limit,
488 const intel_clock_t *clock)
79e53945 489{
79e53945
JB		 490 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
491 INTELPllInvalid ("p1 out of range\n");
492 if (clock->p < limit->p.min || limit->p.max < clock->p)
493 INTELPllInvalid ("p out of range\n");
494 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
495 INTELPllInvalid ("m2 out of range\n");
496 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
497 INTELPllInvalid ("m1 out of range\n");
f2b115e6 498 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
79e53945
JB		 499 INTELPllInvalid ("m1 <= m2\n");
500 if (clock->m < limit->m.min || limit->m.max < clock->m)
501 INTELPllInvalid ("m out of range\n");
502 if (clock->n < limit->n.min || limit->n.max < clock->n)
503 INTELPllInvalid ("n out of range\n");
504 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
505 INTELPllInvalid ("vco out of range\n");
506 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
507 * connector, etc., rather than just a single range.
508 */
509 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
510 INTELPllInvalid ("dot out of range\n");
511
512 return true;
513}
514
d4906093
ML		 515static bool
516intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
517 int target, int refclk, intel_clock_t *best_clock)
518
79e53945
JB		 519{
520 struct drm_device *dev = crtc->dev;
521 struct drm_i915_private *dev_priv = dev->dev_private;
522 intel_clock_t clock;
79e53945
JB		 523 int err = target;
524
bc5e5718 525 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 526 (I915_READ(LVDS)) != 0) {
79e53945
JB		 527 /*
528 * For LVDS, if the panel is on, just rely on its current
529 * settings for dual-channel. We haven't figured out how to
530 * reliably set up different single/dual channel state, if we
531 * even can.
532 */
533 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
534 LVDS_CLKB_POWER_UP)
535 clock.p2 = limit->p2.p2_fast;
536 else
537 clock.p2 = limit->p2.p2_slow;
538 } else {
539 if (target < limit->p2.dot_limit)
540 clock.p2 = limit->p2.p2_slow;
541 else
542 clock.p2 = limit->p2.p2_fast;
543 }
544
545 memset (best_clock, 0, sizeof (*best_clock));
546
42158660
ZY		 547 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
548 clock.m1++) {
549 for (clock.m2 = limit->m2.min;
550 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 551 /* m1 is always 0 in Pineview */
552 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 553 break;
554 for (clock.n = limit->n.min;
555 clock.n <= limit->n.max; clock.n++) {
556 for (clock.p1 = limit->p1.min;
557 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 558 int this_err;
559
2177832f 560 intel_clock(dev, refclk, &clock);
1b894b59
CW		 561 if (!intel_PLL_is_valid(dev, limit,
562 &clock))
79e53945
JB		 563 continue;
564
565 this_err = abs(clock.dot - target);
566 if (this_err < err) {
567 *best_clock = clock;
568 err = this_err;
569 }
570 }
571 }
572 }
573 }
574
575 return (err != target);
576}
577
d4906093
ML		 578static bool
579intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
580 int target, int refclk, intel_clock_t *best_clock)
581{
582 struct drm_device *dev = crtc->dev;
583 struct drm_i915_private *dev_priv = dev->dev_private;
584 intel_clock_t clock;
585 int max_n;
586 bool found;
6ba770dc
AJ		 587 /* approximately equals target * 0.00585 */
588 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 589 found = false;
590
591 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 592 int lvds_reg;
593
c619eed4 594 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 595 lvds_reg = PCH_LVDS;
596 else
597 lvds_reg = LVDS;
598 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 599 LVDS_CLKB_POWER_UP)
600 clock.p2 = limit->p2.p2_fast;
601 else
602 clock.p2 = limit->p2.p2_slow;
603 } else {
604 if (target < limit->p2.dot_limit)
605 clock.p2 = limit->p2.p2_slow;
606 else
607 clock.p2 = limit->p2.p2_fast;
608 }
609
610 memset(best_clock, 0, sizeof(*best_clock));
611 max_n = limit->n.max;
f77f13e2 612 /* based on hardware requirement, prefer smaller n to precision */
d4906093 613 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 614 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 615 for (clock.m1 = limit->m1.max;
616 clock.m1 >= limit->m1.min; clock.m1--) {
617 for (clock.m2 = limit->m2.max;
618 clock.m2 >= limit->m2.min; clock.m2--) {
619 for (clock.p1 = limit->p1.max;
620 clock.p1 >= limit->p1.min; clock.p1--) {
621 int this_err;
622
2177832f 623 intel_clock(dev, refclk, &clock);
1b894b59
CW		 624 if (!intel_PLL_is_valid(dev, limit,
625 &clock))
d4906093 626 continue;
1b894b59
CW		 627
628 this_err = abs(clock.dot - target);
d4906093
ML		 629 if (this_err < err_most) {
630 *best_clock = clock;
631 err_most = this_err;
632 max_n = clock.n;
633 found = true;
634 }
635 }
636 }
637 }
638 }
2c07245f
ZW		 639 return found;
640}
641
5eb08b69 642static bool
f2b115e6
AJ		 643intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
644 int target, int refclk, intel_clock_t *best_clock)
5eb08b69
ZW		 645{
646 struct drm_device *dev = crtc->dev;
647 intel_clock_t clock;
4547668a 648
5eb08b69
ZW		 649 if (target < 200000) {
650 clock.n = 1;
651 clock.p1 = 2;
652 clock.p2 = 10;
653 clock.m1 = 12;
654 clock.m2 = 9;
655 } else {
656 clock.n = 2;
657 clock.p1 = 1;
658 clock.p2 = 10;
659 clock.m1 = 14;
660 clock.m2 = 8;
661 }
662 intel_clock(dev, refclk, &clock);
663 memcpy(best_clock, &clock, sizeof(intel_clock_t));
664 return true;
665}
666
a4fc5ed6
KP		 667/* DisplayPort has only two frequencies, 162MHz and 270MHz */
668static bool
669intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
670 int target, int refclk, intel_clock_t *best_clock)
671{
5eddb70b
CW		 672 intel_clock_t clock;
673 if (target < 200000) {
674 clock.p1 = 2;
675 clock.p2 = 10;
676 clock.n = 2;
677 clock.m1 = 23;
678 clock.m2 = 8;
679 } else {
680 clock.p1 = 1;
681 clock.p2 = 10;
682 clock.n = 1;
683 clock.m1 = 14;
684 clock.m2 = 2;
685 }
686 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
687 clock.p = (clock.p1 * clock.p2);
688 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
689 clock.vco = 0;
690 memcpy(best_clock, &clock, sizeof(intel_clock_t));
691 return true;
a4fc5ed6
KP		 692}
693
9d0498a2
JB		 694/**
695 * intel_wait_for_vblank - wait for vblank on a given pipe
696 * @dev: drm device
697 * @pipe: pipe to wait for
698 *
699 * Wait for vblank to occur on a given pipe. Needed for various bits of
700 * mode setting code.
701 */
702void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 703{
9d0498a2 704 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 705 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 706
300387c0
CW		 707 /* Clear existing vblank status. Note this will clear any other
708 * sticky status fields as well.
709 *
710 * This races with i915_driver_irq_handler() with the result
711 * that either function could miss a vblank event. Here it is not
712 * fatal, as we will either wait upon the next vblank interrupt or
713 * timeout. Generally speaking intel_wait_for_vblank() is only
714 * called during modeset at which time the GPU should be idle and
715 * should *not* be performing page flips and thus not waiting on
716 * vblanks...
717 * Currently, the result of us stealing a vblank from the irq
718 * handler is that a single frame will be skipped during swapbuffers.
719 */
720 I915_WRITE(pipestat_reg,
721 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
722
9d0498a2 723 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 724 if (wait_for(I915_READ(pipestat_reg) &
725 PIPE_VBLANK_INTERRUPT_STATUS,
726 50))
9d0498a2
JB		 727 DRM_DEBUG_KMS("vblank wait timed out\n");
728}
729
ab7ad7f6
KP		 730/*
731 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 732 * @dev: drm device
733 * @pipe: pipe to wait for
734 *
735 * After disabling a pipe, we can't wait for vblank in the usual way,
736 * spinning on the vblank interrupt status bit, since we won't actually
737 * see an interrupt when the pipe is disabled.
738 *
ab7ad7f6
KP		 739 * On Gen4 and above:
740 * wait for the pipe register state bit to turn off
741 *
742 * Otherwise:
743 * wait for the display line value to settle (it usually
744 * ends up stopping at the start of the next frame).
58e10eb9 745 *
9d0498a2 746 */
58e10eb9 747void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 748{
749 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP		 750
751 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 752 int reg = PIPECONF(pipe);
ab7ad7f6
KP		 753
754 /* Wait for the Pipe State to go off */
58e10eb9
CW		 755 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
756 100))
ab7ad7f6
KP		 757 DRM_DEBUG_KMS("pipe_off wait timed out\n");
758 } else {
759 u32 last_line;
58e10eb9 760 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 761 unsigned long timeout = jiffies + msecs_to_jiffies(100);
762
763 /* Wait for the display line to settle */
764 do {
58e10eb9 765 last_line = I915_READ(reg) & DSL_LINEMASK;
ab7ad7f6 766 mdelay(5);
58e10eb9 767 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
ab7ad7f6
KP		 768 time_after(timeout, jiffies));
769 if (time_after(jiffies, timeout))
770 DRM_DEBUG_KMS("pipe_off wait timed out\n");
771 }
79e53945
JB		 772}
773
b24e7179
JB		 774static const char *state_string(bool enabled)
775{
776 return enabled ? "on" : "off";
777}
778
779/* Only for pre-ILK configs */
780static void assert_pll(struct drm_i915_private *dev_priv,
781 enum pipe pipe, bool state)
782{
783 int reg;
784 u32 val;
785 bool cur_state;
786
787 reg = DPLL(pipe);
788 val = I915_READ(reg);
789 cur_state = !!(val & DPLL_VCO_ENABLE);
790 WARN(cur_state != state,
791 "PLL state assertion failure (expected %s, current %s)\n",
792 state_string(state), state_string(cur_state));
793}
794#define assert_pll_enabled(d, p) assert_pll(d, p, true)
795#define assert_pll_disabled(d, p) assert_pll(d, p, false)
796
040484af
JB		 797/* For ILK+ */
798static void assert_pch_pll(struct drm_i915_private *dev_priv,
799 enum pipe pipe, bool state)
800{
801 int reg;
802 u32 val;
803 bool cur_state;
804
805 reg = PCH_DPLL(pipe);
806 val = I915_READ(reg);
807 cur_state = !!(val & DPLL_VCO_ENABLE);
808 WARN(cur_state != state,
809 "PCH PLL state assertion failure (expected %s, current %s)\n",
810 state_string(state), state_string(cur_state));
811}
812#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
813#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
814
815static void assert_fdi_tx(struct drm_i915_private *dev_priv,
816 enum pipe pipe, bool state)
817{
818 int reg;
819 u32 val;
820 bool cur_state;
821
822 reg = FDI_TX_CTL(pipe);
823 val = I915_READ(reg);
824 cur_state = !!(val & FDI_TX_ENABLE);
825 WARN(cur_state != state,
826 "FDI TX state assertion failure (expected %s, current %s)\n",
827 state_string(state), state_string(cur_state));
828}
829#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
830#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
831
832static void assert_fdi_rx(struct drm_i915_private *dev_priv,
833 enum pipe pipe, bool state)
834{
835 int reg;
836 u32 val;
837 bool cur_state;
838
839 reg = FDI_RX_CTL(pipe);
840 val = I915_READ(reg);
841 cur_state = !!(val & FDI_RX_ENABLE);
842 WARN(cur_state != state,
843 "FDI RX state assertion failure (expected %s, current %s)\n",
844 state_string(state), state_string(cur_state));
845}
846#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
847#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
848
849static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
850 enum pipe pipe)
851{
852 int reg;
853 u32 val;
854
855 /* ILK FDI PLL is always enabled */
856 if (dev_priv->info->gen == 5)
857 return;
858
859 reg = FDI_TX_CTL(pipe);
860 val = I915_READ(reg);
861 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
862}
863
864static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
865 enum pipe pipe)
866{
867 int reg;
868 u32 val;
869
870 reg = FDI_RX_CTL(pipe);
871 val = I915_READ(reg);
872 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
873}
874
ea0760cf
JB		 875static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
876 enum pipe pipe)
877{
878 int pp_reg, lvds_reg;
879 u32 val;
880 enum pipe panel_pipe = PIPE_A;
881 bool locked = locked;
882
883 if (HAS_PCH_SPLIT(dev_priv->dev)) {
884 pp_reg = PCH_PP_CONTROL;
885 lvds_reg = PCH_LVDS;
886 } else {
887 pp_reg = PP_CONTROL;
888 lvds_reg = LVDS;
889 }
890
891 val = I915_READ(pp_reg);
892 if (!(val & PANEL_POWER_ON) ||
893 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
894 locked = false;
895
896 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
897 panel_pipe = PIPE_B;
898
899 WARN(panel_pipe == pipe && locked,
900 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 901 pipe_name(pipe));
ea0760cf
JB		 902}
903
63d7bbe9
JB		 904static void assert_pipe(struct drm_i915_private *dev_priv,
905 enum pipe pipe, bool state)
b24e7179
JB		 906{
907 int reg;
908 u32 val;
63d7bbe9 909 bool cur_state;
b24e7179
JB		 910
911 reg = PIPECONF(pipe);
912 val = I915_READ(reg);
63d7bbe9
JB		 913 cur_state = !!(val & PIPECONF_ENABLE);
914 WARN(cur_state != state,
915 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 916 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179 917}
63d7bbe9
JB		 918#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
919#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
b24e7179
JB		 920
921static void assert_plane_enabled(struct drm_i915_private *dev_priv,
922 enum plane plane)
923{
924 int reg;
925 u32 val;
926
927 reg = DSPCNTR(plane);
928 val = I915_READ(reg);
929 WARN(!(val & DISPLAY_PLANE_ENABLE),
930 "plane %c assertion failure, should be active but is disabled\n",
9db4a9c7 931 plane_name(plane));
b24e7179
JB		 932}
933
934static void assert_planes_disabled(struct drm_i915_private *dev_priv,
935 enum pipe pipe)
936{
937 int reg, i;
938 u32 val;
939 int cur_pipe;
940
19ec1358
JB		 941 /* Planes are fixed to pipes on ILK+ */
942 if (HAS_PCH_SPLIT(dev_priv->dev))
943 return;
944
b24e7179
JB		 945 /* Need to check both planes against the pipe */
946 for (i = 0; i < 2; i++) {
947 reg = DSPCNTR(i);
948 val = I915_READ(reg);
949 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
950 DISPPLANE_SEL_PIPE_SHIFT;
951 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 952 "plane %c assertion failure, should be off on pipe %c but is still active\n",
953 plane_name(i), pipe_name(pipe));
b24e7179
JB		 954 }
955}
956
92f2584a
JB		 957static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
958{
959 u32 val;
960 bool enabled;
961
962 val = I915_READ(PCH_DREF_CONTROL);
963 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
964 DREF_SUPERSPREAD_SOURCE_MASK));
965 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
966}
967
968static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
969 enum pipe pipe)
970{
971 int reg;
972 u32 val;
973 bool enabled;
974
975 reg = TRANSCONF(pipe);
976 val = I915_READ(reg);
977 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 978 WARN(enabled,
979 "transcoder assertion failed, should be off on pipe %c but is still active\n",
980 pipe_name(pipe));
92f2584a
JB		 981}
982
291906f1
JB		 983static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
984 enum pipe pipe, int reg)
985{
47a05eca
JB		 986 u32 val = I915_READ(reg);
987 WARN(DP_PIPE_ENABLED(val, pipe),
291906f1 988 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 989 reg, pipe_name(pipe));
291906f1
JB		 990}
991
992static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
993 enum pipe pipe, int reg)
994{
47a05eca
JB		 995 u32 val = I915_READ(reg);
996 WARN(HDMI_PIPE_ENABLED(val, pipe),
291906f1 997 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 998 reg, pipe_name(pipe));
291906f1
JB		 999}
1000
1001static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1002 enum pipe pipe)
1003{
1004 int reg;
1005 u32 val;
291906f1
JB		 1006
1007 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B);
1008 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C);
1009 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D);
1010
1011 reg = PCH_ADPA;
1012 val = I915_READ(reg);
47a05eca 1013 WARN(ADPA_PIPE_ENABLED(val, pipe),
291906f1 1014 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1015 pipe_name(pipe));
291906f1
JB		 1016
1017 reg = PCH_LVDS;
1018 val = I915_READ(reg);
47a05eca 1019 WARN(LVDS_PIPE_ENABLED(val, pipe),
291906f1 1020 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1021 pipe_name(pipe));
291906f1
JB		 1022
1023 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1024 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1025 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1026}
1027
63d7bbe9
JB		 1028/**
1029 * intel_enable_pll - enable a PLL
1030 * @dev_priv: i915 private structure
1031 * @pipe: pipe PLL to enable
1032 *
1033 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1034 * make sure the PLL reg is writable first though, since the panel write
1035 * protect mechanism may be enabled.
1036 *
1037 * Note! This is for pre-ILK only.
1038 */
1039static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1040{
1041 int reg;
1042 u32 val;
1043
1044 /* No really, not for ILK+ */
1045 BUG_ON(dev_priv->info->gen >= 5);
1046
1047 /* PLL is protected by panel, make sure we can write it */
1048 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1049 assert_panel_unlocked(dev_priv, pipe);
1050
1051 reg = DPLL(pipe);
1052 val = I915_READ(reg);
1053 val |= DPLL_VCO_ENABLE;
1054
1055 /* We do this three times for luck */
1056 I915_WRITE(reg, val);
1057 POSTING_READ(reg);
1058 udelay(150); /* wait for warmup */
1059 I915_WRITE(reg, val);
1060 POSTING_READ(reg);
1061 udelay(150); /* wait for warmup */
1062 I915_WRITE(reg, val);
1063 POSTING_READ(reg);
1064 udelay(150); /* wait for warmup */
1065}
1066
1067/**
1068 * intel_disable_pll - disable a PLL
1069 * @dev_priv: i915 private structure
1070 * @pipe: pipe PLL to disable
1071 *
1072 * Disable the PLL for @pipe, making sure the pipe is off first.
1073 *
1074 * Note! This is for pre-ILK only.
1075 */
1076static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1077{
1078 int reg;
1079 u32 val;
1080
1081 /* Don't disable pipe A or pipe A PLLs if needed */
1082 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1083 return;
1084
1085 /* Make sure the pipe isn't still relying on us */
1086 assert_pipe_disabled(dev_priv, pipe);
1087
1088 reg = DPLL(pipe);
1089 val = I915_READ(reg);
1090 val &= ~DPLL_VCO_ENABLE;
1091 I915_WRITE(reg, val);
1092 POSTING_READ(reg);
1093}
1094
92f2584a
JB		 1095/**
1096 * intel_enable_pch_pll - enable PCH PLL
1097 * @dev_priv: i915 private structure
1098 * @pipe: pipe PLL to enable
1099 *
1100 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1101 * drives the transcoder clock.
1102 */
1103static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1104 enum pipe pipe)
1105{
1106 int reg;
1107 u32 val;
1108
1109 /* PCH only available on ILK+ */
1110 BUG_ON(dev_priv->info->gen < 5);
1111
1112 /* PCH refclock must be enabled first */
1113 assert_pch_refclk_enabled(dev_priv);
1114
1115 reg = PCH_DPLL(pipe);
1116 val = I915_READ(reg);
1117 val |= DPLL_VCO_ENABLE;
1118 I915_WRITE(reg, val);
1119 POSTING_READ(reg);
1120 udelay(200);
1121}
1122
1123static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1124 enum pipe pipe)
1125{
1126 int reg;
1127 u32 val;
1128
1129 /* PCH only available on ILK+ */
1130 BUG_ON(dev_priv->info->gen < 5);
1131
1132 /* Make sure transcoder isn't still depending on us */
1133 assert_transcoder_disabled(dev_priv, pipe);
1134
1135 reg = PCH_DPLL(pipe);
1136 val = I915_READ(reg);
1137 val &= ~DPLL_VCO_ENABLE;
1138 I915_WRITE(reg, val);
1139 POSTING_READ(reg);
1140 udelay(200);
1141}
1142
040484af
JB		 1143static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1144 enum pipe pipe)
1145{
1146 int reg;
1147 u32 val;
1148
1149 /* PCH only available on ILK+ */
1150 BUG_ON(dev_priv->info->gen < 5);
1151
1152 /* Make sure PCH DPLL is enabled */
1153 assert_pch_pll_enabled(dev_priv, pipe);
1154
1155 /* FDI must be feeding us bits for PCH ports */
1156 assert_fdi_tx_enabled(dev_priv, pipe);
1157 assert_fdi_rx_enabled(dev_priv, pipe);
1158
1159 reg = TRANSCONF(pipe);
1160 val = I915_READ(reg);
e9bcff5c
JB		 1161
1162 if (HAS_PCH_IBX(dev_priv->dev)) {
1163 /*
1164 * make the BPC in transcoder be consistent with
1165 * that in pipeconf reg.
1166 */
1167 val &= ~PIPE_BPC_MASK;
1168 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1169 }
040484af
JB		 1170 I915_WRITE(reg, val | TRANS_ENABLE);
1171 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1172 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1173}
1174
1175static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1176 enum pipe pipe)
1177{
1178 int reg;
1179 u32 val;
1180
1181 /* FDI relies on the transcoder */
1182 assert_fdi_tx_disabled(dev_priv, pipe);
1183 assert_fdi_rx_disabled(dev_priv, pipe);
1184
291906f1
JB		 1185 /* Ports must be off as well */
1186 assert_pch_ports_disabled(dev_priv, pipe);
1187
040484af
JB		 1188 reg = TRANSCONF(pipe);
1189 val = I915_READ(reg);
1190 val &= ~TRANS_ENABLE;
1191 I915_WRITE(reg, val);
1192 /* wait for PCH transcoder off, transcoder state */
1193 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1194 DRM_ERROR("failed to disable transcoder\n");
1195}
1196
b24e7179 1197/**
309cfea8 1198 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1199 * @dev_priv: i915 private structure
1200 * @pipe: pipe to enable
040484af 1201 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1202 *
1203 * Enable @pipe, making sure that various hardware specific requirements
1204 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1205 *
1206 * @pipe should be %PIPE_A or %PIPE_B.
1207 *
1208 * Will wait until the pipe is actually running (i.e. first vblank) before
1209 * returning.
1210 */
040484af
JB		 1211static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1212 bool pch_port)
b24e7179
JB		 1213{
1214 int reg;
1215 u32 val;
1216
1217 /*
1218 * A pipe without a PLL won't actually be able to drive bits from
1219 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1220 * need the check.
1221 */
1222 if (!HAS_PCH_SPLIT(dev_priv->dev))
1223 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1224 else {
1225 if (pch_port) {
1226 /* if driving the PCH, we need FDI enabled */
1227 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1228 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1229 }
1230 /* FIXME: assert CPU port conditions for SNB+ */
1231 }
b24e7179
JB		 1232
1233 reg = PIPECONF(pipe);
1234 val = I915_READ(reg);
00d70b15
CW		 1235 if (val & PIPECONF_ENABLE)
1236 return;
1237
1238 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1239 intel_wait_for_vblank(dev_priv->dev, pipe);
1240}
1241
1242/**
309cfea8 1243 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1244 * @dev_priv: i915 private structure
1245 * @pipe: pipe to disable
1246 *
1247 * Disable @pipe, making sure that various hardware specific requirements
1248 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1249 *
1250 * @pipe should be %PIPE_A or %PIPE_B.
1251 *
1252 * Will wait until the pipe has shut down before returning.
1253 */
1254static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1255 enum pipe pipe)
1256{
1257 int reg;
1258 u32 val;
1259
1260 /*
1261 * Make sure planes won't keep trying to pump pixels to us,
1262 * or we might hang the display.
1263 */
1264 assert_planes_disabled(dev_priv, pipe);
1265
1266 /* Don't disable pipe A or pipe A PLLs if needed */
1267 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1268 return;
1269
1270 reg = PIPECONF(pipe);
1271 val = I915_READ(reg);
00d70b15
CW		 1272 if ((val & PIPECONF_ENABLE) == 0)
1273 return;
1274
1275 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1276 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1277}
1278
1279/**
1280 * intel_enable_plane - enable a display plane on a given pipe
1281 * @dev_priv: i915 private structure
1282 * @plane: plane to enable
1283 * @pipe: pipe being fed
1284 *
1285 * Enable @plane on @pipe, making sure that @pipe is running first.
1286 */
1287static void intel_enable_plane(struct drm_i915_private *dev_priv,
1288 enum plane plane, enum pipe pipe)
1289{
1290 int reg;
1291 u32 val;
1292
1293 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1294 assert_pipe_enabled(dev_priv, pipe);
1295
1296 reg = DSPCNTR(plane);
1297 val = I915_READ(reg);
00d70b15
CW		 1298 if (val & DISPLAY_PLANE_ENABLE)
1299 return;
1300
1301 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1302 intel_wait_for_vblank(dev_priv->dev, pipe);
1303}
1304
1305/*
1306 * Plane regs are double buffered, going from enabled->disabled needs a
1307 * trigger in order to latch. The display address reg provides this.
1308 */
1309static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1310 enum plane plane)
1311{
1312 u32 reg = DSPADDR(plane);
1313 I915_WRITE(reg, I915_READ(reg));
1314}
1315
1316/**
1317 * intel_disable_plane - disable a display plane
1318 * @dev_priv: i915 private structure
1319 * @plane: plane to disable
1320 * @pipe: pipe consuming the data
1321 *
1322 * Disable @plane; should be an independent operation.
1323 */
1324static void intel_disable_plane(struct drm_i915_private *dev_priv,
1325 enum plane plane, enum pipe pipe)
1326{
1327 int reg;
1328 u32 val;
1329
1330 reg = DSPCNTR(plane);
1331 val = I915_READ(reg);
00d70b15
CW		 1332 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1333 return;
1334
1335 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1336 intel_flush_display_plane(dev_priv, plane);
1337 intel_wait_for_vblank(dev_priv->dev, pipe);
1338}
1339
47a05eca
JB		 1340static void disable_pch_dp(struct drm_i915_private *dev_priv,
1341 enum pipe pipe, int reg)
1342{
1343 u32 val = I915_READ(reg);
1344 if (DP_PIPE_ENABLED(val, pipe))
1345 I915_WRITE(reg, val & ~DP_PORT_EN);
1346}
1347
1348static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1349 enum pipe pipe, int reg)
1350{
1351 u32 val = I915_READ(reg);
1352 if (HDMI_PIPE_ENABLED(val, pipe))
1353 I915_WRITE(reg, val & ~PORT_ENABLE);
1354}
1355
1356/* Disable any ports connected to this transcoder */
1357static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1358 enum pipe pipe)
1359{
1360 u32 reg, val;
1361
1362 val = I915_READ(PCH_PP_CONTROL);
1363 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1364
1365 disable_pch_dp(dev_priv, pipe, PCH_DP_B);
1366 disable_pch_dp(dev_priv, pipe, PCH_DP_C);
1367 disable_pch_dp(dev_priv, pipe, PCH_DP_D);
1368
1369 reg = PCH_ADPA;
1370 val = I915_READ(reg);
1371 if (ADPA_PIPE_ENABLED(val, pipe))
1372 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1373
1374 reg = PCH_LVDS;
1375 val = I915_READ(reg);
1376 if (LVDS_PIPE_ENABLED(val, pipe)) {
1377 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1378 POSTING_READ(reg);
1379 udelay(100);
1380 }
1381
1382 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1383 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1384 disable_pch_hdmi(dev_priv, pipe, HDMID);
1385}
1386
43a9539f
CW		 1387static void i8xx_disable_fbc(struct drm_device *dev)
1388{
1389 struct drm_i915_private *dev_priv = dev->dev_private;
1390 u32 fbc_ctl;
1391
1392 /* Disable compression */
1393 fbc_ctl = I915_READ(FBC_CONTROL);
1394 if ((fbc_ctl & FBC_CTL_EN) == 0)
1395 return;
1396
1397 fbc_ctl &= ~FBC_CTL_EN;
1398 I915_WRITE(FBC_CONTROL, fbc_ctl);
1399
1400 /* Wait for compressing bit to clear */
1401 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1402 DRM_DEBUG_KMS("FBC idle timed out\n");
1403 return;
1404 }
1405
1406 DRM_DEBUG_KMS("disabled FBC\n");
1407}
1408
80824003
JB		 1409static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1410{
1411 struct drm_device *dev = crtc->dev;
1412 struct drm_i915_private *dev_priv = dev->dev_private;
1413 struct drm_framebuffer *fb = crtc->fb;
1414 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1415 struct drm_i915_gem_object *obj = intel_fb->obj;
80824003
JB		 1416 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1417 int plane, i;
1418 u32 fbc_ctl, fbc_ctl2;
1419
bed4a673 1420 if (fb->pitch == dev_priv->cfb_pitch &&
05394f39 1421 obj->fence_reg == dev_priv->cfb_fence &&
bed4a673
CW		 1422 intel_crtc->plane == dev_priv->cfb_plane &&
1423 I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1424 return;
1425
1426 i8xx_disable_fbc(dev);
1427
80824003
JB		 1428 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1429
1430 if (fb->pitch < dev_priv->cfb_pitch)
1431 dev_priv->cfb_pitch = fb->pitch;
1432
1433 /* FBC_CTL wants 64B units */
1434 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
05394f39 1435 dev_priv->cfb_fence = obj->fence_reg;
80824003
JB		 1436 dev_priv->cfb_plane = intel_crtc->plane;
1437 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1438
1439 /* Clear old tags */
1440 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1441 I915_WRITE(FBC_TAG + (i * 4), 0);
1442
1443 /* Set it up... */
de568510
CW		 1444 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1445 fbc_ctl2 |= plane;
80824003
JB		 1446 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1447 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1448
1449 /* enable it... */
1450 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
ee25df2b 1451 if (IS_I945GM(dev))
49677901 1452 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
80824003
JB		 1453 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1454 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
de568510 1455 fbc_ctl |= dev_priv->cfb_fence;
80824003
JB		 1456 I915_WRITE(FBC_CONTROL, fbc_ctl);
1457
28c97730 1458 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
5eddb70b 1459 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
80824003
JB		 1460}
1461
ee5382ae 1462static bool i8xx_fbc_enabled(struct drm_device *dev)
80824003 1463{
80824003
JB		 1464 struct drm_i915_private *dev_priv = dev->dev_private;
1465
1466 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1467}
1468
74dff282
JB		 1469static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1470{
1471 struct drm_device *dev = crtc->dev;
1472 struct drm_i915_private *dev_priv = dev->dev_private;
1473 struct drm_framebuffer *fb = crtc->fb;
1474 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1475 struct drm_i915_gem_object *obj = intel_fb->obj;
74dff282 1476 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1477 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
74dff282
JB		 1478 unsigned long stall_watermark = 200;
1479 u32 dpfc_ctl;
1480
bed4a673
CW		 1481 dpfc_ctl = I915_READ(DPFC_CONTROL);
1482 if (dpfc_ctl & DPFC_CTL_EN) {
f19a079a 1483 if (dev_priv->cfb_fence == obj->fence_reg &&
bed4a673
CW		 1484 dev_priv->cfb_plane == intel_crtc->plane &&
1485 dev_priv->cfb_y == crtc->y)
1486 return;
1487
1488 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
bed4a673
CW		 1489 intel_wait_for_vblank(dev, intel_crtc->pipe);
1490 }
1491
05394f39 1492 dev_priv->cfb_fence = obj->fence_reg;
74dff282 1493 dev_priv->cfb_plane = intel_crtc->plane;
bed4a673 1494 dev_priv->cfb_y = crtc->y;
74dff282
JB		 1495
1496 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
de568510
CW		 1497 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1498 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
74dff282 1499
74dff282
JB		 1500 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1501 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1502 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1503 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1504
1505 /* enable it... */
1506 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1507
28c97730 1508 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
74dff282
JB		 1509}
1510
43a9539f 1511static void g4x_disable_fbc(struct drm_device *dev)
74dff282
JB		 1512{
1513 struct drm_i915_private *dev_priv = dev->dev_private;
1514 u32 dpfc_ctl;
1515
1516 /* Disable compression */
1517 dpfc_ctl = I915_READ(DPFC_CONTROL);
bed4a673
CW		 1518 if (dpfc_ctl & DPFC_CTL_EN) {
1519 dpfc_ctl &= ~DPFC_CTL_EN;
1520 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
74dff282 1521
bed4a673
CW		 1522 DRM_DEBUG_KMS("disabled FBC\n");
1523 }
74dff282
JB		 1524}
1525
ee5382ae 1526static bool g4x_fbc_enabled(struct drm_device *dev)
74dff282 1527{
74dff282
JB		 1528 struct drm_i915_private *dev_priv = dev->dev_private;
1529
1530 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1531}
1532
4efe0708
JB		 1533static void sandybridge_blit_fbc_update(struct drm_device *dev)
1534{
1535 struct drm_i915_private *dev_priv = dev->dev_private;
1536 u32 blt_ecoskpd;
1537
1538 /* Make sure blitter notifies FBC of writes */
fcca7926 1539 gen6_gt_force_wake_get(dev_priv);
4efe0708
JB		 1540 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1541 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1542 GEN6_BLITTER_LOCK_SHIFT;
1543 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1544 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1545 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1546 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1547 GEN6_BLITTER_LOCK_SHIFT);
1548 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1549 POSTING_READ(GEN6_BLITTER_ECOSKPD);
fcca7926 1550 gen6_gt_force_wake_put(dev_priv);
4efe0708
JB		 1551}
1552
b52eb4dc
ZY		 1553static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1554{
1555 struct drm_device *dev = crtc->dev;
1556 struct drm_i915_private *dev_priv = dev->dev_private;
1557 struct drm_framebuffer *fb = crtc->fb;
1558 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1559 struct drm_i915_gem_object *obj = intel_fb->obj;
b52eb4dc 1560 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1561 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
b52eb4dc
ZY		 1562 unsigned long stall_watermark = 200;
1563 u32 dpfc_ctl;
1564
bed4a673
CW		 1565 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1566 if (dpfc_ctl & DPFC_CTL_EN) {
f19a079a 1567 if (dev_priv->cfb_fence == obj->fence_reg &&
bed4a673 1568 dev_priv->cfb_plane == intel_crtc->plane &&
05394f39 1569 dev_priv->cfb_offset == obj->gtt_offset &&
bed4a673
CW		 1570 dev_priv->cfb_y == crtc->y)
1571 return;
1572
1573 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
bed4a673
CW		 1574 intel_wait_for_vblank(dev, intel_crtc->pipe);
1575 }
1576
05394f39 1577 dev_priv->cfb_fence = obj->fence_reg;
b52eb4dc 1578 dev_priv->cfb_plane = intel_crtc->plane;
05394f39 1579 dev_priv->cfb_offset = obj->gtt_offset;
bed4a673 1580 dev_priv->cfb_y = crtc->y;
b52eb4dc 1581
b52eb4dc
ZY		 1582 dpfc_ctl &= DPFC_RESERVED;
1583 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
9ce9d069
CW		 1584 /* Set persistent mode for front-buffer rendering, ala X. */
1585 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
de568510
CW		 1586 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1587 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
b52eb4dc 1588
b52eb4dc
ZY		 1589 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1590 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1591 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1592 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
05394f39 1593 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
b52eb4dc 1594 /* enable it... */
bed4a673 1595 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
b52eb4dc 1596
9c04f015
YL		 1597 if (IS_GEN6(dev)) {
1598 I915_WRITE(SNB_DPFC_CTL_SA,
1599 SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence);
1600 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
4efe0708 1601 sandybridge_blit_fbc_update(dev);
9c04f015
YL		 1602 }
1603
b52eb4dc
ZY		 1604 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1605}
1606
43a9539f 1607static void ironlake_disable_fbc(struct drm_device *dev)
b52eb4dc
ZY		 1608{
1609 struct drm_i915_private *dev_priv = dev->dev_private;
1610 u32 dpfc_ctl;
1611
1612 /* Disable compression */
1613 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
bed4a673
CW		 1614 if (dpfc_ctl & DPFC_CTL_EN) {
1615 dpfc_ctl &= ~DPFC_CTL_EN;
1616 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
b52eb4dc 1617
bed4a673
CW		 1618 DRM_DEBUG_KMS("disabled FBC\n");
1619 }
b52eb4dc
ZY		 1620}
1621
1622static bool ironlake_fbc_enabled(struct drm_device *dev)
1623{
1624 struct drm_i915_private *dev_priv = dev->dev_private;
1625
1626 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1627}
1628
ee5382ae
AJ		 1629bool intel_fbc_enabled(struct drm_device *dev)
1630{
1631 struct drm_i915_private *dev_priv = dev->dev_private;
1632
1633 if (!dev_priv->display.fbc_enabled)
1634 return false;
1635
1636 return dev_priv->display.fbc_enabled(dev);
1637}
1638
1630fe75
CW		 1639static void intel_fbc_work_fn(struct work_struct *__work)
1640{
1641 struct intel_fbc_work *work =
1642 container_of(to_delayed_work(__work),
1643 struct intel_fbc_work, work);
1644 struct drm_device *dev = work->crtc->dev;
1645 struct drm_i915_private *dev_priv = dev->dev_private;
1646
1647 mutex_lock(&dev->struct_mutex);
1648 if (work == dev_priv->fbc_work) {
1649 /* Double check that we haven't switched fb without cancelling
1650 * the prior work.
1651 */
1652 if (work->crtc->fb == work->fb)
1653 dev_priv->display.enable_fbc(work->crtc,
1654 work->interval);
1655
1656 dev_priv->fbc_work = NULL;
1657 }
1658 mutex_unlock(&dev->struct_mutex);
1659
1660 kfree(work);
1661}
1662
1663static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1664{
1665 if (dev_priv->fbc_work == NULL)
1666 return;
1667
1668 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1669
1670 /* Synchronisation is provided by struct_mutex and checking of
1671 * dev_priv->fbc_work, so we can perform the cancellation
1672 * entirely asynchronously.
1673 */
1674 if (cancel_delayed_work(&dev_priv->fbc_work->work))
1675 /* tasklet was killed before being run, clean up */
1676 kfree(dev_priv->fbc_work);
1677
1678 /* Mark the work as no longer wanted so that if it does
1679 * wake-up (because the work was already running and waiting
1680 * for our mutex), it will discover that is no longer
1681 * necessary to run.
1682 */
1683 dev_priv->fbc_work = NULL;
1684}
1685
43a9539f 1686static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
ee5382ae 1687{
1630fe75
CW		 1688 struct intel_fbc_work *work;
1689 struct drm_device *dev = crtc->dev;
1690 struct drm_i915_private *dev_priv = dev->dev_private;
ee5382ae
AJ		 1691
1692 if (!dev_priv->display.enable_fbc)
1693 return;
1694
1630fe75
CW		 1695 intel_cancel_fbc_work(dev_priv);
1696
1697 work = kzalloc(sizeof *work, GFP_KERNEL);
1698 if (work == NULL) {
1699 dev_priv->display.enable_fbc(crtc, interval);
1700 return;
1701 }
1702
1703 work->crtc = crtc;
1704 work->fb = crtc->fb;
1705 work->interval = interval;
1706 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1707
1708 dev_priv->fbc_work = work;
1709
1710 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1711
1712 /* Delay the actual enabling to let pageflipping cease and the
1713 * display to settle before starting the compression.
1714 *
1715 * A more complicated solution would involve tracking vblanks
1716 * following the termination of the page-flipping sequence
1717 * and indeed performing the enable as a co-routine and not
1718 * waiting synchronously upon the vblank.
1719 */
1720 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
ee5382ae
AJ		 1721}
1722
1723void intel_disable_fbc(struct drm_device *dev)
1724{
1725 struct drm_i915_private *dev_priv = dev->dev_private;
1726
1630fe75
CW		 1727 intel_cancel_fbc_work(dev_priv);
1728
ee5382ae
AJ		 1729 if (!dev_priv->display.disable_fbc)
1730 return;
1731
1732 dev_priv->display.disable_fbc(dev);
1733}
1734
80824003
JB		 1735/**
1736 * intel_update_fbc - enable/disable FBC as needed
bed4a673 1737 * @dev: the drm_device
80824003
JB		 1738 *
1739 * Set up the framebuffer compression hardware at mode set time. We
1740 * enable it if possible:
1741 * - plane A only (on pre-965)
1742 * - no pixel mulitply/line duplication
1743 * - no alpha buffer discard
1744 * - no dual wide
1745 * - framebuffer <= 2048 in width, 1536 in height
1746 *
1747 * We can't assume that any compression will take place (worst case),
1748 * so the compressed buffer has to be the same size as the uncompressed
1749 * one. It also must reside (along with the line length buffer) in
1750 * stolen memory.
1751 *
1752 * We need to enable/disable FBC on a global basis.
1753 */
bed4a673 1754static void intel_update_fbc(struct drm_device *dev)
80824003 1755{
80824003 1756 struct drm_i915_private *dev_priv = dev->dev_private;
bed4a673
CW		 1757 struct drm_crtc *crtc = NULL, *tmp_crtc;
1758 struct intel_crtc *intel_crtc;
1759 struct drm_framebuffer *fb;
80824003 1760 struct intel_framebuffer *intel_fb;
05394f39 1761 struct drm_i915_gem_object *obj;
9c928d16
JB		 1762
1763 DRM_DEBUG_KMS("\n");
80824003
JB		 1764
1765 if (!i915_powersave)
1766 return;
1767
ee5382ae 1768 if (!I915_HAS_FBC(dev))
e70236a8
JB		 1769 return;
1770
80824003
JB		 1771 /*
1772 * If FBC is already on, we just have to verify that we can
1773 * keep it that way...
1774 * Need to disable if:
9c928d16 1775 * - more than one pipe is active
80824003
JB		 1776 * - changing FBC params (stride, fence, mode)
1777 * - new fb is too large to fit in compressed buffer
1778 * - going to an unsupported config (interlace, pixel multiply, etc.)
1779 */
9c928d16 1780 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
d210246a 1781 if (tmp_crtc->enabled && tmp_crtc->fb) {
bed4a673
CW		 1782 if (crtc) {
1783 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1784 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1785 goto out_disable;
1786 }
1787 crtc = tmp_crtc;
1788 }
9c928d16 1789 }
bed4a673
CW		 1790
1791 if (!crtc || crtc->fb == NULL) {
1792 DRM_DEBUG_KMS("no output, disabling\n");
1793 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
9c928d16
JB		 1794 goto out_disable;
1795 }
bed4a673
CW		 1796
1797 intel_crtc = to_intel_crtc(crtc);
1798 fb = crtc->fb;
1799 intel_fb = to_intel_framebuffer(fb);
05394f39 1800 obj = intel_fb->obj;
bed4a673 1801
c1a9f047
JB		 1802 if (!i915_enable_fbc) {
1803 DRM_DEBUG_KMS("fbc disabled per module param (default off)\n");
1804 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1805 goto out_disable;
1806 }
05394f39 1807 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
28c97730 1808 DRM_DEBUG_KMS("framebuffer too large, disabling "
5eddb70b 1809 "compression\n");
b5e50c3f 1810 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
80824003
JB		 1811 goto out_disable;
1812 }
bed4a673
CW		 1813 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1814 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
28c97730 1815 DRM_DEBUG_KMS("mode incompatible with compression, "
5eddb70b 1816 "disabling\n");
b5e50c3f 1817 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
80824003
JB		 1818 goto out_disable;
1819 }
bed4a673
CW		 1820 if ((crtc->mode.hdisplay > 2048) ||
1821 (crtc->mode.vdisplay > 1536)) {
28c97730 1822 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
b5e50c3f 1823 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
80824003
JB		 1824 goto out_disable;
1825 }
bed4a673 1826 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
28c97730 1827 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
b5e50c3f 1828 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
80824003
JB		 1829 goto out_disable;
1830 }
de568510
CW		 1831
1832 /* The use of a CPU fence is mandatory in order to detect writes
1833 * by the CPU to the scanout and trigger updates to the FBC.
1834 */
1835 if (obj->tiling_mode != I915_TILING_X ||
1836 obj->fence_reg == I915_FENCE_REG_NONE) {
1837 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
b5e50c3f 1838 dev_priv->no_fbc_reason = FBC_NOT_TILED;
80824003
JB		 1839 goto out_disable;
1840 }
1841
c924b934
JW		 1842 /* If the kernel debugger is active, always disable compression */
1843 if (in_dbg_master())
1844 goto out_disable;
1845
bed4a673 1846 intel_enable_fbc(crtc, 500);
80824003
JB		 1847 return;
1848
1849out_disable:
80824003 1850 /* Multiple disables should be harmless */
a939406f
CW		 1851 if (intel_fbc_enabled(dev)) {
1852 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
ee5382ae 1853 intel_disable_fbc(dev);
a939406f 1854 }
80824003
JB		 1855}
1856
127bd2ac 1857int
48b956c5 1858intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1859 struct drm_i915_gem_object *obj,
919926ae 1860 struct intel_ring_buffer *pipelined)
6b95a207 1861{
ce453d81 1862 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1863 u32 alignment;
1864 int ret;
1865
05394f39 1866 switch (obj->tiling_mode) {
6b95a207 1867 case I915_TILING_NONE:
534843da
CW		 1868 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1869 alignment = 128 * 1024;
a6c45cf0 1870 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1871 alignment = 4 * 1024;
1872 else
1873 alignment = 64 * 1024;
6b95a207
KH		 1874 break;
1875 case I915_TILING_X:
1876 /* pin() will align the object as required by fence */
1877 alignment = 0;
1878 break;
1879 case I915_TILING_Y:
1880 /* FIXME: Is this true? */
1881 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1882 return -EINVAL;
1883 default:
1884 BUG();
1885 }
1886
ce453d81 1887 dev_priv->mm.interruptible = false;
2da3b9b9 1888 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1889 if (ret)
ce453d81 1890 goto err_interruptible;
6b95a207
KH		 1891
1892 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1893 * fence, whereas 965+ only requires a fence if using
1894 * framebuffer compression. For simplicity, we always install
1895 * a fence as the cost is not that onerous.
1896 */
05394f39 1897 if (obj->tiling_mode != I915_TILING_NONE) {
ce453d81 1898 ret = i915_gem_object_get_fence(obj, pipelined);
48b956c5
CW		 1899 if (ret)
1900 goto err_unpin;
6b95a207
KH		 1901 }
1902
ce453d81 1903 dev_priv->mm.interruptible = true;
6b95a207 1904 return 0;
48b956c5
CW		 1905
1906err_unpin:
1907 i915_gem_object_unpin(obj);
ce453d81
CW		 1908err_interruptible:
1909 dev_priv->mm.interruptible = true;
48b956c5 1910 return ret;
6b95a207
KH		 1911}
1912
17638cd6
JB		 1913static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1914 int x, int y)
81255565
JB		 1915{
1916 struct drm_device *dev = crtc->dev;
1917 struct drm_i915_private *dev_priv = dev->dev_private;
1918 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1919 struct intel_framebuffer *intel_fb;
05394f39 1920 struct drm_i915_gem_object *obj;
81255565
JB		 1921 int plane = intel_crtc->plane;
1922 unsigned long Start, Offset;
81255565 1923 u32 dspcntr;
5eddb70b 1924 u32 reg;
81255565
JB		 1925
1926 switch (plane) {
1927 case 0:
1928 case 1:
1929 break;
1930 default:
1931 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1932 return -EINVAL;
1933 }
1934
1935 intel_fb = to_intel_framebuffer(fb);
1936 obj = intel_fb->obj;
81255565 1937
5eddb70b
CW		 1938 reg = DSPCNTR(plane);
1939 dspcntr = I915_READ(reg);
81255565
JB		 1940 /* Mask out pixel format bits in case we change it */
1941 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1942 switch (fb->bits_per_pixel) {
1943 case 8:
1944 dspcntr |= DISPPLANE_8BPP;
1945 break;
1946 case 16:
1947 if (fb->depth == 15)
1948 dspcntr |= DISPPLANE_15_16BPP;
1949 else
1950 dspcntr |= DISPPLANE_16BPP;
1951 break;
1952 case 24:
1953 case 32:
1954 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1955 break;
1956 default:
17638cd6 1957 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
81255565
JB		 1958 return -EINVAL;
1959 }
a6c45cf0 1960 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1961 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1962 dspcntr |= DISPPLANE_TILED;
1963 else
1964 dspcntr &= ~DISPPLANE_TILED;
1965 }
1966
5eddb70b 1967 I915_WRITE(reg, dspcntr);
81255565 1968
05394f39 1969 Start = obj->gtt_offset;
81255565
JB		 1970 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1971
4e6cfefc
CW		 1972 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1973 Start, Offset, x, y, fb->pitch);
5eddb70b 1974 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
a6c45cf0 1975 if (INTEL_INFO(dev)->gen >= 4) {
5eddb70b
CW		 1976 I915_WRITE(DSPSURF(plane), Start);
1977 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1978 I915_WRITE(DSPADDR(plane), Offset);
1979 } else
1980 I915_WRITE(DSPADDR(plane), Start + Offset);
1981 POSTING_READ(reg);
81255565 1982
17638cd6
JB		 1983 return 0;
1984}
1985
1986static int ironlake_update_plane(struct drm_crtc *crtc,
1987 struct drm_framebuffer *fb, int x, int y)
1988{
1989 struct drm_device *dev = crtc->dev;
1990 struct drm_i915_private *dev_priv = dev->dev_private;
1991 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1992 struct intel_framebuffer *intel_fb;
1993 struct drm_i915_gem_object *obj;
1994 int plane = intel_crtc->plane;
1995 unsigned long Start, Offset;
1996 u32 dspcntr;
1997 u32 reg;
1998
1999 switch (plane) {
2000 case 0:
2001 case 1:
2002 break;
2003 default:
2004 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2005 return -EINVAL;
2006 }
2007
2008 intel_fb = to_intel_framebuffer(fb);
2009 obj = intel_fb->obj;
2010
2011 reg = DSPCNTR(plane);
2012 dspcntr = I915_READ(reg);
2013 /* Mask out pixel format bits in case we change it */
2014 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2015 switch (fb->bits_per_pixel) {
2016 case 8:
2017 dspcntr |= DISPPLANE_8BPP;
2018 break;
2019 case 16:
2020 if (fb->depth != 16)
2021 return -EINVAL;
2022
2023 dspcntr |= DISPPLANE_16BPP;
2024 break;
2025 case 24:
2026 case 32:
2027 if (fb->depth == 24)
2028 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2029 else if (fb->depth == 30)
2030 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2031 else
2032 return -EINVAL;
2033 break;
2034 default:
2035 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2036 return -EINVAL;
2037 }
2038
2039 if (obj->tiling_mode != I915_TILING_NONE)
2040 dspcntr |= DISPPLANE_TILED;
2041 else
2042 dspcntr &= ~DISPPLANE_TILED;
2043
2044 /* must disable */
2045 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2046
2047 I915_WRITE(reg, dspcntr);
2048
2049 Start = obj->gtt_offset;
2050 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2051
2052 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2053 Start, Offset, x, y, fb->pitch);
2054 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2055 I915_WRITE(DSPSURF(plane), Start);
2056 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2057 I915_WRITE(DSPADDR(plane), Offset);
2058 POSTING_READ(reg);
2059
2060 return 0;
2061}
2062
2063/* Assume fb object is pinned & idle & fenced and just update base pointers */
2064static int
2065intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2066 int x, int y, enum mode_set_atomic state)
2067{
2068 struct drm_device *dev = crtc->dev;
2069 struct drm_i915_private *dev_priv = dev->dev_private;
2070 int ret;
2071
2072 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2073 if (ret)
2074 return ret;
2075
bed4a673 2076 intel_update_fbc(dev);
3dec0095 2077 intel_increase_pllclock(crtc);
81255565
JB		 2078
2079 return 0;
2080}
2081
5c3b82e2 2082static int
3c4fdcfb
KH		 2083intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2084 struct drm_framebuffer *old_fb)
79e53945
JB		 2085{
2086 struct drm_device *dev = crtc->dev;
79e53945
JB		 2087 struct drm_i915_master_private *master_priv;
2088 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5c3b82e2 2089 int ret;
79e53945
JB		 2090
2091 /* no fb bound */
2092 if (!crtc->fb) {
28c97730 2093 DRM_DEBUG_KMS("No FB bound\n");
5c3b82e2
CW		 2094 return 0;
2095 }
2096
265db958 2097 switch (intel_crtc->plane) {
5c3b82e2
CW		 2098 case 0:
2099 case 1:
2100 break;
2101 default:
5c3b82e2 2102 return -EINVAL;
79e53945
JB		 2103 }
2104
5c3b82e2 2105 mutex_lock(&dev->struct_mutex);
265db958
CW		 2106 ret = intel_pin_and_fence_fb_obj(dev,
2107 to_intel_framebuffer(crtc->fb)->obj,
919926ae 2108 NULL);
5c3b82e2
CW		 2109 if (ret != 0) {
2110 mutex_unlock(&dev->struct_mutex);
2111 return ret;
2112 }
79e53945 2113
265db958 2114 if (old_fb) {
e6c3a2a6 2115 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 2116 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
265db958 2117
e6c3a2a6 2118 wait_event(dev_priv->pending_flip_queue,
01eec727 2119 atomic_read(&dev_priv->mm.wedged) ||
05394f39 2120 atomic_read(&obj->pending_flip) == 0);
85345517
CW		 2121
2122 /* Big Hammer, we also need to ensure that any pending
2123 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2124 * current scanout is retired before unpinning the old
2125 * framebuffer.
01eec727
CW		 2126 *
2127 * This should only fail upon a hung GPU, in which case we
2128 * can safely continue.
85345517 2129 */
a8198eea 2130 ret = i915_gem_object_finish_gpu(obj);
01eec727 2131 (void) ret;
265db958
CW		 2132 }
2133
21c74a8e
JW		 2134 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2135 LEAVE_ATOMIC_MODE_SET);
4e6cfefc 2136 if (ret) {
265db958 2137 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
5c3b82e2 2138 mutex_unlock(&dev->struct_mutex);
4e6cfefc 2139 return ret;
79e53945 2140 }
3c4fdcfb 2141
b7f1de28
CW		 2142 if (old_fb) {
2143 intel_wait_for_vblank(dev, intel_crtc->pipe);
265db958 2144 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2145 }
652c393a 2146
5c3b82e2 2147 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 2148
2149 if (!dev->primary->master)
5c3b82e2 2150 return 0;
79e53945
JB		 2151
2152 master_priv = dev->primary->master->driver_priv;
2153 if (!master_priv->sarea_priv)
5c3b82e2 2154 return 0;
79e53945 2155
265db958 2156 if (intel_crtc->pipe) {
79e53945
JB		 2157 master_priv->sarea_priv->pipeB_x = x;
2158 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 2159 } else {
2160 master_priv->sarea_priv->pipeA_x = x;
2161 master_priv->sarea_priv->pipeA_y = y;
79e53945 2162 }
5c3b82e2
CW		 2163
2164 return 0;
79e53945
JB		 2165}
2166
5eddb70b 2167static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2168{
2169 struct drm_device *dev = crtc->dev;
2170 struct drm_i915_private *dev_priv = dev->dev_private;
2171 u32 dpa_ctl;
2172
28c97730 2173 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2174 dpa_ctl = I915_READ(DP_A);
2175 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2176
2177 if (clock < 200000) {
2178 u32 temp;
2179 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2180 /* workaround for 160Mhz:
2181 1) program 0x4600c bits 15:0 = 0x8124
2182 2) program 0x46010 bit 0 = 1
2183 3) program 0x46034 bit 24 = 1
2184 4) program 0x64000 bit 14 = 1
2185 */
2186 temp = I915_READ(0x4600c);
2187 temp &= 0xffff0000;
2188 I915_WRITE(0x4600c, temp | 0x8124);
2189
2190 temp = I915_READ(0x46010);
2191 I915_WRITE(0x46010, temp | 1);
2192
2193 temp = I915_READ(0x46034);
2194 I915_WRITE(0x46034, temp | (1 << 24));
2195 } else {
2196 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2197 }
2198 I915_WRITE(DP_A, dpa_ctl);
2199
5eddb70b 2200 POSTING_READ(DP_A);
32f9d658
ZW		 2201 udelay(500);
2202}
2203
5e84e1a4
ZW		 2204static void intel_fdi_normal_train(struct drm_crtc *crtc)
2205{
2206 struct drm_device *dev = crtc->dev;
2207 struct drm_i915_private *dev_priv = dev->dev_private;
2208 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2209 int pipe = intel_crtc->pipe;
2210 u32 reg, temp;
2211
2212 /* enable normal train */
2213 reg = FDI_TX_CTL(pipe);
2214 temp = I915_READ(reg);
61e499bf 2215 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2216 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2217 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2218 } else {
2219 temp &= ~FDI_LINK_TRAIN_NONE;
2220 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2221 }
5e84e1a4
ZW		 2222 I915_WRITE(reg, temp);
2223
2224 reg = FDI_RX_CTL(pipe);
2225 temp = I915_READ(reg);
2226 if (HAS_PCH_CPT(dev)) {
2227 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2228 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2229 } else {
2230 temp &= ~FDI_LINK_TRAIN_NONE;
2231 temp |= FDI_LINK_TRAIN_NONE;
2232 }
2233 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2234
2235 /* wait one idle pattern time */
2236 POSTING_READ(reg);
2237 udelay(1000);
357555c0
JB		 2238
2239 /* IVB wants error correction enabled */
2240 if (IS_IVYBRIDGE(dev))
2241 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2242 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2243}
2244
8db9d77b
ZW		 2245/* The FDI link training functions for ILK/Ibexpeak. */
2246static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2247{
2248 struct drm_device *dev = crtc->dev;
2249 struct drm_i915_private *dev_priv = dev->dev_private;
2250 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2251 int pipe = intel_crtc->pipe;
0fc932b8 2252 int plane = intel_crtc->plane;
5eddb70b 2253 u32 reg, temp, tries;
8db9d77b 2254
0fc932b8
JB		 2255 /* FDI needs bits from pipe & plane first */
2256 assert_pipe_enabled(dev_priv, pipe);
2257 assert_plane_enabled(dev_priv, plane);
2258
e1a44743
AJ		 2259 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2260 for train result */
5eddb70b
CW		 2261 reg = FDI_RX_IMR(pipe);
2262 temp = I915_READ(reg);
e1a44743
AJ		 2263 temp &= ~FDI_RX_SYMBOL_LOCK;
2264 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2265 I915_WRITE(reg, temp);
2266 I915_READ(reg);
e1a44743
AJ		 2267 udelay(150);
2268
8db9d77b 2269 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2270 reg = FDI_TX_CTL(pipe);
2271 temp = I915_READ(reg);
77ffb597
AJ		 2272 temp &= ~(7 << 19);
2273 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2274 temp &= ~FDI_LINK_TRAIN_NONE;
2275 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2276 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2277
5eddb70b
CW		 2278 reg = FDI_RX_CTL(pipe);
2279 temp = I915_READ(reg);
8db9d77b
ZW		 2280 temp &= ~FDI_LINK_TRAIN_NONE;
2281 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2282 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2283
2284 POSTING_READ(reg);
8db9d77b
ZW		 2285 udelay(150);
2286
5b2adf89 2287 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2288 if (HAS_PCH_IBX(dev)) {
2289 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2290 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2291 FDI_RX_PHASE_SYNC_POINTER_EN);
2292 }
5b2adf89 2293
5eddb70b 2294 reg = FDI_RX_IIR(pipe);
e1a44743 2295 for (tries = 0; tries < 5; tries++) {
5eddb70b 2296 temp = I915_READ(reg);
8db9d77b
ZW		 2297 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2298
2299 if ((temp & FDI_RX_BIT_LOCK)) {
2300 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2301 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2302 break;
2303 }
8db9d77b 2304 }
e1a44743 2305 if (tries == 5)
5eddb70b 2306 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2307
2308 /* Train 2 */
5eddb70b
CW		 2309 reg = FDI_TX_CTL(pipe);
2310 temp = I915_READ(reg);
8db9d77b
ZW		 2311 temp &= ~FDI_LINK_TRAIN_NONE;
2312 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2313 I915_WRITE(reg, temp);
8db9d77b 2314
5eddb70b
CW		 2315 reg = FDI_RX_CTL(pipe);
2316 temp = I915_READ(reg);
8db9d77b
ZW		 2317 temp &= ~FDI_LINK_TRAIN_NONE;
2318 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2319 I915_WRITE(reg, temp);
8db9d77b 2320
5eddb70b
CW		 2321 POSTING_READ(reg);
2322 udelay(150);
8db9d77b 2323
5eddb70b 2324 reg = FDI_RX_IIR(pipe);
e1a44743 2325 for (tries = 0; tries < 5; tries++) {
5eddb70b 2326 temp = I915_READ(reg);
8db9d77b
ZW		 2327 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2328
2329 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2330 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2331 DRM_DEBUG_KMS("FDI train 2 done.\n");
2332 break;
2333 }
8db9d77b 2334 }
e1a44743 2335 if (tries == 5)
5eddb70b 2336 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2337
2338 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2339
8db9d77b
ZW		 2340}
2341
311bd68e 2342static const int snb_b_fdi_train_param [] = {
8db9d77b
ZW		 2343 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2344 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2345 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2346 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2347};
2348
2349/* The FDI link training functions for SNB/Cougarpoint. */
2350static void gen6_fdi_link_train(struct drm_crtc *crtc)
2351{
2352 struct drm_device *dev = crtc->dev;
2353 struct drm_i915_private *dev_priv = dev->dev_private;
2354 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2355 int pipe = intel_crtc->pipe;
5eddb70b 2356 u32 reg, temp, i;
8db9d77b 2357
e1a44743
AJ		 2358 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2359 for train result */
5eddb70b
CW		 2360 reg = FDI_RX_IMR(pipe);
2361 temp = I915_READ(reg);
e1a44743
AJ		 2362 temp &= ~FDI_RX_SYMBOL_LOCK;
2363 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2364 I915_WRITE(reg, temp);
2365
2366 POSTING_READ(reg);
e1a44743
AJ		 2367 udelay(150);
2368
8db9d77b 2369 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2370 reg = FDI_TX_CTL(pipe);
2371 temp = I915_READ(reg);
77ffb597
AJ		 2372 temp &= ~(7 << 19);
2373 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2374 temp &= ~FDI_LINK_TRAIN_NONE;
2375 temp |= FDI_LINK_TRAIN_PATTERN_1;
2376 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2377 /* SNB-B */
2378 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2379 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2380
5eddb70b
CW		 2381 reg = FDI_RX_CTL(pipe);
2382 temp = I915_READ(reg);
8db9d77b
ZW		 2383 if (HAS_PCH_CPT(dev)) {
2384 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2385 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2386 } else {
2387 temp &= ~FDI_LINK_TRAIN_NONE;
2388 temp |= FDI_LINK_TRAIN_PATTERN_1;
2389 }
5eddb70b
CW		 2390 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2391
2392 POSTING_READ(reg);
8db9d77b
ZW		 2393 udelay(150);
2394
8db9d77b 2395 for (i = 0; i < 4; i++ ) {
5eddb70b
CW		 2396 reg = FDI_TX_CTL(pipe);
2397 temp = I915_READ(reg);
8db9d77b
ZW		 2398 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2399 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2400 I915_WRITE(reg, temp);
2401
2402 POSTING_READ(reg);
8db9d77b
ZW		 2403 udelay(500);
2404
5eddb70b
CW		 2405 reg = FDI_RX_IIR(pipe);
2406 temp = I915_READ(reg);
8db9d77b
ZW		 2407 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2408
2409 if (temp & FDI_RX_BIT_LOCK) {
5eddb70b 2410 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2411 DRM_DEBUG_KMS("FDI train 1 done.\n");
2412 break;
2413 }
2414 }
2415 if (i == 4)
5eddb70b 2416 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2417
2418 /* Train 2 */
5eddb70b
CW		 2419 reg = FDI_TX_CTL(pipe);
2420 temp = I915_READ(reg);
8db9d77b
ZW		 2421 temp &= ~FDI_LINK_TRAIN_NONE;
2422 temp |= FDI_LINK_TRAIN_PATTERN_2;
2423 if (IS_GEN6(dev)) {
2424 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2425 /* SNB-B */
2426 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2427 }
5eddb70b 2428 I915_WRITE(reg, temp);
8db9d77b 2429
5eddb70b
CW		 2430 reg = FDI_RX_CTL(pipe);
2431 temp = I915_READ(reg);
8db9d77b
ZW		 2432 if (HAS_PCH_CPT(dev)) {
2433 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2434 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2435 } else {
2436 temp &= ~FDI_LINK_TRAIN_NONE;
2437 temp |= FDI_LINK_TRAIN_PATTERN_2;
2438 }
5eddb70b
CW		 2439 I915_WRITE(reg, temp);
2440
2441 POSTING_READ(reg);
8db9d77b
ZW		 2442 udelay(150);
2443
2444 for (i = 0; i < 4; i++ ) {
5eddb70b
CW		 2445 reg = FDI_TX_CTL(pipe);
2446 temp = I915_READ(reg);
8db9d77b
ZW		 2447 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2448 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2449 I915_WRITE(reg, temp);
2450
2451 POSTING_READ(reg);
8db9d77b
ZW		 2452 udelay(500);
2453
5eddb70b
CW		 2454 reg = FDI_RX_IIR(pipe);
2455 temp = I915_READ(reg);
8db9d77b
ZW		 2456 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2457
2458 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2459 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2460 DRM_DEBUG_KMS("FDI train 2 done.\n");
2461 break;
2462 }
2463 }
2464 if (i == 4)
5eddb70b 2465 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2466
2467 DRM_DEBUG_KMS("FDI train done.\n");
2468}
2469
357555c0
JB		 2470/* Manual link training for Ivy Bridge A0 parts */
2471static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2472{
2473 struct drm_device *dev = crtc->dev;
2474 struct drm_i915_private *dev_priv = dev->dev_private;
2475 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2476 int pipe = intel_crtc->pipe;
2477 u32 reg, temp, i;
2478
2479 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2480 for train result */
2481 reg = FDI_RX_IMR(pipe);
2482 temp = I915_READ(reg);
2483 temp &= ~FDI_RX_SYMBOL_LOCK;
2484 temp &= ~FDI_RX_BIT_LOCK;
2485 I915_WRITE(reg, temp);
2486
2487 POSTING_READ(reg);
2488 udelay(150);
2489
2490 /* enable CPU FDI TX and PCH FDI RX */
2491 reg = FDI_TX_CTL(pipe);
2492 temp = I915_READ(reg);
2493 temp &= ~(7 << 19);
2494 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2495 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2496 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2497 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2498 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2499 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2500
2501 reg = FDI_RX_CTL(pipe);
2502 temp = I915_READ(reg);
2503 temp &= ~FDI_LINK_TRAIN_AUTO;
2504 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2505 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2506 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2507
2508 POSTING_READ(reg);
2509 udelay(150);
2510
2511 for (i = 0; i < 4; i++ ) {
2512 reg = FDI_TX_CTL(pipe);
2513 temp = I915_READ(reg);
2514 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2515 temp |= snb_b_fdi_train_param[i];
2516 I915_WRITE(reg, temp);
2517
2518 POSTING_READ(reg);
2519 udelay(500);
2520
2521 reg = FDI_RX_IIR(pipe);
2522 temp = I915_READ(reg);
2523 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2524
2525 if (temp & FDI_RX_BIT_LOCK ||
2526 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2527 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2528 DRM_DEBUG_KMS("FDI train 1 done.\n");
2529 break;
2530 }
2531 }
2532 if (i == 4)
2533 DRM_ERROR("FDI train 1 fail!\n");
2534
2535 /* Train 2 */
2536 reg = FDI_TX_CTL(pipe);
2537 temp = I915_READ(reg);
2538 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2539 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2540 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2541 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2542 I915_WRITE(reg, temp);
2543
2544 reg = FDI_RX_CTL(pipe);
2545 temp = I915_READ(reg);
2546 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2547 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2548 I915_WRITE(reg, temp);
2549
2550 POSTING_READ(reg);
2551 udelay(150);
2552
2553 for (i = 0; i < 4; i++ ) {
2554 reg = FDI_TX_CTL(pipe);
2555 temp = I915_READ(reg);
2556 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2557 temp |= snb_b_fdi_train_param[i];
2558 I915_WRITE(reg, temp);
2559
2560 POSTING_READ(reg);
2561 udelay(500);
2562
2563 reg = FDI_RX_IIR(pipe);
2564 temp = I915_READ(reg);
2565 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2566
2567 if (temp & FDI_RX_SYMBOL_LOCK) {
2568 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2569 DRM_DEBUG_KMS("FDI train 2 done.\n");
2570 break;
2571 }
2572 }
2573 if (i == 4)
2574 DRM_ERROR("FDI train 2 fail!\n");
2575
2576 DRM_DEBUG_KMS("FDI train done.\n");
2577}
2578
2579static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2c07245f
ZW		 2580{
2581 struct drm_device *dev = crtc->dev;
2582 struct drm_i915_private *dev_priv = dev->dev_private;
2583 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2584 int pipe = intel_crtc->pipe;
5eddb70b 2585 u32 reg, temp;
79e53945 2586
c64e311e 2587 /* Write the TU size bits so error detection works */
5eddb70b
CW		 2588 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2589 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 2590
c98e9dcf 2591 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2592 reg = FDI_RX_CTL(pipe);
2593 temp = I915_READ(reg);
2594 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2595 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2596 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2597 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2598
2599 POSTING_READ(reg);
c98e9dcf
JB		 2600 udelay(200);
2601
2602 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2603 temp = I915_READ(reg);
2604 I915_WRITE(reg, temp | FDI_PCDCLK);
2605
2606 POSTING_READ(reg);
c98e9dcf
JB		 2607 udelay(200);
2608
2609 /* Enable CPU FDI TX PLL, always on for Ironlake */
5eddb70b
CW		 2610 reg = FDI_TX_CTL(pipe);
2611 temp = I915_READ(reg);
c98e9dcf 2612 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5eddb70b
CW		 2613 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2614
2615 POSTING_READ(reg);
c98e9dcf 2616 udelay(100);
6be4a607 2617 }
0e23b99d
JB		 2618}
2619
0fc932b8
JB		 2620static void ironlake_fdi_disable(struct drm_crtc *crtc)
2621{
2622 struct drm_device *dev = crtc->dev;
2623 struct drm_i915_private *dev_priv = dev->dev_private;
2624 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2625 int pipe = intel_crtc->pipe;
2626 u32 reg, temp;
2627
2628 /* disable CPU FDI tx and PCH FDI rx */
2629 reg = FDI_TX_CTL(pipe);
2630 temp = I915_READ(reg);
2631 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2632 POSTING_READ(reg);
2633
2634 reg = FDI_RX_CTL(pipe);
2635 temp = I915_READ(reg);
2636 temp &= ~(0x7 << 16);
2637 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2638 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2639
2640 POSTING_READ(reg);
2641 udelay(100);
2642
2643 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2644 if (HAS_PCH_IBX(dev)) {
2645 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2646 I915_WRITE(FDI_RX_CHICKEN(pipe),
2647 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18
JB		 2648 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2649 }
0fc932b8
JB		 2650
2651 /* still set train pattern 1 */
2652 reg = FDI_TX_CTL(pipe);
2653 temp = I915_READ(reg);
2654 temp &= ~FDI_LINK_TRAIN_NONE;
2655 temp |= FDI_LINK_TRAIN_PATTERN_1;
2656 I915_WRITE(reg, temp);
2657
2658 reg = FDI_RX_CTL(pipe);
2659 temp = I915_READ(reg);
2660 if (HAS_PCH_CPT(dev)) {
2661 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2662 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2663 } else {
2664 temp &= ~FDI_LINK_TRAIN_NONE;
2665 temp |= FDI_LINK_TRAIN_PATTERN_1;
2666 }
2667 /* BPC in FDI rx is consistent with that in PIPECONF */
2668 temp &= ~(0x07 << 16);
2669 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2670 I915_WRITE(reg, temp);
2671
2672 POSTING_READ(reg);
2673 udelay(100);
2674}
2675
6b383a7f
CW		 2676/*
2677 * When we disable a pipe, we need to clear any pending scanline wait events
2678 * to avoid hanging the ring, which we assume we are waiting on.
2679 */
2680static void intel_clear_scanline_wait(struct drm_device *dev)
2681{
2682 struct drm_i915_private *dev_priv = dev->dev_private;
8168bd48 2683 struct intel_ring_buffer *ring;
6b383a7f
CW		 2684 u32 tmp;
2685
2686 if (IS_GEN2(dev))
2687 /* Can't break the hang on i8xx */
2688 return;
2689
1ec14ad3 2690 ring = LP_RING(dev_priv);
8168bd48
CW		 2691 tmp = I915_READ_CTL(ring);
2692 if (tmp & RING_WAIT)
2693 I915_WRITE_CTL(ring, tmp);
6b383a7f
CW		 2694}
2695
e6c3a2a6
CW		 2696static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2697{
05394f39 2698 struct drm_i915_gem_object *obj;
e6c3a2a6
CW		 2699 struct drm_i915_private *dev_priv;
2700
2701 if (crtc->fb == NULL)
2702 return;
2703
05394f39 2704 obj = to_intel_framebuffer(crtc->fb)->obj;
e6c3a2a6
CW		 2705 dev_priv = crtc->dev->dev_private;
2706 wait_event(dev_priv->pending_flip_queue,
05394f39 2707 atomic_read(&obj->pending_flip) == 0);
e6c3a2a6
CW		 2708}
2709
040484af
JB		 2710static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2711{
2712 struct drm_device *dev = crtc->dev;
2713 struct drm_mode_config *mode_config = &dev->mode_config;
2714 struct intel_encoder *encoder;
2715
2716 /*
2717 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2718 * must be driven by its own crtc; no sharing is possible.
2719 */
2720 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2721 if (encoder->base.crtc != crtc)
2722 continue;
2723
2724 switch (encoder->type) {
2725 case INTEL_OUTPUT_EDP:
2726 if (!intel_encoder_is_pch_edp(&encoder->base))
2727 return false;
2728 continue;
2729 }
2730 }
2731
2732 return true;
2733}
2734
f67a559d
JB		 2735/*
2736 * Enable PCH resources required for PCH ports:
2737 * - PCH PLLs
2738 * - FDI training & RX/TX
2739 * - update transcoder timings
2740 * - DP transcoding bits
2741 * - transcoder
2742 */
2743static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2744{
2745 struct drm_device *dev = crtc->dev;
2746 struct drm_i915_private *dev_priv = dev->dev_private;
2747 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2748 int pipe = intel_crtc->pipe;
5eddb70b 2749 u32 reg, temp;
2c07245f 2750
c98e9dcf 2751 /* For PCH output, training FDI link */
674cf967 2752 dev_priv->display.fdi_link_train(crtc);
2c07245f 2753
92f2584a 2754 intel_enable_pch_pll(dev_priv, pipe);
8db9d77b 2755
c98e9dcf
JB		 2756 if (HAS_PCH_CPT(dev)) {
2757 /* Be sure PCH DPLL SEL is set */
2758 temp = I915_READ(PCH_DPLL_SEL);
5eddb70b 2759 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
c98e9dcf 2760 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
5eddb70b 2761 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
c98e9dcf
JB		 2762 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2763 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2764 }
5eddb70b 2765
d9b6cb56
JB		 2766 /* set transcoder timing, panel must allow it */
2767 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 2768 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2769 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2770 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 2771
5eddb70b
CW		 2772 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2773 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2774 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
8db9d77b 2775
5e84e1a4
ZW		 2776 intel_fdi_normal_train(crtc);
2777
c98e9dcf
JB		 2778 /* For PCH DP, enable TRANS_DP_CTL */
2779 if (HAS_PCH_CPT(dev) &&
2780 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
9325c9f0 2781 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 2782 reg = TRANS_DP_CTL(pipe);
2783 temp = I915_READ(reg);
2784 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 2785 TRANS_DP_SYNC_MASK |
2786 TRANS_DP_BPC_MASK);
5eddb70b
CW		 2787 temp |= (TRANS_DP_OUTPUT_ENABLE |
2788 TRANS_DP_ENH_FRAMING);
9325c9f0 2789 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 2790
2791 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 2792 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 2793 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 2794 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 2795
2796 switch (intel_trans_dp_port_sel(crtc)) {
2797 case PCH_DP_B:
5eddb70b 2798 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 2799 break;
2800 case PCH_DP_C:
5eddb70b 2801 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 2802 break;
2803 case PCH_DP_D:
5eddb70b 2804 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 2805 break;
2806 default:
2807 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 2808 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 2809 break;
32f9d658 2810 }
2c07245f 2811
5eddb70b 2812 I915_WRITE(reg, temp);
6be4a607 2813 }
b52eb4dc 2814
040484af 2815 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 2816}
2817
2818static void ironlake_crtc_enable(struct drm_crtc *crtc)
2819{
2820 struct drm_device *dev = crtc->dev;
2821 struct drm_i915_private *dev_priv = dev->dev_private;
2822 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2823 int pipe = intel_crtc->pipe;
2824 int plane = intel_crtc->plane;
2825 u32 temp;
2826 bool is_pch_port;
2827
2828 if (intel_crtc->active)
2829 return;
2830
2831 intel_crtc->active = true;
2832 intel_update_watermarks(dev);
2833
2834 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2835 temp = I915_READ(PCH_LVDS);
2836 if ((temp & LVDS_PORT_EN) == 0)
2837 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2838 }
2839
2840 is_pch_port = intel_crtc_driving_pch(crtc);
2841
2842 if (is_pch_port)
357555c0 2843 ironlake_fdi_pll_enable(crtc);
f67a559d
JB		 2844 else
2845 ironlake_fdi_disable(crtc);
2846
2847 /* Enable panel fitting for LVDS */
2848 if (dev_priv->pch_pf_size &&
2849 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2850 /* Force use of hard-coded filter coefficients
2851 * as some pre-programmed values are broken,
2852 * e.g. x201.
2853 */
9db4a9c7
JB		 2854 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2855 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2856 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 2857 }
2858
2859 intel_enable_pipe(dev_priv, pipe, is_pch_port);
2860 intel_enable_plane(dev_priv, plane, pipe);
2861
2862 if (is_pch_port)
2863 ironlake_pch_enable(crtc);
c98e9dcf 2864
6be4a607 2865 intel_crtc_load_lut(crtc);
d1ebd816
BW		 2866
2867 mutex_lock(&dev->struct_mutex);
bed4a673 2868 intel_update_fbc(dev);
d1ebd816
BW		 2869 mutex_unlock(&dev->struct_mutex);
2870
6b383a7f 2871 intel_crtc_update_cursor(crtc, true);
6be4a607
JB		 2872}
2873
2874static void ironlake_crtc_disable(struct drm_crtc *crtc)
2875{
2876 struct drm_device *dev = crtc->dev;
2877 struct drm_i915_private *dev_priv = dev->dev_private;
2878 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2879 int pipe = intel_crtc->pipe;
2880 int plane = intel_crtc->plane;
5eddb70b 2881 u32 reg, temp;
b52eb4dc 2882
f7abfe8b
CW		 2883 if (!intel_crtc->active)
2884 return;
2885
e6c3a2a6 2886 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 2887 drm_vblank_off(dev, pipe);
6b383a7f 2888 intel_crtc_update_cursor(crtc, false);
5eddb70b 2889
b24e7179 2890 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 2891
973d04f9
CW		 2892 if (dev_priv->cfb_plane == plane)
2893 intel_disable_fbc(dev);
2c07245f 2894
b24e7179 2895 intel_disable_pipe(dev_priv, pipe);
32f9d658 2896
6be4a607 2897 /* Disable PF */
9db4a9c7
JB		 2898 I915_WRITE(PF_CTL(pipe), 0);
2899 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 2900
0fc932b8 2901 ironlake_fdi_disable(crtc);
2c07245f 2902
47a05eca
JB		 2903 /* This is a horrible layering violation; we should be doing this in
2904 * the connector/encoder ->prepare instead, but we don't always have
2905 * enough information there about the config to know whether it will
2906 * actually be necessary or just cause undesired flicker.
2907 */
2908 intel_disable_pch_ports(dev_priv, pipe);
249c0e64 2909
040484af 2910 intel_disable_transcoder(dev_priv, pipe);
913d8d11 2911
6be4a607
JB		 2912 if (HAS_PCH_CPT(dev)) {
2913 /* disable TRANS_DP_CTL */
5eddb70b
CW		 2914 reg = TRANS_DP_CTL(pipe);
2915 temp = I915_READ(reg);
2916 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 2917 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 2918 I915_WRITE(reg, temp);
6be4a607
JB		 2919
2920 /* disable DPLL_SEL */
2921 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 2922 switch (pipe) {
2923 case 0:
2924 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2925 break;
2926 case 1:
6be4a607 2927 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 2928 break;
2929 case 2:
2930 /* FIXME: manage transcoder PLLs? */
2931 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
2932 break;
2933 default:
2934 BUG(); /* wtf */
2935 }
6be4a607 2936 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 2937 }
e3421a18 2938
6be4a607 2939 /* disable PCH DPLL */
92f2584a 2940 intel_disable_pch_pll(dev_priv, pipe);
8db9d77b 2941
6be4a607 2942 /* Switch from PCDclk to Rawclk */
5eddb70b
CW		 2943 reg = FDI_RX_CTL(pipe);
2944 temp = I915_READ(reg);
2945 I915_WRITE(reg, temp & ~FDI_PCDCLK);
8db9d77b 2946
6be4a607 2947 /* Disable CPU FDI TX PLL */
5eddb70b
CW		 2948 reg = FDI_TX_CTL(pipe);
2949 temp = I915_READ(reg);
2950 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2951
2952 POSTING_READ(reg);
6be4a607 2953 udelay(100);
8db9d77b 2954
5eddb70b
CW		 2955 reg = FDI_RX_CTL(pipe);
2956 temp = I915_READ(reg);
2957 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2c07245f 2958
6be4a607 2959 /* Wait for the clocks to turn off. */
5eddb70b 2960 POSTING_READ(reg);
6be4a607 2961 udelay(100);
6b383a7f 2962
f7abfe8b 2963 intel_crtc->active = false;
6b383a7f 2964 intel_update_watermarks(dev);
d1ebd816
BW		 2965
2966 mutex_lock(&dev->struct_mutex);
6b383a7f
CW		 2967 intel_update_fbc(dev);
2968 intel_clear_scanline_wait(dev);
d1ebd816 2969 mutex_unlock(&dev->struct_mutex);
6be4a607 2970}
1b3c7a47 2971
6be4a607
JB		 2972static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2973{
2974 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2975 int pipe = intel_crtc->pipe;
2976 int plane = intel_crtc->plane;
8db9d77b 2977
6be4a607
JB		 2978 /* XXX: When our outputs are all unaware of DPMS modes other than off
2979 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2980 */
2981 switch (mode) {
2982 case DRM_MODE_DPMS_ON:
2983 case DRM_MODE_DPMS_STANDBY:
2984 case DRM_MODE_DPMS_SUSPEND:
2985 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2986 ironlake_crtc_enable(crtc);
2987 break;
1b3c7a47 2988
6be4a607
JB		 2989 case DRM_MODE_DPMS_OFF:
2990 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2991 ironlake_crtc_disable(crtc);
2c07245f
ZW		 2992 break;
2993 }
2994}
2995
02e792fb
DV		 2996static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2997{
02e792fb 2998 if (!enable && intel_crtc->overlay) {
23f09ce3 2999 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3000 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3001
23f09ce3 3002 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3003 dev_priv->mm.interruptible = false;
3004 (void) intel_overlay_switch_off(intel_crtc->overlay);
3005 dev_priv->mm.interruptible = true;
23f09ce3 3006 mutex_unlock(&dev->struct_mutex);
02e792fb 3007 }
02e792fb 3008
5dcdbcb0
CW		 3009 /* Let userspace switch the overlay on again. In most cases userspace
3010 * has to recompute where to put it anyway.
3011 */
02e792fb
DV		 3012}
3013
0b8765c6 3014static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3015{
3016 struct drm_device *dev = crtc->dev;
79e53945
JB		 3017 struct drm_i915_private *dev_priv = dev->dev_private;
3018 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3019 int pipe = intel_crtc->pipe;
80824003 3020 int plane = intel_crtc->plane;
79e53945 3021
f7abfe8b
CW		 3022 if (intel_crtc->active)
3023 return;
3024
3025 intel_crtc->active = true;
6b383a7f
CW		 3026 intel_update_watermarks(dev);
3027
63d7bbe9 3028 intel_enable_pll(dev_priv, pipe);
040484af 3029 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3030 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3031
0b8765c6 3032 intel_crtc_load_lut(crtc);
bed4a673 3033 intel_update_fbc(dev);
79e53945 3034
0b8765c6
JB		 3035 /* Give the overlay scaler a chance to enable if it's on this pipe */
3036 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3037 intel_crtc_update_cursor(crtc, true);
0b8765c6 3038}
79e53945 3039
0b8765c6
JB		 3040static void i9xx_crtc_disable(struct drm_crtc *crtc)
3041{
3042 struct drm_device *dev = crtc->dev;
3043 struct drm_i915_private *dev_priv = dev->dev_private;
3044 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3045 int pipe = intel_crtc->pipe;
3046 int plane = intel_crtc->plane;
b690e96c 3047
f7abfe8b
CW		 3048 if (!intel_crtc->active)
3049 return;
3050
0b8765c6 3051 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3052 intel_crtc_wait_for_pending_flips(crtc);
3053 drm_vblank_off(dev, pipe);
0b8765c6 3054 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3055 intel_crtc_update_cursor(crtc, false);
0b8765c6 3056
973d04f9
CW		 3057 if (dev_priv->cfb_plane == plane)
3058 intel_disable_fbc(dev);
79e53945 3059
b24e7179 3060 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3061 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3062 intel_disable_pll(dev_priv, pipe);
0b8765c6 3063
f7abfe8b 3064 intel_crtc->active = false;
6b383a7f
CW		 3065 intel_update_fbc(dev);
3066 intel_update_watermarks(dev);
3067 intel_clear_scanline_wait(dev);
0b8765c6
JB		 3068}
3069
3070static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3071{
3072 /* XXX: When our outputs are all unaware of DPMS modes other than off
3073 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3074 */
3075 switch (mode) {
3076 case DRM_MODE_DPMS_ON:
3077 case DRM_MODE_DPMS_STANDBY:
3078 case DRM_MODE_DPMS_SUSPEND:
3079 i9xx_crtc_enable(crtc);
3080 break;
3081 case DRM_MODE_DPMS_OFF:
3082 i9xx_crtc_disable(crtc);
79e53945
JB		 3083 break;
3084 }
2c07245f
ZW		 3085}
3086
3087/**
3088 * Sets the power management mode of the pipe and plane.
2c07245f
ZW		 3089 */
3090static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3091{
3092 struct drm_device *dev = crtc->dev;
e70236a8 3093 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f
ZW		 3094 struct drm_i915_master_private *master_priv;
3095 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3096 int pipe = intel_crtc->pipe;
3097 bool enabled;
3098
032d2a0d
CW		 3099 if (intel_crtc->dpms_mode == mode)
3100 return;
3101
65655d4a 3102 intel_crtc->dpms_mode = mode;
debcaddc 3103
e70236a8 3104 dev_priv->display.dpms(crtc, mode);
79e53945
JB		 3105
3106 if (!dev->primary->master)
3107 return;
3108
3109 master_priv = dev->primary->master->driver_priv;
3110 if (!master_priv->sarea_priv)
3111 return;
3112
3113 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3114
3115 switch (pipe) {
3116 case 0:
3117 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3118 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3119 break;
3120 case 1:
3121 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3122 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3123 break;
3124 default:
9db4a9c7 3125 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3126 break;
3127 }
79e53945
JB		 3128}
3129
cdd59983
CW		 3130static void intel_crtc_disable(struct drm_crtc *crtc)
3131{
3132 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3133 struct drm_device *dev = crtc->dev;
3134
3135 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3136
3137 if (crtc->fb) {
3138 mutex_lock(&dev->struct_mutex);
3139 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3140 mutex_unlock(&dev->struct_mutex);
3141 }
3142}
3143
7e7d76c3
JB		 3144/* Prepare for a mode set.
3145 *
3146 * Note we could be a lot smarter here. We need to figure out which outputs
3147 * will be enabled, which disabled (in short, how the config will changes)
3148 * and perform the minimum necessary steps to accomplish that, e.g. updating
3149 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3150 * panel fitting is in the proper state, etc.
3151 */
3152static void i9xx_crtc_prepare(struct drm_crtc *crtc)
79e53945 3153{
7e7d76c3 3154 i9xx_crtc_disable(crtc);
79e53945
JB		 3155}
3156
7e7d76c3 3157static void i9xx_crtc_commit(struct drm_crtc *crtc)
79e53945 3158{
7e7d76c3 3159 i9xx_crtc_enable(crtc);
7e7d76c3
JB		 3160}
3161
3162static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3163{
7e7d76c3 3164 ironlake_crtc_disable(crtc);
7e7d76c3
JB		 3165}
3166
3167static void ironlake_crtc_commit(struct drm_crtc *crtc)
3168{
7e7d76c3 3169 ironlake_crtc_enable(crtc);
79e53945
JB		 3170}
3171
3172void intel_encoder_prepare (struct drm_encoder *encoder)
3173{
3174 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3175 /* lvds has its own version of prepare see intel_lvds_prepare */
3176 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3177}
3178
3179void intel_encoder_commit (struct drm_encoder *encoder)
3180{
3181 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3182 /* lvds has its own version of commit see intel_lvds_commit */
3183 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3184}
3185
ea5b213a
CW		 3186void intel_encoder_destroy(struct drm_encoder *encoder)
3187{
4ef69c7a 3188 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3189
ea5b213a
CW		 3190 drm_encoder_cleanup(encoder);
3191 kfree(intel_encoder);
3192}
3193
79e53945
JB		 3194static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3195 struct drm_display_mode *mode,
3196 struct drm_display_mode *adjusted_mode)
3197{
2c07245f 3198 struct drm_device *dev = crtc->dev;
89749350 3199
bad720ff 3200 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3201 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3202 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3203 return false;
2c07245f 3204 }
89749350
CW		 3205
3206 /* XXX some encoders set the crtcinfo, others don't.
3207 * Obviously we need some form of conflict resolution here...
3208 */
3209 if (adjusted_mode->crtc_htotal == 0)
3210 drm_mode_set_crtcinfo(adjusted_mode, 0);
3211
79e53945
JB		 3212 return true;
3213}
3214
e70236a8
JB		 3215static int i945_get_display_clock_speed(struct drm_device *dev)
3216{
3217 return 400000;
3218}
79e53945 3219
e70236a8 3220static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3221{
e70236a8
JB		 3222 return 333000;
3223}
79e53945 3224
e70236a8
JB		 3225static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3226{
3227 return 200000;
3228}
79e53945 3229
e70236a8
JB		 3230static int i915gm_get_display_clock_speed(struct drm_device *dev)
3231{
3232 u16 gcfgc = 0;
79e53945 3233
e70236a8
JB		 3234 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3235
3236 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3237 return 133000;
3238 else {
3239 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3240 case GC_DISPLAY_CLOCK_333_MHZ:
3241 return 333000;
3242 default:
3243 case GC_DISPLAY_CLOCK_190_200_MHZ:
3244 return 190000;
79e53945 3245 }
e70236a8
JB		 3246 }
3247}
3248
3249static int i865_get_display_clock_speed(struct drm_device *dev)
3250{
3251 return 266000;
3252}
3253
3254static int i855_get_display_clock_speed(struct drm_device *dev)
3255{
3256 u16 hpllcc = 0;
3257 /* Assume that the hardware is in the high speed state. This
3258 * should be the default.
3259 */
3260 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3261 case GC_CLOCK_133_200:
3262 case GC_CLOCK_100_200:
3263 return 200000;
3264 case GC_CLOCK_166_250:
3265 return 250000;
3266 case GC_CLOCK_100_133:
79e53945 3267 return 133000;
e70236a8 3268 }
79e53945 3269
e70236a8
JB		 3270 /* Shouldn't happen */
3271 return 0;
3272}
79e53945 3273
e70236a8
JB		 3274static int i830_get_display_clock_speed(struct drm_device *dev)
3275{
3276 return 133000;
79e53945
JB		 3277}
3278
2c07245f
ZW		 3279struct fdi_m_n {
3280 u32 tu;
3281 u32 gmch_m;
3282 u32 gmch_n;
3283 u32 link_m;
3284 u32 link_n;
3285};
3286
3287static void
3288fdi_reduce_ratio(u32 *num, u32 *den)
3289{
3290 while (*num > 0xffffff || *den > 0xffffff) {
3291 *num >>= 1;
3292 *den >>= 1;
3293 }
3294}
3295
2c07245f 3296static void
f2b115e6
AJ		 3297ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3298 int link_clock, struct fdi_m_n *m_n)
2c07245f 3299{
2c07245f
ZW		 3300 m_n->tu = 64; /* default size */
3301
22ed1113
CW		 3302 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3303 m_n->gmch_m = bits_per_pixel * pixel_clock;
3304 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3305 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3306
22ed1113
CW		 3307 m_n->link_m = pixel_clock;
3308 m_n->link_n = link_clock;
2c07245f
ZW		 3309 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3310}
3311
3312
7662c8bd
SL		 3313struct intel_watermark_params {
3314 unsigned long fifo_size;
3315 unsigned long max_wm;
3316 unsigned long default_wm;
3317 unsigned long guard_size;
3318 unsigned long cacheline_size;
3319};
3320
f2b115e6 3321/* Pineview has different values for various configs */
d210246a 3322static const struct intel_watermark_params pineview_display_wm = {
f2b115e6
AJ		 3323 PINEVIEW_DISPLAY_FIFO,
3324 PINEVIEW_MAX_WM,
3325 PINEVIEW_DFT_WM,
3326 PINEVIEW_GUARD_WM,
3327 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3328};
d210246a 3329static const struct intel_watermark_params pineview_display_hplloff_wm = {
f2b115e6
AJ		 3330 PINEVIEW_DISPLAY_FIFO,
3331 PINEVIEW_MAX_WM,
3332 PINEVIEW_DFT_HPLLOFF_WM,
3333 PINEVIEW_GUARD_WM,
3334 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3335};
d210246a 3336static const struct intel_watermark_params pineview_cursor_wm = {
f2b115e6
AJ		 3337 PINEVIEW_CURSOR_FIFO,
3338 PINEVIEW_CURSOR_MAX_WM,
3339 PINEVIEW_CURSOR_DFT_WM,
3340 PINEVIEW_CURSOR_GUARD_WM,
3341 PINEVIEW_FIFO_LINE_SIZE,
7662c8bd 3342};
d210246a 3343static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
f2b115e6
AJ		 3344 PINEVIEW_CURSOR_FIFO,
3345 PINEVIEW_CURSOR_MAX_WM,
3346 PINEVIEW_CURSOR_DFT_WM,
3347 PINEVIEW_CURSOR_GUARD_WM,
3348 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3349};
d210246a 3350static const struct intel_watermark_params g4x_wm_info = {
0e442c60
JB		 3351 G4X_FIFO_SIZE,
3352 G4X_MAX_WM,
3353 G4X_MAX_WM,
3354 2,
3355 G4X_FIFO_LINE_SIZE,
3356};
d210246a 3357static const struct intel_watermark_params g4x_cursor_wm_info = {
4fe5e611
ZY		 3358 I965_CURSOR_FIFO,
3359 I965_CURSOR_MAX_WM,
3360 I965_CURSOR_DFT_WM,
3361 2,
3362 G4X_FIFO_LINE_SIZE,
3363};
d210246a 3364static const struct intel_watermark_params i965_cursor_wm_info = {
4fe5e611
ZY		 3365 I965_CURSOR_FIFO,
3366 I965_CURSOR_MAX_WM,
3367 I965_CURSOR_DFT_WM,
3368 2,
3369 I915_FIFO_LINE_SIZE,
3370};
d210246a 3371static const struct intel_watermark_params i945_wm_info = {
dff33cfc 3372 I945_FIFO_SIZE,
7662c8bd
SL		 3373 I915_MAX_WM,
3374 1,
dff33cfc
JB		 3375 2,
3376 I915_FIFO_LINE_SIZE
7662c8bd 3377};
d210246a 3378static const struct intel_watermark_params i915_wm_info = {
dff33cfc 3379 I915_FIFO_SIZE,
7662c8bd
SL		 3380 I915_MAX_WM,
3381 1,
dff33cfc 3382 2,
7662c8bd
SL		 3383 I915_FIFO_LINE_SIZE
3384};
d210246a 3385static const struct intel_watermark_params i855_wm_info = {
7662c8bd
SL		 3386 I855GM_FIFO_SIZE,
3387 I915_MAX_WM,
3388 1,
dff33cfc 3389 2,
7662c8bd
SL		 3390 I830_FIFO_LINE_SIZE
3391};
d210246a 3392static const struct intel_watermark_params i830_wm_info = {
7662c8bd
SL		 3393 I830_FIFO_SIZE,
3394 I915_MAX_WM,
3395 1,
dff33cfc 3396 2,
7662c8bd
SL		 3397 I830_FIFO_LINE_SIZE
3398};
3399
d210246a 3400static const struct intel_watermark_params ironlake_display_wm_info = {
7f8a8569
ZW		 3401 ILK_DISPLAY_FIFO,
3402 ILK_DISPLAY_MAXWM,
3403 ILK_DISPLAY_DFTWM,
3404 2,
3405 ILK_FIFO_LINE_SIZE
3406};
d210246a 3407static const struct intel_watermark_params ironlake_cursor_wm_info = {
c936f44d
ZY		 3408 ILK_CURSOR_FIFO,
3409 ILK_CURSOR_MAXWM,
3410 ILK_CURSOR_DFTWM,
3411 2,
3412 ILK_FIFO_LINE_SIZE
3413};
d210246a 3414static const struct intel_watermark_params ironlake_display_srwm_info = {
7f8a8569
ZW		 3415 ILK_DISPLAY_SR_FIFO,
3416 ILK_DISPLAY_MAX_SRWM,
3417 ILK_DISPLAY_DFT_SRWM,
3418 2,
3419 ILK_FIFO_LINE_SIZE
3420};
d210246a 3421static const struct intel_watermark_params ironlake_cursor_srwm_info = {
7f8a8569
ZW		 3422 ILK_CURSOR_SR_FIFO,
3423 ILK_CURSOR_MAX_SRWM,
3424 ILK_CURSOR_DFT_SRWM,
3425 2,
3426 ILK_FIFO_LINE_SIZE
3427};
3428
d210246a 3429static const struct intel_watermark_params sandybridge_display_wm_info = {
1398261a
YL		 3430 SNB_DISPLAY_FIFO,
3431 SNB_DISPLAY_MAXWM,
3432 SNB_DISPLAY_DFTWM,
3433 2,
3434 SNB_FIFO_LINE_SIZE
3435};
d210246a 3436static const struct intel_watermark_params sandybridge_cursor_wm_info = {
1398261a
YL		 3437 SNB_CURSOR_FIFO,
3438 SNB_CURSOR_MAXWM,
3439 SNB_CURSOR_DFTWM,
3440 2,
3441 SNB_FIFO_LINE_SIZE
3442};
d210246a 3443static const struct intel_watermark_params sandybridge_display_srwm_info = {
1398261a
YL		 3444 SNB_DISPLAY_SR_FIFO,
3445 SNB_DISPLAY_MAX_SRWM,
3446 SNB_DISPLAY_DFT_SRWM,
3447 2,
3448 SNB_FIFO_LINE_SIZE
3449};
d210246a 3450static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1398261a
YL		 3451 SNB_CURSOR_SR_FIFO,
3452 SNB_CURSOR_MAX_SRWM,
3453 SNB_CURSOR_DFT_SRWM,
3454 2,
3455 SNB_FIFO_LINE_SIZE
3456};
3457
3458
dff33cfc
JB		 3459/**
3460 * intel_calculate_wm - calculate watermark level
3461 * @clock_in_khz: pixel clock
3462 * @wm: chip FIFO params
3463 * @pixel_size: display pixel size
3464 * @latency_ns: memory latency for the platform
3465 *
3466 * Calculate the watermark level (the level at which the display plane will
3467 * start fetching from memory again). Each chip has a different display
3468 * FIFO size and allocation, so the caller needs to figure that out and pass
3469 * in the correct intel_watermark_params structure.
3470 *
3471 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3472 * on the pixel size. When it reaches the watermark level, it'll start
3473 * fetching FIFO line sized based chunks from memory until the FIFO fills
3474 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3475 * will occur, and a display engine hang could result.
3476 */
7662c8bd 3477static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
d210246a
CW		 3478 const struct intel_watermark_params *wm,
3479 int fifo_size,
7662c8bd
SL		 3480 int pixel_size,
3481 unsigned long latency_ns)
3482{
390c4dd4 3483 long entries_required, wm_size;
dff33cfc 3484
d660467c
JB		 3485 /*
3486 * Note: we need to make sure we don't overflow for various clock &
3487 * latency values.
3488 * clocks go from a few thousand to several hundred thousand.
3489 * latency is usually a few thousand
3490 */
3491 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3492 1000;
8de9b311 3493 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
7662c8bd 3494
bbb0aef5 3495 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
dff33cfc 3496
d210246a 3497 wm_size = fifo_size - (entries_required + wm->guard_size);
dff33cfc 3498
bbb0aef5 3499 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
7662c8bd 3500
390c4dd4
JB		 3501 /* Don't promote wm_size to unsigned... */
3502 if (wm_size > (long)wm->max_wm)
7662c8bd 3503 wm_size = wm->max_wm;
c3add4b6 3504 if (wm_size <= 0)
7662c8bd
SL		 3505 wm_size = wm->default_wm;
3506 return wm_size;
3507}
3508
3509struct cxsr_latency {
3510 int is_desktop;
95534263 3511 int is_ddr3;
7662c8bd
SL		 3512 unsigned long fsb_freq;
3513 unsigned long mem_freq;
3514 unsigned long display_sr;
3515 unsigned long display_hpll_disable;
3516 unsigned long cursor_sr;
3517 unsigned long cursor_hpll_disable;
3518};
3519
403c89ff 3520static const struct cxsr_latency cxsr_latency_table[] = {
95534263
LP		 3521 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3522 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3523 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3524 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3525 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3526
3527 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3528 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3529 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3530 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3531 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3532
3533 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3534 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3535 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3536 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3537 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3538
3539 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3540 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3541 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3542 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3543 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3544
3545 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3546 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3547 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3548 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3549 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3550
3551 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3552 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3553 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3554 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3555 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
7662c8bd
SL		 3556};
3557
403c89ff
CW		 3558static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3559 int is_ddr3,
3560 int fsb,
3561 int mem)
7662c8bd 3562{
403c89ff 3563 const struct cxsr_latency *latency;
7662c8bd 3564 int i;
7662c8bd
SL		 3565
3566 if (fsb == 0 || mem == 0)
3567 return NULL;
3568
3569 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3570 latency = &cxsr_latency_table[i];
3571 if (is_desktop == latency->is_desktop &&
95534263 3572 is_ddr3 == latency->is_ddr3 &&
decbbcda
JSR		 3573 fsb == latency->fsb_freq && mem == latency->mem_freq)
3574 return latency;
7662c8bd 3575 }
decbbcda 3576
28c97730 3577 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
decbbcda
JSR		 3578
3579 return NULL;
7662c8bd
SL		 3580}
3581
f2b115e6 3582static void pineview_disable_cxsr(struct drm_device *dev)
7662c8bd
SL		 3583{
3584 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd
SL		 3585
3586 /* deactivate cxsr */
3e33d94d 3587 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
7662c8bd
SL		 3588}
3589
bcc24fb4
JB		 3590/*
3591 * Latency for FIFO fetches is dependent on several factors:
3592 * - memory configuration (speed, channels)
3593 * - chipset
3594 * - current MCH state
3595 * It can be fairly high in some situations, so here we assume a fairly
3596 * pessimal value. It's a tradeoff between extra memory fetches (if we
3597 * set this value too high, the FIFO will fetch frequently to stay full)
3598 * and power consumption (set it too low to save power and we might see
3599 * FIFO underruns and display "flicker").
3600 *
3601 * A value of 5us seems to be a good balance; safe for very low end
3602 * platforms but not overly aggressive on lower latency configs.
3603 */
69e302a9 3604static const int latency_ns = 5000;
7662c8bd 3605
e70236a8 3606static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
dff33cfc
JB		 3607{
3608 struct drm_i915_private *dev_priv = dev->dev_private;
3609 uint32_t dsparb = I915_READ(DSPARB);
3610 int size;
3611
8de9b311
CW		 3612 size = dsparb & 0x7f;
3613 if (plane)
3614 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
dff33cfc 3615
28c97730 3616 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3617 plane ? "B" : "A", size);
dff33cfc
JB		 3618
3619 return size;
3620}
7662c8bd 3621
e70236a8
JB		 3622static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3623{
3624 struct drm_i915_private *dev_priv = dev->dev_private;
3625 uint32_t dsparb = I915_READ(DSPARB);
3626 int size;
3627
8de9b311
CW		 3628 size = dsparb & 0x1ff;
3629 if (plane)
3630 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
e70236a8 3631 size >>= 1; /* Convert to cachelines */
dff33cfc 3632
28c97730 3633 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3634 plane ? "B" : "A", size);
dff33cfc
JB		 3635
3636 return size;
3637}
7662c8bd 3638
e70236a8
JB		 3639static int i845_get_fifo_size(struct drm_device *dev, int plane)
3640{
3641 struct drm_i915_private *dev_priv = dev->dev_private;
3642 uint32_t dsparb = I915_READ(DSPARB);
3643 int size;
3644
3645 size = dsparb & 0x7f;
3646 size >>= 2; /* Convert to cachelines */
3647
28c97730 3648 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b
CW		 3649 plane ? "B" : "A",
3650 size);
e70236a8
JB		 3651
3652 return size;
3653}
3654
3655static int i830_get_fifo_size(struct drm_device *dev, int plane)
3656{
3657 struct drm_i915_private *dev_priv = dev->dev_private;
3658 uint32_t dsparb = I915_READ(DSPARB);
3659 int size;
3660
3661 size = dsparb & 0x7f;
3662 size >>= 1; /* Convert to cachelines */
3663
28c97730 3664 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3665 plane ? "B" : "A", size);
e70236a8
JB		 3666
3667 return size;
3668}
3669
d210246a
CW		 3670static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3671{
3672 struct drm_crtc *crtc, *enabled = NULL;
3673
3674 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3675 if (crtc->enabled && crtc->fb) {
3676 if (enabled)
3677 return NULL;
3678 enabled = crtc;
3679 }
3680 }
3681
3682 return enabled;
3683}
3684
3685static void pineview_update_wm(struct drm_device *dev)
d4294342
ZY		 3686{
3687 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 3688 struct drm_crtc *crtc;
403c89ff 3689 const struct cxsr_latency *latency;
d4294342
ZY		 3690 u32 reg;
3691 unsigned long wm;
d4294342 3692
403c89ff 3693 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
95534263 3694 dev_priv->fsb_freq, dev_priv->mem_freq);
d4294342
ZY		 3695 if (!latency) {
3696 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3697 pineview_disable_cxsr(dev);
3698 return;
3699 }
3700
d210246a
CW		 3701 crtc = single_enabled_crtc(dev);
3702 if (crtc) {
3703 int clock = crtc->mode.clock;
3704 int pixel_size = crtc->fb->bits_per_pixel / 8;
d4294342
ZY		 3705
3706 /* Display SR */
d210246a
CW		 3707 wm = intel_calculate_wm(clock, &pineview_display_wm,
3708 pineview_display_wm.fifo_size,
d4294342
ZY		 3709 pixel_size, latency->display_sr);
3710 reg = I915_READ(DSPFW1);
3711 reg &= ~DSPFW_SR_MASK;
3712 reg |= wm << DSPFW_SR_SHIFT;
3713 I915_WRITE(DSPFW1, reg);
3714 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3715
3716 /* cursor SR */
d210246a
CW		 3717 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3718 pineview_display_wm.fifo_size,
d4294342
ZY		 3719 pixel_size, latency->cursor_sr);
3720 reg = I915_READ(DSPFW3);
3721 reg &= ~DSPFW_CURSOR_SR_MASK;
3722 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3723 I915_WRITE(DSPFW3, reg);
3724
3725 /* Display HPLL off SR */
d210246a
CW		 3726 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3727 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 3728 pixel_size, latency->display_hpll_disable);
3729 reg = I915_READ(DSPFW3);
3730 reg &= ~DSPFW_HPLL_SR_MASK;
3731 reg |= wm & DSPFW_HPLL_SR_MASK;
3732 I915_WRITE(DSPFW3, reg);
3733
3734 /* cursor HPLL off SR */
d210246a
CW		 3735 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3736 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 3737 pixel_size, latency->cursor_hpll_disable);
3738 reg = I915_READ(DSPFW3);
3739 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3740 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3741 I915_WRITE(DSPFW3, reg);
3742 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3743
3744 /* activate cxsr */
3e33d94d
CW		 3745 I915_WRITE(DSPFW3,
3746 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
d4294342
ZY		 3747 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3748 } else {
3749 pineview_disable_cxsr(dev);
3750 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3751 }
3752}
3753
417ae147
CW		 3754static bool g4x_compute_wm0(struct drm_device *dev,
3755 int plane,
3756 const struct intel_watermark_params *display,
3757 int display_latency_ns,
3758 const struct intel_watermark_params *cursor,
3759 int cursor_latency_ns,
3760 int *plane_wm,
3761 int *cursor_wm)
3762{
3763 struct drm_crtc *crtc;
3764 int htotal, hdisplay, clock, pixel_size;
3765 int line_time_us, line_count;
3766 int entries, tlb_miss;
3767
3768 crtc = intel_get_crtc_for_plane(dev, plane);
5c72d064
CW		 3769 if (crtc->fb == NULL || !crtc->enabled) {
3770 *cursor_wm = cursor->guard_size;
3771 *plane_wm = display->guard_size;
417ae147 3772 return false;
5c72d064 3773 }
417ae147
CW		 3774
3775 htotal = crtc->mode.htotal;
3776 hdisplay = crtc->mode.hdisplay;
3777 clock = crtc->mode.clock;
3778 pixel_size = crtc->fb->bits_per_pixel / 8;
3779
3780 /* Use the small buffer method to calculate plane watermark */
3781 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3782 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3783 if (tlb_miss > 0)
3784 entries += tlb_miss;
3785 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3786 *plane_wm = entries + display->guard_size;
3787 if (*plane_wm > (int)display->max_wm)
3788 *plane_wm = display->max_wm;
3789
3790 /* Use the large buffer method to calculate cursor watermark */
3791 line_time_us = ((htotal * 1000) / clock);
3792 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3793 entries = line_count * 64 * pixel_size;
3794 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3795 if (tlb_miss > 0)
3796 entries += tlb_miss;
3797 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3798 *cursor_wm = entries + cursor->guard_size;
3799 if (*cursor_wm > (int)cursor->max_wm)
3800 *cursor_wm = (int)cursor->max_wm;
3801
3802 return true;
3803}
3804
3805/*
3806 * Check the wm result.
3807 *
3808 * If any calculated watermark values is larger than the maximum value that
3809 * can be programmed into the associated watermark register, that watermark
3810 * must be disabled.
3811 */
3812static bool g4x_check_srwm(struct drm_device *dev,
3813 int display_wm, int cursor_wm,
3814 const struct intel_watermark_params *display,
3815 const struct intel_watermark_params *cursor)
652c393a 3816{
417ae147
CW		 3817 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
3818 display_wm, cursor_wm);
652c393a 3819
417ae147 3820 if (display_wm > display->max_wm) {
bbb0aef5 3821 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
417ae147
CW		 3822 display_wm, display->max_wm);
3823 return false;
3824 }
0e442c60 3825
417ae147 3826 if (cursor_wm > cursor->max_wm) {
bbb0aef5 3827 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
417ae147
CW		 3828 cursor_wm, cursor->max_wm);
3829 return false;
3830 }
0e442c60 3831
417ae147
CW		 3832 if (!(display_wm || cursor_wm)) {
3833 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
3834 return false;
3835 }
0e442c60 3836
417ae147
CW		 3837 return true;
3838}
0e442c60 3839
417ae147 3840static bool g4x_compute_srwm(struct drm_device *dev,
d210246a
CW		 3841 int plane,
3842 int latency_ns,
417ae147
CW		 3843 const struct intel_watermark_params *display,
3844 const struct intel_watermark_params *cursor,
3845 int *display_wm, int *cursor_wm)
3846{
d210246a
CW		 3847 struct drm_crtc *crtc;
3848 int hdisplay, htotal, pixel_size, clock;
417ae147
CW		 3849 unsigned long line_time_us;
3850 int line_count, line_size;
3851 int small, large;
3852 int entries;
0e442c60 3853
417ae147
CW		 3854 if (!latency_ns) {
3855 *display_wm = *cursor_wm = 0;
3856 return false;
3857 }
0e442c60 3858
d210246a
CW		 3859 crtc = intel_get_crtc_for_plane(dev, plane);
3860 hdisplay = crtc->mode.hdisplay;
3861 htotal = crtc->mode.htotal;
3862 clock = crtc->mode.clock;
3863 pixel_size = crtc->fb->bits_per_pixel / 8;
3864
417ae147
CW		 3865 line_time_us = (htotal * 1000) / clock;
3866 line_count = (latency_ns / line_time_us + 1000) / 1000;
3867 line_size = hdisplay * pixel_size;
0e442c60 3868
417ae147
CW		 3869 /* Use the minimum of the small and large buffer method for primary */
3870 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3871 large = line_count * line_size;
0e442c60 3872
417ae147
CW		 3873 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3874 *display_wm = entries + display->guard_size;
4fe5e611 3875
417ae147
CW		 3876 /* calculate the self-refresh watermark for display cursor */
3877 entries = line_count * pixel_size * 64;
3878 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3879 *cursor_wm = entries + cursor->guard_size;
4fe5e611 3880
417ae147
CW		 3881 return g4x_check_srwm(dev,
3882 *display_wm, *cursor_wm,
3883 display, cursor);
3884}
4fe5e611 3885
7ccb4a53 3886#define single_plane_enabled(mask) is_power_of_2(mask)
d210246a
CW		 3887
3888static void g4x_update_wm(struct drm_device *dev)
417ae147
CW		 3889{
3890 static const int sr_latency_ns = 12000;
3891 struct drm_i915_private *dev_priv = dev->dev_private;
3892 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
d210246a
CW		 3893 int plane_sr, cursor_sr;
3894 unsigned int enabled = 0;
417ae147
CW		 3895
3896 if (g4x_compute_wm0(dev, 0,
3897 &g4x_wm_info, latency_ns,
3898 &g4x_cursor_wm_info, latency_ns,
3899 &planea_wm, &cursora_wm))
d210246a 3900 enabled |= 1;
417ae147
CW		 3901
3902 if (g4x_compute_wm0(dev, 1,
3903 &g4x_wm_info, latency_ns,
3904 &g4x_cursor_wm_info, latency_ns,
3905 &planeb_wm, &cursorb_wm))
d210246a 3906 enabled |= 2;
417ae147
CW		 3907
3908 plane_sr = cursor_sr = 0;
d210246a
CW		 3909 if (single_plane_enabled(enabled) &&
3910 g4x_compute_srwm(dev, ffs(enabled) - 1,
3911 sr_latency_ns,
417ae147
CW		 3912 &g4x_wm_info,
3913 &g4x_cursor_wm_info,
3914 &plane_sr, &cursor_sr))
0e442c60 3915 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
417ae147
CW		 3916 else
3917 I915_WRITE(FW_BLC_SELF,
3918 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
0e442c60 3919
308977ac
CW		 3920 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
3921 planea_wm, cursora_wm,
3922 planeb_wm, cursorb_wm,
3923 plane_sr, cursor_sr);
0e442c60 3924
417ae147
CW		 3925 I915_WRITE(DSPFW1,
3926 (plane_sr << DSPFW_SR_SHIFT) |
0e442c60 3927 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
417ae147
CW		 3928 (planeb_wm << DSPFW_PLANEB_SHIFT) |
3929 planea_wm);
3930 I915_WRITE(DSPFW2,
3931 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
0e442c60
JB		 3932 (cursora_wm << DSPFW_CURSORA_SHIFT));
3933 /* HPLL off in SR has some issues on G4x... disable it */
417ae147
CW		 3934 I915_WRITE(DSPFW3,
3935 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
0e442c60 3936 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
652c393a
JB		 3937}
3938
d210246a 3939static void i965_update_wm(struct drm_device *dev)
7662c8bd
SL		 3940{
3941 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 3942 struct drm_crtc *crtc;
3943 int srwm = 1;
4fe5e611 3944 int cursor_sr = 16;
1dc7546d
JB		 3945
3946 /* Calc sr entries for one plane configs */
d210246a
CW		 3947 crtc = single_enabled_crtc(dev);
3948 if (crtc) {
1dc7546d 3949 /* self-refresh has much higher latency */
69e302a9 3950 static const int sr_latency_ns = 12000;
d210246a
CW		 3951 int clock = crtc->mode.clock;
3952 int htotal = crtc->mode.htotal;
3953 int hdisplay = crtc->mode.hdisplay;
3954 int pixel_size = crtc->fb->bits_per_pixel / 8;
3955 unsigned long line_time_us;
3956 int entries;
1dc7546d 3957
d210246a 3958 line_time_us = ((htotal * 1000) / clock);
1dc7546d
JB		 3959
3960 /* Use ns/us then divide to preserve precision */
d210246a
CW		 3961 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3962 pixel_size * hdisplay;
3963 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
d210246a 3964 srwm = I965_FIFO_SIZE - entries;
1dc7546d
JB		 3965 if (srwm < 0)
3966 srwm = 1;
1b07e04e 3967 srwm &= 0x1ff;
308977ac
CW		 3968 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
3969 entries, srwm);
4fe5e611 3970
d210246a 3971 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
5eddb70b 3972 pixel_size * 64;
d210246a 3973 entries = DIV_ROUND_UP(entries,
8de9b311 3974 i965_cursor_wm_info.cacheline_size);
4fe5e611 3975 cursor_sr = i965_cursor_wm_info.fifo_size -
d210246a 3976 (entries + i965_cursor_wm_info.guard_size);
4fe5e611
ZY		 3977
3978 if (cursor_sr > i965_cursor_wm_info.max_wm)
3979 cursor_sr = i965_cursor_wm_info.max_wm;
3980
3981 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3982 "cursor %d\n", srwm, cursor_sr);
3983
a6c45cf0 3984 if (IS_CRESTLINE(dev))
adcdbc66 3985 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
33c5fd12
DJ		 3986 } else {
3987 /* Turn off self refresh if both pipes are enabled */
a6c45cf0 3988 if (IS_CRESTLINE(dev))
adcdbc66
JB		 3989 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3990 & ~FW_BLC_SELF_EN);
1dc7546d 3991 }
7662c8bd 3992
1dc7546d
JB		 3993 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3994 srwm);
7662c8bd
SL		 3995
3996 /* 965 has limitations... */
417ae147
CW		 3997 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
3998 (8 << 16) | (8 << 8) | (8 << 0));
7662c8bd 3999 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4fe5e611
ZY		 4000 /* update cursor SR watermark */
4001 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
7662c8bd
SL		 4002}
4003
d210246a 4004static void i9xx_update_wm(struct drm_device *dev)
7662c8bd
SL		 4005{
4006 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 4007 const struct intel_watermark_params *wm_info;
dff33cfc
JB		 4008 uint32_t fwater_lo;
4009 uint32_t fwater_hi;
d210246a
CW		 4010 int cwm, srwm = 1;
4011 int fifo_size;
dff33cfc 4012 int planea_wm, planeb_wm;
d210246a 4013 struct drm_crtc *crtc, *enabled = NULL;
7662c8bd 4014
72557b4f 4015 if (IS_I945GM(dev))
d210246a 4016 wm_info = &i945_wm_info;
a6c45cf0 4017 else if (!IS_GEN2(dev))
d210246a 4018 wm_info = &i915_wm_info;
7662c8bd 4019 else
d210246a
CW		 4020 wm_info = &i855_wm_info;
4021
4022 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4023 crtc = intel_get_crtc_for_plane(dev, 0);
4024 if (crtc->enabled && crtc->fb) {
4025 planea_wm = intel_calculate_wm(crtc->mode.clock,
4026 wm_info, fifo_size,
4027 crtc->fb->bits_per_pixel / 8,
4028 latency_ns);
4029 enabled = crtc;
4030 } else
4031 planea_wm = fifo_size - wm_info->guard_size;
4032
4033 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4034 crtc = intel_get_crtc_for_plane(dev, 1);
4035 if (crtc->enabled && crtc->fb) {
4036 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4037 wm_info, fifo_size,
4038 crtc->fb->bits_per_pixel / 8,
4039 latency_ns);
4040 if (enabled == NULL)
4041 enabled = crtc;
4042 else
4043 enabled = NULL;
4044 } else
4045 planeb_wm = fifo_size - wm_info->guard_size;
7662c8bd 4046
28c97730 4047 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
7662c8bd
SL		 4048
4049 /*
4050 * Overlay gets an aggressive default since video jitter is bad.
4051 */
4052 cwm = 2;
4053
18b2190c
AL		 4054 /* Play safe and disable self-refresh before adjusting watermarks. */
4055 if (IS_I945G(dev) || IS_I945GM(dev))
4056 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4057 else if (IS_I915GM(dev))
4058 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4059
dff33cfc 4060 /* Calc sr entries for one plane configs */
d210246a 4061 if (HAS_FW_BLC(dev) && enabled) {
dff33cfc 4062 /* self-refresh has much higher latency */
69e302a9 4063 static const int sr_latency_ns = 6000;
d210246a
CW		 4064 int clock = enabled->mode.clock;
4065 int htotal = enabled->mode.htotal;
4066 int hdisplay = enabled->mode.hdisplay;
4067 int pixel_size = enabled->fb->bits_per_pixel / 8;
4068 unsigned long line_time_us;
4069 int entries;
dff33cfc 4070
d210246a 4071 line_time_us = (htotal * 1000) / clock;
dff33cfc
JB		 4072
4073 /* Use ns/us then divide to preserve precision */
d210246a
CW		 4074 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4075 pixel_size * hdisplay;
4076 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4077 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4078 srwm = wm_info->fifo_size - entries;
dff33cfc
JB		 4079 if (srwm < 0)
4080 srwm = 1;
ee980b80
LP		 4081
4082 if (IS_I945G(dev) || IS_I945GM(dev))
18b2190c
AL		 4083 I915_WRITE(FW_BLC_SELF,
4084 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4085 else if (IS_I915GM(dev))
ee980b80 4086 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
7662c8bd
SL		 4087 }
4088
28c97730 4089 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
5eddb70b 4090 planea_wm, planeb_wm, cwm, srwm);
7662c8bd 4091
dff33cfc
JB		 4092 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4093 fwater_hi = (cwm & 0x1f);
4094
4095 /* Set request length to 8 cachelines per fetch */
4096 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4097 fwater_hi = fwater_hi | (1 << 8);
7662c8bd
SL		 4098
4099 I915_WRITE(FW_BLC, fwater_lo);
4100 I915_WRITE(FW_BLC2, fwater_hi);
18b2190c 4101
d210246a
CW		 4102 if (HAS_FW_BLC(dev)) {
4103 if (enabled) {
4104 if (IS_I945G(dev) || IS_I945GM(dev))
4105 I915_WRITE(FW_BLC_SELF,
4106 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4107 else if (IS_I915GM(dev))
4108 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4109 DRM_DEBUG_KMS("memory self refresh enabled\n");
4110 } else
4111 DRM_DEBUG_KMS("memory self refresh disabled\n");
4112 }
7662c8bd
SL		 4113}
4114
d210246a 4115static void i830_update_wm(struct drm_device *dev)
7662c8bd
SL		 4116{
4117 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4118 struct drm_crtc *crtc;
4119 uint32_t fwater_lo;
dff33cfc 4120 int planea_wm;
7662c8bd 4121
d210246a
CW		 4122 crtc = single_enabled_crtc(dev);
4123 if (crtc == NULL)
4124 return;
7662c8bd 4125
d210246a
CW		 4126 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4127 dev_priv->display.get_fifo_size(dev, 0),
4128 crtc->fb->bits_per_pixel / 8,
4129 latency_ns);
4130 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
f3601326
JB		 4131 fwater_lo |= (3<<8) | planea_wm;
4132
28c97730 4133 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
7662c8bd
SL		 4134
4135 I915_WRITE(FW_BLC, fwater_lo);
4136}
4137
7f8a8569 4138#define ILK_LP0_PLANE_LATENCY 700
c936f44d 4139#define ILK_LP0_CURSOR_LATENCY 1300
7f8a8569 4140
1398261a
YL		 4141/*
4142 * Check the wm result.
4143 *
4144 * If any calculated watermark values is larger than the maximum value that
4145 * can be programmed into the associated watermark register, that watermark
4146 * must be disabled.
1398261a 4147 */
b79d4990
JB		 4148static bool ironlake_check_srwm(struct drm_device *dev, int level,
4149 int fbc_wm, int display_wm, int cursor_wm,
4150 const struct intel_watermark_params *display,
4151 const struct intel_watermark_params *cursor)
1398261a
YL		 4152{
4153 struct drm_i915_private *dev_priv = dev->dev_private;
4154
4155 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4156 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4157
4158 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4159 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4160 fbc_wm, SNB_FBC_MAX_SRWM, level);
1398261a
YL		 4161
4162 /* fbc has it's own way to disable FBC WM */
4163 I915_WRITE(DISP_ARB_CTL,
4164 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4165 return false;
4166 }
4167
b79d4990 4168 if (display_wm > display->max_wm) {
1398261a 4169 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4170 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1398261a
YL		 4171 return false;
4172 }
4173
b79d4990 4174 if (cursor_wm > cursor->max_wm) {
1398261a 4175 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4176 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1398261a
YL		 4177 return false;
4178 }
4179
4180 if (!(fbc_wm || display_wm || cursor_wm)) {
4181 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4182 return false;
4183 }
4184
4185 return true;
4186}
4187
4188/*
4189 * Compute watermark values of WM[1-3],
4190 */
d210246a
CW		 4191static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4192 int latency_ns,
b79d4990
JB		 4193 const struct intel_watermark_params *display,
4194 const struct intel_watermark_params *cursor,
4195 int *fbc_wm, int *display_wm, int *cursor_wm)
1398261a 4196{
d210246a 4197 struct drm_crtc *crtc;
1398261a 4198 unsigned long line_time_us;
d210246a 4199 int hdisplay, htotal, pixel_size, clock;
b79d4990 4200 int line_count, line_size;
1398261a
YL		 4201 int small, large;
4202 int entries;
1398261a
YL		 4203
4204 if (!latency_ns) {
4205 *fbc_wm = *display_wm = *cursor_wm = 0;
4206 return false;
4207 }
4208
d210246a
CW		 4209 crtc = intel_get_crtc_for_plane(dev, plane);
4210 hdisplay = crtc->mode.hdisplay;
4211 htotal = crtc->mode.htotal;
4212 clock = crtc->mode.clock;
4213 pixel_size = crtc->fb->bits_per_pixel / 8;
4214
1398261a
YL		 4215 line_time_us = (htotal * 1000) / clock;
4216 line_count = (latency_ns / line_time_us + 1000) / 1000;
4217 line_size = hdisplay * pixel_size;
4218
4219 /* Use the minimum of the small and large buffer method for primary */
4220 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4221 large = line_count * line_size;
4222
b79d4990
JB		 4223 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4224 *display_wm = entries + display->guard_size;
1398261a
YL		 4225
4226 /*
b79d4990 4227 * Spec says:
1398261a
YL		 4228 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4229 */
4230 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4231
4232 /* calculate the self-refresh watermark for display cursor */
4233 entries = line_count * pixel_size * 64;
b79d4990
JB		 4234 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4235 *cursor_wm = entries + cursor->guard_size;
1398261a 4236
b79d4990
JB		 4237 return ironlake_check_srwm(dev, level,
4238 *fbc_wm, *display_wm, *cursor_wm,
4239 display, cursor);
4240}
4241
d210246a 4242static void ironlake_update_wm(struct drm_device *dev)
b79d4990
JB		 4243{
4244 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4245 int fbc_wm, plane_wm, cursor_wm;
4246 unsigned int enabled;
b79d4990
JB		 4247
4248 enabled = 0;
9f405100
CW		 4249 if (g4x_compute_wm0(dev, 0,
4250 &ironlake_display_wm_info,
4251 ILK_LP0_PLANE_LATENCY,
4252 &ironlake_cursor_wm_info,
4253 ILK_LP0_CURSOR_LATENCY,
4254 &plane_wm, &cursor_wm)) {
b79d4990
JB		 4255 I915_WRITE(WM0_PIPEA_ILK,
4256 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4257 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4258 " plane %d, " "cursor: %d\n",
4259 plane_wm, cursor_wm);
d210246a 4260 enabled |= 1;
b79d4990
JB		 4261 }
4262
9f405100
CW		 4263 if (g4x_compute_wm0(dev, 1,
4264 &ironlake_display_wm_info,
4265 ILK_LP0_PLANE_LATENCY,
4266 &ironlake_cursor_wm_info,
4267 ILK_LP0_CURSOR_LATENCY,
4268 &plane_wm, &cursor_wm)) {
b79d4990
JB		 4269 I915_WRITE(WM0_PIPEB_ILK,
4270 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4271 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4272 " plane %d, cursor: %d\n",
4273 plane_wm, cursor_wm);
d210246a 4274 enabled |= 2;
b79d4990
JB		 4275 }
4276
4277 /*
4278 * Calculate and update the self-refresh watermark only when one
4279 * display plane is used.
4280 */
4281 I915_WRITE(WM3_LP_ILK, 0);
4282 I915_WRITE(WM2_LP_ILK, 0);
4283 I915_WRITE(WM1_LP_ILK, 0);
4284
d210246a 4285 if (!single_plane_enabled(enabled))
b79d4990 4286 return;
d210246a 4287 enabled = ffs(enabled) - 1;
b79d4990
JB		 4288
4289 /* WM1 */
d210246a
CW		 4290 if (!ironlake_compute_srwm(dev, 1, enabled,
4291 ILK_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4292 &ironlake_display_srwm_info,
4293 &ironlake_cursor_srwm_info,
4294 &fbc_wm, &plane_wm, &cursor_wm))
4295 return;
4296
4297 I915_WRITE(WM1_LP_ILK,
4298 WM1_LP_SR_EN |
4299 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4300 (fbc_wm << WM1_LP_FBC_SHIFT) |
4301 (plane_wm << WM1_LP_SR_SHIFT) |
4302 cursor_wm);
4303
4304 /* WM2 */
d210246a
CW		 4305 if (!ironlake_compute_srwm(dev, 2, enabled,
4306 ILK_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4307 &ironlake_display_srwm_info,
4308 &ironlake_cursor_srwm_info,
4309 &fbc_wm, &plane_wm, &cursor_wm))
4310 return;
4311
4312 I915_WRITE(WM2_LP_ILK,
4313 WM2_LP_EN |
4314 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4315 (fbc_wm << WM1_LP_FBC_SHIFT) |
4316 (plane_wm << WM1_LP_SR_SHIFT) |
4317 cursor_wm);
4318
4319 /*
4320 * WM3 is unsupported on ILK, probably because we don't have latency
4321 * data for that power state
4322 */
1398261a
YL		 4323}
4324
d210246a 4325static void sandybridge_update_wm(struct drm_device *dev)
1398261a
YL		 4326{
4327 struct drm_i915_private *dev_priv = dev->dev_private;
a0fa62d3 4328 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
d210246a
CW		 4329 int fbc_wm, plane_wm, cursor_wm;
4330 unsigned int enabled;
1398261a
YL		 4331
4332 enabled = 0;
9f405100
CW		 4333 if (g4x_compute_wm0(dev, 0,
4334 &sandybridge_display_wm_info, latency,
4335 &sandybridge_cursor_wm_info, latency,
4336 &plane_wm, &cursor_wm)) {
1398261a
YL		 4337 I915_WRITE(WM0_PIPEA_ILK,
4338 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4339 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4340 " plane %d, " "cursor: %d\n",
4341 plane_wm, cursor_wm);
d210246a 4342 enabled |= 1;
1398261a
YL		 4343 }
4344
9f405100
CW		 4345 if (g4x_compute_wm0(dev, 1,
4346 &sandybridge_display_wm_info, latency,
4347 &sandybridge_cursor_wm_info, latency,
4348 &plane_wm, &cursor_wm)) {
1398261a
YL		 4349 I915_WRITE(WM0_PIPEB_ILK,
4350 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4351 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4352 " plane %d, cursor: %d\n",
4353 plane_wm, cursor_wm);
d210246a 4354 enabled |= 2;
1398261a
YL		 4355 }
4356
4357 /*
4358 * Calculate and update the self-refresh watermark only when one
4359 * display plane is used.
4360 *
4361 * SNB support 3 levels of watermark.
4362 *
4363 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4364 * and disabled in the descending order
4365 *
4366 */
4367 I915_WRITE(WM3_LP_ILK, 0);
4368 I915_WRITE(WM2_LP_ILK, 0);
4369 I915_WRITE(WM1_LP_ILK, 0);
4370
d210246a 4371 if (!single_plane_enabled(enabled))
1398261a 4372 return;
d210246a 4373 enabled = ffs(enabled) - 1;
1398261a
YL		 4374
4375 /* WM1 */
d210246a
CW		 4376 if (!ironlake_compute_srwm(dev, 1, enabled,
4377 SNB_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4378 &sandybridge_display_srwm_info,
4379 &sandybridge_cursor_srwm_info,
4380 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4381 return;
4382
4383 I915_WRITE(WM1_LP_ILK,
4384 WM1_LP_SR_EN |
4385 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4386 (fbc_wm << WM1_LP_FBC_SHIFT) |
4387 (plane_wm << WM1_LP_SR_SHIFT) |
4388 cursor_wm);
4389
4390 /* WM2 */
d210246a
CW		 4391 if (!ironlake_compute_srwm(dev, 2, enabled,
4392 SNB_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4393 &sandybridge_display_srwm_info,
4394 &sandybridge_cursor_srwm_info,
4395 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4396 return;
4397
4398 I915_WRITE(WM2_LP_ILK,
4399 WM2_LP_EN |
4400 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4401 (fbc_wm << WM1_LP_FBC_SHIFT) |
4402 (plane_wm << WM1_LP_SR_SHIFT) |
4403 cursor_wm);
4404
4405 /* WM3 */
d210246a
CW		 4406 if (!ironlake_compute_srwm(dev, 3, enabled,
4407 SNB_READ_WM3_LATENCY() * 500,
b79d4990
JB		 4408 &sandybridge_display_srwm_info,
4409 &sandybridge_cursor_srwm_info,
4410 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4411 return;
4412
4413 I915_WRITE(WM3_LP_ILK,
4414 WM3_LP_EN |
4415 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4416 (fbc_wm << WM1_LP_FBC_SHIFT) |
4417 (plane_wm << WM1_LP_SR_SHIFT) |
4418 cursor_wm);
4419}
4420
7662c8bd
SL		 4421/**
4422 * intel_update_watermarks - update FIFO watermark values based on current modes
4423 *
4424 * Calculate watermark values for the various WM regs based on current mode
4425 * and plane configuration.
4426 *
4427 * There are several cases to deal with here:
4428 * - normal (i.e. non-self-refresh)
4429 * - self-refresh (SR) mode
4430 * - lines are large relative to FIFO size (buffer can hold up to 2)
4431 * - lines are small relative to FIFO size (buffer can hold more than 2
4432 * lines), so need to account for TLB latency
4433 *
4434 * The normal calculation is:
4435 * watermark = dotclock * bytes per pixel * latency
4436 * where latency is platform & configuration dependent (we assume pessimal
4437 * values here).
4438 *
4439 * The SR calculation is:
4440 * watermark = (trunc(latency/line time)+1) * surface width *
4441 * bytes per pixel
4442 * where
4443 * line time = htotal / dotclock
fa143215 4444 * surface width = hdisplay for normal plane and 64 for cursor
7662c8bd
SL		 4445 * and latency is assumed to be high, as above.
4446 *
4447 * The final value programmed to the register should always be rounded up,
4448 * and include an extra 2 entries to account for clock crossings.
4449 *
4450 * We don't use the sprite, so we can ignore that. And on Crestline we have
4451 * to set the non-SR watermarks to 8.
5eddb70b 4452 */
7662c8bd
SL		 4453static void intel_update_watermarks(struct drm_device *dev)
4454{
e70236a8 4455 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd 4456
d210246a
CW		 4457 if (dev_priv->display.update_wm)
4458 dev_priv->display.update_wm(dev);
7662c8bd
SL		 4459}
4460
a7615030
CW		 4461static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4462{
4463 return dev_priv->lvds_use_ssc && i915_panel_use_ssc;
4464}
4465
5a354204
JB		 4466/**
4467 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4468 * @crtc: CRTC structure
4469 *
4470 * A pipe may be connected to one or more outputs. Based on the depth of the
4471 * attached framebuffer, choose a good color depth to use on the pipe.
4472 *
4473 * If possible, match the pipe depth to the fb depth. In some cases, this
4474 * isn't ideal, because the connected output supports a lesser or restricted
4475 * set of depths. Resolve that here:
4476 * LVDS typically supports only 6bpc, so clamp down in that case
4477 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4478 * Displays may support a restricted set as well, check EDID and clamp as
4479 * appropriate.
4480 *
4481 * RETURNS:
4482 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4483 * true if they don't match).
4484 */
4485static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4486 unsigned int *pipe_bpp)
4487{
4488 struct drm_device *dev = crtc->dev;
4489 struct drm_i915_private *dev_priv = dev->dev_private;
4490 struct drm_encoder *encoder;
4491 struct drm_connector *connector;
4492 unsigned int display_bpc = UINT_MAX, bpc;
4493
4494 /* Walk the encoders & connectors on this crtc, get min bpc */
4495 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4496 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4497
4498 if (encoder->crtc != crtc)
4499 continue;
4500
4501 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4502 unsigned int lvds_bpc;
4503
4504 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4505 LVDS_A3_POWER_UP)
4506 lvds_bpc = 8;
4507 else
4508 lvds_bpc = 6;
4509
4510 if (lvds_bpc < display_bpc) {
4511 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4512 display_bpc = lvds_bpc;
4513 }
4514 continue;
4515 }
4516
4517 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4518 /* Use VBT settings if we have an eDP panel */
4519 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4520
4521 if (edp_bpc < display_bpc) {
4522 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4523 display_bpc = edp_bpc;
4524 }
4525 continue;
4526 }
4527
4528 /* Not one of the known troublemakers, check the EDID */
4529 list_for_each_entry(connector, &dev->mode_config.connector_list,
4530 head) {
4531 if (connector->encoder != encoder)
4532 continue;
4533
4534 if (connector->display_info.bpc < display_bpc) {
4535 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4536 display_bpc = connector->display_info.bpc;
4537 }
4538 }
4539
4540 /*
4541 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4542 * through, clamp it down. (Note: >12bpc will be caught below.)
4543 */
4544 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4545 if (display_bpc > 8 && display_bpc < 12) {
4546 DRM_DEBUG_DRIVER("forcing bpc to 12 for HDMI\n");
4547 display_bpc = 12;
4548 } else {
4549 DRM_DEBUG_DRIVER("forcing bpc to 8 for HDMI\n");
4550 display_bpc = 8;
4551 }
4552 }
4553 }
4554
4555 /*
4556 * We could just drive the pipe at the highest bpc all the time and
4557 * enable dithering as needed, but that costs bandwidth. So choose
4558 * the minimum value that expresses the full color range of the fb but
4559 * also stays within the max display bpc discovered above.
4560 */
4561
4562 switch (crtc->fb->depth) {
4563 case 8:
4564 bpc = 8; /* since we go through a colormap */
4565 break;
4566 case 15:
4567 case 16:
4568 bpc = 6; /* min is 18bpp */
4569 break;
4570 case 24:
4571 bpc = min((unsigned int)8, display_bpc);
4572 break;
4573 case 30:
4574 bpc = min((unsigned int)10, display_bpc);
4575 break;
4576 case 48:
4577 bpc = min((unsigned int)12, display_bpc);
4578 break;
4579 default:
4580 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4581 bpc = min((unsigned int)8, display_bpc);
4582 break;
4583 }
4584
4585 DRM_DEBUG_DRIVER("setting pipe bpc to %d (max display bpc %d)\n",
4586 bpc, display_bpc);
4587
4588 *pipe_bpp = bpc * 3;
4589
4590 return display_bpc != bpc;
4591}
4592
f564048e
EA		 4593static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4594 struct drm_display_mode *mode,
4595 struct drm_display_mode *adjusted_mode,
4596 int x, int y,
4597 struct drm_framebuffer *old_fb)
79e53945
JB		 4598{
4599 struct drm_device *dev = crtc->dev;
4600 struct drm_i915_private *dev_priv = dev->dev_private;
4601 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4602 int pipe = intel_crtc->pipe;
80824003 4603 int plane = intel_crtc->plane;
c751ce4f 4604 int refclk, num_connectors = 0;
652c393a 4605 intel_clock_t clock, reduced_clock;
5eddb70b 4606 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
652c393a 4607 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
a4fc5ed6 4608 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
79e53945 4609 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 4610 struct intel_encoder *encoder;
d4906093 4611 const intel_limit_t *limit;
5c3b82e2 4612 int ret;
fae14981 4613 u32 temp;
aa9b500d 4614 u32 lvds_sync = 0;
79e53945 4615
5eddb70b
CW		 4616 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4617 if (encoder->base.crtc != crtc)
79e53945
JB		 4618 continue;
4619
5eddb70b 4620 switch (encoder->type) {
79e53945
JB		 4621 case INTEL_OUTPUT_LVDS:
4622 is_lvds = true;
4623 break;
4624 case INTEL_OUTPUT_SDVO:
7d57382e 4625 case INTEL_OUTPUT_HDMI:
79e53945 4626 is_sdvo = true;
5eddb70b 4627 if (encoder->needs_tv_clock)
e2f0ba97 4628 is_tv = true;
79e53945
JB		 4629 break;
4630 case INTEL_OUTPUT_DVO:
4631 is_dvo = true;
4632 break;
4633 case INTEL_OUTPUT_TVOUT:
4634 is_tv = true;
4635 break;
4636 case INTEL_OUTPUT_ANALOG:
4637 is_crt = true;
4638 break;
a4fc5ed6
KP		 4639 case INTEL_OUTPUT_DISPLAYPORT:
4640 is_dp = true;
4641 break;
79e53945 4642 }
43565a06 4643
c751ce4f 4644 num_connectors++;
79e53945
JB		 4645 }
4646
a7615030 4647 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
43565a06 4648 refclk = dev_priv->lvds_ssc_freq * 1000;
28c97730 4649 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5eddb70b 4650 refclk / 1000);
a6c45cf0 4651 } else if (!IS_GEN2(dev)) {
79e53945
JB		 4652 refclk = 96000;
4653 } else {
4654 refclk = 48000;
4655 }
4656
d4906093
ML		 4657 /*
4658 * Returns a set of divisors for the desired target clock with the given
4659 * refclk, or FALSE. The returned values represent the clock equation:
4660 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4661 */
1b894b59 4662 limit = intel_limit(crtc, refclk);
d4906093 4663 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
79e53945
JB		 4664 if (!ok) {
4665 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4666 return -EINVAL;
79e53945
JB		 4667 }
4668
cda4b7d3 4669 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4670 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4671
ddc9003c
ZY		 4672 if (is_lvds && dev_priv->lvds_downclock_avail) {
4673 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4674 dev_priv->lvds_downclock,
4675 refclk,
4676 &reduced_clock);
18f9ed12
ZY		 4677 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4678 /*
4679 * If the different P is found, it means that we can't
4680 * switch the display clock by using the FP0/FP1.
4681 * In such case we will disable the LVDS downclock
4682 * feature.
4683 */
4684 DRM_DEBUG_KMS("Different P is found for "
5eddb70b 4685 "LVDS clock/downclock\n");
18f9ed12
ZY		 4686 has_reduced_clock = 0;
4687 }
652c393a 4688 }
7026d4ac
ZW		 4689 /* SDVO TV has fixed PLL values depend on its clock range,
4690 this mirrors vbios setting. */
4691 if (is_sdvo && is_tv) {
4692 if (adjusted_mode->clock >= 100000
5eddb70b 4693 && adjusted_mode->clock < 140500) {
7026d4ac
ZW		 4694 clock.p1 = 2;
4695 clock.p2 = 10;
4696 clock.n = 3;
4697 clock.m1 = 16;
4698 clock.m2 = 8;
4699 } else if (adjusted_mode->clock >= 140500
5eddb70b 4700 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW		 4701 clock.p1 = 1;
4702 clock.p2 = 10;
4703 clock.n = 6;
4704 clock.m1 = 12;
4705 clock.m2 = 8;
4706 }
4707 }
4708
f2b115e6 4709 if (IS_PINEVIEW(dev)) {
2177832f 4710 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
652c393a
JB		 4711 if (has_reduced_clock)
4712 fp2 = (1 << reduced_clock.n) << 16 |
4713 reduced_clock.m1 << 8 | reduced_clock.m2;
4714 } else {
2177832f 4715 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
652c393a
JB		 4716 if (has_reduced_clock)
4717 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4718 reduced_clock.m2;
4719 }
79e53945 4720
929c77fb 4721 dpll = DPLL_VGA_MODE_DIS;
2c07245f 4722
a6c45cf0 4723 if (!IS_GEN2(dev)) {
79e53945
JB		 4724 if (is_lvds)
4725 dpll |= DPLLB_MODE_LVDS;
4726 else
4727 dpll |= DPLLB_MODE_DAC_SERIAL;
4728 if (is_sdvo) {
6c9547ff
CW		 4729 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4730 if (pixel_multiplier > 1) {
4731 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4732 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
6c9547ff 4733 }
79e53945 4734 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 4735 }
929c77fb 4736 if (is_dp)
a4fc5ed6 4737 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945
JB		 4738
4739 /* compute bitmask from p1 value */
f2b115e6
AJ		 4740 if (IS_PINEVIEW(dev))
4741 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
2c07245f 4742 else {
2177832f 4743 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
652c393a
JB		 4744 if (IS_G4X(dev) && has_reduced_clock)
4745 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2c07245f 4746 }
79e53945
JB		 4747 switch (clock.p2) {
4748 case 5:
4749 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4750 break;
4751 case 7:
4752 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4753 break;
4754 case 10:
4755 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4756 break;
4757 case 14:
4758 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4759 break;
4760 }
929c77fb 4761 if (INTEL_INFO(dev)->gen >= 4)
79e53945
JB		 4762 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4763 } else {
4764 if (is_lvds) {
4765 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4766 } else {
4767 if (clock.p1 == 2)
4768 dpll |= PLL_P1_DIVIDE_BY_TWO;
4769 else
4770 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4771 if (clock.p2 == 4)
4772 dpll |= PLL_P2_DIVIDE_BY_4;
4773 }
4774 }
4775
43565a06
KH		 4776 if (is_sdvo && is_tv)
4777 dpll |= PLL_REF_INPUT_TVCLKINBC;
4778 else if (is_tv)
79e53945 4779 /* XXX: just matching BIOS for now */
43565a06 4780 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 4781 dpll |= 3;
a7615030 4782 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 4783 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 4784 else
4785 dpll |= PLL_REF_INPUT_DREFCLK;
4786
4787 /* setup pipeconf */
5eddb70b 4788 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4789
4790 /* Set up the display plane register */
4791 dspcntr = DISPPLANE_GAMMA_ENABLE;
4792
f2b115e6 4793 /* Ironlake's plane is forced to pipe, bit 24 is to
2c07245f 4794 enable color space conversion */
929c77fb
EA		 4795 if (pipe == 0)
4796 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4797 else
4798 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4799
a6c45cf0 4800 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4801 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4802 * core speed.
4803 *
4804 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4805 * pipe == 0 check?
4806 */
e70236a8
JB		 4807 if (mode->clock >
4808 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4809 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4810 else
5eddb70b 4811 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4812 }
4813
929c77fb 4814 dpll |= DPLL_VCO_ENABLE;
8d86dc6a 4815
28c97730 4816 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4817 drm_mode_debug_printmodeline(mode);
4818
fae14981
EA		 4819 I915_WRITE(FP0(pipe), fp);
4820 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5eddb70b 4821
fae14981 4822 POSTING_READ(DPLL(pipe));
c713bb08 4823 udelay(150);
8db9d77b 4824
79e53945
JB		 4825 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4826 * This is an exception to the general rule that mode_set doesn't turn
4827 * things on.
4828 */
4829 if (is_lvds) {
fae14981 4830 temp = I915_READ(LVDS);
5eddb70b 4831 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
b3b095b3 4832 if (pipe == 1) {
929c77fb 4833 temp |= LVDS_PIPEB_SELECT;
b3b095b3 4834 } else {
929c77fb 4835 temp &= ~LVDS_PIPEB_SELECT;
b3b095b3 4836 }
a3e17eb8 4837 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 4838 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 4839 /* Set the B0-B3 data pairs corresponding to whether we're going to
4840 * set the DPLLs for dual-channel mode or not.
4841 */
4842 if (clock.p2 == 7)
5eddb70b 4843 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 4844 else
5eddb70b 4845 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 4846
4847 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4848 * appropriately here, but we need to look more thoroughly into how
4849 * panels behave in the two modes.
4850 */
929c77fb
EA		 4851 /* set the dithering flag on LVDS as needed */
4852 if (INTEL_INFO(dev)->gen >= 4) {
434ed097 4853 if (dev_priv->lvds_dither)
5eddb70b 4854 temp |= LVDS_ENABLE_DITHER;
434ed097 4855 else
5eddb70b 4856 temp &= ~LVDS_ENABLE_DITHER;
898822ce 4857 }
aa9b500d
BF		 4858 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4859 lvds_sync |= LVDS_HSYNC_POLARITY;
4860 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4861 lvds_sync |= LVDS_VSYNC_POLARITY;
4862 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
4863 != lvds_sync) {
4864 char flags[2] = "-+";
4865 DRM_INFO("Changing LVDS panel from "
4866 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
4867 flags[!(temp & LVDS_HSYNC_POLARITY)],
4868 flags[!(temp & LVDS_VSYNC_POLARITY)],
4869 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
4870 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
4871 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4872 temp |= lvds_sync;
4873 }
fae14981 4874 I915_WRITE(LVDS, temp);
79e53945 4875 }
434ed097 4876
929c77fb 4877 if (is_dp) {
a4fc5ed6 4878 intel_dp_set_m_n(crtc, mode, adjusted_mode);
434ed097
JB		 4879 }
4880
fae14981 4881 I915_WRITE(DPLL(pipe), dpll);
5eddb70b 4882
c713bb08 4883 /* Wait for the clocks to stabilize. */
fae14981 4884 POSTING_READ(DPLL(pipe));
c713bb08 4885 udelay(150);
32f9d658 4886
c713bb08
EA		 4887 if (INTEL_INFO(dev)->gen >= 4) {
4888 temp = 0;
4889 if (is_sdvo) {
4890 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4891 if (temp > 1)
4892 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4893 else
4894 temp = 0;
32f9d658 4895 }
c713bb08
EA		 4896 I915_WRITE(DPLL_MD(pipe), temp);
4897 } else {
4898 /* The pixel multiplier can only be updated once the
4899 * DPLL is enabled and the clocks are stable.
4900 *
4901 * So write it again.
4902 */
fae14981 4903 I915_WRITE(DPLL(pipe), dpll);
79e53945 4904 }
79e53945 4905
5eddb70b 4906 intel_crtc->lowfreq_avail = false;
652c393a 4907 if (is_lvds && has_reduced_clock && i915_powersave) {
fae14981 4908 I915_WRITE(FP1(pipe), fp2);
652c393a
JB		 4909 intel_crtc->lowfreq_avail = true;
4910 if (HAS_PIPE_CXSR(dev)) {
28c97730 4911 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a
JB		 4912 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4913 }
4914 } else {
fae14981 4915 I915_WRITE(FP1(pipe), fp);
652c393a 4916 if (HAS_PIPE_CXSR(dev)) {
28c97730 4917 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4918 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4919 }
4920 }
4921
734b4157
KH		 4922 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4923 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4924 /* the chip adds 2 halflines automatically */
4925 adjusted_mode->crtc_vdisplay -= 1;
4926 adjusted_mode->crtc_vtotal -= 1;
4927 adjusted_mode->crtc_vblank_start -= 1;
4928 adjusted_mode->crtc_vblank_end -= 1;
4929 adjusted_mode->crtc_vsync_end -= 1;
4930 adjusted_mode->crtc_vsync_start -= 1;
4931 } else
4932 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4933
5eddb70b
CW		 4934 I915_WRITE(HTOTAL(pipe),
4935 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 4936 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 4937 I915_WRITE(HBLANK(pipe),
4938 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 4939 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 4940 I915_WRITE(HSYNC(pipe),
4941 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 4942 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 4943
4944 I915_WRITE(VTOTAL(pipe),
4945 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 4946 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 4947 I915_WRITE(VBLANK(pipe),
4948 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 4949 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 4950 I915_WRITE(VSYNC(pipe),
4951 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 4952 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b
CW		 4953
4954 /* pipesrc and dspsize control the size that is scaled from,
4955 * which should always be the user's requested size.
79e53945 4956 */
929c77fb
EA		 4957 I915_WRITE(DSPSIZE(plane),
4958 ((mode->vdisplay - 1) << 16) |
4959 (mode->hdisplay - 1));
4960 I915_WRITE(DSPPOS(plane), 0);
5eddb70b
CW		 4961 I915_WRITE(PIPESRC(pipe),
4962 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 4963
f564048e
EA		 4964 I915_WRITE(PIPECONF(pipe), pipeconf);
4965 POSTING_READ(PIPECONF(pipe));
929c77fb 4966 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4967
4968 intel_wait_for_vblank(dev, pipe);
4969
f564048e
EA		 4970 I915_WRITE(DSPCNTR(plane), dspcntr);
4971 POSTING_READ(DSPCNTR(plane));
284d9529 4972 intel_enable_plane(dev_priv, plane, pipe);
f564048e
EA		 4973
4974 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4975
4976 intel_update_watermarks(dev);
4977
f564048e
EA		 4978 return ret;
4979}
4980
4981static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4982 struct drm_display_mode *mode,
4983 struct drm_display_mode *adjusted_mode,
4984 int x, int y,
4985 struct drm_framebuffer *old_fb)
79e53945
JB		 4986{
4987 struct drm_device *dev = crtc->dev;
4988 struct drm_i915_private *dev_priv = dev->dev_private;
4989 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4990 int pipe = intel_crtc->pipe;
80824003 4991 int plane = intel_crtc->plane;
c751ce4f 4992 int refclk, num_connectors = 0;
652c393a 4993 intel_clock_t clock, reduced_clock;
5eddb70b 4994 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
a07d6787 4995 bool ok, has_reduced_clock = false, is_sdvo = false;
a4fc5ed6 4996 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
8e647a27 4997 struct intel_encoder *has_edp_encoder = NULL;
79e53945 4998 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 4999 struct intel_encoder *encoder;
d4906093 5000 const intel_limit_t *limit;
5c3b82e2 5001 int ret;
2c07245f 5002 struct fdi_m_n m_n = {0};
fae14981 5003 u32 temp;
aa9b500d 5004 u32 lvds_sync = 0;
5a354204
JB		 5005 int target_clock, pixel_multiplier, lane, link_bw, factor;
5006 unsigned int pipe_bpp;
5007 bool dither;
79e53945 5008
5eddb70b
CW		 5009 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5010 if (encoder->base.crtc != crtc)
79e53945
JB		 5011 continue;
5012
5eddb70b 5013 switch (encoder->type) {
79e53945
JB		 5014 case INTEL_OUTPUT_LVDS:
5015 is_lvds = true;
5016 break;
5017 case INTEL_OUTPUT_SDVO:
7d57382e 5018 case INTEL_OUTPUT_HDMI:
79e53945 5019 is_sdvo = true;
5eddb70b 5020 if (encoder->needs_tv_clock)
e2f0ba97 5021 is_tv = true;
79e53945 5022 break;
79e53945
JB		 5023 case INTEL_OUTPUT_TVOUT:
5024 is_tv = true;
5025 break;
5026 case INTEL_OUTPUT_ANALOG:
5027 is_crt = true;
5028 break;
a4fc5ed6
KP		 5029 case INTEL_OUTPUT_DISPLAYPORT:
5030 is_dp = true;
5031 break;
32f9d658 5032 case INTEL_OUTPUT_EDP:
5eddb70b 5033 has_edp_encoder = encoder;
32f9d658 5034 break;
79e53945 5035 }
43565a06 5036
c751ce4f 5037 num_connectors++;
79e53945
JB		 5038 }
5039
a7615030 5040 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
43565a06 5041 refclk = dev_priv->lvds_ssc_freq * 1000;
28c97730 5042 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5eddb70b 5043 refclk / 1000);
a07d6787 5044 } else {
79e53945 5045 refclk = 96000;
8febb297
EA		 5046 if (!has_edp_encoder ||
5047 intel_encoder_is_pch_edp(&has_edp_encoder->base))
2c07245f 5048 refclk = 120000; /* 120Mhz refclk */
79e53945
JB		 5049 }
5050
d4906093
ML		 5051 /*
5052 * Returns a set of divisors for the desired target clock with the given
5053 * refclk, or FALSE. The returned values represent the clock equation:
5054 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5055 */
1b894b59 5056 limit = intel_limit(crtc, refclk);
d4906093 5057 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
79e53945
JB		 5058 if (!ok) {
5059 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 5060 return -EINVAL;
79e53945
JB		 5061 }
5062
cda4b7d3 5063 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 5064 intel_crtc_update_cursor(crtc, true);
cda4b7d3 5065
ddc9003c
ZY		 5066 if (is_lvds && dev_priv->lvds_downclock_avail) {
5067 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 5068 dev_priv->lvds_downclock,
5069 refclk,
5070 &reduced_clock);
18f9ed12
ZY		 5071 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
5072 /*
5073 * If the different P is found, it means that we can't
5074 * switch the display clock by using the FP0/FP1.
5075 * In such case we will disable the LVDS downclock
5076 * feature.
5077 */
5078 DRM_DEBUG_KMS("Different P is found for "
5eddb70b 5079 "LVDS clock/downclock\n");
18f9ed12
ZY		 5080 has_reduced_clock = 0;
5081 }
652c393a 5082 }
7026d4ac
ZW		 5083 /* SDVO TV has fixed PLL values depend on its clock range,
5084 this mirrors vbios setting. */
5085 if (is_sdvo && is_tv) {
5086 if (adjusted_mode->clock >= 100000
5eddb70b 5087 && adjusted_mode->clock < 140500) {
7026d4ac
ZW		 5088 clock.p1 = 2;
5089 clock.p2 = 10;
5090 clock.n = 3;
5091 clock.m1 = 16;
5092 clock.m2 = 8;
5093 } else if (adjusted_mode->clock >= 140500
5eddb70b 5094 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW		 5095 clock.p1 = 1;
5096 clock.p2 = 10;
5097 clock.n = 6;
5098 clock.m1 = 12;
5099 clock.m2 = 8;
5100 }
5101 }
5102
2c07245f 5103 /* FDI link */
8febb297
EA		 5104 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5105 lane = 0;
5106 /* CPU eDP doesn't require FDI link, so just set DP M/N
5107 according to current link config */
5108 if (has_edp_encoder &&
5109 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5110 target_clock = mode->clock;
5111 intel_edp_link_config(has_edp_encoder,
5112 &lane, &link_bw);
5113 } else {
5114 /* [e]DP over FDI requires target mode clock
5115 instead of link clock */
5116 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5eb08b69 5117 target_clock = mode->clock;
8febb297
EA		 5118 else
5119 target_clock = adjusted_mode->clock;
5120
5121 /* FDI is a binary signal running at ~2.7GHz, encoding
5122 * each output octet as 10 bits. The actual frequency
5123 * is stored as a divider into a 100MHz clock, and the
5124 * mode pixel clock is stored in units of 1KHz.
5125 * Hence the bw of each lane in terms of the mode signal
5126 * is:
5127 */
5128 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5129 }
58a27471 5130
8febb297
EA		 5131 /* determine panel color depth */
5132 temp = I915_READ(PIPECONF(pipe));
5133 temp &= ~PIPE_BPC_MASK;
5a354204
JB		 5134 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp);
5135 switch (pipe_bpp) {
5136 case 18:
5137 temp |= PIPE_6BPC;
8febb297 5138 break;
5a354204
JB		 5139 case 24:
5140 temp |= PIPE_8BPC;
8febb297 5141 break;
5a354204
JB		 5142 case 30:
5143 temp |= PIPE_10BPC;
8febb297 5144 break;
5a354204
JB		 5145 case 36:
5146 temp |= PIPE_12BPC;
8febb297
EA		 5147 break;
5148 default:
5a354204
JB		 5149 WARN(1, "intel_choose_pipe_bpp returned invalid value\n");
5150 temp |= PIPE_8BPC;
5151 pipe_bpp = 24;
5152 break;
8febb297 5153 }
77ffb597 5154
5a354204
JB		 5155 intel_crtc->bpp = pipe_bpp;
5156 I915_WRITE(PIPECONF(pipe), temp);
5157
8febb297
EA		 5158 if (!lane) {
5159 /*
5160 * Account for spread spectrum to avoid
5161 * oversubscribing the link. Max center spread
5162 * is 2.5%; use 5% for safety's sake.
5163 */
5a354204 5164 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
8febb297 5165 lane = bps / (link_bw * 8) + 1;
5eb08b69 5166 }
2c07245f 5167
8febb297
EA		 5168 intel_crtc->fdi_lanes = lane;
5169
5170 if (pixel_multiplier > 1)
5171 link_bw *= pixel_multiplier;
5a354204
JB		 5172 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5173 &m_n);
8febb297 5174
c038e51e
ZW		 5175 /* Ironlake: try to setup display ref clock before DPLL
5176 * enabling. This is only under driver's control after
5177 * PCH B stepping, previous chipset stepping should be
5178 * ignoring this setting.
5179 */
8febb297
EA		 5180 temp = I915_READ(PCH_DREF_CONTROL);
5181 /* Always enable nonspread source */
5182 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5183 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5184 temp &= ~DREF_SSC_SOURCE_MASK;
5185 temp |= DREF_SSC_SOURCE_ENABLE;
5186 I915_WRITE(PCH_DREF_CONTROL, temp);
5187
5188 POSTING_READ(PCH_DREF_CONTROL);
5189 udelay(200);
fc9a2228 5190
8febb297
EA		 5191 if (has_edp_encoder) {
5192 if (intel_panel_use_ssc(dev_priv)) {
5193 temp |= DREF_SSC1_ENABLE;
fc9a2228 5194 I915_WRITE(PCH_DREF_CONTROL, temp);
8febb297 5195
fc9a2228
CW		 5196 POSTING_READ(PCH_DREF_CONTROL);
5197 udelay(200);
5198 }
8febb297
EA		 5199 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5200
5201 /* Enable CPU source on CPU attached eDP */
5202 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5203 if (intel_panel_use_ssc(dev_priv))
5204 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5205 else
5206 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5207 } else {
5208 /* Enable SSC on PCH eDP if needed */
5209 if (intel_panel_use_ssc(dev_priv)) {
5210 DRM_ERROR("enabling SSC on PCH\n");
5211 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
5212 }
5213 }
5214 I915_WRITE(PCH_DREF_CONTROL, temp);
5215 POSTING_READ(PCH_DREF_CONTROL);
5216 udelay(200);
fc9a2228 5217 }
c038e51e 5218
a07d6787
EA		 5219 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5220 if (has_reduced_clock)
5221 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5222 reduced_clock.m2;
79e53945 5223
c1858123 5224 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5225 factor = 21;
5226 if (is_lvds) {
5227 if ((intel_panel_use_ssc(dev_priv) &&
5228 dev_priv->lvds_ssc_freq == 100) ||
5229 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5230 factor = 25;
5231 } else if (is_sdvo && is_tv)
5232 factor = 20;
c1858123 5233
8febb297
EA		 5234 if (clock.m1 < factor * clock.n)
5235 fp |= FP_CB_TUNE;
2c07245f 5236
5eddb70b 5237 dpll = 0;
2c07245f 5238
a07d6787
EA		 5239 if (is_lvds)
5240 dpll |= DPLLB_MODE_LVDS;
5241 else
5242 dpll |= DPLLB_MODE_DAC_SERIAL;
5243 if (is_sdvo) {
5244 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5245 if (pixel_multiplier > 1) {
5246 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5247 }
a07d6787
EA		 5248 dpll |= DPLL_DVO_HIGH_SPEED;
5249 }
5250 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5251 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5252
a07d6787
EA		 5253 /* compute bitmask from p1 value */
5254 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5255 /* also FPA1 */
5256 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5257
5258 switch (clock.p2) {
5259 case 5:
5260 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5261 break;
5262 case 7:
5263 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5264 break;
5265 case 10:
5266 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5267 break;
5268 case 14:
5269 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5270 break;
79e53945
JB		 5271 }
5272
43565a06
KH		 5273 if (is_sdvo && is_tv)
5274 dpll |= PLL_REF_INPUT_TVCLKINBC;
5275 else if (is_tv)
79e53945 5276 /* XXX: just matching BIOS for now */
43565a06 5277 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5278 dpll |= 3;
a7615030 5279 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5280 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5281 else
5282 dpll |= PLL_REF_INPUT_DREFCLK;
5283
5284 /* setup pipeconf */
5eddb70b 5285 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 5286
5287 /* Set up the display plane register */
5288 dspcntr = DISPPLANE_GAMMA_ENABLE;
5289
28c97730 5290 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 5291 drm_mode_debug_printmodeline(mode);
5292
5c5313c8
JB		 5293 /* PCH eDP needs FDI, but CPU eDP does not */
5294 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
fae14981
EA		 5295 I915_WRITE(PCH_FP0(pipe), fp);
5296 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5eddb70b 5297
fae14981 5298 POSTING_READ(PCH_DPLL(pipe));
79e53945
JB		 5299 udelay(150);
5300 }
5301
8db9d77b
ZW		 5302 /* enable transcoder DPLL */
5303 if (HAS_PCH_CPT(dev)) {
5304 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 5305 switch (pipe) {
5306 case 0:
5eddb70b 5307 temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
9db4a9c7
JB		 5308 break;
5309 case 1:
5eddb70b 5310 temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
9db4a9c7
JB		 5311 break;
5312 case 2:
5313 /* FIXME: manage transcoder PLLs? */
5314 temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL;
5315 break;
5316 default:
5317 BUG();
32f9d658 5318 }
8db9d77b 5319 I915_WRITE(PCH_DPLL_SEL, temp);
5eddb70b
CW		 5320
5321 POSTING_READ(PCH_DPLL_SEL);
8db9d77b
ZW		 5322 udelay(150);
5323 }
5324
79e53945
JB		 5325 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5326 * This is an exception to the general rule that mode_set doesn't turn
5327 * things on.
5328 */
5329 if (is_lvds) {
fae14981 5330 temp = I915_READ(PCH_LVDS);
5eddb70b 5331 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
b3b095b3
ZW		 5332 if (pipe == 1) {
5333 if (HAS_PCH_CPT(dev))
5eddb70b 5334 temp |= PORT_TRANS_B_SEL_CPT;
b3b095b3 5335 else
5eddb70b 5336 temp |= LVDS_PIPEB_SELECT;
b3b095b3
ZW		 5337 } else {
5338 if (HAS_PCH_CPT(dev))
5eddb70b 5339 temp &= ~PORT_TRANS_SEL_MASK;
b3b095b3 5340 else
5eddb70b 5341 temp &= ~LVDS_PIPEB_SELECT;
b3b095b3 5342 }
a3e17eb8 5343 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5344 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5345 /* Set the B0-B3 data pairs corresponding to whether we're going to
5346 * set the DPLLs for dual-channel mode or not.
5347 */
5348 if (clock.p2 == 7)
5eddb70b 5349 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5350 else
5eddb70b 5351 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5352
5353 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5354 * appropriately here, but we need to look more thoroughly into how
5355 * panels behave in the two modes.
5356 */
aa9b500d
BF		 5357 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5358 lvds_sync |= LVDS_HSYNC_POLARITY;
5359 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5360 lvds_sync |= LVDS_VSYNC_POLARITY;
5361 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5362 != lvds_sync) {
5363 char flags[2] = "-+";
5364 DRM_INFO("Changing LVDS panel from "
5365 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5366 flags[!(temp & LVDS_HSYNC_POLARITY)],
5367 flags[!(temp & LVDS_VSYNC_POLARITY)],
5368 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5369 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5370 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5371 temp |= lvds_sync;
5372 }
fae14981 5373 I915_WRITE(PCH_LVDS, temp);
79e53945 5374 }
434ed097 5375
8febb297
EA		 5376 pipeconf &= ~PIPECONF_DITHER_EN;
5377 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5a354204 5378 if ((is_lvds && dev_priv->lvds_dither) || dither) {
8febb297
EA		 5379 pipeconf |= PIPECONF_DITHER_EN;
5380 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
434ed097 5381 }
5c5313c8 5382 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
a4fc5ed6 5383 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 5384 } else {
8db9d77b 5385 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 5386 I915_WRITE(TRANSDATA_M1(pipe), 0);
5387 I915_WRITE(TRANSDATA_N1(pipe), 0);
5388 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5389 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 5390 }
79e53945 5391
8febb297
EA		 5392 if (!has_edp_encoder ||
5393 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
fae14981 5394 I915_WRITE(PCH_DPLL(pipe), dpll);
5eddb70b 5395
32f9d658 5396 /* Wait for the clocks to stabilize. */
fae14981 5397 POSTING_READ(PCH_DPLL(pipe));
32f9d658
ZW		 5398 udelay(150);
5399
8febb297
EA		 5400 /* The pixel multiplier can only be updated once the
5401 * DPLL is enabled and the clocks are stable.
5402 *
5403 * So write it again.
5404 */
fae14981 5405 I915_WRITE(PCH_DPLL(pipe), dpll);
79e53945 5406 }
79e53945 5407
5eddb70b 5408 intel_crtc->lowfreq_avail = false;
652c393a 5409 if (is_lvds && has_reduced_clock && i915_powersave) {
fae14981 5410 I915_WRITE(PCH_FP1(pipe), fp2);
652c393a
JB		 5411 intel_crtc->lowfreq_avail = true;
5412 if (HAS_PIPE_CXSR(dev)) {
28c97730 5413 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a
JB		 5414 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5415 }
5416 } else {
fae14981 5417 I915_WRITE(PCH_FP1(pipe), fp);
652c393a 5418 if (HAS_PIPE_CXSR(dev)) {
28c97730 5419 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 5420 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5421 }
5422 }
5423
734b4157
KH		 5424 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5425 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5426 /* the chip adds 2 halflines automatically */
5427 adjusted_mode->crtc_vdisplay -= 1;
5428 adjusted_mode->crtc_vtotal -= 1;
5429 adjusted_mode->crtc_vblank_start -= 1;
5430 adjusted_mode->crtc_vblank_end -= 1;
5431 adjusted_mode->crtc_vsync_end -= 1;
5432 adjusted_mode->crtc_vsync_start -= 1;
5433 } else
5434 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5435
5eddb70b
CW		 5436 I915_WRITE(HTOTAL(pipe),
5437 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 5438 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 5439 I915_WRITE(HBLANK(pipe),
5440 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 5441 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 5442 I915_WRITE(HSYNC(pipe),
5443 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 5444 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 5445
5446 I915_WRITE(VTOTAL(pipe),
5447 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 5448 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 5449 I915_WRITE(VBLANK(pipe),
5450 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 5451 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 5452 I915_WRITE(VSYNC(pipe),
5453 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 5454 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b 5455
8febb297
EA		 5456 /* pipesrc controls the size that is scaled from, which should
5457 * always be the user's requested size.
79e53945 5458 */
5eddb70b
CW		 5459 I915_WRITE(PIPESRC(pipe),
5460 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 5461
8febb297
EA		 5462 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5463 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5464 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5465 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
2c07245f 5466
8febb297
EA		 5467 if (has_edp_encoder &&
5468 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5469 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f
ZW		 5470 }
5471
5eddb70b
CW		 5472 I915_WRITE(PIPECONF(pipe), pipeconf);
5473 POSTING_READ(PIPECONF(pipe));
79e53945 5474
9d0498a2 5475 intel_wait_for_vblank(dev, pipe);
79e53945 5476
f00a3ddf 5477 if (IS_GEN5(dev)) {
553bd149
ZW		 5478 /* enable address swizzle for tiling buffer */
5479 temp = I915_READ(DISP_ARB_CTL);
5480 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5481 }
5482
5eddb70b 5483 I915_WRITE(DSPCNTR(plane), dspcntr);
b24e7179 5484 POSTING_READ(DSPCNTR(plane));
79e53945 5485
5c3b82e2 5486 ret = intel_pipe_set_base(crtc, x, y, old_fb);
7662c8bd
SL		 5487
5488 intel_update_watermarks(dev);
5489
1f803ee5 5490 return ret;
79e53945
JB		 5491}
5492
f564048e
EA		 5493static int intel_crtc_mode_set(struct drm_crtc *crtc,
5494 struct drm_display_mode *mode,
5495 struct drm_display_mode *adjusted_mode,
5496 int x, int y,
5497 struct drm_framebuffer *old_fb)
5498{
5499 struct drm_device *dev = crtc->dev;
5500 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 5501 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5502 int pipe = intel_crtc->pipe;
f564048e
EA		 5503 int ret;
5504
0b701d27 5505 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5506
f564048e
EA		 5507 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5508 x, y, old_fb);
7662c8bd 5509
79e53945 5510 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5511
1f803ee5 5512 return ret;
79e53945
JB		 5513}
5514
5515/** Loads the palette/gamma unit for the CRTC with the prepared values */
5516void intel_crtc_load_lut(struct drm_crtc *crtc)
5517{
5518 struct drm_device *dev = crtc->dev;
5519 struct drm_i915_private *dev_priv = dev->dev_private;
5520 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 5521 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 5522 int i;
5523
5524 /* The clocks have to be on to load the palette. */
5525 if (!crtc->enabled)
5526 return;
5527
f2b115e6 5528 /* use legacy palette for Ironlake */
bad720ff 5529 if (HAS_PCH_SPLIT(dev))
9db4a9c7 5530 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 5531
79e53945
JB		 5532 for (i = 0; i < 256; i++) {
5533 I915_WRITE(palreg + 4 * i,
5534 (intel_crtc->lut_r[i] << 16) |
5535 (intel_crtc->lut_g[i] << 8) |
5536 intel_crtc->lut_b[i]);
5537 }
5538}
5539
560b85bb
CW		 5540static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5541{
5542 struct drm_device *dev = crtc->dev;
5543 struct drm_i915_private *dev_priv = dev->dev_private;
5544 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5545 bool visible = base != 0;
5546 u32 cntl;
5547
5548 if (intel_crtc->cursor_visible == visible)
5549 return;
5550
9db4a9c7 5551 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 5552 if (visible) {
5553 /* On these chipsets we can only modify the base whilst
5554 * the cursor is disabled.
5555 */
9db4a9c7 5556 I915_WRITE(_CURABASE, base);
560b85bb
CW		 5557
5558 cntl &= ~(CURSOR_FORMAT_MASK);
5559 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5560 cntl |= CURSOR_ENABLE |
5561 CURSOR_GAMMA_ENABLE |
5562 CURSOR_FORMAT_ARGB;
5563 } else
5564 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 5565 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 5566
5567 intel_crtc->cursor_visible = visible;
5568}
5569
5570static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5571{
5572 struct drm_device *dev = crtc->dev;
5573 struct drm_i915_private *dev_priv = dev->dev_private;
5574 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5575 int pipe = intel_crtc->pipe;
5576 bool visible = base != 0;
5577
5578 if (intel_crtc->cursor_visible != visible) {
548f245b 5579 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 5580 if (base) {
5581 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5582 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5583 cntl |= pipe << 28; /* Connect to correct pipe */
5584 } else {
5585 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5586 cntl |= CURSOR_MODE_DISABLE;
5587 }
9db4a9c7 5588 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 5589
5590 intel_crtc->cursor_visible = visible;
5591 }
5592 /* and commit changes on next vblank */
9db4a9c7 5593 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 5594}
5595
cda4b7d3 5596/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 5597static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5598 bool on)
cda4b7d3
CW		 5599{
5600 struct drm_device *dev = crtc->dev;
5601 struct drm_i915_private *dev_priv = dev->dev_private;
5602 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5603 int pipe = intel_crtc->pipe;
5604 int x = intel_crtc->cursor_x;
5605 int y = intel_crtc->cursor_y;
560b85bb 5606 u32 base, pos;
cda4b7d3
CW		 5607 bool visible;
5608
5609 pos = 0;
5610
6b383a7f 5611 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 5612 base = intel_crtc->cursor_addr;
5613 if (x > (int) crtc->fb->width)
5614 base = 0;
5615
5616 if (y > (int) crtc->fb->height)
5617 base = 0;
5618 } else
5619 base = 0;
5620
5621 if (x < 0) {
5622 if (x + intel_crtc->cursor_width < 0)
5623 base = 0;
5624
5625 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5626 x = -x;
5627 }
5628 pos |= x << CURSOR_X_SHIFT;
5629
5630 if (y < 0) {
5631 if (y + intel_crtc->cursor_height < 0)
5632 base = 0;
5633
5634 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5635 y = -y;
5636 }
5637 pos |= y << CURSOR_Y_SHIFT;
5638
5639 visible = base != 0;
560b85bb 5640 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 5641 return;
5642
9db4a9c7 5643 I915_WRITE(CURPOS(pipe), pos);
560b85bb
CW		 5644 if (IS_845G(dev) || IS_I865G(dev))
5645 i845_update_cursor(crtc, base);
5646 else
5647 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 5648
5649 if (visible)
5650 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
5651}
5652
79e53945 5653static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 5654 struct drm_file *file,
79e53945
JB		 5655 uint32_t handle,
5656 uint32_t width, uint32_t height)
5657{
5658 struct drm_device *dev = crtc->dev;
5659 struct drm_i915_private *dev_priv = dev->dev_private;
5660 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 5661 struct drm_i915_gem_object *obj;
cda4b7d3 5662 uint32_t addr;
3f8bc370 5663 int ret;
79e53945 5664
28c97730 5665 DRM_DEBUG_KMS("\n");
79e53945
JB		 5666
5667 /* if we want to turn off the cursor ignore width and height */
5668 if (!handle) {
28c97730 5669 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 5670 addr = 0;
05394f39 5671 obj = NULL;
5004417d 5672 mutex_lock(&dev->struct_mutex);
3f8bc370 5673 goto finish;
79e53945
JB		 5674 }
5675
5676 /* Currently we only support 64x64 cursors */
5677 if (width != 64 || height != 64) {
5678 DRM_ERROR("we currently only support 64x64 cursors\n");
5679 return -EINVAL;
5680 }
5681
05394f39 5682 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 5683 if (&obj->base == NULL)
79e53945
JB		 5684 return -ENOENT;
5685
05394f39 5686 if (obj->base.size < width * height * 4) {
79e53945 5687 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 5688 ret = -ENOMEM;
5689 goto fail;
79e53945
JB		 5690 }
5691
71acb5eb 5692 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 5693 mutex_lock(&dev->struct_mutex);
b295d1b6 5694 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 5695 if (obj->tiling_mode) {
5696 DRM_ERROR("cursor cannot be tiled\n");
5697 ret = -EINVAL;
5698 goto fail_locked;
5699 }
5700
2da3b9b9 5701 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 5702 if (ret) {
5703 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 5704 goto fail_locked;
e7b526bb
CW		 5705 }
5706
d9e86c0e
CW		 5707 ret = i915_gem_object_put_fence(obj);
5708 if (ret) {
2da3b9b9 5709 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 5710 goto fail_unpin;
5711 }
5712
05394f39 5713 addr = obj->gtt_offset;
71acb5eb 5714 } else {
6eeefaf3 5715 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 5716 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 5717 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5718 align);
71acb5eb
DA		 5719 if (ret) {
5720 DRM_ERROR("failed to attach phys object\n");
7f9872e0 5721 goto fail_locked;
71acb5eb 5722 }
05394f39 5723 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 5724 }
5725
a6c45cf0 5726 if (IS_GEN2(dev))
14b60391
JB		 5727 I915_WRITE(CURSIZE, (height << 12) | width);
5728
3f8bc370 5729 finish:
3f8bc370 5730 if (intel_crtc->cursor_bo) {
b295d1b6 5731 if (dev_priv->info->cursor_needs_physical) {
05394f39 5732 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 5733 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5734 } else
5735 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 5736 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 5737 }
80824003 5738
7f9872e0 5739 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 5740
5741 intel_crtc->cursor_addr = addr;
05394f39 5742 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 5743 intel_crtc->cursor_width = width;
5744 intel_crtc->cursor_height = height;
5745
6b383a7f 5746 intel_crtc_update_cursor(crtc, true);
3f8bc370 5747
79e53945 5748 return 0;
e7b526bb 5749fail_unpin:
05394f39 5750 i915_gem_object_unpin(obj);
7f9872e0 5751fail_locked:
34b8686e 5752 mutex_unlock(&dev->struct_mutex);
bc9025bd 5753fail:
05394f39 5754 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 5755 return ret;
79e53945
JB		 5756}
5757
5758static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5759{
79e53945 5760 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5761
cda4b7d3
CW		 5762 intel_crtc->cursor_x = x;
5763 intel_crtc->cursor_y = y;
652c393a 5764
6b383a7f 5765 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 5766
5767 return 0;
5768}
5769
5770/** Sets the color ramps on behalf of RandR */
5771void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5772 u16 blue, int regno)
5773{
5774 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5775
5776 intel_crtc->lut_r[regno] = red >> 8;
5777 intel_crtc->lut_g[regno] = green >> 8;
5778 intel_crtc->lut_b[regno] = blue >> 8;
5779}
5780
b8c00ac5
DA		 5781void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5782 u16 *blue, int regno)
5783{
5784 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5785
5786 *red = intel_crtc->lut_r[regno] << 8;
5787 *green = intel_crtc->lut_g[regno] << 8;
5788 *blue = intel_crtc->lut_b[regno] << 8;
5789}
5790
79e53945 5791static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 5792 u16 *blue, uint32_t start, uint32_t size)
79e53945 5793{
7203425a 5794 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 5795 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5796
7203425a 5797 for (i = start; i < end; i++) {
79e53945
JB		 5798 intel_crtc->lut_r[i] = red[i] >> 8;
5799 intel_crtc->lut_g[i] = green[i] >> 8;
5800 intel_crtc->lut_b[i] = blue[i] >> 8;
5801 }
5802
5803 intel_crtc_load_lut(crtc);
5804}
5805
5806/**
5807 * Get a pipe with a simple mode set on it for doing load-based monitor
5808 * detection.
5809 *
5810 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 5811 * its requirements. The pipe will be connected to no other encoders.
79e53945 5812 *
c751ce4f 5813 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 5814 * configured for it. In the future, it could choose to temporarily disable
5815 * some outputs to free up a pipe for its use.
5816 *
5817 * \return crtc, or NULL if no pipes are available.
5818 */
5819
5820/* VESA 640x480x72Hz mode to set on the pipe */
5821static struct drm_display_mode load_detect_mode = {
5822 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5823 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5824};
5825
d2dff872
CW		 5826static struct drm_framebuffer *
5827intel_framebuffer_create(struct drm_device *dev,
5828 struct drm_mode_fb_cmd *mode_cmd,
5829 struct drm_i915_gem_object *obj)
5830{
5831 struct intel_framebuffer *intel_fb;
5832 int ret;
5833
5834 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5835 if (!intel_fb) {
5836 drm_gem_object_unreference_unlocked(&obj->base);
5837 return ERR_PTR(-ENOMEM);
5838 }
5839
5840 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5841 if (ret) {
5842 drm_gem_object_unreference_unlocked(&obj->base);
5843 kfree(intel_fb);
5844 return ERR_PTR(ret);
5845 }
5846
5847 return &intel_fb->base;
5848}
5849
5850static u32
5851intel_framebuffer_pitch_for_width(int width, int bpp)
5852{
5853 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5854 return ALIGN(pitch, 64);
5855}
5856
5857static u32
5858intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5859{
5860 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5861 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5862}
5863
5864static struct drm_framebuffer *
5865intel_framebuffer_create_for_mode(struct drm_device *dev,
5866 struct drm_display_mode *mode,
5867 int depth, int bpp)
5868{
5869 struct drm_i915_gem_object *obj;
5870 struct drm_mode_fb_cmd mode_cmd;
5871
5872 obj = i915_gem_alloc_object(dev,
5873 intel_framebuffer_size_for_mode(mode, bpp));
5874 if (obj == NULL)
5875 return ERR_PTR(-ENOMEM);
5876
5877 mode_cmd.width = mode->hdisplay;
5878 mode_cmd.height = mode->vdisplay;
5879 mode_cmd.depth = depth;
5880 mode_cmd.bpp = bpp;
5881 mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
5882
5883 return intel_framebuffer_create(dev, &mode_cmd, obj);
5884}
5885
5886static struct drm_framebuffer *
5887mode_fits_in_fbdev(struct drm_device *dev,
5888 struct drm_display_mode *mode)
5889{
5890 struct drm_i915_private *dev_priv = dev->dev_private;
5891 struct drm_i915_gem_object *obj;
5892 struct drm_framebuffer *fb;
5893
5894 if (dev_priv->fbdev == NULL)
5895 return NULL;
5896
5897 obj = dev_priv->fbdev->ifb.obj;
5898 if (obj == NULL)
5899 return NULL;
5900
5901 fb = &dev_priv->fbdev->ifb.base;
5902 if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
5903 fb->bits_per_pixel))
5904 return NULL;
5905
5906 if (obj->base.size < mode->vdisplay * fb->pitch)
5907 return NULL;
5908
5909 return fb;
5910}
5911
7173188d
CW		 5912bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5913 struct drm_connector *connector,
5914 struct drm_display_mode *mode,
8261b191 5915 struct intel_load_detect_pipe *old)
79e53945
JB		 5916{
5917 struct intel_crtc *intel_crtc;
5918 struct drm_crtc *possible_crtc;
4ef69c7a 5919 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5920 struct drm_crtc *crtc = NULL;
5921 struct drm_device *dev = encoder->dev;
d2dff872 5922 struct drm_framebuffer *old_fb;
79e53945
JB		 5923 int i = -1;
5924
d2dff872
CW		 5925 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5926 connector->base.id, drm_get_connector_name(connector),
5927 encoder->base.id, drm_get_encoder_name(encoder));
5928
79e53945
JB		 5929 /*
5930 * Algorithm gets a little messy:
7a5e4805 5931 *
79e53945
JB		 5932 * - if the connector already has an assigned crtc, use it (but make
5933 * sure it's on first)
7a5e4805 5934 *
79e53945
JB		 5935 * - try to find the first unused crtc that can drive this connector,
5936 * and use that if we find one
79e53945
JB		 5937 */
5938
5939 /* See if we already have a CRTC for this connector */
5940 if (encoder->crtc) {
5941 crtc = encoder->crtc;
8261b191 5942
79e53945 5943 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 5944 old->dpms_mode = intel_crtc->dpms_mode;
5945 old->load_detect_temp = false;
5946
5947 /* Make sure the crtc and connector are running */
79e53945 5948 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6492711d
CW		 5949 struct drm_encoder_helper_funcs *encoder_funcs;
5950 struct drm_crtc_helper_funcs *crtc_funcs;
5951
79e53945
JB		 5952 crtc_funcs = crtc->helper_private;
5953 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6492711d
CW		 5954
5955 encoder_funcs = encoder->helper_private;
79e53945
JB		 5956 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5957 }
8261b191 5958
7173188d 5959 return true;
79e53945
JB		 5960 }
5961
5962 /* Find an unused one (if possible) */
5963 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5964 i++;
5965 if (!(encoder->possible_crtcs & (1 << i)))
5966 continue;
5967 if (!possible_crtc->enabled) {
5968 crtc = possible_crtc;
5969 break;
5970 }
79e53945
JB		 5971 }
5972
5973 /*
5974 * If we didn't find an unused CRTC, don't use any.
5975 */
5976 if (!crtc) {
7173188d
CW		 5977 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5978 return false;
79e53945
JB		 5979 }
5980
5981 encoder->crtc = crtc;
c1c43977 5982 connector->encoder = encoder;
79e53945
JB		 5983
5984 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 5985 old->dpms_mode = intel_crtc->dpms_mode;
5986 old->load_detect_temp = true;
d2dff872 5987 old->release_fb = NULL;
79e53945 5988
6492711d
CW		 5989 if (!mode)
5990 mode = &load_detect_mode;
79e53945 5991
d2dff872
CW		 5992 old_fb = crtc->fb;
5993
5994 /* We need a framebuffer large enough to accommodate all accesses
5995 * that the plane may generate whilst we perform load detection.
5996 * We can not rely on the fbcon either being present (we get called
5997 * during its initialisation to detect all boot displays, or it may
5998 * not even exist) or that it is large enough to satisfy the
5999 * requested mode.
6000 */
6001 crtc->fb = mode_fits_in_fbdev(dev, mode);
6002 if (crtc->fb == NULL) {
6003 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6004 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6005 old->release_fb = crtc->fb;
6006 } else
6007 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6008 if (IS_ERR(crtc->fb)) {
6009 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6010 crtc->fb = old_fb;
6011 return false;
79e53945 6012 }
79e53945 6013
d2dff872 6014 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6492711d 6015 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6016 if (old->release_fb)
6017 old->release_fb->funcs->destroy(old->release_fb);
6018 crtc->fb = old_fb;
6492711d 6019 return false;
79e53945 6020 }
7173188d 6021
79e53945 6022 /* let the connector get through one full cycle before testing */
9d0498a2 6023 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 6024
7173188d 6025 return true;
79e53945
JB		 6026}
6027
c1c43977 6028void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
8261b191
CW		 6029 struct drm_connector *connector,
6030 struct intel_load_detect_pipe *old)
79e53945 6031{
4ef69c7a 6032 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6033 struct drm_device *dev = encoder->dev;
6034 struct drm_crtc *crtc = encoder->crtc;
6035 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6036 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6037
d2dff872
CW		 6038 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6039 connector->base.id, drm_get_connector_name(connector),
6040 encoder->base.id, drm_get_encoder_name(encoder));
6041
8261b191 6042 if (old->load_detect_temp) {
c1c43977 6043 connector->encoder = NULL;
79e53945 6044 drm_helper_disable_unused_functions(dev);
d2dff872
CW		 6045
6046 if (old->release_fb)
6047 old->release_fb->funcs->destroy(old->release_fb);
6048
0622a53c 6049 return;
79e53945
JB		 6050 }
6051
c751ce4f 6052 /* Switch crtc and encoder back off if necessary */
0622a53c
CW		 6053 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6054 encoder_funcs->dpms(encoder, old->dpms_mode);
8261b191 6055 crtc_funcs->dpms(crtc, old->dpms_mode);
79e53945
JB		 6056 }
6057}
6058
6059/* Returns the clock of the currently programmed mode of the given pipe. */
6060static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6061{
6062 struct drm_i915_private *dev_priv = dev->dev_private;
6063 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6064 int pipe = intel_crtc->pipe;
548f245b 6065 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6066 u32 fp;
6067 intel_clock_t clock;
6068
6069 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6070 fp = I915_READ(FP0(pipe));
79e53945 6071 else
39adb7a5 6072 fp = I915_READ(FP1(pipe));
79e53945
JB		 6073
6074 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6075 if (IS_PINEVIEW(dev)) {
6076 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6077 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6078 } else {
6079 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6080 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6081 }
6082
a6c45cf0 6083 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6084 if (IS_PINEVIEW(dev))
6085 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6086 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6087 else
6088 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6089 DPLL_FPA01_P1_POST_DIV_SHIFT);
6090
6091 switch (dpll & DPLL_MODE_MASK) {
6092 case DPLLB_MODE_DAC_SERIAL:
6093 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6094 5 : 10;
6095 break;
6096 case DPLLB_MODE_LVDS:
6097 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6098 7 : 14;
6099 break;
6100 default:
28c97730 6101 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6102 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6103 return 0;
6104 }
6105
6106 /* XXX: Handle the 100Mhz refclk */
2177832f 6107 intel_clock(dev, 96000, &clock);
79e53945
JB		 6108 } else {
6109 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6110
6111 if (is_lvds) {
6112 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6113 DPLL_FPA01_P1_POST_DIV_SHIFT);
6114 clock.p2 = 14;
6115
6116 if ((dpll & PLL_REF_INPUT_MASK) ==
6117 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6118 /* XXX: might not be 66MHz */
2177832f 6119 intel_clock(dev, 66000, &clock);
79e53945 6120 } else
2177832f 6121 intel_clock(dev, 48000, &clock);
79e53945
JB		 6122 } else {
6123 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6124 clock.p1 = 2;
6125 else {
6126 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6127 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6128 }
6129 if (dpll & PLL_P2_DIVIDE_BY_4)
6130 clock.p2 = 4;
6131 else
6132 clock.p2 = 2;
6133
2177832f 6134 intel_clock(dev, 48000, &clock);
79e53945
JB		 6135 }
6136 }
6137
6138 /* XXX: It would be nice to validate the clocks, but we can't reuse
6139 * i830PllIsValid() because it relies on the xf86_config connector
6140 * configuration being accurate, which it isn't necessarily.
6141 */
6142
6143 return clock.dot;
6144}
6145
6146/** Returns the currently programmed mode of the given pipe. */
6147struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6148 struct drm_crtc *crtc)
6149{
548f245b 6150 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 6151 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6152 int pipe = intel_crtc->pipe;
6153 struct drm_display_mode *mode;
548f245b
JB		 6154 int htot = I915_READ(HTOTAL(pipe));
6155 int hsync = I915_READ(HSYNC(pipe));
6156 int vtot = I915_READ(VTOTAL(pipe));
6157 int vsync = I915_READ(VSYNC(pipe));
79e53945
JB		 6158
6159 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6160 if (!mode)
6161 return NULL;
6162
6163 mode->clock = intel_crtc_clock_get(dev, crtc);
6164 mode->hdisplay = (htot & 0xffff) + 1;
6165 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6166 mode->hsync_start = (hsync & 0xffff) + 1;
6167 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6168 mode->vdisplay = (vtot & 0xffff) + 1;
6169 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6170 mode->vsync_start = (vsync & 0xffff) + 1;
6171 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6172
6173 drm_mode_set_name(mode);
6174 drm_mode_set_crtcinfo(mode, 0);
6175
6176 return mode;
6177}
6178
652c393a
JB		 6179#define GPU_IDLE_TIMEOUT 500 /* ms */
6180
6181/* When this timer fires, we've been idle for awhile */
6182static void intel_gpu_idle_timer(unsigned long arg)
6183{
6184 struct drm_device *dev = (struct drm_device *)arg;
6185 drm_i915_private_t *dev_priv = dev->dev_private;
6186
ff7ea4c0
CW		 6187 if (!list_empty(&dev_priv->mm.active_list)) {
6188 /* Still processing requests, so just re-arm the timer. */
6189 mod_timer(&dev_priv->idle_timer, jiffies +
6190 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6191 return;
6192 }
652c393a 6193
ff7ea4c0 6194 dev_priv->busy = false;
01dfba93 6195 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 6196}
6197
652c393a
JB		 6198#define CRTC_IDLE_TIMEOUT 1000 /* ms */
6199
6200static void intel_crtc_idle_timer(unsigned long arg)
6201{
6202 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
6203 struct drm_crtc *crtc = &intel_crtc->base;
6204 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
ff7ea4c0 6205 struct intel_framebuffer *intel_fb;
652c393a 6206
ff7ea4c0
CW		 6207 intel_fb = to_intel_framebuffer(crtc->fb);
6208 if (intel_fb && intel_fb->obj->active) {
6209 /* The framebuffer is still being accessed by the GPU. */
6210 mod_timer(&intel_crtc->idle_timer, jiffies +
6211 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6212 return;
6213 }
652c393a 6214
ff7ea4c0 6215 intel_crtc->busy = false;
01dfba93 6216 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 6217}
6218
3dec0095 6219static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6220{
6221 struct drm_device *dev = crtc->dev;
6222 drm_i915_private_t *dev_priv = dev->dev_private;
6223 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6224 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6225 int dpll_reg = DPLL(pipe);
6226 int dpll;
652c393a 6227
bad720ff 6228 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6229 return;
6230
6231 if (!dev_priv->lvds_downclock_avail)
6232 return;
6233
dbdc6479 6234 dpll = I915_READ(dpll_reg);
652c393a 6235 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6236 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a
JB		 6237
6238 /* Unlock panel regs */
dbdc6479
JB		 6239 I915_WRITE(PP_CONTROL,
6240 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
652c393a
JB		 6241
6242 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6243 I915_WRITE(dpll_reg, dpll);
9d0498a2 6244 intel_wait_for_vblank(dev, pipe);
dbdc6479 6245
652c393a
JB		 6246 dpll = I915_READ(dpll_reg);
6247 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6248 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a
JB		 6249
6250 /* ...and lock them again */
6251 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6252 }
6253
6254 /* Schedule downclock */
3dec0095
DV		 6255 mod_timer(&intel_crtc->idle_timer, jiffies +
6256 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
652c393a
JB		 6257}
6258
6259static void intel_decrease_pllclock(struct drm_crtc *crtc)
6260{
6261 struct drm_device *dev = crtc->dev;
6262 drm_i915_private_t *dev_priv = dev->dev_private;
6263 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6264 int pipe = intel_crtc->pipe;
9db4a9c7 6265 int dpll_reg = DPLL(pipe);
652c393a
JB		 6266 int dpll = I915_READ(dpll_reg);
6267
bad720ff 6268 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6269 return;
6270
6271 if (!dev_priv->lvds_downclock_avail)
6272 return;
6273
6274 /*
6275 * Since this is called by a timer, we should never get here in
6276 * the manual case.
6277 */
6278 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
44d98a61 6279 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a
JB		 6280
6281 /* Unlock panel regs */
4a655f04
JB		 6282 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
6283 PANEL_UNLOCK_REGS);
652c393a
JB		 6284
6285 dpll |= DISPLAY_RATE_SELECT_FPA1;
6286 I915_WRITE(dpll_reg, dpll);
9d0498a2 6287 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6288 dpll = I915_READ(dpll_reg);
6289 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6290 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6291
6292 /* ...and lock them again */
6293 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6294 }
6295
6296}
6297
6298/**
6299 * intel_idle_update - adjust clocks for idleness
6300 * @work: work struct
6301 *
6302 * Either the GPU or display (or both) went idle. Check the busy status
6303 * here and adjust the CRTC and GPU clocks as necessary.
6304 */
6305static void intel_idle_update(struct work_struct *work)
6306{
6307 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
6308 idle_work);
6309 struct drm_device *dev = dev_priv->dev;
6310 struct drm_crtc *crtc;
6311 struct intel_crtc *intel_crtc;
6312
6313 if (!i915_powersave)
6314 return;
6315
6316 mutex_lock(&dev->struct_mutex);
6317
7648fa99
JB		 6318 i915_update_gfx_val(dev_priv);
6319
652c393a
JB		 6320 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6321 /* Skip inactive CRTCs */
6322 if (!crtc->fb)
6323 continue;
6324
6325 intel_crtc = to_intel_crtc(crtc);
6326 if (!intel_crtc->busy)
6327 intel_decrease_pllclock(crtc);
6328 }
6329
45ac22c8 6330
652c393a
JB		 6331 mutex_unlock(&dev->struct_mutex);
6332}
6333
6334/**
6335 * intel_mark_busy - mark the GPU and possibly the display busy
6336 * @dev: drm device
6337 * @obj: object we're operating on
6338 *
6339 * Callers can use this function to indicate that the GPU is busy processing
6340 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
6341 * buffer), we'll also mark the display as busy, so we know to increase its
6342 * clock frequency.
6343 */
05394f39 6344void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
652c393a
JB		 6345{
6346 drm_i915_private_t *dev_priv = dev->dev_private;
6347 struct drm_crtc *crtc = NULL;
6348 struct intel_framebuffer *intel_fb;
6349 struct intel_crtc *intel_crtc;
6350
5e17ee74
ZW		 6351 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6352 return;
6353
18b2190c 6354 if (!dev_priv->busy)
28cf798f 6355 dev_priv->busy = true;
18b2190c 6356 else
28cf798f
CW		 6357 mod_timer(&dev_priv->idle_timer, jiffies +
6358 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
652c393a
JB		 6359
6360 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6361 if (!crtc->fb)
6362 continue;
6363
6364 intel_crtc = to_intel_crtc(crtc);
6365 intel_fb = to_intel_framebuffer(crtc->fb);
6366 if (intel_fb->obj == obj) {
6367 if (!intel_crtc->busy) {
6368 /* Non-busy -> busy, upclock */
3dec0095 6369 intel_increase_pllclock(crtc);
652c393a
JB		 6370 intel_crtc->busy = true;
6371 } else {
6372 /* Busy -> busy, put off timer */
6373 mod_timer(&intel_crtc->idle_timer, jiffies +
6374 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6375 }
6376 }
6377 }
6378}
6379
79e53945
JB		 6380static void intel_crtc_destroy(struct drm_crtc *crtc)
6381{
6382 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6383 struct drm_device *dev = crtc->dev;
6384 struct intel_unpin_work *work;
6385 unsigned long flags;
6386
6387 spin_lock_irqsave(&dev->event_lock, flags);
6388 work = intel_crtc->unpin_work;
6389 intel_crtc->unpin_work = NULL;
6390 spin_unlock_irqrestore(&dev->event_lock, flags);
6391
6392 if (work) {
6393 cancel_work_sync(&work->work);
6394 kfree(work);
6395 }
79e53945
JB		 6396
6397 drm_crtc_cleanup(crtc);
67e77c5a 6398
79e53945
JB		 6399 kfree(intel_crtc);
6400}
6401
6b95a207
KH		 6402static void intel_unpin_work_fn(struct work_struct *__work)
6403{
6404 struct intel_unpin_work *work =
6405 container_of(__work, struct intel_unpin_work, work);
6406
6407 mutex_lock(&work->dev->struct_mutex);
b1b87f6b 6408 i915_gem_object_unpin(work->old_fb_obj);
05394f39
CW		 6409 drm_gem_object_unreference(&work->pending_flip_obj->base);
6410 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6411
7782de3b 6412 intel_update_fbc(work->dev);
6b95a207
KH		 6413 mutex_unlock(&work->dev->struct_mutex);
6414 kfree(work);
6415}
6416
1afe3e9d 6417static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6418 struct drm_crtc *crtc)
6b95a207
KH		 6419{
6420 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6421 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6422 struct intel_unpin_work *work;
05394f39 6423 struct drm_i915_gem_object *obj;
6b95a207 6424 struct drm_pending_vblank_event *e;
49b14a5c 6425 struct timeval tnow, tvbl;
6b95a207
KH		 6426 unsigned long flags;
6427
6428 /* Ignore early vblank irqs */
6429 if (intel_crtc == NULL)
6430 return;
6431
49b14a5c
MK		 6432 do_gettimeofday(&tnow);
6433
6b95a207
KH		 6434 spin_lock_irqsave(&dev->event_lock, flags);
6435 work = intel_crtc->unpin_work;
6436 if (work == NULL || !work->pending) {
6437 spin_unlock_irqrestore(&dev->event_lock, flags);
6438 return;
6439 }
6440
6441 intel_crtc->unpin_work = NULL;
6b95a207
KH		 6442
6443 if (work->event) {
6444 e = work->event;
49b14a5c 6445 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df
MK		 6446
6447 /* Called before vblank count and timestamps have
6448 * been updated for the vblank interval of flip
6449 * completion? Need to increment vblank count and
6450 * add one videorefresh duration to returned timestamp
49b14a5c
MK		 6451 * to account for this. We assume this happened if we
6452 * get called over 0.9 frame durations after the last
6453 * timestamped vblank.
6454 *
6455 * This calculation can not be used with vrefresh rates
6456 * below 5Hz (10Hz to be on the safe side) without
6457 * promoting to 64 integers.
0af7e4df 6458 */
49b14a5c
MK		 6459 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6460 9 * crtc->framedur_ns) {
0af7e4df 6461 e->event.sequence++;
49b14a5c
MK		 6462 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6463 crtc->framedur_ns);
0af7e4df
MK		 6464 }
6465
49b14a5c
MK		 6466 e->event.tv_sec = tvbl.tv_sec;
6467 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 6468
6b95a207
KH		 6469 list_add_tail(&e->base.link,
6470 &e->base.file_priv->event_list);
6471 wake_up_interruptible(&e->base.file_priv->event_wait);
6472 }
6473
0af7e4df
MK		 6474 drm_vblank_put(dev, intel_crtc->pipe);
6475
6b95a207
KH		 6476 spin_unlock_irqrestore(&dev->event_lock, flags);
6477
05394f39 6478 obj = work->old_fb_obj;
d9e86c0e 6479
e59f2bac 6480 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW		 6481 &obj->pending_flip.counter);
6482 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 6483 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 6484
6b95a207 6485 schedule_work(&work->work);
e5510fac
JB		 6486
6487 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6488}
6489
1afe3e9d
JB		 6490void intel_finish_page_flip(struct drm_device *dev, int pipe)
6491{
6492 drm_i915_private_t *dev_priv = dev->dev_private;
6493 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6494
49b14a5c 6495 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6496}
6497
6498void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6499{
6500 drm_i915_private_t *dev_priv = dev->dev_private;
6501 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6502
49b14a5c 6503 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6504}
6505
6b95a207
KH		 6506void intel_prepare_page_flip(struct drm_device *dev, int plane)
6507{
6508 drm_i915_private_t *dev_priv = dev->dev_private;
6509 struct intel_crtc *intel_crtc =
6510 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6511 unsigned long flags;
6512
6513 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 6514 if (intel_crtc->unpin_work) {
4e5359cd
SF		 6515 if ((++intel_crtc->unpin_work->pending) > 1)
6516 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 6517 } else {
6518 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6519 }
6b95a207
KH		 6520 spin_unlock_irqrestore(&dev->event_lock, flags);
6521}
6522
8c9f3aaf
JB		 6523static int intel_gen2_queue_flip(struct drm_device *dev,
6524 struct drm_crtc *crtc,
6525 struct drm_framebuffer *fb,
6526 struct drm_i915_gem_object *obj)
6527{
6528 struct drm_i915_private *dev_priv = dev->dev_private;
6529 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6530 unsigned long offset;
6531 u32 flip_mask;
6532 int ret;
6533
6534 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6535 if (ret)
6536 goto out;
6537
6538 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6539 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6540
6541 ret = BEGIN_LP_RING(6);
6542 if (ret)
6543 goto out;
6544
6545 /* Can't queue multiple flips, so wait for the previous
6546 * one to finish before executing the next.
6547 */
6548 if (intel_crtc->plane)
6549 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6550 else
6551 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6552 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6553 OUT_RING(MI_NOOP);
6554 OUT_RING(MI_DISPLAY_FLIP |
6555 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6556 OUT_RING(fb->pitch);
6557 OUT_RING(obj->gtt_offset + offset);
6558 OUT_RING(MI_NOOP);
6559 ADVANCE_LP_RING();
6560out:
6561 return ret;
6562}
6563
6564static int intel_gen3_queue_flip(struct drm_device *dev,
6565 struct drm_crtc *crtc,
6566 struct drm_framebuffer *fb,
6567 struct drm_i915_gem_object *obj)
6568{
6569 struct drm_i915_private *dev_priv = dev->dev_private;
6570 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6571 unsigned long offset;
6572 u32 flip_mask;
6573 int ret;
6574
6575 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6576 if (ret)
6577 goto out;
6578
6579 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6580 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6581
6582 ret = BEGIN_LP_RING(6);
6583 if (ret)
6584 goto out;
6585
6586 if (intel_crtc->plane)
6587 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6588 else
6589 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6590 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6591 OUT_RING(MI_NOOP);
6592 OUT_RING(MI_DISPLAY_FLIP_I915 |
6593 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6594 OUT_RING(fb->pitch);
6595 OUT_RING(obj->gtt_offset + offset);
6596 OUT_RING(MI_NOOP);
6597
6598 ADVANCE_LP_RING();
6599out:
6600 return ret;
6601}
6602
6603static int intel_gen4_queue_flip(struct drm_device *dev,
6604 struct drm_crtc *crtc,
6605 struct drm_framebuffer *fb,
6606 struct drm_i915_gem_object *obj)
6607{
6608 struct drm_i915_private *dev_priv = dev->dev_private;
6609 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6610 uint32_t pf, pipesrc;
6611 int ret;
6612
6613 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6614 if (ret)
6615 goto out;
6616
6617 ret = BEGIN_LP_RING(4);
6618 if (ret)
6619 goto out;
6620
6621 /* i965+ uses the linear or tiled offsets from the
6622 * Display Registers (which do not change across a page-flip)
6623 * so we need only reprogram the base address.
6624 */
6625 OUT_RING(MI_DISPLAY_FLIP |
6626 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6627 OUT_RING(fb->pitch);
6628 OUT_RING(obj->gtt_offset | obj->tiling_mode);
6629
6630 /* XXX Enabling the panel-fitter across page-flip is so far
6631 * untested on non-native modes, so ignore it for now.
6632 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6633 */
6634 pf = 0;
6635 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6636 OUT_RING(pf | pipesrc);
6637 ADVANCE_LP_RING();
6638out:
6639 return ret;
6640}
6641
6642static int intel_gen6_queue_flip(struct drm_device *dev,
6643 struct drm_crtc *crtc,
6644 struct drm_framebuffer *fb,
6645 struct drm_i915_gem_object *obj)
6646{
6647 struct drm_i915_private *dev_priv = dev->dev_private;
6648 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6649 uint32_t pf, pipesrc;
6650 int ret;
6651
6652 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6653 if (ret)
6654 goto out;
6655
6656 ret = BEGIN_LP_RING(4);
6657 if (ret)
6658 goto out;
6659
6660 OUT_RING(MI_DISPLAY_FLIP |
6661 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6662 OUT_RING(fb->pitch | obj->tiling_mode);
6663 OUT_RING(obj->gtt_offset);
6664
6665 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6666 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6667 OUT_RING(pf | pipesrc);
6668 ADVANCE_LP_RING();
6669out:
6670 return ret;
6671}
6672
7c9017e5
JB		 6673/*
6674 * On gen7 we currently use the blit ring because (in early silicon at least)
6675 * the render ring doesn't give us interrpts for page flip completion, which
6676 * means clients will hang after the first flip is queued. Fortunately the
6677 * blit ring generates interrupts properly, so use it instead.
6678 */
6679static int intel_gen7_queue_flip(struct drm_device *dev,
6680 struct drm_crtc *crtc,
6681 struct drm_framebuffer *fb,
6682 struct drm_i915_gem_object *obj)
6683{
6684 struct drm_i915_private *dev_priv = dev->dev_private;
6685 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6686 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6687 int ret;
6688
6689 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6690 if (ret)
6691 goto out;
6692
6693 ret = intel_ring_begin(ring, 4);
6694 if (ret)
6695 goto out;
6696
6697 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
6698 intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));
6699 intel_ring_emit(ring, (obj->gtt_offset));
6700 intel_ring_emit(ring, (MI_NOOP));
6701 intel_ring_advance(ring);
6702out:
6703 return ret;
6704}
6705
8c9f3aaf
JB		 6706static int intel_default_queue_flip(struct drm_device *dev,
6707 struct drm_crtc *crtc,
6708 struct drm_framebuffer *fb,
6709 struct drm_i915_gem_object *obj)
6710{
6711 return -ENODEV;
6712}
6713
6b95a207
KH		 6714static int intel_crtc_page_flip(struct drm_crtc *crtc,
6715 struct drm_framebuffer *fb,
6716 struct drm_pending_vblank_event *event)
6717{
6718 struct drm_device *dev = crtc->dev;
6719 struct drm_i915_private *dev_priv = dev->dev_private;
6720 struct intel_framebuffer *intel_fb;
05394f39 6721 struct drm_i915_gem_object *obj;
6b95a207
KH		 6722 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6723 struct intel_unpin_work *work;
8c9f3aaf 6724 unsigned long flags;
52e68630 6725 int ret;
6b95a207
KH		 6726
6727 work = kzalloc(sizeof *work, GFP_KERNEL);
6728 if (work == NULL)
6729 return -ENOMEM;
6730
6b95a207
KH		 6731 work->event = event;
6732 work->dev = crtc->dev;
6733 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 6734 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 6735 INIT_WORK(&work->work, intel_unpin_work_fn);
6736
6737 /* We borrow the event spin lock for protecting unpin_work */
6738 spin_lock_irqsave(&dev->event_lock, flags);
6739 if (intel_crtc->unpin_work) {
6740 spin_unlock_irqrestore(&dev->event_lock, flags);
6741 kfree(work);
468f0b44
CW		 6742
6743 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 6744 return -EBUSY;
6745 }
6746 intel_crtc->unpin_work = work;
6747 spin_unlock_irqrestore(&dev->event_lock, flags);
6748
6749 intel_fb = to_intel_framebuffer(fb);
6750 obj = intel_fb->obj;
6751
468f0b44 6752 mutex_lock(&dev->struct_mutex);
6b95a207 6753
75dfca80 6754 /* Reference the objects for the scheduled work. */
05394f39
CW		 6755 drm_gem_object_reference(&work->old_fb_obj->base);
6756 drm_gem_object_reference(&obj->base);
6b95a207
KH		 6757
6758 crtc->fb = fb;
96b099fd
CW		 6759
6760 ret = drm_vblank_get(dev, intel_crtc->pipe);
6761 if (ret)
6762 goto cleanup_objs;
6763
e1f99ce6 6764 work->pending_flip_obj = obj;
e1f99ce6 6765
4e5359cd
SF		 6766 work->enable_stall_check = true;
6767
e1f99ce6
CW		 6768 /* Block clients from rendering to the new back buffer until
6769 * the flip occurs and the object is no longer visible.
6770 */
05394f39 6771 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 6772
8c9f3aaf
JB		 6773 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6774 if (ret)
6775 goto cleanup_pending;
6b95a207 6776
7782de3b 6777 intel_disable_fbc(dev);
6b95a207
KH		 6778 mutex_unlock(&dev->struct_mutex);
6779
e5510fac
JB		 6780 trace_i915_flip_request(intel_crtc->plane, obj);
6781
6b95a207 6782 return 0;
96b099fd 6783
8c9f3aaf
JB		 6784cleanup_pending:
6785 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
96b099fd 6786cleanup_objs:
05394f39
CW		 6787 drm_gem_object_unreference(&work->old_fb_obj->base);
6788 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 6789 mutex_unlock(&dev->struct_mutex);
6790
6791 spin_lock_irqsave(&dev->event_lock, flags);
6792 intel_crtc->unpin_work = NULL;
6793 spin_unlock_irqrestore(&dev->event_lock, flags);
6794
6795 kfree(work);
6796
6797 return ret;
6b95a207
KH		 6798}
6799
47f1c6c9
CW		 6800static void intel_sanitize_modesetting(struct drm_device *dev,
6801 int pipe, int plane)
6802{
6803 struct drm_i915_private *dev_priv = dev->dev_private;
6804 u32 reg, val;
6805
6806 if (HAS_PCH_SPLIT(dev))
6807 return;
6808
6809 /* Who knows what state these registers were left in by the BIOS or
6810 * grub?
6811 *
6812 * If we leave the registers in a conflicting state (e.g. with the
6813 * display plane reading from the other pipe than the one we intend
6814 * to use) then when we attempt to teardown the active mode, we will
6815 * not disable the pipes and planes in the correct order -- leaving
6816 * a plane reading from a disabled pipe and possibly leading to
6817 * undefined behaviour.
6818 */
6819
6820 reg = DSPCNTR(plane);
6821 val = I915_READ(reg);
6822
6823 if ((val & DISPLAY_PLANE_ENABLE) == 0)
6824 return;
6825 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6826 return;
6827
6828 /* This display plane is active and attached to the other CPU pipe. */
6829 pipe = !pipe;
6830
6831 /* Disable the plane and wait for it to stop reading from the pipe. */
b24e7179
JB		 6832 intel_disable_plane(dev_priv, plane, pipe);
6833 intel_disable_pipe(dev_priv, pipe);
47f1c6c9 6834}
79e53945 6835
f6e5b160
CW		 6836static void intel_crtc_reset(struct drm_crtc *crtc)
6837{
6838 struct drm_device *dev = crtc->dev;
6839 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6840
6841 /* Reset flags back to the 'unknown' status so that they
6842 * will be correctly set on the initial modeset.
6843 */
6844 intel_crtc->dpms_mode = -1;
6845
6846 /* We need to fix up any BIOS configuration that conflicts with
6847 * our expectations.
6848 */
6849 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6850}
6851
6852static struct drm_crtc_helper_funcs intel_helper_funcs = {
6853 .dpms = intel_crtc_dpms,
6854 .mode_fixup = intel_crtc_mode_fixup,
6855 .mode_set = intel_crtc_mode_set,
6856 .mode_set_base = intel_pipe_set_base,
6857 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6858 .load_lut = intel_crtc_load_lut,
6859 .disable = intel_crtc_disable,
6860};
6861
6862static const struct drm_crtc_funcs intel_crtc_funcs = {
6863 .reset = intel_crtc_reset,
6864 .cursor_set = intel_crtc_cursor_set,
6865 .cursor_move = intel_crtc_cursor_move,
6866 .gamma_set = intel_crtc_gamma_set,
6867 .set_config = drm_crtc_helper_set_config,
6868 .destroy = intel_crtc_destroy,
6869 .page_flip = intel_crtc_page_flip,
6870};
6871
b358d0a6 6872static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 6873{
22fd0fab 6874 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 6875 struct intel_crtc *intel_crtc;
6876 int i;
6877
6878 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6879 if (intel_crtc == NULL)
6880 return;
6881
6882 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6883
6884 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 6885 for (i = 0; i < 256; i++) {
6886 intel_crtc->lut_r[i] = i;
6887 intel_crtc->lut_g[i] = i;
6888 intel_crtc->lut_b[i] = i;
6889 }
6890
80824003
JB		 6891 /* Swap pipes & planes for FBC on pre-965 */
6892 intel_crtc->pipe = pipe;
6893 intel_crtc->plane = pipe;
e2e767ab 6894 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 6895 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 6896 intel_crtc->plane = !pipe;
80824003
JB		 6897 }
6898
22fd0fab
JB		 6899 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6900 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6901 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6902 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6903
5d1d0cc8 6904 intel_crtc_reset(&intel_crtc->base);
04dbff52 6905 intel_crtc->active = true; /* force the pipe off on setup_init_config */
5a354204 6906 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3
JB		 6907
6908 if (HAS_PCH_SPLIT(dev)) {
6909 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6910 intel_helper_funcs.commit = ironlake_crtc_commit;
6911 } else {
6912 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6913 intel_helper_funcs.commit = i9xx_crtc_commit;
6914 }
6915
79e53945
JB		 6916 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6917
652c393a
JB		 6918 intel_crtc->busy = false;
6919
6920 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6921 (unsigned long)intel_crtc);
79e53945
JB		 6922}
6923
08d7b3d1 6924int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 6925 struct drm_file *file)
08d7b3d1
CW		 6926{
6927 drm_i915_private_t *dev_priv = dev->dev_private;
6928 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 6929 struct drm_mode_object *drmmode_obj;
6930 struct intel_crtc *crtc;
08d7b3d1
CW		 6931
6932 if (!dev_priv) {
6933 DRM_ERROR("called with no initialization\n");
6934 return -EINVAL;
6935 }
6936
c05422d5
DV		 6937 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6938 DRM_MODE_OBJECT_CRTC);
08d7b3d1 6939
c05422d5 6940 if (!drmmode_obj) {
08d7b3d1
CW		 6941 DRM_ERROR("no such CRTC id\n");
6942 return -EINVAL;
6943 }
6944
c05422d5
DV		 6945 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6946 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 6947
c05422d5 6948 return 0;
08d7b3d1
CW		 6949}
6950
c5e4df33 6951static int intel_encoder_clones(struct drm_device *dev, int type_mask)
79e53945 6952{
4ef69c7a 6953 struct intel_encoder *encoder;
79e53945 6954 int index_mask = 0;
79e53945
JB		 6955 int entry = 0;
6956
4ef69c7a
CW		 6957 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6958 if (type_mask & encoder->clone_mask)
79e53945
JB		 6959 index_mask |= (1 << entry);
6960 entry++;
6961 }
4ef69c7a 6962
79e53945
JB		 6963 return index_mask;
6964}
6965
4d302442
CW		 6966static bool has_edp_a(struct drm_device *dev)
6967{
6968 struct drm_i915_private *dev_priv = dev->dev_private;
6969
6970 if (!IS_MOBILE(dev))
6971 return false;
6972
6973 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6974 return false;
6975
6976 if (IS_GEN5(dev) &&
6977 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6978 return false;
6979
6980 return true;
6981}
6982
79e53945
JB		 6983static void intel_setup_outputs(struct drm_device *dev)
6984{
725e30ad 6985 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 6986 struct intel_encoder *encoder;
cb0953d7 6987 bool dpd_is_edp = false;
c5d1b51d 6988 bool has_lvds = false;
79e53945 6989
541998a1 6990 if (IS_MOBILE(dev) && !IS_I830(dev))
c5d1b51d
CW		 6991 has_lvds = intel_lvds_init(dev);
6992 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6993 /* disable the panel fitter on everything but LVDS */
6994 I915_WRITE(PFIT_CONTROL, 0);
6995 }
79e53945 6996
bad720ff 6997 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 6998 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 6999
4d302442 7000 if (has_edp_a(dev))
32f9d658
ZW		 7001 intel_dp_init(dev, DP_A);
7002
cb0953d7
AJ		 7003 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7004 intel_dp_init(dev, PCH_DP_D);
7005 }
7006
7007 intel_crt_init(dev);
7008
7009 if (HAS_PCH_SPLIT(dev)) {
7010 int found;
7011
30ad48b7 7012 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca
ZY		 7013 /* PCH SDVOB multiplex with HDMIB */
7014 found = intel_sdvo_init(dev, PCH_SDVOB);
30ad48b7
ZW		 7015 if (!found)
7016 intel_hdmi_init(dev, HDMIB);
5eb08b69
ZW		 7017 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7018 intel_dp_init(dev, PCH_DP_B);
30ad48b7
ZW		 7019 }
7020
7021 if (I915_READ(HDMIC) & PORT_DETECTED)
7022 intel_hdmi_init(dev, HDMIC);
7023
7024 if (I915_READ(HDMID) & PORT_DETECTED)
7025 intel_hdmi_init(dev, HDMID);
7026
5eb08b69
ZW		 7027 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7028 intel_dp_init(dev, PCH_DP_C);
7029
cb0953d7 7030 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5eb08b69
ZW		 7031 intel_dp_init(dev, PCH_DP_D);
7032
103a196f 7033 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 7034 bool found = false;
7d57382e 7035
725e30ad 7036 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 7037 DRM_DEBUG_KMS("probing SDVOB\n");
725e30ad 7038 found = intel_sdvo_init(dev, SDVOB);
b01f2c3a
JB		 7039 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7040 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
725e30ad 7041 intel_hdmi_init(dev, SDVOB);
b01f2c3a 7042 }
27185ae1 7043
b01f2c3a
JB		 7044 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7045 DRM_DEBUG_KMS("probing DP_B\n");
a4fc5ed6 7046 intel_dp_init(dev, DP_B);
b01f2c3a 7047 }
725e30ad 7048 }
13520b05
KH		 7049
7050 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 7051
b01f2c3a
JB		 7052 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7053 DRM_DEBUG_KMS("probing SDVOC\n");
725e30ad 7054 found = intel_sdvo_init(dev, SDVOC);
b01f2c3a 7055 }
27185ae1
ML		 7056
7057 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7058
b01f2c3a
JB		 7059 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7060 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
725e30ad 7061 intel_hdmi_init(dev, SDVOC);
b01f2c3a
JB		 7062 }
7063 if (SUPPORTS_INTEGRATED_DP(dev)) {
7064 DRM_DEBUG_KMS("probing DP_C\n");
a4fc5ed6 7065 intel_dp_init(dev, DP_C);
b01f2c3a 7066 }
725e30ad 7067 }
27185ae1 7068
b01f2c3a
JB		 7069 if (SUPPORTS_INTEGRATED_DP(dev) &&
7070 (I915_READ(DP_D) & DP_DETECTED)) {
7071 DRM_DEBUG_KMS("probing DP_D\n");
a4fc5ed6 7072 intel_dp_init(dev, DP_D);
b01f2c3a 7073 }
bad720ff 7074 } else if (IS_GEN2(dev))
79e53945
JB		 7075 intel_dvo_init(dev);
7076
103a196f 7077 if (SUPPORTS_TV(dev))
79e53945
JB		 7078 intel_tv_init(dev);
7079
4ef69c7a
CW		 7080 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7081 encoder->base.possible_crtcs = encoder->crtc_mask;
7082 encoder->base.possible_clones =
7083 intel_encoder_clones(dev, encoder->clone_mask);
79e53945 7084 }
47356eb6
CW		 7085
7086 intel_panel_setup_backlight(dev);
2c7111db
CW		 7087
7088 /* disable all the possible outputs/crtcs before entering KMS mode */
7089 drm_helper_disable_unused_functions(dev);
79e53945
JB		 7090}
7091
7092static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7093{
7094 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 7095
7096 drm_framebuffer_cleanup(fb);
05394f39 7097 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 7098
7099 kfree(intel_fb);
7100}
7101
7102static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 7103 struct drm_file *file,
79e53945
JB		 7104 unsigned int *handle)
7105{
7106 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 7107 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 7108
05394f39 7109 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 7110}
7111
7112static const struct drm_framebuffer_funcs intel_fb_funcs = {
7113 .destroy = intel_user_framebuffer_destroy,
7114 .create_handle = intel_user_framebuffer_create_handle,
7115};
7116
38651674
DA		 7117int intel_framebuffer_init(struct drm_device *dev,
7118 struct intel_framebuffer *intel_fb,
7119 struct drm_mode_fb_cmd *mode_cmd,
05394f39 7120 struct drm_i915_gem_object *obj)
79e53945 7121{
79e53945
JB		 7122 int ret;
7123
05394f39 7124 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 7125 return -EINVAL;
7126
7127 if (mode_cmd->pitch & 63)
7128 return -EINVAL;
7129
7130 switch (mode_cmd->bpp) {
7131 case 8:
7132 case 16:
b5626747
JB		 7133 /* Only pre-ILK can handle 5:5:5 */
7134 if (mode_cmd->depth == 15 && !HAS_PCH_SPLIT(dev))
7135 return -EINVAL;
7136 break;
7137
57cd6508
CW		 7138 case 24:
7139 case 32:
7140 break;
7141 default:
7142 return -EINVAL;
7143 }
7144
79e53945
JB		 7145 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7146 if (ret) {
7147 DRM_ERROR("framebuffer init failed %d\n", ret);
7148 return ret;
7149 }
7150
7151 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 7152 intel_fb->obj = obj;
79e53945
JB		 7153 return 0;
7154}
7155
79e53945
JB		 7156static struct drm_framebuffer *
7157intel_user_framebuffer_create(struct drm_device *dev,
7158 struct drm_file *filp,
7159 struct drm_mode_fb_cmd *mode_cmd)
7160{
05394f39 7161 struct drm_i915_gem_object *obj;
79e53945 7162
05394f39 7163 obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
c8725226 7164 if (&obj->base == NULL)
cce13ff7 7165 return ERR_PTR(-ENOENT);
79e53945 7166
d2dff872 7167 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 7168}
7169
79e53945 7170static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 7171 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 7172 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 7173};
7174
05394f39 7175static struct drm_i915_gem_object *
aa40d6bb 7176intel_alloc_context_page(struct drm_device *dev)
9ea8d059 7177{
05394f39 7178 struct drm_i915_gem_object *ctx;
9ea8d059
CW		 7179 int ret;
7180
2c34b850
BW		 7181 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7182
aa40d6bb
ZN		 7183 ctx = i915_gem_alloc_object(dev, 4096);
7184 if (!ctx) {
9ea8d059
CW		 7185 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
7186 return NULL;
7187 }
7188
75e9e915 7189 ret = i915_gem_object_pin(ctx, 4096, true);
9ea8d059
CW		 7190 if (ret) {
7191 DRM_ERROR("failed to pin power context: %d\n", ret);
7192 goto err_unref;
7193 }
7194
aa40d6bb 7195 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
9ea8d059
CW		 7196 if (ret) {
7197 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
7198 goto err_unpin;
7199 }
9ea8d059 7200
aa40d6bb 7201 return ctx;
9ea8d059
CW		 7202
7203err_unpin:
aa40d6bb 7204 i915_gem_object_unpin(ctx);
9ea8d059 7205err_unref:
05394f39 7206 drm_gem_object_unreference(&ctx->base);
9ea8d059
CW		 7207 mutex_unlock(&dev->struct_mutex);
7208 return NULL;
7209}
7210
7648fa99
JB		 7211bool ironlake_set_drps(struct drm_device *dev, u8 val)
7212{
7213 struct drm_i915_private *dev_priv = dev->dev_private;
7214 u16 rgvswctl;
7215
7216 rgvswctl = I915_READ16(MEMSWCTL);
7217 if (rgvswctl & MEMCTL_CMD_STS) {
7218 DRM_DEBUG("gpu busy, RCS change rejected\n");
7219 return false; /* still busy with another command */
7220 }
7221
7222 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7223 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
7224 I915_WRITE16(MEMSWCTL, rgvswctl);
7225 POSTING_READ16(MEMSWCTL);
7226
7227 rgvswctl |= MEMCTL_CMD_STS;
7228 I915_WRITE16(MEMSWCTL, rgvswctl);
7229
7230 return true;
7231}
7232
f97108d1
JB		 7233void ironlake_enable_drps(struct drm_device *dev)
7234{
7235 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 7236 u32 rgvmodectl = I915_READ(MEMMODECTL);
f97108d1 7237 u8 fmax, fmin, fstart, vstart;
f97108d1 7238
ea056c14
JB		 7239 /* Enable temp reporting */
7240 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
7241 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
7242
f97108d1
JB		 7243 /* 100ms RC evaluation intervals */
7244 I915_WRITE(RCUPEI, 100000);
7245 I915_WRITE(RCDNEI, 100000);
7246
7247 /* Set max/min thresholds to 90ms and 80ms respectively */
7248 I915_WRITE(RCBMAXAVG, 90000);
7249 I915_WRITE(RCBMINAVG, 80000);
7250
7251 I915_WRITE(MEMIHYST, 1);
7252
7253 /* Set up min, max, and cur for interrupt handling */
7254 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
7255 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
7256 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
7257 MEMMODE_FSTART_SHIFT;
7648fa99 7258
f97108d1
JB		 7259 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
7260 PXVFREQ_PX_SHIFT;
7261
80dbf4b7 7262 dev_priv->fmax = fmax; /* IPS callback will increase this */
7648fa99
JB		 7263 dev_priv->fstart = fstart;
7264
80dbf4b7 7265 dev_priv->max_delay = fstart;
f97108d1
JB		 7266 dev_priv->min_delay = fmin;
7267 dev_priv->cur_delay = fstart;
7268
80dbf4b7
JB		 7269 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
7270 fmax, fmin, fstart);
7648fa99 7271
f97108d1
JB		 7272 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
7273
7274 /*
7275 * Interrupts will be enabled in ironlake_irq_postinstall
7276 */
7277
7278 I915_WRITE(VIDSTART, vstart);
7279 POSTING_READ(VIDSTART);
7280
7281 rgvmodectl |= MEMMODE_SWMODE_EN;
7282 I915_WRITE(MEMMODECTL, rgvmodectl);
7283
481b6af3 7284 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
913d8d11 7285 DRM_ERROR("stuck trying to change perf mode\n");
f97108d1
JB		 7286 msleep(1);
7287
7648fa99 7288 ironlake_set_drps(dev, fstart);
f97108d1 7289
7648fa99
JB		 7290 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
7291 I915_READ(0x112e0);
7292 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
7293 dev_priv->last_count2 = I915_READ(0x112f4);
7294 getrawmonotonic(&dev_priv->last_time2);
f97108d1
JB		 7295}
7296
7297void ironlake_disable_drps(struct drm_device *dev)
7298{
7299 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 7300 u16 rgvswctl = I915_READ16(MEMSWCTL);
f97108d1
JB		 7301
7302 /* Ack interrupts, disable EFC interrupt */
7303 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
7304 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
7305 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
7306 I915_WRITE(DEIIR, DE_PCU_EVENT);
7307 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
7308
7309 /* Go back to the starting frequency */
7648fa99 7310 ironlake_set_drps(dev, dev_priv->fstart);
f97108d1
JB		 7311 msleep(1);
7312 rgvswctl |= MEMCTL_CMD_STS;
7313 I915_WRITE(MEMSWCTL, rgvswctl);
7314 msleep(1);
7315
7316}
7317
3b8d8d91
JB		 7318void gen6_set_rps(struct drm_device *dev, u8 val)
7319{
7320 struct drm_i915_private *dev_priv = dev->dev_private;
7321 u32 swreq;
7322
7323 swreq = (val & 0x3ff) << 25;
7324 I915_WRITE(GEN6_RPNSWREQ, swreq);
7325}
7326
7327void gen6_disable_rps(struct drm_device *dev)
7328{
7329 struct drm_i915_private *dev_priv = dev->dev_private;
7330
7331 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
7332 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
7333 I915_WRITE(GEN6_PMIER, 0);
4912d041
BW		 7334
7335 spin_lock_irq(&dev_priv->rps_lock);
7336 dev_priv->pm_iir = 0;
7337 spin_unlock_irq(&dev_priv->rps_lock);
7338
3b8d8d91
JB		 7339 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
7340}
7341
7648fa99
JB		 7342static unsigned long intel_pxfreq(u32 vidfreq)
7343{
7344 unsigned long freq;
7345 int div = (vidfreq & 0x3f0000) >> 16;
7346 int post = (vidfreq & 0x3000) >> 12;
7347 int pre = (vidfreq & 0x7);
7348
7349 if (!pre)
7350 return 0;
7351
7352 freq = ((div * 133333) / ((1<<post) * pre));
7353
7354 return freq;
7355}
7356
7357void intel_init_emon(struct drm_device *dev)
7358{
7359 struct drm_i915_private *dev_priv = dev->dev_private;
7360 u32 lcfuse;
7361 u8 pxw[16];
7362 int i;
7363
7364 /* Disable to program */
7365 I915_WRITE(ECR, 0);
7366 POSTING_READ(ECR);
7367
7368 /* Program energy weights for various events */
7369 I915_WRITE(SDEW, 0x15040d00);
7370 I915_WRITE(CSIEW0, 0x007f0000);
7371 I915_WRITE(CSIEW1, 0x1e220004);
7372 I915_WRITE(CSIEW2, 0x04000004);
7373
7374 for (i = 0; i < 5; i++)
7375 I915_WRITE(PEW + (i * 4), 0);
7376 for (i = 0; i < 3; i++)
7377 I915_WRITE(DEW + (i * 4), 0);
7378
7379 /* Program P-state weights to account for frequency power adjustment */
7380 for (i = 0; i < 16; i++) {
7381 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
7382 unsigned long freq = intel_pxfreq(pxvidfreq);
7383 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
7384 PXVFREQ_PX_SHIFT;
7385 unsigned long val;
7386
7387 val = vid * vid;
7388 val *= (freq / 1000);
7389 val *= 255;
7390 val /= (127*127*900);
7391 if (val > 0xff)
7392 DRM_ERROR("bad pxval: %ld\n", val);
7393 pxw[i] = val;
7394 }
7395 /* Render standby states get 0 weight */
7396 pxw[14] = 0;
7397 pxw[15] = 0;
7398
7399 for (i = 0; i < 4; i++) {
7400 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
7401 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
7402 I915_WRITE(PXW + (i * 4), val);
7403 }
7404
7405 /* Adjust magic regs to magic values (more experimental results) */
7406 I915_WRITE(OGW0, 0);
7407 I915_WRITE(OGW1, 0);
7408 I915_WRITE(EG0, 0x00007f00);
7409 I915_WRITE(EG1, 0x0000000e);
7410 I915_WRITE(EG2, 0x000e0000);
7411 I915_WRITE(EG3, 0x68000300);
7412 I915_WRITE(EG4, 0x42000000);
7413 I915_WRITE(EG5, 0x00140031);
7414 I915_WRITE(EG6, 0);
7415 I915_WRITE(EG7, 0);
7416
7417 for (i = 0; i < 8; i++)
7418 I915_WRITE(PXWL + (i * 4), 0);
7419
7420 /* Enable PMON + select events */
7421 I915_WRITE(ECR, 0x80000019);
7422
7423 lcfuse = I915_READ(LCFUSE02);
7424
7425 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
7426}
7427
3b8d8d91 7428void gen6_enable_rps(struct drm_i915_private *dev_priv)
8fd26859 7429{
a6044e23
JB		 7430 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
7431 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
7df8721b 7432 u32 pcu_mbox, rc6_mask = 0;
a6044e23 7433 int cur_freq, min_freq, max_freq;
8fd26859
CW		 7434 int i;
7435
7436 /* Here begins a magic sequence of register writes to enable
7437 * auto-downclocking.
7438 *
7439 * Perhaps there might be some value in exposing these to
7440 * userspace...
7441 */
7442 I915_WRITE(GEN6_RC_STATE, 0);
d1ebd816 7443 mutex_lock(&dev_priv->dev->struct_mutex);
fcca7926 7444 gen6_gt_force_wake_get(dev_priv);
8fd26859 7445
3b8d8d91 7446 /* disable the counters and set deterministic thresholds */
8fd26859
CW		 7447 I915_WRITE(GEN6_RC_CONTROL, 0);
7448
7449 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
7450 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
7451 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
7452 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
7453 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
7454
7455 for (i = 0; i < I915_NUM_RINGS; i++)
7456 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
7457
7458 I915_WRITE(GEN6_RC_SLEEP, 0);
7459 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
7460 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
7461 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
7462 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
7463
7df8721b
JB		 7464 if (i915_enable_rc6)
7465 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
7466 GEN6_RC_CTL_RC6_ENABLE;
7467
8fd26859 7468 I915_WRITE(GEN6_RC_CONTROL,
7df8721b 7469 rc6_mask |
9c3d2f7f 7470 GEN6_RC_CTL_EI_MODE(1) |
8fd26859
CW		 7471 GEN6_RC_CTL_HW_ENABLE);
7472
3b8d8d91 7473 I915_WRITE(GEN6_RPNSWREQ,
8fd26859
CW		 7474 GEN6_FREQUENCY(10) |
7475 GEN6_OFFSET(0) |
7476 GEN6_AGGRESSIVE_TURBO);
7477 I915_WRITE(GEN6_RC_VIDEO_FREQ,
7478 GEN6_FREQUENCY(12));
7479
7480 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7481 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
7482 18 << 24 |
7483 6 << 16);
ccab5c82
JB		 7484 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
7485 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8fd26859 7486 I915_WRITE(GEN6_RP_UP_EI, 100000);
ccab5c82 7487 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8fd26859
CW		 7488 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7489 I915_WRITE(GEN6_RP_CONTROL,
7490 GEN6_RP_MEDIA_TURBO |
7491 GEN6_RP_USE_NORMAL_FREQ |
7492 GEN6_RP_MEDIA_IS_GFX |
7493 GEN6_RP_ENABLE |
ccab5c82
JB		 7494 GEN6_RP_UP_BUSY_AVG |
7495 GEN6_RP_DOWN_IDLE_CONT);
8fd26859
CW		 7496
7497 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7498 500))
7499 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7500
7501 I915_WRITE(GEN6_PCODE_DATA, 0);
7502 I915_WRITE(GEN6_PCODE_MAILBOX,
7503 GEN6_PCODE_READY |
7504 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7505 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7506 500))
7507 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7508
a6044e23
JB		 7509 min_freq = (rp_state_cap & 0xff0000) >> 16;
7510 max_freq = rp_state_cap & 0xff;
7511 cur_freq = (gt_perf_status & 0xff00) >> 8;
7512
7513 /* Check for overclock support */
7514 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7515 500))
7516 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7517 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
7518 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
7519 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7520 500))
7521 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7522 if (pcu_mbox & (1<<31)) { /* OC supported */
7523 max_freq = pcu_mbox & 0xff;
e281fcaa 7524 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
a6044e23
JB		 7525 }
7526
7527 /* In units of 100MHz */
7528 dev_priv->max_delay = max_freq;
7529 dev_priv->min_delay = min_freq;
7530 dev_priv->cur_delay = cur_freq;
7531
8fd26859
CW		 7532 /* requires MSI enabled */
7533 I915_WRITE(GEN6_PMIER,
7534 GEN6_PM_MBOX_EVENT |
7535 GEN6_PM_THERMAL_EVENT |
7536 GEN6_PM_RP_DOWN_TIMEOUT |
7537 GEN6_PM_RP_UP_THRESHOLD |
7538 GEN6_PM_RP_DOWN_THRESHOLD |
7539 GEN6_PM_RP_UP_EI_EXPIRED |
7540 GEN6_PM_RP_DOWN_EI_EXPIRED);
4912d041
BW		 7541 spin_lock_irq(&dev_priv->rps_lock);
7542 WARN_ON(dev_priv->pm_iir != 0);
3b8d8d91 7543 I915_WRITE(GEN6_PMIMR, 0);
4912d041 7544 spin_unlock_irq(&dev_priv->rps_lock);
3b8d8d91
JB		 7545 /* enable all PM interrupts */
7546 I915_WRITE(GEN6_PMINTRMSK, 0);
8fd26859 7547
fcca7926 7548 gen6_gt_force_wake_put(dev_priv);
d1ebd816 7549 mutex_unlock(&dev_priv->dev->struct_mutex);
8fd26859
CW		 7550}
7551
23b2f8bb
JB		 7552void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
7553{
7554 int min_freq = 15;
7555 int gpu_freq, ia_freq, max_ia_freq;
7556 int scaling_factor = 180;
7557
7558 max_ia_freq = cpufreq_quick_get_max(0);
7559 /*
7560 * Default to measured freq if none found, PCU will ensure we don't go
7561 * over
7562 */
7563 if (!max_ia_freq)
7564 max_ia_freq = tsc_khz;
7565
7566 /* Convert from kHz to MHz */
7567 max_ia_freq /= 1000;
7568
7569 mutex_lock(&dev_priv->dev->struct_mutex);
7570
7571 /*
7572 * For each potential GPU frequency, load a ring frequency we'd like
7573 * to use for memory access. We do this by specifying the IA frequency
7574 * the PCU should use as a reference to determine the ring frequency.
7575 */
7576 for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
7577 gpu_freq--) {
7578 int diff = dev_priv->max_delay - gpu_freq;
7579
7580 /*
7581 * For GPU frequencies less than 750MHz, just use the lowest
7582 * ring freq.
7583 */
7584 if (gpu_freq < min_freq)
7585 ia_freq = 800;
7586 else
7587 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
7588 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
7589
7590 I915_WRITE(GEN6_PCODE_DATA,
7591 (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
7592 gpu_freq);
7593 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
7594 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7595 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
7596 GEN6_PCODE_READY) == 0, 10)) {
7597 DRM_ERROR("pcode write of freq table timed out\n");
7598 continue;
7599 }
7600 }
7601
7602 mutex_unlock(&dev_priv->dev->struct_mutex);
7603}
7604
6067aaea
JB		 7605static void ironlake_init_clock_gating(struct drm_device *dev)
7606{
7607 struct drm_i915_private *dev_priv = dev->dev_private;
7608 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7609
7610 /* Required for FBC */
7611 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
7612 DPFCRUNIT_CLOCK_GATE_DISABLE |
7613 DPFDUNIT_CLOCK_GATE_DISABLE;
7614 /* Required for CxSR */
7615 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
7616
7617 I915_WRITE(PCH_3DCGDIS0,
7618 MARIUNIT_CLOCK_GATE_DISABLE |
7619 SVSMUNIT_CLOCK_GATE_DISABLE);
7620 I915_WRITE(PCH_3DCGDIS1,
7621 VFMUNIT_CLOCK_GATE_DISABLE);
7622
7623 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7624
6067aaea
JB		 7625 /*
7626 * According to the spec the following bits should be set in
7627 * order to enable memory self-refresh
7628 * The bit 22/21 of 0x42004
7629 * The bit 5 of 0x42020
7630 * The bit 15 of 0x45000
7631 */
7632 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7633 (I915_READ(ILK_DISPLAY_CHICKEN2) |
7634 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
7635 I915_WRITE(ILK_DSPCLK_GATE,
7636 (I915_READ(ILK_DSPCLK_GATE) |
7637 ILK_DPARB_CLK_GATE));
7638 I915_WRITE(DISP_ARB_CTL,
7639 (I915_READ(DISP_ARB_CTL) |
7640 DISP_FBC_WM_DIS));
7641 I915_WRITE(WM3_LP_ILK, 0);
7642 I915_WRITE(WM2_LP_ILK, 0);
7643 I915_WRITE(WM1_LP_ILK, 0);
7644
7645 /*
7646 * Based on the document from hardware guys the following bits
7647 * should be set unconditionally in order to enable FBC.
7648 * The bit 22 of 0x42000
7649 * The bit 22 of 0x42004
7650 * The bit 7,8,9 of 0x42020.
7651 */
7652 if (IS_IRONLAKE_M(dev)) {
7653 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7654 I915_READ(ILK_DISPLAY_CHICKEN1) |
7655 ILK_FBCQ_DIS);
7656 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7657 I915_READ(ILK_DISPLAY_CHICKEN2) |
7658 ILK_DPARB_GATE);
7659 I915_WRITE(ILK_DSPCLK_GATE,
7660 I915_READ(ILK_DSPCLK_GATE) |
7661 ILK_DPFC_DIS1 |
7662 ILK_DPFC_DIS2 |
7663 ILK_CLK_FBC);
7664 }
7665
7666 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7667 I915_READ(ILK_DISPLAY_CHICKEN2) |
7668 ILK_ELPIN_409_SELECT);
7669 I915_WRITE(_3D_CHICKEN2,
7670 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
7671 _3D_CHICKEN2_WM_READ_PIPELINED);
8fd26859
CW		 7672}
7673
6067aaea 7674static void gen6_init_clock_gating(struct drm_device *dev)
652c393a
JB		 7675{
7676 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 7677 int pipe;
6067aaea
JB		 7678 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7679
7680 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
652c393a 7681
6067aaea
JB		 7682 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7683 I915_READ(ILK_DISPLAY_CHICKEN2) |
7684 ILK_ELPIN_409_SELECT);
8956c8bb 7685
6067aaea
JB		 7686 I915_WRITE(WM3_LP_ILK, 0);
7687 I915_WRITE(WM2_LP_ILK, 0);
7688 I915_WRITE(WM1_LP_ILK, 0);
652c393a
JB		 7689
7690 /*
6067aaea
JB		 7691 * According to the spec the following bits should be
7692 * set in order to enable memory self-refresh and fbc:
7693 * The bit21 and bit22 of 0x42000
7694 * The bit21 and bit22 of 0x42004
7695 * The bit5 and bit7 of 0x42020
7696 * The bit14 of 0x70180
7697 * The bit14 of 0x71180
652c393a 7698 */
6067aaea
JB		 7699 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7700 I915_READ(ILK_DISPLAY_CHICKEN1) |
7701 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7702 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7703 I915_READ(ILK_DISPLAY_CHICKEN2) |
7704 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7705 I915_WRITE(ILK_DSPCLK_GATE,
7706 I915_READ(ILK_DSPCLK_GATE) |
7707 ILK_DPARB_CLK_GATE |
7708 ILK_DPFD_CLK_GATE);
8956c8bb 7709
6067aaea
JB		 7710 for_each_pipe(pipe)
7711 I915_WRITE(DSPCNTR(pipe),
7712 I915_READ(DSPCNTR(pipe)) |
7713 DISPPLANE_TRICKLE_FEED_DISABLE);
7714}
8956c8bb 7715
28963a3e
JB		 7716static void ivybridge_init_clock_gating(struct drm_device *dev)
7717{
7718 struct drm_i915_private *dev_priv = dev->dev_private;
7719 int pipe;
7720 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7f8a8569 7721
28963a3e 7722 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
382b0936 7723
28963a3e
JB		 7724 I915_WRITE(WM3_LP_ILK, 0);
7725 I915_WRITE(WM2_LP_ILK, 0);
7726 I915_WRITE(WM1_LP_ILK, 0);
de6e2eaf 7727
28963a3e 7728 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
67e92af0 7729
28963a3e
JB		 7730 for_each_pipe(pipe)
7731 I915_WRITE(DSPCNTR(pipe),
7732 I915_READ(DSPCNTR(pipe)) |
7733 DISPPLANE_TRICKLE_FEED_DISABLE);
7734}
7735
6067aaea
JB		 7736static void g4x_init_clock_gating(struct drm_device *dev)
7737{
7738 struct drm_i915_private *dev_priv = dev->dev_private;
7739 uint32_t dspclk_gate;
8fd26859 7740
6067aaea
JB		 7741 I915_WRITE(RENCLK_GATE_D1, 0);
7742 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7743 GS_UNIT_CLOCK_GATE_DISABLE |
7744 CL_UNIT_CLOCK_GATE_DISABLE);
7745 I915_WRITE(RAMCLK_GATE_D, 0);
7746 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7747 OVRUNIT_CLOCK_GATE_DISABLE |
7748 OVCUNIT_CLOCK_GATE_DISABLE;
7749 if (IS_GM45(dev))
7750 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7751 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7752}
1398261a 7753
6067aaea
JB		 7754static void crestline_init_clock_gating(struct drm_device *dev)
7755{
7756 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 7757
6067aaea
JB		 7758 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7759 I915_WRITE(RENCLK_GATE_D2, 0);
7760 I915_WRITE(DSPCLK_GATE_D, 0);
7761 I915_WRITE(RAMCLK_GATE_D, 0);
7762 I915_WRITE16(DEUC, 0);
7763}
652c393a 7764
6067aaea
JB		 7765static void broadwater_init_clock_gating(struct drm_device *dev)
7766{
7767 struct drm_i915_private *dev_priv = dev->dev_private;
7768
7769 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7770 I965_RCC_CLOCK_GATE_DISABLE |
7771 I965_RCPB_CLOCK_GATE_DISABLE |
7772 I965_ISC_CLOCK_GATE_DISABLE |
7773 I965_FBC_CLOCK_GATE_DISABLE);
7774 I915_WRITE(RENCLK_GATE_D2, 0);
7775}
7776
7777static void gen3_init_clock_gating(struct drm_device *dev)
7778{
7779 struct drm_i915_private *dev_priv = dev->dev_private;
7780 u32 dstate = I915_READ(D_STATE);
7781
7782 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7783 DSTATE_DOT_CLOCK_GATING;
7784 I915_WRITE(D_STATE, dstate);
7785}
7786
7787static void i85x_init_clock_gating(struct drm_device *dev)
7788{
7789 struct drm_i915_private *dev_priv = dev->dev_private;
7790
7791 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7792}
7793
7794static void i830_init_clock_gating(struct drm_device *dev)
7795{
7796 struct drm_i915_private *dev_priv = dev->dev_private;
7797
7798 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
652c393a
JB		 7799}
7800
645c62a5
JB		 7801static void ibx_init_clock_gating(struct drm_device *dev)
7802{
7803 struct drm_i915_private *dev_priv = dev->dev_private;
7804
7805 /*
7806 * On Ibex Peak and Cougar Point, we need to disable clock
7807 * gating for the panel power sequencer or it will fail to
7808 * start up when no ports are active.
7809 */
7810 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7811}
7812
7813static void cpt_init_clock_gating(struct drm_device *dev)
7814{
7815 struct drm_i915_private *dev_priv = dev->dev_private;
7816
7817 /*
7818 * On Ibex Peak and Cougar Point, we need to disable clock
7819 * gating for the panel power sequencer or it will fail to
7820 * start up when no ports are active.
7821 */
7822 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7823 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
7824 DPLS_EDP_PPS_FIX_DIS);
652c393a
JB		 7825}
7826
ac668088 7827static void ironlake_teardown_rc6(struct drm_device *dev)
0cdab21f
CW		 7828{
7829 struct drm_i915_private *dev_priv = dev->dev_private;
7830
7831 if (dev_priv->renderctx) {
ac668088
CW		 7832 i915_gem_object_unpin(dev_priv->renderctx);
7833 drm_gem_object_unreference(&dev_priv->renderctx->base);
0cdab21f
CW		 7834 dev_priv->renderctx = NULL;
7835 }
7836
7837 if (dev_priv->pwrctx) {
ac668088
CW		 7838 i915_gem_object_unpin(dev_priv->pwrctx);
7839 drm_gem_object_unreference(&dev_priv->pwrctx->base);
7840 dev_priv->pwrctx = NULL;
7841 }
7842}
7843
7844static void ironlake_disable_rc6(struct drm_device *dev)
7845{
7846 struct drm_i915_private *dev_priv = dev->dev_private;
7847
7848 if (I915_READ(PWRCTXA)) {
7849 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
7850 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
7851 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
7852 50);
0cdab21f
CW		 7853
7854 I915_WRITE(PWRCTXA, 0);
7855 POSTING_READ(PWRCTXA);
7856
ac668088
CW		 7857 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7858 POSTING_READ(RSTDBYCTL);
0cdab21f 7859 }
ac668088 7860
99507307 7861 ironlake_teardown_rc6(dev);
0cdab21f
CW		 7862}
7863
ac668088 7864static int ironlake_setup_rc6(struct drm_device *dev)
d5bb081b
JB		 7865{
7866 struct drm_i915_private *dev_priv = dev->dev_private;
7867
ac668088
CW		 7868 if (dev_priv->renderctx == NULL)
7869 dev_priv->renderctx = intel_alloc_context_page(dev);
7870 if (!dev_priv->renderctx)
7871 return -ENOMEM;
7872
7873 if (dev_priv->pwrctx == NULL)
7874 dev_priv->pwrctx = intel_alloc_context_page(dev);
7875 if (!dev_priv->pwrctx) {
7876 ironlake_teardown_rc6(dev);
7877 return -ENOMEM;
7878 }
7879
7880 return 0;
d5bb081b
JB		 7881}
7882
7883void ironlake_enable_rc6(struct drm_device *dev)
7884{
7885 struct drm_i915_private *dev_priv = dev->dev_private;
7886 int ret;
7887
ac668088
CW		 7888 /* rc6 disabled by default due to repeated reports of hanging during
7889 * boot and resume.
7890 */
7891 if (!i915_enable_rc6)
7892 return;
7893
2c34b850 7894 mutex_lock(&dev->struct_mutex);
ac668088 7895 ret = ironlake_setup_rc6(dev);
2c34b850
BW		 7896 if (ret) {
7897 mutex_unlock(&dev->struct_mutex);
ac668088 7898 return;
2c34b850 7899 }
ac668088 7900
d5bb081b
JB		 7901 /*
7902 * GPU can automatically power down the render unit if given a page
7903 * to save state.
7904 */
7905 ret = BEGIN_LP_RING(6);
7906 if (ret) {
ac668088 7907 ironlake_teardown_rc6(dev);
2c34b850 7908 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 7909 return;
7910 }
ac668088 7911
d5bb081b
JB		 7912 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
7913 OUT_RING(MI_SET_CONTEXT);
7914 OUT_RING(dev_priv->renderctx->gtt_offset |
7915 MI_MM_SPACE_GTT |
7916 MI_SAVE_EXT_STATE_EN |
7917 MI_RESTORE_EXT_STATE_EN |
7918 MI_RESTORE_INHIBIT);
7919 OUT_RING(MI_SUSPEND_FLUSH);
7920 OUT_RING(MI_NOOP);
7921 OUT_RING(MI_FLUSH);
7922 ADVANCE_LP_RING();
7923
4a246cfc
BW		 7924 /*
7925 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
7926 * does an implicit flush, combined with MI_FLUSH above, it should be
7927 * safe to assume that renderctx is valid
7928 */
7929 ret = intel_wait_ring_idle(LP_RING(dev_priv));
7930 if (ret) {
7931 DRM_ERROR("failed to enable ironlake power power savings\n");
7932 ironlake_teardown_rc6(dev);
7933 mutex_unlock(&dev->struct_mutex);
7934 return;
7935 }
7936
d5bb081b
JB		 7937 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
7938 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2c34b850 7939 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 7940}
7941
645c62a5
JB		 7942void intel_init_clock_gating(struct drm_device *dev)
7943{
7944 struct drm_i915_private *dev_priv = dev->dev_private;
7945
7946 dev_priv->display.init_clock_gating(dev);
7947
7948 if (dev_priv->display.init_pch_clock_gating)
7949 dev_priv->display.init_pch_clock_gating(dev);
7950}
ac668088 7951
e70236a8
JB		 7952/* Set up chip specific display functions */
7953static void intel_init_display(struct drm_device *dev)
7954{
7955 struct drm_i915_private *dev_priv = dev->dev_private;
7956
7957 /* We always want a DPMS function */
f564048e 7958 if (HAS_PCH_SPLIT(dev)) {
f2b115e6 7959 dev_priv->display.dpms = ironlake_crtc_dpms;
f564048e 7960 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
17638cd6 7961 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 7962 } else {
e70236a8 7963 dev_priv->display.dpms = i9xx_crtc_dpms;
f564048e 7964 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
17638cd6 7965 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 7966 }
e70236a8 7967
ee5382ae 7968 if (I915_HAS_FBC(dev)) {
9c04f015 7969 if (HAS_PCH_SPLIT(dev)) {
b52eb4dc
ZY		 7970 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7971 dev_priv->display.enable_fbc = ironlake_enable_fbc;
7972 dev_priv->display.disable_fbc = ironlake_disable_fbc;
7973 } else if (IS_GM45(dev)) {
74dff282
JB		 7974 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
7975 dev_priv->display.enable_fbc = g4x_enable_fbc;
7976 dev_priv->display.disable_fbc = g4x_disable_fbc;
a6c45cf0 7977 } else if (IS_CRESTLINE(dev)) {
e70236a8
JB		 7978 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
7979 dev_priv->display.enable_fbc = i8xx_enable_fbc;
7980 dev_priv->display.disable_fbc = i8xx_disable_fbc;
7981 }
74dff282 7982 /* 855GM needs testing */
e70236a8
JB		 7983 }
7984
7985 /* Returns the core display clock speed */
f2b115e6 7986 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
e70236a8
JB		 7987 dev_priv->display.get_display_clock_speed =
7988 i945_get_display_clock_speed;
7989 else if (IS_I915G(dev))
7990 dev_priv->display.get_display_clock_speed =
7991 i915_get_display_clock_speed;
f2b115e6 7992 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 7993 dev_priv->display.get_display_clock_speed =
7994 i9xx_misc_get_display_clock_speed;
7995 else if (IS_I915GM(dev))
7996 dev_priv->display.get_display_clock_speed =
7997 i915gm_get_display_clock_speed;
7998 else if (IS_I865G(dev))
7999 dev_priv->display.get_display_clock_speed =
8000 i865_get_display_clock_speed;
f0f8a9ce 8001 else if (IS_I85X(dev))
e70236a8
JB		 8002 dev_priv->display.get_display_clock_speed =
8003 i855_get_display_clock_speed;
8004 else /* 852, 830 */
8005 dev_priv->display.get_display_clock_speed =
8006 i830_get_display_clock_speed;
8007
8008 /* For FIFO watermark updates */
7f8a8569 8009 if (HAS_PCH_SPLIT(dev)) {
645c62a5
JB		 8010 if (HAS_PCH_IBX(dev))
8011 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8012 else if (HAS_PCH_CPT(dev))
8013 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8014
f00a3ddf 8015 if (IS_GEN5(dev)) {
7f8a8569
ZW		 8016 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8017 dev_priv->display.update_wm = ironlake_update_wm;
8018 else {
8019 DRM_DEBUG_KMS("Failed to get proper latency. "
8020 "Disable CxSR\n");
8021 dev_priv->display.update_wm = NULL;
1398261a 8022 }
674cf967 8023 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
6067aaea 8024 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
1398261a
YL		 8025 } else if (IS_GEN6(dev)) {
8026 if (SNB_READ_WM0_LATENCY()) {
8027 dev_priv->display.update_wm = sandybridge_update_wm;
8028 } else {
8029 DRM_DEBUG_KMS("Failed to read display plane latency. "
8030 "Disable CxSR\n");
8031 dev_priv->display.update_wm = NULL;
7f8a8569 8032 }
674cf967 8033 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
6067aaea 8034 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
357555c0
JB		 8035 } else if (IS_IVYBRIDGE(dev)) {
8036 /* FIXME: detect B0+ stepping and use auto training */
8037 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
fe100d4d
JB		 8038 if (SNB_READ_WM0_LATENCY()) {
8039 dev_priv->display.update_wm = sandybridge_update_wm;
8040 } else {
8041 DRM_DEBUG_KMS("Failed to read display plane latency. "
8042 "Disable CxSR\n");
8043 dev_priv->display.update_wm = NULL;
8044 }
28963a3e 8045 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6067aaea 8046
7f8a8569
ZW		 8047 } else
8048 dev_priv->display.update_wm = NULL;
8049 } else if (IS_PINEVIEW(dev)) {
d4294342 8050 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
95534263 8051 dev_priv->is_ddr3,
d4294342
ZY		 8052 dev_priv->fsb_freq,
8053 dev_priv->mem_freq)) {
8054 DRM_INFO("failed to find known CxSR latency "
95534263 8055 "(found ddr%s fsb freq %d, mem freq %d), "
d4294342 8056 "disabling CxSR\n",
95534263 8057 (dev_priv->is_ddr3 == 1) ? "3": "2",
d4294342
ZY		 8058 dev_priv->fsb_freq, dev_priv->mem_freq);
8059 /* Disable CxSR and never update its watermark again */
8060 pineview_disable_cxsr(dev);
8061 dev_priv->display.update_wm = NULL;
8062 } else
8063 dev_priv->display.update_wm = pineview_update_wm;
95e0ee92 8064 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6067aaea 8065 } else if (IS_G4X(dev)) {
e70236a8 8066 dev_priv->display.update_wm = g4x_update_wm;
6067aaea
JB		 8067 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8068 } else if (IS_GEN4(dev)) {
e70236a8 8069 dev_priv->display.update_wm = i965_update_wm;
6067aaea
JB		 8070 if (IS_CRESTLINE(dev))
8071 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8072 else if (IS_BROADWATER(dev))
8073 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8074 } else if (IS_GEN3(dev)) {
e70236a8
JB		 8075 dev_priv->display.update_wm = i9xx_update_wm;
8076 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6067aaea
JB		 8077 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8078 } else if (IS_I865G(dev)) {
8079 dev_priv->display.update_wm = i830_update_wm;
8080 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8081 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8f4695ed
AJ		 8082 } else if (IS_I85X(dev)) {
8083 dev_priv->display.update_wm = i9xx_update_wm;
8084 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6067aaea 8085 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
e70236a8 8086 } else {
8f4695ed 8087 dev_priv->display.update_wm = i830_update_wm;
6067aaea 8088 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8f4695ed 8089 if (IS_845G(dev))
e70236a8
JB		 8090 dev_priv->display.get_fifo_size = i845_get_fifo_size;
8091 else
8092 dev_priv->display.get_fifo_size = i830_get_fifo_size;
e70236a8 8093 }
8c9f3aaf
JB		 8094
8095 /* Default just returns -ENODEV to indicate unsupported */
8096 dev_priv->display.queue_flip = intel_default_queue_flip;
8097
8098 switch (INTEL_INFO(dev)->gen) {
8099 case 2:
8100 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8101 break;
8102
8103 case 3:
8104 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8105 break;
8106
8107 case 4:
8108 case 5:
8109 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8110 break;
8111
8112 case 6:
8113 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8114 break;
7c9017e5
JB		 8115 case 7:
8116 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8117 break;
8c9f3aaf 8118 }
e70236a8
JB		 8119}
8120
b690e96c
JB		 8121/*
8122 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8123 * resume, or other times. This quirk makes sure that's the case for
8124 * affected systems.
8125 */
8126static void quirk_pipea_force (struct drm_device *dev)
8127{
8128 struct drm_i915_private *dev_priv = dev->dev_private;
8129
8130 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8131 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
8132}
8133
8134struct intel_quirk {
8135 int device;
8136 int subsystem_vendor;
8137 int subsystem_device;
8138 void (*hook)(struct drm_device *dev);
8139};
8140
8141struct intel_quirk intel_quirks[] = {
8142 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
8143 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
8144 /* HP Mini needs pipe A force quirk (LP: #322104) */
8145 { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
8146
8147 /* Thinkpad R31 needs pipe A force quirk */
8148 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
8149 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8150 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8151
8152 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
8153 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
8154 /* ThinkPad X40 needs pipe A force quirk */
8155
8156 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8157 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8158
8159 /* 855 & before need to leave pipe A & dpll A up */
8160 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8161 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8162};
8163
8164static void intel_init_quirks(struct drm_device *dev)
8165{
8166 struct pci_dev *d = dev->pdev;
8167 int i;
8168
8169 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8170 struct intel_quirk *q = &intel_quirks[i];
8171
8172 if (d->device == q->device &&
8173 (d->subsystem_vendor == q->subsystem_vendor ||
8174 q->subsystem_vendor == PCI_ANY_ID) &&
8175 (d->subsystem_device == q->subsystem_device ||
8176 q->subsystem_device == PCI_ANY_ID))
8177 q->hook(dev);
8178 }
8179}
8180
9cce37f4
JB		 8181/* Disable the VGA plane that we never use */
8182static void i915_disable_vga(struct drm_device *dev)
8183{
8184 struct drm_i915_private *dev_priv = dev->dev_private;
8185 u8 sr1;
8186 u32 vga_reg;
8187
8188 if (HAS_PCH_SPLIT(dev))
8189 vga_reg = CPU_VGACNTRL;
8190 else
8191 vga_reg = VGACNTRL;
8192
8193 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8194 outb(1, VGA_SR_INDEX);
8195 sr1 = inb(VGA_SR_DATA);
8196 outb(sr1 | 1<<5, VGA_SR_DATA);
8197 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8198 udelay(300);
8199
8200 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8201 POSTING_READ(vga_reg);
8202}
8203
79e53945
JB		 8204void intel_modeset_init(struct drm_device *dev)
8205{
652c393a 8206 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 8207 int i;
8208
8209 drm_mode_config_init(dev);
8210
8211 dev->mode_config.min_width = 0;
8212 dev->mode_config.min_height = 0;
8213
8214 dev->mode_config.funcs = (void *)&intel_mode_funcs;
8215
b690e96c
JB		 8216 intel_init_quirks(dev);
8217
e70236a8
JB		 8218 intel_init_display(dev);
8219
a6c45cf0
CW		 8220 if (IS_GEN2(dev)) {
8221 dev->mode_config.max_width = 2048;
8222 dev->mode_config.max_height = 2048;
8223 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 8224 dev->mode_config.max_width = 4096;
8225 dev->mode_config.max_height = 4096;
79e53945 8226 } else {
a6c45cf0
CW		 8227 dev->mode_config.max_width = 8192;
8228 dev->mode_config.max_height = 8192;
79e53945 8229 }
35c3047a 8230 dev->mode_config.fb_base = dev->agp->base;
79e53945 8231
28c97730 8232 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 8233 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 8234
a3524f1b 8235 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945
JB		 8236 intel_crtc_init(dev, i);
8237 }
8238
9cce37f4
JB		 8239 /* Just disable it once at startup */
8240 i915_disable_vga(dev);
79e53945 8241 intel_setup_outputs(dev);
652c393a 8242
645c62a5 8243 intel_init_clock_gating(dev);
9cce37f4 8244
7648fa99 8245 if (IS_IRONLAKE_M(dev)) {
f97108d1 8246 ironlake_enable_drps(dev);
7648fa99
JB		 8247 intel_init_emon(dev);
8248 }
f97108d1 8249
1c70c0ce 8250 if (IS_GEN6(dev) || IS_GEN7(dev)) {
3b8d8d91 8251 gen6_enable_rps(dev_priv);
23b2f8bb
JB		 8252 gen6_update_ring_freq(dev_priv);
8253 }
3b8d8d91 8254
652c393a
JB		 8255 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
8256 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
8257 (unsigned long)dev);
2c7111db
CW		 8258}
8259
8260void intel_modeset_gem_init(struct drm_device *dev)
8261{
8262 if (IS_IRONLAKE_M(dev))
8263 ironlake_enable_rc6(dev);
02e792fb
DV		 8264
8265 intel_setup_overlay(dev);
79e53945
JB		 8266}
8267
8268void intel_modeset_cleanup(struct drm_device *dev)
8269{
652c393a
JB		 8270 struct drm_i915_private *dev_priv = dev->dev_private;
8271 struct drm_crtc *crtc;
8272 struct intel_crtc *intel_crtc;
8273
f87ea761 8274 drm_kms_helper_poll_fini(dev);
652c393a
JB		 8275 mutex_lock(&dev->struct_mutex);
8276
723bfd70
JB		 8277 intel_unregister_dsm_handler();
8278
8279
652c393a
JB		 8280 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8281 /* Skip inactive CRTCs */
8282 if (!crtc->fb)
8283 continue;
8284
8285 intel_crtc = to_intel_crtc(crtc);
3dec0095 8286 intel_increase_pllclock(crtc);
652c393a
JB		 8287 }
8288
973d04f9 8289 intel_disable_fbc(dev);
e70236a8 8290
f97108d1
JB		 8291 if (IS_IRONLAKE_M(dev))
8292 ironlake_disable_drps(dev);
1c70c0ce 8293 if (IS_GEN6(dev) || IS_GEN7(dev))
3b8d8d91 8294 gen6_disable_rps(dev);
f97108d1 8295
d5bb081b
JB		 8296 if (IS_IRONLAKE_M(dev))
8297 ironlake_disable_rc6(dev);
0cdab21f 8298
69341a5e
KH		 8299 mutex_unlock(&dev->struct_mutex);
8300
6c0d9350
DV		 8301 /* Disable the irq before mode object teardown, for the irq might
8302 * enqueue unpin/hotplug work. */
8303 drm_irq_uninstall(dev);
8304 cancel_work_sync(&dev_priv->hotplug_work);
8305
1630fe75
CW		 8306 /* flush any delayed tasks or pending work */
8307 flush_scheduled_work();
8308
3dec0095
DV		 8309 /* Shut off idle work before the crtcs get freed. */
8310 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8311 intel_crtc = to_intel_crtc(crtc);
8312 del_timer_sync(&intel_crtc->idle_timer);
8313 }
8314 del_timer_sync(&dev_priv->idle_timer);
8315 cancel_work_sync(&dev_priv->idle_work);
8316
79e53945
JB		 8317 drm_mode_config_cleanup(dev);
8318}
8319
f1c79df3
ZW		 8320/*
8321 * Return which encoder is currently attached for connector.
8322 */
df0e9248 8323struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 8324{
df0e9248
CW		 8325 return &intel_attached_encoder(connector)->base;
8326}
f1c79df3 8327
df0e9248
CW		 8328void intel_connector_attach_encoder(struct intel_connector *connector,
8329 struct intel_encoder *encoder)
8330{
8331 connector->encoder = encoder;
8332 drm_mode_connector_attach_encoder(&connector->base,
8333 &encoder->base);
79e53945 8334}
28d52043
DA		 8335
8336/*
8337 * set vga decode state - true == enable VGA decode
8338 */
8339int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8340{
8341 struct drm_i915_private *dev_priv = dev->dev_private;
8342 u16 gmch_ctrl;
8343
8344 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8345 if (state)
8346 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8347 else
8348 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8349 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8350 return 0;
8351}
c4a1d9e4
CW		 8352
8353#ifdef CONFIG_DEBUG_FS
8354#include <linux/seq_file.h>
8355
8356struct intel_display_error_state {
8357 struct intel_cursor_error_state {
8358 u32 control;
8359 u32 position;
8360 u32 base;
8361 u32 size;
8362 } cursor[2];
8363
8364 struct intel_pipe_error_state {
8365 u32 conf;
8366 u32 source;
8367
8368 u32 htotal;
8369 u32 hblank;
8370 u32 hsync;
8371 u32 vtotal;
8372 u32 vblank;
8373 u32 vsync;
8374 } pipe[2];
8375
8376 struct intel_plane_error_state {
8377 u32 control;
8378 u32 stride;
8379 u32 size;
8380 u32 pos;
8381 u32 addr;
8382 u32 surface;
8383 u32 tile_offset;
8384 } plane[2];
8385};
8386
8387struct intel_display_error_state *
8388intel_display_capture_error_state(struct drm_device *dev)
8389{
8390 drm_i915_private_t *dev_priv = dev->dev_private;
8391 struct intel_display_error_state *error;
8392 int i;
8393
8394 error = kmalloc(sizeof(*error), GFP_ATOMIC);
8395 if (error == NULL)
8396 return NULL;
8397
8398 for (i = 0; i < 2; i++) {
8399 error->cursor[i].control = I915_READ(CURCNTR(i));
8400 error->cursor[i].position = I915_READ(CURPOS(i));
8401 error->cursor[i].base = I915_READ(CURBASE(i));
8402
8403 error->plane[i].control = I915_READ(DSPCNTR(i));
8404 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8405 error->plane[i].size = I915_READ(DSPSIZE(i));
8406 error->plane[i].pos= I915_READ(DSPPOS(i));
8407 error->plane[i].addr = I915_READ(DSPADDR(i));
8408 if (INTEL_INFO(dev)->gen >= 4) {
8409 error->plane[i].surface = I915_READ(DSPSURF(i));
8410 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8411 }
8412
8413 error->pipe[i].conf = I915_READ(PIPECONF(i));
8414 error->pipe[i].source = I915_READ(PIPESRC(i));
8415 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8416 error->pipe[i].hblank = I915_READ(HBLANK(i));
8417 error->pipe[i].hsync = I915_READ(HSYNC(i));
8418 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8419 error->pipe[i].vblank = I915_READ(VBLANK(i));
8420 error->pipe[i].vsync = I915_READ(VSYNC(i));
8421 }
8422
8423 return error;
8424}
8425
8426void
8427intel_display_print_error_state(struct seq_file *m,
8428 struct drm_device *dev,
8429 struct intel_display_error_state *error)
8430{
8431 int i;
8432
8433 for (i = 0; i < 2; i++) {
8434 seq_printf(m, "Pipe [%d]:\n", i);
8435 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
8436 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
8437 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
8438 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
8439 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
8440 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
8441 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
8442 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
8443
8444 seq_printf(m, "Plane [%d]:\n", i);
8445 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
8446 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
8447 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
8448 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
8449 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
8450 if (INTEL_INFO(dev)->gen >= 4) {
8451 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
8452 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
8453 }
8454
8455 seq_printf(m, "Cursor [%d]:\n", i);
8456 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
8457 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
8458 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
8459 }
8460}
8461#endif
Linux kernel - Deliverables
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