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drm/i915: Convert the ddi cdclk code to get_display_clock_speed
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c
MR		 48/* Primary plane formats supported by all gen */
49#define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_C8, \
51 DRM_FORMAT_RGB565, \
52 DRM_FORMAT_XRGB8888, \
53 DRM_FORMAT_ARGB8888
54
55/* Primary plane formats for gen <= 3 */
56static const uint32_t intel_primary_formats_gen2[] = {
57 COMMON_PRIMARY_FORMATS,
58 DRM_FORMAT_XRGB1555,
59 DRM_FORMAT_ARGB1555,
60};
61
62/* Primary plane formats for gen >= 4 */
63static const uint32_t intel_primary_formats_gen4[] = {
64 COMMON_PRIMARY_FORMATS, \
65 DRM_FORMAT_XBGR8888,
66 DRM_FORMAT_ABGR8888,
67 DRM_FORMAT_XRGB2101010,
68 DRM_FORMAT_ARGB2101010,
69 DRM_FORMAT_XBGR2101010,
70 DRM_FORMAT_ABGR2101010,
71};
72
3d7d6510
MR		 73/* Cursor formats */
74static const uint32_t intel_cursor_formats[] = {
75 DRM_FORMAT_ARGB8888,
76};
77
6b383a7f 78static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 79
f1f644dc 80static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 81 struct intel_crtc_state *pipe_config);
18442d08 82static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 83 struct intel_crtc_state *pipe_config);
f1f644dc 84
e7457a9a 85static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
83a57153
ACO		 86 int x, int y, struct drm_framebuffer *old_fb,
87 struct drm_atomic_state *state);
eb1bfe80
JB		 88static int intel_framebuffer_init(struct drm_device *dev,
89 struct intel_framebuffer *ifb,
90 struct drm_mode_fb_cmd2 *mode_cmd,
91 struct drm_i915_gem_object *obj);
5b18e57c
DV		 92static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
93static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 94static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 95 struct intel_link_m_n *m_n,
96 struct intel_link_m_n *m2_n2);
29407aab 97static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 98static void haswell_set_pipeconf(struct drm_crtc *crtc);
99static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 100static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 101 const struct intel_crtc_state *pipe_config);
d288f65f 102static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 103 const struct intel_crtc_state *pipe_config);
ea2c67bb
MR		 104static void intel_begin_crtc_commit(struct drm_crtc *crtc);
105static void intel_finish_crtc_commit(struct drm_crtc *crtc);
e7457a9a 106
0e32b39c
DA		 107static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
108{
109 if (!connector->mst_port)
110 return connector->encoder;
111 else
112 return &connector->mst_port->mst_encoders[pipe]->base;
113}
114
79e53945 115typedef struct {
0206e353 116 int min, max;
79e53945
JB		 117} intel_range_t;
118
119typedef struct {
0206e353
AJ		 120 int dot_limit;
121 int p2_slow, p2_fast;
79e53945
JB		 122} intel_p2_t;
123
d4906093
ML		 124typedef struct intel_limit intel_limit_t;
125struct intel_limit {
0206e353
AJ		 126 intel_range_t dot, vco, n, m, m1, m2, p, p1;
127 intel_p2_t p2;
d4906093 128};
79e53945 129
d2acd215
DV		 130int
131intel_pch_rawclk(struct drm_device *dev)
132{
133 struct drm_i915_private *dev_priv = dev->dev_private;
134
135 WARN_ON(!HAS_PCH_SPLIT(dev));
136
137 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
138}
139
021357ac
CW		 140static inline u32 /* units of 100MHz */
141intel_fdi_link_freq(struct drm_device *dev)
142{
8b99e68c
CW		 143 if (IS_GEN5(dev)) {
144 struct drm_i915_private *dev_priv = dev->dev_private;
145 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
146 } else
147 return 27;
021357ac
CW		 148}
149
5d536e28 150static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 151 .dot = { .min = 25000, .max = 350000 },
9c333719 152 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 153 .n = { .min = 2, .max = 16 },
0206e353
AJ		 154 .m = { .min = 96, .max = 140 },
155 .m1 = { .min = 18, .max = 26 },
156 .m2 = { .min = 6, .max = 16 },
157 .p = { .min = 4, .max = 128 },
158 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 159 .p2 = { .dot_limit = 165000,
160 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 161};
162
5d536e28
DV		 163static const intel_limit_t intel_limits_i8xx_dvo = {
164 .dot = { .min = 25000, .max = 350000 },
9c333719 165 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 166 .n = { .min = 2, .max = 16 },
5d536e28
DV		 167 .m = { .min = 96, .max = 140 },
168 .m1 = { .min = 18, .max = 26 },
169 .m2 = { .min = 6, .max = 16 },
170 .p = { .min = 4, .max = 128 },
171 .p1 = { .min = 2, .max = 33 },
172 .p2 = { .dot_limit = 165000,
173 .p2_slow = 4, .p2_fast = 4 },
174};
175
e4b36699 176static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 177 .dot = { .min = 25000, .max = 350000 },
9c333719 178 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 179 .n = { .min = 2, .max = 16 },
0206e353
AJ		 180 .m = { .min = 96, .max = 140 },
181 .m1 = { .min = 18, .max = 26 },
182 .m2 = { .min = 6, .max = 16 },
183 .p = { .min = 4, .max = 128 },
184 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 185 .p2 = { .dot_limit = 165000,
186 .p2_slow = 14, .p2_fast = 7 },
e4b36699 187};
273e27ca 188
e4b36699 189static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 190 .dot = { .min = 20000, .max = 400000 },
191 .vco = { .min = 1400000, .max = 2800000 },
192 .n = { .min = 1, .max = 6 },
193 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 194 .m1 = { .min = 8, .max = 18 },
195 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 196 .p = { .min = 5, .max = 80 },
197 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 198 .p2 = { .dot_limit = 200000,
199 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 200};
201
202static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 203 .dot = { .min = 20000, .max = 400000 },
204 .vco = { .min = 1400000, .max = 2800000 },
205 .n = { .min = 1, .max = 6 },
206 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 207 .m1 = { .min = 8, .max = 18 },
208 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 209 .p = { .min = 7, .max = 98 },
210 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 211 .p2 = { .dot_limit = 112000,
212 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 213};
214
273e27ca 215
e4b36699 216static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 217 .dot = { .min = 25000, .max = 270000 },
218 .vco = { .min = 1750000, .max = 3500000},
219 .n = { .min = 1, .max = 4 },
220 .m = { .min = 104, .max = 138 },
221 .m1 = { .min = 17, .max = 23 },
222 .m2 = { .min = 5, .max = 11 },
223 .p = { .min = 10, .max = 30 },
224 .p1 = { .min = 1, .max = 3},
225 .p2 = { .dot_limit = 270000,
226 .p2_slow = 10,
227 .p2_fast = 10
044c7c41 228 },
e4b36699
KP		 229};
230
231static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 232 .dot = { .min = 22000, .max = 400000 },
233 .vco = { .min = 1750000, .max = 3500000},
234 .n = { .min = 1, .max = 4 },
235 .m = { .min = 104, .max = 138 },
236 .m1 = { .min = 16, .max = 23 },
237 .m2 = { .min = 5, .max = 11 },
238 .p = { .min = 5, .max = 80 },
239 .p1 = { .min = 1, .max = 8},
240 .p2 = { .dot_limit = 165000,
241 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 242};
243
244static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 245 .dot = { .min = 20000, .max = 115000 },
246 .vco = { .min = 1750000, .max = 3500000 },
247 .n = { .min = 1, .max = 3 },
248 .m = { .min = 104, .max = 138 },
249 .m1 = { .min = 17, .max = 23 },
250 .m2 = { .min = 5, .max = 11 },
251 .p = { .min = 28, .max = 112 },
252 .p1 = { .min = 2, .max = 8 },
253 .p2 = { .dot_limit = 0,
254 .p2_slow = 14, .p2_fast = 14
044c7c41 255 },
e4b36699
KP		 256};
257
258static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 259 .dot = { .min = 80000, .max = 224000 },
260 .vco = { .min = 1750000, .max = 3500000 },
261 .n = { .min = 1, .max = 3 },
262 .m = { .min = 104, .max = 138 },
263 .m1 = { .min = 17, .max = 23 },
264 .m2 = { .min = 5, .max = 11 },
265 .p = { .min = 14, .max = 42 },
266 .p1 = { .min = 2, .max = 6 },
267 .p2 = { .dot_limit = 0,
268 .p2_slow = 7, .p2_fast = 7
044c7c41 269 },
e4b36699
KP		 270};
271
f2b115e6 272static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 273 .dot = { .min = 20000, .max = 400000},
274 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 275 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 276 .n = { .min = 3, .max = 6 },
277 .m = { .min = 2, .max = 256 },
273e27ca 278 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 279 .m1 = { .min = 0, .max = 0 },
280 .m2 = { .min = 0, .max = 254 },
281 .p = { .min = 5, .max = 80 },
282 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 283 .p2 = { .dot_limit = 200000,
284 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 285};
286
f2b115e6 287static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 288 .dot = { .min = 20000, .max = 400000 },
289 .vco = { .min = 1700000, .max = 3500000 },
290 .n = { .min = 3, .max = 6 },
291 .m = { .min = 2, .max = 256 },
292 .m1 = { .min = 0, .max = 0 },
293 .m2 = { .min = 0, .max = 254 },
294 .p = { .min = 7, .max = 112 },
295 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 296 .p2 = { .dot_limit = 112000,
297 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 298};
299
273e27ca
EA		 300/* Ironlake / Sandybridge
301 *
302 * We calculate clock using (register_value + 2) for N/M1/M2, so here
303 * the range value for them is (actual_value - 2).
304 */
b91ad0ec 305static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 306 .dot = { .min = 25000, .max = 350000 },
307 .vco = { .min = 1760000, .max = 3510000 },
308 .n = { .min = 1, .max = 5 },
309 .m = { .min = 79, .max = 127 },
310 .m1 = { .min = 12, .max = 22 },
311 .m2 = { .min = 5, .max = 9 },
312 .p = { .min = 5, .max = 80 },
313 .p1 = { .min = 1, .max = 8 },
314 .p2 = { .dot_limit = 225000,
315 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 316};
317
b91ad0ec 318static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 319 .dot = { .min = 25000, .max = 350000 },
320 .vco = { .min = 1760000, .max = 3510000 },
321 .n = { .min = 1, .max = 3 },
322 .m = { .min = 79, .max = 118 },
323 .m1 = { .min = 12, .max = 22 },
324 .m2 = { .min = 5, .max = 9 },
325 .p = { .min = 28, .max = 112 },
326 .p1 = { .min = 2, .max = 8 },
327 .p2 = { .dot_limit = 225000,
328 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 329};
330
331static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 332 .dot = { .min = 25000, .max = 350000 },
333 .vco = { .min = 1760000, .max = 3510000 },
334 .n = { .min = 1, .max = 3 },
335 .m = { .min = 79, .max = 127 },
336 .m1 = { .min = 12, .max = 22 },
337 .m2 = { .min = 5, .max = 9 },
338 .p = { .min = 14, .max = 56 },
339 .p1 = { .min = 2, .max = 8 },
340 .p2 = { .dot_limit = 225000,
341 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 342};
343
273e27ca 344/* LVDS 100mhz refclk limits. */
b91ad0ec 345static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 346 .dot = { .min = 25000, .max = 350000 },
347 .vco = { .min = 1760000, .max = 3510000 },
348 .n = { .min = 1, .max = 2 },
349 .m = { .min = 79, .max = 126 },
350 .m1 = { .min = 12, .max = 22 },
351 .m2 = { .min = 5, .max = 9 },
352 .p = { .min = 28, .max = 112 },
0206e353 353 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 354 .p2 = { .dot_limit = 225000,
355 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 356};
357
358static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 359 .dot = { .min = 25000, .max = 350000 },
360 .vco = { .min = 1760000, .max = 3510000 },
361 .n = { .min = 1, .max = 3 },
362 .m = { .min = 79, .max = 126 },
363 .m1 = { .min = 12, .max = 22 },
364 .m2 = { .min = 5, .max = 9 },
365 .p = { .min = 14, .max = 42 },
0206e353 366 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 367 .p2 = { .dot_limit = 225000,
368 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 369};
370
dc730512 371static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 372 /*
373 * These are the data rate limits (measured in fast clocks)
374 * since those are the strictest limits we have. The fast
375 * clock and actual rate limits are more relaxed, so checking
376 * them would make no difference.
377 */
378 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 379 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 380 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 381 .m1 = { .min = 2, .max = 3 },
382 .m2 = { .min = 11, .max = 156 },
b99ab663 383 .p1 = { .min = 2, .max = 3 },
5fdc9c49 384 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 385};
386
ef9348c8
CML		 387static const intel_limit_t intel_limits_chv = {
388 /*
389 * These are the data rate limits (measured in fast clocks)
390 * since those are the strictest limits we have. The fast
391 * clock and actual rate limits are more relaxed, so checking
392 * them would make no difference.
393 */
394 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 395 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 396 .n = { .min = 1, .max = 1 },
397 .m1 = { .min = 2, .max = 2 },
398 .m2 = { .min = 24 << 22, .max = 175 << 22 },
399 .p1 = { .min = 2, .max = 4 },
400 .p2 = { .p2_slow = 1, .p2_fast = 14 },
401};
402
6b4bf1c4
VS		 403static void vlv_clock(int refclk, intel_clock_t *clock)
404{
405 clock->m = clock->m1 * clock->m2;
406 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 407 if (WARN_ON(clock->n == 0 || clock->p == 0))
408 return;
fb03ac01
VS		 409 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
410 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
6b4bf1c4
VS		 411}
412
e0638cdf
PZ		 413/**
414 * Returns whether any output on the specified pipe is of the specified type
415 */
4093561b 416bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 417{
409ee761 418 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 419 struct intel_encoder *encoder;
420
409ee761 421 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 422 if (encoder->type == type)
423 return true;
424
425 return false;
426}
427
d0737e1d
ACO		 428/**
429 * Returns whether any output on the specified pipe will have the specified
430 * type after a staged modeset is complete, i.e., the same as
431 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
432 * encoder->crtc.
433 */
a93e255f
ACO		 434static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
435 int type)
d0737e1d 436{
a93e255f
ACO		 437 struct drm_atomic_state *state = crtc_state->base.state;
438 struct drm_connector_state *connector_state;
d0737e1d 439 struct intel_encoder *encoder;
a93e255f
ACO		 440 int i, num_connectors = 0;
441
442 for (i = 0; i < state->num_connector; i++) {
443 if (!state->connectors[i])
444 continue;
445
446 connector_state = state->connector_states[i];
447 if (connector_state->crtc != crtc_state->base.crtc)
448 continue;
449
450 num_connectors++;
d0737e1d 451
a93e255f
ACO		 452 encoder = to_intel_encoder(connector_state->best_encoder);
453 if (encoder->type == type)
d0737e1d 454 return true;
a93e255f
ACO		 455 }
456
457 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 458
459 return false;
460}
461
a93e255f
ACO		 462static const intel_limit_t *
463intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 464{
a93e255f 465 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 466 const intel_limit_t *limit;
b91ad0ec 467
a93e255f 468 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 469 if (intel_is_dual_link_lvds(dev)) {
1b894b59 470 if (refclk == 100000)
b91ad0ec
ZW		 471 limit = &intel_limits_ironlake_dual_lvds_100m;
472 else
473 limit = &intel_limits_ironlake_dual_lvds;
474 } else {
1b894b59 475 if (refclk == 100000)
b91ad0ec
ZW		 476 limit = &intel_limits_ironlake_single_lvds_100m;
477 else
478 limit = &intel_limits_ironlake_single_lvds;
479 }
c6bb3538 480 } else
b91ad0ec 481 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 482
483 return limit;
484}
485
a93e255f
ACO		 486static const intel_limit_t *
487intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 488{
a93e255f 489 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 490 const intel_limit_t *limit;
491
a93e255f 492 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 493 if (intel_is_dual_link_lvds(dev))
e4b36699 494 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 495 else
e4b36699 496 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 497 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
498 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 499 limit = &intel_limits_g4x_hdmi;
a93e255f 500 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 501 limit = &intel_limits_g4x_sdvo;
044c7c41 502 } else /* The option is for other outputs */
e4b36699 503 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 504
505 return limit;
506}
507
a93e255f
ACO		 508static const intel_limit_t *
509intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 510{
a93e255f 511 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 512 const intel_limit_t *limit;
513
bad720ff 514 if (HAS_PCH_SPLIT(dev))
a93e255f 515 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 516 else if (IS_G4X(dev)) {
a93e255f 517 limit = intel_g4x_limit(crtc_state);
f2b115e6 518 } else if (IS_PINEVIEW(dev)) {
a93e255f 519 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 520 limit = &intel_limits_pineview_lvds;
2177832f 521 else
f2b115e6 522 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 523 } else if (IS_CHERRYVIEW(dev)) {
524 limit = &intel_limits_chv;
a0c4da24 525 } else if (IS_VALLEYVIEW(dev)) {
dc730512 526 limit = &intel_limits_vlv;
a6c45cf0 527 } else if (!IS_GEN2(dev)) {
a93e255f 528 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 529 limit = &intel_limits_i9xx_lvds;
530 else
531 limit = &intel_limits_i9xx_sdvo;
79e53945 532 } else {
a93e255f 533 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 534 limit = &intel_limits_i8xx_lvds;
a93e255f 535 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 536 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 537 else
538 limit = &intel_limits_i8xx_dac;
79e53945
JB		 539 }
540 return limit;
541}
542
f2b115e6
AJ		 543/* m1 is reserved as 0 in Pineview, n is a ring counter */
544static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 545{
2177832f
SL		 546 clock->m = clock->m2 + 2;
547 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 548 if (WARN_ON(clock->n == 0 || clock->p == 0))
549 return;
fb03ac01
VS		 550 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
551 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
2177832f
SL		 552}
553
7429e9d4
DV		 554static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
555{
556 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
557}
558
ac58c3f0 559static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 560{
7429e9d4 561 clock->m = i9xx_dpll_compute_m(clock);
79e53945 562 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 563 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
564 return;
fb03ac01
VS		 565 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
566 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
79e53945
JB		 567}
568
ef9348c8
CML		 569static void chv_clock(int refclk, intel_clock_t *clock)
570{
571 clock->m = clock->m1 * clock->m2;
572 clock->p = clock->p1 * clock->p2;
573 if (WARN_ON(clock->n == 0 || clock->p == 0))
574 return;
575 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
576 clock->n << 22);
577 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
578}
579
7c04d1d9 580#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 581/**
582 * Returns whether the given set of divisors are valid for a given refclk with
583 * the given connectors.
584 */
585
1b894b59
CW		 586static bool intel_PLL_is_valid(struct drm_device *dev,
587 const intel_limit_t *limit,
588 const intel_clock_t *clock)
79e53945 589{
f01b7962
VS		 590 if (clock->n < limit->n.min || limit->n.max < clock->n)
591 INTELPllInvalid("n out of range\n");
79e53945 592 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 593 INTELPllInvalid("p1 out of range\n");
79e53945 594 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 595 INTELPllInvalid("m2 out of range\n");
79e53945 596 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 597 INTELPllInvalid("m1 out of range\n");
f01b7962
VS		 598
599 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
600 if (clock->m1 <= clock->m2)
601 INTELPllInvalid("m1 <= m2\n");
602
603 if (!IS_VALLEYVIEW(dev)) {
604 if (clock->p < limit->p.min || limit->p.max < clock->p)
605 INTELPllInvalid("p out of range\n");
606 if (clock->m < limit->m.min || limit->m.max < clock->m)
607 INTELPllInvalid("m out of range\n");
608 }
609
79e53945 610 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 611 INTELPllInvalid("vco out of range\n");
79e53945
JB		 612 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
613 * connector, etc., rather than just a single range.
614 */
615 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 616 INTELPllInvalid("dot out of range\n");
79e53945
JB		 617
618 return true;
619}
620
d4906093 621static bool
a93e255f
ACO		 622i9xx_find_best_dpll(const intel_limit_t *limit,
623 struct intel_crtc_state *crtc_state,
cec2f356
SP		 624 int target, int refclk, intel_clock_t *match_clock,
625 intel_clock_t *best_clock)
79e53945 626{
a93e255f 627 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 628 struct drm_device *dev = crtc->base.dev;
79e53945 629 intel_clock_t clock;
79e53945
JB		 630 int err = target;
631
a93e255f 632 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 633 /*
a210b028
DV		 634 * For LVDS just rely on its current settings for dual-channel.
635 * We haven't figured out how to reliably set up different
636 * single/dual channel state, if we even can.
79e53945 637 */
1974cad0 638 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 639 clock.p2 = limit->p2.p2_fast;
640 else
641 clock.p2 = limit->p2.p2_slow;
642 } else {
643 if (target < limit->p2.dot_limit)
644 clock.p2 = limit->p2.p2_slow;
645 else
646 clock.p2 = limit->p2.p2_fast;
647 }
648
0206e353 649 memset(best_clock, 0, sizeof(*best_clock));
79e53945 650
42158660
ZY		 651 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
652 clock.m1++) {
653 for (clock.m2 = limit->m2.min;
654 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 655 if (clock.m2 >= clock.m1)
42158660
ZY		 656 break;
657 for (clock.n = limit->n.min;
658 clock.n <= limit->n.max; clock.n++) {
659 for (clock.p1 = limit->p1.min;
660 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 661 int this_err;
662
ac58c3f0
DV		 663 i9xx_clock(refclk, &clock);
664 if (!intel_PLL_is_valid(dev, limit,
665 &clock))
666 continue;
667 if (match_clock &&
668 clock.p != match_clock->p)
669 continue;
670
671 this_err = abs(clock.dot - target);
672 if (this_err < err) {
673 *best_clock = clock;
674 err = this_err;
675 }
676 }
677 }
678 }
679 }
680
681 return (err != target);
682}
683
684static bool
a93e255f
ACO		 685pnv_find_best_dpll(const intel_limit_t *limit,
686 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 687 int target, int refclk, intel_clock_t *match_clock,
688 intel_clock_t *best_clock)
79e53945 689{
a93e255f 690 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 691 struct drm_device *dev = crtc->base.dev;
79e53945 692 intel_clock_t clock;
79e53945
JB		 693 int err = target;
694
a93e255f 695 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 696 /*
a210b028
DV		 697 * For LVDS just rely on its current settings for dual-channel.
698 * We haven't figured out how to reliably set up different
699 * single/dual channel state, if we even can.
79e53945 700 */
1974cad0 701 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 702 clock.p2 = limit->p2.p2_fast;
703 else
704 clock.p2 = limit->p2.p2_slow;
705 } else {
706 if (target < limit->p2.dot_limit)
707 clock.p2 = limit->p2.p2_slow;
708 else
709 clock.p2 = limit->p2.p2_fast;
710 }
711
0206e353 712 memset(best_clock, 0, sizeof(*best_clock));
79e53945 713
42158660
ZY		 714 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
715 clock.m1++) {
716 for (clock.m2 = limit->m2.min;
717 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 718 for (clock.n = limit->n.min;
719 clock.n <= limit->n.max; clock.n++) {
720 for (clock.p1 = limit->p1.min;
721 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 722 int this_err;
723
ac58c3f0 724 pineview_clock(refclk, &clock);
1b894b59
CW		 725 if (!intel_PLL_is_valid(dev, limit,
726 &clock))
79e53945 727 continue;
cec2f356
SP		 728 if (match_clock &&
729 clock.p != match_clock->p)
730 continue;
79e53945
JB		 731
732 this_err = abs(clock.dot - target);
733 if (this_err < err) {
734 *best_clock = clock;
735 err = this_err;
736 }
737 }
738 }
739 }
740 }
741
742 return (err != target);
743}
744
d4906093 745static bool
a93e255f
ACO		 746g4x_find_best_dpll(const intel_limit_t *limit,
747 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 748 int target, int refclk, intel_clock_t *match_clock,
749 intel_clock_t *best_clock)
d4906093 750{
a93e255f 751 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 752 struct drm_device *dev = crtc->base.dev;
d4906093
ML		 753 intel_clock_t clock;
754 int max_n;
755 bool found;
6ba770dc
AJ		 756 /* approximately equals target * 0.00585 */
757 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 758 found = false;
759
a93e255f 760 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 761 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 762 clock.p2 = limit->p2.p2_fast;
763 else
764 clock.p2 = limit->p2.p2_slow;
765 } else {
766 if (target < limit->p2.dot_limit)
767 clock.p2 = limit->p2.p2_slow;
768 else
769 clock.p2 = limit->p2.p2_fast;
770 }
771
772 memset(best_clock, 0, sizeof(*best_clock));
773 max_n = limit->n.max;
f77f13e2 774 /* based on hardware requirement, prefer smaller n to precision */
d4906093 775 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 776 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 777 for (clock.m1 = limit->m1.max;
778 clock.m1 >= limit->m1.min; clock.m1--) {
779 for (clock.m2 = limit->m2.max;
780 clock.m2 >= limit->m2.min; clock.m2--) {
781 for (clock.p1 = limit->p1.max;
782 clock.p1 >= limit->p1.min; clock.p1--) {
783 int this_err;
784
ac58c3f0 785 i9xx_clock(refclk, &clock);
1b894b59
CW		 786 if (!intel_PLL_is_valid(dev, limit,
787 &clock))
d4906093 788 continue;
1b894b59
CW		 789
790 this_err = abs(clock.dot - target);
d4906093
ML		 791 if (this_err < err_most) {
792 *best_clock = clock;
793 err_most = this_err;
794 max_n = clock.n;
795 found = true;
796 }
797 }
798 }
799 }
800 }
2c07245f
ZW		 801 return found;
802}
803
d5dd62bd
ID		 804/*
805 * Check if the calculated PLL configuration is more optimal compared to the
806 * best configuration and error found so far. Return the calculated error.
807 */
808static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
809 const intel_clock_t *calculated_clock,
810 const intel_clock_t *best_clock,
811 unsigned int best_error_ppm,
812 unsigned int *error_ppm)
813{
9ca3ba01
ID		 814 /*
815 * For CHV ignore the error and consider only the P value.
816 * Prefer a bigger P value based on HW requirements.
817 */
818 if (IS_CHERRYVIEW(dev)) {
819 *error_ppm = 0;
820
821 return calculated_clock->p > best_clock->p;
822 }
823
24be4e46
ID		 824 if (WARN_ON_ONCE(!target_freq))
825 return false;
826
d5dd62bd
ID		 827 *error_ppm = div_u64(1000000ULL *
828 abs(target_freq - calculated_clock->dot),
829 target_freq);
830 /*
831 * Prefer a better P value over a better (smaller) error if the error
832 * is small. Ensure this preference for future configurations too by
833 * setting the error to 0.
834 */
835 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
836 *error_ppm = 0;
837
838 return true;
839 }
840
841 return *error_ppm + 10 < best_error_ppm;
842}
843
a0c4da24 844static bool
a93e255f
ACO		 845vlv_find_best_dpll(const intel_limit_t *limit,
846 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 847 int target, int refclk, intel_clock_t *match_clock,
848 intel_clock_t *best_clock)
a0c4da24 849{
a93e255f 850 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 851 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 852 intel_clock_t clock;
69e4f900 853 unsigned int bestppm = 1000000;
27e639bf
VS		 854 /* min update 19.2 MHz */
855 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 856 bool found = false;
a0c4da24 857
6b4bf1c4
VS		 858 target *= 5; /* fast clock */
859
860 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 861
862 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 863 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 864 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 865 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 866 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 867 clock.p = clock.p1 * clock.p2;
a0c4da24 868 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 869 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 870 unsigned int ppm;
69e4f900 871
6b4bf1c4
VS		 872 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
873 refclk * clock.m1);
874
875 vlv_clock(refclk, &clock);
43b0ac53 876
f01b7962
VS		 877 if (!intel_PLL_is_valid(dev, limit,
878 &clock))
43b0ac53
VS		 879 continue;
880
d5dd62bd
ID		 881 if (!vlv_PLL_is_optimal(dev, target,
882 &clock,
883 best_clock,
884 bestppm, &ppm))
885 continue;
6b4bf1c4 886
d5dd62bd
ID		 887 *best_clock = clock;
888 bestppm = ppm;
889 found = true;
a0c4da24
JB		 890 }
891 }
892 }
893 }
a0c4da24 894
49e497ef 895 return found;
a0c4da24 896}
a4fc5ed6 897
ef9348c8 898static bool
a93e255f
ACO		 899chv_find_best_dpll(const intel_limit_t *limit,
900 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 901 int target, int refclk, intel_clock_t *match_clock,
902 intel_clock_t *best_clock)
903{
a93e255f 904 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 905 struct drm_device *dev = crtc->base.dev;
9ca3ba01 906 unsigned int best_error_ppm;
ef9348c8
CML		 907 intel_clock_t clock;
908 uint64_t m2;
909 int found = false;
910
911 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 912 best_error_ppm = 1000000;
ef9348c8
CML		 913
914 /*
915 * Based on hardware doc, the n always set to 1, and m1 always
916 * set to 2. If requires to support 200Mhz refclk, we need to
917 * revisit this because n may not 1 anymore.
918 */
919 clock.n = 1, clock.m1 = 2;
920 target *= 5; /* fast clock */
921
922 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
923 for (clock.p2 = limit->p2.p2_fast;
924 clock.p2 >= limit->p2.p2_slow;
925 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 926 unsigned int error_ppm;
ef9348c8
CML		 927
928 clock.p = clock.p1 * clock.p2;
929
930 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
931 clock.n) << 22, refclk * clock.m1);
932
933 if (m2 > INT_MAX/clock.m1)
934 continue;
935
936 clock.m2 = m2;
937
938 chv_clock(refclk, &clock);
939
940 if (!intel_PLL_is_valid(dev, limit, &clock))
941 continue;
942
9ca3ba01
ID		 943 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
944 best_error_ppm, &error_ppm))
945 continue;
946
947 *best_clock = clock;
948 best_error_ppm = error_ppm;
949 found = true;
ef9348c8
CML		 950 }
951 }
952
953 return found;
954}
955
20ddf665
VS		 956bool intel_crtc_active(struct drm_crtc *crtc)
957{
958 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
959
960 /* Be paranoid as we can arrive here with only partial
961 * state retrieved from the hardware during setup.
962 *
241bfc38 963 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 964 * as Haswell has gained clock readout/fastboot support.
965 *
66e514c1 966 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 967 * properly reconstruct framebuffers.
c3d1f436
MR		 968 *
969 * FIXME: The intel_crtc->active here should be switched to
970 * crtc->state->active once we have proper CRTC states wired up
971 * for atomic.
20ddf665 972 */
c3d1f436 973 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 974 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 975}
976
a5c961d1
PZ		 977enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
978 enum pipe pipe)
979{
980 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
981 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
982
6e3c9717 983 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 984}
985
fbf49ea2
VS		 986static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
987{
988 struct drm_i915_private *dev_priv = dev->dev_private;
989 u32 reg = PIPEDSL(pipe);
990 u32 line1, line2;
991 u32 line_mask;
992
993 if (IS_GEN2(dev))
994 line_mask = DSL_LINEMASK_GEN2;
995 else
996 line_mask = DSL_LINEMASK_GEN3;
997
998 line1 = I915_READ(reg) & line_mask;
999 mdelay(5);
1000 line2 = I915_READ(reg) & line_mask;
1001
1002 return line1 == line2;
1003}
1004
ab7ad7f6
KP		 1005/*
1006 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1007 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1008 *
1009 * After disabling a pipe, we can't wait for vblank in the usual way,
1010 * spinning on the vblank interrupt status bit, since we won't actually
1011 * see an interrupt when the pipe is disabled.
1012 *
ab7ad7f6
KP		 1013 * On Gen4 and above:
1014 * wait for the pipe register state bit to turn off
1015 *
1016 * Otherwise:
1017 * wait for the display line value to settle (it usually
1018 * ends up stopping at the start of the next frame).
58e10eb9 1019 *
9d0498a2 1020 */
575f7ab7 1021static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1022{
575f7ab7 1023 struct drm_device *dev = crtc->base.dev;
9d0498a2 1024 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1025 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1026 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1027
1028 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1029 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1030
1031 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1032 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1033 100))
284637d9 1034 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1035 } else {
ab7ad7f6 1036 /* Wait for the display line to settle */
fbf49ea2 1037 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1038 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1039 }
79e53945
JB		 1040}
1041
b0ea7d37
DL		 1042/*
1043 * ibx_digital_port_connected - is the specified port connected?
1044 * @dev_priv: i915 private structure
1045 * @port: the port to test
1046 *
1047 * Returns true if @port is connected, false otherwise.
1048 */
1049bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1050 struct intel_digital_port *port)
1051{
1052 u32 bit;
1053
c36346e3 1054 if (HAS_PCH_IBX(dev_priv->dev)) {
eba905b2 1055 switch (port->port) {
c36346e3
DL		 1056 case PORT_B:
1057 bit = SDE_PORTB_HOTPLUG;
1058 break;
1059 case PORT_C:
1060 bit = SDE_PORTC_HOTPLUG;
1061 break;
1062 case PORT_D:
1063 bit = SDE_PORTD_HOTPLUG;
1064 break;
1065 default:
1066 return true;
1067 }
1068 } else {
eba905b2 1069 switch (port->port) {
c36346e3
DL		 1070 case PORT_B:
1071 bit = SDE_PORTB_HOTPLUG_CPT;
1072 break;
1073 case PORT_C:
1074 bit = SDE_PORTC_HOTPLUG_CPT;
1075 break;
1076 case PORT_D:
1077 bit = SDE_PORTD_HOTPLUG_CPT;
1078 break;
1079 default:
1080 return true;
1081 }
b0ea7d37
DL		 1082 }
1083
1084 return I915_READ(SDEISR) & bit;
1085}
1086
b24e7179
JB		 1087static const char *state_string(bool enabled)
1088{
1089 return enabled ? "on" : "off";
1090}
1091
1092/* Only for pre-ILK configs */
55607e8a
DV		 1093void assert_pll(struct drm_i915_private *dev_priv,
1094 enum pipe pipe, bool state)
b24e7179
JB		 1095{
1096 int reg;
1097 u32 val;
1098 bool cur_state;
1099
1100 reg = DPLL(pipe);
1101 val = I915_READ(reg);
1102 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1103 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1104 "PLL state assertion failure (expected %s, current %s)\n",
1105 state_string(state), state_string(cur_state));
1106}
b24e7179 1107
23538ef1
JN		 1108/* XXX: the dsi pll is shared between MIPI DSI ports */
1109static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1110{
1111 u32 val;
1112 bool cur_state;
1113
1114 mutex_lock(&dev_priv->dpio_lock);
1115 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1116 mutex_unlock(&dev_priv->dpio_lock);
1117
1118 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1119 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1120 "DSI PLL state assertion failure (expected %s, current %s)\n",
1121 state_string(state), state_string(cur_state));
1122}
1123#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1124#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1125
55607e8a 1126struct intel_shared_dpll *
e2b78267
DV		 1127intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1128{
1129 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1130
6e3c9717 1131 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1132 return NULL;
1133
6e3c9717 1134 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1135}
1136
040484af 1137/* For ILK+ */
55607e8a
DV		 1138void assert_shared_dpll(struct drm_i915_private *dev_priv,
1139 struct intel_shared_dpll *pll,
1140 bool state)
040484af 1141{
040484af 1142 bool cur_state;
5358901f 1143 struct intel_dpll_hw_state hw_state;
040484af 1144
92b27b08 1145 if (WARN (!pll,
46edb027 1146 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1147 return;
ee7b9f93 1148
5358901f 1149 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1150 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1151 "%s assertion failure (expected %s, current %s)\n",
1152 pll->name, state_string(state), state_string(cur_state));
040484af 1153}
040484af
JB		 1154
1155static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1156 enum pipe pipe, bool state)
1157{
1158 int reg;
1159 u32 val;
1160 bool cur_state;
ad80a810
PZ		 1161 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1162 pipe);
040484af 1163
affa9354
PZ		 1164 if (HAS_DDI(dev_priv->dev)) {
1165 /* DDI does not have a specific FDI_TX register */
ad80a810 1166 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1167 val = I915_READ(reg);
ad80a810 1168 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1169 } else {
1170 reg = FDI_TX_CTL(pipe);
1171 val = I915_READ(reg);
1172 cur_state = !!(val & FDI_TX_ENABLE);
1173 }
e2c719b7 1174 I915_STATE_WARN(cur_state != state,
040484af
JB		 1175 "FDI TX state assertion failure (expected %s, current %s)\n",
1176 state_string(state), state_string(cur_state));
1177}
1178#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1179#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1180
1181static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1182 enum pipe pipe, bool state)
1183{
1184 int reg;
1185 u32 val;
1186 bool cur_state;
1187
d63fa0dc
PZ		 1188 reg = FDI_RX_CTL(pipe);
1189 val = I915_READ(reg);
1190 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1191 I915_STATE_WARN(cur_state != state,
040484af
JB		 1192 "FDI RX state assertion failure (expected %s, current %s)\n",
1193 state_string(state), state_string(cur_state));
1194}
1195#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1196#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1197
1198static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1199 enum pipe pipe)
1200{
1201 int reg;
1202 u32 val;
1203
1204 /* ILK FDI PLL is always enabled */
3d13ef2e 1205 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1206 return;
1207
bf507ef7 1208 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1209 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1210 return;
1211
040484af
JB		 1212 reg = FDI_TX_CTL(pipe);
1213 val = I915_READ(reg);
e2c719b7 1214 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1215}
1216
55607e8a
DV		 1217void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1218 enum pipe pipe, bool state)
040484af
JB		 1219{
1220 int reg;
1221 u32 val;
55607e8a 1222 bool cur_state;
040484af
JB		 1223
1224 reg = FDI_RX_CTL(pipe);
1225 val = I915_READ(reg);
55607e8a 1226 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1227 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1228 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1229 state_string(state), state_string(cur_state));
040484af
JB		 1230}
1231
b680c37a
DV		 1232void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1233 enum pipe pipe)
ea0760cf 1234{
bedd4dba
JN		 1235 struct drm_device *dev = dev_priv->dev;
1236 int pp_reg;
ea0760cf
JB		 1237 u32 val;
1238 enum pipe panel_pipe = PIPE_A;
0de3b485 1239 bool locked = true;
ea0760cf 1240
bedd4dba
JN		 1241 if (WARN_ON(HAS_DDI(dev)))
1242 return;
1243
1244 if (HAS_PCH_SPLIT(dev)) {
1245 u32 port_sel;
1246
ea0760cf 1247 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1248 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1249
1250 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1251 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1252 panel_pipe = PIPE_B;
1253 /* XXX: else fix for eDP */
1254 } else if (IS_VALLEYVIEW(dev)) {
1255 /* presumably write lock depends on pipe, not port select */
1256 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1257 panel_pipe = pipe;
ea0760cf
JB		 1258 } else {
1259 pp_reg = PP_CONTROL;
bedd4dba
JN		 1260 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1261 panel_pipe = PIPE_B;
ea0760cf
JB		 1262 }
1263
1264 val = I915_READ(pp_reg);
1265 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1266 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1267 locked = false;
1268
e2c719b7 1269 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1270 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1271 pipe_name(pipe));
ea0760cf
JB		 1272}
1273
93ce0ba6
JN		 1274static void assert_cursor(struct drm_i915_private *dev_priv,
1275 enum pipe pipe, bool state)
1276{
1277 struct drm_device *dev = dev_priv->dev;
1278 bool cur_state;
1279
d9d82081 1280 if (IS_845G(dev) || IS_I865G(dev))
93ce0ba6 1281 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
d9d82081 1282 else
5efb3e28 1283 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1284
e2c719b7 1285 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1286 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1287 pipe_name(pipe), state_string(state), state_string(cur_state));
1288}
1289#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1290#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1291
b840d907
JB		 1292void assert_pipe(struct drm_i915_private *dev_priv,
1293 enum pipe pipe, bool state)
b24e7179
JB		 1294{
1295 int reg;
1296 u32 val;
63d7bbe9 1297 bool cur_state;
702e7a56
PZ		 1298 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1299 pipe);
b24e7179 1300
b6b5d049
VS		 1301 /* if we need the pipe quirk it must be always on */
1302 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1303 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1304 state = true;
1305
f458ebbc 1306 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1307 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1308 cur_state = false;
1309 } else {
1310 reg = PIPECONF(cpu_transcoder);
1311 val = I915_READ(reg);
1312 cur_state = !!(val & PIPECONF_ENABLE);
1313 }
1314
e2c719b7 1315 I915_STATE_WARN(cur_state != state,
63d7bbe9 1316 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1317 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1318}
1319
931872fc
CW		 1320static void assert_plane(struct drm_i915_private *dev_priv,
1321 enum plane plane, bool state)
b24e7179
JB		 1322{
1323 int reg;
1324 u32 val;
931872fc 1325 bool cur_state;
b24e7179
JB		 1326
1327 reg = DSPCNTR(plane);
1328 val = I915_READ(reg);
931872fc 1329 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1330 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1331 "plane %c assertion failure (expected %s, current %s)\n",
1332 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1333}
1334
931872fc
CW		 1335#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1336#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1337
b24e7179
JB		 1338static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1339 enum pipe pipe)
1340{
653e1026 1341 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1342 int reg, i;
1343 u32 val;
1344 int cur_pipe;
1345
653e1026
VS		 1346 /* Primary planes are fixed to pipes on gen4+ */
1347 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1348 reg = DSPCNTR(pipe);
1349 val = I915_READ(reg);
e2c719b7 1350 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1351 "plane %c assertion failure, should be disabled but not\n",
1352 plane_name(pipe));
19ec1358 1353 return;
28c05794 1354 }
19ec1358 1355
b24e7179 1356 /* Need to check both planes against the pipe */
055e393f 1357 for_each_pipe(dev_priv, i) {
b24e7179
JB		 1358 reg = DSPCNTR(i);
1359 val = I915_READ(reg);
1360 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1361 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1362 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1363 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1364 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1365 }
1366}
1367
19332d7a
JB		 1368static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1369 enum pipe pipe)
1370{
20674eef 1371 struct drm_device *dev = dev_priv->dev;
1fe47785 1372 int reg, sprite;
19332d7a
JB		 1373 u32 val;
1374
7feb8b88 1375 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1376 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1377 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1378 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1379 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1380 sprite, pipe_name(pipe));
1381 }
1382 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1383 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1384 reg = SPCNTR(pipe, sprite);
20674eef 1385 val = I915_READ(reg);
e2c719b7 1386 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1387 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1388 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1389 }
1390 } else if (INTEL_INFO(dev)->gen >= 7) {
1391 reg = SPRCTL(pipe);
19332d7a 1392 val = I915_READ(reg);
e2c719b7 1393 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1394 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1395 plane_name(pipe), pipe_name(pipe));
1396 } else if (INTEL_INFO(dev)->gen >= 5) {
1397 reg = DVSCNTR(pipe);
19332d7a 1398 val = I915_READ(reg);
e2c719b7 1399 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1400 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1401 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1402 }
1403}
1404
08c71e5e
VS		 1405static void assert_vblank_disabled(struct drm_crtc *crtc)
1406{
e2c719b7 1407 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1408 drm_crtc_vblank_put(crtc);
1409}
1410
89eff4be 1411static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1412{
1413 u32 val;
1414 bool enabled;
1415
e2c719b7 1416 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1417
92f2584a
JB		 1418 val = I915_READ(PCH_DREF_CONTROL);
1419 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1420 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1421 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1422}
1423
ab9412ba
DV		 1424static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1425 enum pipe pipe)
92f2584a
JB		 1426{
1427 int reg;
1428 u32 val;
1429 bool enabled;
1430
ab9412ba 1431 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1432 val = I915_READ(reg);
1433 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1434 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1435 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1436 pipe_name(pipe));
92f2584a
JB		 1437}
1438
4e634389
KP		 1439static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1440 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1441{
1442 if ((val & DP_PORT_EN) == 0)
1443 return false;
1444
1445 if (HAS_PCH_CPT(dev_priv->dev)) {
1446 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1447 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1448 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1449 return false;
44f37d1f
CML		 1450 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1451 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1452 return false;
f0575e92
KP		 1453 } else {
1454 if ((val & DP_PIPE_MASK) != (pipe << 30))
1455 return false;
1456 }
1457 return true;
1458}
1459
1519b995
KP		 1460static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1461 enum pipe pipe, u32 val)
1462{
dc0fa718 1463 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1464 return false;
1465
1466 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1467 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1468 return false;
44f37d1f
CML		 1469 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1470 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1471 return false;
1519b995 1472 } else {
dc0fa718 1473 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1474 return false;
1475 }
1476 return true;
1477}
1478
1479static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1480 enum pipe pipe, u32 val)
1481{
1482 if ((val & LVDS_PORT_EN) == 0)
1483 return false;
1484
1485 if (HAS_PCH_CPT(dev_priv->dev)) {
1486 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1487 return false;
1488 } else {
1489 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1490 return false;
1491 }
1492 return true;
1493}
1494
1495static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1496 enum pipe pipe, u32 val)
1497{
1498 if ((val & ADPA_DAC_ENABLE) == 0)
1499 return false;
1500 if (HAS_PCH_CPT(dev_priv->dev)) {
1501 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1502 return false;
1503 } else {
1504 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1505 return false;
1506 }
1507 return true;
1508}
1509
291906f1 1510static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1511 enum pipe pipe, int reg, u32 port_sel)
291906f1 1512{
47a05eca 1513 u32 val = I915_READ(reg);
e2c719b7 1514 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1515 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1516 reg, pipe_name(pipe));
de9a35ab 1517
e2c719b7 1518 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1519 && (val & DP_PIPEB_SELECT),
de9a35ab 1520 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1521}
1522
1523static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1524 enum pipe pipe, int reg)
1525{
47a05eca 1526 u32 val = I915_READ(reg);
e2c719b7 1527 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1528 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1529 reg, pipe_name(pipe));
de9a35ab 1530
e2c719b7 1531 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1532 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1533 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1534}
1535
1536static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1537 enum pipe pipe)
1538{
1539 int reg;
1540 u32 val;
291906f1 1541
f0575e92
KP		 1542 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1543 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1544 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1545
1546 reg = PCH_ADPA;
1547 val = I915_READ(reg);
e2c719b7 1548 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1549 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1550 pipe_name(pipe));
291906f1
JB		 1551
1552 reg = PCH_LVDS;
1553 val = I915_READ(reg);
e2c719b7 1554 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1555 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1556 pipe_name(pipe));
291906f1 1557
e2debe91
PZ		 1558 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1559 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1560 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1561}
1562
40e9cf64
JB		 1563static void intel_init_dpio(struct drm_device *dev)
1564{
1565 struct drm_i915_private *dev_priv = dev->dev_private;
1566
1567 if (!IS_VALLEYVIEW(dev))
1568 return;
1569
a09caddd
CML		 1570 /*
1571 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1572 * CHV x1 PHY (DP/HDMI D)
1573 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1574 */
1575 if (IS_CHERRYVIEW(dev)) {
1576 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1577 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1578 } else {
1579 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1580 }
5382f5f3
JB		 1581}
1582
d288f65f 1583static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1584 const struct intel_crtc_state *pipe_config)
87442f73 1585{
426115cf
DV		 1586 struct drm_device *dev = crtc->base.dev;
1587 struct drm_i915_private *dev_priv = dev->dev_private;
1588 int reg = DPLL(crtc->pipe);
d288f65f 1589 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1590
426115cf 1591 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1592
1593 /* No really, not for ILK+ */
1594 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1595
1596 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1597 if (IS_MOBILE(dev_priv->dev))
426115cf 1598 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1599
426115cf
DV		 1600 I915_WRITE(reg, dpll);
1601 POSTING_READ(reg);
1602 udelay(150);
1603
1604 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1605 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1606
d288f65f 1607 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1608 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1609
1610 /* We do this three times for luck */
426115cf 1611 I915_WRITE(reg, dpll);
87442f73
DV		 1612 POSTING_READ(reg);
1613 udelay(150); /* wait for warmup */
426115cf 1614 I915_WRITE(reg, dpll);
87442f73
DV		 1615 POSTING_READ(reg);
1616 udelay(150); /* wait for warmup */
426115cf 1617 I915_WRITE(reg, dpll);
87442f73
DV		 1618 POSTING_READ(reg);
1619 udelay(150); /* wait for warmup */
1620}
1621
d288f65f 1622static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1623 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1624{
1625 struct drm_device *dev = crtc->base.dev;
1626 struct drm_i915_private *dev_priv = dev->dev_private;
1627 int pipe = crtc->pipe;
1628 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1629 u32 tmp;
1630
1631 assert_pipe_disabled(dev_priv, crtc->pipe);
1632
1633 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1634
1635 mutex_lock(&dev_priv->dpio_lock);
1636
1637 /* Enable back the 10bit clock to display controller */
1638 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1639 tmp |= DPIO_DCLKP_EN;
1640 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1641
1642 /*
1643 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1644 */
1645 udelay(1);
1646
1647 /* Enable PLL */
d288f65f 1648 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1649
1650 /* Check PLL is locked */
a11b0703 1651 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1652 DRM_ERROR("PLL %d failed to lock\n", pipe);
1653
a11b0703 1654 /* not sure when this should be written */
d288f65f 1655 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703
VS		 1656 POSTING_READ(DPLL_MD(pipe));
1657
9d556c99
CML		 1658 mutex_unlock(&dev_priv->dpio_lock);
1659}
1660
1c4e0274
VS		 1661static int intel_num_dvo_pipes(struct drm_device *dev)
1662{
1663 struct intel_crtc *crtc;
1664 int count = 0;
1665
1666 for_each_intel_crtc(dev, crtc)
1667 count += crtc->active &&
409ee761 1668 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1669
1670 return count;
1671}
1672
66e3d5c0 1673static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1674{
66e3d5c0
DV		 1675 struct drm_device *dev = crtc->base.dev;
1676 struct drm_i915_private *dev_priv = dev->dev_private;
1677 int reg = DPLL(crtc->pipe);
6e3c9717 1678 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1679
66e3d5c0 1680 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1681
63d7bbe9 1682 /* No really, not for ILK+ */
3d13ef2e 1683 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1684
1685 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1686 if (IS_MOBILE(dev) && !IS_I830(dev))
1687 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1688
1c4e0274
VS		 1689 /* Enable DVO 2x clock on both PLLs if necessary */
1690 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1691 /*
1692 * It appears to be important that we don't enable this
1693 * for the current pipe before otherwise configuring the
1694 * PLL. No idea how this should be handled if multiple
1695 * DVO outputs are enabled simultaneosly.
1696 */
1697 dpll |= DPLL_DVO_2X_MODE;
1698 I915_WRITE(DPLL(!crtc->pipe),
1699 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1700 }
66e3d5c0
DV		 1701
1702 /* Wait for the clocks to stabilize. */
1703 POSTING_READ(reg);
1704 udelay(150);
1705
1706 if (INTEL_INFO(dev)->gen >= 4) {
1707 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1708 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1709 } else {
1710 /* The pixel multiplier can only be updated once the
1711 * DPLL is enabled and the clocks are stable.
1712 *
1713 * So write it again.
1714 */
1715 I915_WRITE(reg, dpll);
1716 }
63d7bbe9
JB		 1717
1718 /* We do this three times for luck */
66e3d5c0 1719 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1720 POSTING_READ(reg);
1721 udelay(150); /* wait for warmup */
66e3d5c0 1722 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1723 POSTING_READ(reg);
1724 udelay(150); /* wait for warmup */
66e3d5c0 1725 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1726 POSTING_READ(reg);
1727 udelay(150); /* wait for warmup */
1728}
1729
1730/**
50b44a44 1731 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1732 * @dev_priv: i915 private structure
1733 * @pipe: pipe PLL to disable
1734 *
1735 * Disable the PLL for @pipe, making sure the pipe is off first.
1736 *
1737 * Note! This is for pre-ILK only.
1738 */
1c4e0274 1739static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1740{
1c4e0274
VS		 1741 struct drm_device *dev = crtc->base.dev;
1742 struct drm_i915_private *dev_priv = dev->dev_private;
1743 enum pipe pipe = crtc->pipe;
1744
1745 /* Disable DVO 2x clock on both PLLs if necessary */
1746 if (IS_I830(dev) &&
409ee761 1747 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1c4e0274
VS		 1748 intel_num_dvo_pipes(dev) == 1) {
1749 I915_WRITE(DPLL(PIPE_B),
1750 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1751 I915_WRITE(DPLL(PIPE_A),
1752 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1753 }
1754
b6b5d049
VS		 1755 /* Don't disable pipe or pipe PLLs if needed */
1756 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1757 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1758 return;
1759
1760 /* Make sure the pipe isn't still relying on us */
1761 assert_pipe_disabled(dev_priv, pipe);
1762
50b44a44
DV		 1763 I915_WRITE(DPLL(pipe), 0);
1764 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1765}
1766
f6071166
JB		 1767static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1768{
1769 u32 val = 0;
1770
1771 /* Make sure the pipe isn't still relying on us */
1772 assert_pipe_disabled(dev_priv, pipe);
1773
e5cbfbfb
ID		 1774 /*
1775 * Leave integrated clock source and reference clock enabled for pipe B.
1776 * The latter is needed for VGA hotplug / manual detection.
1777 */
f6071166 1778 if (pipe == PIPE_B)
e5cbfbfb 1779 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
f6071166
JB		 1780 I915_WRITE(DPLL(pipe), val);
1781 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1782
1783}
1784
1785static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1786{
d752048d 1787 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1788 u32 val;
1789
a11b0703
VS		 1790 /* Make sure the pipe isn't still relying on us */
1791 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1792
a11b0703 1793 /* Set PLL en = 0 */
d17ec4ce 1794 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
a11b0703
VS		 1795 if (pipe != PIPE_A)
1796 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1797 I915_WRITE(DPLL(pipe), val);
1798 POSTING_READ(DPLL(pipe));
d752048d
VS		 1799
1800 mutex_lock(&dev_priv->dpio_lock);
1801
1802 /* Disable 10bit clock to display controller */
1803 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1804 val &= ~DPIO_DCLKP_EN;
1805 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1806
61407f6d
VS		 1807 /* disable left/right clock distribution */
1808 if (pipe != PIPE_B) {
1809 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1810 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1811 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1812 } else {
1813 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1814 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1815 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1816 }
1817
d752048d 1818 mutex_unlock(&dev_priv->dpio_lock);
f6071166
JB		 1819}
1820
e4607fcf
CML		 1821void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1822 struct intel_digital_port *dport)
89b667f8
JB		 1823{
1824 u32 port_mask;
00fc31b7 1825 int dpll_reg;
89b667f8 1826
e4607fcf
CML		 1827 switch (dport->port) {
1828 case PORT_B:
89b667f8 1829 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1830 dpll_reg = DPLL(0);
e4607fcf
CML		 1831 break;
1832 case PORT_C:
89b667f8 1833 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7
CML		 1834 dpll_reg = DPLL(0);
1835 break;
1836 case PORT_D:
1837 port_mask = DPLL_PORTD_READY_MASK;
1838 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1839 break;
1840 default:
1841 BUG();
1842 }
89b667f8 1843
00fc31b7 1844 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
89b667f8 1845 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
00fc31b7 1846 port_name(dport->port), I915_READ(dpll_reg));
89b667f8
JB		 1847}
1848
b14b1055
DV		 1849static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1850{
1851 struct drm_device *dev = crtc->base.dev;
1852 struct drm_i915_private *dev_priv = dev->dev_private;
1853 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1854
be19f0ff
CW		 1855 if (WARN_ON(pll == NULL))
1856 return;
1857
3e369b76 1858 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1859 if (pll->active == 0) {
1860 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1861 WARN_ON(pll->on);
1862 assert_shared_dpll_disabled(dev_priv, pll);
1863
1864 pll->mode_set(dev_priv, pll);
1865 }
1866}
1867
92f2584a 1868/**
85b3894f 1869 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1870 * @dev_priv: i915 private structure
1871 * @pipe: pipe PLL to enable
1872 *
1873 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1874 * drives the transcoder clock.
1875 */
85b3894f 1876static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1877{
3d13ef2e
DL		 1878 struct drm_device *dev = crtc->base.dev;
1879 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1880 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1881
87a875bb 1882 if (WARN_ON(pll == NULL))
48da64a8
CW		 1883 return;
1884
3e369b76 1885 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1886 return;
ee7b9f93 1887
74dd6928 1888 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1889 pll->name, pll->active, pll->on,
e2b78267 1890 crtc->base.base.id);
92f2584a 1891
cdbd2316
DV		 1892 if (pll->active++) {
1893 WARN_ON(!pll->on);
e9d6944e 1894 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1895 return;
1896 }
f4a091c7 1897 WARN_ON(pll->on);
ee7b9f93 1898
bd2bb1b9
PZ		 1899 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1900
46edb027 1901 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1902 pll->enable(dev_priv, pll);
ee7b9f93 1903 pll->on = true;
92f2584a
JB		 1904}
1905
f6daaec2 1906static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1907{
3d13ef2e
DL		 1908 struct drm_device *dev = crtc->base.dev;
1909 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1910 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1911
92f2584a 1912 /* PCH only available on ILK+ */
3d13ef2e 1913 BUG_ON(INTEL_INFO(dev)->gen < 5);
87a875bb 1914 if (WARN_ON(pll == NULL))
ee7b9f93 1915 return;
92f2584a 1916
3e369b76 1917 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1918 return;
7a419866 1919
46edb027
DV		 1920 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1921 pll->name, pll->active, pll->on,
e2b78267 1922 crtc->base.base.id);
7a419866 1923
48da64a8 1924 if (WARN_ON(pll->active == 0)) {
e9d6944e 1925 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1926 return;
1927 }
1928
e9d6944e 1929 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1930 WARN_ON(!pll->on);
cdbd2316 1931 if (--pll->active)
7a419866 1932 return;
ee7b9f93 1933
46edb027 1934 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1935 pll->disable(dev_priv, pll);
ee7b9f93 1936 pll->on = false;
bd2bb1b9
PZ		 1937
1938 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1939}
1940
b8a4f404
PZ		 1941static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1942 enum pipe pipe)
040484af 1943{
23670b32 1944 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1945 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1946 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1947 uint32_t reg, val, pipeconf_val;
040484af
JB		 1948
1949 /* PCH only available on ILK+ */
55522f37 1950 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1951
1952 /* Make sure PCH DPLL is enabled */
e72f9fbf 1953 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1954 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1955
1956 /* FDI must be feeding us bits for PCH ports */
1957 assert_fdi_tx_enabled(dev_priv, pipe);
1958 assert_fdi_rx_enabled(dev_priv, pipe);
1959
23670b32
DV		 1960 if (HAS_PCH_CPT(dev)) {
1961 /* Workaround: Set the timing override bit before enabling the
1962 * pch transcoder. */
1963 reg = TRANS_CHICKEN2(pipe);
1964 val = I915_READ(reg);
1965 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1966 I915_WRITE(reg, val);
59c859d6 1967 }
23670b32 1968
ab9412ba 1969 reg = PCH_TRANSCONF(pipe);
040484af 1970 val = I915_READ(reg);
5f7f726d 1971 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1972
1973 if (HAS_PCH_IBX(dev_priv->dev)) {
1974 /*
1975 * make the BPC in transcoder be consistent with
1976 * that in pipeconf reg.
1977 */
dfd07d72
DV		 1978 val &= ~PIPECONF_BPC_MASK;
1979 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1980 }
5f7f726d
PZ		 1981
1982 val &= ~TRANS_INTERLACE_MASK;
1983 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 1984 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 1985 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 1986 val |= TRANS_LEGACY_INTERLACED_ILK;
1987 else
1988 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1989 else
1990 val |= TRANS_PROGRESSIVE;
1991
040484af
JB		 1992 I915_WRITE(reg, val | TRANS_ENABLE);
1993 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1994 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1995}
1996
8fb033d7 1997static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1998 enum transcoder cpu_transcoder)
040484af 1999{
8fb033d7 2000 u32 val, pipeconf_val;
8fb033d7
PZ		 2001
2002 /* PCH only available on ILK+ */
55522f37 2003 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 2004
8fb033d7 2005 /* FDI must be feeding us bits for PCH ports */
1a240d4d 2006 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2007 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2008
223a6fdf
PZ		 2009 /* Workaround: set timing override bit. */
2010 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2011 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 2012 I915_WRITE(_TRANSA_CHICKEN2, val);
2013
25f3ef11 2014 val = TRANS_ENABLE;
937bb610 2015 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2016
9a76b1c6
PZ		 2017 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2018 PIPECONF_INTERLACED_ILK)
a35f2679 2019 val |= TRANS_INTERLACED;
8fb033d7
PZ		 2020 else
2021 val |= TRANS_PROGRESSIVE;
2022
ab9412ba
DV		 2023 I915_WRITE(LPT_TRANSCONF, val);
2024 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2025 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 2026}
2027
b8a4f404
PZ		 2028static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2029 enum pipe pipe)
040484af 2030{
23670b32
DV		 2031 struct drm_device *dev = dev_priv->dev;
2032 uint32_t reg, val;
040484af
JB		 2033
2034 /* FDI relies on the transcoder */
2035 assert_fdi_tx_disabled(dev_priv, pipe);
2036 assert_fdi_rx_disabled(dev_priv, pipe);
2037
291906f1
JB		 2038 /* Ports must be off as well */
2039 assert_pch_ports_disabled(dev_priv, pipe);
2040
ab9412ba 2041 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2042 val = I915_READ(reg);
2043 val &= ~TRANS_ENABLE;
2044 I915_WRITE(reg, val);
2045 /* wait for PCH transcoder off, transcoder state */
2046 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2047 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2048
2049 if (!HAS_PCH_IBX(dev)) {
2050 /* Workaround: Clear the timing override chicken bit again. */
2051 reg = TRANS_CHICKEN2(pipe);
2052 val = I915_READ(reg);
2053 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2054 I915_WRITE(reg, val);
2055 }
040484af
JB		 2056}
2057
ab4d966c 2058static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2059{
8fb033d7
PZ		 2060 u32 val;
2061
ab9412ba 2062 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2063 val &= ~TRANS_ENABLE;
ab9412ba 2064 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2065 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2066 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2067 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2068
2069 /* Workaround: clear timing override bit. */
2070 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2071 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 2072 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 2073}
2074
b24e7179 2075/**
309cfea8 2076 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2077 * @crtc: crtc responsible for the pipe
b24e7179 2078 *
0372264a 2079 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2080 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2081 */
e1fdc473 2082static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2083{
0372264a
PZ		 2084 struct drm_device *dev = crtc->base.dev;
2085 struct drm_i915_private *dev_priv = dev->dev_private;
2086 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2087 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2088 pipe);
1a240d4d 2089 enum pipe pch_transcoder;
b24e7179
JB		 2090 int reg;
2091 u32 val;
2092
58c6eaa2 2093 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2094 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2095 assert_sprites_disabled(dev_priv, pipe);
2096
681e5811 2097 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2098 pch_transcoder = TRANSCODER_A;
2099 else
2100 pch_transcoder = pipe;
2101
b24e7179
JB		 2102 /*
2103 * A pipe without a PLL won't actually be able to drive bits from
2104 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2105 * need the check.
2106 */
2107 if (!HAS_PCH_SPLIT(dev_priv->dev))
409ee761 2108 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2109 assert_dsi_pll_enabled(dev_priv);
2110 else
2111 assert_pll_enabled(dev_priv, pipe);
040484af 2112 else {
6e3c9717 2113 if (crtc->config->has_pch_encoder) {
040484af 2114 /* if driving the PCH, we need FDI enabled */
cc391bbb 2115 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2116 assert_fdi_tx_pll_enabled(dev_priv,
2117 (enum pipe) cpu_transcoder);
040484af
JB		 2118 }
2119 /* FIXME: assert CPU port conditions for SNB+ */
2120 }
b24e7179 2121
702e7a56 2122 reg = PIPECONF(cpu_transcoder);
b24e7179 2123 val = I915_READ(reg);
7ad25d48 2124 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2125 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2126 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2127 return;
7ad25d48 2128 }
00d70b15
CW		 2129
2130 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2131 POSTING_READ(reg);
b24e7179
JB		 2132}
2133
2134/**
309cfea8 2135 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2136 * @crtc: crtc whose pipes is to be disabled
b24e7179 2137 *
575f7ab7
VS		 2138 * Disable the pipe of @crtc, making sure that various hardware
2139 * specific requirements are met, if applicable, e.g. plane
2140 * disabled, panel fitter off, etc.
b24e7179
JB		 2141 *
2142 * Will wait until the pipe has shut down before returning.
2143 */
575f7ab7 2144static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2145{
575f7ab7 2146 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2147 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2148 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2149 int reg;
2150 u32 val;
2151
2152 /*
2153 * Make sure planes won't keep trying to pump pixels to us,
2154 * or we might hang the display.
2155 */
2156 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2157 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2158 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2159
702e7a56 2160 reg = PIPECONF(cpu_transcoder);
b24e7179 2161 val = I915_READ(reg);
00d70b15
CW		 2162 if ((val & PIPECONF_ENABLE) == 0)
2163 return;
2164
67adc644
VS		 2165 /*
2166 * Double wide has implications for planes
2167 * so best keep it disabled when not needed.
2168 */
6e3c9717 2169 if (crtc->config->double_wide)
67adc644
VS		 2170 val &= ~PIPECONF_DOUBLE_WIDE;
2171
2172 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2173 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2174 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2175 val &= ~PIPECONF_ENABLE;
2176
2177 I915_WRITE(reg, val);
2178 if ((val & PIPECONF_ENABLE) == 0)
2179 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2180}
2181
d74362c9
KP		 2182/*
2183 * Plane regs are double buffered, going from enabled->disabled needs a
2184 * trigger in order to latch. The display address reg provides this.
2185 */
1dba99f4
VS		 2186void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2187 enum plane plane)
d74362c9 2188{
3d13ef2e
DL		 2189 struct drm_device *dev = dev_priv->dev;
2190 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1dba99f4
VS		 2191
2192 I915_WRITE(reg, I915_READ(reg));
2193 POSTING_READ(reg);
d74362c9
KP		 2194}
2195
b24e7179 2196/**
262ca2b0 2197 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
fdd508a6
VS		 2198 * @plane: plane to be enabled
2199 * @crtc: crtc for the plane
b24e7179 2200 *
fdd508a6 2201 * Enable @plane on @crtc, making sure that the pipe is running first.
b24e7179 2202 */
fdd508a6
VS		 2203static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2204 struct drm_crtc *crtc)
b24e7179 2205{
fdd508a6
VS		 2206 struct drm_device *dev = plane->dev;
2207 struct drm_i915_private *dev_priv = dev->dev_private;
2208 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b24e7179
JB		 2209
2210 /* If the pipe isn't enabled, we can't pump pixels and may hang */
fdd508a6 2211 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
b24e7179 2212
98ec7739
VS		 2213 if (intel_crtc->primary_enabled)
2214 return;
0037f71c 2215
4c445e0e 2216 intel_crtc->primary_enabled = true;
939c2fe8 2217
fdd508a6
VS		 2218 dev_priv->display.update_primary_plane(crtc, plane->fb,
2219 crtc->x, crtc->y);
33c3b0d1
VS		 2220
2221 /*
2222 * BDW signals flip done immediately if the plane
2223 * is disabled, even if the plane enable is already
2224 * armed to occur at the next vblank :(
2225 */
2226 if (IS_BROADWELL(dev))
2227 intel_wait_for_vblank(dev, intel_crtc->pipe);
b24e7179
JB		 2228}
2229
b24e7179 2230/**
262ca2b0 2231 * intel_disable_primary_hw_plane - disable the primary hardware plane
fdd508a6
VS		 2232 * @plane: plane to be disabled
2233 * @crtc: crtc for the plane
b24e7179 2234 *
fdd508a6 2235 * Disable @plane on @crtc, making sure that the pipe is running first.
b24e7179 2236 */
fdd508a6
VS		 2237static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2238 struct drm_crtc *crtc)
b24e7179 2239{
fdd508a6
VS		 2240 struct drm_device *dev = plane->dev;
2241 struct drm_i915_private *dev_priv = dev->dev_private;
2242 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2243
32b7eeec
MR		 2244 if (WARN_ON(!intel_crtc->active))
2245 return;
b24e7179 2246
98ec7739
VS		 2247 if (!intel_crtc->primary_enabled)
2248 return;
0037f71c 2249
4c445e0e 2250 intel_crtc->primary_enabled = false;
939c2fe8 2251
fdd508a6
VS		 2252 dev_priv->display.update_primary_plane(crtc, plane->fb,
2253 crtc->x, crtc->y);
b24e7179
JB		 2254}
2255
693db184
CW		 2256static bool need_vtd_wa(struct drm_device *dev)
2257{
2258#ifdef CONFIG_INTEL_IOMMU
2259 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2260 return true;
2261#endif
2262 return false;
2263}
2264
50470bb0 2265unsigned int
6761dd31
TU		 2266intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2267 uint64_t fb_format_modifier)
a57ce0b2 2268{
6761dd31
TU		 2269 unsigned int tile_height;
2270 uint32_t pixel_bytes;
a57ce0b2 2271
b5d0e9bf
DL		 2272 switch (fb_format_modifier) {
2273 case DRM_FORMAT_MOD_NONE:
2274 tile_height = 1;
2275 break;
2276 case I915_FORMAT_MOD_X_TILED:
2277 tile_height = IS_GEN2(dev) ? 16 : 8;
2278 break;
2279 case I915_FORMAT_MOD_Y_TILED:
2280 tile_height = 32;
2281 break;
2282 case I915_FORMAT_MOD_Yf_TILED:
6761dd31
TU		 2283 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2284 switch (pixel_bytes) {
b5d0e9bf 2285 default:
6761dd31 2286 case 1:
b5d0e9bf
DL		 2287 tile_height = 64;
2288 break;
6761dd31
TU		 2289 case 2:
2290 case 4:
b5d0e9bf
DL		 2291 tile_height = 32;
2292 break;
6761dd31 2293 case 8:
b5d0e9bf
DL		 2294 tile_height = 16;
2295 break;
6761dd31 2296 case 16:
b5d0e9bf
DL		 2297 WARN_ONCE(1,
2298 "128-bit pixels are not supported for display!");
2299 tile_height = 16;
2300 break;
2301 }
2302 break;
2303 default:
2304 MISSING_CASE(fb_format_modifier);
2305 tile_height = 1;
2306 break;
2307 }
091df6cb 2308
6761dd31
TU		 2309 return tile_height;
2310}
2311
2312unsigned int
2313intel_fb_align_height(struct drm_device *dev, unsigned int height,
2314 uint32_t pixel_format, uint64_t fb_format_modifier)
2315{
2316 return ALIGN(height, intel_tile_height(dev, pixel_format,
2317 fb_format_modifier));
a57ce0b2
JB		 2318}
2319
f64b98cd
TU		 2320static int
2321intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2322 const struct drm_plane_state *plane_state)
2323{
50470bb0 2324 struct intel_rotation_info *info = &view->rotation_info;
50470bb0 2325
f64b98cd
TU		 2326 *view = i915_ggtt_view_normal;
2327
50470bb0
TU		 2328 if (!plane_state)
2329 return 0;
2330
121920fa 2331 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2332 return 0;
2333
9abc4648 2334 *view = i915_ggtt_view_rotated;
50470bb0
TU		 2335
2336 info->height = fb->height;
2337 info->pixel_format = fb->pixel_format;
2338 info->pitch = fb->pitches[0];
2339 info->fb_modifier = fb->modifier[0];
2340
2341 if (!(info->fb_modifier == I915_FORMAT_MOD_Y_TILED ||
2342 info->fb_modifier == I915_FORMAT_MOD_Yf_TILED)) {
2343 DRM_DEBUG_KMS(
2344 "Y or Yf tiling is needed for 90/270 rotation!\n");
2345 return -EINVAL;
2346 }
2347
f64b98cd
TU		 2348 return 0;
2349}
2350
127bd2ac 2351int
850c4cdc
TU		 2352intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2353 struct drm_framebuffer *fb,
82bc3b2d 2354 const struct drm_plane_state *plane_state,
a4872ba6 2355 struct intel_engine_cs *pipelined)
6b95a207 2356{
850c4cdc 2357 struct drm_device *dev = fb->dev;
ce453d81 2358 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2359 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2360 struct i915_ggtt_view view;
6b95a207
KH		 2361 u32 alignment;
2362 int ret;
2363
ebcdd39e
MR		 2364 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2365
7b911adc
TU		 2366 switch (fb->modifier[0]) {
2367 case DRM_FORMAT_MOD_NONE:
1fada4cc
DL		 2368 if (INTEL_INFO(dev)->gen >= 9)
2369 alignment = 256 * 1024;
2370 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
534843da 2371 alignment = 128 * 1024;
a6c45cf0 2372 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 2373 alignment = 4 * 1024;
2374 else
2375 alignment = 64 * 1024;
6b95a207 2376 break;
7b911adc 2377 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2378 if (INTEL_INFO(dev)->gen >= 9)
2379 alignment = 256 * 1024;
2380 else {
2381 /* pin() will align the object as required by fence */
2382 alignment = 0;
2383 }
6b95a207 2384 break;
7b911adc 2385 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2386 case I915_FORMAT_MOD_Yf_TILED:
2387 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2388 "Y tiling bo slipped through, driver bug!\n"))
2389 return -EINVAL;
2390 alignment = 1 * 1024 * 1024;
2391 break;
6b95a207 2392 default:
7b911adc
TU		 2393 MISSING_CASE(fb->modifier[0]);
2394 return -EINVAL;
6b95a207
KH		 2395 }
2396
f64b98cd
TU		 2397 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2398 if (ret)
2399 return ret;
2400
693db184
CW		 2401 /* Note that the w/a also requires 64 PTE of padding following the
2402 * bo. We currently fill all unused PTE with the shadow page and so
2403 * we should always have valid PTE following the scanout preventing
2404 * the VT-d warning.
2405 */
2406 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2407 alignment = 256 * 1024;
2408
d6dd6843
PZ		 2409 /*
2410 * Global gtt pte registers are special registers which actually forward
2411 * writes to a chunk of system memory. Which means that there is no risk
2412 * that the register values disappear as soon as we call
2413 * intel_runtime_pm_put(), so it is correct to wrap only the
2414 * pin/unpin/fence and not more.
2415 */
2416 intel_runtime_pm_get(dev_priv);
2417
ce453d81 2418 dev_priv->mm.interruptible = false;
e6617330 2419 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
f64b98cd 2420 &view);
48b956c5 2421 if (ret)
ce453d81 2422 goto err_interruptible;
6b95a207
KH		 2423
2424 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2425 * fence, whereas 965+ only requires a fence if using
2426 * framebuffer compression. For simplicity, we always install
2427 * a fence as the cost is not that onerous.
2428 */
06d98131 2429 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2430 if (ret)
2431 goto err_unpin;
1690e1eb 2432
9a5a53b3 2433 i915_gem_object_pin_fence(obj);
6b95a207 2434
ce453d81 2435 dev_priv->mm.interruptible = true;
d6dd6843 2436 intel_runtime_pm_put(dev_priv);
6b95a207 2437 return 0;
48b956c5
CW		 2438
2439err_unpin:
f64b98cd 2440 i915_gem_object_unpin_from_display_plane(obj, &view);
ce453d81
CW		 2441err_interruptible:
2442 dev_priv->mm.interruptible = true;
d6dd6843 2443 intel_runtime_pm_put(dev_priv);
48b956c5 2444 return ret;
6b95a207
KH		 2445}
2446
82bc3b2d
TU		 2447static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2448 const struct drm_plane_state *plane_state)
1690e1eb 2449{
82bc3b2d 2450 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2451 struct i915_ggtt_view view;
2452 int ret;
82bc3b2d 2453
ebcdd39e
MR		 2454 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2455
f64b98cd
TU		 2456 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2457 WARN_ONCE(ret, "Couldn't get view from plane state!");
2458
1690e1eb 2459 i915_gem_object_unpin_fence(obj);
f64b98cd 2460 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2461}
2462
c2c75131
DV		 2463/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2464 * is assumed to be a power-of-two. */
bc752862
CW		 2465unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2466 unsigned int tiling_mode,
2467 unsigned int cpp,
2468 unsigned int pitch)
c2c75131 2469{
bc752862
CW		 2470 if (tiling_mode != I915_TILING_NONE) {
2471 unsigned int tile_rows, tiles;
c2c75131 2472
bc752862
CW		 2473 tile_rows = *y / 8;
2474 *y %= 8;
c2c75131 2475
bc752862
CW		 2476 tiles = *x / (512/cpp);
2477 *x %= 512/cpp;
2478
2479 return tile_rows * pitch * 8 + tiles * 4096;
2480 } else {
2481 unsigned int offset;
2482
2483 offset = *y * pitch + *x * cpp;
2484 *y = 0;
2485 *x = (offset & 4095) / cpp;
2486 return offset & -4096;
2487 }
c2c75131
DV		 2488}
2489
b35d63fa 2490static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2491{
2492 switch (format) {
2493 case DISPPLANE_8BPP:
2494 return DRM_FORMAT_C8;
2495 case DISPPLANE_BGRX555:
2496 return DRM_FORMAT_XRGB1555;
2497 case DISPPLANE_BGRX565:
2498 return DRM_FORMAT_RGB565;
2499 default:
2500 case DISPPLANE_BGRX888:
2501 return DRM_FORMAT_XRGB8888;
2502 case DISPPLANE_RGBX888:
2503 return DRM_FORMAT_XBGR8888;
2504 case DISPPLANE_BGRX101010:
2505 return DRM_FORMAT_XRGB2101010;
2506 case DISPPLANE_RGBX101010:
2507 return DRM_FORMAT_XBGR2101010;
2508 }
2509}
2510
bc8d7dff
DL		 2511static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2512{
2513 switch (format) {
2514 case PLANE_CTL_FORMAT_RGB_565:
2515 return DRM_FORMAT_RGB565;
2516 default:
2517 case PLANE_CTL_FORMAT_XRGB_8888:
2518 if (rgb_order) {
2519 if (alpha)
2520 return DRM_FORMAT_ABGR8888;
2521 else
2522 return DRM_FORMAT_XBGR8888;
2523 } else {
2524 if (alpha)
2525 return DRM_FORMAT_ARGB8888;
2526 else
2527 return DRM_FORMAT_XRGB8888;
2528 }
2529 case PLANE_CTL_FORMAT_XRGB_2101010:
2530 if (rgb_order)
2531 return DRM_FORMAT_XBGR2101010;
2532 else
2533 return DRM_FORMAT_XRGB2101010;
2534 }
2535}
2536
5724dbd1 2537static bool
f6936e29
DV		 2538intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2539 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2540{
2541 struct drm_device *dev = crtc->base.dev;
2542 struct drm_i915_gem_object *obj = NULL;
2543 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2544 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2545 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2546 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2547 PAGE_SIZE);
2548
2549 size_aligned -= base_aligned;
46f297fb 2550
ff2652ea
CW		 2551 if (plane_config->size == 0)
2552 return false;
2553
f37b5c2b
DV		 2554 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2555 base_aligned,
2556 base_aligned,
2557 size_aligned);
46f297fb 2558 if (!obj)
484b41dd 2559 return false;
46f297fb 2560
49af449b
DL		 2561 obj->tiling_mode = plane_config->tiling;
2562 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2563 obj->stride = fb->pitches[0];
46f297fb 2564
6bf129df
DL		 2565 mode_cmd.pixel_format = fb->pixel_format;
2566 mode_cmd.width = fb->width;
2567 mode_cmd.height = fb->height;
2568 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2569 mode_cmd.modifier[0] = fb->modifier[0];
2570 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2571
2572 mutex_lock(&dev->struct_mutex);
6bf129df 2573 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2574 &mode_cmd, obj)) {
46f297fb
JB		 2575 DRM_DEBUG_KMS("intel fb init failed\n");
2576 goto out_unref_obj;
2577 }
46f297fb 2578 mutex_unlock(&dev->struct_mutex);
484b41dd 2579
f6936e29 2580 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2581 return true;
46f297fb
JB		 2582
2583out_unref_obj:
2584 drm_gem_object_unreference(&obj->base);
2585 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2586 return false;
2587}
2588
afd65eb4
MR		 2589/* Update plane->state->fb to match plane->fb after driver-internal updates */
2590static void
2591update_state_fb(struct drm_plane *plane)
2592{
2593 if (plane->fb == plane->state->fb)
2594 return;
2595
2596 if (plane->state->fb)
2597 drm_framebuffer_unreference(plane->state->fb);
2598 plane->state->fb = plane->fb;
2599 if (plane->state->fb)
2600 drm_framebuffer_reference(plane->state->fb);
2601}
2602
5724dbd1 2603static void
f6936e29
DV		 2604intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2605 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2606{
2607 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2608 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2609 struct drm_crtc *c;
2610 struct intel_crtc *i;
2ff8fde1 2611 struct drm_i915_gem_object *obj;
88595ac9
DV		 2612 struct drm_plane *primary = intel_crtc->base.primary;
2613 struct drm_framebuffer *fb;
484b41dd 2614
2d14030b 2615 if (!plane_config->fb)
484b41dd
JB		 2616 return;
2617
f6936e29 2618 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2619 fb = &plane_config->fb->base;
2620 goto valid_fb;
f55548b5 2621 }
484b41dd 2622
2d14030b 2623 kfree(plane_config->fb);
484b41dd
JB		 2624
2625 /*
2626 * Failed to alloc the obj, check to see if we should share
2627 * an fb with another CRTC instead
2628 */
70e1e0ec 2629 for_each_crtc(dev, c) {
484b41dd
JB		 2630 i = to_intel_crtc(c);
2631
2632 if (c == &intel_crtc->base)
2633 continue;
2634
2ff8fde1
MR		 2635 if (!i->active)
2636 continue;
2637
88595ac9
DV		 2638 fb = c->primary->fb;
2639 if (!fb)
484b41dd
JB		 2640 continue;
2641
88595ac9 2642 obj = intel_fb_obj(fb);
2ff8fde1 2643 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2644 drm_framebuffer_reference(fb);
2645 goto valid_fb;
484b41dd
JB		 2646 }
2647 }
88595ac9
DV		 2648
2649 return;
2650
2651valid_fb:
2652 obj = intel_fb_obj(fb);
2653 if (obj->tiling_mode != I915_TILING_NONE)
2654 dev_priv->preserve_bios_swizzle = true;
2655
2656 primary->fb = fb;
2657 primary->state->crtc = &intel_crtc->base;
2658 primary->crtc = &intel_crtc->base;
2659 update_state_fb(primary);
2660 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
46f297fb
JB		 2661}
2662
29b9bde6
DV		 2663static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2664 struct drm_framebuffer *fb,
2665 int x, int y)
81255565
JB		 2666{
2667 struct drm_device *dev = crtc->dev;
2668 struct drm_i915_private *dev_priv = dev->dev_private;
2669 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
c9ba6fad 2670 struct drm_i915_gem_object *obj;
81255565 2671 int plane = intel_crtc->plane;
e506a0c6 2672 unsigned long linear_offset;
81255565 2673 u32 dspcntr;
f45651ba 2674 u32 reg = DSPCNTR(plane);
48404c1e 2675 int pixel_size;
f45651ba 2676
fdd508a6
VS		 2677 if (!intel_crtc->primary_enabled) {
2678 I915_WRITE(reg, 0);
2679 if (INTEL_INFO(dev)->gen >= 4)
2680 I915_WRITE(DSPSURF(plane), 0);
2681 else
2682 I915_WRITE(DSPADDR(plane), 0);
2683 POSTING_READ(reg);
2684 return;
2685 }
2686
c9ba6fad
VS		 2687 obj = intel_fb_obj(fb);
2688 if (WARN_ON(obj == NULL))
2689 return;
2690
2691 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2692
f45651ba
VS		 2693 dspcntr = DISPPLANE_GAMMA_ENABLE;
2694
fdd508a6 2695 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2696
2697 if (INTEL_INFO(dev)->gen < 4) {
2698 if (intel_crtc->pipe == PIPE_B)
2699 dspcntr |= DISPPLANE_SEL_PIPE_B;
2700
2701 /* pipesrc and dspsize control the size that is scaled from,
2702 * which should always be the user's requested size.
2703 */
2704 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2705 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2706 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2707 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2708 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2709 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2710 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2711 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2712 I915_WRITE(PRIMPOS(plane), 0);
2713 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2714 }
81255565 2715
57779d06
VS		 2716 switch (fb->pixel_format) {
2717 case DRM_FORMAT_C8:
81255565
JB		 2718 dspcntr |= DISPPLANE_8BPP;
2719 break;
57779d06
VS		 2720 case DRM_FORMAT_XRGB1555:
2721 case DRM_FORMAT_ARGB1555:
2722 dspcntr |= DISPPLANE_BGRX555;
81255565 2723 break;
57779d06
VS		 2724 case DRM_FORMAT_RGB565:
2725 dspcntr |= DISPPLANE_BGRX565;
2726 break;
2727 case DRM_FORMAT_XRGB8888:
2728 case DRM_FORMAT_ARGB8888:
2729 dspcntr |= DISPPLANE_BGRX888;
2730 break;
2731 case DRM_FORMAT_XBGR8888:
2732 case DRM_FORMAT_ABGR8888:
2733 dspcntr |= DISPPLANE_RGBX888;
2734 break;
2735 case DRM_FORMAT_XRGB2101010:
2736 case DRM_FORMAT_ARGB2101010:
2737 dspcntr |= DISPPLANE_BGRX101010;
2738 break;
2739 case DRM_FORMAT_XBGR2101010:
2740 case DRM_FORMAT_ABGR2101010:
2741 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2742 break;
2743 default:
baba133a 2744 BUG();
81255565 2745 }
57779d06 2746
f45651ba
VS		 2747 if (INTEL_INFO(dev)->gen >= 4 &&
2748 obj->tiling_mode != I915_TILING_NONE)
2749 dspcntr |= DISPPLANE_TILED;
81255565 2750
de1aa629
VS		 2751 if (IS_G4X(dev))
2752 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2753
b9897127 2754 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2755
c2c75131
DV		 2756 if (INTEL_INFO(dev)->gen >= 4) {
2757 intel_crtc->dspaddr_offset =
bc752862 2758 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2759 pixel_size,
bc752862 2760 fb->pitches[0]);
c2c75131
DV		 2761 linear_offset -= intel_crtc->dspaddr_offset;
2762 } else {
e506a0c6 2763 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2764 }
e506a0c6 2765
8e7d688b 2766 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2767 dspcntr |= DISPPLANE_ROTATE_180;
2768
6e3c9717
ACO		 2769 x += (intel_crtc->config->pipe_src_w - 1);
2770 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2771
2772 /* Finding the last pixel of the last line of the display
2773 data and adding to linear_offset*/
2774 linear_offset +=
6e3c9717
ACO		 2775 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2776 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2777 }
2778
2779 I915_WRITE(reg, dspcntr);
2780
01f2c773 2781 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2782 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2783 I915_WRITE(DSPSURF(plane),
2784 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2785 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2786 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2787 } else
f343c5f6 2788 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2789 POSTING_READ(reg);
17638cd6
JB		 2790}
2791
29b9bde6
DV		 2792static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2793 struct drm_framebuffer *fb,
2794 int x, int y)
17638cd6
JB		 2795{
2796 struct drm_device *dev = crtc->dev;
2797 struct drm_i915_private *dev_priv = dev->dev_private;
2798 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
c9ba6fad 2799 struct drm_i915_gem_object *obj;
17638cd6 2800 int plane = intel_crtc->plane;
e506a0c6 2801 unsigned long linear_offset;
17638cd6 2802 u32 dspcntr;
f45651ba 2803 u32 reg = DSPCNTR(plane);
48404c1e 2804 int pixel_size;
f45651ba 2805
fdd508a6
VS		 2806 if (!intel_crtc->primary_enabled) {
2807 I915_WRITE(reg, 0);
2808 I915_WRITE(DSPSURF(plane), 0);
2809 POSTING_READ(reg);
2810 return;
2811 }
2812
c9ba6fad
VS		 2813 obj = intel_fb_obj(fb);
2814 if (WARN_ON(obj == NULL))
2815 return;
2816
2817 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2818
f45651ba
VS		 2819 dspcntr = DISPPLANE_GAMMA_ENABLE;
2820
fdd508a6 2821 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2822
2823 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2824 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2825
57779d06
VS		 2826 switch (fb->pixel_format) {
2827 case DRM_FORMAT_C8:
17638cd6
JB		 2828 dspcntr |= DISPPLANE_8BPP;
2829 break;
57779d06
VS		 2830 case DRM_FORMAT_RGB565:
2831 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2832 break;
57779d06
VS		 2833 case DRM_FORMAT_XRGB8888:
2834 case DRM_FORMAT_ARGB8888:
2835 dspcntr |= DISPPLANE_BGRX888;
2836 break;
2837 case DRM_FORMAT_XBGR8888:
2838 case DRM_FORMAT_ABGR8888:
2839 dspcntr |= DISPPLANE_RGBX888;
2840 break;
2841 case DRM_FORMAT_XRGB2101010:
2842 case DRM_FORMAT_ARGB2101010:
2843 dspcntr |= DISPPLANE_BGRX101010;
2844 break;
2845 case DRM_FORMAT_XBGR2101010:
2846 case DRM_FORMAT_ABGR2101010:
2847 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2848 break;
2849 default:
baba133a 2850 BUG();
17638cd6
JB		 2851 }
2852
2853 if (obj->tiling_mode != I915_TILING_NONE)
2854 dspcntr |= DISPPLANE_TILED;
17638cd6 2855
f45651ba 2856 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2857 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2858
b9897127 2859 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2860 intel_crtc->dspaddr_offset =
bc752862 2861 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2862 pixel_size,
bc752862 2863 fb->pitches[0]);
c2c75131 2864 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2865 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2866 dspcntr |= DISPPLANE_ROTATE_180;
2867
2868 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2869 x += (intel_crtc->config->pipe_src_w - 1);
2870 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2871
2872 /* Finding the last pixel of the last line of the display
2873 data and adding to linear_offset*/
2874 linear_offset +=
6e3c9717
ACO		 2875 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2876 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2877 }
2878 }
2879
2880 I915_WRITE(reg, dspcntr);
17638cd6 2881
01f2c773 2882 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2883 I915_WRITE(DSPSURF(plane),
2884 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2885 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2886 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2887 } else {
2888 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2889 I915_WRITE(DSPLINOFF(plane), linear_offset);
2890 }
17638cd6 2891 POSTING_READ(reg);
17638cd6
JB		 2892}
2893
b321803d
DL		 2894u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2895 uint32_t pixel_format)
2896{
2897 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2898
2899 /*
2900 * The stride is either expressed as a multiple of 64 bytes
2901 * chunks for linear buffers or in number of tiles for tiled
2902 * buffers.
2903 */
2904 switch (fb_modifier) {
2905 case DRM_FORMAT_MOD_NONE:
2906 return 64;
2907 case I915_FORMAT_MOD_X_TILED:
2908 if (INTEL_INFO(dev)->gen == 2)
2909 return 128;
2910 return 512;
2911 case I915_FORMAT_MOD_Y_TILED:
2912 /* No need to check for old gens and Y tiling since this is
2913 * about the display engine and those will be blocked before
2914 * we get here.
2915 */
2916 return 128;
2917 case I915_FORMAT_MOD_Yf_TILED:
2918 if (bits_per_pixel == 8)
2919 return 64;
2920 else
2921 return 128;
2922 default:
2923 MISSING_CASE(fb_modifier);
2924 return 64;
2925 }
2926}
2927
121920fa
TU		 2928unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2929 struct drm_i915_gem_object *obj)
2930{
9abc4648 2931 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
121920fa
TU		 2932
2933 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2934 view = &i915_ggtt_view_rotated;
121920fa
TU		 2935
2936 return i915_gem_obj_ggtt_offset_view(obj, view);
2937}
2938
70d21f0e
DL		 2939static void skylake_update_primary_plane(struct drm_crtc *crtc,
2940 struct drm_framebuffer *fb,
2941 int x, int y)
2942{
2943 struct drm_device *dev = crtc->dev;
2944 struct drm_i915_private *dev_priv = dev->dev_private;
2945 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
70d21f0e
DL		 2946 struct drm_i915_gem_object *obj;
2947 int pipe = intel_crtc->pipe;
b321803d 2948 u32 plane_ctl, stride_div;
121920fa 2949 unsigned long surf_addr;
70d21f0e
DL		 2950
2951 if (!intel_crtc->primary_enabled) {
2952 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2953 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2954 POSTING_READ(PLANE_CTL(pipe, 0));
2955 return;
2956 }
2957
2958 plane_ctl = PLANE_CTL_ENABLE |
2959 PLANE_CTL_PIPE_GAMMA_ENABLE |
2960 PLANE_CTL_PIPE_CSC_ENABLE;
2961
2962 switch (fb->pixel_format) {
2963 case DRM_FORMAT_RGB565:
2964 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2965 break;
2966 case DRM_FORMAT_XRGB8888:
2967 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2968 break;
f75fb42a
JN		 2969 case DRM_FORMAT_ARGB8888:
2970 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2971 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2972 break;
70d21f0e
DL		 2973 case DRM_FORMAT_XBGR8888:
2974 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2975 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2976 break;
f75fb42a
JN		 2977 case DRM_FORMAT_ABGR8888:
2978 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2979 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2980 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2981 break;
70d21f0e
DL		 2982 case DRM_FORMAT_XRGB2101010:
2983 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2984 break;
2985 case DRM_FORMAT_XBGR2101010:
2986 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2987 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2988 break;
2989 default:
2990 BUG();
2991 }
2992
30af77c4
DV		 2993 switch (fb->modifier[0]) {
2994 case DRM_FORMAT_MOD_NONE:
70d21f0e 2995 break;
30af77c4 2996 case I915_FORMAT_MOD_X_TILED:
70d21f0e 2997 plane_ctl |= PLANE_CTL_TILED_X;
b321803d
DL		 2998 break;
2999 case I915_FORMAT_MOD_Y_TILED:
3000 plane_ctl |= PLANE_CTL_TILED_Y;
3001 break;
3002 case I915_FORMAT_MOD_Yf_TILED:
3003 plane_ctl |= PLANE_CTL_TILED_YF;
70d21f0e
DL		 3004 break;
3005 default:
b321803d 3006 MISSING_CASE(fb->modifier[0]);
70d21f0e
DL		 3007 }
3008
3009 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
8e7d688b 3010 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180))
1447dde0 3011 plane_ctl |= PLANE_CTL_ROTATE_180;
70d21f0e 3012
b321803d
DL		 3013 obj = intel_fb_obj(fb);
3014 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3015 fb->pixel_format);
121920fa 3016 surf_addr = intel_plane_obj_offset(to_intel_plane(crtc->primary), obj);
b321803d 3017
70d21f0e 3018 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
70d21f0e
DL		 3019 I915_WRITE(PLANE_POS(pipe, 0), 0);
3020 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
3021 I915_WRITE(PLANE_SIZE(pipe, 0),
6e3c9717
ACO		 3022 (intel_crtc->config->pipe_src_h - 1) << 16 |
3023 (intel_crtc->config->pipe_src_w - 1));
b321803d 3024 I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
121920fa 3025 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3026
3027 POSTING_READ(PLANE_SURF(pipe, 0));
3028}
3029
17638cd6
JB		 3030/* Assume fb object is pinned & idle & fenced and just update base pointers */
3031static int
3032intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3033 int x, int y, enum mode_set_atomic state)
3034{
3035 struct drm_device *dev = crtc->dev;
3036 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3037
6b8e6ed0
CW		 3038 if (dev_priv->display.disable_fbc)
3039 dev_priv->display.disable_fbc(dev);
81255565 3040
29b9bde6
DV		 3041 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3042
3043 return 0;
81255565
JB		 3044}
3045
7514747d 3046static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3047{
96a02917
VS		 3048 struct drm_crtc *crtc;
3049
70e1e0ec 3050 for_each_crtc(dev, crtc) {
96a02917
VS		 3051 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3052 enum plane plane = intel_crtc->plane;
3053
3054 intel_prepare_page_flip(dev, plane);
3055 intel_finish_page_flip_plane(dev, plane);
3056 }
7514747d
VS		 3057}
3058
3059static void intel_update_primary_planes(struct drm_device *dev)
3060{
3061 struct drm_i915_private *dev_priv = dev->dev_private;
3062 struct drm_crtc *crtc;
96a02917 3063
70e1e0ec 3064 for_each_crtc(dev, crtc) {
96a02917
VS		 3065 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3066
51fd371b 3067 drm_modeset_lock(&crtc->mutex, NULL);
947fdaad
CW		 3068 /*
3069 * FIXME: Once we have proper support for primary planes (and
3070 * disabling them without disabling the entire crtc) allow again
66e514c1 3071 * a NULL crtc->primary->fb.
947fdaad 3072 */
f4510a27 3073 if (intel_crtc->active && crtc->primary->fb)
262ca2b0 3074 dev_priv->display.update_primary_plane(crtc,
66e514c1 3075 crtc->primary->fb,
262ca2b0
MR		 3076 crtc->x,
3077 crtc->y);
51fd371b 3078 drm_modeset_unlock(&crtc->mutex);
96a02917
VS		 3079 }
3080}
3081
7514747d
VS		 3082void intel_prepare_reset(struct drm_device *dev)
3083{
f98ce92f
VS		 3084 struct drm_i915_private *dev_priv = to_i915(dev);
3085 struct intel_crtc *crtc;
3086
7514747d
VS		 3087 /* no reset support for gen2 */
3088 if (IS_GEN2(dev))
3089 return;
3090
3091 /* reset doesn't touch the display */
3092 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3093 return;
3094
3095 drm_modeset_lock_all(dev);
f98ce92f
VS		 3096
3097 /*
3098 * Disabling the crtcs gracefully seems nicer. Also the
3099 * g33 docs say we should at least disable all the planes.
3100 */
3101 for_each_intel_crtc(dev, crtc) {
3102 if (crtc->active)
3103 dev_priv->display.crtc_disable(&crtc->base);
3104 }
7514747d
VS		 3105}
3106
3107void intel_finish_reset(struct drm_device *dev)
3108{
3109 struct drm_i915_private *dev_priv = to_i915(dev);
3110
3111 /*
3112 * Flips in the rings will be nuked by the reset,
3113 * so complete all pending flips so that user space
3114 * will get its events and not get stuck.
3115 */
3116 intel_complete_page_flips(dev);
3117
3118 /* no reset support for gen2 */
3119 if (IS_GEN2(dev))
3120 return;
3121
3122 /* reset doesn't touch the display */
3123 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3124 /*
3125 * Flips in the rings have been nuked by the reset,
3126 * so update the base address of all primary
3127 * planes to the the last fb to make sure we're
3128 * showing the correct fb after a reset.
3129 */
3130 intel_update_primary_planes(dev);
3131 return;
3132 }
3133
3134 /*
3135 * The display has been reset as well,
3136 * so need a full re-initialization.
3137 */
3138 intel_runtime_pm_disable_interrupts(dev_priv);
3139 intel_runtime_pm_enable_interrupts(dev_priv);
3140
3141 intel_modeset_init_hw(dev);
3142
3143 spin_lock_irq(&dev_priv->irq_lock);
3144 if (dev_priv->display.hpd_irq_setup)
3145 dev_priv->display.hpd_irq_setup(dev);
3146 spin_unlock_irq(&dev_priv->irq_lock);
3147
3148 intel_modeset_setup_hw_state(dev, true);
3149
3150 intel_hpd_init(dev_priv);
3151
3152 drm_modeset_unlock_all(dev);
3153}
3154
14667a4b
CW		 3155static int
3156intel_finish_fb(struct drm_framebuffer *old_fb)
3157{
2ff8fde1 3158 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
14667a4b
CW		 3159 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3160 bool was_interruptible = dev_priv->mm.interruptible;
3161 int ret;
3162
14667a4b
CW		 3163 /* Big Hammer, we also need to ensure that any pending
3164 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3165 * current scanout is retired before unpinning the old
3166 * framebuffer.
3167 *
3168 * This should only fail upon a hung GPU, in which case we
3169 * can safely continue.
3170 */
3171 dev_priv->mm.interruptible = false;
3172 ret = i915_gem_object_finish_gpu(obj);
3173 dev_priv->mm.interruptible = was_interruptible;
3174
3175 return ret;
3176}
3177
7d5e3799
CW		 3178static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3179{
3180 struct drm_device *dev = crtc->dev;
3181 struct drm_i915_private *dev_priv = dev->dev_private;
3182 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3183 bool pending;
3184
3185 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3186 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3187 return false;
3188
5e2d7afc 3189 spin_lock_irq(&dev->event_lock);
7d5e3799 3190 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3191 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3192
3193 return pending;
3194}
3195
e30e8f75
GP		 3196static void intel_update_pipe_size(struct intel_crtc *crtc)
3197{
3198 struct drm_device *dev = crtc->base.dev;
3199 struct drm_i915_private *dev_priv = dev->dev_private;
3200 const struct drm_display_mode *adjusted_mode;
3201
3202 if (!i915.fastboot)
3203 return;
3204
3205 /*
3206 * Update pipe size and adjust fitter if needed: the reason for this is
3207 * that in compute_mode_changes we check the native mode (not the pfit
3208 * mode) to see if we can flip rather than do a full mode set. In the
3209 * fastboot case, we'll flip, but if we don't update the pipesrc and
3210 * pfit state, we'll end up with a big fb scanned out into the wrong
3211 * sized surface.
3212 *
3213 * To fix this properly, we need to hoist the checks up into
3214 * compute_mode_changes (or above), check the actual pfit state and
3215 * whether the platform allows pfit disable with pipe active, and only
3216 * then update the pipesrc and pfit state, even on the flip path.
3217 */
3218
6e3c9717 3219 adjusted_mode = &crtc->config->base.adjusted_mode;
e30e8f75
GP		 3220
3221 I915_WRITE(PIPESRC(crtc->pipe),
3222 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3223 (adjusted_mode->crtc_vdisplay - 1));
6e3c9717 3224 if (!crtc->config->pch_pfit.enabled &&
409ee761
ACO		 3225 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3226 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
e30e8f75
GP		 3227 I915_WRITE(PF_CTL(crtc->pipe), 0);
3228 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3229 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3230 }
6e3c9717
ACO		 3231 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3232 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
e30e8f75
GP		 3233}
3234
5e84e1a4
ZW		 3235static void intel_fdi_normal_train(struct drm_crtc *crtc)
3236{
3237 struct drm_device *dev = crtc->dev;
3238 struct drm_i915_private *dev_priv = dev->dev_private;
3239 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3240 int pipe = intel_crtc->pipe;
3241 u32 reg, temp;
3242
3243 /* enable normal train */
3244 reg = FDI_TX_CTL(pipe);
3245 temp = I915_READ(reg);
61e499bf 3246 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3247 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3248 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3249 } else {
3250 temp &= ~FDI_LINK_TRAIN_NONE;
3251 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3252 }
5e84e1a4
ZW		 3253 I915_WRITE(reg, temp);
3254
3255 reg = FDI_RX_CTL(pipe);
3256 temp = I915_READ(reg);
3257 if (HAS_PCH_CPT(dev)) {
3258 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3259 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3260 } else {
3261 temp &= ~FDI_LINK_TRAIN_NONE;
3262 temp |= FDI_LINK_TRAIN_NONE;
3263 }
3264 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3265
3266 /* wait one idle pattern time */
3267 POSTING_READ(reg);
3268 udelay(1000);
357555c0
JB		 3269
3270 /* IVB wants error correction enabled */
3271 if (IS_IVYBRIDGE(dev))
3272 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3273 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3274}
3275
8db9d77b
ZW		 3276/* The FDI link training functions for ILK/Ibexpeak. */
3277static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3278{
3279 struct drm_device *dev = crtc->dev;
3280 struct drm_i915_private *dev_priv = dev->dev_private;
3281 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3282 int pipe = intel_crtc->pipe;
5eddb70b 3283 u32 reg, temp, tries;
8db9d77b 3284
1c8562f6 3285 /* FDI needs bits from pipe first */
0fc932b8 3286 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3287
e1a44743
AJ		 3288 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3289 for train result */
5eddb70b
CW		 3290 reg = FDI_RX_IMR(pipe);
3291 temp = I915_READ(reg);
e1a44743
AJ		 3292 temp &= ~FDI_RX_SYMBOL_LOCK;
3293 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3294 I915_WRITE(reg, temp);
3295 I915_READ(reg);
e1a44743
AJ		 3296 udelay(150);
3297
8db9d77b 3298 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3299 reg = FDI_TX_CTL(pipe);
3300 temp = I915_READ(reg);
627eb5a3 3301 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3302 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3303 temp &= ~FDI_LINK_TRAIN_NONE;
3304 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3305 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3306
5eddb70b
CW		 3307 reg = FDI_RX_CTL(pipe);
3308 temp = I915_READ(reg);
8db9d77b
ZW		 3309 temp &= ~FDI_LINK_TRAIN_NONE;
3310 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3311 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3312
3313 POSTING_READ(reg);
8db9d77b
ZW		 3314 udelay(150);
3315
5b2adf89 3316 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3317 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3318 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3319 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3320
5eddb70b 3321 reg = FDI_RX_IIR(pipe);
e1a44743 3322 for (tries = 0; tries < 5; tries++) {
5eddb70b 3323 temp = I915_READ(reg);
8db9d77b
ZW		 3324 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3325
3326 if ((temp & FDI_RX_BIT_LOCK)) {
3327 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3328 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3329 break;
3330 }
8db9d77b 3331 }
e1a44743 3332 if (tries == 5)
5eddb70b 3333 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3334
3335 /* Train 2 */
5eddb70b
CW		 3336 reg = FDI_TX_CTL(pipe);
3337 temp = I915_READ(reg);
8db9d77b
ZW		 3338 temp &= ~FDI_LINK_TRAIN_NONE;
3339 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3340 I915_WRITE(reg, temp);
8db9d77b 3341
5eddb70b
CW		 3342 reg = FDI_RX_CTL(pipe);
3343 temp = I915_READ(reg);
8db9d77b
ZW		 3344 temp &= ~FDI_LINK_TRAIN_NONE;
3345 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3346 I915_WRITE(reg, temp);
8db9d77b 3347
5eddb70b
CW		 3348 POSTING_READ(reg);
3349 udelay(150);
8db9d77b 3350
5eddb70b 3351 reg = FDI_RX_IIR(pipe);
e1a44743 3352 for (tries = 0; tries < 5; tries++) {
5eddb70b 3353 temp = I915_READ(reg);
8db9d77b
ZW		 3354 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3355
3356 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3357 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3358 DRM_DEBUG_KMS("FDI train 2 done.\n");
3359 break;
3360 }
8db9d77b 3361 }
e1a44743 3362 if (tries == 5)
5eddb70b 3363 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3364
3365 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3366
8db9d77b
ZW		 3367}
3368
0206e353 3369static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3370 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3371 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3372 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3373 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3374};
3375
3376/* The FDI link training functions for SNB/Cougarpoint. */
3377static void gen6_fdi_link_train(struct drm_crtc *crtc)
3378{
3379 struct drm_device *dev = crtc->dev;
3380 struct drm_i915_private *dev_priv = dev->dev_private;
3381 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3382 int pipe = intel_crtc->pipe;
fa37d39e 3383 u32 reg, temp, i, retry;
8db9d77b 3384
e1a44743
AJ		 3385 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3386 for train result */
5eddb70b
CW		 3387 reg = FDI_RX_IMR(pipe);
3388 temp = I915_READ(reg);
e1a44743
AJ		 3389 temp &= ~FDI_RX_SYMBOL_LOCK;
3390 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3391 I915_WRITE(reg, temp);
3392
3393 POSTING_READ(reg);
e1a44743
AJ		 3394 udelay(150);
3395
8db9d77b 3396 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3397 reg = FDI_TX_CTL(pipe);
3398 temp = I915_READ(reg);
627eb5a3 3399 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3400 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3401 temp &= ~FDI_LINK_TRAIN_NONE;
3402 temp |= FDI_LINK_TRAIN_PATTERN_1;
3403 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3404 /* SNB-B */
3405 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3406 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3407
d74cf324
DV		 3408 I915_WRITE(FDI_RX_MISC(pipe),
3409 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3410
5eddb70b
CW		 3411 reg = FDI_RX_CTL(pipe);
3412 temp = I915_READ(reg);
8db9d77b
ZW		 3413 if (HAS_PCH_CPT(dev)) {
3414 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3415 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3416 } else {
3417 temp &= ~FDI_LINK_TRAIN_NONE;
3418 temp |= FDI_LINK_TRAIN_PATTERN_1;
3419 }
5eddb70b
CW		 3420 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3421
3422 POSTING_READ(reg);
8db9d77b
ZW		 3423 udelay(150);
3424
0206e353 3425 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3426 reg = FDI_TX_CTL(pipe);
3427 temp = I915_READ(reg);
8db9d77b
ZW		 3428 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3429 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3430 I915_WRITE(reg, temp);
3431
3432 POSTING_READ(reg);
8db9d77b
ZW		 3433 udelay(500);
3434
fa37d39e
SP		 3435 for (retry = 0; retry < 5; retry++) {
3436 reg = FDI_RX_IIR(pipe);
3437 temp = I915_READ(reg);
3438 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3439 if (temp & FDI_RX_BIT_LOCK) {
3440 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3441 DRM_DEBUG_KMS("FDI train 1 done.\n");
3442 break;
3443 }
3444 udelay(50);
8db9d77b 3445 }
fa37d39e
SP		 3446 if (retry < 5)
3447 break;
8db9d77b
ZW		 3448 }
3449 if (i == 4)
5eddb70b 3450 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3451
3452 /* Train 2 */
5eddb70b
CW		 3453 reg = FDI_TX_CTL(pipe);
3454 temp = I915_READ(reg);
8db9d77b
ZW		 3455 temp &= ~FDI_LINK_TRAIN_NONE;
3456 temp |= FDI_LINK_TRAIN_PATTERN_2;
3457 if (IS_GEN6(dev)) {
3458 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3459 /* SNB-B */
3460 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3461 }
5eddb70b 3462 I915_WRITE(reg, temp);
8db9d77b 3463
5eddb70b
CW		 3464 reg = FDI_RX_CTL(pipe);
3465 temp = I915_READ(reg);
8db9d77b
ZW		 3466 if (HAS_PCH_CPT(dev)) {
3467 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3468 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3469 } else {
3470 temp &= ~FDI_LINK_TRAIN_NONE;
3471 temp |= FDI_LINK_TRAIN_PATTERN_2;
3472 }
5eddb70b
CW		 3473 I915_WRITE(reg, temp);
3474
3475 POSTING_READ(reg);
8db9d77b
ZW		 3476 udelay(150);
3477
0206e353 3478 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3479 reg = FDI_TX_CTL(pipe);
3480 temp = I915_READ(reg);
8db9d77b
ZW		 3481 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3482 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3483 I915_WRITE(reg, temp);
3484
3485 POSTING_READ(reg);
8db9d77b
ZW		 3486 udelay(500);
3487
fa37d39e
SP		 3488 for (retry = 0; retry < 5; retry++) {
3489 reg = FDI_RX_IIR(pipe);
3490 temp = I915_READ(reg);
3491 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3492 if (temp & FDI_RX_SYMBOL_LOCK) {
3493 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3494 DRM_DEBUG_KMS("FDI train 2 done.\n");
3495 break;
3496 }
3497 udelay(50);
8db9d77b 3498 }
fa37d39e
SP		 3499 if (retry < 5)
3500 break;
8db9d77b
ZW		 3501 }
3502 if (i == 4)
5eddb70b 3503 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3504
3505 DRM_DEBUG_KMS("FDI train done.\n");
3506}
3507
357555c0
JB		 3508/* Manual link training for Ivy Bridge A0 parts */
3509static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3510{
3511 struct drm_device *dev = crtc->dev;
3512 struct drm_i915_private *dev_priv = dev->dev_private;
3513 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3514 int pipe = intel_crtc->pipe;
139ccd3f 3515 u32 reg, temp, i, j;
357555c0
JB		 3516
3517 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3518 for train result */
3519 reg = FDI_RX_IMR(pipe);
3520 temp = I915_READ(reg);
3521 temp &= ~FDI_RX_SYMBOL_LOCK;
3522 temp &= ~FDI_RX_BIT_LOCK;
3523 I915_WRITE(reg, temp);
3524
3525 POSTING_READ(reg);
3526 udelay(150);
3527
01a415fd
DV		 3528 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3529 I915_READ(FDI_RX_IIR(pipe)));
3530
139ccd3f
JB		 3531 /* Try each vswing and preemphasis setting twice before moving on */
3532 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3533 /* disable first in case we need to retry */
3534 reg = FDI_TX_CTL(pipe);
3535 temp = I915_READ(reg);
3536 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3537 temp &= ~FDI_TX_ENABLE;
3538 I915_WRITE(reg, temp);
357555c0 3539
139ccd3f
JB		 3540 reg = FDI_RX_CTL(pipe);
3541 temp = I915_READ(reg);
3542 temp &= ~FDI_LINK_TRAIN_AUTO;
3543 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3544 temp &= ~FDI_RX_ENABLE;
3545 I915_WRITE(reg, temp);
357555c0 3546
139ccd3f 3547 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3548 reg = FDI_TX_CTL(pipe);
3549 temp = I915_READ(reg);
139ccd3f 3550 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3551 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3552 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3553 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3554 temp |= snb_b_fdi_train_param[j/2];
3555 temp |= FDI_COMPOSITE_SYNC;
3556 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3557
139ccd3f
JB		 3558 I915_WRITE(FDI_RX_MISC(pipe),
3559 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3560
139ccd3f 3561 reg = FDI_RX_CTL(pipe);
357555c0 3562 temp = I915_READ(reg);
139ccd3f
JB		 3563 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3564 temp |= FDI_COMPOSITE_SYNC;
3565 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3566
139ccd3f
JB		 3567 POSTING_READ(reg);
3568 udelay(1); /* should be 0.5us */
357555c0 3569
139ccd3f
JB		 3570 for (i = 0; i < 4; i++) {
3571 reg = FDI_RX_IIR(pipe);
3572 temp = I915_READ(reg);
3573 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3574
139ccd3f
JB		 3575 if (temp & FDI_RX_BIT_LOCK ||
3576 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3577 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3578 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3579 i);
3580 break;
3581 }
3582 udelay(1); /* should be 0.5us */
3583 }
3584 if (i == 4) {
3585 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3586 continue;
3587 }
357555c0 3588
139ccd3f 3589 /* Train 2 */
357555c0
JB		 3590 reg = FDI_TX_CTL(pipe);
3591 temp = I915_READ(reg);
139ccd3f
JB		 3592 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3593 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3594 I915_WRITE(reg, temp);
3595
3596 reg = FDI_RX_CTL(pipe);
3597 temp = I915_READ(reg);
3598 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3599 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3600 I915_WRITE(reg, temp);
3601
3602 POSTING_READ(reg);
139ccd3f 3603 udelay(2); /* should be 1.5us */
357555c0 3604
139ccd3f
JB		 3605 for (i = 0; i < 4; i++) {
3606 reg = FDI_RX_IIR(pipe);
3607 temp = I915_READ(reg);
3608 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3609
139ccd3f
JB		 3610 if (temp & FDI_RX_SYMBOL_LOCK ||
3611 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3612 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3613 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3614 i);
3615 goto train_done;
3616 }
3617 udelay(2); /* should be 1.5us */
357555c0 3618 }
139ccd3f
JB		 3619 if (i == 4)
3620 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3621 }
357555c0 3622
139ccd3f 3623train_done:
357555c0
JB		 3624 DRM_DEBUG_KMS("FDI train done.\n");
3625}
3626
88cefb6c 3627static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3628{
88cefb6c 3629 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3630 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3631 int pipe = intel_crtc->pipe;
5eddb70b 3632 u32 reg, temp;
79e53945 3633
c64e311e 3634
c98e9dcf 3635 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3636 reg = FDI_RX_CTL(pipe);
3637 temp = I915_READ(reg);
627eb5a3 3638 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3639 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3640 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3641 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3642
3643 POSTING_READ(reg);
c98e9dcf
JB		 3644 udelay(200);
3645
3646 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3647 temp = I915_READ(reg);
3648 I915_WRITE(reg, temp | FDI_PCDCLK);
3649
3650 POSTING_READ(reg);
c98e9dcf
JB		 3651 udelay(200);
3652
20749730
PZ		 3653 /* Enable CPU FDI TX PLL, always on for Ironlake */
3654 reg = FDI_TX_CTL(pipe);
3655 temp = I915_READ(reg);
3656 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3657 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3658
20749730
PZ		 3659 POSTING_READ(reg);
3660 udelay(100);
6be4a607 3661 }
0e23b99d
JB		 3662}
3663
88cefb6c
DV		 3664static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3665{
3666 struct drm_device *dev = intel_crtc->base.dev;
3667 struct drm_i915_private *dev_priv = dev->dev_private;
3668 int pipe = intel_crtc->pipe;
3669 u32 reg, temp;
3670
3671 /* Switch from PCDclk to Rawclk */
3672 reg = FDI_RX_CTL(pipe);
3673 temp = I915_READ(reg);
3674 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3675
3676 /* Disable CPU FDI TX PLL */
3677 reg = FDI_TX_CTL(pipe);
3678 temp = I915_READ(reg);
3679 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3680
3681 POSTING_READ(reg);
3682 udelay(100);
3683
3684 reg = FDI_RX_CTL(pipe);
3685 temp = I915_READ(reg);
3686 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3687
3688 /* Wait for the clocks to turn off. */
3689 POSTING_READ(reg);
3690 udelay(100);
3691}
3692
0fc932b8
JB		 3693static void ironlake_fdi_disable(struct drm_crtc *crtc)
3694{
3695 struct drm_device *dev = crtc->dev;
3696 struct drm_i915_private *dev_priv = dev->dev_private;
3697 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3698 int pipe = intel_crtc->pipe;
3699 u32 reg, temp;
3700
3701 /* disable CPU FDI tx and PCH FDI rx */
3702 reg = FDI_TX_CTL(pipe);
3703 temp = I915_READ(reg);
3704 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3705 POSTING_READ(reg);
3706
3707 reg = FDI_RX_CTL(pipe);
3708 temp = I915_READ(reg);
3709 temp &= ~(0x7 << 16);
dfd07d72 3710 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3711 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3712
3713 POSTING_READ(reg);
3714 udelay(100);
3715
3716 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3717 if (HAS_PCH_IBX(dev))
6f06ce18 3718 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3719
3720 /* still set train pattern 1 */
3721 reg = FDI_TX_CTL(pipe);
3722 temp = I915_READ(reg);
3723 temp &= ~FDI_LINK_TRAIN_NONE;
3724 temp |= FDI_LINK_TRAIN_PATTERN_1;
3725 I915_WRITE(reg, temp);
3726
3727 reg = FDI_RX_CTL(pipe);
3728 temp = I915_READ(reg);
3729 if (HAS_PCH_CPT(dev)) {
3730 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3731 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3732 } else {
3733 temp &= ~FDI_LINK_TRAIN_NONE;
3734 temp |= FDI_LINK_TRAIN_PATTERN_1;
3735 }
3736 /* BPC in FDI rx is consistent with that in PIPECONF */
3737 temp &= ~(0x07 << 16);
dfd07d72 3738 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3739 I915_WRITE(reg, temp);
3740
3741 POSTING_READ(reg);
3742 udelay(100);
3743}
3744
5dce5b93
CW		 3745bool intel_has_pending_fb_unpin(struct drm_device *dev)
3746{
3747 struct intel_crtc *crtc;
3748
3749 /* Note that we don't need to be called with mode_config.lock here
3750 * as our list of CRTC objects is static for the lifetime of the
3751 * device and so cannot disappear as we iterate. Similarly, we can
3752 * happily treat the predicates as racy, atomic checks as userspace
3753 * cannot claim and pin a new fb without at least acquring the
3754 * struct_mutex and so serialising with us.
3755 */
d3fcc808 3756 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3757 if (atomic_read(&crtc->unpin_work_count) == 0)
3758 continue;
3759
3760 if (crtc->unpin_work)
3761 intel_wait_for_vblank(dev, crtc->pipe);
3762
3763 return true;
3764 }
3765
3766 return false;
3767}
3768
d6bbafa1
CW		 3769static void page_flip_completed(struct intel_crtc *intel_crtc)
3770{
3771 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3772 struct intel_unpin_work *work = intel_crtc->unpin_work;
3773
3774 /* ensure that the unpin work is consistent wrt ->pending. */
3775 smp_rmb();
3776 intel_crtc->unpin_work = NULL;
3777
3778 if (work->event)
3779 drm_send_vblank_event(intel_crtc->base.dev,
3780 intel_crtc->pipe,
3781 work->event);
3782
3783 drm_crtc_vblank_put(&intel_crtc->base);
3784
3785 wake_up_all(&dev_priv->pending_flip_queue);
3786 queue_work(dev_priv->wq, &work->work);
3787
3788 trace_i915_flip_complete(intel_crtc->plane,
3789 work->pending_flip_obj);
3790}
3791
46a55d30 3792void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3793{
0f91128d 3794 struct drm_device *dev = crtc->dev;
5bb61643 3795 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3796
2c10d571 3797 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW		 3798 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3799 !intel_crtc_has_pending_flip(crtc),
3800 60*HZ) == 0)) {
3801 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3802
5e2d7afc 3803 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3804 if (intel_crtc->unpin_work) {
3805 WARN_ONCE(1, "Removing stuck page flip\n");
3806 page_flip_completed(intel_crtc);
3807 }
5e2d7afc 3808 spin_unlock_irq(&dev->event_lock);
9c787942 3809 }
5bb61643 3810
975d568a
CW		 3811 if (crtc->primary->fb) {
3812 mutex_lock(&dev->struct_mutex);
3813 intel_finish_fb(crtc->primary->fb);
3814 mutex_unlock(&dev->struct_mutex);
3815 }
e6c3a2a6
CW		 3816}
3817
e615efe4
ED		 3818/* Program iCLKIP clock to the desired frequency */
3819static void lpt_program_iclkip(struct drm_crtc *crtc)
3820{
3821 struct drm_device *dev = crtc->dev;
3822 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3823 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3824 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3825 u32 temp;
3826
09153000
DV		 3827 mutex_lock(&dev_priv->dpio_lock);
3828
e615efe4
ED		 3829 /* It is necessary to ungate the pixclk gate prior to programming
3830 * the divisors, and gate it back when it is done.
3831 */
3832 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3833
3834 /* Disable SSCCTL */
3835 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3836 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3837 SBI_SSCCTL_DISABLE,
3838 SBI_ICLK);
e615efe4
ED		 3839
3840 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3841 if (clock == 20000) {
e615efe4
ED		 3842 auxdiv = 1;
3843 divsel = 0x41;
3844 phaseinc = 0x20;
3845 } else {
3846 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3847 * but the adjusted_mode->crtc_clock in in KHz. To get the
3848 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3849 * convert the virtual clock precision to KHz here for higher
3850 * precision.
3851 */
3852 u32 iclk_virtual_root_freq = 172800 * 1000;
3853 u32 iclk_pi_range = 64;
3854 u32 desired_divisor, msb_divisor_value, pi_value;
3855
12d7ceed 3856 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3857 msb_divisor_value = desired_divisor / iclk_pi_range;
3858 pi_value = desired_divisor % iclk_pi_range;
3859
3860 auxdiv = 0;
3861 divsel = msb_divisor_value - 2;
3862 phaseinc = pi_value;
3863 }
3864
3865 /* This should not happen with any sane values */
3866 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3867 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3868 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3869 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3870
3871 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3872 clock,
e615efe4
ED		 3873 auxdiv,
3874 divsel,
3875 phasedir,
3876 phaseinc);
3877
3878 /* Program SSCDIVINTPHASE6 */
988d6ee8 3879 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3880 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3881 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3882 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3883 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3884 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3885 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3886 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3887
3888 /* Program SSCAUXDIV */
988d6ee8 3889 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3890 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3891 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3892 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3893
3894 /* Enable modulator and associated divider */
988d6ee8 3895 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3896 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3897 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3898
3899 /* Wait for initialization time */
3900 udelay(24);
3901
3902 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3903
3904 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3905}
3906
275f01b2
DV		 3907static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3908 enum pipe pch_transcoder)
3909{
3910 struct drm_device *dev = crtc->base.dev;
3911 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3912 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 3913
3914 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3915 I915_READ(HTOTAL(cpu_transcoder)));
3916 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3917 I915_READ(HBLANK(cpu_transcoder)));
3918 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3919 I915_READ(HSYNC(cpu_transcoder)));
3920
3921 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3922 I915_READ(VTOTAL(cpu_transcoder)));
3923 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3924 I915_READ(VBLANK(cpu_transcoder)));
3925 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3926 I915_READ(VSYNC(cpu_transcoder)));
3927 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3928 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3929}
3930
003632d9 3931static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 3932{
3933 struct drm_i915_private *dev_priv = dev->dev_private;
3934 uint32_t temp;
3935
3936 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 3937 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 3938 return;
3939
3940 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3941 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3942
003632d9
ACO		 3943 temp &= ~FDI_BC_BIFURCATION_SELECT;
3944 if (enable)
3945 temp |= FDI_BC_BIFURCATION_SELECT;
3946
3947 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 3948 I915_WRITE(SOUTH_CHICKEN1, temp);
3949 POSTING_READ(SOUTH_CHICKEN1);
3950}
3951
3952static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3953{
3954 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 3955
3956 switch (intel_crtc->pipe) {
3957 case PIPE_A:
3958 break;
3959 case PIPE_B:
6e3c9717 3960 if (intel_crtc->config->fdi_lanes > 2)
003632d9 3961 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 3962 else
003632d9 3963 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 3964
3965 break;
3966 case PIPE_C:
003632d9 3967 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 3968
3969 break;
3970 default:
3971 BUG();
3972 }
3973}
3974
f67a559d
JB		 3975/*
3976 * Enable PCH resources required for PCH ports:
3977 * - PCH PLLs
3978 * - FDI training & RX/TX
3979 * - update transcoder timings
3980 * - DP transcoding bits
3981 * - transcoder
3982 */
3983static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3984{
3985 struct drm_device *dev = crtc->dev;
3986 struct drm_i915_private *dev_priv = dev->dev_private;
3987 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3988 int pipe = intel_crtc->pipe;
ee7b9f93 3989 u32 reg, temp;
2c07245f 3990
ab9412ba 3991 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 3992
1fbc0d78
DV		 3993 if (IS_IVYBRIDGE(dev))
3994 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3995
cd986abb
DV		 3996 /* Write the TU size bits before fdi link training, so that error
3997 * detection works. */
3998 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3999 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4000
c98e9dcf 4001 /* For PCH output, training FDI link */
674cf967 4002 dev_priv->display.fdi_link_train(crtc);
2c07245f 4003
3ad8a208
DV		 4004 /* We need to program the right clock selection before writing the pixel
4005 * mutliplier into the DPLL. */
303b81e0 4006 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4007 u32 sel;
4b645f14 4008
c98e9dcf 4009 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4010 temp |= TRANS_DPLL_ENABLE(pipe);
4011 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4012 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4013 temp |= sel;
4014 else
4015 temp &= ~sel;
c98e9dcf 4016 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4017 }
5eddb70b 4018
3ad8a208
DV		 4019 /* XXX: pch pll's can be enabled any time before we enable the PCH
4020 * transcoder, and we actually should do this to not upset any PCH
4021 * transcoder that already use the clock when we share it.
4022 *
4023 * Note that enable_shared_dpll tries to do the right thing, but
4024 * get_shared_dpll unconditionally resets the pll - we need that to have
4025 * the right LVDS enable sequence. */
85b3894f 4026 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4027
d9b6cb56
JB		 4028 /* set transcoder timing, panel must allow it */
4029 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4030 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4031
303b81e0 4032 intel_fdi_normal_train(crtc);
5e84e1a4 4033
c98e9dcf 4034 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4035 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4036 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4037 reg = TRANS_DP_CTL(pipe);
4038 temp = I915_READ(reg);
4039 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4040 TRANS_DP_SYNC_MASK |
4041 TRANS_DP_BPC_MASK);
5eddb70b
CW		 4042 temp |= (TRANS_DP_OUTPUT_ENABLE |
4043 TRANS_DP_ENH_FRAMING);
9325c9f0 4044 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4045
4046 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4047 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4048 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4049 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4050
4051 switch (intel_trans_dp_port_sel(crtc)) {
4052 case PCH_DP_B:
5eddb70b 4053 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4054 break;
4055 case PCH_DP_C:
5eddb70b 4056 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4057 break;
4058 case PCH_DP_D:
5eddb70b 4059 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4060 break;
4061 default:
e95d41e1 4062 BUG();
32f9d658 4063 }
2c07245f 4064
5eddb70b 4065 I915_WRITE(reg, temp);
6be4a607 4066 }
b52eb4dc 4067
b8a4f404 4068 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4069}
4070
1507e5bd
PZ		 4071static void lpt_pch_enable(struct drm_crtc *crtc)
4072{
4073 struct drm_device *dev = crtc->dev;
4074 struct drm_i915_private *dev_priv = dev->dev_private;
4075 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4076 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4077
ab9412ba 4078 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4079
8c52b5e8 4080 lpt_program_iclkip(crtc);
1507e5bd 4081
0540e488 4082 /* Set transcoder timing. */
275f01b2 4083 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4084
937bb610 4085 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4086}
4087
716c2e55 4088void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 4089{
e2b78267 4090 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 4091
4092 if (pll == NULL)
4093 return;
4094
3e369b76 4095 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
1e6f2ddc 4096 WARN(1, "bad %s crtc mask\n", pll->name);
ee7b9f93
JB		 4097 return;
4098 }
4099
3e369b76
ACO		 4100 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4101 if (pll->config.crtc_mask == 0) {
f4a091c7
DV		 4102 WARN_ON(pll->on);
4103 WARN_ON(pll->active);
4104 }
4105
6e3c9717 4106 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 4107}
4108
190f68c5
ACO		 4109struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4110 struct intel_crtc_state *crtc_state)
ee7b9f93 4111{
e2b78267 4112 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4113 struct intel_shared_dpll *pll;
e2b78267 4114 enum intel_dpll_id i;
ee7b9f93 4115
98b6bd99
DV		 4116 if (HAS_PCH_IBX(dev_priv->dev)) {
4117 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4118 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4119 pll = &dev_priv->shared_dplls[i];
98b6bd99 4120
46edb027
DV		 4121 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4122 crtc->base.base.id, pll->name);
98b6bd99 4123
8bd31e67 4124 WARN_ON(pll->new_config->crtc_mask);
f2a69f44 4125
98b6bd99
DV		 4126 goto found;
4127 }
4128
e72f9fbf
DV		 4129 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4130 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4131
4132 /* Only want to check enabled timings first */
8bd31e67 4133 if (pll->new_config->crtc_mask == 0)
ee7b9f93
JB		 4134 continue;
4135
190f68c5 4136 if (memcmp(&crtc_state->dpll_hw_state,
8bd31e67
ACO		 4137 &pll->new_config->hw_state,
4138 sizeof(pll->new_config->hw_state)) == 0) {
4139 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4140 crtc->base.base.id, pll->name,
8bd31e67
ACO		 4141 pll->new_config->crtc_mask,
4142 pll->active);
ee7b9f93
JB		 4143 goto found;
4144 }
4145 }
4146
4147 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4148 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4149 pll = &dev_priv->shared_dplls[i];
8bd31e67 4150 if (pll->new_config->crtc_mask == 0) {
46edb027
DV		 4151 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4152 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4153 goto found;
4154 }
4155 }
4156
4157 return NULL;
4158
4159found:
8bd31e67 4160 if (pll->new_config->crtc_mask == 0)
190f68c5 4161 pll->new_config->hw_state = crtc_state->dpll_hw_state;
f2a69f44 4162
190f68c5 4163 crtc_state->shared_dpll = i;
46edb027
DV		 4164 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4165 pipe_name(crtc->pipe));
ee7b9f93 4166
8bd31e67 4167 pll->new_config->crtc_mask |= 1 << crtc->pipe;
e04c7350 4168
ee7b9f93
JB		 4169 return pll;
4170}
4171
8bd31e67
ACO		 4172/**
4173 * intel_shared_dpll_start_config - start a new PLL staged config
4174 * @dev_priv: DRM device
4175 * @clear_pipes: mask of pipes that will have their PLLs freed
4176 *
4177 * Starts a new PLL staged config, copying the current config but
4178 * releasing the references of pipes specified in clear_pipes.
4179 */
4180static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4181 unsigned clear_pipes)
4182{
4183 struct intel_shared_dpll *pll;
4184 enum intel_dpll_id i;
4185
4186 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4187 pll = &dev_priv->shared_dplls[i];
4188
4189 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4190 GFP_KERNEL);
4191 if (!pll->new_config)
4192 goto cleanup;
4193
4194 pll->new_config->crtc_mask &= ~clear_pipes;
4195 }
4196
4197 return 0;
4198
4199cleanup:
4200 while (--i >= 0) {
4201 pll = &dev_priv->shared_dplls[i];
f354d733 4202 kfree(pll->new_config);
8bd31e67
ACO		 4203 pll->new_config = NULL;
4204 }
4205
4206 return -ENOMEM;
4207}
4208
4209static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4210{
4211 struct intel_shared_dpll *pll;
4212 enum intel_dpll_id i;
4213
4214 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4215 pll = &dev_priv->shared_dplls[i];
4216
4217 WARN_ON(pll->new_config == &pll->config);
4218
4219 pll->config = *pll->new_config;
4220 kfree(pll->new_config);
4221 pll->new_config = NULL;
4222 }
4223}
4224
4225static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4226{
4227 struct intel_shared_dpll *pll;
4228 enum intel_dpll_id i;
4229
4230 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4231 pll = &dev_priv->shared_dplls[i];
4232
4233 WARN_ON(pll->new_config == &pll->config);
4234
4235 kfree(pll->new_config);
4236 pll->new_config = NULL;
4237 }
4238}
4239
a1520318 4240static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4241{
4242 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4243 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4244 u32 temp;
4245
4246 temp = I915_READ(dslreg);
4247 udelay(500);
4248 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4249 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4250 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4251 }
4252}
4253
bd2e244f
JB		 4254static void skylake_pfit_enable(struct intel_crtc *crtc)
4255{
4256 struct drm_device *dev = crtc->base.dev;
4257 struct drm_i915_private *dev_priv = dev->dev_private;
4258 int pipe = crtc->pipe;
4259
6e3c9717 4260 if (crtc->config->pch_pfit.enabled) {
bd2e244f 4261 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
6e3c9717
ACO		 4262 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4263 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
bd2e244f
JB		 4264 }
4265}
4266
b074cec8
JB		 4267static void ironlake_pfit_enable(struct intel_crtc *crtc)
4268{
4269 struct drm_device *dev = crtc->base.dev;
4270 struct drm_i915_private *dev_priv = dev->dev_private;
4271 int pipe = crtc->pipe;
4272
6e3c9717 4273 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4274 /* Force use of hard-coded filter coefficients
4275 * as some pre-programmed values are broken,
4276 * e.g. x201.
4277 */
4278 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4279 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4280 PF_PIPE_SEL_IVB(pipe));
4281 else
4282 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4283 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4284 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4285 }
4286}
4287
4a3b8769 4288static void intel_enable_sprite_planes(struct drm_crtc *crtc)
bb53d4ae
VS		 4289{
4290 struct drm_device *dev = crtc->dev;
4291 enum pipe pipe = to_intel_crtc(crtc)->pipe;
af2b653b 4292 struct drm_plane *plane;
bb53d4ae
VS		 4293 struct intel_plane *intel_plane;
4294
af2b653b
MR		 4295 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4296 intel_plane = to_intel_plane(plane);
bb53d4ae
VS		 4297 if (intel_plane->pipe == pipe)
4298 intel_plane_restore(&intel_plane->base);
af2b653b 4299 }
bb53d4ae
VS		 4300}
4301
0d703d4e
MR		 4302/*
4303 * Disable a plane internally without actually modifying the plane's state.
4304 * This will allow us to easily restore the plane later by just reprogramming
4305 * its state.
4306 */
4307static void disable_plane_internal(struct drm_plane *plane)
4308{
4309 struct intel_plane *intel_plane = to_intel_plane(plane);
4310 struct drm_plane_state *state =
4311 plane->funcs->atomic_duplicate_state(plane);
4312 struct intel_plane_state *intel_state = to_intel_plane_state(state);
4313
4314 intel_state->visible = false;
4315 intel_plane->commit_plane(plane, intel_state);
4316
4317 intel_plane_destroy_state(plane, state);
4318}
4319
4a3b8769 4320static void intel_disable_sprite_planes(struct drm_crtc *crtc)
bb53d4ae
VS		 4321{
4322 struct drm_device *dev = crtc->dev;
4323 enum pipe pipe = to_intel_crtc(crtc)->pipe;
af2b653b 4324 struct drm_plane *plane;
bb53d4ae
VS		 4325 struct intel_plane *intel_plane;
4326
af2b653b
MR		 4327 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4328 intel_plane = to_intel_plane(plane);
0d703d4e
MR		 4329 if (plane->fb && intel_plane->pipe == pipe)
4330 disable_plane_internal(plane);
af2b653b 4331 }
bb53d4ae
VS		 4332}
4333
20bc8673 4334void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4335{
cea165c3
VS		 4336 struct drm_device *dev = crtc->base.dev;
4337 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4338
6e3c9717 4339 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4340 return;
4341
cea165c3
VS		 4342 /* We can only enable IPS after we enable a plane and wait for a vblank */
4343 intel_wait_for_vblank(dev, crtc->pipe);
4344
d77e4531 4345 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4346 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4347 mutex_lock(&dev_priv->rps.hw_lock);
4348 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4349 mutex_unlock(&dev_priv->rps.hw_lock);
4350 /* Quoting Art Runyan: "its not safe to expect any particular
4351 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4352 * mailbox." Moreover, the mailbox may return a bogus state,
4353 * so we need to just enable it and continue on.
2a114cc1
BW		 4354 */
4355 } else {
4356 I915_WRITE(IPS_CTL, IPS_ENABLE);
4357 /* The bit only becomes 1 in the next vblank, so this wait here
4358 * is essentially intel_wait_for_vblank. If we don't have this
4359 * and don't wait for vblanks until the end of crtc_enable, then
4360 * the HW state readout code will complain that the expected
4361 * IPS_CTL value is not the one we read. */
4362 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4363 DRM_ERROR("Timed out waiting for IPS enable\n");
4364 }
d77e4531
PZ		 4365}
4366
20bc8673 4367void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4368{
4369 struct drm_device *dev = crtc->base.dev;
4370 struct drm_i915_private *dev_priv = dev->dev_private;
4371
6e3c9717 4372 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4373 return;
4374
4375 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4376 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4377 mutex_lock(&dev_priv->rps.hw_lock);
4378 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4379 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4380 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4381 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4382 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4383 } else {
2a114cc1 4384 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4385 POSTING_READ(IPS_CTL);
4386 }
d77e4531
PZ		 4387
4388 /* We need to wait for a vblank before we can disable the plane. */
4389 intel_wait_for_vblank(dev, crtc->pipe);
4390}
4391
4392/** Loads the palette/gamma unit for the CRTC with the prepared values */
4393static void intel_crtc_load_lut(struct drm_crtc *crtc)
4394{
4395 struct drm_device *dev = crtc->dev;
4396 struct drm_i915_private *dev_priv = dev->dev_private;
4397 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4398 enum pipe pipe = intel_crtc->pipe;
4399 int palreg = PALETTE(pipe);
4400 int i;
4401 bool reenable_ips = false;
4402
4403 /* The clocks have to be on to load the palette. */
83d65738 4404 if (!crtc->state->enable || !intel_crtc->active)
d77e4531
PZ		 4405 return;
4406
4407 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
409ee761 4408 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4409 assert_dsi_pll_enabled(dev_priv);
4410 else
4411 assert_pll_enabled(dev_priv, pipe);
4412 }
4413
4414 /* use legacy palette for Ironlake */
7a1db49a 4415 if (!HAS_GMCH_DISPLAY(dev))
d77e4531
PZ		 4416 palreg = LGC_PALETTE(pipe);
4417
4418 /* Workaround : Do not read or write the pipe palette/gamma data while
4419 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4420 */
6e3c9717 4421 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4422 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4423 GAMMA_MODE_MODE_SPLIT)) {
4424 hsw_disable_ips(intel_crtc);
4425 reenable_ips = true;
4426 }
4427
4428 for (i = 0; i < 256; i++) {
4429 I915_WRITE(palreg + 4 * i,
4430 (intel_crtc->lut_r[i] << 16) |
4431 (intel_crtc->lut_g[i] << 8) |
4432 intel_crtc->lut_b[i]);
4433 }
4434
4435 if (reenable_ips)
4436 hsw_enable_ips(intel_crtc);
4437}
4438
d3eedb1a
VS		 4439static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4440{
4441 if (!enable && intel_crtc->overlay) {
4442 struct drm_device *dev = intel_crtc->base.dev;
4443 struct drm_i915_private *dev_priv = dev->dev_private;
4444
4445 mutex_lock(&dev->struct_mutex);
4446 dev_priv->mm.interruptible = false;
4447 (void) intel_overlay_switch_off(intel_crtc->overlay);
4448 dev_priv->mm.interruptible = true;
4449 mutex_unlock(&dev->struct_mutex);
4450 }
4451
4452 /* Let userspace switch the overlay on again. In most cases userspace
4453 * has to recompute where to put it anyway.
4454 */
4455}
4456
d3eedb1a 4457static void intel_crtc_enable_planes(struct drm_crtc *crtc)
a5c4d7bc
VS		 4458{
4459 struct drm_device *dev = crtc->dev;
a5c4d7bc
VS		 4460 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4461 int pipe = intel_crtc->pipe;
a5c4d7bc 4462
fdd508a6 4463 intel_enable_primary_hw_plane(crtc->primary, crtc);
4a3b8769 4464 intel_enable_sprite_planes(crtc);
a5c4d7bc 4465 intel_crtc_update_cursor(crtc, true);
d3eedb1a 4466 intel_crtc_dpms_overlay(intel_crtc, true);
a5c4d7bc
VS		 4467
4468 hsw_enable_ips(intel_crtc);
4469
4470 mutex_lock(&dev->struct_mutex);
7ff0ebcc 4471 intel_fbc_update(dev);
a5c4d7bc 4472 mutex_unlock(&dev->struct_mutex);
f99d7069
DV		 4473
4474 /*
4475 * FIXME: Once we grow proper nuclear flip support out of this we need
4476 * to compute the mask of flip planes precisely. For the time being
4477 * consider this a flip from a NULL plane.
4478 */
4479 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4480}
4481
d3eedb1a 4482static void intel_crtc_disable_planes(struct drm_crtc *crtc)
a5c4d7bc
VS		 4483{
4484 struct drm_device *dev = crtc->dev;
4485 struct drm_i915_private *dev_priv = dev->dev_private;
4486 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4487 int pipe = intel_crtc->pipe;
a5c4d7bc
VS		 4488
4489 intel_crtc_wait_for_pending_flips(crtc);
a5c4d7bc 4490
e35fef21 4491 if (dev_priv->fbc.crtc == intel_crtc)
7ff0ebcc 4492 intel_fbc_disable(dev);
a5c4d7bc
VS		 4493
4494 hsw_disable_ips(intel_crtc);
4495
d3eedb1a 4496 intel_crtc_dpms_overlay(intel_crtc, false);
a5c4d7bc 4497 intel_crtc_update_cursor(crtc, false);
4a3b8769 4498 intel_disable_sprite_planes(crtc);
fdd508a6 4499 intel_disable_primary_hw_plane(crtc->primary, crtc);
f98551ae 4500
f99d7069
DV		 4501 /*
4502 * FIXME: Once we grow proper nuclear flip support out of this we need
4503 * to compute the mask of flip planes precisely. For the time being
4504 * consider this a flip to a NULL plane.
4505 */
4506 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4507}
4508
f67a559d
JB		 4509static void ironlake_crtc_enable(struct drm_crtc *crtc)
4510{
4511 struct drm_device *dev = crtc->dev;
4512 struct drm_i915_private *dev_priv = dev->dev_private;
4513 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4514 struct intel_encoder *encoder;
f67a559d 4515 int pipe = intel_crtc->pipe;
f67a559d 4516
83d65738 4517 WARN_ON(!crtc->state->enable);
08a48469 4518
f67a559d
JB		 4519 if (intel_crtc->active)
4520 return;
4521
6e3c9717 4522 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4523 intel_prepare_shared_dpll(intel_crtc);
4524
6e3c9717 4525 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4526 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4527
4528 intel_set_pipe_timings(intel_crtc);
4529
6e3c9717 4530 if (intel_crtc->config->has_pch_encoder) {
29407aab 4531 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4532 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4533 }
4534
4535 ironlake_set_pipeconf(crtc);
4536
f67a559d 4537 intel_crtc->active = true;
8664281b 4538
a72e4c9f
DV		 4539 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4540 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4541
f6736a1a 4542 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4543 if (encoder->pre_enable)
4544 encoder->pre_enable(encoder);
f67a559d 4545
6e3c9717 4546 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4547 /* Note: FDI PLL enabling _must_ be done before we enable the
4548 * cpu pipes, hence this is separate from all the other fdi/pch
4549 * enabling. */
88cefb6c 4550 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4551 } else {
4552 assert_fdi_tx_disabled(dev_priv, pipe);
4553 assert_fdi_rx_disabled(dev_priv, pipe);
4554 }
f67a559d 4555
b074cec8 4556 ironlake_pfit_enable(intel_crtc);
f67a559d 4557
9c54c0dd
JB		 4558 /*
4559 * On ILK+ LUT must be loaded before the pipe is running but with
4560 * clocks enabled
4561 */
4562 intel_crtc_load_lut(crtc);
4563
f37fcc2a 4564 intel_update_watermarks(crtc);
e1fdc473 4565 intel_enable_pipe(intel_crtc);
f67a559d 4566
6e3c9717 4567 if (intel_crtc->config->has_pch_encoder)
f67a559d 4568 ironlake_pch_enable(crtc);
c98e9dcf 4569
f9b61ff6
DV		 4570 assert_vblank_disabled(crtc);
4571 drm_crtc_vblank_on(crtc);
4572
fa5c73b1
DV		 4573 for_each_encoder_on_crtc(dev, crtc, encoder)
4574 encoder->enable(encoder);
61b77ddd
DV		 4575
4576 if (HAS_PCH_CPT(dev))
a1520318 4577 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100 4578
d3eedb1a 4579 intel_crtc_enable_planes(crtc);
6be4a607
JB		 4580}
4581
42db64ef
PZ		 4582/* IPS only exists on ULT machines and is tied to pipe A. */
4583static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4584{
f5adf94e 4585 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4586}
4587
e4916946
PZ		 4588/*
4589 * This implements the workaround described in the "notes" section of the mode
4590 * set sequence documentation. When going from no pipes or single pipe to
4591 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4592 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4593 */
4594static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4595{
4596 struct drm_device *dev = crtc->base.dev;
4597 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4598
4599 /* We want to get the other_active_crtc only if there's only 1 other
4600 * active crtc. */
d3fcc808 4601 for_each_intel_crtc(dev, crtc_it) {
e4916946
PZ		 4602 if (!crtc_it->active || crtc_it == crtc)
4603 continue;
4604
4605 if (other_active_crtc)
4606 return;
4607
4608 other_active_crtc = crtc_it;
4609 }
4610 if (!other_active_crtc)
4611 return;
4612
4613 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4614 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4615}
4616
4f771f10
PZ		 4617static void haswell_crtc_enable(struct drm_crtc *crtc)
4618{
4619 struct drm_device *dev = crtc->dev;
4620 struct drm_i915_private *dev_priv = dev->dev_private;
4621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4622 struct intel_encoder *encoder;
4623 int pipe = intel_crtc->pipe;
4f771f10 4624
83d65738 4625 WARN_ON(!crtc->state->enable);
4f771f10
PZ		 4626
4627 if (intel_crtc->active)
4628 return;
4629
df8ad70c
DV		 4630 if (intel_crtc_to_shared_dpll(intel_crtc))
4631 intel_enable_shared_dpll(intel_crtc);
4632
6e3c9717 4633 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4634 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 4635
4636 intel_set_pipe_timings(intel_crtc);
4637
6e3c9717
ACO		 4638 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4639 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4640 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 4641 }
4642
6e3c9717 4643 if (intel_crtc->config->has_pch_encoder) {
229fca97 4644 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4645 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 4646 }
4647
4648 haswell_set_pipeconf(crtc);
4649
4650 intel_set_pipe_csc(crtc);
4651
4f771f10 4652 intel_crtc->active = true;
8664281b 4653
a72e4c9f 4654 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ		 4655 for_each_encoder_on_crtc(dev, crtc, encoder)
4656 if (encoder->pre_enable)
4657 encoder->pre_enable(encoder);
4658
6e3c9717 4659 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 4660 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4661 true);
4fe9467d
ID		 4662 dev_priv->display.fdi_link_train(crtc);
4663 }
4664
1f544388 4665 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 4666
bd2e244f
JB		 4667 if (IS_SKYLAKE(dev))
4668 skylake_pfit_enable(intel_crtc);
4669 else
4670 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 4671
4672 /*
4673 * On ILK+ LUT must be loaded before the pipe is running but with
4674 * clocks enabled
4675 */
4676 intel_crtc_load_lut(crtc);
4677
1f544388 4678 intel_ddi_set_pipe_settings(crtc);
8228c251 4679 intel_ddi_enable_transcoder_func(crtc);
4f771f10 4680
f37fcc2a 4681 intel_update_watermarks(crtc);
e1fdc473 4682 intel_enable_pipe(intel_crtc);
42db64ef 4683
6e3c9717 4684 if (intel_crtc->config->has_pch_encoder)
1507e5bd 4685 lpt_pch_enable(crtc);
4f771f10 4686
6e3c9717 4687 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA		 4688 intel_ddi_set_vc_payload_alloc(crtc, true);
4689
f9b61ff6
DV		 4690 assert_vblank_disabled(crtc);
4691 drm_crtc_vblank_on(crtc);
4692
8807e55b 4693 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 4694 encoder->enable(encoder);
8807e55b
JN		 4695 intel_opregion_notify_encoder(encoder, true);
4696 }
4f771f10 4697
e4916946
PZ		 4698 /* If we change the relative order between pipe/planes enabling, we need
4699 * to change the workaround. */
4700 haswell_mode_set_planes_workaround(intel_crtc);
d3eedb1a 4701 intel_crtc_enable_planes(crtc);
4f771f10
PZ		 4702}
4703
bd2e244f
JB		 4704static void skylake_pfit_disable(struct intel_crtc *crtc)
4705{
4706 struct drm_device *dev = crtc->base.dev;
4707 struct drm_i915_private *dev_priv = dev->dev_private;
4708 int pipe = crtc->pipe;
4709
4710 /* To avoid upsetting the power well on haswell only disable the pfit if
4711 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 4712 if (crtc->config->pch_pfit.enabled) {
bd2e244f
JB		 4713 I915_WRITE(PS_CTL(pipe), 0);
4714 I915_WRITE(PS_WIN_POS(pipe), 0);
4715 I915_WRITE(PS_WIN_SZ(pipe), 0);
4716 }
4717}
4718
3f8dce3a
DV		 4719static void ironlake_pfit_disable(struct intel_crtc *crtc)
4720{
4721 struct drm_device *dev = crtc->base.dev;
4722 struct drm_i915_private *dev_priv = dev->dev_private;
4723 int pipe = crtc->pipe;
4724
4725 /* To avoid upsetting the power well on haswell only disable the pfit if
4726 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 4727 if (crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 4728 I915_WRITE(PF_CTL(pipe), 0);
4729 I915_WRITE(PF_WIN_POS(pipe), 0);
4730 I915_WRITE(PF_WIN_SZ(pipe), 0);
4731 }
4732}
4733
6be4a607
JB		 4734static void ironlake_crtc_disable(struct drm_crtc *crtc)
4735{
4736 struct drm_device *dev = crtc->dev;
4737 struct drm_i915_private *dev_priv = dev->dev_private;
4738 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4739 struct intel_encoder *encoder;
6be4a607 4740 int pipe = intel_crtc->pipe;
5eddb70b 4741 u32 reg, temp;
b52eb4dc 4742
f7abfe8b
CW		 4743 if (!intel_crtc->active)
4744 return;
4745
d3eedb1a 4746 intel_crtc_disable_planes(crtc);
a5c4d7bc 4747
ea9d758d
DV		 4748 for_each_encoder_on_crtc(dev, crtc, encoder)
4749 encoder->disable(encoder);
4750
f9b61ff6
DV		 4751 drm_crtc_vblank_off(crtc);
4752 assert_vblank_disabled(crtc);
4753
6e3c9717 4754 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 4755 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 4756
575f7ab7 4757 intel_disable_pipe(intel_crtc);
32f9d658 4758
3f8dce3a 4759 ironlake_pfit_disable(intel_crtc);
2c07245f 4760
bf49ec8c
DV		 4761 for_each_encoder_on_crtc(dev, crtc, encoder)
4762 if (encoder->post_disable)
4763 encoder->post_disable(encoder);
2c07245f 4764
6e3c9717 4765 if (intel_crtc->config->has_pch_encoder) {
d925c59a 4766 ironlake_fdi_disable(crtc);
913d8d11 4767
d925c59a 4768 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 4769
d925c59a
DV		 4770 if (HAS_PCH_CPT(dev)) {
4771 /* disable TRANS_DP_CTL */
4772 reg = TRANS_DP_CTL(pipe);
4773 temp = I915_READ(reg);
4774 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4775 TRANS_DP_PORT_SEL_MASK);
4776 temp |= TRANS_DP_PORT_SEL_NONE;
4777 I915_WRITE(reg, temp);
4778
4779 /* disable DPLL_SEL */
4780 temp = I915_READ(PCH_DPLL_SEL);
11887397 4781 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 4782 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 4783 }
e3421a18 4784
d925c59a 4785 /* disable PCH DPLL */
e72f9fbf 4786 intel_disable_shared_dpll(intel_crtc);
8db9d77b 4787
d925c59a
DV		 4788 ironlake_fdi_pll_disable(intel_crtc);
4789 }
6b383a7f 4790
f7abfe8b 4791 intel_crtc->active = false;
46ba614c 4792 intel_update_watermarks(crtc);
d1ebd816
BW		 4793
4794 mutex_lock(&dev->struct_mutex);
7ff0ebcc 4795 intel_fbc_update(dev);
d1ebd816 4796 mutex_unlock(&dev->struct_mutex);
6be4a607 4797}
1b3c7a47 4798
4f771f10 4799static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 4800{
4f771f10
PZ		 4801 struct drm_device *dev = crtc->dev;
4802 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 4803 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 4804 struct intel_encoder *encoder;
6e3c9717 4805 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 4806
4f771f10
PZ		 4807 if (!intel_crtc->active)
4808 return;
4809
d3eedb1a 4810 intel_crtc_disable_planes(crtc);
dda9a66a 4811
8807e55b
JN		 4812 for_each_encoder_on_crtc(dev, crtc, encoder) {
4813 intel_opregion_notify_encoder(encoder, false);
4f771f10 4814 encoder->disable(encoder);
8807e55b 4815 }
4f771f10 4816
f9b61ff6
DV		 4817 drm_crtc_vblank_off(crtc);
4818 assert_vblank_disabled(crtc);
4819
6e3c9717 4820 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 4821 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4822 false);
575f7ab7 4823 intel_disable_pipe(intel_crtc);
4f771f10 4824
6e3c9717 4825 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 4826 intel_ddi_set_vc_payload_alloc(crtc, false);
4827
ad80a810 4828 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 4829
bd2e244f
JB		 4830 if (IS_SKYLAKE(dev))
4831 skylake_pfit_disable(intel_crtc);
4832 else
4833 ironlake_pfit_disable(intel_crtc);
4f771f10 4834
1f544388 4835 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 4836
6e3c9717 4837 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 4838 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 4839 intel_ddi_fdi_disable(crtc);
83616634 4840 }
4f771f10 4841
97b040aa
ID		 4842 for_each_encoder_on_crtc(dev, crtc, encoder)
4843 if (encoder->post_disable)
4844 encoder->post_disable(encoder);
4845
4f771f10 4846 intel_crtc->active = false;
46ba614c 4847 intel_update_watermarks(crtc);
4f771f10
PZ		 4848
4849 mutex_lock(&dev->struct_mutex);
7ff0ebcc 4850 intel_fbc_update(dev);
4f771f10 4851 mutex_unlock(&dev->struct_mutex);
df8ad70c
DV		 4852
4853 if (intel_crtc_to_shared_dpll(intel_crtc))
4854 intel_disable_shared_dpll(intel_crtc);
4f771f10
PZ		 4855}
4856
ee7b9f93
JB		 4857static void ironlake_crtc_off(struct drm_crtc *crtc)
4858{
4859 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 4860 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 4861}
4862
6441ab5f 4863
2dd24552
JB		 4864static void i9xx_pfit_enable(struct intel_crtc *crtc)
4865{
4866 struct drm_device *dev = crtc->base.dev;
4867 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 4868 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 4869
681a8504 4870 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 4871 return;
4872
2dd24552 4873 /*
c0b03411
DV		 4874 * The panel fitter should only be adjusted whilst the pipe is disabled,
4875 * according to register description and PRM.
2dd24552 4876 */
c0b03411
DV		 4877 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4878 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 4879
b074cec8
JB		 4880 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4881 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 4882
4883 /* Border color in case we don't scale up to the full screen. Black by
4884 * default, change to something else for debugging. */
4885 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 4886}
4887
d05410f9
DA		 4888static enum intel_display_power_domain port_to_power_domain(enum port port)
4889{
4890 switch (port) {
4891 case PORT_A:
4892 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4893 case PORT_B:
4894 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4895 case PORT_C:
4896 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4897 case PORT_D:
4898 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4899 default:
4900 WARN_ON_ONCE(1);
4901 return POWER_DOMAIN_PORT_OTHER;
4902 }
4903}
4904
77d22dca
ID		 4905#define for_each_power_domain(domain, mask) \
4906 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4907 if ((1 << (domain)) & (mask))
4908
319be8ae
ID		 4909enum intel_display_power_domain
4910intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4911{
4912 struct drm_device *dev = intel_encoder->base.dev;
4913 struct intel_digital_port *intel_dig_port;
4914
4915 switch (intel_encoder->type) {
4916 case INTEL_OUTPUT_UNKNOWN:
4917 /* Only DDI platforms should ever use this output type */
4918 WARN_ON_ONCE(!HAS_DDI(dev));
4919 case INTEL_OUTPUT_DISPLAYPORT:
4920 case INTEL_OUTPUT_HDMI:
4921 case INTEL_OUTPUT_EDP:
4922 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 4923 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 4924 case INTEL_OUTPUT_DP_MST:
4925 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4926 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 4927 case INTEL_OUTPUT_ANALOG:
4928 return POWER_DOMAIN_PORT_CRT;
4929 case INTEL_OUTPUT_DSI:
4930 return POWER_DOMAIN_PORT_DSI;
4931 default:
4932 return POWER_DOMAIN_PORT_OTHER;
4933 }
4934}
4935
4936static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 4937{
319be8ae
ID		 4938 struct drm_device *dev = crtc->dev;
4939 struct intel_encoder *intel_encoder;
4940 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4941 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 4942 unsigned long mask;
4943 enum transcoder transcoder;
4944
4945 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4946
4947 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4948 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 4949 if (intel_crtc->config->pch_pfit.enabled ||
4950 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 4951 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4952
319be8ae
ID		 4953 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4954 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4955
77d22dca
ID		 4956 return mask;
4957}
4958
679dacd4 4959static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
77d22dca 4960{
679dacd4 4961 struct drm_device *dev = state->dev;
77d22dca
ID		 4962 struct drm_i915_private *dev_priv = dev->dev_private;
4963 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4964 struct intel_crtc *crtc;
4965
4966 /*
4967 * First get all needed power domains, then put all unneeded, to avoid
4968 * any unnecessary toggling of the power wells.
4969 */
d3fcc808 4970 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 4971 enum intel_display_power_domain domain;
4972
83d65738 4973 if (!crtc->base.state->enable)
77d22dca
ID		 4974 continue;
4975
319be8ae 4976 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
77d22dca
ID		 4977
4978 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4979 intel_display_power_get(dev_priv, domain);
4980 }
4981
50f6e502 4982 if (dev_priv->display.modeset_global_resources)
679dacd4 4983 dev_priv->display.modeset_global_resources(state);
50f6e502 4984
d3fcc808 4985 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 4986 enum intel_display_power_domain domain;
4987
4988 for_each_power_domain(domain, crtc->enabled_power_domains)
4989 intel_display_power_put(dev_priv, domain);
4990
4991 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4992 }
4993
4994 intel_display_set_init_power(dev_priv, false);
4995}
4996
dfcab17e 4997/* returns HPLL frequency in kHz */
f8bf63fd 4998static int valleyview_get_vco(struct drm_i915_private *dev_priv)
30a970c6 4999{
586f49dc 5000 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
30a970c6 5001
586f49dc
JB		 5002 /* Obtain SKU information */
5003 mutex_lock(&dev_priv->dpio_lock);
5004 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5005 CCK_FUSE_HPLL_FREQ_MASK;
5006 mutex_unlock(&dev_priv->dpio_lock);
30a970c6 5007
dfcab17e 5008 return vco_freq[hpll_freq] * 1000;
30a970c6
JB		 5009}
5010
f8bf63fd
VS		 5011static void vlv_update_cdclk(struct drm_device *dev)
5012{
5013 struct drm_i915_private *dev_priv = dev->dev_private;
5014
5015 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
43dc52c3 5016 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
f8bf63fd
VS		 5017 dev_priv->vlv_cdclk_freq);
5018
5019 /*
5020 * Program the gmbus_freq based on the cdclk frequency.
5021 * BSpec erroneously claims we should aim for 4MHz, but
5022 * in fact 1MHz is the correct frequency.
5023 */
6be1e3d3 5024 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
f8bf63fd
VS		 5025}
5026
30a970c6
JB		 5027/* Adjust CDclk dividers to allow high res or save power if possible */
5028static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5029{
5030 struct drm_i915_private *dev_priv = dev->dev_private;
5031 u32 val, cmd;
5032
d197b7d3 5033 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
d60c4473 5034
dfcab17e 5035 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5036 cmd = 2;
dfcab17e 5037 else if (cdclk == 266667)
30a970c6
JB		 5038 cmd = 1;
5039 else
5040 cmd = 0;
5041
5042 mutex_lock(&dev_priv->rps.hw_lock);
5043 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5044 val &= ~DSPFREQGUAR_MASK;
5045 val |= (cmd << DSPFREQGUAR_SHIFT);
5046 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5047 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5048 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5049 50)) {
5050 DRM_ERROR("timed out waiting for CDclk change\n");
5051 }
5052 mutex_unlock(&dev_priv->rps.hw_lock);
5053
dfcab17e 5054 if (cdclk == 400000) {
6bcda4f0 5055 u32 divider;
30a970c6 5056
6bcda4f0 5057 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6
JB		 5058
5059 mutex_lock(&dev_priv->dpio_lock);
5060 /* adjust cdclk divider */
5061 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
9cf33db5 5062 val &= ~DISPLAY_FREQUENCY_VALUES;
30a970c6
JB		 5063 val |= divider;
5064 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5065
5066 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5067 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5068 50))
5069 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5070 mutex_unlock(&dev_priv->dpio_lock);
5071 }
5072
5073 mutex_lock(&dev_priv->dpio_lock);
5074 /* adjust self-refresh exit latency value */
5075 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5076 val &= ~0x7f;
5077
5078 /*
5079 * For high bandwidth configs, we set a higher latency in the bunit
5080 * so that the core display fetch happens in time to avoid underruns.
5081 */
dfcab17e 5082 if (cdclk == 400000)
30a970c6
JB		 5083 val |= 4500 / 250; /* 4.5 usec */
5084 else
5085 val |= 3000 / 250; /* 3.0 usec */
5086 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5087 mutex_unlock(&dev_priv->dpio_lock);
5088
f8bf63fd 5089 vlv_update_cdclk(dev);
30a970c6
JB		 5090}
5091
383c5a6a
VS		 5092static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5093{
5094 struct drm_i915_private *dev_priv = dev->dev_private;
5095 u32 val, cmd;
5096
5097 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
5098
5099 switch (cdclk) {
383c5a6a
VS		 5100 case 333333:
5101 case 320000:
383c5a6a 5102 case 266667:
383c5a6a 5103 case 200000:
383c5a6a
VS		 5104 break;
5105 default:
5f77eeb0 5106 MISSING_CASE(cdclk);
383c5a6a
VS		 5107 return;
5108 }
5109
9d0d3fda
VS		 5110 /*
5111 * Specs are full of misinformation, but testing on actual
5112 * hardware has shown that we just need to write the desired
5113 * CCK divider into the Punit register.
5114 */
5115 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5116
383c5a6a
VS		 5117 mutex_lock(&dev_priv->rps.hw_lock);
5118 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5119 val &= ~DSPFREQGUAR_MASK_CHV;
5120 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5121 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5122 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5123 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5124 50)) {
5125 DRM_ERROR("timed out waiting for CDclk change\n");
5126 }
5127 mutex_unlock(&dev_priv->rps.hw_lock);
5128
5129 vlv_update_cdclk(dev);
5130}
5131
30a970c6
JB		 5132static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5133 int max_pixclk)
5134{
6bcda4f0 5135 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5136 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5137
30a970c6
JB		 5138 /*
5139 * Really only a few cases to deal with, as only 4 CDclks are supported:
5140 * 200MHz
5141 * 267MHz
29dc7ef3 5142 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5143 * 400MHz (VLV only)
5144 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5145 * of the lower bin and adjust if needed.
e37c67a1
VS		 5146 *
5147 * We seem to get an unstable or solid color picture at 200MHz.
5148 * Not sure what's wrong. For now use 200MHz only when all pipes
5149 * are off.
30a970c6 5150 */
6cca3195
VS		 5151 if (!IS_CHERRYVIEW(dev_priv) &&
5152 max_pixclk > freq_320*limit/100)
dfcab17e 5153 return 400000;
6cca3195 5154 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5155 return freq_320;
e37c67a1 5156 else if (max_pixclk > 0)
dfcab17e 5157 return 266667;
e37c67a1
VS		 5158 else
5159 return 200000;
30a970c6
JB		 5160}
5161
2f2d7aa1
VS		 5162/* compute the max pixel clock for new configuration */
5163static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
30a970c6
JB		 5164{
5165 struct drm_device *dev = dev_priv->dev;
5166 struct intel_crtc *intel_crtc;
5167 int max_pixclk = 0;
5168
d3fcc808 5169 for_each_intel_crtc(dev, intel_crtc) {
2f2d7aa1 5170 if (intel_crtc->new_enabled)
30a970c6 5171 max_pixclk = max(max_pixclk,
2d112de7 5172 intel_crtc->new_config->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5173 }
5174
5175 return max_pixclk;
5176}
5177
5178static void valleyview_modeset_global_pipes(struct drm_device *dev,
2f2d7aa1 5179 unsigned *prepare_pipes)
30a970c6
JB		 5180{
5181 struct drm_i915_private *dev_priv = dev->dev_private;
5182 struct intel_crtc *intel_crtc;
2f2d7aa1 5183 int max_pixclk = intel_mode_max_pixclk(dev_priv);
30a970c6 5184
d60c4473
ID		 5185 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
5186 dev_priv->vlv_cdclk_freq)
30a970c6
JB		 5187 return;
5188
2f2d7aa1 5189 /* disable/enable all currently active pipes while we change cdclk */
d3fcc808 5190 for_each_intel_crtc(dev, intel_crtc)
83d65738 5191 if (intel_crtc->base.state->enable)
30a970c6
JB		 5192 *prepare_pipes |= (1 << intel_crtc->pipe);
5193}
5194
1e69cd74
VS		 5195static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5196{
5197 unsigned int credits, default_credits;
5198
5199 if (IS_CHERRYVIEW(dev_priv))
5200 default_credits = PFI_CREDIT(12);
5201 else
5202 default_credits = PFI_CREDIT(8);
5203
5204 if (DIV_ROUND_CLOSEST(dev_priv->vlv_cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5205 /* CHV suggested value is 31 or 63 */
5206 if (IS_CHERRYVIEW(dev_priv))
5207 credits = PFI_CREDIT_31;
5208 else
5209 credits = PFI_CREDIT(15);
5210 } else {
5211 credits = default_credits;
5212 }
5213
5214 /*
5215 * WA - write default credits before re-programming
5216 * FIXME: should we also set the resend bit here?
5217 */
5218 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5219 default_credits);
5220
5221 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5222 credits | PFI_CREDIT_RESEND);
5223
5224 /*
5225 * FIXME is this guaranteed to clear
5226 * immediately or should we poll for it?
5227 */
5228 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5229}
5230
679dacd4 5231static void valleyview_modeset_global_resources(struct drm_atomic_state *state)
30a970c6 5232{
679dacd4 5233 struct drm_device *dev = state->dev;
30a970c6 5234 struct drm_i915_private *dev_priv = dev->dev_private;
2f2d7aa1 5235 int max_pixclk = intel_mode_max_pixclk(dev_priv);
30a970c6
JB		 5236 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5237
383c5a6a 5238 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
738c05c0
ID		 5239 /*
5240 * FIXME: We can end up here with all power domains off, yet
5241 * with a CDCLK frequency other than the minimum. To account
5242 * for this take the PIPE-A power domain, which covers the HW
5243 * blocks needed for the following programming. This can be
5244 * removed once it's guaranteed that we get here either with
5245 * the minimum CDCLK set, or the required power domains
5246 * enabled.
5247 */
5248 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5249
383c5a6a
VS		 5250 if (IS_CHERRYVIEW(dev))
5251 cherryview_set_cdclk(dev, req_cdclk);
5252 else
5253 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 5254
1e69cd74
VS		 5255 vlv_program_pfi_credits(dev_priv);
5256
738c05c0 5257 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
383c5a6a 5258 }
30a970c6
JB		 5259}
5260
89b667f8
JB		 5261static void valleyview_crtc_enable(struct drm_crtc *crtc)
5262{
5263 struct drm_device *dev = crtc->dev;
a72e4c9f 5264 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 5265 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5266 struct intel_encoder *encoder;
5267 int pipe = intel_crtc->pipe;
23538ef1 5268 bool is_dsi;
89b667f8 5269
83d65738 5270 WARN_ON(!crtc->state->enable);
89b667f8
JB		 5271
5272 if (intel_crtc->active)
5273 return;
5274
409ee761 5275 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 5276
1ae0d137
VS		 5277 if (!is_dsi) {
5278 if (IS_CHERRYVIEW(dev))
6e3c9717 5279 chv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 5280 else
6e3c9717 5281 vlv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 5282 }
5b18e57c 5283
6e3c9717 5284 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5285 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 5286
5287 intel_set_pipe_timings(intel_crtc);
5288
c14b0485
VS		 5289 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5290 struct drm_i915_private *dev_priv = dev->dev_private;
5291
5292 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5293 I915_WRITE(CHV_CANVAS(pipe), 0);
5294 }
5295
5b18e57c
DV		 5296 i9xx_set_pipeconf(intel_crtc);
5297
89b667f8 5298 intel_crtc->active = true;
89b667f8 5299
a72e4c9f 5300 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5301
89b667f8
JB		 5302 for_each_encoder_on_crtc(dev, crtc, encoder)
5303 if (encoder->pre_pll_enable)
5304 encoder->pre_pll_enable(encoder);
5305
9d556c99
CML		 5306 if (!is_dsi) {
5307 if (IS_CHERRYVIEW(dev))
6e3c9717 5308 chv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 5309 else
6e3c9717 5310 vlv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 5311 }
89b667f8
JB		 5312
5313 for_each_encoder_on_crtc(dev, crtc, encoder)
5314 if (encoder->pre_enable)
5315 encoder->pre_enable(encoder);
5316
2dd24552
JB		 5317 i9xx_pfit_enable(intel_crtc);
5318
63cbb074
VS		 5319 intel_crtc_load_lut(crtc);
5320
f37fcc2a 5321 intel_update_watermarks(crtc);
e1fdc473 5322 intel_enable_pipe(intel_crtc);
be6a6f8e 5323
4b3a9526
VS		 5324 assert_vblank_disabled(crtc);
5325 drm_crtc_vblank_on(crtc);
5326
f9b61ff6
DV		 5327 for_each_encoder_on_crtc(dev, crtc, encoder)
5328 encoder->enable(encoder);
5329
9ab0460b 5330 intel_crtc_enable_planes(crtc);
d40d9187 5331
56b80e1f 5332 /* Underruns don't raise interrupts, so check manually. */
a72e4c9f 5333 i9xx_check_fifo_underruns(dev_priv);
89b667f8
JB		 5334}
5335
f13c2ef3
DV		 5336static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5337{
5338 struct drm_device *dev = crtc->base.dev;
5339 struct drm_i915_private *dev_priv = dev->dev_private;
5340
6e3c9717
ACO		 5341 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5342 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 5343}
5344
0b8765c6 5345static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 5346{
5347 struct drm_device *dev = crtc->dev;
a72e4c9f 5348 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 5349 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5350 struct intel_encoder *encoder;
79e53945 5351 int pipe = intel_crtc->pipe;
79e53945 5352
83d65738 5353 WARN_ON(!crtc->state->enable);
08a48469 5354
f7abfe8b
CW		 5355 if (intel_crtc->active)
5356 return;
5357
f13c2ef3
DV		 5358 i9xx_set_pll_dividers(intel_crtc);
5359
6e3c9717 5360 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5361 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 5362
5363 intel_set_pipe_timings(intel_crtc);
5364
5b18e57c
DV		 5365 i9xx_set_pipeconf(intel_crtc);
5366
f7abfe8b 5367 intel_crtc->active = true;
6b383a7f 5368
4a3436e8 5369 if (!IS_GEN2(dev))
a72e4c9f 5370 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5371
9d6d9f19
MK		 5372 for_each_encoder_on_crtc(dev, crtc, encoder)
5373 if (encoder->pre_enable)
5374 encoder->pre_enable(encoder);
5375
f6736a1a
DV		 5376 i9xx_enable_pll(intel_crtc);
5377
2dd24552
JB		 5378 i9xx_pfit_enable(intel_crtc);
5379
63cbb074
VS		 5380 intel_crtc_load_lut(crtc);
5381
f37fcc2a 5382 intel_update_watermarks(crtc);
e1fdc473 5383 intel_enable_pipe(intel_crtc);
be6a6f8e 5384
4b3a9526
VS		 5385 assert_vblank_disabled(crtc);
5386 drm_crtc_vblank_on(crtc);
5387
f9b61ff6
DV		 5388 for_each_encoder_on_crtc(dev, crtc, encoder)
5389 encoder->enable(encoder);
5390
9ab0460b 5391 intel_crtc_enable_planes(crtc);
d40d9187 5392
4a3436e8
VS		 5393 /*
5394 * Gen2 reports pipe underruns whenever all planes are disabled.
5395 * So don't enable underrun reporting before at least some planes
5396 * are enabled.
5397 * FIXME: Need to fix the logic to work when we turn off all planes
5398 * but leave the pipe running.
5399 */
5400 if (IS_GEN2(dev))
a72e4c9f 5401 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5402
56b80e1f 5403 /* Underruns don't raise interrupts, so check manually. */
a72e4c9f 5404 i9xx_check_fifo_underruns(dev_priv);
0b8765c6 5405}
79e53945 5406
87476d63
DV		 5407static void i9xx_pfit_disable(struct intel_crtc *crtc)
5408{
5409 struct drm_device *dev = crtc->base.dev;
5410 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 5411
6e3c9717 5412 if (!crtc->config->gmch_pfit.control)
328d8e82 5413 return;
87476d63 5414
328d8e82 5415 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 5416
328d8e82
DV		 5417 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5418 I915_READ(PFIT_CONTROL));
5419 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 5420}
5421
0b8765c6
JB		 5422static void i9xx_crtc_disable(struct drm_crtc *crtc)
5423{
5424 struct drm_device *dev = crtc->dev;
5425 struct drm_i915_private *dev_priv = dev->dev_private;
5426 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5427 struct intel_encoder *encoder;
0b8765c6 5428 int pipe = intel_crtc->pipe;
ef9c3aee 5429
f7abfe8b
CW		 5430 if (!intel_crtc->active)
5431 return;
5432
4a3436e8
VS		 5433 /*
5434 * Gen2 reports pipe underruns whenever all planes are disabled.
5435 * So diasble underrun reporting before all the planes get disabled.
5436 * FIXME: Need to fix the logic to work when we turn off all planes
5437 * but leave the pipe running.
5438 */
5439 if (IS_GEN2(dev))
a72e4c9f 5440 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4a3436e8 5441
564ed191
ID		 5442 /*
5443 * Vblank time updates from the shadow to live plane control register
5444 * are blocked if the memory self-refresh mode is active at that
5445 * moment. So to make sure the plane gets truly disabled, disable
5446 * first the self-refresh mode. The self-refresh enable bit in turn
5447 * will be checked/applied by the HW only at the next frame start
5448 * event which is after the vblank start event, so we need to have a
5449 * wait-for-vblank between disabling the plane and the pipe.
5450 */
5451 intel_set_memory_cxsr(dev_priv, false);
9ab0460b
VS		 5452 intel_crtc_disable_planes(crtc);
5453
6304cd91
VS		 5454 /*
5455 * On gen2 planes are double buffered but the pipe isn't, so we must
5456 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 5457 * We also need to wait on all gmch platforms because of the
5458 * self-refresh mode constraint explained above.
6304cd91 5459 */
564ed191 5460 intel_wait_for_vblank(dev, pipe);
6304cd91 5461
4b3a9526
VS		 5462 for_each_encoder_on_crtc(dev, crtc, encoder)
5463 encoder->disable(encoder);
5464
f9b61ff6
DV		 5465 drm_crtc_vblank_off(crtc);
5466 assert_vblank_disabled(crtc);
5467
575f7ab7 5468 intel_disable_pipe(intel_crtc);
24a1f16d 5469
87476d63 5470 i9xx_pfit_disable(intel_crtc);
24a1f16d 5471
89b667f8
JB		 5472 for_each_encoder_on_crtc(dev, crtc, encoder)
5473 if (encoder->post_disable)
5474 encoder->post_disable(encoder);
5475
409ee761 5476 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 5477 if (IS_CHERRYVIEW(dev))
5478 chv_disable_pll(dev_priv, pipe);
5479 else if (IS_VALLEYVIEW(dev))
5480 vlv_disable_pll(dev_priv, pipe);
5481 else
1c4e0274 5482 i9xx_disable_pll(intel_crtc);
076ed3b2 5483 }
0b8765c6 5484
4a3436e8 5485 if (!IS_GEN2(dev))
a72e4c9f 5486 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4a3436e8 5487
f7abfe8b 5488 intel_crtc->active = false;
46ba614c 5489 intel_update_watermarks(crtc);
f37fcc2a 5490
efa9624e 5491 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5492 intel_fbc_update(dev);
efa9624e 5493 mutex_unlock(&dev->struct_mutex);
0b8765c6
JB		 5494}
5495
ee7b9f93
JB		 5496static void i9xx_crtc_off(struct drm_crtc *crtc)
5497{
5498}
5499
b04c5bd6
BF		 5500/* Master function to enable/disable CRTC and corresponding power wells */
5501void intel_crtc_control(struct drm_crtc *crtc, bool enable)
976f8a20
DV		 5502{
5503 struct drm_device *dev = crtc->dev;
5504 struct drm_i915_private *dev_priv = dev->dev_private;
0e572fe7 5505 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
0e572fe7
DV		 5506 enum intel_display_power_domain domain;
5507 unsigned long domains;
976f8a20 5508
0e572fe7
DV		 5509 if (enable) {
5510 if (!intel_crtc->active) {
e1e9fb84
DV		 5511 domains = get_crtc_power_domains(crtc);
5512 for_each_power_domain(domain, domains)
5513 intel_display_power_get(dev_priv, domain);
5514 intel_crtc->enabled_power_domains = domains;
0e572fe7
DV		 5515
5516 dev_priv->display.crtc_enable(crtc);
5517 }
5518 } else {
5519 if (intel_crtc->active) {
5520 dev_priv->display.crtc_disable(crtc);
5521
e1e9fb84
DV		 5522 domains = intel_crtc->enabled_power_domains;
5523 for_each_power_domain(domain, domains)
5524 intel_display_power_put(dev_priv, domain);
5525 intel_crtc->enabled_power_domains = 0;
0e572fe7
DV		 5526 }
5527 }
b04c5bd6
BF		 5528}
5529
5530/**
5531 * Sets the power management mode of the pipe and plane.
5532 */
5533void intel_crtc_update_dpms(struct drm_crtc *crtc)
5534{
5535 struct drm_device *dev = crtc->dev;
5536 struct intel_encoder *intel_encoder;
5537 bool enable = false;
5538
5539 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5540 enable |= intel_encoder->connectors_active;
5541
5542 intel_crtc_control(crtc, enable);
976f8a20
DV		 5543}
5544
cdd59983
CW		 5545static void intel_crtc_disable(struct drm_crtc *crtc)
5546{
cdd59983 5547 struct drm_device *dev = crtc->dev;
976f8a20 5548 struct drm_connector *connector;
ee7b9f93 5549 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 5550
976f8a20 5551 /* crtc should still be enabled when we disable it. */
83d65738 5552 WARN_ON(!crtc->state->enable);
976f8a20
DV		 5553
5554 dev_priv->display.crtc_disable(crtc);
ee7b9f93
JB		 5555 dev_priv->display.off(crtc);
5556
455a6808 5557 crtc->primary->funcs->disable_plane(crtc->primary);
976f8a20
DV		 5558
5559 /* Update computed state. */
5560 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5561 if (!connector->encoder || !connector->encoder->crtc)
5562 continue;
5563
5564 if (connector->encoder->crtc != crtc)
5565 continue;
5566
5567 connector->dpms = DRM_MODE_DPMS_OFF;
5568 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 5569 }
5570}
5571
ea5b213a 5572void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 5573{
4ef69c7a 5574 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 5575
ea5b213a
CW		 5576 drm_encoder_cleanup(encoder);
5577 kfree(intel_encoder);
7e7d76c3
JB		 5578}
5579
9237329d 5580/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 5581 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5582 * state of the entire output pipe. */
9237329d 5583static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 5584{
5ab432ef
DV		 5585 if (mode == DRM_MODE_DPMS_ON) {
5586 encoder->connectors_active = true;
5587
b2cabb0e 5588 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 5589 } else {
5590 encoder->connectors_active = false;
5591
b2cabb0e 5592 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 5593 }
79e53945
JB		 5594}
5595
0a91ca29
DV		 5596/* Cross check the actual hw state with our own modeset state tracking (and it's
5597 * internal consistency). */
b980514c 5598static void intel_connector_check_state(struct intel_connector *connector)
79e53945 5599{
0a91ca29
DV		 5600 if (connector->get_hw_state(connector)) {
5601 struct intel_encoder *encoder = connector->encoder;
5602 struct drm_crtc *crtc;
5603 bool encoder_enabled;
5604 enum pipe pipe;
5605
5606 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5607 connector->base.base.id,
c23cc417 5608 connector->base.name);
0a91ca29 5609
0e32b39c
DA		 5610 /* there is no real hw state for MST connectors */
5611 if (connector->mst_port)
5612 return;
5613
e2c719b7 5614 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
0a91ca29 5615 "wrong connector dpms state\n");
e2c719b7 5616 I915_STATE_WARN(connector->base.encoder != &encoder->base,
0a91ca29 5617 "active connector not linked to encoder\n");
0a91ca29 5618
36cd7444 5619 if (encoder) {
e2c719b7 5620 I915_STATE_WARN(!encoder->connectors_active,
36cd7444
DA		 5621 "encoder->connectors_active not set\n");
5622
5623 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
e2c719b7
RC		 5624 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
5625 if (I915_STATE_WARN_ON(!encoder->base.crtc))
36cd7444 5626 return;
0a91ca29 5627
36cd7444 5628 crtc = encoder->base.crtc;
0a91ca29 5629
83d65738
MR		 5630 I915_STATE_WARN(!crtc->state->enable,
5631 "crtc not enabled\n");
e2c719b7
RC		 5632 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5633 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
36cd7444
DA		 5634 "encoder active on the wrong pipe\n");
5635 }
0a91ca29 5636 }
79e53945
JB		 5637}
5638
5ab432ef
DV		 5639/* Even simpler default implementation, if there's really no special case to
5640 * consider. */
5641void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 5642{
5ab432ef
DV		 5643 /* All the simple cases only support two dpms states. */
5644 if (mode != DRM_MODE_DPMS_ON)
5645 mode = DRM_MODE_DPMS_OFF;
d4270e57 5646
5ab432ef
DV		 5647 if (mode == connector->dpms)
5648 return;
5649
5650 connector->dpms = mode;
5651
5652 /* Only need to change hw state when actually enabled */
c9976dcf
CW		 5653 if (connector->encoder)
5654 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
0a91ca29 5655
b980514c 5656 intel_modeset_check_state(connector->dev);
79e53945
JB		 5657}
5658
f0947c37
DV		 5659/* Simple connector->get_hw_state implementation for encoders that support only
5660 * one connector and no cloning and hence the encoder state determines the state
5661 * of the connector. */
5662bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 5663{
24929352 5664 enum pipe pipe = 0;
f0947c37 5665 struct intel_encoder *encoder = connector->encoder;
ea5b213a 5666
f0947c37 5667 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 5668}
5669
6d293983 5670static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 5671{
6d293983
ACO		 5672 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
5673 return crtc_state->fdi_lanes;
d272ddfa
VS		 5674
5675 return 0;
5676}
5677
6d293983 5678static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 5679 struct intel_crtc_state *pipe_config)
1857e1da 5680{
6d293983
ACO		 5681 struct drm_atomic_state *state = pipe_config->base.state;
5682 struct intel_crtc *other_crtc;
5683 struct intel_crtc_state *other_crtc_state;
5684
1857e1da
DV		 5685 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5686 pipe_name(pipe), pipe_config->fdi_lanes);
5687 if (pipe_config->fdi_lanes > 4) {
5688 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5689 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 5690 return -EINVAL;
1857e1da
DV		 5691 }
5692
bafb6553 5693 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 5694 if (pipe_config->fdi_lanes > 2) {
5695 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5696 pipe_config->fdi_lanes);
6d293983 5697 return -EINVAL;
1857e1da 5698 } else {
6d293983 5699 return 0;
1857e1da
DV		 5700 }
5701 }
5702
5703 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 5704 return 0;
1857e1da
DV		 5705
5706 /* Ivybridge 3 pipe is really complicated */
5707 switch (pipe) {
5708 case PIPE_A:
6d293983 5709 return 0;
1857e1da 5710 case PIPE_B:
6d293983
ACO		 5711 if (pipe_config->fdi_lanes <= 2)
5712 return 0;
5713
5714 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
5715 other_crtc_state =
5716 intel_atomic_get_crtc_state(state, other_crtc);
5717 if (IS_ERR(other_crtc_state))
5718 return PTR_ERR(other_crtc_state);
5719
5720 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV		 5721 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5722 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 5723 return -EINVAL;
1857e1da 5724 }
6d293983 5725 return 0;
1857e1da 5726 case PIPE_C:
251cc67c
VS		 5727 if (pipe_config->fdi_lanes > 2) {
5728 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
5729 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 5730 return -EINVAL;
251cc67c 5731 }
6d293983
ACO		 5732
5733 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
5734 other_crtc_state =
5735 intel_atomic_get_crtc_state(state, other_crtc);
5736 if (IS_ERR(other_crtc_state))
5737 return PTR_ERR(other_crtc_state);
5738
5739 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 5740 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 5741 return -EINVAL;
1857e1da 5742 }
6d293983 5743 return 0;
1857e1da
DV		 5744 default:
5745 BUG();
5746 }
5747}
5748
e29c22c0
DV		 5749#define RETRY 1
5750static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 5751 struct intel_crtc_state *pipe_config)
877d48d5 5752{
1857e1da 5753 struct drm_device *dev = intel_crtc->base.dev;
2d112de7 5754 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 5755 int lane, link_bw, fdi_dotclock, ret;
5756 bool needs_recompute = false;
877d48d5 5757
e29c22c0 5758retry:
877d48d5
DV		 5759 /* FDI is a binary signal running at ~2.7GHz, encoding
5760 * each output octet as 10 bits. The actual frequency
5761 * is stored as a divider into a 100MHz clock, and the
5762 * mode pixel clock is stored in units of 1KHz.
5763 * Hence the bw of each lane in terms of the mode signal
5764 * is:
5765 */
5766 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5767
241bfc38 5768 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 5769
2bd89a07 5770 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 5771 pipe_config->pipe_bpp);
5772
5773 pipe_config->fdi_lanes = lane;
5774
2bd89a07 5775 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 5776 link_bw, &pipe_config->fdi_m_n);
1857e1da 5777
6d293983
ACO		 5778 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5779 intel_crtc->pipe, pipe_config);
5780 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV		 5781 pipe_config->pipe_bpp -= 2*3;
5782 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5783 pipe_config->pipe_bpp);
5784 needs_recompute = true;
5785 pipe_config->bw_constrained = true;
5786
5787 goto retry;
5788 }
5789
5790 if (needs_recompute)
5791 return RETRY;
5792
6d293983 5793 return ret;
877d48d5
DV		 5794}
5795
42db64ef 5796static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 5797 struct intel_crtc_state *pipe_config)
42db64ef 5798{
d330a953 5799 pipe_config->ips_enabled = i915.enable_ips &&
3c4ca58c 5800 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 5801 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 5802}
5803
a43f6e0f 5804static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 5805 struct intel_crtc_state *pipe_config)
79e53945 5806{
a43f6e0f 5807 struct drm_device *dev = crtc->base.dev;
8bd31e67 5808 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 5809 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
89749350 5810
ad3a4479 5811 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 5812 if (INTEL_INFO(dev)->gen < 4) {
cf532bb2
VS		 5813 int clock_limit =
5814 dev_priv->display.get_display_clock_speed(dev);
5815
5816 /*
5817 * Enable pixel doubling when the dot clock
5818 * is > 90% of the (display) core speed.
5819 *
b397c96b
VS		 5820 * GDG double wide on either pipe,
5821 * otherwise pipe A only.
cf532bb2 5822 */
b397c96b 5823 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 5824 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 5825 clock_limit *= 2;
cf532bb2 5826 pipe_config->double_wide = true;
ad3a4479
VS		 5827 }
5828
241bfc38 5829 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 5830 return -EINVAL;
2c07245f 5831 }
89749350 5832
1d1d0e27
VS		 5833 /*
5834 * Pipe horizontal size must be even in:
5835 * - DVO ganged mode
5836 * - LVDS dual channel mode
5837 * - Double wide pipe
5838 */
a93e255f 5839 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 5840 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5841 pipe_config->pipe_src_w &= ~1;
5842
8693a824
DL		 5843 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5844 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 5845 */
5846 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5847 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 5848 return -EINVAL;
44f46b42 5849
bd080ee5 5850 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 5851 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 5852 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 5853 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5854 * for lvds. */
5855 pipe_config->pipe_bpp = 8*3;
5856 }
5857
f5adf94e 5858 if (HAS_IPS(dev))
a43f6e0f
DV		 5859 hsw_compute_ips_config(crtc, pipe_config);
5860
877d48d5 5861 if (pipe_config->has_pch_encoder)
a43f6e0f 5862 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 5863
e29c22c0 5864 return 0;
79e53945
JB		 5865}
5866
1652d19e
VS		 5867static int skylake_get_display_clock_speed(struct drm_device *dev)
5868{
5869 struct drm_i915_private *dev_priv = to_i915(dev);
5870 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5871 uint32_t cdctl = I915_READ(CDCLK_CTL);
5872 uint32_t linkrate;
5873
5874 if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
5875 WARN(1, "LCPLL1 not enabled\n");
5876 return 24000; /* 24MHz is the cd freq with NSSC ref */
5877 }
5878
5879 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
5880 return 540000;
5881
5882 linkrate = (I915_READ(DPLL_CTRL1) &
5883 DPLL_CRTL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
5884
5885 if (linkrate == DPLL_CRTL1_LINK_RATE_2160 ||
5886 linkrate == DPLL_CRTL1_LINK_RATE_1080) {
5887 /* vco 8640 */
5888 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
5889 case CDCLK_FREQ_450_432:
5890 return 432000;
5891 case CDCLK_FREQ_337_308:
5892 return 308570;
5893 case CDCLK_FREQ_675_617:
5894 return 617140;
5895 default:
5896 WARN(1, "Unknown cd freq selection\n");
5897 }
5898 } else {
5899 /* vco 8100 */
5900 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
5901 case CDCLK_FREQ_450_432:
5902 return 450000;
5903 case CDCLK_FREQ_337_308:
5904 return 337500;
5905 case CDCLK_FREQ_675_617:
5906 return 675000;
5907 default:
5908 WARN(1, "Unknown cd freq selection\n");
5909 }
5910 }
5911
5912 /* error case, do as if DPLL0 isn't enabled */
5913 return 24000;
5914}
5915
5916static int broadwell_get_display_clock_speed(struct drm_device *dev)
5917{
5918 struct drm_i915_private *dev_priv = dev->dev_private;
5919 uint32_t lcpll = I915_READ(LCPLL_CTL);
5920 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
5921
5922 if (lcpll & LCPLL_CD_SOURCE_FCLK)
5923 return 800000;
5924 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5925 return 450000;
5926 else if (freq == LCPLL_CLK_FREQ_450)
5927 return 450000;
5928 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
5929 return 540000;
5930 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
5931 return 337500;
5932 else
5933 return 675000;
5934}
5935
5936static int haswell_get_display_clock_speed(struct drm_device *dev)
5937{
5938 struct drm_i915_private *dev_priv = dev->dev_private;
5939 uint32_t lcpll = I915_READ(LCPLL_CTL);
5940 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
5941
5942 if (lcpll & LCPLL_CD_SOURCE_FCLK)
5943 return 800000;
5944 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5945 return 450000;
5946 else if (freq == LCPLL_CLK_FREQ_450)
5947 return 450000;
5948 else if (IS_HSW_ULT(dev))
5949 return 337500;
5950 else
5951 return 540000;
5952}
5953
25eb05fc
JB		 5954static int valleyview_get_display_clock_speed(struct drm_device *dev)
5955{
d197b7d3 5956 struct drm_i915_private *dev_priv = dev->dev_private;
d197b7d3
VS		 5957 u32 val;
5958 int divider;
5959
6bcda4f0
VS		 5960 if (dev_priv->hpll_freq == 0)
5961 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5962
d197b7d3
VS		 5963 mutex_lock(&dev_priv->dpio_lock);
5964 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5965 mutex_unlock(&dev_priv->dpio_lock);
5966
5967 divider = val & DISPLAY_FREQUENCY_VALUES;
5968
7d007f40
VS		 5969 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5970 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5971 "cdclk change in progress\n");
5972
6bcda4f0 5973 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
25eb05fc
JB		 5974}
5975
b37a6434
VS		 5976static int ilk_get_display_clock_speed(struct drm_device *dev)
5977{
5978 return 450000;
5979}
5980
e70236a8
JB		 5981static int i945_get_display_clock_speed(struct drm_device *dev)
5982{
5983 return 400000;
5984}
79e53945 5985
e70236a8 5986static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 5987{
e907f170 5988 return 333333;
e70236a8 5989}
79e53945 5990
e70236a8
JB		 5991static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5992{
5993 return 200000;
5994}
79e53945 5995
257a7ffc
DV		 5996static int pnv_get_display_clock_speed(struct drm_device *dev)
5997{
5998 u16 gcfgc = 0;
5999
6000 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6001
6002 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6003 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6004 return 266667;
257a7ffc 6005 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6006 return 333333;
257a7ffc 6007 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6008 return 444444;
257a7ffc
DV		 6009 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6010 return 200000;
6011 default:
6012 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6013 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6014 return 133333;
257a7ffc 6015 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6016 return 166667;
257a7ffc
DV		 6017 }
6018}
6019
e70236a8
JB		 6020static int i915gm_get_display_clock_speed(struct drm_device *dev)
6021{
6022 u16 gcfgc = 0;
79e53945 6023
e70236a8
JB		 6024 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6025
6026 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6027 return 133333;
e70236a8
JB		 6028 else {
6029 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6030 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6031 return 333333;
e70236a8
JB		 6032 default:
6033 case GC_DISPLAY_CLOCK_190_200_MHZ:
6034 return 190000;
79e53945 6035 }
e70236a8
JB		 6036 }
6037}
6038
6039static int i865_get_display_clock_speed(struct drm_device *dev)
6040{
e907f170 6041 return 266667;
e70236a8
JB		 6042}
6043
6044static int i855_get_display_clock_speed(struct drm_device *dev)
6045{
6046 u16 hpllcc = 0;
6047 /* Assume that the hardware is in the high speed state. This
6048 * should be the default.
6049 */
6050 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6051 case GC_CLOCK_133_200:
6052 case GC_CLOCK_100_200:
6053 return 200000;
6054 case GC_CLOCK_166_250:
6055 return 250000;
6056 case GC_CLOCK_100_133:
e907f170 6057 return 133333;
e70236a8 6058 }
79e53945 6059
e70236a8
JB		 6060 /* Shouldn't happen */
6061 return 0;
6062}
79e53945 6063
e70236a8
JB		 6064static int i830_get_display_clock_speed(struct drm_device *dev)
6065{
e907f170 6066 return 133333;
79e53945
JB		 6067}
6068
2c07245f 6069static void
a65851af 6070intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 6071{
a65851af
VS		 6072 while (*num > DATA_LINK_M_N_MASK ||
6073 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 6074 *num >>= 1;
6075 *den >>= 1;
6076 }
6077}
6078
a65851af
VS		 6079static void compute_m_n(unsigned int m, unsigned int n,
6080 uint32_t *ret_m, uint32_t *ret_n)
6081{
6082 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6083 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6084 intel_reduce_m_n_ratio(ret_m, ret_n);
6085}
6086
e69d0bc1
DV		 6087void
6088intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6089 int pixel_clock, int link_clock,
6090 struct intel_link_m_n *m_n)
2c07245f 6091{
e69d0bc1 6092 m_n->tu = 64;
a65851af
VS		 6093
6094 compute_m_n(bits_per_pixel * pixel_clock,
6095 link_clock * nlanes * 8,
6096 &m_n->gmch_m, &m_n->gmch_n);
6097
6098 compute_m_n(pixel_clock, link_clock,
6099 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 6100}
6101
a7615030
CW		 6102static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6103{
d330a953
JN		 6104 if (i915.panel_use_ssc >= 0)
6105 return i915.panel_use_ssc != 0;
41aa3448 6106 return dev_priv->vbt.lvds_use_ssc
435793df 6107 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 6108}
6109
a93e255f
ACO		 6110static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
6111 int num_connectors)
c65d77d8 6112{
a93e255f 6113 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 6114 struct drm_i915_private *dev_priv = dev->dev_private;
6115 int refclk;
6116
a93e255f
ACO		 6117 WARN_ON(!crtc_state->base.state);
6118
a0c4da24 6119 if (IS_VALLEYVIEW(dev)) {
9a0ea498 6120 refclk = 100000;
a93e255f 6121 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 6122 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 6123 refclk = dev_priv->vbt.lvds_ssc_freq;
6124 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 6125 } else if (!IS_GEN2(dev)) {
6126 refclk = 96000;
6127 } else {
6128 refclk = 48000;
6129 }
6130
6131 return refclk;
6132}
6133
7429e9d4 6134static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 6135{
7df00d7a 6136 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 6137}
f47709a9 6138
7429e9d4
DV		 6139static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6140{
6141 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 6142}
6143
f47709a9 6144static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 6145 struct intel_crtc_state *crtc_state,
a7516a05
JB		 6146 intel_clock_t *reduced_clock)
6147{
f47709a9 6148 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 6149 u32 fp, fp2 = 0;
6150
6151 if (IS_PINEVIEW(dev)) {
190f68c5 6152 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 6153 if (reduced_clock)
7429e9d4 6154 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 6155 } else {
190f68c5 6156 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 6157 if (reduced_clock)
7429e9d4 6158 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 6159 }
6160
190f68c5 6161 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 6162
f47709a9 6163 crtc->lowfreq_avail = false;
a93e255f 6164 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 6165 reduced_clock) {
190f68c5 6166 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 6167 crtc->lowfreq_avail = true;
a7516a05 6168 } else {
190f68c5 6169 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 6170 }
6171}
6172
5e69f97f
CML		 6173static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6174 pipe)
89b667f8
JB		 6175{
6176 u32 reg_val;
6177
6178 /*
6179 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6180 * and set it to a reasonable value instead.
6181 */
ab3c759a 6182 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 6183 reg_val &= 0xffffff00;
6184 reg_val |= 0x00000030;
ab3c759a 6185 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 6186
ab3c759a 6187 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 6188 reg_val &= 0x8cffffff;
6189 reg_val = 0x8c000000;
ab3c759a 6190 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 6191
ab3c759a 6192 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 6193 reg_val &= 0xffffff00;
ab3c759a 6194 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 6195
ab3c759a 6196 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 6197 reg_val &= 0x00ffffff;
6198 reg_val |= 0xb0000000;
ab3c759a 6199 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 6200}
6201
b551842d
DV		 6202static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6203 struct intel_link_m_n *m_n)
6204{
6205 struct drm_device *dev = crtc->base.dev;
6206 struct drm_i915_private *dev_priv = dev->dev_private;
6207 int pipe = crtc->pipe;
6208
e3b95f1e
DV		 6209 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6210 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6211 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6212 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 6213}
6214
6215static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 6216 struct intel_link_m_n *m_n,
6217 struct intel_link_m_n *m2_n2)
b551842d
DV		 6218{
6219 struct drm_device *dev = crtc->base.dev;
6220 struct drm_i915_private *dev_priv = dev->dev_private;
6221 int pipe = crtc->pipe;
6e3c9717 6222 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 6223
6224 if (INTEL_INFO(dev)->gen >= 5) {
6225 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6226 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6227 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6228 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 6229 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6230 * for gen < 8) and if DRRS is supported (to make sure the
6231 * registers are not unnecessarily accessed).
6232 */
44395bfe 6233 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 6234 crtc->config->has_drrs) {
f769cd24
VK		 6235 I915_WRITE(PIPE_DATA_M2(transcoder),
6236 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6237 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6238 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6239 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6240 }
b551842d 6241 } else {
e3b95f1e
DV		 6242 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6243 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6244 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6245 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 6246 }
6247}
6248
fe3cd48d 6249void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 6250{
fe3cd48d
R		 6251 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6252
6253 if (m_n == M1_N1) {
6254 dp_m_n = &crtc->config->dp_m_n;
6255 dp_m2_n2 = &crtc->config->dp_m2_n2;
6256 } else if (m_n == M2_N2) {
6257
6258 /*
6259 * M2_N2 registers are not supported. Hence m2_n2 divider value
6260 * needs to be programmed into M1_N1.
6261 */
6262 dp_m_n = &crtc->config->dp_m2_n2;
6263 } else {
6264 DRM_ERROR("Unsupported divider value\n");
6265 return;
6266 }
6267
6e3c9717
ACO		 6268 if (crtc->config->has_pch_encoder)
6269 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 6270 else
fe3cd48d 6271 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 6272}
6273
d288f65f 6274static void vlv_update_pll(struct intel_crtc *crtc,
5cec258b 6275 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 6276{
6277 u32 dpll, dpll_md;
6278
6279 /*
6280 * Enable DPIO clock input. We should never disable the reference
6281 * clock for pipe B, since VGA hotplug / manual detection depends
6282 * on it.
6283 */
6284 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6285 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6286 /* We should never disable this, set it here for state tracking */
6287 if (crtc->pipe == PIPE_B)
6288 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6289 dpll |= DPLL_VCO_ENABLE;
d288f65f 6290 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 6291
d288f65f 6292 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 6293 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 6294 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 6295}
6296
d288f65f 6297static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 6298 const struct intel_crtc_state *pipe_config)
a0c4da24 6299{
f47709a9 6300 struct drm_device *dev = crtc->base.dev;
a0c4da24 6301 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 6302 int pipe = crtc->pipe;
bdd4b6a6 6303 u32 mdiv;
a0c4da24 6304 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 6305 u32 coreclk, reg_val;
a0c4da24 6306
09153000
DV		 6307 mutex_lock(&dev_priv->dpio_lock);
6308
d288f65f
VS		 6309 bestn = pipe_config->dpll.n;
6310 bestm1 = pipe_config->dpll.m1;
6311 bestm2 = pipe_config->dpll.m2;
6312 bestp1 = pipe_config->dpll.p1;
6313 bestp2 = pipe_config->dpll.p2;
a0c4da24 6314
89b667f8
JB		 6315 /* See eDP HDMI DPIO driver vbios notes doc */
6316
6317 /* PLL B needs special handling */
bdd4b6a6 6318 if (pipe == PIPE_B)
5e69f97f 6319 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 6320
6321 /* Set up Tx target for periodic Rcomp update */
ab3c759a 6322 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 6323
6324 /* Disable target IRef on PLL */
ab3c759a 6325 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 6326 reg_val &= 0x00ffffff;
ab3c759a 6327 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 6328
6329 /* Disable fast lock */
ab3c759a 6330 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 6331
6332 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 6333 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6334 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6335 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 6336 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 6337
6338 /*
6339 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6340 * but we don't support that).
6341 * Note: don't use the DAC post divider as it seems unstable.
6342 */
6343 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 6344 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 6345
a0c4da24 6346 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 6347 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 6348
89b667f8 6349 /* Set HBR and RBR LPF coefficients */
d288f65f 6350 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 6351 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6352 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 6353 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 6354 0x009f0003);
89b667f8 6355 else
ab3c759a 6356 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 6357 0x00d0000f);
6358
681a8504 6359 if (pipe_config->has_dp_encoder) {
89b667f8 6360 /* Use SSC source */
bdd4b6a6 6361 if (pipe == PIPE_A)
ab3c759a 6362 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6363 0x0df40000);
6364 else
ab3c759a 6365 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6366 0x0df70000);
6367 } else { /* HDMI or VGA */
6368 /* Use bend source */
bdd4b6a6 6369 if (pipe == PIPE_A)
ab3c759a 6370 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6371 0x0df70000);
6372 else
ab3c759a 6373 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6374 0x0df40000);
6375 }
a0c4da24 6376
ab3c759a 6377 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 6378 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 6379 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6380 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 6381 coreclk |= 0x01000000;
ab3c759a 6382 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 6383
ab3c759a 6384 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
09153000 6385 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 6386}
6387
d288f65f 6388static void chv_update_pll(struct intel_crtc *crtc,
5cec258b 6389 struct intel_crtc_state *pipe_config)
1ae0d137 6390{
d288f65f 6391 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
1ae0d137
VS		 6392 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6393 DPLL_VCO_ENABLE;
6394 if (crtc->pipe != PIPE_A)
d288f65f 6395 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 6396
d288f65f
VS		 6397 pipe_config->dpll_hw_state.dpll_md =
6398 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 6399}
6400
d288f65f 6401static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 6402 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 6403{
6404 struct drm_device *dev = crtc->base.dev;
6405 struct drm_i915_private *dev_priv = dev->dev_private;
6406 int pipe = crtc->pipe;
6407 int dpll_reg = DPLL(crtc->pipe);
6408 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 6409 u32 loopfilter, tribuf_calcntr;
9d556c99 6410 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 6411 u32 dpio_val;
9cbe40c1 6412 int vco;
9d556c99 6413
d288f65f
VS		 6414 bestn = pipe_config->dpll.n;
6415 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6416 bestm1 = pipe_config->dpll.m1;
6417 bestm2 = pipe_config->dpll.m2 >> 22;
6418 bestp1 = pipe_config->dpll.p1;
6419 bestp2 = pipe_config->dpll.p2;
9cbe40c1 6420 vco = pipe_config->dpll.vco;
a945ce7e 6421 dpio_val = 0;
9cbe40c1 6422 loopfilter = 0;
9d556c99
CML		 6423
6424 /*
6425 * Enable Refclk and SSC
6426 */
a11b0703 6427 I915_WRITE(dpll_reg,
d288f65f 6428 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703
VS		 6429
6430 mutex_lock(&dev_priv->dpio_lock);
9d556c99 6431
9d556c99
CML		 6432 /* p1 and p2 divider */
6433 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6434 5 << DPIO_CHV_S1_DIV_SHIFT |
6435 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6436 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6437 1 << DPIO_CHV_K_DIV_SHIFT);
6438
6439 /* Feedback post-divider - m2 */
6440 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6441
6442 /* Feedback refclk divider - n and m1 */
6443 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6444 DPIO_CHV_M1_DIV_BY_2 |
6445 1 << DPIO_CHV_N_DIV_SHIFT);
6446
6447 /* M2 fraction division */
a945ce7e
VP		 6448 if (bestm2_frac)
6449 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 6450
6451 /* M2 fraction division enable */
a945ce7e
VP		 6452 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6453 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6454 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6455 if (bestm2_frac)
6456 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6457 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 6458
de3a0fde
VP		 6459 /* Program digital lock detect threshold */
6460 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6461 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6462 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6463 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6464 if (!bestm2_frac)
6465 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6466 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6467
9d556c99 6468 /* Loop filter */
9cbe40c1
VP		 6469 if (vco == 5400000) {
6470 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6471 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6472 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6473 tribuf_calcntr = 0x9;
6474 } else if (vco <= 6200000) {
6475 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6476 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6477 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6478 tribuf_calcntr = 0x9;
6479 } else if (vco <= 6480000) {
6480 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6481 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6482 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6483 tribuf_calcntr = 0x8;
6484 } else {
6485 /* Not supported. Apply the same limits as in the max case */
6486 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6487 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6488 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6489 tribuf_calcntr = 0;
6490 }
9d556c99
CML		 6491 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6492
968040b2 6493 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 6494 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6495 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6496 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6497
9d556c99
CML		 6498 /* AFC Recal */
6499 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6500 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6501 DPIO_AFC_RECAL);
6502
6503 mutex_unlock(&dev_priv->dpio_lock);
6504}
6505
d288f65f
VS		 6506/**
6507 * vlv_force_pll_on - forcibly enable just the PLL
6508 * @dev_priv: i915 private structure
6509 * @pipe: pipe PLL to enable
6510 * @dpll: PLL configuration
6511 *
6512 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6513 * in cases where we need the PLL enabled even when @pipe is not going to
6514 * be enabled.
6515 */
6516void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6517 const struct dpll *dpll)
6518{
6519 struct intel_crtc *crtc =
6520 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 6521 struct intel_crtc_state pipe_config = {
a93e255f 6522 .base.crtc = &crtc->base,
d288f65f
VS		 6523 .pixel_multiplier = 1,
6524 .dpll = *dpll,
6525 };
6526
6527 if (IS_CHERRYVIEW(dev)) {
6528 chv_update_pll(crtc, &pipe_config);
6529 chv_prepare_pll(crtc, &pipe_config);
6530 chv_enable_pll(crtc, &pipe_config);
6531 } else {
6532 vlv_update_pll(crtc, &pipe_config);
6533 vlv_prepare_pll(crtc, &pipe_config);
6534 vlv_enable_pll(crtc, &pipe_config);
6535 }
6536}
6537
6538/**
6539 * vlv_force_pll_off - forcibly disable just the PLL
6540 * @dev_priv: i915 private structure
6541 * @pipe: pipe PLL to disable
6542 *
6543 * Disable the PLL for @pipe. To be used in cases where we need
6544 * the PLL enabled even when @pipe is not going to be enabled.
6545 */
6546void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6547{
6548 if (IS_CHERRYVIEW(dev))
6549 chv_disable_pll(to_i915(dev), pipe);
6550 else
6551 vlv_disable_pll(to_i915(dev), pipe);
6552}
6553
f47709a9 6554static void i9xx_update_pll(struct intel_crtc *crtc,
190f68c5 6555 struct intel_crtc_state *crtc_state,
f47709a9 6556 intel_clock_t *reduced_clock,
eb1cbe48
DV		 6557 int num_connectors)
6558{
f47709a9 6559 struct drm_device *dev = crtc->base.dev;
eb1cbe48 6560 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 6561 u32 dpll;
6562 bool is_sdvo;
190f68c5 6563 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 6564
190f68c5 6565 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 6566
a93e255f
ACO		 6567 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
6568 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 6569
6570 dpll = DPLL_VGA_MODE_DIS;
6571
a93e255f 6572 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 6573 dpll |= DPLLB_MODE_LVDS;
6574 else
6575 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 6576
ef1b460d 6577 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 6578 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 6579 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 6580 }
198a037f
DV		 6581
6582 if (is_sdvo)
4a33e48d 6583 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 6584
190f68c5 6585 if (crtc_state->has_dp_encoder)
4a33e48d 6586 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 6587
6588 /* compute bitmask from p1 value */
6589 if (IS_PINEVIEW(dev))
6590 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6591 else {
6592 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6593 if (IS_G4X(dev) && reduced_clock)
6594 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6595 }
6596 switch (clock->p2) {
6597 case 5:
6598 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6599 break;
6600 case 7:
6601 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6602 break;
6603 case 10:
6604 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6605 break;
6606 case 14:
6607 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6608 break;
6609 }
6610 if (INTEL_INFO(dev)->gen >= 4)
6611 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6612
190f68c5 6613 if (crtc_state->sdvo_tv_clock)
eb1cbe48 6614 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 6615 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 6616 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6617 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6618 else
6619 dpll |= PLL_REF_INPUT_DREFCLK;
6620
6621 dpll |= DPLL_VCO_ENABLE;
190f68c5 6622 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 6623
eb1cbe48 6624 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 6625 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 6626 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 6627 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 6628 }
6629}
6630
f47709a9 6631static void i8xx_update_pll(struct intel_crtc *crtc,
190f68c5 6632 struct intel_crtc_state *crtc_state,
f47709a9 6633 intel_clock_t *reduced_clock,
eb1cbe48
DV		 6634 int num_connectors)
6635{
f47709a9 6636 struct drm_device *dev = crtc->base.dev;
eb1cbe48 6637 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 6638 u32 dpll;
190f68c5 6639 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 6640
190f68c5 6641 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 6642
eb1cbe48
DV		 6643 dpll = DPLL_VGA_MODE_DIS;
6644
a93e255f 6645 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 6646 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6647 } else {
6648 if (clock->p1 == 2)
6649 dpll |= PLL_P1_DIVIDE_BY_TWO;
6650 else
6651 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6652 if (clock->p2 == 4)
6653 dpll |= PLL_P2_DIVIDE_BY_4;
6654 }
6655
a93e255f 6656 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 6657 dpll |= DPLL_DVO_2X_MODE;
6658
a93e255f 6659 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 6660 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6661 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6662 else
6663 dpll |= PLL_REF_INPUT_DREFCLK;
6664
6665 dpll |= DPLL_VCO_ENABLE;
190f68c5 6666 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 6667}
6668
8a654f3b 6669static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 6670{
6671 struct drm_device *dev = intel_crtc->base.dev;
6672 struct drm_i915_private *dev_priv = dev->dev_private;
6673 enum pipe pipe = intel_crtc->pipe;
6e3c9717 6674 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8a654f3b 6675 struct drm_display_mode *adjusted_mode =
6e3c9717 6676 &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 6677 uint32_t crtc_vtotal, crtc_vblank_end;
6678 int vsyncshift = 0;
4d8a62ea
DV		 6679
6680 /* We need to be careful not to changed the adjusted mode, for otherwise
6681 * the hw state checker will get angry at the mismatch. */
6682 crtc_vtotal = adjusted_mode->crtc_vtotal;
6683 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 6684
609aeaca 6685 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 6686 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 6687 crtc_vtotal -= 1;
6688 crtc_vblank_end -= 1;
609aeaca 6689
409ee761 6690 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 6691 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6692 else
6693 vsyncshift = adjusted_mode->crtc_hsync_start -
6694 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 6695 if (vsyncshift < 0)
6696 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 6697 }
6698
6699 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 6700 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 6701
fe2b8f9d 6702 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 6703 (adjusted_mode->crtc_hdisplay - 1) |
6704 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 6705 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 6706 (adjusted_mode->crtc_hblank_start - 1) |
6707 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 6708 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 6709 (adjusted_mode->crtc_hsync_start - 1) |
6710 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6711
fe2b8f9d 6712 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 6713 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 6714 ((crtc_vtotal - 1) << 16));
fe2b8f9d 6715 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 6716 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 6717 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 6718 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 6719 (adjusted_mode->crtc_vsync_start - 1) |
6720 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6721
b5e508d4
PZ		 6722 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6723 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6724 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6725 * bits. */
6726 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6727 (pipe == PIPE_B || pipe == PIPE_C))
6728 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6729
b0e77b9c
PZ		 6730 /* pipesrc controls the size that is scaled from, which should
6731 * always be the user's requested size.
6732 */
6733 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 6734 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6735 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 6736}
6737
1bd1bd80 6738static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 6739 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 6740{
6741 struct drm_device *dev = crtc->base.dev;
6742 struct drm_i915_private *dev_priv = dev->dev_private;
6743 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6744 uint32_t tmp;
6745
6746 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 6747 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6748 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 6749 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 6750 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6751 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 6752 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 6753 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6754 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 6755
6756 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 6757 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6758 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 6759 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 6760 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6761 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 6762 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 6763 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6764 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 6765
6766 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 6767 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6768 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6769 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 6770 }
6771
6772 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 6773 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6774 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6775
2d112de7
ACO		 6776 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6777 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 6778}
6779
f6a83288 6780void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 6781 struct intel_crtc_state *pipe_config)
babea61d 6782{
2d112de7
ACO		 6783 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6784 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6785 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6786 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 6787
2d112de7
ACO		 6788 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6789 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6790 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6791 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 6792
2d112de7 6793 mode->flags = pipe_config->base.adjusted_mode.flags;
babea61d 6794
2d112de7
ACO		 6795 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6796 mode->flags |= pipe_config->base.adjusted_mode.flags;
babea61d
JB		 6797}
6798
84b046f3
DV		 6799static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6800{
6801 struct drm_device *dev = intel_crtc->base.dev;
6802 struct drm_i915_private *dev_priv = dev->dev_private;
6803 uint32_t pipeconf;
6804
9f11a9e4 6805 pipeconf = 0;
84b046f3 6806
b6b5d049
VS		 6807 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6808 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6809 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 6810
6e3c9717 6811 if (intel_crtc->config->double_wide)
cf532bb2 6812 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 6813
ff9ce46e
DV		 6814 /* only g4x and later have fancy bpc/dither controls */
6815 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 6816 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 6817 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 6818 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 6819 PIPECONF_DITHER_TYPE_SP;
84b046f3 6820
6e3c9717 6821 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 6822 case 18:
6823 pipeconf |= PIPECONF_6BPC;
6824 break;
6825 case 24:
6826 pipeconf |= PIPECONF_8BPC;
6827 break;
6828 case 30:
6829 pipeconf |= PIPECONF_10BPC;
6830 break;
6831 default:
6832 /* Case prevented by intel_choose_pipe_bpp_dither. */
6833 BUG();
84b046f3
DV		 6834 }
6835 }
6836
6837 if (HAS_PIPE_CXSR(dev)) {
6838 if (intel_crtc->lowfreq_avail) {
6839 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6840 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6841 } else {
6842 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 6843 }
6844 }
6845
6e3c9717 6846 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 6847 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 6848 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 6849 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6850 else
6851 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6852 } else
84b046f3
DV		 6853 pipeconf |= PIPECONF_PROGRESSIVE;
6854
6e3c9717 6855 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 6856 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 6857
84b046f3
DV		 6858 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6859 POSTING_READ(PIPECONF(intel_crtc->pipe));
6860}
6861
190f68c5
ACO		 6862static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
6863 struct intel_crtc_state *crtc_state)
79e53945 6864{
c7653199 6865 struct drm_device *dev = crtc->base.dev;
79e53945 6866 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 6867 int refclk, num_connectors = 0;
652c393a 6868 intel_clock_t clock, reduced_clock;
a16af721 6869 bool ok, has_reduced_clock = false;
e9fd1c02 6870 bool is_lvds = false, is_dsi = false;
5eddb70b 6871 struct intel_encoder *encoder;
d4906093 6872 const intel_limit_t *limit;
55bb9992
ACO		 6873 struct drm_atomic_state *state = crtc_state->base.state;
6874 struct drm_connector_state *connector_state;
6875 int i;
79e53945 6876
55bb9992
ACO		 6877 for (i = 0; i < state->num_connector; i++) {
6878 if (!state->connectors[i])
d0737e1d
ACO		 6879 continue;
6880
55bb9992
ACO		 6881 connector_state = state->connector_states[i];
6882 if (connector_state->crtc != &crtc->base)
6883 continue;
6884
6885 encoder = to_intel_encoder(connector_state->best_encoder);
6886
5eddb70b 6887 switch (encoder->type) {
79e53945
JB		 6888 case INTEL_OUTPUT_LVDS:
6889 is_lvds = true;
6890 break;
e9fd1c02
JN		 6891 case INTEL_OUTPUT_DSI:
6892 is_dsi = true;
6893 break;
6847d71b
PZ		 6894 default:
6895 break;
79e53945 6896 }
43565a06 6897
c751ce4f 6898 num_connectors++;
79e53945
JB		 6899 }
6900
f2335330 6901 if (is_dsi)
5b18e57c 6902 return 0;
f2335330 6903
190f68c5 6904 if (!crtc_state->clock_set) {
a93e255f 6905 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 6906
e9fd1c02
JN		 6907 /*
6908 * Returns a set of divisors for the desired target clock with
6909 * the given refclk, or FALSE. The returned values represent
6910 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6911 * 2) / p1 / p2.
6912 */
a93e255f
ACO		 6913 limit = intel_limit(crtc_state, refclk);
6914 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 6915 crtc_state->port_clock,
e9fd1c02 6916 refclk, NULL, &clock);
f2335330 6917 if (!ok) {
e9fd1c02
JN		 6918 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6919 return -EINVAL;
6920 }
79e53945 6921
f2335330
JN		 6922 if (is_lvds && dev_priv->lvds_downclock_avail) {
6923 /*
6924 * Ensure we match the reduced clock's P to the target
6925 * clock. If the clocks don't match, we can't switch
6926 * the display clock by using the FP0/FP1. In such case
6927 * we will disable the LVDS downclock feature.
6928 */
6929 has_reduced_clock =
a93e255f 6930 dev_priv->display.find_dpll(limit, crtc_state,
f2335330
JN		 6931 dev_priv->lvds_downclock,
6932 refclk, &clock,
6933 &reduced_clock);
6934 }
6935 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 6936 crtc_state->dpll.n = clock.n;
6937 crtc_state->dpll.m1 = clock.m1;
6938 crtc_state->dpll.m2 = clock.m2;
6939 crtc_state->dpll.p1 = clock.p1;
6940 crtc_state->dpll.p2 = clock.p2;
f47709a9 6941 }
7026d4ac 6942
e9fd1c02 6943 if (IS_GEN2(dev)) {
190f68c5 6944 i8xx_update_pll(crtc, crtc_state,
2a8f64ca
VP		 6945 has_reduced_clock ? &reduced_clock : NULL,
6946 num_connectors);
9d556c99 6947 } else if (IS_CHERRYVIEW(dev)) {
190f68c5 6948 chv_update_pll(crtc, crtc_state);
e9fd1c02 6949 } else if (IS_VALLEYVIEW(dev)) {
190f68c5 6950 vlv_update_pll(crtc, crtc_state);
e9fd1c02 6951 } else {
190f68c5 6952 i9xx_update_pll(crtc, crtc_state,
eb1cbe48 6953 has_reduced_clock ? &reduced_clock : NULL,
eba905b2 6954 num_connectors);
e9fd1c02 6955 }
79e53945 6956
c8f7a0db 6957 return 0;
f564048e
EA		 6958}
6959
2fa2fe9a 6960static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 6961 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 6962{
6963 struct drm_device *dev = crtc->base.dev;
6964 struct drm_i915_private *dev_priv = dev->dev_private;
6965 uint32_t tmp;
6966
dc9e7dec
VS		 6967 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6968 return;
6969
2fa2fe9a 6970 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 6971 if (!(tmp & PFIT_ENABLE))
6972 return;
2fa2fe9a 6973
06922821 6974 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 6975 if (INTEL_INFO(dev)->gen < 4) {
6976 if (crtc->pipe != PIPE_B)
6977 return;
2fa2fe9a
DV		 6978 } else {
6979 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6980 return;
6981 }
6982
06922821 6983 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 6984 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6985 if (INTEL_INFO(dev)->gen < 5)
6986 pipe_config->gmch_pfit.lvds_border_bits =
6987 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6988}
6989
acbec814 6990static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 6991 struct intel_crtc_state *pipe_config)
acbec814
JB		 6992{
6993 struct drm_device *dev = crtc->base.dev;
6994 struct drm_i915_private *dev_priv = dev->dev_private;
6995 int pipe = pipe_config->cpu_transcoder;
6996 intel_clock_t clock;
6997 u32 mdiv;
662c6ecb 6998 int refclk = 100000;
acbec814 6999
f573de5a
SK		 7000 /* In case of MIPI DPLL will not even be used */
7001 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7002 return;
7003
acbec814 7004 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 7005 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
acbec814
JB		 7006 mutex_unlock(&dev_priv->dpio_lock);
7007
7008 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7009 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7010 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7011 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7012 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7013
f646628b 7014 vlv_clock(refclk, &clock);
acbec814 7015
f646628b
VS		 7016 /* clock.dot is the fast clock */
7017 pipe_config->port_clock = clock.dot / 5;
acbec814
JB		 7018}
7019
5724dbd1
DL		 7020static void
7021i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7022 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 7023{
7024 struct drm_device *dev = crtc->base.dev;
7025 struct drm_i915_private *dev_priv = dev->dev_private;
7026 u32 val, base, offset;
7027 int pipe = crtc->pipe, plane = crtc->plane;
7028 int fourcc, pixel_format;
6761dd31 7029 unsigned int aligned_height;
b113d5ee 7030 struct drm_framebuffer *fb;
1b842c89 7031 struct intel_framebuffer *intel_fb;
1ad292b5 7032
42a7b088
DL		 7033 val = I915_READ(DSPCNTR(plane));
7034 if (!(val & DISPLAY_PLANE_ENABLE))
7035 return;
7036
d9806c9f 7037 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 7038 if (!intel_fb) {
1ad292b5
JB		 7039 DRM_DEBUG_KMS("failed to alloc fb\n");
7040 return;
7041 }
7042
1b842c89
DL		 7043 fb = &intel_fb->base;
7044
18c5247e
DV		 7045 if (INTEL_INFO(dev)->gen >= 4) {
7046 if (val & DISPPLANE_TILED) {
49af449b 7047 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 7048 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7049 }
7050 }
1ad292b5
JB		 7051
7052 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 7053 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 7054 fb->pixel_format = fourcc;
7055 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 7056
7057 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 7058 if (plane_config->tiling)
1ad292b5
JB		 7059 offset = I915_READ(DSPTILEOFF(plane));
7060 else
7061 offset = I915_READ(DSPLINOFF(plane));
7062 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7063 } else {
7064 base = I915_READ(DSPADDR(plane));
7065 }
7066 plane_config->base = base;
7067
7068 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 7069 fb->width = ((val >> 16) & 0xfff) + 1;
7070 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 7071
7072 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 7073 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 7074
b113d5ee 7075 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 7076 fb->pixel_format,
7077 fb->modifier[0]);
1ad292b5 7078
f37b5c2b 7079 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 7080
2844a921
DL		 7081 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7082 pipe_name(pipe), plane, fb->width, fb->height,
7083 fb->bits_per_pixel, base, fb->pitches[0],
7084 plane_config->size);
1ad292b5 7085
2d14030b 7086 plane_config->fb = intel_fb;
1ad292b5
JB		 7087}
7088
70b23a98 7089static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7090 struct intel_crtc_state *pipe_config)
70b23a98
VS		 7091{
7092 struct drm_device *dev = crtc->base.dev;
7093 struct drm_i915_private *dev_priv = dev->dev_private;
7094 int pipe = pipe_config->cpu_transcoder;
7095 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7096 intel_clock_t clock;
7097 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
7098 int refclk = 100000;
7099
7100 mutex_lock(&dev_priv->dpio_lock);
7101 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7102 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7103 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7104 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7105 mutex_unlock(&dev_priv->dpio_lock);
7106
7107 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7108 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
7109 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7110 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7111 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7112
7113 chv_clock(refclk, &clock);
7114
7115 /* clock.dot is the fast clock */
7116 pipe_config->port_clock = clock.dot / 5;
7117}
7118
0e8ffe1b 7119static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 7120 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 7121{
7122 struct drm_device *dev = crtc->base.dev;
7123 struct drm_i915_private *dev_priv = dev->dev_private;
7124 uint32_t tmp;
7125
f458ebbc
DV		 7126 if (!intel_display_power_is_enabled(dev_priv,
7127 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 7128 return false;
7129
e143a21c 7130 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 7131 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 7132
0e8ffe1b
DV		 7133 tmp = I915_READ(PIPECONF(crtc->pipe));
7134 if (!(tmp & PIPECONF_ENABLE))
7135 return false;
7136
42571aef
VS		 7137 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7138 switch (tmp & PIPECONF_BPC_MASK) {
7139 case PIPECONF_6BPC:
7140 pipe_config->pipe_bpp = 18;
7141 break;
7142 case PIPECONF_8BPC:
7143 pipe_config->pipe_bpp = 24;
7144 break;
7145 case PIPECONF_10BPC:
7146 pipe_config->pipe_bpp = 30;
7147 break;
7148 default:
7149 break;
7150 }
7151 }
7152
b5a9fa09
DV		 7153 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
7154 pipe_config->limited_color_range = true;
7155
282740f7
VS		 7156 if (INTEL_INFO(dev)->gen < 4)
7157 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7158
1bd1bd80
DV		 7159 intel_get_pipe_timings(crtc, pipe_config);
7160
2fa2fe9a
DV		 7161 i9xx_get_pfit_config(crtc, pipe_config);
7162
6c49f241
DV		 7163 if (INTEL_INFO(dev)->gen >= 4) {
7164 tmp = I915_READ(DPLL_MD(crtc->pipe));
7165 pipe_config->pixel_multiplier =
7166 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7167 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 7168 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 7169 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7170 tmp = I915_READ(DPLL(crtc->pipe));
7171 pipe_config->pixel_multiplier =
7172 ((tmp & SDVO_MULTIPLIER_MASK)
7173 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7174 } else {
7175 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7176 * port and will be fixed up in the encoder->get_config
7177 * function. */
7178 pipe_config->pixel_multiplier = 1;
7179 }
8bcc2795
DV		 7180 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7181 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 7182 /*
7183 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7184 * on 830. Filter it out here so that we don't
7185 * report errors due to that.
7186 */
7187 if (IS_I830(dev))
7188 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7189
8bcc2795
DV		 7190 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7191 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 7192 } else {
7193 /* Mask out read-only status bits. */
7194 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7195 DPLL_PORTC_READY_MASK |
7196 DPLL_PORTB_READY_MASK);
8bcc2795 7197 }
6c49f241 7198
70b23a98
VS		 7199 if (IS_CHERRYVIEW(dev))
7200 chv_crtc_clock_get(crtc, pipe_config);
7201 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 7202 vlv_crtc_clock_get(crtc, pipe_config);
7203 else
7204 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 7205
0e8ffe1b
DV		 7206 return true;
7207}
7208
dde86e2d 7209static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 7210{
7211 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 7212 struct intel_encoder *encoder;
74cfd7ac 7213 u32 val, final;
13d83a67 7214 bool has_lvds = false;
199e5d79 7215 bool has_cpu_edp = false;
199e5d79 7216 bool has_panel = false;
99eb6a01
KP		 7217 bool has_ck505 = false;
7218 bool can_ssc = false;
13d83a67
JB		 7219
7220 /* We need to take the global config into account */
b2784e15 7221 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 7222 switch (encoder->type) {
7223 case INTEL_OUTPUT_LVDS:
7224 has_panel = true;
7225 has_lvds = true;
7226 break;
7227 case INTEL_OUTPUT_EDP:
7228 has_panel = true;
2de6905f 7229 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 7230 has_cpu_edp = true;
7231 break;
6847d71b
PZ		 7232 default:
7233 break;
13d83a67
JB		 7234 }
7235 }
7236
99eb6a01 7237 if (HAS_PCH_IBX(dev)) {
41aa3448 7238 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 7239 can_ssc = has_ck505;
7240 } else {
7241 has_ck505 = false;
7242 can_ssc = true;
7243 }
7244
2de6905f
ID		 7245 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7246 has_panel, has_lvds, has_ck505);
13d83a67
JB		 7247
7248 /* Ironlake: try to setup display ref clock before DPLL
7249 * enabling. This is only under driver's control after
7250 * PCH B stepping, previous chipset stepping should be
7251 * ignoring this setting.
7252 */
74cfd7ac
CW		 7253 val = I915_READ(PCH_DREF_CONTROL);
7254
7255 /* As we must carefully and slowly disable/enable each source in turn,
7256 * compute the final state we want first and check if we need to
7257 * make any changes at all.
7258 */
7259 final = val;
7260 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7261 if (has_ck505)
7262 final |= DREF_NONSPREAD_CK505_ENABLE;
7263 else
7264 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7265
7266 final &= ~DREF_SSC_SOURCE_MASK;
7267 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7268 final &= ~DREF_SSC1_ENABLE;
7269
7270 if (has_panel) {
7271 final |= DREF_SSC_SOURCE_ENABLE;
7272
7273 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7274 final |= DREF_SSC1_ENABLE;
7275
7276 if (has_cpu_edp) {
7277 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7278 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7279 else
7280 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7281 } else
7282 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7283 } else {
7284 final |= DREF_SSC_SOURCE_DISABLE;
7285 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7286 }
7287
7288 if (final == val)
7289 return;
7290
13d83a67 7291 /* Always enable nonspread source */
74cfd7ac 7292 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 7293
99eb6a01 7294 if (has_ck505)
74cfd7ac 7295 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 7296 else
74cfd7ac 7297 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 7298
199e5d79 7299 if (has_panel) {
74cfd7ac
CW		 7300 val &= ~DREF_SSC_SOURCE_MASK;
7301 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 7302
199e5d79 7303 /* SSC must be turned on before enabling the CPU output */
99eb6a01 7304 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 7305 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 7306 val |= DREF_SSC1_ENABLE;
e77166b5 7307 } else
74cfd7ac 7308 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 7309
7310 /* Get SSC going before enabling the outputs */
74cfd7ac 7311 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7312 POSTING_READ(PCH_DREF_CONTROL);
7313 udelay(200);
7314
74cfd7ac 7315 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 7316
7317 /* Enable CPU source on CPU attached eDP */
199e5d79 7318 if (has_cpu_edp) {
99eb6a01 7319 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 7320 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 7321 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 7322 } else
74cfd7ac 7323 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 7324 } else
74cfd7ac 7325 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 7326
74cfd7ac 7327 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7328 POSTING_READ(PCH_DREF_CONTROL);
7329 udelay(200);
7330 } else {
7331 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7332
74cfd7ac 7333 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 7334
7335 /* Turn off CPU output */
74cfd7ac 7336 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 7337
74cfd7ac 7338 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7339 POSTING_READ(PCH_DREF_CONTROL);
7340 udelay(200);
7341
7342 /* Turn off the SSC source */
74cfd7ac
CW		 7343 val &= ~DREF_SSC_SOURCE_MASK;
7344 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 7345
7346 /* Turn off SSC1 */
74cfd7ac 7347 val &= ~DREF_SSC1_ENABLE;
199e5d79 7348
74cfd7ac 7349 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 7350 POSTING_READ(PCH_DREF_CONTROL);
7351 udelay(200);
7352 }
74cfd7ac
CW		 7353
7354 BUG_ON(val != final);
13d83a67
JB		 7355}
7356
f31f2d55 7357static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 7358{
f31f2d55 7359 uint32_t tmp;
dde86e2d 7360
0ff066a9
PZ		 7361 tmp = I915_READ(SOUTH_CHICKEN2);
7362 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7363 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 7364
0ff066a9
PZ		 7365 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7366 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7367 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 7368
0ff066a9
PZ		 7369 tmp = I915_READ(SOUTH_CHICKEN2);
7370 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7371 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 7372
0ff066a9
PZ		 7373 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7374 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7375 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 7376}
7377
7378/* WaMPhyProgramming:hsw */
7379static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7380{
7381 uint32_t tmp;
dde86e2d
PZ		 7382
7383 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7384 tmp &= ~(0xFF << 24);
7385 tmp |= (0x12 << 24);
7386 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7387
dde86e2d
PZ		 7388 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7389 tmp |= (1 << 11);
7390 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7391
7392 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7393 tmp |= (1 << 11);
7394 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7395
dde86e2d
PZ		 7396 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7397 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7398 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7399
7400 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7401 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7402 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7403
0ff066a9
PZ		 7404 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7405 tmp &= ~(7 << 13);
7406 tmp |= (5 << 13);
7407 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 7408
0ff066a9
PZ		 7409 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7410 tmp &= ~(7 << 13);
7411 tmp |= (5 << 13);
7412 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 7413
7414 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7415 tmp &= ~0xFF;
7416 tmp |= 0x1C;
7417 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7418
7419 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7420 tmp &= ~0xFF;
7421 tmp |= 0x1C;
7422 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7423
7424 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7425 tmp &= ~(0xFF << 16);
7426 tmp |= (0x1C << 16);
7427 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7428
7429 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7430 tmp &= ~(0xFF << 16);
7431 tmp |= (0x1C << 16);
7432 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7433
0ff066a9
PZ		 7434 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7435 tmp |= (1 << 27);
7436 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 7437
0ff066a9
PZ		 7438 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7439 tmp |= (1 << 27);
7440 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 7441
0ff066a9
PZ		 7442 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7443 tmp &= ~(0xF << 28);
7444 tmp |= (4 << 28);
7445 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 7446
0ff066a9
PZ		 7447 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7448 tmp &= ~(0xF << 28);
7449 tmp |= (4 << 28);
7450 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 7451}
7452
2fa86a1f
PZ		 7453/* Implements 3 different sequences from BSpec chapter "Display iCLK
7454 * Programming" based on the parameters passed:
7455 * - Sequence to enable CLKOUT_DP
7456 * - Sequence to enable CLKOUT_DP without spread
7457 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7458 */
7459static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7460 bool with_fdi)
f31f2d55
PZ		 7461{
7462 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 7463 uint32_t reg, tmp;
7464
7465 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7466 with_spread = true;
7467 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7468 with_fdi, "LP PCH doesn't have FDI\n"))
7469 with_fdi = false;
f31f2d55
PZ		 7470
7471 mutex_lock(&dev_priv->dpio_lock);
7472
7473 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7474 tmp &= ~SBI_SSCCTL_DISABLE;
7475 tmp |= SBI_SSCCTL_PATHALT;
7476 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7477
7478 udelay(24);
7479
2fa86a1f
PZ		 7480 if (with_spread) {
7481 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7482 tmp &= ~SBI_SSCCTL_PATHALT;
7483 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 7484
2fa86a1f
PZ		 7485 if (with_fdi) {
7486 lpt_reset_fdi_mphy(dev_priv);
7487 lpt_program_fdi_mphy(dev_priv);
7488 }
7489 }
dde86e2d 7490
2fa86a1f
PZ		 7491 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7492 SBI_GEN0 : SBI_DBUFF0;
7493 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7494 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7495 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 7496
7497 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 7498}
7499
47701c3b
PZ		 7500/* Sequence to disable CLKOUT_DP */
7501static void lpt_disable_clkout_dp(struct drm_device *dev)
7502{
7503 struct drm_i915_private *dev_priv = dev->dev_private;
7504 uint32_t reg, tmp;
7505
7506 mutex_lock(&dev_priv->dpio_lock);
7507
7508 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7509 SBI_GEN0 : SBI_DBUFF0;
7510 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7511 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7512 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7513
7514 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7515 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7516 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7517 tmp |= SBI_SSCCTL_PATHALT;
7518 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7519 udelay(32);
7520 }
7521 tmp |= SBI_SSCCTL_DISABLE;
7522 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7523 }
7524
7525 mutex_unlock(&dev_priv->dpio_lock);
7526}
7527
bf8fa3d3
PZ		 7528static void lpt_init_pch_refclk(struct drm_device *dev)
7529{
bf8fa3d3
PZ		 7530 struct intel_encoder *encoder;
7531 bool has_vga = false;
7532
b2784e15 7533 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 7534 switch (encoder->type) {
7535 case INTEL_OUTPUT_ANALOG:
7536 has_vga = true;
7537 break;
6847d71b
PZ		 7538 default:
7539 break;
bf8fa3d3
PZ		 7540 }
7541 }
7542
47701c3b
PZ		 7543 if (has_vga)
7544 lpt_enable_clkout_dp(dev, true, true);
7545 else
7546 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 7547}
7548
dde86e2d
PZ		 7549/*
7550 * Initialize reference clocks when the driver loads
7551 */
7552void intel_init_pch_refclk(struct drm_device *dev)
7553{
7554 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7555 ironlake_init_pch_refclk(dev);
7556 else if (HAS_PCH_LPT(dev))
7557 lpt_init_pch_refclk(dev);
7558}
7559
55bb9992 7560static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 7561{
55bb9992 7562 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 7563 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992
ACO		 7564 struct drm_atomic_state *state = crtc_state->base.state;
7565 struct drm_connector_state *connector_state;
d9d444cb 7566 struct intel_encoder *encoder;
55bb9992 7567 int num_connectors = 0, i;
d9d444cb
JB		 7568 bool is_lvds = false;
7569
55bb9992
ACO		 7570 for (i = 0; i < state->num_connector; i++) {
7571 if (!state->connectors[i])
d0737e1d
ACO		 7572 continue;
7573
55bb9992
ACO		 7574 connector_state = state->connector_states[i];
7575 if (connector_state->crtc != crtc_state->base.crtc)
7576 continue;
7577
7578 encoder = to_intel_encoder(connector_state->best_encoder);
7579
d9d444cb
JB		 7580 switch (encoder->type) {
7581 case INTEL_OUTPUT_LVDS:
7582 is_lvds = true;
7583 break;
6847d71b
PZ		 7584 default:
7585 break;
d9d444cb
JB		 7586 }
7587 num_connectors++;
7588 }
7589
7590 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 7591 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 7592 dev_priv->vbt.lvds_ssc_freq);
e91e941b 7593 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 7594 }
7595
7596 return 120000;
7597}
7598
6ff93609 7599static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 7600{
c8203565 7601 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 7602 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7603 int pipe = intel_crtc->pipe;
c8203565
PZ		 7604 uint32_t val;
7605
78114071 7606 val = 0;
c8203565 7607
6e3c9717 7608 switch (intel_crtc->config->pipe_bpp) {
c8203565 7609 case 18:
dfd07d72 7610 val |= PIPECONF_6BPC;
c8203565
PZ		 7611 break;
7612 case 24:
dfd07d72 7613 val |= PIPECONF_8BPC;
c8203565
PZ		 7614 break;
7615 case 30:
dfd07d72 7616 val |= PIPECONF_10BPC;
c8203565
PZ		 7617 break;
7618 case 36:
dfd07d72 7619 val |= PIPECONF_12BPC;
c8203565
PZ		 7620 break;
7621 default:
cc769b62
PZ		 7622 /* Case prevented by intel_choose_pipe_bpp_dither. */
7623 BUG();
c8203565
PZ		 7624 }
7625
6e3c9717 7626 if (intel_crtc->config->dither)
c8203565
PZ		 7627 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7628
6e3c9717 7629 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 7630 val |= PIPECONF_INTERLACED_ILK;
7631 else
7632 val |= PIPECONF_PROGRESSIVE;
7633
6e3c9717 7634 if (intel_crtc->config->limited_color_range)
3685a8f3 7635 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 7636
c8203565
PZ		 7637 I915_WRITE(PIPECONF(pipe), val);
7638 POSTING_READ(PIPECONF(pipe));
7639}
7640
86d3efce
VS		 7641/*
7642 * Set up the pipe CSC unit.
7643 *
7644 * Currently only full range RGB to limited range RGB conversion
7645 * is supported, but eventually this should handle various
7646 * RGB<->YCbCr scenarios as well.
7647 */
50f3b016 7648static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 7649{
7650 struct drm_device *dev = crtc->dev;
7651 struct drm_i915_private *dev_priv = dev->dev_private;
7652 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7653 int pipe = intel_crtc->pipe;
7654 uint16_t coeff = 0x7800; /* 1.0 */
7655
7656 /*
7657 * TODO: Check what kind of values actually come out of the pipe
7658 * with these coeff/postoff values and adjust to get the best
7659 * accuracy. Perhaps we even need to take the bpc value into
7660 * consideration.
7661 */
7662
6e3c9717 7663 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 7664 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7665
7666 /*
7667 * GY/GU and RY/RU should be the other way around according
7668 * to BSpec, but reality doesn't agree. Just set them up in
7669 * a way that results in the correct picture.
7670 */
7671 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7672 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7673
7674 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7675 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7676
7677 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7678 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7679
7680 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7681 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7682 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7683
7684 if (INTEL_INFO(dev)->gen > 6) {
7685 uint16_t postoff = 0;
7686
6e3c9717 7687 if (intel_crtc->config->limited_color_range)
32cf0cb0 7688 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 7689
7690 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7691 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7692 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7693
7694 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7695 } else {
7696 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7697
6e3c9717 7698 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 7699 mode |= CSC_BLACK_SCREEN_OFFSET;
7700
7701 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7702 }
7703}
7704
6ff93609 7705static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 7706{
756f85cf
PZ		 7707 struct drm_device *dev = crtc->dev;
7708 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 7709 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 7710 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7711 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 7712 uint32_t val;
7713
3eff4faa 7714 val = 0;
ee2b0b38 7715
6e3c9717 7716 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 7717 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7718
6e3c9717 7719 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 7720 val |= PIPECONF_INTERLACED_ILK;
7721 else
7722 val |= PIPECONF_PROGRESSIVE;
7723
702e7a56
PZ		 7724 I915_WRITE(PIPECONF(cpu_transcoder), val);
7725 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 7726
7727 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7728 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 7729
3cdf122c 7730 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 7731 val = 0;
7732
6e3c9717 7733 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 7734 case 18:
7735 val |= PIPEMISC_DITHER_6_BPC;
7736 break;
7737 case 24:
7738 val |= PIPEMISC_DITHER_8_BPC;
7739 break;
7740 case 30:
7741 val |= PIPEMISC_DITHER_10_BPC;
7742 break;
7743 case 36:
7744 val |= PIPEMISC_DITHER_12_BPC;
7745 break;
7746 default:
7747 /* Case prevented by pipe_config_set_bpp. */
7748 BUG();
7749 }
7750
6e3c9717 7751 if (intel_crtc->config->dither)
756f85cf
PZ		 7752 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7753
7754 I915_WRITE(PIPEMISC(pipe), val);
7755 }
ee2b0b38
PZ		 7756}
7757
6591c6e4 7758static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 7759 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 7760 intel_clock_t *clock,
7761 bool *has_reduced_clock,
7762 intel_clock_t *reduced_clock)
7763{
7764 struct drm_device *dev = crtc->dev;
7765 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 7766 int refclk;
d4906093 7767 const intel_limit_t *limit;
a16af721 7768 bool ret, is_lvds = false;
79e53945 7769
a93e255f 7770 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
79e53945 7771
55bb9992 7772 refclk = ironlake_get_refclk(crtc_state);
79e53945 7773
d4906093
ML		 7774 /*
7775 * Returns a set of divisors for the desired target clock with the given
7776 * refclk, or FALSE. The returned values represent the clock equation:
7777 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7778 */
a93e255f
ACO		 7779 limit = intel_limit(crtc_state, refclk);
7780 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7781 crtc_state->port_clock,
ee9300bb 7782 refclk, NULL, clock);
6591c6e4
PZ		 7783 if (!ret)
7784 return false;
cda4b7d3 7785
ddc9003c 7786 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 7787 /*
7788 * Ensure we match the reduced clock's P to the target clock.
7789 * If the clocks don't match, we can't switch the display clock
7790 * by using the FP0/FP1. In such case we will disable the LVDS
7791 * downclock feature.
7792 */
ee9300bb 7793 *has_reduced_clock =
a93e255f 7794 dev_priv->display.find_dpll(limit, crtc_state,
ee9300bb
DV		 7795 dev_priv->lvds_downclock,
7796 refclk, clock,
7797 reduced_clock);
652c393a 7798 }
61e9653f 7799
6591c6e4
PZ		 7800 return true;
7801}
7802
d4b1931c
PZ		 7803int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7804{
7805 /*
7806 * Account for spread spectrum to avoid
7807 * oversubscribing the link. Max center spread
7808 * is 2.5%; use 5% for safety's sake.
7809 */
7810 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 7811 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 7812}
7813
7429e9d4 7814static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 7815{
7429e9d4 7816 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 7817}
7818
de13a2e3 7819static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 7820 struct intel_crtc_state *crtc_state,
7429e9d4 7821 u32 *fp,
9a7c7890 7822 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 7823{
de13a2e3 7824 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 7825 struct drm_device *dev = crtc->dev;
7826 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992
ACO		 7827 struct drm_atomic_state *state = crtc_state->base.state;
7828 struct drm_connector_state *connector_state;
7829 struct intel_encoder *encoder;
de13a2e3 7830 uint32_t dpll;
55bb9992 7831 int factor, num_connectors = 0, i;
09ede541 7832 bool is_lvds = false, is_sdvo = false;
79e53945 7833
55bb9992
ACO		 7834 for (i = 0; i < state->num_connector; i++) {
7835 if (!state->connectors[i])
d0737e1d
ACO		 7836 continue;
7837
55bb9992
ACO		 7838 connector_state = state->connector_states[i];
7839 if (connector_state->crtc != crtc_state->base.crtc)
7840 continue;
7841
7842 encoder = to_intel_encoder(connector_state->best_encoder);
7843
7844 switch (encoder->type) {
79e53945
JB		 7845 case INTEL_OUTPUT_LVDS:
7846 is_lvds = true;
7847 break;
7848 case INTEL_OUTPUT_SDVO:
7d57382e 7849 case INTEL_OUTPUT_HDMI:
79e53945 7850 is_sdvo = true;
79e53945 7851 break;
6847d71b
PZ		 7852 default:
7853 break;
79e53945 7854 }
43565a06 7855
c751ce4f 7856 num_connectors++;
79e53945 7857 }
79e53945 7858
c1858123 7859 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 7860 factor = 21;
7861 if (is_lvds) {
7862 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 7863 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 7864 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 7865 factor = 25;
190f68c5 7866 } else if (crtc_state->sdvo_tv_clock)
8febb297 7867 factor = 20;
c1858123 7868
190f68c5 7869 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 7870 *fp |= FP_CB_TUNE;
2c07245f 7871
9a7c7890
DV		 7872 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7873 *fp2 |= FP_CB_TUNE;
7874
5eddb70b 7875 dpll = 0;
2c07245f 7876
a07d6787
EA		 7877 if (is_lvds)
7878 dpll |= DPLLB_MODE_LVDS;
7879 else
7880 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 7881
190f68c5 7882 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 7883 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 7884
7885 if (is_sdvo)
4a33e48d 7886 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 7887 if (crtc_state->has_dp_encoder)
4a33e48d 7888 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 7889
a07d6787 7890 /* compute bitmask from p1 value */
190f68c5 7891 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 7892 /* also FPA1 */
190f68c5 7893 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 7894
190f68c5 7895 switch (crtc_state->dpll.p2) {
a07d6787
EA		 7896 case 5:
7897 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7898 break;
7899 case 7:
7900 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7901 break;
7902 case 10:
7903 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7904 break;
7905 case 14:
7906 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7907 break;
79e53945
JB		 7908 }
7909
b4c09f3b 7910 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 7911 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 7912 else
7913 dpll |= PLL_REF_INPUT_DREFCLK;
7914
959e16d6 7915 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 7916}
7917
190f68c5
ACO		 7918static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
7919 struct intel_crtc_state *crtc_state)
de13a2e3 7920{
c7653199 7921 struct drm_device *dev = crtc->base.dev;
de13a2e3 7922 intel_clock_t clock, reduced_clock;
cbbab5bd 7923 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 7924 bool ok, has_reduced_clock = false;
8b47047b 7925 bool is_lvds = false;
e2b78267 7926 struct intel_shared_dpll *pll;
de13a2e3 7927
409ee761 7928 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 7929
5dc5298b
PZ		 7930 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7931 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 7932
190f68c5 7933 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 7934 &has_reduced_clock, &reduced_clock);
190f68c5 7935 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 7936 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7937 return -EINVAL;
79e53945 7938 }
f47709a9 7939 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7940 if (!crtc_state->clock_set) {
7941 crtc_state->dpll.n = clock.n;
7942 crtc_state->dpll.m1 = clock.m1;
7943 crtc_state->dpll.m2 = clock.m2;
7944 crtc_state->dpll.p1 = clock.p1;
7945 crtc_state->dpll.p2 = clock.p2;
f47709a9 7946 }
79e53945 7947
5dc5298b 7948 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 7949 if (crtc_state->has_pch_encoder) {
7950 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 7951 if (has_reduced_clock)
7429e9d4 7952 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 7953
190f68c5 7954 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 7955 &fp, &reduced_clock,
7956 has_reduced_clock ? &fp2 : NULL);
7957
190f68c5
ACO		 7958 crtc_state->dpll_hw_state.dpll = dpll;
7959 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 7960 if (has_reduced_clock)
190f68c5 7961 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 7962 else
190f68c5 7963 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 7964
190f68c5 7965 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 7966 if (pll == NULL) {
84f44ce7 7967 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 7968 pipe_name(crtc->pipe));
4b645f14
JB		 7969 return -EINVAL;
7970 }
3fb37703 7971 }
79e53945 7972
ab585dea 7973 if (is_lvds && has_reduced_clock)
c7653199 7974 crtc->lowfreq_avail = true;
bcd644e0 7975 else
c7653199 7976 crtc->lowfreq_avail = false;
e2b78267 7977
c8f7a0db 7978 return 0;
79e53945
JB		 7979}
7980
eb14cb74
VS		 7981static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7982 struct intel_link_m_n *m_n)
7983{
7984 struct drm_device *dev = crtc->base.dev;
7985 struct drm_i915_private *dev_priv = dev->dev_private;
7986 enum pipe pipe = crtc->pipe;
7987
7988 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7989 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7990 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7991 & ~TU_SIZE_MASK;
7992 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7993 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7994 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7995}
7996
7997static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7998 enum transcoder transcoder,
b95af8be
VK		 7999 struct intel_link_m_n *m_n,
8000 struct intel_link_m_n *m2_n2)
72419203
DV		 8001{
8002 struct drm_device *dev = crtc->base.dev;
8003 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 8004 enum pipe pipe = crtc->pipe;
72419203 8005
eb14cb74
VS		 8006 if (INTEL_INFO(dev)->gen >= 5) {
8007 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8008 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8009 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8010 & ~TU_SIZE_MASK;
8011 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8012 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8013 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 8014 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8015 * gen < 8) and if DRRS is supported (to make sure the
8016 * registers are not unnecessarily read).
8017 */
8018 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 8019 crtc->config->has_drrs) {
b95af8be
VK		 8020 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8021 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8022 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8023 & ~TU_SIZE_MASK;
8024 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8025 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8026 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8027 }
eb14cb74
VS		 8028 } else {
8029 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8030 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8031 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8032 & ~TU_SIZE_MASK;
8033 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8034 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8035 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8036 }
8037}
8038
8039void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 8040 struct intel_crtc_state *pipe_config)
eb14cb74 8041{
681a8504 8042 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 8043 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8044 else
8045 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 8046 &pipe_config->dp_m_n,
8047 &pipe_config->dp_m2_n2);
eb14cb74 8048}
72419203 8049
eb14cb74 8050static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 8051 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 8052{
8053 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 8054 &pipe_config->fdi_m_n, NULL);
72419203
DV		 8055}
8056
bd2e244f 8057static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8058 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 8059{
8060 struct drm_device *dev = crtc->base.dev;
8061 struct drm_i915_private *dev_priv = dev->dev_private;
8062 uint32_t tmp;
8063
8064 tmp = I915_READ(PS_CTL(crtc->pipe));
8065
8066 if (tmp & PS_ENABLE) {
8067 pipe_config->pch_pfit.enabled = true;
8068 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
8069 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
8070 }
8071}
8072
5724dbd1
DL		 8073static void
8074skylake_get_initial_plane_config(struct intel_crtc *crtc,
8075 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 8076{
8077 struct drm_device *dev = crtc->base.dev;
8078 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 8079 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 8080 int pipe = crtc->pipe;
8081 int fourcc, pixel_format;
6761dd31 8082 unsigned int aligned_height;
bc8d7dff 8083 struct drm_framebuffer *fb;
1b842c89 8084 struct intel_framebuffer *intel_fb;
bc8d7dff 8085
d9806c9f 8086 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8087 if (!intel_fb) {
bc8d7dff
DL		 8088 DRM_DEBUG_KMS("failed to alloc fb\n");
8089 return;
8090 }
8091
1b842c89
DL		 8092 fb = &intel_fb->base;
8093
bc8d7dff 8094 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 8095 if (!(val & PLANE_CTL_ENABLE))
8096 goto error;
8097
bc8d7dff
DL		 8098 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8099 fourcc = skl_format_to_fourcc(pixel_format,
8100 val & PLANE_CTL_ORDER_RGBX,
8101 val & PLANE_CTL_ALPHA_MASK);
8102 fb->pixel_format = fourcc;
8103 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8104
40f46283
DL		 8105 tiling = val & PLANE_CTL_TILED_MASK;
8106 switch (tiling) {
8107 case PLANE_CTL_TILED_LINEAR:
8108 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
8109 break;
8110 case PLANE_CTL_TILED_X:
8111 plane_config->tiling = I915_TILING_X;
8112 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8113 break;
8114 case PLANE_CTL_TILED_Y:
8115 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
8116 break;
8117 case PLANE_CTL_TILED_YF:
8118 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
8119 break;
8120 default:
8121 MISSING_CASE(tiling);
8122 goto error;
8123 }
8124
bc8d7dff
DL		 8125 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8126 plane_config->base = base;
8127
8128 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8129
8130 val = I915_READ(PLANE_SIZE(pipe, 0));
8131 fb->height = ((val >> 16) & 0xfff) + 1;
8132 fb->width = ((val >> 0) & 0x1fff) + 1;
8133
8134 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 8135 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
8136 fb->pixel_format);
bc8d7dff
DL		 8137 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8138
8139 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8140 fb->pixel_format,
8141 fb->modifier[0]);
bc8d7dff 8142
f37b5c2b 8143 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 8144
8145 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8146 pipe_name(pipe), fb->width, fb->height,
8147 fb->bits_per_pixel, base, fb->pitches[0],
8148 plane_config->size);
8149
2d14030b 8150 plane_config->fb = intel_fb;
bc8d7dff
DL		 8151 return;
8152
8153error:
8154 kfree(fb);
8155}
8156
2fa2fe9a 8157static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8158 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 8159{
8160 struct drm_device *dev = crtc->base.dev;
8161 struct drm_i915_private *dev_priv = dev->dev_private;
8162 uint32_t tmp;
8163
8164 tmp = I915_READ(PF_CTL(crtc->pipe));
8165
8166 if (tmp & PF_ENABLE) {
fd4daa9c 8167 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 8168 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8169 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 8170
8171 /* We currently do not free assignements of panel fitters on
8172 * ivb/hsw (since we don't use the higher upscaling modes which
8173 * differentiates them) so just WARN about this case for now. */
8174 if (IS_GEN7(dev)) {
8175 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8176 PF_PIPE_SEL_IVB(crtc->pipe));
8177 }
2fa2fe9a 8178 }
79e53945
JB		 8179}
8180
5724dbd1
DL		 8181static void
8182ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8183 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 8184{
8185 struct drm_device *dev = crtc->base.dev;
8186 struct drm_i915_private *dev_priv = dev->dev_private;
8187 u32 val, base, offset;
aeee5a49 8188 int pipe = crtc->pipe;
4c6baa59 8189 int fourcc, pixel_format;
6761dd31 8190 unsigned int aligned_height;
b113d5ee 8191 struct drm_framebuffer *fb;
1b842c89 8192 struct intel_framebuffer *intel_fb;
4c6baa59 8193
42a7b088
DL		 8194 val = I915_READ(DSPCNTR(pipe));
8195 if (!(val & DISPLAY_PLANE_ENABLE))
8196 return;
8197
d9806c9f 8198 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8199 if (!intel_fb) {
4c6baa59
JB		 8200 DRM_DEBUG_KMS("failed to alloc fb\n");
8201 return;
8202 }
8203
1b842c89
DL		 8204 fb = &intel_fb->base;
8205
18c5247e
DV		 8206 if (INTEL_INFO(dev)->gen >= 4) {
8207 if (val & DISPPLANE_TILED) {
49af449b 8208 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 8209 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8210 }
8211 }
4c6baa59
JB		 8212
8213 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 8214 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 8215 fb->pixel_format = fourcc;
8216 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 8217
aeee5a49 8218 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 8219 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 8220 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 8221 } else {
49af449b 8222 if (plane_config->tiling)
aeee5a49 8223 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 8224 else
aeee5a49 8225 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 8226 }
8227 plane_config->base = base;
8228
8229 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 8230 fb->width = ((val >> 16) & 0xfff) + 1;
8231 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 8232
8233 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 8234 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 8235
b113d5ee 8236 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8237 fb->pixel_format,
8238 fb->modifier[0]);
4c6baa59 8239
f37b5c2b 8240 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 8241
2844a921
DL		 8242 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8243 pipe_name(pipe), fb->width, fb->height,
8244 fb->bits_per_pixel, base, fb->pitches[0],
8245 plane_config->size);
b113d5ee 8246
2d14030b 8247 plane_config->fb = intel_fb;
4c6baa59
JB		 8248}
8249
0e8ffe1b 8250static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8251 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8252{
8253 struct drm_device *dev = crtc->base.dev;
8254 struct drm_i915_private *dev_priv = dev->dev_private;
8255 uint32_t tmp;
8256
f458ebbc
DV		 8257 if (!intel_display_power_is_enabled(dev_priv,
8258 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 8259 return false;
8260
e143a21c 8261 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8262 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8263
0e8ffe1b
DV		 8264 tmp = I915_READ(PIPECONF(crtc->pipe));
8265 if (!(tmp & PIPECONF_ENABLE))
8266 return false;
8267
42571aef
VS		 8268 switch (tmp & PIPECONF_BPC_MASK) {
8269 case PIPECONF_6BPC:
8270 pipe_config->pipe_bpp = 18;
8271 break;
8272 case PIPECONF_8BPC:
8273 pipe_config->pipe_bpp = 24;
8274 break;
8275 case PIPECONF_10BPC:
8276 pipe_config->pipe_bpp = 30;
8277 break;
8278 case PIPECONF_12BPC:
8279 pipe_config->pipe_bpp = 36;
8280 break;
8281 default:
8282 break;
8283 }
8284
b5a9fa09
DV		 8285 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8286 pipe_config->limited_color_range = true;
8287
ab9412ba 8288 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 8289 struct intel_shared_dpll *pll;
8290
88adfff1
DV		 8291 pipe_config->has_pch_encoder = true;
8292
627eb5a3
DV		 8293 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8294 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8295 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 8296
8297 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 8298
c0d43d62 8299 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 8300 pipe_config->shared_dpll =
8301 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 8302 } else {
8303 tmp = I915_READ(PCH_DPLL_SEL);
8304 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8305 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8306 else
8307 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8308 }
66e985c0
DV		 8309
8310 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8311
8312 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8313 &pipe_config->dpll_hw_state));
c93f54cf
DV		 8314
8315 tmp = pipe_config->dpll_hw_state.dpll;
8316 pipe_config->pixel_multiplier =
8317 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8318 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 8319
8320 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 8321 } else {
8322 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 8323 }
8324
1bd1bd80
DV		 8325 intel_get_pipe_timings(crtc, pipe_config);
8326
2fa2fe9a
DV		 8327 ironlake_get_pfit_config(crtc, pipe_config);
8328
0e8ffe1b
DV		 8329 return true;
8330}
8331
be256dc7
PZ		 8332static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8333{
8334 struct drm_device *dev = dev_priv->dev;
be256dc7 8335 struct intel_crtc *crtc;
be256dc7 8336
d3fcc808 8337 for_each_intel_crtc(dev, crtc)
e2c719b7 8338 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 8339 pipe_name(crtc->pipe));
8340
e2c719b7
RC		 8341 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8342 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8343 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8344 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8345 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8346 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 8347 "CPU PWM1 enabled\n");
c5107b87 8348 if (IS_HASWELL(dev))
e2c719b7 8349 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 8350 "CPU PWM2 enabled\n");
e2c719b7 8351 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 8352 "PCH PWM1 enabled\n");
e2c719b7 8353 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 8354 "Utility pin enabled\n");
e2c719b7 8355 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 8356
9926ada1
PZ		 8357 /*
8358 * In theory we can still leave IRQs enabled, as long as only the HPD
8359 * interrupts remain enabled. We used to check for that, but since it's
8360 * gen-specific and since we only disable LCPLL after we fully disable
8361 * the interrupts, the check below should be enough.
8362 */
e2c719b7 8363 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 8364}
8365
9ccd5aeb
PZ		 8366static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8367{
8368 struct drm_device *dev = dev_priv->dev;
8369
8370 if (IS_HASWELL(dev))
8371 return I915_READ(D_COMP_HSW);
8372 else
8373 return I915_READ(D_COMP_BDW);
8374}
8375
3c4c9b81
PZ		 8376static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8377{
8378 struct drm_device *dev = dev_priv->dev;
8379
8380 if (IS_HASWELL(dev)) {
8381 mutex_lock(&dev_priv->rps.hw_lock);
8382 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8383 val))
f475dadf 8384 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 8385 mutex_unlock(&dev_priv->rps.hw_lock);
8386 } else {
9ccd5aeb
PZ		 8387 I915_WRITE(D_COMP_BDW, val);
8388 POSTING_READ(D_COMP_BDW);
3c4c9b81 8389 }
be256dc7
PZ		 8390}
8391
8392/*
8393 * This function implements pieces of two sequences from BSpec:
8394 * - Sequence for display software to disable LCPLL
8395 * - Sequence for display software to allow package C8+
8396 * The steps implemented here are just the steps that actually touch the LCPLL
8397 * register. Callers should take care of disabling all the display engine
8398 * functions, doing the mode unset, fixing interrupts, etc.
8399 */
6ff58d53
PZ		 8400static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8401 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 8402{
8403 uint32_t val;
8404
8405 assert_can_disable_lcpll(dev_priv);
8406
8407 val = I915_READ(LCPLL_CTL);
8408
8409 if (switch_to_fclk) {
8410 val |= LCPLL_CD_SOURCE_FCLK;
8411 I915_WRITE(LCPLL_CTL, val);
8412
8413 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
8414 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8415 DRM_ERROR("Switching to FCLK failed\n");
8416
8417 val = I915_READ(LCPLL_CTL);
8418 }
8419
8420 val |= LCPLL_PLL_DISABLE;
8421 I915_WRITE(LCPLL_CTL, val);
8422 POSTING_READ(LCPLL_CTL);
8423
8424 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
8425 DRM_ERROR("LCPLL still locked\n");
8426
9ccd5aeb 8427 val = hsw_read_dcomp(dev_priv);
be256dc7 8428 val |= D_COMP_COMP_DISABLE;
3c4c9b81 8429 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 8430 ndelay(100);
8431
9ccd5aeb
PZ		 8432 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8433 1))
be256dc7
PZ		 8434 DRM_ERROR("D_COMP RCOMP still in progress\n");
8435
8436 if (allow_power_down) {
8437 val = I915_READ(LCPLL_CTL);
8438 val |= LCPLL_POWER_DOWN_ALLOW;
8439 I915_WRITE(LCPLL_CTL, val);
8440 POSTING_READ(LCPLL_CTL);
8441 }
8442}
8443
8444/*
8445 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8446 * source.
8447 */
6ff58d53 8448static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 8449{
8450 uint32_t val;
8451
8452 val = I915_READ(LCPLL_CTL);
8453
8454 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8455 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8456 return;
8457
a8a8bd54
PZ		 8458 /*
8459 * Make sure we're not on PC8 state before disabling PC8, otherwise
8460 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 8461 */
59bad947 8462 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 8463
be256dc7
PZ		 8464 if (val & LCPLL_POWER_DOWN_ALLOW) {
8465 val &= ~LCPLL_POWER_DOWN_ALLOW;
8466 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 8467 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 8468 }
8469
9ccd5aeb 8470 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 8471 val |= D_COMP_COMP_FORCE;
8472 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 8473 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 8474
8475 val = I915_READ(LCPLL_CTL);
8476 val &= ~LCPLL_PLL_DISABLE;
8477 I915_WRITE(LCPLL_CTL, val);
8478
8479 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
8480 DRM_ERROR("LCPLL not locked yet\n");
8481
8482 if (val & LCPLL_CD_SOURCE_FCLK) {
8483 val = I915_READ(LCPLL_CTL);
8484 val &= ~LCPLL_CD_SOURCE_FCLK;
8485 I915_WRITE(LCPLL_CTL, val);
8486
8487 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
8488 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8489 DRM_ERROR("Switching back to LCPLL failed\n");
8490 }
215733fa 8491
59bad947 8492 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
be256dc7
PZ		 8493}
8494
765dab67
PZ		 8495/*
8496 * Package states C8 and deeper are really deep PC states that can only be
8497 * reached when all the devices on the system allow it, so even if the graphics
8498 * device allows PC8+, it doesn't mean the system will actually get to these
8499 * states. Our driver only allows PC8+ when going into runtime PM.
8500 *
8501 * The requirements for PC8+ are that all the outputs are disabled, the power
8502 * well is disabled and most interrupts are disabled, and these are also
8503 * requirements for runtime PM. When these conditions are met, we manually do
8504 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8505 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8506 * hang the machine.
8507 *
8508 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8509 * the state of some registers, so when we come back from PC8+ we need to
8510 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8511 * need to take care of the registers kept by RC6. Notice that this happens even
8512 * if we don't put the device in PCI D3 state (which is what currently happens
8513 * because of the runtime PM support).
8514 *
8515 * For more, read "Display Sequences for Package C8" on the hardware
8516 * documentation.
8517 */
a14cb6fc 8518void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 8519{
c67a470b
PZ		 8520 struct drm_device *dev = dev_priv->dev;
8521 uint32_t val;
8522
c67a470b
PZ		 8523 DRM_DEBUG_KMS("Enabling package C8+\n");
8524
c67a470b
PZ		 8525 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8526 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8527 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8528 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8529 }
8530
8531 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 8532 hsw_disable_lcpll(dev_priv, true, true);
8533}
8534
a14cb6fc 8535void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 8536{
8537 struct drm_device *dev = dev_priv->dev;
8538 uint32_t val;
8539
c67a470b
PZ		 8540 DRM_DEBUG_KMS("Disabling package C8+\n");
8541
8542 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 8543 lpt_init_pch_refclk(dev);
8544
8545 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8546 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8547 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8548 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8549 }
8550
8551 intel_prepare_ddi(dev);
c67a470b
PZ		 8552}
8553
190f68c5
ACO		 8554static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8555 struct intel_crtc_state *crtc_state)
09b4ddf9 8556{
190f68c5 8557 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 8558 return -EINVAL;
716c2e55 8559
c7653199 8560 crtc->lowfreq_avail = false;
644cef34 8561
c8f7a0db 8562 return 0;
79e53945
JB		 8563}
8564
96b7dfb7
S		 8565static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8566 enum port port,
5cec258b 8567 struct intel_crtc_state *pipe_config)
96b7dfb7 8568{
3148ade7 8569 u32 temp, dpll_ctl1;
96b7dfb7
S		 8570
8571 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8572 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
8573
8574 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 8575 case SKL_DPLL0:
8576 /*
8577 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8578 * of the shared DPLL framework and thus needs to be read out
8579 * separately
8580 */
8581 dpll_ctl1 = I915_READ(DPLL_CTRL1);
8582 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
8583 break;
96b7dfb7
S		 8584 case SKL_DPLL1:
8585 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8586 break;
8587 case SKL_DPLL2:
8588 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8589 break;
8590 case SKL_DPLL3:
8591 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8592 break;
96b7dfb7
S		 8593 }
8594}
8595
7d2c8175
DL		 8596static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8597 enum port port,
5cec258b 8598 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 8599{
8600 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8601
8602 switch (pipe_config->ddi_pll_sel) {
8603 case PORT_CLK_SEL_WRPLL1:
8604 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8605 break;
8606 case PORT_CLK_SEL_WRPLL2:
8607 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8608 break;
8609 }
8610}
8611
26804afd 8612static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 8613 struct intel_crtc_state *pipe_config)
26804afd
DV		 8614{
8615 struct drm_device *dev = crtc->base.dev;
8616 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 8617 struct intel_shared_dpll *pll;
26804afd
DV		 8618 enum port port;
8619 uint32_t tmp;
8620
8621 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8622
8623 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8624
96b7dfb7
S		 8625 if (IS_SKYLAKE(dev))
8626 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8627 else
8628 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 8629
d452c5b6
DV		 8630 if (pipe_config->shared_dpll >= 0) {
8631 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8632
8633 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8634 &pipe_config->dpll_hw_state));
8635 }
8636
26804afd
DV		 8637 /*
8638 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8639 * DDI E. So just check whether this pipe is wired to DDI E and whether
8640 * the PCH transcoder is on.
8641 */
ca370455
DL		 8642 if (INTEL_INFO(dev)->gen < 9 &&
8643 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 8644 pipe_config->has_pch_encoder = true;
8645
8646 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8647 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8648 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8649
8650 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8651 }
8652}
8653
0e8ffe1b 8654static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8655 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8656{
8657 struct drm_device *dev = crtc->base.dev;
8658 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 8659 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 8660 uint32_t tmp;
8661
f458ebbc 8662 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 8663 POWER_DOMAIN_PIPE(crtc->pipe)))
8664 return false;
8665
e143a21c 8666 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 8667 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8668
eccb140b
DV		 8669 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8670 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8671 enum pipe trans_edp_pipe;
8672 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8673 default:
8674 WARN(1, "unknown pipe linked to edp transcoder\n");
8675 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8676 case TRANS_DDI_EDP_INPUT_A_ON:
8677 trans_edp_pipe = PIPE_A;
8678 break;
8679 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8680 trans_edp_pipe = PIPE_B;
8681 break;
8682 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8683 trans_edp_pipe = PIPE_C;
8684 break;
8685 }
8686
8687 if (trans_edp_pipe == crtc->pipe)
8688 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8689 }
8690
f458ebbc 8691 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 8692 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 8693 return false;
8694
eccb140b 8695 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 8696 if (!(tmp & PIPECONF_ENABLE))
8697 return false;
8698
26804afd 8699 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 8700
1bd1bd80
DV		 8701 intel_get_pipe_timings(crtc, pipe_config);
8702
2fa2fe9a 8703 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
bd2e244f
JB		 8704 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8705 if (IS_SKYLAKE(dev))
8706 skylake_get_pfit_config(crtc, pipe_config);
8707 else
8708 ironlake_get_pfit_config(crtc, pipe_config);
8709 }
88adfff1 8710
e59150dc
JB		 8711 if (IS_HASWELL(dev))
8712 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8713 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 8714
ebb69c95
CT		 8715 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8716 pipe_config->pixel_multiplier =
8717 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8718 } else {
8719 pipe_config->pixel_multiplier = 1;
8720 }
6c49f241 8721
0e8ffe1b
DV		 8722 return true;
8723}
8724
560b85bb
CW		 8725static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8726{
8727 struct drm_device *dev = crtc->dev;
8728 struct drm_i915_private *dev_priv = dev->dev_private;
8729 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 8730 uint32_t cntl = 0, size = 0;
560b85bb 8731
dc41c154 8732 if (base) {
3dd512fb
MR		 8733 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
8734 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 8735 unsigned int stride = roundup_pow_of_two(width) * 4;
8736
8737 switch (stride) {
8738 default:
8739 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8740 width, stride);
8741 stride = 256;
8742 /* fallthrough */
8743 case 256:
8744 case 512:
8745 case 1024:
8746 case 2048:
8747 break;
4b0e333e
CW		 8748 }
8749
dc41c154
VS		 8750 cntl |= CURSOR_ENABLE |
8751 CURSOR_GAMMA_ENABLE |
8752 CURSOR_FORMAT_ARGB |
8753 CURSOR_STRIDE(stride);
8754
8755 size = (height << 12) | width;
4b0e333e 8756 }
560b85bb 8757
dc41c154
VS		 8758 if (intel_crtc->cursor_cntl != 0 &&
8759 (intel_crtc->cursor_base != base ||
8760 intel_crtc->cursor_size != size ||
8761 intel_crtc->cursor_cntl != cntl)) {
8762 /* On these chipsets we can only modify the base/size/stride
8763 * whilst the cursor is disabled.
8764 */
8765 I915_WRITE(_CURACNTR, 0);
4b0e333e 8766 POSTING_READ(_CURACNTR);
dc41c154 8767 intel_crtc->cursor_cntl = 0;
4b0e333e 8768 }
560b85bb 8769
99d1f387 8770 if (intel_crtc->cursor_base != base) {
9db4a9c7 8771 I915_WRITE(_CURABASE, base);
99d1f387
VS		 8772 intel_crtc->cursor_base = base;
8773 }
4726e0b0 8774
dc41c154
VS		 8775 if (intel_crtc->cursor_size != size) {
8776 I915_WRITE(CURSIZE, size);
8777 intel_crtc->cursor_size = size;
4b0e333e 8778 }
560b85bb 8779
4b0e333e 8780 if (intel_crtc->cursor_cntl != cntl) {
4b0e333e
CW		 8781 I915_WRITE(_CURACNTR, cntl);
8782 POSTING_READ(_CURACNTR);
4b0e333e 8783 intel_crtc->cursor_cntl = cntl;
560b85bb 8784 }
560b85bb
CW		 8785}
8786
560b85bb 8787static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 8788{
8789 struct drm_device *dev = crtc->dev;
8790 struct drm_i915_private *dev_priv = dev->dev_private;
8791 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8792 int pipe = intel_crtc->pipe;
4b0e333e
CW		 8793 uint32_t cntl;
8794
8795 cntl = 0;
8796 if (base) {
8797 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 8798 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 8799 case 64:
8800 cntl |= CURSOR_MODE_64_ARGB_AX;
8801 break;
8802 case 128:
8803 cntl |= CURSOR_MODE_128_ARGB_AX;
8804 break;
8805 case 256:
8806 cntl |= CURSOR_MODE_256_ARGB_AX;
8807 break;
8808 default:
3dd512fb 8809 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 8810 return;
65a21cd6 8811 }
4b0e333e 8812 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS		 8813
8814 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8815 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 8816 }
65a21cd6 8817
8e7d688b 8818 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 8819 cntl |= CURSOR_ROTATE_180;
8820
4b0e333e
CW		 8821 if (intel_crtc->cursor_cntl != cntl) {
8822 I915_WRITE(CURCNTR(pipe), cntl);
8823 POSTING_READ(CURCNTR(pipe));
8824 intel_crtc->cursor_cntl = cntl;
65a21cd6 8825 }
4b0e333e 8826
65a21cd6 8827 /* and commit changes on next vblank */
5efb3e28
VS		 8828 I915_WRITE(CURBASE(pipe), base);
8829 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 8830
8831 intel_crtc->cursor_base = base;
65a21cd6
JB		 8832}
8833
cda4b7d3 8834/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 8835static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8836 bool on)
cda4b7d3
CW		 8837{
8838 struct drm_device *dev = crtc->dev;
8839 struct drm_i915_private *dev_priv = dev->dev_private;
8840 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8841 int pipe = intel_crtc->pipe;
3d7d6510
MR		 8842 int x = crtc->cursor_x;
8843 int y = crtc->cursor_y;
d6e4db15 8844 u32 base = 0, pos = 0;
cda4b7d3 8845
d6e4db15 8846 if (on)
cda4b7d3 8847 base = intel_crtc->cursor_addr;
cda4b7d3 8848
6e3c9717 8849 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 8850 base = 0;
8851
6e3c9717 8852 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 8853 base = 0;
8854
8855 if (x < 0) {
3dd512fb 8856 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
cda4b7d3
CW		 8857 base = 0;
8858
8859 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8860 x = -x;
8861 }
8862 pos |= x << CURSOR_X_SHIFT;
8863
8864 if (y < 0) {
3dd512fb 8865 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
cda4b7d3
CW		 8866 base = 0;
8867
8868 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8869 y = -y;
8870 }
8871 pos |= y << CURSOR_Y_SHIFT;
8872
4b0e333e 8873 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 8874 return;
8875
5efb3e28
VS		 8876 I915_WRITE(CURPOS(pipe), pos);
8877
4398ad45
VS		 8878 /* ILK+ do this automagically */
8879 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 8880 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
3dd512fb
MR		 8881 base += (intel_crtc->base.cursor->state->crtc_h *
8882 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
4398ad45
VS		 8883 }
8884
8ac54669 8885 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 8886 i845_update_cursor(crtc, base);
8887 else
8888 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 8889}
8890
dc41c154
VS		 8891static bool cursor_size_ok(struct drm_device *dev,
8892 uint32_t width, uint32_t height)
8893{
8894 if (width == 0 || height == 0)
8895 return false;
8896
8897 /*
8898 * 845g/865g are special in that they are only limited by
8899 * the width of their cursors, the height is arbitrary up to
8900 * the precision of the register. Everything else requires
8901 * square cursors, limited to a few power-of-two sizes.
8902 */
8903 if (IS_845G(dev) || IS_I865G(dev)) {
8904 if ((width & 63) != 0)
8905 return false;
8906
8907 if (width > (IS_845G(dev) ? 64 : 512))
8908 return false;
8909
8910 if (height > 1023)
8911 return false;
8912 } else {
8913 switch (width | height) {
8914 case 256:
8915 case 128:
8916 if (IS_GEN2(dev))
8917 return false;
8918 case 64:
8919 break;
8920 default:
8921 return false;
8922 }
8923 }
8924
8925 return true;
8926}
8927
79e53945 8928static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 8929 u16 *blue, uint32_t start, uint32_t size)
79e53945 8930{
7203425a 8931 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 8932 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 8933
7203425a 8934 for (i = start; i < end; i++) {
79e53945
JB		 8935 intel_crtc->lut_r[i] = red[i] >> 8;
8936 intel_crtc->lut_g[i] = green[i] >> 8;
8937 intel_crtc->lut_b[i] = blue[i] >> 8;
8938 }
8939
8940 intel_crtc_load_lut(crtc);
8941}
8942
79e53945
JB		 8943/* VESA 640x480x72Hz mode to set on the pipe */
8944static struct drm_display_mode load_detect_mode = {
8945 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8946 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8947};
8948
a8bb6818
DV		 8949struct drm_framebuffer *
8950__intel_framebuffer_create(struct drm_device *dev,
8951 struct drm_mode_fb_cmd2 *mode_cmd,
8952 struct drm_i915_gem_object *obj)
d2dff872
CW		 8953{
8954 struct intel_framebuffer *intel_fb;
8955 int ret;
8956
8957 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8958 if (!intel_fb) {
6ccb81f2 8959 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 8960 return ERR_PTR(-ENOMEM);
8961 }
8962
8963 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 8964 if (ret)
8965 goto err;
d2dff872
CW		 8966
8967 return &intel_fb->base;
dd4916c5 8968err:
6ccb81f2 8969 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 8970 kfree(intel_fb);
8971
8972 return ERR_PTR(ret);
d2dff872
CW		 8973}
8974
b5ea642a 8975static struct drm_framebuffer *
a8bb6818
DV		 8976intel_framebuffer_create(struct drm_device *dev,
8977 struct drm_mode_fb_cmd2 *mode_cmd,
8978 struct drm_i915_gem_object *obj)
8979{
8980 struct drm_framebuffer *fb;
8981 int ret;
8982
8983 ret = i915_mutex_lock_interruptible(dev);
8984 if (ret)
8985 return ERR_PTR(ret);
8986 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8987 mutex_unlock(&dev->struct_mutex);
8988
8989 return fb;
8990}
8991
d2dff872
CW		 8992static u32
8993intel_framebuffer_pitch_for_width(int width, int bpp)
8994{
8995 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8996 return ALIGN(pitch, 64);
8997}
8998
8999static u32
9000intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9001{
9002 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 9003 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 9004}
9005
9006static struct drm_framebuffer *
9007intel_framebuffer_create_for_mode(struct drm_device *dev,
9008 struct drm_display_mode *mode,
9009 int depth, int bpp)
9010{
9011 struct drm_i915_gem_object *obj;
0fed39bd 9012 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 9013
9014 obj = i915_gem_alloc_object(dev,
9015 intel_framebuffer_size_for_mode(mode, bpp));
9016 if (obj == NULL)
9017 return ERR_PTR(-ENOMEM);
9018
9019 mode_cmd.width = mode->hdisplay;
9020 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 9021 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9022 bpp);
5ca0c34a 9023 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 9024
9025 return intel_framebuffer_create(dev, &mode_cmd, obj);
9026}
9027
9028static struct drm_framebuffer *
9029mode_fits_in_fbdev(struct drm_device *dev,
9030 struct drm_display_mode *mode)
9031{
4520f53a 9032#ifdef CONFIG_DRM_I915_FBDEV
d2dff872
CW		 9033 struct drm_i915_private *dev_priv = dev->dev_private;
9034 struct drm_i915_gem_object *obj;
9035 struct drm_framebuffer *fb;
9036
4c0e5528 9037 if (!dev_priv->fbdev)
d2dff872
CW		 9038 return NULL;
9039
4c0e5528 9040 if (!dev_priv->fbdev->fb)
d2dff872
CW		 9041 return NULL;
9042
4c0e5528
DV		 9043 obj = dev_priv->fbdev->fb->obj;
9044 BUG_ON(!obj);
9045
8bcd4553 9046 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 9047 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9048 fb->bits_per_pixel))
d2dff872
CW		 9049 return NULL;
9050
01f2c773 9051 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 9052 return NULL;
9053
9054 return fb;
4520f53a
DV		 9055#else
9056 return NULL;
9057#endif
d2dff872
CW		 9058}
9059
d2434ab7 9060bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 9061 struct drm_display_mode *mode,
51fd371b
RC		 9062 struct intel_load_detect_pipe *old,
9063 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 9064{
9065 struct intel_crtc *intel_crtc;
d2434ab7
DV		 9066 struct intel_encoder *intel_encoder =
9067 intel_attached_encoder(connector);
79e53945 9068 struct drm_crtc *possible_crtc;
4ef69c7a 9069 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 9070 struct drm_crtc *crtc = NULL;
9071 struct drm_device *dev = encoder->dev;
94352cf9 9072 struct drm_framebuffer *fb;
51fd371b 9073 struct drm_mode_config *config = &dev->mode_config;
83a57153 9074 struct drm_atomic_state *state = NULL;
944b0c76 9075 struct drm_connector_state *connector_state;
51fd371b 9076 int ret, i = -1;
79e53945 9077
d2dff872 9078 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 9079 connector->base.id, connector->name,
8e329a03 9080 encoder->base.id, encoder->name);
d2dff872 9081
51fd371b
RC		 9082retry:
9083 ret = drm_modeset_lock(&config->connection_mutex, ctx);
9084 if (ret)
9085 goto fail_unlock;
6e9f798d 9086
79e53945
JB		 9087 /*
9088 * Algorithm gets a little messy:
7a5e4805 9089 *
79e53945
JB		 9090 * - if the connector already has an assigned crtc, use it (but make
9091 * sure it's on first)
7a5e4805 9092 *
79e53945
JB		 9093 * - try to find the first unused crtc that can drive this connector,
9094 * and use that if we find one
79e53945
JB		 9095 */
9096
9097 /* See if we already have a CRTC for this connector */
9098 if (encoder->crtc) {
9099 crtc = encoder->crtc;
8261b191 9100
51fd371b 9101 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de
DV		 9102 if (ret)
9103 goto fail_unlock;
9104 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b
RC		 9105 if (ret)
9106 goto fail_unlock;
7b24056b 9107
24218aac 9108 old->dpms_mode = connector->dpms;
8261b191
CW		 9109 old->load_detect_temp = false;
9110
9111 /* Make sure the crtc and connector are running */
24218aac
DV		 9112 if (connector->dpms != DRM_MODE_DPMS_ON)
9113 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 9114
7173188d 9115 return true;
79e53945
JB		 9116 }
9117
9118 /* Find an unused one (if possible) */
70e1e0ec 9119 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 9120 i++;
9121 if (!(encoder->possible_crtcs & (1 << i)))
9122 continue;
83d65738 9123 if (possible_crtc->state->enable)
a459249c
VS		 9124 continue;
9125 /* This can occur when applying the pipe A quirk on resume. */
9126 if (to_intel_crtc(possible_crtc)->new_enabled)
9127 continue;
9128
9129 crtc = possible_crtc;
9130 break;
79e53945
JB		 9131 }
9132
9133 /*
9134 * If we didn't find an unused CRTC, don't use any.
9135 */
9136 if (!crtc) {
7173188d 9137 DRM_DEBUG_KMS("no pipe available for load-detect\n");
51fd371b 9138 goto fail_unlock;
79e53945
JB		 9139 }
9140
51fd371b
RC		 9141 ret = drm_modeset_lock(&crtc->mutex, ctx);
9142 if (ret)
4d02e2de
DV		 9143 goto fail_unlock;
9144 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9145 if (ret)
51fd371b 9146 goto fail_unlock;
fc303101
DV		 9147 intel_encoder->new_crtc = to_intel_crtc(crtc);
9148 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 9149
9150 intel_crtc = to_intel_crtc(crtc);
412b61d8 9151 intel_crtc->new_enabled = true;
6e3c9717 9152 intel_crtc->new_config = intel_crtc->config;
24218aac 9153 old->dpms_mode = connector->dpms;
8261b191 9154 old->load_detect_temp = true;
d2dff872 9155 old->release_fb = NULL;
79e53945 9156
83a57153
ACO		 9157 state = drm_atomic_state_alloc(dev);
9158 if (!state)
9159 return false;
9160
9161 state->acquire_ctx = ctx;
9162
944b0c76
ACO		 9163 connector_state = drm_atomic_get_connector_state(state, connector);
9164 if (IS_ERR(connector_state)) {
9165 ret = PTR_ERR(connector_state);
9166 goto fail;
9167 }
9168
9169 connector_state->crtc = crtc;
9170 connector_state->best_encoder = &intel_encoder->base;
9171
6492711d
CW		 9172 if (!mode)
9173 mode = &load_detect_mode;
79e53945 9174
d2dff872
CW		 9175 /* We need a framebuffer large enough to accommodate all accesses
9176 * that the plane may generate whilst we perform load detection.
9177 * We can not rely on the fbcon either being present (we get called
9178 * during its initialisation to detect all boot displays, or it may
9179 * not even exist) or that it is large enough to satisfy the
9180 * requested mode.
9181 */
94352cf9
DV		 9182 fb = mode_fits_in_fbdev(dev, mode);
9183 if (fb == NULL) {
d2dff872 9184 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 9185 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9186 old->release_fb = fb;
d2dff872
CW		 9187 } else
9188 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 9189 if (IS_ERR(fb)) {
d2dff872 9190 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 9191 goto fail;
79e53945 9192 }
79e53945 9193
83a57153 9194 if (intel_set_mode(crtc, mode, 0, 0, fb, state)) {
6492711d 9195 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 9196 if (old->release_fb)
9197 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 9198 goto fail;
79e53945 9199 }
9128b040 9200 crtc->primary->crtc = crtc;
7173188d 9201
79e53945 9202 /* let the connector get through one full cycle before testing */
9d0498a2 9203 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 9204 return true;
412b61d8
VS		 9205
9206 fail:
83d65738 9207 intel_crtc->new_enabled = crtc->state->enable;
412b61d8 9208 if (intel_crtc->new_enabled)
6e3c9717 9209 intel_crtc->new_config = intel_crtc->config;
412b61d8
VS		 9210 else
9211 intel_crtc->new_config = NULL;
51fd371b 9212fail_unlock:
83a57153
ACO		 9213 if (state) {
9214 drm_atomic_state_free(state);
9215 state = NULL;
9216 }
9217
51fd371b
RC		 9218 if (ret == -EDEADLK) {
9219 drm_modeset_backoff(ctx);
9220 goto retry;
9221 }
9222
412b61d8 9223 return false;
79e53945
JB		 9224}
9225
d2434ab7 9226void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 9227 struct intel_load_detect_pipe *old,
9228 struct drm_modeset_acquire_ctx *ctx)
79e53945 9229{
83a57153 9230 struct drm_device *dev = connector->dev;
d2434ab7
DV		 9231 struct intel_encoder *intel_encoder =
9232 intel_attached_encoder(connector);
4ef69c7a 9233 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 9234 struct drm_crtc *crtc = encoder->crtc;
412b61d8 9235 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 9236 struct drm_atomic_state *state;
944b0c76 9237 struct drm_connector_state *connector_state;
79e53945 9238
d2dff872 9239 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 9240 connector->base.id, connector->name,
8e329a03 9241 encoder->base.id, encoder->name);
d2dff872 9242
8261b191 9243 if (old->load_detect_temp) {
83a57153 9244 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 9245 if (!state)
9246 goto fail;
83a57153
ACO		 9247
9248 state->acquire_ctx = ctx;
9249
944b0c76
ACO		 9250 connector_state = drm_atomic_get_connector_state(state, connector);
9251 if (IS_ERR(connector_state))
9252 goto fail;
9253
fc303101
DV		 9254 to_intel_connector(connector)->new_encoder = NULL;
9255 intel_encoder->new_crtc = NULL;
412b61d8
VS		 9256 intel_crtc->new_enabled = false;
9257 intel_crtc->new_config = NULL;
944b0c76
ACO		 9258
9259 connector_state->best_encoder = NULL;
9260 connector_state->crtc = NULL;
9261
83a57153
ACO		 9262 intel_set_mode(crtc, NULL, 0, 0, NULL, state);
9263
9264 drm_atomic_state_free(state);
d2dff872 9265
36206361
DV		 9266 if (old->release_fb) {
9267 drm_framebuffer_unregister_private(old->release_fb);
9268 drm_framebuffer_unreference(old->release_fb);
9269 }
d2dff872 9270
0622a53c 9271 return;
79e53945
JB		 9272 }
9273
c751ce4f 9274 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 9275 if (old->dpms_mode != DRM_MODE_DPMS_ON)
9276 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 9277
9278 return;
9279fail:
9280 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
9281 drm_atomic_state_free(state);
79e53945
JB		 9282}
9283
da4a1efa 9284static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 9285 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 9286{
9287 struct drm_i915_private *dev_priv = dev->dev_private;
9288 u32 dpll = pipe_config->dpll_hw_state.dpll;
9289
9290 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 9291 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 9292 else if (HAS_PCH_SPLIT(dev))
9293 return 120000;
9294 else if (!IS_GEN2(dev))
9295 return 96000;
9296 else
9297 return 48000;
9298}
9299
79e53945 9300/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 9301static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 9302 struct intel_crtc_state *pipe_config)
79e53945 9303{
f1f644dc 9304 struct drm_device *dev = crtc->base.dev;
79e53945 9305 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 9306 int pipe = pipe_config->cpu_transcoder;
293623f7 9307 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 9308 u32 fp;
9309 intel_clock_t clock;
da4a1efa 9310 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 9311
9312 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 9313 fp = pipe_config->dpll_hw_state.fp0;
79e53945 9314 else
293623f7 9315 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 9316
9317 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 9318 if (IS_PINEVIEW(dev)) {
9319 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9320 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 9321 } else {
9322 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9323 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9324 }
9325
a6c45cf0 9326 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 9327 if (IS_PINEVIEW(dev))
9328 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9329 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 9330 else
9331 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 9332 DPLL_FPA01_P1_POST_DIV_SHIFT);
9333
9334 switch (dpll & DPLL_MODE_MASK) {
9335 case DPLLB_MODE_DAC_SERIAL:
9336 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9337 5 : 10;
9338 break;
9339 case DPLLB_MODE_LVDS:
9340 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9341 7 : 14;
9342 break;
9343 default:
28c97730 9344 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 9345 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 9346 return;
79e53945
JB		 9347 }
9348
ac58c3f0 9349 if (IS_PINEVIEW(dev))
da4a1efa 9350 pineview_clock(refclk, &clock);
ac58c3f0 9351 else
da4a1efa 9352 i9xx_clock(refclk, &clock);
79e53945 9353 } else {
0fb58223 9354 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 9355 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 9356
9357 if (is_lvds) {
9358 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9359 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 9360
9361 if (lvds & LVDS_CLKB_POWER_UP)
9362 clock.p2 = 7;
9363 else
9364 clock.p2 = 14;
79e53945
JB		 9365 } else {
9366 if (dpll & PLL_P1_DIVIDE_BY_TWO)
9367 clock.p1 = 2;
9368 else {
9369 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9370 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9371 }
9372 if (dpll & PLL_P2_DIVIDE_BY_4)
9373 clock.p2 = 4;
9374 else
9375 clock.p2 = 2;
79e53945 9376 }
da4a1efa
VS		 9377
9378 i9xx_clock(refclk, &clock);
79e53945
JB		 9379 }
9380
18442d08
VS		 9381 /*
9382 * This value includes pixel_multiplier. We will use
241bfc38 9383 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 9384 * encoder's get_config() function.
9385 */
9386 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 9387}
9388
6878da05
VS		 9389int intel_dotclock_calculate(int link_freq,
9390 const struct intel_link_m_n *m_n)
f1f644dc 9391{
f1f644dc
JB		 9392 /*
9393 * The calculation for the data clock is:
1041a02f 9394 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 9395 * But we want to avoid losing precison if possible, so:
1041a02f 9396 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 9397 *
9398 * and the link clock is simpler:
1041a02f 9399 * link_clock = (m * link_clock) / n
f1f644dc
JB		 9400 */
9401
6878da05
VS		 9402 if (!m_n->link_n)
9403 return 0;
f1f644dc 9404
6878da05
VS		 9405 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9406}
f1f644dc 9407
18442d08 9408static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 9409 struct intel_crtc_state *pipe_config)
6878da05
VS		 9410{
9411 struct drm_device *dev = crtc->base.dev;
79e53945 9412
18442d08
VS		 9413 /* read out port_clock from the DPLL */
9414 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 9415
f1f644dc 9416 /*
18442d08 9417 * This value does not include pixel_multiplier.
241bfc38 9418 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 9419 * agree once we know their relationship in the encoder's
9420 * get_config() function.
79e53945 9421 */
2d112de7 9422 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 9423 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
9424 &pipe_config->fdi_m_n);
79e53945
JB		 9425}
9426
9427/** Returns the currently programmed mode of the given pipe. */
9428struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9429 struct drm_crtc *crtc)
9430{
548f245b 9431 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 9432 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 9433 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 9434 struct drm_display_mode *mode;
5cec258b 9435 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 9436 int htot = I915_READ(HTOTAL(cpu_transcoder));
9437 int hsync = I915_READ(HSYNC(cpu_transcoder));
9438 int vtot = I915_READ(VTOTAL(cpu_transcoder));
9439 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 9440 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 9441
9442 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9443 if (!mode)
9444 return NULL;
9445
f1f644dc
JB		 9446 /*
9447 * Construct a pipe_config sufficient for getting the clock info
9448 * back out of crtc_clock_get.
9449 *
9450 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9451 * to use a real value here instead.
9452 */
293623f7 9453 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 9454 pipe_config.pixel_multiplier = 1;
293623f7
VS		 9455 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9456 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9457 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 9458 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
9459
773ae034 9460 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 9461 mode->hdisplay = (htot & 0xffff) + 1;
9462 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9463 mode->hsync_start = (hsync & 0xffff) + 1;
9464 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9465 mode->vdisplay = (vtot & 0xffff) + 1;
9466 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9467 mode->vsync_start = (vsync & 0xffff) + 1;
9468 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9469
9470 drm_mode_set_name(mode);
79e53945
JB		 9471
9472 return mode;
9473}
9474
652c393a
JB		 9475static void intel_decrease_pllclock(struct drm_crtc *crtc)
9476{
9477 struct drm_device *dev = crtc->dev;
fbee40df 9478 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 9479 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 9480
baff296c 9481 if (!HAS_GMCH_DISPLAY(dev))
652c393a
JB		 9482 return;
9483
9484 if (!dev_priv->lvds_downclock_avail)
9485 return;
9486
9487 /*
9488 * Since this is called by a timer, we should never get here in
9489 * the manual case.
9490 */
9491 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 9492 int pipe = intel_crtc->pipe;
9493 int dpll_reg = DPLL(pipe);
9494 int dpll;
f6e5b160 9495
44d98a61 9496 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 9497
8ac5a6d5 9498 assert_panel_unlocked(dev_priv, pipe);
652c393a 9499
dc257cf1 9500 dpll = I915_READ(dpll_reg);
652c393a
JB		 9501 dpll |= DISPLAY_RATE_SELECT_FPA1;
9502 I915_WRITE(dpll_reg, dpll);
9d0498a2 9503 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 9504 dpll = I915_READ(dpll_reg);
9505 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 9506 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 9507 }
9508
9509}
9510
f047e395
CW		 9511void intel_mark_busy(struct drm_device *dev)
9512{
c67a470b
PZ		 9513 struct drm_i915_private *dev_priv = dev->dev_private;
9514
f62a0076
CW		 9515 if (dev_priv->mm.busy)
9516 return;
9517
43694d69 9518 intel_runtime_pm_get(dev_priv);
c67a470b 9519 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 9520 if (INTEL_INFO(dev)->gen >= 6)
9521 gen6_rps_busy(dev_priv);
f62a0076 9522 dev_priv->mm.busy = true;
f047e395
CW		 9523}
9524
9525void intel_mark_idle(struct drm_device *dev)
652c393a 9526{
c67a470b 9527 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 9528 struct drm_crtc *crtc;
652c393a 9529
f62a0076
CW		 9530 if (!dev_priv->mm.busy)
9531 return;
9532
9533 dev_priv->mm.busy = false;
9534
70e1e0ec 9535 for_each_crtc(dev, crtc) {
f4510a27 9536 if (!crtc->primary->fb)
652c393a
JB		 9537 continue;
9538
725a5b54 9539 intel_decrease_pllclock(crtc);
652c393a 9540 }
b29c19b6 9541
3d13ef2e 9542 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 9543 gen6_rps_idle(dev->dev_private);
bb4cdd53 9544
43694d69 9545 intel_runtime_pm_put(dev_priv);
652c393a
JB		 9546}
9547
f5de6e07
ACO		 9548static void intel_crtc_set_state(struct intel_crtc *crtc,
9549 struct intel_crtc_state *crtc_state)
9550{
9551 kfree(crtc->config);
9552 crtc->config = crtc_state;
16f3f658 9553 crtc->base.state = &crtc_state->base;
f5de6e07
ACO		 9554}
9555
79e53945
JB		 9556static void intel_crtc_destroy(struct drm_crtc *crtc)
9557{
9558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 9559 struct drm_device *dev = crtc->dev;
9560 struct intel_unpin_work *work;
67e77c5a 9561
5e2d7afc 9562 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 9563 work = intel_crtc->unpin_work;
9564 intel_crtc->unpin_work = NULL;
5e2d7afc 9565 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 9566
9567 if (work) {
9568 cancel_work_sync(&work->work);
9569 kfree(work);
9570 }
79e53945 9571
f5de6e07 9572 intel_crtc_set_state(intel_crtc, NULL);
79e53945 9573 drm_crtc_cleanup(crtc);
67e77c5a 9574
79e53945
JB		 9575 kfree(intel_crtc);
9576}
9577
6b95a207
KH		 9578static void intel_unpin_work_fn(struct work_struct *__work)
9579{
9580 struct intel_unpin_work *work =
9581 container_of(__work, struct intel_unpin_work, work);
b4a98e57 9582 struct drm_device *dev = work->crtc->dev;
f99d7069 9583 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
6b95a207 9584
b4a98e57 9585 mutex_lock(&dev->struct_mutex);
82bc3b2d 9586 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
05394f39 9587 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 9588
7ff0ebcc 9589 intel_fbc_update(dev);
f06cc1b9
JH		 9590
9591 if (work->flip_queued_req)
146d84f0 9592 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 9593 mutex_unlock(&dev->struct_mutex);
9594
f99d7069 9595 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
89ed88ba 9596 drm_framebuffer_unreference(work->old_fb);
f99d7069 9597
b4a98e57
CW		 9598 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9599 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9600
6b95a207
KH		 9601 kfree(work);
9602}
9603
1afe3e9d 9604static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 9605 struct drm_crtc *crtc)
6b95a207 9606{
6b95a207
KH		 9607 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9608 struct intel_unpin_work *work;
6b95a207
KH		 9609 unsigned long flags;
9610
9611 /* Ignore early vblank irqs */
9612 if (intel_crtc == NULL)
9613 return;
9614
f326038a
DV		 9615 /*
9616 * This is called both by irq handlers and the reset code (to complete
9617 * lost pageflips) so needs the full irqsave spinlocks.
9618 */
6b95a207
KH		 9619 spin_lock_irqsave(&dev->event_lock, flags);
9620 work = intel_crtc->unpin_work;
e7d841ca
CW		 9621
9622 /* Ensure we don't miss a work->pending update ... */
9623 smp_rmb();
9624
9625 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 9626 spin_unlock_irqrestore(&dev->event_lock, flags);
9627 return;
9628 }
9629
d6bbafa1 9630 page_flip_completed(intel_crtc);
0af7e4df 9631
6b95a207 9632 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 9633}
9634
1afe3e9d
JB		 9635void intel_finish_page_flip(struct drm_device *dev, int pipe)
9636{
fbee40df 9637 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 9638 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9639
49b14a5c 9640 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 9641}
9642
9643void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9644{
fbee40df 9645 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 9646 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9647
49b14a5c 9648 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 9649}
9650
75f7f3ec
VS		 9651/* Is 'a' after or equal to 'b'? */
9652static bool g4x_flip_count_after_eq(u32 a, u32 b)
9653{
9654 return !((a - b) & 0x80000000);
9655}
9656
9657static bool page_flip_finished(struct intel_crtc *crtc)
9658{
9659 struct drm_device *dev = crtc->base.dev;
9660 struct drm_i915_private *dev_priv = dev->dev_private;
9661
bdfa7542
VS		 9662 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9663 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9664 return true;
9665
75f7f3ec
VS		 9666 /*
9667 * The relevant registers doen't exist on pre-ctg.
9668 * As the flip done interrupt doesn't trigger for mmio
9669 * flips on gmch platforms, a flip count check isn't
9670 * really needed there. But since ctg has the registers,
9671 * include it in the check anyway.
9672 */
9673 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9674 return true;
9675
9676 /*
9677 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9678 * used the same base address. In that case the mmio flip might
9679 * have completed, but the CS hasn't even executed the flip yet.
9680 *
9681 * A flip count check isn't enough as the CS might have updated
9682 * the base address just after start of vblank, but before we
9683 * managed to process the interrupt. This means we'd complete the
9684 * CS flip too soon.
9685 *
9686 * Combining both checks should get us a good enough result. It may
9687 * still happen that the CS flip has been executed, but has not
9688 * yet actually completed. But in case the base address is the same
9689 * anyway, we don't really care.
9690 */
9691 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9692 crtc->unpin_work->gtt_offset &&
9693 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9694 crtc->unpin_work->flip_count);
9695}
9696
6b95a207
KH		 9697void intel_prepare_page_flip(struct drm_device *dev, int plane)
9698{
fbee40df 9699 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 9700 struct intel_crtc *intel_crtc =
9701 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9702 unsigned long flags;
9703
f326038a
DV		 9704
9705 /*
9706 * This is called both by irq handlers and the reset code (to complete
9707 * lost pageflips) so needs the full irqsave spinlocks.
9708 *
9709 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 9710 * generate a page-flip completion irq, i.e. every modeset
9711 * is also accompanied by a spurious intel_prepare_page_flip().
9712 */
6b95a207 9713 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 9714 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 9715 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 9716 spin_unlock_irqrestore(&dev->event_lock, flags);
9717}
9718
eba905b2 9719static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW		 9720{
9721 /* Ensure that the work item is consistent when activating it ... */
9722 smp_wmb();
9723 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9724 /* and that it is marked active as soon as the irq could fire. */
9725 smp_wmb();
9726}
9727
8c9f3aaf
JB		 9728static int intel_gen2_queue_flip(struct drm_device *dev,
9729 struct drm_crtc *crtc,
9730 struct drm_framebuffer *fb,
ed8d1975 9731 struct drm_i915_gem_object *obj,
a4872ba6 9732 struct intel_engine_cs *ring,
ed8d1975 9733 uint32_t flags)
8c9f3aaf 9734{
8c9f3aaf 9735 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 9736 u32 flip_mask;
9737 int ret;
9738
6d90c952 9739 ret = intel_ring_begin(ring, 6);
8c9f3aaf 9740 if (ret)
4fa62c89 9741 return ret;
8c9f3aaf
JB		 9742
9743 /* Can't queue multiple flips, so wait for the previous
9744 * one to finish before executing the next.
9745 */
9746 if (intel_crtc->plane)
9747 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9748 else
9749 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 9750 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9751 intel_ring_emit(ring, MI_NOOP);
9752 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9753 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9754 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 9755 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 9756 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 9757
9758 intel_mark_page_flip_active(intel_crtc);
09246732 9759 __intel_ring_advance(ring);
83d4092b 9760 return 0;
8c9f3aaf
JB		 9761}
9762
9763static int intel_gen3_queue_flip(struct drm_device *dev,
9764 struct drm_crtc *crtc,
9765 struct drm_framebuffer *fb,
ed8d1975 9766 struct drm_i915_gem_object *obj,
a4872ba6 9767 struct intel_engine_cs *ring,
ed8d1975 9768 uint32_t flags)
8c9f3aaf 9769{
8c9f3aaf 9770 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 9771 u32 flip_mask;
9772 int ret;
9773
6d90c952 9774 ret = intel_ring_begin(ring, 6);
8c9f3aaf 9775 if (ret)
4fa62c89 9776 return ret;
8c9f3aaf
JB		 9777
9778 if (intel_crtc->plane)
9779 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9780 else
9781 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 9782 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9783 intel_ring_emit(ring, MI_NOOP);
9784 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9785 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9786 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 9787 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 9788 intel_ring_emit(ring, MI_NOOP);
9789
e7d841ca 9790 intel_mark_page_flip_active(intel_crtc);
09246732 9791 __intel_ring_advance(ring);
83d4092b 9792 return 0;
8c9f3aaf
JB		 9793}
9794
9795static int intel_gen4_queue_flip(struct drm_device *dev,
9796 struct drm_crtc *crtc,
9797 struct drm_framebuffer *fb,
ed8d1975 9798 struct drm_i915_gem_object *obj,
a4872ba6 9799 struct intel_engine_cs *ring,
ed8d1975 9800 uint32_t flags)
8c9f3aaf
JB		 9801{
9802 struct drm_i915_private *dev_priv = dev->dev_private;
9803 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9804 uint32_t pf, pipesrc;
9805 int ret;
9806
6d90c952 9807 ret = intel_ring_begin(ring, 4);
8c9f3aaf 9808 if (ret)
4fa62c89 9809 return ret;
8c9f3aaf
JB		 9810
9811 /* i965+ uses the linear or tiled offsets from the
9812 * Display Registers (which do not change across a page-flip)
9813 * so we need only reprogram the base address.
9814 */
6d90c952
DV		 9815 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9816 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9817 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 9818 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 9819 obj->tiling_mode);
8c9f3aaf
JB		 9820
9821 /* XXX Enabling the panel-fitter across page-flip is so far
9822 * untested on non-native modes, so ignore it for now.
9823 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9824 */
9825 pf = 0;
9826 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 9827 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 9828
9829 intel_mark_page_flip_active(intel_crtc);
09246732 9830 __intel_ring_advance(ring);
83d4092b 9831 return 0;
8c9f3aaf
JB		 9832}
9833
9834static int intel_gen6_queue_flip(struct drm_device *dev,
9835 struct drm_crtc *crtc,
9836 struct drm_framebuffer *fb,
ed8d1975 9837 struct drm_i915_gem_object *obj,
a4872ba6 9838 struct intel_engine_cs *ring,
ed8d1975 9839 uint32_t flags)
8c9f3aaf
JB		 9840{
9841 struct drm_i915_private *dev_priv = dev->dev_private;
9842 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9843 uint32_t pf, pipesrc;
9844 int ret;
9845
6d90c952 9846 ret = intel_ring_begin(ring, 4);
8c9f3aaf 9847 if (ret)
4fa62c89 9848 return ret;
8c9f3aaf 9849
6d90c952
DV		 9850 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9851 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9852 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 9853 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 9854
dc257cf1
DV		 9855 /* Contrary to the suggestions in the documentation,
9856 * "Enable Panel Fitter" does not seem to be required when page
9857 * flipping with a non-native mode, and worse causes a normal
9858 * modeset to fail.
9859 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9860 */
9861 pf = 0;
8c9f3aaf 9862 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 9863 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 9864
9865 intel_mark_page_flip_active(intel_crtc);
09246732 9866 __intel_ring_advance(ring);
83d4092b 9867 return 0;
8c9f3aaf
JB		 9868}
9869
7c9017e5
JB		 9870static int intel_gen7_queue_flip(struct drm_device *dev,
9871 struct drm_crtc *crtc,
9872 struct drm_framebuffer *fb,
ed8d1975 9873 struct drm_i915_gem_object *obj,
a4872ba6 9874 struct intel_engine_cs *ring,
ed8d1975 9875 uint32_t flags)
7c9017e5 9876{
7c9017e5 9877 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 9878 uint32_t plane_bit = 0;
ffe74d75
CW		 9879 int len, ret;
9880
eba905b2 9881 switch (intel_crtc->plane) {
cb05d8de
DV		 9882 case PLANE_A:
9883 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9884 break;
9885 case PLANE_B:
9886 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9887 break;
9888 case PLANE_C:
9889 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9890 break;
9891 default:
9892 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 9893 return -ENODEV;
cb05d8de
DV		 9894 }
9895
ffe74d75 9896 len = 4;
f476828a 9897 if (ring->id == RCS) {
ffe74d75 9898 len += 6;
f476828a
DL		 9899 /*
9900 * On Gen 8, SRM is now taking an extra dword to accommodate
9901 * 48bits addresses, and we need a NOOP for the batch size to
9902 * stay even.
9903 */
9904 if (IS_GEN8(dev))
9905 len += 2;
9906 }
ffe74d75 9907
f66fab8e
VS		 9908 /*
9909 * BSpec MI_DISPLAY_FLIP for IVB:
9910 * "The full packet must be contained within the same cache line."
9911 *
9912 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9913 * cacheline, if we ever start emitting more commands before
9914 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9915 * then do the cacheline alignment, and finally emit the
9916 * MI_DISPLAY_FLIP.
9917 */
9918 ret = intel_ring_cacheline_align(ring);
9919 if (ret)
4fa62c89 9920 return ret;
f66fab8e 9921
ffe74d75 9922 ret = intel_ring_begin(ring, len);
7c9017e5 9923 if (ret)
4fa62c89 9924 return ret;
7c9017e5 9925
ffe74d75
CW		 9926 /* Unmask the flip-done completion message. Note that the bspec says that
9927 * we should do this for both the BCS and RCS, and that we must not unmask
9928 * more than one flip event at any time (or ensure that one flip message
9929 * can be sent by waiting for flip-done prior to queueing new flips).
9930 * Experimentation says that BCS works despite DERRMR masking all
9931 * flip-done completion events and that unmasking all planes at once
9932 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9933 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9934 */
9935 if (ring->id == RCS) {
9936 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9937 intel_ring_emit(ring, DERRMR);
9938 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9939 DERRMR_PIPEB_PRI_FLIP_DONE |
9940 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a
DL		 9941 if (IS_GEN8(dev))
9942 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9943 MI_SRM_LRM_GLOBAL_GTT);
9944 else
9945 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9946 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 9947 intel_ring_emit(ring, DERRMR);
9948 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 9949 if (IS_GEN8(dev)) {
9950 intel_ring_emit(ring, 0);
9951 intel_ring_emit(ring, MI_NOOP);
9952 }
ffe74d75
CW		 9953 }
9954
cb05d8de 9955 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 9956 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 9957 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 9958 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 9959
9960 intel_mark_page_flip_active(intel_crtc);
09246732 9961 __intel_ring_advance(ring);
83d4092b 9962 return 0;
7c9017e5
JB		 9963}
9964
84c33a64
SG		 9965static bool use_mmio_flip(struct intel_engine_cs *ring,
9966 struct drm_i915_gem_object *obj)
9967{
9968 /*
9969 * This is not being used for older platforms, because
9970 * non-availability of flip done interrupt forces us to use
9971 * CS flips. Older platforms derive flip done using some clever
9972 * tricks involving the flip_pending status bits and vblank irqs.
9973 * So using MMIO flips there would disrupt this mechanism.
9974 */
9975
8e09bf83
CW		 9976 if (ring == NULL)
9977 return true;
9978
84c33a64
SG		 9979 if (INTEL_INFO(ring->dev)->gen < 5)
9980 return false;
9981
9982 if (i915.use_mmio_flip < 0)
9983 return false;
9984 else if (i915.use_mmio_flip > 0)
9985 return true;
14bf993e
OM		 9986 else if (i915.enable_execlists)
9987 return true;
84c33a64 9988 else
41c52415 9989 return ring != i915_gem_request_get_ring(obj->last_read_req);
84c33a64
SG		 9990}
9991
ff944564
DL		 9992static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
9993{
9994 struct drm_device *dev = intel_crtc->base.dev;
9995 struct drm_i915_private *dev_priv = dev->dev_private;
9996 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
9997 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9998 struct drm_i915_gem_object *obj = intel_fb->obj;
9999 const enum pipe pipe = intel_crtc->pipe;
10000 u32 ctl, stride;
10001
10002 ctl = I915_READ(PLANE_CTL(pipe, 0));
10003 ctl &= ~PLANE_CTL_TILED_MASK;
10004 if (obj->tiling_mode == I915_TILING_X)
10005 ctl |= PLANE_CTL_TILED_X;
10006
10007 /*
10008 * The stride is either expressed as a multiple of 64 bytes chunks for
10009 * linear buffers or in number of tiles for tiled buffers.
10010 */
10011 stride = fb->pitches[0] >> 6;
10012 if (obj->tiling_mode == I915_TILING_X)
10013 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
10014
10015 /*
10016 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10017 * PLANE_SURF updates, the update is then guaranteed to be atomic.
10018 */
10019 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10020 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10021
10022 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
10023 POSTING_READ(PLANE_SURF(pipe, 0));
10024}
10025
10026static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG		 10027{
10028 struct drm_device *dev = intel_crtc->base.dev;
10029 struct drm_i915_private *dev_priv = dev->dev_private;
10030 struct intel_framebuffer *intel_fb =
10031 to_intel_framebuffer(intel_crtc->base.primary->fb);
10032 struct drm_i915_gem_object *obj = intel_fb->obj;
10033 u32 dspcntr;
10034 u32 reg;
10035
84c33a64
SG		 10036 reg = DSPCNTR(intel_crtc->plane);
10037 dspcntr = I915_READ(reg);
10038
c5d97472
DL		 10039 if (obj->tiling_mode != I915_TILING_NONE)
10040 dspcntr |= DISPPLANE_TILED;
10041 else
10042 dspcntr &= ~DISPPLANE_TILED;
10043
84c33a64
SG		 10044 I915_WRITE(reg, dspcntr);
10045
10046 I915_WRITE(DSPSURF(intel_crtc->plane),
10047 intel_crtc->unpin_work->gtt_offset);
10048 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 10049
ff944564
DL		 10050}
10051
10052/*
10053 * XXX: This is the temporary way to update the plane registers until we get
10054 * around to using the usual plane update functions for MMIO flips
10055 */
10056static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
10057{
10058 struct drm_device *dev = intel_crtc->base.dev;
10059 bool atomic_update;
10060 u32 start_vbl_count;
10061
10062 intel_mark_page_flip_active(intel_crtc);
10063
10064 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
10065
10066 if (INTEL_INFO(dev)->gen >= 9)
10067 skl_do_mmio_flip(intel_crtc);
10068 else
10069 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10070 ilk_do_mmio_flip(intel_crtc);
10071
9362c7c5
ACO		 10072 if (atomic_update)
10073 intel_pipe_update_end(intel_crtc, start_vbl_count);
84c33a64
SG		 10074}
10075
9362c7c5 10076static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 10077{
cc8c4cc2 10078 struct intel_crtc *crtc =
9362c7c5 10079 container_of(work, struct intel_crtc, mmio_flip.work);
cc8c4cc2 10080 struct intel_mmio_flip *mmio_flip;
84c33a64 10081
cc8c4cc2
JH		 10082 mmio_flip = &crtc->mmio_flip;
10083 if (mmio_flip->req)
9c654818
JH		 10084 WARN_ON(__i915_wait_request(mmio_flip->req,
10085 crtc->reset_counter,
10086 false, NULL, NULL) != 0);
84c33a64 10087
cc8c4cc2
JH		 10088 intel_do_mmio_flip(crtc);
10089 if (mmio_flip->req) {
10090 mutex_lock(&crtc->base.dev->struct_mutex);
146d84f0 10091 i915_gem_request_assign(&mmio_flip->req, NULL);
cc8c4cc2
JH		 10092 mutex_unlock(&crtc->base.dev->struct_mutex);
10093 }
84c33a64
SG		 10094}
10095
10096static int intel_queue_mmio_flip(struct drm_device *dev,
10097 struct drm_crtc *crtc,
10098 struct drm_framebuffer *fb,
10099 struct drm_i915_gem_object *obj,
10100 struct intel_engine_cs *ring,
10101 uint32_t flags)
10102{
84c33a64 10103 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
84c33a64 10104
cc8c4cc2
JH		 10105 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
10106 obj->last_write_req);
536f5b5e
ACO		 10107
10108 schedule_work(&intel_crtc->mmio_flip.work);
84c33a64 10109
84c33a64
SG		 10110 return 0;
10111}
10112
8c9f3aaf
JB		 10113static int intel_default_queue_flip(struct drm_device *dev,
10114 struct drm_crtc *crtc,
10115 struct drm_framebuffer *fb,
ed8d1975 10116 struct drm_i915_gem_object *obj,
a4872ba6 10117 struct intel_engine_cs *ring,
ed8d1975 10118 uint32_t flags)
8c9f3aaf
JB		 10119{
10120 return -ENODEV;
10121}
10122
d6bbafa1
CW		 10123static bool __intel_pageflip_stall_check(struct drm_device *dev,
10124 struct drm_crtc *crtc)
10125{
10126 struct drm_i915_private *dev_priv = dev->dev_private;
10127 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10128 struct intel_unpin_work *work = intel_crtc->unpin_work;
10129 u32 addr;
10130
10131 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
10132 return true;
10133
10134 if (!work->enable_stall_check)
10135 return false;
10136
10137 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 10138 if (work->flip_queued_req &&
10139 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 10140 return false;
10141
1e3feefd 10142 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 10143 }
10144
1e3feefd 10145 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 10146 return false;
10147
10148 /* Potential stall - if we see that the flip has happened,
10149 * assume a missed interrupt. */
10150 if (INTEL_INFO(dev)->gen >= 4)
10151 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
10152 else
10153 addr = I915_READ(DSPADDR(intel_crtc->plane));
10154
10155 /* There is a potential issue here with a false positive after a flip
10156 * to the same address. We could address this by checking for a
10157 * non-incrementing frame counter.
10158 */
10159 return addr == work->gtt_offset;
10160}
10161
10162void intel_check_page_flip(struct drm_device *dev, int pipe)
10163{
10164 struct drm_i915_private *dev_priv = dev->dev_private;
10165 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10166 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
f326038a 10167
6c51d46f 10168 WARN_ON(!in_interrupt());
d6bbafa1
CW		 10169
10170 if (crtc == NULL)
10171 return;
10172
f326038a 10173 spin_lock(&dev->event_lock);
d6bbafa1
CW		 10174 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
10175 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
1e3feefd
DV		 10176 intel_crtc->unpin_work->flip_queued_vblank,
10177 drm_vblank_count(dev, pipe));
d6bbafa1
CW		 10178 page_flip_completed(intel_crtc);
10179 }
f326038a 10180 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 10181}
10182
6b95a207
KH		 10183static int intel_crtc_page_flip(struct drm_crtc *crtc,
10184 struct drm_framebuffer *fb,
ed8d1975
KP		 10185 struct drm_pending_vblank_event *event,
10186 uint32_t page_flip_flags)
6b95a207
KH		 10187{
10188 struct drm_device *dev = crtc->dev;
10189 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 10190 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 10191 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 10192 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 10193 struct drm_plane *primary = crtc->primary;
a071fa00 10194 enum pipe pipe = intel_crtc->pipe;
6b95a207 10195 struct intel_unpin_work *work;
a4872ba6 10196 struct intel_engine_cs *ring;
52e68630 10197 int ret;
6b95a207 10198
2ff8fde1
MR		 10199 /*
10200 * drm_mode_page_flip_ioctl() should already catch this, but double
10201 * check to be safe. In the future we may enable pageflipping from
10202 * a disabled primary plane.
10203 */
10204 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10205 return -EBUSY;
10206
e6a595d2 10207 /* Can't change pixel format via MI display flips. */
f4510a27 10208 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 10209 return -EINVAL;
10210
10211 /*
10212 * TILEOFF/LINOFF registers can't be changed via MI display flips.
10213 * Note that pitch changes could also affect these register.
10214 */
10215 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 10216 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10217 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 10218 return -EINVAL;
10219
f900db47
CW		 10220 if (i915_terminally_wedged(&dev_priv->gpu_error))
10221 goto out_hang;
10222
b14c5679 10223 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 10224 if (work == NULL)
10225 return -ENOMEM;
10226
6b95a207 10227 work->event = event;
b4a98e57 10228 work->crtc = crtc;
ab8d6675 10229 work->old_fb = old_fb;
6b95a207
KH		 10230 INIT_WORK(&work->work, intel_unpin_work_fn);
10231
87b6b101 10232 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 10233 if (ret)
10234 goto free_work;
10235
6b95a207 10236 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 10237 spin_lock_irq(&dev->event_lock);
6b95a207 10238 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 10239 /* Before declaring the flip queue wedged, check if
10240 * the hardware completed the operation behind our backs.
10241 */
10242 if (__intel_pageflip_stall_check(dev, crtc)) {
10243 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10244 page_flip_completed(intel_crtc);
10245 } else {
10246 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 10247 spin_unlock_irq(&dev->event_lock);
468f0b44 10248
d6bbafa1
CW		 10249 drm_crtc_vblank_put(crtc);
10250 kfree(work);
10251 return -EBUSY;
10252 }
6b95a207
KH		 10253 }
10254 intel_crtc->unpin_work = work;
5e2d7afc 10255 spin_unlock_irq(&dev->event_lock);
6b95a207 10256
b4a98e57
CW		 10257 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10258 flush_workqueue(dev_priv->wq);
10259
75dfca80 10260 /* Reference the objects for the scheduled work. */
ab8d6675 10261 drm_framebuffer_reference(work->old_fb);
05394f39 10262 drm_gem_object_reference(&obj->base);
6b95a207 10263
f4510a27 10264 crtc->primary->fb = fb;
afd65eb4 10265 update_state_fb(crtc->primary);
1ed1f968 10266
e1f99ce6 10267 work->pending_flip_obj = obj;
e1f99ce6 10268
89ed88ba
CW		 10269 ret = i915_mutex_lock_interruptible(dev);
10270 if (ret)
10271 goto cleanup;
10272
b4a98e57 10273 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 10274 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 10275
75f7f3ec 10276 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 10277 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 10278
4fa62c89
VS		 10279 if (IS_VALLEYVIEW(dev)) {
10280 ring = &dev_priv->ring[BCS];
ab8d6675 10281 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 10282 /* vlv: DISPLAY_FLIP fails to change tiling */
10283 ring = NULL;
48bf5b2d 10284 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 10285 ring = &dev_priv->ring[BCS];
4fa62c89 10286 } else if (INTEL_INFO(dev)->gen >= 7) {
41c52415 10287 ring = i915_gem_request_get_ring(obj->last_read_req);
4fa62c89
VS		 10288 if (ring == NULL || ring->id != RCS)
10289 ring = &dev_priv->ring[BCS];
10290 } else {
10291 ring = &dev_priv->ring[RCS];
10292 }
10293
82bc3b2d
TU		 10294 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
10295 crtc->primary->state, ring);
8c9f3aaf
JB		 10296 if (ret)
10297 goto cleanup_pending;
6b95a207 10298
121920fa
TU		 10299 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
10300 + intel_crtc->dspaddr_offset;
4fa62c89 10301
d6bbafa1 10302 if (use_mmio_flip(ring, obj)) {
84c33a64
SG		 10303 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
10304 page_flip_flags);
d6bbafa1
CW		 10305 if (ret)
10306 goto cleanup_unpin;
10307
f06cc1b9
JH		 10308 i915_gem_request_assign(&work->flip_queued_req,
10309 obj->last_write_req);
d6bbafa1 10310 } else {
84c33a64 10311 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
d6bbafa1
CW		 10312 page_flip_flags);
10313 if (ret)
10314 goto cleanup_unpin;
10315
f06cc1b9
JH		 10316 i915_gem_request_assign(&work->flip_queued_req,
10317 intel_ring_get_request(ring));
d6bbafa1
CW		 10318 }
10319
1e3feefd 10320 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 10321 work->enable_stall_check = true;
4fa62c89 10322
ab8d6675 10323 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a071fa00
DV		 10324 INTEL_FRONTBUFFER_PRIMARY(pipe));
10325
7ff0ebcc 10326 intel_fbc_disable(dev);
f99d7069 10327 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
6b95a207
KH		 10328 mutex_unlock(&dev->struct_mutex);
10329
e5510fac
JB		 10330 trace_i915_flip_request(intel_crtc->plane, obj);
10331
6b95a207 10332 return 0;
96b099fd 10333
4fa62c89 10334cleanup_unpin:
82bc3b2d 10335 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 10336cleanup_pending:
b4a98e57 10337 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 10338 mutex_unlock(&dev->struct_mutex);
10339cleanup:
f4510a27 10340 crtc->primary->fb = old_fb;
afd65eb4 10341 update_state_fb(crtc->primary);
89ed88ba
CW		 10342
10343 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 10344 drm_framebuffer_unreference(work->old_fb);
96b099fd 10345
5e2d7afc 10346 spin_lock_irq(&dev->event_lock);
96b099fd 10347 intel_crtc->unpin_work = NULL;
5e2d7afc 10348 spin_unlock_irq(&dev->event_lock);
96b099fd 10349
87b6b101 10350 drm_crtc_vblank_put(crtc);
7317c75e 10351free_work:
96b099fd
CW		 10352 kfree(work);
10353
f900db47
CW		 10354 if (ret == -EIO) {
10355out_hang:
53a366b9 10356 ret = intel_plane_restore(primary);
f0d3dad3 10357 if (ret == 0 && event) {
5e2d7afc 10358 spin_lock_irq(&dev->event_lock);
a071fa00 10359 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 10360 spin_unlock_irq(&dev->event_lock);
f0d3dad3 10361 }
f900db47 10362 }
96b099fd 10363 return ret;
6b95a207
KH		 10364}
10365
f6e5b160 10366static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 10367 .mode_set_base_atomic = intel_pipe_set_base_atomic,
10368 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 10369 .atomic_begin = intel_begin_crtc_commit,
10370 .atomic_flush = intel_finish_crtc_commit,
f6e5b160
CW		 10371};
10372
9a935856
DV		 10373/**
10374 * intel_modeset_update_staged_output_state
10375 *
10376 * Updates the staged output configuration state, e.g. after we've read out the
10377 * current hw state.
10378 */
10379static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 10380{
7668851f 10381 struct intel_crtc *crtc;
9a935856
DV		 10382 struct intel_encoder *encoder;
10383 struct intel_connector *connector;
f6e5b160 10384
3a3371ff 10385 for_each_intel_connector(dev, connector) {
9a935856
DV		 10386 connector->new_encoder =
10387 to_intel_encoder(connector->base.encoder);
10388 }
f6e5b160 10389
b2784e15 10390 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 10391 encoder->new_crtc =
10392 to_intel_crtc(encoder->base.crtc);
10393 }
7668851f 10394
d3fcc808 10395 for_each_intel_crtc(dev, crtc) {
83d65738 10396 crtc->new_enabled = crtc->base.state->enable;
7bd0a8e7
VS		 10397
10398 if (crtc->new_enabled)
6e3c9717 10399 crtc->new_config = crtc->config;
7bd0a8e7
VS		 10400 else
10401 crtc->new_config = NULL;
7668851f 10402 }
f6e5b160
CW		 10403}
10404
d29b2f9d
ACO		 10405/* Transitional helper to copy current connector/encoder state to
10406 * connector->state. This is needed so that code that is partially
10407 * converted to atomic does the right thing.
10408 */
10409static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
10410{
10411 struct intel_connector *connector;
10412
10413 for_each_intel_connector(dev, connector) {
10414 if (connector->base.encoder) {
10415 connector->base.state->best_encoder =
10416 connector->base.encoder;
10417 connector->base.state->crtc =
10418 connector->base.encoder->crtc;
10419 } else {
10420 connector->base.state->best_encoder = NULL;
10421 connector->base.state->crtc = NULL;
10422 }
10423 }
10424}
10425
9a935856
DV		 10426/**
10427 * intel_modeset_commit_output_state
10428 *
10429 * This function copies the stage display pipe configuration to the real one.
10430 */
10431static void intel_modeset_commit_output_state(struct drm_device *dev)
10432{
7668851f 10433 struct intel_crtc *crtc;
9a935856
DV		 10434 struct intel_encoder *encoder;
10435 struct intel_connector *connector;
f6e5b160 10436
3a3371ff 10437 for_each_intel_connector(dev, connector) {
9a935856
DV		 10438 connector->base.encoder = &connector->new_encoder->base;
10439 }
f6e5b160 10440
b2784e15 10441 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 10442 encoder->base.crtc = &encoder->new_crtc->base;
10443 }
7668851f 10444
d3fcc808 10445 for_each_intel_crtc(dev, crtc) {
83d65738 10446 crtc->base.state->enable = crtc->new_enabled;
7668851f
VS		 10447 crtc->base.enabled = crtc->new_enabled;
10448 }
d29b2f9d
ACO		 10449
10450 intel_modeset_update_connector_atomic_state(dev);
9a935856
DV		 10451}
10452
050f7aeb 10453static void
eba905b2 10454connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 10455 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 10456{
10457 int bpp = pipe_config->pipe_bpp;
10458
10459 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10460 connector->base.base.id,
c23cc417 10461 connector->base.name);
050f7aeb
DV		 10462
10463 /* Don't use an invalid EDID bpc value */
10464 if (connector->base.display_info.bpc &&
10465 connector->base.display_info.bpc * 3 < bpp) {
10466 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10467 bpp, connector->base.display_info.bpc*3);
10468 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10469 }
10470
10471 /* Clamp bpp to 8 on screens without EDID 1.4 */
10472 if (connector->base.display_info.bpc == 0 && bpp > 24) {
10473 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10474 bpp);
10475 pipe_config->pipe_bpp = 24;
10476 }
10477}
10478
4e53c2e0 10479static int
050f7aeb
DV		 10480compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10481 struct drm_framebuffer *fb,
5cec258b 10482 struct intel_crtc_state *pipe_config)
4e53c2e0 10483{
050f7aeb 10484 struct drm_device *dev = crtc->base.dev;
1486017f 10485 struct drm_atomic_state *state;
050f7aeb 10486 struct intel_connector *connector;
1486017f 10487 int bpp, i;
4e53c2e0 10488
d42264b1
DV		 10489 switch (fb->pixel_format) {
10490 case DRM_FORMAT_C8:
4e53c2e0
DV		 10491 bpp = 8*3; /* since we go through a colormap */
10492 break;
d42264b1
DV		 10493 case DRM_FORMAT_XRGB1555:
10494 case DRM_FORMAT_ARGB1555:
10495 /* checked in intel_framebuffer_init already */
10496 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10497 return -EINVAL;
10498 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 10499 bpp = 6*3; /* min is 18bpp */
10500 break;
d42264b1
DV		 10501 case DRM_FORMAT_XBGR8888:
10502 case DRM_FORMAT_ABGR8888:
10503 /* checked in intel_framebuffer_init already */
10504 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10505 return -EINVAL;
10506 case DRM_FORMAT_XRGB8888:
10507 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 10508 bpp = 8*3;
10509 break;
d42264b1
DV		 10510 case DRM_FORMAT_XRGB2101010:
10511 case DRM_FORMAT_ARGB2101010:
10512 case DRM_FORMAT_XBGR2101010:
10513 case DRM_FORMAT_ABGR2101010:
10514 /* checked in intel_framebuffer_init already */
10515 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 10516 return -EINVAL;
4e53c2e0
DV		 10517 bpp = 10*3;
10518 break;
baba133a 10519 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 10520 default:
10521 DRM_DEBUG_KMS("unsupported depth\n");
10522 return -EINVAL;
10523 }
10524
4e53c2e0
DV		 10525 pipe_config->pipe_bpp = bpp;
10526
1486017f
ACO		 10527 state = pipe_config->base.state;
10528
4e53c2e0 10529 /* Clamp display bpp to EDID value */
1486017f
ACO		 10530 for (i = 0; i < state->num_connector; i++) {
10531 if (!state->connectors[i])
10532 continue;
10533
10534 connector = to_intel_connector(state->connectors[i]);
10535 if (state->connector_states[i]->crtc != &crtc->base)
4e53c2e0
DV		 10536 continue;
10537
050f7aeb 10538 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 10539 }
10540
10541 return bpp;
10542}
10543
644db711
DV		 10544static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10545{
10546 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10547 "type: 0x%x flags: 0x%x\n",
1342830c 10548 mode->crtc_clock,
644db711
DV		 10549 mode->crtc_hdisplay, mode->crtc_hsync_start,
10550 mode->crtc_hsync_end, mode->crtc_htotal,
10551 mode->crtc_vdisplay, mode->crtc_vsync_start,
10552 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10553}
10554
c0b03411 10555static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 10556 struct intel_crtc_state *pipe_config,
c0b03411
DV		 10557 const char *context)
10558{
10559 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10560 context, pipe_name(crtc->pipe));
10561
10562 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10563 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10564 pipe_config->pipe_bpp, pipe_config->dither);
10565 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10566 pipe_config->has_pch_encoder,
10567 pipe_config->fdi_lanes,
10568 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10569 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10570 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 10571 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10572 pipe_config->has_dp_encoder,
10573 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10574 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10575 pipe_config->dp_m_n.tu);
b95af8be
VK		 10576
10577 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10578 pipe_config->has_dp_encoder,
10579 pipe_config->dp_m2_n2.gmch_m,
10580 pipe_config->dp_m2_n2.gmch_n,
10581 pipe_config->dp_m2_n2.link_m,
10582 pipe_config->dp_m2_n2.link_n,
10583 pipe_config->dp_m2_n2.tu);
10584
55072d19
DV		 10585 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10586 pipe_config->has_audio,
10587 pipe_config->has_infoframe);
10588
c0b03411 10589 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 10590 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 10591 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 10592 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10593 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 10594 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 10595 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10596 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
c0b03411
DV		 10597 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10598 pipe_config->gmch_pfit.control,
10599 pipe_config->gmch_pfit.pgm_ratios,
10600 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 10601 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 10602 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 10603 pipe_config->pch_pfit.size,
10604 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 10605 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 10606 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
c0b03411
DV		 10607}
10608
bc079e8b
VS		 10609static bool encoders_cloneable(const struct intel_encoder *a,
10610 const struct intel_encoder *b)
accfc0c5 10611{
bc079e8b
VS		 10612 /* masks could be asymmetric, so check both ways */
10613 return a == b || (a->cloneable & (1 << b->type) &&
10614 b->cloneable & (1 << a->type));
10615}
10616
10617static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10618 struct intel_encoder *encoder)
10619{
10620 struct drm_device *dev = crtc->base.dev;
10621 struct intel_encoder *source_encoder;
10622
b2784e15 10623 for_each_intel_encoder(dev, source_encoder) {
bc079e8b
VS		 10624 if (source_encoder->new_crtc != crtc)
10625 continue;
10626
10627 if (!encoders_cloneable(encoder, source_encoder))
10628 return false;
10629 }
10630
10631 return true;
10632}
10633
10634static bool check_encoder_cloning(struct intel_crtc *crtc)
10635{
10636 struct drm_device *dev = crtc->base.dev;
accfc0c5
DV		 10637 struct intel_encoder *encoder;
10638
b2784e15 10639 for_each_intel_encoder(dev, encoder) {
bc079e8b 10640 if (encoder->new_crtc != crtc)
accfc0c5
DV		 10641 continue;
10642
bc079e8b
VS		 10643 if (!check_single_encoder_cloning(crtc, encoder))
10644 return false;
accfc0c5
DV		 10645 }
10646
bc079e8b 10647 return true;
accfc0c5
DV		 10648}
10649
00f0b378
VS		 10650static bool check_digital_port_conflicts(struct drm_device *dev)
10651{
10652 struct intel_connector *connector;
10653 unsigned int used_ports = 0;
10654
10655 /*
10656 * Walk the connector list instead of the encoder
10657 * list to detect the problem on ddi platforms
10658 * where there's just one encoder per digital port.
10659 */
3a3371ff 10660 for_each_intel_connector(dev, connector) {
00f0b378
VS		 10661 struct intel_encoder *encoder = connector->new_encoder;
10662
10663 if (!encoder)
10664 continue;
10665
10666 WARN_ON(!encoder->new_crtc);
10667
10668 switch (encoder->type) {
10669 unsigned int port_mask;
10670 case INTEL_OUTPUT_UNKNOWN:
10671 if (WARN_ON(!HAS_DDI(dev)))
10672 break;
10673 case INTEL_OUTPUT_DISPLAYPORT:
10674 case INTEL_OUTPUT_HDMI:
10675 case INTEL_OUTPUT_EDP:
10676 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10677
10678 /* the same port mustn't appear more than once */
10679 if (used_ports & port_mask)
10680 return false;
10681
10682 used_ports |= port_mask;
10683 default:
10684 break;
10685 }
10686 }
10687
10688 return true;
10689}
10690
83a57153
ACO		 10691static void
10692clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
10693{
10694 struct drm_crtc_state tmp_state;
10695
10696 /* Clear only the intel specific part of the crtc state */
10697 tmp_state = crtc_state->base;
10698 memset(crtc_state, 0, sizeof *crtc_state);
10699 crtc_state->base = tmp_state;
10700}
10701
5cec258b 10702static struct intel_crtc_state *
b8cecdf5 10703intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 10704 struct drm_framebuffer *fb,
83a57153
ACO		 10705 struct drm_display_mode *mode,
10706 struct drm_atomic_state *state)
ee7b9f93 10707{
7758a113 10708 struct drm_device *dev = crtc->dev;
7758a113 10709 struct intel_encoder *encoder;
0b901879
ACO		 10710 struct intel_connector *connector;
10711 struct drm_connector_state *connector_state;
5cec258b 10712 struct intel_crtc_state *pipe_config;
e29c22c0 10713 int plane_bpp, ret = -EINVAL;
0b901879 10714 int i;
e29c22c0 10715 bool retry = true;
ee7b9f93 10716
bc079e8b 10717 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
accfc0c5
DV		 10718 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10719 return ERR_PTR(-EINVAL);
10720 }
10721
00f0b378
VS		 10722 if (!check_digital_port_conflicts(dev)) {
10723 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10724 return ERR_PTR(-EINVAL);
10725 }
10726
83a57153
ACO		 10727 pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
10728 if (IS_ERR(pipe_config))
10729 return pipe_config;
10730
10731 clear_intel_crtc_state(pipe_config);
7758a113 10732
07878248 10733 pipe_config->base.crtc = crtc;
2d112de7
ACO		 10734 drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
10735 drm_mode_copy(&pipe_config->base.mode, mode);
37327abd 10736
e143a21c
DV		 10737 pipe_config->cpu_transcoder =
10738 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 10739 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 10740
2960bc9c
ID		 10741 /*
10742 * Sanitize sync polarity flags based on requested ones. If neither
10743 * positive or negative polarity is requested, treat this as meaning
10744 * negative polarity.
10745 */
2d112de7 10746 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 10747 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 10748 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 10749
2d112de7 10750 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 10751 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 10752 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 10753
050f7aeb
DV		 10754 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10755 * plane pixel format and any sink constraints into account. Returns the
10756 * source plane bpp so that dithering can be selected on mismatches
10757 * after encoders and crtc also have had their say. */
10758 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10759 fb, pipe_config);
4e53c2e0
DV		 10760 if (plane_bpp < 0)
10761 goto fail;
10762
e41a56be
VS		 10763 /*
10764 * Determine the real pipe dimensions. Note that stereo modes can
10765 * increase the actual pipe size due to the frame doubling and
10766 * insertion of additional space for blanks between the frame. This
10767 * is stored in the crtc timings. We use the requested mode to do this
10768 * computation to clearly distinguish it from the adjusted mode, which
10769 * can be changed by the connectors in the below retry loop.
10770 */
2d112de7 10771 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 10772 &pipe_config->pipe_src_w,
10773 &pipe_config->pipe_src_h);
e41a56be 10774
e29c22c0 10775encoder_retry:
ef1b460d 10776 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 10777 pipe_config->port_clock = 0;
ef1b460d 10778 pipe_config->pixel_multiplier = 1;
ff9a6750 10779
135c81b8 10780 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 10781 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10782 CRTC_STEREO_DOUBLE);
135c81b8 10783
7758a113
DV		 10784 /* Pass our mode to the connectors and the CRTC to give them a chance to
10785 * adjust it according to limitations or connector properties, and also
10786 * a chance to reject the mode entirely.
47f1c6c9 10787 */
0b901879
ACO		 10788 for (i = 0; i < state->num_connector; i++) {
10789 connector = to_intel_connector(state->connectors[i]);
10790 if (!connector)
10791 continue;
47f1c6c9 10792
0b901879
ACO		 10793 connector_state = state->connector_states[i];
10794 if (connector_state->crtc != crtc)
7758a113 10795 continue;
7ae89233 10796
0b901879
ACO		 10797 encoder = to_intel_encoder(connector_state->best_encoder);
10798
efea6e8e
DV		 10799 if (!(encoder->compute_config(encoder, pipe_config))) {
10800 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 10801 goto fail;
10802 }
ee7b9f93 10803 }
47f1c6c9 10804
ff9a6750
DV		 10805 /* Set default port clock if not overwritten by the encoder. Needs to be
10806 * done afterwards in case the encoder adjusts the mode. */
10807 if (!pipe_config->port_clock)
2d112de7 10808 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 10809 * pipe_config->pixel_multiplier;
ff9a6750 10810
a43f6e0f 10811 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 10812 if (ret < 0) {
7758a113
DV		 10813 DRM_DEBUG_KMS("CRTC fixup failed\n");
10814 goto fail;
ee7b9f93 10815 }
e29c22c0
DV		 10816
10817 if (ret == RETRY) {
10818 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10819 ret = -EINVAL;
10820 goto fail;
10821 }
10822
10823 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10824 retry = false;
10825 goto encoder_retry;
10826 }
10827
4e53c2e0
DV		 10828 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10829 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10830 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10831
b8cecdf5 10832 return pipe_config;
7758a113 10833fail:
e29c22c0 10834 return ERR_PTR(ret);
ee7b9f93 10835}
47f1c6c9 10836
e2e1ed41
DV		 10837/* Computes which crtcs are affected and sets the relevant bits in the mask. For
10838 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10839static void
10840intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10841 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 10842{
10843 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 10844 struct drm_device *dev = crtc->dev;
10845 struct intel_encoder *encoder;
10846 struct intel_connector *connector;
10847 struct drm_crtc *tmp_crtc;
79e53945 10848
e2e1ed41 10849 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 10850
e2e1ed41
DV		 10851 /* Check which crtcs have changed outputs connected to them, these need
10852 * to be part of the prepare_pipes mask. We don't (yet) support global
10853 * modeset across multiple crtcs, so modeset_pipes will only have one
10854 * bit set at most. */
3a3371ff 10855 for_each_intel_connector(dev, connector) {
e2e1ed41
DV		 10856 if (connector->base.encoder == &connector->new_encoder->base)
10857 continue;
79e53945 10858
e2e1ed41
DV		 10859 if (connector->base.encoder) {
10860 tmp_crtc = connector->base.encoder->crtc;
10861
10862 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10863 }
10864
10865 if (connector->new_encoder)
10866 *prepare_pipes |=
10867 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 10868 }
10869
b2784e15 10870 for_each_intel_encoder(dev, encoder) {
e2e1ed41
DV		 10871 if (encoder->base.crtc == &encoder->new_crtc->base)
10872 continue;
10873
10874 if (encoder->base.crtc) {
10875 tmp_crtc = encoder->base.crtc;
10876
10877 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10878 }
10879
10880 if (encoder->new_crtc)
10881 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 10882 }
10883
7668851f 10884 /* Check for pipes that will be enabled/disabled ... */
d3fcc808 10885 for_each_intel_crtc(dev, intel_crtc) {
83d65738 10886 if (intel_crtc->base.state->enable == intel_crtc->new_enabled)
e2e1ed41 10887 continue;
7e7d76c3 10888
7668851f 10889 if (!intel_crtc->new_enabled)
e2e1ed41 10890 *disable_pipes |= 1 << intel_crtc->pipe;
7668851f
VS		 10891 else
10892 *prepare_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 10893 }
10894
e2e1ed41
DV		 10895
10896 /* set_mode is also used to update properties on life display pipes. */
10897 intel_crtc = to_intel_crtc(crtc);
7668851f 10898 if (intel_crtc->new_enabled)
e2e1ed41
DV		 10899 *prepare_pipes |= 1 << intel_crtc->pipe;
10900
b6c5164d
DV		 10901 /*
10902 * For simplicity do a full modeset on any pipe where the output routing
10903 * changed. We could be more clever, but that would require us to be
10904 * more careful with calling the relevant encoder->mode_set functions.
10905 */
e2e1ed41
DV		 10906 if (*prepare_pipes)
10907 *modeset_pipes = *prepare_pipes;
10908
10909 /* ... and mask these out. */
10910 *modeset_pipes &= ~(*disable_pipes);
10911 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 10912
10913 /*
10914 * HACK: We don't (yet) fully support global modesets. intel_set_config
10915 * obies this rule, but the modeset restore mode of
10916 * intel_modeset_setup_hw_state does not.
10917 */
10918 *modeset_pipes &= 1 << intel_crtc->pipe;
10919 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 10920
10921 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10922 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 10923}
79e53945 10924
ea9d758d 10925static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 10926{
ea9d758d 10927 struct drm_encoder *encoder;
f6e5b160 10928 struct drm_device *dev = crtc->dev;
f6e5b160 10929
ea9d758d
DV		 10930 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10931 if (encoder->crtc == crtc)
10932 return true;
10933
10934 return false;
10935}
10936
10937static void
10938intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10939{
ba41c0de 10940 struct drm_i915_private *dev_priv = dev->dev_private;
ea9d758d
DV		 10941 struct intel_encoder *intel_encoder;
10942 struct intel_crtc *intel_crtc;
10943 struct drm_connector *connector;
10944
ba41c0de
DV		 10945 intel_shared_dpll_commit(dev_priv);
10946
b2784e15 10947 for_each_intel_encoder(dev, intel_encoder) {
ea9d758d
DV		 10948 if (!intel_encoder->base.crtc)
10949 continue;
10950
10951 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10952
10953 if (prepare_pipes & (1 << intel_crtc->pipe))
10954 intel_encoder->connectors_active = false;
10955 }
10956
10957 intel_modeset_commit_output_state(dev);
10958
7668851f 10959 /* Double check state. */
d3fcc808 10960 for_each_intel_crtc(dev, intel_crtc) {
83d65738 10961 WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base));
7bd0a8e7 10962 WARN_ON(intel_crtc->new_config &&
6e3c9717 10963 intel_crtc->new_config != intel_crtc->config);
83d65738 10964 WARN_ON(intel_crtc->base.state->enable != !!intel_crtc->new_config);
ea9d758d
DV		 10965 }
10966
10967 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10968 if (!connector->encoder || !connector->encoder->crtc)
10969 continue;
10970
10971 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10972
10973 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 10974 struct drm_property *dpms_property =
10975 dev->mode_config.dpms_property;
10976
ea9d758d 10977 connector->dpms = DRM_MODE_DPMS_ON;
662595df 10978 drm_object_property_set_value(&connector->base,
68d34720
DV		 10979 dpms_property,
10980 DRM_MODE_DPMS_ON);
ea9d758d
DV		 10981
10982 intel_encoder = to_intel_encoder(connector->encoder);
10983 intel_encoder->connectors_active = true;
10984 }
10985 }
10986
10987}
10988
3bd26263 10989static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 10990{
3bd26263 10991 int diff;
f1f644dc
JB		 10992
10993 if (clock1 == clock2)
10994 return true;
10995
10996 if (!clock1 || !clock2)
10997 return false;
10998
10999 diff = abs(clock1 - clock2);
11000
11001 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11002 return true;
11003
11004 return false;
11005}
11006
25c5b266
DV		 11007#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
11008 list_for_each_entry((intel_crtc), \
11009 &(dev)->mode_config.crtc_list, \
11010 base.head) \
0973f18f 11011 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 11012
0e8ffe1b 11013static bool
2fa2fe9a 11014intel_pipe_config_compare(struct drm_device *dev,
5cec258b
ACO		 11015 struct intel_crtc_state *current_config,
11016 struct intel_crtc_state *pipe_config)
0e8ffe1b 11017{
66e985c0
DV		 11018#define PIPE_CONF_CHECK_X(name) \
11019 if (current_config->name != pipe_config->name) { \
11020 DRM_ERROR("mismatch in " #name " " \
11021 "(expected 0x%08x, found 0x%08x)\n", \
11022 current_config->name, \
11023 pipe_config->name); \
11024 return false; \
11025 }
11026
08a24034
DV		 11027#define PIPE_CONF_CHECK_I(name) \
11028 if (current_config->name != pipe_config->name) { \
11029 DRM_ERROR("mismatch in " #name " " \
11030 "(expected %i, found %i)\n", \
11031 current_config->name, \
11032 pipe_config->name); \
11033 return false; \
88adfff1
DV		 11034 }
11035
b95af8be
VK		 11036/* This is required for BDW+ where there is only one set of registers for
11037 * switching between high and low RR.
11038 * This macro can be used whenever a comparison has to be made between one
11039 * hw state and multiple sw state variables.
11040 */
11041#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
11042 if ((current_config->name != pipe_config->name) && \
11043 (current_config->alt_name != pipe_config->name)) { \
11044 DRM_ERROR("mismatch in " #name " " \
11045 "(expected %i or %i, found %i)\n", \
11046 current_config->name, \
11047 current_config->alt_name, \
11048 pipe_config->name); \
11049 return false; \
11050 }
11051
1bd1bd80
DV		 11052#define PIPE_CONF_CHECK_FLAGS(name, mask) \
11053 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 11054 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 11055 "(expected %i, found %i)\n", \
11056 current_config->name & (mask), \
11057 pipe_config->name & (mask)); \
11058 return false; \
11059 }
11060
5e550656
VS		 11061#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11062 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11063 DRM_ERROR("mismatch in " #name " " \
11064 "(expected %i, found %i)\n", \
11065 current_config->name, \
11066 pipe_config->name); \
11067 return false; \
11068 }
11069
bb760063
DV		 11070#define PIPE_CONF_QUIRK(quirk) \
11071 ((current_config->quirks | pipe_config->quirks) & (quirk))
11072
eccb140b
DV		 11073 PIPE_CONF_CHECK_I(cpu_transcoder);
11074
08a24034
DV		 11075 PIPE_CONF_CHECK_I(has_pch_encoder);
11076 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 11077 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
11078 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
11079 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
11080 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
11081 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 11082
eb14cb74 11083 PIPE_CONF_CHECK_I(has_dp_encoder);
b95af8be
VK		 11084
11085 if (INTEL_INFO(dev)->gen < 8) {
11086 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
11087 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
11088 PIPE_CONF_CHECK_I(dp_m_n.link_m);
11089 PIPE_CONF_CHECK_I(dp_m_n.link_n);
11090 PIPE_CONF_CHECK_I(dp_m_n.tu);
11091
11092 if (current_config->has_drrs) {
11093 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
11094 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
11095 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
11096 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
11097 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
11098 }
11099 } else {
11100 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
11101 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
11102 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
11103 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
11104 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
11105 }
eb14cb74 11106
2d112de7
ACO		 11107 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11108 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11109 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11110 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11111 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11112 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 11113
2d112de7
ACO		 11114 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11115 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11116 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11117 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11118 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11119 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 11120
c93f54cf 11121 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 11122 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 11123 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
11124 IS_VALLEYVIEW(dev))
11125 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 11126 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 11127
9ed109a7
DV		 11128 PIPE_CONF_CHECK_I(has_audio);
11129
2d112de7 11130 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 11131 DRM_MODE_FLAG_INTERLACE);
11132
bb760063 11133 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 11134 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 11135 DRM_MODE_FLAG_PHSYNC);
2d112de7 11136 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 11137 DRM_MODE_FLAG_NHSYNC);
2d112de7 11138 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 11139 DRM_MODE_FLAG_PVSYNC);
2d112de7 11140 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 11141 DRM_MODE_FLAG_NVSYNC);
11142 }
045ac3b5 11143
37327abd
VS		 11144 PIPE_CONF_CHECK_I(pipe_src_w);
11145 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 11146
9953599b
DV		 11147 /*
11148 * FIXME: BIOS likes to set up a cloned config with lvds+external
11149 * screen. Since we don't yet re-compute the pipe config when moving
11150 * just the lvds port away to another pipe the sw tracking won't match.
11151 *
11152 * Proper atomic modesets with recomputed global state will fix this.
11153 * Until then just don't check gmch state for inherited modes.
11154 */
11155 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
11156 PIPE_CONF_CHECK_I(gmch_pfit.control);
11157 /* pfit ratios are autocomputed by the hw on gen4+ */
11158 if (INTEL_INFO(dev)->gen < 4)
11159 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
11160 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
11161 }
11162
fd4daa9c
CW		 11163 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11164 if (current_config->pch_pfit.enabled) {
11165 PIPE_CONF_CHECK_I(pch_pfit.pos);
11166 PIPE_CONF_CHECK_I(pch_pfit.size);
11167 }
2fa2fe9a 11168
e59150dc
JB		 11169 /* BDW+ don't expose a synchronous way to read the state */
11170 if (IS_HASWELL(dev))
11171 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 11172
282740f7
VS		 11173 PIPE_CONF_CHECK_I(double_wide);
11174
26804afd
DV		 11175 PIPE_CONF_CHECK_X(ddi_pll_sel);
11176
c0d43d62 11177 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 11178 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 11179 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 11180 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11181 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 11182 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 11183 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11184 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11185 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 11186
42571aef
VS		 11187 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
11188 PIPE_CONF_CHECK_I(pipe_bpp);
11189
2d112de7 11190 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 11191 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 11192
66e985c0 11193#undef PIPE_CONF_CHECK_X
08a24034 11194#undef PIPE_CONF_CHECK_I
b95af8be 11195#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 11196#undef PIPE_CONF_CHECK_FLAGS
5e550656 11197#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 11198#undef PIPE_CONF_QUIRK
88adfff1 11199
0e8ffe1b
DV		 11200 return true;
11201}
11202
08db6652
DL		 11203static void check_wm_state(struct drm_device *dev)
11204{
11205 struct drm_i915_private *dev_priv = dev->dev_private;
11206 struct skl_ddb_allocation hw_ddb, *sw_ddb;
11207 struct intel_crtc *intel_crtc;
11208 int plane;
11209
11210 if (INTEL_INFO(dev)->gen < 9)
11211 return;
11212
11213 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11214 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11215
11216 for_each_intel_crtc(dev, intel_crtc) {
11217 struct skl_ddb_entry *hw_entry, *sw_entry;
11218 const enum pipe pipe = intel_crtc->pipe;
11219
11220 if (!intel_crtc->active)
11221 continue;
11222
11223 /* planes */
dd740780 11224 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 11225 hw_entry = &hw_ddb.plane[pipe][plane];
11226 sw_entry = &sw_ddb->plane[pipe][plane];
11227
11228 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11229 continue;
11230
11231 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
11232 "(expected (%u,%u), found (%u,%u))\n",
11233 pipe_name(pipe), plane + 1,
11234 sw_entry->start, sw_entry->end,
11235 hw_entry->start, hw_entry->end);
11236 }
11237
11238 /* cursor */
11239 hw_entry = &hw_ddb.cursor[pipe];
11240 sw_entry = &sw_ddb->cursor[pipe];
11241
11242 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11243 continue;
11244
11245 DRM_ERROR("mismatch in DDB state pipe %c cursor "
11246 "(expected (%u,%u), found (%u,%u))\n",
11247 pipe_name(pipe),
11248 sw_entry->start, sw_entry->end,
11249 hw_entry->start, hw_entry->end);
11250 }
11251}
11252
91d1b4bd
DV		 11253static void
11254check_connector_state(struct drm_device *dev)
8af6cf88 11255{
8af6cf88
DV		 11256 struct intel_connector *connector;
11257
3a3371ff 11258 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 11259 /* This also checks the encoder/connector hw state with the
11260 * ->get_hw_state callbacks. */
11261 intel_connector_check_state(connector);
11262
e2c719b7 11263 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
8af6cf88
DV		 11264 "connector's staged encoder doesn't match current encoder\n");
11265 }
91d1b4bd
DV		 11266}
11267
11268static void
11269check_encoder_state(struct drm_device *dev)
11270{
11271 struct intel_encoder *encoder;
11272 struct intel_connector *connector;
8af6cf88 11273
b2784e15 11274 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 11275 bool enabled = false;
11276 bool active = false;
11277 enum pipe pipe, tracked_pipe;
11278
11279 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11280 encoder->base.base.id,
8e329a03 11281 encoder->base.name);
8af6cf88 11282
e2c719b7 11283 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
8af6cf88 11284 "encoder's stage crtc doesn't match current crtc\n");
e2c719b7 11285 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
8af6cf88
DV		 11286 "encoder's active_connectors set, but no crtc\n");
11287
3a3371ff 11288 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 11289 if (connector->base.encoder != &encoder->base)
11290 continue;
11291 enabled = true;
11292 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
11293 active = true;
11294 }
0e32b39c
DA		 11295 /*
11296 * for MST connectors if we unplug the connector is gone
11297 * away but the encoder is still connected to a crtc
11298 * until a modeset happens in response to the hotplug.
11299 */
11300 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
11301 continue;
11302
e2c719b7 11303 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 11304 "encoder's enabled state mismatch "
11305 "(expected %i, found %i)\n",
11306 !!encoder->base.crtc, enabled);
e2c719b7 11307 I915_STATE_WARN(active && !encoder->base.crtc,
8af6cf88
DV		 11308 "active encoder with no crtc\n");
11309
e2c719b7 11310 I915_STATE_WARN(encoder->connectors_active != active,
8af6cf88
DV		 11311 "encoder's computed active state doesn't match tracked active state "
11312 "(expected %i, found %i)\n", active, encoder->connectors_active);
11313
11314 active = encoder->get_hw_state(encoder, &pipe);
e2c719b7 11315 I915_STATE_WARN(active != encoder->connectors_active,
8af6cf88
DV		 11316 "encoder's hw state doesn't match sw tracking "
11317 "(expected %i, found %i)\n",
11318 encoder->connectors_active, active);
11319
11320 if (!encoder->base.crtc)
11321 continue;
11322
11323 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
e2c719b7 11324 I915_STATE_WARN(active && pipe != tracked_pipe,
8af6cf88
DV		 11325 "active encoder's pipe doesn't match"
11326 "(expected %i, found %i)\n",
11327 tracked_pipe, pipe);
11328
11329 }
91d1b4bd
DV		 11330}
11331
11332static void
11333check_crtc_state(struct drm_device *dev)
11334{
fbee40df 11335 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 11336 struct intel_crtc *crtc;
11337 struct intel_encoder *encoder;
5cec258b 11338 struct intel_crtc_state pipe_config;
8af6cf88 11339
d3fcc808 11340 for_each_intel_crtc(dev, crtc) {
8af6cf88
DV		 11341 bool enabled = false;
11342 bool active = false;
11343
045ac3b5
JB		 11344 memset(&pipe_config, 0, sizeof(pipe_config));
11345
8af6cf88
DV		 11346 DRM_DEBUG_KMS("[CRTC:%d]\n",
11347 crtc->base.base.id);
11348
83d65738 11349 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
8af6cf88
DV		 11350 "active crtc, but not enabled in sw tracking\n");
11351
b2784e15 11352 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 11353 if (encoder->base.crtc != &crtc->base)
11354 continue;
11355 enabled = true;
11356 if (encoder->connectors_active)
11357 active = true;
11358 }
6c49f241 11359
e2c719b7 11360 I915_STATE_WARN(active != crtc->active,
8af6cf88
DV		 11361 "crtc's computed active state doesn't match tracked active state "
11362 "(expected %i, found %i)\n", active, crtc->active);
83d65738 11363 I915_STATE_WARN(enabled != crtc->base.state->enable,
8af6cf88 11364 "crtc's computed enabled state doesn't match tracked enabled state "
83d65738
MR		 11365 "(expected %i, found %i)\n", enabled,
11366 crtc->base.state->enable);
8af6cf88 11367
0e8ffe1b
DV		 11368 active = dev_priv->display.get_pipe_config(crtc,
11369 &pipe_config);
d62cf62a 11370
b6b5d049
VS		 11371 /* hw state is inconsistent with the pipe quirk */
11372 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
11373 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
d62cf62a
DV		 11374 active = crtc->active;
11375
b2784e15 11376 for_each_intel_encoder(dev, encoder) {
3eaba51c 11377 enum pipe pipe;
6c49f241
DV		 11378 if (encoder->base.crtc != &crtc->base)
11379 continue;
1d37b689 11380 if (encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 11381 encoder->get_config(encoder, &pipe_config);
11382 }
11383
e2c719b7 11384 I915_STATE_WARN(crtc->active != active,
0e8ffe1b
DV		 11385 "crtc active state doesn't match with hw state "
11386 "(expected %i, found %i)\n", crtc->active, active);
11387
c0b03411 11388 if (active &&
6e3c9717 11389 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
e2c719b7 11390 I915_STATE_WARN(1, "pipe state doesn't match!\n");
c0b03411
DV		 11391 intel_dump_pipe_config(crtc, &pipe_config,
11392 "[hw state]");
6e3c9717 11393 intel_dump_pipe_config(crtc, crtc->config,
c0b03411
DV		 11394 "[sw state]");
11395 }
8af6cf88
DV		 11396 }
11397}
11398
91d1b4bd
DV		 11399static void
11400check_shared_dpll_state(struct drm_device *dev)
11401{
fbee40df 11402 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 11403 struct intel_crtc *crtc;
11404 struct intel_dpll_hw_state dpll_hw_state;
11405 int i;
5358901f
DV		 11406
11407 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11408 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11409 int enabled_crtcs = 0, active_crtcs = 0;
11410 bool active;
11411
11412 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11413
11414 DRM_DEBUG_KMS("%s\n", pll->name);
11415
11416 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
11417
e2c719b7 11418 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 11419 "more active pll users than references: %i vs %i\n",
3e369b76 11420 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 11421 I915_STATE_WARN(pll->active && !pll->on,
5358901f 11422 "pll in active use but not on in sw tracking\n");
e2c719b7 11423 I915_STATE_WARN(pll->on && !pll->active,
35c95375 11424 "pll in on but not on in use in sw tracking\n");
e2c719b7 11425 I915_STATE_WARN(pll->on != active,
5358901f
DV		 11426 "pll on state mismatch (expected %i, found %i)\n",
11427 pll->on, active);
11428
d3fcc808 11429 for_each_intel_crtc(dev, crtc) {
83d65738 11430 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 11431 enabled_crtcs++;
11432 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11433 active_crtcs++;
11434 }
e2c719b7 11435 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 11436 "pll active crtcs mismatch (expected %i, found %i)\n",
11437 pll->active, active_crtcs);
e2c719b7 11438 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 11439 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 11440 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 11441
e2c719b7 11442 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 11443 sizeof(dpll_hw_state)),
11444 "pll hw state mismatch\n");
5358901f 11445 }
8af6cf88
DV		 11446}
11447
91d1b4bd
DV		 11448void
11449intel_modeset_check_state(struct drm_device *dev)
11450{
08db6652 11451 check_wm_state(dev);
91d1b4bd
DV		 11452 check_connector_state(dev);
11453 check_encoder_state(dev);
11454 check_crtc_state(dev);
11455 check_shared_dpll_state(dev);
11456}
11457
5cec258b 11458void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 11459 int dotclock)
11460{
11461 /*
11462 * FDI already provided one idea for the dotclock.
11463 * Yell if the encoder disagrees.
11464 */
2d112de7 11465 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 11466 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 11467 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 11468}
11469
80715b2f
VS		 11470static void update_scanline_offset(struct intel_crtc *crtc)
11471{
11472 struct drm_device *dev = crtc->base.dev;
11473
11474 /*
11475 * The scanline counter increments at the leading edge of hsync.
11476 *
11477 * On most platforms it starts counting from vtotal-1 on the
11478 * first active line. That means the scanline counter value is
11479 * always one less than what we would expect. Ie. just after
11480 * start of vblank, which also occurs at start of hsync (on the
11481 * last active line), the scanline counter will read vblank_start-1.
11482 *
11483 * On gen2 the scanline counter starts counting from 1 instead
11484 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11485 * to keep the value positive), instead of adding one.
11486 *
11487 * On HSW+ the behaviour of the scanline counter depends on the output
11488 * type. For DP ports it behaves like most other platforms, but on HDMI
11489 * there's an extra 1 line difference. So we need to add two instead of
11490 * one to the value.
11491 */
11492 if (IS_GEN2(dev)) {
6e3c9717 11493 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 11494 int vtotal;
11495
11496 vtotal = mode->crtc_vtotal;
11497 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
11498 vtotal /= 2;
11499
11500 crtc->scanline_offset = vtotal - 1;
11501 } else if (HAS_DDI(dev) &&
409ee761 11502 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 11503 crtc->scanline_offset = 2;
11504 } else
11505 crtc->scanline_offset = 1;
11506}
11507
5cec258b 11508static struct intel_crtc_state *
7f27126e
JB		 11509intel_modeset_compute_config(struct drm_crtc *crtc,
11510 struct drm_display_mode *mode,
11511 struct drm_framebuffer *fb,
83a57153 11512 struct drm_atomic_state *state,
7f27126e
JB		 11513 unsigned *modeset_pipes,
11514 unsigned *prepare_pipes,
11515 unsigned *disable_pipes)
11516{
db7542dd 11517 struct drm_device *dev = crtc->dev;
5cec258b 11518 struct intel_crtc_state *pipe_config = NULL;
db7542dd 11519 struct intel_crtc *intel_crtc;
0b901879
ACO		 11520 int ret = 0;
11521
11522 ret = drm_atomic_add_affected_connectors(state, crtc);
11523 if (ret)
11524 return ERR_PTR(ret);
7f27126e
JB		 11525
11526 intel_modeset_affected_pipes(crtc, modeset_pipes,
11527 prepare_pipes, disable_pipes);
11528
db7542dd
ACO		 11529 for_each_intel_crtc_masked(dev, *disable_pipes, intel_crtc) {
11530 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
11531 if (IS_ERR(pipe_config))
11532 return pipe_config;
11533
11534 pipe_config->base.enable = false;
11535 }
7f27126e
JB		 11536
11537 /*
11538 * Note this needs changes when we start tracking multiple modes
11539 * and crtcs. At that point we'll need to compute the whole config
11540 * (i.e. one pipe_config for each crtc) rather than just the one
11541 * for this crtc.
11542 */
db7542dd
ACO		 11543 for_each_intel_crtc_masked(dev, *modeset_pipes, intel_crtc) {
11544 /* FIXME: For now we still expect modeset_pipes has at most
11545 * one bit set. */
11546 if (WARN_ON(&intel_crtc->base != crtc))
11547 continue;
83a57153 11548
db7542dd
ACO		 11549 pipe_config = intel_modeset_pipe_config(crtc, fb, mode, state);
11550 if (IS_ERR(pipe_config))
11551 return pipe_config;
7f27126e 11552
db7542dd
ACO		 11553 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11554 "[modeset]");
11555 }
11556
11557 return intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));;
7f27126e
JB		 11558}
11559
ed6739ef
ACO		 11560static int __intel_set_mode_setup_plls(struct drm_device *dev,
11561 unsigned modeset_pipes,
11562 unsigned disable_pipes)
11563{
11564 struct drm_i915_private *dev_priv = to_i915(dev);
11565 unsigned clear_pipes = modeset_pipes | disable_pipes;
11566 struct intel_crtc *intel_crtc;
11567 int ret = 0;
11568
11569 if (!dev_priv->display.crtc_compute_clock)
11570 return 0;
11571
11572 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
11573 if (ret)
11574 goto done;
11575
11576 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11577 struct intel_crtc_state *state = intel_crtc->new_config;
11578 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11579 state);
11580 if (ret) {
11581 intel_shared_dpll_abort_config(dev_priv);
11582 goto done;
11583 }
11584 }
11585
11586done:
11587 return ret;
11588}
11589
f30da187
DV		 11590static int __intel_set_mode(struct drm_crtc *crtc,
11591 struct drm_display_mode *mode,
7f27126e 11592 int x, int y, struct drm_framebuffer *fb,
5cec258b 11593 struct intel_crtc_state *pipe_config,
7f27126e
JB		 11594 unsigned modeset_pipes,
11595 unsigned prepare_pipes,
11596 unsigned disable_pipes)
a6778b3c
DV		 11597{
11598 struct drm_device *dev = crtc->dev;
fbee40df 11599 struct drm_i915_private *dev_priv = dev->dev_private;
4b4b9238 11600 struct drm_display_mode *saved_mode;
83a57153 11601 struct intel_crtc_state *crtc_state_copy = NULL;
25c5b266 11602 struct intel_crtc *intel_crtc;
c0c36b94 11603 int ret = 0;
a6778b3c 11604
4b4b9238 11605 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 11606 if (!saved_mode)
11607 return -ENOMEM;
a6778b3c 11608
83a57153
ACO		 11609 crtc_state_copy = kmalloc(sizeof(*crtc_state_copy), GFP_KERNEL);
11610 if (!crtc_state_copy) {
11611 ret = -ENOMEM;
11612 goto done;
11613 }
11614
3ac18232 11615 *saved_mode = crtc->mode;
a6778b3c 11616
b9950a13
VS		 11617 if (modeset_pipes)
11618 to_intel_crtc(crtc)->new_config = pipe_config;
11619
30a970c6
JB		 11620 /*
11621 * See if the config requires any additional preparation, e.g.
11622 * to adjust global state with pipes off. We need to do this
11623 * here so we can get the modeset_pipe updated config for the new
11624 * mode set on this crtc. For other crtcs we need to use the
11625 * adjusted_mode bits in the crtc directly.
11626 */
c164f833 11627 if (IS_VALLEYVIEW(dev)) {
2f2d7aa1 11628 valleyview_modeset_global_pipes(dev, &prepare_pipes);
30a970c6 11629
c164f833
VS		 11630 /* may have added more to prepare_pipes than we should */
11631 prepare_pipes &= ~disable_pipes;
11632 }
11633
ed6739ef
ACO		 11634 ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
11635 if (ret)
11636 goto done;
8bd31e67 11637
460da916
DV		 11638 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11639 intel_crtc_disable(&intel_crtc->base);
11640
ea9d758d 11641 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
83d65738 11642 if (intel_crtc->base.state->enable)
ea9d758d
DV		 11643 dev_priv->display.crtc_disable(&intel_crtc->base);
11644 }
a6778b3c 11645
6c4c86f5
DV		 11646 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11647 * to set it here already despite that we pass it down the callchain.
7f27126e
JB		 11648 *
11649 * Note we'll need to fix this up when we start tracking multiple
11650 * pipes; here we assume a single modeset_pipe and only track the
11651 * single crtc and mode.
f6e5b160 11652 */
b8cecdf5 11653 if (modeset_pipes) {
25c5b266 11654 crtc->mode = *mode;
b8cecdf5
DV		 11655 /* mode_set/enable/disable functions rely on a correct pipe
11656 * config. */
f5de6e07 11657 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
c326c0a9
VS		 11658
11659 /*
11660 * Calculate and store various constants which
11661 * are later needed by vblank and swap-completion
11662 * timestamping. They are derived from true hwmode.
11663 */
11664 drm_calc_timestamping_constants(crtc,
2d112de7 11665 &pipe_config->base.adjusted_mode);
b8cecdf5 11666 }
7758a113 11667
ea9d758d
DV		 11668 /* Only after disabling all output pipelines that will be changed can we
11669 * update the the output configuration. */
11670 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 11671
679dacd4 11672 modeset_update_crtc_power_domains(pipe_config->base.state);
47fab737 11673
a6778b3c
DV		 11674 /* Set up the DPLL and any encoders state that needs to adjust or depend
11675 * on the DPLL.
f6e5b160 11676 */
25c5b266 11677 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
455a6808
GP		 11678 struct drm_plane *primary = intel_crtc->base.primary;
11679 int vdisplay, hdisplay;
4c10794f 11680
455a6808
GP		 11681 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11682 ret = primary->funcs->update_plane(primary, &intel_crtc->base,
11683 fb, 0, 0,
11684 hdisplay, vdisplay,
11685 x << 16, y << 16,
11686 hdisplay << 16, vdisplay << 16);
a6778b3c
DV		 11687 }
11688
11689 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
80715b2f
VS		 11690 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11691 update_scanline_offset(intel_crtc);
11692
25c5b266 11693 dev_priv->display.crtc_enable(&intel_crtc->base);
80715b2f 11694 }
a6778b3c 11695
a6778b3c
DV		 11696 /* FIXME: add subpixel order */
11697done:
83d65738 11698 if (ret && crtc->state->enable)
3ac18232 11699 crtc->mode = *saved_mode;
a6778b3c 11700
83a57153
ACO		 11701 if (ret == 0 && pipe_config) {
11702 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11703
11704 /* The pipe_config will be freed with the atomic state, so
11705 * make a copy. */
11706 memcpy(crtc_state_copy, intel_crtc->config,
11707 sizeof *crtc_state_copy);
11708 intel_crtc->config = crtc_state_copy;
11709 intel_crtc->base.state = &crtc_state_copy->base;
11710
11711 if (modeset_pipes)
11712 intel_crtc->new_config = intel_crtc->config;
11713 } else {
11714 kfree(crtc_state_copy);
11715 }
11716
3ac18232 11717 kfree(saved_mode);
a6778b3c 11718 return ret;
f6e5b160
CW		 11719}
11720
7f27126e
JB		 11721static int intel_set_mode_pipes(struct drm_crtc *crtc,
11722 struct drm_display_mode *mode,
11723 int x, int y, struct drm_framebuffer *fb,
5cec258b 11724 struct intel_crtc_state *pipe_config,
7f27126e
JB		 11725 unsigned modeset_pipes,
11726 unsigned prepare_pipes,
11727 unsigned disable_pipes)
f30da187
DV		 11728{
11729 int ret;
11730
7f27126e
JB		 11731 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11732 prepare_pipes, disable_pipes);
f30da187
DV		 11733
11734 if (ret == 0)
11735 intel_modeset_check_state(crtc->dev);
11736
11737 return ret;
11738}
11739
7f27126e
JB		 11740static int intel_set_mode(struct drm_crtc *crtc,
11741 struct drm_display_mode *mode,
83a57153
ACO		 11742 int x, int y, struct drm_framebuffer *fb,
11743 struct drm_atomic_state *state)
7f27126e 11744{
5cec258b 11745 struct intel_crtc_state *pipe_config;
7f27126e 11746 unsigned modeset_pipes, prepare_pipes, disable_pipes;
83a57153 11747 int ret = 0;
7f27126e 11748
83a57153 11749 pipe_config = intel_modeset_compute_config(crtc, mode, fb, state,
7f27126e
JB		 11750 &modeset_pipes,
11751 &prepare_pipes,
11752 &disable_pipes);
11753
83a57153
ACO		 11754 if (IS_ERR(pipe_config)) {
11755 ret = PTR_ERR(pipe_config);
11756 goto out;
11757 }
11758
11759 ret = intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11760 modeset_pipes, prepare_pipes,
11761 disable_pipes);
11762 if (ret)
11763 goto out;
7f27126e 11764
83a57153
ACO		 11765out:
11766 return ret;
7f27126e
JB		 11767}
11768
c0c36b94
CW		 11769void intel_crtc_restore_mode(struct drm_crtc *crtc)
11770{
83a57153
ACO		 11771 struct drm_device *dev = crtc->dev;
11772 struct drm_atomic_state *state;
11773 struct intel_encoder *encoder;
11774 struct intel_connector *connector;
11775 struct drm_connector_state *connector_state;
11776
11777 state = drm_atomic_state_alloc(dev);
11778 if (!state) {
11779 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
11780 crtc->base.id);
11781 return;
11782 }
11783
11784 state->acquire_ctx = dev->mode_config.acquire_ctx;
11785
11786 /* The force restore path in the HW readout code relies on the staged
11787 * config still keeping the user requested config while the actual
11788 * state has been overwritten by the configuration read from HW. We
11789 * need to copy the staged config to the atomic state, otherwise the
11790 * mode set will just reapply the state the HW is already in. */
11791 for_each_intel_encoder(dev, encoder) {
11792 if (&encoder->new_crtc->base != crtc)
11793 continue;
11794
11795 for_each_intel_connector(dev, connector) {
11796 if (connector->new_encoder != encoder)
11797 continue;
11798
11799 connector_state = drm_atomic_get_connector_state(state, &connector->base);
11800 if (IS_ERR(connector_state)) {
11801 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
11802 connector->base.base.id,
11803 connector->base.name,
11804 PTR_ERR(connector_state));
11805 continue;
11806 }
11807
11808 connector_state->crtc = crtc;
11809 connector_state->best_encoder = &encoder->base;
11810 }
11811 }
11812
11813 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb,
11814 state);
11815
11816 drm_atomic_state_free(state);
c0c36b94
CW		 11817}
11818
25c5b266
DV		 11819#undef for_each_intel_crtc_masked
11820
d9e55608
DV		 11821static void intel_set_config_free(struct intel_set_config *config)
11822{
11823 if (!config)
11824 return;
11825
1aa4b628
DV		 11826 kfree(config->save_connector_encoders);
11827 kfree(config->save_encoder_crtcs);
7668851f 11828 kfree(config->save_crtc_enabled);
d9e55608
DV		 11829 kfree(config);
11830}
11831
85f9eb71
DV		 11832static int intel_set_config_save_state(struct drm_device *dev,
11833 struct intel_set_config *config)
11834{
7668851f 11835 struct drm_crtc *crtc;
85f9eb71
DV		 11836 struct drm_encoder *encoder;
11837 struct drm_connector *connector;
11838 int count;
11839
7668851f
VS		 11840 config->save_crtc_enabled =
11841 kcalloc(dev->mode_config.num_crtc,
11842 sizeof(bool), GFP_KERNEL);
11843 if (!config->save_crtc_enabled)
11844 return -ENOMEM;
11845
1aa4b628
DV		 11846 config->save_encoder_crtcs =
11847 kcalloc(dev->mode_config.num_encoder,
11848 sizeof(struct drm_crtc *), GFP_KERNEL);
11849 if (!config->save_encoder_crtcs)
85f9eb71
DV		 11850 return -ENOMEM;
11851
1aa4b628
DV		 11852 config->save_connector_encoders =
11853 kcalloc(dev->mode_config.num_connector,
11854 sizeof(struct drm_encoder *), GFP_KERNEL);
11855 if (!config->save_connector_encoders)
85f9eb71
DV		 11856 return -ENOMEM;
11857
11858 /* Copy data. Note that driver private data is not affected.
11859 * Should anything bad happen only the expected state is
11860 * restored, not the drivers personal bookkeeping.
11861 */
7668851f 11862 count = 0;
70e1e0ec 11863 for_each_crtc(dev, crtc) {
83d65738 11864 config->save_crtc_enabled[count++] = crtc->state->enable;
7668851f
VS		 11865 }
11866
85f9eb71
DV		 11867 count = 0;
11868 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 11869 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 11870 }
11871
11872 count = 0;
11873 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 11874 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 11875 }
11876
11877 return 0;
11878}
11879
11880static void intel_set_config_restore_state(struct drm_device *dev,
11881 struct intel_set_config *config)
11882{
7668851f 11883 struct intel_crtc *crtc;
9a935856
DV		 11884 struct intel_encoder *encoder;
11885 struct intel_connector *connector;
85f9eb71
DV		 11886 int count;
11887
7668851f 11888 count = 0;
d3fcc808 11889 for_each_intel_crtc(dev, crtc) {
7668851f 11890 crtc->new_enabled = config->save_crtc_enabled[count++];
7bd0a8e7
VS		 11891
11892 if (crtc->new_enabled)
6e3c9717 11893 crtc->new_config = crtc->config;
7bd0a8e7
VS		 11894 else
11895 crtc->new_config = NULL;
7668851f
VS		 11896 }
11897
85f9eb71 11898 count = 0;
b2784e15 11899 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 11900 encoder->new_crtc =
11901 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 11902 }
11903
11904 count = 0;
3a3371ff 11905 for_each_intel_connector(dev, connector) {
9a935856
DV		 11906 connector->new_encoder =
11907 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 11908 }
11909}
11910
e3de42b6 11911static bool
2e57f47d 11912is_crtc_connector_off(struct drm_mode_set *set)
e3de42b6
ID		 11913{
11914 int i;
11915
2e57f47d
CW		 11916 if (set->num_connectors == 0)
11917 return false;
11918
11919 if (WARN_ON(set->connectors == NULL))
11920 return false;
11921
11922 for (i = 0; i < set->num_connectors; i++)
11923 if (set->connectors[i]->encoder &&
11924 set->connectors[i]->encoder->crtc == set->crtc &&
11925 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
e3de42b6
ID		 11926 return true;
11927
11928 return false;
11929}
11930
5e2b584e
DV		 11931static void
11932intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11933 struct intel_set_config *config)
11934{
11935
11936 /* We should be able to check here if the fb has the same properties
11937 * and then just flip_or_move it */
2e57f47d
CW		 11938 if (is_crtc_connector_off(set)) {
11939 config->mode_changed = true;
f4510a27 11940 } else if (set->crtc->primary->fb != set->fb) {
3b150f08
MR		 11941 /*
11942 * If we have no fb, we can only flip as long as the crtc is
11943 * active, otherwise we need a full mode set. The crtc may
11944 * be active if we've only disabled the primary plane, or
11945 * in fastboot situations.
11946 */
f4510a27 11947 if (set->crtc->primary->fb == NULL) {
319d9827
JB		 11948 struct intel_crtc *intel_crtc =
11949 to_intel_crtc(set->crtc);
11950
3b150f08 11951 if (intel_crtc->active) {
319d9827
JB		 11952 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11953 config->fb_changed = true;
11954 } else {
11955 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11956 config->mode_changed = true;
11957 }
5e2b584e
DV		 11958 } else if (set->fb == NULL) {
11959 config->mode_changed = true;
72f4901e 11960 } else if (set->fb->pixel_format !=
f4510a27 11961 set->crtc->primary->fb->pixel_format) {
5e2b584e 11962 config->mode_changed = true;
e3de42b6 11963 } else {
5e2b584e 11964 config->fb_changed = true;
e3de42b6 11965 }
5e2b584e
DV		 11966 }
11967
835c5873 11968 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 11969 config->fb_changed = true;
11970
11971 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11972 DRM_DEBUG_KMS("modes are different, full mode set\n");
11973 drm_mode_debug_printmodeline(&set->crtc->mode);
11974 drm_mode_debug_printmodeline(set->mode);
11975 config->mode_changed = true;
11976 }
a1d95703
CW		 11977
11978 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11979 set->crtc->base.id, config->mode_changed, config->fb_changed);
5e2b584e
DV		 11980}
11981
2e431051 11982static int
9a935856
DV		 11983intel_modeset_stage_output_state(struct drm_device *dev,
11984 struct drm_mode_set *set,
944b0c76
ACO		 11985 struct intel_set_config *config,
11986 struct drm_atomic_state *state)
50f56119 11987{
9a935856 11988 struct intel_connector *connector;
944b0c76 11989 struct drm_connector_state *connector_state;
9a935856 11990 struct intel_encoder *encoder;
7668851f 11991 struct intel_crtc *crtc;
f3f08572 11992 int ro;
50f56119 11993
9abdda74 11994 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 11995 * of connectors. For paranoia, double-check this. */
11996 WARN_ON(!set->fb && (set->num_connectors != 0));
11997 WARN_ON(set->fb && (set->num_connectors == 0));
11998
3a3371ff 11999 for_each_intel_connector(dev, connector) {
9a935856
DV		 12000 /* Otherwise traverse passed in connector list and get encoders
12001 * for them. */
50f56119 12002 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 12003 if (set->connectors[ro] == &connector->base) {
0e32b39c 12004 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
50f56119
DV		 12005 break;
12006 }
12007 }
12008
9a935856
DV		 12009 /* If we disable the crtc, disable all its connectors. Also, if
12010 * the connector is on the changing crtc but not on the new
12011 * connector list, disable it. */
12012 if ((!set->fb || ro == set->num_connectors) &&
12013 connector->base.encoder &&
12014 connector->base.encoder->crtc == set->crtc) {
12015 connector->new_encoder = NULL;
12016
12017 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
12018 connector->base.base.id,
c23cc417 12019 connector->base.name);
9a935856
DV		 12020 }
12021
12022
12023 if (&connector->new_encoder->base != connector->base.encoder) {
10634189
ACO		 12024 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n",
12025 connector->base.base.id,
12026 connector->base.name);
5e2b584e 12027 config->mode_changed = true;
50f56119
DV		 12028 }
12029 }
9a935856 12030 /* connector->new_encoder is now updated for all connectors. */
50f56119 12031
9a935856 12032 /* Update crtc of enabled connectors. */
3a3371ff 12033 for_each_intel_connector(dev, connector) {
7668851f
VS		 12034 struct drm_crtc *new_crtc;
12035
9a935856 12036 if (!connector->new_encoder)
50f56119
DV		 12037 continue;
12038
9a935856 12039 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 12040
12041 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 12042 if (set->connectors[ro] == &connector->base)
50f56119
DV		 12043 new_crtc = set->crtc;
12044 }
12045
12046 /* Make sure the new CRTC will work with the encoder */
14509916
TR		 12047 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
12048 new_crtc)) {
5e2b584e 12049 return -EINVAL;
50f56119 12050 }
0e32b39c 12051 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
9a935856 12052
944b0c76
ACO		 12053 connector_state =
12054 drm_atomic_get_connector_state(state, &connector->base);
12055 if (IS_ERR(connector_state))
12056 return PTR_ERR(connector_state);
12057
12058 connector_state->crtc = new_crtc;
12059 connector_state->best_encoder = &connector->new_encoder->base;
12060
9a935856
DV		 12061 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
12062 connector->base.base.id,
c23cc417 12063 connector->base.name,
9a935856
DV		 12064 new_crtc->base.id);
12065 }
12066
12067 /* Check for any encoders that needs to be disabled. */
b2784e15 12068 for_each_intel_encoder(dev, encoder) {
5a65f358 12069 int num_connectors = 0;
3a3371ff 12070 for_each_intel_connector(dev, connector) {
9a935856
DV		 12071 if (connector->new_encoder == encoder) {
12072 WARN_ON(!connector->new_encoder->new_crtc);
5a65f358 12073 num_connectors++;
9a935856
DV		 12074 }
12075 }
5a65f358
PZ		 12076
12077 if (num_connectors == 0)
12078 encoder->new_crtc = NULL;
12079 else if (num_connectors > 1)
12080 return -EINVAL;
12081
9a935856
DV		 12082 /* Only now check for crtc changes so we don't miss encoders
12083 * that will be disabled. */
12084 if (&encoder->new_crtc->base != encoder->base.crtc) {
10634189
ACO		 12085 DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n",
12086 encoder->base.base.id,
12087 encoder->base.name);
5e2b584e 12088 config->mode_changed = true;
50f56119
DV		 12089 }
12090 }
9a935856 12091 /* Now we've also updated encoder->new_crtc for all encoders. */
3a3371ff 12092 for_each_intel_connector(dev, connector) {
944b0c76
ACO		 12093 connector_state =
12094 drm_atomic_get_connector_state(state, &connector->base);
9d918c15
ACO		 12095 if (IS_ERR(connector_state))
12096 return PTR_ERR(connector_state);
944b0c76
ACO		 12097
12098 if (connector->new_encoder) {
0e32b39c
DA		 12099 if (connector->new_encoder != connector->encoder)
12100 connector->encoder = connector->new_encoder;
944b0c76
ACO		 12101 } else {
12102 connector_state->crtc = NULL;
12103 }
0e32b39c 12104 }
d3fcc808 12105 for_each_intel_crtc(dev, crtc) {
7668851f
VS		 12106 crtc->new_enabled = false;
12107
b2784e15 12108 for_each_intel_encoder(dev, encoder) {
7668851f
VS		 12109 if (encoder->new_crtc == crtc) {
12110 crtc->new_enabled = true;
12111 break;
12112 }
12113 }
12114
83d65738 12115 if (crtc->new_enabled != crtc->base.state->enable) {
10634189
ACO		 12116 DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n",
12117 crtc->base.base.id,
7668851f
VS		 12118 crtc->new_enabled ? "en" : "dis");
12119 config->mode_changed = true;
12120 }
7bd0a8e7
VS		 12121
12122 if (crtc->new_enabled)
6e3c9717 12123 crtc->new_config = crtc->config;
7bd0a8e7
VS		 12124 else
12125 crtc->new_config = NULL;
7668851f
VS		 12126 }
12127
2e431051
DV		 12128 return 0;
12129}
12130
7d00a1f5
VS		 12131static void disable_crtc_nofb(struct intel_crtc *crtc)
12132{
12133 struct drm_device *dev = crtc->base.dev;
12134 struct intel_encoder *encoder;
12135 struct intel_connector *connector;
12136
12137 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
12138 pipe_name(crtc->pipe));
12139
3a3371ff 12140 for_each_intel_connector(dev, connector) {
7d00a1f5
VS		 12141 if (connector->new_encoder &&
12142 connector->new_encoder->new_crtc == crtc)
12143 connector->new_encoder = NULL;
12144 }
12145
b2784e15 12146 for_each_intel_encoder(dev, encoder) {
7d00a1f5
VS		 12147 if (encoder->new_crtc == crtc)
12148 encoder->new_crtc = NULL;
12149 }
12150
12151 crtc->new_enabled = false;
7bd0a8e7 12152 crtc->new_config = NULL;
7d00a1f5
VS		 12153}
12154
2e431051
DV		 12155static int intel_crtc_set_config(struct drm_mode_set *set)
12156{
12157 struct drm_device *dev;
2e431051 12158 struct drm_mode_set save_set;
83a57153 12159 struct drm_atomic_state *state = NULL;
2e431051 12160 struct intel_set_config *config;
5cec258b 12161 struct intel_crtc_state *pipe_config;
50f52756 12162 unsigned modeset_pipes, prepare_pipes, disable_pipes;
2e431051 12163 int ret;
2e431051 12164
8d3e375e
DV		 12165 BUG_ON(!set);
12166 BUG_ON(!set->crtc);
12167 BUG_ON(!set->crtc->helper_private);
2e431051 12168
7e53f3a4
DV		 12169 /* Enforce sane interface api - has been abused by the fb helper. */
12170 BUG_ON(!set->mode && set->fb);
12171 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 12172
2e431051
DV		 12173 if (set->fb) {
12174 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
12175 set->crtc->base.id, set->fb->base.id,
12176 (int)set->num_connectors, set->x, set->y);
12177 } else {
12178 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 12179 }
12180
12181 dev = set->crtc->dev;
12182
12183 ret = -ENOMEM;
12184 config = kzalloc(sizeof(*config), GFP_KERNEL);
12185 if (!config)
12186 goto out_config;
12187
12188 ret = intel_set_config_save_state(dev, config);
12189 if (ret)
12190 goto out_config;
12191
12192 save_set.crtc = set->crtc;
12193 save_set.mode = &set->crtc->mode;
12194 save_set.x = set->crtc->x;
12195 save_set.y = set->crtc->y;
f4510a27 12196 save_set.fb = set->crtc->primary->fb;
2e431051
DV		 12197
12198 /* Compute whether we need a full modeset, only an fb base update or no
12199 * change at all. In the future we might also check whether only the
12200 * mode changed, e.g. for LVDS where we only change the panel fitter in
12201 * such cases. */
12202 intel_set_config_compute_mode_changes(set, config);
12203
83a57153
ACO		 12204 state = drm_atomic_state_alloc(dev);
12205 if (!state) {
12206 ret = -ENOMEM;
12207 goto out_config;
12208 }
12209
12210 state->acquire_ctx = dev->mode_config.acquire_ctx;
12211
944b0c76 12212 ret = intel_modeset_stage_output_state(dev, set, config, state);
2e431051
DV		 12213 if (ret)
12214 goto fail;
12215
50f52756 12216 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
83a57153 12217 set->fb, state,
50f52756
JB		 12218 &modeset_pipes,
12219 &prepare_pipes,
12220 &disable_pipes);
20664591 12221 if (IS_ERR(pipe_config)) {
6ac0483b 12222 ret = PTR_ERR(pipe_config);
50f52756 12223 goto fail;
20664591 12224 } else if (pipe_config) {
b9950a13 12225 if (pipe_config->has_audio !=
6e3c9717 12226 to_intel_crtc(set->crtc)->config->has_audio)
20664591
JB		 12227 config->mode_changed = true;
12228
af15d2ce
JB		 12229 /*
12230 * Note we have an issue here with infoframes: current code
12231 * only updates them on the full mode set path per hw
12232 * requirements. So here we should be checking for any
12233 * required changes and forcing a mode set.
12234 */
20664591 12235 }
50f52756 12236
1f9954d0
JB		 12237 intel_update_pipe_size(to_intel_crtc(set->crtc));
12238
5e2b584e 12239 if (config->mode_changed) {
50f52756
JB		 12240 ret = intel_set_mode_pipes(set->crtc, set->mode,
12241 set->x, set->y, set->fb, pipe_config,
12242 modeset_pipes, prepare_pipes,
12243 disable_pipes);
5e2b584e 12244 } else if (config->fb_changed) {
3b150f08 12245 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
455a6808
GP		 12246 struct drm_plane *primary = set->crtc->primary;
12247 int vdisplay, hdisplay;
3b150f08 12248
455a6808
GP		 12249 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
12250 ret = primary->funcs->update_plane(primary, set->crtc, set->fb,
12251 0, 0, hdisplay, vdisplay,
12252 set->x << 16, set->y << 16,
12253 hdisplay << 16, vdisplay << 16);
3b150f08
MR		 12254
12255 /*
12256 * We need to make sure the primary plane is re-enabled if it
12257 * has previously been turned off.
12258 */
12259 if (!intel_crtc->primary_enabled && ret == 0) {
12260 WARN_ON(!intel_crtc->active);
fdd508a6 12261 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
3b150f08
MR		 12262 }
12263
7ca51a3a
JB		 12264 /*
12265 * In the fastboot case this may be our only check of the
12266 * state after boot. It would be better to only do it on
12267 * the first update, but we don't have a nice way of doing that
12268 * (and really, set_config isn't used much for high freq page
12269 * flipping, so increasing its cost here shouldn't be a big
12270 * deal).
12271 */
d330a953 12272 if (i915.fastboot && ret == 0)
7ca51a3a 12273 intel_modeset_check_state(set->crtc->dev);
50f56119
DV		 12274 }
12275
2d05eae1 12276 if (ret) {
bf67dfeb
DV		 12277 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
12278 set->crtc->base.id, ret);
50f56119 12279fail:
2d05eae1 12280 intel_set_config_restore_state(dev, config);
50f56119 12281
83a57153
ACO		 12282 drm_atomic_state_clear(state);
12283
7d00a1f5
VS		 12284 /*
12285 * HACK: if the pipe was on, but we didn't have a framebuffer,
12286 * force the pipe off to avoid oopsing in the modeset code
12287 * due to fb==NULL. This should only happen during boot since
12288 * we don't yet reconstruct the FB from the hardware state.
12289 */
12290 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
12291 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
12292
2d05eae1
CW		 12293 /* Try to restore the config */
12294 if (config->mode_changed &&
12295 intel_set_mode(save_set.crtc, save_set.mode,
83a57153
ACO		 12296 save_set.x, save_set.y, save_set.fb,
12297 state))
2d05eae1
CW		 12298 DRM_ERROR("failed to restore config after modeset failure\n");
12299 }
50f56119 12300
d9e55608 12301out_config:
83a57153
ACO		 12302 if (state)
12303 drm_atomic_state_free(state);
12304
d9e55608 12305 intel_set_config_free(config);
50f56119
DV		 12306 return ret;
12307}
f6e5b160
CW		 12308
12309static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 12310 .gamma_set = intel_crtc_gamma_set,
50f56119 12311 .set_config = intel_crtc_set_config,
f6e5b160
CW		 12312 .destroy = intel_crtc_destroy,
12313 .page_flip = intel_crtc_page_flip,
1356837e
MR		 12314 .atomic_duplicate_state = intel_crtc_duplicate_state,
12315 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 12316};
12317
5358901f
DV		 12318static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
12319 struct intel_shared_dpll *pll,
12320 struct intel_dpll_hw_state *hw_state)
ee7b9f93 12321{
5358901f 12322 uint32_t val;
ee7b9f93 12323
f458ebbc 12324 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 12325 return false;
12326
5358901f 12327 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 12328 hw_state->dpll = val;
12329 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
12330 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 12331
12332 return val & DPLL_VCO_ENABLE;
12333}
12334
15bdd4cf
DV		 12335static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
12336 struct intel_shared_dpll *pll)
12337{
3e369b76
ACO		 12338 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
12339 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 12340}
12341
e7b903d2
DV		 12342static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
12343 struct intel_shared_dpll *pll)
12344{
e7b903d2 12345 /* PCH refclock must be enabled first */
89eff4be 12346 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 12347
3e369b76 12348 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 12349
12350 /* Wait for the clocks to stabilize. */
12351 POSTING_READ(PCH_DPLL(pll->id));
12352 udelay(150);
12353
12354 /* The pixel multiplier can only be updated once the
12355 * DPLL is enabled and the clocks are stable.
12356 *
12357 * So write it again.
12358 */
3e369b76 12359 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 12360 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 12361 udelay(200);
12362}
12363
12364static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
12365 struct intel_shared_dpll *pll)
12366{
12367 struct drm_device *dev = dev_priv->dev;
12368 struct intel_crtc *crtc;
e7b903d2
DV		 12369
12370 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 12371 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 12372 if (intel_crtc_to_shared_dpll(crtc) == pll)
12373 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 12374 }
12375
15bdd4cf
DV		 12376 I915_WRITE(PCH_DPLL(pll->id), 0);
12377 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 12378 udelay(200);
12379}
12380
46edb027
DV		 12381static char *ibx_pch_dpll_names[] = {
12382 "PCH DPLL A",
12383 "PCH DPLL B",
12384};
12385
7c74ade1 12386static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 12387{
e7b903d2 12388 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 12389 int i;
12390
7c74ade1 12391 dev_priv->num_shared_dpll = 2;
ee7b9f93 12392
e72f9fbf 12393 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 12394 dev_priv->shared_dplls[i].id = i;
12395 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 12396 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 12397 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
12398 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 12399 dev_priv->shared_dplls[i].get_hw_state =
12400 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 12401 }
12402}
12403
7c74ade1
DV		 12404static void intel_shared_dpll_init(struct drm_device *dev)
12405{
e7b903d2 12406 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 12407
9cd86933
DV		 12408 if (HAS_DDI(dev))
12409 intel_ddi_pll_init(dev);
12410 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 12411 ibx_pch_dpll_init(dev);
12412 else
12413 dev_priv->num_shared_dpll = 0;
12414
12415 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 12416}
12417
1fc0a8f7
TU		 12418/**
12419 * intel_wm_need_update - Check whether watermarks need updating
12420 * @plane: drm plane
12421 * @state: new plane state
12422 *
12423 * Check current plane state versus the new one to determine whether
12424 * watermarks need to be recalculated.
12425 *
12426 * Returns true or false.
12427 */
12428bool intel_wm_need_update(struct drm_plane *plane,
12429 struct drm_plane_state *state)
12430{
12431 /* Update watermarks on tiling changes. */
12432 if (!plane->state->fb || !state->fb ||
12433 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
12434 plane->state->rotation != state->rotation)
12435 return true;
12436
12437 return false;
12438}
12439
6beb8c23
MR		 12440/**
12441 * intel_prepare_plane_fb - Prepare fb for usage on plane
12442 * @plane: drm plane to prepare for
12443 * @fb: framebuffer to prepare for presentation
12444 *
12445 * Prepares a framebuffer for usage on a display plane. Generally this
12446 * involves pinning the underlying object and updating the frontbuffer tracking
12447 * bits. Some older platforms need special physical address handling for
12448 * cursor planes.
12449 *
12450 * Returns 0 on success, negative error code on failure.
12451 */
12452int
12453intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee
TU		 12454 struct drm_framebuffer *fb,
12455 const struct drm_plane_state *new_state)
465c120c
MR		 12456{
12457 struct drm_device *dev = plane->dev;
6beb8c23
MR		 12458 struct intel_plane *intel_plane = to_intel_plane(plane);
12459 enum pipe pipe = intel_plane->pipe;
12460 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12461 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
12462 unsigned frontbuffer_bits = 0;
12463 int ret = 0;
465c120c 12464
ea2c67bb 12465 if (!obj)
465c120c
MR		 12466 return 0;
12467
6beb8c23
MR		 12468 switch (plane->type) {
12469 case DRM_PLANE_TYPE_PRIMARY:
12470 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
12471 break;
12472 case DRM_PLANE_TYPE_CURSOR:
12473 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
12474 break;
12475 case DRM_PLANE_TYPE_OVERLAY:
12476 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
12477 break;
12478 }
465c120c 12479
6beb8c23 12480 mutex_lock(&dev->struct_mutex);
465c120c 12481
6beb8c23
MR		 12482 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
12483 INTEL_INFO(dev)->cursor_needs_physical) {
12484 int align = IS_I830(dev) ? 16 * 1024 : 256;
12485 ret = i915_gem_object_attach_phys(obj, align);
12486 if (ret)
12487 DRM_DEBUG_KMS("failed to attach phys object\n");
12488 } else {
82bc3b2d 12489 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
6beb8c23 12490 }
465c120c 12491
6beb8c23
MR		 12492 if (ret == 0)
12493 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
fdd508a6 12494
4c34574f 12495 mutex_unlock(&dev->struct_mutex);
465c120c 12496
6beb8c23
MR		 12497 return ret;
12498}
12499
38f3ce3a
MR		 12500/**
12501 * intel_cleanup_plane_fb - Cleans up an fb after plane use
12502 * @plane: drm plane to clean up for
12503 * @fb: old framebuffer that was on plane
12504 *
12505 * Cleans up a framebuffer that has just been removed from a plane.
12506 */
12507void
12508intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee
TU		 12509 struct drm_framebuffer *fb,
12510 const struct drm_plane_state *old_state)
38f3ce3a
MR		 12511{
12512 struct drm_device *dev = plane->dev;
12513 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12514
12515 if (WARN_ON(!obj))
12516 return;
12517
12518 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
12519 !INTEL_INFO(dev)->cursor_needs_physical) {
12520 mutex_lock(&dev->struct_mutex);
82bc3b2d 12521 intel_unpin_fb_obj(fb, old_state);
38f3ce3a
MR		 12522 mutex_unlock(&dev->struct_mutex);
12523 }
465c120c
MR		 12524}
12525
12526static int
3c692a41
GP		 12527intel_check_primary_plane(struct drm_plane *plane,
12528 struct intel_plane_state *state)
12529{
32b7eeec
MR		 12530 struct drm_device *dev = plane->dev;
12531 struct drm_i915_private *dev_priv = dev->dev_private;
2b875c22 12532 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 12533 struct intel_crtc *intel_crtc;
2b875c22 12534 struct drm_framebuffer *fb = state->base.fb;
3c692a41
GP		 12535 struct drm_rect *dest = &state->dst;
12536 struct drm_rect *src = &state->src;
12537 const struct drm_rect *clip = &state->clip;
465c120c
MR		 12538 int ret;
12539
ea2c67bb
MR		 12540 crtc = crtc ? crtc : plane->crtc;
12541 intel_crtc = to_intel_crtc(crtc);
12542
c59cb179
MR		 12543 ret = drm_plane_helper_check_update(plane, crtc, fb,
12544 src, dest, clip,
12545 DRM_PLANE_HELPER_NO_SCALING,
12546 DRM_PLANE_HELPER_NO_SCALING,
12547 false, true, &state->visible);
12548 if (ret)
12549 return ret;
465c120c 12550
32b7eeec
MR		 12551 if (intel_crtc->active) {
12552 intel_crtc->atomic.wait_for_flips = true;
12553
12554 /*
12555 * FBC does not work on some platforms for rotated
12556 * planes, so disable it when rotation is not 0 and
12557 * update it when rotation is set back to 0.
12558 *
12559 * FIXME: This is redundant with the fbc update done in
12560 * the primary plane enable function except that that
12561 * one is done too late. We eventually need to unify
12562 * this.
12563 */
12564 if (intel_crtc->primary_enabled &&
12565 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
e35fef21 12566 dev_priv->fbc.crtc == intel_crtc &&
8e7d688b 12567 state->base.rotation != BIT(DRM_ROTATE_0)) {
32b7eeec
MR		 12568 intel_crtc->atomic.disable_fbc = true;
12569 }
12570
12571 if (state->visible) {
12572 /*
12573 * BDW signals flip done immediately if the plane
12574 * is disabled, even if the plane enable is already
12575 * armed to occur at the next vblank :(
12576 */
12577 if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
12578 intel_crtc->atomic.wait_vblank = true;
12579 }
12580
12581 intel_crtc->atomic.fb_bits |=
12582 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
12583
12584 intel_crtc->atomic.update_fbc = true;
0fda6568 12585
1fc0a8f7 12586 if (intel_wm_need_update(plane, &state->base))
0fda6568 12587 intel_crtc->atomic.update_wm = true;
ccc759dc
GP		 12588 }
12589
14af293f
GP		 12590 return 0;
12591}
12592
12593static void
12594intel_commit_primary_plane(struct drm_plane *plane,
12595 struct intel_plane_state *state)
12596{
2b875c22
MR		 12597 struct drm_crtc *crtc = state->base.crtc;
12598 struct drm_framebuffer *fb = state->base.fb;
12599 struct drm_device *dev = plane->dev;
14af293f 12600 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 12601 struct intel_crtc *intel_crtc;
14af293f
GP		 12602 struct drm_rect *src = &state->src;
12603
ea2c67bb
MR		 12604 crtc = crtc ? crtc : plane->crtc;
12605 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR		 12606
12607 plane->fb = fb;
9dc806fc
MR		 12608 crtc->x = src->x1 >> 16;
12609 crtc->y = src->y1 >> 16;
ccc759dc 12610
ccc759dc 12611 if (intel_crtc->active) {
ccc759dc 12612 if (state->visible) {
ccc759dc
GP		 12613 /* FIXME: kill this fastboot hack */
12614 intel_update_pipe_size(intel_crtc);
465c120c 12615
ccc759dc 12616 intel_crtc->primary_enabled = true;
465c120c 12617
ccc759dc
GP		 12618 dev_priv->display.update_primary_plane(crtc, plane->fb,
12619 crtc->x, crtc->y);
ccc759dc
GP		 12620 } else {
12621 /*
12622 * If clipping results in a non-visible primary plane,
12623 * we'll disable the primary plane. Note that this is
12624 * a bit different than what happens if userspace
12625 * explicitly disables the plane by passing fb=0
12626 * because plane->fb still gets set and pinned.
12627 */
12628 intel_disable_primary_hw_plane(plane, crtc);
48404c1e 12629 }
ccc759dc 12630 }
465c120c
MR		 12631}
12632
32b7eeec 12633static void intel_begin_crtc_commit(struct drm_crtc *crtc)
3c692a41 12634{
32b7eeec 12635 struct drm_device *dev = crtc->dev;
140fd38d 12636 struct drm_i915_private *dev_priv = dev->dev_private;
3c692a41 12637 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ea2c67bb
MR		 12638 struct intel_plane *intel_plane;
12639 struct drm_plane *p;
12640 unsigned fb_bits = 0;
12641
12642 /* Track fb's for any planes being disabled */
12643 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
12644 intel_plane = to_intel_plane(p);
12645
12646 if (intel_crtc->atomic.disabled_planes &
12647 (1 << drm_plane_index(p))) {
12648 switch (p->type) {
12649 case DRM_PLANE_TYPE_PRIMARY:
12650 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
12651 break;
12652 case DRM_PLANE_TYPE_CURSOR:
12653 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
12654 break;
12655 case DRM_PLANE_TYPE_OVERLAY:
12656 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
12657 break;
12658 }
3c692a41 12659
ea2c67bb
MR		 12660 mutex_lock(&dev->struct_mutex);
12661 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
12662 mutex_unlock(&dev->struct_mutex);
12663 }
12664 }
3c692a41 12665
32b7eeec
MR		 12666 if (intel_crtc->atomic.wait_for_flips)
12667 intel_crtc_wait_for_pending_flips(crtc);
3c692a41 12668
32b7eeec
MR		 12669 if (intel_crtc->atomic.disable_fbc)
12670 intel_fbc_disable(dev);
3c692a41 12671
32b7eeec
MR		 12672 if (intel_crtc->atomic.pre_disable_primary)
12673 intel_pre_disable_primary(crtc);
3c692a41 12674
32b7eeec
MR		 12675 if (intel_crtc->atomic.update_wm)
12676 intel_update_watermarks(crtc);
3c692a41 12677
32b7eeec 12678 intel_runtime_pm_get(dev_priv);
3c692a41 12679
c34c9ee4
MR		 12680 /* Perform vblank evasion around commit operation */
12681 if (intel_crtc->active)
12682 intel_crtc->atomic.evade =
12683 intel_pipe_update_start(intel_crtc,
12684 &intel_crtc->atomic.start_vbl_count);
32b7eeec
MR		 12685}
12686
12687static void intel_finish_crtc_commit(struct drm_crtc *crtc)
12688{
12689 struct drm_device *dev = crtc->dev;
12690 struct drm_i915_private *dev_priv = dev->dev_private;
12691 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12692 struct drm_plane *p;
12693
c34c9ee4
MR		 12694 if (intel_crtc->atomic.evade)
12695 intel_pipe_update_end(intel_crtc,
12696 intel_crtc->atomic.start_vbl_count);
3c692a41 12697
140fd38d 12698 intel_runtime_pm_put(dev_priv);
3c692a41 12699
32b7eeec
MR		 12700 if (intel_crtc->atomic.wait_vblank)
12701 intel_wait_for_vblank(dev, intel_crtc->pipe);
12702
12703 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
12704
12705 if (intel_crtc->atomic.update_fbc) {
ccc759dc 12706 mutex_lock(&dev->struct_mutex);
7ff0ebcc 12707 intel_fbc_update(dev);
ccc759dc 12708 mutex_unlock(&dev->struct_mutex);
38f3ce3a 12709 }
3c692a41 12710
32b7eeec
MR		 12711 if (intel_crtc->atomic.post_enable_primary)
12712 intel_post_enable_primary(crtc);
3c692a41 12713
32b7eeec
MR		 12714 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
12715 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
12716 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
12717 false, false);
12718
12719 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
3c692a41
GP		 12720}
12721
cf4c7c12 12722/**
4a3b8769
MR		 12723 * intel_plane_destroy - destroy a plane
12724 * @plane: plane to destroy
cf4c7c12 12725 *
4a3b8769
MR		 12726 * Common destruction function for all types of planes (primary, cursor,
12727 * sprite).
cf4c7c12 12728 */
4a3b8769 12729void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 12730{
12731 struct intel_plane *intel_plane = to_intel_plane(plane);
12732 drm_plane_cleanup(plane);
12733 kfree(intel_plane);
12734}
12735
65a3fea0 12736const struct drm_plane_funcs intel_plane_funcs = {
ff42e093
DV		 12737 .update_plane = drm_plane_helper_update,
12738 .disable_plane = drm_plane_helper_disable,
3d7d6510 12739 .destroy = intel_plane_destroy,
c196e1d6 12740 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 12741 .atomic_get_property = intel_plane_atomic_get_property,
12742 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 12743 .atomic_duplicate_state = intel_plane_duplicate_state,
12744 .atomic_destroy_state = intel_plane_destroy_state,
12745
465c120c
MR		 12746};
12747
12748static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
12749 int pipe)
12750{
12751 struct intel_plane *primary;
8e7d688b 12752 struct intel_plane_state *state;
465c120c
MR		 12753 const uint32_t *intel_primary_formats;
12754 int num_formats;
12755
12756 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12757 if (primary == NULL)
12758 return NULL;
12759
8e7d688b
MR		 12760 state = intel_create_plane_state(&primary->base);
12761 if (!state) {
ea2c67bb
MR		 12762 kfree(primary);
12763 return NULL;
12764 }
8e7d688b 12765 primary->base.state = &state->base;
ea2c67bb 12766
465c120c
MR		 12767 primary->can_scale = false;
12768 primary->max_downscale = 1;
12769 primary->pipe = pipe;
12770 primary->plane = pipe;
c59cb179
MR		 12771 primary->check_plane = intel_check_primary_plane;
12772 primary->commit_plane = intel_commit_primary_plane;
465c120c
MR		 12773 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12774 primary->plane = !pipe;
12775
12776 if (INTEL_INFO(dev)->gen <= 3) {
12777 intel_primary_formats = intel_primary_formats_gen2;
12778 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12779 } else {
12780 intel_primary_formats = intel_primary_formats_gen4;
12781 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12782 }
12783
12784 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 12785 &intel_plane_funcs,
465c120c
MR		 12786 intel_primary_formats, num_formats,
12787 DRM_PLANE_TYPE_PRIMARY);
48404c1e
SJ		 12788
12789 if (INTEL_INFO(dev)->gen >= 4) {
12790 if (!dev->mode_config.rotation_property)
12791 dev->mode_config.rotation_property =
12792 drm_mode_create_rotation_property(dev,
12793 BIT(DRM_ROTATE_0) |
12794 BIT(DRM_ROTATE_180));
12795 if (dev->mode_config.rotation_property)
12796 drm_object_attach_property(&primary->base.base,
12797 dev->mode_config.rotation_property,
8e7d688b 12798 state->base.rotation);
48404c1e
SJ		 12799 }
12800
ea2c67bb
MR		 12801 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
12802
465c120c
MR		 12803 return &primary->base;
12804}
12805
3d7d6510 12806static int
852e787c
GP		 12807intel_check_cursor_plane(struct drm_plane *plane,
12808 struct intel_plane_state *state)
3d7d6510 12809{
2b875c22 12810 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 12811 struct drm_device *dev = plane->dev;
2b875c22 12812 struct drm_framebuffer *fb = state->base.fb;
852e787c
GP		 12813 struct drm_rect *dest = &state->dst;
12814 struct drm_rect *src = &state->src;
12815 const struct drm_rect *clip = &state->clip;
757f9a3e 12816 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
ea2c67bb 12817 struct intel_crtc *intel_crtc;
757f9a3e
GP		 12818 unsigned stride;
12819 int ret;
3d7d6510 12820
ea2c67bb
MR		 12821 crtc = crtc ? crtc : plane->crtc;
12822 intel_crtc = to_intel_crtc(crtc);
12823
757f9a3e 12824 ret = drm_plane_helper_check_update(plane, crtc, fb,
852e787c 12825 src, dest, clip,
3d7d6510
MR		 12826 DRM_PLANE_HELPER_NO_SCALING,
12827 DRM_PLANE_HELPER_NO_SCALING,
852e787c 12828 true, true, &state->visible);
757f9a3e
GP		 12829 if (ret)
12830 return ret;
12831
12832
12833 /* if we want to turn off the cursor ignore width and height */
12834 if (!obj)
32b7eeec 12835 goto finish;
757f9a3e 12836
757f9a3e 12837 /* Check for which cursor types we support */
ea2c67bb
MR		 12838 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
12839 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12840 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 12841 return -EINVAL;
12842 }
12843
ea2c67bb
MR		 12844 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
12845 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 12846 DRM_DEBUG_KMS("buffer is too small\n");
12847 return -ENOMEM;
12848 }
12849
3a656b54 12850 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e
GP		 12851 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12852 ret = -EINVAL;
12853 }
757f9a3e 12854
32b7eeec
MR		 12855finish:
12856 if (intel_crtc->active) {
3749f463 12857 if (plane->state->crtc_w != state->base.crtc_w)
32b7eeec
MR		 12858 intel_crtc->atomic.update_wm = true;
12859
12860 intel_crtc->atomic.fb_bits |=
12861 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
12862 }
12863
757f9a3e 12864 return ret;
852e787c 12865}
3d7d6510 12866
f4a2cf29 12867static void
852e787c
GP		 12868intel_commit_cursor_plane(struct drm_plane *plane,
12869 struct intel_plane_state *state)
12870{
2b875c22 12871 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 12872 struct drm_device *dev = plane->dev;
12873 struct intel_crtc *intel_crtc;
2b875c22 12874 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 12875 uint32_t addr;
852e787c 12876
ea2c67bb
MR		 12877 crtc = crtc ? crtc : plane->crtc;
12878 intel_crtc = to_intel_crtc(crtc);
12879
2b875c22 12880 plane->fb = state->base.fb;
ea2c67bb
MR		 12881 crtc->cursor_x = state->base.crtc_x;
12882 crtc->cursor_y = state->base.crtc_y;
12883
a912f12f
GP		 12884 if (intel_crtc->cursor_bo == obj)
12885 goto update;
4ed91096 12886
f4a2cf29 12887 if (!obj)
a912f12f 12888 addr = 0;
f4a2cf29 12889 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 12890 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 12891 else
a912f12f 12892 addr = obj->phys_handle->busaddr;
852e787c 12893
a912f12f
GP		 12894 intel_crtc->cursor_addr = addr;
12895 intel_crtc->cursor_bo = obj;
12896update:
852e787c 12897
32b7eeec 12898 if (intel_crtc->active)
a912f12f 12899 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 12900}
12901
3d7d6510
MR		 12902static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12903 int pipe)
12904{
12905 struct intel_plane *cursor;
8e7d688b 12906 struct intel_plane_state *state;
3d7d6510
MR		 12907
12908 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12909 if (cursor == NULL)
12910 return NULL;
12911
8e7d688b
MR		 12912 state = intel_create_plane_state(&cursor->base);
12913 if (!state) {
ea2c67bb
MR		 12914 kfree(cursor);
12915 return NULL;
12916 }
8e7d688b 12917 cursor->base.state = &state->base;
ea2c67bb 12918
3d7d6510
MR		 12919 cursor->can_scale = false;
12920 cursor->max_downscale = 1;
12921 cursor->pipe = pipe;
12922 cursor->plane = pipe;
c59cb179
MR		 12923 cursor->check_plane = intel_check_cursor_plane;
12924 cursor->commit_plane = intel_commit_cursor_plane;
3d7d6510
MR		 12925
12926 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 12927 &intel_plane_funcs,
3d7d6510
MR		 12928 intel_cursor_formats,
12929 ARRAY_SIZE(intel_cursor_formats),
12930 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 12931
12932 if (INTEL_INFO(dev)->gen >= 4) {
12933 if (!dev->mode_config.rotation_property)
12934 dev->mode_config.rotation_property =
12935 drm_mode_create_rotation_property(dev,
12936 BIT(DRM_ROTATE_0) |
12937 BIT(DRM_ROTATE_180));
12938 if (dev->mode_config.rotation_property)
12939 drm_object_attach_property(&cursor->base.base,
12940 dev->mode_config.rotation_property,
8e7d688b 12941 state->base.rotation);
4398ad45
VS		 12942 }
12943
ea2c67bb
MR		 12944 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
12945
3d7d6510
MR		 12946 return &cursor->base;
12947}
12948
b358d0a6 12949static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 12950{
fbee40df 12951 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 12952 struct intel_crtc *intel_crtc;
f5de6e07 12953 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 12954 struct drm_plane *primary = NULL;
12955 struct drm_plane *cursor = NULL;
465c120c 12956 int i, ret;
79e53945 12957
955382f3 12958 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 12959 if (intel_crtc == NULL)
12960 return;
12961
f5de6e07
ACO		 12962 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
12963 if (!crtc_state)
12964 goto fail;
12965 intel_crtc_set_state(intel_crtc, crtc_state);
07878248 12966 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 12967
465c120c 12968 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 12969 if (!primary)
12970 goto fail;
12971
12972 cursor = intel_cursor_plane_create(dev, pipe);
12973 if (!cursor)
12974 goto fail;
12975
465c120c 12976 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 12977 cursor, &intel_crtc_funcs);
12978 if (ret)
12979 goto fail;
79e53945
JB		 12980
12981 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 12982 for (i = 0; i < 256; i++) {
12983 intel_crtc->lut_r[i] = i;
12984 intel_crtc->lut_g[i] = i;
12985 intel_crtc->lut_b[i] = i;
12986 }
12987
1f1c2e24
VS		 12988 /*
12989 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 12990 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 12991 */
80824003
JB		 12992 intel_crtc->pipe = pipe;
12993 intel_crtc->plane = pipe;
3a77c4c4 12994 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 12995 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 12996 intel_crtc->plane = !pipe;
80824003
JB		 12997 }
12998
4b0e333e
CW		 12999 intel_crtc->cursor_base = ~0;
13000 intel_crtc->cursor_cntl = ~0;
dc41c154 13001 intel_crtc->cursor_size = ~0;
8d7849db 13002
22fd0fab
JB		 13003 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13004 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13005 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13006 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13007
9362c7c5
ACO		 13008 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
13009
79e53945 13010 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 13011
13012 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 13013 return;
13014
13015fail:
13016 if (primary)
13017 drm_plane_cleanup(primary);
13018 if (cursor)
13019 drm_plane_cleanup(cursor);
f5de6e07 13020 kfree(crtc_state);
3d7d6510 13021 kfree(intel_crtc);
79e53945
JB		 13022}
13023
752aa88a
JB		 13024enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13025{
13026 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 13027 struct drm_device *dev = connector->base.dev;
752aa88a 13028
51fd371b 13029 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 13030
d3babd3f 13031 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 13032 return INVALID_PIPE;
13033
13034 return to_intel_crtc(encoder->crtc)->pipe;
13035}
13036
08d7b3d1 13037int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 13038 struct drm_file *file)
08d7b3d1 13039{
08d7b3d1 13040 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 13041 struct drm_crtc *drmmode_crtc;
c05422d5 13042 struct intel_crtc *crtc;
08d7b3d1 13043
7707e653 13044 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 13045
7707e653 13046 if (!drmmode_crtc) {
08d7b3d1 13047 DRM_ERROR("no such CRTC id\n");
3f2c2057 13048 return -ENOENT;
08d7b3d1
CW		 13049 }
13050
7707e653 13051 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 13052 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 13053
c05422d5 13054 return 0;
08d7b3d1
CW		 13055}
13056
66a9278e 13057static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 13058{
66a9278e
DV		 13059 struct drm_device *dev = encoder->base.dev;
13060 struct intel_encoder *source_encoder;
79e53945 13061 int index_mask = 0;
79e53945
JB		 13062 int entry = 0;
13063
b2784e15 13064 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 13065 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 13066 index_mask |= (1 << entry);
13067
79e53945
JB		 13068 entry++;
13069 }
4ef69c7a 13070
79e53945
JB		 13071 return index_mask;
13072}
13073
4d302442
CW		 13074static bool has_edp_a(struct drm_device *dev)
13075{
13076 struct drm_i915_private *dev_priv = dev->dev_private;
13077
13078 if (!IS_MOBILE(dev))
13079 return false;
13080
13081 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13082 return false;
13083
e3589908 13084 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 13085 return false;
13086
13087 return true;
13088}
13089
84b4e042
JB		 13090static bool intel_crt_present(struct drm_device *dev)
13091{
13092 struct drm_i915_private *dev_priv = dev->dev_private;
13093
884497ed
DL		 13094 if (INTEL_INFO(dev)->gen >= 9)
13095 return false;
13096
cf404ce4 13097 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 13098 return false;
13099
13100 if (IS_CHERRYVIEW(dev))
13101 return false;
13102
13103 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13104 return false;
13105
13106 return true;
13107}
13108
79e53945
JB		 13109static void intel_setup_outputs(struct drm_device *dev)
13110{
725e30ad 13111 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 13112 struct intel_encoder *encoder;
c6f95f27 13113 struct drm_connector *connector;
cb0953d7 13114 bool dpd_is_edp = false;
79e53945 13115
c9093354 13116 intel_lvds_init(dev);
79e53945 13117
84b4e042 13118 if (intel_crt_present(dev))
79935fca 13119 intel_crt_init(dev);
cb0953d7 13120
affa9354 13121 if (HAS_DDI(dev)) {
0e72a5b5
ED		 13122 int found;
13123
de31facd
JB		 13124 /*
13125 * Haswell uses DDI functions to detect digital outputs.
13126 * On SKL pre-D0 the strap isn't connected, so we assume
13127 * it's there.
13128 */
0e72a5b5 13129 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
de31facd
JB		 13130 /* WaIgnoreDDIAStrap: skl */
13131 if (found ||
13132 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
0e72a5b5
ED		 13133 intel_ddi_init(dev, PORT_A);
13134
13135 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13136 * register */
13137 found = I915_READ(SFUSE_STRAP);
13138
13139 if (found & SFUSE_STRAP_DDIB_DETECTED)
13140 intel_ddi_init(dev, PORT_B);
13141 if (found & SFUSE_STRAP_DDIC_DETECTED)
13142 intel_ddi_init(dev, PORT_C);
13143 if (found & SFUSE_STRAP_DDID_DETECTED)
13144 intel_ddi_init(dev, PORT_D);
13145 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 13146 int found;
5d8a7752 13147 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 13148
13149 if (has_edp_a(dev))
13150 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 13151
dc0fa718 13152 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 13153 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 13154 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 13155 if (!found)
e2debe91 13156 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 13157 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 13158 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 13159 }
13160
dc0fa718 13161 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 13162 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 13163
dc0fa718 13164 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 13165 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 13166
5eb08b69 13167 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 13168 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 13169
270b3042 13170 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 13171 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 13172 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 13173 /*
13174 * The DP_DETECTED bit is the latched state of the DDC
13175 * SDA pin at boot. However since eDP doesn't require DDC
13176 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13177 * eDP ports may have been muxed to an alternate function.
13178 * Thus we can't rely on the DP_DETECTED bit alone to detect
13179 * eDP ports. Consult the VBT as well as DP_DETECTED to
13180 * detect eDP ports.
13181 */
d2182a66
VS		 13182 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
13183 !intel_dp_is_edp(dev, PORT_B))
585a94b8
AB		 13184 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
13185 PORT_B);
e17ac6db
VS		 13186 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
13187 intel_dp_is_edp(dev, PORT_B))
13188 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
585a94b8 13189
d2182a66
VS		 13190 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
13191 !intel_dp_is_edp(dev, PORT_C))
6f6005a5
JB		 13192 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
13193 PORT_C);
e17ac6db
VS		 13194 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
13195 intel_dp_is_edp(dev, PORT_C))
13196 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 13197
9418c1f1 13198 if (IS_CHERRYVIEW(dev)) {
e17ac6db 13199 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
9418c1f1
VS		 13200 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
13201 PORT_D);
e17ac6db
VS		 13202 /* eDP not supported on port D, so don't check VBT */
13203 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
13204 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
9418c1f1
VS		 13205 }
13206
3cfca973 13207 intel_dsi_init(dev);
103a196f 13208 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 13209 bool found = false;
7d57382e 13210
e2debe91 13211 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 13212 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 13213 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 13214 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
13215 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 13216 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 13217 }
27185ae1 13218
e7281eab 13219 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 13220 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 13221 }
13520b05
KH		 13222
13223 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 13224
e2debe91 13225 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 13226 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 13227 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 13228 }
27185ae1 13229
e2debe91 13230 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 13231
b01f2c3a
JB		 13232 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
13233 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 13234 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 13235 }
e7281eab 13236 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 13237 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 13238 }
27185ae1 13239
b01f2c3a 13240 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 13241 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 13242 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 13243 } else if (IS_GEN2(dev))
79e53945
JB		 13244 intel_dvo_init(dev);
13245
103a196f 13246 if (SUPPORTS_TV(dev))
79e53945
JB		 13247 intel_tv_init(dev);
13248
c6f95f27
MR		 13249 /*
13250 * FIXME: We don't have full atomic support yet, but we want to be
13251 * able to enable/test plane updates via the atomic interface in the
13252 * meantime. However as soon as we flip DRIVER_ATOMIC on, the DRM core
13253 * will take some atomic codepaths to lookup properties during
13254 * drmModeGetConnector() that unconditionally dereference
13255 * connector->state.
13256 *
13257 * We create a dummy connector state here for each connector to ensure
13258 * the DRM core doesn't try to dereference a NULL connector->state.
13259 * The actual connector properties will never be updated or contain
13260 * useful information, but since we're doing this specifically for
13261 * testing/debug of the plane operations (and only when a specific
13262 * kernel module option is given), that shouldn't really matter.
13263 *
d29b2f9d
ACO		 13264 * We are also relying on these states to convert the legacy mode set
13265 * to use a drm_atomic_state struct. The states are kept consistent
13266 * with actual state, so that it is safe to rely on that instead of
13267 * the staged config.
13268 *
c6f95f27
MR		 13269 * Once atomic support for crtc's + connectors lands, this loop should
13270 * be removed since we'll be setting up real connector state, which
13271 * will contain Intel-specific properties.
13272 */
d29b2f9d
ACO		 13273 list_for_each_entry(connector,
13274 &dev->mode_config.connector_list,
13275 head) {
13276 if (!WARN_ON(connector->state)) {
13277 connector->state = kzalloc(sizeof(*connector->state),
13278 GFP_KERNEL);
c6f95f27
MR		 13279 }
13280 }
13281
0bc12bcb 13282 intel_psr_init(dev);
7c8f8a70 13283
b2784e15 13284 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 13285 encoder->base.possible_crtcs = encoder->crtc_mask;
13286 encoder->base.possible_clones =
66a9278e 13287 intel_encoder_clones(encoder);
79e53945 13288 }
47356eb6 13289
dde86e2d 13290 intel_init_pch_refclk(dev);
270b3042
DV		 13291
13292 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 13293}
13294
13295static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
13296{
60a5ca01 13297 struct drm_device *dev = fb->dev;
79e53945 13298 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 13299
ef2d633e 13300 drm_framebuffer_cleanup(fb);
60a5ca01 13301 mutex_lock(&dev->struct_mutex);
ef2d633e 13302 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 13303 drm_gem_object_unreference(&intel_fb->obj->base);
13304 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 13305 kfree(intel_fb);
13306}
13307
13308static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 13309 struct drm_file *file,
79e53945
JB		 13310 unsigned int *handle)
13311{
13312 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 13313 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 13314
05394f39 13315 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 13316}
13317
13318static const struct drm_framebuffer_funcs intel_fb_funcs = {
13319 .destroy = intel_user_framebuffer_destroy,
13320 .create_handle = intel_user_framebuffer_create_handle,
13321};
13322
b321803d
DL		 13323static
13324u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
13325 uint32_t pixel_format)
13326{
13327 u32 gen = INTEL_INFO(dev)->gen;
13328
13329 if (gen >= 9) {
13330 /* "The stride in bytes must not exceed the of the size of 8K
13331 * pixels and 32K bytes."
13332 */
13333 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
13334 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
13335 return 32*1024;
13336 } else if (gen >= 4) {
13337 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13338 return 16*1024;
13339 else
13340 return 32*1024;
13341 } else if (gen >= 3) {
13342 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13343 return 8*1024;
13344 else
13345 return 16*1024;
13346 } else {
13347 /* XXX DSPC is limited to 4k tiled */
13348 return 8*1024;
13349 }
13350}
13351
b5ea642a
DV		 13352static int intel_framebuffer_init(struct drm_device *dev,
13353 struct intel_framebuffer *intel_fb,
13354 struct drm_mode_fb_cmd2 *mode_cmd,
13355 struct drm_i915_gem_object *obj)
79e53945 13356{
6761dd31 13357 unsigned int aligned_height;
79e53945 13358 int ret;
b321803d 13359 u32 pitch_limit, stride_alignment;
79e53945 13360
dd4916c5
DV		 13361 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
13362
2a80eada
DV		 13363 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
13364 /* Enforce that fb modifier and tiling mode match, but only for
13365 * X-tiled. This is needed for FBC. */
13366 if (!!(obj->tiling_mode == I915_TILING_X) !=
13367 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
13368 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
13369 return -EINVAL;
13370 }
13371 } else {
13372 if (obj->tiling_mode == I915_TILING_X)
13373 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
13374 else if (obj->tiling_mode == I915_TILING_Y) {
13375 DRM_DEBUG("No Y tiling for legacy addfb\n");
13376 return -EINVAL;
13377 }
13378 }
13379
9a8f0a12
TU		 13380 /* Passed in modifier sanity checking. */
13381 switch (mode_cmd->modifier[0]) {
13382 case I915_FORMAT_MOD_Y_TILED:
13383 case I915_FORMAT_MOD_Yf_TILED:
13384 if (INTEL_INFO(dev)->gen < 9) {
13385 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
13386 mode_cmd->modifier[0]);
13387 return -EINVAL;
13388 }
13389 case DRM_FORMAT_MOD_NONE:
13390 case I915_FORMAT_MOD_X_TILED:
13391 break;
13392 default:
c0f40428
JB		 13393 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
13394 mode_cmd->modifier[0]);
57cd6508 13395 return -EINVAL;
c16ed4be 13396 }
57cd6508 13397
b321803d
DL		 13398 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
13399 mode_cmd->pixel_format);
13400 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
13401 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
13402 mode_cmd->pitches[0], stride_alignment);
57cd6508 13403 return -EINVAL;
c16ed4be 13404 }
57cd6508 13405
b321803d
DL		 13406 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
13407 mode_cmd->pixel_format);
a35cdaa0 13408 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 13409 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
13410 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 13411 "tiled" : "linear",
a35cdaa0 13412 mode_cmd->pitches[0], pitch_limit);
5d7bd705 13413 return -EINVAL;
c16ed4be 13414 }
5d7bd705 13415
2a80eada 13416 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 13417 mode_cmd->pitches[0] != obj->stride) {
13418 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
13419 mode_cmd->pitches[0], obj->stride);
5d7bd705 13420 return -EINVAL;
c16ed4be 13421 }
5d7bd705 13422
57779d06 13423 /* Reject formats not supported by any plane early. */
308e5bcb 13424 switch (mode_cmd->pixel_format) {
57779d06 13425 case DRM_FORMAT_C8:
04b3924d
VS		 13426 case DRM_FORMAT_RGB565:
13427 case DRM_FORMAT_XRGB8888:
13428 case DRM_FORMAT_ARGB8888:
57779d06
VS		 13429 break;
13430 case DRM_FORMAT_XRGB1555:
13431 case DRM_FORMAT_ARGB1555:
c16ed4be 13432 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 13433 DRM_DEBUG("unsupported pixel format: %s\n",
13434 drm_get_format_name(mode_cmd->pixel_format));
57779d06 13435 return -EINVAL;
c16ed4be 13436 }
57779d06
VS		 13437 break;
13438 case DRM_FORMAT_XBGR8888:
13439 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 13440 case DRM_FORMAT_XRGB2101010:
13441 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 13442 case DRM_FORMAT_XBGR2101010:
13443 case DRM_FORMAT_ABGR2101010:
c16ed4be 13444 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 13445 DRM_DEBUG("unsupported pixel format: %s\n",
13446 drm_get_format_name(mode_cmd->pixel_format));
57779d06 13447 return -EINVAL;
c16ed4be 13448 }
b5626747 13449 break;
04b3924d
VS		 13450 case DRM_FORMAT_YUYV:
13451 case DRM_FORMAT_UYVY:
13452 case DRM_FORMAT_YVYU:
13453 case DRM_FORMAT_VYUY:
c16ed4be 13454 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 13455 DRM_DEBUG("unsupported pixel format: %s\n",
13456 drm_get_format_name(mode_cmd->pixel_format));
57779d06 13457 return -EINVAL;
c16ed4be 13458 }
57cd6508
CW		 13459 break;
13460 default:
4ee62c76
VS		 13461 DRM_DEBUG("unsupported pixel format: %s\n",
13462 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 13463 return -EINVAL;
13464 }
13465
90f9a336
VS		 13466 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
13467 if (mode_cmd->offsets[0] != 0)
13468 return -EINVAL;
13469
ec2c981e 13470 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 13471 mode_cmd->pixel_format,
13472 mode_cmd->modifier[0]);
53155c0a
DV		 13473 /* FIXME drm helper for size checks (especially planar formats)? */
13474 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
13475 return -EINVAL;
13476
c7d73f6a
DV		 13477 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
13478 intel_fb->obj = obj;
80075d49 13479 intel_fb->obj->framebuffer_references++;
c7d73f6a 13480
79e53945
JB		 13481 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
13482 if (ret) {
13483 DRM_ERROR("framebuffer init failed %d\n", ret);
13484 return ret;
13485 }
13486
79e53945
JB		 13487 return 0;
13488}
13489
79e53945
JB		 13490static struct drm_framebuffer *
13491intel_user_framebuffer_create(struct drm_device *dev,
13492 struct drm_file *filp,
308e5bcb 13493 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 13494{
05394f39 13495 struct drm_i915_gem_object *obj;
79e53945 13496
308e5bcb
JB		 13497 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
13498 mode_cmd->handles[0]));
c8725226 13499 if (&obj->base == NULL)
cce13ff7 13500 return ERR_PTR(-ENOENT);
79e53945 13501
d2dff872 13502 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 13503}
13504
4520f53a 13505#ifndef CONFIG_DRM_I915_FBDEV
0632fef6 13506static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 13507{
13508}
13509#endif
13510
79e53945 13511static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 13512 .fb_create = intel_user_framebuffer_create,
0632fef6 13513 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 13514 .atomic_check = intel_atomic_check,
13515 .atomic_commit = intel_atomic_commit,
79e53945
JB		 13516};
13517
e70236a8
JB		 13518/* Set up chip specific display functions */
13519static void intel_init_display(struct drm_device *dev)
13520{
13521 struct drm_i915_private *dev_priv = dev->dev_private;
13522
ee9300bb
DV		 13523 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
13524 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 13525 else if (IS_CHERRYVIEW(dev))
13526 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 13527 else if (IS_VALLEYVIEW(dev))
13528 dev_priv->display.find_dpll = vlv_find_best_dpll;
13529 else if (IS_PINEVIEW(dev))
13530 dev_priv->display.find_dpll = pnv_find_best_dpll;
13531 else
13532 dev_priv->display.find_dpll = i9xx_find_best_dpll;
13533
bc8d7dff
DL		 13534 if (INTEL_INFO(dev)->gen >= 9) {
13535 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 13536 dev_priv->display.get_initial_plane_config =
13537 skylake_get_initial_plane_config;
bc8d7dff
DL		 13538 dev_priv->display.crtc_compute_clock =
13539 haswell_crtc_compute_clock;
13540 dev_priv->display.crtc_enable = haswell_crtc_enable;
13541 dev_priv->display.crtc_disable = haswell_crtc_disable;
13542 dev_priv->display.off = ironlake_crtc_off;
13543 dev_priv->display.update_primary_plane =
13544 skylake_update_primary_plane;
13545 } else if (HAS_DDI(dev)) {
0e8ffe1b 13546 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 13547 dev_priv->display.get_initial_plane_config =
13548 ironlake_get_initial_plane_config;
797d0259
ACO		 13549 dev_priv->display.crtc_compute_clock =
13550 haswell_crtc_compute_clock;
4f771f10
PZ		 13551 dev_priv->display.crtc_enable = haswell_crtc_enable;
13552 dev_priv->display.crtc_disable = haswell_crtc_disable;
df8ad70c 13553 dev_priv->display.off = ironlake_crtc_off;
bc8d7dff
DL		 13554 dev_priv->display.update_primary_plane =
13555 ironlake_update_primary_plane;
09b4ddf9 13556 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 13557 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 13558 dev_priv->display.get_initial_plane_config =
13559 ironlake_get_initial_plane_config;
3fb37703
ACO		 13560 dev_priv->display.crtc_compute_clock =
13561 ironlake_crtc_compute_clock;
76e5a89c
DV		 13562 dev_priv->display.crtc_enable = ironlake_crtc_enable;
13563 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 13564 dev_priv->display.off = ironlake_crtc_off;
262ca2b0
MR		 13565 dev_priv->display.update_primary_plane =
13566 ironlake_update_primary_plane;
89b667f8
JB		 13567 } else if (IS_VALLEYVIEW(dev)) {
13568 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 13569 dev_priv->display.get_initial_plane_config =
13570 i9xx_get_initial_plane_config;
d6dfee7a 13571 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 13572 dev_priv->display.crtc_enable = valleyview_crtc_enable;
13573 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13574 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR		 13575 dev_priv->display.update_primary_plane =
13576 i9xx_update_primary_plane;
f564048e 13577 } else {
0e8ffe1b 13578 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 13579 dev_priv->display.get_initial_plane_config =
13580 i9xx_get_initial_plane_config;
d6dfee7a 13581 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 13582 dev_priv->display.crtc_enable = i9xx_crtc_enable;
13583 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 13584 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR		 13585 dev_priv->display.update_primary_plane =
13586 i9xx_update_primary_plane;
f564048e 13587 }
e70236a8 13588
e70236a8 13589 /* Returns the core display clock speed */
1652d19e
VS		 13590 if (IS_SKYLAKE(dev))
13591 dev_priv->display.get_display_clock_speed =
13592 skylake_get_display_clock_speed;
13593 else if (IS_BROADWELL(dev))
13594 dev_priv->display.get_display_clock_speed =
13595 broadwell_get_display_clock_speed;
13596 else if (IS_HASWELL(dev))
13597 dev_priv->display.get_display_clock_speed =
13598 haswell_get_display_clock_speed;
13599 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB		 13600 dev_priv->display.get_display_clock_speed =
13601 valleyview_get_display_clock_speed;
b37a6434
VS		 13602 else if (IS_GEN5(dev))
13603 dev_priv->display.get_display_clock_speed =
13604 ilk_get_display_clock_speed;
a7c66cd8
VS		 13605 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
13606 IS_GEN6(dev) || IS_IVYBRIDGE(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 13607 dev_priv->display.get_display_clock_speed =
13608 i945_get_display_clock_speed;
13609 else if (IS_I915G(dev))
13610 dev_priv->display.get_display_clock_speed =
13611 i915_get_display_clock_speed;
257a7ffc 13612 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 13613 dev_priv->display.get_display_clock_speed =
13614 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 13615 else if (IS_PINEVIEW(dev))
13616 dev_priv->display.get_display_clock_speed =
13617 pnv_get_display_clock_speed;
e70236a8
JB		 13618 else if (IS_I915GM(dev))
13619 dev_priv->display.get_display_clock_speed =
13620 i915gm_get_display_clock_speed;
13621 else if (IS_I865G(dev))
13622 dev_priv->display.get_display_clock_speed =
13623 i865_get_display_clock_speed;
f0f8a9ce 13624 else if (IS_I85X(dev))
e70236a8
JB		 13625 dev_priv->display.get_display_clock_speed =
13626 i855_get_display_clock_speed;
13627 else /* 852, 830 */
13628 dev_priv->display.get_display_clock_speed =
13629 i830_get_display_clock_speed;
13630
7c10a2b5 13631 if (IS_GEN5(dev)) {
3bb11b53 13632 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 13633 } else if (IS_GEN6(dev)) {
13634 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 13635 } else if (IS_IVYBRIDGE(dev)) {
13636 /* FIXME: detect B0+ stepping and use auto training */
13637 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 13638 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 13639 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
30a970c6
JB		 13640 } else if (IS_VALLEYVIEW(dev)) {
13641 dev_priv->display.modeset_global_resources =
13642 valleyview_modeset_global_resources;
e70236a8 13643 }
8c9f3aaf 13644
8c9f3aaf
JB		 13645 switch (INTEL_INFO(dev)->gen) {
13646 case 2:
13647 dev_priv->display.queue_flip = intel_gen2_queue_flip;
13648 break;
13649
13650 case 3:
13651 dev_priv->display.queue_flip = intel_gen3_queue_flip;
13652 break;
13653
13654 case 4:
13655 case 5:
13656 dev_priv->display.queue_flip = intel_gen4_queue_flip;
13657 break;
13658
13659 case 6:
13660 dev_priv->display.queue_flip = intel_gen6_queue_flip;
13661 break;
7c9017e5 13662 case 7:
4e0bbc31 13663 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 13664 dev_priv->display.queue_flip = intel_gen7_queue_flip;
13665 break;
830c81db 13666 case 9:
ba343e02
TU		 13667 /* Drop through - unsupported since execlist only. */
13668 default:
13669 /* Default just returns -ENODEV to indicate unsupported */
13670 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 13671 }
7bd688cd
JN		 13672
13673 intel_panel_init_backlight_funcs(dev);
e39b999a
VS		 13674
13675 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 13676}
13677
b690e96c
JB		 13678/*
13679 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
13680 * resume, or other times. This quirk makes sure that's the case for
13681 * affected systems.
13682 */
0206e353 13683static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 13684{
13685 struct drm_i915_private *dev_priv = dev->dev_private;
13686
13687 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 13688 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 13689}
13690
b6b5d049
VS		 13691static void quirk_pipeb_force(struct drm_device *dev)
13692{
13693 struct drm_i915_private *dev_priv = dev->dev_private;
13694
13695 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
13696 DRM_INFO("applying pipe b force quirk\n");
13697}
13698
435793df
KP		 13699/*
13700 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
13701 */
13702static void quirk_ssc_force_disable(struct drm_device *dev)
13703{
13704 struct drm_i915_private *dev_priv = dev->dev_private;
13705 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 13706 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 13707}
13708
4dca20ef 13709/*
5a15ab5b
CE		 13710 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
13711 * brightness value
4dca20ef
CE		 13712 */
13713static void quirk_invert_brightness(struct drm_device *dev)
13714{
13715 struct drm_i915_private *dev_priv = dev->dev_private;
13716 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 13717 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 13718}
13719
9c72cc6f
SD		 13720/* Some VBT's incorrectly indicate no backlight is present */
13721static void quirk_backlight_present(struct drm_device *dev)
13722{
13723 struct drm_i915_private *dev_priv = dev->dev_private;
13724 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
13725 DRM_INFO("applying backlight present quirk\n");
13726}
13727
b690e96c
JB		 13728struct intel_quirk {
13729 int device;
13730 int subsystem_vendor;
13731 int subsystem_device;
13732 void (*hook)(struct drm_device *dev);
13733};
13734
5f85f176
EE		 13735/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13736struct intel_dmi_quirk {
13737 void (*hook)(struct drm_device *dev);
13738 const struct dmi_system_id (*dmi_id_list)[];
13739};
13740
13741static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
13742{
13743 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
13744 return 1;
13745}
13746
13747static const struct intel_dmi_quirk intel_dmi_quirks[] = {
13748 {
13749 .dmi_id_list = &(const struct dmi_system_id[]) {
13750 {
13751 .callback = intel_dmi_reverse_brightness,
13752 .ident = "NCR Corporation",
13753 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
13754 DMI_MATCH(DMI_PRODUCT_NAME, ""),
13755 },
13756 },
13757 { } /* terminating entry */
13758 },
13759 .hook = quirk_invert_brightness,
13760 },
13761};
13762
c43b5634 13763static struct intel_quirk intel_quirks[] = {
b690e96c 13764 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 13765 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 13766
b690e96c
JB		 13767 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
13768 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
13769
b690e96c
JB		 13770 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
13771 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
13772
5f080c0f
VS		 13773 /* 830 needs to leave pipe A & dpll A up */
13774 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
13775
b6b5d049
VS		 13776 /* 830 needs to leave pipe B & dpll B up */
13777 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
13778
435793df
KP		 13779 /* Lenovo U160 cannot use SSC on LVDS */
13780 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 13781
13782 /* Sony Vaio Y cannot use SSC on LVDS */
13783 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 13784
be505f64
AH		 13785 /* Acer Aspire 5734Z must invert backlight brightness */
13786 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
13787
13788 /* Acer/eMachines G725 */
13789 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
13790
13791 /* Acer/eMachines e725 */
13792 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
13793
13794 /* Acer/Packard Bell NCL20 */
13795 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
13796
13797 /* Acer Aspire 4736Z */
13798 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 13799
13800 /* Acer Aspire 5336 */
13801 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 13802
13803 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13804 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 13805
dfb3d47b
SD		 13806 /* Acer C720 Chromebook (Core i3 4005U) */
13807 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
13808
b2a9601c 13809 /* Apple Macbook 2,1 (Core 2 T7400) */
13810 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
13811
d4967d8c
SD		 13812 /* Toshiba CB35 Chromebook (Celeron 2955U) */
13813 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 13814
13815 /* HP Chromebook 14 (Celeron 2955U) */
13816 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 13817
13818 /* Dell Chromebook 11 */
13819 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 13820};
13821
13822static void intel_init_quirks(struct drm_device *dev)
13823{
13824 struct pci_dev *d = dev->pdev;
13825 int i;
13826
13827 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
13828 struct intel_quirk *q = &intel_quirks[i];
13829
13830 if (d->device == q->device &&
13831 (d->subsystem_vendor == q->subsystem_vendor ||
13832 q->subsystem_vendor == PCI_ANY_ID) &&
13833 (d->subsystem_device == q->subsystem_device ||
13834 q->subsystem_device == PCI_ANY_ID))
13835 q->hook(dev);
13836 }
5f85f176
EE		 13837 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
13838 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
13839 intel_dmi_quirks[i].hook(dev);
13840 }
b690e96c
JB		 13841}
13842
9cce37f4
JB		 13843/* Disable the VGA plane that we never use */
13844static void i915_disable_vga(struct drm_device *dev)
13845{
13846 struct drm_i915_private *dev_priv = dev->dev_private;
13847 u8 sr1;
766aa1c4 13848 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 13849
2b37c616 13850 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 13851 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 13852 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 13853 sr1 = inb(VGA_SR_DATA);
13854 outb(sr1 | 1<<5, VGA_SR_DATA);
13855 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
13856 udelay(300);
13857
01f5a626 13858 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 13859 POSTING_READ(vga_reg);
13860}
13861
f817586c
DV		 13862void intel_modeset_init_hw(struct drm_device *dev)
13863{
a8f78b58
ED		 13864 intel_prepare_ddi(dev);
13865
f8bf63fd
VS		 13866 if (IS_VALLEYVIEW(dev))
13867 vlv_update_cdclk(dev);
13868
f817586c
DV		 13869 intel_init_clock_gating(dev);
13870
8090c6b9 13871 intel_enable_gt_powersave(dev);
f817586c
DV		 13872}
13873
79e53945
JB		 13874void intel_modeset_init(struct drm_device *dev)
13875{
652c393a 13876 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 13877 int sprite, ret;
8cc87b75 13878 enum pipe pipe;
46f297fb 13879 struct intel_crtc *crtc;
79e53945
JB		 13880
13881 drm_mode_config_init(dev);
13882
13883 dev->mode_config.min_width = 0;
13884 dev->mode_config.min_height = 0;
13885
019d96cb
DA		 13886 dev->mode_config.preferred_depth = 24;
13887 dev->mode_config.prefer_shadow = 1;
13888
25bab385
TU		 13889 dev->mode_config.allow_fb_modifiers = true;
13890
e6ecefaa 13891 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 13892
b690e96c
JB		 13893 intel_init_quirks(dev);
13894
1fa61106
ED		 13895 intel_init_pm(dev);
13896
e3c74757
BW		 13897 if (INTEL_INFO(dev)->num_pipes == 0)
13898 return;
13899
e70236a8 13900 intel_init_display(dev);
7c10a2b5 13901 intel_init_audio(dev);
e70236a8 13902
a6c45cf0
CW		 13903 if (IS_GEN2(dev)) {
13904 dev->mode_config.max_width = 2048;
13905 dev->mode_config.max_height = 2048;
13906 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 13907 dev->mode_config.max_width = 4096;
13908 dev->mode_config.max_height = 4096;
79e53945 13909 } else {
a6c45cf0
CW		 13910 dev->mode_config.max_width = 8192;
13911 dev->mode_config.max_height = 8192;
79e53945 13912 }
068be561 13913
dc41c154
VS		 13914 if (IS_845G(dev) || IS_I865G(dev)) {
13915 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13916 dev->mode_config.cursor_height = 1023;
13917 } else if (IS_GEN2(dev)) {
068be561
DL		 13918 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13919 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13920 } else {
13921 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13922 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13923 }
13924
5d4545ae 13925 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 13926
28c97730 13927 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 13928 INTEL_INFO(dev)->num_pipes,
13929 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 13930
055e393f 13931 for_each_pipe(dev_priv, pipe) {
8cc87b75 13932 intel_crtc_init(dev, pipe);
3bdcfc0c 13933 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 13934 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 13935 if (ret)
06da8da2 13936 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 13937 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 13938 }
79e53945
JB		 13939 }
13940
f42bb70d
JB		 13941 intel_init_dpio(dev);
13942
e72f9fbf 13943 intel_shared_dpll_init(dev);
ee7b9f93 13944
9cce37f4
JB		 13945 /* Just disable it once at startup */
13946 i915_disable_vga(dev);
79e53945 13947 intel_setup_outputs(dev);
11be49eb
CW		 13948
13949 /* Just in case the BIOS is doing something questionable. */
7ff0ebcc 13950 intel_fbc_disable(dev);
fa9fa083 13951
6e9f798d 13952 drm_modeset_lock_all(dev);
fa9fa083 13953 intel_modeset_setup_hw_state(dev, false);
6e9f798d 13954 drm_modeset_unlock_all(dev);
46f297fb 13955
d3fcc808 13956 for_each_intel_crtc(dev, crtc) {
46f297fb
JB		 13957 if (!crtc->active)
13958 continue;
13959
46f297fb 13960 /*
46f297fb
JB		 13961 * Note that reserving the BIOS fb up front prevents us
13962 * from stuffing other stolen allocations like the ring
13963 * on top. This prevents some ugliness at boot time, and
13964 * can even allow for smooth boot transitions if the BIOS
13965 * fb is large enough for the active pipe configuration.
13966 */
5724dbd1
DL		 13967 if (dev_priv->display.get_initial_plane_config) {
13968 dev_priv->display.get_initial_plane_config(crtc,
46f297fb
JB		 13969 &crtc->plane_config);
13970 /*
13971 * If the fb is shared between multiple heads, we'll
13972 * just get the first one.
13973 */
f6936e29 13974 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
46f297fb 13975 }
46f297fb 13976 }
2c7111db
CW		 13977}
13978
7fad798e
DV		 13979static void intel_enable_pipe_a(struct drm_device *dev)
13980{
13981 struct intel_connector *connector;
13982 struct drm_connector *crt = NULL;
13983 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 13984 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 13985
13986 /* We can't just switch on the pipe A, we need to set things up with a
13987 * proper mode and output configuration. As a gross hack, enable pipe A
13988 * by enabling the load detect pipe once. */
3a3371ff 13989 for_each_intel_connector(dev, connector) {
7fad798e
DV		 13990 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13991 crt = &connector->base;
13992 break;
13993 }
13994 }
13995
13996 if (!crt)
13997 return;
13998
208bf9fd 13999 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 14000 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 14001}
14002
fa555837
DV		 14003static bool
14004intel_check_plane_mapping(struct intel_crtc *crtc)
14005{
7eb552ae
BW		 14006 struct drm_device *dev = crtc->base.dev;
14007 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 14008 u32 reg, val;
14009
7eb552ae 14010 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 14011 return true;
14012
14013 reg = DSPCNTR(!crtc->plane);
14014 val = I915_READ(reg);
14015
14016 if ((val & DISPLAY_PLANE_ENABLE) &&
14017 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14018 return false;
14019
14020 return true;
14021}
14022
24929352
DV		 14023static void intel_sanitize_crtc(struct intel_crtc *crtc)
14024{
14025 struct drm_device *dev = crtc->base.dev;
14026 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 14027 u32 reg;
24929352 14028
24929352 14029 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 14030 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 14031 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14032
d3eaf884 14033 /* restore vblank interrupts to correct state */
9625604c 14034 drm_crtc_vblank_reset(&crtc->base);
d297e103
VS		 14035 if (crtc->active) {
14036 update_scanline_offset(crtc);
9625604c
DV		 14037 drm_crtc_vblank_on(&crtc->base);
14038 }
d3eaf884 14039
24929352 14040 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 14041 * disable the crtc (and hence change the state) if it is wrong. Note
14042 * that gen4+ has a fixed plane -> pipe mapping. */
14043 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 14044 struct intel_connector *connector;
14045 bool plane;
14046
24929352
DV		 14047 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14048 crtc->base.base.id);
14049
14050 /* Pipe has the wrong plane attached and the plane is active.
14051 * Temporarily change the plane mapping and disable everything
14052 * ... */
14053 plane = crtc->plane;
14054 crtc->plane = !plane;
9c8958bc 14055 crtc->primary_enabled = true;
24929352
DV		 14056 dev_priv->display.crtc_disable(&crtc->base);
14057 crtc->plane = plane;
14058
14059 /* ... and break all links. */
3a3371ff 14060 for_each_intel_connector(dev, connector) {
24929352
DV		 14061 if (connector->encoder->base.crtc != &crtc->base)
14062 continue;
14063
7f1950fb
EE		 14064 connector->base.dpms = DRM_MODE_DPMS_OFF;
14065 connector->base.encoder = NULL;
24929352 14066 }
7f1950fb
EE		 14067 /* multiple connectors may have the same encoder:
14068 * handle them and break crtc link separately */
3a3371ff 14069 for_each_intel_connector(dev, connector)
7f1950fb
EE		 14070 if (connector->encoder->base.crtc == &crtc->base) {
14071 connector->encoder->base.crtc = NULL;
14072 connector->encoder->connectors_active = false;
14073 }
24929352
DV		 14074
14075 WARN_ON(crtc->active);
83d65738 14076 crtc->base.state->enable = false;
24929352
DV		 14077 crtc->base.enabled = false;
14078 }
24929352 14079
7fad798e
DV		 14080 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14081 crtc->pipe == PIPE_A && !crtc->active) {
14082 /* BIOS forgot to enable pipe A, this mostly happens after
14083 * resume. Force-enable the pipe to fix this, the update_dpms
14084 * call below we restore the pipe to the right state, but leave
14085 * the required bits on. */
14086 intel_enable_pipe_a(dev);
14087 }
14088
24929352
DV		 14089 /* Adjust the state of the output pipe according to whether we
14090 * have active connectors/encoders. */
14091 intel_crtc_update_dpms(&crtc->base);
14092
83d65738 14093 if (crtc->active != crtc->base.state->enable) {
24929352
DV		 14094 struct intel_encoder *encoder;
14095
14096 /* This can happen either due to bugs in the get_hw_state
14097 * functions or because the pipe is force-enabled due to the
14098 * pipe A quirk. */
14099 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14100 crtc->base.base.id,
83d65738 14101 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 14102 crtc->active ? "enabled" : "disabled");
14103
83d65738 14104 crtc->base.state->enable = crtc->active;
24929352
DV		 14105 crtc->base.enabled = crtc->active;
14106
14107 /* Because we only establish the connector -> encoder ->
14108 * crtc links if something is active, this means the
14109 * crtc is now deactivated. Break the links. connector
14110 * -> encoder links are only establish when things are
14111 * actually up, hence no need to break them. */
14112 WARN_ON(crtc->active);
14113
14114 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14115 WARN_ON(encoder->connectors_active);
14116 encoder->base.crtc = NULL;
14117 }
14118 }
c5ab3bc0 14119
a3ed6aad 14120 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 14121 /*
14122 * We start out with underrun reporting disabled to avoid races.
14123 * For correct bookkeeping mark this on active crtcs.
14124 *
c5ab3bc0
DV		 14125 * Also on gmch platforms we dont have any hardware bits to
14126 * disable the underrun reporting. Which means we need to start
14127 * out with underrun reporting disabled also on inactive pipes,
14128 * since otherwise we'll complain about the garbage we read when
14129 * e.g. coming up after runtime pm.
14130 *
4cc31489
DV		 14131 * No protection against concurrent access is required - at
14132 * worst a fifo underrun happens which also sets this to false.
14133 */
14134 crtc->cpu_fifo_underrun_disabled = true;
14135 crtc->pch_fifo_underrun_disabled = true;
14136 }
24929352
DV		 14137}
14138
14139static void intel_sanitize_encoder(struct intel_encoder *encoder)
14140{
14141 struct intel_connector *connector;
14142 struct drm_device *dev = encoder->base.dev;
14143
14144 /* We need to check both for a crtc link (meaning that the
14145 * encoder is active and trying to read from a pipe) and the
14146 * pipe itself being active. */
14147 bool has_active_crtc = encoder->base.crtc &&
14148 to_intel_crtc(encoder->base.crtc)->active;
14149
14150 if (encoder->connectors_active && !has_active_crtc) {
14151 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14152 encoder->base.base.id,
8e329a03 14153 encoder->base.name);
24929352
DV		 14154
14155 /* Connector is active, but has no active pipe. This is
14156 * fallout from our resume register restoring. Disable
14157 * the encoder manually again. */
14158 if (encoder->base.crtc) {
14159 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14160 encoder->base.base.id,
8e329a03 14161 encoder->base.name);
24929352 14162 encoder->disable(encoder);
a62d1497
VS		 14163 if (encoder->post_disable)
14164 encoder->post_disable(encoder);
24929352 14165 }
7f1950fb
EE		 14166 encoder->base.crtc = NULL;
14167 encoder->connectors_active = false;
24929352
DV		 14168
14169 /* Inconsistent output/port/pipe state happens presumably due to
14170 * a bug in one of the get_hw_state functions. Or someplace else
14171 * in our code, like the register restore mess on resume. Clamp
14172 * things to off as a safer default. */
3a3371ff 14173 for_each_intel_connector(dev, connector) {
24929352
DV		 14174 if (connector->encoder != encoder)
14175 continue;
7f1950fb
EE		 14176 connector->base.dpms = DRM_MODE_DPMS_OFF;
14177 connector->base.encoder = NULL;
24929352
DV		 14178 }
14179 }
14180 /* Enabled encoders without active connectors will be fixed in
14181 * the crtc fixup. */
14182}
14183
04098753 14184void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 14185{
14186 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 14187 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 14188
04098753
ID		 14189 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14190 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14191 i915_disable_vga(dev);
14192 }
14193}
14194
14195void i915_redisable_vga(struct drm_device *dev)
14196{
14197 struct drm_i915_private *dev_priv = dev->dev_private;
14198
8dc8a27c
PZ		 14199 /* This function can be called both from intel_modeset_setup_hw_state or
14200 * at a very early point in our resume sequence, where the power well
14201 * structures are not yet restored. Since this function is at a very
14202 * paranoid "someone might have enabled VGA while we were not looking"
14203 * level, just check if the power well is enabled instead of trying to
14204 * follow the "don't touch the power well if we don't need it" policy
14205 * the rest of the driver uses. */
f458ebbc 14206 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 14207 return;
14208
04098753 14209 i915_redisable_vga_power_on(dev);
0fde901f
KM		 14210}
14211
98ec7739
VS		 14212static bool primary_get_hw_state(struct intel_crtc *crtc)
14213{
14214 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
14215
14216 if (!crtc->active)
14217 return false;
14218
14219 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
14220}
14221
30e984df 14222static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 14223{
14224 struct drm_i915_private *dev_priv = dev->dev_private;
14225 enum pipe pipe;
24929352
DV		 14226 struct intel_crtc *crtc;
14227 struct intel_encoder *encoder;
14228 struct intel_connector *connector;
5358901f 14229 int i;
24929352 14230
d3fcc808 14231 for_each_intel_crtc(dev, crtc) {
6e3c9717 14232 memset(crtc->config, 0, sizeof(*crtc->config));
3b117c8f 14233
6e3c9717 14234 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
9953599b 14235
0e8ffe1b 14236 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 14237 crtc->config);
24929352 14238
83d65738 14239 crtc->base.state->enable = crtc->active;
24929352 14240 crtc->base.enabled = crtc->active;
98ec7739 14241 crtc->primary_enabled = primary_get_hw_state(crtc);
24929352
DV		 14242
14243 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
14244 crtc->base.base.id,
14245 crtc->active ? "enabled" : "disabled");
14246 }
14247
5358901f
DV		 14248 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14249 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14250
3e369b76
ACO		 14251 pll->on = pll->get_hw_state(dev_priv, pll,
14252 &pll->config.hw_state);
5358901f 14253 pll->active = 0;
3e369b76 14254 pll->config.crtc_mask = 0;
d3fcc808 14255 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 14256 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 14257 pll->active++;
3e369b76 14258 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 14259 }
5358901f 14260 }
5358901f 14261
1e6f2ddc 14262 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 14263 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 14264
3e369b76 14265 if (pll->config.crtc_mask)
bd2bb1b9 14266 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 14267 }
14268
b2784e15 14269 for_each_intel_encoder(dev, encoder) {
24929352
DV		 14270 pipe = 0;
14271
14272 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 14273 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14274 encoder->base.crtc = &crtc->base;
6e3c9717 14275 encoder->get_config(encoder, crtc->config);
24929352
DV		 14276 } else {
14277 encoder->base.crtc = NULL;
14278 }
14279
14280 encoder->connectors_active = false;
6f2bcceb 14281 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 14282 encoder->base.base.id,
8e329a03 14283 encoder->base.name,
24929352 14284 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 14285 pipe_name(pipe));
24929352
DV		 14286 }
14287
3a3371ff 14288 for_each_intel_connector(dev, connector) {
24929352
DV		 14289 if (connector->get_hw_state(connector)) {
14290 connector->base.dpms = DRM_MODE_DPMS_ON;
14291 connector->encoder->connectors_active = true;
14292 connector->base.encoder = &connector->encoder->base;
14293 } else {
14294 connector->base.dpms = DRM_MODE_DPMS_OFF;
14295 connector->base.encoder = NULL;
14296 }
14297 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
14298 connector->base.base.id,
c23cc417 14299 connector->base.name,
24929352
DV		 14300 connector->base.encoder ? "enabled" : "disabled");
14301 }
30e984df
DV		 14302}
14303
14304/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
14305 * and i915 state tracking structures. */
14306void intel_modeset_setup_hw_state(struct drm_device *dev,
14307 bool force_restore)
14308{
14309 struct drm_i915_private *dev_priv = dev->dev_private;
14310 enum pipe pipe;
30e984df
DV		 14311 struct intel_crtc *crtc;
14312 struct intel_encoder *encoder;
35c95375 14313 int i;
30e984df
DV		 14314
14315 intel_modeset_readout_hw_state(dev);
24929352 14316
babea61d
JB		 14317 /*
14318 * Now that we have the config, copy it to each CRTC struct
14319 * Note that this could go away if we move to using crtc_config
14320 * checking everywhere.
14321 */
d3fcc808 14322 for_each_intel_crtc(dev, crtc) {
d330a953 14323 if (crtc->active && i915.fastboot) {
6e3c9717
ACO		 14324 intel_mode_from_pipe_config(&crtc->base.mode,
14325 crtc->config);
babea61d
JB		 14326 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
14327 crtc->base.base.id);
14328 drm_mode_debug_printmodeline(&crtc->base.mode);
14329 }
14330 }
14331
24929352 14332 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 14333 for_each_intel_encoder(dev, encoder) {
24929352
DV		 14334 intel_sanitize_encoder(encoder);
14335 }
14336
055e393f 14337 for_each_pipe(dev_priv, pipe) {
24929352
DV		 14338 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14339 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 14340 intel_dump_pipe_config(crtc, crtc->config,
14341 "[setup_hw_state]");
24929352 14342 }
9a935856 14343
d29b2f9d
ACO		 14344 intel_modeset_update_connector_atomic_state(dev);
14345
35c95375
DV		 14346 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14347 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14348
14349 if (!pll->on || pll->active)
14350 continue;
14351
14352 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
14353
14354 pll->disable(dev_priv, pll);
14355 pll->on = false;
14356 }
14357
3078999f
PB		 14358 if (IS_GEN9(dev))
14359 skl_wm_get_hw_state(dev);
14360 else if (HAS_PCH_SPLIT(dev))
243e6a44
VS		 14361 ilk_wm_get_hw_state(dev);
14362
45e2b5f6 14363 if (force_restore) {
7d0bc1ea
VS		 14364 i915_redisable_vga(dev);
14365
f30da187
DV		 14366 /*
14367 * We need to use raw interfaces for restoring state to avoid
14368 * checking (bogus) intermediate states.
14369 */
055e393f 14370 for_each_pipe(dev_priv, pipe) {
b5644d05
JB		 14371 struct drm_crtc *crtc =
14372 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187 14373
83a57153 14374 intel_crtc_restore_mode(crtc);
45e2b5f6
DV		 14375 }
14376 } else {
14377 intel_modeset_update_staged_output_state(dev);
14378 }
8af6cf88
DV		 14379
14380 intel_modeset_check_state(dev);
2c7111db
CW		 14381}
14382
14383void intel_modeset_gem_init(struct drm_device *dev)
14384{
92122789 14385 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd 14386 struct drm_crtc *c;
2ff8fde1 14387 struct drm_i915_gem_object *obj;
484b41dd 14388
ae48434c
ID		 14389 mutex_lock(&dev->struct_mutex);
14390 intel_init_gt_powersave(dev);
14391 mutex_unlock(&dev->struct_mutex);
14392
92122789
JB		 14393 /*
14394 * There may be no VBT; and if the BIOS enabled SSC we can
14395 * just keep using it to avoid unnecessary flicker. Whereas if the
14396 * BIOS isn't using it, don't assume it will work even if the VBT
14397 * indicates as much.
14398 */
14399 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
14400 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14401 DREF_SSC1_ENABLE);
14402
1833b134 14403 intel_modeset_init_hw(dev);
02e792fb
DV		 14404
14405 intel_setup_overlay(dev);
484b41dd
JB		 14406
14407 /*
14408 * Make sure any fbs we allocated at startup are properly
14409 * pinned & fenced. When we do the allocation it's too early
14410 * for this.
14411 */
14412 mutex_lock(&dev->struct_mutex);
70e1e0ec 14413 for_each_crtc(dev, c) {
2ff8fde1
MR		 14414 obj = intel_fb_obj(c->primary->fb);
14415 if (obj == NULL)
484b41dd
JB		 14416 continue;
14417
850c4cdc
TU		 14418 if (intel_pin_and_fence_fb_obj(c->primary,
14419 c->primary->fb,
82bc3b2d 14420 c->primary->state,
850c4cdc 14421 NULL)) {
484b41dd
JB		 14422 DRM_ERROR("failed to pin boot fb on pipe %d\n",
14423 to_intel_crtc(c)->pipe);
66e514c1
DA		 14424 drm_framebuffer_unreference(c->primary->fb);
14425 c->primary->fb = NULL;
afd65eb4 14426 update_state_fb(c->primary);
484b41dd
JB		 14427 }
14428 }
14429 mutex_unlock(&dev->struct_mutex);
0962c3c9
VS		 14430
14431 intel_backlight_register(dev);
79e53945
JB		 14432}
14433
4932e2c3
ID		 14434void intel_connector_unregister(struct intel_connector *intel_connector)
14435{
14436 struct drm_connector *connector = &intel_connector->base;
14437
14438 intel_panel_destroy_backlight(connector);
34ea3d38 14439 drm_connector_unregister(connector);
4932e2c3
ID		 14440}
14441
79e53945
JB		 14442void intel_modeset_cleanup(struct drm_device *dev)
14443{
652c393a 14444 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 14445 struct drm_connector *connector;
652c393a 14446
2eb5252e
ID		 14447 intel_disable_gt_powersave(dev);
14448
0962c3c9
VS		 14449 intel_backlight_unregister(dev);
14450
fd0c0642
DV		 14451 /*
14452 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 14453 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 14454 * experience fancy races otherwise.
14455 */
2aeb7d3a 14456 intel_irq_uninstall(dev_priv);
eb21b92b 14457
fd0c0642
DV		 14458 /*
14459 * Due to the hpd irq storm handling the hotplug work can re-arm the
14460 * poll handlers. Hence disable polling after hpd handling is shut down.
14461 */
f87ea761 14462 drm_kms_helper_poll_fini(dev);
fd0c0642 14463
652c393a
JB		 14464 mutex_lock(&dev->struct_mutex);
14465
723bfd70
JB		 14466 intel_unregister_dsm_handler();
14467
7ff0ebcc 14468 intel_fbc_disable(dev);
e70236a8 14469
69341a5e
KH		 14470 mutex_unlock(&dev->struct_mutex);
14471
1630fe75
CW		 14472 /* flush any delayed tasks or pending work */
14473 flush_scheduled_work();
14474
db31af1d
JN		 14475 /* destroy the backlight and sysfs files before encoders/connectors */
14476 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 14477 struct intel_connector *intel_connector;
14478
14479 intel_connector = to_intel_connector(connector);
14480 intel_connector->unregister(intel_connector);
db31af1d 14481 }
d9255d57 14482
79e53945 14483 drm_mode_config_cleanup(dev);
4d7bb011
DV		 14484
14485 intel_cleanup_overlay(dev);
ae48434c
ID		 14486
14487 mutex_lock(&dev->struct_mutex);
14488 intel_cleanup_gt_powersave(dev);
14489 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 14490}
14491
f1c79df3
ZW		 14492/*
14493 * Return which encoder is currently attached for connector.
14494 */
df0e9248 14495struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 14496{
df0e9248
CW		 14497 return &intel_attached_encoder(connector)->base;
14498}
f1c79df3 14499
df0e9248
CW		 14500void intel_connector_attach_encoder(struct intel_connector *connector,
14501 struct intel_encoder *encoder)
14502{
14503 connector->encoder = encoder;
14504 drm_mode_connector_attach_encoder(&connector->base,
14505 &encoder->base);
79e53945 14506}
28d52043
DA		 14507
14508/*
14509 * set vga decode state - true == enable VGA decode
14510 */
14511int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
14512{
14513 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 14514 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 14515 u16 gmch_ctrl;
14516
75fa041d
CW		 14517 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
14518 DRM_ERROR("failed to read control word\n");
14519 return -EIO;
14520 }
14521
c0cc8a55
CW		 14522 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
14523 return 0;
14524
28d52043
DA		 14525 if (state)
14526 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
14527 else
14528 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 14529
14530 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
14531 DRM_ERROR("failed to write control word\n");
14532 return -EIO;
14533 }
14534
28d52043
DA		 14535 return 0;
14536}
c4a1d9e4 14537
c4a1d9e4 14538struct intel_display_error_state {
ff57f1b0
PZ		 14539
14540 u32 power_well_driver;
14541
63b66e5b
CW		 14542 int num_transcoders;
14543
c4a1d9e4
CW		 14544 struct intel_cursor_error_state {
14545 u32 control;
14546 u32 position;
14547 u32 base;
14548 u32 size;
52331309 14549 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 14550
14551 struct intel_pipe_error_state {
ddf9c536 14552 bool power_domain_on;
c4a1d9e4 14553 u32 source;
f301b1e1 14554 u32 stat;
52331309 14555 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 14556
14557 struct intel_plane_error_state {
14558 u32 control;
14559 u32 stride;
14560 u32 size;
14561 u32 pos;
14562 u32 addr;
14563 u32 surface;
14564 u32 tile_offset;
52331309 14565 } plane[I915_MAX_PIPES];
63b66e5b
CW		 14566
14567 struct intel_transcoder_error_state {
ddf9c536 14568 bool power_domain_on;
63b66e5b
CW		 14569 enum transcoder cpu_transcoder;
14570
14571 u32 conf;
14572
14573 u32 htotal;
14574 u32 hblank;
14575 u32 hsync;
14576 u32 vtotal;
14577 u32 vblank;
14578 u32 vsync;
14579 } transcoder[4];
c4a1d9e4
CW		 14580};
14581
14582struct intel_display_error_state *
14583intel_display_capture_error_state(struct drm_device *dev)
14584{
fbee40df 14585 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 14586 struct intel_display_error_state *error;
63b66e5b
CW		 14587 int transcoders[] = {
14588 TRANSCODER_A,
14589 TRANSCODER_B,
14590 TRANSCODER_C,
14591 TRANSCODER_EDP,
14592 };
c4a1d9e4
CW		 14593 int i;
14594
63b66e5b
CW		 14595 if (INTEL_INFO(dev)->num_pipes == 0)
14596 return NULL;
14597
9d1cb914 14598 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 14599 if (error == NULL)
14600 return NULL;
14601
190be112 14602 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 14603 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
14604
055e393f 14605 for_each_pipe(dev_priv, i) {
ddf9c536 14606 error->pipe[i].power_domain_on =
f458ebbc
DV		 14607 __intel_display_power_is_enabled(dev_priv,
14608 POWER_DOMAIN_PIPE(i));
ddf9c536 14609 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 14610 continue;
14611
5efb3e28
VS		 14612 error->cursor[i].control = I915_READ(CURCNTR(i));
14613 error->cursor[i].position = I915_READ(CURPOS(i));
14614 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 14615
14616 error->plane[i].control = I915_READ(DSPCNTR(i));
14617 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 14618 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 14619 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 14620 error->plane[i].pos = I915_READ(DSPPOS(i));
14621 }
ca291363
PZ		 14622 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14623 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 14624 if (INTEL_INFO(dev)->gen >= 4) {
14625 error->plane[i].surface = I915_READ(DSPSURF(i));
14626 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
14627 }
14628
c4a1d9e4 14629 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 14630
3abfce77 14631 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 14632 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 14633 }
14634
14635 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
14636 if (HAS_DDI(dev_priv->dev))
14637 error->num_transcoders++; /* Account for eDP. */
14638
14639 for (i = 0; i < error->num_transcoders; i++) {
14640 enum transcoder cpu_transcoder = transcoders[i];
14641
ddf9c536 14642 error->transcoder[i].power_domain_on =
f458ebbc 14643 __intel_display_power_is_enabled(dev_priv,
38cc1daf 14644 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 14645 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 14646 continue;
14647
63b66e5b
CW		 14648 error->transcoder[i].cpu_transcoder = cpu_transcoder;
14649
14650 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
14651 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
14652 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
14653 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
14654 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
14655 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
14656 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 14657 }
14658
14659 return error;
14660}
14661
edc3d884
MK		 14662#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
14663
c4a1d9e4 14664void
edc3d884 14665intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 14666 struct drm_device *dev,
14667 struct intel_display_error_state *error)
14668{
055e393f 14669 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 14670 int i;
14671
63b66e5b
CW		 14672 if (!error)
14673 return;
14674
edc3d884 14675 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 14676 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 14677 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 14678 error->power_well_driver);
055e393f 14679 for_each_pipe(dev_priv, i) {
edc3d884 14680 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 14681 err_printf(m, " Power: %s\n",
14682 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 14683 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 14684 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 14685
14686 err_printf(m, "Plane [%d]:\n", i);
14687 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
14688 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 14689 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 14690 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
14691 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 14692 }
4b71a570 14693 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 14694 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 14695 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 14696 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
14697 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 14698 }
14699
edc3d884
MK		 14700 err_printf(m, "Cursor [%d]:\n", i);
14701 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
14702 err_printf(m, " POS: %08x\n", error->cursor[i].position);
14703 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 14704 }
63b66e5b
CW		 14705
14706 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 14707 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 14708 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 14709 err_printf(m, " Power: %s\n",
14710 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 14711 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
14712 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
14713 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
14714 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
14715 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
14716 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
14717 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
14718 }
c4a1d9e4 14719}
e2fcdaa9
VS		 14720
14721void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
14722{
14723 struct intel_crtc *crtc;
14724
14725 for_each_intel_crtc(dev, crtc) {
14726 struct intel_unpin_work *work;
e2fcdaa9 14727
5e2d7afc 14728 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 14729
14730 work = crtc->unpin_work;
14731
14732 if (work && work->event &&
14733 work->event->base.file_priv == file) {
14734 kfree(work->event);
14735 work->event = NULL;
14736 }
14737
5e2d7afc 14738 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 14739 }
14740}
Linux kernel - Deliverables
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