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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
23b2f8bb | 27 | #include <linux/cpufreq.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
79e53945 JB |
35 | #include "drmP.h" |
36 | #include "intel_drv.h" | |
37 | #include "i915_drm.h" | |
38 | #include "i915_drv.h" | |
e5510fac | 39 | #include "i915_trace.h" |
ab2c0672 | 40 | #include "drm_dp_helper.h" |
79e53945 | 41 | #include "drm_crtc_helper.h" |
c0f372b3 | 42 | #include <linux/dma_remapping.h> |
79e53945 | 43 | |
32f9d658 ZW |
44 | #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) |
45 | ||
0206e353 | 46 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type); |
7662c8bd | 47 | static void intel_update_watermarks(struct drm_device *dev); |
3dec0095 | 48 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
6b383a7f | 49 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 JB |
50 | |
51 | typedef struct { | |
0206e353 AJ |
52 | /* given values */ |
53 | int n; | |
54 | int m1, m2; | |
55 | int p1, p2; | |
56 | /* derived values */ | |
57 | int dot; | |
58 | int vco; | |
59 | int m; | |
60 | int p; | |
79e53945 JB |
61 | } intel_clock_t; |
62 | ||
63 | typedef struct { | |
0206e353 | 64 | int min, max; |
79e53945 JB |
65 | } intel_range_t; |
66 | ||
67 | typedef struct { | |
0206e353 AJ |
68 | int dot_limit; |
69 | int p2_slow, p2_fast; | |
79e53945 JB |
70 | } intel_p2_t; |
71 | ||
72 | #define INTEL_P2_NUM 2 | |
d4906093 ML |
73 | typedef struct intel_limit intel_limit_t; |
74 | struct intel_limit { | |
0206e353 AJ |
75 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
76 | intel_p2_t p2; | |
77 | bool (* find_pll)(const intel_limit_t *, struct drm_crtc *, | |
cec2f356 | 78 | int, int, intel_clock_t *, intel_clock_t *); |
d4906093 | 79 | }; |
79e53945 | 80 | |
2377b741 JB |
81 | /* FDI */ |
82 | #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */ | |
83 | ||
d4906093 ML |
84 | static bool |
85 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
86 | int target, int refclk, intel_clock_t *match_clock, |
87 | intel_clock_t *best_clock); | |
d4906093 ML |
88 | static bool |
89 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
90 | int target, int refclk, intel_clock_t *match_clock, |
91 | intel_clock_t *best_clock); | |
79e53945 | 92 | |
a4fc5ed6 KP |
93 | static bool |
94 | intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc, | |
cec2f356 SP |
95 | int target, int refclk, intel_clock_t *match_clock, |
96 | intel_clock_t *best_clock); | |
5eb08b69 | 97 | static bool |
f2b115e6 | 98 | intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc, |
cec2f356 SP |
99 | int target, int refclk, intel_clock_t *match_clock, |
100 | intel_clock_t *best_clock); | |
a4fc5ed6 | 101 | |
021357ac CW |
102 | static inline u32 /* units of 100MHz */ |
103 | intel_fdi_link_freq(struct drm_device *dev) | |
104 | { | |
8b99e68c CW |
105 | if (IS_GEN5(dev)) { |
106 | struct drm_i915_private *dev_priv = dev->dev_private; | |
107 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
108 | } else | |
109 | return 27; | |
021357ac CW |
110 | } |
111 | ||
e4b36699 | 112 | static const intel_limit_t intel_limits_i8xx_dvo = { |
0206e353 AJ |
113 | .dot = { .min = 25000, .max = 350000 }, |
114 | .vco = { .min = 930000, .max = 1400000 }, | |
115 | .n = { .min = 3, .max = 16 }, | |
116 | .m = { .min = 96, .max = 140 }, | |
117 | .m1 = { .min = 18, .max = 26 }, | |
118 | .m2 = { .min = 6, .max = 16 }, | |
119 | .p = { .min = 4, .max = 128 }, | |
120 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
121 | .p2 = { .dot_limit = 165000, |
122 | .p2_slow = 4, .p2_fast = 2 }, | |
d4906093 | 123 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
124 | }; |
125 | ||
126 | static const intel_limit_t intel_limits_i8xx_lvds = { | |
0206e353 AJ |
127 | .dot = { .min = 25000, .max = 350000 }, |
128 | .vco = { .min = 930000, .max = 1400000 }, | |
129 | .n = { .min = 3, .max = 16 }, | |
130 | .m = { .min = 96, .max = 140 }, | |
131 | .m1 = { .min = 18, .max = 26 }, | |
132 | .m2 = { .min = 6, .max = 16 }, | |
133 | .p = { .min = 4, .max = 128 }, | |
134 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
135 | .p2 = { .dot_limit = 165000, |
136 | .p2_slow = 14, .p2_fast = 7 }, | |
d4906093 | 137 | .find_pll = intel_find_best_PLL, |
e4b36699 | 138 | }; |
273e27ca | 139 | |
e4b36699 | 140 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
141 | .dot = { .min = 20000, .max = 400000 }, |
142 | .vco = { .min = 1400000, .max = 2800000 }, | |
143 | .n = { .min = 1, .max = 6 }, | |
144 | .m = { .min = 70, .max = 120 }, | |
145 | .m1 = { .min = 10, .max = 22 }, | |
146 | .m2 = { .min = 5, .max = 9 }, | |
147 | .p = { .min = 5, .max = 80 }, | |
148 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
149 | .p2 = { .dot_limit = 200000, |
150 | .p2_slow = 10, .p2_fast = 5 }, | |
d4906093 | 151 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
152 | }; |
153 | ||
154 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
155 | .dot = { .min = 20000, .max = 400000 }, |
156 | .vco = { .min = 1400000, .max = 2800000 }, | |
157 | .n = { .min = 1, .max = 6 }, | |
158 | .m = { .min = 70, .max = 120 }, | |
159 | .m1 = { .min = 10, .max = 22 }, | |
160 | .m2 = { .min = 5, .max = 9 }, | |
161 | .p = { .min = 7, .max = 98 }, | |
162 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
163 | .p2 = { .dot_limit = 112000, |
164 | .p2_slow = 14, .p2_fast = 7 }, | |
d4906093 | 165 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
166 | }; |
167 | ||
273e27ca | 168 | |
e4b36699 | 169 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
170 | .dot = { .min = 25000, .max = 270000 }, |
171 | .vco = { .min = 1750000, .max = 3500000}, | |
172 | .n = { .min = 1, .max = 4 }, | |
173 | .m = { .min = 104, .max = 138 }, | |
174 | .m1 = { .min = 17, .max = 23 }, | |
175 | .m2 = { .min = 5, .max = 11 }, | |
176 | .p = { .min = 10, .max = 30 }, | |
177 | .p1 = { .min = 1, .max = 3}, | |
178 | .p2 = { .dot_limit = 270000, | |
179 | .p2_slow = 10, | |
180 | .p2_fast = 10 | |
044c7c41 | 181 | }, |
d4906093 | 182 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
183 | }; |
184 | ||
185 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
186 | .dot = { .min = 22000, .max = 400000 }, |
187 | .vco = { .min = 1750000, .max = 3500000}, | |
188 | .n = { .min = 1, .max = 4 }, | |
189 | .m = { .min = 104, .max = 138 }, | |
190 | .m1 = { .min = 16, .max = 23 }, | |
191 | .m2 = { .min = 5, .max = 11 }, | |
192 | .p = { .min = 5, .max = 80 }, | |
193 | .p1 = { .min = 1, .max = 8}, | |
194 | .p2 = { .dot_limit = 165000, | |
195 | .p2_slow = 10, .p2_fast = 5 }, | |
d4906093 | 196 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
197 | }; |
198 | ||
199 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
200 | .dot = { .min = 20000, .max = 115000 }, |
201 | .vco = { .min = 1750000, .max = 3500000 }, | |
202 | .n = { .min = 1, .max = 3 }, | |
203 | .m = { .min = 104, .max = 138 }, | |
204 | .m1 = { .min = 17, .max = 23 }, | |
205 | .m2 = { .min = 5, .max = 11 }, | |
206 | .p = { .min = 28, .max = 112 }, | |
207 | .p1 = { .min = 2, .max = 8 }, | |
208 | .p2 = { .dot_limit = 0, | |
209 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 210 | }, |
d4906093 | 211 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
212 | }; |
213 | ||
214 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
215 | .dot = { .min = 80000, .max = 224000 }, |
216 | .vco = { .min = 1750000, .max = 3500000 }, | |
217 | .n = { .min = 1, .max = 3 }, | |
218 | .m = { .min = 104, .max = 138 }, | |
219 | .m1 = { .min = 17, .max = 23 }, | |
220 | .m2 = { .min = 5, .max = 11 }, | |
221 | .p = { .min = 14, .max = 42 }, | |
222 | .p1 = { .min = 2, .max = 6 }, | |
223 | .p2 = { .dot_limit = 0, | |
224 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 225 | }, |
d4906093 | 226 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
227 | }; |
228 | ||
229 | static const intel_limit_t intel_limits_g4x_display_port = { | |
0206e353 AJ |
230 | .dot = { .min = 161670, .max = 227000 }, |
231 | .vco = { .min = 1750000, .max = 3500000}, | |
232 | .n = { .min = 1, .max = 2 }, | |
233 | .m = { .min = 97, .max = 108 }, | |
234 | .m1 = { .min = 0x10, .max = 0x12 }, | |
235 | .m2 = { .min = 0x05, .max = 0x06 }, | |
236 | .p = { .min = 10, .max = 20 }, | |
237 | .p1 = { .min = 1, .max = 2}, | |
238 | .p2 = { .dot_limit = 0, | |
273e27ca | 239 | .p2_slow = 10, .p2_fast = 10 }, |
0206e353 | 240 | .find_pll = intel_find_pll_g4x_dp, |
e4b36699 KP |
241 | }; |
242 | ||
f2b115e6 | 243 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
244 | .dot = { .min = 20000, .max = 400000}, |
245 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 246 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
247 | .n = { .min = 3, .max = 6 }, |
248 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 249 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
250 | .m1 = { .min = 0, .max = 0 }, |
251 | .m2 = { .min = 0, .max = 254 }, | |
252 | .p = { .min = 5, .max = 80 }, | |
253 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
254 | .p2 = { .dot_limit = 200000, |
255 | .p2_slow = 10, .p2_fast = 5 }, | |
6115707b | 256 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
257 | }; |
258 | ||
f2b115e6 | 259 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
260 | .dot = { .min = 20000, .max = 400000 }, |
261 | .vco = { .min = 1700000, .max = 3500000 }, | |
262 | .n = { .min = 3, .max = 6 }, | |
263 | .m = { .min = 2, .max = 256 }, | |
264 | .m1 = { .min = 0, .max = 0 }, | |
265 | .m2 = { .min = 0, .max = 254 }, | |
266 | .p = { .min = 7, .max = 112 }, | |
267 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
268 | .p2 = { .dot_limit = 112000, |
269 | .p2_slow = 14, .p2_fast = 14 }, | |
6115707b | 270 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
271 | }; |
272 | ||
273e27ca EA |
273 | /* Ironlake / Sandybridge |
274 | * | |
275 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
276 | * the range value for them is (actual_value - 2). | |
277 | */ | |
b91ad0ec | 278 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
279 | .dot = { .min = 25000, .max = 350000 }, |
280 | .vco = { .min = 1760000, .max = 3510000 }, | |
281 | .n = { .min = 1, .max = 5 }, | |
282 | .m = { .min = 79, .max = 127 }, | |
283 | .m1 = { .min = 12, .max = 22 }, | |
284 | .m2 = { .min = 5, .max = 9 }, | |
285 | .p = { .min = 5, .max = 80 }, | |
286 | .p1 = { .min = 1, .max = 8 }, | |
287 | .p2 = { .dot_limit = 225000, | |
288 | .p2_slow = 10, .p2_fast = 5 }, | |
4547668a | 289 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
290 | }; |
291 | ||
b91ad0ec | 292 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
293 | .dot = { .min = 25000, .max = 350000 }, |
294 | .vco = { .min = 1760000, .max = 3510000 }, | |
295 | .n = { .min = 1, .max = 3 }, | |
296 | .m = { .min = 79, .max = 118 }, | |
297 | .m1 = { .min = 12, .max = 22 }, | |
298 | .m2 = { .min = 5, .max = 9 }, | |
299 | .p = { .min = 28, .max = 112 }, | |
300 | .p1 = { .min = 2, .max = 8 }, | |
301 | .p2 = { .dot_limit = 225000, | |
302 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
303 | .find_pll = intel_g4x_find_best_PLL, |
304 | }; | |
305 | ||
306 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
307 | .dot = { .min = 25000, .max = 350000 }, |
308 | .vco = { .min = 1760000, .max = 3510000 }, | |
309 | .n = { .min = 1, .max = 3 }, | |
310 | .m = { .min = 79, .max = 127 }, | |
311 | .m1 = { .min = 12, .max = 22 }, | |
312 | .m2 = { .min = 5, .max = 9 }, | |
313 | .p = { .min = 14, .max = 56 }, | |
314 | .p1 = { .min = 2, .max = 8 }, | |
315 | .p2 = { .dot_limit = 225000, | |
316 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
317 | .find_pll = intel_g4x_find_best_PLL, |
318 | }; | |
319 | ||
273e27ca | 320 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 321 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
322 | .dot = { .min = 25000, .max = 350000 }, |
323 | .vco = { .min = 1760000, .max = 3510000 }, | |
324 | .n = { .min = 1, .max = 2 }, | |
325 | .m = { .min = 79, .max = 126 }, | |
326 | .m1 = { .min = 12, .max = 22 }, | |
327 | .m2 = { .min = 5, .max = 9 }, | |
328 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 329 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
330 | .p2 = { .dot_limit = 225000, |
331 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
332 | .find_pll = intel_g4x_find_best_PLL, |
333 | }; | |
334 | ||
335 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
336 | .dot = { .min = 25000, .max = 350000 }, |
337 | .vco = { .min = 1760000, .max = 3510000 }, | |
338 | .n = { .min = 1, .max = 3 }, | |
339 | .m = { .min = 79, .max = 126 }, | |
340 | .m1 = { .min = 12, .max = 22 }, | |
341 | .m2 = { .min = 5, .max = 9 }, | |
342 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 343 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
344 | .p2 = { .dot_limit = 225000, |
345 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
346 | .find_pll = intel_g4x_find_best_PLL, |
347 | }; | |
348 | ||
349 | static const intel_limit_t intel_limits_ironlake_display_port = { | |
0206e353 AJ |
350 | .dot = { .min = 25000, .max = 350000 }, |
351 | .vco = { .min = 1760000, .max = 3510000}, | |
352 | .n = { .min = 1, .max = 2 }, | |
353 | .m = { .min = 81, .max = 90 }, | |
354 | .m1 = { .min = 12, .max = 22 }, | |
355 | .m2 = { .min = 5, .max = 9 }, | |
356 | .p = { .min = 10, .max = 20 }, | |
357 | .p1 = { .min = 1, .max = 2}, | |
358 | .p2 = { .dot_limit = 0, | |
273e27ca | 359 | .p2_slow = 10, .p2_fast = 10 }, |
0206e353 | 360 | .find_pll = intel_find_pll_ironlake_dp, |
79e53945 JB |
361 | }; |
362 | ||
b0354385 TI |
363 | static bool is_dual_link_lvds(struct drm_i915_private *dev_priv, |
364 | unsigned int reg) | |
365 | { | |
366 | unsigned int val; | |
367 | ||
121d527a TI |
368 | /* use the module option value if specified */ |
369 | if (i915_lvds_channel_mode > 0) | |
370 | return i915_lvds_channel_mode == 2; | |
371 | ||
b0354385 TI |
372 | if (dev_priv->lvds_val) |
373 | val = dev_priv->lvds_val; | |
374 | else { | |
375 | /* BIOS should set the proper LVDS register value at boot, but | |
376 | * in reality, it doesn't set the value when the lid is closed; | |
377 | * we need to check "the value to be set" in VBT when LVDS | |
378 | * register is uninitialized. | |
379 | */ | |
380 | val = I915_READ(reg); | |
381 | if (!(val & ~LVDS_DETECTED)) | |
382 | val = dev_priv->bios_lvds_val; | |
383 | dev_priv->lvds_val = val; | |
384 | } | |
385 | return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP; | |
386 | } | |
387 | ||
1b894b59 CW |
388 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
389 | int refclk) | |
2c07245f | 390 | { |
b91ad0ec ZW |
391 | struct drm_device *dev = crtc->dev; |
392 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2c07245f | 393 | const intel_limit_t *limit; |
b91ad0ec ZW |
394 | |
395 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
b0354385 | 396 | if (is_dual_link_lvds(dev_priv, PCH_LVDS)) { |
b91ad0ec | 397 | /* LVDS dual channel */ |
1b894b59 | 398 | if (refclk == 100000) |
b91ad0ec ZW |
399 | limit = &intel_limits_ironlake_dual_lvds_100m; |
400 | else | |
401 | limit = &intel_limits_ironlake_dual_lvds; | |
402 | } else { | |
1b894b59 | 403 | if (refclk == 100000) |
b91ad0ec ZW |
404 | limit = &intel_limits_ironlake_single_lvds_100m; |
405 | else | |
406 | limit = &intel_limits_ironlake_single_lvds; | |
407 | } | |
408 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || | |
4547668a ZY |
409 | HAS_eDP) |
410 | limit = &intel_limits_ironlake_display_port; | |
2c07245f | 411 | else |
b91ad0ec | 412 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
413 | |
414 | return limit; | |
415 | } | |
416 | ||
044c7c41 ML |
417 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
418 | { | |
419 | struct drm_device *dev = crtc->dev; | |
420 | struct drm_i915_private *dev_priv = dev->dev_private; | |
421 | const intel_limit_t *limit; | |
422 | ||
423 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
b0354385 | 424 | if (is_dual_link_lvds(dev_priv, LVDS)) |
044c7c41 | 425 | /* LVDS with dual channel */ |
e4b36699 | 426 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 ML |
427 | else |
428 | /* LVDS with dual channel */ | |
e4b36699 | 429 | limit = &intel_limits_g4x_single_channel_lvds; |
044c7c41 ML |
430 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
431 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 432 | limit = &intel_limits_g4x_hdmi; |
044c7c41 | 433 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 434 | limit = &intel_limits_g4x_sdvo; |
0206e353 | 435 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
e4b36699 | 436 | limit = &intel_limits_g4x_display_port; |
044c7c41 | 437 | } else /* The option is for other outputs */ |
e4b36699 | 438 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
439 | |
440 | return limit; | |
441 | } | |
442 | ||
1b894b59 | 443 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
79e53945 JB |
444 | { |
445 | struct drm_device *dev = crtc->dev; | |
446 | const intel_limit_t *limit; | |
447 | ||
bad720ff | 448 | if (HAS_PCH_SPLIT(dev)) |
1b894b59 | 449 | limit = intel_ironlake_limit(crtc, refclk); |
2c07245f | 450 | else if (IS_G4X(dev)) { |
044c7c41 | 451 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 452 | } else if (IS_PINEVIEW(dev)) { |
2177832f | 453 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 454 | limit = &intel_limits_pineview_lvds; |
2177832f | 455 | else |
f2b115e6 | 456 | limit = &intel_limits_pineview_sdvo; |
a6c45cf0 CW |
457 | } else if (!IS_GEN2(dev)) { |
458 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
459 | limit = &intel_limits_i9xx_lvds; | |
460 | else | |
461 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 JB |
462 | } else { |
463 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 464 | limit = &intel_limits_i8xx_lvds; |
79e53945 | 465 | else |
e4b36699 | 466 | limit = &intel_limits_i8xx_dvo; |
79e53945 JB |
467 | } |
468 | return limit; | |
469 | } | |
470 | ||
f2b115e6 AJ |
471 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
472 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 473 | { |
2177832f SL |
474 | clock->m = clock->m2 + 2; |
475 | clock->p = clock->p1 * clock->p2; | |
476 | clock->vco = refclk * clock->m / clock->n; | |
477 | clock->dot = clock->vco / clock->p; | |
478 | } | |
479 | ||
480 | static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock) | |
481 | { | |
f2b115e6 AJ |
482 | if (IS_PINEVIEW(dev)) { |
483 | pineview_clock(refclk, clock); | |
2177832f SL |
484 | return; |
485 | } | |
79e53945 JB |
486 | clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); |
487 | clock->p = clock->p1 * clock->p2; | |
488 | clock->vco = refclk * clock->m / (clock->n + 2); | |
489 | clock->dot = clock->vco / clock->p; | |
490 | } | |
491 | ||
79e53945 JB |
492 | /** |
493 | * Returns whether any output on the specified pipe is of the specified type | |
494 | */ | |
4ef69c7a | 495 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type) |
79e53945 | 496 | { |
4ef69c7a CW |
497 | struct drm_device *dev = crtc->dev; |
498 | struct drm_mode_config *mode_config = &dev->mode_config; | |
499 | struct intel_encoder *encoder; | |
500 | ||
501 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) | |
502 | if (encoder->base.crtc == crtc && encoder->type == type) | |
503 | return true; | |
504 | ||
505 | return false; | |
79e53945 JB |
506 | } |
507 | ||
7c04d1d9 | 508 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
509 | /** |
510 | * Returns whether the given set of divisors are valid for a given refclk with | |
511 | * the given connectors. | |
512 | */ | |
513 | ||
1b894b59 CW |
514 | static bool intel_PLL_is_valid(struct drm_device *dev, |
515 | const intel_limit_t *limit, | |
516 | const intel_clock_t *clock) | |
79e53945 | 517 | { |
79e53945 | 518 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 519 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 520 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
0206e353 | 521 | INTELPllInvalid("p out of range\n"); |
79e53945 | 522 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 523 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 524 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 525 | INTELPllInvalid("m1 out of range\n"); |
f2b115e6 | 526 | if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev)) |
0206e353 | 527 | INTELPllInvalid("m1 <= m2\n"); |
79e53945 | 528 | if (clock->m < limit->m.min || limit->m.max < clock->m) |
0206e353 | 529 | INTELPllInvalid("m out of range\n"); |
79e53945 | 530 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
0206e353 | 531 | INTELPllInvalid("n out of range\n"); |
79e53945 | 532 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 533 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
534 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
535 | * connector, etc., rather than just a single range. | |
536 | */ | |
537 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 538 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
539 | |
540 | return true; | |
541 | } | |
542 | ||
d4906093 ML |
543 | static bool |
544 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
545 | int target, int refclk, intel_clock_t *match_clock, |
546 | intel_clock_t *best_clock) | |
d4906093 | 547 | |
79e53945 JB |
548 | { |
549 | struct drm_device *dev = crtc->dev; | |
550 | struct drm_i915_private *dev_priv = dev->dev_private; | |
551 | intel_clock_t clock; | |
79e53945 JB |
552 | int err = target; |
553 | ||
bc5e5718 | 554 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
832cc28d | 555 | (I915_READ(LVDS)) != 0) { |
79e53945 JB |
556 | /* |
557 | * For LVDS, if the panel is on, just rely on its current | |
558 | * settings for dual-channel. We haven't figured out how to | |
559 | * reliably set up different single/dual channel state, if we | |
560 | * even can. | |
561 | */ | |
b0354385 | 562 | if (is_dual_link_lvds(dev_priv, LVDS)) |
79e53945 JB |
563 | clock.p2 = limit->p2.p2_fast; |
564 | else | |
565 | clock.p2 = limit->p2.p2_slow; | |
566 | } else { | |
567 | if (target < limit->p2.dot_limit) | |
568 | clock.p2 = limit->p2.p2_slow; | |
569 | else | |
570 | clock.p2 = limit->p2.p2_fast; | |
571 | } | |
572 | ||
0206e353 | 573 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 574 | |
42158660 ZY |
575 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
576 | clock.m1++) { | |
577 | for (clock.m2 = limit->m2.min; | |
578 | clock.m2 <= limit->m2.max; clock.m2++) { | |
f2b115e6 AJ |
579 | /* m1 is always 0 in Pineview */ |
580 | if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev)) | |
42158660 ZY |
581 | break; |
582 | for (clock.n = limit->n.min; | |
583 | clock.n <= limit->n.max; clock.n++) { | |
584 | for (clock.p1 = limit->p1.min; | |
585 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
586 | int this_err; |
587 | ||
2177832f | 588 | intel_clock(dev, refclk, &clock); |
1b894b59 CW |
589 | if (!intel_PLL_is_valid(dev, limit, |
590 | &clock)) | |
79e53945 | 591 | continue; |
cec2f356 SP |
592 | if (match_clock && |
593 | clock.p != match_clock->p) | |
594 | continue; | |
79e53945 JB |
595 | |
596 | this_err = abs(clock.dot - target); | |
597 | if (this_err < err) { | |
598 | *best_clock = clock; | |
599 | err = this_err; | |
600 | } | |
601 | } | |
602 | } | |
603 | } | |
604 | } | |
605 | ||
606 | return (err != target); | |
607 | } | |
608 | ||
d4906093 ML |
609 | static bool |
610 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
611 | int target, int refclk, intel_clock_t *match_clock, |
612 | intel_clock_t *best_clock) | |
d4906093 ML |
613 | { |
614 | struct drm_device *dev = crtc->dev; | |
615 | struct drm_i915_private *dev_priv = dev->dev_private; | |
616 | intel_clock_t clock; | |
617 | int max_n; | |
618 | bool found; | |
6ba770dc AJ |
619 | /* approximately equals target * 0.00585 */ |
620 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
621 | found = false; |
622 | ||
623 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
4547668a ZY |
624 | int lvds_reg; |
625 | ||
c619eed4 | 626 | if (HAS_PCH_SPLIT(dev)) |
4547668a ZY |
627 | lvds_reg = PCH_LVDS; |
628 | else | |
629 | lvds_reg = LVDS; | |
630 | if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) == | |
d4906093 ML |
631 | LVDS_CLKB_POWER_UP) |
632 | clock.p2 = limit->p2.p2_fast; | |
633 | else | |
634 | clock.p2 = limit->p2.p2_slow; | |
635 | } else { | |
636 | if (target < limit->p2.dot_limit) | |
637 | clock.p2 = limit->p2.p2_slow; | |
638 | else | |
639 | clock.p2 = limit->p2.p2_fast; | |
640 | } | |
641 | ||
642 | memset(best_clock, 0, sizeof(*best_clock)); | |
643 | max_n = limit->n.max; | |
f77f13e2 | 644 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 645 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 646 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
647 | for (clock.m1 = limit->m1.max; |
648 | clock.m1 >= limit->m1.min; clock.m1--) { | |
649 | for (clock.m2 = limit->m2.max; | |
650 | clock.m2 >= limit->m2.min; clock.m2--) { | |
651 | for (clock.p1 = limit->p1.max; | |
652 | clock.p1 >= limit->p1.min; clock.p1--) { | |
653 | int this_err; | |
654 | ||
2177832f | 655 | intel_clock(dev, refclk, &clock); |
1b894b59 CW |
656 | if (!intel_PLL_is_valid(dev, limit, |
657 | &clock)) | |
d4906093 | 658 | continue; |
cec2f356 SP |
659 | if (match_clock && |
660 | clock.p != match_clock->p) | |
661 | continue; | |
1b894b59 CW |
662 | |
663 | this_err = abs(clock.dot - target); | |
d4906093 ML |
664 | if (this_err < err_most) { |
665 | *best_clock = clock; | |
666 | err_most = this_err; | |
667 | max_n = clock.n; | |
668 | found = true; | |
669 | } | |
670 | } | |
671 | } | |
672 | } | |
673 | } | |
2c07245f ZW |
674 | return found; |
675 | } | |
676 | ||
5eb08b69 | 677 | static bool |
f2b115e6 | 678 | intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc, |
cec2f356 SP |
679 | int target, int refclk, intel_clock_t *match_clock, |
680 | intel_clock_t *best_clock) | |
5eb08b69 ZW |
681 | { |
682 | struct drm_device *dev = crtc->dev; | |
683 | intel_clock_t clock; | |
4547668a | 684 | |
5eb08b69 ZW |
685 | if (target < 200000) { |
686 | clock.n = 1; | |
687 | clock.p1 = 2; | |
688 | clock.p2 = 10; | |
689 | clock.m1 = 12; | |
690 | clock.m2 = 9; | |
691 | } else { | |
692 | clock.n = 2; | |
693 | clock.p1 = 1; | |
694 | clock.p2 = 10; | |
695 | clock.m1 = 14; | |
696 | clock.m2 = 8; | |
697 | } | |
698 | intel_clock(dev, refclk, &clock); | |
699 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); | |
700 | return true; | |
701 | } | |
702 | ||
a4fc5ed6 KP |
703 | /* DisplayPort has only two frequencies, 162MHz and 270MHz */ |
704 | static bool | |
705 | intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
706 | int target, int refclk, intel_clock_t *match_clock, |
707 | intel_clock_t *best_clock) | |
a4fc5ed6 | 708 | { |
5eddb70b CW |
709 | intel_clock_t clock; |
710 | if (target < 200000) { | |
711 | clock.p1 = 2; | |
712 | clock.p2 = 10; | |
713 | clock.n = 2; | |
714 | clock.m1 = 23; | |
715 | clock.m2 = 8; | |
716 | } else { | |
717 | clock.p1 = 1; | |
718 | clock.p2 = 10; | |
719 | clock.n = 1; | |
720 | clock.m1 = 14; | |
721 | clock.m2 = 2; | |
722 | } | |
723 | clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2); | |
724 | clock.p = (clock.p1 * clock.p2); | |
725 | clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p; | |
726 | clock.vco = 0; | |
727 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); | |
728 | return true; | |
a4fc5ed6 KP |
729 | } |
730 | ||
9d0498a2 JB |
731 | /** |
732 | * intel_wait_for_vblank - wait for vblank on a given pipe | |
733 | * @dev: drm device | |
734 | * @pipe: pipe to wait for | |
735 | * | |
736 | * Wait for vblank to occur on a given pipe. Needed for various bits of | |
737 | * mode setting code. | |
738 | */ | |
739 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) | |
79e53945 | 740 | { |
9d0498a2 | 741 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 742 | int pipestat_reg = PIPESTAT(pipe); |
9d0498a2 | 743 | |
300387c0 CW |
744 | /* Clear existing vblank status. Note this will clear any other |
745 | * sticky status fields as well. | |
746 | * | |
747 | * This races with i915_driver_irq_handler() with the result | |
748 | * that either function could miss a vblank event. Here it is not | |
749 | * fatal, as we will either wait upon the next vblank interrupt or | |
750 | * timeout. Generally speaking intel_wait_for_vblank() is only | |
751 | * called during modeset at which time the GPU should be idle and | |
752 | * should *not* be performing page flips and thus not waiting on | |
753 | * vblanks... | |
754 | * Currently, the result of us stealing a vblank from the irq | |
755 | * handler is that a single frame will be skipped during swapbuffers. | |
756 | */ | |
757 | I915_WRITE(pipestat_reg, | |
758 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); | |
759 | ||
9d0498a2 | 760 | /* Wait for vblank interrupt bit to set */ |
481b6af3 CW |
761 | if (wait_for(I915_READ(pipestat_reg) & |
762 | PIPE_VBLANK_INTERRUPT_STATUS, | |
763 | 50)) | |
9d0498a2 JB |
764 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
765 | } | |
766 | ||
ab7ad7f6 KP |
767 | /* |
768 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
9d0498a2 JB |
769 | * @dev: drm device |
770 | * @pipe: pipe to wait for | |
771 | * | |
772 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
773 | * spinning on the vblank interrupt status bit, since we won't actually | |
774 | * see an interrupt when the pipe is disabled. | |
775 | * | |
ab7ad7f6 KP |
776 | * On Gen4 and above: |
777 | * wait for the pipe register state bit to turn off | |
778 | * | |
779 | * Otherwise: | |
780 | * wait for the display line value to settle (it usually | |
781 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 782 | * |
9d0498a2 | 783 | */ |
58e10eb9 | 784 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
9d0498a2 JB |
785 | { |
786 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ab7ad7f6 KP |
787 | |
788 | if (INTEL_INFO(dev)->gen >= 4) { | |
58e10eb9 | 789 | int reg = PIPECONF(pipe); |
ab7ad7f6 KP |
790 | |
791 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
792 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
793 | 100)) | |
ab7ad7f6 KP |
794 | DRM_DEBUG_KMS("pipe_off wait timed out\n"); |
795 | } else { | |
796 | u32 last_line; | |
58e10eb9 | 797 | int reg = PIPEDSL(pipe); |
ab7ad7f6 KP |
798 | unsigned long timeout = jiffies + msecs_to_jiffies(100); |
799 | ||
800 | /* Wait for the display line to settle */ | |
801 | do { | |
58e10eb9 | 802 | last_line = I915_READ(reg) & DSL_LINEMASK; |
ab7ad7f6 | 803 | mdelay(5); |
58e10eb9 | 804 | } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) && |
ab7ad7f6 KP |
805 | time_after(timeout, jiffies)); |
806 | if (time_after(jiffies, timeout)) | |
807 | DRM_DEBUG_KMS("pipe_off wait timed out\n"); | |
808 | } | |
79e53945 JB |
809 | } |
810 | ||
b24e7179 JB |
811 | static const char *state_string(bool enabled) |
812 | { | |
813 | return enabled ? "on" : "off"; | |
814 | } | |
815 | ||
816 | /* Only for pre-ILK configs */ | |
817 | static void assert_pll(struct drm_i915_private *dev_priv, | |
818 | enum pipe pipe, bool state) | |
819 | { | |
820 | int reg; | |
821 | u32 val; | |
822 | bool cur_state; | |
823 | ||
824 | reg = DPLL(pipe); | |
825 | val = I915_READ(reg); | |
826 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
827 | WARN(cur_state != state, | |
828 | "PLL state assertion failure (expected %s, current %s)\n", | |
829 | state_string(state), state_string(cur_state)); | |
830 | } | |
831 | #define assert_pll_enabled(d, p) assert_pll(d, p, true) | |
832 | #define assert_pll_disabled(d, p) assert_pll(d, p, false) | |
833 | ||
040484af JB |
834 | /* For ILK+ */ |
835 | static void assert_pch_pll(struct drm_i915_private *dev_priv, | |
836 | enum pipe pipe, bool state) | |
837 | { | |
838 | int reg; | |
839 | u32 val; | |
840 | bool cur_state; | |
841 | ||
d3ccbe86 JB |
842 | if (HAS_PCH_CPT(dev_priv->dev)) { |
843 | u32 pch_dpll; | |
844 | ||
845 | pch_dpll = I915_READ(PCH_DPLL_SEL); | |
846 | ||
847 | /* Make sure the selected PLL is enabled to the transcoder */ | |
848 | WARN(!((pch_dpll >> (4 * pipe)) & 8), | |
849 | "transcoder %d PLL not enabled\n", pipe); | |
850 | ||
851 | /* Convert the transcoder pipe number to a pll pipe number */ | |
852 | pipe = (pch_dpll >> (4 * pipe)) & 1; | |
853 | } | |
854 | ||
040484af JB |
855 | reg = PCH_DPLL(pipe); |
856 | val = I915_READ(reg); | |
857 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
858 | WARN(cur_state != state, | |
859 | "PCH PLL state assertion failure (expected %s, current %s)\n", | |
860 | state_string(state), state_string(cur_state)); | |
861 | } | |
862 | #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true) | |
863 | #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false) | |
864 | ||
865 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
866 | enum pipe pipe, bool state) | |
867 | { | |
868 | int reg; | |
869 | u32 val; | |
870 | bool cur_state; | |
871 | ||
872 | reg = FDI_TX_CTL(pipe); | |
873 | val = I915_READ(reg); | |
874 | cur_state = !!(val & FDI_TX_ENABLE); | |
875 | WARN(cur_state != state, | |
876 | "FDI TX state assertion failure (expected %s, current %s)\n", | |
877 | state_string(state), state_string(cur_state)); | |
878 | } | |
879 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
880 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
881 | ||
882 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
883 | enum pipe pipe, bool state) | |
884 | { | |
885 | int reg; | |
886 | u32 val; | |
887 | bool cur_state; | |
888 | ||
889 | reg = FDI_RX_CTL(pipe); | |
890 | val = I915_READ(reg); | |
891 | cur_state = !!(val & FDI_RX_ENABLE); | |
892 | WARN(cur_state != state, | |
893 | "FDI RX state assertion failure (expected %s, current %s)\n", | |
894 | state_string(state), state_string(cur_state)); | |
895 | } | |
896 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
897 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
898 | ||
899 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
900 | enum pipe pipe) | |
901 | { | |
902 | int reg; | |
903 | u32 val; | |
904 | ||
905 | /* ILK FDI PLL is always enabled */ | |
906 | if (dev_priv->info->gen == 5) | |
907 | return; | |
908 | ||
909 | reg = FDI_TX_CTL(pipe); | |
910 | val = I915_READ(reg); | |
911 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); | |
912 | } | |
913 | ||
914 | static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv, | |
915 | enum pipe pipe) | |
916 | { | |
917 | int reg; | |
918 | u32 val; | |
919 | ||
920 | reg = FDI_RX_CTL(pipe); | |
921 | val = I915_READ(reg); | |
922 | WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n"); | |
923 | } | |
924 | ||
ea0760cf JB |
925 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
926 | enum pipe pipe) | |
927 | { | |
928 | int pp_reg, lvds_reg; | |
929 | u32 val; | |
930 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 931 | bool locked = true; |
ea0760cf JB |
932 | |
933 | if (HAS_PCH_SPLIT(dev_priv->dev)) { | |
934 | pp_reg = PCH_PP_CONTROL; | |
935 | lvds_reg = PCH_LVDS; | |
936 | } else { | |
937 | pp_reg = PP_CONTROL; | |
938 | lvds_reg = LVDS; | |
939 | } | |
940 | ||
941 | val = I915_READ(pp_reg); | |
942 | if (!(val & PANEL_POWER_ON) || | |
943 | ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) | |
944 | locked = false; | |
945 | ||
946 | if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) | |
947 | panel_pipe = PIPE_B; | |
948 | ||
949 | WARN(panel_pipe == pipe && locked, | |
950 | "panel assertion failure, pipe %c regs locked\n", | |
9db4a9c7 | 951 | pipe_name(pipe)); |
ea0760cf JB |
952 | } |
953 | ||
b840d907 JB |
954 | void assert_pipe(struct drm_i915_private *dev_priv, |
955 | enum pipe pipe, bool state) | |
b24e7179 JB |
956 | { |
957 | int reg; | |
958 | u32 val; | |
63d7bbe9 | 959 | bool cur_state; |
b24e7179 | 960 | |
8e636784 DV |
961 | /* if we need the pipe A quirk it must be always on */ |
962 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
963 | state = true; | |
964 | ||
b24e7179 JB |
965 | reg = PIPECONF(pipe); |
966 | val = I915_READ(reg); | |
63d7bbe9 JB |
967 | cur_state = !!(val & PIPECONF_ENABLE); |
968 | WARN(cur_state != state, | |
969 | "pipe %c assertion failure (expected %s, current %s)\n", | |
9db4a9c7 | 970 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
971 | } |
972 | ||
931872fc CW |
973 | static void assert_plane(struct drm_i915_private *dev_priv, |
974 | enum plane plane, bool state) | |
b24e7179 JB |
975 | { |
976 | int reg; | |
977 | u32 val; | |
931872fc | 978 | bool cur_state; |
b24e7179 JB |
979 | |
980 | reg = DSPCNTR(plane); | |
981 | val = I915_READ(reg); | |
931872fc CW |
982 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
983 | WARN(cur_state != state, | |
984 | "plane %c assertion failure (expected %s, current %s)\n", | |
985 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
986 | } |
987 | ||
931872fc CW |
988 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
989 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
990 | ||
b24e7179 JB |
991 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
992 | enum pipe pipe) | |
993 | { | |
994 | int reg, i; | |
995 | u32 val; | |
996 | int cur_pipe; | |
997 | ||
19ec1358 | 998 | /* Planes are fixed to pipes on ILK+ */ |
28c05794 AJ |
999 | if (HAS_PCH_SPLIT(dev_priv->dev)) { |
1000 | reg = DSPCNTR(pipe); | |
1001 | val = I915_READ(reg); | |
1002 | WARN((val & DISPLAY_PLANE_ENABLE), | |
1003 | "plane %c assertion failure, should be disabled but not\n", | |
1004 | plane_name(pipe)); | |
19ec1358 | 1005 | return; |
28c05794 | 1006 | } |
19ec1358 | 1007 | |
b24e7179 JB |
1008 | /* Need to check both planes against the pipe */ |
1009 | for (i = 0; i < 2; i++) { | |
1010 | reg = DSPCNTR(i); | |
1011 | val = I915_READ(reg); | |
1012 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1013 | DISPPLANE_SEL_PIPE_SHIFT; | |
1014 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, | |
9db4a9c7 JB |
1015 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1016 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1017 | } |
1018 | } | |
1019 | ||
92f2584a JB |
1020 | static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
1021 | { | |
1022 | u32 val; | |
1023 | bool enabled; | |
1024 | ||
1025 | val = I915_READ(PCH_DREF_CONTROL); | |
1026 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1027 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
1028 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); | |
1029 | } | |
1030 | ||
1031 | static void assert_transcoder_disabled(struct drm_i915_private *dev_priv, | |
1032 | enum pipe pipe) | |
1033 | { | |
1034 | int reg; | |
1035 | u32 val; | |
1036 | bool enabled; | |
1037 | ||
1038 | reg = TRANSCONF(pipe); | |
1039 | val = I915_READ(reg); | |
1040 | enabled = !!(val & TRANS_ENABLE); | |
9db4a9c7 JB |
1041 | WARN(enabled, |
1042 | "transcoder assertion failed, should be off on pipe %c but is still active\n", | |
1043 | pipe_name(pipe)); | |
92f2584a JB |
1044 | } |
1045 | ||
4e634389 KP |
1046 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1047 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1048 | { |
1049 | if ((val & DP_PORT_EN) == 0) | |
1050 | return false; | |
1051 | ||
1052 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1053 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1054 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1055 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1056 | return false; | |
1057 | } else { | |
1058 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1059 | return false; | |
1060 | } | |
1061 | return true; | |
1062 | } | |
1063 | ||
1519b995 KP |
1064 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1065 | enum pipe pipe, u32 val) | |
1066 | { | |
1067 | if ((val & PORT_ENABLE) == 0) | |
1068 | return false; | |
1069 | ||
1070 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1071 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1072 | return false; | |
1073 | } else { | |
1074 | if ((val & TRANSCODER_MASK) != TRANSCODER(pipe)) | |
1075 | return false; | |
1076 | } | |
1077 | return true; | |
1078 | } | |
1079 | ||
1080 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1081 | enum pipe pipe, u32 val) | |
1082 | { | |
1083 | if ((val & LVDS_PORT_EN) == 0) | |
1084 | return false; | |
1085 | ||
1086 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1087 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1088 | return false; | |
1089 | } else { | |
1090 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1091 | return false; | |
1092 | } | |
1093 | return true; | |
1094 | } | |
1095 | ||
1096 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1097 | enum pipe pipe, u32 val) | |
1098 | { | |
1099 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1100 | return false; | |
1101 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1102 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1103 | return false; | |
1104 | } else { | |
1105 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1106 | return false; | |
1107 | } | |
1108 | return true; | |
1109 | } | |
1110 | ||
291906f1 | 1111 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1112 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1113 | { |
47a05eca | 1114 | u32 val = I915_READ(reg); |
4e634389 | 1115 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1116 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1117 | reg, pipe_name(pipe)); |
291906f1 JB |
1118 | } |
1119 | ||
1120 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1121 | enum pipe pipe, int reg) | |
1122 | { | |
47a05eca | 1123 | u32 val = I915_READ(reg); |
1519b995 | 1124 | WARN(hdmi_pipe_enabled(dev_priv, val, pipe), |
23c99e77 | 1125 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1126 | reg, pipe_name(pipe)); |
291906f1 JB |
1127 | } |
1128 | ||
1129 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1130 | enum pipe pipe) | |
1131 | { | |
1132 | int reg; | |
1133 | u32 val; | |
291906f1 | 1134 | |
f0575e92 KP |
1135 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1136 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1137 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1138 | |
1139 | reg = PCH_ADPA; | |
1140 | val = I915_READ(reg); | |
1519b995 | 1141 | WARN(adpa_pipe_enabled(dev_priv, val, pipe), |
291906f1 | 1142 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1143 | pipe_name(pipe)); |
291906f1 JB |
1144 | |
1145 | reg = PCH_LVDS; | |
1146 | val = I915_READ(reg); | |
1519b995 | 1147 | WARN(lvds_pipe_enabled(dev_priv, val, pipe), |
291906f1 | 1148 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1149 | pipe_name(pipe)); |
291906f1 JB |
1150 | |
1151 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB); | |
1152 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC); | |
1153 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMID); | |
1154 | } | |
1155 | ||
63d7bbe9 JB |
1156 | /** |
1157 | * intel_enable_pll - enable a PLL | |
1158 | * @dev_priv: i915 private structure | |
1159 | * @pipe: pipe PLL to enable | |
1160 | * | |
1161 | * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to | |
1162 | * make sure the PLL reg is writable first though, since the panel write | |
1163 | * protect mechanism may be enabled. | |
1164 | * | |
1165 | * Note! This is for pre-ILK only. | |
1166 | */ | |
1167 | static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1168 | { | |
1169 | int reg; | |
1170 | u32 val; | |
1171 | ||
1172 | /* No really, not for ILK+ */ | |
1173 | BUG_ON(dev_priv->info->gen >= 5); | |
1174 | ||
1175 | /* PLL is protected by panel, make sure we can write it */ | |
1176 | if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) | |
1177 | assert_panel_unlocked(dev_priv, pipe); | |
1178 | ||
1179 | reg = DPLL(pipe); | |
1180 | val = I915_READ(reg); | |
1181 | val |= DPLL_VCO_ENABLE; | |
1182 | ||
1183 | /* We do this three times for luck */ | |
1184 | I915_WRITE(reg, val); | |
1185 | POSTING_READ(reg); | |
1186 | udelay(150); /* wait for warmup */ | |
1187 | I915_WRITE(reg, val); | |
1188 | POSTING_READ(reg); | |
1189 | udelay(150); /* wait for warmup */ | |
1190 | I915_WRITE(reg, val); | |
1191 | POSTING_READ(reg); | |
1192 | udelay(150); /* wait for warmup */ | |
1193 | } | |
1194 | ||
1195 | /** | |
1196 | * intel_disable_pll - disable a PLL | |
1197 | * @dev_priv: i915 private structure | |
1198 | * @pipe: pipe PLL to disable | |
1199 | * | |
1200 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1201 | * | |
1202 | * Note! This is for pre-ILK only. | |
1203 | */ | |
1204 | static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1205 | { | |
1206 | int reg; | |
1207 | u32 val; | |
1208 | ||
1209 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
1210 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1211 | return; | |
1212 | ||
1213 | /* Make sure the pipe isn't still relying on us */ | |
1214 | assert_pipe_disabled(dev_priv, pipe); | |
1215 | ||
1216 | reg = DPLL(pipe); | |
1217 | val = I915_READ(reg); | |
1218 | val &= ~DPLL_VCO_ENABLE; | |
1219 | I915_WRITE(reg, val); | |
1220 | POSTING_READ(reg); | |
1221 | } | |
1222 | ||
92f2584a JB |
1223 | /** |
1224 | * intel_enable_pch_pll - enable PCH PLL | |
1225 | * @dev_priv: i915 private structure | |
1226 | * @pipe: pipe PLL to enable | |
1227 | * | |
1228 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1229 | * drives the transcoder clock. | |
1230 | */ | |
1231 | static void intel_enable_pch_pll(struct drm_i915_private *dev_priv, | |
1232 | enum pipe pipe) | |
1233 | { | |
1234 | int reg; | |
1235 | u32 val; | |
1236 | ||
4c609cb8 JB |
1237 | if (pipe > 1) |
1238 | return; | |
1239 | ||
92f2584a JB |
1240 | /* PCH only available on ILK+ */ |
1241 | BUG_ON(dev_priv->info->gen < 5); | |
1242 | ||
1243 | /* PCH refclock must be enabled first */ | |
1244 | assert_pch_refclk_enabled(dev_priv); | |
1245 | ||
1246 | reg = PCH_DPLL(pipe); | |
1247 | val = I915_READ(reg); | |
1248 | val |= DPLL_VCO_ENABLE; | |
1249 | I915_WRITE(reg, val); | |
1250 | POSTING_READ(reg); | |
1251 | udelay(200); | |
1252 | } | |
1253 | ||
1254 | static void intel_disable_pch_pll(struct drm_i915_private *dev_priv, | |
1255 | enum pipe pipe) | |
1256 | { | |
1257 | int reg; | |
7a419866 JB |
1258 | u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL, |
1259 | pll_sel = TRANSC_DPLL_ENABLE; | |
92f2584a | 1260 | |
4c609cb8 JB |
1261 | if (pipe > 1) |
1262 | return; | |
1263 | ||
92f2584a JB |
1264 | /* PCH only available on ILK+ */ |
1265 | BUG_ON(dev_priv->info->gen < 5); | |
1266 | ||
1267 | /* Make sure transcoder isn't still depending on us */ | |
1268 | assert_transcoder_disabled(dev_priv, pipe); | |
1269 | ||
7a419866 JB |
1270 | if (pipe == 0) |
1271 | pll_sel |= TRANSC_DPLLA_SEL; | |
1272 | else if (pipe == 1) | |
1273 | pll_sel |= TRANSC_DPLLB_SEL; | |
1274 | ||
1275 | ||
1276 | if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel) | |
1277 | return; | |
1278 | ||
92f2584a JB |
1279 | reg = PCH_DPLL(pipe); |
1280 | val = I915_READ(reg); | |
1281 | val &= ~DPLL_VCO_ENABLE; | |
1282 | I915_WRITE(reg, val); | |
1283 | POSTING_READ(reg); | |
1284 | udelay(200); | |
1285 | } | |
1286 | ||
040484af JB |
1287 | static void intel_enable_transcoder(struct drm_i915_private *dev_priv, |
1288 | enum pipe pipe) | |
1289 | { | |
1290 | int reg; | |
5f7f726d | 1291 | u32 val, pipeconf_val; |
7c26e5c6 | 1292 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
040484af JB |
1293 | |
1294 | /* PCH only available on ILK+ */ | |
1295 | BUG_ON(dev_priv->info->gen < 5); | |
1296 | ||
1297 | /* Make sure PCH DPLL is enabled */ | |
1298 | assert_pch_pll_enabled(dev_priv, pipe); | |
1299 | ||
1300 | /* FDI must be feeding us bits for PCH ports */ | |
1301 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1302 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1303 | ||
1304 | reg = TRANSCONF(pipe); | |
1305 | val = I915_READ(reg); | |
5f7f726d | 1306 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1307 | |
1308 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1309 | /* | |
1310 | * make the BPC in transcoder be consistent with | |
1311 | * that in pipeconf reg. | |
1312 | */ | |
1313 | val &= ~PIPE_BPC_MASK; | |
5f7f726d | 1314 | val |= pipeconf_val & PIPE_BPC_MASK; |
e9bcff5c | 1315 | } |
5f7f726d PZ |
1316 | |
1317 | val &= ~TRANS_INTERLACE_MASK; | |
1318 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 PZ |
1319 | if (HAS_PCH_IBX(dev_priv->dev) && |
1320 | intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) | |
1321 | val |= TRANS_LEGACY_INTERLACED_ILK; | |
1322 | else | |
1323 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1324 | else |
1325 | val |= TRANS_PROGRESSIVE; | |
1326 | ||
040484af JB |
1327 | I915_WRITE(reg, val | TRANS_ENABLE); |
1328 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
1329 | DRM_ERROR("failed to enable transcoder %d\n", pipe); | |
1330 | } | |
1331 | ||
1332 | static void intel_disable_transcoder(struct drm_i915_private *dev_priv, | |
1333 | enum pipe pipe) | |
1334 | { | |
1335 | int reg; | |
1336 | u32 val; | |
1337 | ||
1338 | /* FDI relies on the transcoder */ | |
1339 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1340 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1341 | ||
291906f1 JB |
1342 | /* Ports must be off as well */ |
1343 | assert_pch_ports_disabled(dev_priv, pipe); | |
1344 | ||
040484af JB |
1345 | reg = TRANSCONF(pipe); |
1346 | val = I915_READ(reg); | |
1347 | val &= ~TRANS_ENABLE; | |
1348 | I915_WRITE(reg, val); | |
1349 | /* wait for PCH transcoder off, transcoder state */ | |
1350 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4c9c18c2 | 1351 | DRM_ERROR("failed to disable transcoder %d\n", pipe); |
040484af JB |
1352 | } |
1353 | ||
b24e7179 | 1354 | /** |
309cfea8 | 1355 | * intel_enable_pipe - enable a pipe, asserting requirements |
b24e7179 JB |
1356 | * @dev_priv: i915 private structure |
1357 | * @pipe: pipe to enable | |
040484af | 1358 | * @pch_port: on ILK+, is this pipe driving a PCH port or not |
b24e7179 JB |
1359 | * |
1360 | * Enable @pipe, making sure that various hardware specific requirements | |
1361 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. | |
1362 | * | |
1363 | * @pipe should be %PIPE_A or %PIPE_B. | |
1364 | * | |
1365 | * Will wait until the pipe is actually running (i.e. first vblank) before | |
1366 | * returning. | |
1367 | */ | |
040484af JB |
1368 | static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
1369 | bool pch_port) | |
b24e7179 JB |
1370 | { |
1371 | int reg; | |
1372 | u32 val; | |
1373 | ||
1374 | /* | |
1375 | * A pipe without a PLL won't actually be able to drive bits from | |
1376 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1377 | * need the check. | |
1378 | */ | |
1379 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
1380 | assert_pll_enabled(dev_priv, pipe); | |
040484af JB |
1381 | else { |
1382 | if (pch_port) { | |
1383 | /* if driving the PCH, we need FDI enabled */ | |
1384 | assert_fdi_rx_pll_enabled(dev_priv, pipe); | |
1385 | assert_fdi_tx_pll_enabled(dev_priv, pipe); | |
1386 | } | |
1387 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1388 | } | |
b24e7179 JB |
1389 | |
1390 | reg = PIPECONF(pipe); | |
1391 | val = I915_READ(reg); | |
00d70b15 CW |
1392 | if (val & PIPECONF_ENABLE) |
1393 | return; | |
1394 | ||
1395 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
b24e7179 JB |
1396 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1397 | } | |
1398 | ||
1399 | /** | |
309cfea8 | 1400 | * intel_disable_pipe - disable a pipe, asserting requirements |
b24e7179 JB |
1401 | * @dev_priv: i915 private structure |
1402 | * @pipe: pipe to disable | |
1403 | * | |
1404 | * Disable @pipe, making sure that various hardware specific requirements | |
1405 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. | |
1406 | * | |
1407 | * @pipe should be %PIPE_A or %PIPE_B. | |
1408 | * | |
1409 | * Will wait until the pipe has shut down before returning. | |
1410 | */ | |
1411 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, | |
1412 | enum pipe pipe) | |
1413 | { | |
1414 | int reg; | |
1415 | u32 val; | |
1416 | ||
1417 | /* | |
1418 | * Make sure planes won't keep trying to pump pixels to us, | |
1419 | * or we might hang the display. | |
1420 | */ | |
1421 | assert_planes_disabled(dev_priv, pipe); | |
1422 | ||
1423 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
1424 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1425 | return; | |
1426 | ||
1427 | reg = PIPECONF(pipe); | |
1428 | val = I915_READ(reg); | |
00d70b15 CW |
1429 | if ((val & PIPECONF_ENABLE) == 0) |
1430 | return; | |
1431 | ||
1432 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); | |
b24e7179 JB |
1433 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
1434 | } | |
1435 | ||
d74362c9 KP |
1436 | /* |
1437 | * Plane regs are double buffered, going from enabled->disabled needs a | |
1438 | * trigger in order to latch. The display address reg provides this. | |
1439 | */ | |
1440 | static void intel_flush_display_plane(struct drm_i915_private *dev_priv, | |
1441 | enum plane plane) | |
1442 | { | |
1443 | I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane))); | |
1444 | I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane))); | |
1445 | } | |
1446 | ||
b24e7179 JB |
1447 | /** |
1448 | * intel_enable_plane - enable a display plane on a given pipe | |
1449 | * @dev_priv: i915 private structure | |
1450 | * @plane: plane to enable | |
1451 | * @pipe: pipe being fed | |
1452 | * | |
1453 | * Enable @plane on @pipe, making sure that @pipe is running first. | |
1454 | */ | |
1455 | static void intel_enable_plane(struct drm_i915_private *dev_priv, | |
1456 | enum plane plane, enum pipe pipe) | |
1457 | { | |
1458 | int reg; | |
1459 | u32 val; | |
1460 | ||
1461 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
1462 | assert_pipe_enabled(dev_priv, pipe); | |
1463 | ||
1464 | reg = DSPCNTR(plane); | |
1465 | val = I915_READ(reg); | |
00d70b15 CW |
1466 | if (val & DISPLAY_PLANE_ENABLE) |
1467 | return; | |
1468 | ||
1469 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); | |
d74362c9 | 1470 | intel_flush_display_plane(dev_priv, plane); |
b24e7179 JB |
1471 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1472 | } | |
1473 | ||
b24e7179 JB |
1474 | /** |
1475 | * intel_disable_plane - disable a display plane | |
1476 | * @dev_priv: i915 private structure | |
1477 | * @plane: plane to disable | |
1478 | * @pipe: pipe consuming the data | |
1479 | * | |
1480 | * Disable @plane; should be an independent operation. | |
1481 | */ | |
1482 | static void intel_disable_plane(struct drm_i915_private *dev_priv, | |
1483 | enum plane plane, enum pipe pipe) | |
1484 | { | |
1485 | int reg; | |
1486 | u32 val; | |
1487 | ||
1488 | reg = DSPCNTR(plane); | |
1489 | val = I915_READ(reg); | |
00d70b15 CW |
1490 | if ((val & DISPLAY_PLANE_ENABLE) == 0) |
1491 | return; | |
1492 | ||
1493 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); | |
b24e7179 JB |
1494 | intel_flush_display_plane(dev_priv, plane); |
1495 | intel_wait_for_vblank(dev_priv->dev, pipe); | |
1496 | } | |
1497 | ||
47a05eca | 1498 | static void disable_pch_dp(struct drm_i915_private *dev_priv, |
f0575e92 | 1499 | enum pipe pipe, int reg, u32 port_sel) |
47a05eca JB |
1500 | { |
1501 | u32 val = I915_READ(reg); | |
4e634389 | 1502 | if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) { |
f0575e92 | 1503 | DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe); |
47a05eca | 1504 | I915_WRITE(reg, val & ~DP_PORT_EN); |
f0575e92 | 1505 | } |
47a05eca JB |
1506 | } |
1507 | ||
1508 | static void disable_pch_hdmi(struct drm_i915_private *dev_priv, | |
1509 | enum pipe pipe, int reg) | |
1510 | { | |
1511 | u32 val = I915_READ(reg); | |
1519b995 | 1512 | if (hdmi_pipe_enabled(dev_priv, val, pipe)) { |
f0575e92 KP |
1513 | DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n", |
1514 | reg, pipe); | |
47a05eca | 1515 | I915_WRITE(reg, val & ~PORT_ENABLE); |
f0575e92 | 1516 | } |
47a05eca JB |
1517 | } |
1518 | ||
1519 | /* Disable any ports connected to this transcoder */ | |
1520 | static void intel_disable_pch_ports(struct drm_i915_private *dev_priv, | |
1521 | enum pipe pipe) | |
1522 | { | |
1523 | u32 reg, val; | |
1524 | ||
1525 | val = I915_READ(PCH_PP_CONTROL); | |
1526 | I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS); | |
1527 | ||
f0575e92 KP |
1528 | disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1529 | disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1530 | disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
47a05eca JB |
1531 | |
1532 | reg = PCH_ADPA; | |
1533 | val = I915_READ(reg); | |
1519b995 | 1534 | if (adpa_pipe_enabled(dev_priv, val, pipe)) |
47a05eca JB |
1535 | I915_WRITE(reg, val & ~ADPA_DAC_ENABLE); |
1536 | ||
1537 | reg = PCH_LVDS; | |
1538 | val = I915_READ(reg); | |
1519b995 KP |
1539 | if (lvds_pipe_enabled(dev_priv, val, pipe)) { |
1540 | DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val); | |
47a05eca JB |
1541 | I915_WRITE(reg, val & ~LVDS_PORT_EN); |
1542 | POSTING_READ(reg); | |
1543 | udelay(100); | |
1544 | } | |
1545 | ||
1546 | disable_pch_hdmi(dev_priv, pipe, HDMIB); | |
1547 | disable_pch_hdmi(dev_priv, pipe, HDMIC); | |
1548 | disable_pch_hdmi(dev_priv, pipe, HDMID); | |
1549 | } | |
1550 | ||
43a9539f CW |
1551 | static void i8xx_disable_fbc(struct drm_device *dev) |
1552 | { | |
1553 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1554 | u32 fbc_ctl; | |
1555 | ||
1556 | /* Disable compression */ | |
1557 | fbc_ctl = I915_READ(FBC_CONTROL); | |
1558 | if ((fbc_ctl & FBC_CTL_EN) == 0) | |
1559 | return; | |
1560 | ||
1561 | fbc_ctl &= ~FBC_CTL_EN; | |
1562 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
1563 | ||
1564 | /* Wait for compressing bit to clear */ | |
1565 | if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { | |
1566 | DRM_DEBUG_KMS("FBC idle timed out\n"); | |
1567 | return; | |
1568 | } | |
1569 | ||
1570 | DRM_DEBUG_KMS("disabled FBC\n"); | |
1571 | } | |
1572 | ||
80824003 JB |
1573 | static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
1574 | { | |
1575 | struct drm_device *dev = crtc->dev; | |
1576 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1577 | struct drm_framebuffer *fb = crtc->fb; | |
1578 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 1579 | struct drm_i915_gem_object *obj = intel_fb->obj; |
80824003 | 1580 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
016b9b61 | 1581 | int cfb_pitch; |
80824003 JB |
1582 | int plane, i; |
1583 | u32 fbc_ctl, fbc_ctl2; | |
1584 | ||
016b9b61 | 1585 | cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE; |
01f2c773 VS |
1586 | if (fb->pitches[0] < cfb_pitch) |
1587 | cfb_pitch = fb->pitches[0]; | |
80824003 JB |
1588 | |
1589 | /* FBC_CTL wants 64B units */ | |
016b9b61 CW |
1590 | cfb_pitch = (cfb_pitch / 64) - 1; |
1591 | plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB; | |
80824003 JB |
1592 | |
1593 | /* Clear old tags */ | |
1594 | for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) | |
1595 | I915_WRITE(FBC_TAG + (i * 4), 0); | |
1596 | ||
1597 | /* Set it up... */ | |
de568510 CW |
1598 | fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; |
1599 | fbc_ctl2 |= plane; | |
80824003 JB |
1600 | I915_WRITE(FBC_CONTROL2, fbc_ctl2); |
1601 | I915_WRITE(FBC_FENCE_OFF, crtc->y); | |
1602 | ||
1603 | /* enable it... */ | |
1604 | fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC; | |
ee25df2b | 1605 | if (IS_I945GM(dev)) |
49677901 | 1606 | fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ |
016b9b61 | 1607 | fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; |
80824003 | 1608 | fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT; |
016b9b61 | 1609 | fbc_ctl |= obj->fence_reg; |
80824003 JB |
1610 | I915_WRITE(FBC_CONTROL, fbc_ctl); |
1611 | ||
016b9b61 CW |
1612 | DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ", |
1613 | cfb_pitch, crtc->y, intel_crtc->plane); | |
80824003 JB |
1614 | } |
1615 | ||
ee5382ae | 1616 | static bool i8xx_fbc_enabled(struct drm_device *dev) |
80824003 | 1617 | { |
80824003 JB |
1618 | struct drm_i915_private *dev_priv = dev->dev_private; |
1619 | ||
1620 | return I915_READ(FBC_CONTROL) & FBC_CTL_EN; | |
1621 | } | |
1622 | ||
74dff282 JB |
1623 | static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
1624 | { | |
1625 | struct drm_device *dev = crtc->dev; | |
1626 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1627 | struct drm_framebuffer *fb = crtc->fb; | |
1628 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 1629 | struct drm_i915_gem_object *obj = intel_fb->obj; |
74dff282 | 1630 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5eddb70b | 1631 | int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; |
74dff282 JB |
1632 | unsigned long stall_watermark = 200; |
1633 | u32 dpfc_ctl; | |
1634 | ||
74dff282 | 1635 | dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X; |
016b9b61 | 1636 | dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg; |
de568510 | 1637 | I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY); |
74dff282 | 1638 | |
74dff282 JB |
1639 | I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | |
1640 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | | |
1641 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); | |
1642 | I915_WRITE(DPFC_FENCE_YOFF, crtc->y); | |
1643 | ||
1644 | /* enable it... */ | |
1645 | I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN); | |
1646 | ||
28c97730 | 1647 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); |
74dff282 JB |
1648 | } |
1649 | ||
43a9539f | 1650 | static void g4x_disable_fbc(struct drm_device *dev) |
74dff282 JB |
1651 | { |
1652 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1653 | u32 dpfc_ctl; | |
1654 | ||
1655 | /* Disable compression */ | |
1656 | dpfc_ctl = I915_READ(DPFC_CONTROL); | |
bed4a673 CW |
1657 | if (dpfc_ctl & DPFC_CTL_EN) { |
1658 | dpfc_ctl &= ~DPFC_CTL_EN; | |
1659 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); | |
74dff282 | 1660 | |
bed4a673 CW |
1661 | DRM_DEBUG_KMS("disabled FBC\n"); |
1662 | } | |
74dff282 JB |
1663 | } |
1664 | ||
ee5382ae | 1665 | static bool g4x_fbc_enabled(struct drm_device *dev) |
74dff282 | 1666 | { |
74dff282 JB |
1667 | struct drm_i915_private *dev_priv = dev->dev_private; |
1668 | ||
1669 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; | |
1670 | } | |
1671 | ||
4efe0708 JB |
1672 | static void sandybridge_blit_fbc_update(struct drm_device *dev) |
1673 | { | |
1674 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1675 | u32 blt_ecoskpd; | |
1676 | ||
1677 | /* Make sure blitter notifies FBC of writes */ | |
fcca7926 | 1678 | gen6_gt_force_wake_get(dev_priv); |
4efe0708 JB |
1679 | blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD); |
1680 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY << | |
1681 | GEN6_BLITTER_LOCK_SHIFT; | |
1682 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | |
1683 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY; | |
1684 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | |
1685 | blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY << | |
1686 | GEN6_BLITTER_LOCK_SHIFT); | |
1687 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | |
1688 | POSTING_READ(GEN6_BLITTER_ECOSKPD); | |
fcca7926 | 1689 | gen6_gt_force_wake_put(dev_priv); |
4efe0708 JB |
1690 | } |
1691 | ||
b52eb4dc ZY |
1692 | static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
1693 | { | |
1694 | struct drm_device *dev = crtc->dev; | |
1695 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1696 | struct drm_framebuffer *fb = crtc->fb; | |
1697 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 1698 | struct drm_i915_gem_object *obj = intel_fb->obj; |
b52eb4dc | 1699 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5eddb70b | 1700 | int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; |
b52eb4dc ZY |
1701 | unsigned long stall_watermark = 200; |
1702 | u32 dpfc_ctl; | |
1703 | ||
bed4a673 | 1704 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); |
b52eb4dc ZY |
1705 | dpfc_ctl &= DPFC_RESERVED; |
1706 | dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X); | |
9ce9d069 CW |
1707 | /* Set persistent mode for front-buffer rendering, ala X. */ |
1708 | dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE; | |
016b9b61 | 1709 | dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg); |
de568510 | 1710 | I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY); |
b52eb4dc | 1711 | |
b52eb4dc ZY |
1712 | I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | |
1713 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | | |
1714 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); | |
1715 | I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y); | |
05394f39 | 1716 | I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID); |
b52eb4dc | 1717 | /* enable it... */ |
bed4a673 | 1718 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
b52eb4dc | 1719 | |
9c04f015 YL |
1720 | if (IS_GEN6(dev)) { |
1721 | I915_WRITE(SNB_DPFC_CTL_SA, | |
016b9b61 | 1722 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); |
9c04f015 | 1723 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); |
4efe0708 | 1724 | sandybridge_blit_fbc_update(dev); |
9c04f015 YL |
1725 | } |
1726 | ||
b52eb4dc ZY |
1727 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); |
1728 | } | |
1729 | ||
43a9539f | 1730 | static void ironlake_disable_fbc(struct drm_device *dev) |
b52eb4dc ZY |
1731 | { |
1732 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1733 | u32 dpfc_ctl; | |
1734 | ||
1735 | /* Disable compression */ | |
1736 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); | |
bed4a673 CW |
1737 | if (dpfc_ctl & DPFC_CTL_EN) { |
1738 | dpfc_ctl &= ~DPFC_CTL_EN; | |
1739 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); | |
b52eb4dc | 1740 | |
bed4a673 CW |
1741 | DRM_DEBUG_KMS("disabled FBC\n"); |
1742 | } | |
b52eb4dc ZY |
1743 | } |
1744 | ||
1745 | static bool ironlake_fbc_enabled(struct drm_device *dev) | |
1746 | { | |
1747 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1748 | ||
1749 | return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; | |
1750 | } | |
1751 | ||
ee5382ae AJ |
1752 | bool intel_fbc_enabled(struct drm_device *dev) |
1753 | { | |
1754 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1755 | ||
1756 | if (!dev_priv->display.fbc_enabled) | |
1757 | return false; | |
1758 | ||
1759 | return dev_priv->display.fbc_enabled(dev); | |
1760 | } | |
1761 | ||
1630fe75 CW |
1762 | static void intel_fbc_work_fn(struct work_struct *__work) |
1763 | { | |
1764 | struct intel_fbc_work *work = | |
1765 | container_of(to_delayed_work(__work), | |
1766 | struct intel_fbc_work, work); | |
1767 | struct drm_device *dev = work->crtc->dev; | |
1768 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1769 | ||
1770 | mutex_lock(&dev->struct_mutex); | |
1771 | if (work == dev_priv->fbc_work) { | |
1772 | /* Double check that we haven't switched fb without cancelling | |
1773 | * the prior work. | |
1774 | */ | |
016b9b61 | 1775 | if (work->crtc->fb == work->fb) { |
1630fe75 CW |
1776 | dev_priv->display.enable_fbc(work->crtc, |
1777 | work->interval); | |
1778 | ||
016b9b61 CW |
1779 | dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane; |
1780 | dev_priv->cfb_fb = work->crtc->fb->base.id; | |
1781 | dev_priv->cfb_y = work->crtc->y; | |
1782 | } | |
1783 | ||
1630fe75 CW |
1784 | dev_priv->fbc_work = NULL; |
1785 | } | |
1786 | mutex_unlock(&dev->struct_mutex); | |
1787 | ||
1788 | kfree(work); | |
1789 | } | |
1790 | ||
1791 | static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv) | |
1792 | { | |
1793 | if (dev_priv->fbc_work == NULL) | |
1794 | return; | |
1795 | ||
1796 | DRM_DEBUG_KMS("cancelling pending FBC enable\n"); | |
1797 | ||
1798 | /* Synchronisation is provided by struct_mutex and checking of | |
1799 | * dev_priv->fbc_work, so we can perform the cancellation | |
1800 | * entirely asynchronously. | |
1801 | */ | |
1802 | if (cancel_delayed_work(&dev_priv->fbc_work->work)) | |
1803 | /* tasklet was killed before being run, clean up */ | |
1804 | kfree(dev_priv->fbc_work); | |
1805 | ||
1806 | /* Mark the work as no longer wanted so that if it does | |
1807 | * wake-up (because the work was already running and waiting | |
1808 | * for our mutex), it will discover that is no longer | |
1809 | * necessary to run. | |
1810 | */ | |
1811 | dev_priv->fbc_work = NULL; | |
1812 | } | |
1813 | ||
43a9539f | 1814 | static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
ee5382ae | 1815 | { |
1630fe75 CW |
1816 | struct intel_fbc_work *work; |
1817 | struct drm_device *dev = crtc->dev; | |
1818 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee5382ae AJ |
1819 | |
1820 | if (!dev_priv->display.enable_fbc) | |
1821 | return; | |
1822 | ||
1630fe75 CW |
1823 | intel_cancel_fbc_work(dev_priv); |
1824 | ||
1825 | work = kzalloc(sizeof *work, GFP_KERNEL); | |
1826 | if (work == NULL) { | |
1827 | dev_priv->display.enable_fbc(crtc, interval); | |
1828 | return; | |
1829 | } | |
1830 | ||
1831 | work->crtc = crtc; | |
1832 | work->fb = crtc->fb; | |
1833 | work->interval = interval; | |
1834 | INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn); | |
1835 | ||
1836 | dev_priv->fbc_work = work; | |
1837 | ||
1838 | DRM_DEBUG_KMS("scheduling delayed FBC enable\n"); | |
1839 | ||
1840 | /* Delay the actual enabling to let pageflipping cease and the | |
016b9b61 CW |
1841 | * display to settle before starting the compression. Note that |
1842 | * this delay also serves a second purpose: it allows for a | |
1843 | * vblank to pass after disabling the FBC before we attempt | |
1844 | * to modify the control registers. | |
1630fe75 CW |
1845 | * |
1846 | * A more complicated solution would involve tracking vblanks | |
1847 | * following the termination of the page-flipping sequence | |
1848 | * and indeed performing the enable as a co-routine and not | |
1849 | * waiting synchronously upon the vblank. | |
1850 | */ | |
1851 | schedule_delayed_work(&work->work, msecs_to_jiffies(50)); | |
ee5382ae AJ |
1852 | } |
1853 | ||
1854 | void intel_disable_fbc(struct drm_device *dev) | |
1855 | { | |
1856 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1857 | ||
1630fe75 CW |
1858 | intel_cancel_fbc_work(dev_priv); |
1859 | ||
ee5382ae AJ |
1860 | if (!dev_priv->display.disable_fbc) |
1861 | return; | |
1862 | ||
1863 | dev_priv->display.disable_fbc(dev); | |
016b9b61 | 1864 | dev_priv->cfb_plane = -1; |
ee5382ae AJ |
1865 | } |
1866 | ||
80824003 JB |
1867 | /** |
1868 | * intel_update_fbc - enable/disable FBC as needed | |
bed4a673 | 1869 | * @dev: the drm_device |
80824003 JB |
1870 | * |
1871 | * Set up the framebuffer compression hardware at mode set time. We | |
1872 | * enable it if possible: | |
1873 | * - plane A only (on pre-965) | |
1874 | * - no pixel mulitply/line duplication | |
1875 | * - no alpha buffer discard | |
1876 | * - no dual wide | |
1877 | * - framebuffer <= 2048 in width, 1536 in height | |
1878 | * | |
1879 | * We can't assume that any compression will take place (worst case), | |
1880 | * so the compressed buffer has to be the same size as the uncompressed | |
1881 | * one. It also must reside (along with the line length buffer) in | |
1882 | * stolen memory. | |
1883 | * | |
1884 | * We need to enable/disable FBC on a global basis. | |
1885 | */ | |
bed4a673 | 1886 | static void intel_update_fbc(struct drm_device *dev) |
80824003 | 1887 | { |
80824003 | 1888 | struct drm_i915_private *dev_priv = dev->dev_private; |
bed4a673 CW |
1889 | struct drm_crtc *crtc = NULL, *tmp_crtc; |
1890 | struct intel_crtc *intel_crtc; | |
1891 | struct drm_framebuffer *fb; | |
80824003 | 1892 | struct intel_framebuffer *intel_fb; |
05394f39 | 1893 | struct drm_i915_gem_object *obj; |
cd0de039 | 1894 | int enable_fbc; |
9c928d16 JB |
1895 | |
1896 | DRM_DEBUG_KMS("\n"); | |
80824003 JB |
1897 | |
1898 | if (!i915_powersave) | |
1899 | return; | |
1900 | ||
ee5382ae | 1901 | if (!I915_HAS_FBC(dev)) |
e70236a8 JB |
1902 | return; |
1903 | ||
80824003 JB |
1904 | /* |
1905 | * If FBC is already on, we just have to verify that we can | |
1906 | * keep it that way... | |
1907 | * Need to disable if: | |
9c928d16 | 1908 | * - more than one pipe is active |
80824003 JB |
1909 | * - changing FBC params (stride, fence, mode) |
1910 | * - new fb is too large to fit in compressed buffer | |
1911 | * - going to an unsupported config (interlace, pixel multiply, etc.) | |
1912 | */ | |
9c928d16 | 1913 | list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) { |
d210246a | 1914 | if (tmp_crtc->enabled && tmp_crtc->fb) { |
bed4a673 CW |
1915 | if (crtc) { |
1916 | DRM_DEBUG_KMS("more than one pipe active, disabling compression\n"); | |
1917 | dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES; | |
1918 | goto out_disable; | |
1919 | } | |
1920 | crtc = tmp_crtc; | |
1921 | } | |
9c928d16 | 1922 | } |
bed4a673 CW |
1923 | |
1924 | if (!crtc || crtc->fb == NULL) { | |
1925 | DRM_DEBUG_KMS("no output, disabling\n"); | |
1926 | dev_priv->no_fbc_reason = FBC_NO_OUTPUT; | |
9c928d16 JB |
1927 | goto out_disable; |
1928 | } | |
bed4a673 CW |
1929 | |
1930 | intel_crtc = to_intel_crtc(crtc); | |
1931 | fb = crtc->fb; | |
1932 | intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 1933 | obj = intel_fb->obj; |
bed4a673 | 1934 | |
cd0de039 KP |
1935 | enable_fbc = i915_enable_fbc; |
1936 | if (enable_fbc < 0) { | |
1937 | DRM_DEBUG_KMS("fbc set to per-chip default\n"); | |
1938 | enable_fbc = 1; | |
d56d8b28 | 1939 | if (INTEL_INFO(dev)->gen <= 6) |
cd0de039 KP |
1940 | enable_fbc = 0; |
1941 | } | |
1942 | if (!enable_fbc) { | |
1943 | DRM_DEBUG_KMS("fbc disabled per module param\n"); | |
c1a9f047 JB |
1944 | dev_priv->no_fbc_reason = FBC_MODULE_PARAM; |
1945 | goto out_disable; | |
1946 | } | |
05394f39 | 1947 | if (intel_fb->obj->base.size > dev_priv->cfb_size) { |
28c97730 | 1948 | DRM_DEBUG_KMS("framebuffer too large, disabling " |
5eddb70b | 1949 | "compression\n"); |
b5e50c3f | 1950 | dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL; |
80824003 JB |
1951 | goto out_disable; |
1952 | } | |
bed4a673 CW |
1953 | if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) || |
1954 | (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) { | |
28c97730 | 1955 | DRM_DEBUG_KMS("mode incompatible with compression, " |
5eddb70b | 1956 | "disabling\n"); |
b5e50c3f | 1957 | dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE; |
80824003 JB |
1958 | goto out_disable; |
1959 | } | |
bed4a673 CW |
1960 | if ((crtc->mode.hdisplay > 2048) || |
1961 | (crtc->mode.vdisplay > 1536)) { | |
28c97730 | 1962 | DRM_DEBUG_KMS("mode too large for compression, disabling\n"); |
b5e50c3f | 1963 | dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE; |
80824003 JB |
1964 | goto out_disable; |
1965 | } | |
bed4a673 | 1966 | if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) { |
28c97730 | 1967 | DRM_DEBUG_KMS("plane not 0, disabling compression\n"); |
b5e50c3f | 1968 | dev_priv->no_fbc_reason = FBC_BAD_PLANE; |
80824003 JB |
1969 | goto out_disable; |
1970 | } | |
de568510 CW |
1971 | |
1972 | /* The use of a CPU fence is mandatory in order to detect writes | |
1973 | * by the CPU to the scanout and trigger updates to the FBC. | |
1974 | */ | |
1975 | if (obj->tiling_mode != I915_TILING_X || | |
1976 | obj->fence_reg == I915_FENCE_REG_NONE) { | |
1977 | DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n"); | |
b5e50c3f | 1978 | dev_priv->no_fbc_reason = FBC_NOT_TILED; |
80824003 JB |
1979 | goto out_disable; |
1980 | } | |
1981 | ||
c924b934 JW |
1982 | /* If the kernel debugger is active, always disable compression */ |
1983 | if (in_dbg_master()) | |
1984 | goto out_disable; | |
1985 | ||
016b9b61 CW |
1986 | /* If the scanout has not changed, don't modify the FBC settings. |
1987 | * Note that we make the fundamental assumption that the fb->obj | |
1988 | * cannot be unpinned (and have its GTT offset and fence revoked) | |
1989 | * without first being decoupled from the scanout and FBC disabled. | |
1990 | */ | |
1991 | if (dev_priv->cfb_plane == intel_crtc->plane && | |
1992 | dev_priv->cfb_fb == fb->base.id && | |
1993 | dev_priv->cfb_y == crtc->y) | |
1994 | return; | |
1995 | ||
1996 | if (intel_fbc_enabled(dev)) { | |
1997 | /* We update FBC along two paths, after changing fb/crtc | |
1998 | * configuration (modeswitching) and after page-flipping | |
1999 | * finishes. For the latter, we know that not only did | |
2000 | * we disable the FBC at the start of the page-flip | |
2001 | * sequence, but also more than one vblank has passed. | |
2002 | * | |
2003 | * For the former case of modeswitching, it is possible | |
2004 | * to switch between two FBC valid configurations | |
2005 | * instantaneously so we do need to disable the FBC | |
2006 | * before we can modify its control registers. We also | |
2007 | * have to wait for the next vblank for that to take | |
2008 | * effect. However, since we delay enabling FBC we can | |
2009 | * assume that a vblank has passed since disabling and | |
2010 | * that we can safely alter the registers in the deferred | |
2011 | * callback. | |
2012 | * | |
2013 | * In the scenario that we go from a valid to invalid | |
2014 | * and then back to valid FBC configuration we have | |
2015 | * no strict enforcement that a vblank occurred since | |
2016 | * disabling the FBC. However, along all current pipe | |
2017 | * disabling paths we do need to wait for a vblank at | |
2018 | * some point. And we wait before enabling FBC anyway. | |
2019 | */ | |
2020 | DRM_DEBUG_KMS("disabling active FBC for update\n"); | |
2021 | intel_disable_fbc(dev); | |
2022 | } | |
2023 | ||
bed4a673 | 2024 | intel_enable_fbc(crtc, 500); |
80824003 JB |
2025 | return; |
2026 | ||
2027 | out_disable: | |
80824003 | 2028 | /* Multiple disables should be harmless */ |
a939406f CW |
2029 | if (intel_fbc_enabled(dev)) { |
2030 | DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); | |
ee5382ae | 2031 | intel_disable_fbc(dev); |
a939406f | 2032 | } |
80824003 JB |
2033 | } |
2034 | ||
127bd2ac | 2035 | int |
48b956c5 | 2036 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
05394f39 | 2037 | struct drm_i915_gem_object *obj, |
919926ae | 2038 | struct intel_ring_buffer *pipelined) |
6b95a207 | 2039 | { |
ce453d81 | 2040 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
2041 | u32 alignment; |
2042 | int ret; | |
2043 | ||
05394f39 | 2044 | switch (obj->tiling_mode) { |
6b95a207 | 2045 | case I915_TILING_NONE: |
534843da CW |
2046 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
2047 | alignment = 128 * 1024; | |
a6c45cf0 | 2048 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
2049 | alignment = 4 * 1024; |
2050 | else | |
2051 | alignment = 64 * 1024; | |
6b95a207 KH |
2052 | break; |
2053 | case I915_TILING_X: | |
2054 | /* pin() will align the object as required by fence */ | |
2055 | alignment = 0; | |
2056 | break; | |
2057 | case I915_TILING_Y: | |
2058 | /* FIXME: Is this true? */ | |
2059 | DRM_ERROR("Y tiled not allowed for scan out buffers\n"); | |
2060 | return -EINVAL; | |
2061 | default: | |
2062 | BUG(); | |
2063 | } | |
2064 | ||
ce453d81 | 2065 | dev_priv->mm.interruptible = false; |
2da3b9b9 | 2066 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
48b956c5 | 2067 | if (ret) |
ce453d81 | 2068 | goto err_interruptible; |
6b95a207 KH |
2069 | |
2070 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2071 | * fence, whereas 965+ only requires a fence if using | |
2072 | * framebuffer compression. For simplicity, we always install | |
2073 | * a fence as the cost is not that onerous. | |
2074 | */ | |
05394f39 | 2075 | if (obj->tiling_mode != I915_TILING_NONE) { |
ce453d81 | 2076 | ret = i915_gem_object_get_fence(obj, pipelined); |
48b956c5 CW |
2077 | if (ret) |
2078 | goto err_unpin; | |
1690e1eb CW |
2079 | |
2080 | i915_gem_object_pin_fence(obj); | |
6b95a207 KH |
2081 | } |
2082 | ||
ce453d81 | 2083 | dev_priv->mm.interruptible = true; |
6b95a207 | 2084 | return 0; |
48b956c5 CW |
2085 | |
2086 | err_unpin: | |
2087 | i915_gem_object_unpin(obj); | |
ce453d81 CW |
2088 | err_interruptible: |
2089 | dev_priv->mm.interruptible = true; | |
48b956c5 | 2090 | return ret; |
6b95a207 KH |
2091 | } |
2092 | ||
1690e1eb CW |
2093 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
2094 | { | |
2095 | i915_gem_object_unpin_fence(obj); | |
2096 | i915_gem_object_unpin(obj); | |
2097 | } | |
2098 | ||
17638cd6 JB |
2099 | static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
2100 | int x, int y) | |
81255565 JB |
2101 | { |
2102 | struct drm_device *dev = crtc->dev; | |
2103 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2104 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2105 | struct intel_framebuffer *intel_fb; | |
05394f39 | 2106 | struct drm_i915_gem_object *obj; |
81255565 JB |
2107 | int plane = intel_crtc->plane; |
2108 | unsigned long Start, Offset; | |
81255565 | 2109 | u32 dspcntr; |
5eddb70b | 2110 | u32 reg; |
81255565 JB |
2111 | |
2112 | switch (plane) { | |
2113 | case 0: | |
2114 | case 1: | |
2115 | break; | |
2116 | default: | |
2117 | DRM_ERROR("Can't update plane %d in SAREA\n", plane); | |
2118 | return -EINVAL; | |
2119 | } | |
2120 | ||
2121 | intel_fb = to_intel_framebuffer(fb); | |
2122 | obj = intel_fb->obj; | |
81255565 | 2123 | |
5eddb70b CW |
2124 | reg = DSPCNTR(plane); |
2125 | dspcntr = I915_READ(reg); | |
81255565 JB |
2126 | /* Mask out pixel format bits in case we change it */ |
2127 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
2128 | switch (fb->bits_per_pixel) { | |
2129 | case 8: | |
2130 | dspcntr |= DISPPLANE_8BPP; | |
2131 | break; | |
2132 | case 16: | |
2133 | if (fb->depth == 15) | |
2134 | dspcntr |= DISPPLANE_15_16BPP; | |
2135 | else | |
2136 | dspcntr |= DISPPLANE_16BPP; | |
2137 | break; | |
2138 | case 24: | |
2139 | case 32: | |
2140 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; | |
2141 | break; | |
2142 | default: | |
17638cd6 | 2143 | DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel); |
81255565 JB |
2144 | return -EINVAL; |
2145 | } | |
a6c45cf0 | 2146 | if (INTEL_INFO(dev)->gen >= 4) { |
05394f39 | 2147 | if (obj->tiling_mode != I915_TILING_NONE) |
81255565 JB |
2148 | dspcntr |= DISPPLANE_TILED; |
2149 | else | |
2150 | dspcntr &= ~DISPPLANE_TILED; | |
2151 | } | |
2152 | ||
5eddb70b | 2153 | I915_WRITE(reg, dspcntr); |
81255565 | 2154 | |
05394f39 | 2155 | Start = obj->gtt_offset; |
01f2c773 | 2156 | Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
81255565 | 2157 | |
4e6cfefc | 2158 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
01f2c773 VS |
2159 | Start, Offset, x, y, fb->pitches[0]); |
2160 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); | |
a6c45cf0 | 2161 | if (INTEL_INFO(dev)->gen >= 4) { |
5eddb70b CW |
2162 | I915_WRITE(DSPSURF(plane), Start); |
2163 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2164 | I915_WRITE(DSPADDR(plane), Offset); | |
2165 | } else | |
2166 | I915_WRITE(DSPADDR(plane), Start + Offset); | |
2167 | POSTING_READ(reg); | |
81255565 | 2168 | |
17638cd6 JB |
2169 | return 0; |
2170 | } | |
2171 | ||
2172 | static int ironlake_update_plane(struct drm_crtc *crtc, | |
2173 | struct drm_framebuffer *fb, int x, int y) | |
2174 | { | |
2175 | struct drm_device *dev = crtc->dev; | |
2176 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2177 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2178 | struct intel_framebuffer *intel_fb; | |
2179 | struct drm_i915_gem_object *obj; | |
2180 | int plane = intel_crtc->plane; | |
2181 | unsigned long Start, Offset; | |
2182 | u32 dspcntr; | |
2183 | u32 reg; | |
2184 | ||
2185 | switch (plane) { | |
2186 | case 0: | |
2187 | case 1: | |
27f8227b | 2188 | case 2: |
17638cd6 JB |
2189 | break; |
2190 | default: | |
2191 | DRM_ERROR("Can't update plane %d in SAREA\n", plane); | |
2192 | return -EINVAL; | |
2193 | } | |
2194 | ||
2195 | intel_fb = to_intel_framebuffer(fb); | |
2196 | obj = intel_fb->obj; | |
2197 | ||
2198 | reg = DSPCNTR(plane); | |
2199 | dspcntr = I915_READ(reg); | |
2200 | /* Mask out pixel format bits in case we change it */ | |
2201 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
2202 | switch (fb->bits_per_pixel) { | |
2203 | case 8: | |
2204 | dspcntr |= DISPPLANE_8BPP; | |
2205 | break; | |
2206 | case 16: | |
2207 | if (fb->depth != 16) | |
2208 | return -EINVAL; | |
2209 | ||
2210 | dspcntr |= DISPPLANE_16BPP; | |
2211 | break; | |
2212 | case 24: | |
2213 | case 32: | |
2214 | if (fb->depth == 24) | |
2215 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; | |
2216 | else if (fb->depth == 30) | |
2217 | dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA; | |
2218 | else | |
2219 | return -EINVAL; | |
2220 | break; | |
2221 | default: | |
2222 | DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel); | |
2223 | return -EINVAL; | |
2224 | } | |
2225 | ||
2226 | if (obj->tiling_mode != I915_TILING_NONE) | |
2227 | dspcntr |= DISPPLANE_TILED; | |
2228 | else | |
2229 | dspcntr &= ~DISPPLANE_TILED; | |
2230 | ||
2231 | /* must disable */ | |
2232 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2233 | ||
2234 | I915_WRITE(reg, dspcntr); | |
2235 | ||
2236 | Start = obj->gtt_offset; | |
01f2c773 | 2237 | Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
17638cd6 JB |
2238 | |
2239 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", | |
01f2c773 VS |
2240 | Start, Offset, x, y, fb->pitches[0]); |
2241 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); | |
17638cd6 JB |
2242 | I915_WRITE(DSPSURF(plane), Start); |
2243 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2244 | I915_WRITE(DSPADDR(plane), Offset); | |
2245 | POSTING_READ(reg); | |
2246 | ||
2247 | return 0; | |
2248 | } | |
2249 | ||
2250 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ | |
2251 | static int | |
2252 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
2253 | int x, int y, enum mode_set_atomic state) | |
2254 | { | |
2255 | struct drm_device *dev = crtc->dev; | |
2256 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2257 | int ret; | |
2258 | ||
2259 | ret = dev_priv->display.update_plane(crtc, fb, x, y); | |
2260 | if (ret) | |
2261 | return ret; | |
2262 | ||
bed4a673 | 2263 | intel_update_fbc(dev); |
3dec0095 | 2264 | intel_increase_pllclock(crtc); |
81255565 JB |
2265 | |
2266 | return 0; | |
2267 | } | |
2268 | ||
5c3b82e2 | 2269 | static int |
3c4fdcfb KH |
2270 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
2271 | struct drm_framebuffer *old_fb) | |
79e53945 JB |
2272 | { |
2273 | struct drm_device *dev = crtc->dev; | |
79e53945 JB |
2274 | struct drm_i915_master_private *master_priv; |
2275 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5c3b82e2 | 2276 | int ret; |
79e53945 JB |
2277 | |
2278 | /* no fb bound */ | |
2279 | if (!crtc->fb) { | |
a5071c2f | 2280 | DRM_ERROR("No FB bound\n"); |
5c3b82e2 CW |
2281 | return 0; |
2282 | } | |
2283 | ||
265db958 | 2284 | switch (intel_crtc->plane) { |
5c3b82e2 CW |
2285 | case 0: |
2286 | case 1: | |
2287 | break; | |
27f8227b JB |
2288 | case 2: |
2289 | if (IS_IVYBRIDGE(dev)) | |
2290 | break; | |
2291 | /* fall through otherwise */ | |
5c3b82e2 | 2292 | default: |
a5071c2f | 2293 | DRM_ERROR("no plane for crtc\n"); |
5c3b82e2 | 2294 | return -EINVAL; |
79e53945 JB |
2295 | } |
2296 | ||
5c3b82e2 | 2297 | mutex_lock(&dev->struct_mutex); |
265db958 CW |
2298 | ret = intel_pin_and_fence_fb_obj(dev, |
2299 | to_intel_framebuffer(crtc->fb)->obj, | |
919926ae | 2300 | NULL); |
5c3b82e2 CW |
2301 | if (ret != 0) { |
2302 | mutex_unlock(&dev->struct_mutex); | |
a5071c2f | 2303 | DRM_ERROR("pin & fence failed\n"); |
5c3b82e2 CW |
2304 | return ret; |
2305 | } | |
79e53945 | 2306 | |
265db958 | 2307 | if (old_fb) { |
e6c3a2a6 | 2308 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 2309 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; |
265db958 | 2310 | |
e6c3a2a6 | 2311 | wait_event(dev_priv->pending_flip_queue, |
01eec727 | 2312 | atomic_read(&dev_priv->mm.wedged) || |
05394f39 | 2313 | atomic_read(&obj->pending_flip) == 0); |
85345517 CW |
2314 | |
2315 | /* Big Hammer, we also need to ensure that any pending | |
2316 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
2317 | * current scanout is retired before unpinning the old | |
2318 | * framebuffer. | |
01eec727 CW |
2319 | * |
2320 | * This should only fail upon a hung GPU, in which case we | |
2321 | * can safely continue. | |
85345517 | 2322 | */ |
a8198eea | 2323 | ret = i915_gem_object_finish_gpu(obj); |
01eec727 | 2324 | (void) ret; |
265db958 CW |
2325 | } |
2326 | ||
21c74a8e JW |
2327 | ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y, |
2328 | LEAVE_ATOMIC_MODE_SET); | |
4e6cfefc | 2329 | if (ret) { |
1690e1eb | 2330 | intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); |
5c3b82e2 | 2331 | mutex_unlock(&dev->struct_mutex); |
a5071c2f | 2332 | DRM_ERROR("failed to update base address\n"); |
4e6cfefc | 2333 | return ret; |
79e53945 | 2334 | } |
3c4fdcfb | 2335 | |
b7f1de28 CW |
2336 | if (old_fb) { |
2337 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1690e1eb | 2338 | intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); |
b7f1de28 | 2339 | } |
652c393a | 2340 | |
5c3b82e2 | 2341 | mutex_unlock(&dev->struct_mutex); |
79e53945 JB |
2342 | |
2343 | if (!dev->primary->master) | |
5c3b82e2 | 2344 | return 0; |
79e53945 JB |
2345 | |
2346 | master_priv = dev->primary->master->driver_priv; | |
2347 | if (!master_priv->sarea_priv) | |
5c3b82e2 | 2348 | return 0; |
79e53945 | 2349 | |
265db958 | 2350 | if (intel_crtc->pipe) { |
79e53945 JB |
2351 | master_priv->sarea_priv->pipeB_x = x; |
2352 | master_priv->sarea_priv->pipeB_y = y; | |
5c3b82e2 CW |
2353 | } else { |
2354 | master_priv->sarea_priv->pipeA_x = x; | |
2355 | master_priv->sarea_priv->pipeA_y = y; | |
79e53945 | 2356 | } |
5c3b82e2 CW |
2357 | |
2358 | return 0; | |
79e53945 JB |
2359 | } |
2360 | ||
5eddb70b | 2361 | static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock) |
32f9d658 ZW |
2362 | { |
2363 | struct drm_device *dev = crtc->dev; | |
2364 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2365 | u32 dpa_ctl; | |
2366 | ||
28c97730 | 2367 | DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock); |
32f9d658 ZW |
2368 | dpa_ctl = I915_READ(DP_A); |
2369 | dpa_ctl &= ~DP_PLL_FREQ_MASK; | |
2370 | ||
2371 | if (clock < 200000) { | |
2372 | u32 temp; | |
2373 | dpa_ctl |= DP_PLL_FREQ_160MHZ; | |
2374 | /* workaround for 160Mhz: | |
2375 | 1) program 0x4600c bits 15:0 = 0x8124 | |
2376 | 2) program 0x46010 bit 0 = 1 | |
2377 | 3) program 0x46034 bit 24 = 1 | |
2378 | 4) program 0x64000 bit 14 = 1 | |
2379 | */ | |
2380 | temp = I915_READ(0x4600c); | |
2381 | temp &= 0xffff0000; | |
2382 | I915_WRITE(0x4600c, temp | 0x8124); | |
2383 | ||
2384 | temp = I915_READ(0x46010); | |
2385 | I915_WRITE(0x46010, temp | 1); | |
2386 | ||
2387 | temp = I915_READ(0x46034); | |
2388 | I915_WRITE(0x46034, temp | (1 << 24)); | |
2389 | } else { | |
2390 | dpa_ctl |= DP_PLL_FREQ_270MHZ; | |
2391 | } | |
2392 | I915_WRITE(DP_A, dpa_ctl); | |
2393 | ||
5eddb70b | 2394 | POSTING_READ(DP_A); |
32f9d658 ZW |
2395 | udelay(500); |
2396 | } | |
2397 | ||
5e84e1a4 ZW |
2398 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
2399 | { | |
2400 | struct drm_device *dev = crtc->dev; | |
2401 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2402 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2403 | int pipe = intel_crtc->pipe; | |
2404 | u32 reg, temp; | |
2405 | ||
2406 | /* enable normal train */ | |
2407 | reg = FDI_TX_CTL(pipe); | |
2408 | temp = I915_READ(reg); | |
61e499bf | 2409 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
2410 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2411 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
2412 | } else { |
2413 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2414 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 2415 | } |
5e84e1a4 ZW |
2416 | I915_WRITE(reg, temp); |
2417 | ||
2418 | reg = FDI_RX_CTL(pipe); | |
2419 | temp = I915_READ(reg); | |
2420 | if (HAS_PCH_CPT(dev)) { | |
2421 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2422 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
2423 | } else { | |
2424 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2425 | temp |= FDI_LINK_TRAIN_NONE; | |
2426 | } | |
2427 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
2428 | ||
2429 | /* wait one idle pattern time */ | |
2430 | POSTING_READ(reg); | |
2431 | udelay(1000); | |
357555c0 JB |
2432 | |
2433 | /* IVB wants error correction enabled */ | |
2434 | if (IS_IVYBRIDGE(dev)) | |
2435 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
2436 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
2437 | } |
2438 | ||
291427f5 JB |
2439 | static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe) |
2440 | { | |
2441 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2442 | u32 flags = I915_READ(SOUTH_CHICKEN1); | |
2443 | ||
2444 | flags |= FDI_PHASE_SYNC_OVR(pipe); | |
2445 | I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */ | |
2446 | flags |= FDI_PHASE_SYNC_EN(pipe); | |
2447 | I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */ | |
2448 | POSTING_READ(SOUTH_CHICKEN1); | |
2449 | } | |
2450 | ||
8db9d77b ZW |
2451 | /* The FDI link training functions for ILK/Ibexpeak. */ |
2452 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
2453 | { | |
2454 | struct drm_device *dev = crtc->dev; | |
2455 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2456 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2457 | int pipe = intel_crtc->pipe; | |
0fc932b8 | 2458 | int plane = intel_crtc->plane; |
5eddb70b | 2459 | u32 reg, temp, tries; |
8db9d77b | 2460 | |
0fc932b8 JB |
2461 | /* FDI needs bits from pipe & plane first */ |
2462 | assert_pipe_enabled(dev_priv, pipe); | |
2463 | assert_plane_enabled(dev_priv, plane); | |
2464 | ||
e1a44743 AJ |
2465 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2466 | for train result */ | |
5eddb70b CW |
2467 | reg = FDI_RX_IMR(pipe); |
2468 | temp = I915_READ(reg); | |
e1a44743 AJ |
2469 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2470 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2471 | I915_WRITE(reg, temp); |
2472 | I915_READ(reg); | |
e1a44743 AJ |
2473 | udelay(150); |
2474 | ||
8db9d77b | 2475 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2476 | reg = FDI_TX_CTL(pipe); |
2477 | temp = I915_READ(reg); | |
77ffb597 AJ |
2478 | temp &= ~(7 << 19); |
2479 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
8db9d77b ZW |
2480 | temp &= ~FDI_LINK_TRAIN_NONE; |
2481 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 2482 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2483 | |
5eddb70b CW |
2484 | reg = FDI_RX_CTL(pipe); |
2485 | temp = I915_READ(reg); | |
8db9d77b ZW |
2486 | temp &= ~FDI_LINK_TRAIN_NONE; |
2487 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
2488 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2489 | ||
2490 | POSTING_READ(reg); | |
8db9d77b ZW |
2491 | udelay(150); |
2492 | ||
5b2adf89 | 2493 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
6f06ce18 JB |
2494 | if (HAS_PCH_IBX(dev)) { |
2495 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); | |
2496 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
2497 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
2498 | } | |
5b2adf89 | 2499 | |
5eddb70b | 2500 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2501 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2502 | temp = I915_READ(reg); |
8db9d77b ZW |
2503 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2504 | ||
2505 | if ((temp & FDI_RX_BIT_LOCK)) { | |
2506 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 2507 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
2508 | break; |
2509 | } | |
8db9d77b | 2510 | } |
e1a44743 | 2511 | if (tries == 5) |
5eddb70b | 2512 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2513 | |
2514 | /* Train 2 */ | |
5eddb70b CW |
2515 | reg = FDI_TX_CTL(pipe); |
2516 | temp = I915_READ(reg); | |
8db9d77b ZW |
2517 | temp &= ~FDI_LINK_TRAIN_NONE; |
2518 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2519 | I915_WRITE(reg, temp); |
8db9d77b | 2520 | |
5eddb70b CW |
2521 | reg = FDI_RX_CTL(pipe); |
2522 | temp = I915_READ(reg); | |
8db9d77b ZW |
2523 | temp &= ~FDI_LINK_TRAIN_NONE; |
2524 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2525 | I915_WRITE(reg, temp); |
8db9d77b | 2526 | |
5eddb70b CW |
2527 | POSTING_READ(reg); |
2528 | udelay(150); | |
8db9d77b | 2529 | |
5eddb70b | 2530 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2531 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2532 | temp = I915_READ(reg); |
8db9d77b ZW |
2533 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2534 | ||
2535 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 2536 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
2537 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2538 | break; | |
2539 | } | |
8db9d77b | 2540 | } |
e1a44743 | 2541 | if (tries == 5) |
5eddb70b | 2542 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2543 | |
2544 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 2545 | |
8db9d77b ZW |
2546 | } |
2547 | ||
0206e353 | 2548 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
2549 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
2550 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
2551 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
2552 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
2553 | }; | |
2554 | ||
2555 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
2556 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
2557 | { | |
2558 | struct drm_device *dev = crtc->dev; | |
2559 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2560 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2561 | int pipe = intel_crtc->pipe; | |
fa37d39e | 2562 | u32 reg, temp, i, retry; |
8db9d77b | 2563 | |
e1a44743 AJ |
2564 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2565 | for train result */ | |
5eddb70b CW |
2566 | reg = FDI_RX_IMR(pipe); |
2567 | temp = I915_READ(reg); | |
e1a44743 AJ |
2568 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2569 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2570 | I915_WRITE(reg, temp); |
2571 | ||
2572 | POSTING_READ(reg); | |
e1a44743 AJ |
2573 | udelay(150); |
2574 | ||
8db9d77b | 2575 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2576 | reg = FDI_TX_CTL(pipe); |
2577 | temp = I915_READ(reg); | |
77ffb597 AJ |
2578 | temp &= ~(7 << 19); |
2579 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
8db9d77b ZW |
2580 | temp &= ~FDI_LINK_TRAIN_NONE; |
2581 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2582 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2583 | /* SNB-B */ | |
2584 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 2585 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2586 | |
5eddb70b CW |
2587 | reg = FDI_RX_CTL(pipe); |
2588 | temp = I915_READ(reg); | |
8db9d77b ZW |
2589 | if (HAS_PCH_CPT(dev)) { |
2590 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2591 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2592 | } else { | |
2593 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2594 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2595 | } | |
5eddb70b CW |
2596 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2597 | ||
2598 | POSTING_READ(reg); | |
8db9d77b ZW |
2599 | udelay(150); |
2600 | ||
291427f5 JB |
2601 | if (HAS_PCH_CPT(dev)) |
2602 | cpt_phase_pointer_enable(dev, pipe); | |
2603 | ||
0206e353 | 2604 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2605 | reg = FDI_TX_CTL(pipe); |
2606 | temp = I915_READ(reg); | |
8db9d77b ZW |
2607 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2608 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2609 | I915_WRITE(reg, temp); |
2610 | ||
2611 | POSTING_READ(reg); | |
8db9d77b ZW |
2612 | udelay(500); |
2613 | ||
fa37d39e SP |
2614 | for (retry = 0; retry < 5; retry++) { |
2615 | reg = FDI_RX_IIR(pipe); | |
2616 | temp = I915_READ(reg); | |
2617 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2618 | if (temp & FDI_RX_BIT_LOCK) { | |
2619 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
2620 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
2621 | break; | |
2622 | } | |
2623 | udelay(50); | |
8db9d77b | 2624 | } |
fa37d39e SP |
2625 | if (retry < 5) |
2626 | break; | |
8db9d77b ZW |
2627 | } |
2628 | if (i == 4) | |
5eddb70b | 2629 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2630 | |
2631 | /* Train 2 */ | |
5eddb70b CW |
2632 | reg = FDI_TX_CTL(pipe); |
2633 | temp = I915_READ(reg); | |
8db9d77b ZW |
2634 | temp &= ~FDI_LINK_TRAIN_NONE; |
2635 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2636 | if (IS_GEN6(dev)) { | |
2637 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2638 | /* SNB-B */ | |
2639 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
2640 | } | |
5eddb70b | 2641 | I915_WRITE(reg, temp); |
8db9d77b | 2642 | |
5eddb70b CW |
2643 | reg = FDI_RX_CTL(pipe); |
2644 | temp = I915_READ(reg); | |
8db9d77b ZW |
2645 | if (HAS_PCH_CPT(dev)) { |
2646 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2647 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
2648 | } else { | |
2649 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2650 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2651 | } | |
5eddb70b CW |
2652 | I915_WRITE(reg, temp); |
2653 | ||
2654 | POSTING_READ(reg); | |
8db9d77b ZW |
2655 | udelay(150); |
2656 | ||
0206e353 | 2657 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2658 | reg = FDI_TX_CTL(pipe); |
2659 | temp = I915_READ(reg); | |
8db9d77b ZW |
2660 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2661 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2662 | I915_WRITE(reg, temp); |
2663 | ||
2664 | POSTING_READ(reg); | |
8db9d77b ZW |
2665 | udelay(500); |
2666 | ||
fa37d39e SP |
2667 | for (retry = 0; retry < 5; retry++) { |
2668 | reg = FDI_RX_IIR(pipe); | |
2669 | temp = I915_READ(reg); | |
2670 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2671 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
2672 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
2673 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
2674 | break; | |
2675 | } | |
2676 | udelay(50); | |
8db9d77b | 2677 | } |
fa37d39e SP |
2678 | if (retry < 5) |
2679 | break; | |
8db9d77b ZW |
2680 | } |
2681 | if (i == 4) | |
5eddb70b | 2682 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2683 | |
2684 | DRM_DEBUG_KMS("FDI train done.\n"); | |
2685 | } | |
2686 | ||
357555c0 JB |
2687 | /* Manual link training for Ivy Bridge A0 parts */ |
2688 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
2689 | { | |
2690 | struct drm_device *dev = crtc->dev; | |
2691 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2692 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2693 | int pipe = intel_crtc->pipe; | |
2694 | u32 reg, temp, i; | |
2695 | ||
2696 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
2697 | for train result */ | |
2698 | reg = FDI_RX_IMR(pipe); | |
2699 | temp = I915_READ(reg); | |
2700 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
2701 | temp &= ~FDI_RX_BIT_LOCK; | |
2702 | I915_WRITE(reg, temp); | |
2703 | ||
2704 | POSTING_READ(reg); | |
2705 | udelay(150); | |
2706 | ||
2707 | /* enable CPU FDI TX and PCH FDI RX */ | |
2708 | reg = FDI_TX_CTL(pipe); | |
2709 | temp = I915_READ(reg); | |
2710 | temp &= ~(7 << 19); | |
2711 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
2712 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
2713 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; | |
2714 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2715 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
c4f9c4c2 | 2716 | temp |= FDI_COMPOSITE_SYNC; |
357555c0 JB |
2717 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
2718 | ||
2719 | reg = FDI_RX_CTL(pipe); | |
2720 | temp = I915_READ(reg); | |
2721 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
2722 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2723 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
c4f9c4c2 | 2724 | temp |= FDI_COMPOSITE_SYNC; |
357555c0 JB |
2725 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2726 | ||
2727 | POSTING_READ(reg); | |
2728 | udelay(150); | |
2729 | ||
291427f5 JB |
2730 | if (HAS_PCH_CPT(dev)) |
2731 | cpt_phase_pointer_enable(dev, pipe); | |
2732 | ||
0206e353 | 2733 | for (i = 0; i < 4; i++) { |
357555c0 JB |
2734 | reg = FDI_TX_CTL(pipe); |
2735 | temp = I915_READ(reg); | |
2736 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2737 | temp |= snb_b_fdi_train_param[i]; | |
2738 | I915_WRITE(reg, temp); | |
2739 | ||
2740 | POSTING_READ(reg); | |
2741 | udelay(500); | |
2742 | ||
2743 | reg = FDI_RX_IIR(pipe); | |
2744 | temp = I915_READ(reg); | |
2745 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2746 | ||
2747 | if (temp & FDI_RX_BIT_LOCK || | |
2748 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
2749 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
2750 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
2751 | break; | |
2752 | } | |
2753 | } | |
2754 | if (i == 4) | |
2755 | DRM_ERROR("FDI train 1 fail!\n"); | |
2756 | ||
2757 | /* Train 2 */ | |
2758 | reg = FDI_TX_CTL(pipe); | |
2759 | temp = I915_READ(reg); | |
2760 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; | |
2761 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
2762 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2763 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
2764 | I915_WRITE(reg, temp); | |
2765 | ||
2766 | reg = FDI_RX_CTL(pipe); | |
2767 | temp = I915_READ(reg); | |
2768 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2769 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
2770 | I915_WRITE(reg, temp); | |
2771 | ||
2772 | POSTING_READ(reg); | |
2773 | udelay(150); | |
2774 | ||
0206e353 | 2775 | for (i = 0; i < 4; i++) { |
357555c0 JB |
2776 | reg = FDI_TX_CTL(pipe); |
2777 | temp = I915_READ(reg); | |
2778 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2779 | temp |= snb_b_fdi_train_param[i]; | |
2780 | I915_WRITE(reg, temp); | |
2781 | ||
2782 | POSTING_READ(reg); | |
2783 | udelay(500); | |
2784 | ||
2785 | reg = FDI_RX_IIR(pipe); | |
2786 | temp = I915_READ(reg); | |
2787 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2788 | ||
2789 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
2790 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
2791 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
2792 | break; | |
2793 | } | |
2794 | } | |
2795 | if (i == 4) | |
2796 | DRM_ERROR("FDI train 2 fail!\n"); | |
2797 | ||
2798 | DRM_DEBUG_KMS("FDI train done.\n"); | |
2799 | } | |
2800 | ||
2801 | static void ironlake_fdi_pll_enable(struct drm_crtc *crtc) | |
2c07245f ZW |
2802 | { |
2803 | struct drm_device *dev = crtc->dev; | |
2804 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2805 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2806 | int pipe = intel_crtc->pipe; | |
5eddb70b | 2807 | u32 reg, temp; |
79e53945 | 2808 | |
c64e311e | 2809 | /* Write the TU size bits so error detection works */ |
5eddb70b CW |
2810 | I915_WRITE(FDI_RX_TUSIZE1(pipe), |
2811 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
c64e311e | 2812 | |
c98e9dcf | 2813 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
2814 | reg = FDI_RX_CTL(pipe); |
2815 | temp = I915_READ(reg); | |
2816 | temp &= ~((0x7 << 19) | (0x7 << 16)); | |
c98e9dcf | 2817 | temp |= (intel_crtc->fdi_lanes - 1) << 19; |
5eddb70b CW |
2818 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; |
2819 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); | |
2820 | ||
2821 | POSTING_READ(reg); | |
c98e9dcf JB |
2822 | udelay(200); |
2823 | ||
2824 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
2825 | temp = I915_READ(reg); |
2826 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
2827 | ||
2828 | POSTING_READ(reg); | |
c98e9dcf JB |
2829 | udelay(200); |
2830 | ||
2831 | /* Enable CPU FDI TX PLL, always on for Ironlake */ | |
5eddb70b CW |
2832 | reg = FDI_TX_CTL(pipe); |
2833 | temp = I915_READ(reg); | |
c98e9dcf | 2834 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { |
5eddb70b CW |
2835 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); |
2836 | ||
2837 | POSTING_READ(reg); | |
c98e9dcf | 2838 | udelay(100); |
6be4a607 | 2839 | } |
0e23b99d JB |
2840 | } |
2841 | ||
291427f5 JB |
2842 | static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe) |
2843 | { | |
2844 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2845 | u32 flags = I915_READ(SOUTH_CHICKEN1); | |
2846 | ||
2847 | flags &= ~(FDI_PHASE_SYNC_EN(pipe)); | |
2848 | I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */ | |
2849 | flags &= ~(FDI_PHASE_SYNC_OVR(pipe)); | |
2850 | I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */ | |
2851 | POSTING_READ(SOUTH_CHICKEN1); | |
2852 | } | |
0fc932b8 JB |
2853 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
2854 | { | |
2855 | struct drm_device *dev = crtc->dev; | |
2856 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2857 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2858 | int pipe = intel_crtc->pipe; | |
2859 | u32 reg, temp; | |
2860 | ||
2861 | /* disable CPU FDI tx and PCH FDI rx */ | |
2862 | reg = FDI_TX_CTL(pipe); | |
2863 | temp = I915_READ(reg); | |
2864 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
2865 | POSTING_READ(reg); | |
2866 | ||
2867 | reg = FDI_RX_CTL(pipe); | |
2868 | temp = I915_READ(reg); | |
2869 | temp &= ~(0x7 << 16); | |
2870 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; | |
2871 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); | |
2872 | ||
2873 | POSTING_READ(reg); | |
2874 | udelay(100); | |
2875 | ||
2876 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
6f06ce18 JB |
2877 | if (HAS_PCH_IBX(dev)) { |
2878 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); | |
0fc932b8 JB |
2879 | I915_WRITE(FDI_RX_CHICKEN(pipe), |
2880 | I915_READ(FDI_RX_CHICKEN(pipe) & | |
6f06ce18 | 2881 | ~FDI_RX_PHASE_SYNC_POINTER_EN)); |
291427f5 JB |
2882 | } else if (HAS_PCH_CPT(dev)) { |
2883 | cpt_phase_pointer_disable(dev, pipe); | |
6f06ce18 | 2884 | } |
0fc932b8 JB |
2885 | |
2886 | /* still set train pattern 1 */ | |
2887 | reg = FDI_TX_CTL(pipe); | |
2888 | temp = I915_READ(reg); | |
2889 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2890 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2891 | I915_WRITE(reg, temp); | |
2892 | ||
2893 | reg = FDI_RX_CTL(pipe); | |
2894 | temp = I915_READ(reg); | |
2895 | if (HAS_PCH_CPT(dev)) { | |
2896 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2897 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2898 | } else { | |
2899 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2900 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2901 | } | |
2902 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
2903 | temp &= ~(0x07 << 16); | |
2904 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; | |
2905 | I915_WRITE(reg, temp); | |
2906 | ||
2907 | POSTING_READ(reg); | |
2908 | udelay(100); | |
2909 | } | |
2910 | ||
6b383a7f CW |
2911 | /* |
2912 | * When we disable a pipe, we need to clear any pending scanline wait events | |
2913 | * to avoid hanging the ring, which we assume we are waiting on. | |
2914 | */ | |
2915 | static void intel_clear_scanline_wait(struct drm_device *dev) | |
2916 | { | |
2917 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8168bd48 | 2918 | struct intel_ring_buffer *ring; |
6b383a7f CW |
2919 | u32 tmp; |
2920 | ||
2921 | if (IS_GEN2(dev)) | |
2922 | /* Can't break the hang on i8xx */ | |
2923 | return; | |
2924 | ||
1ec14ad3 | 2925 | ring = LP_RING(dev_priv); |
8168bd48 CW |
2926 | tmp = I915_READ_CTL(ring); |
2927 | if (tmp & RING_WAIT) | |
2928 | I915_WRITE_CTL(ring, tmp); | |
6b383a7f CW |
2929 | } |
2930 | ||
e6c3a2a6 CW |
2931 | static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
2932 | { | |
05394f39 | 2933 | struct drm_i915_gem_object *obj; |
e6c3a2a6 CW |
2934 | struct drm_i915_private *dev_priv; |
2935 | ||
2936 | if (crtc->fb == NULL) | |
2937 | return; | |
2938 | ||
05394f39 | 2939 | obj = to_intel_framebuffer(crtc->fb)->obj; |
e6c3a2a6 CW |
2940 | dev_priv = crtc->dev->dev_private; |
2941 | wait_event(dev_priv->pending_flip_queue, | |
05394f39 | 2942 | atomic_read(&obj->pending_flip) == 0); |
e6c3a2a6 CW |
2943 | } |
2944 | ||
040484af JB |
2945 | static bool intel_crtc_driving_pch(struct drm_crtc *crtc) |
2946 | { | |
2947 | struct drm_device *dev = crtc->dev; | |
2948 | struct drm_mode_config *mode_config = &dev->mode_config; | |
2949 | struct intel_encoder *encoder; | |
2950 | ||
2951 | /* | |
2952 | * If there's a non-PCH eDP on this crtc, it must be DP_A, and that | |
2953 | * must be driven by its own crtc; no sharing is possible. | |
2954 | */ | |
2955 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { | |
2956 | if (encoder->base.crtc != crtc) | |
2957 | continue; | |
2958 | ||
2959 | switch (encoder->type) { | |
2960 | case INTEL_OUTPUT_EDP: | |
2961 | if (!intel_encoder_is_pch_edp(&encoder->base)) | |
2962 | return false; | |
2963 | continue; | |
2964 | } | |
2965 | } | |
2966 | ||
2967 | return true; | |
2968 | } | |
2969 | ||
f67a559d JB |
2970 | /* |
2971 | * Enable PCH resources required for PCH ports: | |
2972 | * - PCH PLLs | |
2973 | * - FDI training & RX/TX | |
2974 | * - update transcoder timings | |
2975 | * - DP transcoding bits | |
2976 | * - transcoder | |
2977 | */ | |
2978 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
2979 | { |
2980 | struct drm_device *dev = crtc->dev; | |
2981 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2982 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2983 | int pipe = intel_crtc->pipe; | |
4b645f14 | 2984 | u32 reg, temp, transc_sel; |
2c07245f | 2985 | |
c98e9dcf | 2986 | /* For PCH output, training FDI link */ |
674cf967 | 2987 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 2988 | |
92f2584a | 2989 | intel_enable_pch_pll(dev_priv, pipe); |
8db9d77b | 2990 | |
c98e9dcf | 2991 | if (HAS_PCH_CPT(dev)) { |
4b645f14 JB |
2992 | transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL : |
2993 | TRANSC_DPLLB_SEL; | |
2994 | ||
c98e9dcf JB |
2995 | /* Be sure PCH DPLL SEL is set */ |
2996 | temp = I915_READ(PCH_DPLL_SEL); | |
d64311ab JB |
2997 | if (pipe == 0) { |
2998 | temp &= ~(TRANSA_DPLLB_SEL); | |
c98e9dcf | 2999 | temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL); |
d64311ab JB |
3000 | } else if (pipe == 1) { |
3001 | temp &= ~(TRANSB_DPLLB_SEL); | |
c98e9dcf | 3002 | temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); |
d64311ab JB |
3003 | } else if (pipe == 2) { |
3004 | temp &= ~(TRANSC_DPLLB_SEL); | |
4b645f14 | 3005 | temp |= (TRANSC_DPLL_ENABLE | transc_sel); |
d64311ab | 3006 | } |
c98e9dcf | 3007 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 3008 | } |
5eddb70b | 3009 | |
d9b6cb56 JB |
3010 | /* set transcoder timing, panel must allow it */ |
3011 | assert_panel_unlocked(dev_priv, pipe); | |
5eddb70b CW |
3012 | I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe))); |
3013 | I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe))); | |
3014 | I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe))); | |
8db9d77b | 3015 | |
5eddb70b CW |
3016 | I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe))); |
3017 | I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe))); | |
3018 | I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe))); | |
0529a0d9 | 3019 | I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe))); |
8db9d77b | 3020 | |
5e84e1a4 ZW |
3021 | intel_fdi_normal_train(crtc); |
3022 | ||
c98e9dcf JB |
3023 | /* For PCH DP, enable TRANS_DP_CTL */ |
3024 | if (HAS_PCH_CPT(dev) && | |
417e822d KP |
3025 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
3026 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
9325c9f0 | 3027 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5; |
5eddb70b CW |
3028 | reg = TRANS_DP_CTL(pipe); |
3029 | temp = I915_READ(reg); | |
3030 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
3031 | TRANS_DP_SYNC_MASK | |
3032 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
3033 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
3034 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 3035 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
3036 | |
3037 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 3038 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 3039 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 3040 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
3041 | |
3042 | switch (intel_trans_dp_port_sel(crtc)) { | |
3043 | case PCH_DP_B: | |
5eddb70b | 3044 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
3045 | break; |
3046 | case PCH_DP_C: | |
5eddb70b | 3047 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
3048 | break; |
3049 | case PCH_DP_D: | |
5eddb70b | 3050 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
3051 | break; |
3052 | default: | |
3053 | DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n"); | |
5eddb70b | 3054 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 3055 | break; |
32f9d658 | 3056 | } |
2c07245f | 3057 | |
5eddb70b | 3058 | I915_WRITE(reg, temp); |
6be4a607 | 3059 | } |
b52eb4dc | 3060 | |
040484af | 3061 | intel_enable_transcoder(dev_priv, pipe); |
f67a559d JB |
3062 | } |
3063 | ||
d4270e57 JB |
3064 | void intel_cpt_verify_modeset(struct drm_device *dev, int pipe) |
3065 | { | |
3066 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3067 | int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe); | |
3068 | u32 temp; | |
3069 | ||
3070 | temp = I915_READ(dslreg); | |
3071 | udelay(500); | |
3072 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
3073 | /* Without this, mode sets may fail silently on FDI */ | |
3074 | I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS); | |
3075 | udelay(250); | |
3076 | I915_WRITE(tc2reg, 0); | |
3077 | if (wait_for(I915_READ(dslreg) != temp, 5)) | |
3078 | DRM_ERROR("mode set failed: pipe %d stuck\n", pipe); | |
3079 | } | |
3080 | } | |
3081 | ||
f67a559d JB |
3082 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
3083 | { | |
3084 | struct drm_device *dev = crtc->dev; | |
3085 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3086 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3087 | int pipe = intel_crtc->pipe; | |
3088 | int plane = intel_crtc->plane; | |
3089 | u32 temp; | |
3090 | bool is_pch_port; | |
3091 | ||
3092 | if (intel_crtc->active) | |
3093 | return; | |
3094 | ||
3095 | intel_crtc->active = true; | |
3096 | intel_update_watermarks(dev); | |
3097 | ||
3098 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
3099 | temp = I915_READ(PCH_LVDS); | |
3100 | if ((temp & LVDS_PORT_EN) == 0) | |
3101 | I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN); | |
3102 | } | |
3103 | ||
3104 | is_pch_port = intel_crtc_driving_pch(crtc); | |
3105 | ||
3106 | if (is_pch_port) | |
357555c0 | 3107 | ironlake_fdi_pll_enable(crtc); |
f67a559d JB |
3108 | else |
3109 | ironlake_fdi_disable(crtc); | |
3110 | ||
3111 | /* Enable panel fitting for LVDS */ | |
3112 | if (dev_priv->pch_pf_size && | |
3113 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) { | |
3114 | /* Force use of hard-coded filter coefficients | |
3115 | * as some pre-programmed values are broken, | |
3116 | * e.g. x201. | |
3117 | */ | |
9db4a9c7 JB |
3118 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); |
3119 | I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos); | |
3120 | I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size); | |
f67a559d JB |
3121 | } |
3122 | ||
9c54c0dd JB |
3123 | /* |
3124 | * On ILK+ LUT must be loaded before the pipe is running but with | |
3125 | * clocks enabled | |
3126 | */ | |
3127 | intel_crtc_load_lut(crtc); | |
3128 | ||
f67a559d JB |
3129 | intel_enable_pipe(dev_priv, pipe, is_pch_port); |
3130 | intel_enable_plane(dev_priv, plane, pipe); | |
3131 | ||
3132 | if (is_pch_port) | |
3133 | ironlake_pch_enable(crtc); | |
c98e9dcf | 3134 | |
d1ebd816 | 3135 | mutex_lock(&dev->struct_mutex); |
bed4a673 | 3136 | intel_update_fbc(dev); |
d1ebd816 BW |
3137 | mutex_unlock(&dev->struct_mutex); |
3138 | ||
6b383a7f | 3139 | intel_crtc_update_cursor(crtc, true); |
6be4a607 JB |
3140 | } |
3141 | ||
3142 | static void ironlake_crtc_disable(struct drm_crtc *crtc) | |
3143 | { | |
3144 | struct drm_device *dev = crtc->dev; | |
3145 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3146 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3147 | int pipe = intel_crtc->pipe; | |
3148 | int plane = intel_crtc->plane; | |
5eddb70b | 3149 | u32 reg, temp; |
b52eb4dc | 3150 | |
f7abfe8b CW |
3151 | if (!intel_crtc->active) |
3152 | return; | |
3153 | ||
e6c3a2a6 | 3154 | intel_crtc_wait_for_pending_flips(crtc); |
6be4a607 | 3155 | drm_vblank_off(dev, pipe); |
6b383a7f | 3156 | intel_crtc_update_cursor(crtc, false); |
5eddb70b | 3157 | |
b24e7179 | 3158 | intel_disable_plane(dev_priv, plane, pipe); |
913d8d11 | 3159 | |
973d04f9 CW |
3160 | if (dev_priv->cfb_plane == plane) |
3161 | intel_disable_fbc(dev); | |
2c07245f | 3162 | |
b24e7179 | 3163 | intel_disable_pipe(dev_priv, pipe); |
32f9d658 | 3164 | |
6be4a607 | 3165 | /* Disable PF */ |
9db4a9c7 JB |
3166 | I915_WRITE(PF_CTL(pipe), 0); |
3167 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
2c07245f | 3168 | |
0fc932b8 | 3169 | ironlake_fdi_disable(crtc); |
2c07245f | 3170 | |
47a05eca JB |
3171 | /* This is a horrible layering violation; we should be doing this in |
3172 | * the connector/encoder ->prepare instead, but we don't always have | |
3173 | * enough information there about the config to know whether it will | |
3174 | * actually be necessary or just cause undesired flicker. | |
3175 | */ | |
3176 | intel_disable_pch_ports(dev_priv, pipe); | |
249c0e64 | 3177 | |
040484af | 3178 | intel_disable_transcoder(dev_priv, pipe); |
913d8d11 | 3179 | |
6be4a607 JB |
3180 | if (HAS_PCH_CPT(dev)) { |
3181 | /* disable TRANS_DP_CTL */ | |
5eddb70b CW |
3182 | reg = TRANS_DP_CTL(pipe); |
3183 | temp = I915_READ(reg); | |
3184 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK); | |
cb3543c6 | 3185 | temp |= TRANS_DP_PORT_SEL_NONE; |
5eddb70b | 3186 | I915_WRITE(reg, temp); |
6be4a607 JB |
3187 | |
3188 | /* disable DPLL_SEL */ | |
3189 | temp = I915_READ(PCH_DPLL_SEL); | |
9db4a9c7 JB |
3190 | switch (pipe) { |
3191 | case 0: | |
d64311ab | 3192 | temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL); |
9db4a9c7 JB |
3193 | break; |
3194 | case 1: | |
6be4a607 | 3195 | temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); |
9db4a9c7 JB |
3196 | break; |
3197 | case 2: | |
4b645f14 | 3198 | /* C shares PLL A or B */ |
d64311ab | 3199 | temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL); |
9db4a9c7 JB |
3200 | break; |
3201 | default: | |
3202 | BUG(); /* wtf */ | |
3203 | } | |
6be4a607 | 3204 | I915_WRITE(PCH_DPLL_SEL, temp); |
6be4a607 | 3205 | } |
e3421a18 | 3206 | |
6be4a607 | 3207 | /* disable PCH DPLL */ |
4b645f14 JB |
3208 | if (!intel_crtc->no_pll) |
3209 | intel_disable_pch_pll(dev_priv, pipe); | |
8db9d77b | 3210 | |
6be4a607 | 3211 | /* Switch from PCDclk to Rawclk */ |
5eddb70b CW |
3212 | reg = FDI_RX_CTL(pipe); |
3213 | temp = I915_READ(reg); | |
3214 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
8db9d77b | 3215 | |
6be4a607 | 3216 | /* Disable CPU FDI TX PLL */ |
5eddb70b CW |
3217 | reg = FDI_TX_CTL(pipe); |
3218 | temp = I915_READ(reg); | |
3219 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3220 | ||
3221 | POSTING_READ(reg); | |
6be4a607 | 3222 | udelay(100); |
8db9d77b | 3223 | |
5eddb70b CW |
3224 | reg = FDI_RX_CTL(pipe); |
3225 | temp = I915_READ(reg); | |
3226 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
2c07245f | 3227 | |
6be4a607 | 3228 | /* Wait for the clocks to turn off. */ |
5eddb70b | 3229 | POSTING_READ(reg); |
6be4a607 | 3230 | udelay(100); |
6b383a7f | 3231 | |
f7abfe8b | 3232 | intel_crtc->active = false; |
6b383a7f | 3233 | intel_update_watermarks(dev); |
d1ebd816 BW |
3234 | |
3235 | mutex_lock(&dev->struct_mutex); | |
6b383a7f CW |
3236 | intel_update_fbc(dev); |
3237 | intel_clear_scanline_wait(dev); | |
d1ebd816 | 3238 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 3239 | } |
1b3c7a47 | 3240 | |
6be4a607 JB |
3241 | static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode) |
3242 | { | |
3243 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3244 | int pipe = intel_crtc->pipe; | |
3245 | int plane = intel_crtc->plane; | |
8db9d77b | 3246 | |
6be4a607 JB |
3247 | /* XXX: When our outputs are all unaware of DPMS modes other than off |
3248 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. | |
3249 | */ | |
3250 | switch (mode) { | |
3251 | case DRM_MODE_DPMS_ON: | |
3252 | case DRM_MODE_DPMS_STANDBY: | |
3253 | case DRM_MODE_DPMS_SUSPEND: | |
3254 | DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane); | |
3255 | ironlake_crtc_enable(crtc); | |
3256 | break; | |
1b3c7a47 | 3257 | |
6be4a607 JB |
3258 | case DRM_MODE_DPMS_OFF: |
3259 | DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane); | |
3260 | ironlake_crtc_disable(crtc); | |
2c07245f ZW |
3261 | break; |
3262 | } | |
3263 | } | |
3264 | ||
02e792fb DV |
3265 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
3266 | { | |
02e792fb | 3267 | if (!enable && intel_crtc->overlay) { |
23f09ce3 | 3268 | struct drm_device *dev = intel_crtc->base.dev; |
ce453d81 | 3269 | struct drm_i915_private *dev_priv = dev->dev_private; |
03f77ea5 | 3270 | |
23f09ce3 | 3271 | mutex_lock(&dev->struct_mutex); |
ce453d81 CW |
3272 | dev_priv->mm.interruptible = false; |
3273 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
3274 | dev_priv->mm.interruptible = true; | |
23f09ce3 | 3275 | mutex_unlock(&dev->struct_mutex); |
02e792fb | 3276 | } |
02e792fb | 3277 | |
5dcdbcb0 CW |
3278 | /* Let userspace switch the overlay on again. In most cases userspace |
3279 | * has to recompute where to put it anyway. | |
3280 | */ | |
02e792fb DV |
3281 | } |
3282 | ||
0b8765c6 | 3283 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
3284 | { |
3285 | struct drm_device *dev = crtc->dev; | |
79e53945 JB |
3286 | struct drm_i915_private *dev_priv = dev->dev_private; |
3287 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3288 | int pipe = intel_crtc->pipe; | |
80824003 | 3289 | int plane = intel_crtc->plane; |
79e53945 | 3290 | |
f7abfe8b CW |
3291 | if (intel_crtc->active) |
3292 | return; | |
3293 | ||
3294 | intel_crtc->active = true; | |
6b383a7f CW |
3295 | intel_update_watermarks(dev); |
3296 | ||
63d7bbe9 | 3297 | intel_enable_pll(dev_priv, pipe); |
040484af | 3298 | intel_enable_pipe(dev_priv, pipe, false); |
b24e7179 | 3299 | intel_enable_plane(dev_priv, plane, pipe); |
79e53945 | 3300 | |
0b8765c6 | 3301 | intel_crtc_load_lut(crtc); |
bed4a673 | 3302 | intel_update_fbc(dev); |
79e53945 | 3303 | |
0b8765c6 JB |
3304 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
3305 | intel_crtc_dpms_overlay(intel_crtc, true); | |
6b383a7f | 3306 | intel_crtc_update_cursor(crtc, true); |
0b8765c6 | 3307 | } |
79e53945 | 3308 | |
0b8765c6 JB |
3309 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
3310 | { | |
3311 | struct drm_device *dev = crtc->dev; | |
3312 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3313 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3314 | int pipe = intel_crtc->pipe; | |
3315 | int plane = intel_crtc->plane; | |
b690e96c | 3316 | |
f7abfe8b CW |
3317 | if (!intel_crtc->active) |
3318 | return; | |
3319 | ||
0b8765c6 | 3320 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
e6c3a2a6 CW |
3321 | intel_crtc_wait_for_pending_flips(crtc); |
3322 | drm_vblank_off(dev, pipe); | |
0b8765c6 | 3323 | intel_crtc_dpms_overlay(intel_crtc, false); |
6b383a7f | 3324 | intel_crtc_update_cursor(crtc, false); |
0b8765c6 | 3325 | |
973d04f9 CW |
3326 | if (dev_priv->cfb_plane == plane) |
3327 | intel_disable_fbc(dev); | |
79e53945 | 3328 | |
b24e7179 | 3329 | intel_disable_plane(dev_priv, plane, pipe); |
b24e7179 | 3330 | intel_disable_pipe(dev_priv, pipe); |
63d7bbe9 | 3331 | intel_disable_pll(dev_priv, pipe); |
0b8765c6 | 3332 | |
f7abfe8b | 3333 | intel_crtc->active = false; |
6b383a7f CW |
3334 | intel_update_fbc(dev); |
3335 | intel_update_watermarks(dev); | |
3336 | intel_clear_scanline_wait(dev); | |
0b8765c6 JB |
3337 | } |
3338 | ||
3339 | static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode) | |
3340 | { | |
3341 | /* XXX: When our outputs are all unaware of DPMS modes other than off | |
3342 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. | |
3343 | */ | |
3344 | switch (mode) { | |
3345 | case DRM_MODE_DPMS_ON: | |
3346 | case DRM_MODE_DPMS_STANDBY: | |
3347 | case DRM_MODE_DPMS_SUSPEND: | |
3348 | i9xx_crtc_enable(crtc); | |
3349 | break; | |
3350 | case DRM_MODE_DPMS_OFF: | |
3351 | i9xx_crtc_disable(crtc); | |
79e53945 JB |
3352 | break; |
3353 | } | |
2c07245f ZW |
3354 | } |
3355 | ||
3356 | /** | |
3357 | * Sets the power management mode of the pipe and plane. | |
2c07245f ZW |
3358 | */ |
3359 | static void intel_crtc_dpms(struct drm_crtc *crtc, int mode) | |
3360 | { | |
3361 | struct drm_device *dev = crtc->dev; | |
e70236a8 | 3362 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f ZW |
3363 | struct drm_i915_master_private *master_priv; |
3364 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3365 | int pipe = intel_crtc->pipe; | |
3366 | bool enabled; | |
3367 | ||
032d2a0d CW |
3368 | if (intel_crtc->dpms_mode == mode) |
3369 | return; | |
3370 | ||
65655d4a | 3371 | intel_crtc->dpms_mode = mode; |
debcaddc | 3372 | |
e70236a8 | 3373 | dev_priv->display.dpms(crtc, mode); |
79e53945 JB |
3374 | |
3375 | if (!dev->primary->master) | |
3376 | return; | |
3377 | ||
3378 | master_priv = dev->primary->master->driver_priv; | |
3379 | if (!master_priv->sarea_priv) | |
3380 | return; | |
3381 | ||
3382 | enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF; | |
3383 | ||
3384 | switch (pipe) { | |
3385 | case 0: | |
3386 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; | |
3387 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; | |
3388 | break; | |
3389 | case 1: | |
3390 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; | |
3391 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; | |
3392 | break; | |
3393 | default: | |
9db4a9c7 | 3394 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
79e53945 JB |
3395 | break; |
3396 | } | |
79e53945 JB |
3397 | } |
3398 | ||
cdd59983 CW |
3399 | static void intel_crtc_disable(struct drm_crtc *crtc) |
3400 | { | |
3401 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
3402 | struct drm_device *dev = crtc->dev; | |
3403 | ||
3404 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); | |
931872fc CW |
3405 | assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); |
3406 | assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); | |
cdd59983 CW |
3407 | |
3408 | if (crtc->fb) { | |
3409 | mutex_lock(&dev->struct_mutex); | |
1690e1eb | 3410 | intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); |
cdd59983 CW |
3411 | mutex_unlock(&dev->struct_mutex); |
3412 | } | |
3413 | } | |
3414 | ||
7e7d76c3 JB |
3415 | /* Prepare for a mode set. |
3416 | * | |
3417 | * Note we could be a lot smarter here. We need to figure out which outputs | |
3418 | * will be enabled, which disabled (in short, how the config will changes) | |
3419 | * and perform the minimum necessary steps to accomplish that, e.g. updating | |
3420 | * watermarks, FBC configuration, making sure PLLs are programmed correctly, | |
3421 | * panel fitting is in the proper state, etc. | |
3422 | */ | |
3423 | static void i9xx_crtc_prepare(struct drm_crtc *crtc) | |
79e53945 | 3424 | { |
7e7d76c3 | 3425 | i9xx_crtc_disable(crtc); |
79e53945 JB |
3426 | } |
3427 | ||
7e7d76c3 | 3428 | static void i9xx_crtc_commit(struct drm_crtc *crtc) |
79e53945 | 3429 | { |
7e7d76c3 | 3430 | i9xx_crtc_enable(crtc); |
7e7d76c3 JB |
3431 | } |
3432 | ||
3433 | static void ironlake_crtc_prepare(struct drm_crtc *crtc) | |
3434 | { | |
7e7d76c3 | 3435 | ironlake_crtc_disable(crtc); |
7e7d76c3 JB |
3436 | } |
3437 | ||
3438 | static void ironlake_crtc_commit(struct drm_crtc *crtc) | |
3439 | { | |
7e7d76c3 | 3440 | ironlake_crtc_enable(crtc); |
79e53945 JB |
3441 | } |
3442 | ||
0206e353 | 3443 | void intel_encoder_prepare(struct drm_encoder *encoder) |
79e53945 JB |
3444 | { |
3445 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
3446 | /* lvds has its own version of prepare see intel_lvds_prepare */ | |
3447 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); | |
3448 | } | |
3449 | ||
0206e353 | 3450 | void intel_encoder_commit(struct drm_encoder *encoder) |
79e53945 JB |
3451 | { |
3452 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
d4270e57 JB |
3453 | struct drm_device *dev = encoder->dev; |
3454 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
3455 | struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
3456 | ||
79e53945 JB |
3457 | /* lvds has its own version of commit see intel_lvds_commit */ |
3458 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); | |
d4270e57 JB |
3459 | |
3460 | if (HAS_PCH_CPT(dev)) | |
3461 | intel_cpt_verify_modeset(dev, intel_crtc->pipe); | |
79e53945 JB |
3462 | } |
3463 | ||
ea5b213a CW |
3464 | void intel_encoder_destroy(struct drm_encoder *encoder) |
3465 | { | |
4ef69c7a | 3466 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 3467 | |
ea5b213a CW |
3468 | drm_encoder_cleanup(encoder); |
3469 | kfree(intel_encoder); | |
3470 | } | |
3471 | ||
79e53945 JB |
3472 | static bool intel_crtc_mode_fixup(struct drm_crtc *crtc, |
3473 | struct drm_display_mode *mode, | |
3474 | struct drm_display_mode *adjusted_mode) | |
3475 | { | |
2c07245f | 3476 | struct drm_device *dev = crtc->dev; |
89749350 | 3477 | |
bad720ff | 3478 | if (HAS_PCH_SPLIT(dev)) { |
2c07245f | 3479 | /* FDI link clock is fixed at 2.7G */ |
2377b741 JB |
3480 | if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4) |
3481 | return false; | |
2c07245f | 3482 | } |
89749350 | 3483 | |
ca9bfa7e DV |
3484 | /* All interlaced capable intel hw wants timings in frames. */ |
3485 | drm_mode_set_crtcinfo(adjusted_mode, 0); | |
89749350 | 3486 | |
79e53945 JB |
3487 | return true; |
3488 | } | |
3489 | ||
e70236a8 JB |
3490 | static int i945_get_display_clock_speed(struct drm_device *dev) |
3491 | { | |
3492 | return 400000; | |
3493 | } | |
79e53945 | 3494 | |
e70236a8 | 3495 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 3496 | { |
e70236a8 JB |
3497 | return 333000; |
3498 | } | |
79e53945 | 3499 | |
e70236a8 JB |
3500 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
3501 | { | |
3502 | return 200000; | |
3503 | } | |
79e53945 | 3504 | |
e70236a8 JB |
3505 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
3506 | { | |
3507 | u16 gcfgc = 0; | |
79e53945 | 3508 | |
e70236a8 JB |
3509 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
3510 | ||
3511 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
3512 | return 133000; | |
3513 | else { | |
3514 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
3515 | case GC_DISPLAY_CLOCK_333_MHZ: | |
3516 | return 333000; | |
3517 | default: | |
3518 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
3519 | return 190000; | |
79e53945 | 3520 | } |
e70236a8 JB |
3521 | } |
3522 | } | |
3523 | ||
3524 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
3525 | { | |
3526 | return 266000; | |
3527 | } | |
3528 | ||
3529 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
3530 | { | |
3531 | u16 hpllcc = 0; | |
3532 | /* Assume that the hardware is in the high speed state. This | |
3533 | * should be the default. | |
3534 | */ | |
3535 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
3536 | case GC_CLOCK_133_200: | |
3537 | case GC_CLOCK_100_200: | |
3538 | return 200000; | |
3539 | case GC_CLOCK_166_250: | |
3540 | return 250000; | |
3541 | case GC_CLOCK_100_133: | |
79e53945 | 3542 | return 133000; |
e70236a8 | 3543 | } |
79e53945 | 3544 | |
e70236a8 JB |
3545 | /* Shouldn't happen */ |
3546 | return 0; | |
3547 | } | |
79e53945 | 3548 | |
e70236a8 JB |
3549 | static int i830_get_display_clock_speed(struct drm_device *dev) |
3550 | { | |
3551 | return 133000; | |
79e53945 JB |
3552 | } |
3553 | ||
2c07245f ZW |
3554 | struct fdi_m_n { |
3555 | u32 tu; | |
3556 | u32 gmch_m; | |
3557 | u32 gmch_n; | |
3558 | u32 link_m; | |
3559 | u32 link_n; | |
3560 | }; | |
3561 | ||
3562 | static void | |
3563 | fdi_reduce_ratio(u32 *num, u32 *den) | |
3564 | { | |
3565 | while (*num > 0xffffff || *den > 0xffffff) { | |
3566 | *num >>= 1; | |
3567 | *den >>= 1; | |
3568 | } | |
3569 | } | |
3570 | ||
2c07245f | 3571 | static void |
f2b115e6 AJ |
3572 | ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock, |
3573 | int link_clock, struct fdi_m_n *m_n) | |
2c07245f | 3574 | { |
2c07245f ZW |
3575 | m_n->tu = 64; /* default size */ |
3576 | ||
22ed1113 CW |
3577 | /* BUG_ON(pixel_clock > INT_MAX / 36); */ |
3578 | m_n->gmch_m = bits_per_pixel * pixel_clock; | |
3579 | m_n->gmch_n = link_clock * nlanes * 8; | |
2c07245f ZW |
3580 | fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); |
3581 | ||
22ed1113 CW |
3582 | m_n->link_m = pixel_clock; |
3583 | m_n->link_n = link_clock; | |
2c07245f ZW |
3584 | fdi_reduce_ratio(&m_n->link_m, &m_n->link_n); |
3585 | } | |
3586 | ||
3587 | ||
7662c8bd SL |
3588 | struct intel_watermark_params { |
3589 | unsigned long fifo_size; | |
3590 | unsigned long max_wm; | |
3591 | unsigned long default_wm; | |
3592 | unsigned long guard_size; | |
3593 | unsigned long cacheline_size; | |
3594 | }; | |
3595 | ||
f2b115e6 | 3596 | /* Pineview has different values for various configs */ |
d210246a | 3597 | static const struct intel_watermark_params pineview_display_wm = { |
f2b115e6 AJ |
3598 | PINEVIEW_DISPLAY_FIFO, |
3599 | PINEVIEW_MAX_WM, | |
3600 | PINEVIEW_DFT_WM, | |
3601 | PINEVIEW_GUARD_WM, | |
3602 | PINEVIEW_FIFO_LINE_SIZE | |
7662c8bd | 3603 | }; |
d210246a | 3604 | static const struct intel_watermark_params pineview_display_hplloff_wm = { |
f2b115e6 AJ |
3605 | PINEVIEW_DISPLAY_FIFO, |
3606 | PINEVIEW_MAX_WM, | |
3607 | PINEVIEW_DFT_HPLLOFF_WM, | |
3608 | PINEVIEW_GUARD_WM, | |
3609 | PINEVIEW_FIFO_LINE_SIZE | |
7662c8bd | 3610 | }; |
d210246a | 3611 | static const struct intel_watermark_params pineview_cursor_wm = { |
f2b115e6 AJ |
3612 | PINEVIEW_CURSOR_FIFO, |
3613 | PINEVIEW_CURSOR_MAX_WM, | |
3614 | PINEVIEW_CURSOR_DFT_WM, | |
3615 | PINEVIEW_CURSOR_GUARD_WM, | |
3616 | PINEVIEW_FIFO_LINE_SIZE, | |
7662c8bd | 3617 | }; |
d210246a | 3618 | static const struct intel_watermark_params pineview_cursor_hplloff_wm = { |
f2b115e6 AJ |
3619 | PINEVIEW_CURSOR_FIFO, |
3620 | PINEVIEW_CURSOR_MAX_WM, | |
3621 | PINEVIEW_CURSOR_DFT_WM, | |
3622 | PINEVIEW_CURSOR_GUARD_WM, | |
3623 | PINEVIEW_FIFO_LINE_SIZE | |
7662c8bd | 3624 | }; |
d210246a | 3625 | static const struct intel_watermark_params g4x_wm_info = { |
0e442c60 JB |
3626 | G4X_FIFO_SIZE, |
3627 | G4X_MAX_WM, | |
3628 | G4X_MAX_WM, | |
3629 | 2, | |
3630 | G4X_FIFO_LINE_SIZE, | |
3631 | }; | |
d210246a | 3632 | static const struct intel_watermark_params g4x_cursor_wm_info = { |
4fe5e611 ZY |
3633 | I965_CURSOR_FIFO, |
3634 | I965_CURSOR_MAX_WM, | |
3635 | I965_CURSOR_DFT_WM, | |
3636 | 2, | |
3637 | G4X_FIFO_LINE_SIZE, | |
3638 | }; | |
d210246a | 3639 | static const struct intel_watermark_params i965_cursor_wm_info = { |
4fe5e611 ZY |
3640 | I965_CURSOR_FIFO, |
3641 | I965_CURSOR_MAX_WM, | |
3642 | I965_CURSOR_DFT_WM, | |
3643 | 2, | |
3644 | I915_FIFO_LINE_SIZE, | |
3645 | }; | |
d210246a | 3646 | static const struct intel_watermark_params i945_wm_info = { |
dff33cfc | 3647 | I945_FIFO_SIZE, |
7662c8bd SL |
3648 | I915_MAX_WM, |
3649 | 1, | |
dff33cfc JB |
3650 | 2, |
3651 | I915_FIFO_LINE_SIZE | |
7662c8bd | 3652 | }; |
d210246a | 3653 | static const struct intel_watermark_params i915_wm_info = { |
dff33cfc | 3654 | I915_FIFO_SIZE, |
7662c8bd SL |
3655 | I915_MAX_WM, |
3656 | 1, | |
dff33cfc | 3657 | 2, |
7662c8bd SL |
3658 | I915_FIFO_LINE_SIZE |
3659 | }; | |
d210246a | 3660 | static const struct intel_watermark_params i855_wm_info = { |
7662c8bd SL |
3661 | I855GM_FIFO_SIZE, |
3662 | I915_MAX_WM, | |
3663 | 1, | |
dff33cfc | 3664 | 2, |
7662c8bd SL |
3665 | I830_FIFO_LINE_SIZE |
3666 | }; | |
d210246a | 3667 | static const struct intel_watermark_params i830_wm_info = { |
7662c8bd SL |
3668 | I830_FIFO_SIZE, |
3669 | I915_MAX_WM, | |
3670 | 1, | |
dff33cfc | 3671 | 2, |
7662c8bd SL |
3672 | I830_FIFO_LINE_SIZE |
3673 | }; | |
3674 | ||
d210246a | 3675 | static const struct intel_watermark_params ironlake_display_wm_info = { |
7f8a8569 ZW |
3676 | ILK_DISPLAY_FIFO, |
3677 | ILK_DISPLAY_MAXWM, | |
3678 | ILK_DISPLAY_DFTWM, | |
3679 | 2, | |
3680 | ILK_FIFO_LINE_SIZE | |
3681 | }; | |
d210246a | 3682 | static const struct intel_watermark_params ironlake_cursor_wm_info = { |
c936f44d ZY |
3683 | ILK_CURSOR_FIFO, |
3684 | ILK_CURSOR_MAXWM, | |
3685 | ILK_CURSOR_DFTWM, | |
3686 | 2, | |
3687 | ILK_FIFO_LINE_SIZE | |
3688 | }; | |
d210246a | 3689 | static const struct intel_watermark_params ironlake_display_srwm_info = { |
7f8a8569 ZW |
3690 | ILK_DISPLAY_SR_FIFO, |
3691 | ILK_DISPLAY_MAX_SRWM, | |
3692 | ILK_DISPLAY_DFT_SRWM, | |
3693 | 2, | |
3694 | ILK_FIFO_LINE_SIZE | |
3695 | }; | |
d210246a | 3696 | static const struct intel_watermark_params ironlake_cursor_srwm_info = { |
7f8a8569 ZW |
3697 | ILK_CURSOR_SR_FIFO, |
3698 | ILK_CURSOR_MAX_SRWM, | |
3699 | ILK_CURSOR_DFT_SRWM, | |
3700 | 2, | |
3701 | ILK_FIFO_LINE_SIZE | |
3702 | }; | |
3703 | ||
d210246a | 3704 | static const struct intel_watermark_params sandybridge_display_wm_info = { |
1398261a YL |
3705 | SNB_DISPLAY_FIFO, |
3706 | SNB_DISPLAY_MAXWM, | |
3707 | SNB_DISPLAY_DFTWM, | |
3708 | 2, | |
3709 | SNB_FIFO_LINE_SIZE | |
3710 | }; | |
d210246a | 3711 | static const struct intel_watermark_params sandybridge_cursor_wm_info = { |
1398261a YL |
3712 | SNB_CURSOR_FIFO, |
3713 | SNB_CURSOR_MAXWM, | |
3714 | SNB_CURSOR_DFTWM, | |
3715 | 2, | |
3716 | SNB_FIFO_LINE_SIZE | |
3717 | }; | |
d210246a | 3718 | static const struct intel_watermark_params sandybridge_display_srwm_info = { |
1398261a YL |
3719 | SNB_DISPLAY_SR_FIFO, |
3720 | SNB_DISPLAY_MAX_SRWM, | |
3721 | SNB_DISPLAY_DFT_SRWM, | |
3722 | 2, | |
3723 | SNB_FIFO_LINE_SIZE | |
3724 | }; | |
d210246a | 3725 | static const struct intel_watermark_params sandybridge_cursor_srwm_info = { |
1398261a YL |
3726 | SNB_CURSOR_SR_FIFO, |
3727 | SNB_CURSOR_MAX_SRWM, | |
3728 | SNB_CURSOR_DFT_SRWM, | |
3729 | 2, | |
3730 | SNB_FIFO_LINE_SIZE | |
3731 | }; | |
3732 | ||
3733 | ||
dff33cfc JB |
3734 | /** |
3735 | * intel_calculate_wm - calculate watermark level | |
3736 | * @clock_in_khz: pixel clock | |
3737 | * @wm: chip FIFO params | |
3738 | * @pixel_size: display pixel size | |
3739 | * @latency_ns: memory latency for the platform | |
3740 | * | |
3741 | * Calculate the watermark level (the level at which the display plane will | |
3742 | * start fetching from memory again). Each chip has a different display | |
3743 | * FIFO size and allocation, so the caller needs to figure that out and pass | |
3744 | * in the correct intel_watermark_params structure. | |
3745 | * | |
3746 | * As the pixel clock runs, the FIFO will be drained at a rate that depends | |
3747 | * on the pixel size. When it reaches the watermark level, it'll start | |
3748 | * fetching FIFO line sized based chunks from memory until the FIFO fills | |
3749 | * past the watermark point. If the FIFO drains completely, a FIFO underrun | |
3750 | * will occur, and a display engine hang could result. | |
3751 | */ | |
7662c8bd | 3752 | static unsigned long intel_calculate_wm(unsigned long clock_in_khz, |
d210246a CW |
3753 | const struct intel_watermark_params *wm, |
3754 | int fifo_size, | |
7662c8bd SL |
3755 | int pixel_size, |
3756 | unsigned long latency_ns) | |
3757 | { | |
390c4dd4 | 3758 | long entries_required, wm_size; |
dff33cfc | 3759 | |
d660467c JB |
3760 | /* |
3761 | * Note: we need to make sure we don't overflow for various clock & | |
3762 | * latency values. | |
3763 | * clocks go from a few thousand to several hundred thousand. | |
3764 | * latency is usually a few thousand | |
3765 | */ | |
3766 | entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / | |
3767 | 1000; | |
8de9b311 | 3768 | entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); |
7662c8bd | 3769 | |
bbb0aef5 | 3770 | DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required); |
dff33cfc | 3771 | |
d210246a | 3772 | wm_size = fifo_size - (entries_required + wm->guard_size); |
dff33cfc | 3773 | |
bbb0aef5 | 3774 | DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size); |
7662c8bd | 3775 | |
390c4dd4 JB |
3776 | /* Don't promote wm_size to unsigned... */ |
3777 | if (wm_size > (long)wm->max_wm) | |
7662c8bd | 3778 | wm_size = wm->max_wm; |
c3add4b6 | 3779 | if (wm_size <= 0) |
7662c8bd SL |
3780 | wm_size = wm->default_wm; |
3781 | return wm_size; | |
3782 | } | |
3783 | ||
3784 | struct cxsr_latency { | |
3785 | int is_desktop; | |
95534263 | 3786 | int is_ddr3; |
7662c8bd SL |
3787 | unsigned long fsb_freq; |
3788 | unsigned long mem_freq; | |
3789 | unsigned long display_sr; | |
3790 | unsigned long display_hpll_disable; | |
3791 | unsigned long cursor_sr; | |
3792 | unsigned long cursor_hpll_disable; | |
3793 | }; | |
3794 | ||
403c89ff | 3795 | static const struct cxsr_latency cxsr_latency_table[] = { |
95534263 LP |
3796 | {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ |
3797 | {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ | |
3798 | {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ | |
3799 | {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ | |
3800 | {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ | |
3801 | ||
3802 | {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ | |
3803 | {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ | |
3804 | {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ | |
3805 | {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ | |
3806 | {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ | |
3807 | ||
3808 | {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ | |
3809 | {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ | |
3810 | {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ | |
3811 | {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ | |
3812 | {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ | |
3813 | ||
3814 | {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ | |
3815 | {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ | |
3816 | {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ | |
3817 | {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ | |
3818 | {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ | |
3819 | ||
3820 | {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ | |
3821 | {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ | |
3822 | {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ | |
3823 | {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ | |
3824 | {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ | |
3825 | ||
3826 | {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ | |
3827 | {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ | |
3828 | {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ | |
3829 | {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ | |
3830 | {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ | |
7662c8bd SL |
3831 | }; |
3832 | ||
403c89ff CW |
3833 | static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, |
3834 | int is_ddr3, | |
3835 | int fsb, | |
3836 | int mem) | |
7662c8bd | 3837 | { |
403c89ff | 3838 | const struct cxsr_latency *latency; |
7662c8bd | 3839 | int i; |
7662c8bd SL |
3840 | |
3841 | if (fsb == 0 || mem == 0) | |
3842 | return NULL; | |
3843 | ||
3844 | for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { | |
3845 | latency = &cxsr_latency_table[i]; | |
3846 | if (is_desktop == latency->is_desktop && | |
95534263 | 3847 | is_ddr3 == latency->is_ddr3 && |
decbbcda JSR |
3848 | fsb == latency->fsb_freq && mem == latency->mem_freq) |
3849 | return latency; | |
7662c8bd | 3850 | } |
decbbcda | 3851 | |
28c97730 | 3852 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); |
decbbcda JSR |
3853 | |
3854 | return NULL; | |
7662c8bd SL |
3855 | } |
3856 | ||
f2b115e6 | 3857 | static void pineview_disable_cxsr(struct drm_device *dev) |
7662c8bd SL |
3858 | { |
3859 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7662c8bd SL |
3860 | |
3861 | /* deactivate cxsr */ | |
3e33d94d | 3862 | I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN); |
7662c8bd SL |
3863 | } |
3864 | ||
bcc24fb4 JB |
3865 | /* |
3866 | * Latency for FIFO fetches is dependent on several factors: | |
3867 | * - memory configuration (speed, channels) | |
3868 | * - chipset | |
3869 | * - current MCH state | |
3870 | * It can be fairly high in some situations, so here we assume a fairly | |
3871 | * pessimal value. It's a tradeoff between extra memory fetches (if we | |
3872 | * set this value too high, the FIFO will fetch frequently to stay full) | |
3873 | * and power consumption (set it too low to save power and we might see | |
3874 | * FIFO underruns and display "flicker"). | |
3875 | * | |
3876 | * A value of 5us seems to be a good balance; safe for very low end | |
3877 | * platforms but not overly aggressive on lower latency configs. | |
3878 | */ | |
69e302a9 | 3879 | static const int latency_ns = 5000; |
7662c8bd | 3880 | |
e70236a8 | 3881 | static int i9xx_get_fifo_size(struct drm_device *dev, int plane) |
dff33cfc JB |
3882 | { |
3883 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3884 | uint32_t dsparb = I915_READ(DSPARB); | |
3885 | int size; | |
3886 | ||
8de9b311 CW |
3887 | size = dsparb & 0x7f; |
3888 | if (plane) | |
3889 | size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; | |
dff33cfc | 3890 | |
28c97730 | 3891 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
5eddb70b | 3892 | plane ? "B" : "A", size); |
dff33cfc JB |
3893 | |
3894 | return size; | |
3895 | } | |
7662c8bd | 3896 | |
e70236a8 JB |
3897 | static int i85x_get_fifo_size(struct drm_device *dev, int plane) |
3898 | { | |
3899 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3900 | uint32_t dsparb = I915_READ(DSPARB); | |
3901 | int size; | |
3902 | ||
8de9b311 CW |
3903 | size = dsparb & 0x1ff; |
3904 | if (plane) | |
3905 | size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; | |
e70236a8 | 3906 | size >>= 1; /* Convert to cachelines */ |
dff33cfc | 3907 | |
28c97730 | 3908 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
5eddb70b | 3909 | plane ? "B" : "A", size); |
dff33cfc JB |
3910 | |
3911 | return size; | |
3912 | } | |
7662c8bd | 3913 | |
e70236a8 JB |
3914 | static int i845_get_fifo_size(struct drm_device *dev, int plane) |
3915 | { | |
3916 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3917 | uint32_t dsparb = I915_READ(DSPARB); | |
3918 | int size; | |
3919 | ||
3920 | size = dsparb & 0x7f; | |
3921 | size >>= 2; /* Convert to cachelines */ | |
3922 | ||
28c97730 | 3923 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
5eddb70b CW |
3924 | plane ? "B" : "A", |
3925 | size); | |
e70236a8 JB |
3926 | |
3927 | return size; | |
3928 | } | |
3929 | ||
3930 | static int i830_get_fifo_size(struct drm_device *dev, int plane) | |
3931 | { | |
3932 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3933 | uint32_t dsparb = I915_READ(DSPARB); | |
3934 | int size; | |
3935 | ||
3936 | size = dsparb & 0x7f; | |
3937 | size >>= 1; /* Convert to cachelines */ | |
3938 | ||
28c97730 | 3939 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
5eddb70b | 3940 | plane ? "B" : "A", size); |
e70236a8 JB |
3941 | |
3942 | return size; | |
3943 | } | |
3944 | ||
d210246a CW |
3945 | static struct drm_crtc *single_enabled_crtc(struct drm_device *dev) |
3946 | { | |
3947 | struct drm_crtc *crtc, *enabled = NULL; | |
3948 | ||
3949 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
3950 | if (crtc->enabled && crtc->fb) { | |
3951 | if (enabled) | |
3952 | return NULL; | |
3953 | enabled = crtc; | |
3954 | } | |
3955 | } | |
3956 | ||
3957 | return enabled; | |
3958 | } | |
3959 | ||
3960 | static void pineview_update_wm(struct drm_device *dev) | |
d4294342 ZY |
3961 | { |
3962 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d210246a | 3963 | struct drm_crtc *crtc; |
403c89ff | 3964 | const struct cxsr_latency *latency; |
d4294342 ZY |
3965 | u32 reg; |
3966 | unsigned long wm; | |
d4294342 | 3967 | |
403c89ff | 3968 | latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, |
95534263 | 3969 | dev_priv->fsb_freq, dev_priv->mem_freq); |
d4294342 ZY |
3970 | if (!latency) { |
3971 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); | |
3972 | pineview_disable_cxsr(dev); | |
3973 | return; | |
3974 | } | |
3975 | ||
d210246a CW |
3976 | crtc = single_enabled_crtc(dev); |
3977 | if (crtc) { | |
3978 | int clock = crtc->mode.clock; | |
3979 | int pixel_size = crtc->fb->bits_per_pixel / 8; | |
d4294342 ZY |
3980 | |
3981 | /* Display SR */ | |
d210246a CW |
3982 | wm = intel_calculate_wm(clock, &pineview_display_wm, |
3983 | pineview_display_wm.fifo_size, | |
d4294342 ZY |
3984 | pixel_size, latency->display_sr); |
3985 | reg = I915_READ(DSPFW1); | |
3986 | reg &= ~DSPFW_SR_MASK; | |
3987 | reg |= wm << DSPFW_SR_SHIFT; | |
3988 | I915_WRITE(DSPFW1, reg); | |
3989 | DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); | |
3990 | ||
3991 | /* cursor SR */ | |
d210246a CW |
3992 | wm = intel_calculate_wm(clock, &pineview_cursor_wm, |
3993 | pineview_display_wm.fifo_size, | |
d4294342 ZY |
3994 | pixel_size, latency->cursor_sr); |
3995 | reg = I915_READ(DSPFW3); | |
3996 | reg &= ~DSPFW_CURSOR_SR_MASK; | |
3997 | reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT; | |
3998 | I915_WRITE(DSPFW3, reg); | |
3999 | ||
4000 | /* Display HPLL off SR */ | |
d210246a CW |
4001 | wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, |
4002 | pineview_display_hplloff_wm.fifo_size, | |
d4294342 ZY |
4003 | pixel_size, latency->display_hpll_disable); |
4004 | reg = I915_READ(DSPFW3); | |
4005 | reg &= ~DSPFW_HPLL_SR_MASK; | |
4006 | reg |= wm & DSPFW_HPLL_SR_MASK; | |
4007 | I915_WRITE(DSPFW3, reg); | |
4008 | ||
4009 | /* cursor HPLL off SR */ | |
d210246a CW |
4010 | wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, |
4011 | pineview_display_hplloff_wm.fifo_size, | |
d4294342 ZY |
4012 | pixel_size, latency->cursor_hpll_disable); |
4013 | reg = I915_READ(DSPFW3); | |
4014 | reg &= ~DSPFW_HPLL_CURSOR_MASK; | |
4015 | reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT; | |
4016 | I915_WRITE(DSPFW3, reg); | |
4017 | DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); | |
4018 | ||
4019 | /* activate cxsr */ | |
3e33d94d CW |
4020 | I915_WRITE(DSPFW3, |
4021 | I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN); | |
d4294342 ZY |
4022 | DRM_DEBUG_KMS("Self-refresh is enabled\n"); |
4023 | } else { | |
4024 | pineview_disable_cxsr(dev); | |
4025 | DRM_DEBUG_KMS("Self-refresh is disabled\n"); | |
4026 | } | |
4027 | } | |
4028 | ||
417ae147 CW |
4029 | static bool g4x_compute_wm0(struct drm_device *dev, |
4030 | int plane, | |
4031 | const struct intel_watermark_params *display, | |
4032 | int display_latency_ns, | |
4033 | const struct intel_watermark_params *cursor, | |
4034 | int cursor_latency_ns, | |
4035 | int *plane_wm, | |
4036 | int *cursor_wm) | |
4037 | { | |
4038 | struct drm_crtc *crtc; | |
4039 | int htotal, hdisplay, clock, pixel_size; | |
4040 | int line_time_us, line_count; | |
4041 | int entries, tlb_miss; | |
4042 | ||
4043 | crtc = intel_get_crtc_for_plane(dev, plane); | |
5c72d064 CW |
4044 | if (crtc->fb == NULL || !crtc->enabled) { |
4045 | *cursor_wm = cursor->guard_size; | |
4046 | *plane_wm = display->guard_size; | |
417ae147 | 4047 | return false; |
5c72d064 | 4048 | } |
417ae147 CW |
4049 | |
4050 | htotal = crtc->mode.htotal; | |
4051 | hdisplay = crtc->mode.hdisplay; | |
4052 | clock = crtc->mode.clock; | |
4053 | pixel_size = crtc->fb->bits_per_pixel / 8; | |
4054 | ||
4055 | /* Use the small buffer method to calculate plane watermark */ | |
4056 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; | |
4057 | tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; | |
4058 | if (tlb_miss > 0) | |
4059 | entries += tlb_miss; | |
4060 | entries = DIV_ROUND_UP(entries, display->cacheline_size); | |
4061 | *plane_wm = entries + display->guard_size; | |
4062 | if (*plane_wm > (int)display->max_wm) | |
4063 | *plane_wm = display->max_wm; | |
4064 | ||
4065 | /* Use the large buffer method to calculate cursor watermark */ | |
4066 | line_time_us = ((htotal * 1000) / clock); | |
4067 | line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; | |
4068 | entries = line_count * 64 * pixel_size; | |
4069 | tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; | |
4070 | if (tlb_miss > 0) | |
4071 | entries += tlb_miss; | |
4072 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); | |
4073 | *cursor_wm = entries + cursor->guard_size; | |
4074 | if (*cursor_wm > (int)cursor->max_wm) | |
4075 | *cursor_wm = (int)cursor->max_wm; | |
4076 | ||
4077 | return true; | |
4078 | } | |
4079 | ||
4080 | /* | |
4081 | * Check the wm result. | |
4082 | * | |
4083 | * If any calculated watermark values is larger than the maximum value that | |
4084 | * can be programmed into the associated watermark register, that watermark | |
4085 | * must be disabled. | |
4086 | */ | |
4087 | static bool g4x_check_srwm(struct drm_device *dev, | |
4088 | int display_wm, int cursor_wm, | |
4089 | const struct intel_watermark_params *display, | |
4090 | const struct intel_watermark_params *cursor) | |
652c393a | 4091 | { |
417ae147 CW |
4092 | DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n", |
4093 | display_wm, cursor_wm); | |
652c393a | 4094 | |
417ae147 | 4095 | if (display_wm > display->max_wm) { |
bbb0aef5 | 4096 | DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n", |
417ae147 CW |
4097 | display_wm, display->max_wm); |
4098 | return false; | |
4099 | } | |
0e442c60 | 4100 | |
417ae147 | 4101 | if (cursor_wm > cursor->max_wm) { |
bbb0aef5 | 4102 | DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n", |
417ae147 CW |
4103 | cursor_wm, cursor->max_wm); |
4104 | return false; | |
4105 | } | |
0e442c60 | 4106 | |
417ae147 CW |
4107 | if (!(display_wm || cursor_wm)) { |
4108 | DRM_DEBUG_KMS("SR latency is 0, disabling\n"); | |
4109 | return false; | |
4110 | } | |
0e442c60 | 4111 | |
417ae147 CW |
4112 | return true; |
4113 | } | |
0e442c60 | 4114 | |
417ae147 | 4115 | static bool g4x_compute_srwm(struct drm_device *dev, |
d210246a CW |
4116 | int plane, |
4117 | int latency_ns, | |
417ae147 CW |
4118 | const struct intel_watermark_params *display, |
4119 | const struct intel_watermark_params *cursor, | |
4120 | int *display_wm, int *cursor_wm) | |
4121 | { | |
d210246a CW |
4122 | struct drm_crtc *crtc; |
4123 | int hdisplay, htotal, pixel_size, clock; | |
417ae147 CW |
4124 | unsigned long line_time_us; |
4125 | int line_count, line_size; | |
4126 | int small, large; | |
4127 | int entries; | |
0e442c60 | 4128 | |
417ae147 CW |
4129 | if (!latency_ns) { |
4130 | *display_wm = *cursor_wm = 0; | |
4131 | return false; | |
4132 | } | |
0e442c60 | 4133 | |
d210246a CW |
4134 | crtc = intel_get_crtc_for_plane(dev, plane); |
4135 | hdisplay = crtc->mode.hdisplay; | |
4136 | htotal = crtc->mode.htotal; | |
4137 | clock = crtc->mode.clock; | |
4138 | pixel_size = crtc->fb->bits_per_pixel / 8; | |
4139 | ||
417ae147 CW |
4140 | line_time_us = (htotal * 1000) / clock; |
4141 | line_count = (latency_ns / line_time_us + 1000) / 1000; | |
4142 | line_size = hdisplay * pixel_size; | |
0e442c60 | 4143 | |
417ae147 CW |
4144 | /* Use the minimum of the small and large buffer method for primary */ |
4145 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; | |
4146 | large = line_count * line_size; | |
0e442c60 | 4147 | |
417ae147 CW |
4148 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); |
4149 | *display_wm = entries + display->guard_size; | |
4fe5e611 | 4150 | |
417ae147 CW |
4151 | /* calculate the self-refresh watermark for display cursor */ |
4152 | entries = line_count * pixel_size * 64; | |
4153 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); | |
4154 | *cursor_wm = entries + cursor->guard_size; | |
4fe5e611 | 4155 | |
417ae147 CW |
4156 | return g4x_check_srwm(dev, |
4157 | *display_wm, *cursor_wm, | |
4158 | display, cursor); | |
4159 | } | |
4fe5e611 | 4160 | |
7ccb4a53 | 4161 | #define single_plane_enabled(mask) is_power_of_2(mask) |
d210246a CW |
4162 | |
4163 | static void g4x_update_wm(struct drm_device *dev) | |
417ae147 CW |
4164 | { |
4165 | static const int sr_latency_ns = 12000; | |
4166 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4167 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; | |
d210246a CW |
4168 | int plane_sr, cursor_sr; |
4169 | unsigned int enabled = 0; | |
417ae147 CW |
4170 | |
4171 | if (g4x_compute_wm0(dev, 0, | |
4172 | &g4x_wm_info, latency_ns, | |
4173 | &g4x_cursor_wm_info, latency_ns, | |
4174 | &planea_wm, &cursora_wm)) | |
d210246a | 4175 | enabled |= 1; |
417ae147 CW |
4176 | |
4177 | if (g4x_compute_wm0(dev, 1, | |
4178 | &g4x_wm_info, latency_ns, | |
4179 | &g4x_cursor_wm_info, latency_ns, | |
4180 | &planeb_wm, &cursorb_wm)) | |
d210246a | 4181 | enabled |= 2; |
417ae147 CW |
4182 | |
4183 | plane_sr = cursor_sr = 0; | |
d210246a CW |
4184 | if (single_plane_enabled(enabled) && |
4185 | g4x_compute_srwm(dev, ffs(enabled) - 1, | |
4186 | sr_latency_ns, | |
417ae147 CW |
4187 | &g4x_wm_info, |
4188 | &g4x_cursor_wm_info, | |
4189 | &plane_sr, &cursor_sr)) | |
0e442c60 | 4190 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
417ae147 CW |
4191 | else |
4192 | I915_WRITE(FW_BLC_SELF, | |
4193 | I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN); | |
0e442c60 | 4194 | |
308977ac CW |
4195 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", |
4196 | planea_wm, cursora_wm, | |
4197 | planeb_wm, cursorb_wm, | |
4198 | plane_sr, cursor_sr); | |
0e442c60 | 4199 | |
417ae147 CW |
4200 | I915_WRITE(DSPFW1, |
4201 | (plane_sr << DSPFW_SR_SHIFT) | | |
0e442c60 | 4202 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | |
417ae147 CW |
4203 | (planeb_wm << DSPFW_PLANEB_SHIFT) | |
4204 | planea_wm); | |
4205 | I915_WRITE(DSPFW2, | |
4206 | (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) | | |
0e442c60 JB |
4207 | (cursora_wm << DSPFW_CURSORA_SHIFT)); |
4208 | /* HPLL off in SR has some issues on G4x... disable it */ | |
417ae147 CW |
4209 | I915_WRITE(DSPFW3, |
4210 | (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) | | |
0e442c60 | 4211 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); |
652c393a JB |
4212 | } |
4213 | ||
d210246a | 4214 | static void i965_update_wm(struct drm_device *dev) |
7662c8bd SL |
4215 | { |
4216 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d210246a CW |
4217 | struct drm_crtc *crtc; |
4218 | int srwm = 1; | |
4fe5e611 | 4219 | int cursor_sr = 16; |
1dc7546d JB |
4220 | |
4221 | /* Calc sr entries for one plane configs */ | |
d210246a CW |
4222 | crtc = single_enabled_crtc(dev); |
4223 | if (crtc) { | |
1dc7546d | 4224 | /* self-refresh has much higher latency */ |
69e302a9 | 4225 | static const int sr_latency_ns = 12000; |
d210246a CW |
4226 | int clock = crtc->mode.clock; |
4227 | int htotal = crtc->mode.htotal; | |
4228 | int hdisplay = crtc->mode.hdisplay; | |
4229 | int pixel_size = crtc->fb->bits_per_pixel / 8; | |
4230 | unsigned long line_time_us; | |
4231 | int entries; | |
1dc7546d | 4232 | |
d210246a | 4233 | line_time_us = ((htotal * 1000) / clock); |
1dc7546d JB |
4234 | |
4235 | /* Use ns/us then divide to preserve precision */ | |
d210246a CW |
4236 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
4237 | pixel_size * hdisplay; | |
4238 | entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); | |
d210246a | 4239 | srwm = I965_FIFO_SIZE - entries; |
1dc7546d JB |
4240 | if (srwm < 0) |
4241 | srwm = 1; | |
1b07e04e | 4242 | srwm &= 0x1ff; |
308977ac CW |
4243 | DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", |
4244 | entries, srwm); | |
4fe5e611 | 4245 | |
d210246a | 4246 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
5eddb70b | 4247 | pixel_size * 64; |
d210246a | 4248 | entries = DIV_ROUND_UP(entries, |
8de9b311 | 4249 | i965_cursor_wm_info.cacheline_size); |
4fe5e611 | 4250 | cursor_sr = i965_cursor_wm_info.fifo_size - |
d210246a | 4251 | (entries + i965_cursor_wm_info.guard_size); |
4fe5e611 ZY |
4252 | |
4253 | if (cursor_sr > i965_cursor_wm_info.max_wm) | |
4254 | cursor_sr = i965_cursor_wm_info.max_wm; | |
4255 | ||
4256 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " | |
4257 | "cursor %d\n", srwm, cursor_sr); | |
4258 | ||
a6c45cf0 | 4259 | if (IS_CRESTLINE(dev)) |
adcdbc66 | 4260 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
33c5fd12 DJ |
4261 | } else { |
4262 | /* Turn off self refresh if both pipes are enabled */ | |
a6c45cf0 | 4263 | if (IS_CRESTLINE(dev)) |
adcdbc66 JB |
4264 | I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) |
4265 | & ~FW_BLC_SELF_EN); | |
1dc7546d | 4266 | } |
7662c8bd | 4267 | |
1dc7546d JB |
4268 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", |
4269 | srwm); | |
7662c8bd SL |
4270 | |
4271 | /* 965 has limitations... */ | |
417ae147 CW |
4272 | I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | |
4273 | (8 << 16) | (8 << 8) | (8 << 0)); | |
7662c8bd | 4274 | I915_WRITE(DSPFW2, (8 << 8) | (8 << 0)); |
4fe5e611 ZY |
4275 | /* update cursor SR watermark */ |
4276 | I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); | |
7662c8bd SL |
4277 | } |
4278 | ||
d210246a | 4279 | static void i9xx_update_wm(struct drm_device *dev) |
7662c8bd SL |
4280 | { |
4281 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d210246a | 4282 | const struct intel_watermark_params *wm_info; |
dff33cfc JB |
4283 | uint32_t fwater_lo; |
4284 | uint32_t fwater_hi; | |
d210246a CW |
4285 | int cwm, srwm = 1; |
4286 | int fifo_size; | |
dff33cfc | 4287 | int planea_wm, planeb_wm; |
d210246a | 4288 | struct drm_crtc *crtc, *enabled = NULL; |
7662c8bd | 4289 | |
72557b4f | 4290 | if (IS_I945GM(dev)) |
d210246a | 4291 | wm_info = &i945_wm_info; |
a6c45cf0 | 4292 | else if (!IS_GEN2(dev)) |
d210246a | 4293 | wm_info = &i915_wm_info; |
7662c8bd | 4294 | else |
d210246a CW |
4295 | wm_info = &i855_wm_info; |
4296 | ||
4297 | fifo_size = dev_priv->display.get_fifo_size(dev, 0); | |
4298 | crtc = intel_get_crtc_for_plane(dev, 0); | |
4299 | if (crtc->enabled && crtc->fb) { | |
4300 | planea_wm = intel_calculate_wm(crtc->mode.clock, | |
4301 | wm_info, fifo_size, | |
4302 | crtc->fb->bits_per_pixel / 8, | |
4303 | latency_ns); | |
4304 | enabled = crtc; | |
4305 | } else | |
4306 | planea_wm = fifo_size - wm_info->guard_size; | |
4307 | ||
4308 | fifo_size = dev_priv->display.get_fifo_size(dev, 1); | |
4309 | crtc = intel_get_crtc_for_plane(dev, 1); | |
4310 | if (crtc->enabled && crtc->fb) { | |
4311 | planeb_wm = intel_calculate_wm(crtc->mode.clock, | |
4312 | wm_info, fifo_size, | |
4313 | crtc->fb->bits_per_pixel / 8, | |
4314 | latency_ns); | |
4315 | if (enabled == NULL) | |
4316 | enabled = crtc; | |
4317 | else | |
4318 | enabled = NULL; | |
4319 | } else | |
4320 | planeb_wm = fifo_size - wm_info->guard_size; | |
7662c8bd | 4321 | |
28c97730 | 4322 | DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); |
7662c8bd SL |
4323 | |
4324 | /* | |
4325 | * Overlay gets an aggressive default since video jitter is bad. | |
4326 | */ | |
4327 | cwm = 2; | |
4328 | ||
18b2190c AL |
4329 | /* Play safe and disable self-refresh before adjusting watermarks. */ |
4330 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
4331 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0); | |
4332 | else if (IS_I915GM(dev)) | |
4333 | I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN); | |
4334 | ||
dff33cfc | 4335 | /* Calc sr entries for one plane configs */ |
d210246a | 4336 | if (HAS_FW_BLC(dev) && enabled) { |
dff33cfc | 4337 | /* self-refresh has much higher latency */ |
69e302a9 | 4338 | static const int sr_latency_ns = 6000; |
d210246a CW |
4339 | int clock = enabled->mode.clock; |
4340 | int htotal = enabled->mode.htotal; | |
4341 | int hdisplay = enabled->mode.hdisplay; | |
4342 | int pixel_size = enabled->fb->bits_per_pixel / 8; | |
4343 | unsigned long line_time_us; | |
4344 | int entries; | |
dff33cfc | 4345 | |
d210246a | 4346 | line_time_us = (htotal * 1000) / clock; |
dff33cfc JB |
4347 | |
4348 | /* Use ns/us then divide to preserve precision */ | |
d210246a CW |
4349 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
4350 | pixel_size * hdisplay; | |
4351 | entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); | |
4352 | DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); | |
4353 | srwm = wm_info->fifo_size - entries; | |
dff33cfc JB |
4354 | if (srwm < 0) |
4355 | srwm = 1; | |
ee980b80 LP |
4356 | |
4357 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
18b2190c AL |
4358 | I915_WRITE(FW_BLC_SELF, |
4359 | FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); | |
4360 | else if (IS_I915GM(dev)) | |
ee980b80 | 4361 | I915_WRITE(FW_BLC_SELF, srwm & 0x3f); |
7662c8bd SL |
4362 | } |
4363 | ||
28c97730 | 4364 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", |
5eddb70b | 4365 | planea_wm, planeb_wm, cwm, srwm); |
7662c8bd | 4366 | |
dff33cfc JB |
4367 | fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); |
4368 | fwater_hi = (cwm & 0x1f); | |
4369 | ||
4370 | /* Set request length to 8 cachelines per fetch */ | |
4371 | fwater_lo = fwater_lo | (1 << 24) | (1 << 8); | |
4372 | fwater_hi = fwater_hi | (1 << 8); | |
7662c8bd SL |
4373 | |
4374 | I915_WRITE(FW_BLC, fwater_lo); | |
4375 | I915_WRITE(FW_BLC2, fwater_hi); | |
18b2190c | 4376 | |
d210246a CW |
4377 | if (HAS_FW_BLC(dev)) { |
4378 | if (enabled) { | |
4379 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
4380 | I915_WRITE(FW_BLC_SELF, | |
4381 | FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN); | |
4382 | else if (IS_I915GM(dev)) | |
4383 | I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN); | |
4384 | DRM_DEBUG_KMS("memory self refresh enabled\n"); | |
4385 | } else | |
4386 | DRM_DEBUG_KMS("memory self refresh disabled\n"); | |
4387 | } | |
7662c8bd SL |
4388 | } |
4389 | ||
d210246a | 4390 | static void i830_update_wm(struct drm_device *dev) |
7662c8bd SL |
4391 | { |
4392 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d210246a CW |
4393 | struct drm_crtc *crtc; |
4394 | uint32_t fwater_lo; | |
dff33cfc | 4395 | int planea_wm; |
7662c8bd | 4396 | |
d210246a CW |
4397 | crtc = single_enabled_crtc(dev); |
4398 | if (crtc == NULL) | |
4399 | return; | |
7662c8bd | 4400 | |
d210246a CW |
4401 | planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info, |
4402 | dev_priv->display.get_fifo_size(dev, 0), | |
4403 | crtc->fb->bits_per_pixel / 8, | |
4404 | latency_ns); | |
4405 | fwater_lo = I915_READ(FW_BLC) & ~0xfff; | |
f3601326 JB |
4406 | fwater_lo |= (3<<8) | planea_wm; |
4407 | ||
28c97730 | 4408 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); |
7662c8bd SL |
4409 | |
4410 | I915_WRITE(FW_BLC, fwater_lo); | |
4411 | } | |
4412 | ||
7f8a8569 | 4413 | #define ILK_LP0_PLANE_LATENCY 700 |
c936f44d | 4414 | #define ILK_LP0_CURSOR_LATENCY 1300 |
7f8a8569 | 4415 | |
1398261a YL |
4416 | /* |
4417 | * Check the wm result. | |
4418 | * | |
4419 | * If any calculated watermark values is larger than the maximum value that | |
4420 | * can be programmed into the associated watermark register, that watermark | |
4421 | * must be disabled. | |
1398261a | 4422 | */ |
b79d4990 JB |
4423 | static bool ironlake_check_srwm(struct drm_device *dev, int level, |
4424 | int fbc_wm, int display_wm, int cursor_wm, | |
4425 | const struct intel_watermark_params *display, | |
4426 | const struct intel_watermark_params *cursor) | |
1398261a YL |
4427 | { |
4428 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4429 | ||
4430 | DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d," | |
4431 | " cursor %d\n", level, display_wm, fbc_wm, cursor_wm); | |
4432 | ||
4433 | if (fbc_wm > SNB_FBC_MAX_SRWM) { | |
4434 | DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n", | |
b79d4990 | 4435 | fbc_wm, SNB_FBC_MAX_SRWM, level); |
1398261a YL |
4436 | |
4437 | /* fbc has it's own way to disable FBC WM */ | |
4438 | I915_WRITE(DISP_ARB_CTL, | |
4439 | I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS); | |
4440 | return false; | |
4441 | } | |
4442 | ||
b79d4990 | 4443 | if (display_wm > display->max_wm) { |
1398261a | 4444 | DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n", |
b79d4990 | 4445 | display_wm, SNB_DISPLAY_MAX_SRWM, level); |
1398261a YL |
4446 | return false; |
4447 | } | |
4448 | ||
b79d4990 | 4449 | if (cursor_wm > cursor->max_wm) { |
1398261a | 4450 | DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n", |
b79d4990 | 4451 | cursor_wm, SNB_CURSOR_MAX_SRWM, level); |
1398261a YL |
4452 | return false; |
4453 | } | |
4454 | ||
4455 | if (!(fbc_wm || display_wm || cursor_wm)) { | |
4456 | DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level); | |
4457 | return false; | |
4458 | } | |
4459 | ||
4460 | return true; | |
4461 | } | |
4462 | ||
4463 | /* | |
4464 | * Compute watermark values of WM[1-3], | |
4465 | */ | |
d210246a CW |
4466 | static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane, |
4467 | int latency_ns, | |
b79d4990 JB |
4468 | const struct intel_watermark_params *display, |
4469 | const struct intel_watermark_params *cursor, | |
4470 | int *fbc_wm, int *display_wm, int *cursor_wm) | |
1398261a | 4471 | { |
d210246a | 4472 | struct drm_crtc *crtc; |
1398261a | 4473 | unsigned long line_time_us; |
d210246a | 4474 | int hdisplay, htotal, pixel_size, clock; |
b79d4990 | 4475 | int line_count, line_size; |
1398261a YL |
4476 | int small, large; |
4477 | int entries; | |
1398261a YL |
4478 | |
4479 | if (!latency_ns) { | |
4480 | *fbc_wm = *display_wm = *cursor_wm = 0; | |
4481 | return false; | |
4482 | } | |
4483 | ||
d210246a CW |
4484 | crtc = intel_get_crtc_for_plane(dev, plane); |
4485 | hdisplay = crtc->mode.hdisplay; | |
4486 | htotal = crtc->mode.htotal; | |
4487 | clock = crtc->mode.clock; | |
4488 | pixel_size = crtc->fb->bits_per_pixel / 8; | |
4489 | ||
1398261a YL |
4490 | line_time_us = (htotal * 1000) / clock; |
4491 | line_count = (latency_ns / line_time_us + 1000) / 1000; | |
4492 | line_size = hdisplay * pixel_size; | |
4493 | ||
4494 | /* Use the minimum of the small and large buffer method for primary */ | |
4495 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; | |
4496 | large = line_count * line_size; | |
4497 | ||
b79d4990 JB |
4498 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); |
4499 | *display_wm = entries + display->guard_size; | |
1398261a YL |
4500 | |
4501 | /* | |
b79d4990 | 4502 | * Spec says: |
1398261a YL |
4503 | * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2 |
4504 | */ | |
4505 | *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2; | |
4506 | ||
4507 | /* calculate the self-refresh watermark for display cursor */ | |
4508 | entries = line_count * pixel_size * 64; | |
b79d4990 JB |
4509 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
4510 | *cursor_wm = entries + cursor->guard_size; | |
1398261a | 4511 | |
b79d4990 JB |
4512 | return ironlake_check_srwm(dev, level, |
4513 | *fbc_wm, *display_wm, *cursor_wm, | |
4514 | display, cursor); | |
4515 | } | |
4516 | ||
d210246a | 4517 | static void ironlake_update_wm(struct drm_device *dev) |
b79d4990 JB |
4518 | { |
4519 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d210246a CW |
4520 | int fbc_wm, plane_wm, cursor_wm; |
4521 | unsigned int enabled; | |
b79d4990 JB |
4522 | |
4523 | enabled = 0; | |
9f405100 CW |
4524 | if (g4x_compute_wm0(dev, 0, |
4525 | &ironlake_display_wm_info, | |
4526 | ILK_LP0_PLANE_LATENCY, | |
4527 | &ironlake_cursor_wm_info, | |
4528 | ILK_LP0_CURSOR_LATENCY, | |
4529 | &plane_wm, &cursor_wm)) { | |
b79d4990 JB |
4530 | I915_WRITE(WM0_PIPEA_ILK, |
4531 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); | |
4532 | DRM_DEBUG_KMS("FIFO watermarks For pipe A -" | |
4533 | " plane %d, " "cursor: %d\n", | |
4534 | plane_wm, cursor_wm); | |
d210246a | 4535 | enabled |= 1; |
b79d4990 JB |
4536 | } |
4537 | ||
9f405100 CW |
4538 | if (g4x_compute_wm0(dev, 1, |
4539 | &ironlake_display_wm_info, | |
4540 | ILK_LP0_PLANE_LATENCY, | |
4541 | &ironlake_cursor_wm_info, | |
4542 | ILK_LP0_CURSOR_LATENCY, | |
4543 | &plane_wm, &cursor_wm)) { | |
b79d4990 JB |
4544 | I915_WRITE(WM0_PIPEB_ILK, |
4545 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); | |
4546 | DRM_DEBUG_KMS("FIFO watermarks For pipe B -" | |
4547 | " plane %d, cursor: %d\n", | |
4548 | plane_wm, cursor_wm); | |
d210246a | 4549 | enabled |= 2; |
b79d4990 JB |
4550 | } |
4551 | ||
4552 | /* | |
4553 | * Calculate and update the self-refresh watermark only when one | |
4554 | * display plane is used. | |
4555 | */ | |
4556 | I915_WRITE(WM3_LP_ILK, 0); | |
4557 | I915_WRITE(WM2_LP_ILK, 0); | |
4558 | I915_WRITE(WM1_LP_ILK, 0); | |
4559 | ||
d210246a | 4560 | if (!single_plane_enabled(enabled)) |
b79d4990 | 4561 | return; |
d210246a | 4562 | enabled = ffs(enabled) - 1; |
b79d4990 JB |
4563 | |
4564 | /* WM1 */ | |
d210246a CW |
4565 | if (!ironlake_compute_srwm(dev, 1, enabled, |
4566 | ILK_READ_WM1_LATENCY() * 500, | |
b79d4990 JB |
4567 | &ironlake_display_srwm_info, |
4568 | &ironlake_cursor_srwm_info, | |
4569 | &fbc_wm, &plane_wm, &cursor_wm)) | |
4570 | return; | |
4571 | ||
4572 | I915_WRITE(WM1_LP_ILK, | |
4573 | WM1_LP_SR_EN | | |
4574 | (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
4575 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
4576 | (plane_wm << WM1_LP_SR_SHIFT) | | |
4577 | cursor_wm); | |
4578 | ||
4579 | /* WM2 */ | |
d210246a CW |
4580 | if (!ironlake_compute_srwm(dev, 2, enabled, |
4581 | ILK_READ_WM2_LATENCY() * 500, | |
b79d4990 JB |
4582 | &ironlake_display_srwm_info, |
4583 | &ironlake_cursor_srwm_info, | |
4584 | &fbc_wm, &plane_wm, &cursor_wm)) | |
4585 | return; | |
4586 | ||
4587 | I915_WRITE(WM2_LP_ILK, | |
4588 | WM2_LP_EN | | |
4589 | (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
4590 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
4591 | (plane_wm << WM1_LP_SR_SHIFT) | | |
4592 | cursor_wm); | |
4593 | ||
4594 | /* | |
4595 | * WM3 is unsupported on ILK, probably because we don't have latency | |
4596 | * data for that power state | |
4597 | */ | |
1398261a YL |
4598 | } |
4599 | ||
b840d907 | 4600 | void sandybridge_update_wm(struct drm_device *dev) |
1398261a YL |
4601 | { |
4602 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a0fa62d3 | 4603 | int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ |
47842649 | 4604 | u32 val; |
d210246a CW |
4605 | int fbc_wm, plane_wm, cursor_wm; |
4606 | unsigned int enabled; | |
1398261a YL |
4607 | |
4608 | enabled = 0; | |
9f405100 CW |
4609 | if (g4x_compute_wm0(dev, 0, |
4610 | &sandybridge_display_wm_info, latency, | |
4611 | &sandybridge_cursor_wm_info, latency, | |
4612 | &plane_wm, &cursor_wm)) { | |
47842649 JB |
4613 | val = I915_READ(WM0_PIPEA_ILK); |
4614 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); | |
4615 | I915_WRITE(WM0_PIPEA_ILK, val | | |
4616 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); | |
1398261a YL |
4617 | DRM_DEBUG_KMS("FIFO watermarks For pipe A -" |
4618 | " plane %d, " "cursor: %d\n", | |
4619 | plane_wm, cursor_wm); | |
d210246a | 4620 | enabled |= 1; |
1398261a YL |
4621 | } |
4622 | ||
9f405100 CW |
4623 | if (g4x_compute_wm0(dev, 1, |
4624 | &sandybridge_display_wm_info, latency, | |
4625 | &sandybridge_cursor_wm_info, latency, | |
4626 | &plane_wm, &cursor_wm)) { | |
47842649 JB |
4627 | val = I915_READ(WM0_PIPEB_ILK); |
4628 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); | |
4629 | I915_WRITE(WM0_PIPEB_ILK, val | | |
4630 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); | |
1398261a YL |
4631 | DRM_DEBUG_KMS("FIFO watermarks For pipe B -" |
4632 | " plane %d, cursor: %d\n", | |
4633 | plane_wm, cursor_wm); | |
d210246a | 4634 | enabled |= 2; |
1398261a YL |
4635 | } |
4636 | ||
d6c892df JB |
4637 | /* IVB has 3 pipes */ |
4638 | if (IS_IVYBRIDGE(dev) && | |
4639 | g4x_compute_wm0(dev, 2, | |
4640 | &sandybridge_display_wm_info, latency, | |
4641 | &sandybridge_cursor_wm_info, latency, | |
4642 | &plane_wm, &cursor_wm)) { | |
47842649 JB |
4643 | val = I915_READ(WM0_PIPEC_IVB); |
4644 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); | |
4645 | I915_WRITE(WM0_PIPEC_IVB, val | | |
4646 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); | |
d6c892df JB |
4647 | DRM_DEBUG_KMS("FIFO watermarks For pipe C -" |
4648 | " plane %d, cursor: %d\n", | |
4649 | plane_wm, cursor_wm); | |
4650 | enabled |= 3; | |
4651 | } | |
4652 | ||
1398261a YL |
4653 | /* |
4654 | * Calculate and update the self-refresh watermark only when one | |
4655 | * display plane is used. | |
4656 | * | |
4657 | * SNB support 3 levels of watermark. | |
4658 | * | |
4659 | * WM1/WM2/WM2 watermarks have to be enabled in the ascending order, | |
4660 | * and disabled in the descending order | |
4661 | * | |
4662 | */ | |
4663 | I915_WRITE(WM3_LP_ILK, 0); | |
4664 | I915_WRITE(WM2_LP_ILK, 0); | |
4665 | I915_WRITE(WM1_LP_ILK, 0); | |
4666 | ||
b840d907 JB |
4667 | if (!single_plane_enabled(enabled) || |
4668 | dev_priv->sprite_scaling_enabled) | |
1398261a | 4669 | return; |
d210246a | 4670 | enabled = ffs(enabled) - 1; |
1398261a YL |
4671 | |
4672 | /* WM1 */ | |
d210246a CW |
4673 | if (!ironlake_compute_srwm(dev, 1, enabled, |
4674 | SNB_READ_WM1_LATENCY() * 500, | |
b79d4990 JB |
4675 | &sandybridge_display_srwm_info, |
4676 | &sandybridge_cursor_srwm_info, | |
4677 | &fbc_wm, &plane_wm, &cursor_wm)) | |
1398261a YL |
4678 | return; |
4679 | ||
4680 | I915_WRITE(WM1_LP_ILK, | |
4681 | WM1_LP_SR_EN | | |
4682 | (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
4683 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
4684 | (plane_wm << WM1_LP_SR_SHIFT) | | |
4685 | cursor_wm); | |
4686 | ||
4687 | /* WM2 */ | |
d210246a CW |
4688 | if (!ironlake_compute_srwm(dev, 2, enabled, |
4689 | SNB_READ_WM2_LATENCY() * 500, | |
b79d4990 JB |
4690 | &sandybridge_display_srwm_info, |
4691 | &sandybridge_cursor_srwm_info, | |
4692 | &fbc_wm, &plane_wm, &cursor_wm)) | |
1398261a YL |
4693 | return; |
4694 | ||
4695 | I915_WRITE(WM2_LP_ILK, | |
4696 | WM2_LP_EN | | |
4697 | (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
4698 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
4699 | (plane_wm << WM1_LP_SR_SHIFT) | | |
4700 | cursor_wm); | |
4701 | ||
4702 | /* WM3 */ | |
d210246a CW |
4703 | if (!ironlake_compute_srwm(dev, 3, enabled, |
4704 | SNB_READ_WM3_LATENCY() * 500, | |
b79d4990 JB |
4705 | &sandybridge_display_srwm_info, |
4706 | &sandybridge_cursor_srwm_info, | |
4707 | &fbc_wm, &plane_wm, &cursor_wm)) | |
1398261a YL |
4708 | return; |
4709 | ||
4710 | I915_WRITE(WM3_LP_ILK, | |
4711 | WM3_LP_EN | | |
4712 | (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
4713 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
4714 | (plane_wm << WM1_LP_SR_SHIFT) | | |
4715 | cursor_wm); | |
4716 | } | |
4717 | ||
b840d907 JB |
4718 | static bool |
4719 | sandybridge_compute_sprite_wm(struct drm_device *dev, int plane, | |
4720 | uint32_t sprite_width, int pixel_size, | |
4721 | const struct intel_watermark_params *display, | |
4722 | int display_latency_ns, int *sprite_wm) | |
4723 | { | |
4724 | struct drm_crtc *crtc; | |
4725 | int clock; | |
4726 | int entries, tlb_miss; | |
4727 | ||
4728 | crtc = intel_get_crtc_for_plane(dev, plane); | |
4729 | if (crtc->fb == NULL || !crtc->enabled) { | |
4730 | *sprite_wm = display->guard_size; | |
4731 | return false; | |
4732 | } | |
4733 | ||
4734 | clock = crtc->mode.clock; | |
4735 | ||
4736 | /* Use the small buffer method to calculate the sprite watermark */ | |
4737 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; | |
4738 | tlb_miss = display->fifo_size*display->cacheline_size - | |
4739 | sprite_width * 8; | |
4740 | if (tlb_miss > 0) | |
4741 | entries += tlb_miss; | |
4742 | entries = DIV_ROUND_UP(entries, display->cacheline_size); | |
4743 | *sprite_wm = entries + display->guard_size; | |
4744 | if (*sprite_wm > (int)display->max_wm) | |
4745 | *sprite_wm = display->max_wm; | |
4746 | ||
4747 | return true; | |
4748 | } | |
4749 | ||
4750 | static bool | |
4751 | sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane, | |
4752 | uint32_t sprite_width, int pixel_size, | |
4753 | const struct intel_watermark_params *display, | |
4754 | int latency_ns, int *sprite_wm) | |
4755 | { | |
4756 | struct drm_crtc *crtc; | |
4757 | unsigned long line_time_us; | |
4758 | int clock; | |
4759 | int line_count, line_size; | |
4760 | int small, large; | |
4761 | int entries; | |
4762 | ||
4763 | if (!latency_ns) { | |
4764 | *sprite_wm = 0; | |
4765 | return false; | |
4766 | } | |
4767 | ||
4768 | crtc = intel_get_crtc_for_plane(dev, plane); | |
4769 | clock = crtc->mode.clock; | |
4770 | ||
4771 | line_time_us = (sprite_width * 1000) / clock; | |
4772 | line_count = (latency_ns / line_time_us + 1000) / 1000; | |
4773 | line_size = sprite_width * pixel_size; | |
4774 | ||
4775 | /* Use the minimum of the small and large buffer method for primary */ | |
4776 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; | |
4777 | large = line_count * line_size; | |
4778 | ||
4779 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); | |
4780 | *sprite_wm = entries + display->guard_size; | |
4781 | ||
4782 | return *sprite_wm > 0x3ff ? false : true; | |
4783 | } | |
4784 | ||
4785 | static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe, | |
4786 | uint32_t sprite_width, int pixel_size) | |
4787 | { | |
4788 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4789 | int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ | |
47842649 | 4790 | u32 val; |
b840d907 JB |
4791 | int sprite_wm, reg; |
4792 | int ret; | |
4793 | ||
4794 | switch (pipe) { | |
4795 | case 0: | |
4796 | reg = WM0_PIPEA_ILK; | |
4797 | break; | |
4798 | case 1: | |
4799 | reg = WM0_PIPEB_ILK; | |
4800 | break; | |
4801 | case 2: | |
4802 | reg = WM0_PIPEC_IVB; | |
4803 | break; | |
4804 | default: | |
4805 | return; /* bad pipe */ | |
4806 | } | |
4807 | ||
4808 | ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size, | |
4809 | &sandybridge_display_wm_info, | |
4810 | latency, &sprite_wm); | |
4811 | if (!ret) { | |
4812 | DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n", | |
4813 | pipe); | |
4814 | return; | |
4815 | } | |
4816 | ||
47842649 JB |
4817 | val = I915_READ(reg); |
4818 | val &= ~WM0_PIPE_SPRITE_MASK; | |
4819 | I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT)); | |
b840d907 JB |
4820 | DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm); |
4821 | ||
4822 | ||
4823 | ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, | |
4824 | pixel_size, | |
4825 | &sandybridge_display_srwm_info, | |
4826 | SNB_READ_WM1_LATENCY() * 500, | |
4827 | &sprite_wm); | |
4828 | if (!ret) { | |
4829 | DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n", | |
4830 | pipe); | |
4831 | return; | |
4832 | } | |
4833 | I915_WRITE(WM1S_LP_ILK, sprite_wm); | |
4834 | ||
4835 | /* Only IVB has two more LP watermarks for sprite */ | |
4836 | if (!IS_IVYBRIDGE(dev)) | |
4837 | return; | |
4838 | ||
4839 | ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, | |
4840 | pixel_size, | |
4841 | &sandybridge_display_srwm_info, | |
4842 | SNB_READ_WM2_LATENCY() * 500, | |
4843 | &sprite_wm); | |
4844 | if (!ret) { | |
4845 | DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n", | |
4846 | pipe); | |
4847 | return; | |
4848 | } | |
4849 | I915_WRITE(WM2S_LP_IVB, sprite_wm); | |
4850 | ||
4851 | ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, | |
4852 | pixel_size, | |
4853 | &sandybridge_display_srwm_info, | |
4854 | SNB_READ_WM3_LATENCY() * 500, | |
4855 | &sprite_wm); | |
4856 | if (!ret) { | |
4857 | DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n", | |
4858 | pipe); | |
4859 | return; | |
4860 | } | |
4861 | I915_WRITE(WM3S_LP_IVB, sprite_wm); | |
4862 | } | |
4863 | ||
7662c8bd SL |
4864 | /** |
4865 | * intel_update_watermarks - update FIFO watermark values based on current modes | |
4866 | * | |
4867 | * Calculate watermark values for the various WM regs based on current mode | |
4868 | * and plane configuration. | |
4869 | * | |
4870 | * There are several cases to deal with here: | |
4871 | * - normal (i.e. non-self-refresh) | |
4872 | * - self-refresh (SR) mode | |
4873 | * - lines are large relative to FIFO size (buffer can hold up to 2) | |
4874 | * - lines are small relative to FIFO size (buffer can hold more than 2 | |
4875 | * lines), so need to account for TLB latency | |
4876 | * | |
4877 | * The normal calculation is: | |
4878 | * watermark = dotclock * bytes per pixel * latency | |
4879 | * where latency is platform & configuration dependent (we assume pessimal | |
4880 | * values here). | |
4881 | * | |
4882 | * The SR calculation is: | |
4883 | * watermark = (trunc(latency/line time)+1) * surface width * | |
4884 | * bytes per pixel | |
4885 | * where | |
4886 | * line time = htotal / dotclock | |
fa143215 | 4887 | * surface width = hdisplay for normal plane and 64 for cursor |
7662c8bd SL |
4888 | * and latency is assumed to be high, as above. |
4889 | * | |
4890 | * The final value programmed to the register should always be rounded up, | |
4891 | * and include an extra 2 entries to account for clock crossings. | |
4892 | * | |
4893 | * We don't use the sprite, so we can ignore that. And on Crestline we have | |
4894 | * to set the non-SR watermarks to 8. | |
5eddb70b | 4895 | */ |
7662c8bd SL |
4896 | static void intel_update_watermarks(struct drm_device *dev) |
4897 | { | |
e70236a8 | 4898 | struct drm_i915_private *dev_priv = dev->dev_private; |
7662c8bd | 4899 | |
d210246a CW |
4900 | if (dev_priv->display.update_wm) |
4901 | dev_priv->display.update_wm(dev); | |
7662c8bd SL |
4902 | } |
4903 | ||
b840d907 JB |
4904 | void intel_update_sprite_watermarks(struct drm_device *dev, int pipe, |
4905 | uint32_t sprite_width, int pixel_size) | |
4906 | { | |
4907 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4908 | ||
4909 | if (dev_priv->display.update_sprite_wm) | |
4910 | dev_priv->display.update_sprite_wm(dev, pipe, sprite_width, | |
4911 | pixel_size); | |
4912 | } | |
4913 | ||
a7615030 CW |
4914 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
4915 | { | |
72bbe58c KP |
4916 | if (i915_panel_use_ssc >= 0) |
4917 | return i915_panel_use_ssc != 0; | |
4918 | return dev_priv->lvds_use_ssc | |
435793df | 4919 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
4920 | } |
4921 | ||
5a354204 JB |
4922 | /** |
4923 | * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send | |
4924 | * @crtc: CRTC structure | |
3b5c78a3 | 4925 | * @mode: requested mode |
5a354204 JB |
4926 | * |
4927 | * A pipe may be connected to one or more outputs. Based on the depth of the | |
4928 | * attached framebuffer, choose a good color depth to use on the pipe. | |
4929 | * | |
4930 | * If possible, match the pipe depth to the fb depth. In some cases, this | |
4931 | * isn't ideal, because the connected output supports a lesser or restricted | |
4932 | * set of depths. Resolve that here: | |
4933 | * LVDS typically supports only 6bpc, so clamp down in that case | |
4934 | * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc | |
4935 | * Displays may support a restricted set as well, check EDID and clamp as | |
4936 | * appropriate. | |
3b5c78a3 | 4937 | * DP may want to dither down to 6bpc to fit larger modes |
5a354204 JB |
4938 | * |
4939 | * RETURNS: | |
4940 | * Dithering requirement (i.e. false if display bpc and pipe bpc match, | |
4941 | * true if they don't match). | |
4942 | */ | |
4943 | static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc, | |
3b5c78a3 AJ |
4944 | unsigned int *pipe_bpp, |
4945 | struct drm_display_mode *mode) | |
5a354204 JB |
4946 | { |
4947 | struct drm_device *dev = crtc->dev; | |
4948 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4949 | struct drm_encoder *encoder; | |
4950 | struct drm_connector *connector; | |
4951 | unsigned int display_bpc = UINT_MAX, bpc; | |
4952 | ||
4953 | /* Walk the encoders & connectors on this crtc, get min bpc */ | |
4954 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
4955 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
4956 | ||
4957 | if (encoder->crtc != crtc) | |
4958 | continue; | |
4959 | ||
4960 | if (intel_encoder->type == INTEL_OUTPUT_LVDS) { | |
4961 | unsigned int lvds_bpc; | |
4962 | ||
4963 | if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == | |
4964 | LVDS_A3_POWER_UP) | |
4965 | lvds_bpc = 8; | |
4966 | else | |
4967 | lvds_bpc = 6; | |
4968 | ||
4969 | if (lvds_bpc < display_bpc) { | |
82820490 | 4970 | DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc); |
5a354204 JB |
4971 | display_bpc = lvds_bpc; |
4972 | } | |
4973 | continue; | |
4974 | } | |
4975 | ||
4976 | if (intel_encoder->type == INTEL_OUTPUT_EDP) { | |
4977 | /* Use VBT settings if we have an eDP panel */ | |
4978 | unsigned int edp_bpc = dev_priv->edp.bpp / 3; | |
4979 | ||
4980 | if (edp_bpc < display_bpc) { | |
82820490 | 4981 | DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc); |
5a354204 JB |
4982 | display_bpc = edp_bpc; |
4983 | } | |
4984 | continue; | |
4985 | } | |
4986 | ||
4987 | /* Not one of the known troublemakers, check the EDID */ | |
4988 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
4989 | head) { | |
4990 | if (connector->encoder != encoder) | |
4991 | continue; | |
4992 | ||
62ac41a6 JB |
4993 | /* Don't use an invalid EDID bpc value */ |
4994 | if (connector->display_info.bpc && | |
4995 | connector->display_info.bpc < display_bpc) { | |
82820490 | 4996 | DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc); |
5a354204 JB |
4997 | display_bpc = connector->display_info.bpc; |
4998 | } | |
4999 | } | |
5000 | ||
5001 | /* | |
5002 | * HDMI is either 12 or 8, so if the display lets 10bpc sneak | |
5003 | * through, clamp it down. (Note: >12bpc will be caught below.) | |
5004 | */ | |
5005 | if (intel_encoder->type == INTEL_OUTPUT_HDMI) { | |
5006 | if (display_bpc > 8 && display_bpc < 12) { | |
82820490 | 5007 | DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n"); |
5a354204 JB |
5008 | display_bpc = 12; |
5009 | } else { | |
82820490 | 5010 | DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n"); |
5a354204 JB |
5011 | display_bpc = 8; |
5012 | } | |
5013 | } | |
5014 | } | |
5015 | ||
3b5c78a3 AJ |
5016 | if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) { |
5017 | DRM_DEBUG_KMS("Dithering DP to 6bpc\n"); | |
5018 | display_bpc = 6; | |
5019 | } | |
5020 | ||
5a354204 JB |
5021 | /* |
5022 | * We could just drive the pipe at the highest bpc all the time and | |
5023 | * enable dithering as needed, but that costs bandwidth. So choose | |
5024 | * the minimum value that expresses the full color range of the fb but | |
5025 | * also stays within the max display bpc discovered above. | |
5026 | */ | |
5027 | ||
5028 | switch (crtc->fb->depth) { | |
5029 | case 8: | |
5030 | bpc = 8; /* since we go through a colormap */ | |
5031 | break; | |
5032 | case 15: | |
5033 | case 16: | |
5034 | bpc = 6; /* min is 18bpp */ | |
5035 | break; | |
5036 | case 24: | |
578393cd | 5037 | bpc = 8; |
5a354204 JB |
5038 | break; |
5039 | case 30: | |
578393cd | 5040 | bpc = 10; |
5a354204 JB |
5041 | break; |
5042 | case 48: | |
578393cd | 5043 | bpc = 12; |
5a354204 JB |
5044 | break; |
5045 | default: | |
5046 | DRM_DEBUG("unsupported depth, assuming 24 bits\n"); | |
5047 | bpc = min((unsigned int)8, display_bpc); | |
5048 | break; | |
5049 | } | |
5050 | ||
578393cd KP |
5051 | display_bpc = min(display_bpc, bpc); |
5052 | ||
82820490 AJ |
5053 | DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n", |
5054 | bpc, display_bpc); | |
5a354204 | 5055 | |
578393cd | 5056 | *pipe_bpp = display_bpc * 3; |
5a354204 JB |
5057 | |
5058 | return display_bpc != bpc; | |
5059 | } | |
5060 | ||
c65d77d8 JB |
5061 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
5062 | { | |
5063 | struct drm_device *dev = crtc->dev; | |
5064 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5065 | int refclk; | |
5066 | ||
5067 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && | |
5068 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
5069 | refclk = dev_priv->lvds_ssc_freq * 1000; | |
5070 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", | |
5071 | refclk / 1000); | |
5072 | } else if (!IS_GEN2(dev)) { | |
5073 | refclk = 96000; | |
5074 | } else { | |
5075 | refclk = 48000; | |
5076 | } | |
5077 | ||
5078 | return refclk; | |
5079 | } | |
5080 | ||
5081 | static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode, | |
5082 | intel_clock_t *clock) | |
5083 | { | |
5084 | /* SDVO TV has fixed PLL values depend on its clock range, | |
5085 | this mirrors vbios setting. */ | |
5086 | if (adjusted_mode->clock >= 100000 | |
5087 | && adjusted_mode->clock < 140500) { | |
5088 | clock->p1 = 2; | |
5089 | clock->p2 = 10; | |
5090 | clock->n = 3; | |
5091 | clock->m1 = 16; | |
5092 | clock->m2 = 8; | |
5093 | } else if (adjusted_mode->clock >= 140500 | |
5094 | && adjusted_mode->clock <= 200000) { | |
5095 | clock->p1 = 1; | |
5096 | clock->p2 = 10; | |
5097 | clock->n = 6; | |
5098 | clock->m1 = 12; | |
5099 | clock->m2 = 8; | |
5100 | } | |
5101 | } | |
5102 | ||
a7516a05 JB |
5103 | static void i9xx_update_pll_dividers(struct drm_crtc *crtc, |
5104 | intel_clock_t *clock, | |
5105 | intel_clock_t *reduced_clock) | |
5106 | { | |
5107 | struct drm_device *dev = crtc->dev; | |
5108 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5109 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5110 | int pipe = intel_crtc->pipe; | |
5111 | u32 fp, fp2 = 0; | |
5112 | ||
5113 | if (IS_PINEVIEW(dev)) { | |
5114 | fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2; | |
5115 | if (reduced_clock) | |
5116 | fp2 = (1 << reduced_clock->n) << 16 | | |
5117 | reduced_clock->m1 << 8 | reduced_clock->m2; | |
5118 | } else { | |
5119 | fp = clock->n << 16 | clock->m1 << 8 | clock->m2; | |
5120 | if (reduced_clock) | |
5121 | fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 | | |
5122 | reduced_clock->m2; | |
5123 | } | |
5124 | ||
5125 | I915_WRITE(FP0(pipe), fp); | |
5126 | ||
5127 | intel_crtc->lowfreq_avail = false; | |
5128 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && | |
5129 | reduced_clock && i915_powersave) { | |
5130 | I915_WRITE(FP1(pipe), fp2); | |
5131 | intel_crtc->lowfreq_avail = true; | |
5132 | } else { | |
5133 | I915_WRITE(FP1(pipe), fp); | |
5134 | } | |
5135 | } | |
5136 | ||
f564048e EA |
5137 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
5138 | struct drm_display_mode *mode, | |
5139 | struct drm_display_mode *adjusted_mode, | |
5140 | int x, int y, | |
5141 | struct drm_framebuffer *old_fb) | |
79e53945 JB |
5142 | { |
5143 | struct drm_device *dev = crtc->dev; | |
5144 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5145 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5146 | int pipe = intel_crtc->pipe; | |
80824003 | 5147 | int plane = intel_crtc->plane; |
c751ce4f | 5148 | int refclk, num_connectors = 0; |
652c393a | 5149 | intel_clock_t clock, reduced_clock; |
0529a0d9 | 5150 | u32 dpll, dspcntr, pipeconf, vsyncshift; |
652c393a | 5151 | bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false; |
a4fc5ed6 | 5152 | bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; |
79e53945 | 5153 | struct drm_mode_config *mode_config = &dev->mode_config; |
5eddb70b | 5154 | struct intel_encoder *encoder; |
d4906093 | 5155 | const intel_limit_t *limit; |
5c3b82e2 | 5156 | int ret; |
fae14981 | 5157 | u32 temp; |
aa9b500d | 5158 | u32 lvds_sync = 0; |
79e53945 | 5159 | |
5eddb70b CW |
5160 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { |
5161 | if (encoder->base.crtc != crtc) | |
79e53945 JB |
5162 | continue; |
5163 | ||
5eddb70b | 5164 | switch (encoder->type) { |
79e53945 JB |
5165 | case INTEL_OUTPUT_LVDS: |
5166 | is_lvds = true; | |
5167 | break; | |
5168 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 5169 | case INTEL_OUTPUT_HDMI: |
79e53945 | 5170 | is_sdvo = true; |
5eddb70b | 5171 | if (encoder->needs_tv_clock) |
e2f0ba97 | 5172 | is_tv = true; |
79e53945 JB |
5173 | break; |
5174 | case INTEL_OUTPUT_DVO: | |
5175 | is_dvo = true; | |
5176 | break; | |
5177 | case INTEL_OUTPUT_TVOUT: | |
5178 | is_tv = true; | |
5179 | break; | |
5180 | case INTEL_OUTPUT_ANALOG: | |
5181 | is_crt = true; | |
5182 | break; | |
a4fc5ed6 KP |
5183 | case INTEL_OUTPUT_DISPLAYPORT: |
5184 | is_dp = true; | |
5185 | break; | |
79e53945 | 5186 | } |
43565a06 | 5187 | |
c751ce4f | 5188 | num_connectors++; |
79e53945 JB |
5189 | } |
5190 | ||
c65d77d8 | 5191 | refclk = i9xx_get_refclk(crtc, num_connectors); |
79e53945 | 5192 | |
d4906093 ML |
5193 | /* |
5194 | * Returns a set of divisors for the desired target clock with the given | |
5195 | * refclk, or FALSE. The returned values represent the clock equation: | |
5196 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
5197 | */ | |
1b894b59 | 5198 | limit = intel_limit(crtc, refclk); |
cec2f356 SP |
5199 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL, |
5200 | &clock); | |
79e53945 JB |
5201 | if (!ok) { |
5202 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
5c3b82e2 | 5203 | return -EINVAL; |
79e53945 JB |
5204 | } |
5205 | ||
cda4b7d3 | 5206 | /* Ensure that the cursor is valid for the new mode before changing... */ |
6b383a7f | 5207 | intel_crtc_update_cursor(crtc, true); |
cda4b7d3 | 5208 | |
ddc9003c | 5209 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
5210 | /* |
5211 | * Ensure we match the reduced clock's P to the target clock. | |
5212 | * If the clocks don't match, we can't switch the display clock | |
5213 | * by using the FP0/FP1. In such case we will disable the LVDS | |
5214 | * downclock feature. | |
5215 | */ | |
ddc9003c | 5216 | has_reduced_clock = limit->find_pll(limit, crtc, |
5eddb70b CW |
5217 | dev_priv->lvds_downclock, |
5218 | refclk, | |
cec2f356 | 5219 | &clock, |
5eddb70b | 5220 | &reduced_clock); |
652c393a | 5221 | } |
c65d77d8 JB |
5222 | |
5223 | if (is_sdvo && is_tv) | |
5224 | i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock); | |
7026d4ac | 5225 | |
a7516a05 JB |
5226 | i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ? |
5227 | &reduced_clock : NULL); | |
79e53945 | 5228 | |
929c77fb | 5229 | dpll = DPLL_VGA_MODE_DIS; |
2c07245f | 5230 | |
a6c45cf0 | 5231 | if (!IS_GEN2(dev)) { |
79e53945 JB |
5232 | if (is_lvds) |
5233 | dpll |= DPLLB_MODE_LVDS; | |
5234 | else | |
5235 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
5236 | if (is_sdvo) { | |
6c9547ff CW |
5237 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
5238 | if (pixel_multiplier > 1) { | |
5239 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
5240 | dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; | |
6c9547ff | 5241 | } |
79e53945 | 5242 | dpll |= DPLL_DVO_HIGH_SPEED; |
79e53945 | 5243 | } |
929c77fb | 5244 | if (is_dp) |
a4fc5ed6 | 5245 | dpll |= DPLL_DVO_HIGH_SPEED; |
79e53945 JB |
5246 | |
5247 | /* compute bitmask from p1 value */ | |
f2b115e6 AJ |
5248 | if (IS_PINEVIEW(dev)) |
5249 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
2c07245f | 5250 | else { |
2177832f | 5251 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
652c393a JB |
5252 | if (IS_G4X(dev) && has_reduced_clock) |
5253 | dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
2c07245f | 5254 | } |
79e53945 JB |
5255 | switch (clock.p2) { |
5256 | case 5: | |
5257 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
5258 | break; | |
5259 | case 7: | |
5260 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
5261 | break; | |
5262 | case 10: | |
5263 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
5264 | break; | |
5265 | case 14: | |
5266 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
5267 | break; | |
5268 | } | |
929c77fb | 5269 | if (INTEL_INFO(dev)->gen >= 4) |
79e53945 JB |
5270 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
5271 | } else { | |
5272 | if (is_lvds) { | |
5273 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5274 | } else { | |
5275 | if (clock.p1 == 2) | |
5276 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
5277 | else | |
5278 | dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5279 | if (clock.p2 == 4) | |
5280 | dpll |= PLL_P2_DIVIDE_BY_4; | |
5281 | } | |
5282 | } | |
5283 | ||
43565a06 KH |
5284 | if (is_sdvo && is_tv) |
5285 | dpll |= PLL_REF_INPUT_TVCLKINBC; | |
5286 | else if (is_tv) | |
79e53945 | 5287 | /* XXX: just matching BIOS for now */ |
43565a06 | 5288 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
79e53945 | 5289 | dpll |= 3; |
a7615030 | 5290 | else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 5291 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
5292 | else |
5293 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5294 | ||
5295 | /* setup pipeconf */ | |
5eddb70b | 5296 | pipeconf = I915_READ(PIPECONF(pipe)); |
79e53945 JB |
5297 | |
5298 | /* Set up the display plane register */ | |
5299 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
5300 | ||
929c77fb EA |
5301 | if (pipe == 0) |
5302 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; | |
5303 | else | |
5304 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
79e53945 | 5305 | |
a6c45cf0 | 5306 | if (pipe == 0 && INTEL_INFO(dev)->gen < 4) { |
79e53945 JB |
5307 | /* Enable pixel doubling when the dot clock is > 90% of the (display) |
5308 | * core speed. | |
5309 | * | |
5310 | * XXX: No double-wide on 915GM pipe B. Is that the only reason for the | |
5311 | * pipe == 0 check? | |
5312 | */ | |
e70236a8 JB |
5313 | if (mode->clock > |
5314 | dev_priv->display.get_display_clock_speed(dev) * 9 / 10) | |
5eddb70b | 5315 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
79e53945 | 5316 | else |
5eddb70b | 5317 | pipeconf &= ~PIPECONF_DOUBLE_WIDE; |
79e53945 JB |
5318 | } |
5319 | ||
3b5c78a3 AJ |
5320 | /* default to 8bpc */ |
5321 | pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN); | |
5322 | if (is_dp) { | |
5323 | if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) { | |
5324 | pipeconf |= PIPECONF_BPP_6 | | |
5325 | PIPECONF_DITHER_EN | | |
5326 | PIPECONF_DITHER_TYPE_SP; | |
5327 | } | |
5328 | } | |
5329 | ||
929c77fb | 5330 | dpll |= DPLL_VCO_ENABLE; |
8d86dc6a | 5331 | |
28c97730 | 5332 | DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); |
79e53945 JB |
5333 | drm_mode_debug_printmodeline(mode); |
5334 | ||
fae14981 | 5335 | I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); |
5eddb70b | 5336 | |
fae14981 | 5337 | POSTING_READ(DPLL(pipe)); |
c713bb08 | 5338 | udelay(150); |
8db9d77b | 5339 | |
79e53945 JB |
5340 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. |
5341 | * This is an exception to the general rule that mode_set doesn't turn | |
5342 | * things on. | |
5343 | */ | |
5344 | if (is_lvds) { | |
fae14981 | 5345 | temp = I915_READ(LVDS); |
5eddb70b | 5346 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; |
b3b095b3 | 5347 | if (pipe == 1) { |
929c77fb | 5348 | temp |= LVDS_PIPEB_SELECT; |
b3b095b3 | 5349 | } else { |
929c77fb | 5350 | temp &= ~LVDS_PIPEB_SELECT; |
b3b095b3 | 5351 | } |
a3e17eb8 | 5352 | /* set the corresponsding LVDS_BORDER bit */ |
5eddb70b | 5353 | temp |= dev_priv->lvds_border_bits; |
79e53945 JB |
5354 | /* Set the B0-B3 data pairs corresponding to whether we're going to |
5355 | * set the DPLLs for dual-channel mode or not. | |
5356 | */ | |
5357 | if (clock.p2 == 7) | |
5eddb70b | 5358 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; |
79e53945 | 5359 | else |
5eddb70b | 5360 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); |
79e53945 JB |
5361 | |
5362 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) | |
5363 | * appropriately here, but we need to look more thoroughly into how | |
5364 | * panels behave in the two modes. | |
5365 | */ | |
929c77fb EA |
5366 | /* set the dithering flag on LVDS as needed */ |
5367 | if (INTEL_INFO(dev)->gen >= 4) { | |
434ed097 | 5368 | if (dev_priv->lvds_dither) |
5eddb70b | 5369 | temp |= LVDS_ENABLE_DITHER; |
434ed097 | 5370 | else |
5eddb70b | 5371 | temp &= ~LVDS_ENABLE_DITHER; |
898822ce | 5372 | } |
aa9b500d BF |
5373 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
5374 | lvds_sync |= LVDS_HSYNC_POLARITY; | |
5375 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) | |
5376 | lvds_sync |= LVDS_VSYNC_POLARITY; | |
5377 | if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY)) | |
5378 | != lvds_sync) { | |
5379 | char flags[2] = "-+"; | |
5380 | DRM_INFO("Changing LVDS panel from " | |
5381 | "(%chsync, %cvsync) to (%chsync, %cvsync)\n", | |
5382 | flags[!(temp & LVDS_HSYNC_POLARITY)], | |
5383 | flags[!(temp & LVDS_VSYNC_POLARITY)], | |
5384 | flags[!(lvds_sync & LVDS_HSYNC_POLARITY)], | |
5385 | flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]); | |
5386 | temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); | |
5387 | temp |= lvds_sync; | |
5388 | } | |
fae14981 | 5389 | I915_WRITE(LVDS, temp); |
79e53945 | 5390 | } |
434ed097 | 5391 | |
929c77fb | 5392 | if (is_dp) { |
a4fc5ed6 | 5393 | intel_dp_set_m_n(crtc, mode, adjusted_mode); |
434ed097 JB |
5394 | } |
5395 | ||
fae14981 | 5396 | I915_WRITE(DPLL(pipe), dpll); |
5eddb70b | 5397 | |
c713bb08 | 5398 | /* Wait for the clocks to stabilize. */ |
fae14981 | 5399 | POSTING_READ(DPLL(pipe)); |
c713bb08 | 5400 | udelay(150); |
32f9d658 | 5401 | |
c713bb08 EA |
5402 | if (INTEL_INFO(dev)->gen >= 4) { |
5403 | temp = 0; | |
5404 | if (is_sdvo) { | |
5405 | temp = intel_mode_get_pixel_multiplier(adjusted_mode); | |
5406 | if (temp > 1) | |
5407 | temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
5408 | else | |
5409 | temp = 0; | |
32f9d658 | 5410 | } |
c713bb08 EA |
5411 | I915_WRITE(DPLL_MD(pipe), temp); |
5412 | } else { | |
5413 | /* The pixel multiplier can only be updated once the | |
5414 | * DPLL is enabled and the clocks are stable. | |
5415 | * | |
5416 | * So write it again. | |
5417 | */ | |
fae14981 | 5418 | I915_WRITE(DPLL(pipe), dpll); |
79e53945 | 5419 | } |
79e53945 | 5420 | |
a7516a05 JB |
5421 | if (HAS_PIPE_CXSR(dev)) { |
5422 | if (intel_crtc->lowfreq_avail) { | |
28c97730 | 5423 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); |
652c393a | 5424 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; |
a7516a05 | 5425 | } else { |
28c97730 | 5426 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); |
652c393a JB |
5427 | pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; |
5428 | } | |
5429 | } | |
5430 | ||
617cf884 | 5431 | pipeconf &= ~PIPECONF_INTERLACE_MASK; |
dbb02575 DV |
5432 | if (!IS_GEN2(dev) && |
5433 | adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { | |
734b4157 KH |
5434 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
5435 | /* the chip adds 2 halflines automatically */ | |
734b4157 | 5436 | adjusted_mode->crtc_vtotal -= 1; |
734b4157 | 5437 | adjusted_mode->crtc_vblank_end -= 1; |
0529a0d9 DV |
5438 | vsyncshift = adjusted_mode->crtc_hsync_start |
5439 | - adjusted_mode->crtc_htotal/2; | |
5440 | } else { | |
617cf884 | 5441 | pipeconf |= PIPECONF_PROGRESSIVE; |
0529a0d9 DV |
5442 | vsyncshift = 0; |
5443 | } | |
5444 | ||
5445 | if (!IS_GEN3(dev)) | |
5446 | I915_WRITE(VSYNCSHIFT(pipe), vsyncshift); | |
734b4157 | 5447 | |
5eddb70b CW |
5448 | I915_WRITE(HTOTAL(pipe), |
5449 | (adjusted_mode->crtc_hdisplay - 1) | | |
79e53945 | 5450 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
5eddb70b CW |
5451 | I915_WRITE(HBLANK(pipe), |
5452 | (adjusted_mode->crtc_hblank_start - 1) | | |
79e53945 | 5453 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
5eddb70b CW |
5454 | I915_WRITE(HSYNC(pipe), |
5455 | (adjusted_mode->crtc_hsync_start - 1) | | |
79e53945 | 5456 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
5eddb70b CW |
5457 | |
5458 | I915_WRITE(VTOTAL(pipe), | |
5459 | (adjusted_mode->crtc_vdisplay - 1) | | |
79e53945 | 5460 | ((adjusted_mode->crtc_vtotal - 1) << 16)); |
5eddb70b CW |
5461 | I915_WRITE(VBLANK(pipe), |
5462 | (adjusted_mode->crtc_vblank_start - 1) | | |
79e53945 | 5463 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); |
5eddb70b CW |
5464 | I915_WRITE(VSYNC(pipe), |
5465 | (adjusted_mode->crtc_vsync_start - 1) | | |
79e53945 | 5466 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
5eddb70b CW |
5467 | |
5468 | /* pipesrc and dspsize control the size that is scaled from, | |
5469 | * which should always be the user's requested size. | |
79e53945 | 5470 | */ |
929c77fb EA |
5471 | I915_WRITE(DSPSIZE(plane), |
5472 | ((mode->vdisplay - 1) << 16) | | |
5473 | (mode->hdisplay - 1)); | |
5474 | I915_WRITE(DSPPOS(plane), 0); | |
5eddb70b CW |
5475 | I915_WRITE(PIPESRC(pipe), |
5476 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); | |
2c07245f | 5477 | |
f564048e EA |
5478 | I915_WRITE(PIPECONF(pipe), pipeconf); |
5479 | POSTING_READ(PIPECONF(pipe)); | |
929c77fb | 5480 | intel_enable_pipe(dev_priv, pipe, false); |
f564048e EA |
5481 | |
5482 | intel_wait_for_vblank(dev, pipe); | |
5483 | ||
f564048e EA |
5484 | I915_WRITE(DSPCNTR(plane), dspcntr); |
5485 | POSTING_READ(DSPCNTR(plane)); | |
284d9529 | 5486 | intel_enable_plane(dev_priv, plane, pipe); |
f564048e EA |
5487 | |
5488 | ret = intel_pipe_set_base(crtc, x, y, old_fb); | |
5489 | ||
5490 | intel_update_watermarks(dev); | |
5491 | ||
f564048e EA |
5492 | return ret; |
5493 | } | |
5494 | ||
9fb526db KP |
5495 | /* |
5496 | * Initialize reference clocks when the driver loads | |
5497 | */ | |
5498 | void ironlake_init_pch_refclk(struct drm_device *dev) | |
13d83a67 JB |
5499 | { |
5500 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5501 | struct drm_mode_config *mode_config = &dev->mode_config; | |
13d83a67 | 5502 | struct intel_encoder *encoder; |
13d83a67 JB |
5503 | u32 temp; |
5504 | bool has_lvds = false; | |
199e5d79 KP |
5505 | bool has_cpu_edp = false; |
5506 | bool has_pch_edp = false; | |
5507 | bool has_panel = false; | |
99eb6a01 KP |
5508 | bool has_ck505 = false; |
5509 | bool can_ssc = false; | |
13d83a67 JB |
5510 | |
5511 | /* We need to take the global config into account */ | |
199e5d79 KP |
5512 | list_for_each_entry(encoder, &mode_config->encoder_list, |
5513 | base.head) { | |
5514 | switch (encoder->type) { | |
5515 | case INTEL_OUTPUT_LVDS: | |
5516 | has_panel = true; | |
5517 | has_lvds = true; | |
5518 | break; | |
5519 | case INTEL_OUTPUT_EDP: | |
5520 | has_panel = true; | |
5521 | if (intel_encoder_is_pch_edp(&encoder->base)) | |
5522 | has_pch_edp = true; | |
5523 | else | |
5524 | has_cpu_edp = true; | |
5525 | break; | |
13d83a67 JB |
5526 | } |
5527 | } | |
5528 | ||
99eb6a01 KP |
5529 | if (HAS_PCH_IBX(dev)) { |
5530 | has_ck505 = dev_priv->display_clock_mode; | |
5531 | can_ssc = has_ck505; | |
5532 | } else { | |
5533 | has_ck505 = false; | |
5534 | can_ssc = true; | |
5535 | } | |
5536 | ||
5537 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n", | |
5538 | has_panel, has_lvds, has_pch_edp, has_cpu_edp, | |
5539 | has_ck505); | |
13d83a67 JB |
5540 | |
5541 | /* Ironlake: try to setup display ref clock before DPLL | |
5542 | * enabling. This is only under driver's control after | |
5543 | * PCH B stepping, previous chipset stepping should be | |
5544 | * ignoring this setting. | |
5545 | */ | |
5546 | temp = I915_READ(PCH_DREF_CONTROL); | |
5547 | /* Always enable nonspread source */ | |
5548 | temp &= ~DREF_NONSPREAD_SOURCE_MASK; | |
13d83a67 | 5549 | |
99eb6a01 KP |
5550 | if (has_ck505) |
5551 | temp |= DREF_NONSPREAD_CK505_ENABLE; | |
5552 | else | |
5553 | temp |= DREF_NONSPREAD_SOURCE_ENABLE; | |
13d83a67 | 5554 | |
199e5d79 KP |
5555 | if (has_panel) { |
5556 | temp &= ~DREF_SSC_SOURCE_MASK; | |
5557 | temp |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 5558 | |
199e5d79 | 5559 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 5560 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 5561 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
13d83a67 | 5562 | temp |= DREF_SSC1_ENABLE; |
13d83a67 | 5563 | } |
199e5d79 KP |
5564 | |
5565 | /* Get SSC going before enabling the outputs */ | |
5566 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
5567 | POSTING_READ(PCH_DREF_CONTROL); | |
5568 | udelay(200); | |
5569 | ||
13d83a67 JB |
5570 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
5571 | ||
5572 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 5573 | if (has_cpu_edp) { |
99eb6a01 | 5574 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 5575 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
13d83a67 | 5576 | temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
199e5d79 | 5577 | } |
13d83a67 JB |
5578 | else |
5579 | temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
199e5d79 KP |
5580 | } else |
5581 | temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
5582 | ||
5583 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
5584 | POSTING_READ(PCH_DREF_CONTROL); | |
5585 | udelay(200); | |
5586 | } else { | |
5587 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
5588 | ||
5589 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
5590 | ||
5591 | /* Turn off CPU output */ | |
5592 | temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
5593 | ||
5594 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
5595 | POSTING_READ(PCH_DREF_CONTROL); | |
5596 | udelay(200); | |
5597 | ||
5598 | /* Turn off the SSC source */ | |
5599 | temp &= ~DREF_SSC_SOURCE_MASK; | |
5600 | temp |= DREF_SSC_SOURCE_DISABLE; | |
5601 | ||
5602 | /* Turn off SSC1 */ | |
5603 | temp &= ~ DREF_SSC1_ENABLE; | |
5604 | ||
13d83a67 JB |
5605 | I915_WRITE(PCH_DREF_CONTROL, temp); |
5606 | POSTING_READ(PCH_DREF_CONTROL); | |
5607 | udelay(200); | |
5608 | } | |
5609 | } | |
5610 | ||
d9d444cb JB |
5611 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
5612 | { | |
5613 | struct drm_device *dev = crtc->dev; | |
5614 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5615 | struct intel_encoder *encoder; | |
5616 | struct drm_mode_config *mode_config = &dev->mode_config; | |
5617 | struct intel_encoder *edp_encoder = NULL; | |
5618 | int num_connectors = 0; | |
5619 | bool is_lvds = false; | |
5620 | ||
5621 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { | |
5622 | if (encoder->base.crtc != crtc) | |
5623 | continue; | |
5624 | ||
5625 | switch (encoder->type) { | |
5626 | case INTEL_OUTPUT_LVDS: | |
5627 | is_lvds = true; | |
5628 | break; | |
5629 | case INTEL_OUTPUT_EDP: | |
5630 | edp_encoder = encoder; | |
5631 | break; | |
5632 | } | |
5633 | num_connectors++; | |
5634 | } | |
5635 | ||
5636 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
5637 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", | |
5638 | dev_priv->lvds_ssc_freq); | |
5639 | return dev_priv->lvds_ssc_freq * 1000; | |
5640 | } | |
5641 | ||
5642 | return 120000; | |
5643 | } | |
5644 | ||
f564048e EA |
5645 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, |
5646 | struct drm_display_mode *mode, | |
5647 | struct drm_display_mode *adjusted_mode, | |
5648 | int x, int y, | |
5649 | struct drm_framebuffer *old_fb) | |
79e53945 JB |
5650 | { |
5651 | struct drm_device *dev = crtc->dev; | |
5652 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5653 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5654 | int pipe = intel_crtc->pipe; | |
80824003 | 5655 | int plane = intel_crtc->plane; |
c751ce4f | 5656 | int refclk, num_connectors = 0; |
652c393a | 5657 | intel_clock_t clock, reduced_clock; |
5eddb70b | 5658 | u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf; |
a07d6787 | 5659 | bool ok, has_reduced_clock = false, is_sdvo = false; |
a4fc5ed6 | 5660 | bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; |
8e647a27 | 5661 | struct intel_encoder *has_edp_encoder = NULL; |
79e53945 | 5662 | struct drm_mode_config *mode_config = &dev->mode_config; |
5eddb70b | 5663 | struct intel_encoder *encoder; |
d4906093 | 5664 | const intel_limit_t *limit; |
5c3b82e2 | 5665 | int ret; |
2c07245f | 5666 | struct fdi_m_n m_n = {0}; |
fae14981 | 5667 | u32 temp; |
aa9b500d | 5668 | u32 lvds_sync = 0; |
5a354204 JB |
5669 | int target_clock, pixel_multiplier, lane, link_bw, factor; |
5670 | unsigned int pipe_bpp; | |
5671 | bool dither; | |
79e53945 | 5672 | |
5eddb70b CW |
5673 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { |
5674 | if (encoder->base.crtc != crtc) | |
79e53945 JB |
5675 | continue; |
5676 | ||
5eddb70b | 5677 | switch (encoder->type) { |
79e53945 JB |
5678 | case INTEL_OUTPUT_LVDS: |
5679 | is_lvds = true; | |
5680 | break; | |
5681 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 5682 | case INTEL_OUTPUT_HDMI: |
79e53945 | 5683 | is_sdvo = true; |
5eddb70b | 5684 | if (encoder->needs_tv_clock) |
e2f0ba97 | 5685 | is_tv = true; |
79e53945 | 5686 | break; |
79e53945 JB |
5687 | case INTEL_OUTPUT_TVOUT: |
5688 | is_tv = true; | |
5689 | break; | |
5690 | case INTEL_OUTPUT_ANALOG: | |
5691 | is_crt = true; | |
5692 | break; | |
a4fc5ed6 KP |
5693 | case INTEL_OUTPUT_DISPLAYPORT: |
5694 | is_dp = true; | |
5695 | break; | |
32f9d658 | 5696 | case INTEL_OUTPUT_EDP: |
5eddb70b | 5697 | has_edp_encoder = encoder; |
32f9d658 | 5698 | break; |
79e53945 | 5699 | } |
43565a06 | 5700 | |
c751ce4f | 5701 | num_connectors++; |
79e53945 JB |
5702 | } |
5703 | ||
d9d444cb | 5704 | refclk = ironlake_get_refclk(crtc); |
79e53945 | 5705 | |
d4906093 ML |
5706 | /* |
5707 | * Returns a set of divisors for the desired target clock with the given | |
5708 | * refclk, or FALSE. The returned values represent the clock equation: | |
5709 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
5710 | */ | |
1b894b59 | 5711 | limit = intel_limit(crtc, refclk); |
cec2f356 SP |
5712 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL, |
5713 | &clock); | |
79e53945 JB |
5714 | if (!ok) { |
5715 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
5c3b82e2 | 5716 | return -EINVAL; |
79e53945 JB |
5717 | } |
5718 | ||
cda4b7d3 | 5719 | /* Ensure that the cursor is valid for the new mode before changing... */ |
6b383a7f | 5720 | intel_crtc_update_cursor(crtc, true); |
cda4b7d3 | 5721 | |
ddc9003c | 5722 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
5723 | /* |
5724 | * Ensure we match the reduced clock's P to the target clock. | |
5725 | * If the clocks don't match, we can't switch the display clock | |
5726 | * by using the FP0/FP1. In such case we will disable the LVDS | |
5727 | * downclock feature. | |
5728 | */ | |
ddc9003c | 5729 | has_reduced_clock = limit->find_pll(limit, crtc, |
5eddb70b CW |
5730 | dev_priv->lvds_downclock, |
5731 | refclk, | |
cec2f356 | 5732 | &clock, |
5eddb70b | 5733 | &reduced_clock); |
652c393a | 5734 | } |
7026d4ac ZW |
5735 | /* SDVO TV has fixed PLL values depend on its clock range, |
5736 | this mirrors vbios setting. */ | |
5737 | if (is_sdvo && is_tv) { | |
5738 | if (adjusted_mode->clock >= 100000 | |
5eddb70b | 5739 | && adjusted_mode->clock < 140500) { |
7026d4ac ZW |
5740 | clock.p1 = 2; |
5741 | clock.p2 = 10; | |
5742 | clock.n = 3; | |
5743 | clock.m1 = 16; | |
5744 | clock.m2 = 8; | |
5745 | } else if (adjusted_mode->clock >= 140500 | |
5eddb70b | 5746 | && adjusted_mode->clock <= 200000) { |
7026d4ac ZW |
5747 | clock.p1 = 1; |
5748 | clock.p2 = 10; | |
5749 | clock.n = 6; | |
5750 | clock.m1 = 12; | |
5751 | clock.m2 = 8; | |
5752 | } | |
5753 | } | |
5754 | ||
2c07245f | 5755 | /* FDI link */ |
8febb297 EA |
5756 | pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
5757 | lane = 0; | |
5758 | /* CPU eDP doesn't require FDI link, so just set DP M/N | |
5759 | according to current link config */ | |
5760 | if (has_edp_encoder && | |
5761 | !intel_encoder_is_pch_edp(&has_edp_encoder->base)) { | |
5762 | target_clock = mode->clock; | |
5763 | intel_edp_link_config(has_edp_encoder, | |
5764 | &lane, &link_bw); | |
5765 | } else { | |
5766 | /* [e]DP over FDI requires target mode clock | |
5767 | instead of link clock */ | |
5768 | if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) | |
5eb08b69 | 5769 | target_clock = mode->clock; |
8febb297 EA |
5770 | else |
5771 | target_clock = adjusted_mode->clock; | |
5772 | ||
5773 | /* FDI is a binary signal running at ~2.7GHz, encoding | |
5774 | * each output octet as 10 bits. The actual frequency | |
5775 | * is stored as a divider into a 100MHz clock, and the | |
5776 | * mode pixel clock is stored in units of 1KHz. | |
5777 | * Hence the bw of each lane in terms of the mode signal | |
5778 | * is: | |
5779 | */ | |
5780 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
5781 | } | |
58a27471 | 5782 | |
8febb297 EA |
5783 | /* determine panel color depth */ |
5784 | temp = I915_READ(PIPECONF(pipe)); | |
5785 | temp &= ~PIPE_BPC_MASK; | |
3b5c78a3 | 5786 | dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode); |
5a354204 JB |
5787 | switch (pipe_bpp) { |
5788 | case 18: | |
5789 | temp |= PIPE_6BPC; | |
8febb297 | 5790 | break; |
5a354204 JB |
5791 | case 24: |
5792 | temp |= PIPE_8BPC; | |
8febb297 | 5793 | break; |
5a354204 JB |
5794 | case 30: |
5795 | temp |= PIPE_10BPC; | |
8febb297 | 5796 | break; |
5a354204 JB |
5797 | case 36: |
5798 | temp |= PIPE_12BPC; | |
8febb297 EA |
5799 | break; |
5800 | default: | |
62ac41a6 JB |
5801 | WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n", |
5802 | pipe_bpp); | |
5a354204 JB |
5803 | temp |= PIPE_8BPC; |
5804 | pipe_bpp = 24; | |
5805 | break; | |
8febb297 | 5806 | } |
77ffb597 | 5807 | |
5a354204 JB |
5808 | intel_crtc->bpp = pipe_bpp; |
5809 | I915_WRITE(PIPECONF(pipe), temp); | |
5810 | ||
8febb297 EA |
5811 | if (!lane) { |
5812 | /* | |
5813 | * Account for spread spectrum to avoid | |
5814 | * oversubscribing the link. Max center spread | |
5815 | * is 2.5%; use 5% for safety's sake. | |
5816 | */ | |
5a354204 | 5817 | u32 bps = target_clock * intel_crtc->bpp * 21 / 20; |
8febb297 | 5818 | lane = bps / (link_bw * 8) + 1; |
5eb08b69 | 5819 | } |
2c07245f | 5820 | |
8febb297 EA |
5821 | intel_crtc->fdi_lanes = lane; |
5822 | ||
5823 | if (pixel_multiplier > 1) | |
5824 | link_bw *= pixel_multiplier; | |
5a354204 JB |
5825 | ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, |
5826 | &m_n); | |
8febb297 | 5827 | |
a07d6787 EA |
5828 | fp = clock.n << 16 | clock.m1 << 8 | clock.m2; |
5829 | if (has_reduced_clock) | |
5830 | fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 | | |
5831 | reduced_clock.m2; | |
79e53945 | 5832 | |
c1858123 | 5833 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
5834 | factor = 21; |
5835 | if (is_lvds) { | |
5836 | if ((intel_panel_use_ssc(dev_priv) && | |
5837 | dev_priv->lvds_ssc_freq == 100) || | |
5838 | (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP) | |
5839 | factor = 25; | |
5840 | } else if (is_sdvo && is_tv) | |
5841 | factor = 20; | |
c1858123 | 5842 | |
cb0e0931 | 5843 | if (clock.m < factor * clock.n) |
8febb297 | 5844 | fp |= FP_CB_TUNE; |
2c07245f | 5845 | |
5eddb70b | 5846 | dpll = 0; |
2c07245f | 5847 | |
a07d6787 EA |
5848 | if (is_lvds) |
5849 | dpll |= DPLLB_MODE_LVDS; | |
5850 | else | |
5851 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
5852 | if (is_sdvo) { | |
5853 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); | |
5854 | if (pixel_multiplier > 1) { | |
5855 | dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | |
79e53945 | 5856 | } |
a07d6787 EA |
5857 | dpll |= DPLL_DVO_HIGH_SPEED; |
5858 | } | |
5859 | if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) | |
5860 | dpll |= DPLL_DVO_HIGH_SPEED; | |
79e53945 | 5861 | |
a07d6787 EA |
5862 | /* compute bitmask from p1 value */ |
5863 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5864 | /* also FPA1 */ | |
5865 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
5866 | ||
5867 | switch (clock.p2) { | |
5868 | case 5: | |
5869 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
5870 | break; | |
5871 | case 7: | |
5872 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
5873 | break; | |
5874 | case 10: | |
5875 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
5876 | break; | |
5877 | case 14: | |
5878 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
5879 | break; | |
79e53945 JB |
5880 | } |
5881 | ||
43565a06 KH |
5882 | if (is_sdvo && is_tv) |
5883 | dpll |= PLL_REF_INPUT_TVCLKINBC; | |
5884 | else if (is_tv) | |
79e53945 | 5885 | /* XXX: just matching BIOS for now */ |
43565a06 | 5886 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
79e53945 | 5887 | dpll |= 3; |
a7615030 | 5888 | else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 5889 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
5890 | else |
5891 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5892 | ||
5893 | /* setup pipeconf */ | |
5eddb70b | 5894 | pipeconf = I915_READ(PIPECONF(pipe)); |
79e53945 JB |
5895 | |
5896 | /* Set up the display plane register */ | |
5897 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
5898 | ||
f7cb34d4 | 5899 | DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe); |
79e53945 JB |
5900 | drm_mode_debug_printmodeline(mode); |
5901 | ||
5c5313c8 | 5902 | /* PCH eDP needs FDI, but CPU eDP does not */ |
4b645f14 JB |
5903 | if (!intel_crtc->no_pll) { |
5904 | if (!has_edp_encoder || | |
5905 | intel_encoder_is_pch_edp(&has_edp_encoder->base)) { | |
5906 | I915_WRITE(PCH_FP0(pipe), fp); | |
5907 | I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); | |
5908 | ||
5909 | POSTING_READ(PCH_DPLL(pipe)); | |
5910 | udelay(150); | |
5911 | } | |
5912 | } else { | |
5913 | if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) && | |
5914 | fp == I915_READ(PCH_FP0(0))) { | |
5915 | intel_crtc->use_pll_a = true; | |
5916 | DRM_DEBUG_KMS("using pipe a dpll\n"); | |
5917 | } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) && | |
5918 | fp == I915_READ(PCH_FP0(1))) { | |
5919 | intel_crtc->use_pll_a = false; | |
5920 | DRM_DEBUG_KMS("using pipe b dpll\n"); | |
5921 | } else { | |
5922 | DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n"); | |
5923 | return -EINVAL; | |
5924 | } | |
79e53945 JB |
5925 | } |
5926 | ||
5927 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. | |
5928 | * This is an exception to the general rule that mode_set doesn't turn | |
5929 | * things on. | |
5930 | */ | |
5931 | if (is_lvds) { | |
fae14981 | 5932 | temp = I915_READ(PCH_LVDS); |
5eddb70b | 5933 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; |
7885d205 JB |
5934 | if (HAS_PCH_CPT(dev)) { |
5935 | temp &= ~PORT_TRANS_SEL_MASK; | |
4b645f14 | 5936 | temp |= PORT_TRANS_SEL_CPT(pipe); |
7885d205 JB |
5937 | } else { |
5938 | if (pipe == 1) | |
5939 | temp |= LVDS_PIPEB_SELECT; | |
5940 | else | |
5941 | temp &= ~LVDS_PIPEB_SELECT; | |
5942 | } | |
4b645f14 | 5943 | |
a3e17eb8 | 5944 | /* set the corresponsding LVDS_BORDER bit */ |
5eddb70b | 5945 | temp |= dev_priv->lvds_border_bits; |
79e53945 JB |
5946 | /* Set the B0-B3 data pairs corresponding to whether we're going to |
5947 | * set the DPLLs for dual-channel mode or not. | |
5948 | */ | |
5949 | if (clock.p2 == 7) | |
5eddb70b | 5950 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; |
79e53945 | 5951 | else |
5eddb70b | 5952 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); |
79e53945 JB |
5953 | |
5954 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) | |
5955 | * appropriately here, but we need to look more thoroughly into how | |
5956 | * panels behave in the two modes. | |
5957 | */ | |
aa9b500d BF |
5958 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
5959 | lvds_sync |= LVDS_HSYNC_POLARITY; | |
5960 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) | |
5961 | lvds_sync |= LVDS_VSYNC_POLARITY; | |
5962 | if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY)) | |
5963 | != lvds_sync) { | |
5964 | char flags[2] = "-+"; | |
5965 | DRM_INFO("Changing LVDS panel from " | |
5966 | "(%chsync, %cvsync) to (%chsync, %cvsync)\n", | |
5967 | flags[!(temp & LVDS_HSYNC_POLARITY)], | |
5968 | flags[!(temp & LVDS_VSYNC_POLARITY)], | |
5969 | flags[!(lvds_sync & LVDS_HSYNC_POLARITY)], | |
5970 | flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]); | |
5971 | temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); | |
5972 | temp |= lvds_sync; | |
5973 | } | |
fae14981 | 5974 | I915_WRITE(PCH_LVDS, temp); |
79e53945 | 5975 | } |
434ed097 | 5976 | |
8febb297 EA |
5977 | pipeconf &= ~PIPECONF_DITHER_EN; |
5978 | pipeconf &= ~PIPECONF_DITHER_TYPE_MASK; | |
5a354204 | 5979 | if ((is_lvds && dev_priv->lvds_dither) || dither) { |
8febb297 | 5980 | pipeconf |= PIPECONF_DITHER_EN; |
f74974c7 | 5981 | pipeconf |= PIPECONF_DITHER_TYPE_SP; |
434ed097 | 5982 | } |
5c5313c8 | 5983 | if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) { |
a4fc5ed6 | 5984 | intel_dp_set_m_n(crtc, mode, adjusted_mode); |
8febb297 | 5985 | } else { |
8db9d77b | 5986 | /* For non-DP output, clear any trans DP clock recovery setting.*/ |
9db4a9c7 JB |
5987 | I915_WRITE(TRANSDATA_M1(pipe), 0); |
5988 | I915_WRITE(TRANSDATA_N1(pipe), 0); | |
5989 | I915_WRITE(TRANSDPLINK_M1(pipe), 0); | |
5990 | I915_WRITE(TRANSDPLINK_N1(pipe), 0); | |
8db9d77b | 5991 | } |
79e53945 | 5992 | |
4b645f14 JB |
5993 | if (!intel_crtc->no_pll && |
5994 | (!has_edp_encoder || | |
5995 | intel_encoder_is_pch_edp(&has_edp_encoder->base))) { | |
fae14981 | 5996 | I915_WRITE(PCH_DPLL(pipe), dpll); |
5eddb70b | 5997 | |
32f9d658 | 5998 | /* Wait for the clocks to stabilize. */ |
fae14981 | 5999 | POSTING_READ(PCH_DPLL(pipe)); |
32f9d658 ZW |
6000 | udelay(150); |
6001 | ||
8febb297 EA |
6002 | /* The pixel multiplier can only be updated once the |
6003 | * DPLL is enabled and the clocks are stable. | |
6004 | * | |
6005 | * So write it again. | |
6006 | */ | |
fae14981 | 6007 | I915_WRITE(PCH_DPLL(pipe), dpll); |
79e53945 | 6008 | } |
79e53945 | 6009 | |
5eddb70b | 6010 | intel_crtc->lowfreq_avail = false; |
4b645f14 JB |
6011 | if (!intel_crtc->no_pll) { |
6012 | if (is_lvds && has_reduced_clock && i915_powersave) { | |
6013 | I915_WRITE(PCH_FP1(pipe), fp2); | |
6014 | intel_crtc->lowfreq_avail = true; | |
6015 | if (HAS_PIPE_CXSR(dev)) { | |
6016 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
6017 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
6018 | } | |
6019 | } else { | |
6020 | I915_WRITE(PCH_FP1(pipe), fp); | |
6021 | if (HAS_PIPE_CXSR(dev)) { | |
6022 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
6023 | pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; | |
6024 | } | |
652c393a JB |
6025 | } |
6026 | } | |
6027 | ||
617cf884 | 6028 | pipeconf &= ~PIPECONF_INTERLACE_MASK; |
734b4157 | 6029 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
5def474e | 6030 | pipeconf |= PIPECONF_INTERLACED_ILK; |
734b4157 | 6031 | /* the chip adds 2 halflines automatically */ |
734b4157 | 6032 | adjusted_mode->crtc_vtotal -= 1; |
734b4157 | 6033 | adjusted_mode->crtc_vblank_end -= 1; |
0529a0d9 DV |
6034 | I915_WRITE(VSYNCSHIFT(pipe), |
6035 | adjusted_mode->crtc_hsync_start | |
6036 | - adjusted_mode->crtc_htotal/2); | |
6037 | } else { | |
617cf884 | 6038 | pipeconf |= PIPECONF_PROGRESSIVE; |
0529a0d9 DV |
6039 | I915_WRITE(VSYNCSHIFT(pipe), 0); |
6040 | } | |
734b4157 | 6041 | |
5eddb70b CW |
6042 | I915_WRITE(HTOTAL(pipe), |
6043 | (adjusted_mode->crtc_hdisplay - 1) | | |
79e53945 | 6044 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
5eddb70b CW |
6045 | I915_WRITE(HBLANK(pipe), |
6046 | (adjusted_mode->crtc_hblank_start - 1) | | |
79e53945 | 6047 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
5eddb70b CW |
6048 | I915_WRITE(HSYNC(pipe), |
6049 | (adjusted_mode->crtc_hsync_start - 1) | | |
79e53945 | 6050 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
5eddb70b CW |
6051 | |
6052 | I915_WRITE(VTOTAL(pipe), | |
6053 | (adjusted_mode->crtc_vdisplay - 1) | | |
79e53945 | 6054 | ((adjusted_mode->crtc_vtotal - 1) << 16)); |
5eddb70b CW |
6055 | I915_WRITE(VBLANK(pipe), |
6056 | (adjusted_mode->crtc_vblank_start - 1) | | |
79e53945 | 6057 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); |
5eddb70b CW |
6058 | I915_WRITE(VSYNC(pipe), |
6059 | (adjusted_mode->crtc_vsync_start - 1) | | |
79e53945 | 6060 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
5eddb70b | 6061 | |
8febb297 EA |
6062 | /* pipesrc controls the size that is scaled from, which should |
6063 | * always be the user's requested size. | |
79e53945 | 6064 | */ |
5eddb70b CW |
6065 | I915_WRITE(PIPESRC(pipe), |
6066 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); | |
2c07245f | 6067 | |
8febb297 EA |
6068 | I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); |
6069 | I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n); | |
6070 | I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m); | |
6071 | I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n); | |
2c07245f | 6072 | |
8febb297 EA |
6073 | if (has_edp_encoder && |
6074 | !intel_encoder_is_pch_edp(&has_edp_encoder->base)) { | |
6075 | ironlake_set_pll_edp(crtc, adjusted_mode->clock); | |
2c07245f ZW |
6076 | } |
6077 | ||
5eddb70b CW |
6078 | I915_WRITE(PIPECONF(pipe), pipeconf); |
6079 | POSTING_READ(PIPECONF(pipe)); | |
79e53945 | 6080 | |
9d0498a2 | 6081 | intel_wait_for_vblank(dev, pipe); |
79e53945 | 6082 | |
5eddb70b | 6083 | I915_WRITE(DSPCNTR(plane), dspcntr); |
b24e7179 | 6084 | POSTING_READ(DSPCNTR(plane)); |
79e53945 | 6085 | |
5c3b82e2 | 6086 | ret = intel_pipe_set_base(crtc, x, y, old_fb); |
7662c8bd SL |
6087 | |
6088 | intel_update_watermarks(dev); | |
6089 | ||
1f803ee5 | 6090 | return ret; |
79e53945 JB |
6091 | } |
6092 | ||
f564048e EA |
6093 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
6094 | struct drm_display_mode *mode, | |
6095 | struct drm_display_mode *adjusted_mode, | |
6096 | int x, int y, | |
6097 | struct drm_framebuffer *old_fb) | |
6098 | { | |
6099 | struct drm_device *dev = crtc->dev; | |
6100 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0b701d27 EA |
6101 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6102 | int pipe = intel_crtc->pipe; | |
f564048e EA |
6103 | int ret; |
6104 | ||
0b701d27 | 6105 | drm_vblank_pre_modeset(dev, pipe); |
7662c8bd | 6106 | |
f564048e EA |
6107 | ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode, |
6108 | x, y, old_fb); | |
79e53945 | 6109 | drm_vblank_post_modeset(dev, pipe); |
5c3b82e2 | 6110 | |
d8e70a25 JB |
6111 | if (ret) |
6112 | intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF; | |
6113 | else | |
6114 | intel_crtc->dpms_mode = DRM_MODE_DPMS_ON; | |
120eced9 | 6115 | |
1f803ee5 | 6116 | return ret; |
79e53945 JB |
6117 | } |
6118 | ||
3a9627f4 WF |
6119 | static bool intel_eld_uptodate(struct drm_connector *connector, |
6120 | int reg_eldv, uint32_t bits_eldv, | |
6121 | int reg_elda, uint32_t bits_elda, | |
6122 | int reg_edid) | |
6123 | { | |
6124 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
6125 | uint8_t *eld = connector->eld; | |
6126 | uint32_t i; | |
6127 | ||
6128 | i = I915_READ(reg_eldv); | |
6129 | i &= bits_eldv; | |
6130 | ||
6131 | if (!eld[0]) | |
6132 | return !i; | |
6133 | ||
6134 | if (!i) | |
6135 | return false; | |
6136 | ||
6137 | i = I915_READ(reg_elda); | |
6138 | i &= ~bits_elda; | |
6139 | I915_WRITE(reg_elda, i); | |
6140 | ||
6141 | for (i = 0; i < eld[2]; i++) | |
6142 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) | |
6143 | return false; | |
6144 | ||
6145 | return true; | |
6146 | } | |
6147 | ||
e0dac65e WF |
6148 | static void g4x_write_eld(struct drm_connector *connector, |
6149 | struct drm_crtc *crtc) | |
6150 | { | |
6151 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
6152 | uint8_t *eld = connector->eld; | |
6153 | uint32_t eldv; | |
6154 | uint32_t len; | |
6155 | uint32_t i; | |
6156 | ||
6157 | i = I915_READ(G4X_AUD_VID_DID); | |
6158 | ||
6159 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) | |
6160 | eldv = G4X_ELDV_DEVCL_DEVBLC; | |
6161 | else | |
6162 | eldv = G4X_ELDV_DEVCTG; | |
6163 | ||
3a9627f4 WF |
6164 | if (intel_eld_uptodate(connector, |
6165 | G4X_AUD_CNTL_ST, eldv, | |
6166 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, | |
6167 | G4X_HDMIW_HDMIEDID)) | |
6168 | return; | |
6169 | ||
e0dac65e WF |
6170 | i = I915_READ(G4X_AUD_CNTL_ST); |
6171 | i &= ~(eldv | G4X_ELD_ADDR); | |
6172 | len = (i >> 9) & 0x1f; /* ELD buffer size */ | |
6173 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
6174 | ||
6175 | if (!eld[0]) | |
6176 | return; | |
6177 | ||
6178 | len = min_t(uint8_t, eld[2], len); | |
6179 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
6180 | for (i = 0; i < len; i++) | |
6181 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); | |
6182 | ||
6183 | i = I915_READ(G4X_AUD_CNTL_ST); | |
6184 | i |= eldv; | |
6185 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
6186 | } | |
6187 | ||
6188 | static void ironlake_write_eld(struct drm_connector *connector, | |
6189 | struct drm_crtc *crtc) | |
6190 | { | |
6191 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
6192 | uint8_t *eld = connector->eld; | |
6193 | uint32_t eldv; | |
6194 | uint32_t i; | |
6195 | int len; | |
6196 | int hdmiw_hdmiedid; | |
b6daa025 | 6197 | int aud_config; |
e0dac65e WF |
6198 | int aud_cntl_st; |
6199 | int aud_cntrl_st2; | |
6200 | ||
b3f33cbf | 6201 | if (HAS_PCH_IBX(connector->dev)) { |
1202b4c6 | 6202 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A; |
b6daa025 | 6203 | aud_config = IBX_AUD_CONFIG_A; |
1202b4c6 WF |
6204 | aud_cntl_st = IBX_AUD_CNTL_ST_A; |
6205 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; | |
e0dac65e | 6206 | } else { |
1202b4c6 | 6207 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A; |
b6daa025 | 6208 | aud_config = CPT_AUD_CONFIG_A; |
1202b4c6 WF |
6209 | aud_cntl_st = CPT_AUD_CNTL_ST_A; |
6210 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; | |
e0dac65e WF |
6211 | } |
6212 | ||
6213 | i = to_intel_crtc(crtc)->pipe; | |
6214 | hdmiw_hdmiedid += i * 0x100; | |
6215 | aud_cntl_st += i * 0x100; | |
b6daa025 | 6216 | aud_config += i * 0x100; |
e0dac65e WF |
6217 | |
6218 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i)); | |
6219 | ||
6220 | i = I915_READ(aud_cntl_st); | |
6221 | i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */ | |
6222 | if (!i) { | |
6223 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); | |
6224 | /* operate blindly on all ports */ | |
1202b4c6 WF |
6225 | eldv = IBX_ELD_VALIDB; |
6226 | eldv |= IBX_ELD_VALIDB << 4; | |
6227 | eldv |= IBX_ELD_VALIDB << 8; | |
e0dac65e WF |
6228 | } else { |
6229 | DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i); | |
1202b4c6 | 6230 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
e0dac65e WF |
6231 | } |
6232 | ||
3a9627f4 WF |
6233 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
6234 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
6235 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
b6daa025 WF |
6236 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
6237 | } else | |
6238 | I915_WRITE(aud_config, 0); | |
e0dac65e | 6239 | |
3a9627f4 WF |
6240 | if (intel_eld_uptodate(connector, |
6241 | aud_cntrl_st2, eldv, | |
6242 | aud_cntl_st, IBX_ELD_ADDRESS, | |
6243 | hdmiw_hdmiedid)) | |
6244 | return; | |
6245 | ||
e0dac65e WF |
6246 | i = I915_READ(aud_cntrl_st2); |
6247 | i &= ~eldv; | |
6248 | I915_WRITE(aud_cntrl_st2, i); | |
6249 | ||
6250 | if (!eld[0]) | |
6251 | return; | |
6252 | ||
e0dac65e | 6253 | i = I915_READ(aud_cntl_st); |
1202b4c6 | 6254 | i &= ~IBX_ELD_ADDRESS; |
e0dac65e WF |
6255 | I915_WRITE(aud_cntl_st, i); |
6256 | ||
6257 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
6258 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
6259 | for (i = 0; i < len; i++) | |
6260 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
6261 | ||
6262 | i = I915_READ(aud_cntrl_st2); | |
6263 | i |= eldv; | |
6264 | I915_WRITE(aud_cntrl_st2, i); | |
6265 | } | |
6266 | ||
6267 | void intel_write_eld(struct drm_encoder *encoder, | |
6268 | struct drm_display_mode *mode) | |
6269 | { | |
6270 | struct drm_crtc *crtc = encoder->crtc; | |
6271 | struct drm_connector *connector; | |
6272 | struct drm_device *dev = encoder->dev; | |
6273 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6274 | ||
6275 | connector = drm_select_eld(encoder, mode); | |
6276 | if (!connector) | |
6277 | return; | |
6278 | ||
6279 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", | |
6280 | connector->base.id, | |
6281 | drm_get_connector_name(connector), | |
6282 | connector->encoder->base.id, | |
6283 | drm_get_encoder_name(connector->encoder)); | |
6284 | ||
6285 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; | |
6286 | ||
6287 | if (dev_priv->display.write_eld) | |
6288 | dev_priv->display.write_eld(connector, crtc); | |
6289 | } | |
6290 | ||
79e53945 JB |
6291 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ |
6292 | void intel_crtc_load_lut(struct drm_crtc *crtc) | |
6293 | { | |
6294 | struct drm_device *dev = crtc->dev; | |
6295 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6296 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9db4a9c7 | 6297 | int palreg = PALETTE(intel_crtc->pipe); |
79e53945 JB |
6298 | int i; |
6299 | ||
6300 | /* The clocks have to be on to load the palette. */ | |
6301 | if (!crtc->enabled) | |
6302 | return; | |
6303 | ||
f2b115e6 | 6304 | /* use legacy palette for Ironlake */ |
bad720ff | 6305 | if (HAS_PCH_SPLIT(dev)) |
9db4a9c7 | 6306 | palreg = LGC_PALETTE(intel_crtc->pipe); |
2c07245f | 6307 | |
79e53945 JB |
6308 | for (i = 0; i < 256; i++) { |
6309 | I915_WRITE(palreg + 4 * i, | |
6310 | (intel_crtc->lut_r[i] << 16) | | |
6311 | (intel_crtc->lut_g[i] << 8) | | |
6312 | intel_crtc->lut_b[i]); | |
6313 | } | |
6314 | } | |
6315 | ||
560b85bb CW |
6316 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
6317 | { | |
6318 | struct drm_device *dev = crtc->dev; | |
6319 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6320 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6321 | bool visible = base != 0; | |
6322 | u32 cntl; | |
6323 | ||
6324 | if (intel_crtc->cursor_visible == visible) | |
6325 | return; | |
6326 | ||
9db4a9c7 | 6327 | cntl = I915_READ(_CURACNTR); |
560b85bb CW |
6328 | if (visible) { |
6329 | /* On these chipsets we can only modify the base whilst | |
6330 | * the cursor is disabled. | |
6331 | */ | |
9db4a9c7 | 6332 | I915_WRITE(_CURABASE, base); |
560b85bb CW |
6333 | |
6334 | cntl &= ~(CURSOR_FORMAT_MASK); | |
6335 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ | |
6336 | cntl |= CURSOR_ENABLE | | |
6337 | CURSOR_GAMMA_ENABLE | | |
6338 | CURSOR_FORMAT_ARGB; | |
6339 | } else | |
6340 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); | |
9db4a9c7 | 6341 | I915_WRITE(_CURACNTR, cntl); |
560b85bb CW |
6342 | |
6343 | intel_crtc->cursor_visible = visible; | |
6344 | } | |
6345 | ||
6346 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) | |
6347 | { | |
6348 | struct drm_device *dev = crtc->dev; | |
6349 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6350 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6351 | int pipe = intel_crtc->pipe; | |
6352 | bool visible = base != 0; | |
6353 | ||
6354 | if (intel_crtc->cursor_visible != visible) { | |
548f245b | 6355 | uint32_t cntl = I915_READ(CURCNTR(pipe)); |
560b85bb CW |
6356 | if (base) { |
6357 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); | |
6358 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
6359 | cntl |= pipe << 28; /* Connect to correct pipe */ | |
6360 | } else { | |
6361 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
6362 | cntl |= CURSOR_MODE_DISABLE; | |
6363 | } | |
9db4a9c7 | 6364 | I915_WRITE(CURCNTR(pipe), cntl); |
560b85bb CW |
6365 | |
6366 | intel_crtc->cursor_visible = visible; | |
6367 | } | |
6368 | /* and commit changes on next vblank */ | |
9db4a9c7 | 6369 | I915_WRITE(CURBASE(pipe), base); |
560b85bb CW |
6370 | } |
6371 | ||
65a21cd6 JB |
6372 | static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) |
6373 | { | |
6374 | struct drm_device *dev = crtc->dev; | |
6375 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6376 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6377 | int pipe = intel_crtc->pipe; | |
6378 | bool visible = base != 0; | |
6379 | ||
6380 | if (intel_crtc->cursor_visible != visible) { | |
6381 | uint32_t cntl = I915_READ(CURCNTR_IVB(pipe)); | |
6382 | if (base) { | |
6383 | cntl &= ~CURSOR_MODE; | |
6384 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
6385 | } else { | |
6386 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
6387 | cntl |= CURSOR_MODE_DISABLE; | |
6388 | } | |
6389 | I915_WRITE(CURCNTR_IVB(pipe), cntl); | |
6390 | ||
6391 | intel_crtc->cursor_visible = visible; | |
6392 | } | |
6393 | /* and commit changes on next vblank */ | |
6394 | I915_WRITE(CURBASE_IVB(pipe), base); | |
6395 | } | |
6396 | ||
cda4b7d3 | 6397 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
6398 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
6399 | bool on) | |
cda4b7d3 CW |
6400 | { |
6401 | struct drm_device *dev = crtc->dev; | |
6402 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6403 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6404 | int pipe = intel_crtc->pipe; | |
6405 | int x = intel_crtc->cursor_x; | |
6406 | int y = intel_crtc->cursor_y; | |
560b85bb | 6407 | u32 base, pos; |
cda4b7d3 CW |
6408 | bool visible; |
6409 | ||
6410 | pos = 0; | |
6411 | ||
6b383a7f | 6412 | if (on && crtc->enabled && crtc->fb) { |
cda4b7d3 CW |
6413 | base = intel_crtc->cursor_addr; |
6414 | if (x > (int) crtc->fb->width) | |
6415 | base = 0; | |
6416 | ||
6417 | if (y > (int) crtc->fb->height) | |
6418 | base = 0; | |
6419 | } else | |
6420 | base = 0; | |
6421 | ||
6422 | if (x < 0) { | |
6423 | if (x + intel_crtc->cursor_width < 0) | |
6424 | base = 0; | |
6425 | ||
6426 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
6427 | x = -x; | |
6428 | } | |
6429 | pos |= x << CURSOR_X_SHIFT; | |
6430 | ||
6431 | if (y < 0) { | |
6432 | if (y + intel_crtc->cursor_height < 0) | |
6433 | base = 0; | |
6434 | ||
6435 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
6436 | y = -y; | |
6437 | } | |
6438 | pos |= y << CURSOR_Y_SHIFT; | |
6439 | ||
6440 | visible = base != 0; | |
560b85bb | 6441 | if (!visible && !intel_crtc->cursor_visible) |
cda4b7d3 CW |
6442 | return; |
6443 | ||
65a21cd6 JB |
6444 | if (IS_IVYBRIDGE(dev)) { |
6445 | I915_WRITE(CURPOS_IVB(pipe), pos); | |
6446 | ivb_update_cursor(crtc, base); | |
6447 | } else { | |
6448 | I915_WRITE(CURPOS(pipe), pos); | |
6449 | if (IS_845G(dev) || IS_I865G(dev)) | |
6450 | i845_update_cursor(crtc, base); | |
6451 | else | |
6452 | i9xx_update_cursor(crtc, base); | |
6453 | } | |
cda4b7d3 CW |
6454 | |
6455 | if (visible) | |
6456 | intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj); | |
6457 | } | |
6458 | ||
79e53945 | 6459 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
05394f39 | 6460 | struct drm_file *file, |
79e53945 JB |
6461 | uint32_t handle, |
6462 | uint32_t width, uint32_t height) | |
6463 | { | |
6464 | struct drm_device *dev = crtc->dev; | |
6465 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6466 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 6467 | struct drm_i915_gem_object *obj; |
cda4b7d3 | 6468 | uint32_t addr; |
3f8bc370 | 6469 | int ret; |
79e53945 | 6470 | |
28c97730 | 6471 | DRM_DEBUG_KMS("\n"); |
79e53945 JB |
6472 | |
6473 | /* if we want to turn off the cursor ignore width and height */ | |
6474 | if (!handle) { | |
28c97730 | 6475 | DRM_DEBUG_KMS("cursor off\n"); |
3f8bc370 | 6476 | addr = 0; |
05394f39 | 6477 | obj = NULL; |
5004417d | 6478 | mutex_lock(&dev->struct_mutex); |
3f8bc370 | 6479 | goto finish; |
79e53945 JB |
6480 | } |
6481 | ||
6482 | /* Currently we only support 64x64 cursors */ | |
6483 | if (width != 64 || height != 64) { | |
6484 | DRM_ERROR("we currently only support 64x64 cursors\n"); | |
6485 | return -EINVAL; | |
6486 | } | |
6487 | ||
05394f39 | 6488 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 6489 | if (&obj->base == NULL) |
79e53945 JB |
6490 | return -ENOENT; |
6491 | ||
05394f39 | 6492 | if (obj->base.size < width * height * 4) { |
79e53945 | 6493 | DRM_ERROR("buffer is to small\n"); |
34b8686e DA |
6494 | ret = -ENOMEM; |
6495 | goto fail; | |
79e53945 JB |
6496 | } |
6497 | ||
71acb5eb | 6498 | /* we only need to pin inside GTT if cursor is non-phy */ |
7f9872e0 | 6499 | mutex_lock(&dev->struct_mutex); |
b295d1b6 | 6500 | if (!dev_priv->info->cursor_needs_physical) { |
d9e86c0e CW |
6501 | if (obj->tiling_mode) { |
6502 | DRM_ERROR("cursor cannot be tiled\n"); | |
6503 | ret = -EINVAL; | |
6504 | goto fail_locked; | |
6505 | } | |
6506 | ||
2da3b9b9 | 6507 | ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL); |
e7b526bb CW |
6508 | if (ret) { |
6509 | DRM_ERROR("failed to move cursor bo into the GTT\n"); | |
2da3b9b9 | 6510 | goto fail_locked; |
e7b526bb CW |
6511 | } |
6512 | ||
d9e86c0e CW |
6513 | ret = i915_gem_object_put_fence(obj); |
6514 | if (ret) { | |
2da3b9b9 | 6515 | DRM_ERROR("failed to release fence for cursor"); |
d9e86c0e CW |
6516 | goto fail_unpin; |
6517 | } | |
6518 | ||
05394f39 | 6519 | addr = obj->gtt_offset; |
71acb5eb | 6520 | } else { |
6eeefaf3 | 6521 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
05394f39 | 6522 | ret = i915_gem_attach_phys_object(dev, obj, |
6eeefaf3 CW |
6523 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
6524 | align); | |
71acb5eb DA |
6525 | if (ret) { |
6526 | DRM_ERROR("failed to attach phys object\n"); | |
7f9872e0 | 6527 | goto fail_locked; |
71acb5eb | 6528 | } |
05394f39 | 6529 | addr = obj->phys_obj->handle->busaddr; |
3f8bc370 KH |
6530 | } |
6531 | ||
a6c45cf0 | 6532 | if (IS_GEN2(dev)) |
14b60391 JB |
6533 | I915_WRITE(CURSIZE, (height << 12) | width); |
6534 | ||
3f8bc370 | 6535 | finish: |
3f8bc370 | 6536 | if (intel_crtc->cursor_bo) { |
b295d1b6 | 6537 | if (dev_priv->info->cursor_needs_physical) { |
05394f39 | 6538 | if (intel_crtc->cursor_bo != obj) |
71acb5eb DA |
6539 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); |
6540 | } else | |
6541 | i915_gem_object_unpin(intel_crtc->cursor_bo); | |
05394f39 | 6542 | drm_gem_object_unreference(&intel_crtc->cursor_bo->base); |
3f8bc370 | 6543 | } |
80824003 | 6544 | |
7f9872e0 | 6545 | mutex_unlock(&dev->struct_mutex); |
3f8bc370 KH |
6546 | |
6547 | intel_crtc->cursor_addr = addr; | |
05394f39 | 6548 | intel_crtc->cursor_bo = obj; |
cda4b7d3 CW |
6549 | intel_crtc->cursor_width = width; |
6550 | intel_crtc->cursor_height = height; | |
6551 | ||
6b383a7f | 6552 | intel_crtc_update_cursor(crtc, true); |
3f8bc370 | 6553 | |
79e53945 | 6554 | return 0; |
e7b526bb | 6555 | fail_unpin: |
05394f39 | 6556 | i915_gem_object_unpin(obj); |
7f9872e0 | 6557 | fail_locked: |
34b8686e | 6558 | mutex_unlock(&dev->struct_mutex); |
bc9025bd | 6559 | fail: |
05394f39 | 6560 | drm_gem_object_unreference_unlocked(&obj->base); |
34b8686e | 6561 | return ret; |
79e53945 JB |
6562 | } |
6563 | ||
6564 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
6565 | { | |
79e53945 | 6566 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 6567 | |
cda4b7d3 CW |
6568 | intel_crtc->cursor_x = x; |
6569 | intel_crtc->cursor_y = y; | |
652c393a | 6570 | |
6b383a7f | 6571 | intel_crtc_update_cursor(crtc, true); |
79e53945 JB |
6572 | |
6573 | return 0; | |
6574 | } | |
6575 | ||
6576 | /** Sets the color ramps on behalf of RandR */ | |
6577 | void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, | |
6578 | u16 blue, int regno) | |
6579 | { | |
6580 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6581 | ||
6582 | intel_crtc->lut_r[regno] = red >> 8; | |
6583 | intel_crtc->lut_g[regno] = green >> 8; | |
6584 | intel_crtc->lut_b[regno] = blue >> 8; | |
6585 | } | |
6586 | ||
b8c00ac5 DA |
6587 | void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
6588 | u16 *blue, int regno) | |
6589 | { | |
6590 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6591 | ||
6592 | *red = intel_crtc->lut_r[regno] << 8; | |
6593 | *green = intel_crtc->lut_g[regno] << 8; | |
6594 | *blue = intel_crtc->lut_b[regno] << 8; | |
6595 | } | |
6596 | ||
79e53945 | 6597 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 6598 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 6599 | { |
7203425a | 6600 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 6601 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 6602 | |
7203425a | 6603 | for (i = start; i < end; i++) { |
79e53945 JB |
6604 | intel_crtc->lut_r[i] = red[i] >> 8; |
6605 | intel_crtc->lut_g[i] = green[i] >> 8; | |
6606 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
6607 | } | |
6608 | ||
6609 | intel_crtc_load_lut(crtc); | |
6610 | } | |
6611 | ||
6612 | /** | |
6613 | * Get a pipe with a simple mode set on it for doing load-based monitor | |
6614 | * detection. | |
6615 | * | |
6616 | * It will be up to the load-detect code to adjust the pipe as appropriate for | |
c751ce4f | 6617 | * its requirements. The pipe will be connected to no other encoders. |
79e53945 | 6618 | * |
c751ce4f | 6619 | * Currently this code will only succeed if there is a pipe with no encoders |
79e53945 JB |
6620 | * configured for it. In the future, it could choose to temporarily disable |
6621 | * some outputs to free up a pipe for its use. | |
6622 | * | |
6623 | * \return crtc, or NULL if no pipes are available. | |
6624 | */ | |
6625 | ||
6626 | /* VESA 640x480x72Hz mode to set on the pipe */ | |
6627 | static struct drm_display_mode load_detect_mode = { | |
6628 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
6629 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
6630 | }; | |
6631 | ||
d2dff872 CW |
6632 | static struct drm_framebuffer * |
6633 | intel_framebuffer_create(struct drm_device *dev, | |
308e5bcb | 6634 | struct drm_mode_fb_cmd2 *mode_cmd, |
d2dff872 CW |
6635 | struct drm_i915_gem_object *obj) |
6636 | { | |
6637 | struct intel_framebuffer *intel_fb; | |
6638 | int ret; | |
6639 | ||
6640 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
6641 | if (!intel_fb) { | |
6642 | drm_gem_object_unreference_unlocked(&obj->base); | |
6643 | return ERR_PTR(-ENOMEM); | |
6644 | } | |
6645 | ||
6646 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
6647 | if (ret) { | |
6648 | drm_gem_object_unreference_unlocked(&obj->base); | |
6649 | kfree(intel_fb); | |
6650 | return ERR_PTR(ret); | |
6651 | } | |
6652 | ||
6653 | return &intel_fb->base; | |
6654 | } | |
6655 | ||
6656 | static u32 | |
6657 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
6658 | { | |
6659 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
6660 | return ALIGN(pitch, 64); | |
6661 | } | |
6662 | ||
6663 | static u32 | |
6664 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
6665 | { | |
6666 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
6667 | return ALIGN(pitch * mode->vdisplay, PAGE_SIZE); | |
6668 | } | |
6669 | ||
6670 | static struct drm_framebuffer * | |
6671 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
6672 | struct drm_display_mode *mode, | |
6673 | int depth, int bpp) | |
6674 | { | |
6675 | struct drm_i915_gem_object *obj; | |
308e5bcb | 6676 | struct drm_mode_fb_cmd2 mode_cmd; |
d2dff872 CW |
6677 | |
6678 | obj = i915_gem_alloc_object(dev, | |
6679 | intel_framebuffer_size_for_mode(mode, bpp)); | |
6680 | if (obj == NULL) | |
6681 | return ERR_PTR(-ENOMEM); | |
6682 | ||
6683 | mode_cmd.width = mode->hdisplay; | |
6684 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
6685 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
6686 | bpp); | |
6687 | mode_cmd.pixel_format = 0; | |
d2dff872 CW |
6688 | |
6689 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
6690 | } | |
6691 | ||
6692 | static struct drm_framebuffer * | |
6693 | mode_fits_in_fbdev(struct drm_device *dev, | |
6694 | struct drm_display_mode *mode) | |
6695 | { | |
6696 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6697 | struct drm_i915_gem_object *obj; | |
6698 | struct drm_framebuffer *fb; | |
6699 | ||
6700 | if (dev_priv->fbdev == NULL) | |
6701 | return NULL; | |
6702 | ||
6703 | obj = dev_priv->fbdev->ifb.obj; | |
6704 | if (obj == NULL) | |
6705 | return NULL; | |
6706 | ||
6707 | fb = &dev_priv->fbdev->ifb.base; | |
01f2c773 VS |
6708 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
6709 | fb->bits_per_pixel)) | |
d2dff872 CW |
6710 | return NULL; |
6711 | ||
01f2c773 | 6712 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
6713 | return NULL; |
6714 | ||
6715 | return fb; | |
6716 | } | |
6717 | ||
7173188d CW |
6718 | bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder, |
6719 | struct drm_connector *connector, | |
6720 | struct drm_display_mode *mode, | |
8261b191 | 6721 | struct intel_load_detect_pipe *old) |
79e53945 JB |
6722 | { |
6723 | struct intel_crtc *intel_crtc; | |
6724 | struct drm_crtc *possible_crtc; | |
4ef69c7a | 6725 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
6726 | struct drm_crtc *crtc = NULL; |
6727 | struct drm_device *dev = encoder->dev; | |
d2dff872 | 6728 | struct drm_framebuffer *old_fb; |
79e53945 JB |
6729 | int i = -1; |
6730 | ||
d2dff872 CW |
6731 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
6732 | connector->base.id, drm_get_connector_name(connector), | |
6733 | encoder->base.id, drm_get_encoder_name(encoder)); | |
6734 | ||
79e53945 JB |
6735 | /* |
6736 | * Algorithm gets a little messy: | |
7a5e4805 | 6737 | * |
79e53945 JB |
6738 | * - if the connector already has an assigned crtc, use it (but make |
6739 | * sure it's on first) | |
7a5e4805 | 6740 | * |
79e53945 JB |
6741 | * - try to find the first unused crtc that can drive this connector, |
6742 | * and use that if we find one | |
79e53945 JB |
6743 | */ |
6744 | ||
6745 | /* See if we already have a CRTC for this connector */ | |
6746 | if (encoder->crtc) { | |
6747 | crtc = encoder->crtc; | |
8261b191 | 6748 | |
79e53945 | 6749 | intel_crtc = to_intel_crtc(crtc); |
8261b191 CW |
6750 | old->dpms_mode = intel_crtc->dpms_mode; |
6751 | old->load_detect_temp = false; | |
6752 | ||
6753 | /* Make sure the crtc and connector are running */ | |
79e53945 | 6754 | if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) { |
6492711d CW |
6755 | struct drm_encoder_helper_funcs *encoder_funcs; |
6756 | struct drm_crtc_helper_funcs *crtc_funcs; | |
6757 | ||
79e53945 JB |
6758 | crtc_funcs = crtc->helper_private; |
6759 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); | |
6492711d CW |
6760 | |
6761 | encoder_funcs = encoder->helper_private; | |
79e53945 JB |
6762 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); |
6763 | } | |
8261b191 | 6764 | |
7173188d | 6765 | return true; |
79e53945 JB |
6766 | } |
6767 | ||
6768 | /* Find an unused one (if possible) */ | |
6769 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { | |
6770 | i++; | |
6771 | if (!(encoder->possible_crtcs & (1 << i))) | |
6772 | continue; | |
6773 | if (!possible_crtc->enabled) { | |
6774 | crtc = possible_crtc; | |
6775 | break; | |
6776 | } | |
79e53945 JB |
6777 | } |
6778 | ||
6779 | /* | |
6780 | * If we didn't find an unused CRTC, don't use any. | |
6781 | */ | |
6782 | if (!crtc) { | |
7173188d CW |
6783 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
6784 | return false; | |
79e53945 JB |
6785 | } |
6786 | ||
6787 | encoder->crtc = crtc; | |
c1c43977 | 6788 | connector->encoder = encoder; |
79e53945 JB |
6789 | |
6790 | intel_crtc = to_intel_crtc(crtc); | |
8261b191 CW |
6791 | old->dpms_mode = intel_crtc->dpms_mode; |
6792 | old->load_detect_temp = true; | |
d2dff872 | 6793 | old->release_fb = NULL; |
79e53945 | 6794 | |
6492711d CW |
6795 | if (!mode) |
6796 | mode = &load_detect_mode; | |
79e53945 | 6797 | |
d2dff872 CW |
6798 | old_fb = crtc->fb; |
6799 | ||
6800 | /* We need a framebuffer large enough to accommodate all accesses | |
6801 | * that the plane may generate whilst we perform load detection. | |
6802 | * We can not rely on the fbcon either being present (we get called | |
6803 | * during its initialisation to detect all boot displays, or it may | |
6804 | * not even exist) or that it is large enough to satisfy the | |
6805 | * requested mode. | |
6806 | */ | |
6807 | crtc->fb = mode_fits_in_fbdev(dev, mode); | |
6808 | if (crtc->fb == NULL) { | |
6809 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); | |
6810 | crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); | |
6811 | old->release_fb = crtc->fb; | |
6812 | } else | |
6813 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
6814 | if (IS_ERR(crtc->fb)) { | |
6815 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); | |
6816 | crtc->fb = old_fb; | |
6817 | return false; | |
79e53945 | 6818 | } |
79e53945 | 6819 | |
d2dff872 | 6820 | if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) { |
6492711d | 6821 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
6822 | if (old->release_fb) |
6823 | old->release_fb->funcs->destroy(old->release_fb); | |
6824 | crtc->fb = old_fb; | |
6492711d | 6825 | return false; |
79e53945 | 6826 | } |
7173188d | 6827 | |
79e53945 | 6828 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 6829 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
79e53945 | 6830 | |
7173188d | 6831 | return true; |
79e53945 JB |
6832 | } |
6833 | ||
c1c43977 | 6834 | void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder, |
8261b191 CW |
6835 | struct drm_connector *connector, |
6836 | struct intel_load_detect_pipe *old) | |
79e53945 | 6837 | { |
4ef69c7a | 6838 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
6839 | struct drm_device *dev = encoder->dev; |
6840 | struct drm_crtc *crtc = encoder->crtc; | |
6841 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
6842 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
6843 | ||
d2dff872 CW |
6844 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
6845 | connector->base.id, drm_get_connector_name(connector), | |
6846 | encoder->base.id, drm_get_encoder_name(encoder)); | |
6847 | ||
8261b191 | 6848 | if (old->load_detect_temp) { |
c1c43977 | 6849 | connector->encoder = NULL; |
79e53945 | 6850 | drm_helper_disable_unused_functions(dev); |
d2dff872 CW |
6851 | |
6852 | if (old->release_fb) | |
6853 | old->release_fb->funcs->destroy(old->release_fb); | |
6854 | ||
0622a53c | 6855 | return; |
79e53945 JB |
6856 | } |
6857 | ||
c751ce4f | 6858 | /* Switch crtc and encoder back off if necessary */ |
0622a53c CW |
6859 | if (old->dpms_mode != DRM_MODE_DPMS_ON) { |
6860 | encoder_funcs->dpms(encoder, old->dpms_mode); | |
8261b191 | 6861 | crtc_funcs->dpms(crtc, old->dpms_mode); |
79e53945 JB |
6862 | } |
6863 | } | |
6864 | ||
6865 | /* Returns the clock of the currently programmed mode of the given pipe. */ | |
6866 | static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc) | |
6867 | { | |
6868 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6869 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6870 | int pipe = intel_crtc->pipe; | |
548f245b | 6871 | u32 dpll = I915_READ(DPLL(pipe)); |
79e53945 JB |
6872 | u32 fp; |
6873 | intel_clock_t clock; | |
6874 | ||
6875 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
39adb7a5 | 6876 | fp = I915_READ(FP0(pipe)); |
79e53945 | 6877 | else |
39adb7a5 | 6878 | fp = I915_READ(FP1(pipe)); |
79e53945 JB |
6879 | |
6880 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
6881 | if (IS_PINEVIEW(dev)) { |
6882 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
6883 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
6884 | } else { |
6885 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
6886 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
6887 | } | |
6888 | ||
a6c45cf0 | 6889 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
6890 | if (IS_PINEVIEW(dev)) |
6891 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
6892 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
6893 | else |
6894 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
6895 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
6896 | ||
6897 | switch (dpll & DPLL_MODE_MASK) { | |
6898 | case DPLLB_MODE_DAC_SERIAL: | |
6899 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
6900 | 5 : 10; | |
6901 | break; | |
6902 | case DPLLB_MODE_LVDS: | |
6903 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
6904 | 7 : 14; | |
6905 | break; | |
6906 | default: | |
28c97730 | 6907 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 JB |
6908 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
6909 | return 0; | |
6910 | } | |
6911 | ||
6912 | /* XXX: Handle the 100Mhz refclk */ | |
2177832f | 6913 | intel_clock(dev, 96000, &clock); |
79e53945 JB |
6914 | } else { |
6915 | bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); | |
6916 | ||
6917 | if (is_lvds) { | |
6918 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
6919 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
6920 | clock.p2 = 14; | |
6921 | ||
6922 | if ((dpll & PLL_REF_INPUT_MASK) == | |
6923 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
6924 | /* XXX: might not be 66MHz */ | |
2177832f | 6925 | intel_clock(dev, 66000, &clock); |
79e53945 | 6926 | } else |
2177832f | 6927 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
6928 | } else { |
6929 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
6930 | clock.p1 = 2; | |
6931 | else { | |
6932 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
6933 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
6934 | } | |
6935 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
6936 | clock.p2 = 4; | |
6937 | else | |
6938 | clock.p2 = 2; | |
6939 | ||
2177832f | 6940 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
6941 | } |
6942 | } | |
6943 | ||
6944 | /* XXX: It would be nice to validate the clocks, but we can't reuse | |
6945 | * i830PllIsValid() because it relies on the xf86_config connector | |
6946 | * configuration being accurate, which it isn't necessarily. | |
6947 | */ | |
6948 | ||
6949 | return clock.dot; | |
6950 | } | |
6951 | ||
6952 | /** Returns the currently programmed mode of the given pipe. */ | |
6953 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
6954 | struct drm_crtc *crtc) | |
6955 | { | |
548f245b | 6956 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 JB |
6957 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6958 | int pipe = intel_crtc->pipe; | |
6959 | struct drm_display_mode *mode; | |
548f245b JB |
6960 | int htot = I915_READ(HTOTAL(pipe)); |
6961 | int hsync = I915_READ(HSYNC(pipe)); | |
6962 | int vtot = I915_READ(VTOTAL(pipe)); | |
6963 | int vsync = I915_READ(VSYNC(pipe)); | |
79e53945 JB |
6964 | |
6965 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
6966 | if (!mode) | |
6967 | return NULL; | |
6968 | ||
6969 | mode->clock = intel_crtc_clock_get(dev, crtc); | |
6970 | mode->hdisplay = (htot & 0xffff) + 1; | |
6971 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
6972 | mode->hsync_start = (hsync & 0xffff) + 1; | |
6973 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
6974 | mode->vdisplay = (vtot & 0xffff) + 1; | |
6975 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
6976 | mode->vsync_start = (vsync & 0xffff) + 1; | |
6977 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
6978 | ||
6979 | drm_mode_set_name(mode); | |
6980 | drm_mode_set_crtcinfo(mode, 0); | |
6981 | ||
6982 | return mode; | |
6983 | } | |
6984 | ||
652c393a JB |
6985 | #define GPU_IDLE_TIMEOUT 500 /* ms */ |
6986 | ||
6987 | /* When this timer fires, we've been idle for awhile */ | |
6988 | static void intel_gpu_idle_timer(unsigned long arg) | |
6989 | { | |
6990 | struct drm_device *dev = (struct drm_device *)arg; | |
6991 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6992 | ||
ff7ea4c0 CW |
6993 | if (!list_empty(&dev_priv->mm.active_list)) { |
6994 | /* Still processing requests, so just re-arm the timer. */ | |
6995 | mod_timer(&dev_priv->idle_timer, jiffies + | |
6996 | msecs_to_jiffies(GPU_IDLE_TIMEOUT)); | |
6997 | return; | |
6998 | } | |
652c393a | 6999 | |
ff7ea4c0 | 7000 | dev_priv->busy = false; |
01dfba93 | 7001 | queue_work(dev_priv->wq, &dev_priv->idle_work); |
652c393a JB |
7002 | } |
7003 | ||
652c393a JB |
7004 | #define CRTC_IDLE_TIMEOUT 1000 /* ms */ |
7005 | ||
7006 | static void intel_crtc_idle_timer(unsigned long arg) | |
7007 | { | |
7008 | struct intel_crtc *intel_crtc = (struct intel_crtc *)arg; | |
7009 | struct drm_crtc *crtc = &intel_crtc->base; | |
7010 | drm_i915_private_t *dev_priv = crtc->dev->dev_private; | |
ff7ea4c0 | 7011 | struct intel_framebuffer *intel_fb; |
652c393a | 7012 | |
ff7ea4c0 CW |
7013 | intel_fb = to_intel_framebuffer(crtc->fb); |
7014 | if (intel_fb && intel_fb->obj->active) { | |
7015 | /* The framebuffer is still being accessed by the GPU. */ | |
7016 | mod_timer(&intel_crtc->idle_timer, jiffies + | |
7017 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); | |
7018 | return; | |
7019 | } | |
652c393a | 7020 | |
ff7ea4c0 | 7021 | intel_crtc->busy = false; |
01dfba93 | 7022 | queue_work(dev_priv->wq, &dev_priv->idle_work); |
652c393a JB |
7023 | } |
7024 | ||
3dec0095 | 7025 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
652c393a JB |
7026 | { |
7027 | struct drm_device *dev = crtc->dev; | |
7028 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7029 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7030 | int pipe = intel_crtc->pipe; | |
dbdc6479 JB |
7031 | int dpll_reg = DPLL(pipe); |
7032 | int dpll; | |
652c393a | 7033 | |
bad720ff | 7034 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
7035 | return; |
7036 | ||
7037 | if (!dev_priv->lvds_downclock_avail) | |
7038 | return; | |
7039 | ||
dbdc6479 | 7040 | dpll = I915_READ(dpll_reg); |
652c393a | 7041 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
44d98a61 | 7042 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
652c393a | 7043 | |
8ac5a6d5 | 7044 | assert_panel_unlocked(dev_priv, pipe); |
652c393a JB |
7045 | |
7046 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; | |
7047 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 7048 | intel_wait_for_vblank(dev, pipe); |
dbdc6479 | 7049 | |
652c393a JB |
7050 | dpll = I915_READ(dpll_reg); |
7051 | if (dpll & DISPLAY_RATE_SELECT_FPA1) | |
44d98a61 | 7052 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
652c393a JB |
7053 | } |
7054 | ||
7055 | /* Schedule downclock */ | |
3dec0095 DV |
7056 | mod_timer(&intel_crtc->idle_timer, jiffies + |
7057 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); | |
652c393a JB |
7058 | } |
7059 | ||
7060 | static void intel_decrease_pllclock(struct drm_crtc *crtc) | |
7061 | { | |
7062 | struct drm_device *dev = crtc->dev; | |
7063 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7064 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7065 | int pipe = intel_crtc->pipe; | |
9db4a9c7 | 7066 | int dpll_reg = DPLL(pipe); |
652c393a JB |
7067 | int dpll = I915_READ(dpll_reg); |
7068 | ||
bad720ff | 7069 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
7070 | return; |
7071 | ||
7072 | if (!dev_priv->lvds_downclock_avail) | |
7073 | return; | |
7074 | ||
7075 | /* | |
7076 | * Since this is called by a timer, we should never get here in | |
7077 | * the manual case. | |
7078 | */ | |
7079 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
44d98a61 | 7080 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 7081 | |
8ac5a6d5 | 7082 | assert_panel_unlocked(dev_priv, pipe); |
652c393a JB |
7083 | |
7084 | dpll |= DISPLAY_RATE_SELECT_FPA1; | |
7085 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 7086 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
7087 | dpll = I915_READ(dpll_reg); |
7088 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 7089 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
7090 | } |
7091 | ||
7092 | } | |
7093 | ||
7094 | /** | |
7095 | * intel_idle_update - adjust clocks for idleness | |
7096 | * @work: work struct | |
7097 | * | |
7098 | * Either the GPU or display (or both) went idle. Check the busy status | |
7099 | * here and adjust the CRTC and GPU clocks as necessary. | |
7100 | */ | |
7101 | static void intel_idle_update(struct work_struct *work) | |
7102 | { | |
7103 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
7104 | idle_work); | |
7105 | struct drm_device *dev = dev_priv->dev; | |
7106 | struct drm_crtc *crtc; | |
7107 | struct intel_crtc *intel_crtc; | |
7108 | ||
7109 | if (!i915_powersave) | |
7110 | return; | |
7111 | ||
7112 | mutex_lock(&dev->struct_mutex); | |
7113 | ||
7648fa99 JB |
7114 | i915_update_gfx_val(dev_priv); |
7115 | ||
652c393a JB |
7116 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
7117 | /* Skip inactive CRTCs */ | |
7118 | if (!crtc->fb) | |
7119 | continue; | |
7120 | ||
7121 | intel_crtc = to_intel_crtc(crtc); | |
7122 | if (!intel_crtc->busy) | |
7123 | intel_decrease_pllclock(crtc); | |
7124 | } | |
7125 | ||
45ac22c8 | 7126 | |
652c393a JB |
7127 | mutex_unlock(&dev->struct_mutex); |
7128 | } | |
7129 | ||
7130 | /** | |
7131 | * intel_mark_busy - mark the GPU and possibly the display busy | |
7132 | * @dev: drm device | |
7133 | * @obj: object we're operating on | |
7134 | * | |
7135 | * Callers can use this function to indicate that the GPU is busy processing | |
7136 | * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout | |
7137 | * buffer), we'll also mark the display as busy, so we know to increase its | |
7138 | * clock frequency. | |
7139 | */ | |
05394f39 | 7140 | void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj) |
652c393a JB |
7141 | { |
7142 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7143 | struct drm_crtc *crtc = NULL; | |
7144 | struct intel_framebuffer *intel_fb; | |
7145 | struct intel_crtc *intel_crtc; | |
7146 | ||
5e17ee74 ZW |
7147 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
7148 | return; | |
7149 | ||
18b2190c | 7150 | if (!dev_priv->busy) |
28cf798f | 7151 | dev_priv->busy = true; |
18b2190c | 7152 | else |
28cf798f CW |
7153 | mod_timer(&dev_priv->idle_timer, jiffies + |
7154 | msecs_to_jiffies(GPU_IDLE_TIMEOUT)); | |
652c393a JB |
7155 | |
7156 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
7157 | if (!crtc->fb) | |
7158 | continue; | |
7159 | ||
7160 | intel_crtc = to_intel_crtc(crtc); | |
7161 | intel_fb = to_intel_framebuffer(crtc->fb); | |
7162 | if (intel_fb->obj == obj) { | |
7163 | if (!intel_crtc->busy) { | |
7164 | /* Non-busy -> busy, upclock */ | |
3dec0095 | 7165 | intel_increase_pllclock(crtc); |
652c393a JB |
7166 | intel_crtc->busy = true; |
7167 | } else { | |
7168 | /* Busy -> busy, put off timer */ | |
7169 | mod_timer(&intel_crtc->idle_timer, jiffies + | |
7170 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); | |
7171 | } | |
7172 | } | |
7173 | } | |
7174 | } | |
7175 | ||
79e53945 JB |
7176 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
7177 | { | |
7178 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
7179 | struct drm_device *dev = crtc->dev; |
7180 | struct intel_unpin_work *work; | |
7181 | unsigned long flags; | |
7182 | ||
7183 | spin_lock_irqsave(&dev->event_lock, flags); | |
7184 | work = intel_crtc->unpin_work; | |
7185 | intel_crtc->unpin_work = NULL; | |
7186 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
7187 | ||
7188 | if (work) { | |
7189 | cancel_work_sync(&work->work); | |
7190 | kfree(work); | |
7191 | } | |
79e53945 JB |
7192 | |
7193 | drm_crtc_cleanup(crtc); | |
67e77c5a | 7194 | |
79e53945 JB |
7195 | kfree(intel_crtc); |
7196 | } | |
7197 | ||
6b95a207 KH |
7198 | static void intel_unpin_work_fn(struct work_struct *__work) |
7199 | { | |
7200 | struct intel_unpin_work *work = | |
7201 | container_of(__work, struct intel_unpin_work, work); | |
7202 | ||
7203 | mutex_lock(&work->dev->struct_mutex); | |
1690e1eb | 7204 | intel_unpin_fb_obj(work->old_fb_obj); |
05394f39 CW |
7205 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
7206 | drm_gem_object_unreference(&work->old_fb_obj->base); | |
d9e86c0e | 7207 | |
7782de3b | 7208 | intel_update_fbc(work->dev); |
6b95a207 KH |
7209 | mutex_unlock(&work->dev->struct_mutex); |
7210 | kfree(work); | |
7211 | } | |
7212 | ||
1afe3e9d | 7213 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 7214 | struct drm_crtc *crtc) |
6b95a207 KH |
7215 | { |
7216 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6b95a207 KH |
7217 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7218 | struct intel_unpin_work *work; | |
05394f39 | 7219 | struct drm_i915_gem_object *obj; |
6b95a207 | 7220 | struct drm_pending_vblank_event *e; |
49b14a5c | 7221 | struct timeval tnow, tvbl; |
6b95a207 KH |
7222 | unsigned long flags; |
7223 | ||
7224 | /* Ignore early vblank irqs */ | |
7225 | if (intel_crtc == NULL) | |
7226 | return; | |
7227 | ||
49b14a5c MK |
7228 | do_gettimeofday(&tnow); |
7229 | ||
6b95a207 KH |
7230 | spin_lock_irqsave(&dev->event_lock, flags); |
7231 | work = intel_crtc->unpin_work; | |
7232 | if (work == NULL || !work->pending) { | |
7233 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
7234 | return; | |
7235 | } | |
7236 | ||
7237 | intel_crtc->unpin_work = NULL; | |
6b95a207 KH |
7238 | |
7239 | if (work->event) { | |
7240 | e = work->event; | |
49b14a5c | 7241 | e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl); |
0af7e4df MK |
7242 | |
7243 | /* Called before vblank count and timestamps have | |
7244 | * been updated for the vblank interval of flip | |
7245 | * completion? Need to increment vblank count and | |
7246 | * add one videorefresh duration to returned timestamp | |
49b14a5c MK |
7247 | * to account for this. We assume this happened if we |
7248 | * get called over 0.9 frame durations after the last | |
7249 | * timestamped vblank. | |
7250 | * | |
7251 | * This calculation can not be used with vrefresh rates | |
7252 | * below 5Hz (10Hz to be on the safe side) without | |
7253 | * promoting to 64 integers. | |
0af7e4df | 7254 | */ |
49b14a5c MK |
7255 | if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) > |
7256 | 9 * crtc->framedur_ns) { | |
0af7e4df | 7257 | e->event.sequence++; |
49b14a5c MK |
7258 | tvbl = ns_to_timeval(timeval_to_ns(&tvbl) + |
7259 | crtc->framedur_ns); | |
0af7e4df MK |
7260 | } |
7261 | ||
49b14a5c MK |
7262 | e->event.tv_sec = tvbl.tv_sec; |
7263 | e->event.tv_usec = tvbl.tv_usec; | |
0af7e4df | 7264 | |
6b95a207 KH |
7265 | list_add_tail(&e->base.link, |
7266 | &e->base.file_priv->event_list); | |
7267 | wake_up_interruptible(&e->base.file_priv->event_wait); | |
7268 | } | |
7269 | ||
0af7e4df MK |
7270 | drm_vblank_put(dev, intel_crtc->pipe); |
7271 | ||
6b95a207 KH |
7272 | spin_unlock_irqrestore(&dev->event_lock, flags); |
7273 | ||
05394f39 | 7274 | obj = work->old_fb_obj; |
d9e86c0e | 7275 | |
e59f2bac | 7276 | atomic_clear_mask(1 << intel_crtc->plane, |
05394f39 CW |
7277 | &obj->pending_flip.counter); |
7278 | if (atomic_read(&obj->pending_flip) == 0) | |
f787a5f5 | 7279 | wake_up(&dev_priv->pending_flip_queue); |
d9e86c0e | 7280 | |
6b95a207 | 7281 | schedule_work(&work->work); |
e5510fac JB |
7282 | |
7283 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); | |
6b95a207 KH |
7284 | } |
7285 | ||
1afe3e9d JB |
7286 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
7287 | { | |
7288 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7289 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
7290 | ||
49b14a5c | 7291 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
7292 | } |
7293 | ||
7294 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
7295 | { | |
7296 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7297 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; | |
7298 | ||
49b14a5c | 7299 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
7300 | } |
7301 | ||
6b95a207 KH |
7302 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
7303 | { | |
7304 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7305 | struct intel_crtc *intel_crtc = | |
7306 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
7307 | unsigned long flags; | |
7308 | ||
7309 | spin_lock_irqsave(&dev->event_lock, flags); | |
de3f440f | 7310 | if (intel_crtc->unpin_work) { |
4e5359cd SF |
7311 | if ((++intel_crtc->unpin_work->pending) > 1) |
7312 | DRM_ERROR("Prepared flip multiple times\n"); | |
de3f440f JB |
7313 | } else { |
7314 | DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n"); | |
7315 | } | |
6b95a207 KH |
7316 | spin_unlock_irqrestore(&dev->event_lock, flags); |
7317 | } | |
7318 | ||
8c9f3aaf JB |
7319 | static int intel_gen2_queue_flip(struct drm_device *dev, |
7320 | struct drm_crtc *crtc, | |
7321 | struct drm_framebuffer *fb, | |
7322 | struct drm_i915_gem_object *obj) | |
7323 | { | |
7324 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7325 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7326 | unsigned long offset; | |
7327 | u32 flip_mask; | |
7328 | int ret; | |
7329 | ||
7330 | ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); | |
7331 | if (ret) | |
7332 | goto out; | |
7333 | ||
7334 | /* Offset into the new buffer for cases of shared fbs between CRTCs */ | |
01f2c773 | 7335 | offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8; |
8c9f3aaf JB |
7336 | |
7337 | ret = BEGIN_LP_RING(6); | |
7338 | if (ret) | |
7339 | goto out; | |
7340 | ||
7341 | /* Can't queue multiple flips, so wait for the previous | |
7342 | * one to finish before executing the next. | |
7343 | */ | |
7344 | if (intel_crtc->plane) | |
7345 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
7346 | else | |
7347 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
7348 | OUT_RING(MI_WAIT_FOR_EVENT | flip_mask); | |
7349 | OUT_RING(MI_NOOP); | |
7350 | OUT_RING(MI_DISPLAY_FLIP | | |
7351 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
01f2c773 | 7352 | OUT_RING(fb->pitches[0]); |
8c9f3aaf | 7353 | OUT_RING(obj->gtt_offset + offset); |
c6a32fcb | 7354 | OUT_RING(0); /* aux display base address, unused */ |
8c9f3aaf JB |
7355 | ADVANCE_LP_RING(); |
7356 | out: | |
7357 | return ret; | |
7358 | } | |
7359 | ||
7360 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
7361 | struct drm_crtc *crtc, | |
7362 | struct drm_framebuffer *fb, | |
7363 | struct drm_i915_gem_object *obj) | |
7364 | { | |
7365 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7366 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7367 | unsigned long offset; | |
7368 | u32 flip_mask; | |
7369 | int ret; | |
7370 | ||
7371 | ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); | |
7372 | if (ret) | |
7373 | goto out; | |
7374 | ||
7375 | /* Offset into the new buffer for cases of shared fbs between CRTCs */ | |
01f2c773 | 7376 | offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8; |
8c9f3aaf JB |
7377 | |
7378 | ret = BEGIN_LP_RING(6); | |
7379 | if (ret) | |
7380 | goto out; | |
7381 | ||
7382 | if (intel_crtc->plane) | |
7383 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
7384 | else | |
7385 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
7386 | OUT_RING(MI_WAIT_FOR_EVENT | flip_mask); | |
7387 | OUT_RING(MI_NOOP); | |
7388 | OUT_RING(MI_DISPLAY_FLIP_I915 | | |
7389 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
01f2c773 | 7390 | OUT_RING(fb->pitches[0]); |
8c9f3aaf JB |
7391 | OUT_RING(obj->gtt_offset + offset); |
7392 | OUT_RING(MI_NOOP); | |
7393 | ||
7394 | ADVANCE_LP_RING(); | |
7395 | out: | |
7396 | return ret; | |
7397 | } | |
7398 | ||
7399 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
7400 | struct drm_crtc *crtc, | |
7401 | struct drm_framebuffer *fb, | |
7402 | struct drm_i915_gem_object *obj) | |
7403 | { | |
7404 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7405 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7406 | uint32_t pf, pipesrc; | |
7407 | int ret; | |
7408 | ||
7409 | ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); | |
7410 | if (ret) | |
7411 | goto out; | |
7412 | ||
7413 | ret = BEGIN_LP_RING(4); | |
7414 | if (ret) | |
7415 | goto out; | |
7416 | ||
7417 | /* i965+ uses the linear or tiled offsets from the | |
7418 | * Display Registers (which do not change across a page-flip) | |
7419 | * so we need only reprogram the base address. | |
7420 | */ | |
7421 | OUT_RING(MI_DISPLAY_FLIP | | |
7422 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
01f2c773 | 7423 | OUT_RING(fb->pitches[0]); |
8c9f3aaf JB |
7424 | OUT_RING(obj->gtt_offset | obj->tiling_mode); |
7425 | ||
7426 | /* XXX Enabling the panel-fitter across page-flip is so far | |
7427 | * untested on non-native modes, so ignore it for now. | |
7428 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
7429 | */ | |
7430 | pf = 0; | |
7431 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
7432 | OUT_RING(pf | pipesrc); | |
7433 | ADVANCE_LP_RING(); | |
7434 | out: | |
7435 | return ret; | |
7436 | } | |
7437 | ||
7438 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
7439 | struct drm_crtc *crtc, | |
7440 | struct drm_framebuffer *fb, | |
7441 | struct drm_i915_gem_object *obj) | |
7442 | { | |
7443 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7444 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7445 | uint32_t pf, pipesrc; | |
7446 | int ret; | |
7447 | ||
7448 | ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); | |
7449 | if (ret) | |
7450 | goto out; | |
7451 | ||
7452 | ret = BEGIN_LP_RING(4); | |
7453 | if (ret) | |
7454 | goto out; | |
7455 | ||
7456 | OUT_RING(MI_DISPLAY_FLIP | | |
7457 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
01f2c773 | 7458 | OUT_RING(fb->pitches[0] | obj->tiling_mode); |
8c9f3aaf JB |
7459 | OUT_RING(obj->gtt_offset); |
7460 | ||
7461 | pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
7462 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
7463 | OUT_RING(pf | pipesrc); | |
7464 | ADVANCE_LP_RING(); | |
7465 | out: | |
7466 | return ret; | |
7467 | } | |
7468 | ||
7c9017e5 JB |
7469 | /* |
7470 | * On gen7 we currently use the blit ring because (in early silicon at least) | |
7471 | * the render ring doesn't give us interrpts for page flip completion, which | |
7472 | * means clients will hang after the first flip is queued. Fortunately the | |
7473 | * blit ring generates interrupts properly, so use it instead. | |
7474 | */ | |
7475 | static int intel_gen7_queue_flip(struct drm_device *dev, | |
7476 | struct drm_crtc *crtc, | |
7477 | struct drm_framebuffer *fb, | |
7478 | struct drm_i915_gem_object *obj) | |
7479 | { | |
7480 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7481 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7482 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; | |
7483 | int ret; | |
7484 | ||
7485 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); | |
7486 | if (ret) | |
7487 | goto out; | |
7488 | ||
7489 | ret = intel_ring_begin(ring, 4); | |
7490 | if (ret) | |
7491 | goto out; | |
7492 | ||
7493 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19)); | |
01f2c773 | 7494 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
7c9017e5 JB |
7495 | intel_ring_emit(ring, (obj->gtt_offset)); |
7496 | intel_ring_emit(ring, (MI_NOOP)); | |
7497 | intel_ring_advance(ring); | |
7498 | out: | |
7499 | return ret; | |
7500 | } | |
7501 | ||
8c9f3aaf JB |
7502 | static int intel_default_queue_flip(struct drm_device *dev, |
7503 | struct drm_crtc *crtc, | |
7504 | struct drm_framebuffer *fb, | |
7505 | struct drm_i915_gem_object *obj) | |
7506 | { | |
7507 | return -ENODEV; | |
7508 | } | |
7509 | ||
6b95a207 KH |
7510 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
7511 | struct drm_framebuffer *fb, | |
7512 | struct drm_pending_vblank_event *event) | |
7513 | { | |
7514 | struct drm_device *dev = crtc->dev; | |
7515 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7516 | struct intel_framebuffer *intel_fb; | |
05394f39 | 7517 | struct drm_i915_gem_object *obj; |
6b95a207 KH |
7518 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7519 | struct intel_unpin_work *work; | |
8c9f3aaf | 7520 | unsigned long flags; |
52e68630 | 7521 | int ret; |
6b95a207 KH |
7522 | |
7523 | work = kzalloc(sizeof *work, GFP_KERNEL); | |
7524 | if (work == NULL) | |
7525 | return -ENOMEM; | |
7526 | ||
6b95a207 KH |
7527 | work->event = event; |
7528 | work->dev = crtc->dev; | |
7529 | intel_fb = to_intel_framebuffer(crtc->fb); | |
b1b87f6b | 7530 | work->old_fb_obj = intel_fb->obj; |
6b95a207 KH |
7531 | INIT_WORK(&work->work, intel_unpin_work_fn); |
7532 | ||
7317c75e JB |
7533 | ret = drm_vblank_get(dev, intel_crtc->pipe); |
7534 | if (ret) | |
7535 | goto free_work; | |
7536 | ||
6b95a207 KH |
7537 | /* We borrow the event spin lock for protecting unpin_work */ |
7538 | spin_lock_irqsave(&dev->event_lock, flags); | |
7539 | if (intel_crtc->unpin_work) { | |
7540 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
7541 | kfree(work); | |
7317c75e | 7542 | drm_vblank_put(dev, intel_crtc->pipe); |
468f0b44 CW |
7543 | |
7544 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
6b95a207 KH |
7545 | return -EBUSY; |
7546 | } | |
7547 | intel_crtc->unpin_work = work; | |
7548 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
7549 | ||
7550 | intel_fb = to_intel_framebuffer(fb); | |
7551 | obj = intel_fb->obj; | |
7552 | ||
468f0b44 | 7553 | mutex_lock(&dev->struct_mutex); |
6b95a207 | 7554 | |
75dfca80 | 7555 | /* Reference the objects for the scheduled work. */ |
05394f39 CW |
7556 | drm_gem_object_reference(&work->old_fb_obj->base); |
7557 | drm_gem_object_reference(&obj->base); | |
6b95a207 KH |
7558 | |
7559 | crtc->fb = fb; | |
96b099fd | 7560 | |
e1f99ce6 | 7561 | work->pending_flip_obj = obj; |
e1f99ce6 | 7562 | |
4e5359cd SF |
7563 | work->enable_stall_check = true; |
7564 | ||
e1f99ce6 CW |
7565 | /* Block clients from rendering to the new back buffer until |
7566 | * the flip occurs and the object is no longer visible. | |
7567 | */ | |
05394f39 | 7568 | atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip); |
e1f99ce6 | 7569 | |
8c9f3aaf JB |
7570 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj); |
7571 | if (ret) | |
7572 | goto cleanup_pending; | |
6b95a207 | 7573 | |
7782de3b | 7574 | intel_disable_fbc(dev); |
6b95a207 KH |
7575 | mutex_unlock(&dev->struct_mutex); |
7576 | ||
e5510fac JB |
7577 | trace_i915_flip_request(intel_crtc->plane, obj); |
7578 | ||
6b95a207 | 7579 | return 0; |
96b099fd | 7580 | |
8c9f3aaf JB |
7581 | cleanup_pending: |
7582 | atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip); | |
05394f39 CW |
7583 | drm_gem_object_unreference(&work->old_fb_obj->base); |
7584 | drm_gem_object_unreference(&obj->base); | |
96b099fd CW |
7585 | mutex_unlock(&dev->struct_mutex); |
7586 | ||
7587 | spin_lock_irqsave(&dev->event_lock, flags); | |
7588 | intel_crtc->unpin_work = NULL; | |
7589 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
7590 | ||
7317c75e JB |
7591 | drm_vblank_put(dev, intel_crtc->pipe); |
7592 | free_work: | |
96b099fd CW |
7593 | kfree(work); |
7594 | ||
7595 | return ret; | |
6b95a207 KH |
7596 | } |
7597 | ||
47f1c6c9 CW |
7598 | static void intel_sanitize_modesetting(struct drm_device *dev, |
7599 | int pipe, int plane) | |
7600 | { | |
7601 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7602 | u32 reg, val; | |
7603 | ||
7604 | if (HAS_PCH_SPLIT(dev)) | |
7605 | return; | |
7606 | ||
7607 | /* Who knows what state these registers were left in by the BIOS or | |
7608 | * grub? | |
7609 | * | |
7610 | * If we leave the registers in a conflicting state (e.g. with the | |
7611 | * display plane reading from the other pipe than the one we intend | |
7612 | * to use) then when we attempt to teardown the active mode, we will | |
7613 | * not disable the pipes and planes in the correct order -- leaving | |
7614 | * a plane reading from a disabled pipe and possibly leading to | |
7615 | * undefined behaviour. | |
7616 | */ | |
7617 | ||
7618 | reg = DSPCNTR(plane); | |
7619 | val = I915_READ(reg); | |
7620 | ||
7621 | if ((val & DISPLAY_PLANE_ENABLE) == 0) | |
7622 | return; | |
7623 | if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe) | |
7624 | return; | |
7625 | ||
7626 | /* This display plane is active and attached to the other CPU pipe. */ | |
7627 | pipe = !pipe; | |
7628 | ||
7629 | /* Disable the plane and wait for it to stop reading from the pipe. */ | |
b24e7179 JB |
7630 | intel_disable_plane(dev_priv, plane, pipe); |
7631 | intel_disable_pipe(dev_priv, pipe); | |
47f1c6c9 | 7632 | } |
79e53945 | 7633 | |
f6e5b160 CW |
7634 | static void intel_crtc_reset(struct drm_crtc *crtc) |
7635 | { | |
7636 | struct drm_device *dev = crtc->dev; | |
7637 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7638 | ||
7639 | /* Reset flags back to the 'unknown' status so that they | |
7640 | * will be correctly set on the initial modeset. | |
7641 | */ | |
7642 | intel_crtc->dpms_mode = -1; | |
7643 | ||
7644 | /* We need to fix up any BIOS configuration that conflicts with | |
7645 | * our expectations. | |
7646 | */ | |
7647 | intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane); | |
7648 | } | |
7649 | ||
7650 | static struct drm_crtc_helper_funcs intel_helper_funcs = { | |
7651 | .dpms = intel_crtc_dpms, | |
7652 | .mode_fixup = intel_crtc_mode_fixup, | |
7653 | .mode_set = intel_crtc_mode_set, | |
7654 | .mode_set_base = intel_pipe_set_base, | |
7655 | .mode_set_base_atomic = intel_pipe_set_base_atomic, | |
7656 | .load_lut = intel_crtc_load_lut, | |
7657 | .disable = intel_crtc_disable, | |
7658 | }; | |
7659 | ||
7660 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
7661 | .reset = intel_crtc_reset, | |
7662 | .cursor_set = intel_crtc_cursor_set, | |
7663 | .cursor_move = intel_crtc_cursor_move, | |
7664 | .gamma_set = intel_crtc_gamma_set, | |
7665 | .set_config = drm_crtc_helper_set_config, | |
7666 | .destroy = intel_crtc_destroy, | |
7667 | .page_flip = intel_crtc_page_flip, | |
7668 | }; | |
7669 | ||
b358d0a6 | 7670 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 7671 | { |
22fd0fab | 7672 | drm_i915_private_t *dev_priv = dev->dev_private; |
79e53945 JB |
7673 | struct intel_crtc *intel_crtc; |
7674 | int i; | |
7675 | ||
7676 | intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); | |
7677 | if (intel_crtc == NULL) | |
7678 | return; | |
7679 | ||
7680 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); | |
7681 | ||
7682 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
7683 | for (i = 0; i < 256; i++) { |
7684 | intel_crtc->lut_r[i] = i; | |
7685 | intel_crtc->lut_g[i] = i; | |
7686 | intel_crtc->lut_b[i] = i; | |
7687 | } | |
7688 | ||
80824003 JB |
7689 | /* Swap pipes & planes for FBC on pre-965 */ |
7690 | intel_crtc->pipe = pipe; | |
7691 | intel_crtc->plane = pipe; | |
e2e767ab | 7692 | if (IS_MOBILE(dev) && IS_GEN3(dev)) { |
28c97730 | 7693 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 7694 | intel_crtc->plane = !pipe; |
80824003 JB |
7695 | } |
7696 | ||
22fd0fab JB |
7697 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
7698 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
7699 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
7700 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
7701 | ||
5d1d0cc8 | 7702 | intel_crtc_reset(&intel_crtc->base); |
04dbff52 | 7703 | intel_crtc->active = true; /* force the pipe off on setup_init_config */ |
5a354204 | 7704 | intel_crtc->bpp = 24; /* default for pre-Ironlake */ |
7e7d76c3 JB |
7705 | |
7706 | if (HAS_PCH_SPLIT(dev)) { | |
4b645f14 JB |
7707 | if (pipe == 2 && IS_IVYBRIDGE(dev)) |
7708 | intel_crtc->no_pll = true; | |
7e7d76c3 JB |
7709 | intel_helper_funcs.prepare = ironlake_crtc_prepare; |
7710 | intel_helper_funcs.commit = ironlake_crtc_commit; | |
7711 | } else { | |
7712 | intel_helper_funcs.prepare = i9xx_crtc_prepare; | |
7713 | intel_helper_funcs.commit = i9xx_crtc_commit; | |
7714 | } | |
7715 | ||
79e53945 JB |
7716 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
7717 | ||
652c393a JB |
7718 | intel_crtc->busy = false; |
7719 | ||
7720 | setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer, | |
7721 | (unsigned long)intel_crtc); | |
79e53945 JB |
7722 | } |
7723 | ||
08d7b3d1 | 7724 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 7725 | struct drm_file *file) |
08d7b3d1 CW |
7726 | { |
7727 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7728 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; | |
c05422d5 DV |
7729 | struct drm_mode_object *drmmode_obj; |
7730 | struct intel_crtc *crtc; | |
08d7b3d1 CW |
7731 | |
7732 | if (!dev_priv) { | |
7733 | DRM_ERROR("called with no initialization\n"); | |
7734 | return -EINVAL; | |
7735 | } | |
7736 | ||
c05422d5 DV |
7737 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
7738 | DRM_MODE_OBJECT_CRTC); | |
08d7b3d1 | 7739 | |
c05422d5 | 7740 | if (!drmmode_obj) { |
08d7b3d1 CW |
7741 | DRM_ERROR("no such CRTC id\n"); |
7742 | return -EINVAL; | |
7743 | } | |
7744 | ||
c05422d5 DV |
7745 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
7746 | pipe_from_crtc_id->pipe = crtc->pipe; | |
08d7b3d1 | 7747 | |
c05422d5 | 7748 | return 0; |
08d7b3d1 CW |
7749 | } |
7750 | ||
c5e4df33 | 7751 | static int intel_encoder_clones(struct drm_device *dev, int type_mask) |
79e53945 | 7752 | { |
4ef69c7a | 7753 | struct intel_encoder *encoder; |
79e53945 | 7754 | int index_mask = 0; |
79e53945 JB |
7755 | int entry = 0; |
7756 | ||
4ef69c7a CW |
7757 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
7758 | if (type_mask & encoder->clone_mask) | |
79e53945 JB |
7759 | index_mask |= (1 << entry); |
7760 | entry++; | |
7761 | } | |
4ef69c7a | 7762 | |
79e53945 JB |
7763 | return index_mask; |
7764 | } | |
7765 | ||
4d302442 CW |
7766 | static bool has_edp_a(struct drm_device *dev) |
7767 | { | |
7768 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7769 | ||
7770 | if (!IS_MOBILE(dev)) | |
7771 | return false; | |
7772 | ||
7773 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
7774 | return false; | |
7775 | ||
7776 | if (IS_GEN5(dev) && | |
7777 | (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE)) | |
7778 | return false; | |
7779 | ||
7780 | return true; | |
7781 | } | |
7782 | ||
79e53945 JB |
7783 | static void intel_setup_outputs(struct drm_device *dev) |
7784 | { | |
725e30ad | 7785 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 7786 | struct intel_encoder *encoder; |
cb0953d7 | 7787 | bool dpd_is_edp = false; |
f3cfcba6 | 7788 | bool has_lvds; |
79e53945 | 7789 | |
f3cfcba6 | 7790 | has_lvds = intel_lvds_init(dev); |
c5d1b51d CW |
7791 | if (!has_lvds && !HAS_PCH_SPLIT(dev)) { |
7792 | /* disable the panel fitter on everything but LVDS */ | |
7793 | I915_WRITE(PFIT_CONTROL, 0); | |
7794 | } | |
79e53945 | 7795 | |
bad720ff | 7796 | if (HAS_PCH_SPLIT(dev)) { |
cb0953d7 | 7797 | dpd_is_edp = intel_dpd_is_edp(dev); |
30ad48b7 | 7798 | |
4d302442 | 7799 | if (has_edp_a(dev)) |
32f9d658 ZW |
7800 | intel_dp_init(dev, DP_A); |
7801 | ||
cb0953d7 AJ |
7802 | if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) |
7803 | intel_dp_init(dev, PCH_DP_D); | |
7804 | } | |
7805 | ||
7806 | intel_crt_init(dev); | |
7807 | ||
7808 | if (HAS_PCH_SPLIT(dev)) { | |
7809 | int found; | |
7810 | ||
30ad48b7 | 7811 | if (I915_READ(HDMIB) & PORT_DETECTED) { |
461ed3ca | 7812 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 7813 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 ZW |
7814 | if (!found) |
7815 | intel_hdmi_init(dev, HDMIB); | |
5eb08b69 ZW |
7816 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
7817 | intel_dp_init(dev, PCH_DP_B); | |
30ad48b7 ZW |
7818 | } |
7819 | ||
7820 | if (I915_READ(HDMIC) & PORT_DETECTED) | |
7821 | intel_hdmi_init(dev, HDMIC); | |
7822 | ||
7823 | if (I915_READ(HDMID) & PORT_DETECTED) | |
7824 | intel_hdmi_init(dev, HDMID); | |
7825 | ||
5eb08b69 ZW |
7826 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
7827 | intel_dp_init(dev, PCH_DP_C); | |
7828 | ||
cb0953d7 | 7829 | if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) |
5eb08b69 ZW |
7830 | intel_dp_init(dev, PCH_DP_D); |
7831 | ||
103a196f | 7832 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 7833 | bool found = false; |
7d57382e | 7834 | |
725e30ad | 7835 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 7836 | DRM_DEBUG_KMS("probing SDVOB\n"); |
eef4eacb | 7837 | found = intel_sdvo_init(dev, SDVOB, true); |
b01f2c3a JB |
7838 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
7839 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
725e30ad | 7840 | intel_hdmi_init(dev, SDVOB); |
b01f2c3a | 7841 | } |
27185ae1 | 7842 | |
b01f2c3a JB |
7843 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) { |
7844 | DRM_DEBUG_KMS("probing DP_B\n"); | |
a4fc5ed6 | 7845 | intel_dp_init(dev, DP_B); |
b01f2c3a | 7846 | } |
725e30ad | 7847 | } |
13520b05 KH |
7848 | |
7849 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 7850 | |
b01f2c3a JB |
7851 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
7852 | DRM_DEBUG_KMS("probing SDVOC\n"); | |
eef4eacb | 7853 | found = intel_sdvo_init(dev, SDVOC, false); |
b01f2c3a | 7854 | } |
27185ae1 ML |
7855 | |
7856 | if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) { | |
7857 | ||
b01f2c3a JB |
7858 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
7859 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
725e30ad | 7860 | intel_hdmi_init(dev, SDVOC); |
b01f2c3a JB |
7861 | } |
7862 | if (SUPPORTS_INTEGRATED_DP(dev)) { | |
7863 | DRM_DEBUG_KMS("probing DP_C\n"); | |
a4fc5ed6 | 7864 | intel_dp_init(dev, DP_C); |
b01f2c3a | 7865 | } |
725e30ad | 7866 | } |
27185ae1 | 7867 | |
b01f2c3a JB |
7868 | if (SUPPORTS_INTEGRATED_DP(dev) && |
7869 | (I915_READ(DP_D) & DP_DETECTED)) { | |
7870 | DRM_DEBUG_KMS("probing DP_D\n"); | |
a4fc5ed6 | 7871 | intel_dp_init(dev, DP_D); |
b01f2c3a | 7872 | } |
bad720ff | 7873 | } else if (IS_GEN2(dev)) |
79e53945 JB |
7874 | intel_dvo_init(dev); |
7875 | ||
103a196f | 7876 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
7877 | intel_tv_init(dev); |
7878 | ||
4ef69c7a CW |
7879 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
7880 | encoder->base.possible_crtcs = encoder->crtc_mask; | |
7881 | encoder->base.possible_clones = | |
7882 | intel_encoder_clones(dev, encoder->clone_mask); | |
79e53945 | 7883 | } |
47356eb6 | 7884 | |
2c7111db CW |
7885 | /* disable all the possible outputs/crtcs before entering KMS mode */ |
7886 | drm_helper_disable_unused_functions(dev); | |
9fb526db KP |
7887 | |
7888 | if (HAS_PCH_SPLIT(dev)) | |
7889 | ironlake_init_pch_refclk(dev); | |
79e53945 JB |
7890 | } |
7891 | ||
7892 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
7893 | { | |
7894 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 JB |
7895 | |
7896 | drm_framebuffer_cleanup(fb); | |
05394f39 | 7897 | drm_gem_object_unreference_unlocked(&intel_fb->obj->base); |
79e53945 JB |
7898 | |
7899 | kfree(intel_fb); | |
7900 | } | |
7901 | ||
7902 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 7903 | struct drm_file *file, |
79e53945 JB |
7904 | unsigned int *handle) |
7905 | { | |
7906 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 7907 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 7908 | |
05394f39 | 7909 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
7910 | } |
7911 | ||
7912 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
7913 | .destroy = intel_user_framebuffer_destroy, | |
7914 | .create_handle = intel_user_framebuffer_create_handle, | |
7915 | }; | |
7916 | ||
38651674 DA |
7917 | int intel_framebuffer_init(struct drm_device *dev, |
7918 | struct intel_framebuffer *intel_fb, | |
308e5bcb | 7919 | struct drm_mode_fb_cmd2 *mode_cmd, |
05394f39 | 7920 | struct drm_i915_gem_object *obj) |
79e53945 | 7921 | { |
79e53945 JB |
7922 | int ret; |
7923 | ||
05394f39 | 7924 | if (obj->tiling_mode == I915_TILING_Y) |
57cd6508 CW |
7925 | return -EINVAL; |
7926 | ||
308e5bcb | 7927 | if (mode_cmd->pitches[0] & 63) |
57cd6508 CW |
7928 | return -EINVAL; |
7929 | ||
308e5bcb | 7930 | switch (mode_cmd->pixel_format) { |
04b3924d VS |
7931 | case DRM_FORMAT_RGB332: |
7932 | case DRM_FORMAT_RGB565: | |
7933 | case DRM_FORMAT_XRGB8888: | |
7934 | case DRM_FORMAT_ARGB8888: | |
7935 | case DRM_FORMAT_XRGB2101010: | |
7936 | case DRM_FORMAT_ARGB2101010: | |
308e5bcb | 7937 | /* RGB formats are common across chipsets */ |
b5626747 | 7938 | break; |
04b3924d VS |
7939 | case DRM_FORMAT_YUYV: |
7940 | case DRM_FORMAT_UYVY: | |
7941 | case DRM_FORMAT_YVYU: | |
7942 | case DRM_FORMAT_VYUY: | |
57cd6508 CW |
7943 | break; |
7944 | default: | |
aca25848 ED |
7945 | DRM_DEBUG_KMS("unsupported pixel format %u\n", |
7946 | mode_cmd->pixel_format); | |
57cd6508 CW |
7947 | return -EINVAL; |
7948 | } | |
7949 | ||
79e53945 JB |
7950 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
7951 | if (ret) { | |
7952 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
7953 | return ret; | |
7954 | } | |
7955 | ||
7956 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); | |
79e53945 | 7957 | intel_fb->obj = obj; |
79e53945 JB |
7958 | return 0; |
7959 | } | |
7960 | ||
79e53945 JB |
7961 | static struct drm_framebuffer * |
7962 | intel_user_framebuffer_create(struct drm_device *dev, | |
7963 | struct drm_file *filp, | |
308e5bcb | 7964 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 7965 | { |
05394f39 | 7966 | struct drm_i915_gem_object *obj; |
79e53945 | 7967 | |
308e5bcb JB |
7968 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
7969 | mode_cmd->handles[0])); | |
c8725226 | 7970 | if (&obj->base == NULL) |
cce13ff7 | 7971 | return ERR_PTR(-ENOENT); |
79e53945 | 7972 | |
d2dff872 | 7973 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
7974 | } |
7975 | ||
79e53945 | 7976 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 7977 | .fb_create = intel_user_framebuffer_create, |
eb1f8e4f | 7978 | .output_poll_changed = intel_fb_output_poll_changed, |
79e53945 JB |
7979 | }; |
7980 | ||
05394f39 | 7981 | static struct drm_i915_gem_object * |
aa40d6bb | 7982 | intel_alloc_context_page(struct drm_device *dev) |
9ea8d059 | 7983 | { |
05394f39 | 7984 | struct drm_i915_gem_object *ctx; |
9ea8d059 CW |
7985 | int ret; |
7986 | ||
2c34b850 BW |
7987 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
7988 | ||
aa40d6bb ZN |
7989 | ctx = i915_gem_alloc_object(dev, 4096); |
7990 | if (!ctx) { | |
9ea8d059 CW |
7991 | DRM_DEBUG("failed to alloc power context, RC6 disabled\n"); |
7992 | return NULL; | |
7993 | } | |
7994 | ||
75e9e915 | 7995 | ret = i915_gem_object_pin(ctx, 4096, true); |
9ea8d059 CW |
7996 | if (ret) { |
7997 | DRM_ERROR("failed to pin power context: %d\n", ret); | |
7998 | goto err_unref; | |
7999 | } | |
8000 | ||
aa40d6bb | 8001 | ret = i915_gem_object_set_to_gtt_domain(ctx, 1); |
9ea8d059 CW |
8002 | if (ret) { |
8003 | DRM_ERROR("failed to set-domain on power context: %d\n", ret); | |
8004 | goto err_unpin; | |
8005 | } | |
9ea8d059 | 8006 | |
aa40d6bb | 8007 | return ctx; |
9ea8d059 CW |
8008 | |
8009 | err_unpin: | |
aa40d6bb | 8010 | i915_gem_object_unpin(ctx); |
9ea8d059 | 8011 | err_unref: |
05394f39 | 8012 | drm_gem_object_unreference(&ctx->base); |
9ea8d059 CW |
8013 | mutex_unlock(&dev->struct_mutex); |
8014 | return NULL; | |
8015 | } | |
8016 | ||
7648fa99 JB |
8017 | bool ironlake_set_drps(struct drm_device *dev, u8 val) |
8018 | { | |
8019 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8020 | u16 rgvswctl; | |
8021 | ||
8022 | rgvswctl = I915_READ16(MEMSWCTL); | |
8023 | if (rgvswctl & MEMCTL_CMD_STS) { | |
8024 | DRM_DEBUG("gpu busy, RCS change rejected\n"); | |
8025 | return false; /* still busy with another command */ | |
8026 | } | |
8027 | ||
8028 | rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | | |
8029 | (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; | |
8030 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
8031 | POSTING_READ16(MEMSWCTL); | |
8032 | ||
8033 | rgvswctl |= MEMCTL_CMD_STS; | |
8034 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
8035 | ||
8036 | return true; | |
8037 | } | |
8038 | ||
f97108d1 JB |
8039 | void ironlake_enable_drps(struct drm_device *dev) |
8040 | { | |
8041 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7648fa99 | 8042 | u32 rgvmodectl = I915_READ(MEMMODECTL); |
f97108d1 | 8043 | u8 fmax, fmin, fstart, vstart; |
f97108d1 | 8044 | |
ea056c14 JB |
8045 | /* Enable temp reporting */ |
8046 | I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); | |
8047 | I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); | |
8048 | ||
f97108d1 JB |
8049 | /* 100ms RC evaluation intervals */ |
8050 | I915_WRITE(RCUPEI, 100000); | |
8051 | I915_WRITE(RCDNEI, 100000); | |
8052 | ||
8053 | /* Set max/min thresholds to 90ms and 80ms respectively */ | |
8054 | I915_WRITE(RCBMAXAVG, 90000); | |
8055 | I915_WRITE(RCBMINAVG, 80000); | |
8056 | ||
8057 | I915_WRITE(MEMIHYST, 1); | |
8058 | ||
8059 | /* Set up min, max, and cur for interrupt handling */ | |
8060 | fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; | |
8061 | fmin = (rgvmodectl & MEMMODE_FMIN_MASK); | |
8062 | fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> | |
8063 | MEMMODE_FSTART_SHIFT; | |
7648fa99 | 8064 | |
f97108d1 JB |
8065 | vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >> |
8066 | PXVFREQ_PX_SHIFT; | |
8067 | ||
80dbf4b7 | 8068 | dev_priv->fmax = fmax; /* IPS callback will increase this */ |
7648fa99 JB |
8069 | dev_priv->fstart = fstart; |
8070 | ||
80dbf4b7 | 8071 | dev_priv->max_delay = fstart; |
f97108d1 JB |
8072 | dev_priv->min_delay = fmin; |
8073 | dev_priv->cur_delay = fstart; | |
8074 | ||
80dbf4b7 JB |
8075 | DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", |
8076 | fmax, fmin, fstart); | |
7648fa99 | 8077 | |
f97108d1 JB |
8078 | I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); |
8079 | ||
8080 | /* | |
8081 | * Interrupts will be enabled in ironlake_irq_postinstall | |
8082 | */ | |
8083 | ||
8084 | I915_WRITE(VIDSTART, vstart); | |
8085 | POSTING_READ(VIDSTART); | |
8086 | ||
8087 | rgvmodectl |= MEMMODE_SWMODE_EN; | |
8088 | I915_WRITE(MEMMODECTL, rgvmodectl); | |
8089 | ||
481b6af3 | 8090 | if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) |
913d8d11 | 8091 | DRM_ERROR("stuck trying to change perf mode\n"); |
f97108d1 JB |
8092 | msleep(1); |
8093 | ||
7648fa99 | 8094 | ironlake_set_drps(dev, fstart); |
f97108d1 | 8095 | |
7648fa99 JB |
8096 | dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) + |
8097 | I915_READ(0x112e0); | |
8098 | dev_priv->last_time1 = jiffies_to_msecs(jiffies); | |
8099 | dev_priv->last_count2 = I915_READ(0x112f4); | |
8100 | getrawmonotonic(&dev_priv->last_time2); | |
f97108d1 JB |
8101 | } |
8102 | ||
8103 | void ironlake_disable_drps(struct drm_device *dev) | |
8104 | { | |
8105 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7648fa99 | 8106 | u16 rgvswctl = I915_READ16(MEMSWCTL); |
f97108d1 JB |
8107 | |
8108 | /* Ack interrupts, disable EFC interrupt */ | |
8109 | I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); | |
8110 | I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); | |
8111 | I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); | |
8112 | I915_WRITE(DEIIR, DE_PCU_EVENT); | |
8113 | I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); | |
8114 | ||
8115 | /* Go back to the starting frequency */ | |
7648fa99 | 8116 | ironlake_set_drps(dev, dev_priv->fstart); |
f97108d1 JB |
8117 | msleep(1); |
8118 | rgvswctl |= MEMCTL_CMD_STS; | |
8119 | I915_WRITE(MEMSWCTL, rgvswctl); | |
8120 | msleep(1); | |
8121 | ||
8122 | } | |
8123 | ||
3b8d8d91 JB |
8124 | void gen6_set_rps(struct drm_device *dev, u8 val) |
8125 | { | |
8126 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8127 | u32 swreq; | |
8128 | ||
8129 | swreq = (val & 0x3ff) << 25; | |
8130 | I915_WRITE(GEN6_RPNSWREQ, swreq); | |
8131 | } | |
8132 | ||
8133 | void gen6_disable_rps(struct drm_device *dev) | |
8134 | { | |
8135 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8136 | ||
8137 | I915_WRITE(GEN6_RPNSWREQ, 1 << 31); | |
8138 | I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); | |
8139 | I915_WRITE(GEN6_PMIER, 0); | |
6fdd4d98 DV |
8140 | /* Complete PM interrupt masking here doesn't race with the rps work |
8141 | * item again unmasking PM interrupts because that is using a different | |
8142 | * register (PMIMR) to mask PM interrupts. The only risk is in leaving | |
8143 | * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */ | |
4912d041 BW |
8144 | |
8145 | spin_lock_irq(&dev_priv->rps_lock); | |
8146 | dev_priv->pm_iir = 0; | |
8147 | spin_unlock_irq(&dev_priv->rps_lock); | |
8148 | ||
3b8d8d91 JB |
8149 | I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR)); |
8150 | } | |
8151 | ||
7648fa99 JB |
8152 | static unsigned long intel_pxfreq(u32 vidfreq) |
8153 | { | |
8154 | unsigned long freq; | |
8155 | int div = (vidfreq & 0x3f0000) >> 16; | |
8156 | int post = (vidfreq & 0x3000) >> 12; | |
8157 | int pre = (vidfreq & 0x7); | |
8158 | ||
8159 | if (!pre) | |
8160 | return 0; | |
8161 | ||
8162 | freq = ((div * 133333) / ((1<<post) * pre)); | |
8163 | ||
8164 | return freq; | |
8165 | } | |
8166 | ||
8167 | void intel_init_emon(struct drm_device *dev) | |
8168 | { | |
8169 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8170 | u32 lcfuse; | |
8171 | u8 pxw[16]; | |
8172 | int i; | |
8173 | ||
8174 | /* Disable to program */ | |
8175 | I915_WRITE(ECR, 0); | |
8176 | POSTING_READ(ECR); | |
8177 | ||
8178 | /* Program energy weights for various events */ | |
8179 | I915_WRITE(SDEW, 0x15040d00); | |
8180 | I915_WRITE(CSIEW0, 0x007f0000); | |
8181 | I915_WRITE(CSIEW1, 0x1e220004); | |
8182 | I915_WRITE(CSIEW2, 0x04000004); | |
8183 | ||
8184 | for (i = 0; i < 5; i++) | |
8185 | I915_WRITE(PEW + (i * 4), 0); | |
8186 | for (i = 0; i < 3; i++) | |
8187 | I915_WRITE(DEW + (i * 4), 0); | |
8188 | ||
8189 | /* Program P-state weights to account for frequency power adjustment */ | |
8190 | for (i = 0; i < 16; i++) { | |
8191 | u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4)); | |
8192 | unsigned long freq = intel_pxfreq(pxvidfreq); | |
8193 | unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> | |
8194 | PXVFREQ_PX_SHIFT; | |
8195 | unsigned long val; | |
8196 | ||
8197 | val = vid * vid; | |
8198 | val *= (freq / 1000); | |
8199 | val *= 255; | |
8200 | val /= (127*127*900); | |
8201 | if (val > 0xff) | |
8202 | DRM_ERROR("bad pxval: %ld\n", val); | |
8203 | pxw[i] = val; | |
8204 | } | |
8205 | /* Render standby states get 0 weight */ | |
8206 | pxw[14] = 0; | |
8207 | pxw[15] = 0; | |
8208 | ||
8209 | for (i = 0; i < 4; i++) { | |
8210 | u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | | |
8211 | (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); | |
8212 | I915_WRITE(PXW + (i * 4), val); | |
8213 | } | |
8214 | ||
8215 | /* Adjust magic regs to magic values (more experimental results) */ | |
8216 | I915_WRITE(OGW0, 0); | |
8217 | I915_WRITE(OGW1, 0); | |
8218 | I915_WRITE(EG0, 0x00007f00); | |
8219 | I915_WRITE(EG1, 0x0000000e); | |
8220 | I915_WRITE(EG2, 0x000e0000); | |
8221 | I915_WRITE(EG3, 0x68000300); | |
8222 | I915_WRITE(EG4, 0x42000000); | |
8223 | I915_WRITE(EG5, 0x00140031); | |
8224 | I915_WRITE(EG6, 0); | |
8225 | I915_WRITE(EG7, 0); | |
8226 | ||
8227 | for (i = 0; i < 8; i++) | |
8228 | I915_WRITE(PXWL + (i * 4), 0); | |
8229 | ||
8230 | /* Enable PMON + select events */ | |
8231 | I915_WRITE(ECR, 0x80000019); | |
8232 | ||
8233 | lcfuse = I915_READ(LCFUSE02); | |
8234 | ||
8235 | dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK); | |
8236 | } | |
8237 | ||
c0f372b3 KP |
8238 | static bool intel_enable_rc6(struct drm_device *dev) |
8239 | { | |
8240 | /* | |
8241 | * Respect the kernel parameter if it is set | |
8242 | */ | |
8243 | if (i915_enable_rc6 >= 0) | |
8244 | return i915_enable_rc6; | |
8245 | ||
8246 | /* | |
8247 | * Disable RC6 on Ironlake | |
8248 | */ | |
8249 | if (INTEL_INFO(dev)->gen == 5) | |
8250 | return 0; | |
8251 | ||
8252 | /* | |
371de6e4 | 8253 | * Disable rc6 on Sandybridge |
c0f372b3 KP |
8254 | */ |
8255 | if (INTEL_INFO(dev)->gen == 6) { | |
371de6e4 KP |
8256 | DRM_DEBUG_DRIVER("Sandybridge: RC6 disabled\n"); |
8257 | return 0; | |
c0f372b3 KP |
8258 | } |
8259 | DRM_DEBUG_DRIVER("RC6 enabled\n"); | |
8260 | return 1; | |
8261 | } | |
8262 | ||
3b8d8d91 | 8263 | void gen6_enable_rps(struct drm_i915_private *dev_priv) |
8fd26859 | 8264 | { |
a6044e23 JB |
8265 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
8266 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); | |
7df8721b | 8267 | u32 pcu_mbox, rc6_mask = 0; |
dd202c6d | 8268 | u32 gtfifodbg; |
a6044e23 | 8269 | int cur_freq, min_freq, max_freq; |
8fd26859 CW |
8270 | int i; |
8271 | ||
8272 | /* Here begins a magic sequence of register writes to enable | |
8273 | * auto-downclocking. | |
8274 | * | |
8275 | * Perhaps there might be some value in exposing these to | |
8276 | * userspace... | |
8277 | */ | |
8278 | I915_WRITE(GEN6_RC_STATE, 0); | |
d1ebd816 | 8279 | mutex_lock(&dev_priv->dev->struct_mutex); |
dd202c6d BW |
8280 | |
8281 | /* Clear the DBG now so we don't confuse earlier errors */ | |
8282 | if ((gtfifodbg = I915_READ(GTFIFODBG))) { | |
8283 | DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg); | |
8284 | I915_WRITE(GTFIFODBG, gtfifodbg); | |
8285 | } | |
8286 | ||
fcca7926 | 8287 | gen6_gt_force_wake_get(dev_priv); |
8fd26859 | 8288 | |
3b8d8d91 | 8289 | /* disable the counters and set deterministic thresholds */ |
8fd26859 CW |
8290 | I915_WRITE(GEN6_RC_CONTROL, 0); |
8291 | ||
8292 | I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); | |
8293 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); | |
8294 | I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); | |
8295 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); | |
8296 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); | |
8297 | ||
8298 | for (i = 0; i < I915_NUM_RINGS; i++) | |
8299 | I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10); | |
8300 | ||
8301 | I915_WRITE(GEN6_RC_SLEEP, 0); | |
8302 | I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); | |
8303 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); | |
8304 | I915_WRITE(GEN6_RC6p_THRESHOLD, 100000); | |
8305 | I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ | |
8306 | ||
c0f372b3 | 8307 | if (intel_enable_rc6(dev_priv->dev)) |
7df8721b JB |
8308 | rc6_mask = GEN6_RC_CTL_RC6p_ENABLE | |
8309 | GEN6_RC_CTL_RC6_ENABLE; | |
8310 | ||
8fd26859 | 8311 | I915_WRITE(GEN6_RC_CONTROL, |
7df8721b | 8312 | rc6_mask | |
9c3d2f7f | 8313 | GEN6_RC_CTL_EI_MODE(1) | |
8fd26859 CW |
8314 | GEN6_RC_CTL_HW_ENABLE); |
8315 | ||
3b8d8d91 | 8316 | I915_WRITE(GEN6_RPNSWREQ, |
8fd26859 CW |
8317 | GEN6_FREQUENCY(10) | |
8318 | GEN6_OFFSET(0) | | |
8319 | GEN6_AGGRESSIVE_TURBO); | |
8320 | I915_WRITE(GEN6_RC_VIDEO_FREQ, | |
8321 | GEN6_FREQUENCY(12)); | |
8322 | ||
8323 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); | |
8324 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, | |
8325 | 18 << 24 | | |
8326 | 6 << 16); | |
ccab5c82 JB |
8327 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000); |
8328 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000); | |
8fd26859 | 8329 | I915_WRITE(GEN6_RP_UP_EI, 100000); |
ccab5c82 | 8330 | I915_WRITE(GEN6_RP_DOWN_EI, 5000000); |
8fd26859 CW |
8331 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
8332 | I915_WRITE(GEN6_RP_CONTROL, | |
8333 | GEN6_RP_MEDIA_TURBO | | |
6ed55ee7 | 8334 | GEN6_RP_MEDIA_HW_MODE | |
8fd26859 CW |
8335 | GEN6_RP_MEDIA_IS_GFX | |
8336 | GEN6_RP_ENABLE | | |
ccab5c82 JB |
8337 | GEN6_RP_UP_BUSY_AVG | |
8338 | GEN6_RP_DOWN_IDLE_CONT); | |
8fd26859 CW |
8339 | |
8340 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
8341 | 500)) | |
8342 | DRM_ERROR("timeout waiting for pcode mailbox to become idle\n"); | |
8343 | ||
8344 | I915_WRITE(GEN6_PCODE_DATA, 0); | |
8345 | I915_WRITE(GEN6_PCODE_MAILBOX, | |
8346 | GEN6_PCODE_READY | | |
8347 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE); | |
8348 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
8349 | 500)) | |
8350 | DRM_ERROR("timeout waiting for pcode mailbox to finish\n"); | |
8351 | ||
a6044e23 JB |
8352 | min_freq = (rp_state_cap & 0xff0000) >> 16; |
8353 | max_freq = rp_state_cap & 0xff; | |
8354 | cur_freq = (gt_perf_status & 0xff00) >> 8; | |
8355 | ||
8356 | /* Check for overclock support */ | |
8357 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
8358 | 500)) | |
8359 | DRM_ERROR("timeout waiting for pcode mailbox to become idle\n"); | |
8360 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS); | |
8361 | pcu_mbox = I915_READ(GEN6_PCODE_DATA); | |
8362 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
8363 | 500)) | |
8364 | DRM_ERROR("timeout waiting for pcode mailbox to finish\n"); | |
8365 | if (pcu_mbox & (1<<31)) { /* OC supported */ | |
8366 | max_freq = pcu_mbox & 0xff; | |
e281fcaa | 8367 | DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50); |
a6044e23 JB |
8368 | } |
8369 | ||
8370 | /* In units of 100MHz */ | |
8371 | dev_priv->max_delay = max_freq; | |
8372 | dev_priv->min_delay = min_freq; | |
8373 | dev_priv->cur_delay = cur_freq; | |
8374 | ||
8fd26859 CW |
8375 | /* requires MSI enabled */ |
8376 | I915_WRITE(GEN6_PMIER, | |
8377 | GEN6_PM_MBOX_EVENT | | |
8378 | GEN6_PM_THERMAL_EVENT | | |
8379 | GEN6_PM_RP_DOWN_TIMEOUT | | |
8380 | GEN6_PM_RP_UP_THRESHOLD | | |
8381 | GEN6_PM_RP_DOWN_THRESHOLD | | |
8382 | GEN6_PM_RP_UP_EI_EXPIRED | | |
8383 | GEN6_PM_RP_DOWN_EI_EXPIRED); | |
4912d041 BW |
8384 | spin_lock_irq(&dev_priv->rps_lock); |
8385 | WARN_ON(dev_priv->pm_iir != 0); | |
3b8d8d91 | 8386 | I915_WRITE(GEN6_PMIMR, 0); |
4912d041 | 8387 | spin_unlock_irq(&dev_priv->rps_lock); |
3b8d8d91 JB |
8388 | /* enable all PM interrupts */ |
8389 | I915_WRITE(GEN6_PMINTRMSK, 0); | |
8fd26859 | 8390 | |
fcca7926 | 8391 | gen6_gt_force_wake_put(dev_priv); |
d1ebd816 | 8392 | mutex_unlock(&dev_priv->dev->struct_mutex); |
8fd26859 CW |
8393 | } |
8394 | ||
23b2f8bb JB |
8395 | void gen6_update_ring_freq(struct drm_i915_private *dev_priv) |
8396 | { | |
8397 | int min_freq = 15; | |
8398 | int gpu_freq, ia_freq, max_ia_freq; | |
8399 | int scaling_factor = 180; | |
8400 | ||
8401 | max_ia_freq = cpufreq_quick_get_max(0); | |
8402 | /* | |
8403 | * Default to measured freq if none found, PCU will ensure we don't go | |
8404 | * over | |
8405 | */ | |
8406 | if (!max_ia_freq) | |
8407 | max_ia_freq = tsc_khz; | |
8408 | ||
8409 | /* Convert from kHz to MHz */ | |
8410 | max_ia_freq /= 1000; | |
8411 | ||
8412 | mutex_lock(&dev_priv->dev->struct_mutex); | |
8413 | ||
8414 | /* | |
8415 | * For each potential GPU frequency, load a ring frequency we'd like | |
8416 | * to use for memory access. We do this by specifying the IA frequency | |
8417 | * the PCU should use as a reference to determine the ring frequency. | |
8418 | */ | |
8419 | for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay; | |
8420 | gpu_freq--) { | |
8421 | int diff = dev_priv->max_delay - gpu_freq; | |
8422 | ||
8423 | /* | |
8424 | * For GPU frequencies less than 750MHz, just use the lowest | |
8425 | * ring freq. | |
8426 | */ | |
8427 | if (gpu_freq < min_freq) | |
8428 | ia_freq = 800; | |
8429 | else | |
8430 | ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); | |
8431 | ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); | |
8432 | ||
8433 | I915_WRITE(GEN6_PCODE_DATA, | |
8434 | (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) | | |
8435 | gpu_freq); | |
8436 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | | |
8437 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE); | |
8438 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & | |
8439 | GEN6_PCODE_READY) == 0, 10)) { | |
8440 | DRM_ERROR("pcode write of freq table timed out\n"); | |
8441 | continue; | |
8442 | } | |
8443 | } | |
8444 | ||
8445 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
8446 | } | |
8447 | ||
6067aaea JB |
8448 | static void ironlake_init_clock_gating(struct drm_device *dev) |
8449 | { | |
8450 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8451 | uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; | |
8452 | ||
8453 | /* Required for FBC */ | |
8454 | dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE | | |
8455 | DPFCRUNIT_CLOCK_GATE_DISABLE | | |
8456 | DPFDUNIT_CLOCK_GATE_DISABLE; | |
8457 | /* Required for CxSR */ | |
8458 | dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE; | |
8459 | ||
8460 | I915_WRITE(PCH_3DCGDIS0, | |
8461 | MARIUNIT_CLOCK_GATE_DISABLE | | |
8462 | SVSMUNIT_CLOCK_GATE_DISABLE); | |
8463 | I915_WRITE(PCH_3DCGDIS1, | |
8464 | VFMUNIT_CLOCK_GATE_DISABLE); | |
8465 | ||
8466 | I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); | |
8467 | ||
6067aaea JB |
8468 | /* |
8469 | * According to the spec the following bits should be set in | |
8470 | * order to enable memory self-refresh | |
8471 | * The bit 22/21 of 0x42004 | |
8472 | * The bit 5 of 0x42020 | |
8473 | * The bit 15 of 0x45000 | |
8474 | */ | |
8475 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
8476 | (I915_READ(ILK_DISPLAY_CHICKEN2) | | |
8477 | ILK_DPARB_GATE | ILK_VSDPFD_FULL)); | |
8478 | I915_WRITE(ILK_DSPCLK_GATE, | |
8479 | (I915_READ(ILK_DSPCLK_GATE) | | |
8480 | ILK_DPARB_CLK_GATE)); | |
8481 | I915_WRITE(DISP_ARB_CTL, | |
8482 | (I915_READ(DISP_ARB_CTL) | | |
8483 | DISP_FBC_WM_DIS)); | |
8484 | I915_WRITE(WM3_LP_ILK, 0); | |
8485 | I915_WRITE(WM2_LP_ILK, 0); | |
8486 | I915_WRITE(WM1_LP_ILK, 0); | |
8487 | ||
8488 | /* | |
8489 | * Based on the document from hardware guys the following bits | |
8490 | * should be set unconditionally in order to enable FBC. | |
8491 | * The bit 22 of 0x42000 | |
8492 | * The bit 22 of 0x42004 | |
8493 | * The bit 7,8,9 of 0x42020. | |
8494 | */ | |
8495 | if (IS_IRONLAKE_M(dev)) { | |
8496 | I915_WRITE(ILK_DISPLAY_CHICKEN1, | |
8497 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
8498 | ILK_FBCQ_DIS); | |
8499 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
8500 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
8501 | ILK_DPARB_GATE); | |
8502 | I915_WRITE(ILK_DSPCLK_GATE, | |
8503 | I915_READ(ILK_DSPCLK_GATE) | | |
8504 | ILK_DPFC_DIS1 | | |
8505 | ILK_DPFC_DIS2 | | |
8506 | ILK_CLK_FBC); | |
8507 | } | |
8508 | ||
8509 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
8510 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
8511 | ILK_ELPIN_409_SELECT); | |
8512 | I915_WRITE(_3D_CHICKEN2, | |
8513 | _3D_CHICKEN2_WM_READ_PIPELINED << 16 | | |
8514 | _3D_CHICKEN2_WM_READ_PIPELINED); | |
8fd26859 CW |
8515 | } |
8516 | ||
6067aaea | 8517 | static void gen6_init_clock_gating(struct drm_device *dev) |
652c393a JB |
8518 | { |
8519 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9db4a9c7 | 8520 | int pipe; |
6067aaea JB |
8521 | uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; |
8522 | ||
8523 | I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); | |
652c393a | 8524 | |
6067aaea JB |
8525 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
8526 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
8527 | ILK_ELPIN_409_SELECT); | |
8956c8bb | 8528 | |
6067aaea JB |
8529 | I915_WRITE(WM3_LP_ILK, 0); |
8530 | I915_WRITE(WM2_LP_ILK, 0); | |
8531 | I915_WRITE(WM1_LP_ILK, 0); | |
652c393a | 8532 | |
406478dc EA |
8533 | /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock |
8534 | * gating disable must be set. Failure to set it results in | |
8535 | * flickering pixels due to Z write ordering failures after | |
8536 | * some amount of runtime in the Mesa "fire" demo, and Unigine | |
8537 | * Sanctuary and Tropics, and apparently anything else with | |
8538 | * alpha test or pixel discard. | |
9ca1d10d EA |
8539 | * |
8540 | * According to the spec, bit 11 (RCCUNIT) must also be set, | |
8541 | * but we didn't debug actual testcases to find it out. | |
406478dc | 8542 | */ |
9ca1d10d EA |
8543 | I915_WRITE(GEN6_UCGCTL2, |
8544 | GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | | |
8545 | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); | |
406478dc | 8546 | |
652c393a | 8547 | /* |
6067aaea JB |
8548 | * According to the spec the following bits should be |
8549 | * set in order to enable memory self-refresh and fbc: | |
8550 | * The bit21 and bit22 of 0x42000 | |
8551 | * The bit21 and bit22 of 0x42004 | |
8552 | * The bit5 and bit7 of 0x42020 | |
8553 | * The bit14 of 0x70180 | |
8554 | * The bit14 of 0x71180 | |
652c393a | 8555 | */ |
6067aaea JB |
8556 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
8557 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
8558 | ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); | |
8559 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
8560 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
8561 | ILK_DPARB_GATE | ILK_VSDPFD_FULL); | |
8562 | I915_WRITE(ILK_DSPCLK_GATE, | |
8563 | I915_READ(ILK_DSPCLK_GATE) | | |
8564 | ILK_DPARB_CLK_GATE | | |
8565 | ILK_DPFD_CLK_GATE); | |
8956c8bb | 8566 | |
d74362c9 | 8567 | for_each_pipe(pipe) { |
6067aaea JB |
8568 | I915_WRITE(DSPCNTR(pipe), |
8569 | I915_READ(DSPCNTR(pipe)) | | |
8570 | DISPPLANE_TRICKLE_FEED_DISABLE); | |
d74362c9 KP |
8571 | intel_flush_display_plane(dev_priv, pipe); |
8572 | } | |
6067aaea | 8573 | } |
8956c8bb | 8574 | |
28963a3e JB |
8575 | static void ivybridge_init_clock_gating(struct drm_device *dev) |
8576 | { | |
8577 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8578 | int pipe; | |
8579 | uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; | |
7f8a8569 | 8580 | |
28963a3e | 8581 | I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); |
382b0936 | 8582 | |
28963a3e JB |
8583 | I915_WRITE(WM3_LP_ILK, 0); |
8584 | I915_WRITE(WM2_LP_ILK, 0); | |
8585 | I915_WRITE(WM1_LP_ILK, 0); | |
de6e2eaf | 8586 | |
28963a3e | 8587 | I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE); |
67e92af0 | 8588 | |
116ac8d2 EA |
8589 | I915_WRITE(IVB_CHICKEN3, |
8590 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | | |
8591 | CHICKEN3_DGMG_DONE_FIX_DISABLE); | |
8592 | ||
d74362c9 | 8593 | for_each_pipe(pipe) { |
28963a3e JB |
8594 | I915_WRITE(DSPCNTR(pipe), |
8595 | I915_READ(DSPCNTR(pipe)) | | |
8596 | DISPPLANE_TRICKLE_FEED_DISABLE); | |
d74362c9 KP |
8597 | intel_flush_display_plane(dev_priv, pipe); |
8598 | } | |
28963a3e JB |
8599 | } |
8600 | ||
6067aaea JB |
8601 | static void g4x_init_clock_gating(struct drm_device *dev) |
8602 | { | |
8603 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8604 | uint32_t dspclk_gate; | |
8fd26859 | 8605 | |
6067aaea JB |
8606 | I915_WRITE(RENCLK_GATE_D1, 0); |
8607 | I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | | |
8608 | GS_UNIT_CLOCK_GATE_DISABLE | | |
8609 | CL_UNIT_CLOCK_GATE_DISABLE); | |
8610 | I915_WRITE(RAMCLK_GATE_D, 0); | |
8611 | dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | | |
8612 | OVRUNIT_CLOCK_GATE_DISABLE | | |
8613 | OVCUNIT_CLOCK_GATE_DISABLE; | |
8614 | if (IS_GM45(dev)) | |
8615 | dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; | |
8616 | I915_WRITE(DSPCLK_GATE_D, dspclk_gate); | |
8617 | } | |
1398261a | 8618 | |
6067aaea JB |
8619 | static void crestline_init_clock_gating(struct drm_device *dev) |
8620 | { | |
8621 | struct drm_i915_private *dev_priv = dev->dev_private; | |
652c393a | 8622 | |
6067aaea JB |
8623 | I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); |
8624 | I915_WRITE(RENCLK_GATE_D2, 0); | |
8625 | I915_WRITE(DSPCLK_GATE_D, 0); | |
8626 | I915_WRITE(RAMCLK_GATE_D, 0); | |
8627 | I915_WRITE16(DEUC, 0); | |
8628 | } | |
652c393a | 8629 | |
6067aaea JB |
8630 | static void broadwater_init_clock_gating(struct drm_device *dev) |
8631 | { | |
8632 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8633 | ||
8634 | I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | | |
8635 | I965_RCC_CLOCK_GATE_DISABLE | | |
8636 | I965_RCPB_CLOCK_GATE_DISABLE | | |
8637 | I965_ISC_CLOCK_GATE_DISABLE | | |
8638 | I965_FBC_CLOCK_GATE_DISABLE); | |
8639 | I915_WRITE(RENCLK_GATE_D2, 0); | |
8640 | } | |
8641 | ||
8642 | static void gen3_init_clock_gating(struct drm_device *dev) | |
8643 | { | |
8644 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8645 | u32 dstate = I915_READ(D_STATE); | |
8646 | ||
8647 | dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | | |
8648 | DSTATE_DOT_CLOCK_GATING; | |
8649 | I915_WRITE(D_STATE, dstate); | |
8650 | } | |
8651 | ||
8652 | static void i85x_init_clock_gating(struct drm_device *dev) | |
8653 | { | |
8654 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8655 | ||
8656 | I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); | |
8657 | } | |
8658 | ||
8659 | static void i830_init_clock_gating(struct drm_device *dev) | |
8660 | { | |
8661 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8662 | ||
8663 | I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); | |
652c393a JB |
8664 | } |
8665 | ||
645c62a5 JB |
8666 | static void ibx_init_clock_gating(struct drm_device *dev) |
8667 | { | |
8668 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8669 | ||
8670 | /* | |
8671 | * On Ibex Peak and Cougar Point, we need to disable clock | |
8672 | * gating for the panel power sequencer or it will fail to | |
8673 | * start up when no ports are active. | |
8674 | */ | |
8675 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); | |
8676 | } | |
8677 | ||
8678 | static void cpt_init_clock_gating(struct drm_device *dev) | |
8679 | { | |
8680 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3bcf603f | 8681 | int pipe; |
645c62a5 JB |
8682 | |
8683 | /* | |
8684 | * On Ibex Peak and Cougar Point, we need to disable clock | |
8685 | * gating for the panel power sequencer or it will fail to | |
8686 | * start up when no ports are active. | |
8687 | */ | |
8688 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); | |
8689 | I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | | |
8690 | DPLS_EDP_PPS_FIX_DIS); | |
3bcf603f JB |
8691 | /* Without this, mode sets may fail silently on FDI */ |
8692 | for_each_pipe(pipe) | |
8693 | I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS); | |
652c393a JB |
8694 | } |
8695 | ||
ac668088 | 8696 | static void ironlake_teardown_rc6(struct drm_device *dev) |
0cdab21f CW |
8697 | { |
8698 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8699 | ||
8700 | if (dev_priv->renderctx) { | |
ac668088 CW |
8701 | i915_gem_object_unpin(dev_priv->renderctx); |
8702 | drm_gem_object_unreference(&dev_priv->renderctx->base); | |
0cdab21f CW |
8703 | dev_priv->renderctx = NULL; |
8704 | } | |
8705 | ||
8706 | if (dev_priv->pwrctx) { | |
ac668088 CW |
8707 | i915_gem_object_unpin(dev_priv->pwrctx); |
8708 | drm_gem_object_unreference(&dev_priv->pwrctx->base); | |
8709 | dev_priv->pwrctx = NULL; | |
8710 | } | |
8711 | } | |
8712 | ||
8713 | static void ironlake_disable_rc6(struct drm_device *dev) | |
8714 | { | |
8715 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8716 | ||
8717 | if (I915_READ(PWRCTXA)) { | |
8718 | /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */ | |
8719 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT); | |
8720 | wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON), | |
8721 | 50); | |
0cdab21f CW |
8722 | |
8723 | I915_WRITE(PWRCTXA, 0); | |
8724 | POSTING_READ(PWRCTXA); | |
8725 | ||
ac668088 CW |
8726 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); |
8727 | POSTING_READ(RSTDBYCTL); | |
0cdab21f | 8728 | } |
ac668088 | 8729 | |
99507307 | 8730 | ironlake_teardown_rc6(dev); |
0cdab21f CW |
8731 | } |
8732 | ||
ac668088 | 8733 | static int ironlake_setup_rc6(struct drm_device *dev) |
d5bb081b JB |
8734 | { |
8735 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8736 | ||
ac668088 CW |
8737 | if (dev_priv->renderctx == NULL) |
8738 | dev_priv->renderctx = intel_alloc_context_page(dev); | |
8739 | if (!dev_priv->renderctx) | |
8740 | return -ENOMEM; | |
8741 | ||
8742 | if (dev_priv->pwrctx == NULL) | |
8743 | dev_priv->pwrctx = intel_alloc_context_page(dev); | |
8744 | if (!dev_priv->pwrctx) { | |
8745 | ironlake_teardown_rc6(dev); | |
8746 | return -ENOMEM; | |
8747 | } | |
8748 | ||
8749 | return 0; | |
d5bb081b JB |
8750 | } |
8751 | ||
8752 | void ironlake_enable_rc6(struct drm_device *dev) | |
8753 | { | |
8754 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8755 | int ret; | |
8756 | ||
ac668088 CW |
8757 | /* rc6 disabled by default due to repeated reports of hanging during |
8758 | * boot and resume. | |
8759 | */ | |
c0f372b3 | 8760 | if (!intel_enable_rc6(dev)) |
ac668088 CW |
8761 | return; |
8762 | ||
2c34b850 | 8763 | mutex_lock(&dev->struct_mutex); |
ac668088 | 8764 | ret = ironlake_setup_rc6(dev); |
2c34b850 BW |
8765 | if (ret) { |
8766 | mutex_unlock(&dev->struct_mutex); | |
ac668088 | 8767 | return; |
2c34b850 | 8768 | } |
ac668088 | 8769 | |
d5bb081b JB |
8770 | /* |
8771 | * GPU can automatically power down the render unit if given a page | |
8772 | * to save state. | |
8773 | */ | |
8774 | ret = BEGIN_LP_RING(6); | |
8775 | if (ret) { | |
ac668088 | 8776 | ironlake_teardown_rc6(dev); |
2c34b850 | 8777 | mutex_unlock(&dev->struct_mutex); |
d5bb081b JB |
8778 | return; |
8779 | } | |
ac668088 | 8780 | |
d5bb081b JB |
8781 | OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN); |
8782 | OUT_RING(MI_SET_CONTEXT); | |
8783 | OUT_RING(dev_priv->renderctx->gtt_offset | | |
8784 | MI_MM_SPACE_GTT | | |
8785 | MI_SAVE_EXT_STATE_EN | | |
8786 | MI_RESTORE_EXT_STATE_EN | | |
8787 | MI_RESTORE_INHIBIT); | |
8788 | OUT_RING(MI_SUSPEND_FLUSH); | |
8789 | OUT_RING(MI_NOOP); | |
8790 | OUT_RING(MI_FLUSH); | |
8791 | ADVANCE_LP_RING(); | |
8792 | ||
4a246cfc BW |
8793 | /* |
8794 | * Wait for the command parser to advance past MI_SET_CONTEXT. The HW | |
8795 | * does an implicit flush, combined with MI_FLUSH above, it should be | |
8796 | * safe to assume that renderctx is valid | |
8797 | */ | |
8798 | ret = intel_wait_ring_idle(LP_RING(dev_priv)); | |
8799 | if (ret) { | |
8800 | DRM_ERROR("failed to enable ironlake power power savings\n"); | |
8801 | ironlake_teardown_rc6(dev); | |
8802 | mutex_unlock(&dev->struct_mutex); | |
8803 | return; | |
8804 | } | |
8805 | ||
d5bb081b JB |
8806 | I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN); |
8807 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); | |
2c34b850 | 8808 | mutex_unlock(&dev->struct_mutex); |
d5bb081b JB |
8809 | } |
8810 | ||
645c62a5 JB |
8811 | void intel_init_clock_gating(struct drm_device *dev) |
8812 | { | |
8813 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8814 | ||
8815 | dev_priv->display.init_clock_gating(dev); | |
8816 | ||
8817 | if (dev_priv->display.init_pch_clock_gating) | |
8818 | dev_priv->display.init_pch_clock_gating(dev); | |
8819 | } | |
ac668088 | 8820 | |
e70236a8 JB |
8821 | /* Set up chip specific display functions */ |
8822 | static void intel_init_display(struct drm_device *dev) | |
8823 | { | |
8824 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8825 | ||
8826 | /* We always want a DPMS function */ | |
f564048e | 8827 | if (HAS_PCH_SPLIT(dev)) { |
f2b115e6 | 8828 | dev_priv->display.dpms = ironlake_crtc_dpms; |
f564048e | 8829 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
17638cd6 | 8830 | dev_priv->display.update_plane = ironlake_update_plane; |
f564048e | 8831 | } else { |
e70236a8 | 8832 | dev_priv->display.dpms = i9xx_crtc_dpms; |
f564048e | 8833 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
17638cd6 | 8834 | dev_priv->display.update_plane = i9xx_update_plane; |
f564048e | 8835 | } |
e70236a8 | 8836 | |
ee5382ae | 8837 | if (I915_HAS_FBC(dev)) { |
9c04f015 | 8838 | if (HAS_PCH_SPLIT(dev)) { |
b52eb4dc ZY |
8839 | dev_priv->display.fbc_enabled = ironlake_fbc_enabled; |
8840 | dev_priv->display.enable_fbc = ironlake_enable_fbc; | |
8841 | dev_priv->display.disable_fbc = ironlake_disable_fbc; | |
8842 | } else if (IS_GM45(dev)) { | |
74dff282 JB |
8843 | dev_priv->display.fbc_enabled = g4x_fbc_enabled; |
8844 | dev_priv->display.enable_fbc = g4x_enable_fbc; | |
8845 | dev_priv->display.disable_fbc = g4x_disable_fbc; | |
a6c45cf0 | 8846 | } else if (IS_CRESTLINE(dev)) { |
e70236a8 JB |
8847 | dev_priv->display.fbc_enabled = i8xx_fbc_enabled; |
8848 | dev_priv->display.enable_fbc = i8xx_enable_fbc; | |
8849 | dev_priv->display.disable_fbc = i8xx_disable_fbc; | |
8850 | } | |
74dff282 | 8851 | /* 855GM needs testing */ |
e70236a8 JB |
8852 | } |
8853 | ||
8854 | /* Returns the core display clock speed */ | |
0206e353 | 8855 | if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) |
e70236a8 JB |
8856 | dev_priv->display.get_display_clock_speed = |
8857 | i945_get_display_clock_speed; | |
8858 | else if (IS_I915G(dev)) | |
8859 | dev_priv->display.get_display_clock_speed = | |
8860 | i915_get_display_clock_speed; | |
f2b115e6 | 8861 | else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev)) |
e70236a8 JB |
8862 | dev_priv->display.get_display_clock_speed = |
8863 | i9xx_misc_get_display_clock_speed; | |
8864 | else if (IS_I915GM(dev)) | |
8865 | dev_priv->display.get_display_clock_speed = | |
8866 | i915gm_get_display_clock_speed; | |
8867 | else if (IS_I865G(dev)) | |
8868 | dev_priv->display.get_display_clock_speed = | |
8869 | i865_get_display_clock_speed; | |
f0f8a9ce | 8870 | else if (IS_I85X(dev)) |
e70236a8 JB |
8871 | dev_priv->display.get_display_clock_speed = |
8872 | i855_get_display_clock_speed; | |
8873 | else /* 852, 830 */ | |
8874 | dev_priv->display.get_display_clock_speed = | |
8875 | i830_get_display_clock_speed; | |
8876 | ||
8877 | /* For FIFO watermark updates */ | |
7f8a8569 | 8878 | if (HAS_PCH_SPLIT(dev)) { |
8d715f00 KP |
8879 | dev_priv->display.force_wake_get = __gen6_gt_force_wake_get; |
8880 | dev_priv->display.force_wake_put = __gen6_gt_force_wake_put; | |
8881 | ||
8882 | /* IVB configs may use multi-threaded forcewake */ | |
8883 | if (IS_IVYBRIDGE(dev)) { | |
8884 | u32 ecobus; | |
8885 | ||
c7dffff7 KP |
8886 | /* A small trick here - if the bios hasn't configured MT forcewake, |
8887 | * and if the device is in RC6, then force_wake_mt_get will not wake | |
8888 | * the device and the ECOBUS read will return zero. Which will be | |
8889 | * (correctly) interpreted by the test below as MT forcewake being | |
8890 | * disabled. | |
8891 | */ | |
8d715f00 KP |
8892 | mutex_lock(&dev->struct_mutex); |
8893 | __gen6_gt_force_wake_mt_get(dev_priv); | |
c7dffff7 | 8894 | ecobus = I915_READ_NOTRACE(ECOBUS); |
8d715f00 KP |
8895 | __gen6_gt_force_wake_mt_put(dev_priv); |
8896 | mutex_unlock(&dev->struct_mutex); | |
8897 | ||
8898 | if (ecobus & FORCEWAKE_MT_ENABLE) { | |
8899 | DRM_DEBUG_KMS("Using MT version of forcewake\n"); | |
8900 | dev_priv->display.force_wake_get = | |
8901 | __gen6_gt_force_wake_mt_get; | |
8902 | dev_priv->display.force_wake_put = | |
8903 | __gen6_gt_force_wake_mt_put; | |
8904 | } | |
8905 | } | |
8906 | ||
645c62a5 JB |
8907 | if (HAS_PCH_IBX(dev)) |
8908 | dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating; | |
8909 | else if (HAS_PCH_CPT(dev)) | |
8910 | dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating; | |
8911 | ||
f00a3ddf | 8912 | if (IS_GEN5(dev)) { |
7f8a8569 ZW |
8913 | if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK) |
8914 | dev_priv->display.update_wm = ironlake_update_wm; | |
8915 | else { | |
8916 | DRM_DEBUG_KMS("Failed to get proper latency. " | |
8917 | "Disable CxSR\n"); | |
8918 | dev_priv->display.update_wm = NULL; | |
1398261a | 8919 | } |
674cf967 | 8920 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
6067aaea | 8921 | dev_priv->display.init_clock_gating = ironlake_init_clock_gating; |
e0dac65e | 8922 | dev_priv->display.write_eld = ironlake_write_eld; |
1398261a YL |
8923 | } else if (IS_GEN6(dev)) { |
8924 | if (SNB_READ_WM0_LATENCY()) { | |
8925 | dev_priv->display.update_wm = sandybridge_update_wm; | |
b840d907 | 8926 | dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; |
1398261a YL |
8927 | } else { |
8928 | DRM_DEBUG_KMS("Failed to read display plane latency. " | |
8929 | "Disable CxSR\n"); | |
8930 | dev_priv->display.update_wm = NULL; | |
7f8a8569 | 8931 | } |
674cf967 | 8932 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
6067aaea | 8933 | dev_priv->display.init_clock_gating = gen6_init_clock_gating; |
e0dac65e | 8934 | dev_priv->display.write_eld = ironlake_write_eld; |
357555c0 JB |
8935 | } else if (IS_IVYBRIDGE(dev)) { |
8936 | /* FIXME: detect B0+ stepping and use auto training */ | |
8937 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
fe100d4d JB |
8938 | if (SNB_READ_WM0_LATENCY()) { |
8939 | dev_priv->display.update_wm = sandybridge_update_wm; | |
b840d907 | 8940 | dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; |
fe100d4d JB |
8941 | } else { |
8942 | DRM_DEBUG_KMS("Failed to read display plane latency. " | |
8943 | "Disable CxSR\n"); | |
8944 | dev_priv->display.update_wm = NULL; | |
8945 | } | |
28963a3e | 8946 | dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; |
e0dac65e | 8947 | dev_priv->display.write_eld = ironlake_write_eld; |
7f8a8569 ZW |
8948 | } else |
8949 | dev_priv->display.update_wm = NULL; | |
8950 | } else if (IS_PINEVIEW(dev)) { | |
d4294342 | 8951 | if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), |
95534263 | 8952 | dev_priv->is_ddr3, |
d4294342 ZY |
8953 | dev_priv->fsb_freq, |
8954 | dev_priv->mem_freq)) { | |
8955 | DRM_INFO("failed to find known CxSR latency " | |
95534263 | 8956 | "(found ddr%s fsb freq %d, mem freq %d), " |
d4294342 | 8957 | "disabling CxSR\n", |
0206e353 | 8958 | (dev_priv->is_ddr3 == 1) ? "3" : "2", |
d4294342 ZY |
8959 | dev_priv->fsb_freq, dev_priv->mem_freq); |
8960 | /* Disable CxSR and never update its watermark again */ | |
8961 | pineview_disable_cxsr(dev); | |
8962 | dev_priv->display.update_wm = NULL; | |
8963 | } else | |
8964 | dev_priv->display.update_wm = pineview_update_wm; | |
95e0ee92 | 8965 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; |
6067aaea | 8966 | } else if (IS_G4X(dev)) { |
e0dac65e | 8967 | dev_priv->display.write_eld = g4x_write_eld; |
e70236a8 | 8968 | dev_priv->display.update_wm = g4x_update_wm; |
6067aaea JB |
8969 | dev_priv->display.init_clock_gating = g4x_init_clock_gating; |
8970 | } else if (IS_GEN4(dev)) { | |
e70236a8 | 8971 | dev_priv->display.update_wm = i965_update_wm; |
6067aaea JB |
8972 | if (IS_CRESTLINE(dev)) |
8973 | dev_priv->display.init_clock_gating = crestline_init_clock_gating; | |
8974 | else if (IS_BROADWATER(dev)) | |
8975 | dev_priv->display.init_clock_gating = broadwater_init_clock_gating; | |
8976 | } else if (IS_GEN3(dev)) { | |
e70236a8 JB |
8977 | dev_priv->display.update_wm = i9xx_update_wm; |
8978 | dev_priv->display.get_fifo_size = i9xx_get_fifo_size; | |
6067aaea JB |
8979 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; |
8980 | } else if (IS_I865G(dev)) { | |
8981 | dev_priv->display.update_wm = i830_update_wm; | |
8982 | dev_priv->display.init_clock_gating = i85x_init_clock_gating; | |
8983 | dev_priv->display.get_fifo_size = i830_get_fifo_size; | |
8f4695ed AJ |
8984 | } else if (IS_I85X(dev)) { |
8985 | dev_priv->display.update_wm = i9xx_update_wm; | |
8986 | dev_priv->display.get_fifo_size = i85x_get_fifo_size; | |
6067aaea | 8987 | dev_priv->display.init_clock_gating = i85x_init_clock_gating; |
e70236a8 | 8988 | } else { |
8f4695ed | 8989 | dev_priv->display.update_wm = i830_update_wm; |
6067aaea | 8990 | dev_priv->display.init_clock_gating = i830_init_clock_gating; |
8f4695ed | 8991 | if (IS_845G(dev)) |
e70236a8 JB |
8992 | dev_priv->display.get_fifo_size = i845_get_fifo_size; |
8993 | else | |
8994 | dev_priv->display.get_fifo_size = i830_get_fifo_size; | |
e70236a8 | 8995 | } |
8c9f3aaf JB |
8996 | |
8997 | /* Default just returns -ENODEV to indicate unsupported */ | |
8998 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
8999 | ||
9000 | switch (INTEL_INFO(dev)->gen) { | |
9001 | case 2: | |
9002 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
9003 | break; | |
9004 | ||
9005 | case 3: | |
9006 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
9007 | break; | |
9008 | ||
9009 | case 4: | |
9010 | case 5: | |
9011 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
9012 | break; | |
9013 | ||
9014 | case 6: | |
9015 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
9016 | break; | |
7c9017e5 JB |
9017 | case 7: |
9018 | dev_priv->display.queue_flip = intel_gen7_queue_flip; | |
9019 | break; | |
8c9f3aaf | 9020 | } |
e70236a8 JB |
9021 | } |
9022 | ||
b690e96c JB |
9023 | /* |
9024 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
9025 | * resume, or other times. This quirk makes sure that's the case for | |
9026 | * affected systems. | |
9027 | */ | |
0206e353 | 9028 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
9029 | { |
9030 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9031 | ||
9032 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
9033 | DRM_DEBUG_DRIVER("applying pipe a force quirk\n"); | |
9034 | } | |
9035 | ||
435793df KP |
9036 | /* |
9037 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
9038 | */ | |
9039 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
9040 | { | |
9041 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9042 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
9043 | } | |
9044 | ||
4dca20ef | 9045 | /* |
5a15ab5b CE |
9046 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
9047 | * brightness value | |
4dca20ef CE |
9048 | */ |
9049 | static void quirk_invert_brightness(struct drm_device *dev) | |
9050 | { | |
9051 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9052 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
9053 | } | |
9054 | ||
b690e96c JB |
9055 | struct intel_quirk { |
9056 | int device; | |
9057 | int subsystem_vendor; | |
9058 | int subsystem_device; | |
9059 | void (*hook)(struct drm_device *dev); | |
9060 | }; | |
9061 | ||
9062 | struct intel_quirk intel_quirks[] = { | |
b690e96c | 9063 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
0206e353 | 9064 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c JB |
9065 | |
9066 | /* Thinkpad R31 needs pipe A force quirk */ | |
9067 | { 0x3577, 0x1014, 0x0505, quirk_pipea_force }, | |
9068 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ | |
9069 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
9070 | ||
9071 | /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */ | |
9072 | { 0x3577, 0x1014, 0x0513, quirk_pipea_force }, | |
9073 | /* ThinkPad X40 needs pipe A force quirk */ | |
9074 | ||
9075 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ | |
9076 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
9077 | ||
9078 | /* 855 & before need to leave pipe A & dpll A up */ | |
9079 | { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
9080 | { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
435793df KP |
9081 | |
9082 | /* Lenovo U160 cannot use SSC on LVDS */ | |
9083 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
9084 | |
9085 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
9086 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b CE |
9087 | |
9088 | /* Acer Aspire 5734Z must invert backlight brightness */ | |
9089 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
b690e96c JB |
9090 | }; |
9091 | ||
9092 | static void intel_init_quirks(struct drm_device *dev) | |
9093 | { | |
9094 | struct pci_dev *d = dev->pdev; | |
9095 | int i; | |
9096 | ||
9097 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
9098 | struct intel_quirk *q = &intel_quirks[i]; | |
9099 | ||
9100 | if (d->device == q->device && | |
9101 | (d->subsystem_vendor == q->subsystem_vendor || | |
9102 | q->subsystem_vendor == PCI_ANY_ID) && | |
9103 | (d->subsystem_device == q->subsystem_device || | |
9104 | q->subsystem_device == PCI_ANY_ID)) | |
9105 | q->hook(dev); | |
9106 | } | |
9107 | } | |
9108 | ||
9cce37f4 JB |
9109 | /* Disable the VGA plane that we never use */ |
9110 | static void i915_disable_vga(struct drm_device *dev) | |
9111 | { | |
9112 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9113 | u8 sr1; | |
9114 | u32 vga_reg; | |
9115 | ||
9116 | if (HAS_PCH_SPLIT(dev)) | |
9117 | vga_reg = CPU_VGACNTRL; | |
9118 | else | |
9119 | vga_reg = VGACNTRL; | |
9120 | ||
9121 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); | |
9122 | outb(1, VGA_SR_INDEX); | |
9123 | sr1 = inb(VGA_SR_DATA); | |
9124 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
9125 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
9126 | udelay(300); | |
9127 | ||
9128 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); | |
9129 | POSTING_READ(vga_reg); | |
9130 | } | |
9131 | ||
79e53945 JB |
9132 | void intel_modeset_init(struct drm_device *dev) |
9133 | { | |
652c393a | 9134 | struct drm_i915_private *dev_priv = dev->dev_private; |
b840d907 | 9135 | int i, ret; |
79e53945 JB |
9136 | |
9137 | drm_mode_config_init(dev); | |
9138 | ||
9139 | dev->mode_config.min_width = 0; | |
9140 | dev->mode_config.min_height = 0; | |
9141 | ||
019d96cb DA |
9142 | dev->mode_config.preferred_depth = 24; |
9143 | dev->mode_config.prefer_shadow = 1; | |
9144 | ||
79e53945 JB |
9145 | dev->mode_config.funcs = (void *)&intel_mode_funcs; |
9146 | ||
b690e96c JB |
9147 | intel_init_quirks(dev); |
9148 | ||
e70236a8 JB |
9149 | intel_init_display(dev); |
9150 | ||
a6c45cf0 CW |
9151 | if (IS_GEN2(dev)) { |
9152 | dev->mode_config.max_width = 2048; | |
9153 | dev->mode_config.max_height = 2048; | |
9154 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
9155 | dev->mode_config.max_width = 4096; |
9156 | dev->mode_config.max_height = 4096; | |
79e53945 | 9157 | } else { |
a6c45cf0 CW |
9158 | dev->mode_config.max_width = 8192; |
9159 | dev->mode_config.max_height = 8192; | |
79e53945 | 9160 | } |
35c3047a | 9161 | dev->mode_config.fb_base = dev->agp->base; |
79e53945 | 9162 | |
28c97730 | 9163 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
a3524f1b | 9164 | dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : ""); |
79e53945 | 9165 | |
a3524f1b | 9166 | for (i = 0; i < dev_priv->num_pipe; i++) { |
79e53945 | 9167 | intel_crtc_init(dev, i); |
00c2064b JB |
9168 | ret = intel_plane_init(dev, i); |
9169 | if (ret) | |
9170 | DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret); | |
79e53945 JB |
9171 | } |
9172 | ||
9cce37f4 JB |
9173 | /* Just disable it once at startup */ |
9174 | i915_disable_vga(dev); | |
79e53945 | 9175 | intel_setup_outputs(dev); |
652c393a | 9176 | |
645c62a5 | 9177 | intel_init_clock_gating(dev); |
9cce37f4 | 9178 | |
7648fa99 | 9179 | if (IS_IRONLAKE_M(dev)) { |
f97108d1 | 9180 | ironlake_enable_drps(dev); |
7648fa99 JB |
9181 | intel_init_emon(dev); |
9182 | } | |
f97108d1 | 9183 | |
1c70c0ce | 9184 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
3b8d8d91 | 9185 | gen6_enable_rps(dev_priv); |
23b2f8bb JB |
9186 | gen6_update_ring_freq(dev_priv); |
9187 | } | |
3b8d8d91 | 9188 | |
652c393a JB |
9189 | INIT_WORK(&dev_priv->idle_work, intel_idle_update); |
9190 | setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer, | |
9191 | (unsigned long)dev); | |
2c7111db CW |
9192 | } |
9193 | ||
9194 | void intel_modeset_gem_init(struct drm_device *dev) | |
9195 | { | |
9196 | if (IS_IRONLAKE_M(dev)) | |
9197 | ironlake_enable_rc6(dev); | |
02e792fb DV |
9198 | |
9199 | intel_setup_overlay(dev); | |
79e53945 JB |
9200 | } |
9201 | ||
9202 | void intel_modeset_cleanup(struct drm_device *dev) | |
9203 | { | |
652c393a JB |
9204 | struct drm_i915_private *dev_priv = dev->dev_private; |
9205 | struct drm_crtc *crtc; | |
9206 | struct intel_crtc *intel_crtc; | |
9207 | ||
f87ea761 | 9208 | drm_kms_helper_poll_fini(dev); |
652c393a JB |
9209 | mutex_lock(&dev->struct_mutex); |
9210 | ||
723bfd70 JB |
9211 | intel_unregister_dsm_handler(); |
9212 | ||
9213 | ||
652c393a JB |
9214 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
9215 | /* Skip inactive CRTCs */ | |
9216 | if (!crtc->fb) | |
9217 | continue; | |
9218 | ||
9219 | intel_crtc = to_intel_crtc(crtc); | |
3dec0095 | 9220 | intel_increase_pllclock(crtc); |
652c393a JB |
9221 | } |
9222 | ||
973d04f9 | 9223 | intel_disable_fbc(dev); |
e70236a8 | 9224 | |
f97108d1 JB |
9225 | if (IS_IRONLAKE_M(dev)) |
9226 | ironlake_disable_drps(dev); | |
1c70c0ce | 9227 | if (IS_GEN6(dev) || IS_GEN7(dev)) |
3b8d8d91 | 9228 | gen6_disable_rps(dev); |
f97108d1 | 9229 | |
d5bb081b JB |
9230 | if (IS_IRONLAKE_M(dev)) |
9231 | ironlake_disable_rc6(dev); | |
0cdab21f | 9232 | |
69341a5e KH |
9233 | mutex_unlock(&dev->struct_mutex); |
9234 | ||
6c0d9350 DV |
9235 | /* Disable the irq before mode object teardown, for the irq might |
9236 | * enqueue unpin/hotplug work. */ | |
9237 | drm_irq_uninstall(dev); | |
9238 | cancel_work_sync(&dev_priv->hotplug_work); | |
6fdd4d98 | 9239 | cancel_work_sync(&dev_priv->rps_work); |
6c0d9350 | 9240 | |
1630fe75 CW |
9241 | /* flush any delayed tasks or pending work */ |
9242 | flush_scheduled_work(); | |
9243 | ||
3dec0095 DV |
9244 | /* Shut off idle work before the crtcs get freed. */ |
9245 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
9246 | intel_crtc = to_intel_crtc(crtc); | |
9247 | del_timer_sync(&intel_crtc->idle_timer); | |
9248 | } | |
9249 | del_timer_sync(&dev_priv->idle_timer); | |
9250 | cancel_work_sync(&dev_priv->idle_work); | |
9251 | ||
79e53945 JB |
9252 | drm_mode_config_cleanup(dev); |
9253 | } | |
9254 | ||
f1c79df3 ZW |
9255 | /* |
9256 | * Return which encoder is currently attached for connector. | |
9257 | */ | |
df0e9248 | 9258 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 9259 | { |
df0e9248 CW |
9260 | return &intel_attached_encoder(connector)->base; |
9261 | } | |
f1c79df3 | 9262 | |
df0e9248 CW |
9263 | void intel_connector_attach_encoder(struct intel_connector *connector, |
9264 | struct intel_encoder *encoder) | |
9265 | { | |
9266 | connector->encoder = encoder; | |
9267 | drm_mode_connector_attach_encoder(&connector->base, | |
9268 | &encoder->base); | |
79e53945 | 9269 | } |
28d52043 DA |
9270 | |
9271 | /* | |
9272 | * set vga decode state - true == enable VGA decode | |
9273 | */ | |
9274 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
9275 | { | |
9276 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9277 | u16 gmch_ctrl; | |
9278 | ||
9279 | pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl); | |
9280 | if (state) | |
9281 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
9282 | else | |
9283 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
9284 | pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl); | |
9285 | return 0; | |
9286 | } | |
c4a1d9e4 CW |
9287 | |
9288 | #ifdef CONFIG_DEBUG_FS | |
9289 | #include <linux/seq_file.h> | |
9290 | ||
9291 | struct intel_display_error_state { | |
9292 | struct intel_cursor_error_state { | |
9293 | u32 control; | |
9294 | u32 position; | |
9295 | u32 base; | |
9296 | u32 size; | |
9297 | } cursor[2]; | |
9298 | ||
9299 | struct intel_pipe_error_state { | |
9300 | u32 conf; | |
9301 | u32 source; | |
9302 | ||
9303 | u32 htotal; | |
9304 | u32 hblank; | |
9305 | u32 hsync; | |
9306 | u32 vtotal; | |
9307 | u32 vblank; | |
9308 | u32 vsync; | |
9309 | } pipe[2]; | |
9310 | ||
9311 | struct intel_plane_error_state { | |
9312 | u32 control; | |
9313 | u32 stride; | |
9314 | u32 size; | |
9315 | u32 pos; | |
9316 | u32 addr; | |
9317 | u32 surface; | |
9318 | u32 tile_offset; | |
9319 | } plane[2]; | |
9320 | }; | |
9321 | ||
9322 | struct intel_display_error_state * | |
9323 | intel_display_capture_error_state(struct drm_device *dev) | |
9324 | { | |
0206e353 | 9325 | drm_i915_private_t *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
9326 | struct intel_display_error_state *error; |
9327 | int i; | |
9328 | ||
9329 | error = kmalloc(sizeof(*error), GFP_ATOMIC); | |
9330 | if (error == NULL) | |
9331 | return NULL; | |
9332 | ||
9333 | for (i = 0; i < 2; i++) { | |
9334 | error->cursor[i].control = I915_READ(CURCNTR(i)); | |
9335 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
9336 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
9337 | ||
9338 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
9339 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
9340 | error->plane[i].size = I915_READ(DSPSIZE(i)); | |
0206e353 | 9341 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
c4a1d9e4 CW |
9342 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
9343 | if (INTEL_INFO(dev)->gen >= 4) { | |
9344 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
9345 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
9346 | } | |
9347 | ||
9348 | error->pipe[i].conf = I915_READ(PIPECONF(i)); | |
9349 | error->pipe[i].source = I915_READ(PIPESRC(i)); | |
9350 | error->pipe[i].htotal = I915_READ(HTOTAL(i)); | |
9351 | error->pipe[i].hblank = I915_READ(HBLANK(i)); | |
9352 | error->pipe[i].hsync = I915_READ(HSYNC(i)); | |
9353 | error->pipe[i].vtotal = I915_READ(VTOTAL(i)); | |
9354 | error->pipe[i].vblank = I915_READ(VBLANK(i)); | |
9355 | error->pipe[i].vsync = I915_READ(VSYNC(i)); | |
9356 | } | |
9357 | ||
9358 | return error; | |
9359 | } | |
9360 | ||
9361 | void | |
9362 | intel_display_print_error_state(struct seq_file *m, | |
9363 | struct drm_device *dev, | |
9364 | struct intel_display_error_state *error) | |
9365 | { | |
9366 | int i; | |
9367 | ||
9368 | for (i = 0; i < 2; i++) { | |
9369 | seq_printf(m, "Pipe [%d]:\n", i); | |
9370 | seq_printf(m, " CONF: %08x\n", error->pipe[i].conf); | |
9371 | seq_printf(m, " SRC: %08x\n", error->pipe[i].source); | |
9372 | seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal); | |
9373 | seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank); | |
9374 | seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync); | |
9375 | seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal); | |
9376 | seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank); | |
9377 | seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync); | |
9378 | ||
9379 | seq_printf(m, "Plane [%d]:\n", i); | |
9380 | seq_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
9381 | seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
9382 | seq_printf(m, " SIZE: %08x\n", error->plane[i].size); | |
9383 | seq_printf(m, " POS: %08x\n", error->plane[i].pos); | |
9384 | seq_printf(m, " ADDR: %08x\n", error->plane[i].addr); | |
9385 | if (INTEL_INFO(dev)->gen >= 4) { | |
9386 | seq_printf(m, " SURF: %08x\n", error->plane[i].surface); | |
9387 | seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
9388 | } | |
9389 | ||
9390 | seq_printf(m, "Cursor [%d]:\n", i); | |
9391 | seq_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
9392 | seq_printf(m, " POS: %08x\n", error->cursor[i].position); | |
9393 | seq_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
9394 | } | |
9395 | } | |
9396 | #endif |