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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
27 | #include <linux/i2c.h> | |
28 | #include "drmP.h" | |
29 | #include "intel_drv.h" | |
30 | #include "i915_drm.h" | |
31 | #include "i915_drv.h" | |
32 | ||
33 | #include "drm_crtc_helper.h" | |
34 | ||
35 | bool intel_pipe_has_type (struct drm_crtc *crtc, int type); | |
36 | ||
37 | typedef struct { | |
38 | /* given values */ | |
39 | int n; | |
40 | int m1, m2; | |
41 | int p1, p2; | |
42 | /* derived values */ | |
43 | int dot; | |
44 | int vco; | |
45 | int m; | |
46 | int p; | |
47 | } intel_clock_t; | |
48 | ||
49 | typedef struct { | |
50 | int min, max; | |
51 | } intel_range_t; | |
52 | ||
53 | typedef struct { | |
54 | int dot_limit; | |
55 | int p2_slow, p2_fast; | |
56 | } intel_p2_t; | |
57 | ||
58 | #define INTEL_P2_NUM 2 | |
d4906093 ML |
59 | typedef struct intel_limit intel_limit_t; |
60 | struct intel_limit { | |
79e53945 JB |
61 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
62 | intel_p2_t p2; | |
d4906093 ML |
63 | bool (* find_pll)(const intel_limit_t *, struct drm_crtc *, |
64 | int, int, intel_clock_t *); | |
65 | }; | |
79e53945 JB |
66 | |
67 | #define I8XX_DOT_MIN 25000 | |
68 | #define I8XX_DOT_MAX 350000 | |
69 | #define I8XX_VCO_MIN 930000 | |
70 | #define I8XX_VCO_MAX 1400000 | |
71 | #define I8XX_N_MIN 3 | |
72 | #define I8XX_N_MAX 16 | |
73 | #define I8XX_M_MIN 96 | |
74 | #define I8XX_M_MAX 140 | |
75 | #define I8XX_M1_MIN 18 | |
76 | #define I8XX_M1_MAX 26 | |
77 | #define I8XX_M2_MIN 6 | |
78 | #define I8XX_M2_MAX 16 | |
79 | #define I8XX_P_MIN 4 | |
80 | #define I8XX_P_MAX 128 | |
81 | #define I8XX_P1_MIN 2 | |
82 | #define I8XX_P1_MAX 33 | |
83 | #define I8XX_P1_LVDS_MIN 1 | |
84 | #define I8XX_P1_LVDS_MAX 6 | |
85 | #define I8XX_P2_SLOW 4 | |
86 | #define I8XX_P2_FAST 2 | |
87 | #define I8XX_P2_LVDS_SLOW 14 | |
88 | #define I8XX_P2_LVDS_FAST 14 /* No fast option */ | |
89 | #define I8XX_P2_SLOW_LIMIT 165000 | |
90 | ||
91 | #define I9XX_DOT_MIN 20000 | |
92 | #define I9XX_DOT_MAX 400000 | |
93 | #define I9XX_VCO_MIN 1400000 | |
94 | #define I9XX_VCO_MAX 2800000 | |
2177832f SL |
95 | #define IGD_VCO_MIN 1700000 |
96 | #define IGD_VCO_MAX 3500000 | |
f3cade5c KH |
97 | #define I9XX_N_MIN 1 |
98 | #define I9XX_N_MAX 6 | |
2177832f SL |
99 | /* IGD's Ncounter is a ring counter */ |
100 | #define IGD_N_MIN 3 | |
101 | #define IGD_N_MAX 6 | |
79e53945 JB |
102 | #define I9XX_M_MIN 70 |
103 | #define I9XX_M_MAX 120 | |
2177832f SL |
104 | #define IGD_M_MIN 2 |
105 | #define IGD_M_MAX 256 | |
79e53945 | 106 | #define I9XX_M1_MIN 10 |
f3cade5c | 107 | #define I9XX_M1_MAX 22 |
79e53945 JB |
108 | #define I9XX_M2_MIN 5 |
109 | #define I9XX_M2_MAX 9 | |
2177832f SL |
110 | /* IGD M1 is reserved, and must be 0 */ |
111 | #define IGD_M1_MIN 0 | |
112 | #define IGD_M1_MAX 0 | |
113 | #define IGD_M2_MIN 0 | |
114 | #define IGD_M2_MAX 254 | |
79e53945 JB |
115 | #define I9XX_P_SDVO_DAC_MIN 5 |
116 | #define I9XX_P_SDVO_DAC_MAX 80 | |
117 | #define I9XX_P_LVDS_MIN 7 | |
118 | #define I9XX_P_LVDS_MAX 98 | |
2177832f SL |
119 | #define IGD_P_LVDS_MIN 7 |
120 | #define IGD_P_LVDS_MAX 112 | |
79e53945 JB |
121 | #define I9XX_P1_MIN 1 |
122 | #define I9XX_P1_MAX 8 | |
123 | #define I9XX_P2_SDVO_DAC_SLOW 10 | |
124 | #define I9XX_P2_SDVO_DAC_FAST 5 | |
125 | #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000 | |
126 | #define I9XX_P2_LVDS_SLOW 14 | |
127 | #define I9XX_P2_LVDS_FAST 7 | |
128 | #define I9XX_P2_LVDS_SLOW_LIMIT 112000 | |
129 | ||
130 | #define INTEL_LIMIT_I8XX_DVO_DAC 0 | |
131 | #define INTEL_LIMIT_I8XX_LVDS 1 | |
132 | #define INTEL_LIMIT_I9XX_SDVO_DAC 2 | |
133 | #define INTEL_LIMIT_I9XX_LVDS 3 | |
044c7c41 ML |
134 | #define INTEL_LIMIT_G4X_SDVO 4 |
135 | #define INTEL_LIMIT_G4X_HDMI_DAC 5 | |
136 | #define INTEL_LIMIT_G4X_SINGLE_CHANNEL_LVDS 6 | |
137 | #define INTEL_LIMIT_G4X_DUAL_CHANNEL_LVDS 7 | |
2177832f SL |
138 | #define INTEL_LIMIT_IGD_SDVO_DAC 8 |
139 | #define INTEL_LIMIT_IGD_LVDS 9 | |
2c07245f ZW |
140 | #define INTEL_LIMIT_IGDNG_SDVO_DAC 10 |
141 | #define INTEL_LIMIT_IGDNG_LVDS 11 | |
044c7c41 ML |
142 | |
143 | /*The parameter is for SDVO on G4x platform*/ | |
144 | #define G4X_DOT_SDVO_MIN 25000 | |
145 | #define G4X_DOT_SDVO_MAX 270000 | |
146 | #define G4X_VCO_MIN 1750000 | |
147 | #define G4X_VCO_MAX 3500000 | |
148 | #define G4X_N_SDVO_MIN 1 | |
149 | #define G4X_N_SDVO_MAX 4 | |
150 | #define G4X_M_SDVO_MIN 104 | |
151 | #define G4X_M_SDVO_MAX 138 | |
152 | #define G4X_M1_SDVO_MIN 17 | |
153 | #define G4X_M1_SDVO_MAX 23 | |
154 | #define G4X_M2_SDVO_MIN 5 | |
155 | #define G4X_M2_SDVO_MAX 11 | |
156 | #define G4X_P_SDVO_MIN 10 | |
157 | #define G4X_P_SDVO_MAX 30 | |
158 | #define G4X_P1_SDVO_MIN 1 | |
159 | #define G4X_P1_SDVO_MAX 3 | |
160 | #define G4X_P2_SDVO_SLOW 10 | |
161 | #define G4X_P2_SDVO_FAST 10 | |
162 | #define G4X_P2_SDVO_LIMIT 270000 | |
163 | ||
164 | /*The parameter is for HDMI_DAC on G4x platform*/ | |
165 | #define G4X_DOT_HDMI_DAC_MIN 22000 | |
166 | #define G4X_DOT_HDMI_DAC_MAX 400000 | |
167 | #define G4X_N_HDMI_DAC_MIN 1 | |
168 | #define G4X_N_HDMI_DAC_MAX 4 | |
169 | #define G4X_M_HDMI_DAC_MIN 104 | |
170 | #define G4X_M_HDMI_DAC_MAX 138 | |
171 | #define G4X_M1_HDMI_DAC_MIN 16 | |
172 | #define G4X_M1_HDMI_DAC_MAX 23 | |
173 | #define G4X_M2_HDMI_DAC_MIN 5 | |
174 | #define G4X_M2_HDMI_DAC_MAX 11 | |
175 | #define G4X_P_HDMI_DAC_MIN 5 | |
176 | #define G4X_P_HDMI_DAC_MAX 80 | |
177 | #define G4X_P1_HDMI_DAC_MIN 1 | |
178 | #define G4X_P1_HDMI_DAC_MAX 8 | |
179 | #define G4X_P2_HDMI_DAC_SLOW 10 | |
180 | #define G4X_P2_HDMI_DAC_FAST 5 | |
181 | #define G4X_P2_HDMI_DAC_LIMIT 165000 | |
182 | ||
183 | /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/ | |
184 | #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000 | |
185 | #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000 | |
186 | #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1 | |
187 | #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3 | |
188 | #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104 | |
189 | #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138 | |
190 | #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17 | |
191 | #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23 | |
192 | #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5 | |
193 | #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11 | |
194 | #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28 | |
195 | #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112 | |
196 | #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2 | |
197 | #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8 | |
198 | #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14 | |
199 | #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14 | |
200 | #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0 | |
201 | ||
202 | /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/ | |
203 | #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000 | |
204 | #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000 | |
205 | #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1 | |
206 | #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3 | |
207 | #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104 | |
208 | #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138 | |
209 | #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17 | |
210 | #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23 | |
211 | #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5 | |
212 | #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11 | |
213 | #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14 | |
214 | #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42 | |
215 | #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2 | |
216 | #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6 | |
217 | #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7 | |
218 | #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7 | |
219 | #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0 | |
220 | ||
2c07245f ZW |
221 | /* IGDNG */ |
222 | /* as we calculate clock using (register_value + 2) for | |
223 | N/M1/M2, so here the range value for them is (actual_value-2). | |
224 | */ | |
225 | #define IGDNG_DOT_MIN 25000 | |
226 | #define IGDNG_DOT_MAX 350000 | |
227 | #define IGDNG_VCO_MIN 1760000 | |
228 | #define IGDNG_VCO_MAX 3510000 | |
229 | #define IGDNG_N_MIN 1 | |
230 | #define IGDNG_N_MAX 5 | |
231 | #define IGDNG_M_MIN 79 | |
232 | #define IGDNG_M_MAX 118 | |
233 | #define IGDNG_M1_MIN 12 | |
234 | #define IGDNG_M1_MAX 23 | |
235 | #define IGDNG_M2_MIN 5 | |
236 | #define IGDNG_M2_MAX 9 | |
237 | #define IGDNG_P_SDVO_DAC_MIN 5 | |
238 | #define IGDNG_P_SDVO_DAC_MAX 80 | |
239 | #define IGDNG_P_LVDS_MIN 28 | |
240 | #define IGDNG_P_LVDS_MAX 112 | |
241 | #define IGDNG_P1_MIN 1 | |
242 | #define IGDNG_P1_MAX 8 | |
243 | #define IGDNG_P2_SDVO_DAC_SLOW 10 | |
244 | #define IGDNG_P2_SDVO_DAC_FAST 5 | |
245 | #define IGDNG_P2_LVDS_SLOW 14 /* single channel */ | |
246 | #define IGDNG_P2_LVDS_FAST 7 /* double channel */ | |
247 | #define IGDNG_P2_DOT_LIMIT 225000 /* 225Mhz */ | |
248 | ||
d4906093 ML |
249 | static bool |
250 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
251 | int target, int refclk, intel_clock_t *best_clock); | |
252 | static bool | |
253 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
254 | int target, int refclk, intel_clock_t *best_clock); | |
2c07245f ZW |
255 | static bool |
256 | intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
257 | int target, int refclk, intel_clock_t *best_clock); | |
79e53945 JB |
258 | |
259 | static const intel_limit_t intel_limits[] = { | |
260 | { /* INTEL_LIMIT_I8XX_DVO_DAC */ | |
261 | .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX }, | |
262 | .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX }, | |
263 | .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX }, | |
264 | .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX }, | |
265 | .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX }, | |
266 | .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX }, | |
267 | .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX }, | |
268 | .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX }, | |
269 | .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT, | |
270 | .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST }, | |
d4906093 | 271 | .find_pll = intel_find_best_PLL, |
79e53945 JB |
272 | }, |
273 | { /* INTEL_LIMIT_I8XX_LVDS */ | |
274 | .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX }, | |
275 | .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX }, | |
276 | .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX }, | |
277 | .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX }, | |
278 | .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX }, | |
279 | .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX }, | |
280 | .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX }, | |
281 | .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX }, | |
282 | .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT, | |
283 | .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST }, | |
d4906093 | 284 | .find_pll = intel_find_best_PLL, |
79e53945 JB |
285 | }, |
286 | { /* INTEL_LIMIT_I9XX_SDVO_DAC */ | |
287 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, | |
288 | .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX }, | |
289 | .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX }, | |
290 | .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX }, | |
291 | .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX }, | |
292 | .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX }, | |
293 | .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX }, | |
294 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, | |
295 | .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, | |
296 | .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST }, | |
d4906093 | 297 | .find_pll = intel_find_best_PLL, |
79e53945 JB |
298 | }, |
299 | { /* INTEL_LIMIT_I9XX_LVDS */ | |
300 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, | |
301 | .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX }, | |
302 | .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX }, | |
303 | .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX }, | |
304 | .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX }, | |
305 | .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX }, | |
306 | .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX }, | |
307 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, | |
308 | /* The single-channel range is 25-112Mhz, and dual-channel | |
309 | * is 80-224Mhz. Prefer single channel as much as possible. | |
310 | */ | |
311 | .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, | |
312 | .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST }, | |
d4906093 | 313 | .find_pll = intel_find_best_PLL, |
79e53945 | 314 | }, |
044c7c41 ML |
315 | /* below parameter and function is for G4X Chipset Family*/ |
316 | { /* INTEL_LIMIT_G4X_SDVO */ | |
317 | .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX }, | |
318 | .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX}, | |
319 | .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX }, | |
320 | .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX }, | |
321 | .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX }, | |
322 | .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX }, | |
323 | .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX }, | |
324 | .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX}, | |
325 | .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT, | |
326 | .p2_slow = G4X_P2_SDVO_SLOW, | |
327 | .p2_fast = G4X_P2_SDVO_FAST | |
328 | }, | |
d4906093 | 329 | .find_pll = intel_g4x_find_best_PLL, |
044c7c41 ML |
330 | }, |
331 | { /* INTEL_LIMIT_G4X_HDMI_DAC */ | |
332 | .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX }, | |
333 | .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX}, | |
334 | .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX }, | |
335 | .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX }, | |
336 | .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX }, | |
337 | .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX }, | |
338 | .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX }, | |
339 | .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX}, | |
340 | .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT, | |
341 | .p2_slow = G4X_P2_HDMI_DAC_SLOW, | |
342 | .p2_fast = G4X_P2_HDMI_DAC_FAST | |
343 | }, | |
d4906093 | 344 | .find_pll = intel_g4x_find_best_PLL, |
044c7c41 ML |
345 | }, |
346 | { /* INTEL_LIMIT_G4X_SINGLE_CHANNEL_LVDS */ | |
347 | .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN, | |
348 | .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX }, | |
349 | .vco = { .min = G4X_VCO_MIN, | |
350 | .max = G4X_VCO_MAX }, | |
351 | .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN, | |
352 | .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX }, | |
353 | .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN, | |
354 | .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX }, | |
355 | .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN, | |
356 | .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX }, | |
357 | .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN, | |
358 | .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX }, | |
359 | .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN, | |
360 | .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX }, | |
361 | .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN, | |
362 | .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX }, | |
363 | .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT, | |
364 | .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW, | |
365 | .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST | |
366 | }, | |
d4906093 | 367 | .find_pll = intel_g4x_find_best_PLL, |
044c7c41 ML |
368 | }, |
369 | { /* INTEL_LIMIT_G4X_DUAL_CHANNEL_LVDS */ | |
370 | .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN, | |
371 | .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX }, | |
372 | .vco = { .min = G4X_VCO_MIN, | |
373 | .max = G4X_VCO_MAX }, | |
374 | .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN, | |
375 | .max = G4X_N_DUAL_CHANNEL_LVDS_MAX }, | |
376 | .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN, | |
377 | .max = G4X_M_DUAL_CHANNEL_LVDS_MAX }, | |
378 | .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN, | |
379 | .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX }, | |
380 | .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN, | |
381 | .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX }, | |
382 | .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN, | |
383 | .max = G4X_P_DUAL_CHANNEL_LVDS_MAX }, | |
384 | .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN, | |
385 | .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX }, | |
386 | .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT, | |
387 | .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW, | |
388 | .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST | |
389 | }, | |
d4906093 | 390 | .find_pll = intel_g4x_find_best_PLL, |
044c7c41 | 391 | }, |
2177832f SL |
392 | { /* INTEL_LIMIT_IGD_SDVO */ |
393 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX}, | |
394 | .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX }, | |
395 | .n = { .min = IGD_N_MIN, .max = IGD_N_MAX }, | |
396 | .m = { .min = IGD_M_MIN, .max = IGD_M_MAX }, | |
397 | .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX }, | |
398 | .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX }, | |
399 | .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX }, | |
400 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, | |
401 | .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, | |
402 | .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST }, | |
6115707b | 403 | .find_pll = intel_find_best_PLL, |
2177832f SL |
404 | }, |
405 | { /* INTEL_LIMIT_IGD_LVDS */ | |
406 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, | |
407 | .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX }, | |
408 | .n = { .min = IGD_N_MIN, .max = IGD_N_MAX }, | |
409 | .m = { .min = IGD_M_MIN, .max = IGD_M_MAX }, | |
410 | .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX }, | |
411 | .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX }, | |
412 | .p = { .min = IGD_P_LVDS_MIN, .max = IGD_P_LVDS_MAX }, | |
413 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, | |
414 | /* IGD only supports single-channel mode. */ | |
415 | .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, | |
416 | .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW }, | |
6115707b | 417 | .find_pll = intel_find_best_PLL, |
2177832f | 418 | }, |
2c07245f ZW |
419 | { /* INTEL_LIMIT_IGDNG_SDVO_DAC */ |
420 | .dot = { .min = IGDNG_DOT_MIN, .max = IGDNG_DOT_MAX }, | |
421 | .vco = { .min = IGDNG_VCO_MIN, .max = IGDNG_VCO_MAX }, | |
422 | .n = { .min = IGDNG_N_MIN, .max = IGDNG_N_MAX }, | |
423 | .m = { .min = IGDNG_M_MIN, .max = IGDNG_M_MAX }, | |
424 | .m1 = { .min = IGDNG_M1_MIN, .max = IGDNG_M1_MAX }, | |
425 | .m2 = { .min = IGDNG_M2_MIN, .max = IGDNG_M2_MAX }, | |
426 | .p = { .min = IGDNG_P_SDVO_DAC_MIN, .max = IGDNG_P_SDVO_DAC_MAX }, | |
427 | .p1 = { .min = IGDNG_P1_MIN, .max = IGDNG_P1_MAX }, | |
428 | .p2 = { .dot_limit = IGDNG_P2_DOT_LIMIT, | |
429 | .p2_slow = IGDNG_P2_SDVO_DAC_SLOW, | |
430 | .p2_fast = IGDNG_P2_SDVO_DAC_FAST }, | |
431 | .find_pll = intel_igdng_find_best_PLL, | |
432 | }, | |
433 | { /* INTEL_LIMIT_IGDNG_LVDS */ | |
434 | .dot = { .min = IGDNG_DOT_MIN, .max = IGDNG_DOT_MAX }, | |
435 | .vco = { .min = IGDNG_VCO_MIN, .max = IGDNG_VCO_MAX }, | |
436 | .n = { .min = IGDNG_N_MIN, .max = IGDNG_N_MAX }, | |
437 | .m = { .min = IGDNG_M_MIN, .max = IGDNG_M_MAX }, | |
438 | .m1 = { .min = IGDNG_M1_MIN, .max = IGDNG_M1_MAX }, | |
439 | .m2 = { .min = IGDNG_M2_MIN, .max = IGDNG_M2_MAX }, | |
440 | .p = { .min = IGDNG_P_LVDS_MIN, .max = IGDNG_P_LVDS_MAX }, | |
441 | .p1 = { .min = IGDNG_P1_MIN, .max = IGDNG_P1_MAX }, | |
442 | .p2 = { .dot_limit = IGDNG_P2_DOT_LIMIT, | |
443 | .p2_slow = IGDNG_P2_LVDS_SLOW, | |
444 | .p2_fast = IGDNG_P2_LVDS_FAST }, | |
445 | .find_pll = intel_igdng_find_best_PLL, | |
446 | }, | |
79e53945 JB |
447 | }; |
448 | ||
2c07245f ZW |
449 | static const intel_limit_t *intel_igdng_limit(struct drm_crtc *crtc) |
450 | { | |
451 | const intel_limit_t *limit; | |
452 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
453 | limit = &intel_limits[INTEL_LIMIT_IGDNG_LVDS]; | |
454 | else | |
455 | limit = &intel_limits[INTEL_LIMIT_IGDNG_SDVO_DAC]; | |
456 | ||
457 | return limit; | |
458 | } | |
459 | ||
044c7c41 ML |
460 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
461 | { | |
462 | struct drm_device *dev = crtc->dev; | |
463 | struct drm_i915_private *dev_priv = dev->dev_private; | |
464 | const intel_limit_t *limit; | |
465 | ||
466 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
467 | if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == | |
468 | LVDS_CLKB_POWER_UP) | |
469 | /* LVDS with dual channel */ | |
470 | limit = &intel_limits | |
471 | [INTEL_LIMIT_G4X_DUAL_CHANNEL_LVDS]; | |
472 | else | |
473 | /* LVDS with dual channel */ | |
474 | limit = &intel_limits | |
475 | [INTEL_LIMIT_G4X_SINGLE_CHANNEL_LVDS]; | |
476 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || | |
477 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
478 | limit = &intel_limits[INTEL_LIMIT_G4X_HDMI_DAC]; | |
479 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { | |
480 | limit = &intel_limits[INTEL_LIMIT_G4X_SDVO]; | |
481 | } else /* The option is for other outputs */ | |
482 | limit = &intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC]; | |
483 | ||
484 | return limit; | |
485 | } | |
486 | ||
79e53945 JB |
487 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc) |
488 | { | |
489 | struct drm_device *dev = crtc->dev; | |
490 | const intel_limit_t *limit; | |
491 | ||
2c07245f ZW |
492 | if (IS_IGDNG(dev)) |
493 | limit = intel_igdng_limit(crtc); | |
494 | else if (IS_G4X(dev)) { | |
044c7c41 | 495 | limit = intel_g4x_limit(crtc); |
2177832f | 496 | } else if (IS_I9XX(dev) && !IS_IGD(dev)) { |
79e53945 JB |
497 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
498 | limit = &intel_limits[INTEL_LIMIT_I9XX_LVDS]; | |
499 | else | |
500 | limit = &intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC]; | |
2177832f SL |
501 | } else if (IS_IGD(dev)) { |
502 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
503 | limit = &intel_limits[INTEL_LIMIT_IGD_LVDS]; | |
504 | else | |
505 | limit = &intel_limits[INTEL_LIMIT_IGD_SDVO_DAC]; | |
79e53945 JB |
506 | } else { |
507 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
508 | limit = &intel_limits[INTEL_LIMIT_I8XX_LVDS]; | |
509 | else | |
510 | limit = &intel_limits[INTEL_LIMIT_I8XX_DVO_DAC]; | |
511 | } | |
512 | return limit; | |
513 | } | |
514 | ||
2177832f SL |
515 | /* m1 is reserved as 0 in IGD, n is a ring counter */ |
516 | static void igd_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 517 | { |
2177832f SL |
518 | clock->m = clock->m2 + 2; |
519 | clock->p = clock->p1 * clock->p2; | |
520 | clock->vco = refclk * clock->m / clock->n; | |
521 | clock->dot = clock->vco / clock->p; | |
522 | } | |
523 | ||
524 | static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock) | |
525 | { | |
526 | if (IS_IGD(dev)) { | |
527 | igd_clock(refclk, clock); | |
528 | return; | |
529 | } | |
79e53945 JB |
530 | clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); |
531 | clock->p = clock->p1 * clock->p2; | |
532 | clock->vco = refclk * clock->m / (clock->n + 2); | |
533 | clock->dot = clock->vco / clock->p; | |
534 | } | |
535 | ||
79e53945 JB |
536 | /** |
537 | * Returns whether any output on the specified pipe is of the specified type | |
538 | */ | |
539 | bool intel_pipe_has_type (struct drm_crtc *crtc, int type) | |
540 | { | |
541 | struct drm_device *dev = crtc->dev; | |
542 | struct drm_mode_config *mode_config = &dev->mode_config; | |
543 | struct drm_connector *l_entry; | |
544 | ||
545 | list_for_each_entry(l_entry, &mode_config->connector_list, head) { | |
546 | if (l_entry->encoder && | |
547 | l_entry->encoder->crtc == crtc) { | |
548 | struct intel_output *intel_output = to_intel_output(l_entry); | |
549 | if (intel_output->type == type) | |
550 | return true; | |
551 | } | |
552 | } | |
553 | return false; | |
554 | } | |
555 | ||
7c04d1d9 | 556 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
557 | /** |
558 | * Returns whether the given set of divisors are valid for a given refclk with | |
559 | * the given connectors. | |
560 | */ | |
561 | ||
562 | static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock) | |
563 | { | |
564 | const intel_limit_t *limit = intel_limit (crtc); | |
2177832f | 565 | struct drm_device *dev = crtc->dev; |
79e53945 JB |
566 | |
567 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) | |
568 | INTELPllInvalid ("p1 out of range\n"); | |
569 | if (clock->p < limit->p.min || limit->p.max < clock->p) | |
570 | INTELPllInvalid ("p out of range\n"); | |
571 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) | |
572 | INTELPllInvalid ("m2 out of range\n"); | |
573 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) | |
574 | INTELPllInvalid ("m1 out of range\n"); | |
2177832f | 575 | if (clock->m1 <= clock->m2 && !IS_IGD(dev)) |
79e53945 JB |
576 | INTELPllInvalid ("m1 <= m2\n"); |
577 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
578 | INTELPllInvalid ("m out of range\n"); | |
579 | if (clock->n < limit->n.min || limit->n.max < clock->n) | |
580 | INTELPllInvalid ("n out of range\n"); | |
581 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) | |
582 | INTELPllInvalid ("vco out of range\n"); | |
583 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, | |
584 | * connector, etc., rather than just a single range. | |
585 | */ | |
586 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
587 | INTELPllInvalid ("dot out of range\n"); | |
588 | ||
589 | return true; | |
590 | } | |
591 | ||
d4906093 ML |
592 | static bool |
593 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
594 | int target, int refclk, intel_clock_t *best_clock) | |
595 | ||
79e53945 JB |
596 | { |
597 | struct drm_device *dev = crtc->dev; | |
598 | struct drm_i915_private *dev_priv = dev->dev_private; | |
599 | intel_clock_t clock; | |
79e53945 JB |
600 | int err = target; |
601 | ||
602 | if (IS_I9XX(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && | |
603 | (I915_READ(LVDS) & LVDS_PORT_EN) != 0) { | |
604 | /* | |
605 | * For LVDS, if the panel is on, just rely on its current | |
606 | * settings for dual-channel. We haven't figured out how to | |
607 | * reliably set up different single/dual channel state, if we | |
608 | * even can. | |
609 | */ | |
610 | if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == | |
611 | LVDS_CLKB_POWER_UP) | |
612 | clock.p2 = limit->p2.p2_fast; | |
613 | else | |
614 | clock.p2 = limit->p2.p2_slow; | |
615 | } else { | |
616 | if (target < limit->p2.dot_limit) | |
617 | clock.p2 = limit->p2.p2_slow; | |
618 | else | |
619 | clock.p2 = limit->p2.p2_fast; | |
620 | } | |
621 | ||
622 | memset (best_clock, 0, sizeof (*best_clock)); | |
623 | ||
624 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { | |
2177832f SL |
625 | for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) { |
626 | /* m1 is always 0 in IGD */ | |
627 | if (clock.m2 >= clock.m1 && !IS_IGD(dev)) | |
628 | break; | |
79e53945 JB |
629 | for (clock.n = limit->n.min; clock.n <= limit->n.max; |
630 | clock.n++) { | |
631 | for (clock.p1 = limit->p1.min; | |
632 | clock.p1 <= limit->p1.max; clock.p1++) { | |
633 | int this_err; | |
634 | ||
2177832f | 635 | intel_clock(dev, refclk, &clock); |
79e53945 JB |
636 | |
637 | if (!intel_PLL_is_valid(crtc, &clock)) | |
638 | continue; | |
639 | ||
640 | this_err = abs(clock.dot - target); | |
641 | if (this_err < err) { | |
642 | *best_clock = clock; | |
643 | err = this_err; | |
644 | } | |
645 | } | |
646 | } | |
647 | } | |
648 | } | |
649 | ||
650 | return (err != target); | |
651 | } | |
652 | ||
d4906093 ML |
653 | static bool |
654 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
655 | int target, int refclk, intel_clock_t *best_clock) | |
656 | { | |
657 | struct drm_device *dev = crtc->dev; | |
658 | struct drm_i915_private *dev_priv = dev->dev_private; | |
659 | intel_clock_t clock; | |
660 | int max_n; | |
661 | bool found; | |
662 | /* approximately equals target * 0.00488 */ | |
663 | int err_most = (target >> 8) + (target >> 10); | |
664 | found = false; | |
665 | ||
666 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
667 | if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == | |
668 | LVDS_CLKB_POWER_UP) | |
669 | clock.p2 = limit->p2.p2_fast; | |
670 | else | |
671 | clock.p2 = limit->p2.p2_slow; | |
672 | } else { | |
673 | if (target < limit->p2.dot_limit) | |
674 | clock.p2 = limit->p2.p2_slow; | |
675 | else | |
676 | clock.p2 = limit->p2.p2_fast; | |
677 | } | |
678 | ||
679 | memset(best_clock, 0, sizeof(*best_clock)); | |
680 | max_n = limit->n.max; | |
681 | /* based on hardware requriment prefer smaller n to precision */ | |
682 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { | |
683 | /* based on hardware requirment prefere larger m1,m2, p1 */ | |
684 | for (clock.m1 = limit->m1.max; | |
685 | clock.m1 >= limit->m1.min; clock.m1--) { | |
686 | for (clock.m2 = limit->m2.max; | |
687 | clock.m2 >= limit->m2.min; clock.m2--) { | |
688 | for (clock.p1 = limit->p1.max; | |
689 | clock.p1 >= limit->p1.min; clock.p1--) { | |
690 | int this_err; | |
691 | ||
2177832f | 692 | intel_clock(dev, refclk, &clock); |
d4906093 ML |
693 | if (!intel_PLL_is_valid(crtc, &clock)) |
694 | continue; | |
695 | this_err = abs(clock.dot - target) ; | |
696 | if (this_err < err_most) { | |
697 | *best_clock = clock; | |
698 | err_most = this_err; | |
699 | max_n = clock.n; | |
700 | found = true; | |
701 | } | |
702 | } | |
703 | } | |
704 | } | |
705 | } | |
2c07245f ZW |
706 | return found; |
707 | } | |
708 | ||
709 | static bool | |
710 | intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
711 | int target, int refclk, intel_clock_t *best_clock) | |
712 | { | |
713 | struct drm_device *dev = crtc->dev; | |
714 | struct drm_i915_private *dev_priv = dev->dev_private; | |
715 | intel_clock_t clock; | |
716 | int max_n; | |
717 | bool found; | |
718 | int err_most = 47; | |
719 | found = false; | |
720 | ||
721 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
722 | if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == | |
723 | LVDS_CLKB_POWER_UP) | |
724 | clock.p2 = limit->p2.p2_fast; | |
725 | else | |
726 | clock.p2 = limit->p2.p2_slow; | |
727 | } else { | |
728 | if (target < limit->p2.dot_limit) | |
729 | clock.p2 = limit->p2.p2_slow; | |
730 | else | |
731 | clock.p2 = limit->p2.p2_fast; | |
732 | } | |
733 | ||
734 | memset(best_clock, 0, sizeof(*best_clock)); | |
735 | max_n = limit->n.max; | |
736 | /* based on hardware requriment prefer smaller n to precision */ | |
737 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { | |
738 | /* based on hardware requirment prefere larger m1,m2, p1 */ | |
739 | for (clock.m1 = limit->m1.max; | |
740 | clock.m1 >= limit->m1.min; clock.m1--) { | |
741 | for (clock.m2 = limit->m2.max; | |
742 | clock.m2 >= limit->m2.min; clock.m2--) { | |
743 | for (clock.p1 = limit->p1.max; | |
744 | clock.p1 >= limit->p1.min; clock.p1--) { | |
745 | int this_err; | |
d4906093 | 746 | |
2c07245f ZW |
747 | intel_clock(dev, refclk, &clock); |
748 | if (!intel_PLL_is_valid(crtc, &clock)) | |
749 | continue; | |
750 | this_err = abs((10000 - (target*10000/clock.dot))); | |
751 | if (this_err < err_most) { | |
752 | *best_clock = clock; | |
753 | err_most = this_err; | |
754 | max_n = clock.n; | |
755 | found = true; | |
756 | /* found on first matching */ | |
757 | goto out; | |
758 | } | |
759 | } | |
760 | } | |
761 | } | |
762 | } | |
763 | out: | |
d4906093 ML |
764 | return found; |
765 | } | |
766 | ||
79e53945 JB |
767 | void |
768 | intel_wait_for_vblank(struct drm_device *dev) | |
769 | { | |
770 | /* Wait for 20ms, i.e. one cycle at 50hz. */ | |
580982d3 | 771 | mdelay(20); |
79e53945 JB |
772 | } |
773 | ||
5c3b82e2 | 774 | static int |
3c4fdcfb KH |
775 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
776 | struct drm_framebuffer *old_fb) | |
79e53945 JB |
777 | { |
778 | struct drm_device *dev = crtc->dev; | |
779 | struct drm_i915_private *dev_priv = dev->dev_private; | |
780 | struct drm_i915_master_private *master_priv; | |
781 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
782 | struct intel_framebuffer *intel_fb; | |
783 | struct drm_i915_gem_object *obj_priv; | |
784 | struct drm_gem_object *obj; | |
785 | int pipe = intel_crtc->pipe; | |
786 | unsigned long Start, Offset; | |
787 | int dspbase = (pipe == 0 ? DSPAADDR : DSPBADDR); | |
788 | int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF); | |
789 | int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE; | |
f544847f | 790 | int dsptileoff = (pipe == 0 ? DSPATILEOFF : DSPBTILEOFF); |
79e53945 | 791 | int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR; |
3c4fdcfb | 792 | u32 dspcntr, alignment; |
5c3b82e2 | 793 | int ret; |
79e53945 JB |
794 | |
795 | /* no fb bound */ | |
796 | if (!crtc->fb) { | |
797 | DRM_DEBUG("No FB bound\n"); | |
5c3b82e2 CW |
798 | return 0; |
799 | } | |
800 | ||
801 | switch (pipe) { | |
802 | case 0: | |
803 | case 1: | |
804 | break; | |
805 | default: | |
806 | DRM_ERROR("Can't update pipe %d in SAREA\n", pipe); | |
807 | return -EINVAL; | |
79e53945 JB |
808 | } |
809 | ||
810 | intel_fb = to_intel_framebuffer(crtc->fb); | |
79e53945 JB |
811 | obj = intel_fb->obj; |
812 | obj_priv = obj->driver_private; | |
813 | ||
3c4fdcfb KH |
814 | switch (obj_priv->tiling_mode) { |
815 | case I915_TILING_NONE: | |
816 | alignment = 64 * 1024; | |
817 | break; | |
818 | case I915_TILING_X: | |
2ebed176 CW |
819 | /* pin() will align the object as required by fence */ |
820 | alignment = 0; | |
3c4fdcfb KH |
821 | break; |
822 | case I915_TILING_Y: | |
823 | /* FIXME: Is this true? */ | |
824 | DRM_ERROR("Y tiled not allowed for scan out buffers\n"); | |
5c3b82e2 | 825 | return -EINVAL; |
3c4fdcfb KH |
826 | default: |
827 | BUG(); | |
828 | } | |
829 | ||
5c3b82e2 CW |
830 | mutex_lock(&dev->struct_mutex); |
831 | ret = i915_gem_object_pin(intel_fb->obj, alignment); | |
832 | if (ret != 0) { | |
833 | mutex_unlock(&dev->struct_mutex); | |
834 | return ret; | |
835 | } | |
79e53945 | 836 | |
5c3b82e2 CW |
837 | ret = i915_gem_object_set_to_gtt_domain(intel_fb->obj, 1); |
838 | if (ret != 0) { | |
839 | i915_gem_object_unpin(intel_fb->obj); | |
840 | mutex_unlock(&dev->struct_mutex); | |
841 | return ret; | |
842 | } | |
79e53945 JB |
843 | |
844 | dspcntr = I915_READ(dspcntr_reg); | |
712531bf JB |
845 | /* Mask out pixel format bits in case we change it */ |
846 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
79e53945 JB |
847 | switch (crtc->fb->bits_per_pixel) { |
848 | case 8: | |
849 | dspcntr |= DISPPLANE_8BPP; | |
850 | break; | |
851 | case 16: | |
852 | if (crtc->fb->depth == 15) | |
853 | dspcntr |= DISPPLANE_15_16BPP; | |
854 | else | |
855 | dspcntr |= DISPPLANE_16BPP; | |
856 | break; | |
857 | case 24: | |
858 | case 32: | |
859 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; | |
860 | break; | |
861 | default: | |
862 | DRM_ERROR("Unknown color depth\n"); | |
5c3b82e2 CW |
863 | i915_gem_object_unpin(intel_fb->obj); |
864 | mutex_unlock(&dev->struct_mutex); | |
865 | return -EINVAL; | |
79e53945 | 866 | } |
f544847f JB |
867 | if (IS_I965G(dev)) { |
868 | if (obj_priv->tiling_mode != I915_TILING_NONE) | |
869 | dspcntr |= DISPPLANE_TILED; | |
870 | else | |
871 | dspcntr &= ~DISPPLANE_TILED; | |
872 | } | |
873 | ||
79e53945 JB |
874 | I915_WRITE(dspcntr_reg, dspcntr); |
875 | ||
5c3b82e2 CW |
876 | Start = obj_priv->gtt_offset; |
877 | Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8); | |
878 | ||
79e53945 | 879 | DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y); |
5c3b82e2 | 880 | I915_WRITE(dspstride, crtc->fb->pitch); |
79e53945 JB |
881 | if (IS_I965G(dev)) { |
882 | I915_WRITE(dspbase, Offset); | |
883 | I915_READ(dspbase); | |
884 | I915_WRITE(dspsurf, Start); | |
885 | I915_READ(dspsurf); | |
f544847f | 886 | I915_WRITE(dsptileoff, (y << 16) | x); |
79e53945 JB |
887 | } else { |
888 | I915_WRITE(dspbase, Start + Offset); | |
889 | I915_READ(dspbase); | |
890 | } | |
891 | ||
3c4fdcfb KH |
892 | intel_wait_for_vblank(dev); |
893 | ||
894 | if (old_fb) { | |
895 | intel_fb = to_intel_framebuffer(old_fb); | |
896 | i915_gem_object_unpin(intel_fb->obj); | |
897 | } | |
5c3b82e2 | 898 | mutex_unlock(&dev->struct_mutex); |
79e53945 JB |
899 | |
900 | if (!dev->primary->master) | |
5c3b82e2 | 901 | return 0; |
79e53945 JB |
902 | |
903 | master_priv = dev->primary->master->driver_priv; | |
904 | if (!master_priv->sarea_priv) | |
5c3b82e2 | 905 | return 0; |
79e53945 | 906 | |
5c3b82e2 | 907 | if (pipe) { |
79e53945 JB |
908 | master_priv->sarea_priv->pipeB_x = x; |
909 | master_priv->sarea_priv->pipeB_y = y; | |
5c3b82e2 CW |
910 | } else { |
911 | master_priv->sarea_priv->pipeA_x = x; | |
912 | master_priv->sarea_priv->pipeA_y = y; | |
79e53945 | 913 | } |
5c3b82e2 CW |
914 | |
915 | return 0; | |
79e53945 JB |
916 | } |
917 | ||
2c07245f ZW |
918 | static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode) |
919 | { | |
920 | struct drm_device *dev = crtc->dev; | |
921 | struct drm_i915_private *dev_priv = dev->dev_private; | |
922 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
923 | int pipe = intel_crtc->pipe; | |
924 | int plane = intel_crtc->pipe; | |
925 | int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B; | |
926 | int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; | |
927 | int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR; | |
928 | int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR; | |
929 | int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL; | |
930 | int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL; | |
931 | int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR; | |
932 | int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR; | |
933 | int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF; | |
934 | int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1; | |
935 | int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B; | |
936 | int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B; | |
937 | int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B; | |
938 | int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B; | |
939 | int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B; | |
940 | int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B; | |
941 | int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B; | |
942 | int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B; | |
943 | int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B; | |
944 | int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B; | |
945 | int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B; | |
946 | int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B; | |
947 | u32 temp; | |
948 | int tries = 5, j; | |
79e53945 | 949 | |
2c07245f ZW |
950 | /* XXX: When our outputs are all unaware of DPMS modes other than off |
951 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. | |
952 | */ | |
953 | switch (mode) { | |
954 | case DRM_MODE_DPMS_ON: | |
955 | case DRM_MODE_DPMS_STANDBY: | |
956 | case DRM_MODE_DPMS_SUSPEND: | |
957 | DRM_DEBUG("crtc %d dpms on\n", pipe); | |
958 | /* enable PCH DPLL */ | |
959 | temp = I915_READ(pch_dpll_reg); | |
960 | if ((temp & DPLL_VCO_ENABLE) == 0) { | |
961 | I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE); | |
962 | I915_READ(pch_dpll_reg); | |
963 | } | |
79e53945 | 964 | |
2c07245f ZW |
965 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
966 | temp = I915_READ(fdi_rx_reg); | |
967 | I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE | | |
968 | FDI_SEL_PCDCLK | | |
969 | FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */ | |
970 | I915_READ(fdi_rx_reg); | |
971 | udelay(200); | |
972 | ||
973 | /* Enable CPU FDI TX PLL, always on for IGDNG */ | |
974 | temp = I915_READ(fdi_tx_reg); | |
975 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
976 | I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE); | |
977 | I915_READ(fdi_tx_reg); | |
978 | udelay(100); | |
979 | } | |
980 | ||
981 | /* Enable CPU pipe */ | |
982 | temp = I915_READ(pipeconf_reg); | |
983 | if ((temp & PIPEACONF_ENABLE) == 0) { | |
984 | I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE); | |
985 | I915_READ(pipeconf_reg); | |
986 | udelay(100); | |
987 | } | |
988 | ||
989 | /* configure and enable CPU plane */ | |
990 | temp = I915_READ(dspcntr_reg); | |
991 | if ((temp & DISPLAY_PLANE_ENABLE) == 0) { | |
992 | I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE); | |
993 | /* Flush the plane changes */ | |
994 | I915_WRITE(dspbase_reg, I915_READ(dspbase_reg)); | |
995 | } | |
996 | ||
997 | /* enable CPU FDI TX and PCH FDI RX */ | |
998 | temp = I915_READ(fdi_tx_reg); | |
999 | temp |= FDI_TX_ENABLE; | |
1000 | temp |= FDI_DP_PORT_WIDTH_X4; /* default */ | |
1001 | temp &= ~FDI_LINK_TRAIN_NONE; | |
1002 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
1003 | I915_WRITE(fdi_tx_reg, temp); | |
1004 | I915_READ(fdi_tx_reg); | |
1005 | ||
1006 | temp = I915_READ(fdi_rx_reg); | |
1007 | temp &= ~FDI_LINK_TRAIN_NONE; | |
1008 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
1009 | I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE); | |
1010 | I915_READ(fdi_rx_reg); | |
1011 | ||
1012 | udelay(150); | |
1013 | ||
1014 | /* Train FDI. */ | |
1015 | /* umask FDI RX Interrupt symbol_lock and bit_lock bit | |
1016 | for train result */ | |
1017 | temp = I915_READ(fdi_rx_imr_reg); | |
1018 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
1019 | temp &= ~FDI_RX_BIT_LOCK; | |
1020 | I915_WRITE(fdi_rx_imr_reg, temp); | |
1021 | I915_READ(fdi_rx_imr_reg); | |
1022 | udelay(150); | |
1023 | ||
1024 | temp = I915_READ(fdi_rx_iir_reg); | |
1025 | DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp); | |
1026 | ||
1027 | if ((temp & FDI_RX_BIT_LOCK) == 0) { | |
1028 | for (j = 0; j < tries; j++) { | |
1029 | temp = I915_READ(fdi_rx_iir_reg); | |
1030 | DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp); | |
1031 | if (temp & FDI_RX_BIT_LOCK) | |
1032 | break; | |
1033 | udelay(200); | |
1034 | } | |
1035 | if (j != tries) | |
1036 | I915_WRITE(fdi_rx_iir_reg, | |
1037 | temp | FDI_RX_BIT_LOCK); | |
1038 | else | |
1039 | DRM_DEBUG("train 1 fail\n"); | |
1040 | } else { | |
1041 | I915_WRITE(fdi_rx_iir_reg, | |
1042 | temp | FDI_RX_BIT_LOCK); | |
1043 | DRM_DEBUG("train 1 ok 2!\n"); | |
1044 | } | |
1045 | temp = I915_READ(fdi_tx_reg); | |
1046 | temp &= ~FDI_LINK_TRAIN_NONE; | |
1047 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
1048 | I915_WRITE(fdi_tx_reg, temp); | |
1049 | ||
1050 | temp = I915_READ(fdi_rx_reg); | |
1051 | temp &= ~FDI_LINK_TRAIN_NONE; | |
1052 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
1053 | I915_WRITE(fdi_rx_reg, temp); | |
1054 | ||
1055 | udelay(150); | |
1056 | ||
1057 | temp = I915_READ(fdi_rx_iir_reg); | |
1058 | DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp); | |
1059 | ||
1060 | if ((temp & FDI_RX_SYMBOL_LOCK) == 0) { | |
1061 | for (j = 0; j < tries; j++) { | |
1062 | temp = I915_READ(fdi_rx_iir_reg); | |
1063 | DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp); | |
1064 | if (temp & FDI_RX_SYMBOL_LOCK) | |
1065 | break; | |
1066 | udelay(200); | |
1067 | } | |
1068 | if (j != tries) { | |
1069 | I915_WRITE(fdi_rx_iir_reg, | |
1070 | temp | FDI_RX_SYMBOL_LOCK); | |
1071 | DRM_DEBUG("train 2 ok 1!\n"); | |
1072 | } else | |
1073 | DRM_DEBUG("train 2 fail\n"); | |
1074 | } else { | |
1075 | I915_WRITE(fdi_rx_iir_reg, temp | FDI_RX_SYMBOL_LOCK); | |
1076 | DRM_DEBUG("train 2 ok 2!\n"); | |
1077 | } | |
1078 | DRM_DEBUG("train done\n"); | |
1079 | ||
1080 | /* set transcoder timing */ | |
1081 | I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg)); | |
1082 | I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg)); | |
1083 | I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg)); | |
1084 | ||
1085 | I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg)); | |
1086 | I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg)); | |
1087 | I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg)); | |
1088 | ||
1089 | /* enable PCH transcoder */ | |
1090 | temp = I915_READ(transconf_reg); | |
1091 | I915_WRITE(transconf_reg, temp | TRANS_ENABLE); | |
1092 | I915_READ(transconf_reg); | |
1093 | ||
1094 | while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0) | |
1095 | ; | |
1096 | ||
1097 | /* enable normal */ | |
1098 | ||
1099 | temp = I915_READ(fdi_tx_reg); | |
1100 | temp &= ~FDI_LINK_TRAIN_NONE; | |
1101 | I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE | | |
1102 | FDI_TX_ENHANCE_FRAME_ENABLE); | |
1103 | I915_READ(fdi_tx_reg); | |
1104 | ||
1105 | temp = I915_READ(fdi_rx_reg); | |
1106 | temp &= ~FDI_LINK_TRAIN_NONE; | |
1107 | I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE | | |
1108 | FDI_RX_ENHANCE_FRAME_ENABLE); | |
1109 | I915_READ(fdi_rx_reg); | |
1110 | ||
1111 | /* wait one idle pattern time */ | |
1112 | udelay(100); | |
1113 | ||
1114 | intel_crtc_load_lut(crtc); | |
1115 | ||
1116 | break; | |
1117 | case DRM_MODE_DPMS_OFF: | |
1118 | DRM_DEBUG("crtc %d dpms off\n", pipe); | |
1119 | ||
1120 | /* Disable the VGA plane that we never use */ | |
1121 | I915_WRITE(CPU_VGACNTRL, VGA_DISP_DISABLE); | |
1122 | ||
1123 | /* Disable display plane */ | |
1124 | temp = I915_READ(dspcntr_reg); | |
1125 | if ((temp & DISPLAY_PLANE_ENABLE) != 0) { | |
1126 | I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE); | |
1127 | /* Flush the plane changes */ | |
1128 | I915_WRITE(dspbase_reg, I915_READ(dspbase_reg)); | |
1129 | I915_READ(dspbase_reg); | |
1130 | } | |
1131 | ||
1132 | /* disable cpu pipe, disable after all planes disabled */ | |
1133 | temp = I915_READ(pipeconf_reg); | |
1134 | if ((temp & PIPEACONF_ENABLE) != 0) { | |
1135 | I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE); | |
1136 | I915_READ(pipeconf_reg); | |
1137 | /* wait for cpu pipe off, pipe state */ | |
1138 | while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) | |
1139 | ; | |
1140 | } else | |
1141 | DRM_DEBUG("crtc %d is disabled\n", pipe); | |
1142 | ||
1143 | /* IGDNG-A : disable cpu panel fitter ? */ | |
1144 | temp = I915_READ(pf_ctl_reg); | |
1145 | if ((temp & PF_ENABLE) != 0) { | |
1146 | I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE); | |
1147 | I915_READ(pf_ctl_reg); | |
1148 | } | |
1149 | ||
1150 | /* disable CPU FDI tx and PCH FDI rx */ | |
1151 | temp = I915_READ(fdi_tx_reg); | |
1152 | I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE); | |
1153 | I915_READ(fdi_tx_reg); | |
1154 | ||
1155 | temp = I915_READ(fdi_rx_reg); | |
1156 | I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE); | |
1157 | I915_READ(fdi_rx_reg); | |
1158 | ||
1159 | /* still set train pattern 1 */ | |
1160 | temp = I915_READ(fdi_tx_reg); | |
1161 | temp &= ~FDI_LINK_TRAIN_NONE; | |
1162 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
1163 | I915_WRITE(fdi_tx_reg, temp); | |
1164 | ||
1165 | temp = I915_READ(fdi_rx_reg); | |
1166 | temp &= ~FDI_LINK_TRAIN_NONE; | |
1167 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
1168 | I915_WRITE(fdi_rx_reg, temp); | |
1169 | ||
1170 | /* disable PCH transcoder */ | |
1171 | temp = I915_READ(transconf_reg); | |
1172 | if ((temp & TRANS_ENABLE) != 0) { | |
1173 | I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE); | |
1174 | I915_READ(transconf_reg); | |
1175 | /* wait for PCH transcoder off, transcoder state */ | |
1176 | while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) | |
1177 | ; | |
1178 | } | |
1179 | ||
1180 | /* disable PCH DPLL */ | |
1181 | temp = I915_READ(pch_dpll_reg); | |
1182 | if ((temp & DPLL_VCO_ENABLE) != 0) { | |
1183 | I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE); | |
1184 | I915_READ(pch_dpll_reg); | |
1185 | } | |
1186 | ||
1187 | temp = I915_READ(fdi_rx_reg); | |
1188 | if ((temp & FDI_RX_PLL_ENABLE) != 0) { | |
1189 | temp &= ~FDI_SEL_PCDCLK; | |
1190 | temp &= ~FDI_RX_PLL_ENABLE; | |
1191 | I915_WRITE(fdi_rx_reg, temp); | |
1192 | I915_READ(fdi_rx_reg); | |
1193 | } | |
1194 | ||
1195 | /* Wait for the clocks to turn off. */ | |
1196 | udelay(150); | |
1197 | break; | |
1198 | } | |
1199 | } | |
1200 | ||
1201 | static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode) | |
79e53945 JB |
1202 | { |
1203 | struct drm_device *dev = crtc->dev; | |
79e53945 JB |
1204 | struct drm_i915_private *dev_priv = dev->dev_private; |
1205 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1206 | int pipe = intel_crtc->pipe; | |
1207 | int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; | |
1208 | int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR; | |
1209 | int dspbase_reg = (pipe == 0) ? DSPAADDR : DSPBADDR; | |
1210 | int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; | |
1211 | u32 temp; | |
79e53945 JB |
1212 | |
1213 | /* XXX: When our outputs are all unaware of DPMS modes other than off | |
1214 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. | |
1215 | */ | |
1216 | switch (mode) { | |
1217 | case DRM_MODE_DPMS_ON: | |
1218 | case DRM_MODE_DPMS_STANDBY: | |
1219 | case DRM_MODE_DPMS_SUSPEND: | |
1220 | /* Enable the DPLL */ | |
1221 | temp = I915_READ(dpll_reg); | |
1222 | if ((temp & DPLL_VCO_ENABLE) == 0) { | |
1223 | I915_WRITE(dpll_reg, temp); | |
1224 | I915_READ(dpll_reg); | |
1225 | /* Wait for the clocks to stabilize. */ | |
1226 | udelay(150); | |
1227 | I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE); | |
1228 | I915_READ(dpll_reg); | |
1229 | /* Wait for the clocks to stabilize. */ | |
1230 | udelay(150); | |
1231 | I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE); | |
1232 | I915_READ(dpll_reg); | |
1233 | /* Wait for the clocks to stabilize. */ | |
1234 | udelay(150); | |
1235 | } | |
1236 | ||
1237 | /* Enable the pipe */ | |
1238 | temp = I915_READ(pipeconf_reg); | |
1239 | if ((temp & PIPEACONF_ENABLE) == 0) | |
1240 | I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE); | |
1241 | ||
1242 | /* Enable the plane */ | |
1243 | temp = I915_READ(dspcntr_reg); | |
1244 | if ((temp & DISPLAY_PLANE_ENABLE) == 0) { | |
1245 | I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE); | |
1246 | /* Flush the plane changes */ | |
1247 | I915_WRITE(dspbase_reg, I915_READ(dspbase_reg)); | |
1248 | } | |
1249 | ||
1250 | intel_crtc_load_lut(crtc); | |
1251 | ||
1252 | /* Give the overlay scaler a chance to enable if it's on this pipe */ | |
1253 | //intel_crtc_dpms_video(crtc, true); TODO | |
1254 | break; | |
1255 | case DRM_MODE_DPMS_OFF: | |
1256 | /* Give the overlay scaler a chance to disable if it's on this pipe */ | |
1257 | //intel_crtc_dpms_video(crtc, FALSE); TODO | |
1258 | ||
1259 | /* Disable the VGA plane that we never use */ | |
1260 | I915_WRITE(VGACNTRL, VGA_DISP_DISABLE); | |
1261 | ||
1262 | /* Disable display plane */ | |
1263 | temp = I915_READ(dspcntr_reg); | |
1264 | if ((temp & DISPLAY_PLANE_ENABLE) != 0) { | |
1265 | I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE); | |
1266 | /* Flush the plane changes */ | |
1267 | I915_WRITE(dspbase_reg, I915_READ(dspbase_reg)); | |
1268 | I915_READ(dspbase_reg); | |
1269 | } | |
1270 | ||
1271 | if (!IS_I9XX(dev)) { | |
1272 | /* Wait for vblank for the disable to take effect */ | |
1273 | intel_wait_for_vblank(dev); | |
1274 | } | |
1275 | ||
1276 | /* Next, disable display pipes */ | |
1277 | temp = I915_READ(pipeconf_reg); | |
1278 | if ((temp & PIPEACONF_ENABLE) != 0) { | |
1279 | I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE); | |
1280 | I915_READ(pipeconf_reg); | |
1281 | } | |
1282 | ||
1283 | /* Wait for vblank for the disable to take effect. */ | |
1284 | intel_wait_for_vblank(dev); | |
1285 | ||
1286 | temp = I915_READ(dpll_reg); | |
1287 | if ((temp & DPLL_VCO_ENABLE) != 0) { | |
1288 | I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE); | |
1289 | I915_READ(dpll_reg); | |
1290 | } | |
1291 | ||
1292 | /* Wait for the clocks to turn off. */ | |
1293 | udelay(150); | |
1294 | break; | |
1295 | } | |
2c07245f ZW |
1296 | } |
1297 | ||
1298 | /** | |
1299 | * Sets the power management mode of the pipe and plane. | |
1300 | * | |
1301 | * This code should probably grow support for turning the cursor off and back | |
1302 | * on appropriately at the same time as we're turning the pipe off/on. | |
1303 | */ | |
1304 | static void intel_crtc_dpms(struct drm_crtc *crtc, int mode) | |
1305 | { | |
1306 | struct drm_device *dev = crtc->dev; | |
1307 | struct drm_i915_master_private *master_priv; | |
1308 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1309 | int pipe = intel_crtc->pipe; | |
1310 | bool enabled; | |
1311 | ||
1312 | if (IS_IGDNG(dev)) | |
1313 | igdng_crtc_dpms(crtc, mode); | |
1314 | else | |
1315 | i9xx_crtc_dpms(crtc, mode); | |
79e53945 JB |
1316 | |
1317 | if (!dev->primary->master) | |
1318 | return; | |
1319 | ||
1320 | master_priv = dev->primary->master->driver_priv; | |
1321 | if (!master_priv->sarea_priv) | |
1322 | return; | |
1323 | ||
1324 | enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF; | |
1325 | ||
1326 | switch (pipe) { | |
1327 | case 0: | |
1328 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; | |
1329 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; | |
1330 | break; | |
1331 | case 1: | |
1332 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; | |
1333 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; | |
1334 | break; | |
1335 | default: | |
1336 | DRM_ERROR("Can't update pipe %d in SAREA\n", pipe); | |
1337 | break; | |
1338 | } | |
1339 | ||
1340 | intel_crtc->dpms_mode = mode; | |
1341 | } | |
1342 | ||
1343 | static void intel_crtc_prepare (struct drm_crtc *crtc) | |
1344 | { | |
1345 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
1346 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); | |
1347 | } | |
1348 | ||
1349 | static void intel_crtc_commit (struct drm_crtc *crtc) | |
1350 | { | |
1351 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
1352 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); | |
1353 | } | |
1354 | ||
1355 | void intel_encoder_prepare (struct drm_encoder *encoder) | |
1356 | { | |
1357 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
1358 | /* lvds has its own version of prepare see intel_lvds_prepare */ | |
1359 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); | |
1360 | } | |
1361 | ||
1362 | void intel_encoder_commit (struct drm_encoder *encoder) | |
1363 | { | |
1364 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
1365 | /* lvds has its own version of commit see intel_lvds_commit */ | |
1366 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); | |
1367 | } | |
1368 | ||
1369 | static bool intel_crtc_mode_fixup(struct drm_crtc *crtc, | |
1370 | struct drm_display_mode *mode, | |
1371 | struct drm_display_mode *adjusted_mode) | |
1372 | { | |
2c07245f ZW |
1373 | struct drm_device *dev = crtc->dev; |
1374 | if (IS_IGDNG(dev)) { | |
1375 | /* FDI link clock is fixed at 2.7G */ | |
1376 | if (mode->clock * 3 > 27000 * 4) | |
1377 | return MODE_CLOCK_HIGH; | |
1378 | } | |
79e53945 JB |
1379 | return true; |
1380 | } | |
1381 | ||
1382 | ||
1383 | /** Returns the core display clock speed for i830 - i945 */ | |
1384 | static int intel_get_core_clock_speed(struct drm_device *dev) | |
1385 | { | |
1386 | ||
1387 | /* Core clock values taken from the published datasheets. | |
1388 | * The 830 may go up to 166 Mhz, which we should check. | |
1389 | */ | |
1390 | if (IS_I945G(dev)) | |
1391 | return 400000; | |
1392 | else if (IS_I915G(dev)) | |
1393 | return 333000; | |
2177832f | 1394 | else if (IS_I945GM(dev) || IS_845G(dev) || IS_IGDGM(dev)) |
79e53945 JB |
1395 | return 200000; |
1396 | else if (IS_I915GM(dev)) { | |
1397 | u16 gcfgc = 0; | |
1398 | ||
1399 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
1400 | ||
1401 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
1402 | return 133000; | |
1403 | else { | |
1404 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
1405 | case GC_DISPLAY_CLOCK_333_MHZ: | |
1406 | return 333000; | |
1407 | default: | |
1408 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
1409 | return 190000; | |
1410 | } | |
1411 | } | |
1412 | } else if (IS_I865G(dev)) | |
1413 | return 266000; | |
1414 | else if (IS_I855(dev)) { | |
1415 | u16 hpllcc = 0; | |
1416 | /* Assume that the hardware is in the high speed state. This | |
1417 | * should be the default. | |
1418 | */ | |
1419 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
1420 | case GC_CLOCK_133_200: | |
1421 | case GC_CLOCK_100_200: | |
1422 | return 200000; | |
1423 | case GC_CLOCK_166_250: | |
1424 | return 250000; | |
1425 | case GC_CLOCK_100_133: | |
1426 | return 133000; | |
1427 | } | |
1428 | } else /* 852, 830 */ | |
1429 | return 133000; | |
1430 | ||
1431 | return 0; /* Silence gcc warning */ | |
1432 | } | |
1433 | ||
1434 | ||
1435 | /** | |
1436 | * Return the pipe currently connected to the panel fitter, | |
1437 | * or -1 if the panel fitter is not present or not in use | |
1438 | */ | |
1439 | static int intel_panel_fitter_pipe (struct drm_device *dev) | |
1440 | { | |
1441 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1442 | u32 pfit_control; | |
1443 | ||
1444 | /* i830 doesn't have a panel fitter */ | |
1445 | if (IS_I830(dev)) | |
1446 | return -1; | |
1447 | ||
1448 | pfit_control = I915_READ(PFIT_CONTROL); | |
1449 | ||
1450 | /* See if the panel fitter is in use */ | |
1451 | if ((pfit_control & PFIT_ENABLE) == 0) | |
1452 | return -1; | |
1453 | ||
1454 | /* 965 can place panel fitter on either pipe */ | |
1455 | if (IS_I965G(dev)) | |
1456 | return (pfit_control >> 29) & 0x3; | |
1457 | ||
1458 | /* older chips can only use pipe 1 */ | |
1459 | return 1; | |
1460 | } | |
1461 | ||
2c07245f ZW |
1462 | struct fdi_m_n { |
1463 | u32 tu; | |
1464 | u32 gmch_m; | |
1465 | u32 gmch_n; | |
1466 | u32 link_m; | |
1467 | u32 link_n; | |
1468 | }; | |
1469 | ||
1470 | static void | |
1471 | fdi_reduce_ratio(u32 *num, u32 *den) | |
1472 | { | |
1473 | while (*num > 0xffffff || *den > 0xffffff) { | |
1474 | *num >>= 1; | |
1475 | *den >>= 1; | |
1476 | } | |
1477 | } | |
1478 | ||
1479 | #define DATA_N 0x800000 | |
1480 | #define LINK_N 0x80000 | |
1481 | ||
1482 | static void | |
1483 | igdng_compute_m_n(int bytes_per_pixel, int nlanes, | |
1484 | int pixel_clock, int link_clock, | |
1485 | struct fdi_m_n *m_n) | |
1486 | { | |
1487 | u64 temp; | |
1488 | ||
1489 | m_n->tu = 64; /* default size */ | |
1490 | ||
1491 | temp = (u64) DATA_N * pixel_clock; | |
1492 | temp = div_u64(temp, link_clock); | |
1493 | m_n->gmch_m = (temp * bytes_per_pixel) / nlanes; | |
1494 | m_n->gmch_n = DATA_N; | |
1495 | fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); | |
1496 | ||
1497 | temp = (u64) LINK_N * pixel_clock; | |
1498 | m_n->link_m = div_u64(temp, link_clock); | |
1499 | m_n->link_n = LINK_N; | |
1500 | fdi_reduce_ratio(&m_n->link_m, &m_n->link_n); | |
1501 | } | |
1502 | ||
1503 | ||
5c3b82e2 CW |
1504 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
1505 | struct drm_display_mode *mode, | |
1506 | struct drm_display_mode *adjusted_mode, | |
1507 | int x, int y, | |
1508 | struct drm_framebuffer *old_fb) | |
79e53945 JB |
1509 | { |
1510 | struct drm_device *dev = crtc->dev; | |
1511 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1512 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1513 | int pipe = intel_crtc->pipe; | |
1514 | int fp_reg = (pipe == 0) ? FPA0 : FPB0; | |
1515 | int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; | |
1516 | int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD; | |
1517 | int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR; | |
1518 | int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; | |
1519 | int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B; | |
1520 | int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B; | |
1521 | int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B; | |
1522 | int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B; | |
1523 | int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B; | |
1524 | int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B; | |
1525 | int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE; | |
1526 | int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS; | |
1527 | int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC; | |
43565a06 | 1528 | int refclk, num_outputs = 0; |
79e53945 JB |
1529 | intel_clock_t clock; |
1530 | u32 dpll = 0, fp = 0, dspcntr, pipeconf; | |
1531 | bool ok, is_sdvo = false, is_dvo = false; | |
1532 | bool is_crt = false, is_lvds = false, is_tv = false; | |
1533 | struct drm_mode_config *mode_config = &dev->mode_config; | |
1534 | struct drm_connector *connector; | |
d4906093 | 1535 | const intel_limit_t *limit; |
5c3b82e2 | 1536 | int ret; |
2c07245f ZW |
1537 | struct fdi_m_n m_n = {0}; |
1538 | int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1; | |
1539 | int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1; | |
1540 | int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1; | |
1541 | int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1; | |
1542 | int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0; | |
1543 | int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B; | |
1544 | int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL; | |
1545 | u32 temp; | |
1546 | int sdvo_pixel_multiply; | |
79e53945 JB |
1547 | |
1548 | drm_vblank_pre_modeset(dev, pipe); | |
1549 | ||
1550 | list_for_each_entry(connector, &mode_config->connector_list, head) { | |
1551 | struct intel_output *intel_output = to_intel_output(connector); | |
1552 | ||
1553 | if (!connector->encoder || connector->encoder->crtc != crtc) | |
1554 | continue; | |
1555 | ||
1556 | switch (intel_output->type) { | |
1557 | case INTEL_OUTPUT_LVDS: | |
1558 | is_lvds = true; | |
1559 | break; | |
1560 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 1561 | case INTEL_OUTPUT_HDMI: |
79e53945 | 1562 | is_sdvo = true; |
e2f0ba97 JB |
1563 | if (intel_output->needs_tv_clock) |
1564 | is_tv = true; | |
79e53945 JB |
1565 | break; |
1566 | case INTEL_OUTPUT_DVO: | |
1567 | is_dvo = true; | |
1568 | break; | |
1569 | case INTEL_OUTPUT_TVOUT: | |
1570 | is_tv = true; | |
1571 | break; | |
1572 | case INTEL_OUTPUT_ANALOG: | |
1573 | is_crt = true; | |
1574 | break; | |
1575 | } | |
43565a06 KH |
1576 | |
1577 | num_outputs++; | |
79e53945 JB |
1578 | } |
1579 | ||
43565a06 KH |
1580 | if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) { |
1581 | refclk = dev_priv->lvds_ssc_freq * 1000; | |
1582 | DRM_DEBUG("using SSC reference clock of %d MHz\n", refclk / 1000); | |
1583 | } else if (IS_I9XX(dev)) { | |
79e53945 | 1584 | refclk = 96000; |
2c07245f ZW |
1585 | if (IS_IGDNG(dev)) |
1586 | refclk = 120000; /* 120Mhz refclk */ | |
79e53945 JB |
1587 | } else { |
1588 | refclk = 48000; | |
1589 | } | |
1590 | ||
d4906093 ML |
1591 | /* |
1592 | * Returns a set of divisors for the desired target clock with the given | |
1593 | * refclk, or FALSE. The returned values represent the clock equation: | |
1594 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
1595 | */ | |
1596 | limit = intel_limit(crtc); | |
1597 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock); | |
79e53945 JB |
1598 | if (!ok) { |
1599 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
5c3b82e2 | 1600 | return -EINVAL; |
79e53945 JB |
1601 | } |
1602 | ||
7026d4ac ZW |
1603 | /* SDVO TV has fixed PLL values depend on its clock range, |
1604 | this mirrors vbios setting. */ | |
1605 | if (is_sdvo && is_tv) { | |
1606 | if (adjusted_mode->clock >= 100000 | |
1607 | && adjusted_mode->clock < 140500) { | |
1608 | clock.p1 = 2; | |
1609 | clock.p2 = 10; | |
1610 | clock.n = 3; | |
1611 | clock.m1 = 16; | |
1612 | clock.m2 = 8; | |
1613 | } else if (adjusted_mode->clock >= 140500 | |
1614 | && adjusted_mode->clock <= 200000) { | |
1615 | clock.p1 = 1; | |
1616 | clock.p2 = 10; | |
1617 | clock.n = 6; | |
1618 | clock.m1 = 12; | |
1619 | clock.m2 = 8; | |
1620 | } | |
1621 | } | |
1622 | ||
2c07245f ZW |
1623 | /* FDI link */ |
1624 | if (IS_IGDNG(dev)) | |
1625 | igdng_compute_m_n(3, 4, /* lane num 4 */ | |
1626 | adjusted_mode->clock, | |
1627 | 270000, /* lane clock */ | |
1628 | &m_n); | |
1629 | ||
2177832f SL |
1630 | if (IS_IGD(dev)) |
1631 | fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2; | |
1632 | else | |
1633 | fp = clock.n << 16 | clock.m1 << 8 | clock.m2; | |
79e53945 | 1634 | |
2c07245f ZW |
1635 | if (!IS_IGDNG(dev)) |
1636 | dpll = DPLL_VGA_MODE_DIS; | |
1637 | ||
79e53945 JB |
1638 | if (IS_I9XX(dev)) { |
1639 | if (is_lvds) | |
1640 | dpll |= DPLLB_MODE_LVDS; | |
1641 | else | |
1642 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
1643 | if (is_sdvo) { | |
1644 | dpll |= DPLL_DVO_HIGH_SPEED; | |
2c07245f ZW |
1645 | sdvo_pixel_multiply = adjusted_mode->clock / mode->clock; |
1646 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
79e53945 | 1647 | dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; |
2c07245f ZW |
1648 | else if (IS_IGDNG(dev)) |
1649 | dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | |
79e53945 JB |
1650 | } |
1651 | ||
1652 | /* compute bitmask from p1 value */ | |
2177832f SL |
1653 | if (IS_IGD(dev)) |
1654 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD; | |
2c07245f | 1655 | else { |
2177832f | 1656 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
2c07245f ZW |
1657 | /* also FPA1 */ |
1658 | if (IS_IGDNG(dev)) | |
1659 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
1660 | } | |
79e53945 JB |
1661 | switch (clock.p2) { |
1662 | case 5: | |
1663 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
1664 | break; | |
1665 | case 7: | |
1666 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
1667 | break; | |
1668 | case 10: | |
1669 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
1670 | break; | |
1671 | case 14: | |
1672 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
1673 | break; | |
1674 | } | |
2c07245f | 1675 | if (IS_I965G(dev) && !IS_IGDNG(dev)) |
79e53945 JB |
1676 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
1677 | } else { | |
1678 | if (is_lvds) { | |
1679 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
1680 | } else { | |
1681 | if (clock.p1 == 2) | |
1682 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
1683 | else | |
1684 | dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
1685 | if (clock.p2 == 4) | |
1686 | dpll |= PLL_P2_DIVIDE_BY_4; | |
1687 | } | |
1688 | } | |
1689 | ||
43565a06 KH |
1690 | if (is_sdvo && is_tv) |
1691 | dpll |= PLL_REF_INPUT_TVCLKINBC; | |
1692 | else if (is_tv) | |
79e53945 | 1693 | /* XXX: just matching BIOS for now */ |
43565a06 | 1694 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
79e53945 | 1695 | dpll |= 3; |
43565a06 KH |
1696 | else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) |
1697 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
79e53945 JB |
1698 | else |
1699 | dpll |= PLL_REF_INPUT_DREFCLK; | |
1700 | ||
1701 | /* setup pipeconf */ | |
1702 | pipeconf = I915_READ(pipeconf_reg); | |
1703 | ||
1704 | /* Set up the display plane register */ | |
1705 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
1706 | ||
2c07245f ZW |
1707 | /* IGDNG's plane is forced to pipe, bit 24 is to |
1708 | enable color space conversion */ | |
1709 | if (!IS_IGDNG(dev)) { | |
1710 | if (pipe == 0) | |
1711 | dspcntr |= DISPPLANE_SEL_PIPE_A; | |
1712 | else | |
1713 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
1714 | } | |
79e53945 JB |
1715 | |
1716 | if (pipe == 0 && !IS_I965G(dev)) { | |
1717 | /* Enable pixel doubling when the dot clock is > 90% of the (display) | |
1718 | * core speed. | |
1719 | * | |
1720 | * XXX: No double-wide on 915GM pipe B. Is that the only reason for the | |
1721 | * pipe == 0 check? | |
1722 | */ | |
1723 | if (mode->clock > intel_get_core_clock_speed(dev) * 9 / 10) | |
1724 | pipeconf |= PIPEACONF_DOUBLE_WIDE; | |
1725 | else | |
1726 | pipeconf &= ~PIPEACONF_DOUBLE_WIDE; | |
1727 | } | |
1728 | ||
1729 | dspcntr |= DISPLAY_PLANE_ENABLE; | |
1730 | pipeconf |= PIPEACONF_ENABLE; | |
1731 | dpll |= DPLL_VCO_ENABLE; | |
1732 | ||
1733 | ||
1734 | /* Disable the panel fitter if it was on our pipe */ | |
2c07245f | 1735 | if (!IS_IGDNG(dev) && intel_panel_fitter_pipe(dev) == pipe) |
79e53945 JB |
1736 | I915_WRITE(PFIT_CONTROL, 0); |
1737 | ||
1738 | DRM_DEBUG("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); | |
1739 | drm_mode_debug_printmodeline(mode); | |
1740 | ||
2c07245f ZW |
1741 | /* assign to IGDNG registers */ |
1742 | if (IS_IGDNG(dev)) { | |
1743 | fp_reg = pch_fp_reg; | |
1744 | dpll_reg = pch_dpll_reg; | |
1745 | } | |
79e53945 JB |
1746 | |
1747 | if (dpll & DPLL_VCO_ENABLE) { | |
1748 | I915_WRITE(fp_reg, fp); | |
1749 | I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE); | |
1750 | I915_READ(dpll_reg); | |
1751 | udelay(150); | |
1752 | } | |
1753 | ||
2c07245f ZW |
1754 | if (IS_IGDNG(dev)) { |
1755 | /* enable PCH clock reference source */ | |
1756 | /* XXX need to change the setting for other outputs */ | |
1757 | u32 temp; | |
1758 | temp = I915_READ(PCH_DREF_CONTROL); | |
1759 | temp &= ~DREF_NONSPREAD_SOURCE_MASK; | |
1760 | temp |= DREF_NONSPREAD_CK505_ENABLE; | |
1761 | temp &= ~DREF_SSC_SOURCE_MASK; | |
1762 | temp |= DREF_SSC_SOURCE_ENABLE; | |
1763 | temp &= ~DREF_SSC1_ENABLE; | |
1764 | /* if no eDP, disable source output to CPU */ | |
1765 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
1766 | temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
1767 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
1768 | } | |
1769 | ||
79e53945 JB |
1770 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. |
1771 | * This is an exception to the general rule that mode_set doesn't turn | |
1772 | * things on. | |
1773 | */ | |
1774 | if (is_lvds) { | |
1775 | u32 lvds = I915_READ(LVDS); | |
1776 | ||
1777 | lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT; | |
1778 | /* Set the B0-B3 data pairs corresponding to whether we're going to | |
1779 | * set the DPLLs for dual-channel mode or not. | |
1780 | */ | |
1781 | if (clock.p2 == 7) | |
1782 | lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; | |
1783 | else | |
1784 | lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); | |
1785 | ||
1786 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) | |
1787 | * appropriately here, but we need to look more thoroughly into how | |
1788 | * panels behave in the two modes. | |
1789 | */ | |
1790 | ||
1791 | I915_WRITE(LVDS, lvds); | |
1792 | I915_READ(LVDS); | |
1793 | } | |
1794 | ||
1795 | I915_WRITE(fp_reg, fp); | |
1796 | I915_WRITE(dpll_reg, dpll); | |
1797 | I915_READ(dpll_reg); | |
1798 | /* Wait for the clocks to stabilize. */ | |
1799 | udelay(150); | |
1800 | ||
2c07245f ZW |
1801 | if (IS_I965G(dev) && !IS_IGDNG(dev)) { |
1802 | sdvo_pixel_multiply = adjusted_mode->clock / mode->clock; | |
79e53945 JB |
1803 | I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | |
1804 | ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT)); | |
1805 | } else { | |
1806 | /* write it again -- the BIOS does, after all */ | |
1807 | I915_WRITE(dpll_reg, dpll); | |
1808 | } | |
1809 | I915_READ(dpll_reg); | |
1810 | /* Wait for the clocks to stabilize. */ | |
1811 | udelay(150); | |
1812 | ||
1813 | I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) | | |
1814 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
1815 | I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) | | |
1816 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
1817 | I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) | | |
1818 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
1819 | I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) | | |
1820 | ((adjusted_mode->crtc_vtotal - 1) << 16)); | |
1821 | I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) | | |
1822 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); | |
1823 | I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) | | |
1824 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
1825 | /* pipesrc and dspsize control the size that is scaled from, which should | |
1826 | * always be the user's requested size. | |
1827 | */ | |
2c07245f ZW |
1828 | if (!IS_IGDNG(dev)) { |
1829 | I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) | | |
1830 | (mode->hdisplay - 1)); | |
1831 | I915_WRITE(dsppos_reg, 0); | |
1832 | } | |
79e53945 | 1833 | I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); |
2c07245f ZW |
1834 | |
1835 | if (IS_IGDNG(dev)) { | |
1836 | I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m); | |
1837 | I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n); | |
1838 | I915_WRITE(link_m1_reg, m_n.link_m); | |
1839 | I915_WRITE(link_n1_reg, m_n.link_n); | |
1840 | ||
1841 | /* enable FDI RX PLL too */ | |
1842 | temp = I915_READ(fdi_rx_reg); | |
1843 | I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE); | |
1844 | udelay(200); | |
1845 | } | |
1846 | ||
79e53945 JB |
1847 | I915_WRITE(pipeconf_reg, pipeconf); |
1848 | I915_READ(pipeconf_reg); | |
1849 | ||
1850 | intel_wait_for_vblank(dev); | |
1851 | ||
1852 | I915_WRITE(dspcntr_reg, dspcntr); | |
1853 | ||
1854 | /* Flush the plane changes */ | |
5c3b82e2 CW |
1855 | ret = intel_pipe_set_base(crtc, x, y, old_fb); |
1856 | if (ret != 0) | |
1857 | return ret; | |
79e53945 JB |
1858 | |
1859 | drm_vblank_post_modeset(dev, pipe); | |
5c3b82e2 CW |
1860 | |
1861 | return 0; | |
79e53945 JB |
1862 | } |
1863 | ||
1864 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
1865 | void intel_crtc_load_lut(struct drm_crtc *crtc) | |
1866 | { | |
1867 | struct drm_device *dev = crtc->dev; | |
1868 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1869 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1870 | int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B; | |
1871 | int i; | |
1872 | ||
1873 | /* The clocks have to be on to load the palette. */ | |
1874 | if (!crtc->enabled) | |
1875 | return; | |
1876 | ||
2c07245f ZW |
1877 | /* use legacy palette for IGDNG */ |
1878 | if (IS_IGDNG(dev)) | |
1879 | palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A : | |
1880 | LGC_PALETTE_B; | |
1881 | ||
79e53945 JB |
1882 | for (i = 0; i < 256; i++) { |
1883 | I915_WRITE(palreg + 4 * i, | |
1884 | (intel_crtc->lut_r[i] << 16) | | |
1885 | (intel_crtc->lut_g[i] << 8) | | |
1886 | intel_crtc->lut_b[i]); | |
1887 | } | |
1888 | } | |
1889 | ||
1890 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, | |
1891 | struct drm_file *file_priv, | |
1892 | uint32_t handle, | |
1893 | uint32_t width, uint32_t height) | |
1894 | { | |
1895 | struct drm_device *dev = crtc->dev; | |
1896 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1897 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1898 | struct drm_gem_object *bo; | |
1899 | struct drm_i915_gem_object *obj_priv; | |
1900 | int pipe = intel_crtc->pipe; | |
1901 | uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR; | |
1902 | uint32_t base = (pipe == 0) ? CURABASE : CURBBASE; | |
14b60391 | 1903 | uint32_t temp = I915_READ(control); |
79e53945 | 1904 | size_t addr; |
3f8bc370 | 1905 | int ret; |
79e53945 JB |
1906 | |
1907 | DRM_DEBUG("\n"); | |
1908 | ||
1909 | /* if we want to turn off the cursor ignore width and height */ | |
1910 | if (!handle) { | |
1911 | DRM_DEBUG("cursor off\n"); | |
14b60391 JB |
1912 | if (IS_MOBILE(dev) || IS_I9XX(dev)) { |
1913 | temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
1914 | temp |= CURSOR_MODE_DISABLE; | |
1915 | } else { | |
1916 | temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); | |
1917 | } | |
3f8bc370 KH |
1918 | addr = 0; |
1919 | bo = NULL; | |
5004417d | 1920 | mutex_lock(&dev->struct_mutex); |
3f8bc370 | 1921 | goto finish; |
79e53945 JB |
1922 | } |
1923 | ||
1924 | /* Currently we only support 64x64 cursors */ | |
1925 | if (width != 64 || height != 64) { | |
1926 | DRM_ERROR("we currently only support 64x64 cursors\n"); | |
1927 | return -EINVAL; | |
1928 | } | |
1929 | ||
1930 | bo = drm_gem_object_lookup(dev, file_priv, handle); | |
1931 | if (!bo) | |
1932 | return -ENOENT; | |
1933 | ||
1934 | obj_priv = bo->driver_private; | |
1935 | ||
1936 | if (bo->size < width * height * 4) { | |
1937 | DRM_ERROR("buffer is to small\n"); | |
34b8686e DA |
1938 | ret = -ENOMEM; |
1939 | goto fail; | |
79e53945 JB |
1940 | } |
1941 | ||
71acb5eb | 1942 | /* we only need to pin inside GTT if cursor is non-phy */ |
7f9872e0 | 1943 | mutex_lock(&dev->struct_mutex); |
71acb5eb DA |
1944 | if (!dev_priv->cursor_needs_physical) { |
1945 | ret = i915_gem_object_pin(bo, PAGE_SIZE); | |
1946 | if (ret) { | |
1947 | DRM_ERROR("failed to pin cursor bo\n"); | |
7f9872e0 | 1948 | goto fail_locked; |
71acb5eb | 1949 | } |
79e53945 | 1950 | addr = obj_priv->gtt_offset; |
71acb5eb DA |
1951 | } else { |
1952 | ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1); | |
1953 | if (ret) { | |
1954 | DRM_ERROR("failed to attach phys object\n"); | |
7f9872e0 | 1955 | goto fail_locked; |
71acb5eb DA |
1956 | } |
1957 | addr = obj_priv->phys_obj->handle->busaddr; | |
3f8bc370 KH |
1958 | } |
1959 | ||
14b60391 JB |
1960 | if (!IS_I9XX(dev)) |
1961 | I915_WRITE(CURSIZE, (height << 12) | width); | |
1962 | ||
1963 | /* Hooray for CUR*CNTR differences */ | |
1964 | if (IS_MOBILE(dev) || IS_I9XX(dev)) { | |
1965 | temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); | |
1966 | temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
1967 | temp |= (pipe << 28); /* Connect to correct pipe */ | |
1968 | } else { | |
1969 | temp &= ~(CURSOR_FORMAT_MASK); | |
1970 | temp |= CURSOR_ENABLE; | |
1971 | temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE; | |
1972 | } | |
79e53945 | 1973 | |
3f8bc370 | 1974 | finish: |
79e53945 JB |
1975 | I915_WRITE(control, temp); |
1976 | I915_WRITE(base, addr); | |
1977 | ||
3f8bc370 | 1978 | if (intel_crtc->cursor_bo) { |
71acb5eb DA |
1979 | if (dev_priv->cursor_needs_physical) { |
1980 | if (intel_crtc->cursor_bo != bo) | |
1981 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); | |
1982 | } else | |
1983 | i915_gem_object_unpin(intel_crtc->cursor_bo); | |
3f8bc370 KH |
1984 | drm_gem_object_unreference(intel_crtc->cursor_bo); |
1985 | } | |
7f9872e0 | 1986 | mutex_unlock(&dev->struct_mutex); |
3f8bc370 KH |
1987 | |
1988 | intel_crtc->cursor_addr = addr; | |
1989 | intel_crtc->cursor_bo = bo; | |
1990 | ||
79e53945 | 1991 | return 0; |
34b8686e DA |
1992 | fail: |
1993 | mutex_lock(&dev->struct_mutex); | |
7f9872e0 | 1994 | fail_locked: |
34b8686e DA |
1995 | drm_gem_object_unreference(bo); |
1996 | mutex_unlock(&dev->struct_mutex); | |
1997 | return ret; | |
79e53945 JB |
1998 | } |
1999 | ||
2000 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
2001 | { | |
2002 | struct drm_device *dev = crtc->dev; | |
2003 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2004 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2005 | int pipe = intel_crtc->pipe; | |
2006 | uint32_t temp = 0; | |
2007 | uint32_t adder; | |
2008 | ||
2009 | if (x < 0) { | |
2010 | temp |= (CURSOR_POS_SIGN << CURSOR_X_SHIFT); | |
2011 | x = -x; | |
2012 | } | |
2013 | if (y < 0) { | |
2014 | temp |= (CURSOR_POS_SIGN << CURSOR_Y_SHIFT); | |
2015 | y = -y; | |
2016 | } | |
2017 | ||
2018 | temp |= ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT); | |
2019 | temp |= ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT); | |
2020 | ||
2021 | adder = intel_crtc->cursor_addr; | |
2022 | I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp); | |
2023 | I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder); | |
2024 | ||
2025 | return 0; | |
2026 | } | |
2027 | ||
2028 | /** Sets the color ramps on behalf of RandR */ | |
2029 | void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, | |
2030 | u16 blue, int regno) | |
2031 | { | |
2032 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2033 | ||
2034 | intel_crtc->lut_r[regno] = red >> 8; | |
2035 | intel_crtc->lut_g[regno] = green >> 8; | |
2036 | intel_crtc->lut_b[regno] = blue >> 8; | |
2037 | } | |
2038 | ||
2039 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, | |
2040 | u16 *blue, uint32_t size) | |
2041 | { | |
2042 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2043 | int i; | |
2044 | ||
2045 | if (size != 256) | |
2046 | return; | |
2047 | ||
2048 | for (i = 0; i < 256; i++) { | |
2049 | intel_crtc->lut_r[i] = red[i] >> 8; | |
2050 | intel_crtc->lut_g[i] = green[i] >> 8; | |
2051 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
2052 | } | |
2053 | ||
2054 | intel_crtc_load_lut(crtc); | |
2055 | } | |
2056 | ||
2057 | /** | |
2058 | * Get a pipe with a simple mode set on it for doing load-based monitor | |
2059 | * detection. | |
2060 | * | |
2061 | * It will be up to the load-detect code to adjust the pipe as appropriate for | |
2062 | * its requirements. The pipe will be connected to no other outputs. | |
2063 | * | |
2064 | * Currently this code will only succeed if there is a pipe with no outputs | |
2065 | * configured for it. In the future, it could choose to temporarily disable | |
2066 | * some outputs to free up a pipe for its use. | |
2067 | * | |
2068 | * \return crtc, or NULL if no pipes are available. | |
2069 | */ | |
2070 | ||
2071 | /* VESA 640x480x72Hz mode to set on the pipe */ | |
2072 | static struct drm_display_mode load_detect_mode = { | |
2073 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
2074 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
2075 | }; | |
2076 | ||
2077 | struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output, | |
2078 | struct drm_display_mode *mode, | |
2079 | int *dpms_mode) | |
2080 | { | |
2081 | struct intel_crtc *intel_crtc; | |
2082 | struct drm_crtc *possible_crtc; | |
2083 | struct drm_crtc *supported_crtc =NULL; | |
2084 | struct drm_encoder *encoder = &intel_output->enc; | |
2085 | struct drm_crtc *crtc = NULL; | |
2086 | struct drm_device *dev = encoder->dev; | |
2087 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
2088 | struct drm_crtc_helper_funcs *crtc_funcs; | |
2089 | int i = -1; | |
2090 | ||
2091 | /* | |
2092 | * Algorithm gets a little messy: | |
2093 | * - if the connector already has an assigned crtc, use it (but make | |
2094 | * sure it's on first) | |
2095 | * - try to find the first unused crtc that can drive this connector, | |
2096 | * and use that if we find one | |
2097 | * - if there are no unused crtcs available, try to use the first | |
2098 | * one we found that supports the connector | |
2099 | */ | |
2100 | ||
2101 | /* See if we already have a CRTC for this connector */ | |
2102 | if (encoder->crtc) { | |
2103 | crtc = encoder->crtc; | |
2104 | /* Make sure the crtc and connector are running */ | |
2105 | intel_crtc = to_intel_crtc(crtc); | |
2106 | *dpms_mode = intel_crtc->dpms_mode; | |
2107 | if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) { | |
2108 | crtc_funcs = crtc->helper_private; | |
2109 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); | |
2110 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); | |
2111 | } | |
2112 | return crtc; | |
2113 | } | |
2114 | ||
2115 | /* Find an unused one (if possible) */ | |
2116 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { | |
2117 | i++; | |
2118 | if (!(encoder->possible_crtcs & (1 << i))) | |
2119 | continue; | |
2120 | if (!possible_crtc->enabled) { | |
2121 | crtc = possible_crtc; | |
2122 | break; | |
2123 | } | |
2124 | if (!supported_crtc) | |
2125 | supported_crtc = possible_crtc; | |
2126 | } | |
2127 | ||
2128 | /* | |
2129 | * If we didn't find an unused CRTC, don't use any. | |
2130 | */ | |
2131 | if (!crtc) { | |
2132 | return NULL; | |
2133 | } | |
2134 | ||
2135 | encoder->crtc = crtc; | |
2136 | intel_output->load_detect_temp = true; | |
2137 | ||
2138 | intel_crtc = to_intel_crtc(crtc); | |
2139 | *dpms_mode = intel_crtc->dpms_mode; | |
2140 | ||
2141 | if (!crtc->enabled) { | |
2142 | if (!mode) | |
2143 | mode = &load_detect_mode; | |
3c4fdcfb | 2144 | drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb); |
79e53945 JB |
2145 | } else { |
2146 | if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) { | |
2147 | crtc_funcs = crtc->helper_private; | |
2148 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); | |
2149 | } | |
2150 | ||
2151 | /* Add this connector to the crtc */ | |
2152 | encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode); | |
2153 | encoder_funcs->commit(encoder); | |
2154 | } | |
2155 | /* let the connector get through one full cycle before testing */ | |
2156 | intel_wait_for_vblank(dev); | |
2157 | ||
2158 | return crtc; | |
2159 | } | |
2160 | ||
2161 | void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode) | |
2162 | { | |
2163 | struct drm_encoder *encoder = &intel_output->enc; | |
2164 | struct drm_device *dev = encoder->dev; | |
2165 | struct drm_crtc *crtc = encoder->crtc; | |
2166 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
2167 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
2168 | ||
2169 | if (intel_output->load_detect_temp) { | |
2170 | encoder->crtc = NULL; | |
2171 | intel_output->load_detect_temp = false; | |
2172 | crtc->enabled = drm_helper_crtc_in_use(crtc); | |
2173 | drm_helper_disable_unused_functions(dev); | |
2174 | } | |
2175 | ||
2176 | /* Switch crtc and output back off if necessary */ | |
2177 | if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) { | |
2178 | if (encoder->crtc == crtc) | |
2179 | encoder_funcs->dpms(encoder, dpms_mode); | |
2180 | crtc_funcs->dpms(crtc, dpms_mode); | |
2181 | } | |
2182 | } | |
2183 | ||
2184 | /* Returns the clock of the currently programmed mode of the given pipe. */ | |
2185 | static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc) | |
2186 | { | |
2187 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2188 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2189 | int pipe = intel_crtc->pipe; | |
2190 | u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B); | |
2191 | u32 fp; | |
2192 | intel_clock_t clock; | |
2193 | ||
2194 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
2195 | fp = I915_READ((pipe == 0) ? FPA0 : FPB0); | |
2196 | else | |
2197 | fp = I915_READ((pipe == 0) ? FPA1 : FPB1); | |
2198 | ||
2199 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
2177832f SL |
2200 | if (IS_IGD(dev)) { |
2201 | clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
2202 | clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2203 | } else { | |
2204 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
2205 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2206 | } | |
2207 | ||
79e53945 | 2208 | if (IS_I9XX(dev)) { |
2177832f SL |
2209 | if (IS_IGD(dev)) |
2210 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >> | |
2211 | DPLL_FPA01_P1_POST_DIV_SHIFT_IGD); | |
2212 | else | |
2213 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
2214 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
2215 | ||
2216 | switch (dpll & DPLL_MODE_MASK) { | |
2217 | case DPLLB_MODE_DAC_SERIAL: | |
2218 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
2219 | 5 : 10; | |
2220 | break; | |
2221 | case DPLLB_MODE_LVDS: | |
2222 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
2223 | 7 : 14; | |
2224 | break; | |
2225 | default: | |
2226 | DRM_DEBUG("Unknown DPLL mode %08x in programmed " | |
2227 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); | |
2228 | return 0; | |
2229 | } | |
2230 | ||
2231 | /* XXX: Handle the 100Mhz refclk */ | |
2177832f | 2232 | intel_clock(dev, 96000, &clock); |
79e53945 JB |
2233 | } else { |
2234 | bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); | |
2235 | ||
2236 | if (is_lvds) { | |
2237 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
2238 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
2239 | clock.p2 = 14; | |
2240 | ||
2241 | if ((dpll & PLL_REF_INPUT_MASK) == | |
2242 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
2243 | /* XXX: might not be 66MHz */ | |
2177832f | 2244 | intel_clock(dev, 66000, &clock); |
79e53945 | 2245 | } else |
2177832f | 2246 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
2247 | } else { |
2248 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
2249 | clock.p1 = 2; | |
2250 | else { | |
2251 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
2252 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
2253 | } | |
2254 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
2255 | clock.p2 = 4; | |
2256 | else | |
2257 | clock.p2 = 2; | |
2258 | ||
2177832f | 2259 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
2260 | } |
2261 | } | |
2262 | ||
2263 | /* XXX: It would be nice to validate the clocks, but we can't reuse | |
2264 | * i830PllIsValid() because it relies on the xf86_config connector | |
2265 | * configuration being accurate, which it isn't necessarily. | |
2266 | */ | |
2267 | ||
2268 | return clock.dot; | |
2269 | } | |
2270 | ||
2271 | /** Returns the currently programmed mode of the given pipe. */ | |
2272 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
2273 | struct drm_crtc *crtc) | |
2274 | { | |
2275 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2276 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2277 | int pipe = intel_crtc->pipe; | |
2278 | struct drm_display_mode *mode; | |
2279 | int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B); | |
2280 | int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B); | |
2281 | int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B); | |
2282 | int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B); | |
2283 | ||
2284 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
2285 | if (!mode) | |
2286 | return NULL; | |
2287 | ||
2288 | mode->clock = intel_crtc_clock_get(dev, crtc); | |
2289 | mode->hdisplay = (htot & 0xffff) + 1; | |
2290 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
2291 | mode->hsync_start = (hsync & 0xffff) + 1; | |
2292 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
2293 | mode->vdisplay = (vtot & 0xffff) + 1; | |
2294 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
2295 | mode->vsync_start = (vsync & 0xffff) + 1; | |
2296 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
2297 | ||
2298 | drm_mode_set_name(mode); | |
2299 | drm_mode_set_crtcinfo(mode, 0); | |
2300 | ||
2301 | return mode; | |
2302 | } | |
2303 | ||
2304 | static void intel_crtc_destroy(struct drm_crtc *crtc) | |
2305 | { | |
2306 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2307 | ||
2308 | drm_crtc_cleanup(crtc); | |
2309 | kfree(intel_crtc); | |
2310 | } | |
2311 | ||
2312 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { | |
2313 | .dpms = intel_crtc_dpms, | |
2314 | .mode_fixup = intel_crtc_mode_fixup, | |
2315 | .mode_set = intel_crtc_mode_set, | |
2316 | .mode_set_base = intel_pipe_set_base, | |
2317 | .prepare = intel_crtc_prepare, | |
2318 | .commit = intel_crtc_commit, | |
2319 | }; | |
2320 | ||
2321 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
2322 | .cursor_set = intel_crtc_cursor_set, | |
2323 | .cursor_move = intel_crtc_cursor_move, | |
2324 | .gamma_set = intel_crtc_gamma_set, | |
2325 | .set_config = drm_crtc_helper_set_config, | |
2326 | .destroy = intel_crtc_destroy, | |
2327 | }; | |
2328 | ||
2329 | ||
b358d0a6 | 2330 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 JB |
2331 | { |
2332 | struct intel_crtc *intel_crtc; | |
2333 | int i; | |
2334 | ||
2335 | intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); | |
2336 | if (intel_crtc == NULL) | |
2337 | return; | |
2338 | ||
2339 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); | |
2340 | ||
2341 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
2342 | intel_crtc->pipe = pipe; | |
2343 | for (i = 0; i < 256; i++) { | |
2344 | intel_crtc->lut_r[i] = i; | |
2345 | intel_crtc->lut_g[i] = i; | |
2346 | intel_crtc->lut_b[i] = i; | |
2347 | } | |
2348 | ||
2349 | intel_crtc->cursor_addr = 0; | |
2350 | intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF; | |
2351 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); | |
2352 | ||
2353 | intel_crtc->mode_set.crtc = &intel_crtc->base; | |
2354 | intel_crtc->mode_set.connectors = (struct drm_connector **)(intel_crtc + 1); | |
2355 | intel_crtc->mode_set.num_connectors = 0; | |
2356 | ||
2357 | if (i915_fbpercrtc) { | |
2358 | ||
2359 | ||
2360 | ||
2361 | } | |
2362 | } | |
2363 | ||
08d7b3d1 CW |
2364 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
2365 | struct drm_file *file_priv) | |
2366 | { | |
2367 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2368 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; | |
2369 | struct drm_crtc *crtc = NULL; | |
2370 | int pipe = -1; | |
2371 | ||
2372 | if (!dev_priv) { | |
2373 | DRM_ERROR("called with no initialization\n"); | |
2374 | return -EINVAL; | |
2375 | } | |
2376 | ||
2377 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2378 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2379 | if (crtc->base.id == pipe_from_crtc_id->crtc_id) { | |
2380 | pipe = intel_crtc->pipe; | |
2381 | break; | |
2382 | } | |
2383 | } | |
2384 | ||
2385 | if (pipe == -1) { | |
2386 | DRM_ERROR("no such CRTC id\n"); | |
2387 | return -EINVAL; | |
2388 | } | |
2389 | ||
2390 | pipe_from_crtc_id->pipe = pipe; | |
2391 | ||
2392 | return 0; | |
2393 | } | |
2394 | ||
79e53945 JB |
2395 | struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe) |
2396 | { | |
2397 | struct drm_crtc *crtc = NULL; | |
2398 | ||
2399 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2400 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2401 | if (intel_crtc->pipe == pipe) | |
2402 | break; | |
2403 | } | |
2404 | return crtc; | |
2405 | } | |
2406 | ||
b358d0a6 | 2407 | static int intel_connector_clones(struct drm_device *dev, int type_mask) |
79e53945 JB |
2408 | { |
2409 | int index_mask = 0; | |
2410 | struct drm_connector *connector; | |
2411 | int entry = 0; | |
2412 | ||
2413 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
2414 | struct intel_output *intel_output = to_intel_output(connector); | |
2415 | if (type_mask & (1 << intel_output->type)) | |
2416 | index_mask |= (1 << entry); | |
2417 | entry++; | |
2418 | } | |
2419 | return index_mask; | |
2420 | } | |
2421 | ||
2422 | ||
2423 | static void intel_setup_outputs(struct drm_device *dev) | |
2424 | { | |
725e30ad | 2425 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 JB |
2426 | struct drm_connector *connector; |
2427 | ||
2428 | intel_crt_init(dev); | |
2429 | ||
2430 | /* Set up integrated LVDS */ | |
2c07245f | 2431 | if (IS_MOBILE(dev) && !IS_I830(dev) && !IS_IGDNG(dev)) |
79e53945 JB |
2432 | intel_lvds_init(dev); |
2433 | ||
2c07245f | 2434 | if (IS_IGDNG(dev)) { |
30ad48b7 ZW |
2435 | int found; |
2436 | ||
2437 | if (I915_READ(HDMIB) & PORT_DETECTED) { | |
2438 | /* check SDVOB */ | |
2439 | /* found = intel_sdvo_init(dev, HDMIB); */ | |
2440 | found = 0; | |
2441 | if (!found) | |
2442 | intel_hdmi_init(dev, HDMIB); | |
2443 | } | |
2444 | ||
2445 | if (I915_READ(HDMIC) & PORT_DETECTED) | |
2446 | intel_hdmi_init(dev, HDMIC); | |
2447 | ||
2448 | if (I915_READ(HDMID) & PORT_DETECTED) | |
2449 | intel_hdmi_init(dev, HDMID); | |
2450 | ||
2c07245f | 2451 | } else if (IS_I9XX(dev)) { |
7d57382e | 2452 | int found; |
13520b05 | 2453 | u32 reg; |
7d57382e | 2454 | |
725e30ad EA |
2455 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
2456 | found = intel_sdvo_init(dev, SDVOB); | |
2457 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) | |
2458 | intel_hdmi_init(dev, SDVOB); | |
2459 | } | |
13520b05 KH |
2460 | |
2461 | /* Before G4X SDVOC doesn't have its own detect register */ | |
2462 | if (IS_G4X(dev)) | |
2463 | reg = SDVOC; | |
2464 | else | |
2465 | reg = SDVOB; | |
2466 | ||
2467 | if (I915_READ(reg) & SDVO_DETECTED) { | |
725e30ad EA |
2468 | found = intel_sdvo_init(dev, SDVOC); |
2469 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) | |
2470 | intel_hdmi_init(dev, SDVOC); | |
2471 | } | |
79e53945 JB |
2472 | } else |
2473 | intel_dvo_init(dev); | |
2474 | ||
2c07245f | 2475 | if (IS_I9XX(dev) && IS_MOBILE(dev) && !IS_IGDNG(dev)) |
79e53945 JB |
2476 | intel_tv_init(dev); |
2477 | ||
2478 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
2479 | struct intel_output *intel_output = to_intel_output(connector); | |
2480 | struct drm_encoder *encoder = &intel_output->enc; | |
2481 | int crtc_mask = 0, clone_mask = 0; | |
2482 | ||
2483 | /* valid crtcs */ | |
2484 | switch(intel_output->type) { | |
7d57382e EA |
2485 | case INTEL_OUTPUT_HDMI: |
2486 | crtc_mask = ((1 << 0)| | |
2487 | (1 << 1)); | |
2488 | clone_mask = ((1 << INTEL_OUTPUT_HDMI)); | |
2489 | break; | |
79e53945 JB |
2490 | case INTEL_OUTPUT_DVO: |
2491 | case INTEL_OUTPUT_SDVO: | |
2492 | crtc_mask = ((1 << 0)| | |
2493 | (1 << 1)); | |
2494 | clone_mask = ((1 << INTEL_OUTPUT_ANALOG) | | |
2495 | (1 << INTEL_OUTPUT_DVO) | | |
2496 | (1 << INTEL_OUTPUT_SDVO)); | |
2497 | break; | |
2498 | case INTEL_OUTPUT_ANALOG: | |
2499 | crtc_mask = ((1 << 0)| | |
2500 | (1 << 1)); | |
2501 | clone_mask = ((1 << INTEL_OUTPUT_ANALOG) | | |
2502 | (1 << INTEL_OUTPUT_DVO) | | |
2503 | (1 << INTEL_OUTPUT_SDVO)); | |
2504 | break; | |
2505 | case INTEL_OUTPUT_LVDS: | |
2506 | crtc_mask = (1 << 1); | |
2507 | clone_mask = (1 << INTEL_OUTPUT_LVDS); | |
2508 | break; | |
2509 | case INTEL_OUTPUT_TVOUT: | |
2510 | crtc_mask = ((1 << 0) | | |
2511 | (1 << 1)); | |
2512 | clone_mask = (1 << INTEL_OUTPUT_TVOUT); | |
2513 | break; | |
2514 | } | |
2515 | encoder->possible_crtcs = crtc_mask; | |
2516 | encoder->possible_clones = intel_connector_clones(dev, clone_mask); | |
2517 | } | |
2518 | } | |
2519 | ||
2520 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
2521 | { | |
2522 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
2523 | struct drm_device *dev = fb->dev; | |
2524 | ||
2525 | if (fb->fbdev) | |
2526 | intelfb_remove(dev, fb); | |
2527 | ||
2528 | drm_framebuffer_cleanup(fb); | |
2529 | mutex_lock(&dev->struct_mutex); | |
2530 | drm_gem_object_unreference(intel_fb->obj); | |
2531 | mutex_unlock(&dev->struct_mutex); | |
2532 | ||
2533 | kfree(intel_fb); | |
2534 | } | |
2535 | ||
2536 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
2537 | struct drm_file *file_priv, | |
2538 | unsigned int *handle) | |
2539 | { | |
2540 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
2541 | struct drm_gem_object *object = intel_fb->obj; | |
2542 | ||
2543 | return drm_gem_handle_create(file_priv, object, handle); | |
2544 | } | |
2545 | ||
2546 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
2547 | .destroy = intel_user_framebuffer_destroy, | |
2548 | .create_handle = intel_user_framebuffer_create_handle, | |
2549 | }; | |
2550 | ||
2551 | int intel_framebuffer_create(struct drm_device *dev, | |
2552 | struct drm_mode_fb_cmd *mode_cmd, | |
2553 | struct drm_framebuffer **fb, | |
2554 | struct drm_gem_object *obj) | |
2555 | { | |
2556 | struct intel_framebuffer *intel_fb; | |
2557 | int ret; | |
2558 | ||
2559 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
2560 | if (!intel_fb) | |
2561 | return -ENOMEM; | |
2562 | ||
2563 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); | |
2564 | if (ret) { | |
2565 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
2566 | return ret; | |
2567 | } | |
2568 | ||
2569 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); | |
2570 | ||
2571 | intel_fb->obj = obj; | |
2572 | ||
2573 | *fb = &intel_fb->base; | |
2574 | ||
2575 | return 0; | |
2576 | } | |
2577 | ||
2578 | ||
2579 | static struct drm_framebuffer * | |
2580 | intel_user_framebuffer_create(struct drm_device *dev, | |
2581 | struct drm_file *filp, | |
2582 | struct drm_mode_fb_cmd *mode_cmd) | |
2583 | { | |
2584 | struct drm_gem_object *obj; | |
2585 | struct drm_framebuffer *fb; | |
2586 | int ret; | |
2587 | ||
2588 | obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle); | |
2589 | if (!obj) | |
2590 | return NULL; | |
2591 | ||
2592 | ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj); | |
2593 | if (ret) { | |
496818f0 | 2594 | mutex_lock(&dev->struct_mutex); |
79e53945 | 2595 | drm_gem_object_unreference(obj); |
496818f0 | 2596 | mutex_unlock(&dev->struct_mutex); |
79e53945 JB |
2597 | return NULL; |
2598 | } | |
2599 | ||
2600 | return fb; | |
2601 | } | |
2602 | ||
79e53945 | 2603 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 JB |
2604 | .fb_create = intel_user_framebuffer_create, |
2605 | .fb_changed = intelfb_probe, | |
2606 | }; | |
2607 | ||
2608 | void intel_modeset_init(struct drm_device *dev) | |
2609 | { | |
2610 | int num_pipe; | |
2611 | int i; | |
2612 | ||
2613 | drm_mode_config_init(dev); | |
2614 | ||
2615 | dev->mode_config.min_width = 0; | |
2616 | dev->mode_config.min_height = 0; | |
2617 | ||
2618 | dev->mode_config.funcs = (void *)&intel_mode_funcs; | |
2619 | ||
2620 | if (IS_I965G(dev)) { | |
2621 | dev->mode_config.max_width = 8192; | |
2622 | dev->mode_config.max_height = 8192; | |
2623 | } else { | |
2624 | dev->mode_config.max_width = 2048; | |
2625 | dev->mode_config.max_height = 2048; | |
2626 | } | |
2627 | ||
2628 | /* set memory base */ | |
2629 | if (IS_I9XX(dev)) | |
2630 | dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2); | |
2631 | else | |
2632 | dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0); | |
2633 | ||
2634 | if (IS_MOBILE(dev) || IS_I9XX(dev)) | |
2635 | num_pipe = 2; | |
2636 | else | |
2637 | num_pipe = 1; | |
2638 | DRM_DEBUG("%d display pipe%s available.\n", | |
2639 | num_pipe, num_pipe > 1 ? "s" : ""); | |
2640 | ||
2641 | for (i = 0; i < num_pipe; i++) { | |
2642 | intel_crtc_init(dev, i); | |
2643 | } | |
2644 | ||
2645 | intel_setup_outputs(dev); | |
2646 | } | |
2647 | ||
2648 | void intel_modeset_cleanup(struct drm_device *dev) | |
2649 | { | |
2650 | drm_mode_config_cleanup(dev); | |
2651 | } | |
2652 | ||
2653 | ||
2654 | /* current intel driver doesn't take advantage of encoders | |
2655 | always give back the encoder for the connector | |
2656 | */ | |
2657 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) | |
2658 | { | |
2659 | struct intel_output *intel_output = to_intel_output(connector); | |
2660 | ||
2661 | return &intel_output->enc; | |
2662 | } |