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drm/i915: Use drm_atomic_helper_update_legacy_modeset_state, v2.
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c 48/* Primary plane formats for gen <= 3 */
568db4f2 49static const uint32_t i8xx_primary_formats[] = {
67fe7dc5
DL		 50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
465c120c 52 DRM_FORMAT_XRGB1555,
67fe7dc5 53 DRM_FORMAT_XRGB8888,
465c120c
MR		 54};
55
56/* Primary plane formats for gen >= 4 */
568db4f2 57static const uint32_t i965_primary_formats[] = {
6c0fd451
DL		 58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64};
65
66static const uint32_t skl_primary_formats[] = {
67fe7dc5
DL		 67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
465c120c 70 DRM_FORMAT_XBGR8888,
67fe7dc5 71 DRM_FORMAT_ARGB8888,
465c120c
MR		 72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
465c120c 74 DRM_FORMAT_XBGR2101010,
465c120c
MR		 75};
76
3d7d6510
MR		 77/* Cursor formats */
78static const uint32_t intel_cursor_formats[] = {
79 DRM_FORMAT_ARGB8888,
80};
81
6b383a7f 82static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 83
f1f644dc 84static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 85 struct intel_crtc_state *pipe_config);
18442d08 86static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 87 struct intel_crtc_state *pipe_config);
f1f644dc 88
8c7b5ccb 89static int intel_set_mode(struct drm_crtc *crtc,
83a57153 90 struct drm_atomic_state *state);
eb1bfe80
JB		 91static int intel_framebuffer_init(struct drm_device *dev,
92 struct intel_framebuffer *ifb,
93 struct drm_mode_fb_cmd2 *mode_cmd,
94 struct drm_i915_gem_object *obj);
5b18e57c
DV		 95static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
96static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 97static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 98 struct intel_link_m_n *m_n,
99 struct intel_link_m_n *m2_n2);
29407aab 100static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 101static void haswell_set_pipeconf(struct drm_crtc *crtc);
102static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 103static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 104 const struct intel_crtc_state *pipe_config);
d288f65f 105static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 106 const struct intel_crtc_state *pipe_config);
ea2c67bb
MR		 107static void intel_begin_crtc_commit(struct drm_crtc *crtc);
108static void intel_finish_crtc_commit(struct drm_crtc *crtc);
549e2bfb
CK		 109static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
110 struct intel_crtc_state *crtc_state);
5ab7b0b7
ID		 111static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
112 int num_connectors);
ce22dba9
ML		 113static void intel_crtc_enable_planes(struct drm_crtc *crtc);
114static void intel_crtc_disable_planes(struct drm_crtc *crtc);
e7457a9a 115
0e32b39c
DA		 116static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
117{
118 if (!connector->mst_port)
119 return connector->encoder;
120 else
121 return &connector->mst_port->mst_encoders[pipe]->base;
122}
123
79e53945 124typedef struct {
0206e353 125 int min, max;
79e53945
JB		 126} intel_range_t;
127
128typedef struct {
0206e353
AJ		 129 int dot_limit;
130 int p2_slow, p2_fast;
79e53945
JB		 131} intel_p2_t;
132
d4906093
ML		 133typedef struct intel_limit intel_limit_t;
134struct intel_limit {
0206e353
AJ		 135 intel_range_t dot, vco, n, m, m1, m2, p, p1;
136 intel_p2_t p2;
d4906093 137};
79e53945 138
d2acd215
DV		 139int
140intel_pch_rawclk(struct drm_device *dev)
141{
142 struct drm_i915_private *dev_priv = dev->dev_private;
143
144 WARN_ON(!HAS_PCH_SPLIT(dev));
145
146 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
147}
148
021357ac
CW		 149static inline u32 /* units of 100MHz */
150intel_fdi_link_freq(struct drm_device *dev)
151{
8b99e68c
CW		 152 if (IS_GEN5(dev)) {
153 struct drm_i915_private *dev_priv = dev->dev_private;
154 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
155 } else
156 return 27;
021357ac
CW		 157}
158
5d536e28 159static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 160 .dot = { .min = 25000, .max = 350000 },
9c333719 161 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 162 .n = { .min = 2, .max = 16 },
0206e353
AJ		 163 .m = { .min = 96, .max = 140 },
164 .m1 = { .min = 18, .max = 26 },
165 .m2 = { .min = 6, .max = 16 },
166 .p = { .min = 4, .max = 128 },
167 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 168 .p2 = { .dot_limit = 165000,
169 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 170};
171
5d536e28
DV		 172static const intel_limit_t intel_limits_i8xx_dvo = {
173 .dot = { .min = 25000, .max = 350000 },
9c333719 174 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 175 .n = { .min = 2, .max = 16 },
5d536e28
DV		 176 .m = { .min = 96, .max = 140 },
177 .m1 = { .min = 18, .max = 26 },
178 .m2 = { .min = 6, .max = 16 },
179 .p = { .min = 4, .max = 128 },
180 .p1 = { .min = 2, .max = 33 },
181 .p2 = { .dot_limit = 165000,
182 .p2_slow = 4, .p2_fast = 4 },
183};
184
e4b36699 185static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 186 .dot = { .min = 25000, .max = 350000 },
9c333719 187 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 188 .n = { .min = 2, .max = 16 },
0206e353
AJ		 189 .m = { .min = 96, .max = 140 },
190 .m1 = { .min = 18, .max = 26 },
191 .m2 = { .min = 6, .max = 16 },
192 .p = { .min = 4, .max = 128 },
193 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 194 .p2 = { .dot_limit = 165000,
195 .p2_slow = 14, .p2_fast = 7 },
e4b36699 196};
273e27ca 197
e4b36699 198static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 199 .dot = { .min = 20000, .max = 400000 },
200 .vco = { .min = 1400000, .max = 2800000 },
201 .n = { .min = 1, .max = 6 },
202 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 203 .m1 = { .min = 8, .max = 18 },
204 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 205 .p = { .min = 5, .max = 80 },
206 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 207 .p2 = { .dot_limit = 200000,
208 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 209};
210
211static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 212 .dot = { .min = 20000, .max = 400000 },
213 .vco = { .min = 1400000, .max = 2800000 },
214 .n = { .min = 1, .max = 6 },
215 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 216 .m1 = { .min = 8, .max = 18 },
217 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 218 .p = { .min = 7, .max = 98 },
219 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 220 .p2 = { .dot_limit = 112000,
221 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 222};
223
273e27ca 224
e4b36699 225static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 226 .dot = { .min = 25000, .max = 270000 },
227 .vco = { .min = 1750000, .max = 3500000},
228 .n = { .min = 1, .max = 4 },
229 .m = { .min = 104, .max = 138 },
230 .m1 = { .min = 17, .max = 23 },
231 .m2 = { .min = 5, .max = 11 },
232 .p = { .min = 10, .max = 30 },
233 .p1 = { .min = 1, .max = 3},
234 .p2 = { .dot_limit = 270000,
235 .p2_slow = 10,
236 .p2_fast = 10
044c7c41 237 },
e4b36699
KP		 238};
239
240static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 241 .dot = { .min = 22000, .max = 400000 },
242 .vco = { .min = 1750000, .max = 3500000},
243 .n = { .min = 1, .max = 4 },
244 .m = { .min = 104, .max = 138 },
245 .m1 = { .min = 16, .max = 23 },
246 .m2 = { .min = 5, .max = 11 },
247 .p = { .min = 5, .max = 80 },
248 .p1 = { .min = 1, .max = 8},
249 .p2 = { .dot_limit = 165000,
250 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 251};
252
253static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 254 .dot = { .min = 20000, .max = 115000 },
255 .vco = { .min = 1750000, .max = 3500000 },
256 .n = { .min = 1, .max = 3 },
257 .m = { .min = 104, .max = 138 },
258 .m1 = { .min = 17, .max = 23 },
259 .m2 = { .min = 5, .max = 11 },
260 .p = { .min = 28, .max = 112 },
261 .p1 = { .min = 2, .max = 8 },
262 .p2 = { .dot_limit = 0,
263 .p2_slow = 14, .p2_fast = 14
044c7c41 264 },
e4b36699
KP		 265};
266
267static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 268 .dot = { .min = 80000, .max = 224000 },
269 .vco = { .min = 1750000, .max = 3500000 },
270 .n = { .min = 1, .max = 3 },
271 .m = { .min = 104, .max = 138 },
272 .m1 = { .min = 17, .max = 23 },
273 .m2 = { .min = 5, .max = 11 },
274 .p = { .min = 14, .max = 42 },
275 .p1 = { .min = 2, .max = 6 },
276 .p2 = { .dot_limit = 0,
277 .p2_slow = 7, .p2_fast = 7
044c7c41 278 },
e4b36699
KP		 279};
280
f2b115e6 281static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 282 .dot = { .min = 20000, .max = 400000},
283 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 284 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 285 .n = { .min = 3, .max = 6 },
286 .m = { .min = 2, .max = 256 },
273e27ca 287 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 288 .m1 = { .min = 0, .max = 0 },
289 .m2 = { .min = 0, .max = 254 },
290 .p = { .min = 5, .max = 80 },
291 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 292 .p2 = { .dot_limit = 200000,
293 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 294};
295
f2b115e6 296static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 297 .dot = { .min = 20000, .max = 400000 },
298 .vco = { .min = 1700000, .max = 3500000 },
299 .n = { .min = 3, .max = 6 },
300 .m = { .min = 2, .max = 256 },
301 .m1 = { .min = 0, .max = 0 },
302 .m2 = { .min = 0, .max = 254 },
303 .p = { .min = 7, .max = 112 },
304 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 305 .p2 = { .dot_limit = 112000,
306 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 307};
308
273e27ca
EA		 309/* Ironlake / Sandybridge
310 *
311 * We calculate clock using (register_value + 2) for N/M1/M2, so here
312 * the range value for them is (actual_value - 2).
313 */
b91ad0ec 314static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 315 .dot = { .min = 25000, .max = 350000 },
316 .vco = { .min = 1760000, .max = 3510000 },
317 .n = { .min = 1, .max = 5 },
318 .m = { .min = 79, .max = 127 },
319 .m1 = { .min = 12, .max = 22 },
320 .m2 = { .min = 5, .max = 9 },
321 .p = { .min = 5, .max = 80 },
322 .p1 = { .min = 1, .max = 8 },
323 .p2 = { .dot_limit = 225000,
324 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 325};
326
b91ad0ec 327static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 328 .dot = { .min = 25000, .max = 350000 },
329 .vco = { .min = 1760000, .max = 3510000 },
330 .n = { .min = 1, .max = 3 },
331 .m = { .min = 79, .max = 118 },
332 .m1 = { .min = 12, .max = 22 },
333 .m2 = { .min = 5, .max = 9 },
334 .p = { .min = 28, .max = 112 },
335 .p1 = { .min = 2, .max = 8 },
336 .p2 = { .dot_limit = 225000,
337 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 338};
339
340static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 341 .dot = { .min = 25000, .max = 350000 },
342 .vco = { .min = 1760000, .max = 3510000 },
343 .n = { .min = 1, .max = 3 },
344 .m = { .min = 79, .max = 127 },
345 .m1 = { .min = 12, .max = 22 },
346 .m2 = { .min = 5, .max = 9 },
347 .p = { .min = 14, .max = 56 },
348 .p1 = { .min = 2, .max = 8 },
349 .p2 = { .dot_limit = 225000,
350 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 351};
352
273e27ca 353/* LVDS 100mhz refclk limits. */
b91ad0ec 354static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 355 .dot = { .min = 25000, .max = 350000 },
356 .vco = { .min = 1760000, .max = 3510000 },
357 .n = { .min = 1, .max = 2 },
358 .m = { .min = 79, .max = 126 },
359 .m1 = { .min = 12, .max = 22 },
360 .m2 = { .min = 5, .max = 9 },
361 .p = { .min = 28, .max = 112 },
0206e353 362 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 363 .p2 = { .dot_limit = 225000,
364 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 365};
366
367static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 368 .dot = { .min = 25000, .max = 350000 },
369 .vco = { .min = 1760000, .max = 3510000 },
370 .n = { .min = 1, .max = 3 },
371 .m = { .min = 79, .max = 126 },
372 .m1 = { .min = 12, .max = 22 },
373 .m2 = { .min = 5, .max = 9 },
374 .p = { .min = 14, .max = 42 },
0206e353 375 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 376 .p2 = { .dot_limit = 225000,
377 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 378};
379
dc730512 380static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 381 /*
382 * These are the data rate limits (measured in fast clocks)
383 * since those are the strictest limits we have. The fast
384 * clock and actual rate limits are more relaxed, so checking
385 * them would make no difference.
386 */
387 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 388 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 389 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 390 .m1 = { .min = 2, .max = 3 },
391 .m2 = { .min = 11, .max = 156 },
b99ab663 392 .p1 = { .min = 2, .max = 3 },
5fdc9c49 393 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 394};
395
ef9348c8
CML		 396static const intel_limit_t intel_limits_chv = {
397 /*
398 * These are the data rate limits (measured in fast clocks)
399 * since those are the strictest limits we have. The fast
400 * clock and actual rate limits are more relaxed, so checking
401 * them would make no difference.
402 */
403 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 404 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 405 .n = { .min = 1, .max = 1 },
406 .m1 = { .min = 2, .max = 2 },
407 .m2 = { .min = 24 << 22, .max = 175 << 22 },
408 .p1 = { .min = 2, .max = 4 },
409 .p2 = { .p2_slow = 1, .p2_fast = 14 },
410};
411
5ab7b0b7
ID		 412static const intel_limit_t intel_limits_bxt = {
413 /* FIXME: find real dot limits */
414 .dot = { .min = 0, .max = INT_MAX },
415 .vco = { .min = 4800000, .max = 6480000 },
416 .n = { .min = 1, .max = 1 },
417 .m1 = { .min = 2, .max = 2 },
418 /* FIXME: find real m2 limits */
419 .m2 = { .min = 2 << 22, .max = 255 << 22 },
420 .p1 = { .min = 2, .max = 4 },
421 .p2 = { .p2_slow = 1, .p2_fast = 20 },
422};
423
6b4bf1c4
VS		 424static void vlv_clock(int refclk, intel_clock_t *clock)
425{
426 clock->m = clock->m1 * clock->m2;
427 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 428 if (WARN_ON(clock->n == 0 || clock->p == 0))
429 return;
fb03ac01
VS		 430 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
431 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
6b4bf1c4
VS		 432}
433
e0638cdf
PZ		 434/**
435 * Returns whether any output on the specified pipe is of the specified type
436 */
4093561b 437bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 438{
409ee761 439 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 440 struct intel_encoder *encoder;
441
409ee761 442 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 443 if (encoder->type == type)
444 return true;
445
446 return false;
447}
448
d0737e1d
ACO		 449/**
450 * Returns whether any output on the specified pipe will have the specified
451 * type after a staged modeset is complete, i.e., the same as
452 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
453 * encoder->crtc.
454 */
a93e255f
ACO		 455static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
456 int type)
d0737e1d 457{
a93e255f 458 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 459 struct drm_connector *connector;
a93e255f 460 struct drm_connector_state *connector_state;
d0737e1d 461 struct intel_encoder *encoder;
a93e255f
ACO		 462 int i, num_connectors = 0;
463
da3ced29 464 for_each_connector_in_state(state, connector, connector_state, i) {
a93e255f
ACO		 465 if (connector_state->crtc != crtc_state->base.crtc)
466 continue;
467
468 num_connectors++;
d0737e1d 469
a93e255f
ACO		 470 encoder = to_intel_encoder(connector_state->best_encoder);
471 if (encoder->type == type)
d0737e1d 472 return true;
a93e255f
ACO		 473 }
474
475 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 476
477 return false;
478}
479
a93e255f
ACO		 480static const intel_limit_t *
481intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 482{
a93e255f 483 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 484 const intel_limit_t *limit;
b91ad0ec 485
a93e255f 486 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 487 if (intel_is_dual_link_lvds(dev)) {
1b894b59 488 if (refclk == 100000)
b91ad0ec
ZW		 489 limit = &intel_limits_ironlake_dual_lvds_100m;
490 else
491 limit = &intel_limits_ironlake_dual_lvds;
492 } else {
1b894b59 493 if (refclk == 100000)
b91ad0ec
ZW		 494 limit = &intel_limits_ironlake_single_lvds_100m;
495 else
496 limit = &intel_limits_ironlake_single_lvds;
497 }
c6bb3538 498 } else
b91ad0ec 499 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 500
501 return limit;
502}
503
a93e255f
ACO		 504static const intel_limit_t *
505intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 506{
a93e255f 507 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 508 const intel_limit_t *limit;
509
a93e255f 510 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 511 if (intel_is_dual_link_lvds(dev))
e4b36699 512 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 513 else
e4b36699 514 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 515 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
516 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 517 limit = &intel_limits_g4x_hdmi;
a93e255f 518 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 519 limit = &intel_limits_g4x_sdvo;
044c7c41 520 } else /* The option is for other outputs */
e4b36699 521 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 522
523 return limit;
524}
525
a93e255f
ACO		 526static const intel_limit_t *
527intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 528{
a93e255f 529 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 530 const intel_limit_t *limit;
531
5ab7b0b7
ID		 532 if (IS_BROXTON(dev))
533 limit = &intel_limits_bxt;
534 else if (HAS_PCH_SPLIT(dev))
a93e255f 535 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 536 else if (IS_G4X(dev)) {
a93e255f 537 limit = intel_g4x_limit(crtc_state);
f2b115e6 538 } else if (IS_PINEVIEW(dev)) {
a93e255f 539 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 540 limit = &intel_limits_pineview_lvds;
2177832f 541 else
f2b115e6 542 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 543 } else if (IS_CHERRYVIEW(dev)) {
544 limit = &intel_limits_chv;
a0c4da24 545 } else if (IS_VALLEYVIEW(dev)) {
dc730512 546 limit = &intel_limits_vlv;
a6c45cf0 547 } else if (!IS_GEN2(dev)) {
a93e255f 548 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 549 limit = &intel_limits_i9xx_lvds;
550 else
551 limit = &intel_limits_i9xx_sdvo;
79e53945 552 } else {
a93e255f 553 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 554 limit = &intel_limits_i8xx_lvds;
a93e255f 555 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 556 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 557 else
558 limit = &intel_limits_i8xx_dac;
79e53945
JB		 559 }
560 return limit;
561}
562
f2b115e6
AJ		 563/* m1 is reserved as 0 in Pineview, n is a ring counter */
564static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 565{
2177832f
SL		 566 clock->m = clock->m2 + 2;
567 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 568 if (WARN_ON(clock->n == 0 || clock->p == 0))
569 return;
fb03ac01
VS		 570 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
571 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
2177832f
SL		 572}
573
7429e9d4
DV		 574static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
575{
576 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
577}
578
ac58c3f0 579static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 580{
7429e9d4 581 clock->m = i9xx_dpll_compute_m(clock);
79e53945 582 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 583 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
584 return;
fb03ac01
VS		 585 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
586 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
79e53945
JB		 587}
588
ef9348c8
CML		 589static void chv_clock(int refclk, intel_clock_t *clock)
590{
591 clock->m = clock->m1 * clock->m2;
592 clock->p = clock->p1 * clock->p2;
593 if (WARN_ON(clock->n == 0 || clock->p == 0))
594 return;
595 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
596 clock->n << 22);
597 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
598}
599
7c04d1d9 600#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 601/**
602 * Returns whether the given set of divisors are valid for a given refclk with
603 * the given connectors.
604 */
605
1b894b59
CW		 606static bool intel_PLL_is_valid(struct drm_device *dev,
607 const intel_limit_t *limit,
608 const intel_clock_t *clock)
79e53945 609{
f01b7962
VS		 610 if (clock->n < limit->n.min || limit->n.max < clock->n)
611 INTELPllInvalid("n out of range\n");
79e53945 612 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 613 INTELPllInvalid("p1 out of range\n");
79e53945 614 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 615 INTELPllInvalid("m2 out of range\n");
79e53945 616 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 617 INTELPllInvalid("m1 out of range\n");
f01b7962 618
5ab7b0b7 619 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
f01b7962
VS		 620 if (clock->m1 <= clock->m2)
621 INTELPllInvalid("m1 <= m2\n");
622
5ab7b0b7 623 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
f01b7962
VS		 624 if (clock->p < limit->p.min || limit->p.max < clock->p)
625 INTELPllInvalid("p out of range\n");
626 if (clock->m < limit->m.min || limit->m.max < clock->m)
627 INTELPllInvalid("m out of range\n");
628 }
629
79e53945 630 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 631 INTELPllInvalid("vco out of range\n");
79e53945
JB		 632 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
633 * connector, etc., rather than just a single range.
634 */
635 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 636 INTELPllInvalid("dot out of range\n");
79e53945
JB		 637
638 return true;
639}
640
d4906093 641static bool
a93e255f
ACO		 642i9xx_find_best_dpll(const intel_limit_t *limit,
643 struct intel_crtc_state *crtc_state,
cec2f356
SP		 644 int target, int refclk, intel_clock_t *match_clock,
645 intel_clock_t *best_clock)
79e53945 646{
a93e255f 647 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 648 struct drm_device *dev = crtc->base.dev;
79e53945 649 intel_clock_t clock;
79e53945
JB		 650 int err = target;
651
a93e255f 652 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 653 /*
a210b028
DV		 654 * For LVDS just rely on its current settings for dual-channel.
655 * We haven't figured out how to reliably set up different
656 * single/dual channel state, if we even can.
79e53945 657 */
1974cad0 658 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 659 clock.p2 = limit->p2.p2_fast;
660 else
661 clock.p2 = limit->p2.p2_slow;
662 } else {
663 if (target < limit->p2.dot_limit)
664 clock.p2 = limit->p2.p2_slow;
665 else
666 clock.p2 = limit->p2.p2_fast;
667 }
668
0206e353 669 memset(best_clock, 0, sizeof(*best_clock));
79e53945 670
42158660
ZY		 671 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
672 clock.m1++) {
673 for (clock.m2 = limit->m2.min;
674 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 675 if (clock.m2 >= clock.m1)
42158660
ZY		 676 break;
677 for (clock.n = limit->n.min;
678 clock.n <= limit->n.max; clock.n++) {
679 for (clock.p1 = limit->p1.min;
680 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 681 int this_err;
682
ac58c3f0
DV		 683 i9xx_clock(refclk, &clock);
684 if (!intel_PLL_is_valid(dev, limit,
685 &clock))
686 continue;
687 if (match_clock &&
688 clock.p != match_clock->p)
689 continue;
690
691 this_err = abs(clock.dot - target);
692 if (this_err < err) {
693 *best_clock = clock;
694 err = this_err;
695 }
696 }
697 }
698 }
699 }
700
701 return (err != target);
702}
703
704static bool
a93e255f
ACO		 705pnv_find_best_dpll(const intel_limit_t *limit,
706 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 707 int target, int refclk, intel_clock_t *match_clock,
708 intel_clock_t *best_clock)
79e53945 709{
a93e255f 710 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 711 struct drm_device *dev = crtc->base.dev;
79e53945 712 intel_clock_t clock;
79e53945
JB		 713 int err = target;
714
a93e255f 715 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 716 /*
a210b028
DV		 717 * For LVDS just rely on its current settings for dual-channel.
718 * We haven't figured out how to reliably set up different
719 * single/dual channel state, if we even can.
79e53945 720 */
1974cad0 721 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 722 clock.p2 = limit->p2.p2_fast;
723 else
724 clock.p2 = limit->p2.p2_slow;
725 } else {
726 if (target < limit->p2.dot_limit)
727 clock.p2 = limit->p2.p2_slow;
728 else
729 clock.p2 = limit->p2.p2_fast;
730 }
731
0206e353 732 memset(best_clock, 0, sizeof(*best_clock));
79e53945 733
42158660
ZY		 734 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
735 clock.m1++) {
736 for (clock.m2 = limit->m2.min;
737 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 738 for (clock.n = limit->n.min;
739 clock.n <= limit->n.max; clock.n++) {
740 for (clock.p1 = limit->p1.min;
741 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 742 int this_err;
743
ac58c3f0 744 pineview_clock(refclk, &clock);
1b894b59
CW		 745 if (!intel_PLL_is_valid(dev, limit,
746 &clock))
79e53945 747 continue;
cec2f356
SP		 748 if (match_clock &&
749 clock.p != match_clock->p)
750 continue;
79e53945
JB		 751
752 this_err = abs(clock.dot - target);
753 if (this_err < err) {
754 *best_clock = clock;
755 err = this_err;
756 }
757 }
758 }
759 }
760 }
761
762 return (err != target);
763}
764
d4906093 765static bool
a93e255f
ACO		 766g4x_find_best_dpll(const intel_limit_t *limit,
767 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 768 int target, int refclk, intel_clock_t *match_clock,
769 intel_clock_t *best_clock)
d4906093 770{
a93e255f 771 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 772 struct drm_device *dev = crtc->base.dev;
d4906093
ML		 773 intel_clock_t clock;
774 int max_n;
775 bool found;
6ba770dc
AJ		 776 /* approximately equals target * 0.00585 */
777 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 778 found = false;
779
a93e255f 780 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 781 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 782 clock.p2 = limit->p2.p2_fast;
783 else
784 clock.p2 = limit->p2.p2_slow;
785 } else {
786 if (target < limit->p2.dot_limit)
787 clock.p2 = limit->p2.p2_slow;
788 else
789 clock.p2 = limit->p2.p2_fast;
790 }
791
792 memset(best_clock, 0, sizeof(*best_clock));
793 max_n = limit->n.max;
f77f13e2 794 /* based on hardware requirement, prefer smaller n to precision */
d4906093 795 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 796 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 797 for (clock.m1 = limit->m1.max;
798 clock.m1 >= limit->m1.min; clock.m1--) {
799 for (clock.m2 = limit->m2.max;
800 clock.m2 >= limit->m2.min; clock.m2--) {
801 for (clock.p1 = limit->p1.max;
802 clock.p1 >= limit->p1.min; clock.p1--) {
803 int this_err;
804
ac58c3f0 805 i9xx_clock(refclk, &clock);
1b894b59
CW		 806 if (!intel_PLL_is_valid(dev, limit,
807 &clock))
d4906093 808 continue;
1b894b59
CW		 809
810 this_err = abs(clock.dot - target);
d4906093
ML		 811 if (this_err < err_most) {
812 *best_clock = clock;
813 err_most = this_err;
814 max_n = clock.n;
815 found = true;
816 }
817 }
818 }
819 }
820 }
2c07245f
ZW		 821 return found;
822}
823
d5dd62bd
ID		 824/*
825 * Check if the calculated PLL configuration is more optimal compared to the
826 * best configuration and error found so far. Return the calculated error.
827 */
828static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
829 const intel_clock_t *calculated_clock,
830 const intel_clock_t *best_clock,
831 unsigned int best_error_ppm,
832 unsigned int *error_ppm)
833{
9ca3ba01
ID		 834 /*
835 * For CHV ignore the error and consider only the P value.
836 * Prefer a bigger P value based on HW requirements.
837 */
838 if (IS_CHERRYVIEW(dev)) {
839 *error_ppm = 0;
840
841 return calculated_clock->p > best_clock->p;
842 }
843
24be4e46
ID		 844 if (WARN_ON_ONCE(!target_freq))
845 return false;
846
d5dd62bd
ID		 847 *error_ppm = div_u64(1000000ULL *
848 abs(target_freq - calculated_clock->dot),
849 target_freq);
850 /*
851 * Prefer a better P value over a better (smaller) error if the error
852 * is small. Ensure this preference for future configurations too by
853 * setting the error to 0.
854 */
855 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
856 *error_ppm = 0;
857
858 return true;
859 }
860
861 return *error_ppm + 10 < best_error_ppm;
862}
863
a0c4da24 864static bool
a93e255f
ACO		 865vlv_find_best_dpll(const intel_limit_t *limit,
866 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 867 int target, int refclk, intel_clock_t *match_clock,
868 intel_clock_t *best_clock)
a0c4da24 869{
a93e255f 870 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 871 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 872 intel_clock_t clock;
69e4f900 873 unsigned int bestppm = 1000000;
27e639bf
VS		 874 /* min update 19.2 MHz */
875 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 876 bool found = false;
a0c4da24 877
6b4bf1c4
VS		 878 target *= 5; /* fast clock */
879
880 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 881
882 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 883 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 884 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 885 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 886 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 887 clock.p = clock.p1 * clock.p2;
a0c4da24 888 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 889 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 890 unsigned int ppm;
69e4f900 891
6b4bf1c4
VS		 892 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
893 refclk * clock.m1);
894
895 vlv_clock(refclk, &clock);
43b0ac53 896
f01b7962
VS		 897 if (!intel_PLL_is_valid(dev, limit,
898 &clock))
43b0ac53
VS		 899 continue;
900
d5dd62bd
ID		 901 if (!vlv_PLL_is_optimal(dev, target,
902 &clock,
903 best_clock,
904 bestppm, &ppm))
905 continue;
6b4bf1c4 906
d5dd62bd
ID		 907 *best_clock = clock;
908 bestppm = ppm;
909 found = true;
a0c4da24
JB		 910 }
911 }
912 }
913 }
a0c4da24 914
49e497ef 915 return found;
a0c4da24 916}
a4fc5ed6 917
ef9348c8 918static bool
a93e255f
ACO		 919chv_find_best_dpll(const intel_limit_t *limit,
920 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 921 int target, int refclk, intel_clock_t *match_clock,
922 intel_clock_t *best_clock)
923{
a93e255f 924 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 925 struct drm_device *dev = crtc->base.dev;
9ca3ba01 926 unsigned int best_error_ppm;
ef9348c8
CML		 927 intel_clock_t clock;
928 uint64_t m2;
929 int found = false;
930
931 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 932 best_error_ppm = 1000000;
ef9348c8
CML		 933
934 /*
935 * Based on hardware doc, the n always set to 1, and m1 always
936 * set to 2. If requires to support 200Mhz refclk, we need to
937 * revisit this because n may not 1 anymore.
938 */
939 clock.n = 1, clock.m1 = 2;
940 target *= 5; /* fast clock */
941
942 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
943 for (clock.p2 = limit->p2.p2_fast;
944 clock.p2 >= limit->p2.p2_slow;
945 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 946 unsigned int error_ppm;
ef9348c8
CML		 947
948 clock.p = clock.p1 * clock.p2;
949
950 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
951 clock.n) << 22, refclk * clock.m1);
952
953 if (m2 > INT_MAX/clock.m1)
954 continue;
955
956 clock.m2 = m2;
957
958 chv_clock(refclk, &clock);
959
960 if (!intel_PLL_is_valid(dev, limit, &clock))
961 continue;
962
9ca3ba01
ID		 963 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
964 best_error_ppm, &error_ppm))
965 continue;
966
967 *best_clock = clock;
968 best_error_ppm = error_ppm;
969 found = true;
ef9348c8
CML		 970 }
971 }
972
973 return found;
974}
975
5ab7b0b7
ID		 976bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
977 intel_clock_t *best_clock)
978{
979 int refclk = i9xx_get_refclk(crtc_state, 0);
980
981 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
982 target_clock, refclk, NULL, best_clock);
983}
984
20ddf665
VS		 985bool intel_crtc_active(struct drm_crtc *crtc)
986{
987 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
988
989 /* Be paranoid as we can arrive here with only partial
990 * state retrieved from the hardware during setup.
991 *
241bfc38 992 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 993 * as Haswell has gained clock readout/fastboot support.
994 *
66e514c1 995 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 996 * properly reconstruct framebuffers.
c3d1f436
MR		 997 *
998 * FIXME: The intel_crtc->active here should be switched to
999 * crtc->state->active once we have proper CRTC states wired up
1000 * for atomic.
20ddf665 1001 */
c3d1f436 1002 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 1003 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 1004}
1005
a5c961d1
PZ		 1006enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1007 enum pipe pipe)
1008{
1009 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011
6e3c9717 1012 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 1013}
1014
fbf49ea2
VS		 1015static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1016{
1017 struct drm_i915_private *dev_priv = dev->dev_private;
1018 u32 reg = PIPEDSL(pipe);
1019 u32 line1, line2;
1020 u32 line_mask;
1021
1022 if (IS_GEN2(dev))
1023 line_mask = DSL_LINEMASK_GEN2;
1024 else
1025 line_mask = DSL_LINEMASK_GEN3;
1026
1027 line1 = I915_READ(reg) & line_mask;
1028 mdelay(5);
1029 line2 = I915_READ(reg) & line_mask;
1030
1031 return line1 == line2;
1032}
1033
ab7ad7f6
KP		 1034/*
1035 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1036 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1037 *
1038 * After disabling a pipe, we can't wait for vblank in the usual way,
1039 * spinning on the vblank interrupt status bit, since we won't actually
1040 * see an interrupt when the pipe is disabled.
1041 *
ab7ad7f6
KP		 1042 * On Gen4 and above:
1043 * wait for the pipe register state bit to turn off
1044 *
1045 * Otherwise:
1046 * wait for the display line value to settle (it usually
1047 * ends up stopping at the start of the next frame).
58e10eb9 1048 *
9d0498a2 1049 */
575f7ab7 1050static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1051{
575f7ab7 1052 struct drm_device *dev = crtc->base.dev;
9d0498a2 1053 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1054 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1055 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1056
1057 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1058 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1059
1060 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1061 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1062 100))
284637d9 1063 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1064 } else {
ab7ad7f6 1065 /* Wait for the display line to settle */
fbf49ea2 1066 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1067 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1068 }
79e53945
JB		 1069}
1070
b0ea7d37
DL		 1071/*
1072 * ibx_digital_port_connected - is the specified port connected?
1073 * @dev_priv: i915 private structure
1074 * @port: the port to test
1075 *
1076 * Returns true if @port is connected, false otherwise.
1077 */
1078bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1079 struct intel_digital_port *port)
1080{
1081 u32 bit;
1082
c36346e3 1083 if (HAS_PCH_IBX(dev_priv->dev)) {
eba905b2 1084 switch (port->port) {
c36346e3
DL		 1085 case PORT_B:
1086 bit = SDE_PORTB_HOTPLUG;
1087 break;
1088 case PORT_C:
1089 bit = SDE_PORTC_HOTPLUG;
1090 break;
1091 case PORT_D:
1092 bit = SDE_PORTD_HOTPLUG;
1093 break;
1094 default:
1095 return true;
1096 }
1097 } else {
eba905b2 1098 switch (port->port) {
c36346e3
DL		 1099 case PORT_B:
1100 bit = SDE_PORTB_HOTPLUG_CPT;
1101 break;
1102 case PORT_C:
1103 bit = SDE_PORTC_HOTPLUG_CPT;
1104 break;
1105 case PORT_D:
1106 bit = SDE_PORTD_HOTPLUG_CPT;
1107 break;
1108 default:
1109 return true;
1110 }
b0ea7d37
DL		 1111 }
1112
1113 return I915_READ(SDEISR) & bit;
1114}
1115
b24e7179
JB		 1116static const char *state_string(bool enabled)
1117{
1118 return enabled ? "on" : "off";
1119}
1120
1121/* Only for pre-ILK configs */
55607e8a
DV		 1122void assert_pll(struct drm_i915_private *dev_priv,
1123 enum pipe pipe, bool state)
b24e7179
JB		 1124{
1125 int reg;
1126 u32 val;
1127 bool cur_state;
1128
1129 reg = DPLL(pipe);
1130 val = I915_READ(reg);
1131 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1132 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1133 "PLL state assertion failure (expected %s, current %s)\n",
1134 state_string(state), state_string(cur_state));
1135}
b24e7179 1136
23538ef1
JN		 1137/* XXX: the dsi pll is shared between MIPI DSI ports */
1138static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1139{
1140 u32 val;
1141 bool cur_state;
1142
a580516d 1143 mutex_lock(&dev_priv->sb_lock);
23538ef1 1144 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
a580516d 1145 mutex_unlock(&dev_priv->sb_lock);
23538ef1
JN		 1146
1147 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1148 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1149 "DSI PLL state assertion failure (expected %s, current %s)\n",
1150 state_string(state), state_string(cur_state));
1151}
1152#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1153#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1154
55607e8a 1155struct intel_shared_dpll *
e2b78267
DV		 1156intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1157{
1158 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1159
6e3c9717 1160 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1161 return NULL;
1162
6e3c9717 1163 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1164}
1165
040484af 1166/* For ILK+ */
55607e8a
DV		 1167void assert_shared_dpll(struct drm_i915_private *dev_priv,
1168 struct intel_shared_dpll *pll,
1169 bool state)
040484af 1170{
040484af 1171 bool cur_state;
5358901f 1172 struct intel_dpll_hw_state hw_state;
040484af 1173
92b27b08 1174 if (WARN (!pll,
46edb027 1175 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1176 return;
ee7b9f93 1177
5358901f 1178 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1179 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1180 "%s assertion failure (expected %s, current %s)\n",
1181 pll->name, state_string(state), state_string(cur_state));
040484af 1182}
040484af
JB		 1183
1184static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1185 enum pipe pipe, bool state)
1186{
1187 int reg;
1188 u32 val;
1189 bool cur_state;
ad80a810
PZ		 1190 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1191 pipe);
040484af 1192
affa9354
PZ		 1193 if (HAS_DDI(dev_priv->dev)) {
1194 /* DDI does not have a specific FDI_TX register */
ad80a810 1195 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1196 val = I915_READ(reg);
ad80a810 1197 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1198 } else {
1199 reg = FDI_TX_CTL(pipe);
1200 val = I915_READ(reg);
1201 cur_state = !!(val & FDI_TX_ENABLE);
1202 }
e2c719b7 1203 I915_STATE_WARN(cur_state != state,
040484af
JB		 1204 "FDI TX state assertion failure (expected %s, current %s)\n",
1205 state_string(state), state_string(cur_state));
1206}
1207#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1208#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1209
1210static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1211 enum pipe pipe, bool state)
1212{
1213 int reg;
1214 u32 val;
1215 bool cur_state;
1216
d63fa0dc
PZ		 1217 reg = FDI_RX_CTL(pipe);
1218 val = I915_READ(reg);
1219 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1220 I915_STATE_WARN(cur_state != state,
040484af
JB		 1221 "FDI RX state assertion failure (expected %s, current %s)\n",
1222 state_string(state), state_string(cur_state));
1223}
1224#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1225#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1226
1227static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1228 enum pipe pipe)
1229{
1230 int reg;
1231 u32 val;
1232
1233 /* ILK FDI PLL is always enabled */
3d13ef2e 1234 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1235 return;
1236
bf507ef7 1237 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1238 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1239 return;
1240
040484af
JB		 1241 reg = FDI_TX_CTL(pipe);
1242 val = I915_READ(reg);
e2c719b7 1243 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1244}
1245
55607e8a
DV		 1246void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1247 enum pipe pipe, bool state)
040484af
JB		 1248{
1249 int reg;
1250 u32 val;
55607e8a 1251 bool cur_state;
040484af
JB		 1252
1253 reg = FDI_RX_CTL(pipe);
1254 val = I915_READ(reg);
55607e8a 1255 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1256 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1257 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1258 state_string(state), state_string(cur_state));
040484af
JB		 1259}
1260
b680c37a
DV		 1261void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1262 enum pipe pipe)
ea0760cf 1263{
bedd4dba
JN		 1264 struct drm_device *dev = dev_priv->dev;
1265 int pp_reg;
ea0760cf
JB		 1266 u32 val;
1267 enum pipe panel_pipe = PIPE_A;
0de3b485 1268 bool locked = true;
ea0760cf 1269
bedd4dba
JN		 1270 if (WARN_ON(HAS_DDI(dev)))
1271 return;
1272
1273 if (HAS_PCH_SPLIT(dev)) {
1274 u32 port_sel;
1275
ea0760cf 1276 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1277 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1278
1279 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1280 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1281 panel_pipe = PIPE_B;
1282 /* XXX: else fix for eDP */
1283 } else if (IS_VALLEYVIEW(dev)) {
1284 /* presumably write lock depends on pipe, not port select */
1285 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1286 panel_pipe = pipe;
ea0760cf
JB		 1287 } else {
1288 pp_reg = PP_CONTROL;
bedd4dba
JN		 1289 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1290 panel_pipe = PIPE_B;
ea0760cf
JB		 1291 }
1292
1293 val = I915_READ(pp_reg);
1294 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1295 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1296 locked = false;
1297
e2c719b7 1298 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1299 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1300 pipe_name(pipe));
ea0760cf
JB		 1301}
1302
93ce0ba6
JN		 1303static void assert_cursor(struct drm_i915_private *dev_priv,
1304 enum pipe pipe, bool state)
1305{
1306 struct drm_device *dev = dev_priv->dev;
1307 bool cur_state;
1308
d9d82081 1309 if (IS_845G(dev) || IS_I865G(dev))
93ce0ba6 1310 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
d9d82081 1311 else
5efb3e28 1312 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1313
e2c719b7 1314 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1315 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1316 pipe_name(pipe), state_string(state), state_string(cur_state));
1317}
1318#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1319#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1320
b840d907
JB		 1321void assert_pipe(struct drm_i915_private *dev_priv,
1322 enum pipe pipe, bool state)
b24e7179
JB		 1323{
1324 int reg;
1325 u32 val;
63d7bbe9 1326 bool cur_state;
702e7a56
PZ		 1327 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1328 pipe);
b24e7179 1329
b6b5d049
VS		 1330 /* if we need the pipe quirk it must be always on */
1331 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1332 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1333 state = true;
1334
f458ebbc 1335 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1336 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1337 cur_state = false;
1338 } else {
1339 reg = PIPECONF(cpu_transcoder);
1340 val = I915_READ(reg);
1341 cur_state = !!(val & PIPECONF_ENABLE);
1342 }
1343
e2c719b7 1344 I915_STATE_WARN(cur_state != state,
63d7bbe9 1345 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1346 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1347}
1348
931872fc
CW		 1349static void assert_plane(struct drm_i915_private *dev_priv,
1350 enum plane plane, bool state)
b24e7179
JB		 1351{
1352 int reg;
1353 u32 val;
931872fc 1354 bool cur_state;
b24e7179
JB		 1355
1356 reg = DSPCNTR(plane);
1357 val = I915_READ(reg);
931872fc 1358 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1359 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1360 "plane %c assertion failure (expected %s, current %s)\n",
1361 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1362}
1363
931872fc
CW		 1364#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1365#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1366
b24e7179
JB		 1367static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1368 enum pipe pipe)
1369{
653e1026 1370 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1371 int reg, i;
1372 u32 val;
1373 int cur_pipe;
1374
653e1026
VS		 1375 /* Primary planes are fixed to pipes on gen4+ */
1376 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1377 reg = DSPCNTR(pipe);
1378 val = I915_READ(reg);
e2c719b7 1379 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1380 "plane %c assertion failure, should be disabled but not\n",
1381 plane_name(pipe));
19ec1358 1382 return;
28c05794 1383 }
19ec1358 1384
b24e7179 1385 /* Need to check both planes against the pipe */
055e393f 1386 for_each_pipe(dev_priv, i) {
b24e7179
JB		 1387 reg = DSPCNTR(i);
1388 val = I915_READ(reg);
1389 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1390 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1391 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1392 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1393 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1394 }
1395}
1396
19332d7a
JB		 1397static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1398 enum pipe pipe)
1399{
20674eef 1400 struct drm_device *dev = dev_priv->dev;
1fe47785 1401 int reg, sprite;
19332d7a
JB		 1402 u32 val;
1403
7feb8b88 1404 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1405 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1406 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1407 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1408 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1409 sprite, pipe_name(pipe));
1410 }
1411 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1412 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1413 reg = SPCNTR(pipe, sprite);
20674eef 1414 val = I915_READ(reg);
e2c719b7 1415 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1416 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1417 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1418 }
1419 } else if (INTEL_INFO(dev)->gen >= 7) {
1420 reg = SPRCTL(pipe);
19332d7a 1421 val = I915_READ(reg);
e2c719b7 1422 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1423 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1424 plane_name(pipe), pipe_name(pipe));
1425 } else if (INTEL_INFO(dev)->gen >= 5) {
1426 reg = DVSCNTR(pipe);
19332d7a 1427 val = I915_READ(reg);
e2c719b7 1428 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1429 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1430 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1431 }
1432}
1433
08c71e5e
VS		 1434static void assert_vblank_disabled(struct drm_crtc *crtc)
1435{
e2c719b7 1436 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1437 drm_crtc_vblank_put(crtc);
1438}
1439
89eff4be 1440static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1441{
1442 u32 val;
1443 bool enabled;
1444
e2c719b7 1445 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1446
92f2584a
JB		 1447 val = I915_READ(PCH_DREF_CONTROL);
1448 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1449 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1450 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1451}
1452
ab9412ba
DV		 1453static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1454 enum pipe pipe)
92f2584a
JB		 1455{
1456 int reg;
1457 u32 val;
1458 bool enabled;
1459
ab9412ba 1460 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1461 val = I915_READ(reg);
1462 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1463 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1464 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1465 pipe_name(pipe));
92f2584a
JB		 1466}
1467
4e634389
KP		 1468static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1469 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1470{
1471 if ((val & DP_PORT_EN) == 0)
1472 return false;
1473
1474 if (HAS_PCH_CPT(dev_priv->dev)) {
1475 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1476 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1477 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1478 return false;
44f37d1f
CML		 1479 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1480 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1481 return false;
f0575e92
KP		 1482 } else {
1483 if ((val & DP_PIPE_MASK) != (pipe << 30))
1484 return false;
1485 }
1486 return true;
1487}
1488
1519b995
KP		 1489static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1490 enum pipe pipe, u32 val)
1491{
dc0fa718 1492 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1493 return false;
1494
1495 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1496 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1497 return false;
44f37d1f
CML		 1498 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1499 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1500 return false;
1519b995 1501 } else {
dc0fa718 1502 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1503 return false;
1504 }
1505 return true;
1506}
1507
1508static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1509 enum pipe pipe, u32 val)
1510{
1511 if ((val & LVDS_PORT_EN) == 0)
1512 return false;
1513
1514 if (HAS_PCH_CPT(dev_priv->dev)) {
1515 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1516 return false;
1517 } else {
1518 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1519 return false;
1520 }
1521 return true;
1522}
1523
1524static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1525 enum pipe pipe, u32 val)
1526{
1527 if ((val & ADPA_DAC_ENABLE) == 0)
1528 return false;
1529 if (HAS_PCH_CPT(dev_priv->dev)) {
1530 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1531 return false;
1532 } else {
1533 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1534 return false;
1535 }
1536 return true;
1537}
1538
291906f1 1539static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1540 enum pipe pipe, int reg, u32 port_sel)
291906f1 1541{
47a05eca 1542 u32 val = I915_READ(reg);
e2c719b7 1543 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1544 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1545 reg, pipe_name(pipe));
de9a35ab 1546
e2c719b7 1547 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1548 && (val & DP_PIPEB_SELECT),
de9a35ab 1549 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1550}
1551
1552static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1553 enum pipe pipe, int reg)
1554{
47a05eca 1555 u32 val = I915_READ(reg);
e2c719b7 1556 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1557 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1558 reg, pipe_name(pipe));
de9a35ab 1559
e2c719b7 1560 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1561 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1562 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1563}
1564
1565static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1566 enum pipe pipe)
1567{
1568 int reg;
1569 u32 val;
291906f1 1570
f0575e92
KP		 1571 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1572 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1573 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1574
1575 reg = PCH_ADPA;
1576 val = I915_READ(reg);
e2c719b7 1577 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1578 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1579 pipe_name(pipe));
291906f1
JB		 1580
1581 reg = PCH_LVDS;
1582 val = I915_READ(reg);
e2c719b7 1583 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1584 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1585 pipe_name(pipe));
291906f1 1586
e2debe91
PZ		 1587 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1588 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1589 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1590}
1591
40e9cf64
JB		 1592static void intel_init_dpio(struct drm_device *dev)
1593{
1594 struct drm_i915_private *dev_priv = dev->dev_private;
1595
1596 if (!IS_VALLEYVIEW(dev))
1597 return;
1598
a09caddd
CML		 1599 /*
1600 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1601 * CHV x1 PHY (DP/HDMI D)
1602 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1603 */
1604 if (IS_CHERRYVIEW(dev)) {
1605 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1606 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1607 } else {
1608 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1609 }
5382f5f3
JB		 1610}
1611
d288f65f 1612static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1613 const struct intel_crtc_state *pipe_config)
87442f73 1614{
426115cf
DV		 1615 struct drm_device *dev = crtc->base.dev;
1616 struct drm_i915_private *dev_priv = dev->dev_private;
1617 int reg = DPLL(crtc->pipe);
d288f65f 1618 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1619
426115cf 1620 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1621
1622 /* No really, not for ILK+ */
1623 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1624
1625 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1626 if (IS_MOBILE(dev_priv->dev))
426115cf 1627 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1628
426115cf
DV		 1629 I915_WRITE(reg, dpll);
1630 POSTING_READ(reg);
1631 udelay(150);
1632
1633 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1634 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1635
d288f65f 1636 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1637 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1638
1639 /* We do this three times for luck */
426115cf 1640 I915_WRITE(reg, dpll);
87442f73
DV		 1641 POSTING_READ(reg);
1642 udelay(150); /* wait for warmup */
426115cf 1643 I915_WRITE(reg, dpll);
87442f73
DV		 1644 POSTING_READ(reg);
1645 udelay(150); /* wait for warmup */
426115cf 1646 I915_WRITE(reg, dpll);
87442f73
DV		 1647 POSTING_READ(reg);
1648 udelay(150); /* wait for warmup */
1649}
1650
d288f65f 1651static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1652 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1653{
1654 struct drm_device *dev = crtc->base.dev;
1655 struct drm_i915_private *dev_priv = dev->dev_private;
1656 int pipe = crtc->pipe;
1657 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1658 u32 tmp;
1659
1660 assert_pipe_disabled(dev_priv, crtc->pipe);
1661
1662 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1663
a580516d 1664 mutex_lock(&dev_priv->sb_lock);
9d556c99
CML		 1665
1666 /* Enable back the 10bit clock to display controller */
1667 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1668 tmp |= DPIO_DCLKP_EN;
1669 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1670
54433e91
VS		 1671 mutex_unlock(&dev_priv->sb_lock);
1672
9d556c99
CML		 1673 /*
1674 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1675 */
1676 udelay(1);
1677
1678 /* Enable PLL */
d288f65f 1679 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1680
1681 /* Check PLL is locked */
a11b0703 1682 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1683 DRM_ERROR("PLL %d failed to lock\n", pipe);
1684
a11b0703 1685 /* not sure when this should be written */
d288f65f 1686 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703 1687 POSTING_READ(DPLL_MD(pipe));
9d556c99
CML		 1688}
1689
1c4e0274
VS		 1690static int intel_num_dvo_pipes(struct drm_device *dev)
1691{
1692 struct intel_crtc *crtc;
1693 int count = 0;
1694
1695 for_each_intel_crtc(dev, crtc)
1696 count += crtc->active &&
409ee761 1697 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1698
1699 return count;
1700}
1701
66e3d5c0 1702static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1703{
66e3d5c0
DV		 1704 struct drm_device *dev = crtc->base.dev;
1705 struct drm_i915_private *dev_priv = dev->dev_private;
1706 int reg = DPLL(crtc->pipe);
6e3c9717 1707 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1708
66e3d5c0 1709 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1710
63d7bbe9 1711 /* No really, not for ILK+ */
3d13ef2e 1712 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1713
1714 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1715 if (IS_MOBILE(dev) && !IS_I830(dev))
1716 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1717
1c4e0274
VS		 1718 /* Enable DVO 2x clock on both PLLs if necessary */
1719 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1720 /*
1721 * It appears to be important that we don't enable this
1722 * for the current pipe before otherwise configuring the
1723 * PLL. No idea how this should be handled if multiple
1724 * DVO outputs are enabled simultaneosly.
1725 */
1726 dpll |= DPLL_DVO_2X_MODE;
1727 I915_WRITE(DPLL(!crtc->pipe),
1728 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1729 }
66e3d5c0
DV		 1730
1731 /* Wait for the clocks to stabilize. */
1732 POSTING_READ(reg);
1733 udelay(150);
1734
1735 if (INTEL_INFO(dev)->gen >= 4) {
1736 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1737 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1738 } else {
1739 /* The pixel multiplier can only be updated once the
1740 * DPLL is enabled and the clocks are stable.
1741 *
1742 * So write it again.
1743 */
1744 I915_WRITE(reg, dpll);
1745 }
63d7bbe9
JB		 1746
1747 /* We do this three times for luck */
66e3d5c0 1748 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1749 POSTING_READ(reg);
1750 udelay(150); /* wait for warmup */
66e3d5c0 1751 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1752 POSTING_READ(reg);
1753 udelay(150); /* wait for warmup */
66e3d5c0 1754 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1755 POSTING_READ(reg);
1756 udelay(150); /* wait for warmup */
1757}
1758
1759/**
50b44a44 1760 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1761 * @dev_priv: i915 private structure
1762 * @pipe: pipe PLL to disable
1763 *
1764 * Disable the PLL for @pipe, making sure the pipe is off first.
1765 *
1766 * Note! This is for pre-ILK only.
1767 */
1c4e0274 1768static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1769{
1c4e0274
VS		 1770 struct drm_device *dev = crtc->base.dev;
1771 struct drm_i915_private *dev_priv = dev->dev_private;
1772 enum pipe pipe = crtc->pipe;
1773
1774 /* Disable DVO 2x clock on both PLLs if necessary */
1775 if (IS_I830(dev) &&
409ee761 1776 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1c4e0274
VS		 1777 intel_num_dvo_pipes(dev) == 1) {
1778 I915_WRITE(DPLL(PIPE_B),
1779 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1780 I915_WRITE(DPLL(PIPE_A),
1781 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1782 }
1783
b6b5d049
VS		 1784 /* Don't disable pipe or pipe PLLs if needed */
1785 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1786 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1787 return;
1788
1789 /* Make sure the pipe isn't still relying on us */
1790 assert_pipe_disabled(dev_priv, pipe);
1791
50b44a44
DV		 1792 I915_WRITE(DPLL(pipe), 0);
1793 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1794}
1795
f6071166
JB		 1796static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1797{
1798 u32 val = 0;
1799
1800 /* Make sure the pipe isn't still relying on us */
1801 assert_pipe_disabled(dev_priv, pipe);
1802
e5cbfbfb
ID		 1803 /*
1804 * Leave integrated clock source and reference clock enabled for pipe B.
1805 * The latter is needed for VGA hotplug / manual detection.
1806 */
f6071166 1807 if (pipe == PIPE_B)
e5cbfbfb 1808 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
f6071166
JB		 1809 I915_WRITE(DPLL(pipe), val);
1810 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1811
1812}
1813
1814static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1815{
d752048d 1816 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1817 u32 val;
1818
a11b0703
VS		 1819 /* Make sure the pipe isn't still relying on us */
1820 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1821
a11b0703 1822 /* Set PLL en = 0 */
d17ec4ce 1823 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
a11b0703
VS		 1824 if (pipe != PIPE_A)
1825 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1826 I915_WRITE(DPLL(pipe), val);
1827 POSTING_READ(DPLL(pipe));
d752048d 1828
a580516d 1829 mutex_lock(&dev_priv->sb_lock);
d752048d
VS		 1830
1831 /* Disable 10bit clock to display controller */
1832 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1833 val &= ~DPIO_DCLKP_EN;
1834 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1835
61407f6d
VS		 1836 /* disable left/right clock distribution */
1837 if (pipe != PIPE_B) {
1838 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1839 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1840 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1841 } else {
1842 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1843 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1844 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1845 }
1846
a580516d 1847 mutex_unlock(&dev_priv->sb_lock);
f6071166
JB		 1848}
1849
e4607fcf 1850void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
9b6de0a1
VS		 1851 struct intel_digital_port *dport,
1852 unsigned int expected_mask)
89b667f8
JB		 1853{
1854 u32 port_mask;
00fc31b7 1855 int dpll_reg;
89b667f8 1856
e4607fcf
CML		 1857 switch (dport->port) {
1858 case PORT_B:
89b667f8 1859 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1860 dpll_reg = DPLL(0);
e4607fcf
CML		 1861 break;
1862 case PORT_C:
89b667f8 1863 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7 1864 dpll_reg = DPLL(0);
9b6de0a1 1865 expected_mask <<= 4;
00fc31b7
CML		 1866 break;
1867 case PORT_D:
1868 port_mask = DPLL_PORTD_READY_MASK;
1869 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1870 break;
1871 default:
1872 BUG();
1873 }
89b667f8 1874
9b6de0a1
VS		 1875 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1876 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1877 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
89b667f8
JB		 1878}
1879
b14b1055
DV		 1880static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1881{
1882 struct drm_device *dev = crtc->base.dev;
1883 struct drm_i915_private *dev_priv = dev->dev_private;
1884 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1885
be19f0ff
CW		 1886 if (WARN_ON(pll == NULL))
1887 return;
1888
3e369b76 1889 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1890 if (pll->active == 0) {
1891 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1892 WARN_ON(pll->on);
1893 assert_shared_dpll_disabled(dev_priv, pll);
1894
1895 pll->mode_set(dev_priv, pll);
1896 }
1897}
1898
92f2584a 1899/**
85b3894f 1900 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1901 * @dev_priv: i915 private structure
1902 * @pipe: pipe PLL to enable
1903 *
1904 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1905 * drives the transcoder clock.
1906 */
85b3894f 1907static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1908{
3d13ef2e
DL		 1909 struct drm_device *dev = crtc->base.dev;
1910 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1911 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1912
87a875bb 1913 if (WARN_ON(pll == NULL))
48da64a8
CW		 1914 return;
1915
3e369b76 1916 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1917 return;
ee7b9f93 1918
74dd6928 1919 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1920 pll->name, pll->active, pll->on,
e2b78267 1921 crtc->base.base.id);
92f2584a 1922
cdbd2316
DV		 1923 if (pll->active++) {
1924 WARN_ON(!pll->on);
e9d6944e 1925 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1926 return;
1927 }
f4a091c7 1928 WARN_ON(pll->on);
ee7b9f93 1929
bd2bb1b9
PZ		 1930 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1931
46edb027 1932 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1933 pll->enable(dev_priv, pll);
ee7b9f93 1934 pll->on = true;
92f2584a
JB		 1935}
1936
f6daaec2 1937static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1938{
3d13ef2e
DL		 1939 struct drm_device *dev = crtc->base.dev;
1940 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1941 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1942
92f2584a 1943 /* PCH only available on ILK+ */
3d13ef2e 1944 BUG_ON(INTEL_INFO(dev)->gen < 5);
87a875bb 1945 if (WARN_ON(pll == NULL))
ee7b9f93 1946 return;
92f2584a 1947
3e369b76 1948 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1949 return;
7a419866 1950
46edb027
DV		 1951 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1952 pll->name, pll->active, pll->on,
e2b78267 1953 crtc->base.base.id);
7a419866 1954
48da64a8 1955 if (WARN_ON(pll->active == 0)) {
e9d6944e 1956 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1957 return;
1958 }
1959
e9d6944e 1960 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1961 WARN_ON(!pll->on);
cdbd2316 1962 if (--pll->active)
7a419866 1963 return;
ee7b9f93 1964
46edb027 1965 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1966 pll->disable(dev_priv, pll);
ee7b9f93 1967 pll->on = false;
bd2bb1b9
PZ		 1968
1969 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1970}
1971
b8a4f404
PZ		 1972static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1973 enum pipe pipe)
040484af 1974{
23670b32 1975 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1976 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1977 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1978 uint32_t reg, val, pipeconf_val;
040484af
JB		 1979
1980 /* PCH only available on ILK+ */
55522f37 1981 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1982
1983 /* Make sure PCH DPLL is enabled */
e72f9fbf 1984 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1985 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1986
1987 /* FDI must be feeding us bits for PCH ports */
1988 assert_fdi_tx_enabled(dev_priv, pipe);
1989 assert_fdi_rx_enabled(dev_priv, pipe);
1990
23670b32
DV		 1991 if (HAS_PCH_CPT(dev)) {
1992 /* Workaround: Set the timing override bit before enabling the
1993 * pch transcoder. */
1994 reg = TRANS_CHICKEN2(pipe);
1995 val = I915_READ(reg);
1996 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1997 I915_WRITE(reg, val);
59c859d6 1998 }
23670b32 1999
ab9412ba 2000 reg = PCH_TRANSCONF(pipe);
040484af 2001 val = I915_READ(reg);
5f7f726d 2002 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 2003
2004 if (HAS_PCH_IBX(dev_priv->dev)) {
2005 /*
2006 * make the BPC in transcoder be consistent with
2007 * that in pipeconf reg.
2008 */
dfd07d72
DV		 2009 val &= ~PIPECONF_BPC_MASK;
2010 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 2011 }
5f7f726d
PZ		 2012
2013 val &= ~TRANS_INTERLACE_MASK;
2014 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 2015 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 2016 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 2017 val |= TRANS_LEGACY_INTERLACED_ILK;
2018 else
2019 val |= TRANS_INTERLACED;
5f7f726d
PZ		 2020 else
2021 val |= TRANS_PROGRESSIVE;
2022
040484af
JB		 2023 I915_WRITE(reg, val | TRANS_ENABLE);
2024 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 2025 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 2026}
2027
8fb033d7 2028static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 2029 enum transcoder cpu_transcoder)
040484af 2030{
8fb033d7 2031 u32 val, pipeconf_val;
8fb033d7
PZ		 2032
2033 /* PCH only available on ILK+ */
55522f37 2034 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 2035
8fb033d7 2036 /* FDI must be feeding us bits for PCH ports */
1a240d4d 2037 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2038 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2039
223a6fdf
PZ		 2040 /* Workaround: set timing override bit. */
2041 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2042 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 2043 I915_WRITE(_TRANSA_CHICKEN2, val);
2044
25f3ef11 2045 val = TRANS_ENABLE;
937bb610 2046 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2047
9a76b1c6
PZ		 2048 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2049 PIPECONF_INTERLACED_ILK)
a35f2679 2050 val |= TRANS_INTERLACED;
8fb033d7
PZ		 2051 else
2052 val |= TRANS_PROGRESSIVE;
2053
ab9412ba
DV		 2054 I915_WRITE(LPT_TRANSCONF, val);
2055 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2056 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 2057}
2058
b8a4f404
PZ		 2059static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2060 enum pipe pipe)
040484af 2061{
23670b32
DV		 2062 struct drm_device *dev = dev_priv->dev;
2063 uint32_t reg, val;
040484af
JB		 2064
2065 /* FDI relies on the transcoder */
2066 assert_fdi_tx_disabled(dev_priv, pipe);
2067 assert_fdi_rx_disabled(dev_priv, pipe);
2068
291906f1
JB		 2069 /* Ports must be off as well */
2070 assert_pch_ports_disabled(dev_priv, pipe);
2071
ab9412ba 2072 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2073 val = I915_READ(reg);
2074 val &= ~TRANS_ENABLE;
2075 I915_WRITE(reg, val);
2076 /* wait for PCH transcoder off, transcoder state */
2077 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2078 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2079
2080 if (!HAS_PCH_IBX(dev)) {
2081 /* Workaround: Clear the timing override chicken bit again. */
2082 reg = TRANS_CHICKEN2(pipe);
2083 val = I915_READ(reg);
2084 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2085 I915_WRITE(reg, val);
2086 }
040484af
JB		 2087}
2088
ab4d966c 2089static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2090{
8fb033d7
PZ		 2091 u32 val;
2092
ab9412ba 2093 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2094 val &= ~TRANS_ENABLE;
ab9412ba 2095 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2096 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2097 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2098 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2099
2100 /* Workaround: clear timing override bit. */
2101 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2102 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 2103 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 2104}
2105
b24e7179 2106/**
309cfea8 2107 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2108 * @crtc: crtc responsible for the pipe
b24e7179 2109 *
0372264a 2110 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2111 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2112 */
e1fdc473 2113static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2114{
0372264a
PZ		 2115 struct drm_device *dev = crtc->base.dev;
2116 struct drm_i915_private *dev_priv = dev->dev_private;
2117 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2118 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2119 pipe);
1a240d4d 2120 enum pipe pch_transcoder;
b24e7179
JB		 2121 int reg;
2122 u32 val;
2123
58c6eaa2 2124 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2125 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2126 assert_sprites_disabled(dev_priv, pipe);
2127
681e5811 2128 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2129 pch_transcoder = TRANSCODER_A;
2130 else
2131 pch_transcoder = pipe;
2132
b24e7179
JB		 2133 /*
2134 * A pipe without a PLL won't actually be able to drive bits from
2135 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2136 * need the check.
2137 */
50360403 2138 if (HAS_GMCH_DISPLAY(dev_priv->dev))
409ee761 2139 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2140 assert_dsi_pll_enabled(dev_priv);
2141 else
2142 assert_pll_enabled(dev_priv, pipe);
040484af 2143 else {
6e3c9717 2144 if (crtc->config->has_pch_encoder) {
040484af 2145 /* if driving the PCH, we need FDI enabled */
cc391bbb 2146 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2147 assert_fdi_tx_pll_enabled(dev_priv,
2148 (enum pipe) cpu_transcoder);
040484af
JB		 2149 }
2150 /* FIXME: assert CPU port conditions for SNB+ */
2151 }
b24e7179 2152
702e7a56 2153 reg = PIPECONF(cpu_transcoder);
b24e7179 2154 val = I915_READ(reg);
7ad25d48 2155 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2156 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2157 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2158 return;
7ad25d48 2159 }
00d70b15
CW		 2160
2161 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2162 POSTING_READ(reg);
b24e7179
JB		 2163}
2164
2165/**
309cfea8 2166 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2167 * @crtc: crtc whose pipes is to be disabled
b24e7179 2168 *
575f7ab7
VS		 2169 * Disable the pipe of @crtc, making sure that various hardware
2170 * specific requirements are met, if applicable, e.g. plane
2171 * disabled, panel fitter off, etc.
b24e7179
JB		 2172 *
2173 * Will wait until the pipe has shut down before returning.
2174 */
575f7ab7 2175static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2176{
575f7ab7 2177 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2178 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2179 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2180 int reg;
2181 u32 val;
2182
2183 /*
2184 * Make sure planes won't keep trying to pump pixels to us,
2185 * or we might hang the display.
2186 */
2187 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2188 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2189 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2190
702e7a56 2191 reg = PIPECONF(cpu_transcoder);
b24e7179 2192 val = I915_READ(reg);
00d70b15
CW		 2193 if ((val & PIPECONF_ENABLE) == 0)
2194 return;
2195
67adc644
VS		 2196 /*
2197 * Double wide has implications for planes
2198 * so best keep it disabled when not needed.
2199 */
6e3c9717 2200 if (crtc->config->double_wide)
67adc644
VS		 2201 val &= ~PIPECONF_DOUBLE_WIDE;
2202
2203 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2204 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2205 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2206 val &= ~PIPECONF_ENABLE;
2207
2208 I915_WRITE(reg, val);
2209 if ((val & PIPECONF_ENABLE) == 0)
2210 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2211}
2212
2213/**
262ca2b0 2214 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
fdd508a6
VS		 2215 * @plane: plane to be enabled
2216 * @crtc: crtc for the plane
b24e7179 2217 *
fdd508a6 2218 * Enable @plane on @crtc, making sure that the pipe is running first.
b24e7179 2219 */
fdd508a6
VS		 2220static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2221 struct drm_crtc *crtc)
b24e7179 2222{
fdd508a6
VS		 2223 struct drm_device *dev = plane->dev;
2224 struct drm_i915_private *dev_priv = dev->dev_private;
2225 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b24e7179
JB		 2226
2227 /* If the pipe isn't enabled, we can't pump pixels and may hang */
fdd508a6 2228 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
b70709a6 2229 to_intel_plane_state(plane->state)->visible = true;
939c2fe8 2230
fdd508a6
VS		 2231 dev_priv->display.update_primary_plane(crtc, plane->fb,
2232 crtc->x, crtc->y);
b24e7179
JB		 2233}
2234
693db184
CW		 2235static bool need_vtd_wa(struct drm_device *dev)
2236{
2237#ifdef CONFIG_INTEL_IOMMU
2238 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2239 return true;
2240#endif
2241 return false;
2242}
2243
50470bb0 2244unsigned int
6761dd31
TU		 2245intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2246 uint64_t fb_format_modifier)
a57ce0b2 2247{
6761dd31
TU		 2248 unsigned int tile_height;
2249 uint32_t pixel_bytes;
a57ce0b2 2250
b5d0e9bf
DL		 2251 switch (fb_format_modifier) {
2252 case DRM_FORMAT_MOD_NONE:
2253 tile_height = 1;
2254 break;
2255 case I915_FORMAT_MOD_X_TILED:
2256 tile_height = IS_GEN2(dev) ? 16 : 8;
2257 break;
2258 case I915_FORMAT_MOD_Y_TILED:
2259 tile_height = 32;
2260 break;
2261 case I915_FORMAT_MOD_Yf_TILED:
6761dd31
TU		 2262 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2263 switch (pixel_bytes) {
b5d0e9bf 2264 default:
6761dd31 2265 case 1:
b5d0e9bf
DL		 2266 tile_height = 64;
2267 break;
6761dd31
TU		 2268 case 2:
2269 case 4:
b5d0e9bf
DL		 2270 tile_height = 32;
2271 break;
6761dd31 2272 case 8:
b5d0e9bf
DL		 2273 tile_height = 16;
2274 break;
6761dd31 2275 case 16:
b5d0e9bf
DL		 2276 WARN_ONCE(1,
2277 "128-bit pixels are not supported for display!");
2278 tile_height = 16;
2279 break;
2280 }
2281 break;
2282 default:
2283 MISSING_CASE(fb_format_modifier);
2284 tile_height = 1;
2285 break;
2286 }
091df6cb 2287
6761dd31
TU		 2288 return tile_height;
2289}
2290
2291unsigned int
2292intel_fb_align_height(struct drm_device *dev, unsigned int height,
2293 uint32_t pixel_format, uint64_t fb_format_modifier)
2294{
2295 return ALIGN(height, intel_tile_height(dev, pixel_format,
2296 fb_format_modifier));
a57ce0b2
JB		 2297}
2298
f64b98cd
TU		 2299static int
2300intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2301 const struct drm_plane_state *plane_state)
2302{
50470bb0 2303 struct intel_rotation_info *info = &view->rotation_info;
50470bb0 2304
f64b98cd
TU		 2305 *view = i915_ggtt_view_normal;
2306
50470bb0
TU		 2307 if (!plane_state)
2308 return 0;
2309
121920fa 2310 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2311 return 0;
2312
9abc4648 2313 *view = i915_ggtt_view_rotated;
50470bb0
TU		 2314
2315 info->height = fb->height;
2316 info->pixel_format = fb->pixel_format;
2317 info->pitch = fb->pitches[0];
2318 info->fb_modifier = fb->modifier[0];
2319
f64b98cd
TU		 2320 return 0;
2321}
2322
127bd2ac 2323int
850c4cdc
TU		 2324intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2325 struct drm_framebuffer *fb,
82bc3b2d 2326 const struct drm_plane_state *plane_state,
a4872ba6 2327 struct intel_engine_cs *pipelined)
6b95a207 2328{
850c4cdc 2329 struct drm_device *dev = fb->dev;
ce453d81 2330 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2331 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2332 struct i915_ggtt_view view;
6b95a207
KH		 2333 u32 alignment;
2334 int ret;
2335
ebcdd39e
MR		 2336 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2337
7b911adc
TU		 2338 switch (fb->modifier[0]) {
2339 case DRM_FORMAT_MOD_NONE:
1fada4cc
DL		 2340 if (INTEL_INFO(dev)->gen >= 9)
2341 alignment = 256 * 1024;
2342 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
534843da 2343 alignment = 128 * 1024;
a6c45cf0 2344 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 2345 alignment = 4 * 1024;
2346 else
2347 alignment = 64 * 1024;
6b95a207 2348 break;
7b911adc 2349 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2350 if (INTEL_INFO(dev)->gen >= 9)
2351 alignment = 256 * 1024;
2352 else {
2353 /* pin() will align the object as required by fence */
2354 alignment = 0;
2355 }
6b95a207 2356 break;
7b911adc 2357 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2358 case I915_FORMAT_MOD_Yf_TILED:
2359 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2360 "Y tiling bo slipped through, driver bug!\n"))
2361 return -EINVAL;
2362 alignment = 1 * 1024 * 1024;
2363 break;
6b95a207 2364 default:
7b911adc
TU		 2365 MISSING_CASE(fb->modifier[0]);
2366 return -EINVAL;
6b95a207
KH		 2367 }
2368
f64b98cd
TU		 2369 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2370 if (ret)
2371 return ret;
2372
693db184
CW		 2373 /* Note that the w/a also requires 64 PTE of padding following the
2374 * bo. We currently fill all unused PTE with the shadow page and so
2375 * we should always have valid PTE following the scanout preventing
2376 * the VT-d warning.
2377 */
2378 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2379 alignment = 256 * 1024;
2380
d6dd6843
PZ		 2381 /*
2382 * Global gtt pte registers are special registers which actually forward
2383 * writes to a chunk of system memory. Which means that there is no risk
2384 * that the register values disappear as soon as we call
2385 * intel_runtime_pm_put(), so it is correct to wrap only the
2386 * pin/unpin/fence and not more.
2387 */
2388 intel_runtime_pm_get(dev_priv);
2389
ce453d81 2390 dev_priv->mm.interruptible = false;
e6617330 2391 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
f64b98cd 2392 &view);
48b956c5 2393 if (ret)
ce453d81 2394 goto err_interruptible;
6b95a207
KH		 2395
2396 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2397 * fence, whereas 965+ only requires a fence if using
2398 * framebuffer compression. For simplicity, we always install
2399 * a fence as the cost is not that onerous.
2400 */
06d98131 2401 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2402 if (ret)
2403 goto err_unpin;
1690e1eb 2404
9a5a53b3 2405 i915_gem_object_pin_fence(obj);
6b95a207 2406
ce453d81 2407 dev_priv->mm.interruptible = true;
d6dd6843 2408 intel_runtime_pm_put(dev_priv);
6b95a207 2409 return 0;
48b956c5
CW		 2410
2411err_unpin:
f64b98cd 2412 i915_gem_object_unpin_from_display_plane(obj, &view);
ce453d81
CW		 2413err_interruptible:
2414 dev_priv->mm.interruptible = true;
d6dd6843 2415 intel_runtime_pm_put(dev_priv);
48b956c5 2416 return ret;
6b95a207
KH		 2417}
2418
82bc3b2d
TU		 2419static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2420 const struct drm_plane_state *plane_state)
1690e1eb 2421{
82bc3b2d 2422 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2423 struct i915_ggtt_view view;
2424 int ret;
82bc3b2d 2425
ebcdd39e
MR		 2426 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2427
f64b98cd
TU		 2428 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2429 WARN_ONCE(ret, "Couldn't get view from plane state!");
2430
1690e1eb 2431 i915_gem_object_unpin_fence(obj);
f64b98cd 2432 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2433}
2434
c2c75131
DV		 2435/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2436 * is assumed to be a power-of-two. */
bc752862
CW		 2437unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2438 unsigned int tiling_mode,
2439 unsigned int cpp,
2440 unsigned int pitch)
c2c75131 2441{
bc752862
CW		 2442 if (tiling_mode != I915_TILING_NONE) {
2443 unsigned int tile_rows, tiles;
c2c75131 2444
bc752862
CW		 2445 tile_rows = *y / 8;
2446 *y %= 8;
c2c75131 2447
bc752862
CW		 2448 tiles = *x / (512/cpp);
2449 *x %= 512/cpp;
2450
2451 return tile_rows * pitch * 8 + tiles * 4096;
2452 } else {
2453 unsigned int offset;
2454
2455 offset = *y * pitch + *x * cpp;
2456 *y = 0;
2457 *x = (offset & 4095) / cpp;
2458 return offset & -4096;
2459 }
c2c75131
DV		 2460}
2461
b35d63fa 2462static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2463{
2464 switch (format) {
2465 case DISPPLANE_8BPP:
2466 return DRM_FORMAT_C8;
2467 case DISPPLANE_BGRX555:
2468 return DRM_FORMAT_XRGB1555;
2469 case DISPPLANE_BGRX565:
2470 return DRM_FORMAT_RGB565;
2471 default:
2472 case DISPPLANE_BGRX888:
2473 return DRM_FORMAT_XRGB8888;
2474 case DISPPLANE_RGBX888:
2475 return DRM_FORMAT_XBGR8888;
2476 case DISPPLANE_BGRX101010:
2477 return DRM_FORMAT_XRGB2101010;
2478 case DISPPLANE_RGBX101010:
2479 return DRM_FORMAT_XBGR2101010;
2480 }
2481}
2482
bc8d7dff
DL		 2483static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2484{
2485 switch (format) {
2486 case PLANE_CTL_FORMAT_RGB_565:
2487 return DRM_FORMAT_RGB565;
2488 default:
2489 case PLANE_CTL_FORMAT_XRGB_8888:
2490 if (rgb_order) {
2491 if (alpha)
2492 return DRM_FORMAT_ABGR8888;
2493 else
2494 return DRM_FORMAT_XBGR8888;
2495 } else {
2496 if (alpha)
2497 return DRM_FORMAT_ARGB8888;
2498 else
2499 return DRM_FORMAT_XRGB8888;
2500 }
2501 case PLANE_CTL_FORMAT_XRGB_2101010:
2502 if (rgb_order)
2503 return DRM_FORMAT_XBGR2101010;
2504 else
2505 return DRM_FORMAT_XRGB2101010;
2506 }
2507}
2508
5724dbd1 2509static bool
f6936e29
DV		 2510intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2511 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2512{
2513 struct drm_device *dev = crtc->base.dev;
2514 struct drm_i915_gem_object *obj = NULL;
2515 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2516 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2517 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2518 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2519 PAGE_SIZE);
2520
2521 size_aligned -= base_aligned;
46f297fb 2522
ff2652ea
CW		 2523 if (plane_config->size == 0)
2524 return false;
2525
f37b5c2b
DV		 2526 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2527 base_aligned,
2528 base_aligned,
2529 size_aligned);
46f297fb 2530 if (!obj)
484b41dd 2531 return false;
46f297fb 2532
49af449b
DL		 2533 obj->tiling_mode = plane_config->tiling;
2534 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2535 obj->stride = fb->pitches[0];
46f297fb 2536
6bf129df
DL		 2537 mode_cmd.pixel_format = fb->pixel_format;
2538 mode_cmd.width = fb->width;
2539 mode_cmd.height = fb->height;
2540 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2541 mode_cmd.modifier[0] = fb->modifier[0];
2542 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2543
2544 mutex_lock(&dev->struct_mutex);
6bf129df 2545 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2546 &mode_cmd, obj)) {
46f297fb
JB		 2547 DRM_DEBUG_KMS("intel fb init failed\n");
2548 goto out_unref_obj;
2549 }
46f297fb 2550 mutex_unlock(&dev->struct_mutex);
484b41dd 2551
f6936e29 2552 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2553 return true;
46f297fb
JB		 2554
2555out_unref_obj:
2556 drm_gem_object_unreference(&obj->base);
2557 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2558 return false;
2559}
2560
afd65eb4
MR		 2561/* Update plane->state->fb to match plane->fb after driver-internal updates */
2562static void
2563update_state_fb(struct drm_plane *plane)
2564{
2565 if (plane->fb == plane->state->fb)
2566 return;
2567
2568 if (plane->state->fb)
2569 drm_framebuffer_unreference(plane->state->fb);
2570 plane->state->fb = plane->fb;
2571 if (plane->state->fb)
2572 drm_framebuffer_reference(plane->state->fb);
2573}
2574
5724dbd1 2575static void
f6936e29
DV		 2576intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2577 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2578{
2579 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2580 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2581 struct drm_crtc *c;
2582 struct intel_crtc *i;
2ff8fde1 2583 struct drm_i915_gem_object *obj;
88595ac9
DV		 2584 struct drm_plane *primary = intel_crtc->base.primary;
2585 struct drm_framebuffer *fb;
484b41dd 2586
2d14030b 2587 if (!plane_config->fb)
484b41dd
JB		 2588 return;
2589
f6936e29 2590 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2591 fb = &plane_config->fb->base;
2592 goto valid_fb;
f55548b5 2593 }
484b41dd 2594
2d14030b 2595 kfree(plane_config->fb);
484b41dd
JB		 2596
2597 /*
2598 * Failed to alloc the obj, check to see if we should share
2599 * an fb with another CRTC instead
2600 */
70e1e0ec 2601 for_each_crtc(dev, c) {
484b41dd
JB		 2602 i = to_intel_crtc(c);
2603
2604 if (c == &intel_crtc->base)
2605 continue;
2606
2ff8fde1
MR		 2607 if (!i->active)
2608 continue;
2609
88595ac9
DV		 2610 fb = c->primary->fb;
2611 if (!fb)
484b41dd
JB		 2612 continue;
2613
88595ac9 2614 obj = intel_fb_obj(fb);
2ff8fde1 2615 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2616 drm_framebuffer_reference(fb);
2617 goto valid_fb;
484b41dd
JB		 2618 }
2619 }
88595ac9
DV		 2620
2621 return;
2622
2623valid_fb:
2624 obj = intel_fb_obj(fb);
2625 if (obj->tiling_mode != I915_TILING_NONE)
2626 dev_priv->preserve_bios_swizzle = true;
2627
2628 primary->fb = fb;
2629 primary->state->crtc = &intel_crtc->base;
2630 primary->crtc = &intel_crtc->base;
2631 update_state_fb(primary);
2632 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
46f297fb
JB		 2633}
2634
29b9bde6
DV		 2635static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2636 struct drm_framebuffer *fb,
2637 int x, int y)
81255565
JB		 2638{
2639 struct drm_device *dev = crtc->dev;
2640 struct drm_i915_private *dev_priv = dev->dev_private;
2641 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2642 struct drm_plane *primary = crtc->primary;
2643 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2644 struct drm_i915_gem_object *obj;
81255565 2645 int plane = intel_crtc->plane;
e506a0c6 2646 unsigned long linear_offset;
81255565 2647 u32 dspcntr;
f45651ba 2648 u32 reg = DSPCNTR(plane);
48404c1e 2649 int pixel_size;
f45651ba 2650
b70709a6 2651 if (!visible || !fb) {
fdd508a6
VS		 2652 I915_WRITE(reg, 0);
2653 if (INTEL_INFO(dev)->gen >= 4)
2654 I915_WRITE(DSPSURF(plane), 0);
2655 else
2656 I915_WRITE(DSPADDR(plane), 0);
2657 POSTING_READ(reg);
2658 return;
2659 }
2660
c9ba6fad
VS		 2661 obj = intel_fb_obj(fb);
2662 if (WARN_ON(obj == NULL))
2663 return;
2664
2665 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2666
f45651ba
VS		 2667 dspcntr = DISPPLANE_GAMMA_ENABLE;
2668
fdd508a6 2669 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2670
2671 if (INTEL_INFO(dev)->gen < 4) {
2672 if (intel_crtc->pipe == PIPE_B)
2673 dspcntr |= DISPPLANE_SEL_PIPE_B;
2674
2675 /* pipesrc and dspsize control the size that is scaled from,
2676 * which should always be the user's requested size.
2677 */
2678 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2679 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2680 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2681 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2682 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2683 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2684 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2685 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2686 I915_WRITE(PRIMPOS(plane), 0);
2687 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2688 }
81255565 2689
57779d06
VS		 2690 switch (fb->pixel_format) {
2691 case DRM_FORMAT_C8:
81255565
JB		 2692 dspcntr |= DISPPLANE_8BPP;
2693 break;
57779d06 2694 case DRM_FORMAT_XRGB1555:
57779d06 2695 dspcntr |= DISPPLANE_BGRX555;
81255565 2696 break;
57779d06
VS		 2697 case DRM_FORMAT_RGB565:
2698 dspcntr |= DISPPLANE_BGRX565;
2699 break;
2700 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2701 dspcntr |= DISPPLANE_BGRX888;
2702 break;
2703 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2704 dspcntr |= DISPPLANE_RGBX888;
2705 break;
2706 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2707 dspcntr |= DISPPLANE_BGRX101010;
2708 break;
2709 case DRM_FORMAT_XBGR2101010:
57779d06 2710 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2711 break;
2712 default:
baba133a 2713 BUG();
81255565 2714 }
57779d06 2715
f45651ba
VS		 2716 if (INTEL_INFO(dev)->gen >= 4 &&
2717 obj->tiling_mode != I915_TILING_NONE)
2718 dspcntr |= DISPPLANE_TILED;
81255565 2719
de1aa629
VS		 2720 if (IS_G4X(dev))
2721 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2722
b9897127 2723 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2724
c2c75131
DV		 2725 if (INTEL_INFO(dev)->gen >= 4) {
2726 intel_crtc->dspaddr_offset =
bc752862 2727 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2728 pixel_size,
bc752862 2729 fb->pitches[0]);
c2c75131
DV		 2730 linear_offset -= intel_crtc->dspaddr_offset;
2731 } else {
e506a0c6 2732 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2733 }
e506a0c6 2734
8e7d688b 2735 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2736 dspcntr |= DISPPLANE_ROTATE_180;
2737
6e3c9717
ACO		 2738 x += (intel_crtc->config->pipe_src_w - 1);
2739 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2740
2741 /* Finding the last pixel of the last line of the display
2742 data and adding to linear_offset*/
2743 linear_offset +=
6e3c9717
ACO		 2744 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2745 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2746 }
2747
2748 I915_WRITE(reg, dspcntr);
2749
01f2c773 2750 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2751 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2752 I915_WRITE(DSPSURF(plane),
2753 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2754 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2755 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2756 } else
f343c5f6 2757 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2758 POSTING_READ(reg);
17638cd6
JB		 2759}
2760
29b9bde6
DV		 2761static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2762 struct drm_framebuffer *fb,
2763 int x, int y)
17638cd6
JB		 2764{
2765 struct drm_device *dev = crtc->dev;
2766 struct drm_i915_private *dev_priv = dev->dev_private;
2767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2768 struct drm_plane *primary = crtc->primary;
2769 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2770 struct drm_i915_gem_object *obj;
17638cd6 2771 int plane = intel_crtc->plane;
e506a0c6 2772 unsigned long linear_offset;
17638cd6 2773 u32 dspcntr;
f45651ba 2774 u32 reg = DSPCNTR(plane);
48404c1e 2775 int pixel_size;
f45651ba 2776
b70709a6 2777 if (!visible || !fb) {
fdd508a6
VS		 2778 I915_WRITE(reg, 0);
2779 I915_WRITE(DSPSURF(plane), 0);
2780 POSTING_READ(reg);
2781 return;
2782 }
2783
c9ba6fad
VS		 2784 obj = intel_fb_obj(fb);
2785 if (WARN_ON(obj == NULL))
2786 return;
2787
2788 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2789
f45651ba
VS		 2790 dspcntr = DISPPLANE_GAMMA_ENABLE;
2791
fdd508a6 2792 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2793
2794 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2795 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2796
57779d06
VS		 2797 switch (fb->pixel_format) {
2798 case DRM_FORMAT_C8:
17638cd6
JB		 2799 dspcntr |= DISPPLANE_8BPP;
2800 break;
57779d06
VS		 2801 case DRM_FORMAT_RGB565:
2802 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2803 break;
57779d06 2804 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2805 dspcntr |= DISPPLANE_BGRX888;
2806 break;
2807 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2808 dspcntr |= DISPPLANE_RGBX888;
2809 break;
2810 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2811 dspcntr |= DISPPLANE_BGRX101010;
2812 break;
2813 case DRM_FORMAT_XBGR2101010:
57779d06 2814 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2815 break;
2816 default:
baba133a 2817 BUG();
17638cd6
JB		 2818 }
2819
2820 if (obj->tiling_mode != I915_TILING_NONE)
2821 dspcntr |= DISPPLANE_TILED;
17638cd6 2822
f45651ba 2823 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2824 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2825
b9897127 2826 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2827 intel_crtc->dspaddr_offset =
bc752862 2828 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2829 pixel_size,
bc752862 2830 fb->pitches[0]);
c2c75131 2831 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2832 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2833 dspcntr |= DISPPLANE_ROTATE_180;
2834
2835 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2836 x += (intel_crtc->config->pipe_src_w - 1);
2837 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2838
2839 /* Finding the last pixel of the last line of the display
2840 data and adding to linear_offset*/
2841 linear_offset +=
6e3c9717
ACO		 2842 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2843 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2844 }
2845 }
2846
2847 I915_WRITE(reg, dspcntr);
17638cd6 2848
01f2c773 2849 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2850 I915_WRITE(DSPSURF(plane),
2851 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2852 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2853 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2854 } else {
2855 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2856 I915_WRITE(DSPLINOFF(plane), linear_offset);
2857 }
17638cd6 2858 POSTING_READ(reg);
17638cd6
JB		 2859}
2860
b321803d
DL		 2861u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2862 uint32_t pixel_format)
2863{
2864 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2865
2866 /*
2867 * The stride is either expressed as a multiple of 64 bytes
2868 * chunks for linear buffers or in number of tiles for tiled
2869 * buffers.
2870 */
2871 switch (fb_modifier) {
2872 case DRM_FORMAT_MOD_NONE:
2873 return 64;
2874 case I915_FORMAT_MOD_X_TILED:
2875 if (INTEL_INFO(dev)->gen == 2)
2876 return 128;
2877 return 512;
2878 case I915_FORMAT_MOD_Y_TILED:
2879 /* No need to check for old gens and Y tiling since this is
2880 * about the display engine and those will be blocked before
2881 * we get here.
2882 */
2883 return 128;
2884 case I915_FORMAT_MOD_Yf_TILED:
2885 if (bits_per_pixel == 8)
2886 return 64;
2887 else
2888 return 128;
2889 default:
2890 MISSING_CASE(fb_modifier);
2891 return 64;
2892 }
2893}
2894
121920fa
TU		 2895unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2896 struct drm_i915_gem_object *obj)
2897{
9abc4648 2898 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
121920fa
TU		 2899
2900 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2901 view = &i915_ggtt_view_rotated;
121920fa
TU		 2902
2903 return i915_gem_obj_ggtt_offset_view(obj, view);
2904}
2905
a1b2278e
CK		 2906/*
2907 * This function detaches (aka. unbinds) unused scalers in hardware
2908 */
2909void skl_detach_scalers(struct intel_crtc *intel_crtc)
2910{
2911 struct drm_device *dev;
2912 struct drm_i915_private *dev_priv;
2913 struct intel_crtc_scaler_state *scaler_state;
2914 int i;
2915
2916 if (!intel_crtc || !intel_crtc->config)
2917 return;
2918
2919 dev = intel_crtc->base.dev;
2920 dev_priv = dev->dev_private;
2921 scaler_state = &intel_crtc->config->scaler_state;
2922
2923 /* loop through and disable scalers that aren't in use */
2924 for (i = 0; i < intel_crtc->num_scalers; i++) {
2925 if (!scaler_state->scalers[i].in_use) {
2926 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2927 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2928 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2929 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2930 intel_crtc->base.base.id, intel_crtc->pipe, i);
2931 }
2932 }
2933}
2934
6156a456 2935u32 skl_plane_ctl_format(uint32_t pixel_format)
70d21f0e 2936{
6156a456 2937 switch (pixel_format) {
d161cf7a 2938 case DRM_FORMAT_C8:
c34ce3d1 2939 return PLANE_CTL_FORMAT_INDEXED;
70d21f0e 2940 case DRM_FORMAT_RGB565:
c34ce3d1 2941 return PLANE_CTL_FORMAT_RGB_565;
70d21f0e 2942 case DRM_FORMAT_XBGR8888:
c34ce3d1 2943 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
6156a456 2944 case DRM_FORMAT_XRGB8888:
c34ce3d1 2945 return PLANE_CTL_FORMAT_XRGB_8888;
6156a456
CK		 2946 /*
2947 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2948 * to be already pre-multiplied. We need to add a knob (or a different
2949 * DRM_FORMAT) for user-space to configure that.
2950 */
f75fb42a 2951 case DRM_FORMAT_ABGR8888:
c34ce3d1 2952 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
6156a456 2953 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
6156a456 2954 case DRM_FORMAT_ARGB8888:
c34ce3d1 2955 return PLANE_CTL_FORMAT_XRGB_8888 |
6156a456 2956 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
70d21f0e 2957 case DRM_FORMAT_XRGB2101010:
c34ce3d1 2958 return PLANE_CTL_FORMAT_XRGB_2101010;
70d21f0e 2959 case DRM_FORMAT_XBGR2101010:
c34ce3d1 2960 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
6156a456 2961 case DRM_FORMAT_YUYV:
c34ce3d1 2962 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
6156a456 2963 case DRM_FORMAT_YVYU:
c34ce3d1 2964 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
6156a456 2965 case DRM_FORMAT_UYVY:
c34ce3d1 2966 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
6156a456 2967 case DRM_FORMAT_VYUY:
c34ce3d1 2968 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
70d21f0e 2969 default:
4249eeef 2970 MISSING_CASE(pixel_format);
70d21f0e 2971 }
8cfcba41 2972
c34ce3d1 2973 return 0;
6156a456 2974}
70d21f0e 2975
6156a456
CK		 2976u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2977{
6156a456 2978 switch (fb_modifier) {
30af77c4 2979 case DRM_FORMAT_MOD_NONE:
70d21f0e 2980 break;
30af77c4 2981 case I915_FORMAT_MOD_X_TILED:
c34ce3d1 2982 return PLANE_CTL_TILED_X;
b321803d 2983 case I915_FORMAT_MOD_Y_TILED:
c34ce3d1 2984 return PLANE_CTL_TILED_Y;
b321803d 2985 case I915_FORMAT_MOD_Yf_TILED:
c34ce3d1 2986 return PLANE_CTL_TILED_YF;
70d21f0e 2987 default:
6156a456 2988 MISSING_CASE(fb_modifier);
70d21f0e 2989 }
8cfcba41 2990
c34ce3d1 2991 return 0;
6156a456 2992}
70d21f0e 2993
6156a456
CK		 2994u32 skl_plane_ctl_rotation(unsigned int rotation)
2995{
3b7a5119 2996 switch (rotation) {
6156a456
CK		 2997 case BIT(DRM_ROTATE_0):
2998 break;
1e8df167
SJ		 2999 /*
3000 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3001 * while i915 HW rotation is clockwise, thats why this swapping.
3002 */
3b7a5119 3003 case BIT(DRM_ROTATE_90):
1e8df167 3004 return PLANE_CTL_ROTATE_270;
3b7a5119 3005 case BIT(DRM_ROTATE_180):
c34ce3d1 3006 return PLANE_CTL_ROTATE_180;
3b7a5119 3007 case BIT(DRM_ROTATE_270):
1e8df167 3008 return PLANE_CTL_ROTATE_90;
6156a456
CK		 3009 default:
3010 MISSING_CASE(rotation);
3011 }
3012
c34ce3d1 3013 return 0;
6156a456
CK		 3014}
3015
3016static void skylake_update_primary_plane(struct drm_crtc *crtc,
3017 struct drm_framebuffer *fb,
3018 int x, int y)
3019{
3020 struct drm_device *dev = crtc->dev;
3021 struct drm_i915_private *dev_priv = dev->dev_private;
3022 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 3023 struct drm_plane *plane = crtc->primary;
3024 bool visible = to_intel_plane_state(plane->state)->visible;
6156a456
CK		 3025 struct drm_i915_gem_object *obj;
3026 int pipe = intel_crtc->pipe;
3027 u32 plane_ctl, stride_div, stride;
3028 u32 tile_height, plane_offset, plane_size;
3029 unsigned int rotation;
3030 int x_offset, y_offset;
3031 unsigned long surf_addr;
6156a456
CK		 3032 struct intel_crtc_state *crtc_state = intel_crtc->config;
3033 struct intel_plane_state *plane_state;
3034 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3035 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3036 int scaler_id = -1;
3037
6156a456
CK		 3038 plane_state = to_intel_plane_state(plane->state);
3039
b70709a6 3040 if (!visible || !fb) {
6156a456
CK		 3041 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3042 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3043 POSTING_READ(PLANE_CTL(pipe, 0));
3044 return;
3b7a5119 3045 }
70d21f0e 3046
6156a456
CK		 3047 plane_ctl = PLANE_CTL_ENABLE |
3048 PLANE_CTL_PIPE_GAMMA_ENABLE |
3049 PLANE_CTL_PIPE_CSC_ENABLE;
3050
3051 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3052 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3053 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3054
3055 rotation = plane->state->rotation;
3056 plane_ctl |= skl_plane_ctl_rotation(rotation);
3057
b321803d
DL		 3058 obj = intel_fb_obj(fb);
3059 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3060 fb->pixel_format);
3b7a5119
SJ		 3061 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3062
6156a456
CK		 3063 /*
3064 * FIXME: intel_plane_state->src, dst aren't set when transitional
3065 * update_plane helpers are called from legacy paths.
3066 * Once full atomic crtc is available, below check can be avoided.
3067 */
3068 if (drm_rect_width(&plane_state->src)) {
3069 scaler_id = plane_state->scaler_id;
3070 src_x = plane_state->src.x1 >> 16;
3071 src_y = plane_state->src.y1 >> 16;
3072 src_w = drm_rect_width(&plane_state->src) >> 16;
3073 src_h = drm_rect_height(&plane_state->src) >> 16;
3074 dst_x = plane_state->dst.x1;
3075 dst_y = plane_state->dst.y1;
3076 dst_w = drm_rect_width(&plane_state->dst);
3077 dst_h = drm_rect_height(&plane_state->dst);
3078
3079 WARN_ON(x != src_x || y != src_y);
3080 } else {
3081 src_w = intel_crtc->config->pipe_src_w;
3082 src_h = intel_crtc->config->pipe_src_h;
3083 }
3084
3b7a5119
SJ		 3085 if (intel_rotation_90_or_270(rotation)) {
3086 /* stride = Surface height in tiles */
2614f17d 3087 tile_height = intel_tile_height(dev, fb->pixel_format,
3b7a5119
SJ		 3088 fb->modifier[0]);
3089 stride = DIV_ROUND_UP(fb->height, tile_height);
6156a456 3090 x_offset = stride * tile_height - y - src_h;
3b7a5119 3091 y_offset = x;
6156a456 3092 plane_size = (src_w - 1) << 16 | (src_h - 1);
3b7a5119
SJ		 3093 } else {
3094 stride = fb->pitches[0] / stride_div;
3095 x_offset = x;
3096 y_offset = y;
6156a456 3097 plane_size = (src_h - 1) << 16 | (src_w - 1);
3b7a5119
SJ		 3098 }
3099 plane_offset = y_offset << 16 | x_offset;
b321803d 3100
70d21f0e 3101 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3b7a5119
SJ		 3102 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3103 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3104 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
6156a456
CK		 3105
3106 if (scaler_id >= 0) {
3107 uint32_t ps_ctrl = 0;
3108
3109 WARN_ON(!dst_w || !dst_h);
3110 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3111 crtc_state->scaler_state.scalers[scaler_id].mode;
3112 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3113 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3114 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3115 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3116 I915_WRITE(PLANE_POS(pipe, 0), 0);
3117 } else {
3118 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3119 }
3120
121920fa 3121 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3122
3123 POSTING_READ(PLANE_SURF(pipe, 0));
3124}
3125
17638cd6
JB		 3126/* Assume fb object is pinned & idle & fenced and just update base pointers */
3127static int
3128intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3129 int x, int y, enum mode_set_atomic state)
3130{
3131 struct drm_device *dev = crtc->dev;
3132 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3133
6b8e6ed0
CW		 3134 if (dev_priv->display.disable_fbc)
3135 dev_priv->display.disable_fbc(dev);
81255565 3136
29b9bde6
DV		 3137 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3138
3139 return 0;
81255565
JB		 3140}
3141
7514747d 3142static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3143{
96a02917
VS		 3144 struct drm_crtc *crtc;
3145
70e1e0ec 3146 for_each_crtc(dev, crtc) {
96a02917
VS		 3147 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3148 enum plane plane = intel_crtc->plane;
3149
3150 intel_prepare_page_flip(dev, plane);
3151 intel_finish_page_flip_plane(dev, plane);
3152 }
7514747d
VS		 3153}
3154
3155static void intel_update_primary_planes(struct drm_device *dev)
3156{
3157 struct drm_i915_private *dev_priv = dev->dev_private;
3158 struct drm_crtc *crtc;
96a02917 3159
70e1e0ec 3160 for_each_crtc(dev, crtc) {
96a02917
VS		 3161 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3162
51fd371b 3163 drm_modeset_lock(&crtc->mutex, NULL);
947fdaad
CW		 3164 /*
3165 * FIXME: Once we have proper support for primary planes (and
3166 * disabling them without disabling the entire crtc) allow again
66e514c1 3167 * a NULL crtc->primary->fb.
947fdaad 3168 */
f4510a27 3169 if (intel_crtc->active && crtc->primary->fb)
262ca2b0 3170 dev_priv->display.update_primary_plane(crtc,
66e514c1 3171 crtc->primary->fb,
262ca2b0
MR		 3172 crtc->x,
3173 crtc->y);
51fd371b 3174 drm_modeset_unlock(&crtc->mutex);
96a02917
VS		 3175 }
3176}
3177
7514747d
VS		 3178void intel_prepare_reset(struct drm_device *dev)
3179{
3180 /* no reset support for gen2 */
3181 if (IS_GEN2(dev))
3182 return;
3183
3184 /* reset doesn't touch the display */
3185 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3186 return;
3187
3188 drm_modeset_lock_all(dev);
f98ce92f
VS		 3189 /*
3190 * Disabling the crtcs gracefully seems nicer. Also the
3191 * g33 docs say we should at least disable all the planes.
3192 */
6b72d486 3193 intel_display_suspend(dev);
7514747d
VS		 3194}
3195
3196void intel_finish_reset(struct drm_device *dev)
3197{
3198 struct drm_i915_private *dev_priv = to_i915(dev);
3199
3200 /*
3201 * Flips in the rings will be nuked by the reset,
3202 * so complete all pending flips so that user space
3203 * will get its events and not get stuck.
3204 */
3205 intel_complete_page_flips(dev);
3206
3207 /* no reset support for gen2 */
3208 if (IS_GEN2(dev))
3209 return;
3210
3211 /* reset doesn't touch the display */
3212 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3213 /*
3214 * Flips in the rings have been nuked by the reset,
3215 * so update the base address of all primary
3216 * planes to the the last fb to make sure we're
3217 * showing the correct fb after a reset.
3218 */
3219 intel_update_primary_planes(dev);
3220 return;
3221 }
3222
3223 /*
3224 * The display has been reset as well,
3225 * so need a full re-initialization.
3226 */
3227 intel_runtime_pm_disable_interrupts(dev_priv);
3228 intel_runtime_pm_enable_interrupts(dev_priv);
3229
3230 intel_modeset_init_hw(dev);
3231
3232 spin_lock_irq(&dev_priv->irq_lock);
3233 if (dev_priv->display.hpd_irq_setup)
3234 dev_priv->display.hpd_irq_setup(dev);
3235 spin_unlock_irq(&dev_priv->irq_lock);
3236
3237 intel_modeset_setup_hw_state(dev, true);
3238
3239 intel_hpd_init(dev_priv);
3240
3241 drm_modeset_unlock_all(dev);
3242}
3243
2e2f351d 3244static void
14667a4b
CW		 3245intel_finish_fb(struct drm_framebuffer *old_fb)
3246{
2ff8fde1 3247 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2e2f351d 3248 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14667a4b
CW		 3249 bool was_interruptible = dev_priv->mm.interruptible;
3250 int ret;
3251
14667a4b
CW		 3252 /* Big Hammer, we also need to ensure that any pending
3253 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3254 * current scanout is retired before unpinning the old
2e2f351d
CW		 3255 * framebuffer. Note that we rely on userspace rendering
3256 * into the buffer attached to the pipe they are waiting
3257 * on. If not, userspace generates a GPU hang with IPEHR
3258 * point to the MI_WAIT_FOR_EVENT.
14667a4b
CW		 3259 *
3260 * This should only fail upon a hung GPU, in which case we
3261 * can safely continue.
3262 */
3263 dev_priv->mm.interruptible = false;
2e2f351d 3264 ret = i915_gem_object_wait_rendering(obj, true);
14667a4b
CW		 3265 dev_priv->mm.interruptible = was_interruptible;
3266
2e2f351d 3267 WARN_ON(ret);
14667a4b
CW		 3268}
3269
7d5e3799
CW		 3270static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3271{
3272 struct drm_device *dev = crtc->dev;
3273 struct drm_i915_private *dev_priv = dev->dev_private;
3274 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3275 bool pending;
3276
3277 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3278 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3279 return false;
3280
5e2d7afc 3281 spin_lock_irq(&dev->event_lock);
7d5e3799 3282 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3283 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3284
3285 return pending;
3286}
3287
e30e8f75
GP		 3288static void intel_update_pipe_size(struct intel_crtc *crtc)
3289{
3290 struct drm_device *dev = crtc->base.dev;
3291 struct drm_i915_private *dev_priv = dev->dev_private;
3292 const struct drm_display_mode *adjusted_mode;
3293
3294 if (!i915.fastboot)
3295 return;
3296
3297 /*
3298 * Update pipe size and adjust fitter if needed: the reason for this is
3299 * that in compute_mode_changes we check the native mode (not the pfit
3300 * mode) to see if we can flip rather than do a full mode set. In the
3301 * fastboot case, we'll flip, but if we don't update the pipesrc and
3302 * pfit state, we'll end up with a big fb scanned out into the wrong
3303 * sized surface.
3304 *
3305 * To fix this properly, we need to hoist the checks up into
3306 * compute_mode_changes (or above), check the actual pfit state and
3307 * whether the platform allows pfit disable with pipe active, and only
3308 * then update the pipesrc and pfit state, even on the flip path.
3309 */
3310
6e3c9717 3311 adjusted_mode = &crtc->config->base.adjusted_mode;
e30e8f75
GP		 3312
3313 I915_WRITE(PIPESRC(crtc->pipe),
3314 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3315 (adjusted_mode->crtc_vdisplay - 1));
6e3c9717 3316 if (!crtc->config->pch_pfit.enabled &&
409ee761
ACO		 3317 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3318 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
e30e8f75
GP		 3319 I915_WRITE(PF_CTL(crtc->pipe), 0);
3320 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3321 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3322 }
6e3c9717
ACO		 3323 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3324 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
e30e8f75
GP		 3325}
3326
5e84e1a4
ZW		 3327static void intel_fdi_normal_train(struct drm_crtc *crtc)
3328{
3329 struct drm_device *dev = crtc->dev;
3330 struct drm_i915_private *dev_priv = dev->dev_private;
3331 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3332 int pipe = intel_crtc->pipe;
3333 u32 reg, temp;
3334
3335 /* enable normal train */
3336 reg = FDI_TX_CTL(pipe);
3337 temp = I915_READ(reg);
61e499bf 3338 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3339 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3340 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3341 } else {
3342 temp &= ~FDI_LINK_TRAIN_NONE;
3343 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3344 }
5e84e1a4
ZW		 3345 I915_WRITE(reg, temp);
3346
3347 reg = FDI_RX_CTL(pipe);
3348 temp = I915_READ(reg);
3349 if (HAS_PCH_CPT(dev)) {
3350 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3351 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3352 } else {
3353 temp &= ~FDI_LINK_TRAIN_NONE;
3354 temp |= FDI_LINK_TRAIN_NONE;
3355 }
3356 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3357
3358 /* wait one idle pattern time */
3359 POSTING_READ(reg);
3360 udelay(1000);
357555c0
JB		 3361
3362 /* IVB wants error correction enabled */
3363 if (IS_IVYBRIDGE(dev))
3364 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3365 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3366}
3367
8db9d77b
ZW		 3368/* The FDI link training functions for ILK/Ibexpeak. */
3369static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3370{
3371 struct drm_device *dev = crtc->dev;
3372 struct drm_i915_private *dev_priv = dev->dev_private;
3373 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3374 int pipe = intel_crtc->pipe;
5eddb70b 3375 u32 reg, temp, tries;
8db9d77b 3376
1c8562f6 3377 /* FDI needs bits from pipe first */
0fc932b8 3378 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3379
e1a44743
AJ		 3380 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3381 for train result */
5eddb70b
CW		 3382 reg = FDI_RX_IMR(pipe);
3383 temp = I915_READ(reg);
e1a44743
AJ		 3384 temp &= ~FDI_RX_SYMBOL_LOCK;
3385 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3386 I915_WRITE(reg, temp);
3387 I915_READ(reg);
e1a44743
AJ		 3388 udelay(150);
3389
8db9d77b 3390 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3391 reg = FDI_TX_CTL(pipe);
3392 temp = I915_READ(reg);
627eb5a3 3393 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3394 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3395 temp &= ~FDI_LINK_TRAIN_NONE;
3396 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3397 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3398
5eddb70b
CW		 3399 reg = FDI_RX_CTL(pipe);
3400 temp = I915_READ(reg);
8db9d77b
ZW		 3401 temp &= ~FDI_LINK_TRAIN_NONE;
3402 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3403 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3404
3405 POSTING_READ(reg);
8db9d77b
ZW		 3406 udelay(150);
3407
5b2adf89 3408 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3409 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3410 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3411 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3412
5eddb70b 3413 reg = FDI_RX_IIR(pipe);
e1a44743 3414 for (tries = 0; tries < 5; tries++) {
5eddb70b 3415 temp = I915_READ(reg);
8db9d77b
ZW		 3416 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3417
3418 if ((temp & FDI_RX_BIT_LOCK)) {
3419 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3420 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3421 break;
3422 }
8db9d77b 3423 }
e1a44743 3424 if (tries == 5)
5eddb70b 3425 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3426
3427 /* Train 2 */
5eddb70b
CW		 3428 reg = FDI_TX_CTL(pipe);
3429 temp = I915_READ(reg);
8db9d77b
ZW		 3430 temp &= ~FDI_LINK_TRAIN_NONE;
3431 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3432 I915_WRITE(reg, temp);
8db9d77b 3433
5eddb70b
CW		 3434 reg = FDI_RX_CTL(pipe);
3435 temp = I915_READ(reg);
8db9d77b
ZW		 3436 temp &= ~FDI_LINK_TRAIN_NONE;
3437 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3438 I915_WRITE(reg, temp);
8db9d77b 3439
5eddb70b
CW		 3440 POSTING_READ(reg);
3441 udelay(150);
8db9d77b 3442
5eddb70b 3443 reg = FDI_RX_IIR(pipe);
e1a44743 3444 for (tries = 0; tries < 5; tries++) {
5eddb70b 3445 temp = I915_READ(reg);
8db9d77b
ZW		 3446 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3447
3448 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3449 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3450 DRM_DEBUG_KMS("FDI train 2 done.\n");
3451 break;
3452 }
8db9d77b 3453 }
e1a44743 3454 if (tries == 5)
5eddb70b 3455 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3456
3457 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3458
8db9d77b
ZW		 3459}
3460
0206e353 3461static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3462 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3463 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3464 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3465 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3466};
3467
3468/* The FDI link training functions for SNB/Cougarpoint. */
3469static void gen6_fdi_link_train(struct drm_crtc *crtc)
3470{
3471 struct drm_device *dev = crtc->dev;
3472 struct drm_i915_private *dev_priv = dev->dev_private;
3473 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3474 int pipe = intel_crtc->pipe;
fa37d39e 3475 u32 reg, temp, i, retry;
8db9d77b 3476
e1a44743
AJ		 3477 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3478 for train result */
5eddb70b
CW		 3479 reg = FDI_RX_IMR(pipe);
3480 temp = I915_READ(reg);
e1a44743
AJ		 3481 temp &= ~FDI_RX_SYMBOL_LOCK;
3482 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3483 I915_WRITE(reg, temp);
3484
3485 POSTING_READ(reg);
e1a44743
AJ		 3486 udelay(150);
3487
8db9d77b 3488 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3489 reg = FDI_TX_CTL(pipe);
3490 temp = I915_READ(reg);
627eb5a3 3491 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3492 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3493 temp &= ~FDI_LINK_TRAIN_NONE;
3494 temp |= FDI_LINK_TRAIN_PATTERN_1;
3495 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3496 /* SNB-B */
3497 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3498 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3499
d74cf324
DV		 3500 I915_WRITE(FDI_RX_MISC(pipe),
3501 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3502
5eddb70b
CW		 3503 reg = FDI_RX_CTL(pipe);
3504 temp = I915_READ(reg);
8db9d77b
ZW		 3505 if (HAS_PCH_CPT(dev)) {
3506 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3507 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3508 } else {
3509 temp &= ~FDI_LINK_TRAIN_NONE;
3510 temp |= FDI_LINK_TRAIN_PATTERN_1;
3511 }
5eddb70b
CW		 3512 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3513
3514 POSTING_READ(reg);
8db9d77b
ZW		 3515 udelay(150);
3516
0206e353 3517 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3518 reg = FDI_TX_CTL(pipe);
3519 temp = I915_READ(reg);
8db9d77b
ZW		 3520 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3521 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3522 I915_WRITE(reg, temp);
3523
3524 POSTING_READ(reg);
8db9d77b
ZW		 3525 udelay(500);
3526
fa37d39e
SP		 3527 for (retry = 0; retry < 5; retry++) {
3528 reg = FDI_RX_IIR(pipe);
3529 temp = I915_READ(reg);
3530 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3531 if (temp & FDI_RX_BIT_LOCK) {
3532 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3533 DRM_DEBUG_KMS("FDI train 1 done.\n");
3534 break;
3535 }
3536 udelay(50);
8db9d77b 3537 }
fa37d39e
SP		 3538 if (retry < 5)
3539 break;
8db9d77b
ZW		 3540 }
3541 if (i == 4)
5eddb70b 3542 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3543
3544 /* Train 2 */
5eddb70b
CW		 3545 reg = FDI_TX_CTL(pipe);
3546 temp = I915_READ(reg);
8db9d77b
ZW		 3547 temp &= ~FDI_LINK_TRAIN_NONE;
3548 temp |= FDI_LINK_TRAIN_PATTERN_2;
3549 if (IS_GEN6(dev)) {
3550 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3551 /* SNB-B */
3552 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3553 }
5eddb70b 3554 I915_WRITE(reg, temp);
8db9d77b 3555
5eddb70b
CW		 3556 reg = FDI_RX_CTL(pipe);
3557 temp = I915_READ(reg);
8db9d77b
ZW		 3558 if (HAS_PCH_CPT(dev)) {
3559 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3560 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3561 } else {
3562 temp &= ~FDI_LINK_TRAIN_NONE;
3563 temp |= FDI_LINK_TRAIN_PATTERN_2;
3564 }
5eddb70b
CW		 3565 I915_WRITE(reg, temp);
3566
3567 POSTING_READ(reg);
8db9d77b
ZW		 3568 udelay(150);
3569
0206e353 3570 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3571 reg = FDI_TX_CTL(pipe);
3572 temp = I915_READ(reg);
8db9d77b
ZW		 3573 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3574 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3575 I915_WRITE(reg, temp);
3576
3577 POSTING_READ(reg);
8db9d77b
ZW		 3578 udelay(500);
3579
fa37d39e
SP		 3580 for (retry = 0; retry < 5; retry++) {
3581 reg = FDI_RX_IIR(pipe);
3582 temp = I915_READ(reg);
3583 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3584 if (temp & FDI_RX_SYMBOL_LOCK) {
3585 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3586 DRM_DEBUG_KMS("FDI train 2 done.\n");
3587 break;
3588 }
3589 udelay(50);
8db9d77b 3590 }
fa37d39e
SP		 3591 if (retry < 5)
3592 break;
8db9d77b
ZW		 3593 }
3594 if (i == 4)
5eddb70b 3595 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3596
3597 DRM_DEBUG_KMS("FDI train done.\n");
3598}
3599
357555c0
JB		 3600/* Manual link training for Ivy Bridge A0 parts */
3601static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3602{
3603 struct drm_device *dev = crtc->dev;
3604 struct drm_i915_private *dev_priv = dev->dev_private;
3605 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3606 int pipe = intel_crtc->pipe;
139ccd3f 3607 u32 reg, temp, i, j;
357555c0
JB		 3608
3609 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3610 for train result */
3611 reg = FDI_RX_IMR(pipe);
3612 temp = I915_READ(reg);
3613 temp &= ~FDI_RX_SYMBOL_LOCK;
3614 temp &= ~FDI_RX_BIT_LOCK;
3615 I915_WRITE(reg, temp);
3616
3617 POSTING_READ(reg);
3618 udelay(150);
3619
01a415fd
DV		 3620 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3621 I915_READ(FDI_RX_IIR(pipe)));
3622
139ccd3f
JB		 3623 /* Try each vswing and preemphasis setting twice before moving on */
3624 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3625 /* disable first in case we need to retry */
3626 reg = FDI_TX_CTL(pipe);
3627 temp = I915_READ(reg);
3628 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3629 temp &= ~FDI_TX_ENABLE;
3630 I915_WRITE(reg, temp);
357555c0 3631
139ccd3f
JB		 3632 reg = FDI_RX_CTL(pipe);
3633 temp = I915_READ(reg);
3634 temp &= ~FDI_LINK_TRAIN_AUTO;
3635 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3636 temp &= ~FDI_RX_ENABLE;
3637 I915_WRITE(reg, temp);
357555c0 3638
139ccd3f 3639 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3640 reg = FDI_TX_CTL(pipe);
3641 temp = I915_READ(reg);
139ccd3f 3642 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3643 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3644 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3645 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3646 temp |= snb_b_fdi_train_param[j/2];
3647 temp |= FDI_COMPOSITE_SYNC;
3648 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3649
139ccd3f
JB		 3650 I915_WRITE(FDI_RX_MISC(pipe),
3651 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3652
139ccd3f 3653 reg = FDI_RX_CTL(pipe);
357555c0 3654 temp = I915_READ(reg);
139ccd3f
JB		 3655 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3656 temp |= FDI_COMPOSITE_SYNC;
3657 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3658
139ccd3f
JB		 3659 POSTING_READ(reg);
3660 udelay(1); /* should be 0.5us */
357555c0 3661
139ccd3f
JB		 3662 for (i = 0; i < 4; i++) {
3663 reg = FDI_RX_IIR(pipe);
3664 temp = I915_READ(reg);
3665 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3666
139ccd3f
JB		 3667 if (temp & FDI_RX_BIT_LOCK ||
3668 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3669 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3670 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3671 i);
3672 break;
3673 }
3674 udelay(1); /* should be 0.5us */
3675 }
3676 if (i == 4) {
3677 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3678 continue;
3679 }
357555c0 3680
139ccd3f 3681 /* Train 2 */
357555c0
JB		 3682 reg = FDI_TX_CTL(pipe);
3683 temp = I915_READ(reg);
139ccd3f
JB		 3684 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3685 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3686 I915_WRITE(reg, temp);
3687
3688 reg = FDI_RX_CTL(pipe);
3689 temp = I915_READ(reg);
3690 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3691 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3692 I915_WRITE(reg, temp);
3693
3694 POSTING_READ(reg);
139ccd3f 3695 udelay(2); /* should be 1.5us */
357555c0 3696
139ccd3f
JB		 3697 for (i = 0; i < 4; i++) {
3698 reg = FDI_RX_IIR(pipe);
3699 temp = I915_READ(reg);
3700 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3701
139ccd3f
JB		 3702 if (temp & FDI_RX_SYMBOL_LOCK ||
3703 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3704 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3705 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3706 i);
3707 goto train_done;
3708 }
3709 udelay(2); /* should be 1.5us */
357555c0 3710 }
139ccd3f
JB		 3711 if (i == 4)
3712 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3713 }
357555c0 3714
139ccd3f 3715train_done:
357555c0
JB		 3716 DRM_DEBUG_KMS("FDI train done.\n");
3717}
3718
88cefb6c 3719static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3720{
88cefb6c 3721 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3722 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3723 int pipe = intel_crtc->pipe;
5eddb70b 3724 u32 reg, temp;
79e53945 3725
c64e311e 3726
c98e9dcf 3727 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3728 reg = FDI_RX_CTL(pipe);
3729 temp = I915_READ(reg);
627eb5a3 3730 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3731 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3732 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3733 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3734
3735 POSTING_READ(reg);
c98e9dcf
JB		 3736 udelay(200);
3737
3738 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3739 temp = I915_READ(reg);
3740 I915_WRITE(reg, temp | FDI_PCDCLK);
3741
3742 POSTING_READ(reg);
c98e9dcf
JB		 3743 udelay(200);
3744
20749730
PZ		 3745 /* Enable CPU FDI TX PLL, always on for Ironlake */
3746 reg = FDI_TX_CTL(pipe);
3747 temp = I915_READ(reg);
3748 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3749 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3750
20749730
PZ		 3751 POSTING_READ(reg);
3752 udelay(100);
6be4a607 3753 }
0e23b99d
JB		 3754}
3755
88cefb6c
DV		 3756static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3757{
3758 struct drm_device *dev = intel_crtc->base.dev;
3759 struct drm_i915_private *dev_priv = dev->dev_private;
3760 int pipe = intel_crtc->pipe;
3761 u32 reg, temp;
3762
3763 /* Switch from PCDclk to Rawclk */
3764 reg = FDI_RX_CTL(pipe);
3765 temp = I915_READ(reg);
3766 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3767
3768 /* Disable CPU FDI TX PLL */
3769 reg = FDI_TX_CTL(pipe);
3770 temp = I915_READ(reg);
3771 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3772
3773 POSTING_READ(reg);
3774 udelay(100);
3775
3776 reg = FDI_RX_CTL(pipe);
3777 temp = I915_READ(reg);
3778 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3779
3780 /* Wait for the clocks to turn off. */
3781 POSTING_READ(reg);
3782 udelay(100);
3783}
3784
0fc932b8
JB		 3785static void ironlake_fdi_disable(struct drm_crtc *crtc)
3786{
3787 struct drm_device *dev = crtc->dev;
3788 struct drm_i915_private *dev_priv = dev->dev_private;
3789 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3790 int pipe = intel_crtc->pipe;
3791 u32 reg, temp;
3792
3793 /* disable CPU FDI tx and PCH FDI rx */
3794 reg = FDI_TX_CTL(pipe);
3795 temp = I915_READ(reg);
3796 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3797 POSTING_READ(reg);
3798
3799 reg = FDI_RX_CTL(pipe);
3800 temp = I915_READ(reg);
3801 temp &= ~(0x7 << 16);
dfd07d72 3802 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3803 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3804
3805 POSTING_READ(reg);
3806 udelay(100);
3807
3808 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3809 if (HAS_PCH_IBX(dev))
6f06ce18 3810 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3811
3812 /* still set train pattern 1 */
3813 reg = FDI_TX_CTL(pipe);
3814 temp = I915_READ(reg);
3815 temp &= ~FDI_LINK_TRAIN_NONE;
3816 temp |= FDI_LINK_TRAIN_PATTERN_1;
3817 I915_WRITE(reg, temp);
3818
3819 reg = FDI_RX_CTL(pipe);
3820 temp = I915_READ(reg);
3821 if (HAS_PCH_CPT(dev)) {
3822 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3823 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3824 } else {
3825 temp &= ~FDI_LINK_TRAIN_NONE;
3826 temp |= FDI_LINK_TRAIN_PATTERN_1;
3827 }
3828 /* BPC in FDI rx is consistent with that in PIPECONF */
3829 temp &= ~(0x07 << 16);
dfd07d72 3830 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3831 I915_WRITE(reg, temp);
3832
3833 POSTING_READ(reg);
3834 udelay(100);
3835}
3836
5dce5b93
CW		 3837bool intel_has_pending_fb_unpin(struct drm_device *dev)
3838{
3839 struct intel_crtc *crtc;
3840
3841 /* Note that we don't need to be called with mode_config.lock here
3842 * as our list of CRTC objects is static for the lifetime of the
3843 * device and so cannot disappear as we iterate. Similarly, we can
3844 * happily treat the predicates as racy, atomic checks as userspace
3845 * cannot claim and pin a new fb without at least acquring the
3846 * struct_mutex and so serialising with us.
3847 */
d3fcc808 3848 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3849 if (atomic_read(&crtc->unpin_work_count) == 0)
3850 continue;
3851
3852 if (crtc->unpin_work)
3853 intel_wait_for_vblank(dev, crtc->pipe);
3854
3855 return true;
3856 }
3857
3858 return false;
3859}
3860
d6bbafa1
CW		 3861static void page_flip_completed(struct intel_crtc *intel_crtc)
3862{
3863 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3864 struct intel_unpin_work *work = intel_crtc->unpin_work;
3865
3866 /* ensure that the unpin work is consistent wrt ->pending. */
3867 smp_rmb();
3868 intel_crtc->unpin_work = NULL;
3869
3870 if (work->event)
3871 drm_send_vblank_event(intel_crtc->base.dev,
3872 intel_crtc->pipe,
3873 work->event);
3874
3875 drm_crtc_vblank_put(&intel_crtc->base);
3876
3877 wake_up_all(&dev_priv->pending_flip_queue);
3878 queue_work(dev_priv->wq, &work->work);
3879
3880 trace_i915_flip_complete(intel_crtc->plane,
3881 work->pending_flip_obj);
3882}
3883
46a55d30 3884void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3885{
0f91128d 3886 struct drm_device *dev = crtc->dev;
5bb61643 3887 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3888
2c10d571 3889 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW		 3890 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3891 !intel_crtc_has_pending_flip(crtc),
3892 60*HZ) == 0)) {
3893 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3894
5e2d7afc 3895 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3896 if (intel_crtc->unpin_work) {
3897 WARN_ONCE(1, "Removing stuck page flip\n");
3898 page_flip_completed(intel_crtc);
3899 }
5e2d7afc 3900 spin_unlock_irq(&dev->event_lock);
9c787942 3901 }
5bb61643 3902
975d568a
CW		 3903 if (crtc->primary->fb) {
3904 mutex_lock(&dev->struct_mutex);
3905 intel_finish_fb(crtc->primary->fb);
3906 mutex_unlock(&dev->struct_mutex);
3907 }
e6c3a2a6
CW		 3908}
3909
e615efe4
ED		 3910/* Program iCLKIP clock to the desired frequency */
3911static void lpt_program_iclkip(struct drm_crtc *crtc)
3912{
3913 struct drm_device *dev = crtc->dev;
3914 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3915 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3916 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3917 u32 temp;
3918
a580516d 3919 mutex_lock(&dev_priv->sb_lock);
09153000 3920
e615efe4
ED		 3921 /* It is necessary to ungate the pixclk gate prior to programming
3922 * the divisors, and gate it back when it is done.
3923 */
3924 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3925
3926 /* Disable SSCCTL */
3927 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3928 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3929 SBI_SSCCTL_DISABLE,
3930 SBI_ICLK);
e615efe4
ED		 3931
3932 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3933 if (clock == 20000) {
e615efe4
ED		 3934 auxdiv = 1;
3935 divsel = 0x41;
3936 phaseinc = 0x20;
3937 } else {
3938 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3939 * but the adjusted_mode->crtc_clock in in KHz. To get the
3940 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3941 * convert the virtual clock precision to KHz here for higher
3942 * precision.
3943 */
3944 u32 iclk_virtual_root_freq = 172800 * 1000;
3945 u32 iclk_pi_range = 64;
3946 u32 desired_divisor, msb_divisor_value, pi_value;
3947
12d7ceed 3948 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3949 msb_divisor_value = desired_divisor / iclk_pi_range;
3950 pi_value = desired_divisor % iclk_pi_range;
3951
3952 auxdiv = 0;
3953 divsel = msb_divisor_value - 2;
3954 phaseinc = pi_value;
3955 }
3956
3957 /* This should not happen with any sane values */
3958 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3959 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3960 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3961 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3962
3963 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3964 clock,
e615efe4
ED		 3965 auxdiv,
3966 divsel,
3967 phasedir,
3968 phaseinc);
3969
3970 /* Program SSCDIVINTPHASE6 */
988d6ee8 3971 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3972 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3973 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3974 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3975 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3976 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3977 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3978 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3979
3980 /* Program SSCAUXDIV */
988d6ee8 3981 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3982 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3983 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3984 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3985
3986 /* Enable modulator and associated divider */
988d6ee8 3987 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3988 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3989 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3990
3991 /* Wait for initialization time */
3992 udelay(24);
3993
3994 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000 3995
a580516d 3996 mutex_unlock(&dev_priv->sb_lock);
e615efe4
ED		 3997}
3998
275f01b2
DV		 3999static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4000 enum pipe pch_transcoder)
4001{
4002 struct drm_device *dev = crtc->base.dev;
4003 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 4004 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 4005
4006 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4007 I915_READ(HTOTAL(cpu_transcoder)));
4008 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4009 I915_READ(HBLANK(cpu_transcoder)));
4010 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4011 I915_READ(HSYNC(cpu_transcoder)));
4012
4013 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4014 I915_READ(VTOTAL(cpu_transcoder)));
4015 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4016 I915_READ(VBLANK(cpu_transcoder)));
4017 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4018 I915_READ(VSYNC(cpu_transcoder)));
4019 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4020 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4021}
4022
003632d9 4023static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 4024{
4025 struct drm_i915_private *dev_priv = dev->dev_private;
4026 uint32_t temp;
4027
4028 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 4029 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 4030 return;
4031
4032 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4033 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4034
003632d9
ACO		 4035 temp &= ~FDI_BC_BIFURCATION_SELECT;
4036 if (enable)
4037 temp |= FDI_BC_BIFURCATION_SELECT;
4038
4039 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 4040 I915_WRITE(SOUTH_CHICKEN1, temp);
4041 POSTING_READ(SOUTH_CHICKEN1);
4042}
4043
4044static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4045{
4046 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 4047
4048 switch (intel_crtc->pipe) {
4049 case PIPE_A:
4050 break;
4051 case PIPE_B:
6e3c9717 4052 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4053 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4054 else
003632d9 4055 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4056
4057 break;
4058 case PIPE_C:
003632d9 4059 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4060
4061 break;
4062 default:
4063 BUG();
4064 }
4065}
4066
f67a559d
JB		 4067/*
4068 * Enable PCH resources required for PCH ports:
4069 * - PCH PLLs
4070 * - FDI training & RX/TX
4071 * - update transcoder timings
4072 * - DP transcoding bits
4073 * - transcoder
4074 */
4075static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 4076{
4077 struct drm_device *dev = crtc->dev;
4078 struct drm_i915_private *dev_priv = dev->dev_private;
4079 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4080 int pipe = intel_crtc->pipe;
ee7b9f93 4081 u32 reg, temp;
2c07245f 4082
ab9412ba 4083 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4084
1fbc0d78
DV		 4085 if (IS_IVYBRIDGE(dev))
4086 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4087
cd986abb
DV		 4088 /* Write the TU size bits before fdi link training, so that error
4089 * detection works. */
4090 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4091 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4092
c98e9dcf 4093 /* For PCH output, training FDI link */
674cf967 4094 dev_priv->display.fdi_link_train(crtc);
2c07245f 4095
3ad8a208
DV		 4096 /* We need to program the right clock selection before writing the pixel
4097 * mutliplier into the DPLL. */
303b81e0 4098 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4099 u32 sel;
4b645f14 4100
c98e9dcf 4101 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4102 temp |= TRANS_DPLL_ENABLE(pipe);
4103 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4104 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4105 temp |= sel;
4106 else
4107 temp &= ~sel;
c98e9dcf 4108 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4109 }
5eddb70b 4110
3ad8a208
DV		 4111 /* XXX: pch pll's can be enabled any time before we enable the PCH
4112 * transcoder, and we actually should do this to not upset any PCH
4113 * transcoder that already use the clock when we share it.
4114 *
4115 * Note that enable_shared_dpll tries to do the right thing, but
4116 * get_shared_dpll unconditionally resets the pll - we need that to have
4117 * the right LVDS enable sequence. */
85b3894f 4118 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4119
d9b6cb56
JB		 4120 /* set transcoder timing, panel must allow it */
4121 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4122 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4123
303b81e0 4124 intel_fdi_normal_train(crtc);
5e84e1a4 4125
c98e9dcf 4126 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4127 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4128 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4129 reg = TRANS_DP_CTL(pipe);
4130 temp = I915_READ(reg);
4131 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4132 TRANS_DP_SYNC_MASK |
4133 TRANS_DP_BPC_MASK);
e3ef4479 4134 temp |= TRANS_DP_OUTPUT_ENABLE;
9325c9f0 4135 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4136
4137 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4138 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4139 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4140 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4141
4142 switch (intel_trans_dp_port_sel(crtc)) {
4143 case PCH_DP_B:
5eddb70b 4144 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4145 break;
4146 case PCH_DP_C:
5eddb70b 4147 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4148 break;
4149 case PCH_DP_D:
5eddb70b 4150 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4151 break;
4152 default:
e95d41e1 4153 BUG();
32f9d658 4154 }
2c07245f 4155
5eddb70b 4156 I915_WRITE(reg, temp);
6be4a607 4157 }
b52eb4dc 4158
b8a4f404 4159 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4160}
4161
1507e5bd
PZ		 4162static void lpt_pch_enable(struct drm_crtc *crtc)
4163{
4164 struct drm_device *dev = crtc->dev;
4165 struct drm_i915_private *dev_priv = dev->dev_private;
4166 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4167 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4168
ab9412ba 4169 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4170
8c52b5e8 4171 lpt_program_iclkip(crtc);
1507e5bd 4172
0540e488 4173 /* Set transcoder timing. */
275f01b2 4174 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4175
937bb610 4176 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4177}
4178
190f68c5
ACO		 4179struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4180 struct intel_crtc_state *crtc_state)
ee7b9f93 4181{
e2b78267 4182 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4183 struct intel_shared_dpll *pll;
e2b78267 4184 enum intel_dpll_id i;
ee7b9f93 4185
98b6bd99
DV		 4186 if (HAS_PCH_IBX(dev_priv->dev)) {
4187 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4188 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4189 pll = &dev_priv->shared_dplls[i];
98b6bd99 4190
46edb027
DV		 4191 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4192 crtc->base.base.id, pll->name);
98b6bd99 4193
8bd31e67 4194 WARN_ON(pll->new_config->crtc_mask);
f2a69f44 4195
98b6bd99
DV		 4196 goto found;
4197 }
4198
bcddf610
S		 4199 if (IS_BROXTON(dev_priv->dev)) {
4200 /* PLL is attached to port in bxt */
4201 struct intel_encoder *encoder;
4202 struct intel_digital_port *intel_dig_port;
4203
4204 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4205 if (WARN_ON(!encoder))
4206 return NULL;
4207
4208 intel_dig_port = enc_to_dig_port(&encoder->base);
4209 /* 1:1 mapping between ports and PLLs */
4210 i = (enum intel_dpll_id)intel_dig_port->port;
4211 pll = &dev_priv->shared_dplls[i];
4212 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4213 crtc->base.base.id, pll->name);
4214 WARN_ON(pll->new_config->crtc_mask);
4215
4216 goto found;
4217 }
4218
e72f9fbf
DV		 4219 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4220 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4221
4222 /* Only want to check enabled timings first */
8bd31e67 4223 if (pll->new_config->crtc_mask == 0)
ee7b9f93
JB		 4224 continue;
4225
190f68c5 4226 if (memcmp(&crtc_state->dpll_hw_state,
8bd31e67
ACO		 4227 &pll->new_config->hw_state,
4228 sizeof(pll->new_config->hw_state)) == 0) {
4229 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4230 crtc->base.base.id, pll->name,
8bd31e67
ACO		 4231 pll->new_config->crtc_mask,
4232 pll->active);
ee7b9f93
JB		 4233 goto found;
4234 }
4235 }
4236
4237 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4238 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4239 pll = &dev_priv->shared_dplls[i];
8bd31e67 4240 if (pll->new_config->crtc_mask == 0) {
46edb027
DV		 4241 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4242 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4243 goto found;
4244 }
4245 }
4246
4247 return NULL;
4248
4249found:
8bd31e67 4250 if (pll->new_config->crtc_mask == 0)
190f68c5 4251 pll->new_config->hw_state = crtc_state->dpll_hw_state;
f2a69f44 4252
190f68c5 4253 crtc_state->shared_dpll = i;
46edb027
DV		 4254 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4255 pipe_name(crtc->pipe));
ee7b9f93 4256
8bd31e67 4257 pll->new_config->crtc_mask |= 1 << crtc->pipe;
e04c7350 4258
ee7b9f93
JB		 4259 return pll;
4260}
4261
8bd31e67
ACO		 4262/**
4263 * intel_shared_dpll_start_config - start a new PLL staged config
4264 * @dev_priv: DRM device
4265 * @clear_pipes: mask of pipes that will have their PLLs freed
4266 *
4267 * Starts a new PLL staged config, copying the current config but
4268 * releasing the references of pipes specified in clear_pipes.
4269 */
4270static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4271 unsigned clear_pipes)
4272{
4273 struct intel_shared_dpll *pll;
4274 enum intel_dpll_id i;
4275
4276 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4277 pll = &dev_priv->shared_dplls[i];
4278
4279 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4280 GFP_KERNEL);
4281 if (!pll->new_config)
4282 goto cleanup;
4283
4284 pll->new_config->crtc_mask &= ~clear_pipes;
4285 }
4286
4287 return 0;
4288
4289cleanup:
4290 while (--i >= 0) {
4291 pll = &dev_priv->shared_dplls[i];
f354d733 4292 kfree(pll->new_config);
8bd31e67
ACO		 4293 pll->new_config = NULL;
4294 }
4295
4296 return -ENOMEM;
4297}
4298
4299static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4300{
4301 struct intel_shared_dpll *pll;
4302 enum intel_dpll_id i;
4303
4304 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4305 pll = &dev_priv->shared_dplls[i];
4306
4307 WARN_ON(pll->new_config == &pll->config);
4308
4309 pll->config = *pll->new_config;
4310 kfree(pll->new_config);
4311 pll->new_config = NULL;
4312 }
4313}
4314
4315static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4316{
4317 struct intel_shared_dpll *pll;
4318 enum intel_dpll_id i;
4319
4320 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4321 pll = &dev_priv->shared_dplls[i];
4322
4323 WARN_ON(pll->new_config == &pll->config);
4324
4325 kfree(pll->new_config);
4326 pll->new_config = NULL;
4327 }
4328}
4329
a1520318 4330static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4331{
4332 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4333 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4334 u32 temp;
4335
4336 temp = I915_READ(dslreg);
4337 udelay(500);
4338 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4339 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4340 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4341 }
4342}
4343
a1b2278e
CK		 4344/**
4345 * skl_update_scaler_users - Stages update to crtc's scaler state
4346 * @intel_crtc: crtc
4347 * @crtc_state: crtc_state
4348 * @plane: plane (NULL indicates crtc is requesting update)
4349 * @plane_state: plane's state
4350 * @force_detach: request unconditional detachment of scaler
4351 *
4352 * This function updates scaler state for requested plane or crtc.
4353 * To request scaler usage update for a plane, caller shall pass plane pointer.
4354 * To request scaler usage update for crtc, caller shall pass plane pointer
4355 * as NULL.
4356 *
4357 * Return
4358 * 0 - scaler_usage updated successfully
4359 * error - requested scaling cannot be supported or other error condition
4360 */
4361int
4362skl_update_scaler_users(
4363 struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state,
4364 struct intel_plane *intel_plane, struct intel_plane_state *plane_state,
4365 int force_detach)
4366{
4367 int need_scaling;
4368 int idx;
4369 int src_w, src_h, dst_w, dst_h;
4370 int *scaler_id;
4371 struct drm_framebuffer *fb;
4372 struct intel_crtc_scaler_state *scaler_state;
6156a456 4373 unsigned int rotation;
a1b2278e
CK		 4374
4375 if (!intel_crtc || !crtc_state)
4376 return 0;
4377
4378 scaler_state = &crtc_state->scaler_state;
4379
4380 idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX;
4381 fb = intel_plane ? plane_state->base.fb : NULL;
4382
4383 if (intel_plane) {
4384 src_w = drm_rect_width(&plane_state->src) >> 16;
4385 src_h = drm_rect_height(&plane_state->src) >> 16;
4386 dst_w = drm_rect_width(&plane_state->dst);
4387 dst_h = drm_rect_height(&plane_state->dst);
4388 scaler_id = &plane_state->scaler_id;
6156a456 4389 rotation = plane_state->base.rotation;
a1b2278e
CK		 4390 } else {
4391 struct drm_display_mode *adjusted_mode =
4392 &crtc_state->base.adjusted_mode;
4393 src_w = crtc_state->pipe_src_w;
4394 src_h = crtc_state->pipe_src_h;
4395 dst_w = adjusted_mode->hdisplay;
4396 dst_h = adjusted_mode->vdisplay;
4397 scaler_id = &scaler_state->scaler_id;
6156a456 4398 rotation = DRM_ROTATE_0;
a1b2278e 4399 }
6156a456
CK		 4400
4401 need_scaling = intel_rotation_90_or_270(rotation) ?
4402 (src_h != dst_w || src_w != dst_h):
4403 (src_w != dst_w || src_h != dst_h);
a1b2278e
CK		 4404
4405 /*
4406 * if plane is being disabled or scaler is no more required or force detach
4407 * - free scaler binded to this plane/crtc
4408 * - in order to do this, update crtc->scaler_usage
4409 *
4410 * Here scaler state in crtc_state is set free so that
4411 * scaler can be assigned to other user. Actual register
4412 * update to free the scaler is done in plane/panel-fit programming.
4413 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4414 */
4415 if (force_detach || !need_scaling || (intel_plane &&
4416 (!fb || !plane_state->visible))) {
4417 if (*scaler_id >= 0) {
4418 scaler_state->scaler_users &= ~(1 << idx);
4419 scaler_state->scalers[*scaler_id].in_use = 0;
4420
4421 DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4422 "crtc_state = %p scaler_users = 0x%x\n",
4423 intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC",
4424 intel_plane ? intel_plane->base.base.id :
4425 intel_crtc->base.base.id, crtc_state,
4426 scaler_state->scaler_users);
4427 *scaler_id = -1;
4428 }
4429 return 0;
4430 }
4431
4432 /* range checks */
4433 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4434 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4435
4436 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4437 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4438 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4439 "size is out of scaler range\n",
4440 intel_plane ? "PLANE" : "CRTC",
4441 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4442 intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h);
4443 return -EINVAL;
4444 }
4445
4446 /* check colorkey */
225c228a
CK		 4447 if (WARN_ON(intel_plane &&
4448 intel_plane->ckey.flags != I915_SET_COLORKEY_NONE)) {
4449 DRM_DEBUG_KMS("PLANE:%d scaling %ux%u->%ux%u not allowed with colorkey",
4450 intel_plane->base.base.id, src_w, src_h, dst_w, dst_h);
a1b2278e
CK		 4451 return -EINVAL;
4452 }
4453
4454 /* Check src format */
4455 if (intel_plane) {
4456 switch (fb->pixel_format) {
4457 case DRM_FORMAT_RGB565:
4458 case DRM_FORMAT_XBGR8888:
4459 case DRM_FORMAT_XRGB8888:
4460 case DRM_FORMAT_ABGR8888:
4461 case DRM_FORMAT_ARGB8888:
4462 case DRM_FORMAT_XRGB2101010:
a1b2278e 4463 case DRM_FORMAT_XBGR2101010:
a1b2278e
CK		 4464 case DRM_FORMAT_YUYV:
4465 case DRM_FORMAT_YVYU:
4466 case DRM_FORMAT_UYVY:
4467 case DRM_FORMAT_VYUY:
4468 break;
4469 default:
4470 DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4471 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4472 return -EINVAL;
4473 }
4474 }
4475
4476 /* mark this plane as a scaler user in crtc_state */
4477 scaler_state->scaler_users |= (1 << idx);
4478 DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4479 "crtc_state = %p scaler_users = 0x%x\n",
4480 intel_plane ? "PLANE" : "CRTC",
4481 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4482 src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users);
4483 return 0;
4484}
4485
4486static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
bd2e244f
JB		 4487{
4488 struct drm_device *dev = crtc->base.dev;
4489 struct drm_i915_private *dev_priv = dev->dev_private;
4490 int pipe = crtc->pipe;
a1b2278e
CK		 4491 struct intel_crtc_scaler_state *scaler_state =
4492 &crtc->config->scaler_state;
4493
4494 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4495
4496 /* To update pfit, first update scaler state */
4497 skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable);
4498 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4499 skl_detach_scalers(crtc);
4500 if (!enable)
4501 return;
bd2e244f 4502
6e3c9717 4503 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK		 4504 int id;
4505
4506 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4507 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4508 return;
4509 }
4510
4511 id = scaler_state->scaler_id;
4512 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4513 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4514 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4515 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4516
4517 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB		 4518 }
4519}
4520
b074cec8
JB		 4521static void ironlake_pfit_enable(struct intel_crtc *crtc)
4522{
4523 struct drm_device *dev = crtc->base.dev;
4524 struct drm_i915_private *dev_priv = dev->dev_private;
4525 int pipe = crtc->pipe;
4526
6e3c9717 4527 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4528 /* Force use of hard-coded filter coefficients
4529 * as some pre-programmed values are broken,
4530 * e.g. x201.
4531 */
4532 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4533 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4534 PF_PIPE_SEL_IVB(pipe));
4535 else
4536 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4537 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4538 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4539 }
4540}
4541
4a3b8769 4542static void intel_enable_sprite_planes(struct drm_crtc *crtc)
bb53d4ae
VS		 4543{
4544 struct drm_device *dev = crtc->dev;
4545 enum pipe pipe = to_intel_crtc(crtc)->pipe;
af2b653b 4546 struct drm_plane *plane;
bb53d4ae
VS		 4547 struct intel_plane *intel_plane;
4548
af2b653b
MR		 4549 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4550 intel_plane = to_intel_plane(plane);
bb53d4ae
VS		 4551 if (intel_plane->pipe == pipe)
4552 intel_plane_restore(&intel_plane->base);
af2b653b 4553 }
bb53d4ae
VS		 4554}
4555
20bc8673 4556void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4557{
cea165c3
VS		 4558 struct drm_device *dev = crtc->base.dev;
4559 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4560
6e3c9717 4561 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4562 return;
4563
cea165c3
VS		 4564 /* We can only enable IPS after we enable a plane and wait for a vblank */
4565 intel_wait_for_vblank(dev, crtc->pipe);
4566
d77e4531 4567 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4568 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4569 mutex_lock(&dev_priv->rps.hw_lock);
4570 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4571 mutex_unlock(&dev_priv->rps.hw_lock);
4572 /* Quoting Art Runyan: "its not safe to expect any particular
4573 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4574 * mailbox." Moreover, the mailbox may return a bogus state,
4575 * so we need to just enable it and continue on.
2a114cc1
BW		 4576 */
4577 } else {
4578 I915_WRITE(IPS_CTL, IPS_ENABLE);
4579 /* The bit only becomes 1 in the next vblank, so this wait here
4580 * is essentially intel_wait_for_vblank. If we don't have this
4581 * and don't wait for vblanks until the end of crtc_enable, then
4582 * the HW state readout code will complain that the expected
4583 * IPS_CTL value is not the one we read. */
4584 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4585 DRM_ERROR("Timed out waiting for IPS enable\n");
4586 }
d77e4531
PZ		 4587}
4588
20bc8673 4589void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4590{
4591 struct drm_device *dev = crtc->base.dev;
4592 struct drm_i915_private *dev_priv = dev->dev_private;
4593
6e3c9717 4594 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4595 return;
4596
4597 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4598 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4599 mutex_lock(&dev_priv->rps.hw_lock);
4600 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4601 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4602 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4603 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4604 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4605 } else {
2a114cc1 4606 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4607 POSTING_READ(IPS_CTL);
4608 }
d77e4531
PZ		 4609
4610 /* We need to wait for a vblank before we can disable the plane. */
4611 intel_wait_for_vblank(dev, crtc->pipe);
4612}
4613
4614/** Loads the palette/gamma unit for the CRTC with the prepared values */
4615static void intel_crtc_load_lut(struct drm_crtc *crtc)
4616{
4617 struct drm_device *dev = crtc->dev;
4618 struct drm_i915_private *dev_priv = dev->dev_private;
4619 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4620 enum pipe pipe = intel_crtc->pipe;
4621 int palreg = PALETTE(pipe);
4622 int i;
4623 bool reenable_ips = false;
4624
4625 /* The clocks have to be on to load the palette. */
83d65738 4626 if (!crtc->state->enable || !intel_crtc->active)
d77e4531
PZ		 4627 return;
4628
50360403 4629 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
409ee761 4630 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4631 assert_dsi_pll_enabled(dev_priv);
4632 else
4633 assert_pll_enabled(dev_priv, pipe);
4634 }
4635
4636 /* use legacy palette for Ironlake */
7a1db49a 4637 if (!HAS_GMCH_DISPLAY(dev))
d77e4531
PZ		 4638 palreg = LGC_PALETTE(pipe);
4639
4640 /* Workaround : Do not read or write the pipe palette/gamma data while
4641 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4642 */
6e3c9717 4643 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4644 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4645 GAMMA_MODE_MODE_SPLIT)) {
4646 hsw_disable_ips(intel_crtc);
4647 reenable_ips = true;
4648 }
4649
4650 for (i = 0; i < 256; i++) {
4651 I915_WRITE(palreg + 4 * i,
4652 (intel_crtc->lut_r[i] << 16) |
4653 (intel_crtc->lut_g[i] << 8) |
4654 intel_crtc->lut_b[i]);
4655 }
4656
4657 if (reenable_ips)
4658 hsw_enable_ips(intel_crtc);
4659}
4660
7cac945f 4661static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
d3eedb1a 4662{
7cac945f 4663 if (intel_crtc->overlay) {
d3eedb1a
VS		 4664 struct drm_device *dev = intel_crtc->base.dev;
4665 struct drm_i915_private *dev_priv = dev->dev_private;
4666
4667 mutex_lock(&dev->struct_mutex);
4668 dev_priv->mm.interruptible = false;
4669 (void) intel_overlay_switch_off(intel_crtc->overlay);
4670 dev_priv->mm.interruptible = true;
4671 mutex_unlock(&dev->struct_mutex);
4672 }
4673
4674 /* Let userspace switch the overlay on again. In most cases userspace
4675 * has to recompute where to put it anyway.
4676 */
4677}
4678
87d4300a
ML		 4679/**
4680 * intel_post_enable_primary - Perform operations after enabling primary plane
4681 * @crtc: the CRTC whose primary plane was just enabled
4682 *
4683 * Performs potentially sleeping operations that must be done after the primary
4684 * plane is enabled, such as updating FBC and IPS. Note that this may be
4685 * called due to an explicit primary plane update, or due to an implicit
4686 * re-enable that is caused when a sprite plane is updated to no longer
4687 * completely hide the primary plane.
4688 */
4689static void
4690intel_post_enable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4691{
4692 struct drm_device *dev = crtc->dev;
87d4300a 4693 struct drm_i915_private *dev_priv = dev->dev_private;
a5c4d7bc
VS		 4694 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4695 int pipe = intel_crtc->pipe;
a5c4d7bc 4696
87d4300a
ML		 4697 /*
4698 * BDW signals flip done immediately if the plane
4699 * is disabled, even if the plane enable is already
4700 * armed to occur at the next vblank :(
4701 */
4702 if (IS_BROADWELL(dev))
4703 intel_wait_for_vblank(dev, pipe);
a5c4d7bc 4704
87d4300a
ML		 4705 /*
4706 * FIXME IPS should be fine as long as one plane is
4707 * enabled, but in practice it seems to have problems
4708 * when going from primary only to sprite only and vice
4709 * versa.
4710 */
a5c4d7bc
VS		 4711 hsw_enable_ips(intel_crtc);
4712
4713 mutex_lock(&dev->struct_mutex);
7ff0ebcc 4714 intel_fbc_update(dev);
a5c4d7bc 4715 mutex_unlock(&dev->struct_mutex);
f99d7069
DV		 4716
4717 /*
87d4300a
ML		 4718 * Gen2 reports pipe underruns whenever all planes are disabled.
4719 * So don't enable underrun reporting before at least some planes
4720 * are enabled.
4721 * FIXME: Need to fix the logic to work when we turn off all planes
4722 * but leave the pipe running.
f99d7069 4723 */
87d4300a
ML		 4724 if (IS_GEN2(dev))
4725 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4726
4727 /* Underruns don't raise interrupts, so check manually. */
4728 if (HAS_GMCH_DISPLAY(dev))
4729 i9xx_check_fifo_underruns(dev_priv);
a5c4d7bc
VS		 4730}
4731
87d4300a
ML		 4732/**
4733 * intel_pre_disable_primary - Perform operations before disabling primary plane
4734 * @crtc: the CRTC whose primary plane is to be disabled
4735 *
4736 * Performs potentially sleeping operations that must be done before the
4737 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4738 * be called due to an explicit primary plane update, or due to an implicit
4739 * disable that is caused when a sprite plane completely hides the primary
4740 * plane.
4741 */
4742static void
4743intel_pre_disable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4744{
4745 struct drm_device *dev = crtc->dev;
4746 struct drm_i915_private *dev_priv = dev->dev_private;
4747 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4748 int pipe = intel_crtc->pipe;
a5c4d7bc 4749
87d4300a
ML		 4750 /*
4751 * Gen2 reports pipe underruns whenever all planes are disabled.
4752 * So diasble underrun reporting before all the planes get disabled.
4753 * FIXME: Need to fix the logic to work when we turn off all planes
4754 * but leave the pipe running.
4755 */
4756 if (IS_GEN2(dev))
4757 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
a5c4d7bc 4758
87d4300a
ML		 4759 /*
4760 * Vblank time updates from the shadow to live plane control register
4761 * are blocked if the memory self-refresh mode is active at that
4762 * moment. So to make sure the plane gets truly disabled, disable
4763 * first the self-refresh mode. The self-refresh enable bit in turn
4764 * will be checked/applied by the HW only at the next frame start
4765 * event which is after the vblank start event, so we need to have a
4766 * wait-for-vblank between disabling the plane and the pipe.
4767 */
4768 if (HAS_GMCH_DISPLAY(dev))
4769 intel_set_memory_cxsr(dev_priv, false);
4770
4771 mutex_lock(&dev->struct_mutex);
e35fef21 4772 if (dev_priv->fbc.crtc == intel_crtc)
7ff0ebcc 4773 intel_fbc_disable(dev);
87d4300a 4774 mutex_unlock(&dev->struct_mutex);
a5c4d7bc 4775
87d4300a
ML		 4776 /*
4777 * FIXME IPS should be fine as long as one plane is
4778 * enabled, but in practice it seems to have problems
4779 * when going from primary only to sprite only and vice
4780 * versa.
4781 */
a5c4d7bc 4782 hsw_disable_ips(intel_crtc);
87d4300a
ML		 4783}
4784
4785static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4786{
2d847d45
RV		 4787 struct drm_device *dev = crtc->dev;
4788 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4789 int pipe = intel_crtc->pipe;
4790
87d4300a
ML		 4791 intel_enable_primary_hw_plane(crtc->primary, crtc);
4792 intel_enable_sprite_planes(crtc);
4793 intel_crtc_update_cursor(crtc, true);
87d4300a
ML		 4794
4795 intel_post_enable_primary(crtc);
2d847d45
RV		 4796
4797 /*
4798 * FIXME: Once we grow proper nuclear flip support out of this we need
4799 * to compute the mask of flip planes precisely. For the time being
4800 * consider this a flip to a NULL plane.
4801 */
4802 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
87d4300a
ML		 4803}
4804
4805static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4806{
4807 struct drm_device *dev = crtc->dev;
4808 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4809 struct intel_plane *intel_plane;
4810 int pipe = intel_crtc->pipe;
4811
4812 intel_crtc_wait_for_pending_flips(crtc);
4813
4814 intel_pre_disable_primary(crtc);
a5c4d7bc 4815
7cac945f 4816 intel_crtc_dpms_overlay_disable(intel_crtc);
27321ae8
ML		 4817 for_each_intel_plane(dev, intel_plane) {
4818 if (intel_plane->pipe == pipe) {
4819 struct drm_crtc *from = intel_plane->base.crtc;
4820
4821 intel_plane->disable_plane(&intel_plane->base,
4822 from ?: crtc, true);
4823 }
4824 }
f98551ae 4825
f99d7069
DV		 4826 /*
4827 * FIXME: Once we grow proper nuclear flip support out of this we need
4828 * to compute the mask of flip planes precisely. For the time being
4829 * consider this a flip to a NULL plane.
4830 */
4831 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4832}
4833
f67a559d
JB		 4834static void ironlake_crtc_enable(struct drm_crtc *crtc)
4835{
4836 struct drm_device *dev = crtc->dev;
4837 struct drm_i915_private *dev_priv = dev->dev_private;
4838 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4839 struct intel_encoder *encoder;
f67a559d 4840 int pipe = intel_crtc->pipe;
f67a559d 4841
83d65738 4842 WARN_ON(!crtc->state->enable);
08a48469 4843
f67a559d
JB		 4844 if (intel_crtc->active)
4845 return;
4846
6e3c9717 4847 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4848 intel_prepare_shared_dpll(intel_crtc);
4849
6e3c9717 4850 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4851 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4852
4853 intel_set_pipe_timings(intel_crtc);
4854
6e3c9717 4855 if (intel_crtc->config->has_pch_encoder) {
29407aab 4856 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4857 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4858 }
4859
4860 ironlake_set_pipeconf(crtc);
4861
f67a559d 4862 intel_crtc->active = true;
8664281b 4863
a72e4c9f
DV		 4864 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4865 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4866
f6736a1a 4867 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4868 if (encoder->pre_enable)
4869 encoder->pre_enable(encoder);
f67a559d 4870
6e3c9717 4871 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4872 /* Note: FDI PLL enabling _must_ be done before we enable the
4873 * cpu pipes, hence this is separate from all the other fdi/pch
4874 * enabling. */
88cefb6c 4875 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4876 } else {
4877 assert_fdi_tx_disabled(dev_priv, pipe);
4878 assert_fdi_rx_disabled(dev_priv, pipe);
4879 }
f67a559d 4880
b074cec8 4881 ironlake_pfit_enable(intel_crtc);
f67a559d 4882
9c54c0dd
JB		 4883 /*
4884 * On ILK+ LUT must be loaded before the pipe is running but with
4885 * clocks enabled
4886 */
4887 intel_crtc_load_lut(crtc);
4888
f37fcc2a 4889 intel_update_watermarks(crtc);
e1fdc473 4890 intel_enable_pipe(intel_crtc);
f67a559d 4891
6e3c9717 4892 if (intel_crtc->config->has_pch_encoder)
f67a559d 4893 ironlake_pch_enable(crtc);
c98e9dcf 4894
f9b61ff6
DV		 4895 assert_vblank_disabled(crtc);
4896 drm_crtc_vblank_on(crtc);
4897
fa5c73b1
DV		 4898 for_each_encoder_on_crtc(dev, crtc, encoder)
4899 encoder->enable(encoder);
61b77ddd
DV		 4900
4901 if (HAS_PCH_CPT(dev))
a1520318 4902 cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB		 4903}
4904
42db64ef
PZ		 4905/* IPS only exists on ULT machines and is tied to pipe A. */
4906static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4907{
f5adf94e 4908 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4909}
4910
e4916946
PZ		 4911/*
4912 * This implements the workaround described in the "notes" section of the mode
4913 * set sequence documentation. When going from no pipes or single pipe to
4914 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4915 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4916 */
4917static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4918{
4919 struct drm_device *dev = crtc->base.dev;
4920 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4921
4922 /* We want to get the other_active_crtc only if there's only 1 other
4923 * active crtc. */
d3fcc808 4924 for_each_intel_crtc(dev, crtc_it) {
e4916946
PZ		 4925 if (!crtc_it->active || crtc_it == crtc)
4926 continue;
4927
4928 if (other_active_crtc)
4929 return;
4930
4931 other_active_crtc = crtc_it;
4932 }
4933 if (!other_active_crtc)
4934 return;
4935
4936 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4937 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4938}
4939
4f771f10
PZ		 4940static void haswell_crtc_enable(struct drm_crtc *crtc)
4941{
4942 struct drm_device *dev = crtc->dev;
4943 struct drm_i915_private *dev_priv = dev->dev_private;
4944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4945 struct intel_encoder *encoder;
4946 int pipe = intel_crtc->pipe;
4f771f10 4947
83d65738 4948 WARN_ON(!crtc->state->enable);
4f771f10
PZ		 4949
4950 if (intel_crtc->active)
4951 return;
4952
df8ad70c
DV		 4953 if (intel_crtc_to_shared_dpll(intel_crtc))
4954 intel_enable_shared_dpll(intel_crtc);
4955
6e3c9717 4956 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4957 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 4958
4959 intel_set_pipe_timings(intel_crtc);
4960
6e3c9717
ACO		 4961 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4962 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4963 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 4964 }
4965
6e3c9717 4966 if (intel_crtc->config->has_pch_encoder) {
229fca97 4967 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4968 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 4969 }
4970
4971 haswell_set_pipeconf(crtc);
4972
4973 intel_set_pipe_csc(crtc);
4974
4f771f10 4975 intel_crtc->active = true;
8664281b 4976
a72e4c9f 4977 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ		 4978 for_each_encoder_on_crtc(dev, crtc, encoder)
4979 if (encoder->pre_enable)
4980 encoder->pre_enable(encoder);
4981
6e3c9717 4982 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 4983 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4984 true);
4fe9467d
ID		 4985 dev_priv->display.fdi_link_train(crtc);
4986 }
4987
1f544388 4988 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 4989
ff6d9f55 4990 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 4991 skylake_pfit_update(intel_crtc, 1);
ff6d9f55 4992 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 4993 ironlake_pfit_enable(intel_crtc);
ff6d9f55
JB		 4994 else
4995 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10
PZ		 4996
4997 /*
4998 * On ILK+ LUT must be loaded before the pipe is running but with
4999 * clocks enabled
5000 */
5001 intel_crtc_load_lut(crtc);
5002
1f544388 5003 intel_ddi_set_pipe_settings(crtc);
8228c251 5004 intel_ddi_enable_transcoder_func(crtc);
4f771f10 5005
f37fcc2a 5006 intel_update_watermarks(crtc);
e1fdc473 5007 intel_enable_pipe(intel_crtc);
42db64ef 5008
6e3c9717 5009 if (intel_crtc->config->has_pch_encoder)
1507e5bd 5010 lpt_pch_enable(crtc);
4f771f10 5011
6e3c9717 5012 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA		 5013 intel_ddi_set_vc_payload_alloc(crtc, true);
5014
f9b61ff6
DV		 5015 assert_vblank_disabled(crtc);
5016 drm_crtc_vblank_on(crtc);
5017
8807e55b 5018 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 5019 encoder->enable(encoder);
8807e55b
JN		 5020 intel_opregion_notify_encoder(encoder, true);
5021 }
4f771f10 5022
e4916946
PZ		 5023 /* If we change the relative order between pipe/planes enabling, we need
5024 * to change the workaround. */
5025 haswell_mode_set_planes_workaround(intel_crtc);
4f771f10
PZ		 5026}
5027
3f8dce3a
DV		 5028static void ironlake_pfit_disable(struct intel_crtc *crtc)
5029{
5030 struct drm_device *dev = crtc->base.dev;
5031 struct drm_i915_private *dev_priv = dev->dev_private;
5032 int pipe = crtc->pipe;
5033
5034 /* To avoid upsetting the power well on haswell only disable the pfit if
5035 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 5036 if (crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 5037 I915_WRITE(PF_CTL(pipe), 0);
5038 I915_WRITE(PF_WIN_POS(pipe), 0);
5039 I915_WRITE(PF_WIN_SZ(pipe), 0);
5040 }
5041}
5042
6be4a607
JB		 5043static void ironlake_crtc_disable(struct drm_crtc *crtc)
5044{
5045 struct drm_device *dev = crtc->dev;
5046 struct drm_i915_private *dev_priv = dev->dev_private;
5047 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5048 struct intel_encoder *encoder;
6be4a607 5049 int pipe = intel_crtc->pipe;
5eddb70b 5050 u32 reg, temp;
b52eb4dc 5051
f7abfe8b
CW		 5052 if (!intel_crtc->active)
5053 return;
5054
ea9d758d
DV		 5055 for_each_encoder_on_crtc(dev, crtc, encoder)
5056 encoder->disable(encoder);
5057
f9b61ff6
DV		 5058 drm_crtc_vblank_off(crtc);
5059 assert_vblank_disabled(crtc);
5060
6e3c9717 5061 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 5062 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 5063
575f7ab7 5064 intel_disable_pipe(intel_crtc);
32f9d658 5065
3f8dce3a 5066 ironlake_pfit_disable(intel_crtc);
2c07245f 5067
5a74f70a
VS		 5068 if (intel_crtc->config->has_pch_encoder)
5069 ironlake_fdi_disable(crtc);
5070
bf49ec8c
DV		 5071 for_each_encoder_on_crtc(dev, crtc, encoder)
5072 if (encoder->post_disable)
5073 encoder->post_disable(encoder);
2c07245f 5074
6e3c9717 5075 if (intel_crtc->config->has_pch_encoder) {
d925c59a 5076 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 5077
d925c59a
DV		 5078 if (HAS_PCH_CPT(dev)) {
5079 /* disable TRANS_DP_CTL */
5080 reg = TRANS_DP_CTL(pipe);
5081 temp = I915_READ(reg);
5082 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5083 TRANS_DP_PORT_SEL_MASK);
5084 temp |= TRANS_DP_PORT_SEL_NONE;
5085 I915_WRITE(reg, temp);
5086
5087 /* disable DPLL_SEL */
5088 temp = I915_READ(PCH_DPLL_SEL);
11887397 5089 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 5090 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 5091 }
e3421a18 5092
d925c59a 5093 /* disable PCH DPLL */
e72f9fbf 5094 intel_disable_shared_dpll(intel_crtc);
8db9d77b 5095
d925c59a
DV		 5096 ironlake_fdi_pll_disable(intel_crtc);
5097 }
6b383a7f 5098
f7abfe8b 5099 intel_crtc->active = false;
46ba614c 5100 intel_update_watermarks(crtc);
d1ebd816
BW		 5101
5102 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5103 intel_fbc_update(dev);
d1ebd816 5104 mutex_unlock(&dev->struct_mutex);
6be4a607 5105}
1b3c7a47 5106
4f771f10 5107static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 5108{
4f771f10
PZ		 5109 struct drm_device *dev = crtc->dev;
5110 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5111 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5112 struct intel_encoder *encoder;
6e3c9717 5113 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 5114
4f771f10
PZ		 5115 if (!intel_crtc->active)
5116 return;
5117
8807e55b
JN		 5118 for_each_encoder_on_crtc(dev, crtc, encoder) {
5119 intel_opregion_notify_encoder(encoder, false);
4f771f10 5120 encoder->disable(encoder);
8807e55b 5121 }
4f771f10 5122
f9b61ff6
DV		 5123 drm_crtc_vblank_off(crtc);
5124 assert_vblank_disabled(crtc);
5125
6e3c9717 5126 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 5127 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5128 false);
575f7ab7 5129 intel_disable_pipe(intel_crtc);
4f771f10 5130
6e3c9717 5131 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 5132 intel_ddi_set_vc_payload_alloc(crtc, false);
5133
ad80a810 5134 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5135
ff6d9f55 5136 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 5137 skylake_pfit_update(intel_crtc, 0);
ff6d9f55 5138 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5139 ironlake_pfit_disable(intel_crtc);
ff6d9f55
JB		 5140 else
5141 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10 5142
1f544388 5143 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5144
6e3c9717 5145 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 5146 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 5147 intel_ddi_fdi_disable(crtc);
83616634 5148 }
4f771f10 5149
97b040aa
ID		 5150 for_each_encoder_on_crtc(dev, crtc, encoder)
5151 if (encoder->post_disable)
5152 encoder->post_disable(encoder);
5153
4f771f10 5154 intel_crtc->active = false;
46ba614c 5155 intel_update_watermarks(crtc);
4f771f10
PZ		 5156
5157 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5158 intel_fbc_update(dev);
4f771f10 5159 mutex_unlock(&dev->struct_mutex);
df8ad70c
DV		 5160
5161 if (intel_crtc_to_shared_dpll(intel_crtc))
5162 intel_disable_shared_dpll(intel_crtc);
4f771f10
PZ		 5163}
5164
2dd24552
JB		 5165static void i9xx_pfit_enable(struct intel_crtc *crtc)
5166{
5167 struct drm_device *dev = crtc->base.dev;
5168 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5169 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5170
681a8504 5171 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 5172 return;
5173
2dd24552 5174 /*
c0b03411
DV		 5175 * The panel fitter should only be adjusted whilst the pipe is disabled,
5176 * according to register description and PRM.
2dd24552 5177 */
c0b03411
DV		 5178 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5179 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5180
b074cec8
JB		 5181 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5182 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 5183
5184 /* Border color in case we don't scale up to the full screen. Black by
5185 * default, change to something else for debugging. */
5186 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 5187}
5188
d05410f9
DA		 5189static enum intel_display_power_domain port_to_power_domain(enum port port)
5190{
5191 switch (port) {
5192 case PORT_A:
5193 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5194 case PORT_B:
5195 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5196 case PORT_C:
5197 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5198 case PORT_D:
5199 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5200 default:
5201 WARN_ON_ONCE(1);
5202 return POWER_DOMAIN_PORT_OTHER;
5203 }
5204}
5205
77d22dca
ID		 5206#define for_each_power_domain(domain, mask) \
5207 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5208 if ((1 << (domain)) & (mask))
5209
319be8ae
ID		 5210enum intel_display_power_domain
5211intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5212{
5213 struct drm_device *dev = intel_encoder->base.dev;
5214 struct intel_digital_port *intel_dig_port;
5215
5216 switch (intel_encoder->type) {
5217 case INTEL_OUTPUT_UNKNOWN:
5218 /* Only DDI platforms should ever use this output type */
5219 WARN_ON_ONCE(!HAS_DDI(dev));
5220 case INTEL_OUTPUT_DISPLAYPORT:
5221 case INTEL_OUTPUT_HDMI:
5222 case INTEL_OUTPUT_EDP:
5223 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5224 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 5225 case INTEL_OUTPUT_DP_MST:
5226 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5227 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 5228 case INTEL_OUTPUT_ANALOG:
5229 return POWER_DOMAIN_PORT_CRT;
5230 case INTEL_OUTPUT_DSI:
5231 return POWER_DOMAIN_PORT_DSI;
5232 default:
5233 return POWER_DOMAIN_PORT_OTHER;
5234 }
5235}
5236
5237static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5238{
319be8ae
ID		 5239 struct drm_device *dev = crtc->dev;
5240 struct intel_encoder *intel_encoder;
5241 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5242 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 5243 unsigned long mask;
5244 enum transcoder transcoder;
5245
5246 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5247
5248 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5249 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 5250 if (intel_crtc->config->pch_pfit.enabled ||
5251 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 5252 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5253
319be8ae
ID		 5254 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5255 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5256
77d22dca
ID		 5257 return mask;
5258}
5259
679dacd4 5260static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
77d22dca 5261{
679dacd4 5262 struct drm_device *dev = state->dev;
77d22dca
ID		 5263 struct drm_i915_private *dev_priv = dev->dev_private;
5264 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5265 struct intel_crtc *crtc;
5266
5267 /*
5268 * First get all needed power domains, then put all unneeded, to avoid
5269 * any unnecessary toggling of the power wells.
5270 */
d3fcc808 5271 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5272 enum intel_display_power_domain domain;
5273
83d65738 5274 if (!crtc->base.state->enable)
77d22dca
ID		 5275 continue;
5276
319be8ae 5277 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
77d22dca
ID		 5278
5279 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5280 intel_display_power_get(dev_priv, domain);
5281 }
5282
50f6e502 5283 if (dev_priv->display.modeset_global_resources)
679dacd4 5284 dev_priv->display.modeset_global_resources(state);
50f6e502 5285
d3fcc808 5286 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5287 enum intel_display_power_domain domain;
5288
5289 for_each_power_domain(domain, crtc->enabled_power_domains)
5290 intel_display_power_put(dev_priv, domain);
5291
5292 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5293 }
5294
5295 intel_display_set_init_power(dev_priv, false);
5296}
5297
560a7ae4
DL		 5298static void intel_update_max_cdclk(struct drm_device *dev)
5299{
5300 struct drm_i915_private *dev_priv = dev->dev_private;
5301
5302 if (IS_SKYLAKE(dev)) {
5303 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5304
5305 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5306 dev_priv->max_cdclk_freq = 675000;
5307 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5308 dev_priv->max_cdclk_freq = 540000;
5309 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5310 dev_priv->max_cdclk_freq = 450000;
5311 else
5312 dev_priv->max_cdclk_freq = 337500;
5313 } else if (IS_BROADWELL(dev)) {
5314 /*
5315 * FIXME with extra cooling we can allow
5316 * 540 MHz for ULX and 675 Mhz for ULT.
5317 * How can we know if extra cooling is
5318 * available? PCI ID, VTB, something else?
5319 */
5320 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5321 dev_priv->max_cdclk_freq = 450000;
5322 else if (IS_BDW_ULX(dev))
5323 dev_priv->max_cdclk_freq = 450000;
5324 else if (IS_BDW_ULT(dev))
5325 dev_priv->max_cdclk_freq = 540000;
5326 else
5327 dev_priv->max_cdclk_freq = 675000;
5328 } else if (IS_VALLEYVIEW(dev)) {
5329 dev_priv->max_cdclk_freq = 400000;
5330 } else {
5331 /* otherwise assume cdclk is fixed */
5332 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5333 }
5334
5335 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5336 dev_priv->max_cdclk_freq);
5337}
5338
5339static void intel_update_cdclk(struct drm_device *dev)
5340{
5341 struct drm_i915_private *dev_priv = dev->dev_private;
5342
5343 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5344 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5345 dev_priv->cdclk_freq);
5346
5347 /*
5348 * Program the gmbus_freq based on the cdclk frequency.
5349 * BSpec erroneously claims we should aim for 4MHz, but
5350 * in fact 1MHz is the correct frequency.
5351 */
5352 if (IS_VALLEYVIEW(dev)) {
5353 /*
5354 * Program the gmbus_freq based on the cdclk frequency.
5355 * BSpec erroneously claims we should aim for 4MHz, but
5356 * in fact 1MHz is the correct frequency.
5357 */
5358 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5359 }
5360
5361 if (dev_priv->max_cdclk_freq == 0)
5362 intel_update_max_cdclk(dev);
5363}
5364
70d0c574 5365static void broxton_set_cdclk(struct drm_device *dev, int frequency)
f8437dd1
VK		 5366{
5367 struct drm_i915_private *dev_priv = dev->dev_private;
5368 uint32_t divider;
5369 uint32_t ratio;
5370 uint32_t current_freq;
5371 int ret;
5372
5373 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5374 switch (frequency) {
5375 case 144000:
5376 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5377 ratio = BXT_DE_PLL_RATIO(60);
5378 break;
5379 case 288000:
5380 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5381 ratio = BXT_DE_PLL_RATIO(60);
5382 break;
5383 case 384000:
5384 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5385 ratio = BXT_DE_PLL_RATIO(60);
5386 break;
5387 case 576000:
5388 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5389 ratio = BXT_DE_PLL_RATIO(60);
5390 break;
5391 case 624000:
5392 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5393 ratio = BXT_DE_PLL_RATIO(65);
5394 break;
5395 case 19200:
5396 /*
5397 * Bypass frequency with DE PLL disabled. Init ratio, divider
5398 * to suppress GCC warning.
5399 */
5400 ratio = 0;
5401 divider = 0;
5402 break;
5403 default:
5404 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5405
5406 return;
5407 }
5408
5409 mutex_lock(&dev_priv->rps.hw_lock);
5410 /* Inform power controller of upcoming frequency change */
5411 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5412 0x80000000);
5413 mutex_unlock(&dev_priv->rps.hw_lock);
5414
5415 if (ret) {
5416 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5417 ret, frequency);
5418 return;
5419 }
5420
5421 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5422 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5423 current_freq = current_freq * 500 + 1000;
5424
5425 /*
5426 * DE PLL has to be disabled when
5427 * - setting to 19.2MHz (bypass, PLL isn't used)
5428 * - before setting to 624MHz (PLL needs toggling)
5429 * - before setting to any frequency from 624MHz (PLL needs toggling)
5430 */
5431 if (frequency == 19200 || frequency == 624000 ||
5432 current_freq == 624000) {
5433 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5434 /* Timeout 200us */
5435 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5436 1))
5437 DRM_ERROR("timout waiting for DE PLL unlock\n");
5438 }
5439
5440 if (frequency != 19200) {
5441 uint32_t val;
5442
5443 val = I915_READ(BXT_DE_PLL_CTL);
5444 val &= ~BXT_DE_PLL_RATIO_MASK;
5445 val |= ratio;
5446 I915_WRITE(BXT_DE_PLL_CTL, val);
5447
5448 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5449 /* Timeout 200us */
5450 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5451 DRM_ERROR("timeout waiting for DE PLL lock\n");
5452
5453 val = I915_READ(CDCLK_CTL);
5454 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5455 val |= divider;
5456 /*
5457 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5458 * enable otherwise.
5459 */
5460 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5461 if (frequency >= 500000)
5462 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5463
5464 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5465 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5466 val |= (frequency - 1000) / 500;
5467 I915_WRITE(CDCLK_CTL, val);
5468 }
5469
5470 mutex_lock(&dev_priv->rps.hw_lock);
5471 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5472 DIV_ROUND_UP(frequency, 25000));
5473 mutex_unlock(&dev_priv->rps.hw_lock);
5474
5475 if (ret) {
5476 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5477 ret, frequency);
5478 return;
5479 }
5480
a47871bd 5481 intel_update_cdclk(dev);
f8437dd1
VK		 5482}
5483
5484void broxton_init_cdclk(struct drm_device *dev)
5485{
5486 struct drm_i915_private *dev_priv = dev->dev_private;
5487 uint32_t val;
5488
5489 /*
5490 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5491 * or else the reset will hang because there is no PCH to respond.
5492 * Move the handshake programming to initialization sequence.
5493 * Previously was left up to BIOS.
5494 */
5495 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5496 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5497 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5498
5499 /* Enable PG1 for cdclk */
5500 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5501
5502 /* check if cd clock is enabled */
5503 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5504 DRM_DEBUG_KMS("Display already initialized\n");
5505 return;
5506 }
5507
5508 /*
5509 * FIXME:
5510 * - The initial CDCLK needs to be read from VBT.
5511 * Need to make this change after VBT has changes for BXT.
5512 * - check if setting the max (or any) cdclk freq is really necessary
5513 * here, it belongs to modeset time
5514 */
5515 broxton_set_cdclk(dev, 624000);
5516
5517 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
22e02c0b
VS		 5518 POSTING_READ(DBUF_CTL);
5519
f8437dd1
VK		 5520 udelay(10);
5521
5522 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5523 DRM_ERROR("DBuf power enable timeout!\n");
5524}
5525
5526void broxton_uninit_cdclk(struct drm_device *dev)
5527{
5528 struct drm_i915_private *dev_priv = dev->dev_private;
5529
5530 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
22e02c0b
VS		 5531 POSTING_READ(DBUF_CTL);
5532
f8437dd1
VK		 5533 udelay(10);
5534
5535 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5536 DRM_ERROR("DBuf power disable timeout!\n");
5537
5538 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5539 broxton_set_cdclk(dev, 19200);
5540
5541 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5542}
5543
5d96d8af
DL		 5544static const struct skl_cdclk_entry {
5545 unsigned int freq;
5546 unsigned int vco;
5547} skl_cdclk_frequencies[] = {
5548 { .freq = 308570, .vco = 8640 },
5549 { .freq = 337500, .vco = 8100 },
5550 { .freq = 432000, .vco = 8640 },
5551 { .freq = 450000, .vco = 8100 },
5552 { .freq = 540000, .vco = 8100 },
5553 { .freq = 617140, .vco = 8640 },
5554 { .freq = 675000, .vco = 8100 },
5555};
5556
5557static unsigned int skl_cdclk_decimal(unsigned int freq)
5558{
5559 return (freq - 1000) / 500;
5560}
5561
5562static unsigned int skl_cdclk_get_vco(unsigned int freq)
5563{
5564 unsigned int i;
5565
5566 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5567 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5568
5569 if (e->freq == freq)
5570 return e->vco;
5571 }
5572
5573 return 8100;
5574}
5575
5576static void
5577skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5578{
5579 unsigned int min_freq;
5580 u32 val;
5581
5582 /* select the minimum CDCLK before enabling DPLL 0 */
5583 val = I915_READ(CDCLK_CTL);
5584 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5585 val |= CDCLK_FREQ_337_308;
5586
5587 if (required_vco == 8640)
5588 min_freq = 308570;
5589 else
5590 min_freq = 337500;
5591
5592 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5593
5594 I915_WRITE(CDCLK_CTL, val);
5595 POSTING_READ(CDCLK_CTL);
5596
5597 /*
5598 * We always enable DPLL0 with the lowest link rate possible, but still
5599 * taking into account the VCO required to operate the eDP panel at the
5600 * desired frequency. The usual DP link rates operate with a VCO of
5601 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5602 * The modeset code is responsible for the selection of the exact link
5603 * rate later on, with the constraint of choosing a frequency that
5604 * works with required_vco.
5605 */
5606 val = I915_READ(DPLL_CTRL1);
5607
5608 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5609 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5610 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5611 if (required_vco == 8640)
5612 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5613 SKL_DPLL0);
5614 else
5615 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5616 SKL_DPLL0);
5617
5618 I915_WRITE(DPLL_CTRL1, val);
5619 POSTING_READ(DPLL_CTRL1);
5620
5621 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5622
5623 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5624 DRM_ERROR("DPLL0 not locked\n");
5625}
5626
5627static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5628{
5629 int ret;
5630 u32 val;
5631
5632 /* inform PCU we want to change CDCLK */
5633 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5634 mutex_lock(&dev_priv->rps.hw_lock);
5635 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5636 mutex_unlock(&dev_priv->rps.hw_lock);
5637
5638 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5639}
5640
5641static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5642{
5643 unsigned int i;
5644
5645 for (i = 0; i < 15; i++) {
5646 if (skl_cdclk_pcu_ready(dev_priv))
5647 return true;
5648 udelay(10);
5649 }
5650
5651 return false;
5652}
5653
5654static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5655{
560a7ae4 5656 struct drm_device *dev = dev_priv->dev;
5d96d8af
DL		 5657 u32 freq_select, pcu_ack;
5658
5659 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5660
5661 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5662 DRM_ERROR("failed to inform PCU about cdclk change\n");
5663 return;
5664 }
5665
5666 /* set CDCLK_CTL */
5667 switch(freq) {
5668 case 450000:
5669 case 432000:
5670 freq_select = CDCLK_FREQ_450_432;
5671 pcu_ack = 1;
5672 break;
5673 case 540000:
5674 freq_select = CDCLK_FREQ_540;
5675 pcu_ack = 2;
5676 break;
5677 case 308570:
5678 case 337500:
5679 default:
5680 freq_select = CDCLK_FREQ_337_308;
5681 pcu_ack = 0;
5682 break;
5683 case 617140:
5684 case 675000:
5685 freq_select = CDCLK_FREQ_675_617;
5686 pcu_ack = 3;
5687 break;
5688 }
5689
5690 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5691 POSTING_READ(CDCLK_CTL);
5692
5693 /* inform PCU of the change */
5694 mutex_lock(&dev_priv->rps.hw_lock);
5695 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5696 mutex_unlock(&dev_priv->rps.hw_lock);
560a7ae4
DL		 5697
5698 intel_update_cdclk(dev);
5d96d8af
DL		 5699}
5700
5701void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5702{
5703 /* disable DBUF power */
5704 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5705 POSTING_READ(DBUF_CTL);
5706
5707 udelay(10);
5708
5709 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5710 DRM_ERROR("DBuf power disable timeout\n");
5711
5712 /* disable DPLL0 */
5713 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5714 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5715 DRM_ERROR("Couldn't disable DPLL0\n");
5716
5717 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5718}
5719
5720void skl_init_cdclk(struct drm_i915_private *dev_priv)
5721{
5722 u32 val;
5723 unsigned int required_vco;
5724
5725 /* enable PCH reset handshake */
5726 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5727 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5728
5729 /* enable PG1 and Misc I/O */
5730 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5731
5732 /* DPLL0 already enabed !? */
5733 if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5734 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5735 return;
5736 }
5737
5738 /* enable DPLL0 */
5739 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5740 skl_dpll0_enable(dev_priv, required_vco);
5741
5742 /* set CDCLK to the frequency the BIOS chose */
5743 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5744
5745 /* enable DBUF power */
5746 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5747 POSTING_READ(DBUF_CTL);
5748
5749 udelay(10);
5750
5751 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5752 DRM_ERROR("DBuf power enable timeout\n");
5753}
5754
dfcab17e 5755/* returns HPLL frequency in kHz */
f8bf63fd 5756static int valleyview_get_vco(struct drm_i915_private *dev_priv)
30a970c6 5757{
586f49dc 5758 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
30a970c6 5759
586f49dc 5760 /* Obtain SKU information */
a580516d 5761 mutex_lock(&dev_priv->sb_lock);
586f49dc
JB		 5762 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5763 CCK_FUSE_HPLL_FREQ_MASK;
a580516d 5764 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5765
dfcab17e 5766 return vco_freq[hpll_freq] * 1000;
30a970c6
JB		 5767}
5768
5769/* Adjust CDclk dividers to allow high res or save power if possible */
5770static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5771{
5772 struct drm_i915_private *dev_priv = dev->dev_private;
5773 u32 val, cmd;
5774
164dfd28
VK		 5775 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5776 != dev_priv->cdclk_freq);
d60c4473 5777
dfcab17e 5778 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5779 cmd = 2;
dfcab17e 5780 else if (cdclk == 266667)
30a970c6
JB		 5781 cmd = 1;
5782 else
5783 cmd = 0;
5784
5785 mutex_lock(&dev_priv->rps.hw_lock);
5786 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5787 val &= ~DSPFREQGUAR_MASK;
5788 val |= (cmd << DSPFREQGUAR_SHIFT);
5789 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5790 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5791 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5792 50)) {
5793 DRM_ERROR("timed out waiting for CDclk change\n");
5794 }
5795 mutex_unlock(&dev_priv->rps.hw_lock);
5796
54433e91
VS		 5797 mutex_lock(&dev_priv->sb_lock);
5798
dfcab17e 5799 if (cdclk == 400000) {
6bcda4f0 5800 u32 divider;
30a970c6 5801
6bcda4f0 5802 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6 5803
30a970c6
JB		 5804 /* adjust cdclk divider */
5805 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
9cf33db5 5806 val &= ~DISPLAY_FREQUENCY_VALUES;
30a970c6
JB		 5807 val |= divider;
5808 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5809
5810 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5811 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5812 50))
5813 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5814 }
5815
30a970c6
JB		 5816 /* adjust self-refresh exit latency value */
5817 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5818 val &= ~0x7f;
5819
5820 /*
5821 * For high bandwidth configs, we set a higher latency in the bunit
5822 * so that the core display fetch happens in time to avoid underruns.
5823 */
dfcab17e 5824 if (cdclk == 400000)
30a970c6
JB		 5825 val |= 4500 / 250; /* 4.5 usec */
5826 else
5827 val |= 3000 / 250; /* 3.0 usec */
5828 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
54433e91 5829
a580516d 5830 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5831
b6283055 5832 intel_update_cdclk(dev);
30a970c6
JB		 5833}
5834
383c5a6a
VS		 5835static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5836{
5837 struct drm_i915_private *dev_priv = dev->dev_private;
5838 u32 val, cmd;
5839
164dfd28
VK		 5840 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5841 != dev_priv->cdclk_freq);
383c5a6a
VS		 5842
5843 switch (cdclk) {
383c5a6a
VS		 5844 case 333333:
5845 case 320000:
383c5a6a 5846 case 266667:
383c5a6a 5847 case 200000:
383c5a6a
VS		 5848 break;
5849 default:
5f77eeb0 5850 MISSING_CASE(cdclk);
383c5a6a
VS		 5851 return;
5852 }
5853
9d0d3fda
VS		 5854 /*
5855 * Specs are full of misinformation, but testing on actual
5856 * hardware has shown that we just need to write the desired
5857 * CCK divider into the Punit register.
5858 */
5859 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5860
383c5a6a
VS		 5861 mutex_lock(&dev_priv->rps.hw_lock);
5862 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5863 val &= ~DSPFREQGUAR_MASK_CHV;
5864 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5865 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5866 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5867 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5868 50)) {
5869 DRM_ERROR("timed out waiting for CDclk change\n");
5870 }
5871 mutex_unlock(&dev_priv->rps.hw_lock);
5872
b6283055 5873 intel_update_cdclk(dev);
383c5a6a
VS		 5874}
5875
30a970c6
JB		 5876static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5877 int max_pixclk)
5878{
6bcda4f0 5879 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5880 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5881
30a970c6
JB		 5882 /*
5883 * Really only a few cases to deal with, as only 4 CDclks are supported:
5884 * 200MHz
5885 * 267MHz
29dc7ef3 5886 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5887 * 400MHz (VLV only)
5888 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5889 * of the lower bin and adjust if needed.
e37c67a1
VS		 5890 *
5891 * We seem to get an unstable or solid color picture at 200MHz.
5892 * Not sure what's wrong. For now use 200MHz only when all pipes
5893 * are off.
30a970c6 5894 */
6cca3195
VS		 5895 if (!IS_CHERRYVIEW(dev_priv) &&
5896 max_pixclk > freq_320*limit/100)
dfcab17e 5897 return 400000;
6cca3195 5898 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5899 return freq_320;
e37c67a1 5900 else if (max_pixclk > 0)
dfcab17e 5901 return 266667;
e37c67a1
VS		 5902 else
5903 return 200000;
30a970c6
JB		 5904}
5905
f8437dd1
VK		 5906static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5907 int max_pixclk)
5908{
5909 /*
5910 * FIXME:
5911 * - remove the guardband, it's not needed on BXT
5912 * - set 19.2MHz bypass frequency if there are no active pipes
5913 */
5914 if (max_pixclk > 576000*9/10)
5915 return 624000;
5916 else if (max_pixclk > 384000*9/10)
5917 return 576000;
5918 else if (max_pixclk > 288000*9/10)
5919 return 384000;
5920 else if (max_pixclk > 144000*9/10)
5921 return 288000;
5922 else
5923 return 144000;
5924}
5925
a821fc46
ACO		 5926/* Compute the max pixel clock for new configuration. Uses atomic state if
5927 * that's non-NULL, look at current state otherwise. */
5928static int intel_mode_max_pixclk(struct drm_device *dev,
5929 struct drm_atomic_state *state)
30a970c6 5930{
30a970c6 5931 struct intel_crtc *intel_crtc;
304603f4 5932 struct intel_crtc_state *crtc_state;
30a970c6
JB		 5933 int max_pixclk = 0;
5934
d3fcc808 5935 for_each_intel_crtc(dev, intel_crtc) {
a821fc46
ACO		 5936 if (state)
5937 crtc_state =
5938 intel_atomic_get_crtc_state(state, intel_crtc);
5939 else
5940 crtc_state = intel_crtc->config;
304603f4
ACO		 5941 if (IS_ERR(crtc_state))
5942 return PTR_ERR(crtc_state);
5943
5944 if (!crtc_state->base.enable)
5945 continue;
5946
5947 max_pixclk = max(max_pixclk,
5948 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5949 }
5950
5951 return max_pixclk;
5952}
5953
0a9ab303 5954static int valleyview_modeset_global_pipes(struct drm_atomic_state *state)
30a970c6 5955{
304603f4 5956 struct drm_i915_private *dev_priv = to_i915(state->dev);
0a9ab303
ACO		 5957 struct drm_crtc *crtc;
5958 struct drm_crtc_state *crtc_state;
a821fc46 5959 int max_pixclk = intel_mode_max_pixclk(state->dev, state);
0a9ab303 5960 int cdclk, i;
30a970c6 5961
304603f4
ACO		 5962 if (max_pixclk < 0)
5963 return max_pixclk;
30a970c6 5964
f8437dd1
VK		 5965 if (IS_VALLEYVIEW(dev_priv))
5966 cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5967 else
5968 cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
5969
5970 if (cdclk == dev_priv->cdclk_freq)
304603f4 5971 return 0;
30a970c6 5972
0a9ab303
ACO		 5973 /* add all active pipes to the state */
5974 for_each_crtc(state->dev, crtc) {
5975 if (!crtc->state->enable)
5976 continue;
5977
5978 crtc_state = drm_atomic_get_crtc_state(state, crtc);
5979 if (IS_ERR(crtc_state))
5980 return PTR_ERR(crtc_state);
5981 }
5982
2f2d7aa1 5983 /* disable/enable all currently active pipes while we change cdclk */
0a9ab303
ACO		 5984 for_each_crtc_in_state(state, crtc, crtc_state, i)
5985 if (crtc_state->enable)
5986 crtc_state->mode_changed = true;
304603f4
ACO		 5987
5988 return 0;
30a970c6
JB		 5989}
5990
1e69cd74
VS		 5991static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5992{
5993 unsigned int credits, default_credits;
5994
5995 if (IS_CHERRYVIEW(dev_priv))
5996 default_credits = PFI_CREDIT(12);
5997 else
5998 default_credits = PFI_CREDIT(8);
5999
164dfd28 6000 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
1e69cd74
VS		 6001 /* CHV suggested value is 31 or 63 */
6002 if (IS_CHERRYVIEW(dev_priv))
6003 credits = PFI_CREDIT_31;
6004 else
6005 credits = PFI_CREDIT(15);
6006 } else {
6007 credits = default_credits;
6008 }
6009
6010 /*
6011 * WA - write default credits before re-programming
6012 * FIXME: should we also set the resend bit here?
6013 */
6014 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6015 default_credits);
6016
6017 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6018 credits | PFI_CREDIT_RESEND);
6019
6020 /*
6021 * FIXME is this guaranteed to clear
6022 * immediately or should we poll for it?
6023 */
6024 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6025}
6026
a821fc46 6027static void valleyview_modeset_global_resources(struct drm_atomic_state *old_state)
30a970c6 6028{
a821fc46 6029 struct drm_device *dev = old_state->dev;
30a970c6 6030 struct drm_i915_private *dev_priv = dev->dev_private;
a821fc46 6031 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
304603f4
ACO		 6032 int req_cdclk;
6033
a821fc46
ACO		 6034 /* The path in intel_mode_max_pixclk() with a NULL atomic state should
6035 * never fail. */
304603f4
ACO		 6036 if (WARN_ON(max_pixclk < 0))
6037 return;
30a970c6 6038
304603f4 6039 req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
30a970c6 6040
164dfd28 6041 if (req_cdclk != dev_priv->cdclk_freq) {
738c05c0
ID		 6042 /*
6043 * FIXME: We can end up here with all power domains off, yet
6044 * with a CDCLK frequency other than the minimum. To account
6045 * for this take the PIPE-A power domain, which covers the HW
6046 * blocks needed for the following programming. This can be
6047 * removed once it's guaranteed that we get here either with
6048 * the minimum CDCLK set, or the required power domains
6049 * enabled.
6050 */
6051 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6052
383c5a6a
VS		 6053 if (IS_CHERRYVIEW(dev))
6054 cherryview_set_cdclk(dev, req_cdclk);
6055 else
6056 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 6057
1e69cd74
VS		 6058 vlv_program_pfi_credits(dev_priv);
6059
738c05c0 6060 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
383c5a6a 6061 }
30a970c6
JB		 6062}
6063
89b667f8
JB		 6064static void valleyview_crtc_enable(struct drm_crtc *crtc)
6065{
6066 struct drm_device *dev = crtc->dev;
a72e4c9f 6067 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 6068 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6069 struct intel_encoder *encoder;
6070 int pipe = intel_crtc->pipe;
23538ef1 6071 bool is_dsi;
89b667f8 6072
83d65738 6073 WARN_ON(!crtc->state->enable);
89b667f8
JB		 6074
6075 if (intel_crtc->active)
6076 return;
6077
409ee761 6078 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 6079
1ae0d137
VS		 6080 if (!is_dsi) {
6081 if (IS_CHERRYVIEW(dev))
6e3c9717 6082 chv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 6083 else
6e3c9717 6084 vlv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 6085 }
5b18e57c 6086
6e3c9717 6087 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6088 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6089
6090 intel_set_pipe_timings(intel_crtc);
6091
c14b0485
VS		 6092 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6093 struct drm_i915_private *dev_priv = dev->dev_private;
6094
6095 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6096 I915_WRITE(CHV_CANVAS(pipe), 0);
6097 }
6098
5b18e57c
DV		 6099 i9xx_set_pipeconf(intel_crtc);
6100
89b667f8 6101 intel_crtc->active = true;
89b667f8 6102
a72e4c9f 6103 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6104
89b667f8
JB		 6105 for_each_encoder_on_crtc(dev, crtc, encoder)
6106 if (encoder->pre_pll_enable)
6107 encoder->pre_pll_enable(encoder);
6108
9d556c99
CML		 6109 if (!is_dsi) {
6110 if (IS_CHERRYVIEW(dev))
6e3c9717 6111 chv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6112 else
6e3c9717 6113 vlv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6114 }
89b667f8
JB		 6115
6116 for_each_encoder_on_crtc(dev, crtc, encoder)
6117 if (encoder->pre_enable)
6118 encoder->pre_enable(encoder);
6119
2dd24552
JB		 6120 i9xx_pfit_enable(intel_crtc);
6121
63cbb074
VS		 6122 intel_crtc_load_lut(crtc);
6123
f37fcc2a 6124 intel_update_watermarks(crtc);
e1fdc473 6125 intel_enable_pipe(intel_crtc);
be6a6f8e 6126
4b3a9526
VS		 6127 assert_vblank_disabled(crtc);
6128 drm_crtc_vblank_on(crtc);
6129
f9b61ff6
DV		 6130 for_each_encoder_on_crtc(dev, crtc, encoder)
6131 encoder->enable(encoder);
89b667f8
JB		 6132}
6133
f13c2ef3
DV		 6134static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6135{
6136 struct drm_device *dev = crtc->base.dev;
6137 struct drm_i915_private *dev_priv = dev->dev_private;
6138
6e3c9717
ACO		 6139 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6140 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 6141}
6142
0b8765c6 6143static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 6144{
6145 struct drm_device *dev = crtc->dev;
a72e4c9f 6146 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 6147 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6148 struct intel_encoder *encoder;
79e53945 6149 int pipe = intel_crtc->pipe;
79e53945 6150
83d65738 6151 WARN_ON(!crtc->state->enable);
08a48469 6152
f7abfe8b
CW		 6153 if (intel_crtc->active)
6154 return;
6155
f13c2ef3
DV		 6156 i9xx_set_pll_dividers(intel_crtc);
6157
6e3c9717 6158 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6159 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6160
6161 intel_set_pipe_timings(intel_crtc);
6162
5b18e57c
DV		 6163 i9xx_set_pipeconf(intel_crtc);
6164
f7abfe8b 6165 intel_crtc->active = true;
6b383a7f 6166
4a3436e8 6167 if (!IS_GEN2(dev))
a72e4c9f 6168 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6169
9d6d9f19
MK		 6170 for_each_encoder_on_crtc(dev, crtc, encoder)
6171 if (encoder->pre_enable)
6172 encoder->pre_enable(encoder);
6173
f6736a1a
DV		 6174 i9xx_enable_pll(intel_crtc);
6175
2dd24552
JB		 6176 i9xx_pfit_enable(intel_crtc);
6177
63cbb074
VS		 6178 intel_crtc_load_lut(crtc);
6179
f37fcc2a 6180 intel_update_watermarks(crtc);
e1fdc473 6181 intel_enable_pipe(intel_crtc);
be6a6f8e 6182
4b3a9526
VS		 6183 assert_vblank_disabled(crtc);
6184 drm_crtc_vblank_on(crtc);
6185
f9b61ff6
DV		 6186 for_each_encoder_on_crtc(dev, crtc, encoder)
6187 encoder->enable(encoder);
0b8765c6 6188}
79e53945 6189
87476d63
DV		 6190static void i9xx_pfit_disable(struct intel_crtc *crtc)
6191{
6192 struct drm_device *dev = crtc->base.dev;
6193 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 6194
6e3c9717 6195 if (!crtc->config->gmch_pfit.control)
328d8e82 6196 return;
87476d63 6197
328d8e82 6198 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 6199
328d8e82
DV		 6200 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6201 I915_READ(PFIT_CONTROL));
6202 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 6203}
6204
0b8765c6
JB		 6205static void i9xx_crtc_disable(struct drm_crtc *crtc)
6206{
6207 struct drm_device *dev = crtc->dev;
6208 struct drm_i915_private *dev_priv = dev->dev_private;
6209 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6210 struct intel_encoder *encoder;
0b8765c6 6211 int pipe = intel_crtc->pipe;
ef9c3aee 6212
f7abfe8b
CW		 6213 if (!intel_crtc->active)
6214 return;
6215
6304cd91
VS		 6216 /*
6217 * On gen2 planes are double buffered but the pipe isn't, so we must
6218 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 6219 * We also need to wait on all gmch platforms because of the
6220 * self-refresh mode constraint explained above.
6304cd91 6221 */
564ed191 6222 intel_wait_for_vblank(dev, pipe);
6304cd91 6223
4b3a9526
VS		 6224 for_each_encoder_on_crtc(dev, crtc, encoder)
6225 encoder->disable(encoder);
6226
f9b61ff6
DV		 6227 drm_crtc_vblank_off(crtc);
6228 assert_vblank_disabled(crtc);
6229
575f7ab7 6230 intel_disable_pipe(intel_crtc);
24a1f16d 6231
87476d63 6232 i9xx_pfit_disable(intel_crtc);
24a1f16d 6233
89b667f8
JB		 6234 for_each_encoder_on_crtc(dev, crtc, encoder)
6235 if (encoder->post_disable)
6236 encoder->post_disable(encoder);
6237
409ee761 6238 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 6239 if (IS_CHERRYVIEW(dev))
6240 chv_disable_pll(dev_priv, pipe);
6241 else if (IS_VALLEYVIEW(dev))
6242 vlv_disable_pll(dev_priv, pipe);
6243 else
1c4e0274 6244 i9xx_disable_pll(intel_crtc);
076ed3b2 6245 }
0b8765c6 6246
4a3436e8 6247 if (!IS_GEN2(dev))
a72e4c9f 6248 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4a3436e8 6249
f7abfe8b 6250 intel_crtc->active = false;
46ba614c 6251 intel_update_watermarks(crtc);
f37fcc2a 6252
efa9624e 6253 mutex_lock(&dev->struct_mutex);
7ff0ebcc 6254 intel_fbc_update(dev);
efa9624e 6255 mutex_unlock(&dev->struct_mutex);
0b8765c6
JB		 6256}
6257
6b72d486
ML		 6258/*
6259 * turn all crtc's off, but do not adjust state
6260 * This has to be paired with a call to intel_modeset_setup_hw_state.
6261 */
6262void intel_display_suspend(struct drm_device *dev)
6263{
6264 struct drm_i915_private *dev_priv = to_i915(dev);
6265 struct drm_crtc *crtc;
6266
6267 for_each_crtc(dev, crtc) {
6268 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6269 enum intel_display_power_domain domain;
6270 unsigned long domains;
6271
6272 if (!intel_crtc->active)
6273 continue;
6274
6275 intel_crtc_disable_planes(crtc);
6276 dev_priv->display.crtc_disable(crtc);
6277
6278 domains = intel_crtc->enabled_power_domains;
6279 for_each_power_domain(domain, domains)
6280 intel_display_power_put(dev_priv, domain);
6281 intel_crtc->enabled_power_domains = 0;
6282 }
6283}
6284
b04c5bd6
BF		 6285/* Master function to enable/disable CRTC and corresponding power wells */
6286void intel_crtc_control(struct drm_crtc *crtc, bool enable)
976f8a20
DV		 6287{
6288 struct drm_device *dev = crtc->dev;
6289 struct drm_i915_private *dev_priv = dev->dev_private;
0e572fe7 6290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
0e572fe7
DV		 6291 enum intel_display_power_domain domain;
6292 unsigned long domains;
976f8a20 6293
1b509259
ML		 6294 if (enable == intel_crtc->active)
6295 return;
6296
6297 if (enable && !crtc->state->enable)
6298 return;
6299
6300 crtc->state->active = enable;
0e572fe7 6301 if (enable) {
1b509259
ML		 6302 domains = get_crtc_power_domains(crtc);
6303 for_each_power_domain(domain, domains)
6304 intel_display_power_get(dev_priv, domain);
6305 intel_crtc->enabled_power_domains = domains;
6306
6307 dev_priv->display.crtc_enable(crtc);
6308 intel_crtc_enable_planes(crtc);
0e572fe7 6309 } else {
1b509259
ML		 6310 intel_crtc_disable_planes(crtc);
6311 dev_priv->display.crtc_disable(crtc);
6312
6313 domains = intel_crtc->enabled_power_domains;
6314 for_each_power_domain(domain, domains)
6315 intel_display_power_put(dev_priv, domain);
6316 intel_crtc->enabled_power_domains = 0;
0e572fe7 6317 }
b04c5bd6
BF		 6318}
6319
6320/**
6321 * Sets the power management mode of the pipe and plane.
6322 */
6323void intel_crtc_update_dpms(struct drm_crtc *crtc)
6324{
6325 struct drm_device *dev = crtc->dev;
6326 struct intel_encoder *intel_encoder;
6327 bool enable = false;
6328
6329 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6330 enable |= intel_encoder->connectors_active;
6331
6332 intel_crtc_control(crtc, enable);
976f8a20
DV		 6333}
6334
ea5b213a 6335void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 6336{
4ef69c7a 6337 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 6338
ea5b213a
CW		 6339 drm_encoder_cleanup(encoder);
6340 kfree(intel_encoder);
7e7d76c3
JB		 6341}
6342
9237329d 6343/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 6344 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6345 * state of the entire output pipe. */
9237329d 6346static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 6347{
5ab432ef
DV		 6348 if (mode == DRM_MODE_DPMS_ON) {
6349 encoder->connectors_active = true;
6350
b2cabb0e 6351 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 6352 } else {
6353 encoder->connectors_active = false;
6354
b2cabb0e 6355 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 6356 }
79e53945
JB		 6357}
6358
0a91ca29
DV		 6359/* Cross check the actual hw state with our own modeset state tracking (and it's
6360 * internal consistency). */
b980514c 6361static void intel_connector_check_state(struct intel_connector *connector)
79e53945 6362{
0a91ca29
DV		 6363 if (connector->get_hw_state(connector)) {
6364 struct intel_encoder *encoder = connector->encoder;
6365 struct drm_crtc *crtc;
6366 bool encoder_enabled;
6367 enum pipe pipe;
6368
6369 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6370 connector->base.base.id,
c23cc417 6371 connector->base.name);
0a91ca29 6372
0e32b39c
DA		 6373 /* there is no real hw state for MST connectors */
6374 if (connector->mst_port)
6375 return;
6376
e2c719b7 6377 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
0a91ca29 6378 "wrong connector dpms state\n");
e2c719b7 6379 I915_STATE_WARN(connector->base.encoder != &encoder->base,
0a91ca29 6380 "active connector not linked to encoder\n");
0a91ca29 6381
36cd7444 6382 if (encoder) {
e2c719b7 6383 I915_STATE_WARN(!encoder->connectors_active,
36cd7444
DA		 6384 "encoder->connectors_active not set\n");
6385
6386 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
e2c719b7
RC		 6387 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6388 if (I915_STATE_WARN_ON(!encoder->base.crtc))
36cd7444 6389 return;
0a91ca29 6390
36cd7444 6391 crtc = encoder->base.crtc;
0a91ca29 6392
83d65738
MR		 6393 I915_STATE_WARN(!crtc->state->enable,
6394 "crtc not enabled\n");
e2c719b7
RC		 6395 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6396 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
36cd7444
DA		 6397 "encoder active on the wrong pipe\n");
6398 }
0a91ca29 6399 }
79e53945
JB		 6400}
6401
08d9bc92
ACO		 6402int intel_connector_init(struct intel_connector *connector)
6403{
6404 struct drm_connector_state *connector_state;
6405
6406 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6407 if (!connector_state)
6408 return -ENOMEM;
6409
6410 connector->base.state = connector_state;
6411 return 0;
6412}
6413
6414struct intel_connector *intel_connector_alloc(void)
6415{
6416 struct intel_connector *connector;
6417
6418 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6419 if (!connector)
6420 return NULL;
6421
6422 if (intel_connector_init(connector) < 0) {
6423 kfree(connector);
6424 return NULL;
6425 }
6426
6427 return connector;
6428}
6429
5ab432ef
DV		 6430/* Even simpler default implementation, if there's really no special case to
6431 * consider. */
6432void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 6433{
5ab432ef
DV		 6434 /* All the simple cases only support two dpms states. */
6435 if (mode != DRM_MODE_DPMS_ON)
6436 mode = DRM_MODE_DPMS_OFF;
d4270e57 6437
5ab432ef
DV		 6438 if (mode == connector->dpms)
6439 return;
6440
6441 connector->dpms = mode;
6442
6443 /* Only need to change hw state when actually enabled */
c9976dcf
CW		 6444 if (connector->encoder)
6445 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
0a91ca29 6446
b980514c 6447 intel_modeset_check_state(connector->dev);
79e53945
JB		 6448}
6449
f0947c37
DV		 6450/* Simple connector->get_hw_state implementation for encoders that support only
6451 * one connector and no cloning and hence the encoder state determines the state
6452 * of the connector. */
6453bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 6454{
24929352 6455 enum pipe pipe = 0;
f0947c37 6456 struct intel_encoder *encoder = connector->encoder;
ea5b213a 6457
f0947c37 6458 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 6459}
6460
6d293983 6461static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 6462{
6d293983
ACO		 6463 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6464 return crtc_state->fdi_lanes;
d272ddfa
VS		 6465
6466 return 0;
6467}
6468
6d293983 6469static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6470 struct intel_crtc_state *pipe_config)
1857e1da 6471{
6d293983
ACO		 6472 struct drm_atomic_state *state = pipe_config->base.state;
6473 struct intel_crtc *other_crtc;
6474 struct intel_crtc_state *other_crtc_state;
6475
1857e1da
DV		 6476 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6477 pipe_name(pipe), pipe_config->fdi_lanes);
6478 if (pipe_config->fdi_lanes > 4) {
6479 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6480 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6481 return -EINVAL;
1857e1da
DV		 6482 }
6483
bafb6553 6484 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 6485 if (pipe_config->fdi_lanes > 2) {
6486 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6487 pipe_config->fdi_lanes);
6d293983 6488 return -EINVAL;
1857e1da 6489 } else {
6d293983 6490 return 0;
1857e1da
DV		 6491 }
6492 }
6493
6494 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 6495 return 0;
1857e1da
DV		 6496
6497 /* Ivybridge 3 pipe is really complicated */
6498 switch (pipe) {
6499 case PIPE_A:
6d293983 6500 return 0;
1857e1da 6501 case PIPE_B:
6d293983
ACO		 6502 if (pipe_config->fdi_lanes <= 2)
6503 return 0;
6504
6505 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6506 other_crtc_state =
6507 intel_atomic_get_crtc_state(state, other_crtc);
6508 if (IS_ERR(other_crtc_state))
6509 return PTR_ERR(other_crtc_state);
6510
6511 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV		 6512 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6513 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6514 return -EINVAL;
1857e1da 6515 }
6d293983 6516 return 0;
1857e1da 6517 case PIPE_C:
251cc67c
VS		 6518 if (pipe_config->fdi_lanes > 2) {
6519 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6520 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6521 return -EINVAL;
251cc67c 6522 }
6d293983
ACO		 6523
6524 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6525 other_crtc_state =
6526 intel_atomic_get_crtc_state(state, other_crtc);
6527 if (IS_ERR(other_crtc_state))
6528 return PTR_ERR(other_crtc_state);
6529
6530 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6531 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6532 return -EINVAL;
1857e1da 6533 }
6d293983 6534 return 0;
1857e1da
DV		 6535 default:
6536 BUG();
6537 }
6538}
6539
e29c22c0
DV		 6540#define RETRY 1
6541static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6542 struct intel_crtc_state *pipe_config)
877d48d5 6543{
1857e1da 6544 struct drm_device *dev = intel_crtc->base.dev;
2d112de7 6545 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 6546 int lane, link_bw, fdi_dotclock, ret;
6547 bool needs_recompute = false;
877d48d5 6548
e29c22c0 6549retry:
877d48d5
DV		 6550 /* FDI is a binary signal running at ~2.7GHz, encoding
6551 * each output octet as 10 bits. The actual frequency
6552 * is stored as a divider into a 100MHz clock, and the
6553 * mode pixel clock is stored in units of 1KHz.
6554 * Hence the bw of each lane in terms of the mode signal
6555 * is:
6556 */
6557 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6558
241bfc38 6559 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6560
2bd89a07 6561 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 6562 pipe_config->pipe_bpp);
6563
6564 pipe_config->fdi_lanes = lane;
6565
2bd89a07 6566 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6567 link_bw, &pipe_config->fdi_m_n);
1857e1da 6568
6d293983
ACO		 6569 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6570 intel_crtc->pipe, pipe_config);
6571 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV		 6572 pipe_config->pipe_bpp -= 2*3;
6573 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6574 pipe_config->pipe_bpp);
6575 needs_recompute = true;
6576 pipe_config->bw_constrained = true;
6577
6578 goto retry;
6579 }
6580
6581 if (needs_recompute)
6582 return RETRY;
6583
6d293983 6584 return ret;
877d48d5
DV		 6585}
6586
8cfb3407
VS		 6587static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6588 struct intel_crtc_state *pipe_config)
6589{
6590 if (pipe_config->pipe_bpp > 24)
6591 return false;
6592
6593 /* HSW can handle pixel rate up to cdclk? */
6594 if (IS_HASWELL(dev_priv->dev))
6595 return true;
6596
6597 /*
b432e5cf
VS		 6598 * We compare against max which means we must take
6599 * the increased cdclk requirement into account when
6600 * calculating the new cdclk.
6601 *
6602 * Should measure whether using a lower cdclk w/o IPS
8cfb3407
VS		 6603 */
6604 return ilk_pipe_pixel_rate(pipe_config) <=
6605 dev_priv->max_cdclk_freq * 95 / 100;
6606}
6607
42db64ef 6608static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6609 struct intel_crtc_state *pipe_config)
42db64ef 6610{
8cfb3407
VS		 6611 struct drm_device *dev = crtc->base.dev;
6612 struct drm_i915_private *dev_priv = dev->dev_private;
6613
d330a953 6614 pipe_config->ips_enabled = i915.enable_ips &&
8cfb3407
VS		 6615 hsw_crtc_supports_ips(crtc) &&
6616 pipe_config_supports_ips(dev_priv, pipe_config);
42db64ef
PZ		 6617}
6618
a43f6e0f 6619static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6620 struct intel_crtc_state *pipe_config)
79e53945 6621{
a43f6e0f 6622 struct drm_device *dev = crtc->base.dev;
8bd31e67 6623 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 6624 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
d03c93d4 6625 int ret;
89749350 6626
ad3a4479 6627 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 6628 if (INTEL_INFO(dev)->gen < 4) {
44913155 6629 int clock_limit = dev_priv->max_cdclk_freq;
cf532bb2
VS		 6630
6631 /*
6632 * Enable pixel doubling when the dot clock
6633 * is > 90% of the (display) core speed.
6634 *
b397c96b
VS		 6635 * GDG double wide on either pipe,
6636 * otherwise pipe A only.
cf532bb2 6637 */
b397c96b 6638 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 6639 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 6640 clock_limit *= 2;
cf532bb2 6641 pipe_config->double_wide = true;
ad3a4479
VS		 6642 }
6643
241bfc38 6644 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 6645 return -EINVAL;
2c07245f 6646 }
89749350 6647
1d1d0e27
VS		 6648 /*
6649 * Pipe horizontal size must be even in:
6650 * - DVO ganged mode
6651 * - LVDS dual channel mode
6652 * - Double wide pipe
6653 */
a93e255f 6654 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 6655 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6656 pipe_config->pipe_src_w &= ~1;
6657
8693a824
DL		 6658 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6659 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 6660 */
6661 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6662 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 6663 return -EINVAL;
44f46b42 6664
f5adf94e 6665 if (HAS_IPS(dev))
a43f6e0f
DV		 6666 hsw_compute_ips_config(crtc, pipe_config);
6667
877d48d5 6668 if (pipe_config->has_pch_encoder)
a43f6e0f 6669 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6670
d03c93d4
CK		 6671 /* FIXME: remove below call once atomic mode set is place and all crtc
6672 * related checks called from atomic_crtc_check function */
6673 ret = 0;
6674 DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6675 crtc, pipe_config->base.state);
6676 ret = intel_atomic_setup_scalers(dev, crtc, pipe_config);
6677
6678 return ret;
79e53945
JB		 6679}
6680
1652d19e
VS		 6681static int skylake_get_display_clock_speed(struct drm_device *dev)
6682{
6683 struct drm_i915_private *dev_priv = to_i915(dev);
6684 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6685 uint32_t cdctl = I915_READ(CDCLK_CTL);
6686 uint32_t linkrate;
6687
414355a7 6688 if (!(lcpll1 & LCPLL_PLL_ENABLE))
1652d19e 6689 return 24000; /* 24MHz is the cd freq with NSSC ref */
1652d19e
VS		 6690
6691 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6692 return 540000;
6693
6694 linkrate = (I915_READ(DPLL_CTRL1) &
71cd8423 6695 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1652d19e 6696
71cd8423
DL		 6697 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6698 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
1652d19e
VS		 6699 /* vco 8640 */
6700 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6701 case CDCLK_FREQ_450_432:
6702 return 432000;
6703 case CDCLK_FREQ_337_308:
6704 return 308570;
6705 case CDCLK_FREQ_675_617:
6706 return 617140;
6707 default:
6708 WARN(1, "Unknown cd freq selection\n");
6709 }
6710 } else {
6711 /* vco 8100 */
6712 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6713 case CDCLK_FREQ_450_432:
6714 return 450000;
6715 case CDCLK_FREQ_337_308:
6716 return 337500;
6717 case CDCLK_FREQ_675_617:
6718 return 675000;
6719 default:
6720 WARN(1, "Unknown cd freq selection\n");
6721 }
6722 }
6723
6724 /* error case, do as if DPLL0 isn't enabled */
6725 return 24000;
6726}
6727
6728static int broadwell_get_display_clock_speed(struct drm_device *dev)
6729{
6730 struct drm_i915_private *dev_priv = dev->dev_private;
6731 uint32_t lcpll = I915_READ(LCPLL_CTL);
6732 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6733
6734 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6735 return 800000;
6736 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6737 return 450000;
6738 else if (freq == LCPLL_CLK_FREQ_450)
6739 return 450000;
6740 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6741 return 540000;
6742 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6743 return 337500;
6744 else
6745 return 675000;
6746}
6747
6748static int haswell_get_display_clock_speed(struct drm_device *dev)
6749{
6750 struct drm_i915_private *dev_priv = dev->dev_private;
6751 uint32_t lcpll = I915_READ(LCPLL_CTL);
6752 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6753
6754 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6755 return 800000;
6756 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6757 return 450000;
6758 else if (freq == LCPLL_CLK_FREQ_450)
6759 return 450000;
6760 else if (IS_HSW_ULT(dev))
6761 return 337500;
6762 else
6763 return 540000;
79e53945
JB		 6764}
6765
25eb05fc
JB		 6766static int valleyview_get_display_clock_speed(struct drm_device *dev)
6767{
d197b7d3 6768 struct drm_i915_private *dev_priv = dev->dev_private;
d197b7d3
VS		 6769 u32 val;
6770 int divider;
6771
6bcda4f0
VS		 6772 if (dev_priv->hpll_freq == 0)
6773 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6774
a580516d 6775 mutex_lock(&dev_priv->sb_lock);
d197b7d3 6776 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
a580516d 6777 mutex_unlock(&dev_priv->sb_lock);
d197b7d3
VS		 6778
6779 divider = val & DISPLAY_FREQUENCY_VALUES;
6780
7d007f40
VS		 6781 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6782 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6783 "cdclk change in progress\n");
6784
6bcda4f0 6785 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
25eb05fc
JB		 6786}
6787
b37a6434
VS		 6788static int ilk_get_display_clock_speed(struct drm_device *dev)
6789{
6790 return 450000;
6791}
6792
e70236a8
JB		 6793static int i945_get_display_clock_speed(struct drm_device *dev)
6794{
6795 return 400000;
6796}
79e53945 6797
e70236a8 6798static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6799{
e907f170 6800 return 333333;
e70236a8 6801}
79e53945 6802
e70236a8
JB		 6803static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6804{
6805 return 200000;
6806}
79e53945 6807
257a7ffc
DV		 6808static int pnv_get_display_clock_speed(struct drm_device *dev)
6809{
6810 u16 gcfgc = 0;
6811
6812 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6813
6814 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6815 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6816 return 266667;
257a7ffc 6817 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6818 return 333333;
257a7ffc 6819 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6820 return 444444;
257a7ffc
DV		 6821 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6822 return 200000;
6823 default:
6824 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6825 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6826 return 133333;
257a7ffc 6827 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6828 return 166667;
257a7ffc
DV		 6829 }
6830}
6831
e70236a8
JB		 6832static int i915gm_get_display_clock_speed(struct drm_device *dev)
6833{
6834 u16 gcfgc = 0;
79e53945 6835
e70236a8
JB		 6836 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6837
6838 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6839 return 133333;
e70236a8
JB		 6840 else {
6841 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6842 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6843 return 333333;
e70236a8
JB		 6844 default:
6845 case GC_DISPLAY_CLOCK_190_200_MHZ:
6846 return 190000;
79e53945 6847 }
e70236a8
JB		 6848 }
6849}
6850
6851static int i865_get_display_clock_speed(struct drm_device *dev)
6852{
e907f170 6853 return 266667;
e70236a8
JB		 6854}
6855
1b1d2716 6856static int i85x_get_display_clock_speed(struct drm_device *dev)
e70236a8
JB		 6857{
6858 u16 hpllcc = 0;
1b1d2716 6859
65cd2b3f
VS		 6860 /*
6861 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6862 * encoding is different :(
6863 * FIXME is this the right way to detect 852GM/852GMV?
6864 */
6865 if (dev->pdev->revision == 0x1)
6866 return 133333;
6867
1b1d2716
VS		 6868 pci_bus_read_config_word(dev->pdev->bus,
6869 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6870
e70236a8
JB		 6871 /* Assume that the hardware is in the high speed state. This
6872 * should be the default.
6873 */
6874 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6875 case GC_CLOCK_133_200:
1b1d2716 6876 case GC_CLOCK_133_200_2:
e70236a8
JB		 6877 case GC_CLOCK_100_200:
6878 return 200000;
6879 case GC_CLOCK_166_250:
6880 return 250000;
6881 case GC_CLOCK_100_133:
e907f170 6882 return 133333;
1b1d2716
VS		 6883 case GC_CLOCK_133_266:
6884 case GC_CLOCK_133_266_2:
6885 case GC_CLOCK_166_266:
6886 return 266667;
e70236a8 6887 }
79e53945 6888
e70236a8
JB		 6889 /* Shouldn't happen */
6890 return 0;
6891}
79e53945 6892
e70236a8
JB		 6893static int i830_get_display_clock_speed(struct drm_device *dev)
6894{
e907f170 6895 return 133333;
79e53945
JB		 6896}
6897
34edce2f
VS		 6898static unsigned int intel_hpll_vco(struct drm_device *dev)
6899{
6900 struct drm_i915_private *dev_priv = dev->dev_private;
6901 static const unsigned int blb_vco[8] = {
6902 [0] = 3200000,
6903 [1] = 4000000,
6904 [2] = 5333333,
6905 [3] = 4800000,
6906 [4] = 6400000,
6907 };
6908 static const unsigned int pnv_vco[8] = {
6909 [0] = 3200000,
6910 [1] = 4000000,
6911 [2] = 5333333,
6912 [3] = 4800000,
6913 [4] = 2666667,
6914 };
6915 static const unsigned int cl_vco[8] = {
6916 [0] = 3200000,
6917 [1] = 4000000,
6918 [2] = 5333333,
6919 [3] = 6400000,
6920 [4] = 3333333,
6921 [5] = 3566667,
6922 [6] = 4266667,
6923 };
6924 static const unsigned int elk_vco[8] = {
6925 [0] = 3200000,
6926 [1] = 4000000,
6927 [2] = 5333333,
6928 [3] = 4800000,
6929 };
6930 static const unsigned int ctg_vco[8] = {
6931 [0] = 3200000,
6932 [1] = 4000000,
6933 [2] = 5333333,
6934 [3] = 6400000,
6935 [4] = 2666667,
6936 [5] = 4266667,
6937 };
6938 const unsigned int *vco_table;
6939 unsigned int vco;
6940 uint8_t tmp = 0;
6941
6942 /* FIXME other chipsets? */
6943 if (IS_GM45(dev))
6944 vco_table = ctg_vco;
6945 else if (IS_G4X(dev))
6946 vco_table = elk_vco;
6947 else if (IS_CRESTLINE(dev))
6948 vco_table = cl_vco;
6949 else if (IS_PINEVIEW(dev))
6950 vco_table = pnv_vco;
6951 else if (IS_G33(dev))
6952 vco_table = blb_vco;
6953 else
6954 return 0;
6955
6956 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6957
6958 vco = vco_table[tmp & 0x7];
6959 if (vco == 0)
6960 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6961 else
6962 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6963
6964 return vco;
6965}
6966
6967static int gm45_get_display_clock_speed(struct drm_device *dev)
6968{
6969 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6970 uint16_t tmp = 0;
6971
6972 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6973
6974 cdclk_sel = (tmp >> 12) & 0x1;
6975
6976 switch (vco) {
6977 case 2666667:
6978 case 4000000:
6979 case 5333333:
6980 return cdclk_sel ? 333333 : 222222;
6981 case 3200000:
6982 return cdclk_sel ? 320000 : 228571;
6983 default:
6984 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6985 return 222222;
6986 }
6987}
6988
6989static int i965gm_get_display_clock_speed(struct drm_device *dev)
6990{
6991 static const uint8_t div_3200[] = { 16, 10, 8 };
6992 static const uint8_t div_4000[] = { 20, 12, 10 };
6993 static const uint8_t div_5333[] = { 24, 16, 14 };
6994 const uint8_t *div_table;
6995 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6996 uint16_t tmp = 0;
6997
6998 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6999
7000 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7001
7002 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7003 goto fail;
7004
7005 switch (vco) {
7006 case 3200000:
7007 div_table = div_3200;
7008 break;
7009 case 4000000:
7010 div_table = div_4000;
7011 break;
7012 case 5333333:
7013 div_table = div_5333;
7014 break;
7015 default:
7016 goto fail;
7017 }
7018
7019 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7020
7021 fail:
7022 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7023 return 200000;
7024}
7025
7026static int g33_get_display_clock_speed(struct drm_device *dev)
7027{
7028 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7029 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7030 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7031 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7032 const uint8_t *div_table;
7033 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7034 uint16_t tmp = 0;
7035
7036 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7037
7038 cdclk_sel = (tmp >> 4) & 0x7;
7039
7040 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7041 goto fail;
7042
7043 switch (vco) {
7044 case 3200000:
7045 div_table = div_3200;
7046 break;
7047 case 4000000:
7048 div_table = div_4000;
7049 break;
7050 case 4800000:
7051 div_table = div_4800;
7052 break;
7053 case 5333333:
7054 div_table = div_5333;
7055 break;
7056 default:
7057 goto fail;
7058 }
7059
7060 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7061
7062 fail:
7063 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7064 return 190476;
7065}
7066
2c07245f 7067static void
a65851af 7068intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 7069{
a65851af
VS		 7070 while (*num > DATA_LINK_M_N_MASK ||
7071 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 7072 *num >>= 1;
7073 *den >>= 1;
7074 }
7075}
7076
a65851af
VS		 7077static void compute_m_n(unsigned int m, unsigned int n,
7078 uint32_t *ret_m, uint32_t *ret_n)
7079{
7080 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7081 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7082 intel_reduce_m_n_ratio(ret_m, ret_n);
7083}
7084
e69d0bc1
DV		 7085void
7086intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7087 int pixel_clock, int link_clock,
7088 struct intel_link_m_n *m_n)
2c07245f 7089{
e69d0bc1 7090 m_n->tu = 64;
a65851af
VS		 7091
7092 compute_m_n(bits_per_pixel * pixel_clock,
7093 link_clock * nlanes * 8,
7094 &m_n->gmch_m, &m_n->gmch_n);
7095
7096 compute_m_n(pixel_clock, link_clock,
7097 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 7098}
7099
a7615030
CW		 7100static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7101{
d330a953
JN		 7102 if (i915.panel_use_ssc >= 0)
7103 return i915.panel_use_ssc != 0;
41aa3448 7104 return dev_priv->vbt.lvds_use_ssc
435793df 7105 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 7106}
7107
a93e255f
ACO		 7108static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7109 int num_connectors)
c65d77d8 7110{
a93e255f 7111 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 7112 struct drm_i915_private *dev_priv = dev->dev_private;
7113 int refclk;
7114
a93e255f
ACO		 7115 WARN_ON(!crtc_state->base.state);
7116
5ab7b0b7 7117 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
9a0ea498 7118 refclk = 100000;
a93e255f 7119 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 7120 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 7121 refclk = dev_priv->vbt.lvds_ssc_freq;
7122 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 7123 } else if (!IS_GEN2(dev)) {
7124 refclk = 96000;
7125 } else {
7126 refclk = 48000;
7127 }
7128
7129 return refclk;
7130}
7131
7429e9d4 7132static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 7133{
7df00d7a 7134 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 7135}
f47709a9 7136
7429e9d4
DV		 7137static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7138{
7139 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 7140}
7141
f47709a9 7142static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 7143 struct intel_crtc_state *crtc_state,
a7516a05
JB		 7144 intel_clock_t *reduced_clock)
7145{
f47709a9 7146 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 7147 u32 fp, fp2 = 0;
7148
7149 if (IS_PINEVIEW(dev)) {
190f68c5 7150 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7151 if (reduced_clock)
7429e9d4 7152 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 7153 } else {
190f68c5 7154 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7155 if (reduced_clock)
7429e9d4 7156 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 7157 }
7158
190f68c5 7159 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 7160
f47709a9 7161 crtc->lowfreq_avail = false;
a93e255f 7162 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 7163 reduced_clock) {
190f68c5 7164 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 7165 crtc->lowfreq_avail = true;
a7516a05 7166 } else {
190f68c5 7167 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 7168 }
7169}
7170
5e69f97f
CML		 7171static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7172 pipe)
89b667f8
JB		 7173{
7174 u32 reg_val;
7175
7176 /*
7177 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7178 * and set it to a reasonable value instead.
7179 */
ab3c759a 7180 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 7181 reg_val &= 0xffffff00;
7182 reg_val |= 0x00000030;
ab3c759a 7183 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7184
ab3c759a 7185 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7186 reg_val &= 0x8cffffff;
7187 reg_val = 0x8c000000;
ab3c759a 7188 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 7189
ab3c759a 7190 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 7191 reg_val &= 0xffffff00;
ab3c759a 7192 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7193
ab3c759a 7194 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7195 reg_val &= 0x00ffffff;
7196 reg_val |= 0xb0000000;
ab3c759a 7197 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 7198}
7199
b551842d
DV		 7200static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7201 struct intel_link_m_n *m_n)
7202{
7203 struct drm_device *dev = crtc->base.dev;
7204 struct drm_i915_private *dev_priv = dev->dev_private;
7205 int pipe = crtc->pipe;
7206
e3b95f1e
DV		 7207 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7208 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7209 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7210 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 7211}
7212
7213static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 7214 struct intel_link_m_n *m_n,
7215 struct intel_link_m_n *m2_n2)
b551842d
DV		 7216{
7217 struct drm_device *dev = crtc->base.dev;
7218 struct drm_i915_private *dev_priv = dev->dev_private;
7219 int pipe = crtc->pipe;
6e3c9717 7220 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 7221
7222 if (INTEL_INFO(dev)->gen >= 5) {
7223 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7224 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7225 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7226 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 7227 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7228 * for gen < 8) and if DRRS is supported (to make sure the
7229 * registers are not unnecessarily accessed).
7230 */
44395bfe 7231 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 7232 crtc->config->has_drrs) {
f769cd24
VK		 7233 I915_WRITE(PIPE_DATA_M2(transcoder),
7234 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7235 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7236 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7237 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7238 }
b551842d 7239 } else {
e3b95f1e
DV		 7240 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7241 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7242 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7243 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 7244 }
7245}
7246
fe3cd48d 7247void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 7248{
fe3cd48d
R		 7249 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7250
7251 if (m_n == M1_N1) {
7252 dp_m_n = &crtc->config->dp_m_n;
7253 dp_m2_n2 = &crtc->config->dp_m2_n2;
7254 } else if (m_n == M2_N2) {
7255
7256 /*
7257 * M2_N2 registers are not supported. Hence m2_n2 divider value
7258 * needs to be programmed into M1_N1.
7259 */
7260 dp_m_n = &crtc->config->dp_m2_n2;
7261 } else {
7262 DRM_ERROR("Unsupported divider value\n");
7263 return;
7264 }
7265
6e3c9717
ACO		 7266 if (crtc->config->has_pch_encoder)
7267 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 7268 else
fe3cd48d 7269 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 7270}
7271
d288f65f 7272static void vlv_update_pll(struct intel_crtc *crtc,
5cec258b 7273 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 7274{
7275 u32 dpll, dpll_md;
7276
7277 /*
7278 * Enable DPIO clock input. We should never disable the reference
7279 * clock for pipe B, since VGA hotplug / manual detection depends
7280 * on it.
7281 */
7282 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
7283 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
7284 /* We should never disable this, set it here for state tracking */
7285 if (crtc->pipe == PIPE_B)
7286 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7287 dpll |= DPLL_VCO_ENABLE;
d288f65f 7288 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 7289
d288f65f 7290 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 7291 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 7292 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 7293}
7294
d288f65f 7295static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7296 const struct intel_crtc_state *pipe_config)
a0c4da24 7297{
f47709a9 7298 struct drm_device *dev = crtc->base.dev;
a0c4da24 7299 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 7300 int pipe = crtc->pipe;
bdd4b6a6 7301 u32 mdiv;
a0c4da24 7302 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 7303 u32 coreclk, reg_val;
a0c4da24 7304
a580516d 7305 mutex_lock(&dev_priv->sb_lock);
09153000 7306
d288f65f
VS		 7307 bestn = pipe_config->dpll.n;
7308 bestm1 = pipe_config->dpll.m1;
7309 bestm2 = pipe_config->dpll.m2;
7310 bestp1 = pipe_config->dpll.p1;
7311 bestp2 = pipe_config->dpll.p2;
a0c4da24 7312
89b667f8
JB		 7313 /* See eDP HDMI DPIO driver vbios notes doc */
7314
7315 /* PLL B needs special handling */
bdd4b6a6 7316 if (pipe == PIPE_B)
5e69f97f 7317 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 7318
7319 /* Set up Tx target for periodic Rcomp update */
ab3c759a 7320 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 7321
7322 /* Disable target IRef on PLL */
ab3c759a 7323 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 7324 reg_val &= 0x00ffffff;
ab3c759a 7325 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 7326
7327 /* Disable fast lock */
ab3c759a 7328 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 7329
7330 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 7331 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7332 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7333 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 7334 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 7335
7336 /*
7337 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7338 * but we don't support that).
7339 * Note: don't use the DAC post divider as it seems unstable.
7340 */
7341 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 7342 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7343
a0c4da24 7344 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 7345 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7346
89b667f8 7347 /* Set HBR and RBR LPF coefficients */
d288f65f 7348 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 7349 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7350 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 7351 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 7352 0x009f0003);
89b667f8 7353 else
ab3c759a 7354 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 7355 0x00d0000f);
7356
681a8504 7357 if (pipe_config->has_dp_encoder) {
89b667f8 7358 /* Use SSC source */
bdd4b6a6 7359 if (pipe == PIPE_A)
ab3c759a 7360 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7361 0x0df40000);
7362 else
ab3c759a 7363 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7364 0x0df70000);
7365 } else { /* HDMI or VGA */
7366 /* Use bend source */
bdd4b6a6 7367 if (pipe == PIPE_A)
ab3c759a 7368 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7369 0x0df70000);
7370 else
ab3c759a 7371 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7372 0x0df40000);
7373 }
a0c4da24 7374
ab3c759a 7375 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 7376 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 7377 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7378 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 7379 coreclk |= 0x01000000;
ab3c759a 7380 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 7381
ab3c759a 7382 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
a580516d 7383 mutex_unlock(&dev_priv->sb_lock);
a0c4da24
JB		 7384}
7385
d288f65f 7386static void chv_update_pll(struct intel_crtc *crtc,
5cec258b 7387 struct intel_crtc_state *pipe_config)
1ae0d137 7388{
d288f65f 7389 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
1ae0d137
VS		 7390 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7391 DPLL_VCO_ENABLE;
7392 if (crtc->pipe != PIPE_A)
d288f65f 7393 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 7394
d288f65f
VS		 7395 pipe_config->dpll_hw_state.dpll_md =
7396 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 7397}
7398
d288f65f 7399static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7400 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 7401{
7402 struct drm_device *dev = crtc->base.dev;
7403 struct drm_i915_private *dev_priv = dev->dev_private;
7404 int pipe = crtc->pipe;
7405 int dpll_reg = DPLL(crtc->pipe);
7406 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 7407 u32 loopfilter, tribuf_calcntr;
9d556c99 7408 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 7409 u32 dpio_val;
9cbe40c1 7410 int vco;
9d556c99 7411
d288f65f
VS		 7412 bestn = pipe_config->dpll.n;
7413 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7414 bestm1 = pipe_config->dpll.m1;
7415 bestm2 = pipe_config->dpll.m2 >> 22;
7416 bestp1 = pipe_config->dpll.p1;
7417 bestp2 = pipe_config->dpll.p2;
9cbe40c1 7418 vco = pipe_config->dpll.vco;
a945ce7e 7419 dpio_val = 0;
9cbe40c1 7420 loopfilter = 0;
9d556c99
CML		 7421
7422 /*
7423 * Enable Refclk and SSC
7424 */
a11b0703 7425 I915_WRITE(dpll_reg,
d288f65f 7426 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703 7427
a580516d 7428 mutex_lock(&dev_priv->sb_lock);
9d556c99 7429
9d556c99
CML		 7430 /* p1 and p2 divider */
7431 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7432 5 << DPIO_CHV_S1_DIV_SHIFT |
7433 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7434 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7435 1 << DPIO_CHV_K_DIV_SHIFT);
7436
7437 /* Feedback post-divider - m2 */
7438 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7439
7440 /* Feedback refclk divider - n and m1 */
7441 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7442 DPIO_CHV_M1_DIV_BY_2 |
7443 1 << DPIO_CHV_N_DIV_SHIFT);
7444
7445 /* M2 fraction division */
a945ce7e
VP		 7446 if (bestm2_frac)
7447 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 7448
7449 /* M2 fraction division enable */
a945ce7e
VP		 7450 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7451 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7452 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7453 if (bestm2_frac)
7454 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7455 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 7456
de3a0fde
VP		 7457 /* Program digital lock detect threshold */
7458 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7459 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7460 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7461 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7462 if (!bestm2_frac)
7463 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7464 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7465
9d556c99 7466 /* Loop filter */
9cbe40c1
VP		 7467 if (vco == 5400000) {
7468 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7469 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7470 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7471 tribuf_calcntr = 0x9;
7472 } else if (vco <= 6200000) {
7473 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7474 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7475 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7476 tribuf_calcntr = 0x9;
7477 } else if (vco <= 6480000) {
7478 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7479 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7480 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7481 tribuf_calcntr = 0x8;
7482 } else {
7483 /* Not supported. Apply the same limits as in the max case */
7484 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7485 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7486 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7487 tribuf_calcntr = 0;
7488 }
9d556c99
CML		 7489 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7490
968040b2 7491 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 7492 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7493 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7494 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7495
9d556c99
CML		 7496 /* AFC Recal */
7497 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7498 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7499 DPIO_AFC_RECAL);
7500
a580516d 7501 mutex_unlock(&dev_priv->sb_lock);
9d556c99
CML		 7502}
7503
d288f65f
VS		 7504/**
7505 * vlv_force_pll_on - forcibly enable just the PLL
7506 * @dev_priv: i915 private structure
7507 * @pipe: pipe PLL to enable
7508 * @dpll: PLL configuration
7509 *
7510 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7511 * in cases where we need the PLL enabled even when @pipe is not going to
7512 * be enabled.
7513 */
7514void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7515 const struct dpll *dpll)
7516{
7517 struct intel_crtc *crtc =
7518 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 7519 struct intel_crtc_state pipe_config = {
a93e255f 7520 .base.crtc = &crtc->base,
d288f65f
VS		 7521 .pixel_multiplier = 1,
7522 .dpll = *dpll,
7523 };
7524
7525 if (IS_CHERRYVIEW(dev)) {
7526 chv_update_pll(crtc, &pipe_config);
7527 chv_prepare_pll(crtc, &pipe_config);
7528 chv_enable_pll(crtc, &pipe_config);
7529 } else {
7530 vlv_update_pll(crtc, &pipe_config);
7531 vlv_prepare_pll(crtc, &pipe_config);
7532 vlv_enable_pll(crtc, &pipe_config);
7533 }
7534}
7535
7536/**
7537 * vlv_force_pll_off - forcibly disable just the PLL
7538 * @dev_priv: i915 private structure
7539 * @pipe: pipe PLL to disable
7540 *
7541 * Disable the PLL for @pipe. To be used in cases where we need
7542 * the PLL enabled even when @pipe is not going to be enabled.
7543 */
7544void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7545{
7546 if (IS_CHERRYVIEW(dev))
7547 chv_disable_pll(to_i915(dev), pipe);
7548 else
7549 vlv_disable_pll(to_i915(dev), pipe);
7550}
7551
f47709a9 7552static void i9xx_update_pll(struct intel_crtc *crtc,
190f68c5 7553 struct intel_crtc_state *crtc_state,
f47709a9 7554 intel_clock_t *reduced_clock,
eb1cbe48
DV		 7555 int num_connectors)
7556{
f47709a9 7557 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7558 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 7559 u32 dpll;
7560 bool is_sdvo;
190f68c5 7561 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7562
190f68c5 7563 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7564
a93e255f
ACO		 7565 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7566 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 7567
7568 dpll = DPLL_VGA_MODE_DIS;
7569
a93e255f 7570 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 7571 dpll |= DPLLB_MODE_LVDS;
7572 else
7573 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 7574
ef1b460d 7575 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 7576 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 7577 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 7578 }
198a037f
DV		 7579
7580 if (is_sdvo)
4a33e48d 7581 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 7582
190f68c5 7583 if (crtc_state->has_dp_encoder)
4a33e48d 7584 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 7585
7586 /* compute bitmask from p1 value */
7587 if (IS_PINEVIEW(dev))
7588 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7589 else {
7590 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7591 if (IS_G4X(dev) && reduced_clock)
7592 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7593 }
7594 switch (clock->p2) {
7595 case 5:
7596 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7597 break;
7598 case 7:
7599 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7600 break;
7601 case 10:
7602 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7603 break;
7604 case 14:
7605 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7606 break;
7607 }
7608 if (INTEL_INFO(dev)->gen >= 4)
7609 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7610
190f68c5 7611 if (crtc_state->sdvo_tv_clock)
eb1cbe48 7612 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 7613 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7614 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7615 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7616 else
7617 dpll |= PLL_REF_INPUT_DREFCLK;
7618
7619 dpll |= DPLL_VCO_ENABLE;
190f68c5 7620 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 7621
eb1cbe48 7622 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 7623 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 7624 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 7625 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 7626 }
7627}
7628
f47709a9 7629static void i8xx_update_pll(struct intel_crtc *crtc,
190f68c5 7630 struct intel_crtc_state *crtc_state,
f47709a9 7631 intel_clock_t *reduced_clock,
eb1cbe48
DV		 7632 int num_connectors)
7633{
f47709a9 7634 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7635 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 7636 u32 dpll;
190f68c5 7637 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7638
190f68c5 7639 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7640
eb1cbe48
DV		 7641 dpll = DPLL_VGA_MODE_DIS;
7642
a93e255f 7643 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 7644 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7645 } else {
7646 if (clock->p1 == 2)
7647 dpll |= PLL_P1_DIVIDE_BY_TWO;
7648 else
7649 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7650 if (clock->p2 == 4)
7651 dpll |= PLL_P2_DIVIDE_BY_4;
7652 }
7653
a93e255f 7654 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 7655 dpll |= DPLL_DVO_2X_MODE;
7656
a93e255f 7657 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7658 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7659 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7660 else
7661 dpll |= PLL_REF_INPUT_DREFCLK;
7662
7663 dpll |= DPLL_VCO_ENABLE;
190f68c5 7664 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 7665}
7666
8a654f3b 7667static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 7668{
7669 struct drm_device *dev = intel_crtc->base.dev;
7670 struct drm_i915_private *dev_priv = dev->dev_private;
7671 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7672 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8a654f3b 7673 struct drm_display_mode *adjusted_mode =
6e3c9717 7674 &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 7675 uint32_t crtc_vtotal, crtc_vblank_end;
7676 int vsyncshift = 0;
4d8a62ea
DV		 7677
7678 /* We need to be careful not to changed the adjusted mode, for otherwise
7679 * the hw state checker will get angry at the mismatch. */
7680 crtc_vtotal = adjusted_mode->crtc_vtotal;
7681 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 7682
609aeaca 7683 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 7684 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 7685 crtc_vtotal -= 1;
7686 crtc_vblank_end -= 1;
609aeaca 7687
409ee761 7688 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 7689 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7690 else
7691 vsyncshift = adjusted_mode->crtc_hsync_start -
7692 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 7693 if (vsyncshift < 0)
7694 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 7695 }
7696
7697 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 7698 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 7699
fe2b8f9d 7700 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 7701 (adjusted_mode->crtc_hdisplay - 1) |
7702 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 7703 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 7704 (adjusted_mode->crtc_hblank_start - 1) |
7705 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 7706 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 7707 (adjusted_mode->crtc_hsync_start - 1) |
7708 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7709
fe2b8f9d 7710 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 7711 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 7712 ((crtc_vtotal - 1) << 16));
fe2b8f9d 7713 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 7714 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 7715 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 7716 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 7717 (adjusted_mode->crtc_vsync_start - 1) |
7718 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7719
b5e508d4
PZ		 7720 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7721 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7722 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7723 * bits. */
7724 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7725 (pipe == PIPE_B || pipe == PIPE_C))
7726 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7727
b0e77b9c
PZ		 7728 /* pipesrc controls the size that is scaled from, which should
7729 * always be the user's requested size.
7730 */
7731 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 7732 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7733 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 7734}
7735
1bd1bd80 7736static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7737 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 7738{
7739 struct drm_device *dev = crtc->base.dev;
7740 struct drm_i915_private *dev_priv = dev->dev_private;
7741 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7742 uint32_t tmp;
7743
7744 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 7745 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7746 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7747 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 7748 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7749 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7750 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 7751 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7752 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7753
7754 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 7755 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7756 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7757 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 7758 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7759 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7760 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 7761 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7762 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7763
7764 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 7765 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7766 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7767 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 7768 }
7769
7770 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 7771 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7772 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7773
2d112de7
ACO		 7774 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7775 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 7776}
7777
f6a83288 7778void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7779 struct intel_crtc_state *pipe_config)
babea61d 7780{
2d112de7
ACO		 7781 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7782 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7783 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7784 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7785
2d112de7
ACO		 7786 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7787 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7788 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7789 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7790
2d112de7 7791 mode->flags = pipe_config->base.adjusted_mode.flags;
babea61d 7792
2d112de7
ACO		 7793 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7794 mode->flags |= pipe_config->base.adjusted_mode.flags;
babea61d
JB		 7795}
7796
84b046f3
DV		 7797static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7798{
7799 struct drm_device *dev = intel_crtc->base.dev;
7800 struct drm_i915_private *dev_priv = dev->dev_private;
7801 uint32_t pipeconf;
7802
9f11a9e4 7803 pipeconf = 0;
84b046f3 7804
b6b5d049
VS		 7805 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7806 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7807 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7808
6e3c9717 7809 if (intel_crtc->config->double_wide)
cf532bb2 7810 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7811
ff9ce46e
DV		 7812 /* only g4x and later have fancy bpc/dither controls */
7813 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 7814 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7815 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7816 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7817 PIPECONF_DITHER_TYPE_SP;
84b046f3 7818
6e3c9717 7819 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 7820 case 18:
7821 pipeconf |= PIPECONF_6BPC;
7822 break;
7823 case 24:
7824 pipeconf |= PIPECONF_8BPC;
7825 break;
7826 case 30:
7827 pipeconf |= PIPECONF_10BPC;
7828 break;
7829 default:
7830 /* Case prevented by intel_choose_pipe_bpp_dither. */
7831 BUG();
84b046f3
DV		 7832 }
7833 }
7834
7835 if (HAS_PIPE_CXSR(dev)) {
7836 if (intel_crtc->lowfreq_avail) {
7837 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7838 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7839 } else {
7840 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 7841 }
7842 }
7843
6e3c9717 7844 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7845 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7846 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 7847 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7848 else
7849 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7850 } else
84b046f3
DV		 7851 pipeconf |= PIPECONF_PROGRESSIVE;
7852
6e3c9717 7853 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 7854 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7855
84b046f3
DV		 7856 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7857 POSTING_READ(PIPECONF(intel_crtc->pipe));
7858}
7859
190f68c5
ACO		 7860static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7861 struct intel_crtc_state *crtc_state)
79e53945 7862{
c7653199 7863 struct drm_device *dev = crtc->base.dev;
79e53945 7864 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 7865 int refclk, num_connectors = 0;
652c393a 7866 intel_clock_t clock, reduced_clock;
a16af721 7867 bool ok, has_reduced_clock = false;
e9fd1c02 7868 bool is_lvds = false, is_dsi = false;
5eddb70b 7869 struct intel_encoder *encoder;
d4906093 7870 const intel_limit_t *limit;
55bb9992 7871 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 7872 struct drm_connector *connector;
55bb9992
ACO		 7873 struct drm_connector_state *connector_state;
7874 int i;
79e53945 7875
dd3cd74a
ACO		 7876 memset(&crtc_state->dpll_hw_state, 0,
7877 sizeof(crtc_state->dpll_hw_state));
7878
da3ced29 7879 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 7880 if (connector_state->crtc != &crtc->base)
7881 continue;
7882
7883 encoder = to_intel_encoder(connector_state->best_encoder);
7884
5eddb70b 7885 switch (encoder->type) {
79e53945
JB		 7886 case INTEL_OUTPUT_LVDS:
7887 is_lvds = true;
7888 break;
e9fd1c02
JN		 7889 case INTEL_OUTPUT_DSI:
7890 is_dsi = true;
7891 break;
6847d71b
PZ		 7892 default:
7893 break;
79e53945 7894 }
43565a06 7895
c751ce4f 7896 num_connectors++;
79e53945
JB		 7897 }
7898
f2335330 7899 if (is_dsi)
5b18e57c 7900 return 0;
f2335330 7901
190f68c5 7902 if (!crtc_state->clock_set) {
a93e255f 7903 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 7904
e9fd1c02
JN		 7905 /*
7906 * Returns a set of divisors for the desired target clock with
7907 * the given refclk, or FALSE. The returned values represent
7908 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7909 * 2) / p1 / p2.
7910 */
a93e255f
ACO		 7911 limit = intel_limit(crtc_state, refclk);
7912 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7913 crtc_state->port_clock,
e9fd1c02 7914 refclk, NULL, &clock);
f2335330 7915 if (!ok) {
e9fd1c02
JN		 7916 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7917 return -EINVAL;
7918 }
79e53945 7919
f2335330
JN		 7920 if (is_lvds && dev_priv->lvds_downclock_avail) {
7921 /*
7922 * Ensure we match the reduced clock's P to the target
7923 * clock. If the clocks don't match, we can't switch
7924 * the display clock by using the FP0/FP1. In such case
7925 * we will disable the LVDS downclock feature.
7926 */
7927 has_reduced_clock =
a93e255f 7928 dev_priv->display.find_dpll(limit, crtc_state,
f2335330
JN		 7929 dev_priv->lvds_downclock,
7930 refclk, &clock,
7931 &reduced_clock);
7932 }
7933 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7934 crtc_state->dpll.n = clock.n;
7935 crtc_state->dpll.m1 = clock.m1;
7936 crtc_state->dpll.m2 = clock.m2;
7937 crtc_state->dpll.p1 = clock.p1;
7938 crtc_state->dpll.p2 = clock.p2;
f47709a9 7939 }
7026d4ac 7940
e9fd1c02 7941 if (IS_GEN2(dev)) {
190f68c5 7942 i8xx_update_pll(crtc, crtc_state,
2a8f64ca
VP		 7943 has_reduced_clock ? &reduced_clock : NULL,
7944 num_connectors);
9d556c99 7945 } else if (IS_CHERRYVIEW(dev)) {
190f68c5 7946 chv_update_pll(crtc, crtc_state);
e9fd1c02 7947 } else if (IS_VALLEYVIEW(dev)) {
190f68c5 7948 vlv_update_pll(crtc, crtc_state);
e9fd1c02 7949 } else {
190f68c5 7950 i9xx_update_pll(crtc, crtc_state,
eb1cbe48 7951 has_reduced_clock ? &reduced_clock : NULL,
eba905b2 7952 num_connectors);
e9fd1c02 7953 }
79e53945 7954
c8f7a0db 7955 return 0;
f564048e
EA		 7956}
7957
2fa2fe9a 7958static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7959 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 7960{
7961 struct drm_device *dev = crtc->base.dev;
7962 struct drm_i915_private *dev_priv = dev->dev_private;
7963 uint32_t tmp;
7964
dc9e7dec
VS		 7965 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7966 return;
7967
2fa2fe9a 7968 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 7969 if (!(tmp & PFIT_ENABLE))
7970 return;
2fa2fe9a 7971
06922821 7972 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 7973 if (INTEL_INFO(dev)->gen < 4) {
7974 if (crtc->pipe != PIPE_B)
7975 return;
2fa2fe9a
DV		 7976 } else {
7977 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7978 return;
7979 }
7980
06922821 7981 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 7982 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7983 if (INTEL_INFO(dev)->gen < 5)
7984 pipe_config->gmch_pfit.lvds_border_bits =
7985 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7986}
7987
acbec814 7988static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7989 struct intel_crtc_state *pipe_config)
acbec814
JB		 7990{
7991 struct drm_device *dev = crtc->base.dev;
7992 struct drm_i915_private *dev_priv = dev->dev_private;
7993 int pipe = pipe_config->cpu_transcoder;
7994 intel_clock_t clock;
7995 u32 mdiv;
662c6ecb 7996 int refclk = 100000;
acbec814 7997
f573de5a
SK		 7998 /* In case of MIPI DPLL will not even be used */
7999 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
8000 return;
8001
a580516d 8002 mutex_lock(&dev_priv->sb_lock);
ab3c759a 8003 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
a580516d 8004 mutex_unlock(&dev_priv->sb_lock);
acbec814
JB		 8005
8006 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8007 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8008 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8009 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8010 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8011
f646628b 8012 vlv_clock(refclk, &clock);
acbec814 8013
f646628b
VS		 8014 /* clock.dot is the fast clock */
8015 pipe_config->port_clock = clock.dot / 5;
acbec814
JB		 8016}
8017
5724dbd1
DL		 8018static void
8019i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8020 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 8021{
8022 struct drm_device *dev = crtc->base.dev;
8023 struct drm_i915_private *dev_priv = dev->dev_private;
8024 u32 val, base, offset;
8025 int pipe = crtc->pipe, plane = crtc->plane;
8026 int fourcc, pixel_format;
6761dd31 8027 unsigned int aligned_height;
b113d5ee 8028 struct drm_framebuffer *fb;
1b842c89 8029 struct intel_framebuffer *intel_fb;
1ad292b5 8030
42a7b088
DL		 8031 val = I915_READ(DSPCNTR(plane));
8032 if (!(val & DISPLAY_PLANE_ENABLE))
8033 return;
8034
d9806c9f 8035 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8036 if (!intel_fb) {
1ad292b5
JB		 8037 DRM_DEBUG_KMS("failed to alloc fb\n");
8038 return;
8039 }
8040
1b842c89
DL		 8041 fb = &intel_fb->base;
8042
18c5247e
DV		 8043 if (INTEL_INFO(dev)->gen >= 4) {
8044 if (val & DISPPLANE_TILED) {
49af449b 8045 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 8046 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8047 }
8048 }
1ad292b5
JB		 8049
8050 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 8051 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 8052 fb->pixel_format = fourcc;
8053 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 8054
8055 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 8056 if (plane_config->tiling)
1ad292b5
JB		 8057 offset = I915_READ(DSPTILEOFF(plane));
8058 else
8059 offset = I915_READ(DSPLINOFF(plane));
8060 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8061 } else {
8062 base = I915_READ(DSPADDR(plane));
8063 }
8064 plane_config->base = base;
8065
8066 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 8067 fb->width = ((val >> 16) & 0xfff) + 1;
8068 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 8069
8070 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 8071 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 8072
b113d5ee 8073 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8074 fb->pixel_format,
8075 fb->modifier[0]);
1ad292b5 8076
f37b5c2b 8077 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 8078
2844a921
DL		 8079 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8080 pipe_name(pipe), plane, fb->width, fb->height,
8081 fb->bits_per_pixel, base, fb->pitches[0],
8082 plane_config->size);
1ad292b5 8083
2d14030b 8084 plane_config->fb = intel_fb;
1ad292b5
JB		 8085}
8086
70b23a98 8087static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 8088 struct intel_crtc_state *pipe_config)
70b23a98
VS		 8089{
8090 struct drm_device *dev = crtc->base.dev;
8091 struct drm_i915_private *dev_priv = dev->dev_private;
8092 int pipe = pipe_config->cpu_transcoder;
8093 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8094 intel_clock_t clock;
8095 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
8096 int refclk = 100000;
8097
a580516d 8098 mutex_lock(&dev_priv->sb_lock);
70b23a98
VS		 8099 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8100 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8101 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8102 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
a580516d 8103 mutex_unlock(&dev_priv->sb_lock);
70b23a98
VS		 8104
8105 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8106 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
8107 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8108 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8109 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8110
8111 chv_clock(refclk, &clock);
8112
8113 /* clock.dot is the fast clock */
8114 pipe_config->port_clock = clock.dot / 5;
8115}
8116
0e8ffe1b 8117static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8118 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8119{
8120 struct drm_device *dev = crtc->base.dev;
8121 struct drm_i915_private *dev_priv = dev->dev_private;
8122 uint32_t tmp;
8123
f458ebbc
DV		 8124 if (!intel_display_power_is_enabled(dev_priv,
8125 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 8126 return false;
8127
e143a21c 8128 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8129 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8130
0e8ffe1b
DV		 8131 tmp = I915_READ(PIPECONF(crtc->pipe));
8132 if (!(tmp & PIPECONF_ENABLE))
8133 return false;
8134
42571aef
VS		 8135 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8136 switch (tmp & PIPECONF_BPC_MASK) {
8137 case PIPECONF_6BPC:
8138 pipe_config->pipe_bpp = 18;
8139 break;
8140 case PIPECONF_8BPC:
8141 pipe_config->pipe_bpp = 24;
8142 break;
8143 case PIPECONF_10BPC:
8144 pipe_config->pipe_bpp = 30;
8145 break;
8146 default:
8147 break;
8148 }
8149 }
8150
b5a9fa09
DV		 8151 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8152 pipe_config->limited_color_range = true;
8153
282740f7
VS		 8154 if (INTEL_INFO(dev)->gen < 4)
8155 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8156
1bd1bd80
DV		 8157 intel_get_pipe_timings(crtc, pipe_config);
8158
2fa2fe9a
DV		 8159 i9xx_get_pfit_config(crtc, pipe_config);
8160
6c49f241
DV		 8161 if (INTEL_INFO(dev)->gen >= 4) {
8162 tmp = I915_READ(DPLL_MD(crtc->pipe));
8163 pipe_config->pixel_multiplier =
8164 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8165 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 8166 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 8167 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8168 tmp = I915_READ(DPLL(crtc->pipe));
8169 pipe_config->pixel_multiplier =
8170 ((tmp & SDVO_MULTIPLIER_MASK)
8171 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8172 } else {
8173 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8174 * port and will be fixed up in the encoder->get_config
8175 * function. */
8176 pipe_config->pixel_multiplier = 1;
8177 }
8bcc2795
DV		 8178 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8179 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 8180 /*
8181 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8182 * on 830. Filter it out here so that we don't
8183 * report errors due to that.
8184 */
8185 if (IS_I830(dev))
8186 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8187
8bcc2795
DV		 8188 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8189 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 8190 } else {
8191 /* Mask out read-only status bits. */
8192 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8193 DPLL_PORTC_READY_MASK |
8194 DPLL_PORTB_READY_MASK);
8bcc2795 8195 }
6c49f241 8196
70b23a98
VS		 8197 if (IS_CHERRYVIEW(dev))
8198 chv_crtc_clock_get(crtc, pipe_config);
8199 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 8200 vlv_crtc_clock_get(crtc, pipe_config);
8201 else
8202 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 8203
0e8ffe1b
DV		 8204 return true;
8205}
8206
dde86e2d 8207static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 8208{
8209 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 8210 struct intel_encoder *encoder;
74cfd7ac 8211 u32 val, final;
13d83a67 8212 bool has_lvds = false;
199e5d79 8213 bool has_cpu_edp = false;
199e5d79 8214 bool has_panel = false;
99eb6a01
KP		 8215 bool has_ck505 = false;
8216 bool can_ssc = false;
13d83a67
JB		 8217
8218 /* We need to take the global config into account */
b2784e15 8219 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 8220 switch (encoder->type) {
8221 case INTEL_OUTPUT_LVDS:
8222 has_panel = true;
8223 has_lvds = true;
8224 break;
8225 case INTEL_OUTPUT_EDP:
8226 has_panel = true;
2de6905f 8227 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 8228 has_cpu_edp = true;
8229 break;
6847d71b
PZ		 8230 default:
8231 break;
13d83a67
JB		 8232 }
8233 }
8234
99eb6a01 8235 if (HAS_PCH_IBX(dev)) {
41aa3448 8236 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 8237 can_ssc = has_ck505;
8238 } else {
8239 has_ck505 = false;
8240 can_ssc = true;
8241 }
8242
2de6905f
ID		 8243 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8244 has_panel, has_lvds, has_ck505);
13d83a67
JB		 8245
8246 /* Ironlake: try to setup display ref clock before DPLL
8247 * enabling. This is only under driver's control after
8248 * PCH B stepping, previous chipset stepping should be
8249 * ignoring this setting.
8250 */
74cfd7ac
CW		 8251 val = I915_READ(PCH_DREF_CONTROL);
8252
8253 /* As we must carefully and slowly disable/enable each source in turn,
8254 * compute the final state we want first and check if we need to
8255 * make any changes at all.
8256 */
8257 final = val;
8258 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8259 if (has_ck505)
8260 final |= DREF_NONSPREAD_CK505_ENABLE;
8261 else
8262 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8263
8264 final &= ~DREF_SSC_SOURCE_MASK;
8265 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8266 final &= ~DREF_SSC1_ENABLE;
8267
8268 if (has_panel) {
8269 final |= DREF_SSC_SOURCE_ENABLE;
8270
8271 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8272 final |= DREF_SSC1_ENABLE;
8273
8274 if (has_cpu_edp) {
8275 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8276 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8277 else
8278 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8279 } else
8280 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8281 } else {
8282 final |= DREF_SSC_SOURCE_DISABLE;
8283 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8284 }
8285
8286 if (final == val)
8287 return;
8288
13d83a67 8289 /* Always enable nonspread source */
74cfd7ac 8290 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 8291
99eb6a01 8292 if (has_ck505)
74cfd7ac 8293 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 8294 else
74cfd7ac 8295 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 8296
199e5d79 8297 if (has_panel) {
74cfd7ac
CW		 8298 val &= ~DREF_SSC_SOURCE_MASK;
8299 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 8300
199e5d79 8301 /* SSC must be turned on before enabling the CPU output */
99eb6a01 8302 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8303 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 8304 val |= DREF_SSC1_ENABLE;
e77166b5 8305 } else
74cfd7ac 8306 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 8307
8308 /* Get SSC going before enabling the outputs */
74cfd7ac 8309 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8310 POSTING_READ(PCH_DREF_CONTROL);
8311 udelay(200);
8312
74cfd7ac 8313 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 8314
8315 /* Enable CPU source on CPU attached eDP */
199e5d79 8316 if (has_cpu_edp) {
99eb6a01 8317 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8318 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 8319 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 8320 } else
74cfd7ac 8321 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 8322 } else
74cfd7ac 8323 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8324
74cfd7ac 8325 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8326 POSTING_READ(PCH_DREF_CONTROL);
8327 udelay(200);
8328 } else {
8329 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8330
74cfd7ac 8331 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 8332
8333 /* Turn off CPU output */
74cfd7ac 8334 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8335
74cfd7ac 8336 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8337 POSTING_READ(PCH_DREF_CONTROL);
8338 udelay(200);
8339
8340 /* Turn off the SSC source */
74cfd7ac
CW		 8341 val &= ~DREF_SSC_SOURCE_MASK;
8342 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 8343
8344 /* Turn off SSC1 */
74cfd7ac 8345 val &= ~DREF_SSC1_ENABLE;
199e5d79 8346
74cfd7ac 8347 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 8348 POSTING_READ(PCH_DREF_CONTROL);
8349 udelay(200);
8350 }
74cfd7ac
CW		 8351
8352 BUG_ON(val != final);
13d83a67
JB		 8353}
8354
f31f2d55 8355static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 8356{
f31f2d55 8357 uint32_t tmp;
dde86e2d 8358
0ff066a9
PZ		 8359 tmp = I915_READ(SOUTH_CHICKEN2);
8360 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8361 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8362
0ff066a9
PZ		 8363 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8364 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8365 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 8366
0ff066a9
PZ		 8367 tmp = I915_READ(SOUTH_CHICKEN2);
8368 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8369 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8370
0ff066a9
PZ		 8371 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8372 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8373 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 8374}
8375
8376/* WaMPhyProgramming:hsw */
8377static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8378{
8379 uint32_t tmp;
dde86e2d
PZ		 8380
8381 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8382 tmp &= ~(0xFF << 24);
8383 tmp |= (0x12 << 24);
8384 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8385
dde86e2d
PZ		 8386 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8387 tmp |= (1 << 11);
8388 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8389
8390 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8391 tmp |= (1 << 11);
8392 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8393
dde86e2d
PZ		 8394 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8395 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8396 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8397
8398 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8399 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8400 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8401
0ff066a9
PZ		 8402 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8403 tmp &= ~(7 << 13);
8404 tmp |= (5 << 13);
8405 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 8406
0ff066a9
PZ		 8407 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8408 tmp &= ~(7 << 13);
8409 tmp |= (5 << 13);
8410 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 8411
8412 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8413 tmp &= ~0xFF;
8414 tmp |= 0x1C;
8415 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8416
8417 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8418 tmp &= ~0xFF;
8419 tmp |= 0x1C;
8420 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8421
8422 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8423 tmp &= ~(0xFF << 16);
8424 tmp |= (0x1C << 16);
8425 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8426
8427 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8428 tmp &= ~(0xFF << 16);
8429 tmp |= (0x1C << 16);
8430 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8431
0ff066a9
PZ		 8432 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8433 tmp |= (1 << 27);
8434 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 8435
0ff066a9
PZ		 8436 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8437 tmp |= (1 << 27);
8438 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 8439
0ff066a9
PZ		 8440 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8441 tmp &= ~(0xF << 28);
8442 tmp |= (4 << 28);
8443 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 8444
0ff066a9
PZ		 8445 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8446 tmp &= ~(0xF << 28);
8447 tmp |= (4 << 28);
8448 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 8449}
8450
2fa86a1f
PZ		 8451/* Implements 3 different sequences from BSpec chapter "Display iCLK
8452 * Programming" based on the parameters passed:
8453 * - Sequence to enable CLKOUT_DP
8454 * - Sequence to enable CLKOUT_DP without spread
8455 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8456 */
8457static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8458 bool with_fdi)
f31f2d55
PZ		 8459{
8460 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 8461 uint32_t reg, tmp;
8462
8463 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8464 with_spread = true;
8465 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8466 with_fdi, "LP PCH doesn't have FDI\n"))
8467 with_fdi = false;
f31f2d55 8468
a580516d 8469 mutex_lock(&dev_priv->sb_lock);
f31f2d55
PZ		 8470
8471 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8472 tmp &= ~SBI_SSCCTL_DISABLE;
8473 tmp |= SBI_SSCCTL_PATHALT;
8474 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8475
8476 udelay(24);
8477
2fa86a1f
PZ		 8478 if (with_spread) {
8479 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8480 tmp &= ~SBI_SSCCTL_PATHALT;
8481 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 8482
2fa86a1f
PZ		 8483 if (with_fdi) {
8484 lpt_reset_fdi_mphy(dev_priv);
8485 lpt_program_fdi_mphy(dev_priv);
8486 }
8487 }
dde86e2d 8488
2fa86a1f
PZ		 8489 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8490 SBI_GEN0 : SBI_DBUFF0;
8491 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8492 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8493 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246 8494
a580516d 8495 mutex_unlock(&dev_priv->sb_lock);
dde86e2d
PZ		 8496}
8497
47701c3b
PZ		 8498/* Sequence to disable CLKOUT_DP */
8499static void lpt_disable_clkout_dp(struct drm_device *dev)
8500{
8501 struct drm_i915_private *dev_priv = dev->dev_private;
8502 uint32_t reg, tmp;
8503
a580516d 8504 mutex_lock(&dev_priv->sb_lock);
47701c3b
PZ		 8505
8506 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8507 SBI_GEN0 : SBI_DBUFF0;
8508 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8509 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8510 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8511
8512 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8513 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8514 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8515 tmp |= SBI_SSCCTL_PATHALT;
8516 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8517 udelay(32);
8518 }
8519 tmp |= SBI_SSCCTL_DISABLE;
8520 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8521 }
8522
a580516d 8523 mutex_unlock(&dev_priv->sb_lock);
47701c3b
PZ		 8524}
8525
bf8fa3d3
PZ		 8526static void lpt_init_pch_refclk(struct drm_device *dev)
8527{
bf8fa3d3
PZ		 8528 struct intel_encoder *encoder;
8529 bool has_vga = false;
8530
b2784e15 8531 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 8532 switch (encoder->type) {
8533 case INTEL_OUTPUT_ANALOG:
8534 has_vga = true;
8535 break;
6847d71b
PZ		 8536 default:
8537 break;
bf8fa3d3
PZ		 8538 }
8539 }
8540
47701c3b
PZ		 8541 if (has_vga)
8542 lpt_enable_clkout_dp(dev, true, true);
8543 else
8544 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 8545}
8546
dde86e2d
PZ		 8547/*
8548 * Initialize reference clocks when the driver loads
8549 */
8550void intel_init_pch_refclk(struct drm_device *dev)
8551{
8552 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8553 ironlake_init_pch_refclk(dev);
8554 else if (HAS_PCH_LPT(dev))
8555 lpt_init_pch_refclk(dev);
8556}
8557
55bb9992 8558static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 8559{
55bb9992 8560 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 8561 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8562 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8563 struct drm_connector *connector;
55bb9992 8564 struct drm_connector_state *connector_state;
d9d444cb 8565 struct intel_encoder *encoder;
55bb9992 8566 int num_connectors = 0, i;
d9d444cb
JB		 8567 bool is_lvds = false;
8568
da3ced29 8569 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8570 if (connector_state->crtc != crtc_state->base.crtc)
8571 continue;
8572
8573 encoder = to_intel_encoder(connector_state->best_encoder);
8574
d9d444cb
JB		 8575 switch (encoder->type) {
8576 case INTEL_OUTPUT_LVDS:
8577 is_lvds = true;
8578 break;
6847d71b
PZ		 8579 default:
8580 break;
d9d444cb
JB		 8581 }
8582 num_connectors++;
8583 }
8584
8585 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 8586 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 8587 dev_priv->vbt.lvds_ssc_freq);
e91e941b 8588 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 8589 }
8590
8591 return 120000;
8592}
8593
6ff93609 8594static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 8595{
c8203565 8596 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 8597 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8598 int pipe = intel_crtc->pipe;
c8203565
PZ		 8599 uint32_t val;
8600
78114071 8601 val = 0;
c8203565 8602
6e3c9717 8603 switch (intel_crtc->config->pipe_bpp) {
c8203565 8604 case 18:
dfd07d72 8605 val |= PIPECONF_6BPC;
c8203565
PZ		 8606 break;
8607 case 24:
dfd07d72 8608 val |= PIPECONF_8BPC;
c8203565
PZ		 8609 break;
8610 case 30:
dfd07d72 8611 val |= PIPECONF_10BPC;
c8203565
PZ		 8612 break;
8613 case 36:
dfd07d72 8614 val |= PIPECONF_12BPC;
c8203565
PZ		 8615 break;
8616 default:
cc769b62
PZ		 8617 /* Case prevented by intel_choose_pipe_bpp_dither. */
8618 BUG();
c8203565
PZ		 8619 }
8620
6e3c9717 8621 if (intel_crtc->config->dither)
c8203565
PZ		 8622 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8623
6e3c9717 8624 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 8625 val |= PIPECONF_INTERLACED_ILK;
8626 else
8627 val |= PIPECONF_PROGRESSIVE;
8628
6e3c9717 8629 if (intel_crtc->config->limited_color_range)
3685a8f3 8630 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 8631
c8203565
PZ		 8632 I915_WRITE(PIPECONF(pipe), val);
8633 POSTING_READ(PIPECONF(pipe));
8634}
8635
86d3efce
VS		 8636/*
8637 * Set up the pipe CSC unit.
8638 *
8639 * Currently only full range RGB to limited range RGB conversion
8640 * is supported, but eventually this should handle various
8641 * RGB<->YCbCr scenarios as well.
8642 */
50f3b016 8643static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 8644{
8645 struct drm_device *dev = crtc->dev;
8646 struct drm_i915_private *dev_priv = dev->dev_private;
8647 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8648 int pipe = intel_crtc->pipe;
8649 uint16_t coeff = 0x7800; /* 1.0 */
8650
8651 /*
8652 * TODO: Check what kind of values actually come out of the pipe
8653 * with these coeff/postoff values and adjust to get the best
8654 * accuracy. Perhaps we even need to take the bpc value into
8655 * consideration.
8656 */
8657
6e3c9717 8658 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8659 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8660
8661 /*
8662 * GY/GU and RY/RU should be the other way around according
8663 * to BSpec, but reality doesn't agree. Just set them up in
8664 * a way that results in the correct picture.
8665 */
8666 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8667 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8668
8669 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8670 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8671
8672 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8673 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8674
8675 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8676 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8677 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8678
8679 if (INTEL_INFO(dev)->gen > 6) {
8680 uint16_t postoff = 0;
8681
6e3c9717 8682 if (intel_crtc->config->limited_color_range)
32cf0cb0 8683 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 8684
8685 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8686 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8687 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8688
8689 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8690 } else {
8691 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8692
6e3c9717 8693 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8694 mode |= CSC_BLACK_SCREEN_OFFSET;
8695
8696 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8697 }
8698}
8699
6ff93609 8700static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8701{
756f85cf
PZ		 8702 struct drm_device *dev = crtc->dev;
8703 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 8704 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8705 enum pipe pipe = intel_crtc->pipe;
6e3c9717 8706 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 8707 uint32_t val;
8708
3eff4faa 8709 val = 0;
ee2b0b38 8710
6e3c9717 8711 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 8712 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8713
6e3c9717 8714 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 8715 val |= PIPECONF_INTERLACED_ILK;
8716 else
8717 val |= PIPECONF_PROGRESSIVE;
8718
702e7a56
PZ		 8719 I915_WRITE(PIPECONF(cpu_transcoder), val);
8720 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 8721
8722 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8723 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 8724
3cdf122c 8725 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 8726 val = 0;
8727
6e3c9717 8728 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 8729 case 18:
8730 val |= PIPEMISC_DITHER_6_BPC;
8731 break;
8732 case 24:
8733 val |= PIPEMISC_DITHER_8_BPC;
8734 break;
8735 case 30:
8736 val |= PIPEMISC_DITHER_10_BPC;
8737 break;
8738 case 36:
8739 val |= PIPEMISC_DITHER_12_BPC;
8740 break;
8741 default:
8742 /* Case prevented by pipe_config_set_bpp. */
8743 BUG();
8744 }
8745
6e3c9717 8746 if (intel_crtc->config->dither)
756f85cf
PZ		 8747 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8748
8749 I915_WRITE(PIPEMISC(pipe), val);
8750 }
ee2b0b38
PZ		 8751}
8752
6591c6e4 8753static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 8754 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 8755 intel_clock_t *clock,
8756 bool *has_reduced_clock,
8757 intel_clock_t *reduced_clock)
8758{
8759 struct drm_device *dev = crtc->dev;
8760 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 8761 int refclk;
d4906093 8762 const intel_limit_t *limit;
a16af721 8763 bool ret, is_lvds = false;
79e53945 8764
a93e255f 8765 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
79e53945 8766
55bb9992 8767 refclk = ironlake_get_refclk(crtc_state);
79e53945 8768
d4906093
ML		 8769 /*
8770 * Returns a set of divisors for the desired target clock with the given
8771 * refclk, or FALSE. The returned values represent the clock equation:
8772 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8773 */
a93e255f
ACO		 8774 limit = intel_limit(crtc_state, refclk);
8775 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 8776 crtc_state->port_clock,
ee9300bb 8777 refclk, NULL, clock);
6591c6e4
PZ		 8778 if (!ret)
8779 return false;
cda4b7d3 8780
ddc9003c 8781 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 8782 /*
8783 * Ensure we match the reduced clock's P to the target clock.
8784 * If the clocks don't match, we can't switch the display clock
8785 * by using the FP0/FP1. In such case we will disable the LVDS
8786 * downclock feature.
8787 */
ee9300bb 8788 *has_reduced_clock =
a93e255f 8789 dev_priv->display.find_dpll(limit, crtc_state,
ee9300bb
DV		 8790 dev_priv->lvds_downclock,
8791 refclk, clock,
8792 reduced_clock);
652c393a 8793 }
61e9653f 8794
6591c6e4
PZ		 8795 return true;
8796}
8797
d4b1931c
PZ		 8798int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8799{
8800 /*
8801 * Account for spread spectrum to avoid
8802 * oversubscribing the link. Max center spread
8803 * is 2.5%; use 5% for safety's sake.
8804 */
8805 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8806 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 8807}
8808
7429e9d4 8809static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8810{
7429e9d4 8811 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 8812}
8813
de13a2e3 8814static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 8815 struct intel_crtc_state *crtc_state,
7429e9d4 8816 u32 *fp,
9a7c7890 8817 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 8818{
de13a2e3 8819 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 8820 struct drm_device *dev = crtc->dev;
8821 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8822 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8823 struct drm_connector *connector;
55bb9992
ACO		 8824 struct drm_connector_state *connector_state;
8825 struct intel_encoder *encoder;
de13a2e3 8826 uint32_t dpll;
55bb9992 8827 int factor, num_connectors = 0, i;
09ede541 8828 bool is_lvds = false, is_sdvo = false;
79e53945 8829
da3ced29 8830 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8831 if (connector_state->crtc != crtc_state->base.crtc)
8832 continue;
8833
8834 encoder = to_intel_encoder(connector_state->best_encoder);
8835
8836 switch (encoder->type) {
79e53945
JB		 8837 case INTEL_OUTPUT_LVDS:
8838 is_lvds = true;
8839 break;
8840 case INTEL_OUTPUT_SDVO:
7d57382e 8841 case INTEL_OUTPUT_HDMI:
79e53945 8842 is_sdvo = true;
79e53945 8843 break;
6847d71b
PZ		 8844 default:
8845 break;
79e53945 8846 }
43565a06 8847
c751ce4f 8848 num_connectors++;
79e53945 8849 }
79e53945 8850
c1858123 8851 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 8852 factor = 21;
8853 if (is_lvds) {
8854 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8855 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8856 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8857 factor = 25;
190f68c5 8858 } else if (crtc_state->sdvo_tv_clock)
8febb297 8859 factor = 20;
c1858123 8860
190f68c5 8861 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 8862 *fp |= FP_CB_TUNE;
2c07245f 8863
9a7c7890
DV		 8864 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8865 *fp2 |= FP_CB_TUNE;
8866
5eddb70b 8867 dpll = 0;
2c07245f 8868
a07d6787
EA		 8869 if (is_lvds)
8870 dpll |= DPLLB_MODE_LVDS;
8871 else
8872 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8873
190f68c5 8874 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8875 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 8876
8877 if (is_sdvo)
4a33e48d 8878 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8879 if (crtc_state->has_dp_encoder)
4a33e48d 8880 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8881
a07d6787 8882 /* compute bitmask from p1 value */
190f68c5 8883 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8884 /* also FPA1 */
190f68c5 8885 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8886
190f68c5 8887 switch (crtc_state->dpll.p2) {
a07d6787
EA		 8888 case 5:
8889 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8890 break;
8891 case 7:
8892 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8893 break;
8894 case 10:
8895 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8896 break;
8897 case 14:
8898 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8899 break;
79e53945
JB		 8900 }
8901
b4c09f3b 8902 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 8903 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 8904 else
8905 dpll |= PLL_REF_INPUT_DREFCLK;
8906
959e16d6 8907 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 8908}
8909
190f68c5
ACO		 8910static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8911 struct intel_crtc_state *crtc_state)
de13a2e3 8912{
c7653199 8913 struct drm_device *dev = crtc->base.dev;
de13a2e3 8914 intel_clock_t clock, reduced_clock;
cbbab5bd 8915 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 8916 bool ok, has_reduced_clock = false;
8b47047b 8917 bool is_lvds = false;
e2b78267 8918 struct intel_shared_dpll *pll;
de13a2e3 8919
dd3cd74a
ACO		 8920 memset(&crtc_state->dpll_hw_state, 0,
8921 sizeof(crtc_state->dpll_hw_state));
8922
409ee761 8923 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 8924
5dc5298b
PZ		 8925 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8926 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 8927
190f68c5 8928 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 8929 &has_reduced_clock, &reduced_clock);
190f68c5 8930 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 8931 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8932 return -EINVAL;
79e53945 8933 }
f47709a9 8934 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 8935 if (!crtc_state->clock_set) {
8936 crtc_state->dpll.n = clock.n;
8937 crtc_state->dpll.m1 = clock.m1;
8938 crtc_state->dpll.m2 = clock.m2;
8939 crtc_state->dpll.p1 = clock.p1;
8940 crtc_state->dpll.p2 = clock.p2;
f47709a9 8941 }
79e53945 8942
5dc5298b 8943 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 8944 if (crtc_state->has_pch_encoder) {
8945 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 8946 if (has_reduced_clock)
7429e9d4 8947 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 8948
190f68c5 8949 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 8950 &fp, &reduced_clock,
8951 has_reduced_clock ? &fp2 : NULL);
8952
190f68c5
ACO		 8953 crtc_state->dpll_hw_state.dpll = dpll;
8954 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 8955 if (has_reduced_clock)
190f68c5 8956 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 8957 else
190f68c5 8958 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 8959
190f68c5 8960 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 8961 if (pll == NULL) {
84f44ce7 8962 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 8963 pipe_name(crtc->pipe));
4b645f14
JB		 8964 return -EINVAL;
8965 }
3fb37703 8966 }
79e53945 8967
ab585dea 8968 if (is_lvds && has_reduced_clock)
c7653199 8969 crtc->lowfreq_avail = true;
bcd644e0 8970 else
c7653199 8971 crtc->lowfreq_avail = false;
e2b78267 8972
c8f7a0db 8973 return 0;
79e53945
JB		 8974}
8975
eb14cb74
VS		 8976static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8977 struct intel_link_m_n *m_n)
8978{
8979 struct drm_device *dev = crtc->base.dev;
8980 struct drm_i915_private *dev_priv = dev->dev_private;
8981 enum pipe pipe = crtc->pipe;
8982
8983 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8984 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8985 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8986 & ~TU_SIZE_MASK;
8987 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8988 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8989 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8990}
8991
8992static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8993 enum transcoder transcoder,
b95af8be
VK		 8994 struct intel_link_m_n *m_n,
8995 struct intel_link_m_n *m2_n2)
72419203
DV		 8996{
8997 struct drm_device *dev = crtc->base.dev;
8998 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 8999 enum pipe pipe = crtc->pipe;
72419203 9000
eb14cb74
VS		 9001 if (INTEL_INFO(dev)->gen >= 5) {
9002 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9003 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9004 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9005 & ~TU_SIZE_MASK;
9006 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9007 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9008 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 9009 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9010 * gen < 8) and if DRRS is supported (to make sure the
9011 * registers are not unnecessarily read).
9012 */
9013 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 9014 crtc->config->has_drrs) {
b95af8be
VK		 9015 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9016 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9017 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9018 & ~TU_SIZE_MASK;
9019 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9020 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9021 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9022 }
eb14cb74
VS		 9023 } else {
9024 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9025 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9026 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9027 & ~TU_SIZE_MASK;
9028 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9029 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9030 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9031 }
9032}
9033
9034void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 9035 struct intel_crtc_state *pipe_config)
eb14cb74 9036{
681a8504 9037 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 9038 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9039 else
9040 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 9041 &pipe_config->dp_m_n,
9042 &pipe_config->dp_m2_n2);
eb14cb74 9043}
72419203 9044
eb14cb74 9045static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 9046 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 9047{
9048 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 9049 &pipe_config->fdi_m_n, NULL);
72419203
DV		 9050}
9051
bd2e244f 9052static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9053 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 9054{
9055 struct drm_device *dev = crtc->base.dev;
9056 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK		 9057 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9058 uint32_t ps_ctrl = 0;
9059 int id = -1;
9060 int i;
bd2e244f 9061
a1b2278e
CK		 9062 /* find scaler attached to this pipe */
9063 for (i = 0; i < crtc->num_scalers; i++) {
9064 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9065 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9066 id = i;
9067 pipe_config->pch_pfit.enabled = true;
9068 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9069 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9070 break;
9071 }
9072 }
bd2e244f 9073
a1b2278e
CK		 9074 scaler_state->scaler_id = id;
9075 if (id >= 0) {
9076 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9077 } else {
9078 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB		 9079 }
9080}
9081
5724dbd1
DL		 9082static void
9083skylake_get_initial_plane_config(struct intel_crtc *crtc,
9084 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 9085{
9086 struct drm_device *dev = crtc->base.dev;
9087 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 9088 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 9089 int pipe = crtc->pipe;
9090 int fourcc, pixel_format;
6761dd31 9091 unsigned int aligned_height;
bc8d7dff 9092 struct drm_framebuffer *fb;
1b842c89 9093 struct intel_framebuffer *intel_fb;
bc8d7dff 9094
d9806c9f 9095 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9096 if (!intel_fb) {
bc8d7dff
DL		 9097 DRM_DEBUG_KMS("failed to alloc fb\n");
9098 return;
9099 }
9100
1b842c89
DL		 9101 fb = &intel_fb->base;
9102
bc8d7dff 9103 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 9104 if (!(val & PLANE_CTL_ENABLE))
9105 goto error;
9106
bc8d7dff
DL		 9107 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9108 fourcc = skl_format_to_fourcc(pixel_format,
9109 val & PLANE_CTL_ORDER_RGBX,
9110 val & PLANE_CTL_ALPHA_MASK);
9111 fb->pixel_format = fourcc;
9112 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9113
40f46283
DL		 9114 tiling = val & PLANE_CTL_TILED_MASK;
9115 switch (tiling) {
9116 case PLANE_CTL_TILED_LINEAR:
9117 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9118 break;
9119 case PLANE_CTL_TILED_X:
9120 plane_config->tiling = I915_TILING_X;
9121 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9122 break;
9123 case PLANE_CTL_TILED_Y:
9124 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9125 break;
9126 case PLANE_CTL_TILED_YF:
9127 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9128 break;
9129 default:
9130 MISSING_CASE(tiling);
9131 goto error;
9132 }
9133
bc8d7dff
DL		 9134 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9135 plane_config->base = base;
9136
9137 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9138
9139 val = I915_READ(PLANE_SIZE(pipe, 0));
9140 fb->height = ((val >> 16) & 0xfff) + 1;
9141 fb->width = ((val >> 0) & 0x1fff) + 1;
9142
9143 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 9144 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9145 fb->pixel_format);
bc8d7dff
DL		 9146 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9147
9148 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9149 fb->pixel_format,
9150 fb->modifier[0]);
bc8d7dff 9151
f37b5c2b 9152 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 9153
9154 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9155 pipe_name(pipe), fb->width, fb->height,
9156 fb->bits_per_pixel, base, fb->pitches[0],
9157 plane_config->size);
9158
2d14030b 9159 plane_config->fb = intel_fb;
bc8d7dff
DL		 9160 return;
9161
9162error:
9163 kfree(fb);
9164}
9165
2fa2fe9a 9166static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9167 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 9168{
9169 struct drm_device *dev = crtc->base.dev;
9170 struct drm_i915_private *dev_priv = dev->dev_private;
9171 uint32_t tmp;
9172
9173 tmp = I915_READ(PF_CTL(crtc->pipe));
9174
9175 if (tmp & PF_ENABLE) {
fd4daa9c 9176 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 9177 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9178 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 9179
9180 /* We currently do not free assignements of panel fitters on
9181 * ivb/hsw (since we don't use the higher upscaling modes which
9182 * differentiates them) so just WARN about this case for now. */
9183 if (IS_GEN7(dev)) {
9184 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9185 PF_PIPE_SEL_IVB(crtc->pipe));
9186 }
2fa2fe9a 9187 }
79e53945
JB		 9188}
9189
5724dbd1
DL		 9190static void
9191ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9192 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 9193{
9194 struct drm_device *dev = crtc->base.dev;
9195 struct drm_i915_private *dev_priv = dev->dev_private;
9196 u32 val, base, offset;
aeee5a49 9197 int pipe = crtc->pipe;
4c6baa59 9198 int fourcc, pixel_format;
6761dd31 9199 unsigned int aligned_height;
b113d5ee 9200 struct drm_framebuffer *fb;
1b842c89 9201 struct intel_framebuffer *intel_fb;
4c6baa59 9202
42a7b088
DL		 9203 val = I915_READ(DSPCNTR(pipe));
9204 if (!(val & DISPLAY_PLANE_ENABLE))
9205 return;
9206
d9806c9f 9207 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9208 if (!intel_fb) {
4c6baa59
JB		 9209 DRM_DEBUG_KMS("failed to alloc fb\n");
9210 return;
9211 }
9212
1b842c89
DL		 9213 fb = &intel_fb->base;
9214
18c5247e
DV		 9215 if (INTEL_INFO(dev)->gen >= 4) {
9216 if (val & DISPPLANE_TILED) {
49af449b 9217 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 9218 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9219 }
9220 }
4c6baa59
JB		 9221
9222 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 9223 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 9224 fb->pixel_format = fourcc;
9225 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 9226
aeee5a49 9227 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 9228 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 9229 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 9230 } else {
49af449b 9231 if (plane_config->tiling)
aeee5a49 9232 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 9233 else
aeee5a49 9234 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 9235 }
9236 plane_config->base = base;
9237
9238 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 9239 fb->width = ((val >> 16) & 0xfff) + 1;
9240 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 9241
9242 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 9243 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 9244
b113d5ee 9245 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9246 fb->pixel_format,
9247 fb->modifier[0]);
4c6baa59 9248
f37b5c2b 9249 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 9250
2844a921
DL		 9251 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9252 pipe_name(pipe), fb->width, fb->height,
9253 fb->bits_per_pixel, base, fb->pitches[0],
9254 plane_config->size);
b113d5ee 9255
2d14030b 9256 plane_config->fb = intel_fb;
4c6baa59
JB		 9257}
9258
0e8ffe1b 9259static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9260 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9261{
9262 struct drm_device *dev = crtc->base.dev;
9263 struct drm_i915_private *dev_priv = dev->dev_private;
9264 uint32_t tmp;
9265
f458ebbc
DV		 9266 if (!intel_display_power_is_enabled(dev_priv,
9267 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 9268 return false;
9269
e143a21c 9270 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 9271 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 9272
0e8ffe1b
DV		 9273 tmp = I915_READ(PIPECONF(crtc->pipe));
9274 if (!(tmp & PIPECONF_ENABLE))
9275 return false;
9276
42571aef
VS		 9277 switch (tmp & PIPECONF_BPC_MASK) {
9278 case PIPECONF_6BPC:
9279 pipe_config->pipe_bpp = 18;
9280 break;
9281 case PIPECONF_8BPC:
9282 pipe_config->pipe_bpp = 24;
9283 break;
9284 case PIPECONF_10BPC:
9285 pipe_config->pipe_bpp = 30;
9286 break;
9287 case PIPECONF_12BPC:
9288 pipe_config->pipe_bpp = 36;
9289 break;
9290 default:
9291 break;
9292 }
9293
b5a9fa09
DV		 9294 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9295 pipe_config->limited_color_range = true;
9296
ab9412ba 9297 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 9298 struct intel_shared_dpll *pll;
9299
88adfff1
DV		 9300 pipe_config->has_pch_encoder = true;
9301
627eb5a3
DV		 9302 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9303 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9304 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 9305
9306 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 9307
c0d43d62 9308 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 9309 pipe_config->shared_dpll =
9310 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 9311 } else {
9312 tmp = I915_READ(PCH_DPLL_SEL);
9313 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9314 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9315 else
9316 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9317 }
66e985c0
DV		 9318
9319 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9320
9321 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9322 &pipe_config->dpll_hw_state));
c93f54cf
DV		 9323
9324 tmp = pipe_config->dpll_hw_state.dpll;
9325 pipe_config->pixel_multiplier =
9326 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9327 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 9328
9329 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 9330 } else {
9331 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 9332 }
9333
1bd1bd80
DV		 9334 intel_get_pipe_timings(crtc, pipe_config);
9335
2fa2fe9a
DV		 9336 ironlake_get_pfit_config(crtc, pipe_config);
9337
0e8ffe1b
DV		 9338 return true;
9339}
9340
be256dc7
PZ		 9341static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9342{
9343 struct drm_device *dev = dev_priv->dev;
be256dc7 9344 struct intel_crtc *crtc;
be256dc7 9345
d3fcc808 9346 for_each_intel_crtc(dev, crtc)
e2c719b7 9347 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 9348 pipe_name(crtc->pipe));
9349
e2c719b7
RC		 9350 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9351 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9352 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9353 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9354 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9355 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 9356 "CPU PWM1 enabled\n");
c5107b87 9357 if (IS_HASWELL(dev))
e2c719b7 9358 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 9359 "CPU PWM2 enabled\n");
e2c719b7 9360 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 9361 "PCH PWM1 enabled\n");
e2c719b7 9362 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 9363 "Utility pin enabled\n");
e2c719b7 9364 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 9365
9926ada1
PZ		 9366 /*
9367 * In theory we can still leave IRQs enabled, as long as only the HPD
9368 * interrupts remain enabled. We used to check for that, but since it's
9369 * gen-specific and since we only disable LCPLL after we fully disable
9370 * the interrupts, the check below should be enough.
9371 */
e2c719b7 9372 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 9373}
9374
9ccd5aeb
PZ		 9375static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9376{
9377 struct drm_device *dev = dev_priv->dev;
9378
9379 if (IS_HASWELL(dev))
9380 return I915_READ(D_COMP_HSW);
9381 else
9382 return I915_READ(D_COMP_BDW);
9383}
9384
3c4c9b81
PZ		 9385static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9386{
9387 struct drm_device *dev = dev_priv->dev;
9388
9389 if (IS_HASWELL(dev)) {
9390 mutex_lock(&dev_priv->rps.hw_lock);
9391 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9392 val))
f475dadf 9393 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 9394 mutex_unlock(&dev_priv->rps.hw_lock);
9395 } else {
9ccd5aeb
PZ		 9396 I915_WRITE(D_COMP_BDW, val);
9397 POSTING_READ(D_COMP_BDW);
3c4c9b81 9398 }
be256dc7
PZ		 9399}
9400
9401/*
9402 * This function implements pieces of two sequences from BSpec:
9403 * - Sequence for display software to disable LCPLL
9404 * - Sequence for display software to allow package C8+
9405 * The steps implemented here are just the steps that actually touch the LCPLL
9406 * register. Callers should take care of disabling all the display engine
9407 * functions, doing the mode unset, fixing interrupts, etc.
9408 */
6ff58d53
PZ		 9409static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9410 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 9411{
9412 uint32_t val;
9413
9414 assert_can_disable_lcpll(dev_priv);
9415
9416 val = I915_READ(LCPLL_CTL);
9417
9418 if (switch_to_fclk) {
9419 val |= LCPLL_CD_SOURCE_FCLK;
9420 I915_WRITE(LCPLL_CTL, val);
9421
9422 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9423 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9424 DRM_ERROR("Switching to FCLK failed\n");
9425
9426 val = I915_READ(LCPLL_CTL);
9427 }
9428
9429 val |= LCPLL_PLL_DISABLE;
9430 I915_WRITE(LCPLL_CTL, val);
9431 POSTING_READ(LCPLL_CTL);
9432
9433 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9434 DRM_ERROR("LCPLL still locked\n");
9435
9ccd5aeb 9436 val = hsw_read_dcomp(dev_priv);
be256dc7 9437 val |= D_COMP_COMP_DISABLE;
3c4c9b81 9438 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9439 ndelay(100);
9440
9ccd5aeb
PZ		 9441 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9442 1))
be256dc7
PZ		 9443 DRM_ERROR("D_COMP RCOMP still in progress\n");
9444
9445 if (allow_power_down) {
9446 val = I915_READ(LCPLL_CTL);
9447 val |= LCPLL_POWER_DOWN_ALLOW;
9448 I915_WRITE(LCPLL_CTL, val);
9449 POSTING_READ(LCPLL_CTL);
9450 }
9451}
9452
9453/*
9454 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9455 * source.
9456 */
6ff58d53 9457static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 9458{
9459 uint32_t val;
9460
9461 val = I915_READ(LCPLL_CTL);
9462
9463 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9464 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9465 return;
9466
a8a8bd54
PZ		 9467 /*
9468 * Make sure we're not on PC8 state before disabling PC8, otherwise
9469 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 9470 */
59bad947 9471 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 9472
be256dc7
PZ		 9473 if (val & LCPLL_POWER_DOWN_ALLOW) {
9474 val &= ~LCPLL_POWER_DOWN_ALLOW;
9475 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 9476 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 9477 }
9478
9ccd5aeb 9479 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 9480 val |= D_COMP_COMP_FORCE;
9481 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 9482 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9483
9484 val = I915_READ(LCPLL_CTL);
9485 val &= ~LCPLL_PLL_DISABLE;
9486 I915_WRITE(LCPLL_CTL, val);
9487
9488 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9489 DRM_ERROR("LCPLL not locked yet\n");
9490
9491 if (val & LCPLL_CD_SOURCE_FCLK) {
9492 val = I915_READ(LCPLL_CTL);
9493 val &= ~LCPLL_CD_SOURCE_FCLK;
9494 I915_WRITE(LCPLL_CTL, val);
9495
9496 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9497 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9498 DRM_ERROR("Switching back to LCPLL failed\n");
9499 }
215733fa 9500
59bad947 9501 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b6283055 9502 intel_update_cdclk(dev_priv->dev);
be256dc7
PZ		 9503}
9504
765dab67
PZ		 9505/*
9506 * Package states C8 and deeper are really deep PC states that can only be
9507 * reached when all the devices on the system allow it, so even if the graphics
9508 * device allows PC8+, it doesn't mean the system will actually get to these
9509 * states. Our driver only allows PC8+ when going into runtime PM.
9510 *
9511 * The requirements for PC8+ are that all the outputs are disabled, the power
9512 * well is disabled and most interrupts are disabled, and these are also
9513 * requirements for runtime PM. When these conditions are met, we manually do
9514 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9515 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9516 * hang the machine.
9517 *
9518 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9519 * the state of some registers, so when we come back from PC8+ we need to
9520 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9521 * need to take care of the registers kept by RC6. Notice that this happens even
9522 * if we don't put the device in PCI D3 state (which is what currently happens
9523 * because of the runtime PM support).
9524 *
9525 * For more, read "Display Sequences for Package C8" on the hardware
9526 * documentation.
9527 */
a14cb6fc 9528void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 9529{
c67a470b
PZ		 9530 struct drm_device *dev = dev_priv->dev;
9531 uint32_t val;
9532
c67a470b
PZ		 9533 DRM_DEBUG_KMS("Enabling package C8+\n");
9534
c67a470b
PZ		 9535 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9536 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9537 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9538 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9539 }
9540
9541 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 9542 hsw_disable_lcpll(dev_priv, true, true);
9543}
9544
a14cb6fc 9545void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 9546{
9547 struct drm_device *dev = dev_priv->dev;
9548 uint32_t val;
9549
c67a470b
PZ		 9550 DRM_DEBUG_KMS("Disabling package C8+\n");
9551
9552 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 9553 lpt_init_pch_refclk(dev);
9554
9555 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9556 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9557 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9558 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9559 }
9560
9561 intel_prepare_ddi(dev);
c67a470b
PZ		 9562}
9563
a821fc46 9564static void broxton_modeset_global_resources(struct drm_atomic_state *old_state)
f8437dd1 9565{
a821fc46 9566 struct drm_device *dev = old_state->dev;
f8437dd1 9567 struct drm_i915_private *dev_priv = dev->dev_private;
a821fc46 9568 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
f8437dd1
VK		 9569 int req_cdclk;
9570
9571 /* see the comment in valleyview_modeset_global_resources */
9572 if (WARN_ON(max_pixclk < 0))
9573 return;
9574
9575 req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
9576
9577 if (req_cdclk != dev_priv->cdclk_freq)
9578 broxton_set_cdclk(dev, req_cdclk);
9579}
9580
b432e5cf
VS		 9581/* compute the max rate for new configuration */
9582static int ilk_max_pixel_rate(struct drm_i915_private *dev_priv)
9583{
9584 struct drm_device *dev = dev_priv->dev;
9585 struct intel_crtc *intel_crtc;
9586 struct drm_crtc *crtc;
9587 int max_pixel_rate = 0;
9588 int pixel_rate;
9589
9590 for_each_crtc(dev, crtc) {
9591 if (!crtc->state->enable)
9592 continue;
9593
9594 intel_crtc = to_intel_crtc(crtc);
9595 pixel_rate = ilk_pipe_pixel_rate(intel_crtc->config);
9596
9597 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9598 if (IS_BROADWELL(dev) && intel_crtc->config->ips_enabled)
9599 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9600
9601 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9602 }
9603
9604 return max_pixel_rate;
9605}
9606
9607static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9608{
9609 struct drm_i915_private *dev_priv = dev->dev_private;
9610 uint32_t val, data;
9611 int ret;
9612
9613 if (WARN((I915_READ(LCPLL_CTL) &
9614 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9615 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9616 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9617 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9618 "trying to change cdclk frequency with cdclk not enabled\n"))
9619 return;
9620
9621 mutex_lock(&dev_priv->rps.hw_lock);
9622 ret = sandybridge_pcode_write(dev_priv,
9623 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9624 mutex_unlock(&dev_priv->rps.hw_lock);
9625 if (ret) {
9626 DRM_ERROR("failed to inform pcode about cdclk change\n");
9627 return;
9628 }
9629
9630 val = I915_READ(LCPLL_CTL);
9631 val |= LCPLL_CD_SOURCE_FCLK;
9632 I915_WRITE(LCPLL_CTL, val);
9633
9634 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9635 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9636 DRM_ERROR("Switching to FCLK failed\n");
9637
9638 val = I915_READ(LCPLL_CTL);
9639 val &= ~LCPLL_CLK_FREQ_MASK;
9640
9641 switch (cdclk) {
9642 case 450000:
9643 val |= LCPLL_CLK_FREQ_450;
9644 data = 0;
9645 break;
9646 case 540000:
9647 val |= LCPLL_CLK_FREQ_54O_BDW;
9648 data = 1;
9649 break;
9650 case 337500:
9651 val |= LCPLL_CLK_FREQ_337_5_BDW;
9652 data = 2;
9653 break;
9654 case 675000:
9655 val |= LCPLL_CLK_FREQ_675_BDW;
9656 data = 3;
9657 break;
9658 default:
9659 WARN(1, "invalid cdclk frequency\n");
9660 return;
9661 }
9662
9663 I915_WRITE(LCPLL_CTL, val);
9664
9665 val = I915_READ(LCPLL_CTL);
9666 val &= ~LCPLL_CD_SOURCE_FCLK;
9667 I915_WRITE(LCPLL_CTL, val);
9668
9669 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9670 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9671 DRM_ERROR("Switching back to LCPLL failed\n");
9672
9673 mutex_lock(&dev_priv->rps.hw_lock);
9674 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9675 mutex_unlock(&dev_priv->rps.hw_lock);
9676
9677 intel_update_cdclk(dev);
9678
9679 WARN(cdclk != dev_priv->cdclk_freq,
9680 "cdclk requested %d kHz but got %d kHz\n",
9681 cdclk, dev_priv->cdclk_freq);
9682}
9683
9684static int broadwell_calc_cdclk(struct drm_i915_private *dev_priv,
9685 int max_pixel_rate)
9686{
9687 int cdclk;
9688
9689 /*
9690 * FIXME should also account for plane ratio
9691 * once 64bpp pixel formats are supported.
9692 */
9693 if (max_pixel_rate > 540000)
9694 cdclk = 675000;
9695 else if (max_pixel_rate > 450000)
9696 cdclk = 540000;
9697 else if (max_pixel_rate > 337500)
9698 cdclk = 450000;
9699 else
9700 cdclk = 337500;
9701
9702 /*
9703 * FIXME move the cdclk caclulation to
9704 * compute_config() so we can fail gracegully.
9705 */
9706 if (cdclk > dev_priv->max_cdclk_freq) {
9707 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9708 cdclk, dev_priv->max_cdclk_freq);
9709 cdclk = dev_priv->max_cdclk_freq;
9710 }
9711
9712 return cdclk;
9713}
9714
9715static int broadwell_modeset_global_pipes(struct drm_atomic_state *state)
9716{
9717 struct drm_i915_private *dev_priv = to_i915(state->dev);
9718 struct drm_crtc *crtc;
9719 struct drm_crtc_state *crtc_state;
9720 int max_pixclk = ilk_max_pixel_rate(dev_priv);
9721 int cdclk, i;
9722
9723 cdclk = broadwell_calc_cdclk(dev_priv, max_pixclk);
9724
9725 if (cdclk == dev_priv->cdclk_freq)
9726 return 0;
9727
9728 /* add all active pipes to the state */
9729 for_each_crtc(state->dev, crtc) {
9730 if (!crtc->state->enable)
9731 continue;
9732
9733 crtc_state = drm_atomic_get_crtc_state(state, crtc);
9734 if (IS_ERR(crtc_state))
9735 return PTR_ERR(crtc_state);
9736 }
9737
9738 /* disable/enable all currently active pipes while we change cdclk */
9739 for_each_crtc_in_state(state, crtc, crtc_state, i)
9740 if (crtc_state->enable)
9741 crtc_state->mode_changed = true;
9742
9743 return 0;
9744}
9745
9746static void broadwell_modeset_global_resources(struct drm_atomic_state *state)
9747{
9748 struct drm_device *dev = state->dev;
9749 struct drm_i915_private *dev_priv = dev->dev_private;
9750 int max_pixel_rate = ilk_max_pixel_rate(dev_priv);
9751 int req_cdclk = broadwell_calc_cdclk(dev_priv, max_pixel_rate);
9752
9753 if (req_cdclk != dev_priv->cdclk_freq)
9754 broadwell_set_cdclk(dev, req_cdclk);
9755}
9756
190f68c5
ACO		 9757static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9758 struct intel_crtc_state *crtc_state)
09b4ddf9 9759{
190f68c5 9760 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 9761 return -EINVAL;
716c2e55 9762
c7653199 9763 crtc->lowfreq_avail = false;
644cef34 9764
c8f7a0db 9765 return 0;
79e53945
JB		 9766}
9767
3760b59c
S		 9768static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9769 enum port port,
9770 struct intel_crtc_state *pipe_config)
9771{
9772 switch (port) {
9773 case PORT_A:
9774 pipe_config->ddi_pll_sel = SKL_DPLL0;
9775 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9776 break;
9777 case PORT_B:
9778 pipe_config->ddi_pll_sel = SKL_DPLL1;
9779 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9780 break;
9781 case PORT_C:
9782 pipe_config->ddi_pll_sel = SKL_DPLL2;
9783 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9784 break;
9785 default:
9786 DRM_ERROR("Incorrect port type\n");
9787 }
9788}
9789
96b7dfb7
S		 9790static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9791 enum port port,
5cec258b 9792 struct intel_crtc_state *pipe_config)
96b7dfb7 9793{
3148ade7 9794 u32 temp, dpll_ctl1;
96b7dfb7
S		 9795
9796 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9797 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9798
9799 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 9800 case SKL_DPLL0:
9801 /*
9802 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9803 * of the shared DPLL framework and thus needs to be read out
9804 * separately
9805 */
9806 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9807 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9808 break;
96b7dfb7
S		 9809 case SKL_DPLL1:
9810 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9811 break;
9812 case SKL_DPLL2:
9813 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9814 break;
9815 case SKL_DPLL3:
9816 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9817 break;
96b7dfb7
S		 9818 }
9819}
9820
7d2c8175
DL		 9821static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9822 enum port port,
5cec258b 9823 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 9824{
9825 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9826
9827 switch (pipe_config->ddi_pll_sel) {
9828 case PORT_CLK_SEL_WRPLL1:
9829 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9830 break;
9831 case PORT_CLK_SEL_WRPLL2:
9832 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9833 break;
9834 }
9835}
9836
26804afd 9837static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 9838 struct intel_crtc_state *pipe_config)
26804afd
DV		 9839{
9840 struct drm_device *dev = crtc->base.dev;
9841 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 9842 struct intel_shared_dpll *pll;
26804afd
DV		 9843 enum port port;
9844 uint32_t tmp;
9845
9846 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9847
9848 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9849
96b7dfb7
S		 9850 if (IS_SKYLAKE(dev))
9851 skylake_get_ddi_pll(dev_priv, port, pipe_config);
3760b59c
S		 9852 else if (IS_BROXTON(dev))
9853 bxt_get_ddi_pll(dev_priv, port, pipe_config);
96b7dfb7
S		 9854 else
9855 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 9856
d452c5b6
DV		 9857 if (pipe_config->shared_dpll >= 0) {
9858 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9859
9860 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9861 &pipe_config->dpll_hw_state));
9862 }
9863
26804afd
DV		 9864 /*
9865 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9866 * DDI E. So just check whether this pipe is wired to DDI E and whether
9867 * the PCH transcoder is on.
9868 */
ca370455
DL		 9869 if (INTEL_INFO(dev)->gen < 9 &&
9870 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 9871 pipe_config->has_pch_encoder = true;
9872
9873 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9874 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9875 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9876
9877 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9878 }
9879}
9880
0e8ffe1b 9881static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9882 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9883{
9884 struct drm_device *dev = crtc->base.dev;
9885 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 9886 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 9887 uint32_t tmp;
9888
f458ebbc 9889 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 9890 POWER_DOMAIN_PIPE(crtc->pipe)))
9891 return false;
9892
e143a21c 9893 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 9894 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9895
eccb140b
DV		 9896 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9897 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9898 enum pipe trans_edp_pipe;
9899 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9900 default:
9901 WARN(1, "unknown pipe linked to edp transcoder\n");
9902 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9903 case TRANS_DDI_EDP_INPUT_A_ON:
9904 trans_edp_pipe = PIPE_A;
9905 break;
9906 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9907 trans_edp_pipe = PIPE_B;
9908 break;
9909 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9910 trans_edp_pipe = PIPE_C;
9911 break;
9912 }
9913
9914 if (trans_edp_pipe == crtc->pipe)
9915 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9916 }
9917
f458ebbc 9918 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 9919 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 9920 return false;
9921
eccb140b 9922 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 9923 if (!(tmp & PIPECONF_ENABLE))
9924 return false;
9925
26804afd 9926 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 9927
1bd1bd80
DV		 9928 intel_get_pipe_timings(crtc, pipe_config);
9929
a1b2278e
CK		 9930 if (INTEL_INFO(dev)->gen >= 9) {
9931 skl_init_scalers(dev, crtc, pipe_config);
9932 }
9933
2fa2fe9a 9934 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
af99ceda
CK		 9935
9936 if (INTEL_INFO(dev)->gen >= 9) {
9937 pipe_config->scaler_state.scaler_id = -1;
9938 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9939 }
9940
bd2e244f 9941 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
ff6d9f55 9942 if (INTEL_INFO(dev)->gen == 9)
bd2e244f 9943 skylake_get_pfit_config(crtc, pipe_config);
ff6d9f55 9944 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 9945 ironlake_get_pfit_config(crtc, pipe_config);
ff6d9f55
JB		 9946 else
9947 MISSING_CASE(INTEL_INFO(dev)->gen);
bd2e244f 9948 }
88adfff1 9949
e59150dc
JB		 9950 if (IS_HASWELL(dev))
9951 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9952 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 9953
ebb69c95
CT		 9954 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9955 pipe_config->pixel_multiplier =
9956 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9957 } else {
9958 pipe_config->pixel_multiplier = 1;
9959 }
6c49f241 9960
0e8ffe1b
DV		 9961 return true;
9962}
9963
560b85bb
CW		 9964static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9965{
9966 struct drm_device *dev = crtc->dev;
9967 struct drm_i915_private *dev_priv = dev->dev_private;
9968 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 9969 uint32_t cntl = 0, size = 0;
560b85bb 9970
dc41c154 9971 if (base) {
3dd512fb
MR		 9972 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9973 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 9974 unsigned int stride = roundup_pow_of_two(width) * 4;
9975
9976 switch (stride) {
9977 default:
9978 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9979 width, stride);
9980 stride = 256;
9981 /* fallthrough */
9982 case 256:
9983 case 512:
9984 case 1024:
9985 case 2048:
9986 break;
4b0e333e
CW		 9987 }
9988
dc41c154
VS		 9989 cntl |= CURSOR_ENABLE |
9990 CURSOR_GAMMA_ENABLE |
9991 CURSOR_FORMAT_ARGB |
9992 CURSOR_STRIDE(stride);
9993
9994 size = (height << 12) | width;
4b0e333e 9995 }
560b85bb 9996
dc41c154
VS		 9997 if (intel_crtc->cursor_cntl != 0 &&
9998 (intel_crtc->cursor_base != base ||
9999 intel_crtc->cursor_size != size ||
10000 intel_crtc->cursor_cntl != cntl)) {
10001 /* On these chipsets we can only modify the base/size/stride
10002 * whilst the cursor is disabled.
10003 */
10004 I915_WRITE(_CURACNTR, 0);
4b0e333e 10005 POSTING_READ(_CURACNTR);
dc41c154 10006 intel_crtc->cursor_cntl = 0;
4b0e333e 10007 }
560b85bb 10008
99d1f387 10009 if (intel_crtc->cursor_base != base) {
9db4a9c7 10010 I915_WRITE(_CURABASE, base);
99d1f387
VS		 10011 intel_crtc->cursor_base = base;
10012 }
4726e0b0 10013
dc41c154
VS		 10014 if (intel_crtc->cursor_size != size) {
10015 I915_WRITE(CURSIZE, size);
10016 intel_crtc->cursor_size = size;
4b0e333e 10017 }
560b85bb 10018
4b0e333e 10019 if (intel_crtc->cursor_cntl != cntl) {
4b0e333e
CW		 10020 I915_WRITE(_CURACNTR, cntl);
10021 POSTING_READ(_CURACNTR);
4b0e333e 10022 intel_crtc->cursor_cntl = cntl;
560b85bb 10023 }
560b85bb
CW		 10024}
10025
560b85bb 10026static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 10027{
10028 struct drm_device *dev = crtc->dev;
10029 struct drm_i915_private *dev_priv = dev->dev_private;
10030 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10031 int pipe = intel_crtc->pipe;
4b0e333e
CW		 10032 uint32_t cntl;
10033
10034 cntl = 0;
10035 if (base) {
10036 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 10037 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 10038 case 64:
10039 cntl |= CURSOR_MODE_64_ARGB_AX;
10040 break;
10041 case 128:
10042 cntl |= CURSOR_MODE_128_ARGB_AX;
10043 break;
10044 case 256:
10045 cntl |= CURSOR_MODE_256_ARGB_AX;
10046 break;
10047 default:
3dd512fb 10048 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 10049 return;
65a21cd6 10050 }
4b0e333e 10051 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS		 10052
10053 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
10054 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 10055 }
65a21cd6 10056
8e7d688b 10057 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 10058 cntl |= CURSOR_ROTATE_180;
10059
4b0e333e
CW		 10060 if (intel_crtc->cursor_cntl != cntl) {
10061 I915_WRITE(CURCNTR(pipe), cntl);
10062 POSTING_READ(CURCNTR(pipe));
10063 intel_crtc->cursor_cntl = cntl;
65a21cd6 10064 }
4b0e333e 10065
65a21cd6 10066 /* and commit changes on next vblank */
5efb3e28
VS		 10067 I915_WRITE(CURBASE(pipe), base);
10068 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 10069
10070 intel_crtc->cursor_base = base;
65a21cd6
JB		 10071}
10072
cda4b7d3 10073/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 10074static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10075 bool on)
cda4b7d3
CW		 10076{
10077 struct drm_device *dev = crtc->dev;
10078 struct drm_i915_private *dev_priv = dev->dev_private;
10079 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10080 int pipe = intel_crtc->pipe;
3d7d6510
MR		 10081 int x = crtc->cursor_x;
10082 int y = crtc->cursor_y;
d6e4db15 10083 u32 base = 0, pos = 0;
cda4b7d3 10084
d6e4db15 10085 if (on)
cda4b7d3 10086 base = intel_crtc->cursor_addr;
cda4b7d3 10087
6e3c9717 10088 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 10089 base = 0;
10090
6e3c9717 10091 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 10092 base = 0;
10093
10094 if (x < 0) {
3dd512fb 10095 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
cda4b7d3
CW		 10096 base = 0;
10097
10098 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10099 x = -x;
10100 }
10101 pos |= x << CURSOR_X_SHIFT;
10102
10103 if (y < 0) {
3dd512fb 10104 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
cda4b7d3
CW		 10105 base = 0;
10106
10107 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10108 y = -y;
10109 }
10110 pos |= y << CURSOR_Y_SHIFT;
10111
4b0e333e 10112 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 10113 return;
10114
5efb3e28
VS		 10115 I915_WRITE(CURPOS(pipe), pos);
10116
4398ad45
VS		 10117 /* ILK+ do this automagically */
10118 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 10119 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
3dd512fb
MR		 10120 base += (intel_crtc->base.cursor->state->crtc_h *
10121 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
4398ad45
VS		 10122 }
10123
8ac54669 10124 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 10125 i845_update_cursor(crtc, base);
10126 else
10127 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 10128}
10129
dc41c154
VS		 10130static bool cursor_size_ok(struct drm_device *dev,
10131 uint32_t width, uint32_t height)
10132{
10133 if (width == 0 || height == 0)
10134 return false;
10135
10136 /*
10137 * 845g/865g are special in that they are only limited by
10138 * the width of their cursors, the height is arbitrary up to
10139 * the precision of the register. Everything else requires
10140 * square cursors, limited to a few power-of-two sizes.
10141 */
10142 if (IS_845G(dev) || IS_I865G(dev)) {
10143 if ((width & 63) != 0)
10144 return false;
10145
10146 if (width > (IS_845G(dev) ? 64 : 512))
10147 return false;
10148
10149 if (height > 1023)
10150 return false;
10151 } else {
10152 switch (width | height) {
10153 case 256:
10154 case 128:
10155 if (IS_GEN2(dev))
10156 return false;
10157 case 64:
10158 break;
10159 default:
10160 return false;
10161 }
10162 }
10163
10164 return true;
10165}
10166
79e53945 10167static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 10168 u16 *blue, uint32_t start, uint32_t size)
79e53945 10169{
7203425a 10170 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 10171 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 10172
7203425a 10173 for (i = start; i < end; i++) {
79e53945
JB		 10174 intel_crtc->lut_r[i] = red[i] >> 8;
10175 intel_crtc->lut_g[i] = green[i] >> 8;
10176 intel_crtc->lut_b[i] = blue[i] >> 8;
10177 }
10178
10179 intel_crtc_load_lut(crtc);
10180}
10181
79e53945
JB		 10182/* VESA 640x480x72Hz mode to set on the pipe */
10183static struct drm_display_mode load_detect_mode = {
10184 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10185 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10186};
10187
a8bb6818
DV		 10188struct drm_framebuffer *
10189__intel_framebuffer_create(struct drm_device *dev,
10190 struct drm_mode_fb_cmd2 *mode_cmd,
10191 struct drm_i915_gem_object *obj)
d2dff872
CW		 10192{
10193 struct intel_framebuffer *intel_fb;
10194 int ret;
10195
10196 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10197 if (!intel_fb) {
6ccb81f2 10198 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 10199 return ERR_PTR(-ENOMEM);
10200 }
10201
10202 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 10203 if (ret)
10204 goto err;
d2dff872
CW		 10205
10206 return &intel_fb->base;
dd4916c5 10207err:
6ccb81f2 10208 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 10209 kfree(intel_fb);
10210
10211 return ERR_PTR(ret);
d2dff872
CW		 10212}
10213
b5ea642a 10214static struct drm_framebuffer *
a8bb6818
DV		 10215intel_framebuffer_create(struct drm_device *dev,
10216 struct drm_mode_fb_cmd2 *mode_cmd,
10217 struct drm_i915_gem_object *obj)
10218{
10219 struct drm_framebuffer *fb;
10220 int ret;
10221
10222 ret = i915_mutex_lock_interruptible(dev);
10223 if (ret)
10224 return ERR_PTR(ret);
10225 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10226 mutex_unlock(&dev->struct_mutex);
10227
10228 return fb;
10229}
10230
d2dff872
CW		 10231static u32
10232intel_framebuffer_pitch_for_width(int width, int bpp)
10233{
10234 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10235 return ALIGN(pitch, 64);
10236}
10237
10238static u32
10239intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10240{
10241 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 10242 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 10243}
10244
10245static struct drm_framebuffer *
10246intel_framebuffer_create_for_mode(struct drm_device *dev,
10247 struct drm_display_mode *mode,
10248 int depth, int bpp)
10249{
10250 struct drm_i915_gem_object *obj;
0fed39bd 10251 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 10252
10253 obj = i915_gem_alloc_object(dev,
10254 intel_framebuffer_size_for_mode(mode, bpp));
10255 if (obj == NULL)
10256 return ERR_PTR(-ENOMEM);
10257
10258 mode_cmd.width = mode->hdisplay;
10259 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 10260 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10261 bpp);
5ca0c34a 10262 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 10263
10264 return intel_framebuffer_create(dev, &mode_cmd, obj);
10265}
10266
10267static struct drm_framebuffer *
10268mode_fits_in_fbdev(struct drm_device *dev,
10269 struct drm_display_mode *mode)
10270{
4520f53a 10271#ifdef CONFIG_DRM_I915_FBDEV
d2dff872
CW		 10272 struct drm_i915_private *dev_priv = dev->dev_private;
10273 struct drm_i915_gem_object *obj;
10274 struct drm_framebuffer *fb;
10275
4c0e5528 10276 if (!dev_priv->fbdev)
d2dff872
CW		 10277 return NULL;
10278
4c0e5528 10279 if (!dev_priv->fbdev->fb)
d2dff872
CW		 10280 return NULL;
10281
4c0e5528
DV		 10282 obj = dev_priv->fbdev->fb->obj;
10283 BUG_ON(!obj);
10284
8bcd4553 10285 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 10286 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10287 fb->bits_per_pixel))
d2dff872
CW		 10288 return NULL;
10289
01f2c773 10290 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 10291 return NULL;
10292
10293 return fb;
4520f53a
DV		 10294#else
10295 return NULL;
10296#endif
d2dff872
CW		 10297}
10298
d3a40d1b
ACO		 10299static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10300 struct drm_crtc *crtc,
10301 struct drm_display_mode *mode,
10302 struct drm_framebuffer *fb,
10303 int x, int y)
10304{
10305 struct drm_plane_state *plane_state;
10306 int hdisplay, vdisplay;
10307 int ret;
10308
10309 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10310 if (IS_ERR(plane_state))
10311 return PTR_ERR(plane_state);
10312
10313 if (mode)
10314 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10315 else
10316 hdisplay = vdisplay = 0;
10317
10318 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10319 if (ret)
10320 return ret;
10321 drm_atomic_set_fb_for_plane(plane_state, fb);
10322 plane_state->crtc_x = 0;
10323 plane_state->crtc_y = 0;
10324 plane_state->crtc_w = hdisplay;
10325 plane_state->crtc_h = vdisplay;
10326 plane_state->src_x = x << 16;
10327 plane_state->src_y = y << 16;
10328 plane_state->src_w = hdisplay << 16;
10329 plane_state->src_h = vdisplay << 16;
10330
10331 return 0;
10332}
10333
d2434ab7 10334bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 10335 struct drm_display_mode *mode,
51fd371b
RC		 10336 struct intel_load_detect_pipe *old,
10337 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 10338{
10339 struct intel_crtc *intel_crtc;
d2434ab7
DV		 10340 struct intel_encoder *intel_encoder =
10341 intel_attached_encoder(connector);
79e53945 10342 struct drm_crtc *possible_crtc;
4ef69c7a 10343 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 10344 struct drm_crtc *crtc = NULL;
10345 struct drm_device *dev = encoder->dev;
94352cf9 10346 struct drm_framebuffer *fb;
51fd371b 10347 struct drm_mode_config *config = &dev->mode_config;
83a57153 10348 struct drm_atomic_state *state = NULL;
944b0c76 10349 struct drm_connector_state *connector_state;
4be07317 10350 struct intel_crtc_state *crtc_state;
51fd371b 10351 int ret, i = -1;
79e53945 10352
d2dff872 10353 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10354 connector->base.id, connector->name,
8e329a03 10355 encoder->base.id, encoder->name);
d2dff872 10356
51fd371b
RC		 10357retry:
10358 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10359 if (ret)
10360 goto fail_unlock;
6e9f798d 10361
79e53945
JB		 10362 /*
10363 * Algorithm gets a little messy:
7a5e4805 10364 *
79e53945
JB		 10365 * - if the connector already has an assigned crtc, use it (but make
10366 * sure it's on first)
7a5e4805 10367 *
79e53945
JB		 10368 * - try to find the first unused crtc that can drive this connector,
10369 * and use that if we find one
79e53945
JB		 10370 */
10371
10372 /* See if we already have a CRTC for this connector */
10373 if (encoder->crtc) {
10374 crtc = encoder->crtc;
8261b191 10375
51fd371b 10376 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de
DV		 10377 if (ret)
10378 goto fail_unlock;
10379 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b
RC		 10380 if (ret)
10381 goto fail_unlock;
7b24056b 10382
24218aac 10383 old->dpms_mode = connector->dpms;
8261b191
CW		 10384 old->load_detect_temp = false;
10385
10386 /* Make sure the crtc and connector are running */
24218aac
DV		 10387 if (connector->dpms != DRM_MODE_DPMS_ON)
10388 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 10389
7173188d 10390 return true;
79e53945
JB		 10391 }
10392
10393 /* Find an unused one (if possible) */
70e1e0ec 10394 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 10395 i++;
10396 if (!(encoder->possible_crtcs & (1 << i)))
10397 continue;
83d65738 10398 if (possible_crtc->state->enable)
a459249c
VS		 10399 continue;
10400 /* This can occur when applying the pipe A quirk on resume. */
10401 if (to_intel_crtc(possible_crtc)->new_enabled)
10402 continue;
10403
10404 crtc = possible_crtc;
10405 break;
79e53945
JB		 10406 }
10407
10408 /*
10409 * If we didn't find an unused CRTC, don't use any.
10410 */
10411 if (!crtc) {
7173188d 10412 DRM_DEBUG_KMS("no pipe available for load-detect\n");
51fd371b 10413 goto fail_unlock;
79e53945
JB		 10414 }
10415
51fd371b
RC		 10416 ret = drm_modeset_lock(&crtc->mutex, ctx);
10417 if (ret)
4d02e2de
DV		 10418 goto fail_unlock;
10419 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10420 if (ret)
51fd371b 10421 goto fail_unlock;
fc303101
DV		 10422 intel_encoder->new_crtc = to_intel_crtc(crtc);
10423 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 10424
10425 intel_crtc = to_intel_crtc(crtc);
412b61d8 10426 intel_crtc->new_enabled = true;
24218aac 10427 old->dpms_mode = connector->dpms;
8261b191 10428 old->load_detect_temp = true;
d2dff872 10429 old->release_fb = NULL;
79e53945 10430
83a57153
ACO		 10431 state = drm_atomic_state_alloc(dev);
10432 if (!state)
10433 return false;
10434
10435 state->acquire_ctx = ctx;
10436
944b0c76
ACO		 10437 connector_state = drm_atomic_get_connector_state(state, connector);
10438 if (IS_ERR(connector_state)) {
10439 ret = PTR_ERR(connector_state);
10440 goto fail;
10441 }
10442
10443 connector_state->crtc = crtc;
10444 connector_state->best_encoder = &intel_encoder->base;
10445
4be07317
ACO		 10446 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10447 if (IS_ERR(crtc_state)) {
10448 ret = PTR_ERR(crtc_state);
10449 goto fail;
10450 }
10451
49d6fa21 10452 crtc_state->base.active = crtc_state->base.enable = true;
4be07317 10453
6492711d
CW		 10454 if (!mode)
10455 mode = &load_detect_mode;
79e53945 10456
d2dff872
CW		 10457 /* We need a framebuffer large enough to accommodate all accesses
10458 * that the plane may generate whilst we perform load detection.
10459 * We can not rely on the fbcon either being present (we get called
10460 * during its initialisation to detect all boot displays, or it may
10461 * not even exist) or that it is large enough to satisfy the
10462 * requested mode.
10463 */
94352cf9
DV		 10464 fb = mode_fits_in_fbdev(dev, mode);
10465 if (fb == NULL) {
d2dff872 10466 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 10467 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10468 old->release_fb = fb;
d2dff872
CW		 10469 } else
10470 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 10471 if (IS_ERR(fb)) {
d2dff872 10472 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 10473 goto fail;
79e53945 10474 }
79e53945 10475
d3a40d1b
ACO		 10476 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10477 if (ret)
10478 goto fail;
10479
8c7b5ccb
ACO		 10480 drm_mode_copy(&crtc_state->base.mode, mode);
10481
10482 if (intel_set_mode(crtc, state)) {
6492711d 10483 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 10484 if (old->release_fb)
10485 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 10486 goto fail;
79e53945 10487 }
9128b040 10488 crtc->primary->crtc = crtc;
7173188d 10489
79e53945 10490 /* let the connector get through one full cycle before testing */
9d0498a2 10491 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 10492 return true;
412b61d8
VS		 10493
10494 fail:
83d65738 10495 intel_crtc->new_enabled = crtc->state->enable;
51fd371b 10496fail_unlock:
e5d958ef
ACO		 10497 drm_atomic_state_free(state);
10498 state = NULL;
83a57153 10499
51fd371b
RC		 10500 if (ret == -EDEADLK) {
10501 drm_modeset_backoff(ctx);
10502 goto retry;
10503 }
10504
412b61d8 10505 return false;
79e53945
JB		 10506}
10507
d2434ab7 10508void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 10509 struct intel_load_detect_pipe *old,
10510 struct drm_modeset_acquire_ctx *ctx)
79e53945 10511{
83a57153 10512 struct drm_device *dev = connector->dev;
d2434ab7
DV		 10513 struct intel_encoder *intel_encoder =
10514 intel_attached_encoder(connector);
4ef69c7a 10515 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 10516 struct drm_crtc *crtc = encoder->crtc;
412b61d8 10517 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 10518 struct drm_atomic_state *state;
944b0c76 10519 struct drm_connector_state *connector_state;
4be07317 10520 struct intel_crtc_state *crtc_state;
d3a40d1b 10521 int ret;
79e53945 10522
d2dff872 10523 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10524 connector->base.id, connector->name,
8e329a03 10525 encoder->base.id, encoder->name);
d2dff872 10526
8261b191 10527 if (old->load_detect_temp) {
83a57153 10528 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 10529 if (!state)
10530 goto fail;
83a57153
ACO		 10531
10532 state->acquire_ctx = ctx;
10533
944b0c76
ACO		 10534 connector_state = drm_atomic_get_connector_state(state, connector);
10535 if (IS_ERR(connector_state))
10536 goto fail;
10537
4be07317
ACO		 10538 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10539 if (IS_ERR(crtc_state))
10540 goto fail;
10541
fc303101
DV		 10542 to_intel_connector(connector)->new_encoder = NULL;
10543 intel_encoder->new_crtc = NULL;
412b61d8 10544 intel_crtc->new_enabled = false;
944b0c76
ACO		 10545
10546 connector_state->best_encoder = NULL;
10547 connector_state->crtc = NULL;
10548
49d6fa21 10549 crtc_state->base.enable = crtc_state->base.active = false;
4be07317 10550
d3a40d1b
ACO		 10551 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10552 0, 0);
10553 if (ret)
10554 goto fail;
10555
2bfb4627
ACO		 10556 ret = intel_set_mode(crtc, state);
10557 if (ret)
10558 goto fail;
d2dff872 10559
36206361
DV		 10560 if (old->release_fb) {
10561 drm_framebuffer_unregister_private(old->release_fb);
10562 drm_framebuffer_unreference(old->release_fb);
10563 }
d2dff872 10564
0622a53c 10565 return;
79e53945
JB		 10566 }
10567
c751ce4f 10568 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 10569 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10570 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 10571
10572 return;
10573fail:
10574 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10575 drm_atomic_state_free(state);
79e53945
JB		 10576}
10577
da4a1efa 10578static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 10579 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 10580{
10581 struct drm_i915_private *dev_priv = dev->dev_private;
10582 u32 dpll = pipe_config->dpll_hw_state.dpll;
10583
10584 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 10585 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 10586 else if (HAS_PCH_SPLIT(dev))
10587 return 120000;
10588 else if (!IS_GEN2(dev))
10589 return 96000;
10590 else
10591 return 48000;
10592}
10593
79e53945 10594/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 10595static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 10596 struct intel_crtc_state *pipe_config)
79e53945 10597{
f1f644dc 10598 struct drm_device *dev = crtc->base.dev;
79e53945 10599 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 10600 int pipe = pipe_config->cpu_transcoder;
293623f7 10601 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 10602 u32 fp;
10603 intel_clock_t clock;
da4a1efa 10604 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 10605
10606 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 10607 fp = pipe_config->dpll_hw_state.fp0;
79e53945 10608 else
293623f7 10609 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 10610
10611 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 10612 if (IS_PINEVIEW(dev)) {
10613 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10614 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 10615 } else {
10616 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10617 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10618 }
10619
a6c45cf0 10620 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 10621 if (IS_PINEVIEW(dev))
10622 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10623 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 10624 else
10625 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 10626 DPLL_FPA01_P1_POST_DIV_SHIFT);
10627
10628 switch (dpll & DPLL_MODE_MASK) {
10629 case DPLLB_MODE_DAC_SERIAL:
10630 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10631 5 : 10;
10632 break;
10633 case DPLLB_MODE_LVDS:
10634 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10635 7 : 14;
10636 break;
10637 default:
28c97730 10638 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 10639 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 10640 return;
79e53945
JB		 10641 }
10642
ac58c3f0 10643 if (IS_PINEVIEW(dev))
da4a1efa 10644 pineview_clock(refclk, &clock);
ac58c3f0 10645 else
da4a1efa 10646 i9xx_clock(refclk, &clock);
79e53945 10647 } else {
0fb58223 10648 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 10649 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 10650
10651 if (is_lvds) {
10652 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10653 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 10654
10655 if (lvds & LVDS_CLKB_POWER_UP)
10656 clock.p2 = 7;
10657 else
10658 clock.p2 = 14;
79e53945
JB		 10659 } else {
10660 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10661 clock.p1 = 2;
10662 else {
10663 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10664 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10665 }
10666 if (dpll & PLL_P2_DIVIDE_BY_4)
10667 clock.p2 = 4;
10668 else
10669 clock.p2 = 2;
79e53945 10670 }
da4a1efa
VS		 10671
10672 i9xx_clock(refclk, &clock);
79e53945
JB		 10673 }
10674
18442d08
VS		 10675 /*
10676 * This value includes pixel_multiplier. We will use
241bfc38 10677 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 10678 * encoder's get_config() function.
10679 */
10680 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 10681}
10682
6878da05
VS		 10683int intel_dotclock_calculate(int link_freq,
10684 const struct intel_link_m_n *m_n)
f1f644dc 10685{
f1f644dc
JB		 10686 /*
10687 * The calculation for the data clock is:
1041a02f 10688 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 10689 * But we want to avoid losing precison if possible, so:
1041a02f 10690 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 10691 *
10692 * and the link clock is simpler:
1041a02f 10693 * link_clock = (m * link_clock) / n
f1f644dc
JB		 10694 */
10695
6878da05
VS		 10696 if (!m_n->link_n)
10697 return 0;
f1f644dc 10698
6878da05
VS		 10699 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10700}
f1f644dc 10701
18442d08 10702static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 10703 struct intel_crtc_state *pipe_config)
6878da05
VS		 10704{
10705 struct drm_device *dev = crtc->base.dev;
79e53945 10706
18442d08
VS		 10707 /* read out port_clock from the DPLL */
10708 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 10709
f1f644dc 10710 /*
18442d08 10711 * This value does not include pixel_multiplier.
241bfc38 10712 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 10713 * agree once we know their relationship in the encoder's
10714 * get_config() function.
79e53945 10715 */
2d112de7 10716 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 10717 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10718 &pipe_config->fdi_m_n);
79e53945
JB		 10719}
10720
10721/** Returns the currently programmed mode of the given pipe. */
10722struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10723 struct drm_crtc *crtc)
10724{
548f245b 10725 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 10726 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 10727 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 10728 struct drm_display_mode *mode;
5cec258b 10729 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 10730 int htot = I915_READ(HTOTAL(cpu_transcoder));
10731 int hsync = I915_READ(HSYNC(cpu_transcoder));
10732 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10733 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 10734 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 10735
10736 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10737 if (!mode)
10738 return NULL;
10739
f1f644dc
JB		 10740 /*
10741 * Construct a pipe_config sufficient for getting the clock info
10742 * back out of crtc_clock_get.
10743 *
10744 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10745 * to use a real value here instead.
10746 */
293623f7 10747 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 10748 pipe_config.pixel_multiplier = 1;
293623f7
VS		 10749 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10750 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10751 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 10752 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10753
773ae034 10754 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 10755 mode->hdisplay = (htot & 0xffff) + 1;
10756 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10757 mode->hsync_start = (hsync & 0xffff) + 1;
10758 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10759 mode->vdisplay = (vtot & 0xffff) + 1;
10760 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10761 mode->vsync_start = (vsync & 0xffff) + 1;
10762 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10763
10764 drm_mode_set_name(mode);
79e53945
JB		 10765
10766 return mode;
10767}
10768
652c393a
JB		 10769static void intel_decrease_pllclock(struct drm_crtc *crtc)
10770{
10771 struct drm_device *dev = crtc->dev;
fbee40df 10772 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10773 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 10774
baff296c 10775 if (!HAS_GMCH_DISPLAY(dev))
652c393a
JB		 10776 return;
10777
10778 if (!dev_priv->lvds_downclock_avail)
10779 return;
10780
10781 /*
10782 * Since this is called by a timer, we should never get here in
10783 * the manual case.
10784 */
10785 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 10786 int pipe = intel_crtc->pipe;
10787 int dpll_reg = DPLL(pipe);
10788 int dpll;
f6e5b160 10789
44d98a61 10790 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 10791
8ac5a6d5 10792 assert_panel_unlocked(dev_priv, pipe);
652c393a 10793
dc257cf1 10794 dpll = I915_READ(dpll_reg);
652c393a
JB		 10795 dpll |= DISPLAY_RATE_SELECT_FPA1;
10796 I915_WRITE(dpll_reg, dpll);
9d0498a2 10797 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 10798 dpll = I915_READ(dpll_reg);
10799 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 10800 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 10801 }
10802
10803}
10804
f047e395
CW		 10805void intel_mark_busy(struct drm_device *dev)
10806{
c67a470b
PZ		 10807 struct drm_i915_private *dev_priv = dev->dev_private;
10808
f62a0076
CW		 10809 if (dev_priv->mm.busy)
10810 return;
10811
43694d69 10812 intel_runtime_pm_get(dev_priv);
c67a470b 10813 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 10814 if (INTEL_INFO(dev)->gen >= 6)
10815 gen6_rps_busy(dev_priv);
f62a0076 10816 dev_priv->mm.busy = true;
f047e395
CW		 10817}
10818
10819void intel_mark_idle(struct drm_device *dev)
652c393a 10820{
c67a470b 10821 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10822 struct drm_crtc *crtc;
652c393a 10823
f62a0076
CW		 10824 if (!dev_priv->mm.busy)
10825 return;
10826
10827 dev_priv->mm.busy = false;
10828
70e1e0ec 10829 for_each_crtc(dev, crtc) {
f4510a27 10830 if (!crtc->primary->fb)
652c393a
JB		 10831 continue;
10832
725a5b54 10833 intel_decrease_pllclock(crtc);
652c393a 10834 }
b29c19b6 10835
3d13ef2e 10836 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 10837 gen6_rps_idle(dev->dev_private);
bb4cdd53 10838
43694d69 10839 intel_runtime_pm_put(dev_priv);
652c393a
JB		 10840}
10841
79e53945
JB		 10842static void intel_crtc_destroy(struct drm_crtc *crtc)
10843{
10844 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 10845 struct drm_device *dev = crtc->dev;
10846 struct intel_unpin_work *work;
67e77c5a 10847
5e2d7afc 10848 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 10849 work = intel_crtc->unpin_work;
10850 intel_crtc->unpin_work = NULL;
5e2d7afc 10851 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 10852
10853 if (work) {
10854 cancel_work_sync(&work->work);
10855 kfree(work);
10856 }
79e53945
JB		 10857
10858 drm_crtc_cleanup(crtc);
67e77c5a 10859
79e53945
JB		 10860 kfree(intel_crtc);
10861}
10862
6b95a207
KH		 10863static void intel_unpin_work_fn(struct work_struct *__work)
10864{
10865 struct intel_unpin_work *work =
10866 container_of(__work, struct intel_unpin_work, work);
b4a98e57 10867 struct drm_device *dev = work->crtc->dev;
f99d7069 10868 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
6b95a207 10869
b4a98e57 10870 mutex_lock(&dev->struct_mutex);
82bc3b2d 10871 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
05394f39 10872 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 10873
7ff0ebcc 10874 intel_fbc_update(dev);
f06cc1b9
JH		 10875
10876 if (work->flip_queued_req)
146d84f0 10877 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 10878 mutex_unlock(&dev->struct_mutex);
10879
f99d7069 10880 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
89ed88ba 10881 drm_framebuffer_unreference(work->old_fb);
f99d7069 10882
b4a98e57
CW		 10883 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10884 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10885
6b95a207
KH		 10886 kfree(work);
10887}
10888
1afe3e9d 10889static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 10890 struct drm_crtc *crtc)
6b95a207 10891{
6b95a207
KH		 10892 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10893 struct intel_unpin_work *work;
6b95a207
KH		 10894 unsigned long flags;
10895
10896 /* Ignore early vblank irqs */
10897 if (intel_crtc == NULL)
10898 return;
10899
f326038a
DV		 10900 /*
10901 * This is called both by irq handlers and the reset code (to complete
10902 * lost pageflips) so needs the full irqsave spinlocks.
10903 */
6b95a207
KH		 10904 spin_lock_irqsave(&dev->event_lock, flags);
10905 work = intel_crtc->unpin_work;
e7d841ca
CW		 10906
10907 /* Ensure we don't miss a work->pending update ... */
10908 smp_rmb();
10909
10910 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 10911 spin_unlock_irqrestore(&dev->event_lock, flags);
10912 return;
10913 }
10914
d6bbafa1 10915 page_flip_completed(intel_crtc);
0af7e4df 10916
6b95a207 10917 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 10918}
10919
1afe3e9d
JB		 10920void intel_finish_page_flip(struct drm_device *dev, int pipe)
10921{
fbee40df 10922 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10923 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10924
49b14a5c 10925 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10926}
10927
10928void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10929{
fbee40df 10930 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10931 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10932
49b14a5c 10933 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10934}
10935
75f7f3ec
VS		 10936/* Is 'a' after or equal to 'b'? */
10937static bool g4x_flip_count_after_eq(u32 a, u32 b)
10938{
10939 return !((a - b) & 0x80000000);
10940}
10941
10942static bool page_flip_finished(struct intel_crtc *crtc)
10943{
10944 struct drm_device *dev = crtc->base.dev;
10945 struct drm_i915_private *dev_priv = dev->dev_private;
10946
bdfa7542
VS		 10947 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10948 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10949 return true;
10950
75f7f3ec
VS		 10951 /*
10952 * The relevant registers doen't exist on pre-ctg.
10953 * As the flip done interrupt doesn't trigger for mmio
10954 * flips on gmch platforms, a flip count check isn't
10955 * really needed there. But since ctg has the registers,
10956 * include it in the check anyway.
10957 */
10958 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10959 return true;
10960
10961 /*
10962 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10963 * used the same base address. In that case the mmio flip might
10964 * have completed, but the CS hasn't even executed the flip yet.
10965 *
10966 * A flip count check isn't enough as the CS might have updated
10967 * the base address just after start of vblank, but before we
10968 * managed to process the interrupt. This means we'd complete the
10969 * CS flip too soon.
10970 *
10971 * Combining both checks should get us a good enough result. It may
10972 * still happen that the CS flip has been executed, but has not
10973 * yet actually completed. But in case the base address is the same
10974 * anyway, we don't really care.
10975 */
10976 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10977 crtc->unpin_work->gtt_offset &&
10978 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10979 crtc->unpin_work->flip_count);
10980}
10981
6b95a207
KH		 10982void intel_prepare_page_flip(struct drm_device *dev, int plane)
10983{
fbee40df 10984 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 10985 struct intel_crtc *intel_crtc =
10986 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10987 unsigned long flags;
10988
f326038a
DV		 10989
10990 /*
10991 * This is called both by irq handlers and the reset code (to complete
10992 * lost pageflips) so needs the full irqsave spinlocks.
10993 *
10994 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 10995 * generate a page-flip completion irq, i.e. every modeset
10996 * is also accompanied by a spurious intel_prepare_page_flip().
10997 */
6b95a207 10998 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 10999 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 11000 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 11001 spin_unlock_irqrestore(&dev->event_lock, flags);
11002}
11003
eba905b2 11004static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW		 11005{
11006 /* Ensure that the work item is consistent when activating it ... */
11007 smp_wmb();
11008 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
11009 /* and that it is marked active as soon as the irq could fire. */
11010 smp_wmb();
11011}
11012
8c9f3aaf
JB		 11013static int intel_gen2_queue_flip(struct drm_device *dev,
11014 struct drm_crtc *crtc,
11015 struct drm_framebuffer *fb,
ed8d1975 11016 struct drm_i915_gem_object *obj,
a4872ba6 11017 struct intel_engine_cs *ring,
ed8d1975 11018 uint32_t flags)
8c9f3aaf 11019{
8c9f3aaf 11020 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 11021 u32 flip_mask;
11022 int ret;
11023
6d90c952 11024 ret = intel_ring_begin(ring, 6);
8c9f3aaf 11025 if (ret)
4fa62c89 11026 return ret;
8c9f3aaf
JB		 11027
11028 /* Can't queue multiple flips, so wait for the previous
11029 * one to finish before executing the next.
11030 */
11031 if (intel_crtc->plane)
11032 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11033 else
11034 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 11035 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11036 intel_ring_emit(ring, MI_NOOP);
11037 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11038 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11039 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 11040 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 11041 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 11042
11043 intel_mark_page_flip_active(intel_crtc);
09246732 11044 __intel_ring_advance(ring);
83d4092b 11045 return 0;
8c9f3aaf
JB		 11046}
11047
11048static int intel_gen3_queue_flip(struct drm_device *dev,
11049 struct drm_crtc *crtc,
11050 struct drm_framebuffer *fb,
ed8d1975 11051 struct drm_i915_gem_object *obj,
a4872ba6 11052 struct intel_engine_cs *ring,
ed8d1975 11053 uint32_t flags)
8c9f3aaf 11054{
8c9f3aaf 11055 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 11056 u32 flip_mask;
11057 int ret;
11058
6d90c952 11059 ret = intel_ring_begin(ring, 6);
8c9f3aaf 11060 if (ret)
4fa62c89 11061 return ret;
8c9f3aaf
JB		 11062
11063 if (intel_crtc->plane)
11064 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11065 else
11066 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 11067 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11068 intel_ring_emit(ring, MI_NOOP);
11069 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11070 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11071 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 11072 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 11073 intel_ring_emit(ring, MI_NOOP);
11074
e7d841ca 11075 intel_mark_page_flip_active(intel_crtc);
09246732 11076 __intel_ring_advance(ring);
83d4092b 11077 return 0;
8c9f3aaf
JB		 11078}
11079
11080static int intel_gen4_queue_flip(struct drm_device *dev,
11081 struct drm_crtc *crtc,
11082 struct drm_framebuffer *fb,
ed8d1975 11083 struct drm_i915_gem_object *obj,
a4872ba6 11084 struct intel_engine_cs *ring,
ed8d1975 11085 uint32_t flags)
8c9f3aaf
JB		 11086{
11087 struct drm_i915_private *dev_priv = dev->dev_private;
11088 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11089 uint32_t pf, pipesrc;
11090 int ret;
11091
6d90c952 11092 ret = intel_ring_begin(ring, 4);
8c9f3aaf 11093 if (ret)
4fa62c89 11094 return ret;
8c9f3aaf
JB		 11095
11096 /* i965+ uses the linear or tiled offsets from the
11097 * Display Registers (which do not change across a page-flip)
11098 * so we need only reprogram the base address.
11099 */
6d90c952
DV		 11100 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11101 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11102 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 11103 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 11104 obj->tiling_mode);
8c9f3aaf
JB		 11105
11106 /* XXX Enabling the panel-fitter across page-flip is so far
11107 * untested on non-native modes, so ignore it for now.
11108 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11109 */
11110 pf = 0;
11111 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 11112 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 11113
11114 intel_mark_page_flip_active(intel_crtc);
09246732 11115 __intel_ring_advance(ring);
83d4092b 11116 return 0;
8c9f3aaf
JB		 11117}
11118
11119static int intel_gen6_queue_flip(struct drm_device *dev,
11120 struct drm_crtc *crtc,
11121 struct drm_framebuffer *fb,
ed8d1975 11122 struct drm_i915_gem_object *obj,
a4872ba6 11123 struct intel_engine_cs *ring,
ed8d1975 11124 uint32_t flags)
8c9f3aaf
JB		 11125{
11126 struct drm_i915_private *dev_priv = dev->dev_private;
11127 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11128 uint32_t pf, pipesrc;
11129 int ret;
11130
6d90c952 11131 ret = intel_ring_begin(ring, 4);
8c9f3aaf 11132 if (ret)
4fa62c89 11133 return ret;
8c9f3aaf 11134
6d90c952
DV		 11135 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11136 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11137 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 11138 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 11139
dc257cf1
DV		 11140 /* Contrary to the suggestions in the documentation,
11141 * "Enable Panel Fitter" does not seem to be required when page
11142 * flipping with a non-native mode, and worse causes a normal
11143 * modeset to fail.
11144 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11145 */
11146 pf = 0;
8c9f3aaf 11147 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 11148 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 11149
11150 intel_mark_page_flip_active(intel_crtc);
09246732 11151 __intel_ring_advance(ring);
83d4092b 11152 return 0;
8c9f3aaf
JB		 11153}
11154
7c9017e5
JB		 11155static int intel_gen7_queue_flip(struct drm_device *dev,
11156 struct drm_crtc *crtc,
11157 struct drm_framebuffer *fb,
ed8d1975 11158 struct drm_i915_gem_object *obj,
a4872ba6 11159 struct intel_engine_cs *ring,
ed8d1975 11160 uint32_t flags)
7c9017e5 11161{
7c9017e5 11162 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 11163 uint32_t plane_bit = 0;
ffe74d75
CW		 11164 int len, ret;
11165
eba905b2 11166 switch (intel_crtc->plane) {
cb05d8de
DV		 11167 case PLANE_A:
11168 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11169 break;
11170 case PLANE_B:
11171 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11172 break;
11173 case PLANE_C:
11174 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11175 break;
11176 default:
11177 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 11178 return -ENODEV;
cb05d8de
DV		 11179 }
11180
ffe74d75 11181 len = 4;
f476828a 11182 if (ring->id == RCS) {
ffe74d75 11183 len += 6;
f476828a
DL		 11184 /*
11185 * On Gen 8, SRM is now taking an extra dword to accommodate
11186 * 48bits addresses, and we need a NOOP for the batch size to
11187 * stay even.
11188 */
11189 if (IS_GEN8(dev))
11190 len += 2;
11191 }
ffe74d75 11192
f66fab8e
VS		 11193 /*
11194 * BSpec MI_DISPLAY_FLIP for IVB:
11195 * "The full packet must be contained within the same cache line."
11196 *
11197 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11198 * cacheline, if we ever start emitting more commands before
11199 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11200 * then do the cacheline alignment, and finally emit the
11201 * MI_DISPLAY_FLIP.
11202 */
11203 ret = intel_ring_cacheline_align(ring);
11204 if (ret)
4fa62c89 11205 return ret;
f66fab8e 11206
ffe74d75 11207 ret = intel_ring_begin(ring, len);
7c9017e5 11208 if (ret)
4fa62c89 11209 return ret;
7c9017e5 11210
ffe74d75
CW		 11211 /* Unmask the flip-done completion message. Note that the bspec says that
11212 * we should do this for both the BCS and RCS, and that we must not unmask
11213 * more than one flip event at any time (or ensure that one flip message
11214 * can be sent by waiting for flip-done prior to queueing new flips).
11215 * Experimentation says that BCS works despite DERRMR masking all
11216 * flip-done completion events and that unmasking all planes at once
11217 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11218 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11219 */
11220 if (ring->id == RCS) {
11221 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11222 intel_ring_emit(ring, DERRMR);
11223 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11224 DERRMR_PIPEB_PRI_FLIP_DONE |
11225 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a
DL		 11226 if (IS_GEN8(dev))
11227 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11228 MI_SRM_LRM_GLOBAL_GTT);
11229 else
11230 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11231 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 11232 intel_ring_emit(ring, DERRMR);
11233 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 11234 if (IS_GEN8(dev)) {
11235 intel_ring_emit(ring, 0);
11236 intel_ring_emit(ring, MI_NOOP);
11237 }
ffe74d75
CW		 11238 }
11239
cb05d8de 11240 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 11241 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 11242 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 11243 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 11244
11245 intel_mark_page_flip_active(intel_crtc);
09246732 11246 __intel_ring_advance(ring);
83d4092b 11247 return 0;
7c9017e5
JB		 11248}
11249
84c33a64
SG		 11250static bool use_mmio_flip(struct intel_engine_cs *ring,
11251 struct drm_i915_gem_object *obj)
11252{
11253 /*
11254 * This is not being used for older platforms, because
11255 * non-availability of flip done interrupt forces us to use
11256 * CS flips. Older platforms derive flip done using some clever
11257 * tricks involving the flip_pending status bits and vblank irqs.
11258 * So using MMIO flips there would disrupt this mechanism.
11259 */
11260
8e09bf83
CW		 11261 if (ring == NULL)
11262 return true;
11263
84c33a64
SG		 11264 if (INTEL_INFO(ring->dev)->gen < 5)
11265 return false;
11266
11267 if (i915.use_mmio_flip < 0)
11268 return false;
11269 else if (i915.use_mmio_flip > 0)
11270 return true;
14bf993e
OM		 11271 else if (i915.enable_execlists)
11272 return true;
84c33a64 11273 else
b4716185 11274 return ring != i915_gem_request_get_ring(obj->last_write_req);
84c33a64
SG		 11275}
11276
ff944564
DL		 11277static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11278{
11279 struct drm_device *dev = intel_crtc->base.dev;
11280 struct drm_i915_private *dev_priv = dev->dev_private;
11281 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
ff944564
DL		 11282 const enum pipe pipe = intel_crtc->pipe;
11283 u32 ctl, stride;
11284
11285 ctl = I915_READ(PLANE_CTL(pipe, 0));
11286 ctl &= ~PLANE_CTL_TILED_MASK;
2ebef630
TU		 11287 switch (fb->modifier[0]) {
11288 case DRM_FORMAT_MOD_NONE:
11289 break;
11290 case I915_FORMAT_MOD_X_TILED:
ff944564 11291 ctl |= PLANE_CTL_TILED_X;
2ebef630
TU		 11292 break;
11293 case I915_FORMAT_MOD_Y_TILED:
11294 ctl |= PLANE_CTL_TILED_Y;
11295 break;
11296 case I915_FORMAT_MOD_Yf_TILED:
11297 ctl |= PLANE_CTL_TILED_YF;
11298 break;
11299 default:
11300 MISSING_CASE(fb->modifier[0]);
11301 }
ff944564
DL		 11302
11303 /*
11304 * The stride is either expressed as a multiple of 64 bytes chunks for
11305 * linear buffers or in number of tiles for tiled buffers.
11306 */
2ebef630
TU		 11307 stride = fb->pitches[0] /
11308 intel_fb_stride_alignment(dev, fb->modifier[0],
11309 fb->pixel_format);
ff944564
DL		 11310
11311 /*
11312 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11313 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11314 */
11315 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11316 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11317
11318 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11319 POSTING_READ(PLANE_SURF(pipe, 0));
11320}
11321
11322static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG		 11323{
11324 struct drm_device *dev = intel_crtc->base.dev;
11325 struct drm_i915_private *dev_priv = dev->dev_private;
11326 struct intel_framebuffer *intel_fb =
11327 to_intel_framebuffer(intel_crtc->base.primary->fb);
11328 struct drm_i915_gem_object *obj = intel_fb->obj;
11329 u32 dspcntr;
11330 u32 reg;
11331
84c33a64
SG		 11332 reg = DSPCNTR(intel_crtc->plane);
11333 dspcntr = I915_READ(reg);
11334
c5d97472
DL		 11335 if (obj->tiling_mode != I915_TILING_NONE)
11336 dspcntr |= DISPPLANE_TILED;
11337 else
11338 dspcntr &= ~DISPPLANE_TILED;
11339
84c33a64
SG		 11340 I915_WRITE(reg, dspcntr);
11341
11342 I915_WRITE(DSPSURF(intel_crtc->plane),
11343 intel_crtc->unpin_work->gtt_offset);
11344 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 11345
ff944564
DL		 11346}
11347
11348/*
11349 * XXX: This is the temporary way to update the plane registers until we get
11350 * around to using the usual plane update functions for MMIO flips
11351 */
11352static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11353{
11354 struct drm_device *dev = intel_crtc->base.dev;
11355 bool atomic_update;
11356 u32 start_vbl_count;
11357
11358 intel_mark_page_flip_active(intel_crtc);
11359
11360 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
11361
11362 if (INTEL_INFO(dev)->gen >= 9)
11363 skl_do_mmio_flip(intel_crtc);
11364 else
11365 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11366 ilk_do_mmio_flip(intel_crtc);
11367
9362c7c5
ACO		 11368 if (atomic_update)
11369 intel_pipe_update_end(intel_crtc, start_vbl_count);
84c33a64
SG		 11370}
11371
9362c7c5 11372static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 11373{
b2cfe0ab
CW		 11374 struct intel_mmio_flip *mmio_flip =
11375 container_of(work, struct intel_mmio_flip, work);
84c33a64 11376
eed29a5b
DV		 11377 if (mmio_flip->req)
11378 WARN_ON(__i915_wait_request(mmio_flip->req,
b2cfe0ab 11379 mmio_flip->crtc->reset_counter,
bcafc4e3
CW		 11380 false, NULL,
11381 &mmio_flip->i915->rps.mmioflips));
84c33a64 11382
b2cfe0ab
CW		 11383 intel_do_mmio_flip(mmio_flip->crtc);
11384
eed29a5b 11385 i915_gem_request_unreference__unlocked(mmio_flip->req);
b2cfe0ab 11386 kfree(mmio_flip);
84c33a64
SG		 11387}
11388
11389static int intel_queue_mmio_flip(struct drm_device *dev,
11390 struct drm_crtc *crtc,
11391 struct drm_framebuffer *fb,
11392 struct drm_i915_gem_object *obj,
11393 struct intel_engine_cs *ring,
11394 uint32_t flags)
11395{
b2cfe0ab
CW		 11396 struct intel_mmio_flip *mmio_flip;
11397
11398 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11399 if (mmio_flip == NULL)
11400 return -ENOMEM;
84c33a64 11401
bcafc4e3 11402 mmio_flip->i915 = to_i915(dev);
eed29a5b 11403 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
b2cfe0ab 11404 mmio_flip->crtc = to_intel_crtc(crtc);
536f5b5e 11405
b2cfe0ab
CW		 11406 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11407 schedule_work(&mmio_flip->work);
84c33a64 11408
84c33a64
SG		 11409 return 0;
11410}
11411
8c9f3aaf
JB		 11412static int intel_default_queue_flip(struct drm_device *dev,
11413 struct drm_crtc *crtc,
11414 struct drm_framebuffer *fb,
ed8d1975 11415 struct drm_i915_gem_object *obj,
a4872ba6 11416 struct intel_engine_cs *ring,
ed8d1975 11417 uint32_t flags)
8c9f3aaf
JB		 11418{
11419 return -ENODEV;
11420}
11421
d6bbafa1
CW		 11422static bool __intel_pageflip_stall_check(struct drm_device *dev,
11423 struct drm_crtc *crtc)
11424{
11425 struct drm_i915_private *dev_priv = dev->dev_private;
11426 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11427 struct intel_unpin_work *work = intel_crtc->unpin_work;
11428 u32 addr;
11429
11430 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11431 return true;
11432
11433 if (!work->enable_stall_check)
11434 return false;
11435
11436 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 11437 if (work->flip_queued_req &&
11438 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 11439 return false;
11440
1e3feefd 11441 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 11442 }
11443
1e3feefd 11444 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 11445 return false;
11446
11447 /* Potential stall - if we see that the flip has happened,
11448 * assume a missed interrupt. */
11449 if (INTEL_INFO(dev)->gen >= 4)
11450 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11451 else
11452 addr = I915_READ(DSPADDR(intel_crtc->plane));
11453
11454 /* There is a potential issue here with a false positive after a flip
11455 * to the same address. We could address this by checking for a
11456 * non-incrementing frame counter.
11457 */
11458 return addr == work->gtt_offset;
11459}
11460
11461void intel_check_page_flip(struct drm_device *dev, int pipe)
11462{
11463 struct drm_i915_private *dev_priv = dev->dev_private;
11464 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11465 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 11466 struct intel_unpin_work *work;
f326038a 11467
6c51d46f 11468 WARN_ON(!in_interrupt());
d6bbafa1
CW		 11469
11470 if (crtc == NULL)
11471 return;
11472
f326038a 11473 spin_lock(&dev->event_lock);
6ad790c0
CW		 11474 work = intel_crtc->unpin_work;
11475 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 11476 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 11477 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 11478 page_flip_completed(intel_crtc);
6ad790c0 11479 work = NULL;
d6bbafa1 11480 }
6ad790c0
CW		 11481 if (work != NULL &&
11482 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11483 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 11484 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 11485}
11486
6b95a207
KH		 11487static int intel_crtc_page_flip(struct drm_crtc *crtc,
11488 struct drm_framebuffer *fb,
ed8d1975
KP		 11489 struct drm_pending_vblank_event *event,
11490 uint32_t page_flip_flags)
6b95a207
KH		 11491{
11492 struct drm_device *dev = crtc->dev;
11493 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 11494 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 11495 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 11496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 11497 struct drm_plane *primary = crtc->primary;
a071fa00 11498 enum pipe pipe = intel_crtc->pipe;
6b95a207 11499 struct intel_unpin_work *work;
a4872ba6 11500 struct intel_engine_cs *ring;
cf5d8a46 11501 bool mmio_flip;
52e68630 11502 int ret;
6b95a207 11503
2ff8fde1
MR		 11504 /*
11505 * drm_mode_page_flip_ioctl() should already catch this, but double
11506 * check to be safe. In the future we may enable pageflipping from
11507 * a disabled primary plane.
11508 */
11509 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11510 return -EBUSY;
11511
e6a595d2 11512 /* Can't change pixel format via MI display flips. */
f4510a27 11513 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 11514 return -EINVAL;
11515
11516 /*
11517 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11518 * Note that pitch changes could also affect these register.
11519 */
11520 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 11521 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11522 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 11523 return -EINVAL;
11524
f900db47
CW		 11525 if (i915_terminally_wedged(&dev_priv->gpu_error))
11526 goto out_hang;
11527
b14c5679 11528 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 11529 if (work == NULL)
11530 return -ENOMEM;
11531
6b95a207 11532 work->event = event;
b4a98e57 11533 work->crtc = crtc;
ab8d6675 11534 work->old_fb = old_fb;
6b95a207
KH		 11535 INIT_WORK(&work->work, intel_unpin_work_fn);
11536
87b6b101 11537 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 11538 if (ret)
11539 goto free_work;
11540
6b95a207 11541 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 11542 spin_lock_irq(&dev->event_lock);
6b95a207 11543 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 11544 /* Before declaring the flip queue wedged, check if
11545 * the hardware completed the operation behind our backs.
11546 */
11547 if (__intel_pageflip_stall_check(dev, crtc)) {
11548 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11549 page_flip_completed(intel_crtc);
11550 } else {
11551 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 11552 spin_unlock_irq(&dev->event_lock);
468f0b44 11553
d6bbafa1
CW		 11554 drm_crtc_vblank_put(crtc);
11555 kfree(work);
11556 return -EBUSY;
11557 }
6b95a207
KH		 11558 }
11559 intel_crtc->unpin_work = work;
5e2d7afc 11560 spin_unlock_irq(&dev->event_lock);
6b95a207 11561
b4a98e57
CW		 11562 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11563 flush_workqueue(dev_priv->wq);
11564
75dfca80 11565 /* Reference the objects for the scheduled work. */
ab8d6675 11566 drm_framebuffer_reference(work->old_fb);
05394f39 11567 drm_gem_object_reference(&obj->base);
6b95a207 11568
f4510a27 11569 crtc->primary->fb = fb;
afd65eb4 11570 update_state_fb(crtc->primary);
1ed1f968 11571
e1f99ce6 11572 work->pending_flip_obj = obj;
e1f99ce6 11573
89ed88ba
CW		 11574 ret = i915_mutex_lock_interruptible(dev);
11575 if (ret)
11576 goto cleanup;
11577
b4a98e57 11578 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 11579 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 11580
75f7f3ec 11581 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 11582 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 11583
4fa62c89
VS		 11584 if (IS_VALLEYVIEW(dev)) {
11585 ring = &dev_priv->ring[BCS];
ab8d6675 11586 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 11587 /* vlv: DISPLAY_FLIP fails to change tiling */
11588 ring = NULL;
48bf5b2d 11589 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 11590 ring = &dev_priv->ring[BCS];
4fa62c89 11591 } else if (INTEL_INFO(dev)->gen >= 7) {
b4716185 11592 ring = i915_gem_request_get_ring(obj->last_write_req);
4fa62c89
VS		 11593 if (ring == NULL || ring->id != RCS)
11594 ring = &dev_priv->ring[BCS];
11595 } else {
11596 ring = &dev_priv->ring[RCS];
11597 }
11598
cf5d8a46
CW		 11599 mmio_flip = use_mmio_flip(ring, obj);
11600
11601 /* When using CS flips, we want to emit semaphores between rings.
11602 * However, when using mmio flips we will create a task to do the
11603 * synchronisation, so all we want here is to pin the framebuffer
11604 * into the display plane and skip any waits.
11605 */
82bc3b2d 11606 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
cf5d8a46 11607 crtc->primary->state,
b4716185 11608 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring);
8c9f3aaf
JB		 11609 if (ret)
11610 goto cleanup_pending;
6b95a207 11611
121920fa
TU		 11612 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11613 + intel_crtc->dspaddr_offset;
4fa62c89 11614
cf5d8a46 11615 if (mmio_flip) {
84c33a64
SG		 11616 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11617 page_flip_flags);
d6bbafa1
CW		 11618 if (ret)
11619 goto cleanup_unpin;
11620
f06cc1b9
JH		 11621 i915_gem_request_assign(&work->flip_queued_req,
11622 obj->last_write_req);
d6bbafa1 11623 } else {
d94b5030
CW		 11624 if (obj->last_write_req) {
11625 ret = i915_gem_check_olr(obj->last_write_req);
11626 if (ret)
11627 goto cleanup_unpin;
11628 }
11629
84c33a64 11630 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
d6bbafa1
CW		 11631 page_flip_flags);
11632 if (ret)
11633 goto cleanup_unpin;
11634
f06cc1b9
JH		 11635 i915_gem_request_assign(&work->flip_queued_req,
11636 intel_ring_get_request(ring));
d6bbafa1
CW		 11637 }
11638
1e3feefd 11639 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 11640 work->enable_stall_check = true;
4fa62c89 11641
ab8d6675 11642 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a071fa00
DV		 11643 INTEL_FRONTBUFFER_PRIMARY(pipe));
11644
7ff0ebcc 11645 intel_fbc_disable(dev);
f99d7069 11646 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
6b95a207
KH		 11647 mutex_unlock(&dev->struct_mutex);
11648
e5510fac
JB		 11649 trace_i915_flip_request(intel_crtc->plane, obj);
11650
6b95a207 11651 return 0;
96b099fd 11652
4fa62c89 11653cleanup_unpin:
82bc3b2d 11654 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 11655cleanup_pending:
b4a98e57 11656 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 11657 mutex_unlock(&dev->struct_mutex);
11658cleanup:
f4510a27 11659 crtc->primary->fb = old_fb;
afd65eb4 11660 update_state_fb(crtc->primary);
89ed88ba
CW		 11661
11662 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 11663 drm_framebuffer_unreference(work->old_fb);
96b099fd 11664
5e2d7afc 11665 spin_lock_irq(&dev->event_lock);
96b099fd 11666 intel_crtc->unpin_work = NULL;
5e2d7afc 11667 spin_unlock_irq(&dev->event_lock);
96b099fd 11668
87b6b101 11669 drm_crtc_vblank_put(crtc);
7317c75e 11670free_work:
96b099fd
CW		 11671 kfree(work);
11672
f900db47
CW		 11673 if (ret == -EIO) {
11674out_hang:
53a366b9 11675 ret = intel_plane_restore(primary);
f0d3dad3 11676 if (ret == 0 && event) {
5e2d7afc 11677 spin_lock_irq(&dev->event_lock);
a071fa00 11678 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 11679 spin_unlock_irq(&dev->event_lock);
f0d3dad3 11680 }
f900db47 11681 }
96b099fd 11682 return ret;
6b95a207
KH		 11683}
11684
65b38e0d 11685static const struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 11686 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11687 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 11688 .atomic_begin = intel_begin_crtc_commit,
11689 .atomic_flush = intel_finish_crtc_commit,
f6e5b160
CW		 11690};
11691
9a935856
DV		 11692/**
11693 * intel_modeset_update_staged_output_state
11694 *
11695 * Updates the staged output configuration state, e.g. after we've read out the
11696 * current hw state.
11697 */
11698static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 11699{
7668851f 11700 struct intel_crtc *crtc;
9a935856
DV		 11701 struct intel_encoder *encoder;
11702 struct intel_connector *connector;
f6e5b160 11703
3a3371ff 11704 for_each_intel_connector(dev, connector) {
9a935856
DV		 11705 connector->new_encoder =
11706 to_intel_encoder(connector->base.encoder);
11707 }
f6e5b160 11708
b2784e15 11709 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 11710 encoder->new_crtc =
11711 to_intel_crtc(encoder->base.crtc);
11712 }
7668851f 11713
d3fcc808 11714 for_each_intel_crtc(dev, crtc) {
83d65738 11715 crtc->new_enabled = crtc->base.state->enable;
7668851f 11716 }
f6e5b160
CW		 11717}
11718
d29b2f9d
ACO		 11719/* Transitional helper to copy current connector/encoder state to
11720 * connector->state. This is needed so that code that is partially
11721 * converted to atomic does the right thing.
11722 */
11723static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11724{
11725 struct intel_connector *connector;
11726
11727 for_each_intel_connector(dev, connector) {
11728 if (connector->base.encoder) {
11729 connector->base.state->best_encoder =
11730 connector->base.encoder;
11731 connector->base.state->crtc =
11732 connector->base.encoder->crtc;
11733 } else {
11734 connector->base.state->best_encoder = NULL;
11735 connector->base.state->crtc = NULL;
11736 }
11737 }
11738}
11739
050f7aeb 11740static void
eba905b2 11741connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 11742 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 11743{
11744 int bpp = pipe_config->pipe_bpp;
11745
11746 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11747 connector->base.base.id,
c23cc417 11748 connector->base.name);
050f7aeb
DV		 11749
11750 /* Don't use an invalid EDID bpc value */
11751 if (connector->base.display_info.bpc &&
11752 connector->base.display_info.bpc * 3 < bpp) {
11753 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11754 bpp, connector->base.display_info.bpc*3);
11755 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11756 }
11757
11758 /* Clamp bpp to 8 on screens without EDID 1.4 */
11759 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11760 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11761 bpp);
11762 pipe_config->pipe_bpp = 24;
11763 }
11764}
11765
4e53c2e0 11766static int
050f7aeb 11767compute_baseline_pipe_bpp(struct intel_crtc *crtc,
5cec258b 11768 struct intel_crtc_state *pipe_config)
4e53c2e0 11769{
050f7aeb 11770 struct drm_device *dev = crtc->base.dev;
1486017f 11771 struct drm_atomic_state *state;
da3ced29
ACO		 11772 struct drm_connector *connector;
11773 struct drm_connector_state *connector_state;
1486017f 11774 int bpp, i;
4e53c2e0 11775
d328c9d7 11776 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
4e53c2e0 11777 bpp = 10*3;
d328c9d7
DV		 11778 else if (INTEL_INFO(dev)->gen >= 5)
11779 bpp = 12*3;
11780 else
11781 bpp = 8*3;
11782
4e53c2e0 11783
4e53c2e0
DV		 11784 pipe_config->pipe_bpp = bpp;
11785
1486017f
ACO		 11786 state = pipe_config->base.state;
11787
4e53c2e0 11788 /* Clamp display bpp to EDID value */
da3ced29
ACO		 11789 for_each_connector_in_state(state, connector, connector_state, i) {
11790 if (connector_state->crtc != &crtc->base)
4e53c2e0
DV		 11791 continue;
11792
da3ced29
ACO		 11793 connected_sink_compute_bpp(to_intel_connector(connector),
11794 pipe_config);
4e53c2e0
DV		 11795 }
11796
11797 return bpp;
11798}
11799
644db711
DV		 11800static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11801{
11802 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11803 "type: 0x%x flags: 0x%x\n",
1342830c 11804 mode->crtc_clock,
644db711
DV		 11805 mode->crtc_hdisplay, mode->crtc_hsync_start,
11806 mode->crtc_hsync_end, mode->crtc_htotal,
11807 mode->crtc_vdisplay, mode->crtc_vsync_start,
11808 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11809}
11810
c0b03411 11811static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 11812 struct intel_crtc_state *pipe_config,
c0b03411
DV		 11813 const char *context)
11814{
6a60cd87
CK		 11815 struct drm_device *dev = crtc->base.dev;
11816 struct drm_plane *plane;
11817 struct intel_plane *intel_plane;
11818 struct intel_plane_state *state;
11819 struct drm_framebuffer *fb;
11820
11821 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11822 context, pipe_config, pipe_name(crtc->pipe));
c0b03411
DV		 11823
11824 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11825 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11826 pipe_config->pipe_bpp, pipe_config->dither);
11827 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11828 pipe_config->has_pch_encoder,
11829 pipe_config->fdi_lanes,
11830 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11831 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11832 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 11833 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11834 pipe_config->has_dp_encoder,
11835 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11836 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11837 pipe_config->dp_m_n.tu);
b95af8be
VK		 11838
11839 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11840 pipe_config->has_dp_encoder,
11841 pipe_config->dp_m2_n2.gmch_m,
11842 pipe_config->dp_m2_n2.gmch_n,
11843 pipe_config->dp_m2_n2.link_m,
11844 pipe_config->dp_m2_n2.link_n,
11845 pipe_config->dp_m2_n2.tu);
11846
55072d19
DV		 11847 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11848 pipe_config->has_audio,
11849 pipe_config->has_infoframe);
11850
c0b03411 11851 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 11852 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 11853 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 11854 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11855 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 11856 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 11857 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11858 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
0ec463d3
TU		 11859 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11860 crtc->num_scalers,
11861 pipe_config->scaler_state.scaler_users,
11862 pipe_config->scaler_state.scaler_id);
c0b03411
DV		 11863 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11864 pipe_config->gmch_pfit.control,
11865 pipe_config->gmch_pfit.pgm_ratios,
11866 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 11867 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 11868 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 11869 pipe_config->pch_pfit.size,
11870 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 11871 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 11872 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87 11873
415ff0f6
TU		 11874 if (IS_BROXTON(dev)) {
11875 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, "
11876 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11877 "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n",
11878 pipe_config->ddi_pll_sel,
11879 pipe_config->dpll_hw_state.ebb0,
11880 pipe_config->dpll_hw_state.pll0,
11881 pipe_config->dpll_hw_state.pll1,
11882 pipe_config->dpll_hw_state.pll2,
11883 pipe_config->dpll_hw_state.pll3,
11884 pipe_config->dpll_hw_state.pll6,
11885 pipe_config->dpll_hw_state.pll8,
11886 pipe_config->dpll_hw_state.pcsdw12);
11887 } else if (IS_SKYLAKE(dev)) {
11888 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11889 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11890 pipe_config->ddi_pll_sel,
11891 pipe_config->dpll_hw_state.ctrl1,
11892 pipe_config->dpll_hw_state.cfgcr1,
11893 pipe_config->dpll_hw_state.cfgcr2);
11894 } else if (HAS_DDI(dev)) {
11895 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11896 pipe_config->ddi_pll_sel,
11897 pipe_config->dpll_hw_state.wrpll);
11898 } else {
11899 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11900 "fp0: 0x%x, fp1: 0x%x\n",
11901 pipe_config->dpll_hw_state.dpll,
11902 pipe_config->dpll_hw_state.dpll_md,
11903 pipe_config->dpll_hw_state.fp0,
11904 pipe_config->dpll_hw_state.fp1);
11905 }
11906
6a60cd87
CK		 11907 DRM_DEBUG_KMS("planes on this crtc\n");
11908 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11909 intel_plane = to_intel_plane(plane);
11910 if (intel_plane->pipe != crtc->pipe)
11911 continue;
11912
11913 state = to_intel_plane_state(plane->state);
11914 fb = state->base.fb;
11915 if (!fb) {
11916 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11917 "disabled, scaler_id = %d\n",
11918 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11919 plane->base.id, intel_plane->pipe,
11920 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11921 drm_plane_index(plane), state->scaler_id);
11922 continue;
11923 }
11924
11925 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11926 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11927 plane->base.id, intel_plane->pipe,
11928 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11929 drm_plane_index(plane));
11930 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11931 fb->base.id, fb->width, fb->height, fb->pixel_format);
11932 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11933 state->scaler_id,
11934 state->src.x1 >> 16, state->src.y1 >> 16,
11935 drm_rect_width(&state->src) >> 16,
11936 drm_rect_height(&state->src) >> 16,
11937 state->dst.x1, state->dst.y1,
11938 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11939 }
c0b03411
DV		 11940}
11941
bc079e8b
VS		 11942static bool encoders_cloneable(const struct intel_encoder *a,
11943 const struct intel_encoder *b)
accfc0c5 11944{
bc079e8b
VS		 11945 /* masks could be asymmetric, so check both ways */
11946 return a == b || (a->cloneable & (1 << b->type) &&
11947 b->cloneable & (1 << a->type));
11948}
11949
98a221da
ACO		 11950static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11951 struct intel_crtc *crtc,
bc079e8b
VS		 11952 struct intel_encoder *encoder)
11953{
bc079e8b 11954 struct intel_encoder *source_encoder;
da3ced29 11955 struct drm_connector *connector;
98a221da
ACO		 11956 struct drm_connector_state *connector_state;
11957 int i;
bc079e8b 11958
da3ced29 11959 for_each_connector_in_state(state, connector, connector_state, i) {
98a221da 11960 if (connector_state->crtc != &crtc->base)
bc079e8b
VS		 11961 continue;
11962
98a221da
ACO		 11963 source_encoder =
11964 to_intel_encoder(connector_state->best_encoder);
bc079e8b
VS		 11965 if (!encoders_cloneable(encoder, source_encoder))
11966 return false;
11967 }
11968
11969 return true;
11970}
11971
98a221da
ACO		 11972static bool check_encoder_cloning(struct drm_atomic_state *state,
11973 struct intel_crtc *crtc)
bc079e8b 11974{
accfc0c5 11975 struct intel_encoder *encoder;
da3ced29 11976 struct drm_connector *connector;
98a221da
ACO		 11977 struct drm_connector_state *connector_state;
11978 int i;
accfc0c5 11979
da3ced29 11980 for_each_connector_in_state(state, connector, connector_state, i) {
98a221da
ACO		 11981 if (connector_state->crtc != &crtc->base)
11982 continue;
11983
11984 encoder = to_intel_encoder(connector_state->best_encoder);
11985 if (!check_single_encoder_cloning(state, crtc, encoder))
bc079e8b 11986 return false;
accfc0c5
DV		 11987 }
11988
bc079e8b 11989 return true;
accfc0c5
DV		 11990}
11991
5448a00d 11992static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 11993{
5448a00d
ACO		 11994 struct drm_device *dev = state->dev;
11995 struct intel_encoder *encoder;
da3ced29 11996 struct drm_connector *connector;
5448a00d 11997 struct drm_connector_state *connector_state;
00f0b378 11998 unsigned int used_ports = 0;
5448a00d 11999 int i;
00f0b378
VS		 12000
12001 /*
12002 * Walk the connector list instead of the encoder
12003 * list to detect the problem on ddi platforms
12004 * where there's just one encoder per digital port.
12005 */
da3ced29 12006 for_each_connector_in_state(state, connector, connector_state, i) {
5448a00d 12007 if (!connector_state->best_encoder)
00f0b378
VS		 12008 continue;
12009
5448a00d
ACO		 12010 encoder = to_intel_encoder(connector_state->best_encoder);
12011
12012 WARN_ON(!connector_state->crtc);
00f0b378
VS		 12013
12014 switch (encoder->type) {
12015 unsigned int port_mask;
12016 case INTEL_OUTPUT_UNKNOWN:
12017 if (WARN_ON(!HAS_DDI(dev)))
12018 break;
12019 case INTEL_OUTPUT_DISPLAYPORT:
12020 case INTEL_OUTPUT_HDMI:
12021 case INTEL_OUTPUT_EDP:
12022 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12023
12024 /* the same port mustn't appear more than once */
12025 if (used_ports & port_mask)
12026 return false;
12027
12028 used_ports |= port_mask;
12029 default:
12030 break;
12031 }
12032 }
12033
12034 return true;
12035}
12036
83a57153
ACO		 12037static void
12038clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12039{
12040 struct drm_crtc_state tmp_state;
663a3640 12041 struct intel_crtc_scaler_state scaler_state;
4978cc93
ACO		 12042 struct intel_dpll_hw_state dpll_hw_state;
12043 enum intel_dpll_id shared_dpll;
8504c74c 12044 uint32_t ddi_pll_sel;
83a57153 12045
7546a384
ACO		 12046 /* FIXME: before the switch to atomic started, a new pipe_config was
12047 * kzalloc'd. Code that depends on any field being zero should be
12048 * fixed, so that the crtc_state can be safely duplicated. For now,
12049 * only fields that are know to not cause problems are preserved. */
12050
83a57153 12051 tmp_state = crtc_state->base;
663a3640 12052 scaler_state = crtc_state->scaler_state;
4978cc93
ACO		 12053 shared_dpll = crtc_state->shared_dpll;
12054 dpll_hw_state = crtc_state->dpll_hw_state;
8504c74c 12055 ddi_pll_sel = crtc_state->ddi_pll_sel;
4978cc93 12056
83a57153 12057 memset(crtc_state, 0, sizeof *crtc_state);
4978cc93 12058
83a57153 12059 crtc_state->base = tmp_state;
663a3640 12060 crtc_state->scaler_state = scaler_state;
4978cc93
ACO		 12061 crtc_state->shared_dpll = shared_dpll;
12062 crtc_state->dpll_hw_state = dpll_hw_state;
8504c74c 12063 crtc_state->ddi_pll_sel = ddi_pll_sel;
83a57153
ACO		 12064}
12065
548ee15b 12066static int
b8cecdf5 12067intel_modeset_pipe_config(struct drm_crtc *crtc,
548ee15b
ACO		 12068 struct drm_atomic_state *state,
12069 struct intel_crtc_state *pipe_config)
ee7b9f93 12070{
7758a113 12071 struct intel_encoder *encoder;
da3ced29 12072 struct drm_connector *connector;
0b901879 12073 struct drm_connector_state *connector_state;
d328c9d7 12074 int base_bpp, ret = -EINVAL;
0b901879 12075 int i;
e29c22c0 12076 bool retry = true;
ee7b9f93 12077
98a221da 12078 if (!check_encoder_cloning(state, to_intel_crtc(crtc))) {
accfc0c5 12079 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
548ee15b 12080 return -EINVAL;
accfc0c5
DV		 12081 }
12082
5448a00d 12083 if (!check_digital_port_conflicts(state)) {
00f0b378 12084 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
548ee15b 12085 return -EINVAL;
00f0b378
VS		 12086 }
12087
83a57153 12088 clear_intel_crtc_state(pipe_config);
7758a113 12089
e143a21c
DV		 12090 pipe_config->cpu_transcoder =
12091 (enum transcoder) to_intel_crtc(crtc)->pipe;
b8cecdf5 12092
2960bc9c
ID		 12093 /*
12094 * Sanitize sync polarity flags based on requested ones. If neither
12095 * positive or negative polarity is requested, treat this as meaning
12096 * negative polarity.
12097 */
2d112de7 12098 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12099 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 12100 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 12101
2d112de7 12102 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12103 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 12104 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 12105
050f7aeb
DV		 12106 /* Compute a starting value for pipe_config->pipe_bpp taking the source
12107 * plane pixel format and any sink constraints into account. Returns the
12108 * source plane bpp so that dithering can be selected on mismatches
12109 * after encoders and crtc also have had their say. */
d328c9d7
DV		 12110 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12111 pipe_config);
12112 if (base_bpp < 0)
4e53c2e0
DV		 12113 goto fail;
12114
e41a56be
VS		 12115 /*
12116 * Determine the real pipe dimensions. Note that stereo modes can
12117 * increase the actual pipe size due to the frame doubling and
12118 * insertion of additional space for blanks between the frame. This
12119 * is stored in the crtc timings. We use the requested mode to do this
12120 * computation to clearly distinguish it from the adjusted mode, which
12121 * can be changed by the connectors in the below retry loop.
12122 */
2d112de7 12123 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 12124 &pipe_config->pipe_src_w,
12125 &pipe_config->pipe_src_h);
e41a56be 12126
e29c22c0 12127encoder_retry:
ef1b460d 12128 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 12129 pipe_config->port_clock = 0;
ef1b460d 12130 pipe_config->pixel_multiplier = 1;
ff9a6750 12131
135c81b8 12132 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 12133 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12134 CRTC_STEREO_DOUBLE);
135c81b8 12135
7758a113
DV		 12136 /* Pass our mode to the connectors and the CRTC to give them a chance to
12137 * adjust it according to limitations or connector properties, and also
12138 * a chance to reject the mode entirely.
47f1c6c9 12139 */
da3ced29 12140 for_each_connector_in_state(state, connector, connector_state, i) {
0b901879 12141 if (connector_state->crtc != crtc)
7758a113 12142 continue;
7ae89233 12143
0b901879
ACO		 12144 encoder = to_intel_encoder(connector_state->best_encoder);
12145
efea6e8e
DV		 12146 if (!(encoder->compute_config(encoder, pipe_config))) {
12147 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 12148 goto fail;
12149 }
ee7b9f93 12150 }
47f1c6c9 12151
ff9a6750
DV		 12152 /* Set default port clock if not overwritten by the encoder. Needs to be
12153 * done afterwards in case the encoder adjusts the mode. */
12154 if (!pipe_config->port_clock)
2d112de7 12155 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 12156 * pipe_config->pixel_multiplier;
ff9a6750 12157
a43f6e0f 12158 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 12159 if (ret < 0) {
7758a113
DV		 12160 DRM_DEBUG_KMS("CRTC fixup failed\n");
12161 goto fail;
ee7b9f93 12162 }
e29c22c0
DV		 12163
12164 if (ret == RETRY) {
12165 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12166 ret = -EINVAL;
12167 goto fail;
12168 }
12169
12170 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12171 retry = false;
12172 goto encoder_retry;
12173 }
12174
d328c9d7 12175 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
4e53c2e0 12176 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
d328c9d7 12177 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
4e53c2e0 12178
548ee15b 12179 return 0;
7758a113 12180fail:
548ee15b 12181 return ret;
ee7b9f93 12182}
47f1c6c9 12183
ea9d758d 12184static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 12185{
ea9d758d 12186 struct drm_encoder *encoder;
f6e5b160 12187 struct drm_device *dev = crtc->dev;
f6e5b160 12188
ea9d758d
DV		 12189 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
12190 if (encoder->crtc == crtc)
12191 return true;
12192
12193 return false;
12194}
12195
0a9ab303
ACO		 12196static bool
12197needs_modeset(struct drm_crtc_state *state)
12198{
12199 return state->mode_changed || state->active_changed;
12200}
12201
ea9d758d 12202static void
0a9ab303 12203intel_modeset_update_state(struct drm_atomic_state *state)
ea9d758d 12204{
0a9ab303 12205 struct drm_device *dev = state->dev;
ba41c0de 12206 struct drm_i915_private *dev_priv = dev->dev_private;
ea9d758d 12207 struct intel_encoder *intel_encoder;
0a9ab303
ACO		 12208 struct drm_crtc *crtc;
12209 struct drm_crtc_state *crtc_state;
ea9d758d
DV		 12210 struct drm_connector *connector;
12211
ba41c0de 12212 intel_shared_dpll_commit(dev_priv);
69024de8 12213 drm_atomic_helper_swap_state(state->dev, state);
ba41c0de 12214
b2784e15 12215 for_each_intel_encoder(dev, intel_encoder) {
ea9d758d
DV		 12216 if (!intel_encoder->base.crtc)
12217 continue;
12218
69024de8
ML		 12219 crtc = intel_encoder->base.crtc;
12220 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12221 if (!crtc_state || !needs_modeset(crtc->state))
12222 continue;
ea9d758d 12223
69024de8 12224 intel_encoder->connectors_active = false;
ea9d758d
DV		 12225 }
12226
3cb480bc
ML		 12227 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12228 intel_modeset_update_staged_output_state(state->dev);
ea9d758d 12229
7668851f 12230 /* Double check state. */
0a9ab303
ACO		 12231 for_each_crtc(dev, crtc) {
12232 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
3cb480bc
ML		 12233
12234 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
ea9d758d
DV		 12235 }
12236
12237 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12238 if (!connector->encoder || !connector->encoder->crtc)
12239 continue;
12240
69024de8
ML		 12241 crtc = connector->encoder->crtc;
12242 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12243 if (!crtc_state || !needs_modeset(crtc->state))
12244 continue;
ea9d758d 12245
69024de8
ML		 12246 if (crtc->state->enable) {
12247 struct drm_property *dpms_property =
12248 dev->mode_config.dpms_property;
68d34720 12249
69024de8
ML		 12250 connector->dpms = DRM_MODE_DPMS_ON;
12251 drm_object_property_set_value(&connector->base, dpms_property, DRM_MODE_DPMS_ON);
ea9d758d 12252
69024de8
ML		 12253 intel_encoder = to_intel_encoder(connector->encoder);
12254 intel_encoder->connectors_active = true;
12255 } else
12256 connector->dpms = DRM_MODE_DPMS_OFF;
ea9d758d 12257 }
ea9d758d
DV		 12258}
12259
3bd26263 12260static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 12261{
3bd26263 12262 int diff;
f1f644dc
JB		 12263
12264 if (clock1 == clock2)
12265 return true;
12266
12267 if (!clock1 || !clock2)
12268 return false;
12269
12270 diff = abs(clock1 - clock2);
12271
12272 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12273 return true;
12274
12275 return false;
12276}
12277
25c5b266
DV		 12278#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12279 list_for_each_entry((intel_crtc), \
12280 &(dev)->mode_config.crtc_list, \
12281 base.head) \
0973f18f 12282 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 12283
0e8ffe1b 12284static bool
2fa2fe9a 12285intel_pipe_config_compare(struct drm_device *dev,
5cec258b
ACO		 12286 struct intel_crtc_state *current_config,
12287 struct intel_crtc_state *pipe_config)
0e8ffe1b 12288{
66e985c0
DV		 12289#define PIPE_CONF_CHECK_X(name) \
12290 if (current_config->name != pipe_config->name) { \
12291 DRM_ERROR("mismatch in " #name " " \
12292 "(expected 0x%08x, found 0x%08x)\n", \
12293 current_config->name, \
12294 pipe_config->name); \
12295 return false; \
12296 }
12297
08a24034
DV		 12298#define PIPE_CONF_CHECK_I(name) \
12299 if (current_config->name != pipe_config->name) { \
12300 DRM_ERROR("mismatch in " #name " " \
12301 "(expected %i, found %i)\n", \
12302 current_config->name, \
12303 pipe_config->name); \
12304 return false; \
88adfff1
DV		 12305 }
12306
b95af8be
VK		 12307/* This is required for BDW+ where there is only one set of registers for
12308 * switching between high and low RR.
12309 * This macro can be used whenever a comparison has to be made between one
12310 * hw state and multiple sw state variables.
12311 */
12312#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12313 if ((current_config->name != pipe_config->name) && \
12314 (current_config->alt_name != pipe_config->name)) { \
12315 DRM_ERROR("mismatch in " #name " " \
12316 "(expected %i or %i, found %i)\n", \
12317 current_config->name, \
12318 current_config->alt_name, \
12319 pipe_config->name); \
12320 return false; \
12321 }
12322
1bd1bd80
DV		 12323#define PIPE_CONF_CHECK_FLAGS(name, mask) \
12324 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 12325 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 12326 "(expected %i, found %i)\n", \
12327 current_config->name & (mask), \
12328 pipe_config->name & (mask)); \
12329 return false; \
12330 }
12331
5e550656
VS		 12332#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12333 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12334 DRM_ERROR("mismatch in " #name " " \
12335 "(expected %i, found %i)\n", \
12336 current_config->name, \
12337 pipe_config->name); \
12338 return false; \
12339 }
12340
bb760063
DV		 12341#define PIPE_CONF_QUIRK(quirk) \
12342 ((current_config->quirks | pipe_config->quirks) & (quirk))
12343
eccb140b
DV		 12344 PIPE_CONF_CHECK_I(cpu_transcoder);
12345
08a24034
DV		 12346 PIPE_CONF_CHECK_I(has_pch_encoder);
12347 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 12348 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
12349 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
12350 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
12351 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
12352 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 12353
eb14cb74 12354 PIPE_CONF_CHECK_I(has_dp_encoder);
b95af8be
VK		 12355
12356 if (INTEL_INFO(dev)->gen < 8) {
12357 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
12358 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
12359 PIPE_CONF_CHECK_I(dp_m_n.link_m);
12360 PIPE_CONF_CHECK_I(dp_m_n.link_n);
12361 PIPE_CONF_CHECK_I(dp_m_n.tu);
12362
12363 if (current_config->has_drrs) {
12364 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
12365 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
12366 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
12367 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
12368 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
12369 }
12370 } else {
12371 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
12372 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
12373 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
12374 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
12375 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
12376 }
eb14cb74 12377
2d112de7
ACO		 12378 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12379 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12380 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12381 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12382 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12383 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 12384
2d112de7
ACO		 12385 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12386 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12387 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12388 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12389 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12390 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 12391
c93f54cf 12392 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 12393 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 12394 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12395 IS_VALLEYVIEW(dev))
12396 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 12397 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 12398
9ed109a7
DV		 12399 PIPE_CONF_CHECK_I(has_audio);
12400
2d112de7 12401 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 12402 DRM_MODE_FLAG_INTERLACE);
12403
bb760063 12404 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 12405 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12406 DRM_MODE_FLAG_PHSYNC);
2d112de7 12407 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12408 DRM_MODE_FLAG_NHSYNC);
2d112de7 12409 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12410 DRM_MODE_FLAG_PVSYNC);
2d112de7 12411 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 12412 DRM_MODE_FLAG_NVSYNC);
12413 }
045ac3b5 12414
37327abd
VS		 12415 PIPE_CONF_CHECK_I(pipe_src_w);
12416 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 12417
9953599b
DV		 12418 /*
12419 * FIXME: BIOS likes to set up a cloned config with lvds+external
12420 * screen. Since we don't yet re-compute the pipe config when moving
12421 * just the lvds port away to another pipe the sw tracking won't match.
12422 *
12423 * Proper atomic modesets with recomputed global state will fix this.
12424 * Until then just don't check gmch state for inherited modes.
12425 */
12426 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
12427 PIPE_CONF_CHECK_I(gmch_pfit.control);
12428 /* pfit ratios are autocomputed by the hw on gen4+ */
12429 if (INTEL_INFO(dev)->gen < 4)
12430 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12431 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12432 }
12433
fd4daa9c
CW		 12434 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12435 if (current_config->pch_pfit.enabled) {
12436 PIPE_CONF_CHECK_I(pch_pfit.pos);
12437 PIPE_CONF_CHECK_I(pch_pfit.size);
12438 }
2fa2fe9a 12439
a1b2278e
CK		 12440 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12441
e59150dc
JB		 12442 /* BDW+ don't expose a synchronous way to read the state */
12443 if (IS_HASWELL(dev))
12444 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 12445
282740f7
VS		 12446 PIPE_CONF_CHECK_I(double_wide);
12447
26804afd
DV		 12448 PIPE_CONF_CHECK_X(ddi_pll_sel);
12449
c0d43d62 12450 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 12451 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 12452 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 12453 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12454 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 12455 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 12456 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12457 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12458 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 12459
42571aef
VS		 12460 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12461 PIPE_CONF_CHECK_I(pipe_bpp);
12462
2d112de7 12463 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 12464 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 12465
66e985c0 12466#undef PIPE_CONF_CHECK_X
08a24034 12467#undef PIPE_CONF_CHECK_I
b95af8be 12468#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 12469#undef PIPE_CONF_CHECK_FLAGS
5e550656 12470#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 12471#undef PIPE_CONF_QUIRK
88adfff1 12472
0e8ffe1b
DV		 12473 return true;
12474}
12475
08db6652
DL		 12476static void check_wm_state(struct drm_device *dev)
12477{
12478 struct drm_i915_private *dev_priv = dev->dev_private;
12479 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12480 struct intel_crtc *intel_crtc;
12481 int plane;
12482
12483 if (INTEL_INFO(dev)->gen < 9)
12484 return;
12485
12486 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12487 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12488
12489 for_each_intel_crtc(dev, intel_crtc) {
12490 struct skl_ddb_entry *hw_entry, *sw_entry;
12491 const enum pipe pipe = intel_crtc->pipe;
12492
12493 if (!intel_crtc->active)
12494 continue;
12495
12496 /* planes */
dd740780 12497 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 12498 hw_entry = &hw_ddb.plane[pipe][plane];
12499 sw_entry = &sw_ddb->plane[pipe][plane];
12500
12501 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12502 continue;
12503
12504 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12505 "(expected (%u,%u), found (%u,%u))\n",
12506 pipe_name(pipe), plane + 1,
12507 sw_entry->start, sw_entry->end,
12508 hw_entry->start, hw_entry->end);
12509 }
12510
12511 /* cursor */
12512 hw_entry = &hw_ddb.cursor[pipe];
12513 sw_entry = &sw_ddb->cursor[pipe];
12514
12515 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12516 continue;
12517
12518 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12519 "(expected (%u,%u), found (%u,%u))\n",
12520 pipe_name(pipe),
12521 sw_entry->start, sw_entry->end,
12522 hw_entry->start, hw_entry->end);
12523 }
12524}
12525
91d1b4bd
DV		 12526static void
12527check_connector_state(struct drm_device *dev)
8af6cf88 12528{
8af6cf88
DV		 12529 struct intel_connector *connector;
12530
3a3371ff 12531 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 12532 /* This also checks the encoder/connector hw state with the
12533 * ->get_hw_state callbacks. */
12534 intel_connector_check_state(connector);
12535
e2c719b7 12536 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
8af6cf88
DV		 12537 "connector's staged encoder doesn't match current encoder\n");
12538 }
91d1b4bd
DV		 12539}
12540
12541static void
12542check_encoder_state(struct drm_device *dev)
12543{
12544 struct intel_encoder *encoder;
12545 struct intel_connector *connector;
8af6cf88 12546
b2784e15 12547 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 12548 bool enabled = false;
12549 bool active = false;
12550 enum pipe pipe, tracked_pipe;
12551
12552 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12553 encoder->base.base.id,
8e329a03 12554 encoder->base.name);
8af6cf88 12555
e2c719b7 12556 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
8af6cf88 12557 "encoder's stage crtc doesn't match current crtc\n");
e2c719b7 12558 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
8af6cf88
DV		 12559 "encoder's active_connectors set, but no crtc\n");
12560
3a3371ff 12561 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 12562 if (connector->base.encoder != &encoder->base)
12563 continue;
12564 enabled = true;
12565 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12566 active = true;
12567 }
0e32b39c
DA		 12568 /*
12569 * for MST connectors if we unplug the connector is gone
12570 * away but the encoder is still connected to a crtc
12571 * until a modeset happens in response to the hotplug.
12572 */
12573 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12574 continue;
12575
e2c719b7 12576 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 12577 "encoder's enabled state mismatch "
12578 "(expected %i, found %i)\n",
12579 !!encoder->base.crtc, enabled);
e2c719b7 12580 I915_STATE_WARN(active && !encoder->base.crtc,
8af6cf88
DV		 12581 "active encoder with no crtc\n");
12582
e2c719b7 12583 I915_STATE_WARN(encoder->connectors_active != active,
8af6cf88
DV		 12584 "encoder's computed active state doesn't match tracked active state "
12585 "(expected %i, found %i)\n", active, encoder->connectors_active);
12586
12587 active = encoder->get_hw_state(encoder, &pipe);
e2c719b7 12588 I915_STATE_WARN(active != encoder->connectors_active,
8af6cf88
DV		 12589 "encoder's hw state doesn't match sw tracking "
12590 "(expected %i, found %i)\n",
12591 encoder->connectors_active, active);
12592
12593 if (!encoder->base.crtc)
12594 continue;
12595
12596 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
e2c719b7 12597 I915_STATE_WARN(active && pipe != tracked_pipe,
8af6cf88
DV		 12598 "active encoder's pipe doesn't match"
12599 "(expected %i, found %i)\n",
12600 tracked_pipe, pipe);
12601
12602 }
91d1b4bd
DV		 12603}
12604
12605static void
12606check_crtc_state(struct drm_device *dev)
12607{
fbee40df 12608 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12609 struct intel_crtc *crtc;
12610 struct intel_encoder *encoder;
5cec258b 12611 struct intel_crtc_state pipe_config;
8af6cf88 12612
d3fcc808 12613 for_each_intel_crtc(dev, crtc) {
8af6cf88
DV		 12614 bool enabled = false;
12615 bool active = false;
12616
045ac3b5
JB		 12617 memset(&pipe_config, 0, sizeof(pipe_config));
12618
8af6cf88
DV		 12619 DRM_DEBUG_KMS("[CRTC:%d]\n",
12620 crtc->base.base.id);
12621
83d65738 12622 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
8af6cf88
DV		 12623 "active crtc, but not enabled in sw tracking\n");
12624
b2784e15 12625 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 12626 if (encoder->base.crtc != &crtc->base)
12627 continue;
12628 enabled = true;
12629 if (encoder->connectors_active)
12630 active = true;
12631 }
6c49f241 12632
e2c719b7 12633 I915_STATE_WARN(active != crtc->active,
8af6cf88
DV		 12634 "crtc's computed active state doesn't match tracked active state "
12635 "(expected %i, found %i)\n", active, crtc->active);
83d65738 12636 I915_STATE_WARN(enabled != crtc->base.state->enable,
8af6cf88 12637 "crtc's computed enabled state doesn't match tracked enabled state "
83d65738
MR		 12638 "(expected %i, found %i)\n", enabled,
12639 crtc->base.state->enable);
8af6cf88 12640
0e8ffe1b
DV		 12641 active = dev_priv->display.get_pipe_config(crtc,
12642 &pipe_config);
d62cf62a 12643
b6b5d049
VS		 12644 /* hw state is inconsistent with the pipe quirk */
12645 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12646 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
d62cf62a
DV		 12647 active = crtc->active;
12648
b2784e15 12649 for_each_intel_encoder(dev, encoder) {
3eaba51c 12650 enum pipe pipe;
6c49f241
DV		 12651 if (encoder->base.crtc != &crtc->base)
12652 continue;
1d37b689 12653 if (encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 12654 encoder->get_config(encoder, &pipe_config);
12655 }
12656
e2c719b7 12657 I915_STATE_WARN(crtc->active != active,
0e8ffe1b
DV		 12658 "crtc active state doesn't match with hw state "
12659 "(expected %i, found %i)\n", crtc->active, active);
12660
c0b03411 12661 if (active &&
6e3c9717 12662 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
e2c719b7 12663 I915_STATE_WARN(1, "pipe state doesn't match!\n");
c0b03411
DV		 12664 intel_dump_pipe_config(crtc, &pipe_config,
12665 "[hw state]");
6e3c9717 12666 intel_dump_pipe_config(crtc, crtc->config,
c0b03411
DV		 12667 "[sw state]");
12668 }
8af6cf88
DV		 12669 }
12670}
12671
91d1b4bd
DV		 12672static void
12673check_shared_dpll_state(struct drm_device *dev)
12674{
fbee40df 12675 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12676 struct intel_crtc *crtc;
12677 struct intel_dpll_hw_state dpll_hw_state;
12678 int i;
5358901f
DV		 12679
12680 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12681 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12682 int enabled_crtcs = 0, active_crtcs = 0;
12683 bool active;
12684
12685 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12686
12687 DRM_DEBUG_KMS("%s\n", pll->name);
12688
12689 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12690
e2c719b7 12691 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 12692 "more active pll users than references: %i vs %i\n",
3e369b76 12693 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 12694 I915_STATE_WARN(pll->active && !pll->on,
5358901f 12695 "pll in active use but not on in sw tracking\n");
e2c719b7 12696 I915_STATE_WARN(pll->on && !pll->active,
35c95375 12697 "pll in on but not on in use in sw tracking\n");
e2c719b7 12698 I915_STATE_WARN(pll->on != active,
5358901f
DV		 12699 "pll on state mismatch (expected %i, found %i)\n",
12700 pll->on, active);
12701
d3fcc808 12702 for_each_intel_crtc(dev, crtc) {
83d65738 12703 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 12704 enabled_crtcs++;
12705 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12706 active_crtcs++;
12707 }
e2c719b7 12708 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 12709 "pll active crtcs mismatch (expected %i, found %i)\n",
12710 pll->active, active_crtcs);
e2c719b7 12711 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 12712 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 12713 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 12714
e2c719b7 12715 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 12716 sizeof(dpll_hw_state)),
12717 "pll hw state mismatch\n");
5358901f 12718 }
8af6cf88
DV		 12719}
12720
91d1b4bd
DV		 12721void
12722intel_modeset_check_state(struct drm_device *dev)
12723{
08db6652 12724 check_wm_state(dev);
91d1b4bd
DV		 12725 check_connector_state(dev);
12726 check_encoder_state(dev);
12727 check_crtc_state(dev);
12728 check_shared_dpll_state(dev);
12729}
12730
5cec258b 12731void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 12732 int dotclock)
12733{
12734 /*
12735 * FDI already provided one idea for the dotclock.
12736 * Yell if the encoder disagrees.
12737 */
2d112de7 12738 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 12739 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 12740 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 12741}
12742
80715b2f
VS		 12743static void update_scanline_offset(struct intel_crtc *crtc)
12744{
12745 struct drm_device *dev = crtc->base.dev;
12746
12747 /*
12748 * The scanline counter increments at the leading edge of hsync.
12749 *
12750 * On most platforms it starts counting from vtotal-1 on the
12751 * first active line. That means the scanline counter value is
12752 * always one less than what we would expect. Ie. just after
12753 * start of vblank, which also occurs at start of hsync (on the
12754 * last active line), the scanline counter will read vblank_start-1.
12755 *
12756 * On gen2 the scanline counter starts counting from 1 instead
12757 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12758 * to keep the value positive), instead of adding one.
12759 *
12760 * On HSW+ the behaviour of the scanline counter depends on the output
12761 * type. For DP ports it behaves like most other platforms, but on HDMI
12762 * there's an extra 1 line difference. So we need to add two instead of
12763 * one to the value.
12764 */
12765 if (IS_GEN2(dev)) {
6e3c9717 12766 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 12767 int vtotal;
12768
12769 vtotal = mode->crtc_vtotal;
12770 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12771 vtotal /= 2;
12772
12773 crtc->scanline_offset = vtotal - 1;
12774 } else if (HAS_DDI(dev) &&
409ee761 12775 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 12776 crtc->scanline_offset = 2;
12777 } else
12778 crtc->scanline_offset = 1;
12779}
12780
5cec258b 12781static struct intel_crtc_state *
7f27126e 12782intel_modeset_compute_config(struct drm_crtc *crtc,
0a9ab303 12783 struct drm_atomic_state *state)
7f27126e 12784{
548ee15b 12785 struct intel_crtc_state *pipe_config;
0b901879
ACO		 12786 int ret = 0;
12787
12788 ret = drm_atomic_add_affected_connectors(state, crtc);
12789 if (ret)
12790 return ERR_PTR(ret);
7f27126e 12791
8c7b5ccb
ACO		 12792 ret = drm_atomic_helper_check_modeset(state->dev, state);
12793 if (ret)
12794 return ERR_PTR(ret);
7f27126e 12795
7f27126e
JB		 12796 /*
12797 * Note this needs changes when we start tracking multiple modes
12798 * and crtcs. At that point we'll need to compute the whole config
12799 * (i.e. one pipe_config for each crtc) rather than just the one
12800 * for this crtc.
12801 */
548ee15b
ACO		 12802 pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
12803 if (IS_ERR(pipe_config))
12804 return pipe_config;
83a57153 12805
4fed33f6 12806 if (!pipe_config->base.enable)
548ee15b 12807 return pipe_config;
7f27126e 12808
8c7b5ccb 12809 ret = intel_modeset_pipe_config(crtc, state, pipe_config);
548ee15b
ACO		 12810 if (ret)
12811 return ERR_PTR(ret);
12812
8d8c9b51
ACO		 12813 /* Check things that can only be changed through modeset */
12814 if (pipe_config->has_audio !=
12815 to_intel_crtc(crtc)->config->has_audio)
12816 pipe_config->base.mode_changed = true;
12817
12818 /*
12819 * Note we have an issue here with infoframes: current code
12820 * only updates them on the full mode set path per hw
12821 * requirements. So here we should be checking for any
12822 * required changes and forcing a mode set.
12823 */
12824
548ee15b 12825 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,"[modeset]");
db7542dd 12826
8c7b5ccb
ACO		 12827 ret = drm_atomic_helper_check_planes(state->dev, state);
12828 if (ret)
12829 return ERR_PTR(ret);
12830
548ee15b 12831 return pipe_config;
7f27126e
JB		 12832}
12833
0a9ab303 12834static int __intel_set_mode_setup_plls(struct drm_atomic_state *state)
ed6739ef 12835{
225da59b 12836 struct drm_device *dev = state->dev;
ed6739ef 12837 struct drm_i915_private *dev_priv = to_i915(dev);
0a9ab303 12838 unsigned clear_pipes = 0;
ed6739ef 12839 struct intel_crtc *intel_crtc;
0a9ab303
ACO		 12840 struct intel_crtc_state *intel_crtc_state;
12841 struct drm_crtc *crtc;
12842 struct drm_crtc_state *crtc_state;
ed6739ef 12843 int ret = 0;
0a9ab303 12844 int i;
ed6739ef
ACO		 12845
12846 if (!dev_priv->display.crtc_compute_clock)
12847 return 0;
12848
0a9ab303
ACO		 12849 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12850 intel_crtc = to_intel_crtc(crtc);
4978cc93 12851 intel_crtc_state = to_intel_crtc_state(crtc_state);
0a9ab303 12852
4978cc93 12853 if (needs_modeset(crtc_state)) {
0a9ab303 12854 clear_pipes |= 1 << intel_crtc->pipe;
4978cc93 12855 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
4978cc93 12856 }
0a9ab303
ACO		 12857 }
12858
ed6739ef
ACO		 12859 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
12860 if (ret)
12861 goto done;
12862
0a9ab303
ACO		 12863 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12864 if (!needs_modeset(crtc_state) || !crtc_state->enable)
225da59b
ACO		 12865 continue;
12866
0a9ab303
ACO		 12867 intel_crtc = to_intel_crtc(crtc);
12868 intel_crtc_state = to_intel_crtc_state(crtc_state);
12869
ed6739ef 12870 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
0a9ab303 12871 intel_crtc_state);
ed6739ef
ACO		 12872 if (ret) {
12873 intel_shared_dpll_abort_config(dev_priv);
12874 goto done;
12875 }
12876 }
12877
12878done:
12879 return ret;
12880}
12881
054518dd
ACO		 12882/* Code that should eventually be part of atomic_check() */
12883static int __intel_set_mode_checks(struct drm_atomic_state *state)
12884{
12885 struct drm_device *dev = state->dev;
12886 int ret;
12887
12888 /*
12889 * See if the config requires any additional preparation, e.g.
12890 * to adjust global state with pipes off. We need to do this
12891 * here so we can get the modeset_pipe updated config for the new
12892 * mode set on this crtc. For other crtcs we need to use the
12893 * adjusted_mode bits in the crtc directly.
12894 */
b432e5cf
VS		 12895 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev) || IS_BROADWELL(dev)) {
12896 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev))
12897 ret = valleyview_modeset_global_pipes(state);
12898 else
12899 ret = broadwell_modeset_global_pipes(state);
12900
054518dd
ACO		 12901 if (ret)
12902 return ret;
12903 }
12904
12905 ret = __intel_set_mode_setup_plls(state);
12906 if (ret)
12907 return ret;
12908
12909 return 0;
12910}
12911
0a9ab303 12912static int __intel_set_mode(struct drm_crtc *modeset_crtc,
0a9ab303 12913 struct intel_crtc_state *pipe_config)
a6778b3c 12914{
0a9ab303 12915 struct drm_device *dev = modeset_crtc->dev;
fbee40df 12916 struct drm_i915_private *dev_priv = dev->dev_private;
304603f4 12917 struct drm_atomic_state *state = pipe_config->base.state;
0a9ab303
ACO		 12918 struct drm_crtc *crtc;
12919 struct drm_crtc_state *crtc_state;
c0c36b94 12920 int ret = 0;
0a9ab303 12921 int i;
a6778b3c 12922
054518dd
ACO		 12923 ret = __intel_set_mode_checks(state);
12924 if (ret < 0)
12925 return ret;
12926
d4afb8cc
ACO		 12927 ret = drm_atomic_helper_prepare_planes(dev, state);
12928 if (ret)
12929 return ret;
12930
0a9ab303
ACO		 12931 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12932 if (!needs_modeset(crtc_state))
12933 continue;
460da916 12934
69024de8
ML		 12935 intel_crtc_disable_planes(crtc);
12936 dev_priv->display.crtc_disable(crtc);
12937 if (!crtc_state->enable)
12938 drm_plane_helper_disable(crtc->primary);
ea9d758d 12939 }
a6778b3c 12940
ea9d758d
DV		 12941 /* Only after disabling all output pipelines that will be changed can we
12942 * update the the output configuration. */
0a9ab303 12943 intel_modeset_update_state(state);
f6e5b160 12944
a821fc46
ACO		 12945 /* The state has been swaped above, so state actually contains the
12946 * old state now. */
12947
304603f4 12948 modeset_update_crtc_power_domains(state);
47fab737 12949
d4afb8cc 12950 drm_atomic_helper_commit_planes(dev, state);
a6778b3c
DV		 12951
12952 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
0a9ab303 12953 for_each_crtc_in_state(state, crtc, crtc_state, i) {
a821fc46 12954 if (!needs_modeset(crtc->state) || !crtc->state->enable)
0a9ab303
ACO		 12955 continue;
12956
12957 update_scanline_offset(to_intel_crtc(crtc));
80715b2f 12958
0a9ab303
ACO		 12959 dev_priv->display.crtc_enable(crtc);
12960 intel_crtc_enable_planes(crtc);
80715b2f 12961 }
a6778b3c 12962
a6778b3c 12963 /* FIXME: add subpixel order */
83a57153 12964
d4afb8cc
ACO		 12965 drm_atomic_helper_cleanup_planes(dev, state);
12966
2bfb4627
ACO		 12967 drm_atomic_state_free(state);
12968
9eb45f22 12969 return 0;
f6e5b160
CW		 12970}
12971
0a9ab303 12972static int intel_set_mode_with_config(struct drm_crtc *crtc,
0a9ab303 12973 struct intel_crtc_state *pipe_config)
f30da187
DV		 12974{
12975 int ret;
12976
8c7b5ccb 12977 ret = __intel_set_mode(crtc, pipe_config);
f30da187
DV		 12978
12979 if (ret == 0)
12980 intel_modeset_check_state(crtc->dev);
12981
12982 return ret;
12983}
12984
7f27126e 12985static int intel_set_mode(struct drm_crtc *crtc,
83a57153 12986 struct drm_atomic_state *state)
7f27126e 12987{
5cec258b 12988 struct intel_crtc_state *pipe_config;
83a57153 12989 int ret = 0;
7f27126e 12990
8c7b5ccb 12991 pipe_config = intel_modeset_compute_config(crtc, state);
83a57153
ACO		 12992 if (IS_ERR(pipe_config)) {
12993 ret = PTR_ERR(pipe_config);
12994 goto out;
12995 }
12996
8c7b5ccb 12997 ret = intel_set_mode_with_config(crtc, pipe_config);
83a57153
ACO		 12998 if (ret)
12999 goto out;
7f27126e 13000
83a57153
ACO		 13001out:
13002 return ret;
7f27126e
JB		 13003}
13004
c0c36b94
CW		 13005void intel_crtc_restore_mode(struct drm_crtc *crtc)
13006{
83a57153
ACO		 13007 struct drm_device *dev = crtc->dev;
13008 struct drm_atomic_state *state;
4be07317 13009 struct intel_crtc *intel_crtc;
83a57153
ACO		 13010 struct intel_encoder *encoder;
13011 struct intel_connector *connector;
13012 struct drm_connector_state *connector_state;
4be07317 13013 struct intel_crtc_state *crtc_state;
2bfb4627 13014 int ret;
83a57153
ACO		 13015
13016 state = drm_atomic_state_alloc(dev);
13017 if (!state) {
13018 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
13019 crtc->base.id);
13020 return;
13021 }
13022
13023 state->acquire_ctx = dev->mode_config.acquire_ctx;
13024
13025 /* The force restore path in the HW readout code relies on the staged
13026 * config still keeping the user requested config while the actual
13027 * state has been overwritten by the configuration read from HW. We
13028 * need to copy the staged config to the atomic state, otherwise the
13029 * mode set will just reapply the state the HW is already in. */
13030 for_each_intel_encoder(dev, encoder) {
13031 if (&encoder->new_crtc->base != crtc)
13032 continue;
13033
13034 for_each_intel_connector(dev, connector) {
13035 if (connector->new_encoder != encoder)
13036 continue;
13037
13038 connector_state = drm_atomic_get_connector_state(state, &connector->base);
13039 if (IS_ERR(connector_state)) {
13040 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
13041 connector->base.base.id,
13042 connector->base.name,
13043 PTR_ERR(connector_state));
13044 continue;
13045 }
13046
13047 connector_state->crtc = crtc;
13048 connector_state->best_encoder = &encoder->base;
13049 }
13050 }
13051
4be07317
ACO		 13052 for_each_intel_crtc(dev, intel_crtc) {
13053 if (intel_crtc->new_enabled == intel_crtc->base.enabled)
13054 continue;
13055
13056 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
13057 if (IS_ERR(crtc_state)) {
13058 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
13059 intel_crtc->base.base.id,
13060 PTR_ERR(crtc_state));
13061 continue;
13062 }
13063
49d6fa21
ML		 13064 crtc_state->base.active = crtc_state->base.enable =
13065 intel_crtc->new_enabled;
8c7b5ccb
ACO		 13066
13067 if (&intel_crtc->base == crtc)
13068 drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
4be07317
ACO		 13069 }
13070
d3a40d1b
ACO		 13071 intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
13072 crtc->primary->fb, crtc->x, crtc->y);
13073
2bfb4627
ACO		 13074 ret = intel_set_mode(crtc, state);
13075 if (ret)
13076 drm_atomic_state_free(state);
c0c36b94
CW		 13077}
13078
25c5b266
DV		 13079#undef for_each_intel_crtc_masked
13080
b7885264
ACO		 13081static bool intel_connector_in_mode_set(struct intel_connector *connector,
13082 struct drm_mode_set *set)
13083{
13084 int ro;
13085
13086 for (ro = 0; ro < set->num_connectors; ro++)
13087 if (set->connectors[ro] == &connector->base)
13088 return true;
13089
13090 return false;
13091}
13092
2e431051 13093static int
9a935856
DV		 13094intel_modeset_stage_output_state(struct drm_device *dev,
13095 struct drm_mode_set *set,
944b0c76 13096 struct drm_atomic_state *state)
50f56119 13097{
9a935856 13098 struct intel_connector *connector;
d5432a9d 13099 struct drm_connector *drm_connector;
944b0c76 13100 struct drm_connector_state *connector_state;
d5432a9d
ACO		 13101 struct drm_crtc *crtc;
13102 struct drm_crtc_state *crtc_state;
13103 int i, ret;
50f56119 13104
9abdda74 13105 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 13106 * of connectors. For paranoia, double-check this. */
13107 WARN_ON(!set->fb && (set->num_connectors != 0));
13108 WARN_ON(set->fb && (set->num_connectors == 0));
13109
3a3371ff 13110 for_each_intel_connector(dev, connector) {
b7885264
ACO		 13111 bool in_mode_set = intel_connector_in_mode_set(connector, set);
13112
d5432a9d
ACO		 13113 if (!in_mode_set && connector->base.state->crtc != set->crtc)
13114 continue;
13115
13116 connector_state =
13117 drm_atomic_get_connector_state(state, &connector->base);
13118 if (IS_ERR(connector_state))
13119 return PTR_ERR(connector_state);
13120
b7885264
ACO		 13121 if (in_mode_set) {
13122 int pipe = to_intel_crtc(set->crtc)->pipe;
d5432a9d
ACO		 13123 connector_state->best_encoder =
13124 &intel_find_encoder(connector, pipe)->base;
50f56119
DV		 13125 }
13126
d5432a9d 13127 if (connector->base.state->crtc != set->crtc)
b7885264
ACO		 13128 continue;
13129
9a935856
DV		 13130 /* If we disable the crtc, disable all its connectors. Also, if
13131 * the connector is on the changing crtc but not on the new
13132 * connector list, disable it. */
b7885264 13133 if (!set->fb || !in_mode_set) {
d5432a9d 13134 connector_state->best_encoder = NULL;
9a935856
DV		 13135
13136 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
13137 connector->base.base.id,
c23cc417 13138 connector->base.name);
9a935856 13139 }
50f56119 13140 }
9a935856 13141 /* connector->new_encoder is now updated for all connectors. */
50f56119 13142
d5432a9d
ACO		 13143 for_each_connector_in_state(state, drm_connector, connector_state, i) {
13144 connector = to_intel_connector(drm_connector);
13145
13146 if (!connector_state->best_encoder) {
13147 ret = drm_atomic_set_crtc_for_connector(connector_state,
13148 NULL);
13149 if (ret)
13150 return ret;
7668851f 13151
50f56119 13152 continue;
d5432a9d 13153 }
50f56119 13154
d5432a9d
ACO		 13155 if (intel_connector_in_mode_set(connector, set)) {
13156 struct drm_crtc *crtc = connector->base.state->crtc;
13157
13158 /* If this connector was in a previous crtc, add it
13159 * to the state. We might need to disable it. */
13160 if (crtc) {
13161 crtc_state =
13162 drm_atomic_get_crtc_state(state, crtc);
13163 if (IS_ERR(crtc_state))
13164 return PTR_ERR(crtc_state);
13165 }
13166
13167 ret = drm_atomic_set_crtc_for_connector(connector_state,
13168 set->crtc);
13169 if (ret)
13170 return ret;
13171 }
50f56119
DV		 13172
13173 /* Make sure the new CRTC will work with the encoder */
d5432a9d
ACO		 13174 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
13175 connector_state->crtc)) {
5e2b584e 13176 return -EINVAL;
50f56119 13177 }
944b0c76 13178
9a935856
DV		 13179 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
13180 connector->base.base.id,
c23cc417 13181 connector->base.name,
d5432a9d 13182 connector_state->crtc->base.id);
944b0c76 13183
d5432a9d
ACO		 13184 if (connector_state->best_encoder != &connector->encoder->base)
13185 connector->encoder =
13186 to_intel_encoder(connector_state->best_encoder);
0e32b39c 13187 }
7668851f 13188
d5432a9d 13189 for_each_crtc_in_state(state, crtc, crtc_state, i) {
49d6fa21
ML		 13190 bool has_connectors;
13191
d5432a9d
ACO		 13192 ret = drm_atomic_add_affected_connectors(state, crtc);
13193 if (ret)
13194 return ret;
4be07317 13195
49d6fa21
ML		 13196 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
13197 if (has_connectors != crtc_state->enable)
13198 crtc_state->enable =
13199 crtc_state->active = has_connectors;
7668851f
VS		 13200 }
13201
8c7b5ccb
ACO		 13202 ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
13203 set->fb, set->x, set->y);
13204 if (ret)
13205 return ret;
13206
13207 crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
13208 if (IS_ERR(crtc_state))
13209 return PTR_ERR(crtc_state);
13210
13211 if (set->mode)
13212 drm_mode_copy(&crtc_state->mode, set->mode);
13213
13214 if (set->num_connectors)
13215 crtc_state->active = true;
13216
2e431051
DV		 13217 return 0;
13218}
13219
bb546623
ACO		 13220static bool primary_plane_visible(struct drm_crtc *crtc)
13221{
13222 struct intel_plane_state *plane_state =
13223 to_intel_plane_state(crtc->primary->state);
13224
13225 return plane_state->visible;
13226}
13227
2e431051
DV		 13228static int intel_crtc_set_config(struct drm_mode_set *set)
13229{
13230 struct drm_device *dev;
83a57153 13231 struct drm_atomic_state *state = NULL;
5cec258b 13232 struct intel_crtc_state *pipe_config;
bb546623 13233 bool primary_plane_was_visible;
2e431051 13234 int ret;
2e431051 13235
8d3e375e
DV		 13236 BUG_ON(!set);
13237 BUG_ON(!set->crtc);
13238 BUG_ON(!set->crtc->helper_private);
2e431051 13239
7e53f3a4
DV		 13240 /* Enforce sane interface api - has been abused by the fb helper. */
13241 BUG_ON(!set->mode && set->fb);
13242 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 13243
2e431051
DV		 13244 if (set->fb) {
13245 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
13246 set->crtc->base.id, set->fb->base.id,
13247 (int)set->num_connectors, set->x, set->y);
13248 } else {
13249 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 13250 }
13251
13252 dev = set->crtc->dev;
13253
83a57153 13254 state = drm_atomic_state_alloc(dev);
7cbf41d6
ACO		 13255 if (!state)
13256 return -ENOMEM;
83a57153
ACO		 13257
13258 state->acquire_ctx = dev->mode_config.acquire_ctx;
13259
462a425a 13260 ret = intel_modeset_stage_output_state(dev, set, state);
2e431051 13261 if (ret)
7cbf41d6 13262 goto out;
2e431051 13263
8c7b5ccb 13264 pipe_config = intel_modeset_compute_config(set->crtc, state);
20664591 13265 if (IS_ERR(pipe_config)) {
6ac0483b 13266 ret = PTR_ERR(pipe_config);
7cbf41d6 13267 goto out;
20664591 13268 }
50f52756 13269
1f9954d0
JB		 13270 intel_update_pipe_size(to_intel_crtc(set->crtc));
13271
bb546623
ACO		 13272 primary_plane_was_visible = primary_plane_visible(set->crtc);
13273
8c7b5ccb 13274 ret = intel_set_mode_with_config(set->crtc, pipe_config);
bb546623
ACO		 13275
13276 if (ret == 0 &&
13277 pipe_config->base.enable &&
13278 pipe_config->base.planes_changed &&
13279 !needs_modeset(&pipe_config->base)) {
3b150f08 13280 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
3b150f08
MR		 13281
13282 /*
13283 * We need to make sure the primary plane is re-enabled if it
13284 * has previously been turned off.
13285 */
bb546623
ACO		 13286 if (ret == 0 && !primary_plane_was_visible &&
13287 primary_plane_visible(set->crtc)) {
3b150f08 13288 WARN_ON(!intel_crtc->active);
87d4300a 13289 intel_post_enable_primary(set->crtc);
3b150f08
MR		 13290 }
13291
7ca51a3a
JB		 13292 /*
13293 * In the fastboot case this may be our only check of the
13294 * state after boot. It would be better to only do it on
13295 * the first update, but we don't have a nice way of doing that
13296 * (and really, set_config isn't used much for high freq page
13297 * flipping, so increasing its cost here shouldn't be a big
13298 * deal).
13299 */
d330a953 13300 if (i915.fastboot && ret == 0)
7ca51a3a 13301 intel_modeset_check_state(set->crtc->dev);
50f56119
DV		 13302 }
13303
2d05eae1 13304 if (ret) {
bf67dfeb
DV		 13305 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
13306 set->crtc->base.id, ret);
2d05eae1 13307 }
50f56119 13308
7cbf41d6 13309out:
2bfb4627
ACO		 13310 if (ret)
13311 drm_atomic_state_free(state);
50f56119
DV		 13312 return ret;
13313}
f6e5b160
CW		 13314
13315static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 13316 .gamma_set = intel_crtc_gamma_set,
50f56119 13317 .set_config = intel_crtc_set_config,
f6e5b160
CW		 13318 .destroy = intel_crtc_destroy,
13319 .page_flip = intel_crtc_page_flip,
1356837e
MR		 13320 .atomic_duplicate_state = intel_crtc_duplicate_state,
13321 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 13322};
13323
5358901f
DV		 13324static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13325 struct intel_shared_dpll *pll,
13326 struct intel_dpll_hw_state *hw_state)
ee7b9f93 13327{
5358901f 13328 uint32_t val;
ee7b9f93 13329
f458ebbc 13330 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 13331 return false;
13332
5358901f 13333 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 13334 hw_state->dpll = val;
13335 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13336 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 13337
13338 return val & DPLL_VCO_ENABLE;
13339}
13340
15bdd4cf
DV		 13341static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13342 struct intel_shared_dpll *pll)
13343{
3e369b76
ACO		 13344 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13345 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 13346}
13347
e7b903d2
DV		 13348static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13349 struct intel_shared_dpll *pll)
13350{
e7b903d2 13351 /* PCH refclock must be enabled first */
89eff4be 13352 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 13353
3e369b76 13354 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 13355
13356 /* Wait for the clocks to stabilize. */
13357 POSTING_READ(PCH_DPLL(pll->id));
13358 udelay(150);
13359
13360 /* The pixel multiplier can only be updated once the
13361 * DPLL is enabled and the clocks are stable.
13362 *
13363 * So write it again.
13364 */
3e369b76 13365 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 13366 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13367 udelay(200);
13368}
13369
13370static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13371 struct intel_shared_dpll *pll)
13372{
13373 struct drm_device *dev = dev_priv->dev;
13374 struct intel_crtc *crtc;
e7b903d2
DV		 13375
13376 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 13377 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 13378 if (intel_crtc_to_shared_dpll(crtc) == pll)
13379 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 13380 }
13381
15bdd4cf
DV		 13382 I915_WRITE(PCH_DPLL(pll->id), 0);
13383 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13384 udelay(200);
13385}
13386
46edb027
DV		 13387static char *ibx_pch_dpll_names[] = {
13388 "PCH DPLL A",
13389 "PCH DPLL B",
13390};
13391
7c74ade1 13392static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 13393{
e7b903d2 13394 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 13395 int i;
13396
7c74ade1 13397 dev_priv->num_shared_dpll = 2;
ee7b9f93 13398
e72f9fbf 13399 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 13400 dev_priv->shared_dplls[i].id = i;
13401 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 13402 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 13403 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13404 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 13405 dev_priv->shared_dplls[i].get_hw_state =
13406 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 13407 }
13408}
13409
7c74ade1
DV		 13410static void intel_shared_dpll_init(struct drm_device *dev)
13411{
e7b903d2 13412 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 13413
b6283055
VS		 13414 intel_update_cdclk(dev);
13415
9cd86933
DV		 13416 if (HAS_DDI(dev))
13417 intel_ddi_pll_init(dev);
13418 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 13419 ibx_pch_dpll_init(dev);
13420 else
13421 dev_priv->num_shared_dpll = 0;
13422
13423 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 13424}
13425
1fc0a8f7
TU		 13426/**
13427 * intel_wm_need_update - Check whether watermarks need updating
13428 * @plane: drm plane
13429 * @state: new plane state
13430 *
13431 * Check current plane state versus the new one to determine whether
13432 * watermarks need to be recalculated.
13433 *
13434 * Returns true or false.
13435 */
13436bool intel_wm_need_update(struct drm_plane *plane,
13437 struct drm_plane_state *state)
13438{
13439 /* Update watermarks on tiling changes. */
13440 if (!plane->state->fb || !state->fb ||
13441 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
13442 plane->state->rotation != state->rotation)
13443 return true;
13444
13445 return false;
13446}
13447
6beb8c23
MR		 13448/**
13449 * intel_prepare_plane_fb - Prepare fb for usage on plane
13450 * @plane: drm plane to prepare for
13451 * @fb: framebuffer to prepare for presentation
13452 *
13453 * Prepares a framebuffer for usage on a display plane. Generally this
13454 * involves pinning the underlying object and updating the frontbuffer tracking
13455 * bits. Some older platforms need special physical address handling for
13456 * cursor planes.
13457 *
13458 * Returns 0 on success, negative error code on failure.
13459 */
13460int
13461intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13462 struct drm_framebuffer *fb,
13463 const struct drm_plane_state *new_state)
465c120c
MR		 13464{
13465 struct drm_device *dev = plane->dev;
6beb8c23
MR		 13466 struct intel_plane *intel_plane = to_intel_plane(plane);
13467 enum pipe pipe = intel_plane->pipe;
13468 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13469 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13470 unsigned frontbuffer_bits = 0;
13471 int ret = 0;
465c120c 13472
ea2c67bb 13473 if (!obj)
465c120c
MR		 13474 return 0;
13475
6beb8c23
MR		 13476 switch (plane->type) {
13477 case DRM_PLANE_TYPE_PRIMARY:
13478 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
13479 break;
13480 case DRM_PLANE_TYPE_CURSOR:
13481 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
13482 break;
13483 case DRM_PLANE_TYPE_OVERLAY:
13484 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
13485 break;
13486 }
465c120c 13487
6beb8c23 13488 mutex_lock(&dev->struct_mutex);
465c120c 13489
6beb8c23
MR		 13490 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13491 INTEL_INFO(dev)->cursor_needs_physical) {
13492 int align = IS_I830(dev) ? 16 * 1024 : 256;
13493 ret = i915_gem_object_attach_phys(obj, align);
13494 if (ret)
13495 DRM_DEBUG_KMS("failed to attach phys object\n");
13496 } else {
82bc3b2d 13497 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
6beb8c23 13498 }
465c120c 13499
6beb8c23
MR		 13500 if (ret == 0)
13501 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
fdd508a6 13502
4c34574f 13503 mutex_unlock(&dev->struct_mutex);
465c120c 13504
6beb8c23
MR		 13505 return ret;
13506}
13507
38f3ce3a
MR		 13508/**
13509 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13510 * @plane: drm plane to clean up for
13511 * @fb: old framebuffer that was on plane
13512 *
13513 * Cleans up a framebuffer that has just been removed from a plane.
13514 */
13515void
13516intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13517 struct drm_framebuffer *fb,
13518 const struct drm_plane_state *old_state)
38f3ce3a
MR		 13519{
13520 struct drm_device *dev = plane->dev;
13521 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13522
13523 if (WARN_ON(!obj))
13524 return;
13525
13526 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13527 !INTEL_INFO(dev)->cursor_needs_physical) {
13528 mutex_lock(&dev->struct_mutex);
82bc3b2d 13529 intel_unpin_fb_obj(fb, old_state);
38f3ce3a
MR		 13530 mutex_unlock(&dev->struct_mutex);
13531 }
465c120c
MR		 13532}
13533
6156a456
CK		 13534int
13535skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13536{
13537 int max_scale;
13538 struct drm_device *dev;
13539 struct drm_i915_private *dev_priv;
13540 int crtc_clock, cdclk;
13541
13542 if (!intel_crtc || !crtc_state)
13543 return DRM_PLANE_HELPER_NO_SCALING;
13544
13545 dev = intel_crtc->base.dev;
13546 dev_priv = dev->dev_private;
13547 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13548 cdclk = dev_priv->display.get_display_clock_speed(dev);
13549
13550 if (!crtc_clock || !cdclk)
13551 return DRM_PLANE_HELPER_NO_SCALING;
13552
13553 /*
13554 * skl max scale is lower of:
13555 * close to 3 but not 3, -1 is for that purpose
13556 * or
13557 * cdclk/crtc_clock
13558 */
13559 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13560
13561 return max_scale;
13562}
13563
465c120c 13564static int
3c692a41
GP		 13565intel_check_primary_plane(struct drm_plane *plane,
13566 struct intel_plane_state *state)
13567{
32b7eeec
MR		 13568 struct drm_device *dev = plane->dev;
13569 struct drm_i915_private *dev_priv = dev->dev_private;
2b875c22 13570 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 13571 struct intel_crtc *intel_crtc;
6156a456 13572 struct intel_crtc_state *crtc_state;
2b875c22 13573 struct drm_framebuffer *fb = state->base.fb;
3c692a41
GP		 13574 struct drm_rect *dest = &state->dst;
13575 struct drm_rect *src = &state->src;
13576 const struct drm_rect *clip = &state->clip;
d8106366 13577 bool can_position = false;
6156a456
CK		 13578 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13579 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
465c120c
MR		 13580 int ret;
13581
ea2c67bb
MR		 13582 crtc = crtc ? crtc : plane->crtc;
13583 intel_crtc = to_intel_crtc(crtc);
6156a456
CK		 13584 crtc_state = state->base.state ?
13585 intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL;
ea2c67bb 13586
6156a456 13587 if (INTEL_INFO(dev)->gen >= 9) {
225c228a
CK		 13588 /* use scaler when colorkey is not required */
13589 if (to_intel_plane(plane)->ckey.flags == I915_SET_COLORKEY_NONE) {
13590 min_scale = 1;
13591 max_scale = skl_max_scale(intel_crtc, crtc_state);
13592 }
d8106366 13593 can_position = true;
6156a456 13594 }
d8106366 13595
c59cb179
MR		 13596 ret = drm_plane_helper_check_update(plane, crtc, fb,
13597 src, dest, clip,
6156a456
CK		 13598 min_scale,
13599 max_scale,
d8106366
SJ		 13600 can_position, true,
13601 &state->visible);
c59cb179
MR		 13602 if (ret)
13603 return ret;
465c120c 13604
32b7eeec 13605 if (intel_crtc->active) {
b70709a6
ML		 13606 struct intel_plane_state *old_state =
13607 to_intel_plane_state(plane->state);
13608
32b7eeec
MR		 13609 intel_crtc->atomic.wait_for_flips = true;
13610
13611 /*
13612 * FBC does not work on some platforms for rotated
13613 * planes, so disable it when rotation is not 0 and
13614 * update it when rotation is set back to 0.
13615 *
13616 * FIXME: This is redundant with the fbc update done in
13617 * the primary plane enable function except that that
13618 * one is done too late. We eventually need to unify
13619 * this.
13620 */
b70709a6 13621 if (state->visible &&
32b7eeec 13622 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
e35fef21 13623 dev_priv->fbc.crtc == intel_crtc &&
8e7d688b 13624 state->base.rotation != BIT(DRM_ROTATE_0)) {
32b7eeec
MR		 13625 intel_crtc->atomic.disable_fbc = true;
13626 }
13627
b70709a6 13628 if (state->visible && !old_state->visible) {
32b7eeec
MR		 13629 /*
13630 * BDW signals flip done immediately if the plane
13631 * is disabled, even if the plane enable is already
13632 * armed to occur at the next vblank :(
13633 */
b70709a6 13634 if (IS_BROADWELL(dev))
32b7eeec
MR		 13635 intel_crtc->atomic.wait_vblank = true;
13636 }
13637
13638 intel_crtc->atomic.fb_bits |=
13639 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
13640
13641 intel_crtc->atomic.update_fbc = true;
0fda6568 13642
1fc0a8f7 13643 if (intel_wm_need_update(plane, &state->base))
0fda6568 13644 intel_crtc->atomic.update_wm = true;
ccc759dc
GP		 13645 }
13646
6156a456
CK		 13647 if (INTEL_INFO(dev)->gen >= 9) {
13648 ret = skl_update_scaler_users(intel_crtc, crtc_state,
13649 to_intel_plane(plane), state, 0);
13650 if (ret)
13651 return ret;
13652 }
13653
14af293f
GP		 13654 return 0;
13655}
13656
13657static void
13658intel_commit_primary_plane(struct drm_plane *plane,
13659 struct intel_plane_state *state)
13660{
2b875c22
MR		 13661 struct drm_crtc *crtc = state->base.crtc;
13662 struct drm_framebuffer *fb = state->base.fb;
13663 struct drm_device *dev = plane->dev;
14af293f 13664 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 13665 struct intel_crtc *intel_crtc;
14af293f
GP		 13666 struct drm_rect *src = &state->src;
13667
ea2c67bb
MR		 13668 crtc = crtc ? crtc : plane->crtc;
13669 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR		 13670
13671 plane->fb = fb;
9dc806fc
MR		 13672 crtc->x = src->x1 >> 16;
13673 crtc->y = src->y1 >> 16;
ccc759dc 13674
ccc759dc 13675 if (intel_crtc->active) {
27321ae8 13676 if (state->visible)
ccc759dc
GP		 13677 /* FIXME: kill this fastboot hack */
13678 intel_update_pipe_size(intel_crtc);
465c120c 13679
27321ae8
ML		 13680 dev_priv->display.update_primary_plane(crtc, plane->fb,
13681 crtc->x, crtc->y);
ccc759dc 13682 }
465c120c
MR		 13683}
13684
a8ad0d8e
ML		 13685static void
13686intel_disable_primary_plane(struct drm_plane *plane,
13687 struct drm_crtc *crtc,
13688 bool force)
13689{
13690 struct drm_device *dev = plane->dev;
13691 struct drm_i915_private *dev_priv = dev->dev_private;
13692
a8ad0d8e
ML		 13693 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13694}
13695
32b7eeec 13696static void intel_begin_crtc_commit(struct drm_crtc *crtc)
3c692a41 13697{
32b7eeec 13698 struct drm_device *dev = crtc->dev;
140fd38d 13699 struct drm_i915_private *dev_priv = dev->dev_private;
3c692a41 13700 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ea2c67bb
MR		 13701 struct intel_plane *intel_plane;
13702 struct drm_plane *p;
13703 unsigned fb_bits = 0;
13704
13705 /* Track fb's for any planes being disabled */
13706 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
13707 intel_plane = to_intel_plane(p);
13708
13709 if (intel_crtc->atomic.disabled_planes &
13710 (1 << drm_plane_index(p))) {
13711 switch (p->type) {
13712 case DRM_PLANE_TYPE_PRIMARY:
13713 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
13714 break;
13715 case DRM_PLANE_TYPE_CURSOR:
13716 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
13717 break;
13718 case DRM_PLANE_TYPE_OVERLAY:
13719 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
13720 break;
13721 }
3c692a41 13722
ea2c67bb
MR		 13723 mutex_lock(&dev->struct_mutex);
13724 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
13725 mutex_unlock(&dev->struct_mutex);
13726 }
13727 }
3c692a41 13728
32b7eeec
MR		 13729 if (intel_crtc->atomic.wait_for_flips)
13730 intel_crtc_wait_for_pending_flips(crtc);
3c692a41 13731
32b7eeec
MR		 13732 if (intel_crtc->atomic.disable_fbc)
13733 intel_fbc_disable(dev);
3c692a41 13734
32b7eeec
MR		 13735 if (intel_crtc->atomic.pre_disable_primary)
13736 intel_pre_disable_primary(crtc);
3c692a41 13737
32b7eeec
MR		 13738 if (intel_crtc->atomic.update_wm)
13739 intel_update_watermarks(crtc);
3c692a41 13740
32b7eeec 13741 intel_runtime_pm_get(dev_priv);
3c692a41 13742
c34c9ee4
MR		 13743 /* Perform vblank evasion around commit operation */
13744 if (intel_crtc->active)
13745 intel_crtc->atomic.evade =
13746 intel_pipe_update_start(intel_crtc,
13747 &intel_crtc->atomic.start_vbl_count);
32b7eeec
MR		 13748}
13749
13750static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13751{
13752 struct drm_device *dev = crtc->dev;
13753 struct drm_i915_private *dev_priv = dev->dev_private;
13754 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13755 struct drm_plane *p;
13756
c34c9ee4
MR		 13757 if (intel_crtc->atomic.evade)
13758 intel_pipe_update_end(intel_crtc,
13759 intel_crtc->atomic.start_vbl_count);
3c692a41 13760
140fd38d 13761 intel_runtime_pm_put(dev_priv);
3c692a41 13762
32b7eeec
MR		 13763 if (intel_crtc->atomic.wait_vblank)
13764 intel_wait_for_vblank(dev, intel_crtc->pipe);
13765
13766 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
13767
13768 if (intel_crtc->atomic.update_fbc) {
ccc759dc 13769 mutex_lock(&dev->struct_mutex);
7ff0ebcc 13770 intel_fbc_update(dev);
ccc759dc 13771 mutex_unlock(&dev->struct_mutex);
38f3ce3a 13772 }
3c692a41 13773
32b7eeec
MR		 13774 if (intel_crtc->atomic.post_enable_primary)
13775 intel_post_enable_primary(crtc);
3c692a41 13776
32b7eeec
MR		 13777 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
13778 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
13779 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
13780 false, false);
13781
13782 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
3c692a41
GP		 13783}
13784
cf4c7c12 13785/**
4a3b8769
MR		 13786 * intel_plane_destroy - destroy a plane
13787 * @plane: plane to destroy
cf4c7c12 13788 *
4a3b8769
MR		 13789 * Common destruction function for all types of planes (primary, cursor,
13790 * sprite).
cf4c7c12 13791 */
4a3b8769 13792void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 13793{
13794 struct intel_plane *intel_plane = to_intel_plane(plane);
13795 drm_plane_cleanup(plane);
13796 kfree(intel_plane);
13797}
13798
65a3fea0 13799const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR		 13800 .update_plane = drm_atomic_helper_update_plane,
13801 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13802 .destroy = intel_plane_destroy,
c196e1d6 13803 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 13804 .atomic_get_property = intel_plane_atomic_get_property,
13805 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 13806 .atomic_duplicate_state = intel_plane_duplicate_state,
13807 .atomic_destroy_state = intel_plane_destroy_state,
13808
465c120c
MR		 13809};
13810
13811static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13812 int pipe)
13813{
13814 struct intel_plane *primary;
8e7d688b 13815 struct intel_plane_state *state;
465c120c
MR		 13816 const uint32_t *intel_primary_formats;
13817 int num_formats;
13818
13819 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13820 if (primary == NULL)
13821 return NULL;
13822
8e7d688b
MR		 13823 state = intel_create_plane_state(&primary->base);
13824 if (!state) {
ea2c67bb
MR		 13825 kfree(primary);
13826 return NULL;
13827 }
8e7d688b 13828 primary->base.state = &state->base;
ea2c67bb 13829
465c120c
MR		 13830 primary->can_scale = false;
13831 primary->max_downscale = 1;
6156a456
CK		 13832 if (INTEL_INFO(dev)->gen >= 9) {
13833 primary->can_scale = true;
af99ceda 13834 state->scaler_id = -1;
6156a456 13835 }
465c120c
MR		 13836 primary->pipe = pipe;
13837 primary->plane = pipe;
c59cb179
MR		 13838 primary->check_plane = intel_check_primary_plane;
13839 primary->commit_plane = intel_commit_primary_plane;
a8ad0d8e 13840 primary->disable_plane = intel_disable_primary_plane;
08e221fb 13841 primary->ckey.flags = I915_SET_COLORKEY_NONE;
465c120c
MR		 13842 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13843 primary->plane = !pipe;
13844
6c0fd451
DL		 13845 if (INTEL_INFO(dev)->gen >= 9) {
13846 intel_primary_formats = skl_primary_formats;
13847 num_formats = ARRAY_SIZE(skl_primary_formats);
13848 } else if (INTEL_INFO(dev)->gen >= 4) {
568db4f2
DL		 13849 intel_primary_formats = i965_primary_formats;
13850 num_formats = ARRAY_SIZE(i965_primary_formats);
6c0fd451
DL		 13851 } else {
13852 intel_primary_formats = i8xx_primary_formats;
13853 num_formats = ARRAY_SIZE(i8xx_primary_formats);
465c120c
MR		 13854 }
13855
13856 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 13857 &intel_plane_funcs,
465c120c
MR		 13858 intel_primary_formats, num_formats,
13859 DRM_PLANE_TYPE_PRIMARY);
48404c1e 13860
3b7a5119
SJ		 13861 if (INTEL_INFO(dev)->gen >= 4)
13862 intel_create_rotation_property(dev, primary);
48404c1e 13863
ea2c67bb
MR		 13864 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13865
465c120c
MR		 13866 return &primary->base;
13867}
13868
3b7a5119
SJ		 13869void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13870{
13871 if (!dev->mode_config.rotation_property) {
13872 unsigned long flags = BIT(DRM_ROTATE_0) |
13873 BIT(DRM_ROTATE_180);
13874
13875 if (INTEL_INFO(dev)->gen >= 9)
13876 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13877
13878 dev->mode_config.rotation_property =
13879 drm_mode_create_rotation_property(dev, flags);
13880 }
13881 if (dev->mode_config.rotation_property)
13882 drm_object_attach_property(&plane->base.base,
13883 dev->mode_config.rotation_property,
13884 plane->base.state->rotation);
13885}
13886
3d7d6510 13887static int
852e787c
GP		 13888intel_check_cursor_plane(struct drm_plane *plane,
13889 struct intel_plane_state *state)
3d7d6510 13890{
2b875c22 13891 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 13892 struct drm_device *dev = plane->dev;
2b875c22 13893 struct drm_framebuffer *fb = state->base.fb;
852e787c
GP		 13894 struct drm_rect *dest = &state->dst;
13895 struct drm_rect *src = &state->src;
13896 const struct drm_rect *clip = &state->clip;
757f9a3e 13897 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
ea2c67bb 13898 struct intel_crtc *intel_crtc;
757f9a3e
GP		 13899 unsigned stride;
13900 int ret;
3d7d6510 13901
ea2c67bb
MR		 13902 crtc = crtc ? crtc : plane->crtc;
13903 intel_crtc = to_intel_crtc(crtc);
13904
757f9a3e 13905 ret = drm_plane_helper_check_update(plane, crtc, fb,
852e787c 13906 src, dest, clip,
3d7d6510
MR		 13907 DRM_PLANE_HELPER_NO_SCALING,
13908 DRM_PLANE_HELPER_NO_SCALING,
852e787c 13909 true, true, &state->visible);
757f9a3e
GP		 13910 if (ret)
13911 return ret;
13912
13913
13914 /* if we want to turn off the cursor ignore width and height */
13915 if (!obj)
32b7eeec 13916 goto finish;
757f9a3e 13917
757f9a3e 13918 /* Check for which cursor types we support */
ea2c67bb
MR		 13919 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
13920 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13921 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 13922 return -EINVAL;
13923 }
13924
ea2c67bb
MR		 13925 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13926 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 13927 DRM_DEBUG_KMS("buffer is too small\n");
13928 return -ENOMEM;
13929 }
13930
3a656b54 13931 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e
GP		 13932 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13933 ret = -EINVAL;
13934 }
757f9a3e 13935
32b7eeec
MR		 13936finish:
13937 if (intel_crtc->active) {
3749f463 13938 if (plane->state->crtc_w != state->base.crtc_w)
32b7eeec
MR		 13939 intel_crtc->atomic.update_wm = true;
13940
13941 intel_crtc->atomic.fb_bits |=
13942 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
13943 }
13944
757f9a3e 13945 return ret;
852e787c 13946}
3d7d6510 13947
a8ad0d8e
ML		 13948static void
13949intel_disable_cursor_plane(struct drm_plane *plane,
13950 struct drm_crtc *crtc,
13951 bool force)
13952{
13953 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13954
13955 if (!force) {
13956 plane->fb = NULL;
13957 intel_crtc->cursor_bo = NULL;
13958 intel_crtc->cursor_addr = 0;
13959 }
13960
13961 intel_crtc_update_cursor(crtc, false);
13962}
13963
f4a2cf29 13964static void
852e787c
GP		 13965intel_commit_cursor_plane(struct drm_plane *plane,
13966 struct intel_plane_state *state)
13967{
2b875c22 13968 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 13969 struct drm_device *dev = plane->dev;
13970 struct intel_crtc *intel_crtc;
2b875c22 13971 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 13972 uint32_t addr;
852e787c 13973
ea2c67bb
MR		 13974 crtc = crtc ? crtc : plane->crtc;
13975 intel_crtc = to_intel_crtc(crtc);
13976
2b875c22 13977 plane->fb = state->base.fb;
ea2c67bb
MR		 13978 crtc->cursor_x = state->base.crtc_x;
13979 crtc->cursor_y = state->base.crtc_y;
13980
a912f12f
GP		 13981 if (intel_crtc->cursor_bo == obj)
13982 goto update;
4ed91096 13983
f4a2cf29 13984 if (!obj)
a912f12f 13985 addr = 0;
f4a2cf29 13986 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 13987 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 13988 else
a912f12f 13989 addr = obj->phys_handle->busaddr;
852e787c 13990
a912f12f
GP		 13991 intel_crtc->cursor_addr = addr;
13992 intel_crtc->cursor_bo = obj;
13993update:
852e787c 13994
32b7eeec 13995 if (intel_crtc->active)
a912f12f 13996 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 13997}
13998
3d7d6510
MR		 13999static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14000 int pipe)
14001{
14002 struct intel_plane *cursor;
8e7d688b 14003 struct intel_plane_state *state;
3d7d6510
MR		 14004
14005 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14006 if (cursor == NULL)
14007 return NULL;
14008
8e7d688b
MR		 14009 state = intel_create_plane_state(&cursor->base);
14010 if (!state) {
ea2c67bb
MR		 14011 kfree(cursor);
14012 return NULL;
14013 }
8e7d688b 14014 cursor->base.state = &state->base;
ea2c67bb 14015
3d7d6510
MR		 14016 cursor->can_scale = false;
14017 cursor->max_downscale = 1;
14018 cursor->pipe = pipe;
14019 cursor->plane = pipe;
c59cb179
MR		 14020 cursor->check_plane = intel_check_cursor_plane;
14021 cursor->commit_plane = intel_commit_cursor_plane;
a8ad0d8e 14022 cursor->disable_plane = intel_disable_cursor_plane;
3d7d6510
MR		 14023
14024 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 14025 &intel_plane_funcs,
3d7d6510
MR		 14026 intel_cursor_formats,
14027 ARRAY_SIZE(intel_cursor_formats),
14028 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 14029
14030 if (INTEL_INFO(dev)->gen >= 4) {
14031 if (!dev->mode_config.rotation_property)
14032 dev->mode_config.rotation_property =
14033 drm_mode_create_rotation_property(dev,
14034 BIT(DRM_ROTATE_0) |
14035 BIT(DRM_ROTATE_180));
14036 if (dev->mode_config.rotation_property)
14037 drm_object_attach_property(&cursor->base.base,
14038 dev->mode_config.rotation_property,
8e7d688b 14039 state->base.rotation);
4398ad45
VS		 14040 }
14041
af99ceda
CK		 14042 if (INTEL_INFO(dev)->gen >=9)
14043 state->scaler_id = -1;
14044
ea2c67bb
MR		 14045 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14046
3d7d6510
MR		 14047 return &cursor->base;
14048}
14049
549e2bfb
CK		 14050static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14051 struct intel_crtc_state *crtc_state)
14052{
14053 int i;
14054 struct intel_scaler *intel_scaler;
14055 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14056
14057 for (i = 0; i < intel_crtc->num_scalers; i++) {
14058 intel_scaler = &scaler_state->scalers[i];
14059 intel_scaler->in_use = 0;
14060 intel_scaler->id = i;
14061
14062 intel_scaler->mode = PS_SCALER_MODE_DYN;
14063 }
14064
14065 scaler_state->scaler_id = -1;
14066}
14067
b358d0a6 14068static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 14069{
fbee40df 14070 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 14071 struct intel_crtc *intel_crtc;
f5de6e07 14072 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 14073 struct drm_plane *primary = NULL;
14074 struct drm_plane *cursor = NULL;
465c120c 14075 int i, ret;
79e53945 14076
955382f3 14077 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 14078 if (intel_crtc == NULL)
14079 return;
14080
f5de6e07
ACO		 14081 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14082 if (!crtc_state)
14083 goto fail;
550acefd
ACO		 14084 intel_crtc->config = crtc_state;
14085 intel_crtc->base.state = &crtc_state->base;
07878248 14086 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 14087
549e2bfb
CK		 14088 /* initialize shared scalers */
14089 if (INTEL_INFO(dev)->gen >= 9) {
14090 if (pipe == PIPE_C)
14091 intel_crtc->num_scalers = 1;
14092 else
14093 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14094
14095 skl_init_scalers(dev, intel_crtc, crtc_state);
14096 }
14097
465c120c 14098 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 14099 if (!primary)
14100 goto fail;
14101
14102 cursor = intel_cursor_plane_create(dev, pipe);
14103 if (!cursor)
14104 goto fail;
14105
465c120c 14106 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 14107 cursor, &intel_crtc_funcs);
14108 if (ret)
14109 goto fail;
79e53945
JB		 14110
14111 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 14112 for (i = 0; i < 256; i++) {
14113 intel_crtc->lut_r[i] = i;
14114 intel_crtc->lut_g[i] = i;
14115 intel_crtc->lut_b[i] = i;
14116 }
14117
1f1c2e24
VS		 14118 /*
14119 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 14120 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 14121 */
80824003
JB		 14122 intel_crtc->pipe = pipe;
14123 intel_crtc->plane = pipe;
3a77c4c4 14124 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 14125 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 14126 intel_crtc->plane = !pipe;
80824003
JB		 14127 }
14128
4b0e333e
CW		 14129 intel_crtc->cursor_base = ~0;
14130 intel_crtc->cursor_cntl = ~0;
dc41c154 14131 intel_crtc->cursor_size = ~0;
8d7849db 14132
22fd0fab
JB		 14133 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14134 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14135 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14136 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14137
79e53945 14138 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 14139
14140 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 14141 return;
14142
14143fail:
14144 if (primary)
14145 drm_plane_cleanup(primary);
14146 if (cursor)
14147 drm_plane_cleanup(cursor);
f5de6e07 14148 kfree(crtc_state);
3d7d6510 14149 kfree(intel_crtc);
79e53945
JB		 14150}
14151
752aa88a
JB		 14152enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14153{
14154 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 14155 struct drm_device *dev = connector->base.dev;
752aa88a 14156
51fd371b 14157 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 14158
d3babd3f 14159 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 14160 return INVALID_PIPE;
14161
14162 return to_intel_crtc(encoder->crtc)->pipe;
14163}
14164
08d7b3d1 14165int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 14166 struct drm_file *file)
08d7b3d1 14167{
08d7b3d1 14168 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 14169 struct drm_crtc *drmmode_crtc;
c05422d5 14170 struct intel_crtc *crtc;
08d7b3d1 14171
7707e653 14172 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 14173
7707e653 14174 if (!drmmode_crtc) {
08d7b3d1 14175 DRM_ERROR("no such CRTC id\n");
3f2c2057 14176 return -ENOENT;
08d7b3d1
CW		 14177 }
14178
7707e653 14179 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 14180 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 14181
c05422d5 14182 return 0;
08d7b3d1
CW		 14183}
14184
66a9278e 14185static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 14186{
66a9278e
DV		 14187 struct drm_device *dev = encoder->base.dev;
14188 struct intel_encoder *source_encoder;
79e53945 14189 int index_mask = 0;
79e53945
JB		 14190 int entry = 0;
14191
b2784e15 14192 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 14193 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 14194 index_mask |= (1 << entry);
14195
79e53945
JB		 14196 entry++;
14197 }
4ef69c7a 14198
79e53945
JB		 14199 return index_mask;
14200}
14201
4d302442
CW		 14202static bool has_edp_a(struct drm_device *dev)
14203{
14204 struct drm_i915_private *dev_priv = dev->dev_private;
14205
14206 if (!IS_MOBILE(dev))
14207 return false;
14208
14209 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14210 return false;
14211
e3589908 14212 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 14213 return false;
14214
14215 return true;
14216}
14217
84b4e042
JB		 14218static bool intel_crt_present(struct drm_device *dev)
14219{
14220 struct drm_i915_private *dev_priv = dev->dev_private;
14221
884497ed
DL		 14222 if (INTEL_INFO(dev)->gen >= 9)
14223 return false;
14224
cf404ce4 14225 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 14226 return false;
14227
14228 if (IS_CHERRYVIEW(dev))
14229 return false;
14230
14231 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14232 return false;
14233
14234 return true;
14235}
14236
79e53945
JB		 14237static void intel_setup_outputs(struct drm_device *dev)
14238{
725e30ad 14239 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 14240 struct intel_encoder *encoder;
cb0953d7 14241 bool dpd_is_edp = false;
79e53945 14242
c9093354 14243 intel_lvds_init(dev);
79e53945 14244
84b4e042 14245 if (intel_crt_present(dev))
79935fca 14246 intel_crt_init(dev);
cb0953d7 14247
c776eb2e
VK		 14248 if (IS_BROXTON(dev)) {
14249 /*
14250 * FIXME: Broxton doesn't support port detection via the
14251 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14252 * detect the ports.
14253 */
14254 intel_ddi_init(dev, PORT_A);
14255 intel_ddi_init(dev, PORT_B);
14256 intel_ddi_init(dev, PORT_C);
14257 } else if (HAS_DDI(dev)) {
0e72a5b5
ED		 14258 int found;
14259
de31facd
JB		 14260 /*
14261 * Haswell uses DDI functions to detect digital outputs.
14262 * On SKL pre-D0 the strap isn't connected, so we assume
14263 * it's there.
14264 */
0e72a5b5 14265 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
de31facd
JB		 14266 /* WaIgnoreDDIAStrap: skl */
14267 if (found ||
14268 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
0e72a5b5
ED		 14269 intel_ddi_init(dev, PORT_A);
14270
14271 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14272 * register */
14273 found = I915_READ(SFUSE_STRAP);
14274
14275 if (found & SFUSE_STRAP_DDIB_DETECTED)
14276 intel_ddi_init(dev, PORT_B);
14277 if (found & SFUSE_STRAP_DDIC_DETECTED)
14278 intel_ddi_init(dev, PORT_C);
14279 if (found & SFUSE_STRAP_DDID_DETECTED)
14280 intel_ddi_init(dev, PORT_D);
14281 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 14282 int found;
5d8a7752 14283 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 14284
14285 if (has_edp_a(dev))
14286 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 14287
dc0fa718 14288 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 14289 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 14290 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 14291 if (!found)
e2debe91 14292 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 14293 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 14294 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 14295 }
14296
dc0fa718 14297 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 14298 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 14299
dc0fa718 14300 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 14301 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 14302
5eb08b69 14303 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 14304 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 14305
270b3042 14306 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 14307 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 14308 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 14309 /*
14310 * The DP_DETECTED bit is the latched state of the DDC
14311 * SDA pin at boot. However since eDP doesn't require DDC
14312 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14313 * eDP ports may have been muxed to an alternate function.
14314 * Thus we can't rely on the DP_DETECTED bit alone to detect
14315 * eDP ports. Consult the VBT as well as DP_DETECTED to
14316 * detect eDP ports.
14317 */
d2182a66
VS		 14318 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14319 !intel_dp_is_edp(dev, PORT_B))
585a94b8
AB		 14320 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14321 PORT_B);
e17ac6db
VS		 14322 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14323 intel_dp_is_edp(dev, PORT_B))
14324 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
585a94b8 14325
d2182a66
VS		 14326 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14327 !intel_dp_is_edp(dev, PORT_C))
6f6005a5
JB		 14328 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14329 PORT_C);
e17ac6db
VS		 14330 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14331 intel_dp_is_edp(dev, PORT_C))
14332 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 14333
9418c1f1 14334 if (IS_CHERRYVIEW(dev)) {
e17ac6db 14335 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
9418c1f1
VS		 14336 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14337 PORT_D);
e17ac6db
VS		 14338 /* eDP not supported on port D, so don't check VBT */
14339 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14340 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
9418c1f1
VS		 14341 }
14342
3cfca973 14343 intel_dsi_init(dev);
103a196f 14344 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 14345 bool found = false;
7d57382e 14346
e2debe91 14347 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14348 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 14349 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 14350 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
14351 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 14352 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 14353 }
27185ae1 14354
e7281eab 14355 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 14356 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 14357 }
13520b05
KH		 14358
14359 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 14360
e2debe91 14361 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14362 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 14363 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 14364 }
27185ae1 14365
e2debe91 14366 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 14367
b01f2c3a
JB		 14368 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
14369 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 14370 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 14371 }
e7281eab 14372 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 14373 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 14374 }
27185ae1 14375
b01f2c3a 14376 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 14377 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 14378 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 14379 } else if (IS_GEN2(dev))
79e53945
JB		 14380 intel_dvo_init(dev);
14381
103a196f 14382 if (SUPPORTS_TV(dev))
79e53945
JB		 14383 intel_tv_init(dev);
14384
0bc12bcb 14385 intel_psr_init(dev);
7c8f8a70 14386
b2784e15 14387 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 14388 encoder->base.possible_crtcs = encoder->crtc_mask;
14389 encoder->base.possible_clones =
66a9278e 14390 intel_encoder_clones(encoder);
79e53945 14391 }
47356eb6 14392
dde86e2d 14393 intel_init_pch_refclk(dev);
270b3042
DV		 14394
14395 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 14396}
14397
14398static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14399{
60a5ca01 14400 struct drm_device *dev = fb->dev;
79e53945 14401 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 14402
ef2d633e 14403 drm_framebuffer_cleanup(fb);
60a5ca01 14404 mutex_lock(&dev->struct_mutex);
ef2d633e 14405 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 14406 drm_gem_object_unreference(&intel_fb->obj->base);
14407 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 14408 kfree(intel_fb);
14409}
14410
14411static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 14412 struct drm_file *file,
79e53945
JB		 14413 unsigned int *handle)
14414{
14415 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 14416 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 14417
05394f39 14418 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 14419}
14420
14421static const struct drm_framebuffer_funcs intel_fb_funcs = {
14422 .destroy = intel_user_framebuffer_destroy,
14423 .create_handle = intel_user_framebuffer_create_handle,
14424};
14425
b321803d
DL		 14426static
14427u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14428 uint32_t pixel_format)
14429{
14430 u32 gen = INTEL_INFO(dev)->gen;
14431
14432 if (gen >= 9) {
14433 /* "The stride in bytes must not exceed the of the size of 8K
14434 * pixels and 32K bytes."
14435 */
14436 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14437 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14438 return 32*1024;
14439 } else if (gen >= 4) {
14440 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14441 return 16*1024;
14442 else
14443 return 32*1024;
14444 } else if (gen >= 3) {
14445 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14446 return 8*1024;
14447 else
14448 return 16*1024;
14449 } else {
14450 /* XXX DSPC is limited to 4k tiled */
14451 return 8*1024;
14452 }
14453}
14454
b5ea642a
DV		 14455static int intel_framebuffer_init(struct drm_device *dev,
14456 struct intel_framebuffer *intel_fb,
14457 struct drm_mode_fb_cmd2 *mode_cmd,
14458 struct drm_i915_gem_object *obj)
79e53945 14459{
6761dd31 14460 unsigned int aligned_height;
79e53945 14461 int ret;
b321803d 14462 u32 pitch_limit, stride_alignment;
79e53945 14463
dd4916c5
DV		 14464 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14465
2a80eada
DV		 14466 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14467 /* Enforce that fb modifier and tiling mode match, but only for
14468 * X-tiled. This is needed for FBC. */
14469 if (!!(obj->tiling_mode == I915_TILING_X) !=
14470 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14471 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14472 return -EINVAL;
14473 }
14474 } else {
14475 if (obj->tiling_mode == I915_TILING_X)
14476 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14477 else if (obj->tiling_mode == I915_TILING_Y) {
14478 DRM_DEBUG("No Y tiling for legacy addfb\n");
14479 return -EINVAL;
14480 }
14481 }
14482
9a8f0a12
TU		 14483 /* Passed in modifier sanity checking. */
14484 switch (mode_cmd->modifier[0]) {
14485 case I915_FORMAT_MOD_Y_TILED:
14486 case I915_FORMAT_MOD_Yf_TILED:
14487 if (INTEL_INFO(dev)->gen < 9) {
14488 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14489 mode_cmd->modifier[0]);
14490 return -EINVAL;
14491 }
14492 case DRM_FORMAT_MOD_NONE:
14493 case I915_FORMAT_MOD_X_TILED:
14494 break;
14495 default:
c0f40428
JB		 14496 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14497 mode_cmd->modifier[0]);
57cd6508 14498 return -EINVAL;
c16ed4be 14499 }
57cd6508 14500
b321803d
DL		 14501 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14502 mode_cmd->pixel_format);
14503 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14504 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14505 mode_cmd->pitches[0], stride_alignment);
57cd6508 14506 return -EINVAL;
c16ed4be 14507 }
57cd6508 14508
b321803d
DL		 14509 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14510 mode_cmd->pixel_format);
a35cdaa0 14511 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 14512 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14513 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 14514 "tiled" : "linear",
a35cdaa0 14515 mode_cmd->pitches[0], pitch_limit);
5d7bd705 14516 return -EINVAL;
c16ed4be 14517 }
5d7bd705 14518
2a80eada 14519 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 14520 mode_cmd->pitches[0] != obj->stride) {
14521 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14522 mode_cmd->pitches[0], obj->stride);
5d7bd705 14523 return -EINVAL;
c16ed4be 14524 }
5d7bd705 14525
57779d06 14526 /* Reject formats not supported by any plane early. */
308e5bcb 14527 switch (mode_cmd->pixel_format) {
57779d06 14528 case DRM_FORMAT_C8:
04b3924d
VS		 14529 case DRM_FORMAT_RGB565:
14530 case DRM_FORMAT_XRGB8888:
14531 case DRM_FORMAT_ARGB8888:
57779d06
VS		 14532 break;
14533 case DRM_FORMAT_XRGB1555:
c16ed4be 14534 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 14535 DRM_DEBUG("unsupported pixel format: %s\n",
14536 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14537 return -EINVAL;
c16ed4be 14538 }
57779d06 14539 break;
57779d06 14540 case DRM_FORMAT_ABGR8888:
6c0fd451
DL		 14541 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14542 DRM_DEBUG("unsupported pixel format: %s\n",
14543 drm_get_format_name(mode_cmd->pixel_format));
14544 return -EINVAL;
14545 }
14546 break;
14547 case DRM_FORMAT_XBGR8888:
04b3924d 14548 case DRM_FORMAT_XRGB2101010:
57779d06 14549 case DRM_FORMAT_XBGR2101010:
c16ed4be 14550 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 14551 DRM_DEBUG("unsupported pixel format: %s\n",
14552 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14553 return -EINVAL;
c16ed4be 14554 }
b5626747 14555 break;
7531208b
DL		 14556 case DRM_FORMAT_ABGR2101010:
14557 if (!IS_VALLEYVIEW(dev)) {
14558 DRM_DEBUG("unsupported pixel format: %s\n",
14559 drm_get_format_name(mode_cmd->pixel_format));
14560 return -EINVAL;
14561 }
14562 break;
04b3924d
VS		 14563 case DRM_FORMAT_YUYV:
14564 case DRM_FORMAT_UYVY:
14565 case DRM_FORMAT_YVYU:
14566 case DRM_FORMAT_VYUY:
c16ed4be 14567 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 14568 DRM_DEBUG("unsupported pixel format: %s\n",
14569 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14570 return -EINVAL;
c16ed4be 14571 }
57cd6508
CW		 14572 break;
14573 default:
4ee62c76
VS		 14574 DRM_DEBUG("unsupported pixel format: %s\n",
14575 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 14576 return -EINVAL;
14577 }
14578
90f9a336
VS		 14579 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14580 if (mode_cmd->offsets[0] != 0)
14581 return -EINVAL;
14582
ec2c981e 14583 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 14584 mode_cmd->pixel_format,
14585 mode_cmd->modifier[0]);
53155c0a
DV		 14586 /* FIXME drm helper for size checks (especially planar formats)? */
14587 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14588 return -EINVAL;
14589
c7d73f6a
DV		 14590 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14591 intel_fb->obj = obj;
80075d49 14592 intel_fb->obj->framebuffer_references++;
c7d73f6a 14593
79e53945
JB		 14594 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14595 if (ret) {
14596 DRM_ERROR("framebuffer init failed %d\n", ret);
14597 return ret;
14598 }
14599
79e53945
JB		 14600 return 0;
14601}
14602
79e53945
JB		 14603static struct drm_framebuffer *
14604intel_user_framebuffer_create(struct drm_device *dev,
14605 struct drm_file *filp,
308e5bcb 14606 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 14607{
05394f39 14608 struct drm_i915_gem_object *obj;
79e53945 14609
308e5bcb
JB		 14610 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14611 mode_cmd->handles[0]));
c8725226 14612 if (&obj->base == NULL)
cce13ff7 14613 return ERR_PTR(-ENOENT);
79e53945 14614
d2dff872 14615 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 14616}
14617
4520f53a 14618#ifndef CONFIG_DRM_I915_FBDEV
0632fef6 14619static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 14620{
14621}
14622#endif
14623
79e53945 14624static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 14625 .fb_create = intel_user_framebuffer_create,
0632fef6 14626 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 14627 .atomic_check = intel_atomic_check,
14628 .atomic_commit = intel_atomic_commit,
79e53945
JB		 14629};
14630
e70236a8
JB		 14631/* Set up chip specific display functions */
14632static void intel_init_display(struct drm_device *dev)
14633{
14634 struct drm_i915_private *dev_priv = dev->dev_private;
14635
ee9300bb
DV		 14636 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14637 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 14638 else if (IS_CHERRYVIEW(dev))
14639 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 14640 else if (IS_VALLEYVIEW(dev))
14641 dev_priv->display.find_dpll = vlv_find_best_dpll;
14642 else if (IS_PINEVIEW(dev))
14643 dev_priv->display.find_dpll = pnv_find_best_dpll;
14644 else
14645 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14646
bc8d7dff
DL		 14647 if (INTEL_INFO(dev)->gen >= 9) {
14648 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14649 dev_priv->display.get_initial_plane_config =
14650 skylake_get_initial_plane_config;
bc8d7dff
DL		 14651 dev_priv->display.crtc_compute_clock =
14652 haswell_crtc_compute_clock;
14653 dev_priv->display.crtc_enable = haswell_crtc_enable;
14654 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14655 dev_priv->display.update_primary_plane =
14656 skylake_update_primary_plane;
14657 } else if (HAS_DDI(dev)) {
0e8ffe1b 14658 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14659 dev_priv->display.get_initial_plane_config =
14660 ironlake_get_initial_plane_config;
797d0259
ACO		 14661 dev_priv->display.crtc_compute_clock =
14662 haswell_crtc_compute_clock;
4f771f10
PZ		 14663 dev_priv->display.crtc_enable = haswell_crtc_enable;
14664 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14665 dev_priv->display.update_primary_plane =
14666 ironlake_update_primary_plane;
09b4ddf9 14667 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 14668 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 14669 dev_priv->display.get_initial_plane_config =
14670 ironlake_get_initial_plane_config;
3fb37703
ACO		 14671 dev_priv->display.crtc_compute_clock =
14672 ironlake_crtc_compute_clock;
76e5a89c
DV		 14673 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14674 dev_priv->display.crtc_disable = ironlake_crtc_disable;
262ca2b0
MR		 14675 dev_priv->display.update_primary_plane =
14676 ironlake_update_primary_plane;
89b667f8
JB		 14677 } else if (IS_VALLEYVIEW(dev)) {
14678 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14679 dev_priv->display.get_initial_plane_config =
14680 i9xx_get_initial_plane_config;
d6dfee7a 14681 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 14682 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14683 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14684 dev_priv->display.update_primary_plane =
14685 i9xx_update_primary_plane;
f564048e 14686 } else {
0e8ffe1b 14687 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14688 dev_priv->display.get_initial_plane_config =
14689 i9xx_get_initial_plane_config;
d6dfee7a 14690 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 14691 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14692 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14693 dev_priv->display.update_primary_plane =
14694 i9xx_update_primary_plane;
f564048e 14695 }
e70236a8 14696
e70236a8 14697 /* Returns the core display clock speed */
1652d19e
VS		 14698 if (IS_SKYLAKE(dev))
14699 dev_priv->display.get_display_clock_speed =
14700 skylake_get_display_clock_speed;
14701 else if (IS_BROADWELL(dev))
14702 dev_priv->display.get_display_clock_speed =
14703 broadwell_get_display_clock_speed;
14704 else if (IS_HASWELL(dev))
14705 dev_priv->display.get_display_clock_speed =
14706 haswell_get_display_clock_speed;
14707 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB		 14708 dev_priv->display.get_display_clock_speed =
14709 valleyview_get_display_clock_speed;
b37a6434
VS		 14710 else if (IS_GEN5(dev))
14711 dev_priv->display.get_display_clock_speed =
14712 ilk_get_display_clock_speed;
a7c66cd8 14713 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
34edce2f 14714 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
e70236a8
JB		 14715 dev_priv->display.get_display_clock_speed =
14716 i945_get_display_clock_speed;
34edce2f
VS		 14717 else if (IS_GM45(dev))
14718 dev_priv->display.get_display_clock_speed =
14719 gm45_get_display_clock_speed;
14720 else if (IS_CRESTLINE(dev))
14721 dev_priv->display.get_display_clock_speed =
14722 i965gm_get_display_clock_speed;
14723 else if (IS_PINEVIEW(dev))
14724 dev_priv->display.get_display_clock_speed =
14725 pnv_get_display_clock_speed;
14726 else if (IS_G33(dev) || IS_G4X(dev))
14727 dev_priv->display.get_display_clock_speed =
14728 g33_get_display_clock_speed;
e70236a8
JB		 14729 else if (IS_I915G(dev))
14730 dev_priv->display.get_display_clock_speed =
14731 i915_get_display_clock_speed;
257a7ffc 14732 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 14733 dev_priv->display.get_display_clock_speed =
14734 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 14735 else if (IS_PINEVIEW(dev))
14736 dev_priv->display.get_display_clock_speed =
14737 pnv_get_display_clock_speed;
e70236a8
JB		 14738 else if (IS_I915GM(dev))
14739 dev_priv->display.get_display_clock_speed =
14740 i915gm_get_display_clock_speed;
14741 else if (IS_I865G(dev))
14742 dev_priv->display.get_display_clock_speed =
14743 i865_get_display_clock_speed;
f0f8a9ce 14744 else if (IS_I85X(dev))
e70236a8 14745 dev_priv->display.get_display_clock_speed =
1b1d2716 14746 i85x_get_display_clock_speed;
623e01e5
VS		 14747 else { /* 830 */
14748 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
e70236a8
JB		 14749 dev_priv->display.get_display_clock_speed =
14750 i830_get_display_clock_speed;
623e01e5 14751 }
e70236a8 14752
7c10a2b5 14753 if (IS_GEN5(dev)) {
3bb11b53 14754 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 14755 } else if (IS_GEN6(dev)) {
14756 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 14757 } else if (IS_IVYBRIDGE(dev)) {
14758 /* FIXME: detect B0+ stepping and use auto training */
14759 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 14760 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 14761 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
b432e5cf
VS		 14762 if (IS_BROADWELL(dev))
14763 dev_priv->display.modeset_global_resources =
14764 broadwell_modeset_global_resources;
30a970c6
JB		 14765 } else if (IS_VALLEYVIEW(dev)) {
14766 dev_priv->display.modeset_global_resources =
14767 valleyview_modeset_global_resources;
f8437dd1
VK		 14768 } else if (IS_BROXTON(dev)) {
14769 dev_priv->display.modeset_global_resources =
14770 broxton_modeset_global_resources;
e70236a8 14771 }
8c9f3aaf 14772
8c9f3aaf
JB		 14773 switch (INTEL_INFO(dev)->gen) {
14774 case 2:
14775 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14776 break;
14777
14778 case 3:
14779 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14780 break;
14781
14782 case 4:
14783 case 5:
14784 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14785 break;
14786
14787 case 6:
14788 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14789 break;
7c9017e5 14790 case 7:
4e0bbc31 14791 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 14792 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14793 break;
830c81db 14794 case 9:
ba343e02
TU		 14795 /* Drop through - unsupported since execlist only. */
14796 default:
14797 /* Default just returns -ENODEV to indicate unsupported */
14798 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 14799 }
7bd688cd
JN		 14800
14801 intel_panel_init_backlight_funcs(dev);
e39b999a
VS		 14802
14803 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 14804}
14805
b690e96c
JB		 14806/*
14807 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14808 * resume, or other times. This quirk makes sure that's the case for
14809 * affected systems.
14810 */
0206e353 14811static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 14812{
14813 struct drm_i915_private *dev_priv = dev->dev_private;
14814
14815 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 14816 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 14817}
14818
b6b5d049
VS		 14819static void quirk_pipeb_force(struct drm_device *dev)
14820{
14821 struct drm_i915_private *dev_priv = dev->dev_private;
14822
14823 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14824 DRM_INFO("applying pipe b force quirk\n");
14825}
14826
435793df
KP		 14827/*
14828 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14829 */
14830static void quirk_ssc_force_disable(struct drm_device *dev)
14831{
14832 struct drm_i915_private *dev_priv = dev->dev_private;
14833 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 14834 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 14835}
14836
4dca20ef 14837/*
5a15ab5b
CE		 14838 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14839 * brightness value
4dca20ef
CE		 14840 */
14841static void quirk_invert_brightness(struct drm_device *dev)
14842{
14843 struct drm_i915_private *dev_priv = dev->dev_private;
14844 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 14845 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 14846}
14847
9c72cc6f
SD		 14848/* Some VBT's incorrectly indicate no backlight is present */
14849static void quirk_backlight_present(struct drm_device *dev)
14850{
14851 struct drm_i915_private *dev_priv = dev->dev_private;
14852 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14853 DRM_INFO("applying backlight present quirk\n");
14854}
14855
b690e96c
JB		 14856struct intel_quirk {
14857 int device;
14858 int subsystem_vendor;
14859 int subsystem_device;
14860 void (*hook)(struct drm_device *dev);
14861};
14862
5f85f176
EE		 14863/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14864struct intel_dmi_quirk {
14865 void (*hook)(struct drm_device *dev);
14866 const struct dmi_system_id (*dmi_id_list)[];
14867};
14868
14869static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14870{
14871 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14872 return 1;
14873}
14874
14875static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14876 {
14877 .dmi_id_list = &(const struct dmi_system_id[]) {
14878 {
14879 .callback = intel_dmi_reverse_brightness,
14880 .ident = "NCR Corporation",
14881 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14882 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14883 },
14884 },
14885 { } /* terminating entry */
14886 },
14887 .hook = quirk_invert_brightness,
14888 },
14889};
14890
c43b5634 14891static struct intel_quirk intel_quirks[] = {
b690e96c
JB		 14892 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14893 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14894
b690e96c
JB		 14895 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14896 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14897
5f080c0f
VS		 14898 /* 830 needs to leave pipe A & dpll A up */
14899 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14900
b6b5d049
VS		 14901 /* 830 needs to leave pipe B & dpll B up */
14902 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14903
435793df
KP		 14904 /* Lenovo U160 cannot use SSC on LVDS */
14905 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 14906
14907 /* Sony Vaio Y cannot use SSC on LVDS */
14908 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 14909
be505f64
AH		 14910 /* Acer Aspire 5734Z must invert backlight brightness */
14911 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14912
14913 /* Acer/eMachines G725 */
14914 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14915
14916 /* Acer/eMachines e725 */
14917 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14918
14919 /* Acer/Packard Bell NCL20 */
14920 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14921
14922 /* Acer Aspire 4736Z */
14923 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 14924
14925 /* Acer Aspire 5336 */
14926 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 14927
14928 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14929 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 14930
dfb3d47b
SD		 14931 /* Acer C720 Chromebook (Core i3 4005U) */
14932 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14933
b2a9601c 14934 /* Apple Macbook 2,1 (Core 2 T7400) */
14935 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14936
d4967d8c
SD		 14937 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14938 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 14939
14940 /* HP Chromebook 14 (Celeron 2955U) */
14941 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 14942
14943 /* Dell Chromebook 11 */
14944 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 14945};
14946
14947static void intel_init_quirks(struct drm_device *dev)
14948{
14949 struct pci_dev *d = dev->pdev;
14950 int i;
14951
14952 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14953 struct intel_quirk *q = &intel_quirks[i];
14954
14955 if (d->device == q->device &&
14956 (d->subsystem_vendor == q->subsystem_vendor ||
14957 q->subsystem_vendor == PCI_ANY_ID) &&
14958 (d->subsystem_device == q->subsystem_device ||
14959 q->subsystem_device == PCI_ANY_ID))
14960 q->hook(dev);
14961 }
5f85f176
EE		 14962 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14963 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14964 intel_dmi_quirks[i].hook(dev);
14965 }
b690e96c
JB		 14966}
14967
9cce37f4
JB		 14968/* Disable the VGA plane that we never use */
14969static void i915_disable_vga(struct drm_device *dev)
14970{
14971 struct drm_i915_private *dev_priv = dev->dev_private;
14972 u8 sr1;
766aa1c4 14973 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 14974
2b37c616 14975 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 14976 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 14977 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 14978 sr1 = inb(VGA_SR_DATA);
14979 outb(sr1 | 1<<5, VGA_SR_DATA);
14980 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14981 udelay(300);
14982
01f5a626 14983 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 14984 POSTING_READ(vga_reg);
14985}
14986
f817586c
DV		 14987void intel_modeset_init_hw(struct drm_device *dev)
14988{
b6283055 14989 intel_update_cdclk(dev);
a8f78b58 14990 intel_prepare_ddi(dev);
f817586c 14991 intel_init_clock_gating(dev);
8090c6b9 14992 intel_enable_gt_powersave(dev);
f817586c
DV		 14993}
14994
79e53945
JB		 14995void intel_modeset_init(struct drm_device *dev)
14996{
652c393a 14997 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 14998 int sprite, ret;
8cc87b75 14999 enum pipe pipe;
46f297fb 15000 struct intel_crtc *crtc;
79e53945
JB		 15001
15002 drm_mode_config_init(dev);
15003
15004 dev->mode_config.min_width = 0;
15005 dev->mode_config.min_height = 0;
15006
019d96cb
DA		 15007 dev->mode_config.preferred_depth = 24;
15008 dev->mode_config.prefer_shadow = 1;
15009
25bab385
TU		 15010 dev->mode_config.allow_fb_modifiers = true;
15011
e6ecefaa 15012 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 15013
b690e96c
JB		 15014 intel_init_quirks(dev);
15015
1fa61106
ED		 15016 intel_init_pm(dev);
15017
e3c74757
BW		 15018 if (INTEL_INFO(dev)->num_pipes == 0)
15019 return;
15020
e70236a8 15021 intel_init_display(dev);
7c10a2b5 15022 intel_init_audio(dev);
e70236a8 15023
a6c45cf0
CW		 15024 if (IS_GEN2(dev)) {
15025 dev->mode_config.max_width = 2048;
15026 dev->mode_config.max_height = 2048;
15027 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 15028 dev->mode_config.max_width = 4096;
15029 dev->mode_config.max_height = 4096;
79e53945 15030 } else {
a6c45cf0
CW		 15031 dev->mode_config.max_width = 8192;
15032 dev->mode_config.max_height = 8192;
79e53945 15033 }
068be561 15034
dc41c154
VS		 15035 if (IS_845G(dev) || IS_I865G(dev)) {
15036 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15037 dev->mode_config.cursor_height = 1023;
15038 } else if (IS_GEN2(dev)) {
068be561
DL		 15039 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15040 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15041 } else {
15042 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15043 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15044 }
15045
5d4545ae 15046 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 15047
28c97730 15048 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 15049 INTEL_INFO(dev)->num_pipes,
15050 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 15051
055e393f 15052 for_each_pipe(dev_priv, pipe) {
8cc87b75 15053 intel_crtc_init(dev, pipe);
3bdcfc0c 15054 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 15055 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 15056 if (ret)
06da8da2 15057 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 15058 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 15059 }
79e53945
JB		 15060 }
15061
f42bb70d
JB		 15062 intel_init_dpio(dev);
15063
e72f9fbf 15064 intel_shared_dpll_init(dev);
ee7b9f93 15065
9cce37f4
JB		 15066 /* Just disable it once at startup */
15067 i915_disable_vga(dev);
79e53945 15068 intel_setup_outputs(dev);
11be49eb
CW		 15069
15070 /* Just in case the BIOS is doing something questionable. */
7ff0ebcc 15071 intel_fbc_disable(dev);
fa9fa083 15072
6e9f798d 15073 drm_modeset_lock_all(dev);
fa9fa083 15074 intel_modeset_setup_hw_state(dev, false);
6e9f798d 15075 drm_modeset_unlock_all(dev);
46f297fb 15076
d3fcc808 15077 for_each_intel_crtc(dev, crtc) {
46f297fb
JB		 15078 if (!crtc->active)
15079 continue;
15080
46f297fb 15081 /*
46f297fb
JB		 15082 * Note that reserving the BIOS fb up front prevents us
15083 * from stuffing other stolen allocations like the ring
15084 * on top. This prevents some ugliness at boot time, and
15085 * can even allow for smooth boot transitions if the BIOS
15086 * fb is large enough for the active pipe configuration.
15087 */
5724dbd1
DL		 15088 if (dev_priv->display.get_initial_plane_config) {
15089 dev_priv->display.get_initial_plane_config(crtc,
46f297fb
JB		 15090 &crtc->plane_config);
15091 /*
15092 * If the fb is shared between multiple heads, we'll
15093 * just get the first one.
15094 */
f6936e29 15095 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
46f297fb 15096 }
46f297fb 15097 }
2c7111db
CW		 15098}
15099
7fad798e
DV		 15100static void intel_enable_pipe_a(struct drm_device *dev)
15101{
15102 struct intel_connector *connector;
15103 struct drm_connector *crt = NULL;
15104 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 15105 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 15106
15107 /* We can't just switch on the pipe A, we need to set things up with a
15108 * proper mode and output configuration. As a gross hack, enable pipe A
15109 * by enabling the load detect pipe once. */
3a3371ff 15110 for_each_intel_connector(dev, connector) {
7fad798e
DV		 15111 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15112 crt = &connector->base;
15113 break;
15114 }
15115 }
15116
15117 if (!crt)
15118 return;
15119
208bf9fd 15120 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 15121 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 15122}
15123
fa555837
DV		 15124static bool
15125intel_check_plane_mapping(struct intel_crtc *crtc)
15126{
7eb552ae
BW		 15127 struct drm_device *dev = crtc->base.dev;
15128 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 15129 u32 reg, val;
15130
7eb552ae 15131 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 15132 return true;
15133
15134 reg = DSPCNTR(!crtc->plane);
15135 val = I915_READ(reg);
15136
15137 if ((val & DISPLAY_PLANE_ENABLE) &&
15138 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15139 return false;
15140
15141 return true;
15142}
15143
24929352
DV		 15144static void intel_sanitize_crtc(struct intel_crtc *crtc)
15145{
15146 struct drm_device *dev = crtc->base.dev;
15147 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 15148 u32 reg;
24929352 15149
24929352 15150 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 15151 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 15152 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15153
d3eaf884 15154 /* restore vblank interrupts to correct state */
9625604c 15155 drm_crtc_vblank_reset(&crtc->base);
d297e103
VS		 15156 if (crtc->active) {
15157 update_scanline_offset(crtc);
9625604c
DV		 15158 drm_crtc_vblank_on(&crtc->base);
15159 }
d3eaf884 15160
24929352 15161 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 15162 * disable the crtc (and hence change the state) if it is wrong. Note
15163 * that gen4+ has a fixed plane -> pipe mapping. */
15164 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 15165 struct intel_connector *connector;
15166 bool plane;
15167
24929352
DV		 15168 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15169 crtc->base.base.id);
15170
15171 /* Pipe has the wrong plane attached and the plane is active.
15172 * Temporarily change the plane mapping and disable everything
15173 * ... */
15174 plane = crtc->plane;
b70709a6 15175 to_intel_plane_state(crtc->base.primary->state)->visible = true;
24929352 15176 crtc->plane = !plane;
1b509259 15177 intel_crtc_control(&crtc->base, false);
24929352
DV		 15178 crtc->plane = plane;
15179
15180 /* ... and break all links. */
3a3371ff 15181 for_each_intel_connector(dev, connector) {
24929352
DV		 15182 if (connector->encoder->base.crtc != &crtc->base)
15183 continue;
15184
7f1950fb
EE		 15185 connector->base.dpms = DRM_MODE_DPMS_OFF;
15186 connector->base.encoder = NULL;
24929352 15187 }
7f1950fb
EE		 15188 /* multiple connectors may have the same encoder:
15189 * handle them and break crtc link separately */
3a3371ff 15190 for_each_intel_connector(dev, connector)
7f1950fb
EE		 15191 if (connector->encoder->base.crtc == &crtc->base) {
15192 connector->encoder->base.crtc = NULL;
15193 connector->encoder->connectors_active = false;
15194 }
24929352
DV		 15195
15196 WARN_ON(crtc->active);
83d65738 15197 crtc->base.state->enable = false;
49d6fa21 15198 crtc->base.state->active = false;
24929352
DV		 15199 crtc->base.enabled = false;
15200 }
24929352 15201
7fad798e
DV		 15202 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15203 crtc->pipe == PIPE_A && !crtc->active) {
15204 /* BIOS forgot to enable pipe A, this mostly happens after
15205 * resume. Force-enable the pipe to fix this, the update_dpms
15206 * call below we restore the pipe to the right state, but leave
15207 * the required bits on. */
15208 intel_enable_pipe_a(dev);
15209 }
15210
24929352
DV		 15211 /* Adjust the state of the output pipe according to whether we
15212 * have active connectors/encoders. */
15213 intel_crtc_update_dpms(&crtc->base);
15214
83d65738 15215 if (crtc->active != crtc->base.state->enable) {
24929352
DV		 15216 struct intel_encoder *encoder;
15217
15218 /* This can happen either due to bugs in the get_hw_state
15219 * functions or because the pipe is force-enabled due to the
15220 * pipe A quirk. */
15221 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15222 crtc->base.base.id,
83d65738 15223 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 15224 crtc->active ? "enabled" : "disabled");
15225
83d65738 15226 crtc->base.state->enable = crtc->active;
49d6fa21 15227 crtc->base.state->active = crtc->active;
24929352
DV		 15228 crtc->base.enabled = crtc->active;
15229
15230 /* Because we only establish the connector -> encoder ->
15231 * crtc links if something is active, this means the
15232 * crtc is now deactivated. Break the links. connector
15233 * -> encoder links are only establish when things are
15234 * actually up, hence no need to break them. */
15235 WARN_ON(crtc->active);
15236
15237 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
15238 WARN_ON(encoder->connectors_active);
15239 encoder->base.crtc = NULL;
15240 }
15241 }
c5ab3bc0 15242
a3ed6aad 15243 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 15244 /*
15245 * We start out with underrun reporting disabled to avoid races.
15246 * For correct bookkeeping mark this on active crtcs.
15247 *
c5ab3bc0
DV		 15248 * Also on gmch platforms we dont have any hardware bits to
15249 * disable the underrun reporting. Which means we need to start
15250 * out with underrun reporting disabled also on inactive pipes,
15251 * since otherwise we'll complain about the garbage we read when
15252 * e.g. coming up after runtime pm.
15253 *
4cc31489
DV		 15254 * No protection against concurrent access is required - at
15255 * worst a fifo underrun happens which also sets this to false.
15256 */
15257 crtc->cpu_fifo_underrun_disabled = true;
15258 crtc->pch_fifo_underrun_disabled = true;
15259 }
24929352
DV		 15260}
15261
15262static void intel_sanitize_encoder(struct intel_encoder *encoder)
15263{
15264 struct intel_connector *connector;
15265 struct drm_device *dev = encoder->base.dev;
15266
15267 /* We need to check both for a crtc link (meaning that the
15268 * encoder is active and trying to read from a pipe) and the
15269 * pipe itself being active. */
15270 bool has_active_crtc = encoder->base.crtc &&
15271 to_intel_crtc(encoder->base.crtc)->active;
15272
15273 if (encoder->connectors_active && !has_active_crtc) {
15274 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15275 encoder->base.base.id,
8e329a03 15276 encoder->base.name);
24929352
DV		 15277
15278 /* Connector is active, but has no active pipe. This is
15279 * fallout from our resume register restoring. Disable
15280 * the encoder manually again. */
15281 if (encoder->base.crtc) {
15282 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15283 encoder->base.base.id,
8e329a03 15284 encoder->base.name);
24929352 15285 encoder->disable(encoder);
a62d1497
VS		 15286 if (encoder->post_disable)
15287 encoder->post_disable(encoder);
24929352 15288 }
7f1950fb
EE		 15289 encoder->base.crtc = NULL;
15290 encoder->connectors_active = false;
24929352
DV		 15291
15292 /* Inconsistent output/port/pipe state happens presumably due to
15293 * a bug in one of the get_hw_state functions. Or someplace else
15294 * in our code, like the register restore mess on resume. Clamp
15295 * things to off as a safer default. */
3a3371ff 15296 for_each_intel_connector(dev, connector) {
24929352
DV		 15297 if (connector->encoder != encoder)
15298 continue;
7f1950fb
EE		 15299 connector->base.dpms = DRM_MODE_DPMS_OFF;
15300 connector->base.encoder = NULL;
24929352
DV		 15301 }
15302 }
15303 /* Enabled encoders without active connectors will be fixed in
15304 * the crtc fixup. */
15305}
15306
04098753 15307void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 15308{
15309 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 15310 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 15311
04098753
ID		 15312 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15313 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15314 i915_disable_vga(dev);
15315 }
15316}
15317
15318void i915_redisable_vga(struct drm_device *dev)
15319{
15320 struct drm_i915_private *dev_priv = dev->dev_private;
15321
8dc8a27c
PZ		 15322 /* This function can be called both from intel_modeset_setup_hw_state or
15323 * at a very early point in our resume sequence, where the power well
15324 * structures are not yet restored. Since this function is at a very
15325 * paranoid "someone might have enabled VGA while we were not looking"
15326 * level, just check if the power well is enabled instead of trying to
15327 * follow the "don't touch the power well if we don't need it" policy
15328 * the rest of the driver uses. */
f458ebbc 15329 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 15330 return;
15331
04098753 15332 i915_redisable_vga_power_on(dev);
0fde901f
KM		 15333}
15334
98ec7739
VS		 15335static bool primary_get_hw_state(struct intel_crtc *crtc)
15336{
15337 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15338
15339 if (!crtc->active)
15340 return false;
15341
15342 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
15343}
15344
30e984df 15345static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 15346{
15347 struct drm_i915_private *dev_priv = dev->dev_private;
15348 enum pipe pipe;
24929352
DV		 15349 struct intel_crtc *crtc;
15350 struct intel_encoder *encoder;
15351 struct intel_connector *connector;
5358901f 15352 int i;
24929352 15353
d3fcc808 15354 for_each_intel_crtc(dev, crtc) {
b70709a6
ML		 15355 struct drm_plane *primary = crtc->base.primary;
15356 struct intel_plane_state *plane_state;
15357
6e3c9717 15358 memset(crtc->config, 0, sizeof(*crtc->config));
3b117c8f 15359
6e3c9717 15360 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
9953599b 15361
0e8ffe1b 15362 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 15363 crtc->config);
24929352 15364
83d65738 15365 crtc->base.state->enable = crtc->active;
49d6fa21 15366 crtc->base.state->active = crtc->active;
24929352 15367 crtc->base.enabled = crtc->active;
b70709a6
ML		 15368
15369 plane_state = to_intel_plane_state(primary->state);
15370 plane_state->visible = primary_get_hw_state(crtc);
24929352
DV		 15371
15372 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15373 crtc->base.base.id,
15374 crtc->active ? "enabled" : "disabled");
15375 }
15376
5358901f
DV		 15377 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15378 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15379
3e369b76
ACO		 15380 pll->on = pll->get_hw_state(dev_priv, pll,
15381 &pll->config.hw_state);
5358901f 15382 pll->active = 0;
3e369b76 15383 pll->config.crtc_mask = 0;
d3fcc808 15384 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 15385 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 15386 pll->active++;
3e369b76 15387 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 15388 }
5358901f 15389 }
5358901f 15390
1e6f2ddc 15391 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 15392 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 15393
3e369b76 15394 if (pll->config.crtc_mask)
bd2bb1b9 15395 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 15396 }
15397
b2784e15 15398 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15399 pipe = 0;
15400
15401 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 15402 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15403 encoder->base.crtc = &crtc->base;
6e3c9717 15404 encoder->get_config(encoder, crtc->config);
24929352
DV		 15405 } else {
15406 encoder->base.crtc = NULL;
15407 }
15408
15409 encoder->connectors_active = false;
6f2bcceb 15410 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 15411 encoder->base.base.id,
8e329a03 15412 encoder->base.name,
24929352 15413 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 15414 pipe_name(pipe));
24929352
DV		 15415 }
15416
3a3371ff 15417 for_each_intel_connector(dev, connector) {
24929352
DV		 15418 if (connector->get_hw_state(connector)) {
15419 connector->base.dpms = DRM_MODE_DPMS_ON;
15420 connector->encoder->connectors_active = true;
15421 connector->base.encoder = &connector->encoder->base;
15422 } else {
15423 connector->base.dpms = DRM_MODE_DPMS_OFF;
15424 connector->base.encoder = NULL;
15425 }
15426 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15427 connector->base.base.id,
c23cc417 15428 connector->base.name,
24929352
DV		 15429 connector->base.encoder ? "enabled" : "disabled");
15430 }
30e984df
DV		 15431}
15432
15433/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15434 * and i915 state tracking structures. */
15435void intel_modeset_setup_hw_state(struct drm_device *dev,
15436 bool force_restore)
15437{
15438 struct drm_i915_private *dev_priv = dev->dev_private;
15439 enum pipe pipe;
30e984df
DV		 15440 struct intel_crtc *crtc;
15441 struct intel_encoder *encoder;
35c95375 15442 int i;
30e984df
DV		 15443
15444 intel_modeset_readout_hw_state(dev);
24929352 15445
babea61d
JB		 15446 /*
15447 * Now that we have the config, copy it to each CRTC struct
15448 * Note that this could go away if we move to using crtc_config
15449 * checking everywhere.
15450 */
d3fcc808 15451 for_each_intel_crtc(dev, crtc) {
d330a953 15452 if (crtc->active && i915.fastboot) {
6e3c9717
ACO		 15453 intel_mode_from_pipe_config(&crtc->base.mode,
15454 crtc->config);
babea61d
JB		 15455 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15456 crtc->base.base.id);
15457 drm_mode_debug_printmodeline(&crtc->base.mode);
15458 }
15459 }
15460
24929352 15461 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 15462 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15463 intel_sanitize_encoder(encoder);
15464 }
15465
055e393f 15466 for_each_pipe(dev_priv, pipe) {
24929352
DV		 15467 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15468 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 15469 intel_dump_pipe_config(crtc, crtc->config,
15470 "[setup_hw_state]");
24929352 15471 }
9a935856 15472
d29b2f9d
ACO		 15473 intel_modeset_update_connector_atomic_state(dev);
15474
35c95375
DV		 15475 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15476 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15477
15478 if (!pll->on || pll->active)
15479 continue;
15480
15481 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15482
15483 pll->disable(dev_priv, pll);
15484 pll->on = false;
15485 }
15486
3078999f
PB		 15487 if (IS_GEN9(dev))
15488 skl_wm_get_hw_state(dev);
15489 else if (HAS_PCH_SPLIT(dev))
243e6a44
VS		 15490 ilk_wm_get_hw_state(dev);
15491
45e2b5f6 15492 if (force_restore) {
7d0bc1ea
VS		 15493 i915_redisable_vga(dev);
15494
f30da187
DV		 15495 /*
15496 * We need to use raw interfaces for restoring state to avoid
15497 * checking (bogus) intermediate states.
15498 */
055e393f 15499 for_each_pipe(dev_priv, pipe) {
b5644d05
JB		 15500 struct drm_crtc *crtc =
15501 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187 15502
83a57153 15503 intel_crtc_restore_mode(crtc);
45e2b5f6
DV		 15504 }
15505 } else {
15506 intel_modeset_update_staged_output_state(dev);
15507 }
8af6cf88
DV		 15508
15509 intel_modeset_check_state(dev);
2c7111db
CW		 15510}
15511
15512void intel_modeset_gem_init(struct drm_device *dev)
15513{
92122789 15514 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd 15515 struct drm_crtc *c;
2ff8fde1 15516 struct drm_i915_gem_object *obj;
e0d6149b 15517 int ret;
484b41dd 15518
ae48434c
ID		 15519 mutex_lock(&dev->struct_mutex);
15520 intel_init_gt_powersave(dev);
15521 mutex_unlock(&dev->struct_mutex);
15522
92122789
JB		 15523 /*
15524 * There may be no VBT; and if the BIOS enabled SSC we can
15525 * just keep using it to avoid unnecessary flicker. Whereas if the
15526 * BIOS isn't using it, don't assume it will work even if the VBT
15527 * indicates as much.
15528 */
15529 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15530 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15531 DREF_SSC1_ENABLE);
15532
1833b134 15533 intel_modeset_init_hw(dev);
02e792fb
DV		 15534
15535 intel_setup_overlay(dev);
484b41dd
JB		 15536
15537 /*
15538 * Make sure any fbs we allocated at startup are properly
15539 * pinned & fenced. When we do the allocation it's too early
15540 * for this.
15541 */
70e1e0ec 15542 for_each_crtc(dev, c) {
2ff8fde1
MR		 15543 obj = intel_fb_obj(c->primary->fb);
15544 if (obj == NULL)
484b41dd
JB		 15545 continue;
15546
e0d6149b
TU		 15547 mutex_lock(&dev->struct_mutex);
15548 ret = intel_pin_and_fence_fb_obj(c->primary,
15549 c->primary->fb,
15550 c->primary->state,
15551 NULL);
15552 mutex_unlock(&dev->struct_mutex);
15553 if (ret) {
484b41dd
JB		 15554 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15555 to_intel_crtc(c)->pipe);
66e514c1
DA		 15556 drm_framebuffer_unreference(c->primary->fb);
15557 c->primary->fb = NULL;
afd65eb4 15558 update_state_fb(c->primary);
484b41dd
JB		 15559 }
15560 }
0962c3c9
VS		 15561
15562 intel_backlight_register(dev);
79e53945
JB		 15563}
15564
4932e2c3
ID		 15565void intel_connector_unregister(struct intel_connector *intel_connector)
15566{
15567 struct drm_connector *connector = &intel_connector->base;
15568
15569 intel_panel_destroy_backlight(connector);
34ea3d38 15570 drm_connector_unregister(connector);
4932e2c3
ID		 15571}
15572
79e53945
JB		 15573void intel_modeset_cleanup(struct drm_device *dev)
15574{
652c393a 15575 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 15576 struct drm_connector *connector;
652c393a 15577
2eb5252e
ID		 15578 intel_disable_gt_powersave(dev);
15579
0962c3c9
VS		 15580 intel_backlight_unregister(dev);
15581
fd0c0642
DV		 15582 /*
15583 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 15584 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 15585 * experience fancy races otherwise.
15586 */
2aeb7d3a 15587 intel_irq_uninstall(dev_priv);
eb21b92b 15588
fd0c0642
DV		 15589 /*
15590 * Due to the hpd irq storm handling the hotplug work can re-arm the
15591 * poll handlers. Hence disable polling after hpd handling is shut down.
15592 */
f87ea761 15593 drm_kms_helper_poll_fini(dev);
fd0c0642 15594
652c393a
JB		 15595 mutex_lock(&dev->struct_mutex);
15596
723bfd70
JB		 15597 intel_unregister_dsm_handler();
15598
7ff0ebcc 15599 intel_fbc_disable(dev);
e70236a8 15600
69341a5e
KH		 15601 mutex_unlock(&dev->struct_mutex);
15602
1630fe75
CW		 15603 /* flush any delayed tasks or pending work */
15604 flush_scheduled_work();
15605
db31af1d
JN		 15606 /* destroy the backlight and sysfs files before encoders/connectors */
15607 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 15608 struct intel_connector *intel_connector;
15609
15610 intel_connector = to_intel_connector(connector);
15611 intel_connector->unregister(intel_connector);
db31af1d 15612 }
d9255d57 15613
79e53945 15614 drm_mode_config_cleanup(dev);
4d7bb011
DV		 15615
15616 intel_cleanup_overlay(dev);
ae48434c
ID		 15617
15618 mutex_lock(&dev->struct_mutex);
15619 intel_cleanup_gt_powersave(dev);
15620 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 15621}
15622
f1c79df3
ZW		 15623/*
15624 * Return which encoder is currently attached for connector.
15625 */
df0e9248 15626struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 15627{
df0e9248
CW		 15628 return &intel_attached_encoder(connector)->base;
15629}
f1c79df3 15630
df0e9248
CW		 15631void intel_connector_attach_encoder(struct intel_connector *connector,
15632 struct intel_encoder *encoder)
15633{
15634 connector->encoder = encoder;
15635 drm_mode_connector_attach_encoder(&connector->base,
15636 &encoder->base);
79e53945 15637}
28d52043
DA		 15638
15639/*
15640 * set vga decode state - true == enable VGA decode
15641 */
15642int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15643{
15644 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 15645 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 15646 u16 gmch_ctrl;
15647
75fa041d
CW		 15648 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15649 DRM_ERROR("failed to read control word\n");
15650 return -EIO;
15651 }
15652
c0cc8a55
CW		 15653 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15654 return 0;
15655
28d52043
DA		 15656 if (state)
15657 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15658 else
15659 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 15660
15661 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15662 DRM_ERROR("failed to write control word\n");
15663 return -EIO;
15664 }
15665
28d52043
DA		 15666 return 0;
15667}
c4a1d9e4 15668
c4a1d9e4 15669struct intel_display_error_state {
ff57f1b0
PZ		 15670
15671 u32 power_well_driver;
15672
63b66e5b
CW		 15673 int num_transcoders;
15674
c4a1d9e4
CW		 15675 struct intel_cursor_error_state {
15676 u32 control;
15677 u32 position;
15678 u32 base;
15679 u32 size;
52331309 15680 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 15681
15682 struct intel_pipe_error_state {
ddf9c536 15683 bool power_domain_on;
c4a1d9e4 15684 u32 source;
f301b1e1 15685 u32 stat;
52331309 15686 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 15687
15688 struct intel_plane_error_state {
15689 u32 control;
15690 u32 stride;
15691 u32 size;
15692 u32 pos;
15693 u32 addr;
15694 u32 surface;
15695 u32 tile_offset;
52331309 15696 } plane[I915_MAX_PIPES];
63b66e5b
CW		 15697
15698 struct intel_transcoder_error_state {
ddf9c536 15699 bool power_domain_on;
63b66e5b
CW		 15700 enum transcoder cpu_transcoder;
15701
15702 u32 conf;
15703
15704 u32 htotal;
15705 u32 hblank;
15706 u32 hsync;
15707 u32 vtotal;
15708 u32 vblank;
15709 u32 vsync;
15710 } transcoder[4];
c4a1d9e4
CW		 15711};
15712
15713struct intel_display_error_state *
15714intel_display_capture_error_state(struct drm_device *dev)
15715{
fbee40df 15716 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 15717 struct intel_display_error_state *error;
63b66e5b
CW		 15718 int transcoders[] = {
15719 TRANSCODER_A,
15720 TRANSCODER_B,
15721 TRANSCODER_C,
15722 TRANSCODER_EDP,
15723 };
c4a1d9e4
CW		 15724 int i;
15725
63b66e5b
CW		 15726 if (INTEL_INFO(dev)->num_pipes == 0)
15727 return NULL;
15728
9d1cb914 15729 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 15730 if (error == NULL)
15731 return NULL;
15732
190be112 15733 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 15734 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15735
055e393f 15736 for_each_pipe(dev_priv, i) {
ddf9c536 15737 error->pipe[i].power_domain_on =
f458ebbc
DV		 15738 __intel_display_power_is_enabled(dev_priv,
15739 POWER_DOMAIN_PIPE(i));
ddf9c536 15740 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 15741 continue;
15742
5efb3e28
VS		 15743 error->cursor[i].control = I915_READ(CURCNTR(i));
15744 error->cursor[i].position = I915_READ(CURPOS(i));
15745 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 15746
15747 error->plane[i].control = I915_READ(DSPCNTR(i));
15748 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 15749 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 15750 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 15751 error->plane[i].pos = I915_READ(DSPPOS(i));
15752 }
ca291363
PZ		 15753 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15754 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 15755 if (INTEL_INFO(dev)->gen >= 4) {
15756 error->plane[i].surface = I915_READ(DSPSURF(i));
15757 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15758 }
15759
c4a1d9e4 15760 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 15761
3abfce77 15762 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 15763 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 15764 }
15765
15766 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15767 if (HAS_DDI(dev_priv->dev))
15768 error->num_transcoders++; /* Account for eDP. */
15769
15770 for (i = 0; i < error->num_transcoders; i++) {
15771 enum transcoder cpu_transcoder = transcoders[i];
15772
ddf9c536 15773 error->transcoder[i].power_domain_on =
f458ebbc 15774 __intel_display_power_is_enabled(dev_priv,
38cc1daf 15775 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 15776 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 15777 continue;
15778
63b66e5b
CW		 15779 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15780
15781 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15782 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15783 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15784 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15785 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15786 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15787 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 15788 }
15789
15790 return error;
15791}
15792
edc3d884
MK		 15793#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15794
c4a1d9e4 15795void
edc3d884 15796intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 15797 struct drm_device *dev,
15798 struct intel_display_error_state *error)
15799{
055e393f 15800 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 15801 int i;
15802
63b66e5b
CW		 15803 if (!error)
15804 return;
15805
edc3d884 15806 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 15807 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 15808 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 15809 error->power_well_driver);
055e393f 15810 for_each_pipe(dev_priv, i) {
edc3d884 15811 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 15812 err_printf(m, " Power: %s\n",
15813 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 15814 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 15815 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 15816
15817 err_printf(m, "Plane [%d]:\n", i);
15818 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15819 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 15820 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 15821 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15822 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 15823 }
4b71a570 15824 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 15825 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 15826 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 15827 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15828 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 15829 }
15830
edc3d884
MK		 15831 err_printf(m, "Cursor [%d]:\n", i);
15832 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15833 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15834 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 15835 }
63b66e5b
CW		 15836
15837 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 15838 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 15839 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 15840 err_printf(m, " Power: %s\n",
15841 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 15842 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15843 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15844 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15845 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15846 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15847 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15848 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15849 }
c4a1d9e4 15850}
e2fcdaa9
VS		 15851
15852void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15853{
15854 struct intel_crtc *crtc;
15855
15856 for_each_intel_crtc(dev, crtc) {
15857 struct intel_unpin_work *work;
e2fcdaa9 15858
5e2d7afc 15859 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 15860
15861 work = crtc->unpin_work;
15862
15863 if (work && work->event &&
15864 work->event->base.file_priv == file) {
15865 kfree(work->event);
15866 work->event = NULL;
15867 }
15868
5e2d7afc 15869 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 15870 }
15871}
Linux kernel - Deliverables
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