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drm/i915: Eliminate one indent leel from vlv_find_best_dpll
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
3dec0095 44static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 45static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 46
f1f644dc
JB		 47static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
48 struct intel_crtc_config *pipe_config);
18442d08
VS		 49static void ironlake_pch_clock_get(struct intel_crtc *crtc,
50 struct intel_crtc_config *pipe_config);
f1f644dc 51
e7457a9a
DL		 52static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
53 int x, int y, struct drm_framebuffer *old_fb);
54
55
79e53945 56typedef struct {
0206e353 57 int min, max;
79e53945
JB		 58} intel_range_t;
59
60typedef struct {
0206e353
AJ		 61 int dot_limit;
62 int p2_slow, p2_fast;
79e53945
JB		 63} intel_p2_t;
64
d4906093
ML		 65typedef struct intel_limit intel_limit_t;
66struct intel_limit {
0206e353
AJ		 67 intel_range_t dot, vco, n, m, m1, m2, p, p1;
68 intel_p2_t p2;
d4906093 69};
79e53945 70
d2acd215
DV		 71int
72intel_pch_rawclk(struct drm_device *dev)
73{
74 struct drm_i915_private *dev_priv = dev->dev_private;
75
76 WARN_ON(!HAS_PCH_SPLIT(dev));
77
78 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
79}
80
021357ac
CW		 81static inline u32 /* units of 100MHz */
82intel_fdi_link_freq(struct drm_device *dev)
83{
8b99e68c
CW		 84 if (IS_GEN5(dev)) {
85 struct drm_i915_private *dev_priv = dev->dev_private;
86 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
87 } else
88 return 27;
021357ac
CW		 89}
90
5d536e28 91static const intel_limit_t intel_limits_i8xx_dac = {
0206e353
AJ		 92 .dot = { .min = 25000, .max = 350000 },
93 .vco = { .min = 930000, .max = 1400000 },
94 .n = { .min = 3, .max = 16 },
95 .m = { .min = 96, .max = 140 },
96 .m1 = { .min = 18, .max = 26 },
97 .m2 = { .min = 6, .max = 16 },
98 .p = { .min = 4, .max = 128 },
99 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 100 .p2 = { .dot_limit = 165000,
101 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 102};
103
5d536e28
DV		 104static const intel_limit_t intel_limits_i8xx_dvo = {
105 .dot = { .min = 25000, .max = 350000 },
106 .vco = { .min = 930000, .max = 1400000 },
107 .n = { .min = 3, .max = 16 },
108 .m = { .min = 96, .max = 140 },
109 .m1 = { .min = 18, .max = 26 },
110 .m2 = { .min = 6, .max = 16 },
111 .p = { .min = 4, .max = 128 },
112 .p1 = { .min = 2, .max = 33 },
113 .p2 = { .dot_limit = 165000,
114 .p2_slow = 4, .p2_fast = 4 },
115};
116
e4b36699 117static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 118 .dot = { .min = 25000, .max = 350000 },
119 .vco = { .min = 930000, .max = 1400000 },
120 .n = { .min = 3, .max = 16 },
121 .m = { .min = 96, .max = 140 },
122 .m1 = { .min = 18, .max = 26 },
123 .m2 = { .min = 6, .max = 16 },
124 .p = { .min = 4, .max = 128 },
125 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 126 .p2 = { .dot_limit = 165000,
127 .p2_slow = 14, .p2_fast = 7 },
e4b36699 128};
273e27ca 129
e4b36699 130static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 131 .dot = { .min = 20000, .max = 400000 },
132 .vco = { .min = 1400000, .max = 2800000 },
133 .n = { .min = 1, .max = 6 },
134 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 135 .m1 = { .min = 8, .max = 18 },
136 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 137 .p = { .min = 5, .max = 80 },
138 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 139 .p2 = { .dot_limit = 200000,
140 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 141};
142
143static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 144 .dot = { .min = 20000, .max = 400000 },
145 .vco = { .min = 1400000, .max = 2800000 },
146 .n = { .min = 1, .max = 6 },
147 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 148 .m1 = { .min = 8, .max = 18 },
149 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 150 .p = { .min = 7, .max = 98 },
151 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 152 .p2 = { .dot_limit = 112000,
153 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 154};
155
273e27ca 156
e4b36699 157static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 158 .dot = { .min = 25000, .max = 270000 },
159 .vco = { .min = 1750000, .max = 3500000},
160 .n = { .min = 1, .max = 4 },
161 .m = { .min = 104, .max = 138 },
162 .m1 = { .min = 17, .max = 23 },
163 .m2 = { .min = 5, .max = 11 },
164 .p = { .min = 10, .max = 30 },
165 .p1 = { .min = 1, .max = 3},
166 .p2 = { .dot_limit = 270000,
167 .p2_slow = 10,
168 .p2_fast = 10
044c7c41 169 },
e4b36699
KP		 170};
171
172static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 173 .dot = { .min = 22000, .max = 400000 },
174 .vco = { .min = 1750000, .max = 3500000},
175 .n = { .min = 1, .max = 4 },
176 .m = { .min = 104, .max = 138 },
177 .m1 = { .min = 16, .max = 23 },
178 .m2 = { .min = 5, .max = 11 },
179 .p = { .min = 5, .max = 80 },
180 .p1 = { .min = 1, .max = 8},
181 .p2 = { .dot_limit = 165000,
182 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 183};
184
185static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 186 .dot = { .min = 20000, .max = 115000 },
187 .vco = { .min = 1750000, .max = 3500000 },
188 .n = { .min = 1, .max = 3 },
189 .m = { .min = 104, .max = 138 },
190 .m1 = { .min = 17, .max = 23 },
191 .m2 = { .min = 5, .max = 11 },
192 .p = { .min = 28, .max = 112 },
193 .p1 = { .min = 2, .max = 8 },
194 .p2 = { .dot_limit = 0,
195 .p2_slow = 14, .p2_fast = 14
044c7c41 196 },
e4b36699
KP		 197};
198
199static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 200 .dot = { .min = 80000, .max = 224000 },
201 .vco = { .min = 1750000, .max = 3500000 },
202 .n = { .min = 1, .max = 3 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 17, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 14, .max = 42 },
207 .p1 = { .min = 2, .max = 6 },
208 .p2 = { .dot_limit = 0,
209 .p2_slow = 7, .p2_fast = 7
044c7c41 210 },
e4b36699
KP		 211};
212
f2b115e6 213static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 214 .dot = { .min = 20000, .max = 400000},
215 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 216 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 217 .n = { .min = 3, .max = 6 },
218 .m = { .min = 2, .max = 256 },
273e27ca 219 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 220 .m1 = { .min = 0, .max = 0 },
221 .m2 = { .min = 0, .max = 254 },
222 .p = { .min = 5, .max = 80 },
223 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 224 .p2 = { .dot_limit = 200000,
225 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 226};
227
f2b115e6 228static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 229 .dot = { .min = 20000, .max = 400000 },
230 .vco = { .min = 1700000, .max = 3500000 },
231 .n = { .min = 3, .max = 6 },
232 .m = { .min = 2, .max = 256 },
233 .m1 = { .min = 0, .max = 0 },
234 .m2 = { .min = 0, .max = 254 },
235 .p = { .min = 7, .max = 112 },
236 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 237 .p2 = { .dot_limit = 112000,
238 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 239};
240
273e27ca
EA		 241/* Ironlake / Sandybridge
242 *
243 * We calculate clock using (register_value + 2) for N/M1/M2, so here
244 * the range value for them is (actual_value - 2).
245 */
b91ad0ec 246static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 247 .dot = { .min = 25000, .max = 350000 },
248 .vco = { .min = 1760000, .max = 3510000 },
249 .n = { .min = 1, .max = 5 },
250 .m = { .min = 79, .max = 127 },
251 .m1 = { .min = 12, .max = 22 },
252 .m2 = { .min = 5, .max = 9 },
253 .p = { .min = 5, .max = 80 },
254 .p1 = { .min = 1, .max = 8 },
255 .p2 = { .dot_limit = 225000,
256 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 257};
258
b91ad0ec 259static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 260 .dot = { .min = 25000, .max = 350000 },
261 .vco = { .min = 1760000, .max = 3510000 },
262 .n = { .min = 1, .max = 3 },
263 .m = { .min = 79, .max = 118 },
264 .m1 = { .min = 12, .max = 22 },
265 .m2 = { .min = 5, .max = 9 },
266 .p = { .min = 28, .max = 112 },
267 .p1 = { .min = 2, .max = 8 },
268 .p2 = { .dot_limit = 225000,
269 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 270};
271
272static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 273 .dot = { .min = 25000, .max = 350000 },
274 .vco = { .min = 1760000, .max = 3510000 },
275 .n = { .min = 1, .max = 3 },
276 .m = { .min = 79, .max = 127 },
277 .m1 = { .min = 12, .max = 22 },
278 .m2 = { .min = 5, .max = 9 },
279 .p = { .min = 14, .max = 56 },
280 .p1 = { .min = 2, .max = 8 },
281 .p2 = { .dot_limit = 225000,
282 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 283};
284
273e27ca 285/* LVDS 100mhz refclk limits. */
b91ad0ec 286static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 287 .dot = { .min = 25000, .max = 350000 },
288 .vco = { .min = 1760000, .max = 3510000 },
289 .n = { .min = 1, .max = 2 },
290 .m = { .min = 79, .max = 126 },
291 .m1 = { .min = 12, .max = 22 },
292 .m2 = { .min = 5, .max = 9 },
293 .p = { .min = 28, .max = 112 },
0206e353 294 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 295 .p2 = { .dot_limit = 225000,
296 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 297};
298
299static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 300 .dot = { .min = 25000, .max = 350000 },
301 .vco = { .min = 1760000, .max = 3510000 },
302 .n = { .min = 1, .max = 3 },
303 .m = { .min = 79, .max = 126 },
304 .m1 = { .min = 12, .max = 22 },
305 .m2 = { .min = 5, .max = 9 },
306 .p = { .min = 14, .max = 42 },
0206e353 307 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 308 .p2 = { .dot_limit = 225000,
309 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 310};
311
a0c4da24
JB		 312static const intel_limit_t intel_limits_vlv_dac = {
313 .dot = { .min = 25000, .max = 270000 },
314 .vco = { .min = 4000000, .max = 6000000 },
315 .n = { .min = 1, .max = 7 },
316 .m = { .min = 22, .max = 450 }, /* guess */
317 .m1 = { .min = 2, .max = 3 },
318 .m2 = { .min = 11, .max = 156 },
319 .p = { .min = 10, .max = 30 },
75e53986 320 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 321 .p2 = { .dot_limit = 270000,
322 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 323};
324
325static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 326 .dot = { .min = 25000, .max = 270000 },
327 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 328 .n = { .min = 1, .max = 7 },
329 .m = { .min = 60, .max = 300 }, /* guess */
330 .m1 = { .min = 2, .max = 3 },
331 .m2 = { .min = 11, .max = 156 },
332 .p = { .min = 10, .max = 30 },
333 .p1 = { .min = 2, .max = 3 },
334 .p2 = { .dot_limit = 270000,
335 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 336};
337
e0638cdf
PZ		 338/**
339 * Returns whether any output on the specified pipe is of the specified type
340 */
341static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
342{
343 struct drm_device *dev = crtc->dev;
344 struct intel_encoder *encoder;
345
346 for_each_encoder_on_crtc(dev, crtc, encoder)
347 if (encoder->type == type)
348 return true;
349
350 return false;
351}
352
1b894b59
CW		 353static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
354 int refclk)
2c07245f 355{
b91ad0ec 356 struct drm_device *dev = crtc->dev;
2c07245f 357 const intel_limit_t *limit;
b91ad0ec
ZW		 358
359 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 360 if (intel_is_dual_link_lvds(dev)) {
1b894b59 361 if (refclk == 100000)
b91ad0ec
ZW		 362 limit = &intel_limits_ironlake_dual_lvds_100m;
363 else
364 limit = &intel_limits_ironlake_dual_lvds;
365 } else {
1b894b59 366 if (refclk == 100000)
b91ad0ec
ZW		 367 limit = &intel_limits_ironlake_single_lvds_100m;
368 else
369 limit = &intel_limits_ironlake_single_lvds;
370 }
c6bb3538 371 } else
b91ad0ec 372 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 373
374 return limit;
375}
376
044c7c41
ML		 377static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
378{
379 struct drm_device *dev = crtc->dev;
044c7c41
ML		 380 const intel_limit_t *limit;
381
382 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 383 if (intel_is_dual_link_lvds(dev))
e4b36699 384 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 385 else
e4b36699 386 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 387 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
388 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 389 limit = &intel_limits_g4x_hdmi;
044c7c41 390 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 391 limit = &intel_limits_g4x_sdvo;
044c7c41 392 } else /* The option is for other outputs */
e4b36699 393 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 394
395 return limit;
396}
397
1b894b59 398static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 399{
400 struct drm_device *dev = crtc->dev;
401 const intel_limit_t *limit;
402
bad720ff 403 if (HAS_PCH_SPLIT(dev))
1b894b59 404 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 405 else if (IS_G4X(dev)) {
044c7c41 406 limit = intel_g4x_limit(crtc);
f2b115e6 407 } else if (IS_PINEVIEW(dev)) {
2177832f 408 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 409 limit = &intel_limits_pineview_lvds;
2177832f 410 else
f2b115e6 411 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 412 } else if (IS_VALLEYVIEW(dev)) {
413 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
414 limit = &intel_limits_vlv_dac;
a0c4da24 415 else
65ce4bf5 416 limit = &intel_limits_vlv_hdmi;
a6c45cf0
CW		 417 } else if (!IS_GEN2(dev)) {
418 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
419 limit = &intel_limits_i9xx_lvds;
420 else
421 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 422 } else {
423 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 424 limit = &intel_limits_i8xx_lvds;
5d536e28 425 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
e4b36699 426 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 427 else
428 limit = &intel_limits_i8xx_dac;
79e53945
JB		 429 }
430 return limit;
431}
432
f2b115e6
AJ		 433/* m1 is reserved as 0 in Pineview, n is a ring counter */
434static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 435{
2177832f
SL		 436 clock->m = clock->m2 + 2;
437 clock->p = clock->p1 * clock->p2;
438 clock->vco = refclk * clock->m / clock->n;
439 clock->dot = clock->vco / clock->p;
440}
441
7429e9d4
DV		 442static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
443{
444 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
445}
446
ac58c3f0 447static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 448{
7429e9d4 449 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 450 clock->p = clock->p1 * clock->p2;
451 clock->vco = refclk * clock->m / (clock->n + 2);
452 clock->dot = clock->vco / clock->p;
453}
454
7c04d1d9 455#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 456/**
457 * Returns whether the given set of divisors are valid for a given refclk with
458 * the given connectors.
459 */
460
1b894b59
CW		 461static bool intel_PLL_is_valid(struct drm_device *dev,
462 const intel_limit_t *limit,
463 const intel_clock_t *clock)
79e53945 464{
79e53945 465 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 466 INTELPllInvalid("p1 out of range\n");
79e53945 467 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 468 INTELPllInvalid("p out of range\n");
79e53945 469 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 470 INTELPllInvalid("m2 out of range\n");
79e53945 471 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 472 INTELPllInvalid("m1 out of range\n");
f2b115e6 473 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 474 INTELPllInvalid("m1 <= m2\n");
79e53945 475 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 476 INTELPllInvalid("m out of range\n");
79e53945 477 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 478 INTELPllInvalid("n out of range\n");
79e53945 479 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 480 INTELPllInvalid("vco out of range\n");
79e53945
JB		 481 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
482 * connector, etc., rather than just a single range.
483 */
484 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 485 INTELPllInvalid("dot out of range\n");
79e53945
JB		 486
487 return true;
488}
489
d4906093 490static bool
ee9300bb 491i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 492 int target, int refclk, intel_clock_t *match_clock,
493 intel_clock_t *best_clock)
79e53945
JB		 494{
495 struct drm_device *dev = crtc->dev;
79e53945 496 intel_clock_t clock;
79e53945
JB		 497 int err = target;
498
a210b028 499 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 500 /*
a210b028
DV		 501 * For LVDS just rely on its current settings for dual-channel.
502 * We haven't figured out how to reliably set up different
503 * single/dual channel state, if we even can.
79e53945 504 */
1974cad0 505 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 506 clock.p2 = limit->p2.p2_fast;
507 else
508 clock.p2 = limit->p2.p2_slow;
509 } else {
510 if (target < limit->p2.dot_limit)
511 clock.p2 = limit->p2.p2_slow;
512 else
513 clock.p2 = limit->p2.p2_fast;
514 }
515
0206e353 516 memset(best_clock, 0, sizeof(*best_clock));
79e53945 517
42158660
ZY		 518 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
519 clock.m1++) {
520 for (clock.m2 = limit->m2.min;
521 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 522 if (clock.m2 >= clock.m1)
42158660
ZY		 523 break;
524 for (clock.n = limit->n.min;
525 clock.n <= limit->n.max; clock.n++) {
526 for (clock.p1 = limit->p1.min;
527 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 528 int this_err;
529
ac58c3f0
DV		 530 i9xx_clock(refclk, &clock);
531 if (!intel_PLL_is_valid(dev, limit,
532 &clock))
533 continue;
534 if (match_clock &&
535 clock.p != match_clock->p)
536 continue;
537
538 this_err = abs(clock.dot - target);
539 if (this_err < err) {
540 *best_clock = clock;
541 err = this_err;
542 }
543 }
544 }
545 }
546 }
547
548 return (err != target);
549}
550
551static bool
ee9300bb
DV		 552pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
553 int target, int refclk, intel_clock_t *match_clock,
554 intel_clock_t *best_clock)
79e53945
JB		 555{
556 struct drm_device *dev = crtc->dev;
79e53945 557 intel_clock_t clock;
79e53945
JB		 558 int err = target;
559
a210b028 560 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 561 /*
a210b028
DV		 562 * For LVDS just rely on its current settings for dual-channel.
563 * We haven't figured out how to reliably set up different
564 * single/dual channel state, if we even can.
79e53945 565 */
1974cad0 566 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 567 clock.p2 = limit->p2.p2_fast;
568 else
569 clock.p2 = limit->p2.p2_slow;
570 } else {
571 if (target < limit->p2.dot_limit)
572 clock.p2 = limit->p2.p2_slow;
573 else
574 clock.p2 = limit->p2.p2_fast;
575 }
576
0206e353 577 memset(best_clock, 0, sizeof(*best_clock));
79e53945 578
42158660
ZY		 579 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
580 clock.m1++) {
581 for (clock.m2 = limit->m2.min;
582 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 583 for (clock.n = limit->n.min;
584 clock.n <= limit->n.max; clock.n++) {
585 for (clock.p1 = limit->p1.min;
586 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 587 int this_err;
588
ac58c3f0 589 pineview_clock(refclk, &clock);
1b894b59
CW		 590 if (!intel_PLL_is_valid(dev, limit,
591 &clock))
79e53945 592 continue;
cec2f356
SP		 593 if (match_clock &&
594 clock.p != match_clock->p)
595 continue;
79e53945
JB		 596
597 this_err = abs(clock.dot - target);
598 if (this_err < err) {
599 *best_clock = clock;
600 err = this_err;
601 }
602 }
603 }
604 }
605 }
606
607 return (err != target);
608}
609
d4906093 610static bool
ee9300bb
DV		 611g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
612 int target, int refclk, intel_clock_t *match_clock,
613 intel_clock_t *best_clock)
d4906093
ML		 614{
615 struct drm_device *dev = crtc->dev;
d4906093
ML		 616 intel_clock_t clock;
617 int max_n;
618 bool found;
6ba770dc
AJ		 619 /* approximately equals target * 0.00585 */
620 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 621 found = false;
622
623 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 624 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 625 clock.p2 = limit->p2.p2_fast;
626 else
627 clock.p2 = limit->p2.p2_slow;
628 } else {
629 if (target < limit->p2.dot_limit)
630 clock.p2 = limit->p2.p2_slow;
631 else
632 clock.p2 = limit->p2.p2_fast;
633 }
634
635 memset(best_clock, 0, sizeof(*best_clock));
636 max_n = limit->n.max;
f77f13e2 637 /* based on hardware requirement, prefer smaller n to precision */
d4906093 638 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 639 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 640 for (clock.m1 = limit->m1.max;
641 clock.m1 >= limit->m1.min; clock.m1--) {
642 for (clock.m2 = limit->m2.max;
643 clock.m2 >= limit->m2.min; clock.m2--) {
644 for (clock.p1 = limit->p1.max;
645 clock.p1 >= limit->p1.min; clock.p1--) {
646 int this_err;
647
ac58c3f0 648 i9xx_clock(refclk, &clock);
1b894b59
CW		 649 if (!intel_PLL_is_valid(dev, limit,
650 &clock))
d4906093 651 continue;
1b894b59
CW		 652
653 this_err = abs(clock.dot - target);
d4906093
ML		 654 if (this_err < err_most) {
655 *best_clock = clock;
656 err_most = this_err;
657 max_n = clock.n;
658 found = true;
659 }
660 }
661 }
662 }
663 }
2c07245f
ZW		 664 return found;
665}
666
a0c4da24 667static bool
ee9300bb
DV		 668vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
669 int target, int refclk, intel_clock_t *match_clock,
670 intel_clock_t *best_clock)
a0c4da24
JB		 671{
672 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
673 u32 m, n, fastclk;
f3f08572 674 u32 updrate, minupdate, p;
a0c4da24
JB		 675 unsigned long bestppm, ppm, absppm;
676 int dotclk, flag;
677
af447bd3 678 flag = 0;
a0c4da24
JB		 679 dotclk = target * 1000;
680 bestppm = 1000000;
681 ppm = absppm = 0;
682 fastclk = dotclk / (2*100);
683 updrate = 0;
684 minupdate = 19200;
a0c4da24
JB		 685 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
686 bestm1 = bestm2 = bestp1 = bestp2 = 0;
687
688 /* based on hardware requirement, prefer smaller n to precision */
689 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
690 updrate = refclk / n;
691 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
692 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
693 if (p2 > 10)
694 p2 = p2 - 1;
695 p = p1 * p2;
696 /* based on hardware requirement, prefer bigger m1,m2 values */
697 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
698 m2 = (((2*(fastclk * p * n / m1 )) +
699 refclk) / (2*refclk));
700 m = m1 * m2;
701 vco = updrate * m;
43b0ac53
VS		 702
703 if (vco < limit->vco.min || vco >= limit->vco.max)
704 continue;
705
706 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
707 absppm = (ppm > 0) ? ppm : (-ppm);
708 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
709 bestppm = 0;
710 flag = 1;
711 }
712 if (absppm < bestppm - 10) {
713 bestppm = absppm;
714 flag = 1;
715 }
716 if (flag) {
717 bestn = n;
718 bestm1 = m1;
719 bestm2 = m2;
720 bestp1 = p1;
721 bestp2 = p2;
722 flag = 0;
a0c4da24
JB		 723 }
724 }
725 }
726 }
727 }
728 best_clock->n = bestn;
729 best_clock->m1 = bestm1;
730 best_clock->m2 = bestm2;
731 best_clock->p1 = bestp1;
732 best_clock->p2 = bestp2;
733
734 return true;
735}
a4fc5ed6 736
20ddf665
VS		 737bool intel_crtc_active(struct drm_crtc *crtc)
738{
739 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
740
741 /* Be paranoid as we can arrive here with only partial
742 * state retrieved from the hardware during setup.
743 *
241bfc38 744 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 745 * as Haswell has gained clock readout/fastboot support.
746 *
747 * We can ditch the crtc->fb check as soon as we can
748 * properly reconstruct framebuffers.
749 */
750 return intel_crtc->active && crtc->fb &&
241bfc38 751 intel_crtc->config.adjusted_mode.crtc_clock;
20ddf665
VS		 752}
753
a5c961d1
PZ		 754enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
755 enum pipe pipe)
756{
757 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
758 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
759
3b117c8f 760 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 761}
762
a928d536
PZ		 763static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
764{
765 struct drm_i915_private *dev_priv = dev->dev_private;
766 u32 frame, frame_reg = PIPEFRAME(pipe);
767
768 frame = I915_READ(frame_reg);
769
770 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
771 DRM_DEBUG_KMS("vblank wait timed out\n");
772}
773
9d0498a2
JB		 774/**
775 * intel_wait_for_vblank - wait for vblank on a given pipe
776 * @dev: drm device
777 * @pipe: pipe to wait for
778 *
779 * Wait for vblank to occur on a given pipe. Needed for various bits of
780 * mode setting code.
781 */
782void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 783{
9d0498a2 784 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 785 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 786
a928d536
PZ		 787 if (INTEL_INFO(dev)->gen >= 5) {
788 ironlake_wait_for_vblank(dev, pipe);
789 return;
790 }
791
300387c0
CW		 792 /* Clear existing vblank status. Note this will clear any other
793 * sticky status fields as well.
794 *
795 * This races with i915_driver_irq_handler() with the result
796 * that either function could miss a vblank event. Here it is not
797 * fatal, as we will either wait upon the next vblank interrupt or
798 * timeout. Generally speaking intel_wait_for_vblank() is only
799 * called during modeset at which time the GPU should be idle and
800 * should *not* be performing page flips and thus not waiting on
801 * vblanks...
802 * Currently, the result of us stealing a vblank from the irq
803 * handler is that a single frame will be skipped during swapbuffers.
804 */
805 I915_WRITE(pipestat_reg,
806 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
807
9d0498a2 808 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 809 if (wait_for(I915_READ(pipestat_reg) &
810 PIPE_VBLANK_INTERRUPT_STATUS,
811 50))
9d0498a2
JB		 812 DRM_DEBUG_KMS("vblank wait timed out\n");
813}
814
ab7ad7f6
KP		 815/*
816 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 817 * @dev: drm device
818 * @pipe: pipe to wait for
819 *
820 * After disabling a pipe, we can't wait for vblank in the usual way,
821 * spinning on the vblank interrupt status bit, since we won't actually
822 * see an interrupt when the pipe is disabled.
823 *
ab7ad7f6
KP		 824 * On Gen4 and above:
825 * wait for the pipe register state bit to turn off
826 *
827 * Otherwise:
828 * wait for the display line value to settle (it usually
829 * ends up stopping at the start of the next frame).
58e10eb9 830 *
9d0498a2 831 */
58e10eb9 832void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 833{
834 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 835 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
836 pipe);
ab7ad7f6
KP		 837
838 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 839 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 840
841 /* Wait for the Pipe State to go off */
58e10eb9
CW		 842 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
843 100))
284637d9 844 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 845 } else {
837ba00f 846 u32 last_line, line_mask;
58e10eb9 847 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 848 unsigned long timeout = jiffies + msecs_to_jiffies(100);
849
837ba00f
PZ		 850 if (IS_GEN2(dev))
851 line_mask = DSL_LINEMASK_GEN2;
852 else
853 line_mask = DSL_LINEMASK_GEN3;
854
ab7ad7f6
KP		 855 /* Wait for the display line to settle */
856 do {
837ba00f 857 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 858 mdelay(5);
837ba00f 859 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 860 time_after(timeout, jiffies));
861 if (time_after(jiffies, timeout))
284637d9 862 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 863 }
79e53945
JB		 864}
865
b0ea7d37
DL		 866/*
867 * ibx_digital_port_connected - is the specified port connected?
868 * @dev_priv: i915 private structure
869 * @port: the port to test
870 *
871 * Returns true if @port is connected, false otherwise.
872 */
873bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
874 struct intel_digital_port *port)
875{
876 u32 bit;
877
c36346e3
DL		 878 if (HAS_PCH_IBX(dev_priv->dev)) {
879 switch(port->port) {
880 case PORT_B:
881 bit = SDE_PORTB_HOTPLUG;
882 break;
883 case PORT_C:
884 bit = SDE_PORTC_HOTPLUG;
885 break;
886 case PORT_D:
887 bit = SDE_PORTD_HOTPLUG;
888 break;
889 default:
890 return true;
891 }
892 } else {
893 switch(port->port) {
894 case PORT_B:
895 bit = SDE_PORTB_HOTPLUG_CPT;
896 break;
897 case PORT_C:
898 bit = SDE_PORTC_HOTPLUG_CPT;
899 break;
900 case PORT_D:
901 bit = SDE_PORTD_HOTPLUG_CPT;
902 break;
903 default:
904 return true;
905 }
b0ea7d37
DL		 906 }
907
908 return I915_READ(SDEISR) & bit;
909}
910
b24e7179
JB		 911static const char *state_string(bool enabled)
912{
913 return enabled ? "on" : "off";
914}
915
916/* Only for pre-ILK configs */
55607e8a
DV		 917void assert_pll(struct drm_i915_private *dev_priv,
918 enum pipe pipe, bool state)
b24e7179
JB		 919{
920 int reg;
921 u32 val;
922 bool cur_state;
923
924 reg = DPLL(pipe);
925 val = I915_READ(reg);
926 cur_state = !!(val & DPLL_VCO_ENABLE);
927 WARN(cur_state != state,
928 "PLL state assertion failure (expected %s, current %s)\n",
929 state_string(state), state_string(cur_state));
930}
b24e7179 931
23538ef1
JN		 932/* XXX: the dsi pll is shared between MIPI DSI ports */
933static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
934{
935 u32 val;
936 bool cur_state;
937
938 mutex_lock(&dev_priv->dpio_lock);
939 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
940 mutex_unlock(&dev_priv->dpio_lock);
941
942 cur_state = val & DSI_PLL_VCO_EN;
943 WARN(cur_state != state,
944 "DSI PLL state assertion failure (expected %s, current %s)\n",
945 state_string(state), state_string(cur_state));
946}
947#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
948#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
949
55607e8a 950struct intel_shared_dpll *
e2b78267
DV		 951intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
952{
953 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
954
a43f6e0f 955 if (crtc->config.shared_dpll < 0)
e2b78267
DV		 956 return NULL;
957
a43f6e0f 958 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
e2b78267
DV		 959}
960
040484af 961/* For ILK+ */
55607e8a
DV		 962void assert_shared_dpll(struct drm_i915_private *dev_priv,
963 struct intel_shared_dpll *pll,
964 bool state)
040484af 965{
040484af 966 bool cur_state;
5358901f 967 struct intel_dpll_hw_state hw_state;
040484af 968
9d82aa17
ED		 969 if (HAS_PCH_LPT(dev_priv->dev)) {
970 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
971 return;
972 }
973
92b27b08 974 if (WARN (!pll,
46edb027 975 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 976 return;
ee7b9f93 977
5358901f 978 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
92b27b08 979 WARN(cur_state != state,
5358901f
DV		 980 "%s assertion failure (expected %s, current %s)\n",
981 pll->name, state_string(state), state_string(cur_state));
040484af 982}
040484af
JB		 983
984static void assert_fdi_tx(struct drm_i915_private *dev_priv,
985 enum pipe pipe, bool state)
986{
987 int reg;
988 u32 val;
989 bool cur_state;
ad80a810
PZ		 990 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
991 pipe);
040484af 992
affa9354
PZ		 993 if (HAS_DDI(dev_priv->dev)) {
994 /* DDI does not have a specific FDI_TX register */
ad80a810 995 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 996 val = I915_READ(reg);
ad80a810 997 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 998 } else {
999 reg = FDI_TX_CTL(pipe);
1000 val = I915_READ(reg);
1001 cur_state = !!(val & FDI_TX_ENABLE);
1002 }
040484af
JB		 1003 WARN(cur_state != state,
1004 "FDI TX state assertion failure (expected %s, current %s)\n",
1005 state_string(state), state_string(cur_state));
1006}
1007#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1008#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1009
1010static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1011 enum pipe pipe, bool state)
1012{
1013 int reg;
1014 u32 val;
1015 bool cur_state;
1016
d63fa0dc
PZ		 1017 reg = FDI_RX_CTL(pipe);
1018 val = I915_READ(reg);
1019 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1020 WARN(cur_state != state,
1021 "FDI RX state assertion failure (expected %s, current %s)\n",
1022 state_string(state), state_string(cur_state));
1023}
1024#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1025#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1026
1027static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1028 enum pipe pipe)
1029{
1030 int reg;
1031 u32 val;
1032
1033 /* ILK FDI PLL is always enabled */
1034 if (dev_priv->info->gen == 5)
1035 return;
1036
bf507ef7 1037 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1038 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1039 return;
1040
040484af
JB		 1041 reg = FDI_TX_CTL(pipe);
1042 val = I915_READ(reg);
1043 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1044}
1045
55607e8a
DV		 1046void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1047 enum pipe pipe, bool state)
040484af
JB		 1048{
1049 int reg;
1050 u32 val;
55607e8a 1051 bool cur_state;
040484af
JB		 1052
1053 reg = FDI_RX_CTL(pipe);
1054 val = I915_READ(reg);
55607e8a
DV		 1055 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1056 WARN(cur_state != state,
1057 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1058 state_string(state), state_string(cur_state));
040484af
JB		 1059}
1060
ea0760cf
JB		 1061static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1062 enum pipe pipe)
1063{
1064 int pp_reg, lvds_reg;
1065 u32 val;
1066 enum pipe panel_pipe = PIPE_A;
0de3b485 1067 bool locked = true;
ea0760cf
JB		 1068
1069 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1070 pp_reg = PCH_PP_CONTROL;
1071 lvds_reg = PCH_LVDS;
1072 } else {
1073 pp_reg = PP_CONTROL;
1074 lvds_reg = LVDS;
1075 }
1076
1077 val = I915_READ(pp_reg);
1078 if (!(val & PANEL_POWER_ON) ||
1079 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1080 locked = false;
1081
1082 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1083 panel_pipe = PIPE_B;
1084
1085 WARN(panel_pipe == pipe && locked,
1086 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1087 pipe_name(pipe));
ea0760cf
JB		 1088}
1089
93ce0ba6
JN		 1090static void assert_cursor(struct drm_i915_private *dev_priv,
1091 enum pipe pipe, bool state)
1092{
1093 struct drm_device *dev = dev_priv->dev;
1094 bool cur_state;
1095
1096 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1097 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1098 else if (IS_845G(dev) || IS_I865G(dev))
1099 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1100 else
1101 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1102
1103 WARN(cur_state != state,
1104 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1105 pipe_name(pipe), state_string(state), state_string(cur_state));
1106}
1107#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1108#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1109
b840d907
JB		 1110void assert_pipe(struct drm_i915_private *dev_priv,
1111 enum pipe pipe, bool state)
b24e7179
JB		 1112{
1113 int reg;
1114 u32 val;
63d7bbe9 1115 bool cur_state;
702e7a56
PZ		 1116 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1117 pipe);
b24e7179 1118
8e636784
DV		 1119 /* if we need the pipe A quirk it must be always on */
1120 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1121 state = true;
1122
b97186f0
PZ		 1123 if (!intel_display_power_enabled(dev_priv->dev,
1124 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1125 cur_state = false;
1126 } else {
1127 reg = PIPECONF(cpu_transcoder);
1128 val = I915_READ(reg);
1129 cur_state = !!(val & PIPECONF_ENABLE);
1130 }
1131
63d7bbe9
JB		 1132 WARN(cur_state != state,
1133 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1134 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1135}
1136
931872fc
CW		 1137static void assert_plane(struct drm_i915_private *dev_priv,
1138 enum plane plane, bool state)
b24e7179
JB		 1139{
1140 int reg;
1141 u32 val;
931872fc 1142 bool cur_state;
b24e7179
JB		 1143
1144 reg = DSPCNTR(plane);
1145 val = I915_READ(reg);
931872fc
CW		 1146 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1147 WARN(cur_state != state,
1148 "plane %c assertion failure (expected %s, current %s)\n",
1149 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1150}
1151
931872fc
CW		 1152#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1153#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1154
b24e7179
JB		 1155static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1156 enum pipe pipe)
1157{
653e1026 1158 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1159 int reg, i;
1160 u32 val;
1161 int cur_pipe;
1162
653e1026
VS		 1163 /* Primary planes are fixed to pipes on gen4+ */
1164 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1165 reg = DSPCNTR(pipe);
1166 val = I915_READ(reg);
1167 WARN((val & DISPLAY_PLANE_ENABLE),
1168 "plane %c assertion failure, should be disabled but not\n",
1169 plane_name(pipe));
19ec1358 1170 return;
28c05794 1171 }
19ec1358 1172
b24e7179 1173 /* Need to check both planes against the pipe */
08e2a7de 1174 for_each_pipe(i) {
b24e7179
JB		 1175 reg = DSPCNTR(i);
1176 val = I915_READ(reg);
1177 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1178 DISPPLANE_SEL_PIPE_SHIFT;
1179 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1180 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1181 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1182 }
1183}
1184
19332d7a
JB		 1185static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1186 enum pipe pipe)
1187{
20674eef 1188 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1189 int reg, i;
1190 u32 val;
1191
20674eef
VS		 1192 if (IS_VALLEYVIEW(dev)) {
1193 for (i = 0; i < dev_priv->num_plane; i++) {
1194 reg = SPCNTR(pipe, i);
1195 val = I915_READ(reg);
1196 WARN((val & SP_ENABLE),
1197 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1198 sprite_name(pipe, i), pipe_name(pipe));
1199 }
1200 } else if (INTEL_INFO(dev)->gen >= 7) {
1201 reg = SPRCTL(pipe);
19332d7a 1202 val = I915_READ(reg);
20674eef 1203 WARN((val & SPRITE_ENABLE),
06da8da2 1204 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1205 plane_name(pipe), pipe_name(pipe));
1206 } else if (INTEL_INFO(dev)->gen >= 5) {
1207 reg = DVSCNTR(pipe);
19332d7a 1208 val = I915_READ(reg);
20674eef 1209 WARN((val & DVS_ENABLE),
06da8da2 1210 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1211 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1212 }
1213}
1214
92f2584a
JB		 1215static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1216{
1217 u32 val;
1218 bool enabled;
1219
9d82aa17
ED		 1220 if (HAS_PCH_LPT(dev_priv->dev)) {
1221 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1222 return;
1223 }
1224
92f2584a
JB		 1225 val = I915_READ(PCH_DREF_CONTROL);
1226 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1227 DREF_SUPERSPREAD_SOURCE_MASK));
1228 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1229}
1230
ab9412ba
DV		 1231static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1232 enum pipe pipe)
92f2584a
JB		 1233{
1234 int reg;
1235 u32 val;
1236 bool enabled;
1237
ab9412ba 1238 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1239 val = I915_READ(reg);
1240 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1241 WARN(enabled,
1242 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1243 pipe_name(pipe));
92f2584a
JB		 1244}
1245
4e634389
KP		 1246static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1247 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1248{
1249 if ((val & DP_PORT_EN) == 0)
1250 return false;
1251
1252 if (HAS_PCH_CPT(dev_priv->dev)) {
1253 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1254 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1255 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1256 return false;
1257 } else {
1258 if ((val & DP_PIPE_MASK) != (pipe << 30))
1259 return false;
1260 }
1261 return true;
1262}
1263
1519b995
KP		 1264static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1265 enum pipe pipe, u32 val)
1266{
dc0fa718 1267 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1268 return false;
1269
1270 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1271 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1272 return false;
1273 } else {
dc0fa718 1274 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1275 return false;
1276 }
1277 return true;
1278}
1279
1280static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1281 enum pipe pipe, u32 val)
1282{
1283 if ((val & LVDS_PORT_EN) == 0)
1284 return false;
1285
1286 if (HAS_PCH_CPT(dev_priv->dev)) {
1287 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1288 return false;
1289 } else {
1290 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1291 return false;
1292 }
1293 return true;
1294}
1295
1296static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1297 enum pipe pipe, u32 val)
1298{
1299 if ((val & ADPA_DAC_ENABLE) == 0)
1300 return false;
1301 if (HAS_PCH_CPT(dev_priv->dev)) {
1302 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1303 return false;
1304 } else {
1305 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1306 return false;
1307 }
1308 return true;
1309}
1310
291906f1 1311static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1312 enum pipe pipe, int reg, u32 port_sel)
291906f1 1313{
47a05eca 1314 u32 val = I915_READ(reg);
4e634389 1315 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1316 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1317 reg, pipe_name(pipe));
de9a35ab 1318
75c5da27
DV		 1319 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1320 && (val & DP_PIPEB_SELECT),
de9a35ab 1321 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1322}
1323
1324static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1325 enum pipe pipe, int reg)
1326{
47a05eca 1327 u32 val = I915_READ(reg);
b70ad586 1328 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1329 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1330 reg, pipe_name(pipe));
de9a35ab 1331
dc0fa718 1332 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1333 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1334 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1335}
1336
1337static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1338 enum pipe pipe)
1339{
1340 int reg;
1341 u32 val;
291906f1 1342
f0575e92
KP		 1343 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1344 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1345 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1346
1347 reg = PCH_ADPA;
1348 val = I915_READ(reg);
b70ad586 1349 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1350 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1351 pipe_name(pipe));
291906f1
JB		 1352
1353 reg = PCH_LVDS;
1354 val = I915_READ(reg);
b70ad586 1355 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1356 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1357 pipe_name(pipe));
291906f1 1358
e2debe91
PZ		 1359 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1360 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1361 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1362}
1363
426115cf 1364static void vlv_enable_pll(struct intel_crtc *crtc)
87442f73 1365{
426115cf
DV		 1366 struct drm_device *dev = crtc->base.dev;
1367 struct drm_i915_private *dev_priv = dev->dev_private;
1368 int reg = DPLL(crtc->pipe);
1369 u32 dpll = crtc->config.dpll_hw_state.dpll;
87442f73 1370
426115cf 1371 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1372
1373 /* No really, not for ILK+ */
1374 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1375
1376 /* PLL is protected by panel, make sure we can write it */
1377 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
426115cf 1378 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1379
426115cf
DV		 1380 I915_WRITE(reg, dpll);
1381 POSTING_READ(reg);
1382 udelay(150);
1383
1384 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1385 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1386
1387 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1388 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1389
1390 /* We do this three times for luck */
426115cf 1391 I915_WRITE(reg, dpll);
87442f73
DV		 1392 POSTING_READ(reg);
1393 udelay(150); /* wait for warmup */
426115cf 1394 I915_WRITE(reg, dpll);
87442f73
DV		 1395 POSTING_READ(reg);
1396 udelay(150); /* wait for warmup */
426115cf 1397 I915_WRITE(reg, dpll);
87442f73
DV		 1398 POSTING_READ(reg);
1399 udelay(150); /* wait for warmup */
1400}
1401
66e3d5c0 1402static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1403{
66e3d5c0
DV		 1404 struct drm_device *dev = crtc->base.dev;
1405 struct drm_i915_private *dev_priv = dev->dev_private;
1406 int reg = DPLL(crtc->pipe);
1407 u32 dpll = crtc->config.dpll_hw_state.dpll;
63d7bbe9 1408
66e3d5c0 1409 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1410
63d7bbe9 1411 /* No really, not for ILK+ */
87442f73 1412 BUG_ON(dev_priv->info->gen >= 5);
63d7bbe9
JB		 1413
1414 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1415 if (IS_MOBILE(dev) && !IS_I830(dev))
1416 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1417
66e3d5c0
DV		 1418 I915_WRITE(reg, dpll);
1419
1420 /* Wait for the clocks to stabilize. */
1421 POSTING_READ(reg);
1422 udelay(150);
1423
1424 if (INTEL_INFO(dev)->gen >= 4) {
1425 I915_WRITE(DPLL_MD(crtc->pipe),
1426 crtc->config.dpll_hw_state.dpll_md);
1427 } else {
1428 /* The pixel multiplier can only be updated once the
1429 * DPLL is enabled and the clocks are stable.
1430 *
1431 * So write it again.
1432 */
1433 I915_WRITE(reg, dpll);
1434 }
63d7bbe9
JB		 1435
1436 /* We do this three times for luck */
66e3d5c0 1437 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1438 POSTING_READ(reg);
1439 udelay(150); /* wait for warmup */
66e3d5c0 1440 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1441 POSTING_READ(reg);
1442 udelay(150); /* wait for warmup */
66e3d5c0 1443 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1444 POSTING_READ(reg);
1445 udelay(150); /* wait for warmup */
1446}
1447
1448/**
50b44a44 1449 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1450 * @dev_priv: i915 private structure
1451 * @pipe: pipe PLL to disable
1452 *
1453 * Disable the PLL for @pipe, making sure the pipe is off first.
1454 *
1455 * Note! This is for pre-ILK only.
1456 */
50b44a44 1457static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9 1458{
63d7bbe9
JB		 1459 /* Don't disable pipe A or pipe A PLLs if needed */
1460 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1461 return;
1462
1463 /* Make sure the pipe isn't still relying on us */
1464 assert_pipe_disabled(dev_priv, pipe);
1465
50b44a44
DV		 1466 I915_WRITE(DPLL(pipe), 0);
1467 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1468}
1469
89b667f8
JB		 1470void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1471{
1472 u32 port_mask;
1473
1474 if (!port)
1475 port_mask = DPLL_PORTB_READY_MASK;
1476 else
1477 port_mask = DPLL_PORTC_READY_MASK;
1478
1479 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1480 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1481 'B' + port, I915_READ(DPLL(0)));
1482}
1483
92f2584a 1484/**
e72f9fbf 1485 * ironlake_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1486 * @dev_priv: i915 private structure
1487 * @pipe: pipe PLL to enable
1488 *
1489 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1490 * drives the transcoder clock.
1491 */
e2b78267 1492static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1493{
e2b78267
DV		 1494 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1495 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1496
48da64a8 1497 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1498 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1499 if (WARN_ON(pll == NULL))
48da64a8
CW		 1500 return;
1501
1502 if (WARN_ON(pll->refcount == 0))
1503 return;
ee7b9f93 1504
46edb027
DV		 1505 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1506 pll->name, pll->active, pll->on,
e2b78267 1507 crtc->base.base.id);
92f2584a 1508
cdbd2316
DV		 1509 if (pll->active++) {
1510 WARN_ON(!pll->on);
e9d6944e 1511 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1512 return;
1513 }
f4a091c7 1514 WARN_ON(pll->on);
ee7b9f93 1515
46edb027 1516 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1517 pll->enable(dev_priv, pll);
ee7b9f93 1518 pll->on = true;
92f2584a
JB		 1519}
1520
e2b78267 1521static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1522{
e2b78267
DV		 1523 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1524 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1525
92f2584a
JB		 1526 /* PCH only available on ILK+ */
1527 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1528 if (WARN_ON(pll == NULL))
ee7b9f93 1529 return;
92f2584a 1530
48da64a8
CW		 1531 if (WARN_ON(pll->refcount == 0))
1532 return;
7a419866 1533
46edb027
DV		 1534 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1535 pll->name, pll->active, pll->on,
e2b78267 1536 crtc->base.base.id);
7a419866 1537
48da64a8 1538 if (WARN_ON(pll->active == 0)) {
e9d6944e 1539 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1540 return;
1541 }
1542
e9d6944e 1543 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1544 WARN_ON(!pll->on);
cdbd2316 1545 if (--pll->active)
7a419866 1546 return;
ee7b9f93 1547
46edb027 1548 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1549 pll->disable(dev_priv, pll);
ee7b9f93 1550 pll->on = false;
92f2584a
JB		 1551}
1552
b8a4f404
PZ		 1553static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1554 enum pipe pipe)
040484af 1555{
23670b32 1556 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1557 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1559 uint32_t reg, val, pipeconf_val;
040484af
JB		 1560
1561 /* PCH only available on ILK+ */
1562 BUG_ON(dev_priv->info->gen < 5);
1563
1564 /* Make sure PCH DPLL is enabled */
e72f9fbf 1565 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1566 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1567
1568 /* FDI must be feeding us bits for PCH ports */
1569 assert_fdi_tx_enabled(dev_priv, pipe);
1570 assert_fdi_rx_enabled(dev_priv, pipe);
1571
23670b32
DV		 1572 if (HAS_PCH_CPT(dev)) {
1573 /* Workaround: Set the timing override bit before enabling the
1574 * pch transcoder. */
1575 reg = TRANS_CHICKEN2(pipe);
1576 val = I915_READ(reg);
1577 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1578 I915_WRITE(reg, val);
59c859d6 1579 }
23670b32 1580
ab9412ba 1581 reg = PCH_TRANSCONF(pipe);
040484af 1582 val = I915_READ(reg);
5f7f726d 1583 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1584
1585 if (HAS_PCH_IBX(dev_priv->dev)) {
1586 /*
1587 * make the BPC in transcoder be consistent with
1588 * that in pipeconf reg.
1589 */
dfd07d72
DV		 1590 val &= ~PIPECONF_BPC_MASK;
1591 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1592 }
5f7f726d
PZ		 1593
1594 val &= ~TRANS_INTERLACE_MASK;
1595 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1596 if (HAS_PCH_IBX(dev_priv->dev) &&
1597 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1598 val |= TRANS_LEGACY_INTERLACED_ILK;
1599 else
1600 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1601 else
1602 val |= TRANS_PROGRESSIVE;
1603
040484af
JB		 1604 I915_WRITE(reg, val | TRANS_ENABLE);
1605 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1606 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1607}
1608
8fb033d7 1609static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1610 enum transcoder cpu_transcoder)
040484af 1611{
8fb033d7 1612 u32 val, pipeconf_val;
8fb033d7
PZ		 1613
1614 /* PCH only available on ILK+ */
1615 BUG_ON(dev_priv->info->gen < 5);
1616
8fb033d7 1617 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1618 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1619 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1620
223a6fdf
PZ		 1621 /* Workaround: set timing override bit. */
1622 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1623 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1624 I915_WRITE(_TRANSA_CHICKEN2, val);
1625
25f3ef11 1626 val = TRANS_ENABLE;
937bb610 1627 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1628
9a76b1c6
PZ		 1629 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1630 PIPECONF_INTERLACED_ILK)
a35f2679 1631 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1632 else
1633 val |= TRANS_PROGRESSIVE;
1634
ab9412ba
DV		 1635 I915_WRITE(LPT_TRANSCONF, val);
1636 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1637 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1638}
1639
b8a4f404
PZ		 1640static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1641 enum pipe pipe)
040484af 1642{
23670b32
DV		 1643 struct drm_device *dev = dev_priv->dev;
1644 uint32_t reg, val;
040484af
JB		 1645
1646 /* FDI relies on the transcoder */
1647 assert_fdi_tx_disabled(dev_priv, pipe);
1648 assert_fdi_rx_disabled(dev_priv, pipe);
1649
291906f1
JB		 1650 /* Ports must be off as well */
1651 assert_pch_ports_disabled(dev_priv, pipe);
1652
ab9412ba 1653 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1654 val = I915_READ(reg);
1655 val &= ~TRANS_ENABLE;
1656 I915_WRITE(reg, val);
1657 /* wait for PCH transcoder off, transcoder state */
1658 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1659 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1660
1661 if (!HAS_PCH_IBX(dev)) {
1662 /* Workaround: Clear the timing override chicken bit again. */
1663 reg = TRANS_CHICKEN2(pipe);
1664 val = I915_READ(reg);
1665 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1666 I915_WRITE(reg, val);
1667 }
040484af
JB		 1668}
1669
ab4d966c 1670static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1671{
8fb033d7
PZ		 1672 u32 val;
1673
ab9412ba 1674 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1675 val &= ~TRANS_ENABLE;
ab9412ba 1676 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1677 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1678 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1679 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1680
1681 /* Workaround: clear timing override bit. */
1682 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1683 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1684 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1685}
1686
b24e7179 1687/**
309cfea8 1688 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1689 * @dev_priv: i915 private structure
1690 * @pipe: pipe to enable
040484af 1691 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1692 *
1693 * Enable @pipe, making sure that various hardware specific requirements
1694 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1695 *
1696 * @pipe should be %PIPE_A or %PIPE_B.
1697 *
1698 * Will wait until the pipe is actually running (i.e. first vblank) before
1699 * returning.
1700 */
040484af 1701static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
23538ef1 1702 bool pch_port, bool dsi)
b24e7179 1703{
702e7a56
PZ		 1704 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1705 pipe);
1a240d4d 1706 enum pipe pch_transcoder;
b24e7179
JB		 1707 int reg;
1708 u32 val;
1709
58c6eaa2 1710 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1711 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 1712 assert_sprites_disabled(dev_priv, pipe);
1713
681e5811 1714 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1715 pch_transcoder = TRANSCODER_A;
1716 else
1717 pch_transcoder = pipe;
1718
b24e7179
JB		 1719 /*
1720 * A pipe without a PLL won't actually be able to drive bits from
1721 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1722 * need the check.
1723 */
1724 if (!HAS_PCH_SPLIT(dev_priv->dev))
23538ef1
JN		 1725 if (dsi)
1726 assert_dsi_pll_enabled(dev_priv);
1727 else
1728 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1729 else {
1730 if (pch_port) {
1731 /* if driving the PCH, we need FDI enabled */
cc391bbb 1732 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1733 assert_fdi_tx_pll_enabled(dev_priv,
1734 (enum pipe) cpu_transcoder);
040484af
JB		 1735 }
1736 /* FIXME: assert CPU port conditions for SNB+ */
1737 }
b24e7179 1738
702e7a56 1739 reg = PIPECONF(cpu_transcoder);
b24e7179 1740 val = I915_READ(reg);
00d70b15
CW		 1741 if (val & PIPECONF_ENABLE)
1742 return;
1743
1744 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1745 intel_wait_for_vblank(dev_priv->dev, pipe);
1746}
1747
1748/**
309cfea8 1749 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1750 * @dev_priv: i915 private structure
1751 * @pipe: pipe to disable
1752 *
1753 * Disable @pipe, making sure that various hardware specific requirements
1754 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1755 *
1756 * @pipe should be %PIPE_A or %PIPE_B.
1757 *
1758 * Will wait until the pipe has shut down before returning.
1759 */
1760static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1761 enum pipe pipe)
1762{
702e7a56
PZ		 1763 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1764 pipe);
b24e7179
JB		 1765 int reg;
1766 u32 val;
1767
1768 /*
1769 * Make sure planes won't keep trying to pump pixels to us,
1770 * or we might hang the display.
1771 */
1772 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1773 assert_cursor_disabled(dev_priv, pipe);
19332d7a 1774 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1775
1776 /* Don't disable pipe A or pipe A PLLs if needed */
1777 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1778 return;
1779
702e7a56 1780 reg = PIPECONF(cpu_transcoder);
b24e7179 1781 val = I915_READ(reg);
00d70b15
CW		 1782 if ((val & PIPECONF_ENABLE) == 0)
1783 return;
1784
1785 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1786 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1787}
1788
d74362c9
KP		 1789/*
1790 * Plane regs are double buffered, going from enabled->disabled needs a
1791 * trigger in order to latch. The display address reg provides this.
1792 */
6f1d69b0 1793void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1794 enum plane plane)
1795{
14f86147
DL		 1796 if (dev_priv->info->gen >= 4)
1797 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1798 else
1799 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1800}
1801
b24e7179
JB		 1802/**
1803 * intel_enable_plane - enable a display plane on a given pipe
1804 * @dev_priv: i915 private structure
1805 * @plane: plane to enable
1806 * @pipe: pipe being fed
1807 *
1808 * Enable @plane on @pipe, making sure that @pipe is running first.
1809 */
1810static void intel_enable_plane(struct drm_i915_private *dev_priv,
1811 enum plane plane, enum pipe pipe)
1812{
1813 int reg;
1814 u32 val;
1815
1816 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1817 assert_pipe_enabled(dev_priv, pipe);
1818
1819 reg = DSPCNTR(plane);
1820 val = I915_READ(reg);
00d70b15
CW		 1821 if (val & DISPLAY_PLANE_ENABLE)
1822 return;
1823
1824 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1825 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1826 intel_wait_for_vblank(dev_priv->dev, pipe);
1827}
1828
b24e7179
JB		 1829/**
1830 * intel_disable_plane - disable a display plane
1831 * @dev_priv: i915 private structure
1832 * @plane: plane to disable
1833 * @pipe: pipe consuming the data
1834 *
1835 * Disable @plane; should be an independent operation.
1836 */
1837static void intel_disable_plane(struct drm_i915_private *dev_priv,
1838 enum plane plane, enum pipe pipe)
1839{
1840 int reg;
1841 u32 val;
1842
1843 reg = DSPCNTR(plane);
1844 val = I915_READ(reg);
00d70b15
CW		 1845 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1846 return;
1847
1848 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1849 intel_flush_display_plane(dev_priv, plane);
1850 intel_wait_for_vblank(dev_priv->dev, pipe);
1851}
1852
693db184
CW		 1853static bool need_vtd_wa(struct drm_device *dev)
1854{
1855#ifdef CONFIG_INTEL_IOMMU
1856 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1857 return true;
1858#endif
1859 return false;
1860}
1861
127bd2ac 1862int
48b956c5 1863intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1864 struct drm_i915_gem_object *obj,
919926ae 1865 struct intel_ring_buffer *pipelined)
6b95a207 1866{
ce453d81 1867 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1868 u32 alignment;
1869 int ret;
1870
05394f39 1871 switch (obj->tiling_mode) {
6b95a207 1872 case I915_TILING_NONE:
534843da
CW		 1873 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1874 alignment = 128 * 1024;
a6c45cf0 1875 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1876 alignment = 4 * 1024;
1877 else
1878 alignment = 64 * 1024;
6b95a207
KH		 1879 break;
1880 case I915_TILING_X:
1881 /* pin() will align the object as required by fence */
1882 alignment = 0;
1883 break;
1884 case I915_TILING_Y:
8bb6e959
DV		 1885 /* Despite that we check this in framebuffer_init userspace can
1886 * screw us over and change the tiling after the fact. Only
1887 * pinned buffers can't change their tiling. */
1888 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1889 return -EINVAL;
1890 default:
1891 BUG();
1892 }
1893
693db184
CW		 1894 /* Note that the w/a also requires 64 PTE of padding following the
1895 * bo. We currently fill all unused PTE with the shadow page and so
1896 * we should always have valid PTE following the scanout preventing
1897 * the VT-d warning.
1898 */
1899 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1900 alignment = 256 * 1024;
1901
ce453d81 1902 dev_priv->mm.interruptible = false;
2da3b9b9 1903 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1904 if (ret)
ce453d81 1905 goto err_interruptible;
6b95a207
KH		 1906
1907 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1908 * fence, whereas 965+ only requires a fence if using
1909 * framebuffer compression. For simplicity, we always install
1910 * a fence as the cost is not that onerous.
1911 */
06d98131 1912 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1913 if (ret)
1914 goto err_unpin;
1690e1eb 1915
9a5a53b3 1916 i915_gem_object_pin_fence(obj);
6b95a207 1917
ce453d81 1918 dev_priv->mm.interruptible = true;
6b95a207 1919 return 0;
48b956c5
CW		 1920
1921err_unpin:
cc98b413 1922 i915_gem_object_unpin_from_display_plane(obj);
ce453d81
CW		 1923err_interruptible:
1924 dev_priv->mm.interruptible = true;
48b956c5 1925 return ret;
6b95a207
KH		 1926}
1927
1690e1eb
CW		 1928void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1929{
1930 i915_gem_object_unpin_fence(obj);
cc98b413 1931 i915_gem_object_unpin_from_display_plane(obj);
1690e1eb
CW		 1932}
1933
c2c75131
DV		 1934/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1935 * is assumed to be a power-of-two. */
bc752862
CW		 1936unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1937 unsigned int tiling_mode,
1938 unsigned int cpp,
1939 unsigned int pitch)
c2c75131 1940{
bc752862
CW		 1941 if (tiling_mode != I915_TILING_NONE) {
1942 unsigned int tile_rows, tiles;
c2c75131 1943
bc752862
CW		 1944 tile_rows = *y / 8;
1945 *y %= 8;
c2c75131 1946
bc752862
CW		 1947 tiles = *x / (512/cpp);
1948 *x %= 512/cpp;
1949
1950 return tile_rows * pitch * 8 + tiles * 4096;
1951 } else {
1952 unsigned int offset;
1953
1954 offset = *y * pitch + *x * cpp;
1955 *y = 0;
1956 *x = (offset & 4095) / cpp;
1957 return offset & -4096;
1958 }
c2c75131
DV		 1959}
1960
17638cd6
JB		 1961static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1962 int x, int y)
81255565
JB		 1963{
1964 struct drm_device *dev = crtc->dev;
1965 struct drm_i915_private *dev_priv = dev->dev_private;
1966 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1967 struct intel_framebuffer *intel_fb;
05394f39 1968 struct drm_i915_gem_object *obj;
81255565 1969 int plane = intel_crtc->plane;
e506a0c6 1970 unsigned long linear_offset;
81255565 1971 u32 dspcntr;
5eddb70b 1972 u32 reg;
81255565
JB		 1973
1974 switch (plane) {
1975 case 0:
1976 case 1:
1977 break;
1978 default:
84f44ce7 1979 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1980 return -EINVAL;
1981 }
1982
1983 intel_fb = to_intel_framebuffer(fb);
1984 obj = intel_fb->obj;
81255565 1985
5eddb70b
CW		 1986 reg = DSPCNTR(plane);
1987 dspcntr = I915_READ(reg);
81255565
JB		 1988 /* Mask out pixel format bits in case we change it */
1989 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1990 switch (fb->pixel_format) {
1991 case DRM_FORMAT_C8:
81255565
JB		 1992 dspcntr |= DISPPLANE_8BPP;
1993 break;
57779d06
VS		 1994 case DRM_FORMAT_XRGB1555:
1995 case DRM_FORMAT_ARGB1555:
1996 dspcntr |= DISPPLANE_BGRX555;
81255565 1997 break;
57779d06
VS		 1998 case DRM_FORMAT_RGB565:
1999 dspcntr |= DISPPLANE_BGRX565;
2000 break;
2001 case DRM_FORMAT_XRGB8888:
2002 case DRM_FORMAT_ARGB8888:
2003 dspcntr |= DISPPLANE_BGRX888;
2004 break;
2005 case DRM_FORMAT_XBGR8888:
2006 case DRM_FORMAT_ABGR8888:
2007 dspcntr |= DISPPLANE_RGBX888;
2008 break;
2009 case DRM_FORMAT_XRGB2101010:
2010 case DRM_FORMAT_ARGB2101010:
2011 dspcntr |= DISPPLANE_BGRX101010;
2012 break;
2013 case DRM_FORMAT_XBGR2101010:
2014 case DRM_FORMAT_ABGR2101010:
2015 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2016 break;
2017 default:
baba133a 2018 BUG();
81255565 2019 }
57779d06 2020
a6c45cf0 2021 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2022 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2023 dspcntr |= DISPPLANE_TILED;
2024 else
2025 dspcntr &= ~DISPPLANE_TILED;
2026 }
2027
de1aa629
VS		 2028 if (IS_G4X(dev))
2029 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2030
5eddb70b 2031 I915_WRITE(reg, dspcntr);
81255565 2032
e506a0c6 2033 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2034
c2c75131
DV		 2035 if (INTEL_INFO(dev)->gen >= 4) {
2036 intel_crtc->dspaddr_offset =
bc752862
CW		 2037 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2038 fb->bits_per_pixel / 8,
2039 fb->pitches[0]);
c2c75131
DV		 2040 linear_offset -= intel_crtc->dspaddr_offset;
2041 } else {
e506a0c6 2042 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2043 }
e506a0c6 2044
f343c5f6
BW		 2045 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2046 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2047 fb->pitches[0]);
01f2c773 2048 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2049 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131 2050 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2051 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2052 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2053 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2054 } else
f343c5f6 2055 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2056 POSTING_READ(reg);
81255565 2057
17638cd6
JB		 2058 return 0;
2059}
2060
2061static int ironlake_update_plane(struct drm_crtc *crtc,
2062 struct drm_framebuffer *fb, int x, int y)
2063{
2064 struct drm_device *dev = crtc->dev;
2065 struct drm_i915_private *dev_priv = dev->dev_private;
2066 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2067 struct intel_framebuffer *intel_fb;
2068 struct drm_i915_gem_object *obj;
2069 int plane = intel_crtc->plane;
e506a0c6 2070 unsigned long linear_offset;
17638cd6
JB		 2071 u32 dspcntr;
2072 u32 reg;
2073
2074 switch (plane) {
2075 case 0:
2076 case 1:
27f8227b 2077 case 2:
17638cd6
JB		 2078 break;
2079 default:
84f44ce7 2080 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2081 return -EINVAL;
2082 }
2083
2084 intel_fb = to_intel_framebuffer(fb);
2085 obj = intel_fb->obj;
2086
2087 reg = DSPCNTR(plane);
2088 dspcntr = I915_READ(reg);
2089 /* Mask out pixel format bits in case we change it */
2090 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2091 switch (fb->pixel_format) {
2092 case DRM_FORMAT_C8:
17638cd6
JB		 2093 dspcntr |= DISPPLANE_8BPP;
2094 break;
57779d06
VS		 2095 case DRM_FORMAT_RGB565:
2096 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2097 break;
57779d06
VS		 2098 case DRM_FORMAT_XRGB8888:
2099 case DRM_FORMAT_ARGB8888:
2100 dspcntr |= DISPPLANE_BGRX888;
2101 break;
2102 case DRM_FORMAT_XBGR8888:
2103 case DRM_FORMAT_ABGR8888:
2104 dspcntr |= DISPPLANE_RGBX888;
2105 break;
2106 case DRM_FORMAT_XRGB2101010:
2107 case DRM_FORMAT_ARGB2101010:
2108 dspcntr |= DISPPLANE_BGRX101010;
2109 break;
2110 case DRM_FORMAT_XBGR2101010:
2111 case DRM_FORMAT_ABGR2101010:
2112 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2113 break;
2114 default:
baba133a 2115 BUG();
17638cd6
JB		 2116 }
2117
2118 if (obj->tiling_mode != I915_TILING_NONE)
2119 dspcntr |= DISPPLANE_TILED;
2120 else
2121 dspcntr &= ~DISPPLANE_TILED;
2122
1f5d76db
PZ		 2123 if (IS_HASWELL(dev))
2124 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2125 else
2126 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6
JB		 2127
2128 I915_WRITE(reg, dspcntr);
2129
e506a0c6 2130 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2131 intel_crtc->dspaddr_offset =
bc752862
CW		 2132 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2133 fb->bits_per_pixel / 8,
2134 fb->pitches[0]);
c2c75131 2135 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2136
f343c5f6
BW		 2137 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2138 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2139 fb->pitches[0]);
01f2c773 2140 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131 2141 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2142 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2143 if (IS_HASWELL(dev)) {
2144 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2145 } else {
2146 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2147 I915_WRITE(DSPLINOFF(plane), linear_offset);
2148 }
17638cd6
JB		 2149 POSTING_READ(reg);
2150
2151 return 0;
2152}
2153
2154/* Assume fb object is pinned & idle & fenced and just update base pointers */
2155static int
2156intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2157 int x, int y, enum mode_set_atomic state)
2158{
2159 struct drm_device *dev = crtc->dev;
2160 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2161
6b8e6ed0
CW		 2162 if (dev_priv->display.disable_fbc)
2163 dev_priv->display.disable_fbc(dev);
3dec0095 2164 intel_increase_pllclock(crtc);
81255565 2165
6b8e6ed0 2166 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2167}
2168
96a02917
VS		 2169void intel_display_handle_reset(struct drm_device *dev)
2170{
2171 struct drm_i915_private *dev_priv = dev->dev_private;
2172 struct drm_crtc *crtc;
2173
2174 /*
2175 * Flips in the rings have been nuked by the reset,
2176 * so complete all pending flips so that user space
2177 * will get its events and not get stuck.
2178 *
2179 * Also update the base address of all primary
2180 * planes to the the last fb to make sure we're
2181 * showing the correct fb after a reset.
2182 *
2183 * Need to make two loops over the crtcs so that we
2184 * don't try to grab a crtc mutex before the
2185 * pending_flip_queue really got woken up.
2186 */
2187
2188 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2189 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2190 enum plane plane = intel_crtc->plane;
2191
2192 intel_prepare_page_flip(dev, plane);
2193 intel_finish_page_flip_plane(dev, plane);
2194 }
2195
2196 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2197 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2198
2199 mutex_lock(&crtc->mutex);
2200 if (intel_crtc->active)
2201 dev_priv->display.update_plane(crtc, crtc->fb,
2202 crtc->x, crtc->y);
2203 mutex_unlock(&crtc->mutex);
2204 }
2205}
2206
14667a4b
CW		 2207static int
2208intel_finish_fb(struct drm_framebuffer *old_fb)
2209{
2210 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2211 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2212 bool was_interruptible = dev_priv->mm.interruptible;
2213 int ret;
2214
14667a4b
CW		 2215 /* Big Hammer, we also need to ensure that any pending
2216 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2217 * current scanout is retired before unpinning the old
2218 * framebuffer.
2219 *
2220 * This should only fail upon a hung GPU, in which case we
2221 * can safely continue.
2222 */
2223 dev_priv->mm.interruptible = false;
2224 ret = i915_gem_object_finish_gpu(obj);
2225 dev_priv->mm.interruptible = was_interruptible;
2226
2227 return ret;
2228}
2229
198598d0
VS		 2230static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2231{
2232 struct drm_device *dev = crtc->dev;
2233 struct drm_i915_master_private *master_priv;
2234 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2235
2236 if (!dev->primary->master)
2237 return;
2238
2239 master_priv = dev->primary->master->driver_priv;
2240 if (!master_priv->sarea_priv)
2241 return;
2242
2243 switch (intel_crtc->pipe) {
2244 case 0:
2245 master_priv->sarea_priv->pipeA_x = x;
2246 master_priv->sarea_priv->pipeA_y = y;
2247 break;
2248 case 1:
2249 master_priv->sarea_priv->pipeB_x = x;
2250 master_priv->sarea_priv->pipeB_y = y;
2251 break;
2252 default:
2253 break;
2254 }
2255}
2256
5c3b82e2 2257static int
3c4fdcfb 2258intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2259 struct drm_framebuffer *fb)
79e53945
JB		 2260{
2261 struct drm_device *dev = crtc->dev;
6b8e6ed0 2262 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2263 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2264 struct drm_framebuffer *old_fb;
5c3b82e2 2265 int ret;
79e53945
JB		 2266
2267 /* no fb bound */
94352cf9 2268 if (!fb) {
a5071c2f 2269 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2270 return 0;
2271 }
2272
7eb552ae 2273 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2274 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2275 plane_name(intel_crtc->plane),
2276 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2277 return -EINVAL;
79e53945
JB		 2278 }
2279
5c3b82e2 2280 mutex_lock(&dev->struct_mutex);
265db958 2281 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2282 to_intel_framebuffer(fb)->obj,
919926ae 2283 NULL);
5c3b82e2
CW		 2284 if (ret != 0) {
2285 mutex_unlock(&dev->struct_mutex);
a5071c2f 2286 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2287 return ret;
2288 }
79e53945 2289
4d6a3e63
JB		 2290 /* Update pipe size and adjust fitter if needed */
2291 if (i915_fastboot) {
2292 I915_WRITE(PIPESRC(intel_crtc->pipe),
2293 ((crtc->mode.hdisplay - 1) << 16) |
2294 (crtc->mode.vdisplay - 1));
fd4daa9c 2295 if (!intel_crtc->config.pch_pfit.enabled &&
4d6a3e63
JB		 2296 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2297 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2298 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2299 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2300 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2301 }
2302 }
2303
94352cf9 2304 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2305 if (ret) {
94352cf9 2306 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2307 mutex_unlock(&dev->struct_mutex);
a5071c2f 2308 DRM_ERROR("failed to update base address\n");
4e6cfefc 2309 return ret;
79e53945 2310 }
3c4fdcfb 2311
94352cf9
DV		 2312 old_fb = crtc->fb;
2313 crtc->fb = fb;
6c4c86f5
DV		 2314 crtc->x = x;
2315 crtc->y = y;
94352cf9 2316
b7f1de28 2317 if (old_fb) {
d7697eea
DV		 2318 if (intel_crtc->active && old_fb != fb)
2319 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2320 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2321 }
652c393a 2322
6b8e6ed0 2323 intel_update_fbc(dev);
4906557e 2324 intel_edp_psr_update(dev);
5c3b82e2 2325 mutex_unlock(&dev->struct_mutex);
79e53945 2326
198598d0 2327 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2328
2329 return 0;
79e53945
JB		 2330}
2331
5e84e1a4
ZW		 2332static void intel_fdi_normal_train(struct drm_crtc *crtc)
2333{
2334 struct drm_device *dev = crtc->dev;
2335 struct drm_i915_private *dev_priv = dev->dev_private;
2336 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2337 int pipe = intel_crtc->pipe;
2338 u32 reg, temp;
2339
2340 /* enable normal train */
2341 reg = FDI_TX_CTL(pipe);
2342 temp = I915_READ(reg);
61e499bf 2343 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2344 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2345 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2346 } else {
2347 temp &= ~FDI_LINK_TRAIN_NONE;
2348 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2349 }
5e84e1a4
ZW		 2350 I915_WRITE(reg, temp);
2351
2352 reg = FDI_RX_CTL(pipe);
2353 temp = I915_READ(reg);
2354 if (HAS_PCH_CPT(dev)) {
2355 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2356 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2357 } else {
2358 temp &= ~FDI_LINK_TRAIN_NONE;
2359 temp |= FDI_LINK_TRAIN_NONE;
2360 }
2361 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2362
2363 /* wait one idle pattern time */
2364 POSTING_READ(reg);
2365 udelay(1000);
357555c0
JB		 2366
2367 /* IVB wants error correction enabled */
2368 if (IS_IVYBRIDGE(dev))
2369 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2370 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2371}
2372
1e833f40
DV		 2373static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2374{
2375 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2376}
2377
01a415fd
DV		 2378static void ivb_modeset_global_resources(struct drm_device *dev)
2379{
2380 struct drm_i915_private *dev_priv = dev->dev_private;
2381 struct intel_crtc *pipe_B_crtc =
2382 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2383 struct intel_crtc *pipe_C_crtc =
2384 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2385 uint32_t temp;
2386
1e833f40
DV		 2387 /*
2388 * When everything is off disable fdi C so that we could enable fdi B
2389 * with all lanes. Note that we don't care about enabled pipes without
2390 * an enabled pch encoder.
2391 */
2392 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2393 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2394 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2395 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2396
2397 temp = I915_READ(SOUTH_CHICKEN1);
2398 temp &= ~FDI_BC_BIFURCATION_SELECT;
2399 DRM_DEBUG_KMS("disabling fdi C rx\n");
2400 I915_WRITE(SOUTH_CHICKEN1, temp);
2401 }
2402}
2403
8db9d77b
ZW		 2404/* The FDI link training functions for ILK/Ibexpeak. */
2405static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2406{
2407 struct drm_device *dev = crtc->dev;
2408 struct drm_i915_private *dev_priv = dev->dev_private;
2409 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2410 int pipe = intel_crtc->pipe;
0fc932b8 2411 int plane = intel_crtc->plane;
5eddb70b 2412 u32 reg, temp, tries;
8db9d77b 2413
0fc932b8
JB		 2414 /* FDI needs bits from pipe & plane first */
2415 assert_pipe_enabled(dev_priv, pipe);
2416 assert_plane_enabled(dev_priv, plane);
2417
e1a44743
AJ		 2418 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2419 for train result */
5eddb70b
CW		 2420 reg = FDI_RX_IMR(pipe);
2421 temp = I915_READ(reg);
e1a44743
AJ		 2422 temp &= ~FDI_RX_SYMBOL_LOCK;
2423 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2424 I915_WRITE(reg, temp);
2425 I915_READ(reg);
e1a44743
AJ		 2426 udelay(150);
2427
8db9d77b 2428 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2429 reg = FDI_TX_CTL(pipe);
2430 temp = I915_READ(reg);
627eb5a3
DV		 2431 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2432 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2433 temp &= ~FDI_LINK_TRAIN_NONE;
2434 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2435 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2436
5eddb70b
CW		 2437 reg = FDI_RX_CTL(pipe);
2438 temp = I915_READ(reg);
8db9d77b
ZW		 2439 temp &= ~FDI_LINK_TRAIN_NONE;
2440 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2441 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2442
2443 POSTING_READ(reg);
8db9d77b
ZW		 2444 udelay(150);
2445
5b2adf89 2446 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2447 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2448 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2449 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2450
5eddb70b 2451 reg = FDI_RX_IIR(pipe);
e1a44743 2452 for (tries = 0; tries < 5; tries++) {
5eddb70b 2453 temp = I915_READ(reg);
8db9d77b
ZW		 2454 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2455
2456 if ((temp & FDI_RX_BIT_LOCK)) {
2457 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2458 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2459 break;
2460 }
8db9d77b 2461 }
e1a44743 2462 if (tries == 5)
5eddb70b 2463 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2464
2465 /* Train 2 */
5eddb70b
CW		 2466 reg = FDI_TX_CTL(pipe);
2467 temp = I915_READ(reg);
8db9d77b
ZW		 2468 temp &= ~FDI_LINK_TRAIN_NONE;
2469 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2470 I915_WRITE(reg, temp);
8db9d77b 2471
5eddb70b
CW		 2472 reg = FDI_RX_CTL(pipe);
2473 temp = I915_READ(reg);
8db9d77b
ZW		 2474 temp &= ~FDI_LINK_TRAIN_NONE;
2475 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2476 I915_WRITE(reg, temp);
8db9d77b 2477
5eddb70b
CW		 2478 POSTING_READ(reg);
2479 udelay(150);
8db9d77b 2480
5eddb70b 2481 reg = FDI_RX_IIR(pipe);
e1a44743 2482 for (tries = 0; tries < 5; tries++) {
5eddb70b 2483 temp = I915_READ(reg);
8db9d77b
ZW		 2484 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2485
2486 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2487 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2488 DRM_DEBUG_KMS("FDI train 2 done.\n");
2489 break;
2490 }
8db9d77b 2491 }
e1a44743 2492 if (tries == 5)
5eddb70b 2493 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2494
2495 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2496
8db9d77b
ZW		 2497}
2498
0206e353 2499static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2500 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2501 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2502 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2503 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2504};
2505
2506/* The FDI link training functions for SNB/Cougarpoint. */
2507static void gen6_fdi_link_train(struct drm_crtc *crtc)
2508{
2509 struct drm_device *dev = crtc->dev;
2510 struct drm_i915_private *dev_priv = dev->dev_private;
2511 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2512 int pipe = intel_crtc->pipe;
fa37d39e 2513 u32 reg, temp, i, retry;
8db9d77b 2514
e1a44743
AJ		 2515 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2516 for train result */
5eddb70b
CW		 2517 reg = FDI_RX_IMR(pipe);
2518 temp = I915_READ(reg);
e1a44743
AJ		 2519 temp &= ~FDI_RX_SYMBOL_LOCK;
2520 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2521 I915_WRITE(reg, temp);
2522
2523 POSTING_READ(reg);
e1a44743
AJ		 2524 udelay(150);
2525
8db9d77b 2526 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2527 reg = FDI_TX_CTL(pipe);
2528 temp = I915_READ(reg);
627eb5a3
DV		 2529 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2530 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2531 temp &= ~FDI_LINK_TRAIN_NONE;
2532 temp |= FDI_LINK_TRAIN_PATTERN_1;
2533 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2534 /* SNB-B */
2535 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2536 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2537
d74cf324
DV		 2538 I915_WRITE(FDI_RX_MISC(pipe),
2539 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2540
5eddb70b
CW		 2541 reg = FDI_RX_CTL(pipe);
2542 temp = I915_READ(reg);
8db9d77b
ZW		 2543 if (HAS_PCH_CPT(dev)) {
2544 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2545 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2546 } else {
2547 temp &= ~FDI_LINK_TRAIN_NONE;
2548 temp |= FDI_LINK_TRAIN_PATTERN_1;
2549 }
5eddb70b
CW		 2550 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2551
2552 POSTING_READ(reg);
8db9d77b
ZW		 2553 udelay(150);
2554
0206e353 2555 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2556 reg = FDI_TX_CTL(pipe);
2557 temp = I915_READ(reg);
8db9d77b
ZW		 2558 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2559 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2560 I915_WRITE(reg, temp);
2561
2562 POSTING_READ(reg);
8db9d77b
ZW		 2563 udelay(500);
2564
fa37d39e
SP		 2565 for (retry = 0; retry < 5; retry++) {
2566 reg = FDI_RX_IIR(pipe);
2567 temp = I915_READ(reg);
2568 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2569 if (temp & FDI_RX_BIT_LOCK) {
2570 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2571 DRM_DEBUG_KMS("FDI train 1 done.\n");
2572 break;
2573 }
2574 udelay(50);
8db9d77b 2575 }
fa37d39e
SP		 2576 if (retry < 5)
2577 break;
8db9d77b
ZW		 2578 }
2579 if (i == 4)
5eddb70b 2580 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2581
2582 /* Train 2 */
5eddb70b
CW		 2583 reg = FDI_TX_CTL(pipe);
2584 temp = I915_READ(reg);
8db9d77b
ZW		 2585 temp &= ~FDI_LINK_TRAIN_NONE;
2586 temp |= FDI_LINK_TRAIN_PATTERN_2;
2587 if (IS_GEN6(dev)) {
2588 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2589 /* SNB-B */
2590 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2591 }
5eddb70b 2592 I915_WRITE(reg, temp);
8db9d77b 2593
5eddb70b
CW		 2594 reg = FDI_RX_CTL(pipe);
2595 temp = I915_READ(reg);
8db9d77b
ZW		 2596 if (HAS_PCH_CPT(dev)) {
2597 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2598 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2599 } else {
2600 temp &= ~FDI_LINK_TRAIN_NONE;
2601 temp |= FDI_LINK_TRAIN_PATTERN_2;
2602 }
5eddb70b
CW		 2603 I915_WRITE(reg, temp);
2604
2605 POSTING_READ(reg);
8db9d77b
ZW		 2606 udelay(150);
2607
0206e353 2608 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2609 reg = FDI_TX_CTL(pipe);
2610 temp = I915_READ(reg);
8db9d77b
ZW		 2611 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2612 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2613 I915_WRITE(reg, temp);
2614
2615 POSTING_READ(reg);
8db9d77b
ZW		 2616 udelay(500);
2617
fa37d39e
SP		 2618 for (retry = 0; retry < 5; retry++) {
2619 reg = FDI_RX_IIR(pipe);
2620 temp = I915_READ(reg);
2621 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2622 if (temp & FDI_RX_SYMBOL_LOCK) {
2623 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2624 DRM_DEBUG_KMS("FDI train 2 done.\n");
2625 break;
2626 }
2627 udelay(50);
8db9d77b 2628 }
fa37d39e
SP		 2629 if (retry < 5)
2630 break;
8db9d77b
ZW		 2631 }
2632 if (i == 4)
5eddb70b 2633 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2634
2635 DRM_DEBUG_KMS("FDI train done.\n");
2636}
2637
357555c0
JB		 2638/* Manual link training for Ivy Bridge A0 parts */
2639static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2640{
2641 struct drm_device *dev = crtc->dev;
2642 struct drm_i915_private *dev_priv = dev->dev_private;
2643 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2644 int pipe = intel_crtc->pipe;
139ccd3f 2645 u32 reg, temp, i, j;
357555c0
JB		 2646
2647 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2648 for train result */
2649 reg = FDI_RX_IMR(pipe);
2650 temp = I915_READ(reg);
2651 temp &= ~FDI_RX_SYMBOL_LOCK;
2652 temp &= ~FDI_RX_BIT_LOCK;
2653 I915_WRITE(reg, temp);
2654
2655 POSTING_READ(reg);
2656 udelay(150);
2657
01a415fd
DV		 2658 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2659 I915_READ(FDI_RX_IIR(pipe)));
2660
139ccd3f
JB		 2661 /* Try each vswing and preemphasis setting twice before moving on */
2662 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2663 /* disable first in case we need to retry */
2664 reg = FDI_TX_CTL(pipe);
2665 temp = I915_READ(reg);
2666 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2667 temp &= ~FDI_TX_ENABLE;
2668 I915_WRITE(reg, temp);
357555c0 2669
139ccd3f
JB		 2670 reg = FDI_RX_CTL(pipe);
2671 temp = I915_READ(reg);
2672 temp &= ~FDI_LINK_TRAIN_AUTO;
2673 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2674 temp &= ~FDI_RX_ENABLE;
2675 I915_WRITE(reg, temp);
357555c0 2676
139ccd3f 2677 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 2678 reg = FDI_TX_CTL(pipe);
2679 temp = I915_READ(reg);
139ccd3f
JB		 2680 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2681 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2682 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 2683 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 2684 temp |= snb_b_fdi_train_param[j/2];
2685 temp |= FDI_COMPOSITE_SYNC;
2686 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 2687
139ccd3f
JB		 2688 I915_WRITE(FDI_RX_MISC(pipe),
2689 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 2690
139ccd3f 2691 reg = FDI_RX_CTL(pipe);
357555c0 2692 temp = I915_READ(reg);
139ccd3f
JB		 2693 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2694 temp |= FDI_COMPOSITE_SYNC;
2695 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 2696
139ccd3f
JB		 2697 POSTING_READ(reg);
2698 udelay(1); /* should be 0.5us */
357555c0 2699
139ccd3f
JB		 2700 for (i = 0; i < 4; i++) {
2701 reg = FDI_RX_IIR(pipe);
2702 temp = I915_READ(reg);
2703 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2704
139ccd3f
JB		 2705 if (temp & FDI_RX_BIT_LOCK ||
2706 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2707 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2708 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2709 i);
2710 break;
2711 }
2712 udelay(1); /* should be 0.5us */
2713 }
2714 if (i == 4) {
2715 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2716 continue;
2717 }
357555c0 2718
139ccd3f 2719 /* Train 2 */
357555c0
JB		 2720 reg = FDI_TX_CTL(pipe);
2721 temp = I915_READ(reg);
139ccd3f
JB		 2722 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2723 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2724 I915_WRITE(reg, temp);
2725
2726 reg = FDI_RX_CTL(pipe);
2727 temp = I915_READ(reg);
2728 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2729 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 2730 I915_WRITE(reg, temp);
2731
2732 POSTING_READ(reg);
139ccd3f 2733 udelay(2); /* should be 1.5us */
357555c0 2734
139ccd3f
JB		 2735 for (i = 0; i < 4; i++) {
2736 reg = FDI_RX_IIR(pipe);
2737 temp = I915_READ(reg);
2738 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2739
139ccd3f
JB		 2740 if (temp & FDI_RX_SYMBOL_LOCK ||
2741 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2742 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2743 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2744 i);
2745 goto train_done;
2746 }
2747 udelay(2); /* should be 1.5us */
357555c0 2748 }
139ccd3f
JB		 2749 if (i == 4)
2750 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 2751 }
357555c0 2752
139ccd3f 2753train_done:
357555c0
JB		 2754 DRM_DEBUG_KMS("FDI train done.\n");
2755}
2756
88cefb6c 2757static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2758{
88cefb6c 2759 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2760 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2761 int pipe = intel_crtc->pipe;
5eddb70b 2762 u32 reg, temp;
79e53945 2763
c64e311e 2764
c98e9dcf 2765 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2766 reg = FDI_RX_CTL(pipe);
2767 temp = I915_READ(reg);
627eb5a3
DV		 2768 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2769 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2770 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2771 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2772
2773 POSTING_READ(reg);
c98e9dcf
JB		 2774 udelay(200);
2775
2776 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2777 temp = I915_READ(reg);
2778 I915_WRITE(reg, temp | FDI_PCDCLK);
2779
2780 POSTING_READ(reg);
c98e9dcf
JB		 2781 udelay(200);
2782
20749730
PZ		 2783 /* Enable CPU FDI TX PLL, always on for Ironlake */
2784 reg = FDI_TX_CTL(pipe);
2785 temp = I915_READ(reg);
2786 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2787 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2788
20749730
PZ		 2789 POSTING_READ(reg);
2790 udelay(100);
6be4a607 2791 }
0e23b99d
JB		 2792}
2793
88cefb6c
DV		 2794static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2795{
2796 struct drm_device *dev = intel_crtc->base.dev;
2797 struct drm_i915_private *dev_priv = dev->dev_private;
2798 int pipe = intel_crtc->pipe;
2799 u32 reg, temp;
2800
2801 /* Switch from PCDclk to Rawclk */
2802 reg = FDI_RX_CTL(pipe);
2803 temp = I915_READ(reg);
2804 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2805
2806 /* Disable CPU FDI TX PLL */
2807 reg = FDI_TX_CTL(pipe);
2808 temp = I915_READ(reg);
2809 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2810
2811 POSTING_READ(reg);
2812 udelay(100);
2813
2814 reg = FDI_RX_CTL(pipe);
2815 temp = I915_READ(reg);
2816 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2817
2818 /* Wait for the clocks to turn off. */
2819 POSTING_READ(reg);
2820 udelay(100);
2821}
2822
0fc932b8
JB		 2823static void ironlake_fdi_disable(struct drm_crtc *crtc)
2824{
2825 struct drm_device *dev = crtc->dev;
2826 struct drm_i915_private *dev_priv = dev->dev_private;
2827 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2828 int pipe = intel_crtc->pipe;
2829 u32 reg, temp;
2830
2831 /* disable CPU FDI tx and PCH FDI rx */
2832 reg = FDI_TX_CTL(pipe);
2833 temp = I915_READ(reg);
2834 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2835 POSTING_READ(reg);
2836
2837 reg = FDI_RX_CTL(pipe);
2838 temp = I915_READ(reg);
2839 temp &= ~(0x7 << 16);
dfd07d72 2840 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2841 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2842
2843 POSTING_READ(reg);
2844 udelay(100);
2845
2846 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2847 if (HAS_PCH_IBX(dev)) {
2848 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2849 }
0fc932b8
JB		 2850
2851 /* still set train pattern 1 */
2852 reg = FDI_TX_CTL(pipe);
2853 temp = I915_READ(reg);
2854 temp &= ~FDI_LINK_TRAIN_NONE;
2855 temp |= FDI_LINK_TRAIN_PATTERN_1;
2856 I915_WRITE(reg, temp);
2857
2858 reg = FDI_RX_CTL(pipe);
2859 temp = I915_READ(reg);
2860 if (HAS_PCH_CPT(dev)) {
2861 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2862 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2863 } else {
2864 temp &= ~FDI_LINK_TRAIN_NONE;
2865 temp |= FDI_LINK_TRAIN_PATTERN_1;
2866 }
2867 /* BPC in FDI rx is consistent with that in PIPECONF */
2868 temp &= ~(0x07 << 16);
dfd07d72 2869 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2870 I915_WRITE(reg, temp);
2871
2872 POSTING_READ(reg);
2873 udelay(100);
2874}
2875
5bb61643
CW		 2876static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2877{
2878 struct drm_device *dev = crtc->dev;
2879 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2880 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2881 unsigned long flags;
2882 bool pending;
2883
10d83730
VS		 2884 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2885 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2886 return false;
2887
2888 spin_lock_irqsave(&dev->event_lock, flags);
2889 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2890 spin_unlock_irqrestore(&dev->event_lock, flags);
2891
2892 return pending;
2893}
2894
e6c3a2a6
CW		 2895static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2896{
0f91128d 2897 struct drm_device *dev = crtc->dev;
5bb61643 2898 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2899
2900 if (crtc->fb == NULL)
2901 return;
2902
2c10d571
DV		 2903 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2904
5bb61643
CW		 2905 wait_event(dev_priv->pending_flip_queue,
2906 !intel_crtc_has_pending_flip(crtc));
2907
0f91128d
CW		 2908 mutex_lock(&dev->struct_mutex);
2909 intel_finish_fb(crtc->fb);
2910 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2911}
2912
e615efe4
ED		 2913/* Program iCLKIP clock to the desired frequency */
2914static void lpt_program_iclkip(struct drm_crtc *crtc)
2915{
2916 struct drm_device *dev = crtc->dev;
2917 struct drm_i915_private *dev_priv = dev->dev_private;
241bfc38 2918 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
e615efe4
ED		 2919 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2920 u32 temp;
2921
09153000
DV		 2922 mutex_lock(&dev_priv->dpio_lock);
2923
e615efe4
ED		 2924 /* It is necessary to ungate the pixclk gate prior to programming
2925 * the divisors, and gate it back when it is done.
2926 */
2927 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2928
2929 /* Disable SSCCTL */
2930 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2931 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2932 SBI_SSCCTL_DISABLE,
2933 SBI_ICLK);
e615efe4
ED		 2934
2935 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 2936 if (clock == 20000) {
e615efe4
ED		 2937 auxdiv = 1;
2938 divsel = 0x41;
2939 phaseinc = 0x20;
2940 } else {
2941 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 2942 * but the adjusted_mode->crtc_clock in in KHz. To get the
2943 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 2944 * convert the virtual clock precision to KHz here for higher
2945 * precision.
2946 */
2947 u32 iclk_virtual_root_freq = 172800 * 1000;
2948 u32 iclk_pi_range = 64;
2949 u32 desired_divisor, msb_divisor_value, pi_value;
2950
12d7ceed 2951 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 2952 msb_divisor_value = desired_divisor / iclk_pi_range;
2953 pi_value = desired_divisor % iclk_pi_range;
2954
2955 auxdiv = 0;
2956 divsel = msb_divisor_value - 2;
2957 phaseinc = pi_value;
2958 }
2959
2960 /* This should not happen with any sane values */
2961 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2962 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2963 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2964 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2965
2966 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 2967 clock,
e615efe4
ED		 2968 auxdiv,
2969 divsel,
2970 phasedir,
2971 phaseinc);
2972
2973 /* Program SSCDIVINTPHASE6 */
988d6ee8 2974 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2975 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2976 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2977 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2978 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2979 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2980 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2981 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2982
2983 /* Program SSCAUXDIV */
988d6ee8 2984 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2985 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2986 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2987 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2988
2989 /* Enable modulator and associated divider */
988d6ee8 2990 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2991 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2992 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2993
2994 /* Wait for initialization time */
2995 udelay(24);
2996
2997 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2998
2999 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3000}
3001
275f01b2
DV		 3002static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3003 enum pipe pch_transcoder)
3004{
3005 struct drm_device *dev = crtc->base.dev;
3006 struct drm_i915_private *dev_priv = dev->dev_private;
3007 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3008
3009 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3010 I915_READ(HTOTAL(cpu_transcoder)));
3011 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3012 I915_READ(HBLANK(cpu_transcoder)));
3013 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3014 I915_READ(HSYNC(cpu_transcoder)));
3015
3016 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3017 I915_READ(VTOTAL(cpu_transcoder)));
3018 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3019 I915_READ(VBLANK(cpu_transcoder)));
3020 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3021 I915_READ(VSYNC(cpu_transcoder)));
3022 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3023 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3024}
3025
f67a559d
JB		 3026/*
3027 * Enable PCH resources required for PCH ports:
3028 * - PCH PLLs
3029 * - FDI training & RX/TX
3030 * - update transcoder timings
3031 * - DP transcoding bits
3032 * - transcoder
3033 */
3034static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3035{
3036 struct drm_device *dev = crtc->dev;
3037 struct drm_i915_private *dev_priv = dev->dev_private;
3038 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3039 int pipe = intel_crtc->pipe;
ee7b9f93 3040 u32 reg, temp;
2c07245f 3041
ab9412ba 3042 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 3043
cd986abb
DV		 3044 /* Write the TU size bits before fdi link training, so that error
3045 * detection works. */
3046 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3047 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3048
c98e9dcf 3049 /* For PCH output, training FDI link */
674cf967 3050 dev_priv->display.fdi_link_train(crtc);
2c07245f 3051
3ad8a208
DV		 3052 /* We need to program the right clock selection before writing the pixel
3053 * mutliplier into the DPLL. */
303b81e0 3054 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3055 u32 sel;
4b645f14 3056
c98e9dcf 3057 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 3058 temp |= TRANS_DPLL_ENABLE(pipe);
3059 sel = TRANS_DPLLB_SEL(pipe);
a43f6e0f 3060 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 3061 temp |= sel;
3062 else
3063 temp &= ~sel;
c98e9dcf 3064 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3065 }
5eddb70b 3066
3ad8a208
DV		 3067 /* XXX: pch pll's can be enabled any time before we enable the PCH
3068 * transcoder, and we actually should do this to not upset any PCH
3069 * transcoder that already use the clock when we share it.
3070 *
3071 * Note that enable_shared_dpll tries to do the right thing, but
3072 * get_shared_dpll unconditionally resets the pll - we need that to have
3073 * the right LVDS enable sequence. */
3074 ironlake_enable_shared_dpll(intel_crtc);
3075
d9b6cb56
JB		 3076 /* set transcoder timing, panel must allow it */
3077 assert_panel_unlocked(dev_priv, pipe);
275f01b2 3078 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 3079
303b81e0 3080 intel_fdi_normal_train(crtc);
5e84e1a4 3081
c98e9dcf
JB		 3082 /* For PCH DP, enable TRANS_DP_CTL */
3083 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3084 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3085 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3086 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3087 reg = TRANS_DP_CTL(pipe);
3088 temp = I915_READ(reg);
3089 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3090 TRANS_DP_SYNC_MASK |
3091 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3092 temp |= (TRANS_DP_OUTPUT_ENABLE |
3093 TRANS_DP_ENH_FRAMING);
9325c9f0 3094 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3095
3096 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3097 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3098 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3099 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3100
3101 switch (intel_trans_dp_port_sel(crtc)) {
3102 case PCH_DP_B:
5eddb70b 3103 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3104 break;
3105 case PCH_DP_C:
5eddb70b 3106 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3107 break;
3108 case PCH_DP_D:
5eddb70b 3109 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3110 break;
3111 default:
e95d41e1 3112 BUG();
32f9d658 3113 }
2c07245f 3114
5eddb70b 3115 I915_WRITE(reg, temp);
6be4a607 3116 }
b52eb4dc 3117
b8a4f404 3118 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3119}
3120
1507e5bd
PZ		 3121static void lpt_pch_enable(struct drm_crtc *crtc)
3122{
3123 struct drm_device *dev = crtc->dev;
3124 struct drm_i915_private *dev_priv = dev->dev_private;
3125 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3126 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3127
ab9412ba 3128 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3129
8c52b5e8 3130 lpt_program_iclkip(crtc);
1507e5bd 3131
0540e488 3132 /* Set transcoder timing. */
275f01b2 3133 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3134
937bb610 3135 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3136}
3137
e2b78267 3138static void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3139{
e2b78267 3140 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 3141
3142 if (pll == NULL)
3143 return;
3144
3145 if (pll->refcount == 0) {
46edb027 3146 WARN(1, "bad %s refcount\n", pll->name);
ee7b9f93
JB		 3147 return;
3148 }
3149
f4a091c7
DV		 3150 if (--pll->refcount == 0) {
3151 WARN_ON(pll->on);
3152 WARN_ON(pll->active);
3153 }
3154
a43f6e0f 3155 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 3156}
3157
b89a1d39 3158static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3159{
e2b78267
DV		 3160 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3161 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3162 enum intel_dpll_id i;
ee7b9f93 3163
ee7b9f93 3164 if (pll) {
46edb027
DV		 3165 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3166 crtc->base.base.id, pll->name);
e2b78267 3167 intel_put_shared_dpll(crtc);
ee7b9f93
JB		 3168 }
3169
98b6bd99
DV		 3170 if (HAS_PCH_IBX(dev_priv->dev)) {
3171 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 3172 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 3173 pll = &dev_priv->shared_dplls[i];
98b6bd99 3174
46edb027
DV		 3175 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3176 crtc->base.base.id, pll->name);
98b6bd99
DV		 3177
3178 goto found;
3179 }
3180
e72f9fbf
DV		 3181 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3182 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 3183
3184 /* Only want to check enabled timings first */
3185 if (pll->refcount == 0)
3186 continue;
3187
b89a1d39
DV		 3188 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3189 sizeof(pll->hw_state)) == 0) {
46edb027 3190 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
e2b78267 3191 crtc->base.base.id,
46edb027 3192 pll->name, pll->refcount, pll->active);
ee7b9f93
JB		 3193
3194 goto found;
3195 }
3196 }
3197
3198 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 3199 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3200 pll = &dev_priv->shared_dplls[i];
ee7b9f93 3201 if (pll->refcount == 0) {
46edb027
DV		 3202 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3203 crtc->base.base.id, pll->name);
ee7b9f93
JB		 3204 goto found;
3205 }
3206 }
3207
3208 return NULL;
3209
3210found:
a43f6e0f 3211 crtc->config.shared_dpll = i;
46edb027
DV		 3212 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3213 pipe_name(crtc->pipe));
ee7b9f93 3214
cdbd2316 3215 if (pll->active == 0) {
66e985c0
DV		 3216 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3217 sizeof(pll->hw_state));
3218
46edb027 3219 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
cdbd2316 3220 WARN_ON(pll->on);
e9d6944e 3221 assert_shared_dpll_disabled(dev_priv, pll);
ee7b9f93 3222
15bdd4cf 3223 pll->mode_set(dev_priv, pll);
cdbd2316
DV		 3224 }
3225 pll->refcount++;
e04c7350 3226
ee7b9f93
JB		 3227 return pll;
3228}
3229
a1520318 3230static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3231{
3232 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3233 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3234 u32 temp;
3235
3236 temp = I915_READ(dslreg);
3237 udelay(500);
3238 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3239 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3240 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3241 }
3242}
3243
b074cec8
JB		 3244static void ironlake_pfit_enable(struct intel_crtc *crtc)
3245{
3246 struct drm_device *dev = crtc->base.dev;
3247 struct drm_i915_private *dev_priv = dev->dev_private;
3248 int pipe = crtc->pipe;
3249
fd4daa9c 3250 if (crtc->config.pch_pfit.enabled) {
b074cec8
JB		 3251 /* Force use of hard-coded filter coefficients
3252 * as some pre-programmed values are broken,
3253 * e.g. x201.
3254 */
3255 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3256 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3257 PF_PIPE_SEL_IVB(pipe));
3258 else
3259 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3260 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3261 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
d4270e57
JB		 3262 }
3263}
3264
bb53d4ae
VS		 3265static void intel_enable_planes(struct drm_crtc *crtc)
3266{
3267 struct drm_device *dev = crtc->dev;
3268 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3269 struct intel_plane *intel_plane;
3270
3271 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3272 if (intel_plane->pipe == pipe)
3273 intel_plane_restore(&intel_plane->base);
3274}
3275
3276static void intel_disable_planes(struct drm_crtc *crtc)
3277{
3278 struct drm_device *dev = crtc->dev;
3279 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3280 struct intel_plane *intel_plane;
3281
3282 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3283 if (intel_plane->pipe == pipe)
3284 intel_plane_disable(&intel_plane->base);
3285}
3286
d77e4531
PZ		 3287static void hsw_enable_ips(struct intel_crtc *crtc)
3288{
3289 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3290
3291 if (!crtc->config.ips_enabled)
3292 return;
3293
3294 /* We can only enable IPS after we enable a plane and wait for a vblank.
3295 * We guarantee that the plane is enabled by calling intel_enable_ips
3296 * only after intel_enable_plane. And intel_enable_plane already waits
3297 * for a vblank, so all we need to do here is to enable the IPS bit. */
3298 assert_plane_enabled(dev_priv, crtc->plane);
3299 I915_WRITE(IPS_CTL, IPS_ENABLE);
3300}
3301
3302static void hsw_disable_ips(struct intel_crtc *crtc)
3303{
3304 struct drm_device *dev = crtc->base.dev;
3305 struct drm_i915_private *dev_priv = dev->dev_private;
3306
3307 if (!crtc->config.ips_enabled)
3308 return;
3309
3310 assert_plane_enabled(dev_priv, crtc->plane);
3311 I915_WRITE(IPS_CTL, 0);
3312 POSTING_READ(IPS_CTL);
3313
3314 /* We need to wait for a vblank before we can disable the plane. */
3315 intel_wait_for_vblank(dev, crtc->pipe);
3316}
3317
3318/** Loads the palette/gamma unit for the CRTC with the prepared values */
3319static void intel_crtc_load_lut(struct drm_crtc *crtc)
3320{
3321 struct drm_device *dev = crtc->dev;
3322 struct drm_i915_private *dev_priv = dev->dev_private;
3323 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3324 enum pipe pipe = intel_crtc->pipe;
3325 int palreg = PALETTE(pipe);
3326 int i;
3327 bool reenable_ips = false;
3328
3329 /* The clocks have to be on to load the palette. */
3330 if (!crtc->enabled || !intel_crtc->active)
3331 return;
3332
3333 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3334 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3335 assert_dsi_pll_enabled(dev_priv);
3336 else
3337 assert_pll_enabled(dev_priv, pipe);
3338 }
3339
3340 /* use legacy palette for Ironlake */
3341 if (HAS_PCH_SPLIT(dev))
3342 palreg = LGC_PALETTE(pipe);
3343
3344 /* Workaround : Do not read or write the pipe palette/gamma data while
3345 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3346 */
3347 if (intel_crtc->config.ips_enabled &&
3348 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3349 GAMMA_MODE_MODE_SPLIT)) {
3350 hsw_disable_ips(intel_crtc);
3351 reenable_ips = true;
3352 }
3353
3354 for (i = 0; i < 256; i++) {
3355 I915_WRITE(palreg + 4 * i,
3356 (intel_crtc->lut_r[i] << 16) |
3357 (intel_crtc->lut_g[i] << 8) |
3358 intel_crtc->lut_b[i]);
3359 }
3360
3361 if (reenable_ips)
3362 hsw_enable_ips(intel_crtc);
3363}
3364
f67a559d
JB		 3365static void ironlake_crtc_enable(struct drm_crtc *crtc)
3366{
3367 struct drm_device *dev = crtc->dev;
3368 struct drm_i915_private *dev_priv = dev->dev_private;
3369 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3370 struct intel_encoder *encoder;
f67a559d
JB		 3371 int pipe = intel_crtc->pipe;
3372 int plane = intel_crtc->plane;
f67a559d 3373
08a48469
DV		 3374 WARN_ON(!crtc->enabled);
3375
f67a559d
JB		 3376 if (intel_crtc->active)
3377 return;
3378
3379 intel_crtc->active = true;
8664281b
PZ		 3380
3381 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3382 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3383
f6736a1a 3384 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 3385 if (encoder->pre_enable)
3386 encoder->pre_enable(encoder);
f67a559d 3387
5bfe2ac0 3388 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3389 /* Note: FDI PLL enabling _must_ be done before we enable the
3390 * cpu pipes, hence this is separate from all the other fdi/pch
3391 * enabling. */
88cefb6c 3392 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3393 } else {
3394 assert_fdi_tx_disabled(dev_priv, pipe);
3395 assert_fdi_rx_disabled(dev_priv, pipe);
3396 }
f67a559d 3397
b074cec8 3398 ironlake_pfit_enable(intel_crtc);
f67a559d 3399
9c54c0dd
JB		 3400 /*
3401 * On ILK+ LUT must be loaded before the pipe is running but with
3402 * clocks enabled
3403 */
3404 intel_crtc_load_lut(crtc);
3405
f37fcc2a 3406 intel_update_watermarks(crtc);
5bfe2ac0 3407 intel_enable_pipe(dev_priv, pipe,
23538ef1 3408 intel_crtc->config.has_pch_encoder, false);
f67a559d 3409 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3410 intel_enable_planes(crtc);
5c38d48c 3411 intel_crtc_update_cursor(crtc, true);
f67a559d 3412
5bfe2ac0 3413 if (intel_crtc->config.has_pch_encoder)
f67a559d 3414 ironlake_pch_enable(crtc);
c98e9dcf 3415
d1ebd816 3416 mutex_lock(&dev->struct_mutex);
bed4a673 3417 intel_update_fbc(dev);
d1ebd816
BW		 3418 mutex_unlock(&dev->struct_mutex);
3419
fa5c73b1
DV		 3420 for_each_encoder_on_crtc(dev, crtc, encoder)
3421 encoder->enable(encoder);
61b77ddd
DV		 3422
3423 if (HAS_PCH_CPT(dev))
a1520318 3424 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3425
3426 /*
3427 * There seems to be a race in PCH platform hw (at least on some
3428 * outputs) where an enabled pipe still completes any pageflip right
3429 * away (as if the pipe is off) instead of waiting for vblank. As soon
3430 * as the first vblank happend, everything works as expected. Hence just
3431 * wait for one vblank before returning to avoid strange things
3432 * happening.
3433 */
3434 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3435}
3436
42db64ef
PZ		 3437/* IPS only exists on ULT machines and is tied to pipe A. */
3438static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3439{
f5adf94e 3440 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 3441}
3442
4f771f10
PZ		 3443static void haswell_crtc_enable(struct drm_crtc *crtc)
3444{
3445 struct drm_device *dev = crtc->dev;
3446 struct drm_i915_private *dev_priv = dev->dev_private;
3447 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3448 struct intel_encoder *encoder;
3449 int pipe = intel_crtc->pipe;
3450 int plane = intel_crtc->plane;
4f771f10
PZ		 3451
3452 WARN_ON(!crtc->enabled);
3453
3454 if (intel_crtc->active)
3455 return;
3456
3457 intel_crtc->active = true;
8664281b
PZ		 3458
3459 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3460 if (intel_crtc->config.has_pch_encoder)
3461 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3462
5bfe2ac0 3463 if (intel_crtc->config.has_pch_encoder)
04945641 3464 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3465
3466 for_each_encoder_on_crtc(dev, crtc, encoder)
3467 if (encoder->pre_enable)
3468 encoder->pre_enable(encoder);
3469
1f544388 3470 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3471
b074cec8 3472 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3473
3474 /*
3475 * On ILK+ LUT must be loaded before the pipe is running but with
3476 * clocks enabled
3477 */
3478 intel_crtc_load_lut(crtc);
3479
1f544388 3480 intel_ddi_set_pipe_settings(crtc);
8228c251 3481 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3482
f37fcc2a 3483 intel_update_watermarks(crtc);
5bfe2ac0 3484 intel_enable_pipe(dev_priv, pipe,
23538ef1 3485 intel_crtc->config.has_pch_encoder, false);
4f771f10 3486 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3487 intel_enable_planes(crtc);
5c38d48c 3488 intel_crtc_update_cursor(crtc, true);
4f771f10 3489
42db64ef
PZ		 3490 hsw_enable_ips(intel_crtc);
3491
5bfe2ac0 3492 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3493 lpt_pch_enable(crtc);
4f771f10
PZ		 3494
3495 mutex_lock(&dev->struct_mutex);
3496 intel_update_fbc(dev);
3497 mutex_unlock(&dev->struct_mutex);
3498
8807e55b 3499 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 3500 encoder->enable(encoder);
8807e55b
JN		 3501 intel_opregion_notify_encoder(encoder, true);
3502 }
4f771f10 3503
4f771f10
PZ		 3504 /*
3505 * There seems to be a race in PCH platform hw (at least on some
3506 * outputs) where an enabled pipe still completes any pageflip right
3507 * away (as if the pipe is off) instead of waiting for vblank. As soon
3508 * as the first vblank happend, everything works as expected. Hence just
3509 * wait for one vblank before returning to avoid strange things
3510 * happening.
3511 */
3512 intel_wait_for_vblank(dev, intel_crtc->pipe);
3513}
3514
3f8dce3a
DV		 3515static void ironlake_pfit_disable(struct intel_crtc *crtc)
3516{
3517 struct drm_device *dev = crtc->base.dev;
3518 struct drm_i915_private *dev_priv = dev->dev_private;
3519 int pipe = crtc->pipe;
3520
3521 /* To avoid upsetting the power well on haswell only disable the pfit if
3522 * it's in use. The hw state code will make sure we get this right. */
fd4daa9c 3523 if (crtc->config.pch_pfit.enabled) {
3f8dce3a
DV		 3524 I915_WRITE(PF_CTL(pipe), 0);
3525 I915_WRITE(PF_WIN_POS(pipe), 0);
3526 I915_WRITE(PF_WIN_SZ(pipe), 0);
3527 }
3528}
3529
6be4a607
JB		 3530static void ironlake_crtc_disable(struct drm_crtc *crtc)
3531{
3532 struct drm_device *dev = crtc->dev;
3533 struct drm_i915_private *dev_priv = dev->dev_private;
3534 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3535 struct intel_encoder *encoder;
6be4a607
JB		 3536 int pipe = intel_crtc->pipe;
3537 int plane = intel_crtc->plane;
5eddb70b 3538 u32 reg, temp;
b52eb4dc 3539
ef9c3aee 3540
f7abfe8b
CW		 3541 if (!intel_crtc->active)
3542 return;
3543
ea9d758d
DV		 3544 for_each_encoder_on_crtc(dev, crtc, encoder)
3545 encoder->disable(encoder);
3546
e6c3a2a6 3547 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3548 drm_vblank_off(dev, pipe);
913d8d11 3549
5c3fe8b0 3550 if (dev_priv->fbc.plane == plane)
973d04f9 3551 intel_disable_fbc(dev);
2c07245f 3552
0d5b8c61 3553 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3554 intel_disable_planes(crtc);
0d5b8c61
VS		 3555 intel_disable_plane(dev_priv, plane, pipe);
3556
d925c59a
DV		 3557 if (intel_crtc->config.has_pch_encoder)
3558 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3559
b24e7179 3560 intel_disable_pipe(dev_priv, pipe);
32f9d658 3561
3f8dce3a 3562 ironlake_pfit_disable(intel_crtc);
2c07245f 3563
bf49ec8c
DV		 3564 for_each_encoder_on_crtc(dev, crtc, encoder)
3565 if (encoder->post_disable)
3566 encoder->post_disable(encoder);
2c07245f 3567
d925c59a
DV		 3568 if (intel_crtc->config.has_pch_encoder) {
3569 ironlake_fdi_disable(crtc);
913d8d11 3570
d925c59a
DV		 3571 ironlake_disable_pch_transcoder(dev_priv, pipe);
3572 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
6be4a607 3573
d925c59a
DV		 3574 if (HAS_PCH_CPT(dev)) {
3575 /* disable TRANS_DP_CTL */
3576 reg = TRANS_DP_CTL(pipe);
3577 temp = I915_READ(reg);
3578 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3579 TRANS_DP_PORT_SEL_MASK);
3580 temp |= TRANS_DP_PORT_SEL_NONE;
3581 I915_WRITE(reg, temp);
3582
3583 /* disable DPLL_SEL */
3584 temp = I915_READ(PCH_DPLL_SEL);
11887397 3585 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 3586 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 3587 }
e3421a18 3588
d925c59a 3589 /* disable PCH DPLL */
e72f9fbf 3590 intel_disable_shared_dpll(intel_crtc);
8db9d77b 3591
d925c59a
DV		 3592 ironlake_fdi_pll_disable(intel_crtc);
3593 }
6b383a7f 3594
f7abfe8b 3595 intel_crtc->active = false;
46ba614c 3596 intel_update_watermarks(crtc);
d1ebd816
BW		 3597
3598 mutex_lock(&dev->struct_mutex);
6b383a7f 3599 intel_update_fbc(dev);
d1ebd816 3600 mutex_unlock(&dev->struct_mutex);
6be4a607 3601}
1b3c7a47 3602
4f771f10 3603static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3604{
4f771f10
PZ		 3605 struct drm_device *dev = crtc->dev;
3606 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3607 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3608 struct intel_encoder *encoder;
3609 int pipe = intel_crtc->pipe;
3610 int plane = intel_crtc->plane;
3b117c8f 3611 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3612
4f771f10
PZ		 3613 if (!intel_crtc->active)
3614 return;
3615
8807e55b
JN		 3616 for_each_encoder_on_crtc(dev, crtc, encoder) {
3617 intel_opregion_notify_encoder(encoder, false);
4f771f10 3618 encoder->disable(encoder);
8807e55b 3619 }
4f771f10
PZ		 3620
3621 intel_crtc_wait_for_pending_flips(crtc);
3622 drm_vblank_off(dev, pipe);
4f771f10 3623
891348b2 3624 /* FBC must be disabled before disabling the plane on HSW. */
5c3fe8b0 3625 if (dev_priv->fbc.plane == plane)
4f771f10
PZ		 3626 intel_disable_fbc(dev);
3627
42db64ef
PZ		 3628 hsw_disable_ips(intel_crtc);
3629
0d5b8c61 3630 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3631 intel_disable_planes(crtc);
891348b2
RV		 3632 intel_disable_plane(dev_priv, plane, pipe);
3633
8664281b
PZ		 3634 if (intel_crtc->config.has_pch_encoder)
3635 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3636 intel_disable_pipe(dev_priv, pipe);
3637
ad80a810 3638 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3639
3f8dce3a 3640 ironlake_pfit_disable(intel_crtc);
4f771f10 3641
1f544388 3642 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3643
3644 for_each_encoder_on_crtc(dev, crtc, encoder)
3645 if (encoder->post_disable)
3646 encoder->post_disable(encoder);
3647
88adfff1 3648 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3649 lpt_disable_pch_transcoder(dev_priv);
8664281b 3650 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3651 intel_ddi_fdi_disable(crtc);
83616634 3652 }
4f771f10
PZ		 3653
3654 intel_crtc->active = false;
46ba614c 3655 intel_update_watermarks(crtc);
4f771f10
PZ		 3656
3657 mutex_lock(&dev->struct_mutex);
3658 intel_update_fbc(dev);
3659 mutex_unlock(&dev->struct_mutex);
3660}
3661
ee7b9f93
JB		 3662static void ironlake_crtc_off(struct drm_crtc *crtc)
3663{
3664 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 3665 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 3666}
3667
6441ab5f
PZ		 3668static void haswell_crtc_off(struct drm_crtc *crtc)
3669{
3670 intel_ddi_put_crtc_pll(crtc);
3671}
3672
02e792fb
DV		 3673static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3674{
02e792fb 3675 if (!enable && intel_crtc->overlay) {
23f09ce3 3676 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3677 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3678
23f09ce3 3679 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3680 dev_priv->mm.interruptible = false;
3681 (void) intel_overlay_switch_off(intel_crtc->overlay);
3682 dev_priv->mm.interruptible = true;
23f09ce3 3683 mutex_unlock(&dev->struct_mutex);
02e792fb 3684 }
02e792fb 3685
5dcdbcb0
CW		 3686 /* Let userspace switch the overlay on again. In most cases userspace
3687 * has to recompute where to put it anyway.
3688 */
02e792fb
DV		 3689}
3690
61bc95c1
EE		 3691/**
3692 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3693 * cursor plane briefly if not already running after enabling the display
3694 * plane.
3695 * This workaround avoids occasional blank screens when self refresh is
3696 * enabled.
3697 */
3698static void
3699g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3700{
3701 u32 cntl = I915_READ(CURCNTR(pipe));
3702
3703 if ((cntl & CURSOR_MODE) == 0) {
3704 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3705
3706 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3707 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3708 intel_wait_for_vblank(dev_priv->dev, pipe);
3709 I915_WRITE(CURCNTR(pipe), cntl);
3710 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3711 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3712 }
3713}
3714
2dd24552
JB		 3715static void i9xx_pfit_enable(struct intel_crtc *crtc)
3716{
3717 struct drm_device *dev = crtc->base.dev;
3718 struct drm_i915_private *dev_priv = dev->dev_private;
3719 struct intel_crtc_config *pipe_config = &crtc->config;
3720
328d8e82 3721 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3722 return;
3723
2dd24552 3724 /*
c0b03411
DV		 3725 * The panel fitter should only be adjusted whilst the pipe is disabled,
3726 * according to register description and PRM.
2dd24552 3727 */
c0b03411
DV		 3728 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3729 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3730
b074cec8
JB		 3731 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3732 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3733
3734 /* Border color in case we don't scale up to the full screen. Black by
3735 * default, change to something else for debugging. */
3736 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3737}
3738
89b667f8
JB		 3739static void valleyview_crtc_enable(struct drm_crtc *crtc)
3740{
3741 struct drm_device *dev = crtc->dev;
3742 struct drm_i915_private *dev_priv = dev->dev_private;
3743 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3744 struct intel_encoder *encoder;
3745 int pipe = intel_crtc->pipe;
3746 int plane = intel_crtc->plane;
23538ef1 3747 bool is_dsi;
89b667f8
JB		 3748
3749 WARN_ON(!crtc->enabled);
3750
3751 if (intel_crtc->active)
3752 return;
3753
3754 intel_crtc->active = true;
89b667f8 3755
89b667f8
JB		 3756 for_each_encoder_on_crtc(dev, crtc, encoder)
3757 if (encoder->pre_pll_enable)
3758 encoder->pre_pll_enable(encoder);
3759
23538ef1
JN		 3760 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
3761
e9fd1c02
JN		 3762 if (!is_dsi)
3763 vlv_enable_pll(intel_crtc);
89b667f8
JB		 3764
3765 for_each_encoder_on_crtc(dev, crtc, encoder)
3766 if (encoder->pre_enable)
3767 encoder->pre_enable(encoder);
3768
2dd24552
JB		 3769 i9xx_pfit_enable(intel_crtc);
3770
63cbb074
VS		 3771 intel_crtc_load_lut(crtc);
3772
f37fcc2a 3773 intel_update_watermarks(crtc);
23538ef1 3774 intel_enable_pipe(dev_priv, pipe, false, is_dsi);
89b667f8 3775 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3776 intel_enable_planes(crtc);
5c38d48c 3777 intel_crtc_update_cursor(crtc, true);
89b667f8 3778
89b667f8 3779 intel_update_fbc(dev);
5004945f
JN		 3780
3781 for_each_encoder_on_crtc(dev, crtc, encoder)
3782 encoder->enable(encoder);
89b667f8
JB		 3783}
3784
0b8765c6 3785static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3786{
3787 struct drm_device *dev = crtc->dev;
79e53945
JB		 3788 struct drm_i915_private *dev_priv = dev->dev_private;
3789 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3790 struct intel_encoder *encoder;
79e53945 3791 int pipe = intel_crtc->pipe;
80824003 3792 int plane = intel_crtc->plane;
79e53945 3793
08a48469
DV		 3794 WARN_ON(!crtc->enabled);
3795
f7abfe8b
CW		 3796 if (intel_crtc->active)
3797 return;
3798
3799 intel_crtc->active = true;
6b383a7f 3800
9d6d9f19
MK		 3801 for_each_encoder_on_crtc(dev, crtc, encoder)
3802 if (encoder->pre_enable)
3803 encoder->pre_enable(encoder);
3804
f6736a1a
DV		 3805 i9xx_enable_pll(intel_crtc);
3806
2dd24552
JB		 3807 i9xx_pfit_enable(intel_crtc);
3808
63cbb074
VS		 3809 intel_crtc_load_lut(crtc);
3810
f37fcc2a 3811 intel_update_watermarks(crtc);
23538ef1 3812 intel_enable_pipe(dev_priv, pipe, false, false);
b24e7179 3813 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3814 intel_enable_planes(crtc);
22e407d7 3815 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE		 3816 if (IS_G4X(dev))
3817 g4x_fixup_plane(dev_priv, pipe);
22e407d7 3818 intel_crtc_update_cursor(crtc, true);
79e53945 3819
0b8765c6
JB		 3820 /* Give the overlay scaler a chance to enable if it's on this pipe */
3821 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3822
f440eb13 3823 intel_update_fbc(dev);
ef9c3aee 3824
fa5c73b1
DV		 3825 for_each_encoder_on_crtc(dev, crtc, encoder)
3826 encoder->enable(encoder);
0b8765c6 3827}
79e53945 3828
87476d63
DV		 3829static void i9xx_pfit_disable(struct intel_crtc *crtc)
3830{
3831 struct drm_device *dev = crtc->base.dev;
3832 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3833
328d8e82
DV		 3834 if (!crtc->config.gmch_pfit.control)
3835 return;
87476d63 3836
328d8e82 3837 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3838
328d8e82
DV		 3839 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3840 I915_READ(PFIT_CONTROL));
3841 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3842}
3843
0b8765c6
JB		 3844static void i9xx_crtc_disable(struct drm_crtc *crtc)
3845{
3846 struct drm_device *dev = crtc->dev;
3847 struct drm_i915_private *dev_priv = dev->dev_private;
3848 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3849 struct intel_encoder *encoder;
0b8765c6
JB		 3850 int pipe = intel_crtc->pipe;
3851 int plane = intel_crtc->plane;
ef9c3aee 3852
f7abfe8b
CW		 3853 if (!intel_crtc->active)
3854 return;
3855
ea9d758d
DV		 3856 for_each_encoder_on_crtc(dev, crtc, encoder)
3857 encoder->disable(encoder);
3858
0b8765c6 3859 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3860 intel_crtc_wait_for_pending_flips(crtc);
3861 drm_vblank_off(dev, pipe);
0b8765c6 3862
5c3fe8b0 3863 if (dev_priv->fbc.plane == plane)
973d04f9 3864 intel_disable_fbc(dev);
79e53945 3865
0d5b8c61
VS		 3866 intel_crtc_dpms_overlay(intel_crtc, false);
3867 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3868 intel_disable_planes(crtc);
b24e7179 3869 intel_disable_plane(dev_priv, plane, pipe);
0d5b8c61 3870
b24e7179 3871 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3872
87476d63 3873 i9xx_pfit_disable(intel_crtc);
24a1f16d 3874
89b667f8
JB		 3875 for_each_encoder_on_crtc(dev, crtc, encoder)
3876 if (encoder->post_disable)
3877 encoder->post_disable(encoder);
3878
e9fd1c02
JN		 3879 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3880 i9xx_disable_pll(dev_priv, pipe);
0b8765c6 3881
f7abfe8b 3882 intel_crtc->active = false;
46ba614c 3883 intel_update_watermarks(crtc);
f37fcc2a 3884
6b383a7f 3885 intel_update_fbc(dev);
0b8765c6
JB		 3886}
3887
ee7b9f93
JB		 3888static void i9xx_crtc_off(struct drm_crtc *crtc)
3889{
3890}
3891
976f8a20
DV		 3892static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3893 bool enabled)
2c07245f
ZW		 3894{
3895 struct drm_device *dev = crtc->dev;
3896 struct drm_i915_master_private *master_priv;
3897 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3898 int pipe = intel_crtc->pipe;
79e53945
JB		 3899
3900 if (!dev->primary->master)
3901 return;
3902
3903 master_priv = dev->primary->master->driver_priv;
3904 if (!master_priv->sarea_priv)
3905 return;
3906
79e53945
JB		 3907 switch (pipe) {
3908 case 0:
3909 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3910 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3911 break;
3912 case 1:
3913 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3914 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3915 break;
3916 default:
9db4a9c7 3917 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3918 break;
3919 }
79e53945
JB		 3920}
3921
976f8a20
DV		 3922/**
3923 * Sets the power management mode of the pipe and plane.
3924 */
3925void intel_crtc_update_dpms(struct drm_crtc *crtc)
3926{
3927 struct drm_device *dev = crtc->dev;
3928 struct drm_i915_private *dev_priv = dev->dev_private;
3929 struct intel_encoder *intel_encoder;
3930 bool enable = false;
3931
3932 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3933 enable |= intel_encoder->connectors_active;
3934
3935 if (enable)
3936 dev_priv->display.crtc_enable(crtc);
3937 else
3938 dev_priv->display.crtc_disable(crtc);
3939
3940 intel_crtc_update_sarea(crtc, enable);
3941}
3942
cdd59983
CW		 3943static void intel_crtc_disable(struct drm_crtc *crtc)
3944{
cdd59983 3945 struct drm_device *dev = crtc->dev;
976f8a20 3946 struct drm_connector *connector;
ee7b9f93 3947 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3948 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3949
976f8a20
DV		 3950 /* crtc should still be enabled when we disable it. */
3951 WARN_ON(!crtc->enabled);
3952
3953 dev_priv->display.crtc_disable(crtc);
c77bf565 3954 intel_crtc->eld_vld = false;
976f8a20 3955 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3956 dev_priv->display.off(crtc);
3957
931872fc 3958 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
93ce0ba6 3959 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
931872fc 3960 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3961
3962 if (crtc->fb) {
3963 mutex_lock(&dev->struct_mutex);
1690e1eb 3964 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3965 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3966 crtc->fb = NULL;
3967 }
3968
3969 /* Update computed state. */
3970 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3971 if (!connector->encoder || !connector->encoder->crtc)
3972 continue;
3973
3974 if (connector->encoder->crtc != crtc)
3975 continue;
3976
3977 connector->dpms = DRM_MODE_DPMS_OFF;
3978 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3979 }
3980}
3981
ea5b213a 3982void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3983{
4ef69c7a 3984 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3985
ea5b213a
CW		 3986 drm_encoder_cleanup(encoder);
3987 kfree(intel_encoder);
7e7d76c3
JB		 3988}
3989
9237329d 3990/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 3991 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3992 * state of the entire output pipe. */
9237329d 3993static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3994{
5ab432ef
DV		 3995 if (mode == DRM_MODE_DPMS_ON) {
3996 encoder->connectors_active = true;
3997
b2cabb0e 3998 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3999 } else {
4000 encoder->connectors_active = false;
4001
b2cabb0e 4002 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 4003 }
79e53945
JB		 4004}
4005
0a91ca29
DV		 4006/* Cross check the actual hw state with our own modeset state tracking (and it's
4007 * internal consistency). */
b980514c 4008static void intel_connector_check_state(struct intel_connector *connector)
79e53945 4009{
0a91ca29
DV		 4010 if (connector->get_hw_state(connector)) {
4011 struct intel_encoder *encoder = connector->encoder;
4012 struct drm_crtc *crtc;
4013 bool encoder_enabled;
4014 enum pipe pipe;
4015
4016 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4017 connector->base.base.id,
4018 drm_get_connector_name(&connector->base));
4019
4020 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4021 "wrong connector dpms state\n");
4022 WARN(connector->base.encoder != &encoder->base,
4023 "active connector not linked to encoder\n");
4024 WARN(!encoder->connectors_active,
4025 "encoder->connectors_active not set\n");
4026
4027 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4028 WARN(!encoder_enabled, "encoder not enabled\n");
4029 if (WARN_ON(!encoder->base.crtc))
4030 return;
4031
4032 crtc = encoder->base.crtc;
4033
4034 WARN(!crtc->enabled, "crtc not enabled\n");
4035 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4036 WARN(pipe != to_intel_crtc(crtc)->pipe,
4037 "encoder active on the wrong pipe\n");
4038 }
79e53945
JB		 4039}
4040
5ab432ef
DV		 4041/* Even simpler default implementation, if there's really no special case to
4042 * consider. */
4043void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 4044{
5ab432ef 4045 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 4046
5ab432ef
DV		 4047 /* All the simple cases only support two dpms states. */
4048 if (mode != DRM_MODE_DPMS_ON)
4049 mode = DRM_MODE_DPMS_OFF;
d4270e57 4050
5ab432ef
DV		 4051 if (mode == connector->dpms)
4052 return;
4053
4054 connector->dpms = mode;
4055
4056 /* Only need to change hw state when actually enabled */
4057 if (encoder->base.crtc)
4058 intel_encoder_dpms(encoder, mode);
4059 else
8af6cf88 4060 WARN_ON(encoder->connectors_active != false);
0a91ca29 4061
b980514c 4062 intel_modeset_check_state(connector->dev);
79e53945
JB		 4063}
4064
f0947c37
DV		 4065/* Simple connector->get_hw_state implementation for encoders that support only
4066 * one connector and no cloning and hence the encoder state determines the state
4067 * of the connector. */
4068bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 4069{
24929352 4070 enum pipe pipe = 0;
f0947c37 4071 struct intel_encoder *encoder = connector->encoder;
ea5b213a 4072
f0947c37 4073 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 4074}
4075
1857e1da
DV		 4076static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4077 struct intel_crtc_config *pipe_config)
4078{
4079 struct drm_i915_private *dev_priv = dev->dev_private;
4080 struct intel_crtc *pipe_B_crtc =
4081 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4082
4083 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4084 pipe_name(pipe), pipe_config->fdi_lanes);
4085 if (pipe_config->fdi_lanes > 4) {
4086 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4087 pipe_name(pipe), pipe_config->fdi_lanes);
4088 return false;
4089 }
4090
4091 if (IS_HASWELL(dev)) {
4092 if (pipe_config->fdi_lanes > 2) {
4093 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4094 pipe_config->fdi_lanes);
4095 return false;
4096 } else {
4097 return true;
4098 }
4099 }
4100
4101 if (INTEL_INFO(dev)->num_pipes == 2)
4102 return true;
4103
4104 /* Ivybridge 3 pipe is really complicated */
4105 switch (pipe) {
4106 case PIPE_A:
4107 return true;
4108 case PIPE_B:
4109 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4110 pipe_config->fdi_lanes > 2) {
4111 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4112 pipe_name(pipe), pipe_config->fdi_lanes);
4113 return false;
4114 }
4115 return true;
4116 case PIPE_C:
1e833f40 4117 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 4118 pipe_B_crtc->config.fdi_lanes <= 2) {
4119 if (pipe_config->fdi_lanes > 2) {
4120 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4121 pipe_name(pipe), pipe_config->fdi_lanes);
4122 return false;
4123 }
4124 } else {
4125 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4126 return false;
4127 }
4128 return true;
4129 default:
4130 BUG();
4131 }
4132}
4133
e29c22c0
DV		 4134#define RETRY 1
4135static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4136 struct intel_crtc_config *pipe_config)
877d48d5 4137{
1857e1da 4138 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 4139 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 4140 int lane, link_bw, fdi_dotclock;
e29c22c0 4141 bool setup_ok, needs_recompute = false;
877d48d5 4142
e29c22c0 4143retry:
877d48d5
DV		 4144 /* FDI is a binary signal running at ~2.7GHz, encoding
4145 * each output octet as 10 bits. The actual frequency
4146 * is stored as a divider into a 100MHz clock, and the
4147 * mode pixel clock is stored in units of 1KHz.
4148 * Hence the bw of each lane in terms of the mode signal
4149 * is:
4150 */
4151 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4152
241bfc38 4153 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 4154
2bd89a07 4155 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4156 pipe_config->pipe_bpp);
4157
4158 pipe_config->fdi_lanes = lane;
4159
2bd89a07 4160 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4161 link_bw, &pipe_config->fdi_m_n);
1857e1da 4162
e29c22c0
DV		 4163 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4164 intel_crtc->pipe, pipe_config);
4165 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4166 pipe_config->pipe_bpp -= 2*3;
4167 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4168 pipe_config->pipe_bpp);
4169 needs_recompute = true;
4170 pipe_config->bw_constrained = true;
4171
4172 goto retry;
4173 }
4174
4175 if (needs_recompute)
4176 return RETRY;
4177
4178 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4179}
4180
42db64ef
PZ		 4181static void hsw_compute_ips_config(struct intel_crtc *crtc,
4182 struct intel_crtc_config *pipe_config)
4183{
3c4ca58c
PZ		 4184 pipe_config->ips_enabled = i915_enable_ips &&
4185 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 4186 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 4187}
4188
a43f6e0f 4189static int intel_crtc_compute_config(struct intel_crtc *crtc,
e29c22c0 4190 struct intel_crtc_config *pipe_config)
79e53945 4191{
a43f6e0f 4192 struct drm_device *dev = crtc->base.dev;
b8cecdf5 4193 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4194
ad3a4479 4195 /* FIXME should check pixel clock limits on all platforms */
cf532bb2
VS		 4196 if (INTEL_INFO(dev)->gen < 4) {
4197 struct drm_i915_private *dev_priv = dev->dev_private;
4198 int clock_limit =
4199 dev_priv->display.get_display_clock_speed(dev);
4200
4201 /*
4202 * Enable pixel doubling when the dot clock
4203 * is > 90% of the (display) core speed.
4204 *
b397c96b
VS		 4205 * GDG double wide on either pipe,
4206 * otherwise pipe A only.
cf532bb2 4207 */
b397c96b 4208 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 4209 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 4210 clock_limit *= 2;
cf532bb2 4211 pipe_config->double_wide = true;
ad3a4479
VS		 4212 }
4213
241bfc38 4214 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 4215 return -EINVAL;
2c07245f 4216 }
89749350 4217
1d1d0e27
VS		 4218 /*
4219 * Pipe horizontal size must be even in:
4220 * - DVO ganged mode
4221 * - LVDS dual channel mode
4222 * - Double wide pipe
4223 */
4224 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4225 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4226 pipe_config->pipe_src_w &= ~1;
4227
8693a824
DL		 4228 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4229 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4230 */
4231 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4232 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4233 return -EINVAL;
44f46b42 4234
bd080ee5 4235 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4236 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4237 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4238 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4239 * for lvds. */
4240 pipe_config->pipe_bpp = 8*3;
4241 }
4242
f5adf94e 4243 if (HAS_IPS(dev))
a43f6e0f
DV		 4244 hsw_compute_ips_config(crtc, pipe_config);
4245
4246 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4247 * clock survives for now. */
4248 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4249 pipe_config->shared_dpll = crtc->config.shared_dpll;
42db64ef 4250
877d48d5 4251 if (pipe_config->has_pch_encoder)
a43f6e0f 4252 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 4253
e29c22c0 4254 return 0;
79e53945
JB		 4255}
4256
25eb05fc
JB		 4257static int valleyview_get_display_clock_speed(struct drm_device *dev)
4258{
4259 return 400000; /* FIXME */
4260}
4261
e70236a8
JB		 4262static int i945_get_display_clock_speed(struct drm_device *dev)
4263{
4264 return 400000;
4265}
79e53945 4266
e70236a8 4267static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4268{
e70236a8
JB		 4269 return 333000;
4270}
79e53945 4271
e70236a8
JB		 4272static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4273{
4274 return 200000;
4275}
79e53945 4276
257a7ffc
DV		 4277static int pnv_get_display_clock_speed(struct drm_device *dev)
4278{
4279 u16 gcfgc = 0;
4280
4281 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4282
4283 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4284 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4285 return 267000;
4286 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4287 return 333000;
4288 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4289 return 444000;
4290 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4291 return 200000;
4292 default:
4293 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4294 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4295 return 133000;
4296 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4297 return 167000;
4298 }
4299}
4300
e70236a8
JB		 4301static int i915gm_get_display_clock_speed(struct drm_device *dev)
4302{
4303 u16 gcfgc = 0;
79e53945 4304
e70236a8
JB		 4305 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4306
4307 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4308 return 133000;
4309 else {
4310 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4311 case GC_DISPLAY_CLOCK_333_MHZ:
4312 return 333000;
4313 default:
4314 case GC_DISPLAY_CLOCK_190_200_MHZ:
4315 return 190000;
79e53945 4316 }
e70236a8
JB		 4317 }
4318}
4319
4320static int i865_get_display_clock_speed(struct drm_device *dev)
4321{
4322 return 266000;
4323}
4324
4325static int i855_get_display_clock_speed(struct drm_device *dev)
4326{
4327 u16 hpllcc = 0;
4328 /* Assume that the hardware is in the high speed state. This
4329 * should be the default.
4330 */
4331 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4332 case GC_CLOCK_133_200:
4333 case GC_CLOCK_100_200:
4334 return 200000;
4335 case GC_CLOCK_166_250:
4336 return 250000;
4337 case GC_CLOCK_100_133:
79e53945 4338 return 133000;
e70236a8 4339 }
79e53945 4340
e70236a8
JB		 4341 /* Shouldn't happen */
4342 return 0;
4343}
79e53945 4344
e70236a8
JB		 4345static int i830_get_display_clock_speed(struct drm_device *dev)
4346{
4347 return 133000;
79e53945
JB		 4348}
4349
2c07245f 4350static void
a65851af 4351intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4352{
a65851af
VS		 4353 while (*num > DATA_LINK_M_N_MASK ||
4354 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4355 *num >>= 1;
4356 *den >>= 1;
4357 }
4358}
4359
a65851af
VS		 4360static void compute_m_n(unsigned int m, unsigned int n,
4361 uint32_t *ret_m, uint32_t *ret_n)
4362{
4363 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4364 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4365 intel_reduce_m_n_ratio(ret_m, ret_n);
4366}
4367
e69d0bc1
DV		 4368void
4369intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4370 int pixel_clock, int link_clock,
4371 struct intel_link_m_n *m_n)
2c07245f 4372{
e69d0bc1 4373 m_n->tu = 64;
a65851af
VS		 4374
4375 compute_m_n(bits_per_pixel * pixel_clock,
4376 link_clock * nlanes * 8,
4377 &m_n->gmch_m, &m_n->gmch_n);
4378
4379 compute_m_n(pixel_clock, link_clock,
4380 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4381}
4382
a7615030
CW		 4383static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4384{
72bbe58c
KP		 4385 if (i915_panel_use_ssc >= 0)
4386 return i915_panel_use_ssc != 0;
41aa3448 4387 return dev_priv->vbt.lvds_use_ssc
435793df 4388 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4389}
4390
c65d77d8
JB		 4391static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4392{
4393 struct drm_device *dev = crtc->dev;
4394 struct drm_i915_private *dev_priv = dev->dev_private;
4395 int refclk;
4396
a0c4da24 4397 if (IS_VALLEYVIEW(dev)) {
9a0ea498 4398 refclk = 100000;
a0c4da24 4399 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4400 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4401 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4402 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4403 refclk / 1000);
4404 } else if (!IS_GEN2(dev)) {
4405 refclk = 96000;
4406 } else {
4407 refclk = 48000;
4408 }
4409
4410 return refclk;
4411}
4412
7429e9d4 4413static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 4414{
7df00d7a 4415 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 4416}
f47709a9 4417
7429e9d4
DV		 4418static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4419{
4420 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 4421}
4422
f47709a9 4423static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4424 intel_clock_t *reduced_clock)
4425{
f47709a9 4426 struct drm_device *dev = crtc->base.dev;
a7516a05 4427 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4428 int pipe = crtc->pipe;
a7516a05
JB		 4429 u32 fp, fp2 = 0;
4430
4431 if (IS_PINEVIEW(dev)) {
7429e9d4 4432 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4433 if (reduced_clock)
7429e9d4 4434 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4435 } else {
7429e9d4 4436 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4437 if (reduced_clock)
7429e9d4 4438 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4439 }
4440
4441 I915_WRITE(FP0(pipe), fp);
8bcc2795 4442 crtc->config.dpll_hw_state.fp0 = fp;
a7516a05 4443
f47709a9
DV		 4444 crtc->lowfreq_avail = false;
4445 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4446 reduced_clock && i915_powersave) {
4447 I915_WRITE(FP1(pipe), fp2);
8bcc2795 4448 crtc->config.dpll_hw_state.fp1 = fp2;
f47709a9 4449 crtc->lowfreq_avail = true;
a7516a05
JB		 4450 } else {
4451 I915_WRITE(FP1(pipe), fp);
8bcc2795 4452 crtc->config.dpll_hw_state.fp1 = fp;
a7516a05
JB		 4453 }
4454}
4455
5e69f97f
CML		 4456static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4457 pipe)
89b667f8
JB		 4458{
4459 u32 reg_val;
4460
4461 /*
4462 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4463 * and set it to a reasonable value instead.
4464 */
5e69f97f 4465 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8
JB		 4466 reg_val &= 0xffffff00;
4467 reg_val |= 0x00000030;
5e69f97f 4468 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4469
5e69f97f 4470 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4471 reg_val &= 0x8cffffff;
4472 reg_val = 0x8c000000;
5e69f97f 4473 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8 4474
5e69f97f 4475 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8 4476 reg_val &= 0xffffff00;
5e69f97f 4477 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4478
5e69f97f 4479 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4480 reg_val &= 0x00ffffff;
4481 reg_val |= 0xb0000000;
5e69f97f 4482 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4483}
4484
b551842d
DV		 4485static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4486 struct intel_link_m_n *m_n)
4487{
4488 struct drm_device *dev = crtc->base.dev;
4489 struct drm_i915_private *dev_priv = dev->dev_private;
4490 int pipe = crtc->pipe;
4491
e3b95f1e
DV		 4492 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4493 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4494 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4495 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4496}
4497
4498static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4499 struct intel_link_m_n *m_n)
4500{
4501 struct drm_device *dev = crtc->base.dev;
4502 struct drm_i915_private *dev_priv = dev->dev_private;
4503 int pipe = crtc->pipe;
4504 enum transcoder transcoder = crtc->config.cpu_transcoder;
4505
4506 if (INTEL_INFO(dev)->gen >= 5) {
4507 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4508 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4509 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4510 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4511 } else {
e3b95f1e
DV		 4512 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4513 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4514 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4515 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4516 }
4517}
4518
03afc4a2
DV		 4519static void intel_dp_set_m_n(struct intel_crtc *crtc)
4520{
4521 if (crtc->config.has_pch_encoder)
4522 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4523 else
4524 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4525}
4526
f47709a9 4527static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4528{
f47709a9 4529 struct drm_device *dev = crtc->base.dev;
a0c4da24 4530 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4531 int pipe = crtc->pipe;
89b667f8 4532 u32 dpll, mdiv;
a0c4da24 4533 u32 bestn, bestm1, bestm2, bestp1, bestp2;
198a037f 4534 u32 coreclk, reg_val, dpll_md;
a0c4da24 4535
09153000
DV		 4536 mutex_lock(&dev_priv->dpio_lock);
4537
f47709a9
DV		 4538 bestn = crtc->config.dpll.n;
4539 bestm1 = crtc->config.dpll.m1;
4540 bestm2 = crtc->config.dpll.m2;
4541 bestp1 = crtc->config.dpll.p1;
4542 bestp2 = crtc->config.dpll.p2;
a0c4da24 4543
89b667f8
JB		 4544 /* See eDP HDMI DPIO driver vbios notes doc */
4545
4546 /* PLL B needs special handling */
4547 if (pipe)
5e69f97f 4548 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 4549
4550 /* Set up Tx target for periodic Rcomp update */
5e69f97f 4551 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4552
4553 /* Disable target IRef on PLL */
5e69f97f 4554 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
89b667f8 4555 reg_val &= 0x00ffffff;
5e69f97f 4556 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4557
4558 /* Disable fast lock */
5e69f97f 4559 vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4560
4561 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4562 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4563 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4564 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4565 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4566
4567 /*
4568 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4569 * but we don't support that).
4570 * Note: don't use the DAC post divider as it seems unstable.
4571 */
4572 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5e69f97f 4573 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4574
a0c4da24 4575 mdiv |= DPIO_ENABLE_CALIBRATION;
5e69f97f 4576 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4577
89b667f8 4578 /* Set HBR and RBR LPF coefficients */
ff9a6750 4579 if (crtc->config.port_clock == 162000 ||
99750bd4 4580 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
89b667f8 4581 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5e69f97f 4582 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
885b0120 4583 0x009f0003);
89b667f8 4584 else
5e69f97f 4585 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
89b667f8
JB		 4586 0x00d0000f);
4587
4588 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4589 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4590 /* Use SSC source */
4591 if (!pipe)
5e69f97f 4592 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4593 0x0df40000);
4594 else
5e69f97f 4595 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4596 0x0df70000);
4597 } else { /* HDMI or VGA */
4598 /* Use bend source */
4599 if (!pipe)
5e69f97f 4600 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4601 0x0df70000);
4602 else
5e69f97f 4603 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4604 0x0df40000);
4605 }
a0c4da24 4606
5e69f97f 4607 coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4608 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4609 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4610 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4611 coreclk |= 0x01000000;
5e69f97f 4612 vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4613
5e69f97f 4614 vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4615
89b667f8
JB		 4616 /* Enable DPIO clock input */
4617 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4618 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4619 if (pipe)
4620 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
a0c4da24
JB		 4621
4622 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4623 crtc->config.dpll_hw_state.dpll = dpll;
4624
ef1b460d
DV		 4625 dpll_md = (crtc->config.pixel_multiplier - 1)
4626 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795
DV		 4627 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4628
89b667f8
JB		 4629 if (crtc->config.has_dp_encoder)
4630 intel_dp_set_m_n(crtc);
09153000
DV		 4631
4632 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4633}
4634
f47709a9
DV		 4635static void i9xx_update_pll(struct intel_crtc *crtc,
4636 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4637 int num_connectors)
4638{
f47709a9 4639 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4640 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 4641 u32 dpll;
4642 bool is_sdvo;
f47709a9 4643 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4644
f47709a9 4645 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4646
f47709a9
DV		 4647 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4648 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4649
4650 dpll = DPLL_VGA_MODE_DIS;
4651
f47709a9 4652 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4653 dpll |= DPLLB_MODE_LVDS;
4654 else
4655 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4656
ef1b460d 4657 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4658 dpll |= (crtc->config.pixel_multiplier - 1)
4659 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4660 }
198a037f
DV		 4661
4662 if (is_sdvo)
4a33e48d 4663 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 4664
f47709a9 4665 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4a33e48d 4666 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 4667
4668 /* compute bitmask from p1 value */
4669 if (IS_PINEVIEW(dev))
4670 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4671 else {
4672 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4673 if (IS_G4X(dev) && reduced_clock)
4674 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4675 }
4676 switch (clock->p2) {
4677 case 5:
4678 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4679 break;
4680 case 7:
4681 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4682 break;
4683 case 10:
4684 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4685 break;
4686 case 14:
4687 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4688 break;
4689 }
4690 if (INTEL_INFO(dev)->gen >= 4)
4691 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4692
09ede541 4693 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4694 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4695 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4696 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4697 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4698 else
4699 dpll |= PLL_REF_INPUT_DREFCLK;
4700
4701 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4702 crtc->config.dpll_hw_state.dpll = dpll;
4703
eb1cbe48 4704 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4705 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4706 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795 4707 crtc->config.dpll_hw_state.dpll_md = dpll_md;
eb1cbe48 4708 }
66e3d5c0
DV		 4709
4710 if (crtc->config.has_dp_encoder)
4711 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4712}
4713
f47709a9 4714static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4715 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4716 int num_connectors)
4717{
f47709a9 4718 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4719 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 4720 u32 dpll;
f47709a9 4721 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4722
f47709a9 4723 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4724
eb1cbe48
DV		 4725 dpll = DPLL_VGA_MODE_DIS;
4726
f47709a9 4727 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4728 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4729 } else {
4730 if (clock->p1 == 2)
4731 dpll |= PLL_P1_DIVIDE_BY_TWO;
4732 else
4733 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4734 if (clock->p2 == 4)
4735 dpll |= PLL_P2_DIVIDE_BY_4;
4736 }
4737
4a33e48d
DV		 4738 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4739 dpll |= DPLL_DVO_2X_MODE;
4740
f47709a9 4741 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4742 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4743 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4744 else
4745 dpll |= PLL_REF_INPUT_DREFCLK;
4746
4747 dpll |= DPLL_VCO_ENABLE;
8bcc2795 4748 crtc->config.dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 4749}
4750
8a654f3b 4751static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4752{
4753 struct drm_device *dev = intel_crtc->base.dev;
4754 struct drm_i915_private *dev_priv = dev->dev_private;
4755 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4756 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4757 struct drm_display_mode *adjusted_mode =
4758 &intel_crtc->config.adjusted_mode;
4d8a62ea
DV		 4759 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4760
4761 /* We need to be careful not to changed the adjusted mode, for otherwise
4762 * the hw state checker will get angry at the mismatch. */
4763 crtc_vtotal = adjusted_mode->crtc_vtotal;
4764 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4765
4766 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4767 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4768 crtc_vtotal -= 1;
4769 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4770 vsyncshift = adjusted_mode->crtc_hsync_start
4771 - adjusted_mode->crtc_htotal / 2;
4772 } else {
4773 vsyncshift = 0;
4774 }
4775
4776 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4777 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4778
fe2b8f9d 4779 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4780 (adjusted_mode->crtc_hdisplay - 1) |
4781 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4782 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4783 (adjusted_mode->crtc_hblank_start - 1) |
4784 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4785 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4786 (adjusted_mode->crtc_hsync_start - 1) |
4787 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4788
fe2b8f9d 4789 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4790 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4791 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4792 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4793 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4794 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4795 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4796 (adjusted_mode->crtc_vsync_start - 1) |
4797 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4798
b5e508d4
PZ		 4799 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4800 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4801 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4802 * bits. */
4803 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4804 (pipe == PIPE_B || pipe == PIPE_C))
4805 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4806
b0e77b9c
PZ		 4807 /* pipesrc controls the size that is scaled from, which should
4808 * always be the user's requested size.
4809 */
4810 I915_WRITE(PIPESRC(pipe),
37327abd
VS		 4811 ((intel_crtc->config.pipe_src_w - 1) << 16) |
4812 (intel_crtc->config.pipe_src_h - 1));
b0e77b9c
PZ		 4813}
4814
1bd1bd80
DV		 4815static void intel_get_pipe_timings(struct intel_crtc *crtc,
4816 struct intel_crtc_config *pipe_config)
4817{
4818 struct drm_device *dev = crtc->base.dev;
4819 struct drm_i915_private *dev_priv = dev->dev_private;
4820 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4821 uint32_t tmp;
4822
4823 tmp = I915_READ(HTOTAL(cpu_transcoder));
4824 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4825 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4826 tmp = I915_READ(HBLANK(cpu_transcoder));
4827 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4828 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4829 tmp = I915_READ(HSYNC(cpu_transcoder));
4830 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4831 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4832
4833 tmp = I915_READ(VTOTAL(cpu_transcoder));
4834 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4835 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4836 tmp = I915_READ(VBLANK(cpu_transcoder));
4837 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4838 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4839 tmp = I915_READ(VSYNC(cpu_transcoder));
4840 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4841 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4842
4843 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4844 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4845 pipe_config->adjusted_mode.crtc_vtotal += 1;
4846 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4847 }
4848
4849 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 4850 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
4851 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
4852
4853 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
4854 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 4855}
4856
babea61d
JB		 4857static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4858 struct intel_crtc_config *pipe_config)
4859{
4860 struct drm_crtc *crtc = &intel_crtc->base;
4861
4862 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4863 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4864 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4865 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4866
4867 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4868 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4869 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4870 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4871
4872 crtc->mode.flags = pipe_config->adjusted_mode.flags;
4873
241bfc38 4874 crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock;
babea61d
JB		 4875 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4876}
4877
84b046f3
DV		 4878static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4879{
4880 struct drm_device *dev = intel_crtc->base.dev;
4881 struct drm_i915_private *dev_priv = dev->dev_private;
4882 uint32_t pipeconf;
4883
9f11a9e4 4884 pipeconf = 0;
84b046f3 4885
67c72a12
DV		 4886 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
4887 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
4888 pipeconf |= PIPECONF_ENABLE;
4889
cf532bb2
VS		 4890 if (intel_crtc->config.double_wide)
4891 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 4892
ff9ce46e
DV		 4893 /* only g4x and later have fancy bpc/dither controls */
4894 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e
DV		 4895 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4896 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4897 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4898 PIPECONF_DITHER_TYPE_SP;
84b046f3 4899
ff9ce46e
DV		 4900 switch (intel_crtc->config.pipe_bpp) {
4901 case 18:
4902 pipeconf |= PIPECONF_6BPC;
4903 break;
4904 case 24:
4905 pipeconf |= PIPECONF_8BPC;
4906 break;
4907 case 30:
4908 pipeconf |= PIPECONF_10BPC;
4909 break;
4910 default:
4911 /* Case prevented by intel_choose_pipe_bpp_dither. */
4912 BUG();
84b046f3
DV		 4913 }
4914 }
4915
4916 if (HAS_PIPE_CXSR(dev)) {
4917 if (intel_crtc->lowfreq_avail) {
4918 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4919 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4920 } else {
4921 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 4922 }
4923 }
4924
84b046f3
DV		 4925 if (!IS_GEN2(dev) &&
4926 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4927 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4928 else
4929 pipeconf |= PIPECONF_PROGRESSIVE;
4930
9f11a9e4
DV		 4931 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4932 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 4933
84b046f3
DV		 4934 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4935 POSTING_READ(PIPECONF(intel_crtc->pipe));
4936}
4937
f564048e 4938static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4939 int x, int y,
94352cf9 4940 struct drm_framebuffer *fb)
79e53945
JB		 4941{
4942 struct drm_device *dev = crtc->dev;
4943 struct drm_i915_private *dev_priv = dev->dev_private;
4944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4945 int pipe = intel_crtc->pipe;
80824003 4946 int plane = intel_crtc->plane;
c751ce4f 4947 int refclk, num_connectors = 0;
652c393a 4948 intel_clock_t clock, reduced_clock;
84b046f3 4949 u32 dspcntr;
a16af721 4950 bool ok, has_reduced_clock = false;
e9fd1c02 4951 bool is_lvds = false, is_dsi = false;
5eddb70b 4952 struct intel_encoder *encoder;
d4906093 4953 const intel_limit_t *limit;
5c3b82e2 4954 int ret;
79e53945 4955
6c2b7c12 4956 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4957 switch (encoder->type) {
79e53945
JB		 4958 case INTEL_OUTPUT_LVDS:
4959 is_lvds = true;
4960 break;
e9fd1c02
JN		 4961 case INTEL_OUTPUT_DSI:
4962 is_dsi = true;
4963 break;
79e53945 4964 }
43565a06 4965
c751ce4f 4966 num_connectors++;
79e53945
JB		 4967 }
4968
f2335330
JN		 4969 if (is_dsi)
4970 goto skip_dpll;
4971
4972 if (!intel_crtc->config.clock_set) {
4973 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4974
e9fd1c02
JN		 4975 /*
4976 * Returns a set of divisors for the desired target clock with
4977 * the given refclk, or FALSE. The returned values represent
4978 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
4979 * 2) / p1 / p2.
4980 */
4981 limit = intel_limit(crtc, refclk);
4982 ok = dev_priv->display.find_dpll(limit, crtc,
4983 intel_crtc->config.port_clock,
4984 refclk, NULL, &clock);
f2335330 4985 if (!ok) {
e9fd1c02
JN		 4986 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4987 return -EINVAL;
4988 }
79e53945 4989
f2335330
JN		 4990 if (is_lvds && dev_priv->lvds_downclock_avail) {
4991 /*
4992 * Ensure we match the reduced clock's P to the target
4993 * clock. If the clocks don't match, we can't switch
4994 * the display clock by using the FP0/FP1. In such case
4995 * we will disable the LVDS downclock feature.
4996 */
4997 has_reduced_clock =
4998 dev_priv->display.find_dpll(limit, crtc,
4999 dev_priv->lvds_downclock,
5000 refclk, &clock,
5001 &reduced_clock);
5002 }
5003 /* Compat-code for transition, will disappear. */
f47709a9
DV		 5004 intel_crtc->config.dpll.n = clock.n;
5005 intel_crtc->config.dpll.m1 = clock.m1;
5006 intel_crtc->config.dpll.m2 = clock.m2;
5007 intel_crtc->config.dpll.p1 = clock.p1;
5008 intel_crtc->config.dpll.p2 = clock.p2;
5009 }
7026d4ac 5010
e9fd1c02 5011 if (IS_GEN2(dev)) {
8a654f3b 5012 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 5013 has_reduced_clock ? &reduced_clock : NULL,
5014 num_connectors);
e9fd1c02 5015 } else if (IS_VALLEYVIEW(dev)) {
f2335330 5016 vlv_update_pll(intel_crtc);
e9fd1c02 5017 } else {
f47709a9 5018 i9xx_update_pll(intel_crtc,
eb1cbe48 5019 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 5020 num_connectors);
e9fd1c02 5021 }
79e53945 5022
f2335330 5023skip_dpll:
79e53945
JB		 5024 /* Set up the display plane register */
5025 dspcntr = DISPPLANE_GAMMA_ENABLE;
5026
da6ecc5d
JB		 5027 if (!IS_VALLEYVIEW(dev)) {
5028 if (pipe == 0)
5029 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5030 else
5031 dspcntr |= DISPPLANE_SEL_PIPE_B;
5032 }
79e53945 5033
8a654f3b 5034 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 5035
5036 /* pipesrc and dspsize control the size that is scaled from,
5037 * which should always be the user's requested size.
79e53945 5038 */
929c77fb 5039 I915_WRITE(DSPSIZE(plane),
37327abd
VS		 5040 ((intel_crtc->config.pipe_src_h - 1) << 16) |
5041 (intel_crtc->config.pipe_src_w - 1));
929c77fb 5042 I915_WRITE(DSPPOS(plane), 0);
2c07245f 5043
84b046f3
DV		 5044 i9xx_set_pipeconf(intel_crtc);
5045
f564048e
EA		 5046 I915_WRITE(DSPCNTR(plane), dspcntr);
5047 POSTING_READ(DSPCNTR(plane));
5048
94352cf9 5049 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e 5050
f564048e
EA		 5051 return ret;
5052}
5053
2fa2fe9a
DV		 5054static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5055 struct intel_crtc_config *pipe_config)
5056{
5057 struct drm_device *dev = crtc->base.dev;
5058 struct drm_i915_private *dev_priv = dev->dev_private;
5059 uint32_t tmp;
5060
5061 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 5062 if (!(tmp & PFIT_ENABLE))
5063 return;
2fa2fe9a 5064
06922821 5065 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 5066 if (INTEL_INFO(dev)->gen < 4) {
5067 if (crtc->pipe != PIPE_B)
5068 return;
2fa2fe9a
DV		 5069 } else {
5070 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5071 return;
5072 }
5073
06922821 5074 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 5075 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5076 if (INTEL_INFO(dev)->gen < 5)
5077 pipe_config->gmch_pfit.lvds_border_bits =
5078 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5079}
5080
acbec814
JB		 5081static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5082 struct intel_crtc_config *pipe_config)
5083{
5084 struct drm_device *dev = crtc->base.dev;
5085 struct drm_i915_private *dev_priv = dev->dev_private;
5086 int pipe = pipe_config->cpu_transcoder;
5087 intel_clock_t clock;
5088 u32 mdiv;
662c6ecb 5089 int refclk = 100000;
acbec814
JB		 5090
5091 mutex_lock(&dev_priv->dpio_lock);
5092 mdiv = vlv_dpio_read(dev_priv, pipe, DPIO_DIV(pipe));
5093 mutex_unlock(&dev_priv->dpio_lock);
5094
5095 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5096 clock.m2 = mdiv & DPIO_M2DIV_MASK;
5097 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5098 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5099 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5100
662c6ecb
CW		 5101 clock.vco = refclk * clock.m1 * clock.m2 / clock.n;
5102 clock.dot = 2 * clock.vco / (clock.p1 * clock.p2);
acbec814
JB		 5103
5104 pipe_config->port_clock = clock.dot / 10;
5105}
5106
0e8ffe1b
DV		 5107static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5108 struct intel_crtc_config *pipe_config)
5109{
5110 struct drm_device *dev = crtc->base.dev;
5111 struct drm_i915_private *dev_priv = dev->dev_private;
5112 uint32_t tmp;
5113
e143a21c 5114 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 5115 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5116
0e8ffe1b
DV		 5117 tmp = I915_READ(PIPECONF(crtc->pipe));
5118 if (!(tmp & PIPECONF_ENABLE))
5119 return false;
5120
42571aef
VS		 5121 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5122 switch (tmp & PIPECONF_BPC_MASK) {
5123 case PIPECONF_6BPC:
5124 pipe_config->pipe_bpp = 18;
5125 break;
5126 case PIPECONF_8BPC:
5127 pipe_config->pipe_bpp = 24;
5128 break;
5129 case PIPECONF_10BPC:
5130 pipe_config->pipe_bpp = 30;
5131 break;
5132 default:
5133 break;
5134 }
5135 }
5136
282740f7
VS		 5137 if (INTEL_INFO(dev)->gen < 4)
5138 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5139
1bd1bd80
DV		 5140 intel_get_pipe_timings(crtc, pipe_config);
5141
2fa2fe9a
DV		 5142 i9xx_get_pfit_config(crtc, pipe_config);
5143
6c49f241
DV		 5144 if (INTEL_INFO(dev)->gen >= 4) {
5145 tmp = I915_READ(DPLL_MD(crtc->pipe));
5146 pipe_config->pixel_multiplier =
5147 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5148 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 5149 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 5150 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5151 tmp = I915_READ(DPLL(crtc->pipe));
5152 pipe_config->pixel_multiplier =
5153 ((tmp & SDVO_MULTIPLIER_MASK)
5154 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5155 } else {
5156 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5157 * port and will be fixed up in the encoder->get_config
5158 * function. */
5159 pipe_config->pixel_multiplier = 1;
5160 }
8bcc2795
DV		 5161 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5162 if (!IS_VALLEYVIEW(dev)) {
5163 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5164 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 5165 } else {
5166 /* Mask out read-only status bits. */
5167 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5168 DPLL_PORTC_READY_MASK |
5169 DPLL_PORTB_READY_MASK);
8bcc2795 5170 }
6c49f241 5171
acbec814
JB		 5172 if (IS_VALLEYVIEW(dev))
5173 vlv_crtc_clock_get(crtc, pipe_config);
5174 else
5175 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 5176
0e8ffe1b
DV		 5177 return true;
5178}
5179
dde86e2d 5180static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5181{
5182 struct drm_i915_private *dev_priv = dev->dev_private;
5183 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5184 struct intel_encoder *encoder;
74cfd7ac 5185 u32 val, final;
13d83a67 5186 bool has_lvds = false;
199e5d79 5187 bool has_cpu_edp = false;
199e5d79 5188 bool has_panel = false;
99eb6a01
KP		 5189 bool has_ck505 = false;
5190 bool can_ssc = false;
13d83a67
JB		 5191
5192 /* We need to take the global config into account */
199e5d79
KP		 5193 list_for_each_entry(encoder, &mode_config->encoder_list,
5194 base.head) {
5195 switch (encoder->type) {
5196 case INTEL_OUTPUT_LVDS:
5197 has_panel = true;
5198 has_lvds = true;
5199 break;
5200 case INTEL_OUTPUT_EDP:
5201 has_panel = true;
2de6905f 5202 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5203 has_cpu_edp = true;
5204 break;
13d83a67
JB		 5205 }
5206 }
5207
99eb6a01 5208 if (HAS_PCH_IBX(dev)) {
41aa3448 5209 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5210 can_ssc = has_ck505;
5211 } else {
5212 has_ck505 = false;
5213 can_ssc = true;
5214 }
5215
2de6905f
ID		 5216 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5217 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5218
5219 /* Ironlake: try to setup display ref clock before DPLL
5220 * enabling. This is only under driver's control after
5221 * PCH B stepping, previous chipset stepping should be
5222 * ignoring this setting.
5223 */
74cfd7ac
CW		 5224 val = I915_READ(PCH_DREF_CONTROL);
5225
5226 /* As we must carefully and slowly disable/enable each source in turn,
5227 * compute the final state we want first and check if we need to
5228 * make any changes at all.
5229 */
5230 final = val;
5231 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5232 if (has_ck505)
5233 final |= DREF_NONSPREAD_CK505_ENABLE;
5234 else
5235 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5236
5237 final &= ~DREF_SSC_SOURCE_MASK;
5238 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5239 final &= ~DREF_SSC1_ENABLE;
5240
5241 if (has_panel) {
5242 final |= DREF_SSC_SOURCE_ENABLE;
5243
5244 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5245 final |= DREF_SSC1_ENABLE;
5246
5247 if (has_cpu_edp) {
5248 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5249 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5250 else
5251 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5252 } else
5253 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5254 } else {
5255 final |= DREF_SSC_SOURCE_DISABLE;
5256 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5257 }
5258
5259 if (final == val)
5260 return;
5261
13d83a67 5262 /* Always enable nonspread source */
74cfd7ac 5263 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5264
99eb6a01 5265 if (has_ck505)
74cfd7ac 5266 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5267 else
74cfd7ac 5268 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5269
199e5d79 5270 if (has_panel) {
74cfd7ac
CW		 5271 val &= ~DREF_SSC_SOURCE_MASK;
5272 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5273
199e5d79 5274 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5275 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5276 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5277 val |= DREF_SSC1_ENABLE;
e77166b5 5278 } else
74cfd7ac 5279 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5280
5281 /* Get SSC going before enabling the outputs */
74cfd7ac 5282 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5283 POSTING_READ(PCH_DREF_CONTROL);
5284 udelay(200);
5285
74cfd7ac 5286 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5287
5288 /* Enable CPU source on CPU attached eDP */
199e5d79 5289 if (has_cpu_edp) {
99eb6a01 5290 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5291 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5292 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5293 }
13d83a67 5294 else
74cfd7ac 5295 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5296 } else
74cfd7ac 5297 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5298
74cfd7ac 5299 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5300 POSTING_READ(PCH_DREF_CONTROL);
5301 udelay(200);
5302 } else {
5303 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5304
74cfd7ac 5305 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5306
5307 /* Turn off CPU output */
74cfd7ac 5308 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5309
74cfd7ac 5310 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5311 POSTING_READ(PCH_DREF_CONTROL);
5312 udelay(200);
5313
5314 /* Turn off the SSC source */
74cfd7ac
CW		 5315 val &= ~DREF_SSC_SOURCE_MASK;
5316 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5317
5318 /* Turn off SSC1 */
74cfd7ac 5319 val &= ~DREF_SSC1_ENABLE;
199e5d79 5320
74cfd7ac 5321 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5322 POSTING_READ(PCH_DREF_CONTROL);
5323 udelay(200);
5324 }
74cfd7ac
CW		 5325
5326 BUG_ON(val != final);
13d83a67
JB		 5327}
5328
f31f2d55 5329static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 5330{
f31f2d55 5331 uint32_t tmp;
dde86e2d 5332
0ff066a9
PZ		 5333 tmp = I915_READ(SOUTH_CHICKEN2);
5334 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5335 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5336
0ff066a9
PZ		 5337 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5338 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5339 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 5340
0ff066a9
PZ		 5341 tmp = I915_READ(SOUTH_CHICKEN2);
5342 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5343 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5344
0ff066a9
PZ		 5345 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5346 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5347 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 5348}
5349
5350/* WaMPhyProgramming:hsw */
5351static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5352{
5353 uint32_t tmp;
dde86e2d
PZ		 5354
5355 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5356 tmp &= ~(0xFF << 24);
5357 tmp |= (0x12 << 24);
5358 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5359
dde86e2d
PZ		 5360 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5361 tmp |= (1 << 11);
5362 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5363
5364 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5365 tmp |= (1 << 11);
5366 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5367
dde86e2d
PZ		 5368 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5369 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5370 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5371
5372 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5373 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5374 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5375
0ff066a9
PZ		 5376 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5377 tmp &= ~(7 << 13);
5378 tmp |= (5 << 13);
5379 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 5380
0ff066a9
PZ		 5381 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5382 tmp &= ~(7 << 13);
5383 tmp |= (5 << 13);
5384 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 5385
5386 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5387 tmp &= ~0xFF;
5388 tmp |= 0x1C;
5389 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5390
5391 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5392 tmp &= ~0xFF;
5393 tmp |= 0x1C;
5394 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5395
5396 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5397 tmp &= ~(0xFF << 16);
5398 tmp |= (0x1C << 16);
5399 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5400
5401 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5402 tmp &= ~(0xFF << 16);
5403 tmp |= (0x1C << 16);
5404 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5405
0ff066a9
PZ		 5406 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5407 tmp |= (1 << 27);
5408 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 5409
0ff066a9
PZ		 5410 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5411 tmp |= (1 << 27);
5412 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 5413
0ff066a9
PZ		 5414 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5415 tmp &= ~(0xF << 28);
5416 tmp |= (4 << 28);
5417 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 5418
0ff066a9
PZ		 5419 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5420 tmp &= ~(0xF << 28);
5421 tmp |= (4 << 28);
5422 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 5423}
5424
2fa86a1f
PZ		 5425/* Implements 3 different sequences from BSpec chapter "Display iCLK
5426 * Programming" based on the parameters passed:
5427 * - Sequence to enable CLKOUT_DP
5428 * - Sequence to enable CLKOUT_DP without spread
5429 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5430 */
5431static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5432 bool with_fdi)
f31f2d55
PZ		 5433{
5434 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 5435 uint32_t reg, tmp;
5436
5437 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5438 with_spread = true;
5439 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5440 with_fdi, "LP PCH doesn't have FDI\n"))
5441 with_fdi = false;
f31f2d55
PZ		 5442
5443 mutex_lock(&dev_priv->dpio_lock);
5444
5445 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5446 tmp &= ~SBI_SSCCTL_DISABLE;
5447 tmp |= SBI_SSCCTL_PATHALT;
5448 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5449
5450 udelay(24);
5451
2fa86a1f
PZ		 5452 if (with_spread) {
5453 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5454 tmp &= ~SBI_SSCCTL_PATHALT;
5455 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 5456
2fa86a1f
PZ		 5457 if (with_fdi) {
5458 lpt_reset_fdi_mphy(dev_priv);
5459 lpt_program_fdi_mphy(dev_priv);
5460 }
5461 }
dde86e2d 5462
2fa86a1f
PZ		 5463 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5464 SBI_GEN0 : SBI_DBUFF0;
5465 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5466 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5467 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 5468
5469 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5470}
5471
47701c3b
PZ		 5472/* Sequence to disable CLKOUT_DP */
5473static void lpt_disable_clkout_dp(struct drm_device *dev)
5474{
5475 struct drm_i915_private *dev_priv = dev->dev_private;
5476 uint32_t reg, tmp;
5477
5478 mutex_lock(&dev_priv->dpio_lock);
5479
5480 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5481 SBI_GEN0 : SBI_DBUFF0;
5482 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5483 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5484 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5485
5486 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5487 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5488 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5489 tmp |= SBI_SSCCTL_PATHALT;
5490 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5491 udelay(32);
5492 }
5493 tmp |= SBI_SSCCTL_DISABLE;
5494 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5495 }
5496
5497 mutex_unlock(&dev_priv->dpio_lock);
5498}
5499
bf8fa3d3
PZ		 5500static void lpt_init_pch_refclk(struct drm_device *dev)
5501{
5502 struct drm_mode_config *mode_config = &dev->mode_config;
5503 struct intel_encoder *encoder;
5504 bool has_vga = false;
5505
5506 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5507 switch (encoder->type) {
5508 case INTEL_OUTPUT_ANALOG:
5509 has_vga = true;
5510 break;
5511 }
5512 }
5513
47701c3b
PZ		 5514 if (has_vga)
5515 lpt_enable_clkout_dp(dev, true, true);
5516 else
5517 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 5518}
5519
dde86e2d
PZ		 5520/*
5521 * Initialize reference clocks when the driver loads
5522 */
5523void intel_init_pch_refclk(struct drm_device *dev)
5524{
5525 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5526 ironlake_init_pch_refclk(dev);
5527 else if (HAS_PCH_LPT(dev))
5528 lpt_init_pch_refclk(dev);
5529}
5530
d9d444cb
JB		 5531static int ironlake_get_refclk(struct drm_crtc *crtc)
5532{
5533 struct drm_device *dev = crtc->dev;
5534 struct drm_i915_private *dev_priv = dev->dev_private;
5535 struct intel_encoder *encoder;
d9d444cb
JB		 5536 int num_connectors = 0;
5537 bool is_lvds = false;
5538
6c2b7c12 5539 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5540 switch (encoder->type) {
5541 case INTEL_OUTPUT_LVDS:
5542 is_lvds = true;
5543 break;
d9d444cb
JB		 5544 }
5545 num_connectors++;
5546 }
5547
5548 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5549 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5550 dev_priv->vbt.lvds_ssc_freq);
5551 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5552 }
5553
5554 return 120000;
5555}
5556
6ff93609 5557static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5558{
c8203565 5559 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5560 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5561 int pipe = intel_crtc->pipe;
c8203565
PZ		 5562 uint32_t val;
5563
78114071 5564 val = 0;
c8203565 5565
965e0c48 5566 switch (intel_crtc->config.pipe_bpp) {
c8203565 5567 case 18:
dfd07d72 5568 val |= PIPECONF_6BPC;
c8203565
PZ		 5569 break;
5570 case 24:
dfd07d72 5571 val |= PIPECONF_8BPC;
c8203565
PZ		 5572 break;
5573 case 30:
dfd07d72 5574 val |= PIPECONF_10BPC;
c8203565
PZ		 5575 break;
5576 case 36:
dfd07d72 5577 val |= PIPECONF_12BPC;
c8203565
PZ		 5578 break;
5579 default:
cc769b62
PZ		 5580 /* Case prevented by intel_choose_pipe_bpp_dither. */
5581 BUG();
c8203565
PZ		 5582 }
5583
d8b32247 5584 if (intel_crtc->config.dither)
c8203565
PZ		 5585 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5586
6ff93609 5587 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5588 val |= PIPECONF_INTERLACED_ILK;
5589 else
5590 val |= PIPECONF_PROGRESSIVE;
5591
50f3b016 5592 if (intel_crtc->config.limited_color_range)
3685a8f3 5593 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 5594
c8203565
PZ		 5595 I915_WRITE(PIPECONF(pipe), val);
5596 POSTING_READ(PIPECONF(pipe));
5597}
5598
86d3efce
VS		 5599/*
5600 * Set up the pipe CSC unit.
5601 *
5602 * Currently only full range RGB to limited range RGB conversion
5603 * is supported, but eventually this should handle various
5604 * RGB<->YCbCr scenarios as well.
5605 */
50f3b016 5606static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5607{
5608 struct drm_device *dev = crtc->dev;
5609 struct drm_i915_private *dev_priv = dev->dev_private;
5610 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5611 int pipe = intel_crtc->pipe;
5612 uint16_t coeff = 0x7800; /* 1.0 */
5613
5614 /*
5615 * TODO: Check what kind of values actually come out of the pipe
5616 * with these coeff/postoff values and adjust to get the best
5617 * accuracy. Perhaps we even need to take the bpc value into
5618 * consideration.
5619 */
5620
50f3b016 5621 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5622 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5623
5624 /*
5625 * GY/GU and RY/RU should be the other way around according
5626 * to BSpec, but reality doesn't agree. Just set them up in
5627 * a way that results in the correct picture.
5628 */
5629 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5630 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5631
5632 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5633 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5634
5635 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5636 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5637
5638 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5639 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5640 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5641
5642 if (INTEL_INFO(dev)->gen > 6) {
5643 uint16_t postoff = 0;
5644
50f3b016 5645 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5646 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5647
5648 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5649 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5650 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5651
5652 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5653 } else {
5654 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5655
50f3b016 5656 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5657 mode |= CSC_BLACK_SCREEN_OFFSET;
5658
5659 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5660 }
5661}
5662
6ff93609 5663static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5664{
5665 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5666 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5667 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5668 uint32_t val;
5669
3eff4faa 5670 val = 0;
ee2b0b38 5671
d8b32247 5672 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5673 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5674
6ff93609 5675 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5676 val |= PIPECONF_INTERLACED_ILK;
5677 else
5678 val |= PIPECONF_PROGRESSIVE;
5679
702e7a56
PZ		 5680 I915_WRITE(PIPECONF(cpu_transcoder), val);
5681 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 5682
5683 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5684 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
ee2b0b38
PZ		 5685}
5686
6591c6e4 5687static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5688 intel_clock_t *clock,
5689 bool *has_reduced_clock,
5690 intel_clock_t *reduced_clock)
5691{
5692 struct drm_device *dev = crtc->dev;
5693 struct drm_i915_private *dev_priv = dev->dev_private;
5694 struct intel_encoder *intel_encoder;
5695 int refclk;
d4906093 5696 const intel_limit_t *limit;
a16af721 5697 bool ret, is_lvds = false;
79e53945 5698
6591c6e4
PZ		 5699 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5700 switch (intel_encoder->type) {
79e53945
JB		 5701 case INTEL_OUTPUT_LVDS:
5702 is_lvds = true;
5703 break;
79e53945
JB		 5704 }
5705 }
5706
d9d444cb 5707 refclk = ironlake_get_refclk(crtc);
79e53945 5708
d4906093
ML		 5709 /*
5710 * Returns a set of divisors for the desired target clock with the given
5711 * refclk, or FALSE. The returned values represent the clock equation:
5712 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5713 */
1b894b59 5714 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5715 ret = dev_priv->display.find_dpll(limit, crtc,
5716 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5717 refclk, NULL, clock);
6591c6e4
PZ		 5718 if (!ret)
5719 return false;
cda4b7d3 5720
ddc9003c 5721 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5722 /*
5723 * Ensure we match the reduced clock's P to the target clock.
5724 * If the clocks don't match, we can't switch the display clock
5725 * by using the FP0/FP1. In such case we will disable the LVDS
5726 * downclock feature.
5727 */
ee9300bb
DV		 5728 *has_reduced_clock =
5729 dev_priv->display.find_dpll(limit, crtc,
5730 dev_priv->lvds_downclock,
5731 refclk, clock,
5732 reduced_clock);
652c393a 5733 }
61e9653f 5734
6591c6e4
PZ		 5735 return true;
5736}
5737
01a415fd
DV		 5738static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5739{
5740 struct drm_i915_private *dev_priv = dev->dev_private;
5741 uint32_t temp;
5742
5743 temp = I915_READ(SOUTH_CHICKEN1);
5744 if (temp & FDI_BC_BIFURCATION_SELECT)
5745 return;
5746
5747 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5748 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5749
5750 temp |= FDI_BC_BIFURCATION_SELECT;
5751 DRM_DEBUG_KMS("enabling fdi C rx\n");
5752 I915_WRITE(SOUTH_CHICKEN1, temp);
5753 POSTING_READ(SOUTH_CHICKEN1);
5754}
5755
ebfd86fd 5756static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
01a415fd
DV		 5757{
5758 struct drm_device *dev = intel_crtc->base.dev;
5759 struct drm_i915_private *dev_priv = dev->dev_private;
01a415fd
DV		 5760
5761 switch (intel_crtc->pipe) {
5762 case PIPE_A:
ebfd86fd 5763 break;
01a415fd 5764 case PIPE_B:
ebfd86fd 5765 if (intel_crtc->config.fdi_lanes > 2)
01a415fd
DV		 5766 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5767 else
5768 cpt_enable_fdi_bc_bifurcation(dev);
5769
ebfd86fd 5770 break;
01a415fd 5771 case PIPE_C:
01a415fd
DV		 5772 cpt_enable_fdi_bc_bifurcation(dev);
5773
ebfd86fd 5774 break;
01a415fd
DV		 5775 default:
5776 BUG();
5777 }
5778}
5779
d4b1931c
PZ		 5780int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5781{
5782 /*
5783 * Account for spread spectrum to avoid
5784 * oversubscribing the link. Max center spread
5785 * is 2.5%; use 5% for safety's sake.
5786 */
5787 u32 bps = target_clock * bpp * 21 / 20;
5788 return bps / (link_bw * 8) + 1;
5789}
5790
7429e9d4 5791static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 5792{
7429e9d4 5793 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 5794}
5795
de13a2e3 5796static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5797 u32 *fp,
9a7c7890 5798 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5799{
de13a2e3 5800 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5801 struct drm_device *dev = crtc->dev;
5802 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5803 struct intel_encoder *intel_encoder;
5804 uint32_t dpll;
6cc5f341 5805 int factor, num_connectors = 0;
09ede541 5806 bool is_lvds = false, is_sdvo = false;
79e53945 5807
de13a2e3
PZ		 5808 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5809 switch (intel_encoder->type) {
79e53945
JB		 5810 case INTEL_OUTPUT_LVDS:
5811 is_lvds = true;
5812 break;
5813 case INTEL_OUTPUT_SDVO:
7d57382e 5814 case INTEL_OUTPUT_HDMI:
79e53945 5815 is_sdvo = true;
79e53945 5816 break;
79e53945 5817 }
43565a06 5818
c751ce4f 5819 num_connectors++;
79e53945 5820 }
79e53945 5821
c1858123 5822 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5823 factor = 21;
5824 if (is_lvds) {
5825 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5826 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5827 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5828 factor = 25;
09ede541 5829 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5830 factor = 20;
c1858123 5831
7429e9d4 5832 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5833 *fp |= FP_CB_TUNE;
2c07245f 5834
9a7c7890
DV		 5835 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5836 *fp2 |= FP_CB_TUNE;
5837
5eddb70b 5838 dpll = 0;
2c07245f 5839
a07d6787
EA		 5840 if (is_lvds)
5841 dpll |= DPLLB_MODE_LVDS;
5842 else
5843 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5844
ef1b460d
DV		 5845 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5846 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5847
5848 if (is_sdvo)
4a33e48d 5849 dpll |= DPLL_SDVO_HIGH_SPEED;
9566e9af 5850 if (intel_crtc->config.has_dp_encoder)
4a33e48d 5851 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 5852
a07d6787 5853 /* compute bitmask from p1 value */
7429e9d4 5854 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5855 /* also FPA1 */
7429e9d4 5856 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5857
7429e9d4 5858 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5859 case 5:
5860 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5861 break;
5862 case 7:
5863 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5864 break;
5865 case 10:
5866 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5867 break;
5868 case 14:
5869 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5870 break;
79e53945
JB		 5871 }
5872
b4c09f3b 5873 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5874 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5875 else
5876 dpll |= PLL_REF_INPUT_DREFCLK;
5877
959e16d6 5878 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 5879}
5880
5881static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5882 int x, int y,
5883 struct drm_framebuffer *fb)
5884{
5885 struct drm_device *dev = crtc->dev;
5886 struct drm_i915_private *dev_priv = dev->dev_private;
5887 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5888 int pipe = intel_crtc->pipe;
5889 int plane = intel_crtc->plane;
5890 int num_connectors = 0;
5891 intel_clock_t clock, reduced_clock;
cbbab5bd 5892 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5893 bool ok, has_reduced_clock = false;
8b47047b 5894 bool is_lvds = false;
de13a2e3 5895 struct intel_encoder *encoder;
e2b78267 5896 struct intel_shared_dpll *pll;
de13a2e3 5897 int ret;
de13a2e3
PZ		 5898
5899 for_each_encoder_on_crtc(dev, crtc, encoder) {
5900 switch (encoder->type) {
5901 case INTEL_OUTPUT_LVDS:
5902 is_lvds = true;
5903 break;
de13a2e3
PZ		 5904 }
5905
5906 num_connectors++;
a07d6787 5907 }
79e53945 5908
5dc5298b
PZ		 5909 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5910 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5911
ff9a6750 5912 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 5913 &has_reduced_clock, &reduced_clock);
ee9300bb 5914 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 5915 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5916 return -EINVAL;
79e53945 5917 }
f47709a9
DV		 5918 /* Compat-code for transition, will disappear. */
5919 if (!intel_crtc->config.clock_set) {
5920 intel_crtc->config.dpll.n = clock.n;
5921 intel_crtc->config.dpll.m1 = clock.m1;
5922 intel_crtc->config.dpll.m2 = clock.m2;
5923 intel_crtc->config.dpll.p1 = clock.p1;
5924 intel_crtc->config.dpll.p2 = clock.p2;
5925 }
79e53945 5926
5dc5298b 5927 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5928 if (intel_crtc->config.has_pch_encoder) {
7429e9d4 5929 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5930 if (has_reduced_clock)
7429e9d4 5931 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5932
7429e9d4 5933 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5934 &fp, &reduced_clock,
5935 has_reduced_clock ? &fp2 : NULL);
5936
959e16d6 5937 intel_crtc->config.dpll_hw_state.dpll = dpll;
66e985c0
DV		 5938 intel_crtc->config.dpll_hw_state.fp0 = fp;
5939 if (has_reduced_clock)
5940 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5941 else
5942 intel_crtc->config.dpll_hw_state.fp1 = fp;
5943
b89a1d39 5944 pll = intel_get_shared_dpll(intel_crtc);
ee7b9f93 5945 if (pll == NULL) {
84f44ce7
VS		 5946 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5947 pipe_name(pipe));
4b645f14
JB		 5948 return -EINVAL;
5949 }
ee7b9f93 5950 } else
e72f9fbf 5951 intel_put_shared_dpll(intel_crtc);
79e53945 5952
03afc4a2
DV		 5953 if (intel_crtc->config.has_dp_encoder)
5954 intel_dp_set_m_n(intel_crtc);
79e53945 5955
bcd644e0
DV		 5956 if (is_lvds && has_reduced_clock && i915_powersave)
5957 intel_crtc->lowfreq_avail = true;
5958 else
5959 intel_crtc->lowfreq_avail = false;
e2b78267
DV		 5960
5961 if (intel_crtc->config.has_pch_encoder) {
5962 pll = intel_crtc_to_shared_dpll(intel_crtc);
5963
652c393a
JB		 5964 }
5965
8a654f3b 5966 intel_set_pipe_timings(intel_crtc);
5eddb70b 5967
ca3a0ff8 5968 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5969 intel_cpu_transcoder_set_m_n(intel_crtc,
5970 &intel_crtc->config.fdi_m_n);
5971 }
2c07245f 5972
ebfd86fd
DV		 5973 if (IS_IVYBRIDGE(dev))
5974 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
79e53945 5975
6ff93609 5976 ironlake_set_pipeconf(crtc);
79e53945 5977
a1f9e77e
PZ		 5978 /* Set up the display plane register */
5979 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5980 POSTING_READ(DSPCNTR(plane));
79e53945 5981
94352cf9 5982 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd 5983
1857e1da 5984 return ret;
79e53945
JB		 5985}
5986
eb14cb74
VS		 5987static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
5988 struct intel_link_m_n *m_n)
5989{
5990 struct drm_device *dev = crtc->base.dev;
5991 struct drm_i915_private *dev_priv = dev->dev_private;
5992 enum pipe pipe = crtc->pipe;
5993
5994 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
5995 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
5996 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
5997 & ~TU_SIZE_MASK;
5998 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
5999 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6000 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6001}
6002
6003static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6004 enum transcoder transcoder,
6005 struct intel_link_m_n *m_n)
72419203
DV		 6006{
6007 struct drm_device *dev = crtc->base.dev;
6008 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 6009 enum pipe pipe = crtc->pipe;
72419203 6010
eb14cb74
VS		 6011 if (INTEL_INFO(dev)->gen >= 5) {
6012 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6013 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6014 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6015 & ~TU_SIZE_MASK;
6016 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6017 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6018 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6019 } else {
6020 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6021 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6022 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6023 & ~TU_SIZE_MASK;
6024 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6025 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6026 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6027 }
6028}
6029
6030void intel_dp_get_m_n(struct intel_crtc *crtc,
6031 struct intel_crtc_config *pipe_config)
6032{
6033 if (crtc->config.has_pch_encoder)
6034 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6035 else
6036 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6037 &pipe_config->dp_m_n);
6038}
72419203 6039
eb14cb74
VS		 6040static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6041 struct intel_crtc_config *pipe_config)
6042{
6043 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6044 &pipe_config->fdi_m_n);
72419203
DV		 6045}
6046
2fa2fe9a
DV		 6047static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6048 struct intel_crtc_config *pipe_config)
6049{
6050 struct drm_device *dev = crtc->base.dev;
6051 struct drm_i915_private *dev_priv = dev->dev_private;
6052 uint32_t tmp;
6053
6054 tmp = I915_READ(PF_CTL(crtc->pipe));
6055
6056 if (tmp & PF_ENABLE) {
fd4daa9c 6057 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 6058 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6059 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 6060
6061 /* We currently do not free assignements of panel fitters on
6062 * ivb/hsw (since we don't use the higher upscaling modes which
6063 * differentiates them) so just WARN about this case for now. */
6064 if (IS_GEN7(dev)) {
6065 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6066 PF_PIPE_SEL_IVB(crtc->pipe));
6067 }
2fa2fe9a 6068 }
79e53945
JB		 6069}
6070
0e8ffe1b
DV		 6071static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6072 struct intel_crtc_config *pipe_config)
6073{
6074 struct drm_device *dev = crtc->base.dev;
6075 struct drm_i915_private *dev_priv = dev->dev_private;
6076 uint32_t tmp;
6077
e143a21c 6078 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 6079 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 6080
0e8ffe1b
DV		 6081 tmp = I915_READ(PIPECONF(crtc->pipe));
6082 if (!(tmp & PIPECONF_ENABLE))
6083 return false;
6084
42571aef
VS		 6085 switch (tmp & PIPECONF_BPC_MASK) {
6086 case PIPECONF_6BPC:
6087 pipe_config->pipe_bpp = 18;
6088 break;
6089 case PIPECONF_8BPC:
6090 pipe_config->pipe_bpp = 24;
6091 break;
6092 case PIPECONF_10BPC:
6093 pipe_config->pipe_bpp = 30;
6094 break;
6095 case PIPECONF_12BPC:
6096 pipe_config->pipe_bpp = 36;
6097 break;
6098 default:
6099 break;
6100 }
6101
ab9412ba 6102 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 6103 struct intel_shared_dpll *pll;
6104
88adfff1
DV		 6105 pipe_config->has_pch_encoder = true;
6106
627eb5a3
DV		 6107 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6108 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6109 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6110
6111 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 6112
c0d43d62 6113 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 6114 pipe_config->shared_dpll =
6115 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 6116 } else {
6117 tmp = I915_READ(PCH_DPLL_SEL);
6118 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6119 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6120 else
6121 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6122 }
66e985c0
DV		 6123
6124 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6125
6126 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6127 &pipe_config->dpll_hw_state));
c93f54cf
DV		 6128
6129 tmp = pipe_config->dpll_hw_state.dpll;
6130 pipe_config->pixel_multiplier =
6131 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6132 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 6133
6134 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 6135 } else {
6136 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 6137 }
6138
1bd1bd80
DV		 6139 intel_get_pipe_timings(crtc, pipe_config);
6140
2fa2fe9a
DV		 6141 ironlake_get_pfit_config(crtc, pipe_config);
6142
0e8ffe1b
DV		 6143 return true;
6144}
6145
be256dc7
PZ		 6146static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6147{
6148 struct drm_device *dev = dev_priv->dev;
6149 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6150 struct intel_crtc *crtc;
6151 unsigned long irqflags;
bd633a7c 6152 uint32_t val;
be256dc7
PZ		 6153
6154 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6155 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
6156 pipe_name(crtc->pipe));
6157
6158 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6159 WARN(plls->spll_refcount, "SPLL enabled\n");
6160 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6161 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6162 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6163 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6164 "CPU PWM1 enabled\n");
6165 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6166 "CPU PWM2 enabled\n");
6167 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6168 "PCH PWM1 enabled\n");
6169 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6170 "Utility pin enabled\n");
6171 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6172
6173 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6174 val = I915_READ(DEIMR);
6175 WARN((val & ~DE_PCH_EVENT_IVB) != val,
6176 "Unexpected DEIMR bits enabled: 0x%x\n", val);
6177 val = I915_READ(SDEIMR);
bd633a7c 6178 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
be256dc7
PZ		 6179 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6180 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6181}
6182
6183/*
6184 * This function implements pieces of two sequences from BSpec:
6185 * - Sequence for display software to disable LCPLL
6186 * - Sequence for display software to allow package C8+
6187 * The steps implemented here are just the steps that actually touch the LCPLL
6188 * register. Callers should take care of disabling all the display engine
6189 * functions, doing the mode unset, fixing interrupts, etc.
6190 */
6ff58d53
PZ		 6191static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6192 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 6193{
6194 uint32_t val;
6195
6196 assert_can_disable_lcpll(dev_priv);
6197
6198 val = I915_READ(LCPLL_CTL);
6199
6200 if (switch_to_fclk) {
6201 val |= LCPLL_CD_SOURCE_FCLK;
6202 I915_WRITE(LCPLL_CTL, val);
6203
6204 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6205 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6206 DRM_ERROR("Switching to FCLK failed\n");
6207
6208 val = I915_READ(LCPLL_CTL);
6209 }
6210
6211 val |= LCPLL_PLL_DISABLE;
6212 I915_WRITE(LCPLL_CTL, val);
6213 POSTING_READ(LCPLL_CTL);
6214
6215 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6216 DRM_ERROR("LCPLL still locked\n");
6217
6218 val = I915_READ(D_COMP);
6219 val |= D_COMP_COMP_DISABLE;
515b2392
PZ		 6220 mutex_lock(&dev_priv->rps.hw_lock);
6221 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6222 DRM_ERROR("Failed to disable D_COMP\n");
6223 mutex_unlock(&dev_priv->rps.hw_lock);
be256dc7
PZ		 6224 POSTING_READ(D_COMP);
6225 ndelay(100);
6226
6227 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6228 DRM_ERROR("D_COMP RCOMP still in progress\n");
6229
6230 if (allow_power_down) {
6231 val = I915_READ(LCPLL_CTL);
6232 val |= LCPLL_POWER_DOWN_ALLOW;
6233 I915_WRITE(LCPLL_CTL, val);
6234 POSTING_READ(LCPLL_CTL);
6235 }
6236}
6237
6238/*
6239 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6240 * source.
6241 */
6ff58d53 6242static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 6243{
6244 uint32_t val;
6245
6246 val = I915_READ(LCPLL_CTL);
6247
6248 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6249 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6250 return;
6251
215733fa
PZ		 6252 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6253 * we'll hang the machine! */
6254 dev_priv->uncore.funcs.force_wake_get(dev_priv);
6255
be256dc7
PZ		 6256 if (val & LCPLL_POWER_DOWN_ALLOW) {
6257 val &= ~LCPLL_POWER_DOWN_ALLOW;
6258 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 6259 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 6260 }
6261
6262 val = I915_READ(D_COMP);
6263 val |= D_COMP_COMP_FORCE;
6264 val &= ~D_COMP_COMP_DISABLE;
515b2392
PZ		 6265 mutex_lock(&dev_priv->rps.hw_lock);
6266 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6267 DRM_ERROR("Failed to enable D_COMP\n");
6268 mutex_unlock(&dev_priv->rps.hw_lock);
35d8f2eb 6269 POSTING_READ(D_COMP);
be256dc7
PZ		 6270
6271 val = I915_READ(LCPLL_CTL);
6272 val &= ~LCPLL_PLL_DISABLE;
6273 I915_WRITE(LCPLL_CTL, val);
6274
6275 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6276 DRM_ERROR("LCPLL not locked yet\n");
6277
6278 if (val & LCPLL_CD_SOURCE_FCLK) {
6279 val = I915_READ(LCPLL_CTL);
6280 val &= ~LCPLL_CD_SOURCE_FCLK;
6281 I915_WRITE(LCPLL_CTL, val);
6282
6283 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6284 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6285 DRM_ERROR("Switching back to LCPLL failed\n");
6286 }
215733fa
PZ		 6287
6288 dev_priv->uncore.funcs.force_wake_put(dev_priv);
be256dc7
PZ		 6289}
6290
c67a470b
PZ		 6291void hsw_enable_pc8_work(struct work_struct *__work)
6292{
6293 struct drm_i915_private *dev_priv =
6294 container_of(to_delayed_work(__work), struct drm_i915_private,
6295 pc8.enable_work);
6296 struct drm_device *dev = dev_priv->dev;
6297 uint32_t val;
6298
6299 if (dev_priv->pc8.enabled)
6300 return;
6301
6302 DRM_DEBUG_KMS("Enabling package C8+\n");
6303
6304 dev_priv->pc8.enabled = true;
6305
6306 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6307 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6308 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6309 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6310 }
6311
6312 lpt_disable_clkout_dp(dev);
6313 hsw_pc8_disable_interrupts(dev);
6314 hsw_disable_lcpll(dev_priv, true, true);
6315}
6316
6317static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6318{
6319 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6320 WARN(dev_priv->pc8.disable_count < 1,
6321 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6322
6323 dev_priv->pc8.disable_count--;
6324 if (dev_priv->pc8.disable_count != 0)
6325 return;
6326
6327 schedule_delayed_work(&dev_priv->pc8.enable_work,
90058745 6328 msecs_to_jiffies(i915_pc8_timeout));
c67a470b
PZ		 6329}
6330
6331static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6332{
6333 struct drm_device *dev = dev_priv->dev;
6334 uint32_t val;
6335
6336 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6337 WARN(dev_priv->pc8.disable_count < 0,
6338 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6339
6340 dev_priv->pc8.disable_count++;
6341 if (dev_priv->pc8.disable_count != 1)
6342 return;
6343
6344 cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6345 if (!dev_priv->pc8.enabled)
6346 return;
6347
6348 DRM_DEBUG_KMS("Disabling package C8+\n");
6349
6350 hsw_restore_lcpll(dev_priv);
6351 hsw_pc8_restore_interrupts(dev);
6352 lpt_init_pch_refclk(dev);
6353
6354 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6355 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6356 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6357 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6358 }
6359
6360 intel_prepare_ddi(dev);
6361 i915_gem_init_swizzling(dev);
6362 mutex_lock(&dev_priv->rps.hw_lock);
6363 gen6_update_ring_freq(dev);
6364 mutex_unlock(&dev_priv->rps.hw_lock);
6365 dev_priv->pc8.enabled = false;
6366}
6367
6368void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6369{
6370 mutex_lock(&dev_priv->pc8.lock);
6371 __hsw_enable_package_c8(dev_priv);
6372 mutex_unlock(&dev_priv->pc8.lock);
6373}
6374
6375void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6376{
6377 mutex_lock(&dev_priv->pc8.lock);
6378 __hsw_disable_package_c8(dev_priv);
6379 mutex_unlock(&dev_priv->pc8.lock);
6380}
6381
6382static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6383{
6384 struct drm_device *dev = dev_priv->dev;
6385 struct intel_crtc *crtc;
6386 uint32_t val;
6387
6388 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6389 if (crtc->base.enabled)
6390 return false;
6391
6392 /* This case is still possible since we have the i915.disable_power_well
6393 * parameter and also the KVMr or something else might be requesting the
6394 * power well. */
6395 val = I915_READ(HSW_PWR_WELL_DRIVER);
6396 if (val != 0) {
6397 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6398 return false;
6399 }
6400
6401 return true;
6402}
6403
6404/* Since we're called from modeset_global_resources there's no way to
6405 * symmetrically increase and decrease the refcount, so we use
6406 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6407 * or not.
6408 */
6409static void hsw_update_package_c8(struct drm_device *dev)
6410{
6411 struct drm_i915_private *dev_priv = dev->dev_private;
6412 bool allow;
6413
6414 if (!i915_enable_pc8)
6415 return;
6416
6417 mutex_lock(&dev_priv->pc8.lock);
6418
6419 allow = hsw_can_enable_package_c8(dev_priv);
6420
6421 if (allow == dev_priv->pc8.requirements_met)
6422 goto done;
6423
6424 dev_priv->pc8.requirements_met = allow;
6425
6426 if (allow)
6427 __hsw_enable_package_c8(dev_priv);
6428 else
6429 __hsw_disable_package_c8(dev_priv);
6430
6431done:
6432 mutex_unlock(&dev_priv->pc8.lock);
6433}
6434
6435static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6436{
6437 if (!dev_priv->pc8.gpu_idle) {
6438 dev_priv->pc8.gpu_idle = true;
6439 hsw_enable_package_c8(dev_priv);
6440 }
6441}
6442
6443static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6444{
6445 if (dev_priv->pc8.gpu_idle) {
6446 dev_priv->pc8.gpu_idle = false;
6447 hsw_disable_package_c8(dev_priv);
6448 }
be256dc7
PZ		 6449}
6450
d6dd9eb1
DV		 6451static void haswell_modeset_global_resources(struct drm_device *dev)
6452{
d6dd9eb1
DV		 6453 bool enable = false;
6454 struct intel_crtc *crtc;
d6dd9eb1
DV		 6455
6456 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 6457 if (!crtc->base.enabled)
6458 continue;
d6dd9eb1 6459
fd4daa9c 6460 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.enabled ||
e7a639c4 6461 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 6462 enable = true;
6463 }
6464
d6dd9eb1 6465 intel_set_power_well(dev, enable);
c67a470b
PZ		 6466
6467 hsw_update_package_c8(dev);
d6dd9eb1
DV		 6468}
6469
09b4ddf9 6470static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 6471 int x, int y,
6472 struct drm_framebuffer *fb)
6473{
6474 struct drm_device *dev = crtc->dev;
6475 struct drm_i915_private *dev_priv = dev->dev_private;
6476 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 6477 int plane = intel_crtc->plane;
09b4ddf9 6478 int ret;
09b4ddf9 6479
ff9a6750 6480 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 6481 return -EINVAL;
6482
03afc4a2
DV		 6483 if (intel_crtc->config.has_dp_encoder)
6484 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 6485
6486 intel_crtc->lowfreq_avail = false;
09b4ddf9 6487
8a654f3b 6488 intel_set_pipe_timings(intel_crtc);
09b4ddf9 6489
ca3a0ff8 6490 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 6491 intel_cpu_transcoder_set_m_n(intel_crtc,
6492 &intel_crtc->config.fdi_m_n);
6493 }
09b4ddf9 6494
6ff93609 6495 haswell_set_pipeconf(crtc);
09b4ddf9 6496
50f3b016 6497 intel_set_pipe_csc(crtc);
86d3efce 6498
09b4ddf9 6499 /* Set up the display plane register */
86d3efce 6500 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 6501 POSTING_READ(DSPCNTR(plane));
6502
6503 ret = intel_pipe_set_base(crtc, x, y, fb);
6504
1f803ee5 6505 return ret;
79e53945
JB		 6506}
6507
0e8ffe1b
DV		 6508static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6509 struct intel_crtc_config *pipe_config)
6510{
6511 struct drm_device *dev = crtc->base.dev;
6512 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 6513 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 6514 uint32_t tmp;
6515
e143a21c 6516 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 6517 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6518
eccb140b
DV		 6519 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6520 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6521 enum pipe trans_edp_pipe;
6522 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6523 default:
6524 WARN(1, "unknown pipe linked to edp transcoder\n");
6525 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6526 case TRANS_DDI_EDP_INPUT_A_ON:
6527 trans_edp_pipe = PIPE_A;
6528 break;
6529 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6530 trans_edp_pipe = PIPE_B;
6531 break;
6532 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6533 trans_edp_pipe = PIPE_C;
6534 break;
6535 }
6536
6537 if (trans_edp_pipe == crtc->pipe)
6538 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6539 }
6540
b97186f0 6541 if (!intel_display_power_enabled(dev,
eccb140b 6542 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 6543 return false;
6544
eccb140b 6545 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 6546 if (!(tmp & PIPECONF_ENABLE))
6547 return false;
6548
88adfff1 6549 /*
f196e6be 6550 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 6551 * DDI E. So just check whether this pipe is wired to DDI E and whether
6552 * the PCH transcoder is on.
6553 */
eccb140b 6554 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 6555 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 6556 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 6557 pipe_config->has_pch_encoder = true;
6558
627eb5a3
DV		 6559 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6560 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6561 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6562
6563 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 6564 }
6565
1bd1bd80
DV		 6566 intel_get_pipe_timings(crtc, pipe_config);
6567
2fa2fe9a
DV		 6568 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6569 if (intel_display_power_enabled(dev, pfit_domain))
6570 ironlake_get_pfit_config(crtc, pipe_config);
88adfff1 6571
42db64ef
PZ		 6572 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6573 (I915_READ(IPS_CTL) & IPS_ENABLE);
6574
6c49f241
DV		 6575 pipe_config->pixel_multiplier = 1;
6576
0e8ffe1b
DV		 6577 return true;
6578}
6579
f564048e 6580static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6581 int x, int y,
94352cf9 6582 struct drm_framebuffer *fb)
f564048e
EA		 6583{
6584 struct drm_device *dev = crtc->dev;
6585 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19 6586 struct intel_encoder *encoder;
0b701d27 6587 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 6588 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6589 int pipe = intel_crtc->pipe;
f564048e
EA		 6590 int ret;
6591
0b701d27 6592 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6593
b8cecdf5
DV		 6594 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6595
79e53945 6596 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6597
9256aa19
DV		 6598 if (ret != 0)
6599 return ret;
6600
6601 for_each_encoder_on_crtc(dev, crtc, encoder) {
6602 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6603 encoder->base.base.id,
6604 drm_get_encoder_name(&encoder->base),
6605 mode->base.id, mode->name);
36f2d1f1 6606 encoder->mode_set(encoder);
9256aa19
DV		 6607 }
6608
6609 return 0;
79e53945
JB		 6610}
6611
3a9627f4
WF		 6612static bool intel_eld_uptodate(struct drm_connector *connector,
6613 int reg_eldv, uint32_t bits_eldv,
6614 int reg_elda, uint32_t bits_elda,
6615 int reg_edid)
6616{
6617 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6618 uint8_t *eld = connector->eld;
6619 uint32_t i;
6620
6621 i = I915_READ(reg_eldv);
6622 i &= bits_eldv;
6623
6624 if (!eld[0])
6625 return !i;
6626
6627 if (!i)
6628 return false;
6629
6630 i = I915_READ(reg_elda);
6631 i &= ~bits_elda;
6632 I915_WRITE(reg_elda, i);
6633
6634 for (i = 0; i < eld[2]; i++)
6635 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6636 return false;
6637
6638 return true;
6639}
6640
e0dac65e
WF		 6641static void g4x_write_eld(struct drm_connector *connector,
6642 struct drm_crtc *crtc)
6643{
6644 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6645 uint8_t *eld = connector->eld;
6646 uint32_t eldv;
6647 uint32_t len;
6648 uint32_t i;
6649
6650 i = I915_READ(G4X_AUD_VID_DID);
6651
6652 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6653 eldv = G4X_ELDV_DEVCL_DEVBLC;
6654 else
6655 eldv = G4X_ELDV_DEVCTG;
6656
3a9627f4
WF		 6657 if (intel_eld_uptodate(connector,
6658 G4X_AUD_CNTL_ST, eldv,
6659 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6660 G4X_HDMIW_HDMIEDID))
6661 return;
6662
e0dac65e
WF		 6663 i = I915_READ(G4X_AUD_CNTL_ST);
6664 i &= ~(eldv | G4X_ELD_ADDR);
6665 len = (i >> 9) & 0x1f; /* ELD buffer size */
6666 I915_WRITE(G4X_AUD_CNTL_ST, i);
6667
6668 if (!eld[0])
6669 return;
6670
6671 len = min_t(uint8_t, eld[2], len);
6672 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6673 for (i = 0; i < len; i++)
6674 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6675
6676 i = I915_READ(G4X_AUD_CNTL_ST);
6677 i |= eldv;
6678 I915_WRITE(G4X_AUD_CNTL_ST, i);
6679}
6680
83358c85
WX		 6681static void haswell_write_eld(struct drm_connector *connector,
6682 struct drm_crtc *crtc)
6683{
6684 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6685 uint8_t *eld = connector->eld;
6686 struct drm_device *dev = crtc->dev;
7b9f35a6 6687 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6688 uint32_t eldv;
6689 uint32_t i;
6690 int len;
6691 int pipe = to_intel_crtc(crtc)->pipe;
6692 int tmp;
6693
6694 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6695 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6696 int aud_config = HSW_AUD_CFG(pipe);
6697 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6698
6699
6700 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6701
6702 /* Audio output enable */
6703 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6704 tmp = I915_READ(aud_cntrl_st2);
6705 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6706 I915_WRITE(aud_cntrl_st2, tmp);
6707
6708 /* Wait for 1 vertical blank */
6709 intel_wait_for_vblank(dev, pipe);
6710
6711 /* Set ELD valid state */
6712 tmp = I915_READ(aud_cntrl_st2);
7e7cb34f 6713 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
83358c85
WX		 6714 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6715 I915_WRITE(aud_cntrl_st2, tmp);
6716 tmp = I915_READ(aud_cntrl_st2);
7e7cb34f 6717 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
83358c85
WX		 6718
6719 /* Enable HDMI mode */
6720 tmp = I915_READ(aud_config);
7e7cb34f 6721 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
83358c85
WX		 6722 /* clear N_programing_enable and N_value_index */
6723 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6724 I915_WRITE(aud_config, tmp);
6725
6726 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6727
6728 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6729 intel_crtc->eld_vld = true;
83358c85
WX		 6730
6731 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6732 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6733 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6734 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6735 } else
6736 I915_WRITE(aud_config, 0);
6737
6738 if (intel_eld_uptodate(connector,
6739 aud_cntrl_st2, eldv,
6740 aud_cntl_st, IBX_ELD_ADDRESS,
6741 hdmiw_hdmiedid))
6742 return;
6743
6744 i = I915_READ(aud_cntrl_st2);
6745 i &= ~eldv;
6746 I915_WRITE(aud_cntrl_st2, i);
6747
6748 if (!eld[0])
6749 return;
6750
6751 i = I915_READ(aud_cntl_st);
6752 i &= ~IBX_ELD_ADDRESS;
6753 I915_WRITE(aud_cntl_st, i);
6754 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6755 DRM_DEBUG_DRIVER("port num:%d\n", i);
6756
6757 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6758 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6759 for (i = 0; i < len; i++)
6760 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6761
6762 i = I915_READ(aud_cntrl_st2);
6763 i |= eldv;
6764 I915_WRITE(aud_cntrl_st2, i);
6765
6766}
6767
e0dac65e
WF		 6768static void ironlake_write_eld(struct drm_connector *connector,
6769 struct drm_crtc *crtc)
6770{
6771 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6772 uint8_t *eld = connector->eld;
6773 uint32_t eldv;
6774 uint32_t i;
6775 int len;
6776 int hdmiw_hdmiedid;
b6daa025 6777 int aud_config;
e0dac65e
WF		 6778 int aud_cntl_st;
6779 int aud_cntrl_st2;
9b138a83 6780 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6781
b3f33cbf 6782 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6783 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6784 aud_config = IBX_AUD_CFG(pipe);
6785 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6786 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6787 } else {
9b138a83
WX		 6788 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6789 aud_config = CPT_AUD_CFG(pipe);
6790 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6791 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6792 }
6793
9b138a83 6794 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6795
6796 i = I915_READ(aud_cntl_st);
9b138a83 6797 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6798 if (!i) {
6799 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6800 /* operate blindly on all ports */
1202b4c6
WF		 6801 eldv = IBX_ELD_VALIDB;
6802 eldv |= IBX_ELD_VALIDB << 4;
6803 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6804 } else {
2582a850 6805 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6806 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6807 }
6808
3a9627f4
WF		 6809 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6810 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6811 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6812 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6813 } else
6814 I915_WRITE(aud_config, 0);
e0dac65e 6815
3a9627f4
WF		 6816 if (intel_eld_uptodate(connector,
6817 aud_cntrl_st2, eldv,
6818 aud_cntl_st, IBX_ELD_ADDRESS,
6819 hdmiw_hdmiedid))
6820 return;
6821
e0dac65e
WF		 6822 i = I915_READ(aud_cntrl_st2);
6823 i &= ~eldv;
6824 I915_WRITE(aud_cntrl_st2, i);
6825
6826 if (!eld[0])
6827 return;
6828
e0dac65e 6829 i = I915_READ(aud_cntl_st);
1202b4c6 6830 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6831 I915_WRITE(aud_cntl_st, i);
6832
6833 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6834 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6835 for (i = 0; i < len; i++)
6836 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6837
6838 i = I915_READ(aud_cntrl_st2);
6839 i |= eldv;
6840 I915_WRITE(aud_cntrl_st2, i);
6841}
6842
6843void intel_write_eld(struct drm_encoder *encoder,
6844 struct drm_display_mode *mode)
6845{
6846 struct drm_crtc *crtc = encoder->crtc;
6847 struct drm_connector *connector;
6848 struct drm_device *dev = encoder->dev;
6849 struct drm_i915_private *dev_priv = dev->dev_private;
6850
6851 connector = drm_select_eld(encoder, mode);
6852 if (!connector)
6853 return;
6854
6855 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6856 connector->base.id,
6857 drm_get_connector_name(connector),
6858 connector->encoder->base.id,
6859 drm_get_encoder_name(connector->encoder));
6860
6861 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6862
6863 if (dev_priv->display.write_eld)
6864 dev_priv->display.write_eld(connector, crtc);
6865}
6866
560b85bb
CW		 6867static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6868{
6869 struct drm_device *dev = crtc->dev;
6870 struct drm_i915_private *dev_priv = dev->dev_private;
6871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6872 bool visible = base != 0;
6873 u32 cntl;
6874
6875 if (intel_crtc->cursor_visible == visible)
6876 return;
6877
9db4a9c7 6878 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6879 if (visible) {
6880 /* On these chipsets we can only modify the base whilst
6881 * the cursor is disabled.
6882 */
9db4a9c7 6883 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6884
6885 cntl &= ~(CURSOR_FORMAT_MASK);
6886 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6887 cntl |= CURSOR_ENABLE |
6888 CURSOR_GAMMA_ENABLE |
6889 CURSOR_FORMAT_ARGB;
6890 } else
6891 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6892 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6893
6894 intel_crtc->cursor_visible = visible;
6895}
6896
6897static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6898{
6899 struct drm_device *dev = crtc->dev;
6900 struct drm_i915_private *dev_priv = dev->dev_private;
6901 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6902 int pipe = intel_crtc->pipe;
6903 bool visible = base != 0;
6904
6905 if (intel_crtc->cursor_visible != visible) {
548f245b 6906 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6907 if (base) {
6908 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6909 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6910 cntl |= pipe << 28; /* Connect to correct pipe */
6911 } else {
6912 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6913 cntl |= CURSOR_MODE_DISABLE;
6914 }
9db4a9c7 6915 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6916
6917 intel_crtc->cursor_visible = visible;
6918 }
6919 /* and commit changes on next vblank */
9db4a9c7 6920 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6921}
6922
65a21cd6
JB		 6923static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6924{
6925 struct drm_device *dev = crtc->dev;
6926 struct drm_i915_private *dev_priv = dev->dev_private;
6927 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6928 int pipe = intel_crtc->pipe;
6929 bool visible = base != 0;
6930
6931 if (intel_crtc->cursor_visible != visible) {
6932 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6933 if (base) {
6934 cntl &= ~CURSOR_MODE;
6935 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6936 } else {
6937 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6938 cntl |= CURSOR_MODE_DISABLE;
6939 }
1f5d76db 6940 if (IS_HASWELL(dev)) {
86d3efce 6941 cntl |= CURSOR_PIPE_CSC_ENABLE;
1f5d76db
PZ		 6942 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
6943 }
65a21cd6
JB		 6944 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6945
6946 intel_crtc->cursor_visible = visible;
6947 }
6948 /* and commit changes on next vblank */
6949 I915_WRITE(CURBASE_IVB(pipe), base);
6950}
6951
cda4b7d3 6952/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6953static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6954 bool on)
cda4b7d3
CW		 6955{
6956 struct drm_device *dev = crtc->dev;
6957 struct drm_i915_private *dev_priv = dev->dev_private;
6958 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6959 int pipe = intel_crtc->pipe;
6960 int x = intel_crtc->cursor_x;
6961 int y = intel_crtc->cursor_y;
d6e4db15 6962 u32 base = 0, pos = 0;
cda4b7d3
CW		 6963 bool visible;
6964
d6e4db15 6965 if (on)
cda4b7d3 6966 base = intel_crtc->cursor_addr;
cda4b7d3 6967
d6e4db15
VS		 6968 if (x >= intel_crtc->config.pipe_src_w)
6969 base = 0;
6970
6971 if (y >= intel_crtc->config.pipe_src_h)
cda4b7d3
CW		 6972 base = 0;
6973
6974 if (x < 0) {
efc9064e 6975 if (x + intel_crtc->cursor_width <= 0)
cda4b7d3
CW		 6976 base = 0;
6977
6978 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6979 x = -x;
6980 }
6981 pos |= x << CURSOR_X_SHIFT;
6982
6983 if (y < 0) {
efc9064e 6984 if (y + intel_crtc->cursor_height <= 0)
cda4b7d3
CW		 6985 base = 0;
6986
6987 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6988 y = -y;
6989 }
6990 pos |= y << CURSOR_Y_SHIFT;
6991
6992 visible = base != 0;
560b85bb 6993 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6994 return;
6995
0cd83aa9 6996 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6997 I915_WRITE(CURPOS_IVB(pipe), pos);
6998 ivb_update_cursor(crtc, base);
6999 } else {
7000 I915_WRITE(CURPOS(pipe), pos);
7001 if (IS_845G(dev) || IS_I865G(dev))
7002 i845_update_cursor(crtc, base);
7003 else
7004 i9xx_update_cursor(crtc, base);
7005 }
cda4b7d3
CW		 7006}
7007
79e53945 7008static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 7009 struct drm_file *file,
79e53945
JB		 7010 uint32_t handle,
7011 uint32_t width, uint32_t height)
7012{
7013 struct drm_device *dev = crtc->dev;
7014 struct drm_i915_private *dev_priv = dev->dev_private;
7015 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 7016 struct drm_i915_gem_object *obj;
cda4b7d3 7017 uint32_t addr;
3f8bc370 7018 int ret;
79e53945 7019
79e53945
JB		 7020 /* if we want to turn off the cursor ignore width and height */
7021 if (!handle) {
28c97730 7022 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 7023 addr = 0;
05394f39 7024 obj = NULL;
5004417d 7025 mutex_lock(&dev->struct_mutex);
3f8bc370 7026 goto finish;
79e53945
JB		 7027 }
7028
7029 /* Currently we only support 64x64 cursors */
7030 if (width != 64 || height != 64) {
7031 DRM_ERROR("we currently only support 64x64 cursors\n");
7032 return -EINVAL;
7033 }
7034
05394f39 7035 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 7036 if (&obj->base == NULL)
79e53945
JB		 7037 return -ENOENT;
7038
05394f39 7039 if (obj->base.size < width * height * 4) {
79e53945 7040 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 7041 ret = -ENOMEM;
7042 goto fail;
79e53945
JB		 7043 }
7044
71acb5eb 7045 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 7046 mutex_lock(&dev->struct_mutex);
b295d1b6 7047 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 7048 unsigned alignment;
7049
d9e86c0e
CW		 7050 if (obj->tiling_mode) {
7051 DRM_ERROR("cursor cannot be tiled\n");
7052 ret = -EINVAL;
7053 goto fail_locked;
7054 }
7055
693db184
CW		 7056 /* Note that the w/a also requires 2 PTE of padding following
7057 * the bo. We currently fill all unused PTE with the shadow
7058 * page and so we should always have valid PTE following the
7059 * cursor preventing the VT-d warning.
7060 */
7061 alignment = 0;
7062 if (need_vtd_wa(dev))
7063 alignment = 64*1024;
7064
7065 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 7066 if (ret) {
7067 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 7068 goto fail_locked;
e7b526bb
CW		 7069 }
7070
d9e86c0e
CW		 7071 ret = i915_gem_object_put_fence(obj);
7072 if (ret) {
2da3b9b9 7073 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 7074 goto fail_unpin;
7075 }
7076
f343c5f6 7077 addr = i915_gem_obj_ggtt_offset(obj);
71acb5eb 7078 } else {
6eeefaf3 7079 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 7080 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 7081 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7082 align);
71acb5eb
DA		 7083 if (ret) {
7084 DRM_ERROR("failed to attach phys object\n");
7f9872e0 7085 goto fail_locked;
71acb5eb 7086 }
05394f39 7087 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 7088 }
7089
a6c45cf0 7090 if (IS_GEN2(dev))
14b60391
JB		 7091 I915_WRITE(CURSIZE, (height << 12) | width);
7092
3f8bc370 7093 finish:
3f8bc370 7094 if (intel_crtc->cursor_bo) {
b295d1b6 7095 if (dev_priv->info->cursor_needs_physical) {
05394f39 7096 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 7097 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7098 } else
cc98b413 7099 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
05394f39 7100 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 7101 }
80824003 7102
7f9872e0 7103 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 7104
7105 intel_crtc->cursor_addr = addr;
05394f39 7106 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 7107 intel_crtc->cursor_width = width;
7108 intel_crtc->cursor_height = height;
7109
f2f5f771
VS		 7110 if (intel_crtc->active)
7111 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 7112
79e53945 7113 return 0;
e7b526bb 7114fail_unpin:
cc98b413 7115 i915_gem_object_unpin_from_display_plane(obj);
7f9872e0 7116fail_locked:
34b8686e 7117 mutex_unlock(&dev->struct_mutex);
bc9025bd 7118fail:
05394f39 7119 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 7120 return ret;
79e53945
JB		 7121}
7122
7123static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7124{
79e53945 7125 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7126
cda4b7d3
CW		 7127 intel_crtc->cursor_x = x;
7128 intel_crtc->cursor_y = y;
652c393a 7129
f2f5f771
VS		 7130 if (intel_crtc->active)
7131 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 7132
7133 return 0;
b8c00ac5
DA		 7134}
7135
79e53945 7136static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 7137 u16 *blue, uint32_t start, uint32_t size)
79e53945 7138{
7203425a 7139 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 7140 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7141
7203425a 7142 for (i = start; i < end; i++) {
79e53945
JB		 7143 intel_crtc->lut_r[i] = red[i] >> 8;
7144 intel_crtc->lut_g[i] = green[i] >> 8;
7145 intel_crtc->lut_b[i] = blue[i] >> 8;
7146 }
7147
7148 intel_crtc_load_lut(crtc);
7149}
7150
79e53945
JB		 7151/* VESA 640x480x72Hz mode to set on the pipe */
7152static struct drm_display_mode load_detect_mode = {
7153 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7154 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7155};
7156
d2dff872
CW		 7157static struct drm_framebuffer *
7158intel_framebuffer_create(struct drm_device *dev,
308e5bcb 7159 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 7160 struct drm_i915_gem_object *obj)
7161{
7162 struct intel_framebuffer *intel_fb;
7163 int ret;
7164
7165 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7166 if (!intel_fb) {
7167 drm_gem_object_unreference_unlocked(&obj->base);
7168 return ERR_PTR(-ENOMEM);
7169 }
7170
7171 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7172 if (ret) {
7173 drm_gem_object_unreference_unlocked(&obj->base);
7174 kfree(intel_fb);
7175 return ERR_PTR(ret);
7176 }
7177
7178 return &intel_fb->base;
7179}
7180
7181static u32
7182intel_framebuffer_pitch_for_width(int width, int bpp)
7183{
7184 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7185 return ALIGN(pitch, 64);
7186}
7187
7188static u32
7189intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7190{
7191 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7192 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7193}
7194
7195static struct drm_framebuffer *
7196intel_framebuffer_create_for_mode(struct drm_device *dev,
7197 struct drm_display_mode *mode,
7198 int depth, int bpp)
7199{
7200 struct drm_i915_gem_object *obj;
0fed39bd 7201 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 7202
7203 obj = i915_gem_alloc_object(dev,
7204 intel_framebuffer_size_for_mode(mode, bpp));
7205 if (obj == NULL)
7206 return ERR_PTR(-ENOMEM);
7207
7208 mode_cmd.width = mode->hdisplay;
7209 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 7210 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7211 bpp);
5ca0c34a 7212 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 7213
7214 return intel_framebuffer_create(dev, &mode_cmd, obj);
7215}
7216
7217static struct drm_framebuffer *
7218mode_fits_in_fbdev(struct drm_device *dev,
7219 struct drm_display_mode *mode)
7220{
7221 struct drm_i915_private *dev_priv = dev->dev_private;
7222 struct drm_i915_gem_object *obj;
7223 struct drm_framebuffer *fb;
7224
7225 if (dev_priv->fbdev == NULL)
7226 return NULL;
7227
7228 obj = dev_priv->fbdev->ifb.obj;
7229 if (obj == NULL)
7230 return NULL;
7231
7232 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 7233 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7234 fb->bits_per_pixel))
d2dff872
CW		 7235 return NULL;
7236
01f2c773 7237 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 7238 return NULL;
7239
7240 return fb;
7241}
7242
d2434ab7 7243bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 7244 struct drm_display_mode *mode,
8261b191 7245 struct intel_load_detect_pipe *old)
79e53945
JB		 7246{
7247 struct intel_crtc *intel_crtc;
d2434ab7
DV		 7248 struct intel_encoder *intel_encoder =
7249 intel_attached_encoder(connector);
79e53945 7250 struct drm_crtc *possible_crtc;
4ef69c7a 7251 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 7252 struct drm_crtc *crtc = NULL;
7253 struct drm_device *dev = encoder->dev;
94352cf9 7254 struct drm_framebuffer *fb;
79e53945
JB		 7255 int i = -1;
7256
d2dff872
CW		 7257 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7258 connector->base.id, drm_get_connector_name(connector),
7259 encoder->base.id, drm_get_encoder_name(encoder));
7260
79e53945
JB		 7261 /*
7262 * Algorithm gets a little messy:
7a5e4805 7263 *
79e53945
JB		 7264 * - if the connector already has an assigned crtc, use it (but make
7265 * sure it's on first)
7a5e4805 7266 *
79e53945
JB		 7267 * - try to find the first unused crtc that can drive this connector,
7268 * and use that if we find one
79e53945
JB		 7269 */
7270
7271 /* See if we already have a CRTC for this connector */
7272 if (encoder->crtc) {
7273 crtc = encoder->crtc;
8261b191 7274
7b24056b
DV		 7275 mutex_lock(&crtc->mutex);
7276
24218aac 7277 old->dpms_mode = connector->dpms;
8261b191
CW		 7278 old->load_detect_temp = false;
7279
7280 /* Make sure the crtc and connector are running */
24218aac
DV		 7281 if (connector->dpms != DRM_MODE_DPMS_ON)
7282 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 7283
7173188d 7284 return true;
79e53945
JB		 7285 }
7286
7287 /* Find an unused one (if possible) */
7288 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7289 i++;
7290 if (!(encoder->possible_crtcs & (1 << i)))
7291 continue;
7292 if (!possible_crtc->enabled) {
7293 crtc = possible_crtc;
7294 break;
7295 }
79e53945
JB		 7296 }
7297
7298 /*
7299 * If we didn't find an unused CRTC, don't use any.
7300 */
7301 if (!crtc) {
7173188d
CW		 7302 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7303 return false;
79e53945
JB		 7304 }
7305
7b24056b 7306 mutex_lock(&crtc->mutex);
fc303101
DV		 7307 intel_encoder->new_crtc = to_intel_crtc(crtc);
7308 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 7309
7310 intel_crtc = to_intel_crtc(crtc);
24218aac 7311 old->dpms_mode = connector->dpms;
8261b191 7312 old->load_detect_temp = true;
d2dff872 7313 old->release_fb = NULL;
79e53945 7314
6492711d
CW		 7315 if (!mode)
7316 mode = &load_detect_mode;
79e53945 7317
d2dff872
CW		 7318 /* We need a framebuffer large enough to accommodate all accesses
7319 * that the plane may generate whilst we perform load detection.
7320 * We can not rely on the fbcon either being present (we get called
7321 * during its initialisation to detect all boot displays, or it may
7322 * not even exist) or that it is large enough to satisfy the
7323 * requested mode.
7324 */
94352cf9
DV		 7325 fb = mode_fits_in_fbdev(dev, mode);
7326 if (fb == NULL) {
d2dff872 7327 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 7328 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7329 old->release_fb = fb;
d2dff872
CW		 7330 } else
7331 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 7332 if (IS_ERR(fb)) {
d2dff872 7333 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 7334 mutex_unlock(&crtc->mutex);
0e8b3d3e 7335 return false;
79e53945 7336 }
79e53945 7337
c0c36b94 7338 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 7339 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 7340 if (old->release_fb)
7341 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 7342 mutex_unlock(&crtc->mutex);
0e8b3d3e 7343 return false;
79e53945 7344 }
7173188d 7345
79e53945 7346 /* let the connector get through one full cycle before testing */
9d0498a2 7347 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 7348 return true;
79e53945
JB		 7349}
7350
d2434ab7 7351void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 7352 struct intel_load_detect_pipe *old)
79e53945 7353{
d2434ab7
DV		 7354 struct intel_encoder *intel_encoder =
7355 intel_attached_encoder(connector);
4ef69c7a 7356 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 7357 struct drm_crtc *crtc = encoder->crtc;
79e53945 7358
d2dff872
CW		 7359 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7360 connector->base.id, drm_get_connector_name(connector),
7361 encoder->base.id, drm_get_encoder_name(encoder));
7362
8261b191 7363 if (old->load_detect_temp) {
fc303101
DV		 7364 to_intel_connector(connector)->new_encoder = NULL;
7365 intel_encoder->new_crtc = NULL;
7366 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 7367
36206361
DV		 7368 if (old->release_fb) {
7369 drm_framebuffer_unregister_private(old->release_fb);
7370 drm_framebuffer_unreference(old->release_fb);
7371 }
d2dff872 7372
67c96400 7373 mutex_unlock(&crtc->mutex);
0622a53c 7374 return;
79e53945
JB		 7375 }
7376
c751ce4f 7377 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 7378 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7379 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 7380
7381 mutex_unlock(&crtc->mutex);
79e53945
JB		 7382}
7383
da4a1efa
VS		 7384static int i9xx_pll_refclk(struct drm_device *dev,
7385 const struct intel_crtc_config *pipe_config)
7386{
7387 struct drm_i915_private *dev_priv = dev->dev_private;
7388 u32 dpll = pipe_config->dpll_hw_state.dpll;
7389
7390 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7391 return dev_priv->vbt.lvds_ssc_freq * 1000;
7392 else if (HAS_PCH_SPLIT(dev))
7393 return 120000;
7394 else if (!IS_GEN2(dev))
7395 return 96000;
7396 else
7397 return 48000;
7398}
7399
79e53945 7400/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc
JB		 7401static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7402 struct intel_crtc_config *pipe_config)
79e53945 7403{
f1f644dc 7404 struct drm_device *dev = crtc->base.dev;
79e53945 7405 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 7406 int pipe = pipe_config->cpu_transcoder;
293623f7 7407 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 7408 u32 fp;
7409 intel_clock_t clock;
da4a1efa 7410 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 7411
7412 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 7413 fp = pipe_config->dpll_hw_state.fp0;
79e53945 7414 else
293623f7 7415 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 7416
7417 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 7418 if (IS_PINEVIEW(dev)) {
7419 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7420 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 7421 } else {
7422 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7423 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7424 }
7425
a6c45cf0 7426 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 7427 if (IS_PINEVIEW(dev))
7428 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7429 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 7430 else
7431 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 7432 DPLL_FPA01_P1_POST_DIV_SHIFT);
7433
7434 switch (dpll & DPLL_MODE_MASK) {
7435 case DPLLB_MODE_DAC_SERIAL:
7436 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7437 5 : 10;
7438 break;
7439 case DPLLB_MODE_LVDS:
7440 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7441 7 : 14;
7442 break;
7443 default:
28c97730 7444 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 7445 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 7446 return;
79e53945
JB		 7447 }
7448
ac58c3f0 7449 if (IS_PINEVIEW(dev))
da4a1efa 7450 pineview_clock(refclk, &clock);
ac58c3f0 7451 else
da4a1efa 7452 i9xx_clock(refclk, &clock);
79e53945
JB		 7453 } else {
7454 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7455
7456 if (is_lvds) {
7457 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7458 DPLL_FPA01_P1_POST_DIV_SHIFT);
7459 clock.p2 = 14;
79e53945
JB		 7460 } else {
7461 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7462 clock.p1 = 2;
7463 else {
7464 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7465 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7466 }
7467 if (dpll & PLL_P2_DIVIDE_BY_4)
7468 clock.p2 = 4;
7469 else
7470 clock.p2 = 2;
79e53945 7471 }
da4a1efa
VS		 7472
7473 i9xx_clock(refclk, &clock);
79e53945
JB		 7474 }
7475
18442d08
VS		 7476 /*
7477 * This value includes pixel_multiplier. We will use
241bfc38 7478 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 7479 * encoder's get_config() function.
7480 */
7481 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 7482}
7483
6878da05
VS		 7484int intel_dotclock_calculate(int link_freq,
7485 const struct intel_link_m_n *m_n)
f1f644dc 7486{
f1f644dc
JB		 7487 /*
7488 * The calculation for the data clock is:
1041a02f 7489 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 7490 * But we want to avoid losing precison if possible, so:
1041a02f 7491 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 7492 *
7493 * and the link clock is simpler:
1041a02f 7494 * link_clock = (m * link_clock) / n
f1f644dc
JB		 7495 */
7496
6878da05
VS		 7497 if (!m_n->link_n)
7498 return 0;
f1f644dc 7499
6878da05
VS		 7500 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
7501}
f1f644dc 7502
18442d08
VS		 7503static void ironlake_pch_clock_get(struct intel_crtc *crtc,
7504 struct intel_crtc_config *pipe_config)
6878da05
VS		 7505{
7506 struct drm_device *dev = crtc->base.dev;
79e53945 7507
18442d08
VS		 7508 /* read out port_clock from the DPLL */
7509 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 7510
f1f644dc 7511 /*
18442d08 7512 * This value does not include pixel_multiplier.
241bfc38 7513 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 7514 * agree once we know their relationship in the encoder's
7515 * get_config() function.
79e53945 7516 */
241bfc38 7517 pipe_config->adjusted_mode.crtc_clock =
18442d08
VS		 7518 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
7519 &pipe_config->fdi_m_n);
79e53945
JB		 7520}
7521
7522/** Returns the currently programmed mode of the given pipe. */
7523struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7524 struct drm_crtc *crtc)
7525{
548f245b 7526 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 7527 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 7528 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 7529 struct drm_display_mode *mode;
f1f644dc 7530 struct intel_crtc_config pipe_config;
fe2b8f9d
PZ		 7531 int htot = I915_READ(HTOTAL(cpu_transcoder));
7532 int hsync = I915_READ(HSYNC(cpu_transcoder));
7533 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7534 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 7535 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 7536
7537 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7538 if (!mode)
7539 return NULL;
7540
f1f644dc
JB		 7541 /*
7542 * Construct a pipe_config sufficient for getting the clock info
7543 * back out of crtc_clock_get.
7544 *
7545 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7546 * to use a real value here instead.
7547 */
293623f7 7548 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 7549 pipe_config.pixel_multiplier = 1;
293623f7
VS		 7550 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
7551 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
7552 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 7553 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7554
773ae034 7555 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 7556 mode->hdisplay = (htot & 0xffff) + 1;
7557 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7558 mode->hsync_start = (hsync & 0xffff) + 1;
7559 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7560 mode->vdisplay = (vtot & 0xffff) + 1;
7561 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7562 mode->vsync_start = (vsync & 0xffff) + 1;
7563 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7564
7565 drm_mode_set_name(mode);
79e53945
JB		 7566
7567 return mode;
7568}
7569
3dec0095 7570static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7571{
7572 struct drm_device *dev = crtc->dev;
7573 drm_i915_private_t *dev_priv = dev->dev_private;
7574 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7575 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7576 int dpll_reg = DPLL(pipe);
7577 int dpll;
652c393a 7578
bad720ff 7579 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7580 return;
7581
7582 if (!dev_priv->lvds_downclock_avail)
7583 return;
7584
dbdc6479 7585 dpll = I915_READ(dpll_reg);
652c393a 7586 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7587 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7588
8ac5a6d5 7589 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7590
7591 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7592 I915_WRITE(dpll_reg, dpll);
9d0498a2 7593 intel_wait_for_vblank(dev, pipe);
dbdc6479 7594
652c393a
JB		 7595 dpll = I915_READ(dpll_reg);
7596 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7597 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7598 }
652c393a
JB		 7599}
7600
7601static void intel_decrease_pllclock(struct drm_crtc *crtc)
7602{
7603 struct drm_device *dev = crtc->dev;
7604 drm_i915_private_t *dev_priv = dev->dev_private;
7605 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7606
bad720ff 7607 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7608 return;
7609
7610 if (!dev_priv->lvds_downclock_avail)
7611 return;
7612
7613 /*
7614 * Since this is called by a timer, we should never get here in
7615 * the manual case.
7616 */
7617 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7618 int pipe = intel_crtc->pipe;
7619 int dpll_reg = DPLL(pipe);
7620 int dpll;
f6e5b160 7621
44d98a61 7622 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7623
8ac5a6d5 7624 assert_panel_unlocked(dev_priv, pipe);
652c393a 7625
dc257cf1 7626 dpll = I915_READ(dpll_reg);
652c393a
JB		 7627 dpll |= DISPLAY_RATE_SELECT_FPA1;
7628 I915_WRITE(dpll_reg, dpll);
9d0498a2 7629 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7630 dpll = I915_READ(dpll_reg);
7631 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7632 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7633 }
7634
7635}
7636
f047e395
CW		 7637void intel_mark_busy(struct drm_device *dev)
7638{
c67a470b
PZ		 7639 struct drm_i915_private *dev_priv = dev->dev_private;
7640
7641 hsw_package_c8_gpu_busy(dev_priv);
7642 i915_update_gfx_val(dev_priv);
f047e395
CW		 7643}
7644
7645void intel_mark_idle(struct drm_device *dev)
652c393a 7646{
c67a470b 7647 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 7648 struct drm_crtc *crtc;
652c393a 7649
c67a470b
PZ		 7650 hsw_package_c8_gpu_idle(dev_priv);
7651
652c393a
JB		 7652 if (!i915_powersave)
7653 return;
7654
652c393a 7655 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7656 if (!crtc->fb)
7657 continue;
7658
725a5b54 7659 intel_decrease_pllclock(crtc);
652c393a 7660 }
652c393a
JB		 7661}
7662
c65355bb
CW		 7663void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7664 struct intel_ring_buffer *ring)
652c393a 7665{
f047e395
CW		 7666 struct drm_device *dev = obj->base.dev;
7667 struct drm_crtc *crtc;
652c393a 7668
f047e395 7669 if (!i915_powersave)
acb87dfb
CW		 7670 return;
7671
652c393a
JB		 7672 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7673 if (!crtc->fb)
7674 continue;
7675
c65355bb
CW		 7676 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7677 continue;
7678
7679 intel_increase_pllclock(crtc);
7680 if (ring && intel_fbc_enabled(dev))
7681 ring->fbc_dirty = true;
652c393a
JB		 7682 }
7683}
7684
79e53945
JB		 7685static void intel_crtc_destroy(struct drm_crtc *crtc)
7686{
7687 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7688 struct drm_device *dev = crtc->dev;
7689 struct intel_unpin_work *work;
7690 unsigned long flags;
7691
7692 spin_lock_irqsave(&dev->event_lock, flags);
7693 work = intel_crtc->unpin_work;
7694 intel_crtc->unpin_work = NULL;
7695 spin_unlock_irqrestore(&dev->event_lock, flags);
7696
7697 if (work) {
7698 cancel_work_sync(&work->work);
7699 kfree(work);
7700 }
79e53945 7701
40ccc72b
MK		 7702 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7703
79e53945 7704 drm_crtc_cleanup(crtc);
67e77c5a 7705
79e53945
JB		 7706 kfree(intel_crtc);
7707}
7708
6b95a207
KH		 7709static void intel_unpin_work_fn(struct work_struct *__work)
7710{
7711 struct intel_unpin_work *work =
7712 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7713 struct drm_device *dev = work->crtc->dev;
6b95a207 7714
b4a98e57 7715 mutex_lock(&dev->struct_mutex);
1690e1eb 7716 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7717 drm_gem_object_unreference(&work->pending_flip_obj->base);
7718 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7719
b4a98e57
CW		 7720 intel_update_fbc(dev);
7721 mutex_unlock(&dev->struct_mutex);
7722
7723 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7724 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7725
6b95a207
KH		 7726 kfree(work);
7727}
7728
1afe3e9d 7729static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7730 struct drm_crtc *crtc)
6b95a207
KH		 7731{
7732 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7733 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7734 struct intel_unpin_work *work;
6b95a207
KH		 7735 unsigned long flags;
7736
7737 /* Ignore early vblank irqs */
7738 if (intel_crtc == NULL)
7739 return;
7740
7741 spin_lock_irqsave(&dev->event_lock, flags);
7742 work = intel_crtc->unpin_work;
e7d841ca
CW		 7743
7744 /* Ensure we don't miss a work->pending update ... */
7745 smp_rmb();
7746
7747 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7748 spin_unlock_irqrestore(&dev->event_lock, flags);
7749 return;
7750 }
7751
e7d841ca
CW		 7752 /* and that the unpin work is consistent wrt ->pending. */
7753 smp_rmb();
7754
6b95a207 7755 intel_crtc->unpin_work = NULL;
6b95a207 7756
45a066eb
RC		 7757 if (work->event)
7758 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7759
0af7e4df
MK		 7760 drm_vblank_put(dev, intel_crtc->pipe);
7761
6b95a207
KH		 7762 spin_unlock_irqrestore(&dev->event_lock, flags);
7763
2c10d571 7764 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7765
7766 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7767
7768 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7769}
7770
1afe3e9d
JB		 7771void intel_finish_page_flip(struct drm_device *dev, int pipe)
7772{
7773 drm_i915_private_t *dev_priv = dev->dev_private;
7774 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7775
49b14a5c 7776 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7777}
7778
7779void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7780{
7781 drm_i915_private_t *dev_priv = dev->dev_private;
7782 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7783
49b14a5c 7784 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7785}
7786
6b95a207
KH		 7787void intel_prepare_page_flip(struct drm_device *dev, int plane)
7788{
7789 drm_i915_private_t *dev_priv = dev->dev_private;
7790 struct intel_crtc *intel_crtc =
7791 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7792 unsigned long flags;
7793
e7d841ca
CW		 7794 /* NB: An MMIO update of the plane base pointer will also
7795 * generate a page-flip completion irq, i.e. every modeset
7796 * is also accompanied by a spurious intel_prepare_page_flip().
7797 */
6b95a207 7798 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7799 if (intel_crtc->unpin_work)
7800 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7801 spin_unlock_irqrestore(&dev->event_lock, flags);
7802}
7803
e7d841ca
CW		 7804inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7805{
7806 /* Ensure that the work item is consistent when activating it ... */
7807 smp_wmb();
7808 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7809 /* and that it is marked active as soon as the irq could fire. */
7810 smp_wmb();
7811}
7812
8c9f3aaf
JB		 7813static int intel_gen2_queue_flip(struct drm_device *dev,
7814 struct drm_crtc *crtc,
7815 struct drm_framebuffer *fb,
ed8d1975
KP		 7816 struct drm_i915_gem_object *obj,
7817 uint32_t flags)
8c9f3aaf
JB		 7818{
7819 struct drm_i915_private *dev_priv = dev->dev_private;
7820 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7821 u32 flip_mask;
6d90c952 7822 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7823 int ret;
7824
6d90c952 7825 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7826 if (ret)
83d4092b 7827 goto err;
8c9f3aaf 7828
6d90c952 7829 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7830 if (ret)
83d4092b 7831 goto err_unpin;
8c9f3aaf
JB		 7832
7833 /* Can't queue multiple flips, so wait for the previous
7834 * one to finish before executing the next.
7835 */
7836 if (intel_crtc->plane)
7837 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7838 else
7839 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7840 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7841 intel_ring_emit(ring, MI_NOOP);
7842 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7843 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7844 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7845 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952 7846 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7847
7848 intel_mark_page_flip_active(intel_crtc);
09246732 7849 __intel_ring_advance(ring);
83d4092b
CW		 7850 return 0;
7851
7852err_unpin:
7853 intel_unpin_fb_obj(obj);
7854err:
8c9f3aaf
JB		 7855 return ret;
7856}
7857
7858static int intel_gen3_queue_flip(struct drm_device *dev,
7859 struct drm_crtc *crtc,
7860 struct drm_framebuffer *fb,
ed8d1975
KP		 7861 struct drm_i915_gem_object *obj,
7862 uint32_t flags)
8c9f3aaf
JB		 7863{
7864 struct drm_i915_private *dev_priv = dev->dev_private;
7865 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7866 u32 flip_mask;
6d90c952 7867 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7868 int ret;
7869
6d90c952 7870 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7871 if (ret)
83d4092b 7872 goto err;
8c9f3aaf 7873
6d90c952 7874 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7875 if (ret)
83d4092b 7876 goto err_unpin;
8c9f3aaf
JB		 7877
7878 if (intel_crtc->plane)
7879 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7880 else
7881 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7882 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7883 intel_ring_emit(ring, MI_NOOP);
7884 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7885 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7886 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7887 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952
DV		 7888 intel_ring_emit(ring, MI_NOOP);
7889
e7d841ca 7890 intel_mark_page_flip_active(intel_crtc);
09246732 7891 __intel_ring_advance(ring);
83d4092b
CW		 7892 return 0;
7893
7894err_unpin:
7895 intel_unpin_fb_obj(obj);
7896err:
8c9f3aaf
JB		 7897 return ret;
7898}
7899
7900static int intel_gen4_queue_flip(struct drm_device *dev,
7901 struct drm_crtc *crtc,
7902 struct drm_framebuffer *fb,
ed8d1975
KP		 7903 struct drm_i915_gem_object *obj,
7904 uint32_t flags)
8c9f3aaf
JB		 7905{
7906 struct drm_i915_private *dev_priv = dev->dev_private;
7907 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7908 uint32_t pf, pipesrc;
6d90c952 7909 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7910 int ret;
7911
6d90c952 7912 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7913 if (ret)
83d4092b 7914 goto err;
8c9f3aaf 7915
6d90c952 7916 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7917 if (ret)
83d4092b 7918 goto err_unpin;
8c9f3aaf
JB		 7919
7920 /* i965+ uses the linear or tiled offsets from the
7921 * Display Registers (which do not change across a page-flip)
7922 * so we need only reprogram the base address.
7923 */
6d90c952
DV		 7924 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7925 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7926 intel_ring_emit(ring, fb->pitches[0]);
c2c75131 7927 intel_ring_emit(ring,
f343c5f6 7928 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
c2c75131 7929 obj->tiling_mode);
8c9f3aaf
JB		 7930
7931 /* XXX Enabling the panel-fitter across page-flip is so far
7932 * untested on non-native modes, so ignore it for now.
7933 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7934 */
7935 pf = 0;
7936 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7937 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7938
7939 intel_mark_page_flip_active(intel_crtc);
09246732 7940 __intel_ring_advance(ring);
83d4092b
CW		 7941 return 0;
7942
7943err_unpin:
7944 intel_unpin_fb_obj(obj);
7945err:
8c9f3aaf
JB		 7946 return ret;
7947}
7948
7949static int intel_gen6_queue_flip(struct drm_device *dev,
7950 struct drm_crtc *crtc,
7951 struct drm_framebuffer *fb,
ed8d1975
KP		 7952 struct drm_i915_gem_object *obj,
7953 uint32_t flags)
8c9f3aaf
JB		 7954{
7955 struct drm_i915_private *dev_priv = dev->dev_private;
7956 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7957 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7958 uint32_t pf, pipesrc;
7959 int ret;
7960
6d90c952 7961 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7962 if (ret)
83d4092b 7963 goto err;
8c9f3aaf 7964
6d90c952 7965 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7966 if (ret)
83d4092b 7967 goto err_unpin;
8c9f3aaf 7968
6d90c952
DV		 7969 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7970 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7971 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
f343c5f6 7972 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8c9f3aaf 7973
dc257cf1
DV		 7974 /* Contrary to the suggestions in the documentation,
7975 * "Enable Panel Fitter" does not seem to be required when page
7976 * flipping with a non-native mode, and worse causes a normal
7977 * modeset to fail.
7978 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7979 */
7980 pf = 0;
8c9f3aaf 7981 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7982 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7983
7984 intel_mark_page_flip_active(intel_crtc);
09246732 7985 __intel_ring_advance(ring);
83d4092b
CW		 7986 return 0;
7987
7988err_unpin:
7989 intel_unpin_fb_obj(obj);
7990err:
8c9f3aaf
JB		 7991 return ret;
7992}
7993
7c9017e5
JB		 7994static int intel_gen7_queue_flip(struct drm_device *dev,
7995 struct drm_crtc *crtc,
7996 struct drm_framebuffer *fb,
ed8d1975
KP		 7997 struct drm_i915_gem_object *obj,
7998 uint32_t flags)
7c9017e5
JB		 7999{
8000 struct drm_i915_private *dev_priv = dev->dev_private;
8001 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ffe74d75 8002 struct intel_ring_buffer *ring;
cb05d8de 8003 uint32_t plane_bit = 0;
ffe74d75
CW		 8004 int len, ret;
8005
8006 ring = obj->ring;
1c5fd085 8007 if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
ffe74d75 8008 ring = &dev_priv->ring[BCS];
7c9017e5
JB		 8009
8010 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8011 if (ret)
83d4092b 8012 goto err;
7c9017e5 8013
cb05d8de
DV		 8014 switch(intel_crtc->plane) {
8015 case PLANE_A:
8016 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8017 break;
8018 case PLANE_B:
8019 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8020 break;
8021 case PLANE_C:
8022 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8023 break;
8024 default:
8025 WARN_ONCE(1, "unknown plane in flip command\n");
8026 ret = -ENODEV;
ab3951eb 8027 goto err_unpin;
cb05d8de
DV		 8028 }
8029
ffe74d75
CW		 8030 len = 4;
8031 if (ring->id == RCS)
8032 len += 6;
8033
8034 ret = intel_ring_begin(ring, len);
7c9017e5 8035 if (ret)
83d4092b 8036 goto err_unpin;
7c9017e5 8037
ffe74d75
CW		 8038 /* Unmask the flip-done completion message. Note that the bspec says that
8039 * we should do this for both the BCS and RCS, and that we must not unmask
8040 * more than one flip event at any time (or ensure that one flip message
8041 * can be sent by waiting for flip-done prior to queueing new flips).
8042 * Experimentation says that BCS works despite DERRMR masking all
8043 * flip-done completion events and that unmasking all planes at once
8044 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8045 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8046 */
8047 if (ring->id == RCS) {
8048 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8049 intel_ring_emit(ring, DERRMR);
8050 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8051 DERRMR_PIPEB_PRI_FLIP_DONE |
8052 DERRMR_PIPEC_PRI_FLIP_DONE));
8053 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8054 intel_ring_emit(ring, DERRMR);
8055 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8056 }
8057
cb05d8de 8058 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 8059 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
f343c5f6 8060 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7c9017e5 8061 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 8062
8063 intel_mark_page_flip_active(intel_crtc);
09246732 8064 __intel_ring_advance(ring);
83d4092b
CW		 8065 return 0;
8066
8067err_unpin:
8068 intel_unpin_fb_obj(obj);
8069err:
7c9017e5
JB		 8070 return ret;
8071}
8072
8c9f3aaf
JB		 8073static int intel_default_queue_flip(struct drm_device *dev,
8074 struct drm_crtc *crtc,
8075 struct drm_framebuffer *fb,
ed8d1975
KP		 8076 struct drm_i915_gem_object *obj,
8077 uint32_t flags)
8c9f3aaf
JB		 8078{
8079 return -ENODEV;
8080}
8081
6b95a207
KH		 8082static int intel_crtc_page_flip(struct drm_crtc *crtc,
8083 struct drm_framebuffer *fb,
ed8d1975
KP		 8084 struct drm_pending_vblank_event *event,
8085 uint32_t page_flip_flags)
6b95a207
KH		 8086{
8087 struct drm_device *dev = crtc->dev;
8088 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 8089 struct drm_framebuffer *old_fb = crtc->fb;
8090 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 8091 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8092 struct intel_unpin_work *work;
8c9f3aaf 8093 unsigned long flags;
52e68630 8094 int ret;
6b95a207 8095
e6a595d2
VS		 8096 /* Can't change pixel format via MI display flips. */
8097 if (fb->pixel_format != crtc->fb->pixel_format)
8098 return -EINVAL;
8099
8100 /*
8101 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8102 * Note that pitch changes could also affect these register.
8103 */
8104 if (INTEL_INFO(dev)->gen > 3 &&
8105 (fb->offsets[0] != crtc->fb->offsets[0] ||
8106 fb->pitches[0] != crtc->fb->pitches[0]))
8107 return -EINVAL;
8108
b14c5679 8109 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 8110 if (work == NULL)
8111 return -ENOMEM;
8112
6b95a207 8113 work->event = event;
b4a98e57 8114 work->crtc = crtc;
4a35f83b 8115 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 8116 INIT_WORK(&work->work, intel_unpin_work_fn);
8117
7317c75e
JB		 8118 ret = drm_vblank_get(dev, intel_crtc->pipe);
8119 if (ret)
8120 goto free_work;
8121
6b95a207
KH		 8122 /* We borrow the event spin lock for protecting unpin_work */
8123 spin_lock_irqsave(&dev->event_lock, flags);
8124 if (intel_crtc->unpin_work) {
8125 spin_unlock_irqrestore(&dev->event_lock, flags);
8126 kfree(work);
7317c75e 8127 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 8128
8129 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 8130 return -EBUSY;
8131 }
8132 intel_crtc->unpin_work = work;
8133 spin_unlock_irqrestore(&dev->event_lock, flags);
8134
b4a98e57
CW		 8135 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8136 flush_workqueue(dev_priv->wq);
8137
79158103
CW		 8138 ret = i915_mutex_lock_interruptible(dev);
8139 if (ret)
8140 goto cleanup;
6b95a207 8141
75dfca80 8142 /* Reference the objects for the scheduled work. */
05394f39
CW		 8143 drm_gem_object_reference(&work->old_fb_obj->base);
8144 drm_gem_object_reference(&obj->base);
6b95a207
KH		 8145
8146 crtc->fb = fb;
96b099fd 8147
e1f99ce6 8148 work->pending_flip_obj = obj;
e1f99ce6 8149
4e5359cd
SF		 8150 work->enable_stall_check = true;
8151
b4a98e57 8152 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 8153 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 8154
ed8d1975 8155 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8c9f3aaf
JB		 8156 if (ret)
8157 goto cleanup_pending;
6b95a207 8158
7782de3b 8159 intel_disable_fbc(dev);
c65355bb 8160 intel_mark_fb_busy(obj, NULL);
6b95a207
KH		 8161 mutex_unlock(&dev->struct_mutex);
8162
e5510fac
JB		 8163 trace_i915_flip_request(intel_crtc->plane, obj);
8164
6b95a207 8165 return 0;
96b099fd 8166
8c9f3aaf 8167cleanup_pending:
b4a98e57 8168 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 8169 crtc->fb = old_fb;
05394f39
CW		 8170 drm_gem_object_unreference(&work->old_fb_obj->base);
8171 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 8172 mutex_unlock(&dev->struct_mutex);
8173
79158103 8174cleanup:
96b099fd
CW		 8175 spin_lock_irqsave(&dev->event_lock, flags);
8176 intel_crtc->unpin_work = NULL;
8177 spin_unlock_irqrestore(&dev->event_lock, flags);
8178
7317c75e
JB		 8179 drm_vblank_put(dev, intel_crtc->pipe);
8180free_work:
96b099fd
CW		 8181 kfree(work);
8182
8183 return ret;
6b95a207
KH		 8184}
8185
f6e5b160 8186static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 8187 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8188 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 8189};
8190
50f56119
DV		 8191static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8192 struct drm_crtc *crtc)
8193{
8194 struct drm_device *dev;
8195 struct drm_crtc *tmp;
8196 int crtc_mask = 1;
47f1c6c9 8197
50f56119 8198 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 8199
50f56119 8200 dev = crtc->dev;
47f1c6c9 8201
50f56119
DV		 8202 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8203 if (tmp == crtc)
8204 break;
8205 crtc_mask <<= 1;
8206 }
47f1c6c9 8207
50f56119
DV		 8208 if (encoder->possible_crtcs & crtc_mask)
8209 return true;
8210 return false;
47f1c6c9 8211}
79e53945 8212
9a935856
DV		 8213/**
8214 * intel_modeset_update_staged_output_state
8215 *
8216 * Updates the staged output configuration state, e.g. after we've read out the
8217 * current hw state.
8218 */
8219static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 8220{
9a935856
DV		 8221 struct intel_encoder *encoder;
8222 struct intel_connector *connector;
f6e5b160 8223
9a935856
DV		 8224 list_for_each_entry(connector, &dev->mode_config.connector_list,
8225 base.head) {
8226 connector->new_encoder =
8227 to_intel_encoder(connector->base.encoder);
8228 }
f6e5b160 8229
9a935856
DV		 8230 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8231 base.head) {
8232 encoder->new_crtc =
8233 to_intel_crtc(encoder->base.crtc);
8234 }
f6e5b160
CW		 8235}
8236
9a935856
DV		 8237/**
8238 * intel_modeset_commit_output_state
8239 *
8240 * This function copies the stage display pipe configuration to the real one.
8241 */
8242static void intel_modeset_commit_output_state(struct drm_device *dev)
8243{
8244 struct intel_encoder *encoder;
8245 struct intel_connector *connector;
f6e5b160 8246
9a935856
DV		 8247 list_for_each_entry(connector, &dev->mode_config.connector_list,
8248 base.head) {
8249 connector->base.encoder = &connector->new_encoder->base;
8250 }
f6e5b160 8251
9a935856
DV		 8252 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8253 base.head) {
8254 encoder->base.crtc = &encoder->new_crtc->base;
8255 }
8256}
8257
050f7aeb
DV		 8258static void
8259connected_sink_compute_bpp(struct intel_connector * connector,
8260 struct intel_crtc_config *pipe_config)
8261{
8262 int bpp = pipe_config->pipe_bpp;
8263
8264 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8265 connector->base.base.id,
8266 drm_get_connector_name(&connector->base));
8267
8268 /* Don't use an invalid EDID bpc value */
8269 if (connector->base.display_info.bpc &&
8270 connector->base.display_info.bpc * 3 < bpp) {
8271 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8272 bpp, connector->base.display_info.bpc*3);
8273 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8274 }
8275
8276 /* Clamp bpp to 8 on screens without EDID 1.4 */
8277 if (connector->base.display_info.bpc == 0 && bpp > 24) {
8278 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8279 bpp);
8280 pipe_config->pipe_bpp = 24;
8281 }
8282}
8283
4e53c2e0 8284static int
050f7aeb
DV		 8285compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8286 struct drm_framebuffer *fb,
8287 struct intel_crtc_config *pipe_config)
4e53c2e0 8288{
050f7aeb
DV		 8289 struct drm_device *dev = crtc->base.dev;
8290 struct intel_connector *connector;
4e53c2e0
DV		 8291 int bpp;
8292
d42264b1
DV		 8293 switch (fb->pixel_format) {
8294 case DRM_FORMAT_C8:
4e53c2e0
DV		 8295 bpp = 8*3; /* since we go through a colormap */
8296 break;
d42264b1
DV		 8297 case DRM_FORMAT_XRGB1555:
8298 case DRM_FORMAT_ARGB1555:
8299 /* checked in intel_framebuffer_init already */
8300 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8301 return -EINVAL;
8302 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 8303 bpp = 6*3; /* min is 18bpp */
8304 break;
d42264b1
DV		 8305 case DRM_FORMAT_XBGR8888:
8306 case DRM_FORMAT_ABGR8888:
8307 /* checked in intel_framebuffer_init already */
8308 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8309 return -EINVAL;
8310 case DRM_FORMAT_XRGB8888:
8311 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 8312 bpp = 8*3;
8313 break;
d42264b1
DV		 8314 case DRM_FORMAT_XRGB2101010:
8315 case DRM_FORMAT_ARGB2101010:
8316 case DRM_FORMAT_XBGR2101010:
8317 case DRM_FORMAT_ABGR2101010:
8318 /* checked in intel_framebuffer_init already */
8319 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 8320 return -EINVAL;
4e53c2e0
DV		 8321 bpp = 10*3;
8322 break;
baba133a 8323 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 8324 default:
8325 DRM_DEBUG_KMS("unsupported depth\n");
8326 return -EINVAL;
8327 }
8328
4e53c2e0
DV		 8329 pipe_config->pipe_bpp = bpp;
8330
8331 /* Clamp display bpp to EDID value */
8332 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 8333 base.head) {
1b829e05
DV		 8334 if (!connector->new_encoder ||
8335 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 8336 continue;
8337
050f7aeb 8338 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 8339 }
8340
8341 return bpp;
8342}
8343
644db711
DV		 8344static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
8345{
8346 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8347 "type: 0x%x flags: 0x%x\n",
1342830c 8348 mode->crtc_clock,
644db711
DV		 8349 mode->crtc_hdisplay, mode->crtc_hsync_start,
8350 mode->crtc_hsync_end, mode->crtc_htotal,
8351 mode->crtc_vdisplay, mode->crtc_vsync_start,
8352 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
8353}
8354
c0b03411
DV		 8355static void intel_dump_pipe_config(struct intel_crtc *crtc,
8356 struct intel_crtc_config *pipe_config,
8357 const char *context)
8358{
8359 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8360 context, pipe_name(crtc->pipe));
8361
8362 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8363 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8364 pipe_config->pipe_bpp, pipe_config->dither);
8365 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8366 pipe_config->has_pch_encoder,
8367 pipe_config->fdi_lanes,
8368 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8369 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8370 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 8371 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8372 pipe_config->has_dp_encoder,
8373 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8374 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8375 pipe_config->dp_m_n.tu);
c0b03411
DV		 8376 DRM_DEBUG_KMS("requested mode:\n");
8377 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8378 DRM_DEBUG_KMS("adjusted mode:\n");
8379 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
644db711 8380 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
d71b8d4a 8381 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 8382 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8383 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
c0b03411
DV		 8384 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8385 pipe_config->gmch_pfit.control,
8386 pipe_config->gmch_pfit.pgm_ratios,
8387 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 8388 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 8389 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 8390 pipe_config->pch_pfit.size,
8391 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 8392 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 8393 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
c0b03411
DV		 8394}
8395
accfc0c5
DV		 8396static bool check_encoder_cloning(struct drm_crtc *crtc)
8397{
8398 int num_encoders = 0;
8399 bool uncloneable_encoders = false;
8400 struct intel_encoder *encoder;
8401
8402 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8403 base.head) {
8404 if (&encoder->new_crtc->base != crtc)
8405 continue;
8406
8407 num_encoders++;
8408 if (!encoder->cloneable)
8409 uncloneable_encoders = true;
8410 }
8411
8412 return !(num_encoders > 1 && uncloneable_encoders);
8413}
8414
b8cecdf5
DV		 8415static struct intel_crtc_config *
8416intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 8417 struct drm_framebuffer *fb,
b8cecdf5 8418 struct drm_display_mode *mode)
ee7b9f93 8419{
7758a113 8420 struct drm_device *dev = crtc->dev;
7758a113 8421 struct intel_encoder *encoder;
b8cecdf5 8422 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 8423 int plane_bpp, ret = -EINVAL;
8424 bool retry = true;
ee7b9f93 8425
accfc0c5
DV		 8426 if (!check_encoder_cloning(crtc)) {
8427 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8428 return ERR_PTR(-EINVAL);
8429 }
8430
b8cecdf5
DV		 8431 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8432 if (!pipe_config)
7758a113
DV		 8433 return ERR_PTR(-ENOMEM);
8434
b8cecdf5
DV		 8435 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8436 drm_mode_copy(&pipe_config->requested_mode, mode);
37327abd 8437
e143a21c
DV		 8438 pipe_config->cpu_transcoder =
8439 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 8440 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 8441
2960bc9c
ID		 8442 /*
8443 * Sanitize sync polarity flags based on requested ones. If neither
8444 * positive or negative polarity is requested, treat this as meaning
8445 * negative polarity.
8446 */
8447 if (!(pipe_config->adjusted_mode.flags &
8448 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8449 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8450
8451 if (!(pipe_config->adjusted_mode.flags &
8452 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8453 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8454
050f7aeb
DV		 8455 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8456 * plane pixel format and any sink constraints into account. Returns the
8457 * source plane bpp so that dithering can be selected on mismatches
8458 * after encoders and crtc also have had their say. */
8459 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8460 fb, pipe_config);
4e53c2e0
DV		 8461 if (plane_bpp < 0)
8462 goto fail;
8463
e29c22c0 8464encoder_retry:
ef1b460d 8465 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 8466 pipe_config->port_clock = 0;
ef1b460d 8467 pipe_config->pixel_multiplier = 1;
ff9a6750 8468
135c81b8 8469 /* Fill in default crtc timings, allow encoders to overwrite them. */
6ce70f5e 8470 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
135c81b8 8471
350a10ca
DL		 8472 /* set_crtcinfo() may have adjusted hdisplay/vdisplay */
8473 pipe_config->pipe_src_w = pipe_config->adjusted_mode.crtc_hdisplay;
8474 pipe_config->pipe_src_h = pipe_config->adjusted_mode.crtc_vdisplay;
8475
7758a113
DV		 8476 /* Pass our mode to the connectors and the CRTC to give them a chance to
8477 * adjust it according to limitations or connector properties, and also
8478 * a chance to reject the mode entirely.
47f1c6c9 8479 */
7758a113
DV		 8480 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8481 base.head) {
47f1c6c9 8482
7758a113
DV		 8483 if (&encoder->new_crtc->base != crtc)
8484 continue;
7ae89233 8485
efea6e8e
DV		 8486 if (!(encoder->compute_config(encoder, pipe_config))) {
8487 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 8488 goto fail;
8489 }
ee7b9f93 8490 }
47f1c6c9 8491
ff9a6750
DV		 8492 /* Set default port clock if not overwritten by the encoder. Needs to be
8493 * done afterwards in case the encoder adjusts the mode. */
8494 if (!pipe_config->port_clock)
241bfc38
DL		 8495 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
8496 * pipe_config->pixel_multiplier;
ff9a6750 8497
a43f6e0f 8498 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 8499 if (ret < 0) {
7758a113
DV		 8500 DRM_DEBUG_KMS("CRTC fixup failed\n");
8501 goto fail;
ee7b9f93 8502 }
e29c22c0
DV		 8503
8504 if (ret == RETRY) {
8505 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8506 ret = -EINVAL;
8507 goto fail;
8508 }
8509
8510 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8511 retry = false;
8512 goto encoder_retry;
8513 }
8514
4e53c2e0
DV		 8515 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8516 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8517 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8518
b8cecdf5 8519 return pipe_config;
7758a113 8520fail:
b8cecdf5 8521 kfree(pipe_config);
e29c22c0 8522 return ERR_PTR(ret);
ee7b9f93 8523}
47f1c6c9 8524
e2e1ed41
DV		 8525/* Computes which crtcs are affected and sets the relevant bits in the mask. For
8526 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8527static void
8528intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8529 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 8530{
8531 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 8532 struct drm_device *dev = crtc->dev;
8533 struct intel_encoder *encoder;
8534 struct intel_connector *connector;
8535 struct drm_crtc *tmp_crtc;
79e53945 8536
e2e1ed41 8537 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 8538
e2e1ed41
DV		 8539 /* Check which crtcs have changed outputs connected to them, these need
8540 * to be part of the prepare_pipes mask. We don't (yet) support global
8541 * modeset across multiple crtcs, so modeset_pipes will only have one
8542 * bit set at most. */
8543 list_for_each_entry(connector, &dev->mode_config.connector_list,
8544 base.head) {
8545 if (connector->base.encoder == &connector->new_encoder->base)
8546 continue;
79e53945 8547
e2e1ed41
DV		 8548 if (connector->base.encoder) {
8549 tmp_crtc = connector->base.encoder->crtc;
8550
8551 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8552 }
8553
8554 if (connector->new_encoder)
8555 *prepare_pipes |=
8556 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 8557 }
8558
e2e1ed41
DV		 8559 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8560 base.head) {
8561 if (encoder->base.crtc == &encoder->new_crtc->base)
8562 continue;
8563
8564 if (encoder->base.crtc) {
8565 tmp_crtc = encoder->base.crtc;
8566
8567 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8568 }
8569
8570 if (encoder->new_crtc)
8571 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 8572 }
8573
e2e1ed41
DV		 8574 /* Check for any pipes that will be fully disabled ... */
8575 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8576 base.head) {
8577 bool used = false;
22fd0fab 8578
e2e1ed41
DV		 8579 /* Don't try to disable disabled crtcs. */
8580 if (!intel_crtc->base.enabled)
8581 continue;
7e7d76c3 8582
e2e1ed41
DV		 8583 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8584 base.head) {
8585 if (encoder->new_crtc == intel_crtc)
8586 used = true;
8587 }
8588
8589 if (!used)
8590 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 8591 }
8592
e2e1ed41
DV		 8593
8594 /* set_mode is also used to update properties on life display pipes. */
8595 intel_crtc = to_intel_crtc(crtc);
8596 if (crtc->enabled)
8597 *prepare_pipes |= 1 << intel_crtc->pipe;
8598
b6c5164d
DV		 8599 /*
8600 * For simplicity do a full modeset on any pipe where the output routing
8601 * changed. We could be more clever, but that would require us to be
8602 * more careful with calling the relevant encoder->mode_set functions.
8603 */
e2e1ed41
DV		 8604 if (*prepare_pipes)
8605 *modeset_pipes = *prepare_pipes;
8606
8607 /* ... and mask these out. */
8608 *modeset_pipes &= ~(*disable_pipes);
8609 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 8610
8611 /*
8612 * HACK: We don't (yet) fully support global modesets. intel_set_config
8613 * obies this rule, but the modeset restore mode of
8614 * intel_modeset_setup_hw_state does not.
8615 */
8616 *modeset_pipes &= 1 << intel_crtc->pipe;
8617 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 8618
8619 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8620 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 8621}
79e53945 8622
ea9d758d 8623static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 8624{
ea9d758d 8625 struct drm_encoder *encoder;
f6e5b160 8626 struct drm_device *dev = crtc->dev;
f6e5b160 8627
ea9d758d
DV		 8628 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8629 if (encoder->crtc == crtc)
8630 return true;
8631
8632 return false;
8633}
8634
8635static void
8636intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8637{
8638 struct intel_encoder *intel_encoder;
8639 struct intel_crtc *intel_crtc;
8640 struct drm_connector *connector;
8641
8642 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8643 base.head) {
8644 if (!intel_encoder->base.crtc)
8645 continue;
8646
8647 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8648
8649 if (prepare_pipes & (1 << intel_crtc->pipe))
8650 intel_encoder->connectors_active = false;
8651 }
8652
8653 intel_modeset_commit_output_state(dev);
8654
8655 /* Update computed state. */
8656 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8657 base.head) {
8658 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8659 }
8660
8661 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8662 if (!connector->encoder || !connector->encoder->crtc)
8663 continue;
8664
8665 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8666
8667 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8668 struct drm_property *dpms_property =
8669 dev->mode_config.dpms_property;
8670
ea9d758d 8671 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8672 drm_object_property_set_value(&connector->base,
68d34720
DV		 8673 dpms_property,
8674 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8675
8676 intel_encoder = to_intel_encoder(connector->encoder);
8677 intel_encoder->connectors_active = true;
8678 }
8679 }
8680
8681}
8682
3bd26263 8683static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 8684{
3bd26263 8685 int diff;
f1f644dc
JB		 8686
8687 if (clock1 == clock2)
8688 return true;
8689
8690 if (!clock1 || !clock2)
8691 return false;
8692
8693 diff = abs(clock1 - clock2);
8694
8695 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8696 return true;
8697
8698 return false;
8699}
8700
25c5b266
DV		 8701#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8702 list_for_each_entry((intel_crtc), \
8703 &(dev)->mode_config.crtc_list, \
8704 base.head) \
0973f18f 8705 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8706
0e8ffe1b 8707static bool
2fa2fe9a
DV		 8708intel_pipe_config_compare(struct drm_device *dev,
8709 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8710 struct intel_crtc_config *pipe_config)
8711{
66e985c0
DV		 8712#define PIPE_CONF_CHECK_X(name) \
8713 if (current_config->name != pipe_config->name) { \
8714 DRM_ERROR("mismatch in " #name " " \
8715 "(expected 0x%08x, found 0x%08x)\n", \
8716 current_config->name, \
8717 pipe_config->name); \
8718 return false; \
8719 }
8720
08a24034
DV		 8721#define PIPE_CONF_CHECK_I(name) \
8722 if (current_config->name != pipe_config->name) { \
8723 DRM_ERROR("mismatch in " #name " " \
8724 "(expected %i, found %i)\n", \
8725 current_config->name, \
8726 pipe_config->name); \
8727 return false; \
88adfff1
DV		 8728 }
8729
1bd1bd80
DV		 8730#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8731 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 8732 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 8733 "(expected %i, found %i)\n", \
8734 current_config->name & (mask), \
8735 pipe_config->name & (mask)); \
8736 return false; \
8737 }
8738
5e550656
VS		 8739#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
8740 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
8741 DRM_ERROR("mismatch in " #name " " \
8742 "(expected %i, found %i)\n", \
8743 current_config->name, \
8744 pipe_config->name); \
8745 return false; \
8746 }
8747
bb760063
DV		 8748#define PIPE_CONF_QUIRK(quirk) \
8749 ((current_config->quirks | pipe_config->quirks) & (quirk))
8750
eccb140b
DV		 8751 PIPE_CONF_CHECK_I(cpu_transcoder);
8752
08a24034
DV		 8753 PIPE_CONF_CHECK_I(has_pch_encoder);
8754 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8755 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8756 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8757 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8758 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8759 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8760
eb14cb74
VS		 8761 PIPE_CONF_CHECK_I(has_dp_encoder);
8762 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
8763 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
8764 PIPE_CONF_CHECK_I(dp_m_n.link_m);
8765 PIPE_CONF_CHECK_I(dp_m_n.link_n);
8766 PIPE_CONF_CHECK_I(dp_m_n.tu);
8767
1bd1bd80
DV		 8768 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8769 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8770 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8771 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8772 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8773 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8774
8775 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8776 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8777 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8778 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8779 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8780 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8781
c93f54cf 8782 PIPE_CONF_CHECK_I(pixel_multiplier);
6c49f241 8783
1bd1bd80
DV		 8784 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8785 DRM_MODE_FLAG_INTERLACE);
8786
bb760063
DV		 8787 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8788 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8789 DRM_MODE_FLAG_PHSYNC);
8790 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8791 DRM_MODE_FLAG_NHSYNC);
8792 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8793 DRM_MODE_FLAG_PVSYNC);
8794 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8795 DRM_MODE_FLAG_NVSYNC);
8796 }
045ac3b5 8797
37327abd
VS		 8798 PIPE_CONF_CHECK_I(pipe_src_w);
8799 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 8800
2fa2fe9a
DV		 8801 PIPE_CONF_CHECK_I(gmch_pfit.control);
8802 /* pfit ratios are autocomputed by the hw on gen4+ */
8803 if (INTEL_INFO(dev)->gen < 4)
8804 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8805 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
fd4daa9c
CW		 8806 PIPE_CONF_CHECK_I(pch_pfit.enabled);
8807 if (current_config->pch_pfit.enabled) {
8808 PIPE_CONF_CHECK_I(pch_pfit.pos);
8809 PIPE_CONF_CHECK_I(pch_pfit.size);
8810 }
2fa2fe9a 8811
42db64ef
PZ		 8812 PIPE_CONF_CHECK_I(ips_enabled);
8813
282740f7
VS		 8814 PIPE_CONF_CHECK_I(double_wide);
8815
c0d43d62 8816 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 8817 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 8818 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 8819 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8820 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
c0d43d62 8821
42571aef
VS		 8822 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
8823 PIPE_CONF_CHECK_I(pipe_bpp);
8824
d71b8d4a 8825 if (!IS_HASWELL(dev)) {
241bfc38 8826 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
d71b8d4a
VS		 8827 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
8828 }
5e550656 8829
66e985c0 8830#undef PIPE_CONF_CHECK_X
08a24034 8831#undef PIPE_CONF_CHECK_I
1bd1bd80 8832#undef PIPE_CONF_CHECK_FLAGS
5e550656 8833#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 8834#undef PIPE_CONF_QUIRK
88adfff1 8835
0e8ffe1b
DV		 8836 return true;
8837}
8838
91d1b4bd
DV		 8839static void
8840check_connector_state(struct drm_device *dev)
8af6cf88 8841{
8af6cf88
DV		 8842 struct intel_connector *connector;
8843
8844 list_for_each_entry(connector, &dev->mode_config.connector_list,
8845 base.head) {
8846 /* This also checks the encoder/connector hw state with the
8847 * ->get_hw_state callbacks. */
8848 intel_connector_check_state(connector);
8849
8850 WARN(&connector->new_encoder->base != connector->base.encoder,
8851 "connector's staged encoder doesn't match current encoder\n");
8852 }
91d1b4bd
DV		 8853}
8854
8855static void
8856check_encoder_state(struct drm_device *dev)
8857{
8858 struct intel_encoder *encoder;
8859 struct intel_connector *connector;
8af6cf88
DV		 8860
8861 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8862 base.head) {
8863 bool enabled = false;
8864 bool active = false;
8865 enum pipe pipe, tracked_pipe;
8866
8867 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8868 encoder->base.base.id,
8869 drm_get_encoder_name(&encoder->base));
8870
8871 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8872 "encoder's stage crtc doesn't match current crtc\n");
8873 WARN(encoder->connectors_active && !encoder->base.crtc,
8874 "encoder's active_connectors set, but no crtc\n");
8875
8876 list_for_each_entry(connector, &dev->mode_config.connector_list,
8877 base.head) {
8878 if (connector->base.encoder != &encoder->base)
8879 continue;
8880 enabled = true;
8881 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8882 active = true;
8883 }
8884 WARN(!!encoder->base.crtc != enabled,
8885 "encoder's enabled state mismatch "
8886 "(expected %i, found %i)\n",
8887 !!encoder->base.crtc, enabled);
8888 WARN(active && !encoder->base.crtc,
8889 "active encoder with no crtc\n");
8890
8891 WARN(encoder->connectors_active != active,
8892 "encoder's computed active state doesn't match tracked active state "
8893 "(expected %i, found %i)\n", active, encoder->connectors_active);
8894
8895 active = encoder->get_hw_state(encoder, &pipe);
8896 WARN(active != encoder->connectors_active,
8897 "encoder's hw state doesn't match sw tracking "
8898 "(expected %i, found %i)\n",
8899 encoder->connectors_active, active);
8900
8901 if (!encoder->base.crtc)
8902 continue;
8903
8904 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8905 WARN(active && pipe != tracked_pipe,
8906 "active encoder's pipe doesn't match"
8907 "(expected %i, found %i)\n",
8908 tracked_pipe, pipe);
8909
8910 }
91d1b4bd
DV		 8911}
8912
8913static void
8914check_crtc_state(struct drm_device *dev)
8915{
8916 drm_i915_private_t *dev_priv = dev->dev_private;
8917 struct intel_crtc *crtc;
8918 struct intel_encoder *encoder;
8919 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8920
8921 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8922 base.head) {
8923 bool enabled = false;
8924 bool active = false;
8925
045ac3b5
JB		 8926 memset(&pipe_config, 0, sizeof(pipe_config));
8927
8af6cf88
DV		 8928 DRM_DEBUG_KMS("[CRTC:%d]\n",
8929 crtc->base.base.id);
8930
8931 WARN(crtc->active && !crtc->base.enabled,
8932 "active crtc, but not enabled in sw tracking\n");
8933
8934 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8935 base.head) {
8936 if (encoder->base.crtc != &crtc->base)
8937 continue;
8938 enabled = true;
8939 if (encoder->connectors_active)
8940 active = true;
8941 }
6c49f241 8942
8af6cf88
DV		 8943 WARN(active != crtc->active,
8944 "crtc's computed active state doesn't match tracked active state "
8945 "(expected %i, found %i)\n", active, crtc->active);
8946 WARN(enabled != crtc->base.enabled,
8947 "crtc's computed enabled state doesn't match tracked enabled state "
8948 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8949
0e8ffe1b
DV		 8950 active = dev_priv->display.get_pipe_config(crtc,
8951 &pipe_config);
d62cf62a
DV		 8952
8953 /* hw state is inconsistent with the pipe A quirk */
8954 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8955 active = crtc->active;
8956
6c49f241
DV		 8957 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8958 base.head) {
3eaba51c 8959 enum pipe pipe;
6c49f241
DV		 8960 if (encoder->base.crtc != &crtc->base)
8961 continue;
3eaba51c
VS		 8962 if (encoder->get_config &&
8963 encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 8964 encoder->get_config(encoder, &pipe_config);
8965 }
8966
0e8ffe1b
DV		 8967 WARN(crtc->active != active,
8968 "crtc active state doesn't match with hw state "
8969 "(expected %i, found %i)\n", crtc->active, active);
8970
c0b03411
DV		 8971 if (active &&
8972 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8973 WARN(1, "pipe state doesn't match!\n");
8974 intel_dump_pipe_config(crtc, &pipe_config,
8975 "[hw state]");
8976 intel_dump_pipe_config(crtc, &crtc->config,
8977 "[sw state]");
8978 }
8af6cf88
DV		 8979 }
8980}
8981
91d1b4bd
DV		 8982static void
8983check_shared_dpll_state(struct drm_device *dev)
8984{
8985 drm_i915_private_t *dev_priv = dev->dev_private;
8986 struct intel_crtc *crtc;
8987 struct intel_dpll_hw_state dpll_hw_state;
8988 int i;
5358901f
DV		 8989
8990 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8991 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8992 int enabled_crtcs = 0, active_crtcs = 0;
8993 bool active;
8994
8995 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8996
8997 DRM_DEBUG_KMS("%s\n", pll->name);
8998
8999 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9000
9001 WARN(pll->active > pll->refcount,
9002 "more active pll users than references: %i vs %i\n",
9003 pll->active, pll->refcount);
9004 WARN(pll->active && !pll->on,
9005 "pll in active use but not on in sw tracking\n");
35c95375
DV		 9006 WARN(pll->on && !pll->active,
9007 "pll in on but not on in use in sw tracking\n");
5358901f
DV		 9008 WARN(pll->on != active,
9009 "pll on state mismatch (expected %i, found %i)\n",
9010 pll->on, active);
9011
9012 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9013 base.head) {
9014 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9015 enabled_crtcs++;
9016 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9017 active_crtcs++;
9018 }
9019 WARN(pll->active != active_crtcs,
9020 "pll active crtcs mismatch (expected %i, found %i)\n",
9021 pll->active, active_crtcs);
9022 WARN(pll->refcount != enabled_crtcs,
9023 "pll enabled crtcs mismatch (expected %i, found %i)\n",
9024 pll->refcount, enabled_crtcs);
66e985c0
DV		 9025
9026 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9027 sizeof(dpll_hw_state)),
9028 "pll hw state mismatch\n");
5358901f 9029 }
8af6cf88
DV		 9030}
9031
91d1b4bd
DV		 9032void
9033intel_modeset_check_state(struct drm_device *dev)
9034{
9035 check_connector_state(dev);
9036 check_encoder_state(dev);
9037 check_crtc_state(dev);
9038 check_shared_dpll_state(dev);
9039}
9040
18442d08
VS		 9041void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9042 int dotclock)
9043{
9044 /*
9045 * FDI already provided one idea for the dotclock.
9046 * Yell if the encoder disagrees.
9047 */
241bfc38 9048 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
18442d08 9049 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
241bfc38 9050 pipe_config->adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 9051}
9052
f30da187
DV		 9053static int __intel_set_mode(struct drm_crtc *crtc,
9054 struct drm_display_mode *mode,
9055 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 9056{
9057 struct drm_device *dev = crtc->dev;
dbf2b54e 9058 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 9059 struct drm_display_mode *saved_mode, *saved_hwmode;
9060 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 9061 struct intel_crtc *intel_crtc;
9062 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 9063 int ret = 0;
a6778b3c 9064
a1e22653 9065 saved_mode = kcalloc(2, sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 9066 if (!saved_mode)
9067 return -ENOMEM;
3ac18232 9068 saved_hwmode = saved_mode + 1;
a6778b3c 9069
e2e1ed41 9070 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 9071 &prepare_pipes, &disable_pipes);
9072
3ac18232
TG		 9073 *saved_hwmode = crtc->hwmode;
9074 *saved_mode = crtc->mode;
a6778b3c 9075
25c5b266
DV		 9076 /* Hack: Because we don't (yet) support global modeset on multiple
9077 * crtcs, we don't keep track of the new mode for more than one crtc.
9078 * Hence simply check whether any bit is set in modeset_pipes in all the
9079 * pieces of code that are not yet converted to deal with mutliple crtcs
9080 * changing their mode at the same time. */
25c5b266 9081 if (modeset_pipes) {
4e53c2e0 9082 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 9083 if (IS_ERR(pipe_config)) {
9084 ret = PTR_ERR(pipe_config);
9085 pipe_config = NULL;
9086
3ac18232 9087 goto out;
25c5b266 9088 }
c0b03411
DV		 9089 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9090 "[modeset]");
25c5b266 9091 }
a6778b3c 9092
460da916
DV		 9093 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9094 intel_crtc_disable(&intel_crtc->base);
9095
ea9d758d
DV		 9096 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9097 if (intel_crtc->base.enabled)
9098 dev_priv->display.crtc_disable(&intel_crtc->base);
9099 }
a6778b3c 9100
6c4c86f5
DV		 9101 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9102 * to set it here already despite that we pass it down the callchain.
f6e5b160 9103 */
b8cecdf5 9104 if (modeset_pipes) {
25c5b266 9105 crtc->mode = *mode;
b8cecdf5
DV		 9106 /* mode_set/enable/disable functions rely on a correct pipe
9107 * config. */
9108 to_intel_crtc(crtc)->config = *pipe_config;
9109 }
7758a113 9110
ea9d758d
DV		 9111 /* Only after disabling all output pipelines that will be changed can we
9112 * update the the output configuration. */
9113 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 9114
47fab737
DV		 9115 if (dev_priv->display.modeset_global_resources)
9116 dev_priv->display.modeset_global_resources(dev);
9117
a6778b3c
DV		 9118 /* Set up the DPLL and any encoders state that needs to adjust or depend
9119 * on the DPLL.
f6e5b160 9120 */
25c5b266 9121 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 9122 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 9123 x, y, fb);
9124 if (ret)
9125 goto done;
a6778b3c
DV		 9126 }
9127
9128 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 9129 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9130 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 9131
25c5b266
DV		 9132 if (modeset_pipes) {
9133 /* Store real post-adjustment hardware mode. */
b8cecdf5 9134 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 9135
25c5b266
DV		 9136 /* Calculate and store various constants which
9137 * are later needed by vblank and swap-completion
9138 * timestamping. They are derived from true hwmode.
9139 */
9140 drm_calc_timestamping_constants(crtc);
9141 }
a6778b3c
DV		 9142
9143 /* FIXME: add subpixel order */
9144done:
c0c36b94 9145 if (ret && crtc->enabled) {
3ac18232
TG		 9146 crtc->hwmode = *saved_hwmode;
9147 crtc->mode = *saved_mode;
a6778b3c
DV		 9148 }
9149
3ac18232 9150out:
b8cecdf5 9151 kfree(pipe_config);
3ac18232 9152 kfree(saved_mode);
a6778b3c 9153 return ret;
f6e5b160
CW		 9154}
9155
e7457a9a
DL		 9156static int intel_set_mode(struct drm_crtc *crtc,
9157 struct drm_display_mode *mode,
9158 int x, int y, struct drm_framebuffer *fb)
f30da187
DV		 9159{
9160 int ret;
9161
9162 ret = __intel_set_mode(crtc, mode, x, y, fb);
9163
9164 if (ret == 0)
9165 intel_modeset_check_state(crtc->dev);
9166
9167 return ret;
9168}
9169
c0c36b94
CW		 9170void intel_crtc_restore_mode(struct drm_crtc *crtc)
9171{
9172 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9173}
9174
25c5b266
DV		 9175#undef for_each_intel_crtc_masked
9176
d9e55608
DV		 9177static void intel_set_config_free(struct intel_set_config *config)
9178{
9179 if (!config)
9180 return;
9181
1aa4b628
DV		 9182 kfree(config->save_connector_encoders);
9183 kfree(config->save_encoder_crtcs);
d9e55608
DV		 9184 kfree(config);
9185}
9186
85f9eb71
DV		 9187static int intel_set_config_save_state(struct drm_device *dev,
9188 struct intel_set_config *config)
9189{
85f9eb71
DV		 9190 struct drm_encoder *encoder;
9191 struct drm_connector *connector;
9192 int count;
9193
1aa4b628
DV		 9194 config->save_encoder_crtcs =
9195 kcalloc(dev->mode_config.num_encoder,
9196 sizeof(struct drm_crtc *), GFP_KERNEL);
9197 if (!config->save_encoder_crtcs)
85f9eb71
DV		 9198 return -ENOMEM;
9199
1aa4b628
DV		 9200 config->save_connector_encoders =
9201 kcalloc(dev->mode_config.num_connector,
9202 sizeof(struct drm_encoder *), GFP_KERNEL);
9203 if (!config->save_connector_encoders)
85f9eb71
DV		 9204 return -ENOMEM;
9205
9206 /* Copy data. Note that driver private data is not affected.
9207 * Should anything bad happen only the expected state is
9208 * restored, not the drivers personal bookkeeping.
9209 */
85f9eb71
DV		 9210 count = 0;
9211 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 9212 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 9213 }
9214
9215 count = 0;
9216 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 9217 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 9218 }
9219
9220 return 0;
9221}
9222
9223static void intel_set_config_restore_state(struct drm_device *dev,
9224 struct intel_set_config *config)
9225{
9a935856
DV		 9226 struct intel_encoder *encoder;
9227 struct intel_connector *connector;
85f9eb71
DV		 9228 int count;
9229
85f9eb71 9230 count = 0;
9a935856
DV		 9231 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9232 encoder->new_crtc =
9233 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 9234 }
9235
9236 count = 0;
9a935856
DV		 9237 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9238 connector->new_encoder =
9239 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 9240 }
9241}
9242
e3de42b6 9243static bool
2e57f47d 9244is_crtc_connector_off(struct drm_mode_set *set)
e3de42b6
ID		 9245{
9246 int i;
9247
2e57f47d
CW		 9248 if (set->num_connectors == 0)
9249 return false;
9250
9251 if (WARN_ON(set->connectors == NULL))
9252 return false;
9253
9254 for (i = 0; i < set->num_connectors; i++)
9255 if (set->connectors[i]->encoder &&
9256 set->connectors[i]->encoder->crtc == set->crtc &&
9257 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
e3de42b6
ID		 9258 return true;
9259
9260 return false;
9261}
9262
5e2b584e
DV		 9263static void
9264intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9265 struct intel_set_config *config)
9266{
9267
9268 /* We should be able to check here if the fb has the same properties
9269 * and then just flip_or_move it */
2e57f47d
CW		 9270 if (is_crtc_connector_off(set)) {
9271 config->mode_changed = true;
e3de42b6 9272 } else if (set->crtc->fb != set->fb) {
5e2b584e
DV		 9273 /* If we have no fb then treat it as a full mode set */
9274 if (set->crtc->fb == NULL) {
319d9827
JB		 9275 struct intel_crtc *intel_crtc =
9276 to_intel_crtc(set->crtc);
9277
9278 if (intel_crtc->active && i915_fastboot) {
9279 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9280 config->fb_changed = true;
9281 } else {
9282 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9283 config->mode_changed = true;
9284 }
5e2b584e
DV		 9285 } else if (set->fb == NULL) {
9286 config->mode_changed = true;
72f4901e
DV		 9287 } else if (set->fb->pixel_format !=
9288 set->crtc->fb->pixel_format) {
5e2b584e 9289 config->mode_changed = true;
e3de42b6 9290 } else {
5e2b584e 9291 config->fb_changed = true;
e3de42b6 9292 }
5e2b584e
DV		 9293 }
9294
835c5873 9295 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 9296 config->fb_changed = true;
9297
9298 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9299 DRM_DEBUG_KMS("modes are different, full mode set\n");
9300 drm_mode_debug_printmodeline(&set->crtc->mode);
9301 drm_mode_debug_printmodeline(set->mode);
9302 config->mode_changed = true;
9303 }
a1d95703
CW		 9304
9305 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9306 set->crtc->base.id, config->mode_changed, config->fb_changed);
5e2b584e
DV		 9307}
9308
2e431051 9309static int
9a935856
DV		 9310intel_modeset_stage_output_state(struct drm_device *dev,
9311 struct drm_mode_set *set,
9312 struct intel_set_config *config)
50f56119 9313{
85f9eb71 9314 struct drm_crtc *new_crtc;
9a935856
DV		 9315 struct intel_connector *connector;
9316 struct intel_encoder *encoder;
f3f08572 9317 int ro;
50f56119 9318
9abdda74 9319 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 9320 * of connectors. For paranoia, double-check this. */
9321 WARN_ON(!set->fb && (set->num_connectors != 0));
9322 WARN_ON(set->fb && (set->num_connectors == 0));
9323
9a935856
DV		 9324 list_for_each_entry(connector, &dev->mode_config.connector_list,
9325 base.head) {
9326 /* Otherwise traverse passed in connector list and get encoders
9327 * for them. */
50f56119 9328 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 9329 if (set->connectors[ro] == &connector->base) {
9330 connector->new_encoder = connector->encoder;
50f56119
DV		 9331 break;
9332 }
9333 }
9334
9a935856
DV		 9335 /* If we disable the crtc, disable all its connectors. Also, if
9336 * the connector is on the changing crtc but not on the new
9337 * connector list, disable it. */
9338 if ((!set->fb || ro == set->num_connectors) &&
9339 connector->base.encoder &&
9340 connector->base.encoder->crtc == set->crtc) {
9341 connector->new_encoder = NULL;
9342
9343 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9344 connector->base.base.id,
9345 drm_get_connector_name(&connector->base));
9346 }
9347
9348
9349 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 9350 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 9351 config->mode_changed = true;
50f56119
DV		 9352 }
9353 }
9a935856 9354 /* connector->new_encoder is now updated for all connectors. */
50f56119 9355
9a935856 9356 /* Update crtc of enabled connectors. */
9a935856
DV		 9357 list_for_each_entry(connector, &dev->mode_config.connector_list,
9358 base.head) {
9359 if (!connector->new_encoder)
50f56119
DV		 9360 continue;
9361
9a935856 9362 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 9363
9364 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 9365 if (set->connectors[ro] == &connector->base)
50f56119
DV		 9366 new_crtc = set->crtc;
9367 }
9368
9369 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 9370 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9371 new_crtc)) {
5e2b584e 9372 return -EINVAL;
50f56119 9373 }
9a935856
DV		 9374 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9375
9376 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9377 connector->base.base.id,
9378 drm_get_connector_name(&connector->base),
9379 new_crtc->base.id);
9380 }
9381
9382 /* Check for any encoders that needs to be disabled. */
9383 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9384 base.head) {
9385 list_for_each_entry(connector,
9386 &dev->mode_config.connector_list,
9387 base.head) {
9388 if (connector->new_encoder == encoder) {
9389 WARN_ON(!connector->new_encoder->new_crtc);
9390
9391 goto next_encoder;
9392 }
9393 }
9394 encoder->new_crtc = NULL;
9395next_encoder:
9396 /* Only now check for crtc changes so we don't miss encoders
9397 * that will be disabled. */
9398 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 9399 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 9400 config->mode_changed = true;
50f56119
DV		 9401 }
9402 }
9a935856 9403 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 9404
2e431051
DV		 9405 return 0;
9406}
9407
9408static int intel_crtc_set_config(struct drm_mode_set *set)
9409{
9410 struct drm_device *dev;
2e431051
DV		 9411 struct drm_mode_set save_set;
9412 struct intel_set_config *config;
9413 int ret;
2e431051 9414
8d3e375e
DV		 9415 BUG_ON(!set);
9416 BUG_ON(!set->crtc);
9417 BUG_ON(!set->crtc->helper_private);
2e431051 9418
7e53f3a4
DV		 9419 /* Enforce sane interface api - has been abused by the fb helper. */
9420 BUG_ON(!set->mode && set->fb);
9421 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 9422
2e431051
DV		 9423 if (set->fb) {
9424 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9425 set->crtc->base.id, set->fb->base.id,
9426 (int)set->num_connectors, set->x, set->y);
9427 } else {
9428 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 9429 }
9430
9431 dev = set->crtc->dev;
9432
9433 ret = -ENOMEM;
9434 config = kzalloc(sizeof(*config), GFP_KERNEL);
9435 if (!config)
9436 goto out_config;
9437
9438 ret = intel_set_config_save_state(dev, config);
9439 if (ret)
9440 goto out_config;
9441
9442 save_set.crtc = set->crtc;
9443 save_set.mode = &set->crtc->mode;
9444 save_set.x = set->crtc->x;
9445 save_set.y = set->crtc->y;
9446 save_set.fb = set->crtc->fb;
9447
9448 /* Compute whether we need a full modeset, only an fb base update or no
9449 * change at all. In the future we might also check whether only the
9450 * mode changed, e.g. for LVDS where we only change the panel fitter in
9451 * such cases. */
9452 intel_set_config_compute_mode_changes(set, config);
9453
9a935856 9454 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 9455 if (ret)
9456 goto fail;
9457
5e2b584e 9458 if (config->mode_changed) {
c0c36b94
CW		 9459 ret = intel_set_mode(set->crtc, set->mode,
9460 set->x, set->y, set->fb);
5e2b584e 9461 } else if (config->fb_changed) {
4878cae2
VS		 9462 intel_crtc_wait_for_pending_flips(set->crtc);
9463
4f660f49 9464 ret = intel_pipe_set_base(set->crtc,
94352cf9 9465 set->x, set->y, set->fb);
50f56119
DV		 9466 }
9467
2d05eae1 9468 if (ret) {
bf67dfeb
DV		 9469 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9470 set->crtc->base.id, ret);
50f56119 9471fail:
2d05eae1 9472 intel_set_config_restore_state(dev, config);
50f56119 9473
2d05eae1
CW		 9474 /* Try to restore the config */
9475 if (config->mode_changed &&
9476 intel_set_mode(save_set.crtc, save_set.mode,
9477 save_set.x, save_set.y, save_set.fb))
9478 DRM_ERROR("failed to restore config after modeset failure\n");
9479 }
50f56119 9480
d9e55608
DV		 9481out_config:
9482 intel_set_config_free(config);
50f56119
DV		 9483 return ret;
9484}
f6e5b160
CW		 9485
9486static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 9487 .cursor_set = intel_crtc_cursor_set,
9488 .cursor_move = intel_crtc_cursor_move,
9489 .gamma_set = intel_crtc_gamma_set,
50f56119 9490 .set_config = intel_crtc_set_config,
f6e5b160
CW		 9491 .destroy = intel_crtc_destroy,
9492 .page_flip = intel_crtc_page_flip,
9493};
9494
79f689aa
PZ		 9495static void intel_cpu_pll_init(struct drm_device *dev)
9496{
affa9354 9497 if (HAS_DDI(dev))
79f689aa
PZ		 9498 intel_ddi_pll_init(dev);
9499}
9500
5358901f
DV		 9501static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9502 struct intel_shared_dpll *pll,
9503 struct intel_dpll_hw_state *hw_state)
ee7b9f93 9504{
5358901f 9505 uint32_t val;
ee7b9f93 9506
5358901f 9507 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 9508 hw_state->dpll = val;
9509 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9510 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 9511
9512 return val & DPLL_VCO_ENABLE;
9513}
9514
15bdd4cf
DV		 9515static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9516 struct intel_shared_dpll *pll)
9517{
9518 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9519 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9520}
9521
e7b903d2
DV		 9522static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9523 struct intel_shared_dpll *pll)
9524{
e7b903d2
DV		 9525 /* PCH refclock must be enabled first */
9526 assert_pch_refclk_enabled(dev_priv);
9527
15bdd4cf
DV		 9528 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9529
9530 /* Wait for the clocks to stabilize. */
9531 POSTING_READ(PCH_DPLL(pll->id));
9532 udelay(150);
9533
9534 /* The pixel multiplier can only be updated once the
9535 * DPLL is enabled and the clocks are stable.
9536 *
9537 * So write it again.
9538 */
9539 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9540 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9541 udelay(200);
9542}
9543
9544static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9545 struct intel_shared_dpll *pll)
9546{
9547 struct drm_device *dev = dev_priv->dev;
9548 struct intel_crtc *crtc;
e7b903d2
DV		 9549
9550 /* Make sure no transcoder isn't still depending on us. */
9551 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9552 if (intel_crtc_to_shared_dpll(crtc) == pll)
9553 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 9554 }
9555
15bdd4cf
DV		 9556 I915_WRITE(PCH_DPLL(pll->id), 0);
9557 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9558 udelay(200);
9559}
9560
46edb027
DV		 9561static char *ibx_pch_dpll_names[] = {
9562 "PCH DPLL A",
9563 "PCH DPLL B",
9564};
9565
7c74ade1 9566static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 9567{
e7b903d2 9568 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 9569 int i;
9570
7c74ade1 9571 dev_priv->num_shared_dpll = 2;
ee7b9f93 9572
e72f9fbf 9573 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 9574 dev_priv->shared_dplls[i].id = i;
9575 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 9576 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 9577 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9578 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 9579 dev_priv->shared_dplls[i].get_hw_state =
9580 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 9581 }
9582}
9583
7c74ade1
DV		 9584static void intel_shared_dpll_init(struct drm_device *dev)
9585{
e7b903d2 9586 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1
DV		 9587
9588 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9589 ibx_pch_dpll_init(dev);
9590 else
9591 dev_priv->num_shared_dpll = 0;
9592
9593 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9594 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9595 dev_priv->num_shared_dpll);
9596}
9597
b358d0a6 9598static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 9599{
22fd0fab 9600 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 9601 struct intel_crtc *intel_crtc;
9602 int i;
9603
955382f3 9604 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 9605 if (intel_crtc == NULL)
9606 return;
9607
9608 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9609
9610 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 9611 for (i = 0; i < 256; i++) {
9612 intel_crtc->lut_r[i] = i;
9613 intel_crtc->lut_g[i] = i;
9614 intel_crtc->lut_b[i] = i;
9615 }
9616
80824003
JB		 9617 /* Swap pipes & planes for FBC on pre-965 */
9618 intel_crtc->pipe = pipe;
9619 intel_crtc->plane = pipe;
e2e767ab 9620 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 9621 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 9622 intel_crtc->plane = !pipe;
80824003
JB		 9623 }
9624
22fd0fab
JB		 9625 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9626 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9627 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9628 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9629
79e53945 9630 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 9631}
9632
08d7b3d1 9633int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 9634 struct drm_file *file)
08d7b3d1 9635{
08d7b3d1 9636 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 9637 struct drm_mode_object *drmmode_obj;
9638 struct intel_crtc *crtc;
08d7b3d1 9639
1cff8f6b
DV		 9640 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9641 return -ENODEV;
08d7b3d1 9642
c05422d5
DV		 9643 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9644 DRM_MODE_OBJECT_CRTC);
08d7b3d1 9645
c05422d5 9646 if (!drmmode_obj) {
08d7b3d1
CW		 9647 DRM_ERROR("no such CRTC id\n");
9648 return -EINVAL;
9649 }
9650
c05422d5
DV		 9651 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9652 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 9653
c05422d5 9654 return 0;
08d7b3d1
CW		 9655}
9656
66a9278e 9657static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 9658{
66a9278e
DV		 9659 struct drm_device *dev = encoder->base.dev;
9660 struct intel_encoder *source_encoder;
79e53945 9661 int index_mask = 0;
79e53945
JB		 9662 int entry = 0;
9663
66a9278e
DV		 9664 list_for_each_entry(source_encoder,
9665 &dev->mode_config.encoder_list, base.head) {
9666
9667 if (encoder == source_encoder)
79e53945 9668 index_mask |= (1 << entry);
66a9278e
DV		 9669
9670 /* Intel hw has only one MUX where enocoders could be cloned. */
9671 if (encoder->cloneable && source_encoder->cloneable)
9672 index_mask |= (1 << entry);
9673
79e53945
JB		 9674 entry++;
9675 }
4ef69c7a 9676
79e53945
JB		 9677 return index_mask;
9678}
9679
4d302442
CW		 9680static bool has_edp_a(struct drm_device *dev)
9681{
9682 struct drm_i915_private *dev_priv = dev->dev_private;
9683
9684 if (!IS_MOBILE(dev))
9685 return false;
9686
9687 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9688 return false;
9689
9690 if (IS_GEN5(dev) &&
9691 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9692 return false;
9693
9694 return true;
9695}
9696
79e53945
JB		 9697static void intel_setup_outputs(struct drm_device *dev)
9698{
725e30ad 9699 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 9700 struct intel_encoder *encoder;
cb0953d7 9701 bool dpd_is_edp = false;
79e53945 9702
c9093354 9703 intel_lvds_init(dev);
79e53945 9704
c40c0f5b 9705 if (!IS_ULT(dev))
79935fca 9706 intel_crt_init(dev);
cb0953d7 9707
affa9354 9708 if (HAS_DDI(dev)) {
0e72a5b5
ED		 9709 int found;
9710
9711 /* Haswell uses DDI functions to detect digital outputs */
9712 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9713 /* DDI A only supports eDP */
9714 if (found)
9715 intel_ddi_init(dev, PORT_A);
9716
9717 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9718 * register */
9719 found = I915_READ(SFUSE_STRAP);
9720
9721 if (found & SFUSE_STRAP_DDIB_DETECTED)
9722 intel_ddi_init(dev, PORT_B);
9723 if (found & SFUSE_STRAP_DDIC_DETECTED)
9724 intel_ddi_init(dev, PORT_C);
9725 if (found & SFUSE_STRAP_DDID_DETECTED)
9726 intel_ddi_init(dev, PORT_D);
9727 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 9728 int found;
270b3042
DV		 9729 dpd_is_edp = intel_dpd_is_edp(dev);
9730
9731 if (has_edp_a(dev))
9732 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 9733
dc0fa718 9734 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 9735 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 9736 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 9737 if (!found)
e2debe91 9738 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 9739 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 9740 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 9741 }
9742
dc0fa718 9743 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 9744 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 9745
dc0fa718 9746 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 9747 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 9748
5eb08b69 9749 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 9750 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 9751
270b3042 9752 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 9753 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 9754 } else if (IS_VALLEYVIEW(dev)) {
19c03924 9755 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
6f6005a5
JB		 9756 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9757 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9758 PORT_C);
9759 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9760 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9761 PORT_C);
9762 }
19c03924 9763
dc0fa718 9764 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 9765 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9766 PORT_B);
67cfc203
VS		 9767 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9768 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 9769 }
3cfca973
JN		 9770
9771 intel_dsi_init(dev);
103a196f 9772 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 9773 bool found = false;
7d57382e 9774
e2debe91 9775 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9776 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 9777 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 9778 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9779 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 9780 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 9781 }
27185ae1 9782
e7281eab 9783 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9784 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 9785 }
13520b05
KH		 9786
9787 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 9788
e2debe91 9789 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9790 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 9791 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 9792 }
27185ae1 9793
e2debe91 9794 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 9795
b01f2c3a
JB		 9796 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9797 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 9798 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 9799 }
e7281eab 9800 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9801 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 9802 }
27185ae1 9803
b01f2c3a 9804 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 9805 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 9806 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 9807 } else if (IS_GEN2(dev))
79e53945
JB		 9808 intel_dvo_init(dev);
9809
103a196f 9810 if (SUPPORTS_TV(dev))
79e53945
JB		 9811 intel_tv_init(dev);
9812
4ef69c7a
CW		 9813 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9814 encoder->base.possible_crtcs = encoder->crtc_mask;
9815 encoder->base.possible_clones =
66a9278e 9816 intel_encoder_clones(encoder);
79e53945 9817 }
47356eb6 9818
dde86e2d 9819 intel_init_pch_refclk(dev);
270b3042
DV		 9820
9821 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 9822}
9823
ddfe1567
CW		 9824void intel_framebuffer_fini(struct intel_framebuffer *fb)
9825{
9826 drm_framebuffer_cleanup(&fb->base);
9827 drm_gem_object_unreference_unlocked(&fb->obj->base);
9828}
9829
79e53945
JB		 9830static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9831{
9832 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 9833
ddfe1567 9834 intel_framebuffer_fini(intel_fb);
79e53945
JB		 9835 kfree(intel_fb);
9836}
9837
9838static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 9839 struct drm_file *file,
79e53945
JB		 9840 unsigned int *handle)
9841{
9842 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 9843 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 9844
05394f39 9845 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 9846}
9847
9848static const struct drm_framebuffer_funcs intel_fb_funcs = {
9849 .destroy = intel_user_framebuffer_destroy,
9850 .create_handle = intel_user_framebuffer_create_handle,
9851};
9852
38651674
DA		 9853int intel_framebuffer_init(struct drm_device *dev,
9854 struct intel_framebuffer *intel_fb,
308e5bcb 9855 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 9856 struct drm_i915_gem_object *obj)
79e53945 9857{
a35cdaa0 9858 int pitch_limit;
79e53945
JB		 9859 int ret;
9860
c16ed4be
CW		 9861 if (obj->tiling_mode == I915_TILING_Y) {
9862 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 9863 return -EINVAL;
c16ed4be 9864 }
57cd6508 9865
c16ed4be
CW		 9866 if (mode_cmd->pitches[0] & 63) {
9867 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9868 mode_cmd->pitches[0]);
57cd6508 9869 return -EINVAL;
c16ed4be 9870 }
57cd6508 9871
a35cdaa0
CW		 9872 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9873 pitch_limit = 32*1024;
9874 } else if (INTEL_INFO(dev)->gen >= 4) {
9875 if (obj->tiling_mode)
9876 pitch_limit = 16*1024;
9877 else
9878 pitch_limit = 32*1024;
9879 } else if (INTEL_INFO(dev)->gen >= 3) {
9880 if (obj->tiling_mode)
9881 pitch_limit = 8*1024;
9882 else
9883 pitch_limit = 16*1024;
9884 } else
9885 /* XXX DSPC is limited to 4k tiled */
9886 pitch_limit = 8*1024;
9887
9888 if (mode_cmd->pitches[0] > pitch_limit) {
9889 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9890 obj->tiling_mode ? "tiled" : "linear",
9891 mode_cmd->pitches[0], pitch_limit);
5d7bd705 9892 return -EINVAL;
c16ed4be 9893 }
5d7bd705
VS		 9894
9895 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 9896 mode_cmd->pitches[0] != obj->stride) {
9897 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9898 mode_cmd->pitches[0], obj->stride);
5d7bd705 9899 return -EINVAL;
c16ed4be 9900 }
5d7bd705 9901
57779d06 9902 /* Reject formats not supported by any plane early. */
308e5bcb 9903 switch (mode_cmd->pixel_format) {
57779d06 9904 case DRM_FORMAT_C8:
04b3924d
VS		 9905 case DRM_FORMAT_RGB565:
9906 case DRM_FORMAT_XRGB8888:
9907 case DRM_FORMAT_ARGB8888:
57779d06
VS		 9908 break;
9909 case DRM_FORMAT_XRGB1555:
9910 case DRM_FORMAT_ARGB1555:
c16ed4be 9911 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 9912 DRM_DEBUG("unsupported pixel format: %s\n",
9913 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9914 return -EINVAL;
c16ed4be 9915 }
57779d06
VS		 9916 break;
9917 case DRM_FORMAT_XBGR8888:
9918 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 9919 case DRM_FORMAT_XRGB2101010:
9920 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 9921 case DRM_FORMAT_XBGR2101010:
9922 case DRM_FORMAT_ABGR2101010:
c16ed4be 9923 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 9924 DRM_DEBUG("unsupported pixel format: %s\n",
9925 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9926 return -EINVAL;
c16ed4be 9927 }
b5626747 9928 break;
04b3924d
VS		 9929 case DRM_FORMAT_YUYV:
9930 case DRM_FORMAT_UYVY:
9931 case DRM_FORMAT_YVYU:
9932 case DRM_FORMAT_VYUY:
c16ed4be 9933 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 9934 DRM_DEBUG("unsupported pixel format: %s\n",
9935 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9936 return -EINVAL;
c16ed4be 9937 }
57cd6508
CW		 9938 break;
9939 default:
4ee62c76
VS		 9940 DRM_DEBUG("unsupported pixel format: %s\n",
9941 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 9942 return -EINVAL;
9943 }
9944
90f9a336
VS		 9945 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9946 if (mode_cmd->offsets[0] != 0)
9947 return -EINVAL;
9948
c7d73f6a
DV		 9949 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9950 intel_fb->obj = obj;
9951
79e53945
JB		 9952 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9953 if (ret) {
9954 DRM_ERROR("framebuffer init failed %d\n", ret);
9955 return ret;
9956 }
9957
79e53945
JB		 9958 return 0;
9959}
9960
79e53945
JB		 9961static struct drm_framebuffer *
9962intel_user_framebuffer_create(struct drm_device *dev,
9963 struct drm_file *filp,
308e5bcb 9964 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 9965{
05394f39 9966 struct drm_i915_gem_object *obj;
79e53945 9967
308e5bcb
JB		 9968 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9969 mode_cmd->handles[0]));
c8725226 9970 if (&obj->base == NULL)
cce13ff7 9971 return ERR_PTR(-ENOENT);
79e53945 9972
d2dff872 9973 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 9974}
9975
79e53945 9976static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 9977 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 9978 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 9979};
9980
e70236a8
JB		 9981/* Set up chip specific display functions */
9982static void intel_init_display(struct drm_device *dev)
9983{
9984 struct drm_i915_private *dev_priv = dev->dev_private;
9985
ee9300bb
DV		 9986 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9987 dev_priv->display.find_dpll = g4x_find_best_dpll;
9988 else if (IS_VALLEYVIEW(dev))
9989 dev_priv->display.find_dpll = vlv_find_best_dpll;
9990 else if (IS_PINEVIEW(dev))
9991 dev_priv->display.find_dpll = pnv_find_best_dpll;
9992 else
9993 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9994
affa9354 9995 if (HAS_DDI(dev)) {
0e8ffe1b 9996 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 9997 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 9998 dev_priv->display.crtc_enable = haswell_crtc_enable;
9999 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 10000 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 10001 dev_priv->display.update_plane = ironlake_update_plane;
10002 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 10003 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 10004 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 10005 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10006 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 10007 dev_priv->display.off = ironlake_crtc_off;
17638cd6 10008 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 10009 } else if (IS_VALLEYVIEW(dev)) {
10010 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10011 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10012 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10013 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10014 dev_priv->display.off = i9xx_crtc_off;
10015 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 10016 } else {
0e8ffe1b 10017 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 10018 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 10019 dev_priv->display.crtc_enable = i9xx_crtc_enable;
10020 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 10021 dev_priv->display.off = i9xx_crtc_off;
17638cd6 10022 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 10023 }
e70236a8 10024
e70236a8 10025 /* Returns the core display clock speed */
25eb05fc
JB		 10026 if (IS_VALLEYVIEW(dev))
10027 dev_priv->display.get_display_clock_speed =
10028 valleyview_get_display_clock_speed;
10029 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 10030 dev_priv->display.get_display_clock_speed =
10031 i945_get_display_clock_speed;
10032 else if (IS_I915G(dev))
10033 dev_priv->display.get_display_clock_speed =
10034 i915_get_display_clock_speed;
257a7ffc 10035 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 10036 dev_priv->display.get_display_clock_speed =
10037 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 10038 else if (IS_PINEVIEW(dev))
10039 dev_priv->display.get_display_clock_speed =
10040 pnv_get_display_clock_speed;
e70236a8
JB		 10041 else if (IS_I915GM(dev))
10042 dev_priv->display.get_display_clock_speed =
10043 i915gm_get_display_clock_speed;
10044 else if (IS_I865G(dev))
10045 dev_priv->display.get_display_clock_speed =
10046 i865_get_display_clock_speed;
f0f8a9ce 10047 else if (IS_I85X(dev))
e70236a8
JB		 10048 dev_priv->display.get_display_clock_speed =
10049 i855_get_display_clock_speed;
10050 else /* 852, 830 */
10051 dev_priv->display.get_display_clock_speed =
10052 i830_get_display_clock_speed;
10053
7f8a8569 10054 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 10055 if (IS_GEN5(dev)) {
674cf967 10056 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 10057 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 10058 } else if (IS_GEN6(dev)) {
674cf967 10059 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 10060 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 10061 } else if (IS_IVYBRIDGE(dev)) {
10062 /* FIXME: detect B0+ stepping and use auto training */
10063 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 10064 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 10065 dev_priv->display.modeset_global_resources =
10066 ivb_modeset_global_resources;
c82e4d26
ED		 10067 } else if (IS_HASWELL(dev)) {
10068 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 10069 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 10070 dev_priv->display.modeset_global_resources =
10071 haswell_modeset_global_resources;
a0e63c22 10072 }
6067aaea 10073 } else if (IS_G4X(dev)) {
e0dac65e 10074 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 10075 }
8c9f3aaf
JB		 10076
10077 /* Default just returns -ENODEV to indicate unsupported */
10078 dev_priv->display.queue_flip = intel_default_queue_flip;
10079
10080 switch (INTEL_INFO(dev)->gen) {
10081 case 2:
10082 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10083 break;
10084
10085 case 3:
10086 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10087 break;
10088
10089 case 4:
10090 case 5:
10091 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10092 break;
10093
10094 case 6:
10095 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10096 break;
7c9017e5
JB		 10097 case 7:
10098 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10099 break;
8c9f3aaf 10100 }
e70236a8
JB		 10101}
10102
b690e96c
JB		 10103/*
10104 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10105 * resume, or other times. This quirk makes sure that's the case for
10106 * affected systems.
10107 */
0206e353 10108static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 10109{
10110 struct drm_i915_private *dev_priv = dev->dev_private;
10111
10112 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 10113 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 10114}
10115
435793df
KP		 10116/*
10117 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10118 */
10119static void quirk_ssc_force_disable(struct drm_device *dev)
10120{
10121 struct drm_i915_private *dev_priv = dev->dev_private;
10122 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 10123 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 10124}
10125
4dca20ef 10126/*
5a15ab5b
CE		 10127 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10128 * brightness value
4dca20ef
CE		 10129 */
10130static void quirk_invert_brightness(struct drm_device *dev)
10131{
10132 struct drm_i915_private *dev_priv = dev->dev_private;
10133 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 10134 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 10135}
10136
e85843be
KM		 10137/*
10138 * Some machines (Dell XPS13) suffer broken backlight controls if
10139 * BLM_PCH_PWM_ENABLE is set.
10140 */
10141static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
10142{
10143 struct drm_i915_private *dev_priv = dev->dev_private;
10144 dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
10145 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10146}
10147
b690e96c
JB		 10148struct intel_quirk {
10149 int device;
10150 int subsystem_vendor;
10151 int subsystem_device;
10152 void (*hook)(struct drm_device *dev);
10153};
10154
5f85f176
EE		 10155/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10156struct intel_dmi_quirk {
10157 void (*hook)(struct drm_device *dev);
10158 const struct dmi_system_id (*dmi_id_list)[];
10159};
10160
10161static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10162{
10163 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10164 return 1;
10165}
10166
10167static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10168 {
10169 .dmi_id_list = &(const struct dmi_system_id[]) {
10170 {
10171 .callback = intel_dmi_reverse_brightness,
10172 .ident = "NCR Corporation",
10173 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10174 DMI_MATCH(DMI_PRODUCT_NAME, ""),
10175 },
10176 },
10177 { } /* terminating entry */
10178 },
10179 .hook = quirk_invert_brightness,
10180 },
10181};
10182
c43b5634 10183static struct intel_quirk intel_quirks[] = {
b690e96c 10184 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 10185 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 10186
b690e96c
JB		 10187 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10188 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10189
b690e96c
JB		 10190 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10191 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10192
ccd0d36e 10193 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 10194 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 10195 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 10196
10197 /* Lenovo U160 cannot use SSC on LVDS */
10198 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 10199
10200 /* Sony Vaio Y cannot use SSC on LVDS */
10201 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 10202
ee1452d7
JN		 10203 /*
10204 * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
10205 * seem to use inverted backlight PWM.
10206 */
10207 { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness },
e85843be
KM		 10208
10209 /* Dell XPS13 HD Sandy Bridge */
10210 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10211 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10212 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
b690e96c
JB		 10213};
10214
10215static void intel_init_quirks(struct drm_device *dev)
10216{
10217 struct pci_dev *d = dev->pdev;
10218 int i;
10219
10220 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10221 struct intel_quirk *q = &intel_quirks[i];
10222
10223 if (d->device == q->device &&
10224 (d->subsystem_vendor == q->subsystem_vendor ||
10225 q->subsystem_vendor == PCI_ANY_ID) &&
10226 (d->subsystem_device == q->subsystem_device ||
10227 q->subsystem_device == PCI_ANY_ID))
10228 q->hook(dev);
10229 }
5f85f176
EE		 10230 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10231 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10232 intel_dmi_quirks[i].hook(dev);
10233 }
b690e96c
JB		 10234}
10235
9cce37f4
JB		 10236/* Disable the VGA plane that we never use */
10237static void i915_disable_vga(struct drm_device *dev)
10238{
10239 struct drm_i915_private *dev_priv = dev->dev_private;
10240 u8 sr1;
766aa1c4 10241 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 10242
10243 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 10244 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 10245 sr1 = inb(VGA_SR_DATA);
10246 outb(sr1 | 1<<5, VGA_SR_DATA);
10247 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10248 udelay(300);
10249
10250 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10251 POSTING_READ(vga_reg);
10252}
10253
6e1b4fda 10254static void i915_enable_vga_mem(struct drm_device *dev)
81b5c7bc
AW		 10255{
10256 /* Enable VGA memory on Intel HD */
10257 if (HAS_PCH_SPLIT(dev)) {
10258 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10259 outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10260 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10261 VGA_RSRC_LEGACY_MEM |
10262 VGA_RSRC_NORMAL_IO |
10263 VGA_RSRC_NORMAL_MEM);
10264 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10265 }
10266}
10267
6e1b4fda
VS		 10268void i915_disable_vga_mem(struct drm_device *dev)
10269{
10270 /* Disable VGA memory on Intel HD */
10271 if (HAS_PCH_SPLIT(dev)) {
10272 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10273 outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10274 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10275 VGA_RSRC_NORMAL_IO |
10276 VGA_RSRC_NORMAL_MEM);
10277 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10278 }
10279}
10280
f817586c
DV		 10281void intel_modeset_init_hw(struct drm_device *dev)
10282{
a8f78b58
ED		 10283 intel_prepare_ddi(dev);
10284
f817586c
DV		 10285 intel_init_clock_gating(dev);
10286
79f5b2c7 10287 mutex_lock(&dev->struct_mutex);
8090c6b9 10288 intel_enable_gt_powersave(dev);
79f5b2c7 10289 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 10290}
10291
7d708ee4
ID		 10292void intel_modeset_suspend_hw(struct drm_device *dev)
10293{
10294 intel_suspend_hw(dev);
10295}
10296
79e53945
JB		 10297void intel_modeset_init(struct drm_device *dev)
10298{
652c393a 10299 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 10300 int i, j, ret;
79e53945
JB		 10301
10302 drm_mode_config_init(dev);
10303
10304 dev->mode_config.min_width = 0;
10305 dev->mode_config.min_height = 0;
10306
019d96cb
DA		 10307 dev->mode_config.preferred_depth = 24;
10308 dev->mode_config.prefer_shadow = 1;
10309
e6ecefaa 10310 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 10311
b690e96c
JB		 10312 intel_init_quirks(dev);
10313
1fa61106
ED		 10314 intel_init_pm(dev);
10315
e3c74757
BW		 10316 if (INTEL_INFO(dev)->num_pipes == 0)
10317 return;
10318
e70236a8
JB		 10319 intel_init_display(dev);
10320
a6c45cf0
CW		 10321 if (IS_GEN2(dev)) {
10322 dev->mode_config.max_width = 2048;
10323 dev->mode_config.max_height = 2048;
10324 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 10325 dev->mode_config.max_width = 4096;
10326 dev->mode_config.max_height = 4096;
79e53945 10327 } else {
a6c45cf0
CW		 10328 dev->mode_config.max_width = 8192;
10329 dev->mode_config.max_height = 8192;
79e53945 10330 }
5d4545ae 10331 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 10332
28c97730 10333 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 10334 INTEL_INFO(dev)->num_pipes,
10335 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 10336
08e2a7de 10337 for_each_pipe(i) {
79e53945 10338 intel_crtc_init(dev, i);
7f1f3851
JB		 10339 for (j = 0; j < dev_priv->num_plane; j++) {
10340 ret = intel_plane_init(dev, i, j);
10341 if (ret)
06da8da2
VS		 10342 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10343 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 10344 }
79e53945
JB		 10345 }
10346
79f689aa 10347 intel_cpu_pll_init(dev);
e72f9fbf 10348 intel_shared_dpll_init(dev);
ee7b9f93 10349
9cce37f4
JB		 10350 /* Just disable it once at startup */
10351 i915_disable_vga(dev);
79e53945 10352 intel_setup_outputs(dev);
11be49eb
CW		 10353
10354 /* Just in case the BIOS is doing something questionable. */
10355 intel_disable_fbc(dev);
2c7111db
CW		 10356}
10357
24929352
DV		 10358static void
10359intel_connector_break_all_links(struct intel_connector *connector)
10360{
10361 connector->base.dpms = DRM_MODE_DPMS_OFF;
10362 connector->base.encoder = NULL;
10363 connector->encoder->connectors_active = false;
10364 connector->encoder->base.crtc = NULL;
10365}
10366
7fad798e
DV		 10367static void intel_enable_pipe_a(struct drm_device *dev)
10368{
10369 struct intel_connector *connector;
10370 struct drm_connector *crt = NULL;
10371 struct intel_load_detect_pipe load_detect_temp;
10372
10373 /* We can't just switch on the pipe A, we need to set things up with a
10374 * proper mode and output configuration. As a gross hack, enable pipe A
10375 * by enabling the load detect pipe once. */
10376 list_for_each_entry(connector,
10377 &dev->mode_config.connector_list,
10378 base.head) {
10379 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10380 crt = &connector->base;
10381 break;
10382 }
10383 }
10384
10385 if (!crt)
10386 return;
10387
10388 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10389 intel_release_load_detect_pipe(crt, &load_detect_temp);
10390
652c393a 10391
7fad798e
DV		 10392}
10393
fa555837
DV		 10394static bool
10395intel_check_plane_mapping(struct intel_crtc *crtc)
10396{
7eb552ae
BW		 10397 struct drm_device *dev = crtc->base.dev;
10398 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 10399 u32 reg, val;
10400
7eb552ae 10401 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 10402 return true;
10403
10404 reg = DSPCNTR(!crtc->plane);
10405 val = I915_READ(reg);
10406
10407 if ((val & DISPLAY_PLANE_ENABLE) &&
10408 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10409 return false;
10410
10411 return true;
10412}
10413
24929352
DV		 10414static void intel_sanitize_crtc(struct intel_crtc *crtc)
10415{
10416 struct drm_device *dev = crtc->base.dev;
10417 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 10418 u32 reg;
24929352 10419
24929352 10420 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 10421 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 10422 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10423
10424 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 10425 * disable the crtc (and hence change the state) if it is wrong. Note
10426 * that gen4+ has a fixed plane -> pipe mapping. */
10427 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 10428 struct intel_connector *connector;
10429 bool plane;
10430
24929352
DV		 10431 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10432 crtc->base.base.id);
10433
10434 /* Pipe has the wrong plane attached and the plane is active.
10435 * Temporarily change the plane mapping and disable everything
10436 * ... */
10437 plane = crtc->plane;
10438 crtc->plane = !plane;
10439 dev_priv->display.crtc_disable(&crtc->base);
10440 crtc->plane = plane;
10441
10442 /* ... and break all links. */
10443 list_for_each_entry(connector, &dev->mode_config.connector_list,
10444 base.head) {
10445 if (connector->encoder->base.crtc != &crtc->base)
10446 continue;
10447
10448 intel_connector_break_all_links(connector);
10449 }
10450
10451 WARN_ON(crtc->active);
10452 crtc->base.enabled = false;
10453 }
24929352 10454
7fad798e
DV		 10455 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10456 crtc->pipe == PIPE_A && !crtc->active) {
10457 /* BIOS forgot to enable pipe A, this mostly happens after
10458 * resume. Force-enable the pipe to fix this, the update_dpms
10459 * call below we restore the pipe to the right state, but leave
10460 * the required bits on. */
10461 intel_enable_pipe_a(dev);
10462 }
10463
24929352
DV		 10464 /* Adjust the state of the output pipe according to whether we
10465 * have active connectors/encoders. */
10466 intel_crtc_update_dpms(&crtc->base);
10467
10468 if (crtc->active != crtc->base.enabled) {
10469 struct intel_encoder *encoder;
10470
10471 /* This can happen either due to bugs in the get_hw_state
10472 * functions or because the pipe is force-enabled due to the
10473 * pipe A quirk. */
10474 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10475 crtc->base.base.id,
10476 crtc->base.enabled ? "enabled" : "disabled",
10477 crtc->active ? "enabled" : "disabled");
10478
10479 crtc->base.enabled = crtc->active;
10480
10481 /* Because we only establish the connector -> encoder ->
10482 * crtc links if something is active, this means the
10483 * crtc is now deactivated. Break the links. connector
10484 * -> encoder links are only establish when things are
10485 * actually up, hence no need to break them. */
10486 WARN_ON(crtc->active);
10487
10488 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10489 WARN_ON(encoder->connectors_active);
10490 encoder->base.crtc = NULL;
10491 }
10492 }
10493}
10494
10495static void intel_sanitize_encoder(struct intel_encoder *encoder)
10496{
10497 struct intel_connector *connector;
10498 struct drm_device *dev = encoder->base.dev;
10499
10500 /* We need to check both for a crtc link (meaning that the
10501 * encoder is active and trying to read from a pipe) and the
10502 * pipe itself being active. */
10503 bool has_active_crtc = encoder->base.crtc &&
10504 to_intel_crtc(encoder->base.crtc)->active;
10505
10506 if (encoder->connectors_active && !has_active_crtc) {
10507 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10508 encoder->base.base.id,
10509 drm_get_encoder_name(&encoder->base));
10510
10511 /* Connector is active, but has no active pipe. This is
10512 * fallout from our resume register restoring. Disable
10513 * the encoder manually again. */
10514 if (encoder->base.crtc) {
10515 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10516 encoder->base.base.id,
10517 drm_get_encoder_name(&encoder->base));
10518 encoder->disable(encoder);
10519 }
10520
10521 /* Inconsistent output/port/pipe state happens presumably due to
10522 * a bug in one of the get_hw_state functions. Or someplace else
10523 * in our code, like the register restore mess on resume. Clamp
10524 * things to off as a safer default. */
10525 list_for_each_entry(connector,
10526 &dev->mode_config.connector_list,
10527 base.head) {
10528 if (connector->encoder != encoder)
10529 continue;
10530
10531 intel_connector_break_all_links(connector);
10532 }
10533 }
10534 /* Enabled encoders without active connectors will be fixed in
10535 * the crtc fixup. */
10536}
10537
44cec740 10538void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 10539{
10540 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 10541 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 10542
8dc8a27c
PZ		 10543 /* This function can be called both from intel_modeset_setup_hw_state or
10544 * at a very early point in our resume sequence, where the power well
10545 * structures are not yet restored. Since this function is at a very
10546 * paranoid "someone might have enabled VGA while we were not looking"
10547 * level, just check if the power well is enabled instead of trying to
10548 * follow the "don't touch the power well if we don't need it" policy
10549 * the rest of the driver uses. */
10550 if (HAS_POWER_WELL(dev) &&
6aedd1f5 10551 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
8dc8a27c
PZ		 10552 return;
10553
0fde901f
KM		 10554 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
10555 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 10556 i915_disable_vga(dev);
6e1b4fda 10557 i915_disable_vga_mem(dev);
0fde901f
KM		 10558 }
10559}
10560
30e984df 10561static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 10562{
10563 struct drm_i915_private *dev_priv = dev->dev_private;
10564 enum pipe pipe;
24929352
DV		 10565 struct intel_crtc *crtc;
10566 struct intel_encoder *encoder;
10567 struct intel_connector *connector;
5358901f 10568 int i;
24929352 10569
0e8ffe1b
DV		 10570 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10571 base.head) {
88adfff1 10572 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 10573
0e8ffe1b
DV		 10574 crtc->active = dev_priv->display.get_pipe_config(crtc,
10575 &crtc->config);
24929352
DV		 10576
10577 crtc->base.enabled = crtc->active;
10578
10579 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10580 crtc->base.base.id,
10581 crtc->active ? "enabled" : "disabled");
10582 }
10583
5358901f 10584 /* FIXME: Smash this into the new shared dpll infrastructure. */
affa9354 10585 if (HAS_DDI(dev))
6441ab5f
PZ		 10586 intel_ddi_setup_hw_pll_state(dev);
10587
5358901f
DV		 10588 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10589 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10590
10591 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10592 pll->active = 0;
10593 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10594 base.head) {
10595 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10596 pll->active++;
10597 }
10598 pll->refcount = pll->active;
10599
35c95375
DV		 10600 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10601 pll->name, pll->refcount, pll->on);
5358901f
DV		 10602 }
10603
24929352
DV		 10604 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10605 base.head) {
10606 pipe = 0;
10607
10608 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 10609 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10610 encoder->base.crtc = &crtc->base;
510d5f2f 10611 if (encoder->get_config)
045ac3b5 10612 encoder->get_config(encoder, &crtc->config);
24929352
DV		 10613 } else {
10614 encoder->base.crtc = NULL;
10615 }
10616
10617 encoder->connectors_active = false;
10618 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10619 encoder->base.base.id,
10620 drm_get_encoder_name(&encoder->base),
10621 encoder->base.crtc ? "enabled" : "disabled",
10622 pipe);
10623 }
10624
10625 list_for_each_entry(connector, &dev->mode_config.connector_list,
10626 base.head) {
10627 if (connector->get_hw_state(connector)) {
10628 connector->base.dpms = DRM_MODE_DPMS_ON;
10629 connector->encoder->connectors_active = true;
10630 connector->base.encoder = &connector->encoder->base;
10631 } else {
10632 connector->base.dpms = DRM_MODE_DPMS_OFF;
10633 connector->base.encoder = NULL;
10634 }
10635 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10636 connector->base.base.id,
10637 drm_get_connector_name(&connector->base),
10638 connector->base.encoder ? "enabled" : "disabled");
10639 }
30e984df
DV		 10640}
10641
10642/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10643 * and i915 state tracking structures. */
10644void intel_modeset_setup_hw_state(struct drm_device *dev,
10645 bool force_restore)
10646{
10647 struct drm_i915_private *dev_priv = dev->dev_private;
10648 enum pipe pipe;
30e984df
DV		 10649 struct intel_crtc *crtc;
10650 struct intel_encoder *encoder;
35c95375 10651 int i;
30e984df
DV		 10652
10653 intel_modeset_readout_hw_state(dev);
24929352 10654
babea61d
JB		 10655 /*
10656 * Now that we have the config, copy it to each CRTC struct
10657 * Note that this could go away if we move to using crtc_config
10658 * checking everywhere.
10659 */
10660 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10661 base.head) {
10662 if (crtc->active && i915_fastboot) {
10663 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10664
10665 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10666 crtc->base.base.id);
10667 drm_mode_debug_printmodeline(&crtc->base.mode);
10668 }
10669 }
10670
24929352
DV		 10671 /* HW state is read out, now we need to sanitize this mess. */
10672 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10673 base.head) {
10674 intel_sanitize_encoder(encoder);
10675 }
10676
10677 for_each_pipe(pipe) {
10678 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10679 intel_sanitize_crtc(crtc);
c0b03411 10680 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 10681 }
9a935856 10682
35c95375
DV		 10683 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10684 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10685
10686 if (!pll->on || pll->active)
10687 continue;
10688
10689 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10690
10691 pll->disable(dev_priv, pll);
10692 pll->on = false;
10693 }
10694
45e2b5f6 10695 if (force_restore) {
7d0bc1ea
VS		 10696 i915_redisable_vga(dev);
10697
f30da187
DV		 10698 /*
10699 * We need to use raw interfaces for restoring state to avoid
10700 * checking (bogus) intermediate states.
10701 */
45e2b5f6 10702 for_each_pipe(pipe) {
b5644d05
JB		 10703 struct drm_crtc *crtc =
10704 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 10705
10706 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10707 crtc->fb);
45e2b5f6
DV		 10708 }
10709 } else {
10710 intel_modeset_update_staged_output_state(dev);
10711 }
8af6cf88
DV		 10712
10713 intel_modeset_check_state(dev);
2e938892
DV		 10714
10715 drm_mode_config_reset(dev);
2c7111db
CW		 10716}
10717
10718void intel_modeset_gem_init(struct drm_device *dev)
10719{
1833b134 10720 intel_modeset_init_hw(dev);
02e792fb
DV		 10721
10722 intel_setup_overlay(dev);
24929352 10723
45e2b5f6 10724 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 10725}
10726
10727void intel_modeset_cleanup(struct drm_device *dev)
10728{
652c393a
JB		 10729 struct drm_i915_private *dev_priv = dev->dev_private;
10730 struct drm_crtc *crtc;
652c393a 10731
fd0c0642
DV		 10732 /*
10733 * Interrupts and polling as the first thing to avoid creating havoc.
10734 * Too much stuff here (turning of rps, connectors, ...) would
10735 * experience fancy races otherwise.
10736 */
10737 drm_irq_uninstall(dev);
10738 cancel_work_sync(&dev_priv->hotplug_work);
10739 /*
10740 * Due to the hpd irq storm handling the hotplug work can re-arm the
10741 * poll handlers. Hence disable polling after hpd handling is shut down.
10742 */
f87ea761 10743 drm_kms_helper_poll_fini(dev);
fd0c0642 10744
652c393a
JB		 10745 mutex_lock(&dev->struct_mutex);
10746
723bfd70
JB		 10747 intel_unregister_dsm_handler();
10748
652c393a
JB		 10749 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10750 /* Skip inactive CRTCs */
10751 if (!crtc->fb)
10752 continue;
10753
3dec0095 10754 intel_increase_pllclock(crtc);
652c393a
JB		 10755 }
10756
973d04f9 10757 intel_disable_fbc(dev);
e70236a8 10758
6e1b4fda 10759 i915_enable_vga_mem(dev);
81b5c7bc 10760
8090c6b9 10761 intel_disable_gt_powersave(dev);
0cdab21f 10762
930ebb46
DV		 10763 ironlake_teardown_rc6(dev);
10764
69341a5e
KH		 10765 mutex_unlock(&dev->struct_mutex);
10766
1630fe75
CW		 10767 /* flush any delayed tasks or pending work */
10768 flush_scheduled_work();
10769
dc652f90
JN		 10770 /* destroy backlight, if any, before the connectors */
10771 intel_panel_destroy_backlight(dev);
10772
79e53945 10773 drm_mode_config_cleanup(dev);
4d7bb011
DV		 10774
10775 intel_cleanup_overlay(dev);
79e53945
JB		 10776}
10777
f1c79df3
ZW		 10778/*
10779 * Return which encoder is currently attached for connector.
10780 */
df0e9248 10781struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 10782{
df0e9248
CW		 10783 return &intel_attached_encoder(connector)->base;
10784}
f1c79df3 10785
df0e9248
CW		 10786void intel_connector_attach_encoder(struct intel_connector *connector,
10787 struct intel_encoder *encoder)
10788{
10789 connector->encoder = encoder;
10790 drm_mode_connector_attach_encoder(&connector->base,
10791 &encoder->base);
79e53945 10792}
28d52043
DA		 10793
10794/*
10795 * set vga decode state - true == enable VGA decode
10796 */
10797int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10798{
10799 struct drm_i915_private *dev_priv = dev->dev_private;
10800 u16 gmch_ctrl;
10801
10802 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10803 if (state)
10804 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10805 else
10806 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10807 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10808 return 0;
10809}
c4a1d9e4 10810
c4a1d9e4 10811struct intel_display_error_state {
ff57f1b0
PZ		 10812
10813 u32 power_well_driver;
10814
63b66e5b
CW		 10815 int num_transcoders;
10816
c4a1d9e4
CW		 10817 struct intel_cursor_error_state {
10818 u32 control;
10819 u32 position;
10820 u32 base;
10821 u32 size;
52331309 10822 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 10823
10824 struct intel_pipe_error_state {
c4a1d9e4 10825 u32 source;
52331309 10826 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 10827
10828 struct intel_plane_error_state {
10829 u32 control;
10830 u32 stride;
10831 u32 size;
10832 u32 pos;
10833 u32 addr;
10834 u32 surface;
10835 u32 tile_offset;
52331309 10836 } plane[I915_MAX_PIPES];
63b66e5b
CW		 10837
10838 struct intel_transcoder_error_state {
10839 enum transcoder cpu_transcoder;
10840
10841 u32 conf;
10842
10843 u32 htotal;
10844 u32 hblank;
10845 u32 hsync;
10846 u32 vtotal;
10847 u32 vblank;
10848 u32 vsync;
10849 } transcoder[4];
c4a1d9e4
CW		 10850};
10851
10852struct intel_display_error_state *
10853intel_display_capture_error_state(struct drm_device *dev)
10854{
0206e353 10855 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 10856 struct intel_display_error_state *error;
63b66e5b
CW		 10857 int transcoders[] = {
10858 TRANSCODER_A,
10859 TRANSCODER_B,
10860 TRANSCODER_C,
10861 TRANSCODER_EDP,
10862 };
c4a1d9e4
CW		 10863 int i;
10864
63b66e5b
CW		 10865 if (INTEL_INFO(dev)->num_pipes == 0)
10866 return NULL;
10867
c4a1d9e4
CW		 10868 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10869 if (error == NULL)
10870 return NULL;
10871
ff57f1b0
PZ		 10872 if (HAS_POWER_WELL(dev))
10873 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10874
52331309 10875 for_each_pipe(i) {
a18c4c3d
PZ		 10876 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10877 error->cursor[i].control = I915_READ(CURCNTR(i));
10878 error->cursor[i].position = I915_READ(CURPOS(i));
10879 error->cursor[i].base = I915_READ(CURBASE(i));
10880 } else {
10881 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10882 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10883 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10884 }
c4a1d9e4
CW		 10885
10886 error->plane[i].control = I915_READ(DSPCNTR(i));
10887 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 10888 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 10889 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 10890 error->plane[i].pos = I915_READ(DSPPOS(i));
10891 }
ca291363
PZ		 10892 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10893 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 10894 if (INTEL_INFO(dev)->gen >= 4) {
10895 error->plane[i].surface = I915_READ(DSPSURF(i));
10896 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10897 }
10898
c4a1d9e4 10899 error->pipe[i].source = I915_READ(PIPESRC(i));
63b66e5b
CW		 10900 }
10901
10902 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
10903 if (HAS_DDI(dev_priv->dev))
10904 error->num_transcoders++; /* Account for eDP. */
10905
10906 for (i = 0; i < error->num_transcoders; i++) {
10907 enum transcoder cpu_transcoder = transcoders[i];
10908
10909 error->transcoder[i].cpu_transcoder = cpu_transcoder;
10910
10911 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10912 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10913 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10914 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10915 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10916 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10917 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 10918 }
10919
12d217c7
PZ		 10920 /* In the code above we read the registers without checking if the power
10921 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10922 * prevent the next I915_WRITE from detecting it and printing an error
10923 * message. */
907b28c5 10924 intel_uncore_clear_errors(dev);
12d217c7 10925
c4a1d9e4
CW		 10926 return error;
10927}
10928
edc3d884
MK		 10929#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10930
c4a1d9e4 10931void
edc3d884 10932intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 10933 struct drm_device *dev,
10934 struct intel_display_error_state *error)
10935{
10936 int i;
10937
63b66e5b
CW		 10938 if (!error)
10939 return;
10940
edc3d884 10941 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 10942 if (HAS_POWER_WELL(dev))
edc3d884 10943 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 10944 error->power_well_driver);
52331309 10945 for_each_pipe(i) {
edc3d884 10946 err_printf(m, "Pipe [%d]:\n", i);
edc3d884 10947 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
edc3d884
MK		 10948
10949 err_printf(m, "Plane [%d]:\n", i);
10950 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10951 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 10952 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 10953 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
10954 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 10955 }
4b71a570 10956 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 10957 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 10958 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 10959 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
10960 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 10961 }
10962
edc3d884
MK		 10963 err_printf(m, "Cursor [%d]:\n", i);
10964 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
10965 err_printf(m, " POS: %08x\n", error->cursor[i].position);
10966 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 10967 }
63b66e5b
CW		 10968
10969 for (i = 0; i < error->num_transcoders; i++) {
10970 err_printf(m, " CPU transcoder: %c\n",
10971 transcoder_name(error->transcoder[i].cpu_transcoder));
10972 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
10973 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
10974 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
10975 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
10976 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
10977 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
10978 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
10979 }
c4a1d9e4 10980}
Linux kernel - Deliverables
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