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drm/i915: Store max cdclk value in dev_priv
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c 48/* Primary plane formats for gen <= 3 */
568db4f2 49static const uint32_t i8xx_primary_formats[] = {
67fe7dc5
DL		 50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
465c120c 52 DRM_FORMAT_XRGB1555,
67fe7dc5 53 DRM_FORMAT_XRGB8888,
465c120c
MR		 54};
55
56/* Primary plane formats for gen >= 4 */
568db4f2 57static const uint32_t i965_primary_formats[] = {
6c0fd451
DL		 58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64};
65
66static const uint32_t skl_primary_formats[] = {
67fe7dc5
DL		 67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
465c120c 70 DRM_FORMAT_XBGR8888,
67fe7dc5 71 DRM_FORMAT_ARGB8888,
465c120c
MR		 72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
465c120c 74 DRM_FORMAT_XBGR2101010,
465c120c
MR		 75};
76
3d7d6510
MR		 77/* Cursor formats */
78static const uint32_t intel_cursor_formats[] = {
79 DRM_FORMAT_ARGB8888,
80};
81
6b383a7f 82static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 83
f1f644dc 84static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 85 struct intel_crtc_state *pipe_config);
18442d08 86static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 87 struct intel_crtc_state *pipe_config);
f1f644dc 88
8c7b5ccb 89static int intel_set_mode(struct drm_crtc *crtc,
83a57153 90 struct drm_atomic_state *state);
eb1bfe80
JB		 91static int intel_framebuffer_init(struct drm_device *dev,
92 struct intel_framebuffer *ifb,
93 struct drm_mode_fb_cmd2 *mode_cmd,
94 struct drm_i915_gem_object *obj);
5b18e57c
DV		 95static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
96static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 97static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 98 struct intel_link_m_n *m_n,
99 struct intel_link_m_n *m2_n2);
29407aab 100static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 101static void haswell_set_pipeconf(struct drm_crtc *crtc);
102static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 103static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 104 const struct intel_crtc_state *pipe_config);
d288f65f 105static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 106 const struct intel_crtc_state *pipe_config);
ea2c67bb
MR		 107static void intel_begin_crtc_commit(struct drm_crtc *crtc);
108static void intel_finish_crtc_commit(struct drm_crtc *crtc);
549e2bfb
CK		 109static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
110 struct intel_crtc_state *crtc_state);
5ab7b0b7
ID		 111static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
112 int num_connectors);
ce22dba9
ML		 113static void intel_crtc_enable_planes(struct drm_crtc *crtc);
114static void intel_crtc_disable_planes(struct drm_crtc *crtc);
e7457a9a 115
0e32b39c
DA		 116static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
117{
118 if (!connector->mst_port)
119 return connector->encoder;
120 else
121 return &connector->mst_port->mst_encoders[pipe]->base;
122}
123
79e53945 124typedef struct {
0206e353 125 int min, max;
79e53945
JB		 126} intel_range_t;
127
128typedef struct {
0206e353
AJ		 129 int dot_limit;
130 int p2_slow, p2_fast;
79e53945
JB		 131} intel_p2_t;
132
d4906093
ML		 133typedef struct intel_limit intel_limit_t;
134struct intel_limit {
0206e353
AJ		 135 intel_range_t dot, vco, n, m, m1, m2, p, p1;
136 intel_p2_t p2;
d4906093 137};
79e53945 138
d2acd215
DV		 139int
140intel_pch_rawclk(struct drm_device *dev)
141{
142 struct drm_i915_private *dev_priv = dev->dev_private;
143
144 WARN_ON(!HAS_PCH_SPLIT(dev));
145
146 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
147}
148
021357ac
CW		 149static inline u32 /* units of 100MHz */
150intel_fdi_link_freq(struct drm_device *dev)
151{
8b99e68c
CW		 152 if (IS_GEN5(dev)) {
153 struct drm_i915_private *dev_priv = dev->dev_private;
154 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
155 } else
156 return 27;
021357ac
CW		 157}
158
5d536e28 159static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 160 .dot = { .min = 25000, .max = 350000 },
9c333719 161 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 162 .n = { .min = 2, .max = 16 },
0206e353
AJ		 163 .m = { .min = 96, .max = 140 },
164 .m1 = { .min = 18, .max = 26 },
165 .m2 = { .min = 6, .max = 16 },
166 .p = { .min = 4, .max = 128 },
167 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 168 .p2 = { .dot_limit = 165000,
169 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 170};
171
5d536e28
DV		 172static const intel_limit_t intel_limits_i8xx_dvo = {
173 .dot = { .min = 25000, .max = 350000 },
9c333719 174 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 175 .n = { .min = 2, .max = 16 },
5d536e28
DV		 176 .m = { .min = 96, .max = 140 },
177 .m1 = { .min = 18, .max = 26 },
178 .m2 = { .min = 6, .max = 16 },
179 .p = { .min = 4, .max = 128 },
180 .p1 = { .min = 2, .max = 33 },
181 .p2 = { .dot_limit = 165000,
182 .p2_slow = 4, .p2_fast = 4 },
183};
184
e4b36699 185static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 186 .dot = { .min = 25000, .max = 350000 },
9c333719 187 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 188 .n = { .min = 2, .max = 16 },
0206e353
AJ		 189 .m = { .min = 96, .max = 140 },
190 .m1 = { .min = 18, .max = 26 },
191 .m2 = { .min = 6, .max = 16 },
192 .p = { .min = 4, .max = 128 },
193 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 194 .p2 = { .dot_limit = 165000,
195 .p2_slow = 14, .p2_fast = 7 },
e4b36699 196};
273e27ca 197
e4b36699 198static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 199 .dot = { .min = 20000, .max = 400000 },
200 .vco = { .min = 1400000, .max = 2800000 },
201 .n = { .min = 1, .max = 6 },
202 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 203 .m1 = { .min = 8, .max = 18 },
204 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 205 .p = { .min = 5, .max = 80 },
206 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 207 .p2 = { .dot_limit = 200000,
208 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 209};
210
211static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 212 .dot = { .min = 20000, .max = 400000 },
213 .vco = { .min = 1400000, .max = 2800000 },
214 .n = { .min = 1, .max = 6 },
215 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 216 .m1 = { .min = 8, .max = 18 },
217 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 218 .p = { .min = 7, .max = 98 },
219 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 220 .p2 = { .dot_limit = 112000,
221 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 222};
223
273e27ca 224
e4b36699 225static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 226 .dot = { .min = 25000, .max = 270000 },
227 .vco = { .min = 1750000, .max = 3500000},
228 .n = { .min = 1, .max = 4 },
229 .m = { .min = 104, .max = 138 },
230 .m1 = { .min = 17, .max = 23 },
231 .m2 = { .min = 5, .max = 11 },
232 .p = { .min = 10, .max = 30 },
233 .p1 = { .min = 1, .max = 3},
234 .p2 = { .dot_limit = 270000,
235 .p2_slow = 10,
236 .p2_fast = 10
044c7c41 237 },
e4b36699
KP		 238};
239
240static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 241 .dot = { .min = 22000, .max = 400000 },
242 .vco = { .min = 1750000, .max = 3500000},
243 .n = { .min = 1, .max = 4 },
244 .m = { .min = 104, .max = 138 },
245 .m1 = { .min = 16, .max = 23 },
246 .m2 = { .min = 5, .max = 11 },
247 .p = { .min = 5, .max = 80 },
248 .p1 = { .min = 1, .max = 8},
249 .p2 = { .dot_limit = 165000,
250 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 251};
252
253static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 254 .dot = { .min = 20000, .max = 115000 },
255 .vco = { .min = 1750000, .max = 3500000 },
256 .n = { .min = 1, .max = 3 },
257 .m = { .min = 104, .max = 138 },
258 .m1 = { .min = 17, .max = 23 },
259 .m2 = { .min = 5, .max = 11 },
260 .p = { .min = 28, .max = 112 },
261 .p1 = { .min = 2, .max = 8 },
262 .p2 = { .dot_limit = 0,
263 .p2_slow = 14, .p2_fast = 14
044c7c41 264 },
e4b36699
KP		 265};
266
267static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 268 .dot = { .min = 80000, .max = 224000 },
269 .vco = { .min = 1750000, .max = 3500000 },
270 .n = { .min = 1, .max = 3 },
271 .m = { .min = 104, .max = 138 },
272 .m1 = { .min = 17, .max = 23 },
273 .m2 = { .min = 5, .max = 11 },
274 .p = { .min = 14, .max = 42 },
275 .p1 = { .min = 2, .max = 6 },
276 .p2 = { .dot_limit = 0,
277 .p2_slow = 7, .p2_fast = 7
044c7c41 278 },
e4b36699
KP		 279};
280
f2b115e6 281static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 282 .dot = { .min = 20000, .max = 400000},
283 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 284 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 285 .n = { .min = 3, .max = 6 },
286 .m = { .min = 2, .max = 256 },
273e27ca 287 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 288 .m1 = { .min = 0, .max = 0 },
289 .m2 = { .min = 0, .max = 254 },
290 .p = { .min = 5, .max = 80 },
291 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 292 .p2 = { .dot_limit = 200000,
293 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 294};
295
f2b115e6 296static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 297 .dot = { .min = 20000, .max = 400000 },
298 .vco = { .min = 1700000, .max = 3500000 },
299 .n = { .min = 3, .max = 6 },
300 .m = { .min = 2, .max = 256 },
301 .m1 = { .min = 0, .max = 0 },
302 .m2 = { .min = 0, .max = 254 },
303 .p = { .min = 7, .max = 112 },
304 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 305 .p2 = { .dot_limit = 112000,
306 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 307};
308
273e27ca
EA		 309/* Ironlake / Sandybridge
310 *
311 * We calculate clock using (register_value + 2) for N/M1/M2, so here
312 * the range value for them is (actual_value - 2).
313 */
b91ad0ec 314static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 315 .dot = { .min = 25000, .max = 350000 },
316 .vco = { .min = 1760000, .max = 3510000 },
317 .n = { .min = 1, .max = 5 },
318 .m = { .min = 79, .max = 127 },
319 .m1 = { .min = 12, .max = 22 },
320 .m2 = { .min = 5, .max = 9 },
321 .p = { .min = 5, .max = 80 },
322 .p1 = { .min = 1, .max = 8 },
323 .p2 = { .dot_limit = 225000,
324 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 325};
326
b91ad0ec 327static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 328 .dot = { .min = 25000, .max = 350000 },
329 .vco = { .min = 1760000, .max = 3510000 },
330 .n = { .min = 1, .max = 3 },
331 .m = { .min = 79, .max = 118 },
332 .m1 = { .min = 12, .max = 22 },
333 .m2 = { .min = 5, .max = 9 },
334 .p = { .min = 28, .max = 112 },
335 .p1 = { .min = 2, .max = 8 },
336 .p2 = { .dot_limit = 225000,
337 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 338};
339
340static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 341 .dot = { .min = 25000, .max = 350000 },
342 .vco = { .min = 1760000, .max = 3510000 },
343 .n = { .min = 1, .max = 3 },
344 .m = { .min = 79, .max = 127 },
345 .m1 = { .min = 12, .max = 22 },
346 .m2 = { .min = 5, .max = 9 },
347 .p = { .min = 14, .max = 56 },
348 .p1 = { .min = 2, .max = 8 },
349 .p2 = { .dot_limit = 225000,
350 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 351};
352
273e27ca 353/* LVDS 100mhz refclk limits. */
b91ad0ec 354static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 355 .dot = { .min = 25000, .max = 350000 },
356 .vco = { .min = 1760000, .max = 3510000 },
357 .n = { .min = 1, .max = 2 },
358 .m = { .min = 79, .max = 126 },
359 .m1 = { .min = 12, .max = 22 },
360 .m2 = { .min = 5, .max = 9 },
361 .p = { .min = 28, .max = 112 },
0206e353 362 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 363 .p2 = { .dot_limit = 225000,
364 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 365};
366
367static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 368 .dot = { .min = 25000, .max = 350000 },
369 .vco = { .min = 1760000, .max = 3510000 },
370 .n = { .min = 1, .max = 3 },
371 .m = { .min = 79, .max = 126 },
372 .m1 = { .min = 12, .max = 22 },
373 .m2 = { .min = 5, .max = 9 },
374 .p = { .min = 14, .max = 42 },
0206e353 375 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 376 .p2 = { .dot_limit = 225000,
377 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 378};
379
dc730512 380static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 381 /*
382 * These are the data rate limits (measured in fast clocks)
383 * since those are the strictest limits we have. The fast
384 * clock and actual rate limits are more relaxed, so checking
385 * them would make no difference.
386 */
387 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 388 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 389 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 390 .m1 = { .min = 2, .max = 3 },
391 .m2 = { .min = 11, .max = 156 },
b99ab663 392 .p1 = { .min = 2, .max = 3 },
5fdc9c49 393 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 394};
395
ef9348c8
CML		 396static const intel_limit_t intel_limits_chv = {
397 /*
398 * These are the data rate limits (measured in fast clocks)
399 * since those are the strictest limits we have. The fast
400 * clock and actual rate limits are more relaxed, so checking
401 * them would make no difference.
402 */
403 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 404 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 405 .n = { .min = 1, .max = 1 },
406 .m1 = { .min = 2, .max = 2 },
407 .m2 = { .min = 24 << 22, .max = 175 << 22 },
408 .p1 = { .min = 2, .max = 4 },
409 .p2 = { .p2_slow = 1, .p2_fast = 14 },
410};
411
5ab7b0b7
ID		 412static const intel_limit_t intel_limits_bxt = {
413 /* FIXME: find real dot limits */
414 .dot = { .min = 0, .max = INT_MAX },
415 .vco = { .min = 4800000, .max = 6480000 },
416 .n = { .min = 1, .max = 1 },
417 .m1 = { .min = 2, .max = 2 },
418 /* FIXME: find real m2 limits */
419 .m2 = { .min = 2 << 22, .max = 255 << 22 },
420 .p1 = { .min = 2, .max = 4 },
421 .p2 = { .p2_slow = 1, .p2_fast = 20 },
422};
423
6b4bf1c4
VS		 424static void vlv_clock(int refclk, intel_clock_t *clock)
425{
426 clock->m = clock->m1 * clock->m2;
427 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 428 if (WARN_ON(clock->n == 0 || clock->p == 0))
429 return;
fb03ac01
VS		 430 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
431 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
6b4bf1c4
VS		 432}
433
e0638cdf
PZ		 434/**
435 * Returns whether any output on the specified pipe is of the specified type
436 */
4093561b 437bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 438{
409ee761 439 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 440 struct intel_encoder *encoder;
441
409ee761 442 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 443 if (encoder->type == type)
444 return true;
445
446 return false;
447}
448
d0737e1d
ACO		 449/**
450 * Returns whether any output on the specified pipe will have the specified
451 * type after a staged modeset is complete, i.e., the same as
452 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
453 * encoder->crtc.
454 */
a93e255f
ACO		 455static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
456 int type)
d0737e1d 457{
a93e255f 458 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 459 struct drm_connector *connector;
a93e255f 460 struct drm_connector_state *connector_state;
d0737e1d 461 struct intel_encoder *encoder;
a93e255f
ACO		 462 int i, num_connectors = 0;
463
da3ced29 464 for_each_connector_in_state(state, connector, connector_state, i) {
a93e255f
ACO		 465 if (connector_state->crtc != crtc_state->base.crtc)
466 continue;
467
468 num_connectors++;
d0737e1d 469
a93e255f
ACO		 470 encoder = to_intel_encoder(connector_state->best_encoder);
471 if (encoder->type == type)
d0737e1d 472 return true;
a93e255f
ACO		 473 }
474
475 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 476
477 return false;
478}
479
a93e255f
ACO		 480static const intel_limit_t *
481intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 482{
a93e255f 483 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 484 const intel_limit_t *limit;
b91ad0ec 485
a93e255f 486 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 487 if (intel_is_dual_link_lvds(dev)) {
1b894b59 488 if (refclk == 100000)
b91ad0ec
ZW		 489 limit = &intel_limits_ironlake_dual_lvds_100m;
490 else
491 limit = &intel_limits_ironlake_dual_lvds;
492 } else {
1b894b59 493 if (refclk == 100000)
b91ad0ec
ZW		 494 limit = &intel_limits_ironlake_single_lvds_100m;
495 else
496 limit = &intel_limits_ironlake_single_lvds;
497 }
c6bb3538 498 } else
b91ad0ec 499 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 500
501 return limit;
502}
503
a93e255f
ACO		 504static const intel_limit_t *
505intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 506{
a93e255f 507 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 508 const intel_limit_t *limit;
509
a93e255f 510 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 511 if (intel_is_dual_link_lvds(dev))
e4b36699 512 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 513 else
e4b36699 514 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 515 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
516 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 517 limit = &intel_limits_g4x_hdmi;
a93e255f 518 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 519 limit = &intel_limits_g4x_sdvo;
044c7c41 520 } else /* The option is for other outputs */
e4b36699 521 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 522
523 return limit;
524}
525
a93e255f
ACO		 526static const intel_limit_t *
527intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 528{
a93e255f 529 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 530 const intel_limit_t *limit;
531
5ab7b0b7
ID		 532 if (IS_BROXTON(dev))
533 limit = &intel_limits_bxt;
534 else if (HAS_PCH_SPLIT(dev))
a93e255f 535 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 536 else if (IS_G4X(dev)) {
a93e255f 537 limit = intel_g4x_limit(crtc_state);
f2b115e6 538 } else if (IS_PINEVIEW(dev)) {
a93e255f 539 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 540 limit = &intel_limits_pineview_lvds;
2177832f 541 else
f2b115e6 542 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 543 } else if (IS_CHERRYVIEW(dev)) {
544 limit = &intel_limits_chv;
a0c4da24 545 } else if (IS_VALLEYVIEW(dev)) {
dc730512 546 limit = &intel_limits_vlv;
a6c45cf0 547 } else if (!IS_GEN2(dev)) {
a93e255f 548 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 549 limit = &intel_limits_i9xx_lvds;
550 else
551 limit = &intel_limits_i9xx_sdvo;
79e53945 552 } else {
a93e255f 553 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 554 limit = &intel_limits_i8xx_lvds;
a93e255f 555 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 556 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 557 else
558 limit = &intel_limits_i8xx_dac;
79e53945
JB		 559 }
560 return limit;
561}
562
f2b115e6
AJ		 563/* m1 is reserved as 0 in Pineview, n is a ring counter */
564static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 565{
2177832f
SL		 566 clock->m = clock->m2 + 2;
567 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 568 if (WARN_ON(clock->n == 0 || clock->p == 0))
569 return;
fb03ac01
VS		 570 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
571 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
2177832f
SL		 572}
573
7429e9d4
DV		 574static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
575{
576 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
577}
578
ac58c3f0 579static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 580{
7429e9d4 581 clock->m = i9xx_dpll_compute_m(clock);
79e53945 582 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 583 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
584 return;
fb03ac01
VS		 585 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
586 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
79e53945
JB		 587}
588
ef9348c8
CML		 589static void chv_clock(int refclk, intel_clock_t *clock)
590{
591 clock->m = clock->m1 * clock->m2;
592 clock->p = clock->p1 * clock->p2;
593 if (WARN_ON(clock->n == 0 || clock->p == 0))
594 return;
595 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
596 clock->n << 22);
597 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
598}
599
7c04d1d9 600#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 601/**
602 * Returns whether the given set of divisors are valid for a given refclk with
603 * the given connectors.
604 */
605
1b894b59
CW		 606static bool intel_PLL_is_valid(struct drm_device *dev,
607 const intel_limit_t *limit,
608 const intel_clock_t *clock)
79e53945 609{
f01b7962
VS		 610 if (clock->n < limit->n.min || limit->n.max < clock->n)
611 INTELPllInvalid("n out of range\n");
79e53945 612 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 613 INTELPllInvalid("p1 out of range\n");
79e53945 614 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 615 INTELPllInvalid("m2 out of range\n");
79e53945 616 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 617 INTELPllInvalid("m1 out of range\n");
f01b7962 618
5ab7b0b7 619 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
f01b7962
VS		 620 if (clock->m1 <= clock->m2)
621 INTELPllInvalid("m1 <= m2\n");
622
5ab7b0b7 623 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
f01b7962
VS		 624 if (clock->p < limit->p.min || limit->p.max < clock->p)
625 INTELPllInvalid("p out of range\n");
626 if (clock->m < limit->m.min || limit->m.max < clock->m)
627 INTELPllInvalid("m out of range\n");
628 }
629
79e53945 630 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 631 INTELPllInvalid("vco out of range\n");
79e53945
JB		 632 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
633 * connector, etc., rather than just a single range.
634 */
635 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 636 INTELPllInvalid("dot out of range\n");
79e53945
JB		 637
638 return true;
639}
640
d4906093 641static bool
a93e255f
ACO		 642i9xx_find_best_dpll(const intel_limit_t *limit,
643 struct intel_crtc_state *crtc_state,
cec2f356
SP		 644 int target, int refclk, intel_clock_t *match_clock,
645 intel_clock_t *best_clock)
79e53945 646{
a93e255f 647 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 648 struct drm_device *dev = crtc->base.dev;
79e53945 649 intel_clock_t clock;
79e53945
JB		 650 int err = target;
651
a93e255f 652 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 653 /*
a210b028
DV		 654 * For LVDS just rely on its current settings for dual-channel.
655 * We haven't figured out how to reliably set up different
656 * single/dual channel state, if we even can.
79e53945 657 */
1974cad0 658 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 659 clock.p2 = limit->p2.p2_fast;
660 else
661 clock.p2 = limit->p2.p2_slow;
662 } else {
663 if (target < limit->p2.dot_limit)
664 clock.p2 = limit->p2.p2_slow;
665 else
666 clock.p2 = limit->p2.p2_fast;
667 }
668
0206e353 669 memset(best_clock, 0, sizeof(*best_clock));
79e53945 670
42158660
ZY		 671 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
672 clock.m1++) {
673 for (clock.m2 = limit->m2.min;
674 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 675 if (clock.m2 >= clock.m1)
42158660
ZY		 676 break;
677 for (clock.n = limit->n.min;
678 clock.n <= limit->n.max; clock.n++) {
679 for (clock.p1 = limit->p1.min;
680 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 681 int this_err;
682
ac58c3f0
DV		 683 i9xx_clock(refclk, &clock);
684 if (!intel_PLL_is_valid(dev, limit,
685 &clock))
686 continue;
687 if (match_clock &&
688 clock.p != match_clock->p)
689 continue;
690
691 this_err = abs(clock.dot - target);
692 if (this_err < err) {
693 *best_clock = clock;
694 err = this_err;
695 }
696 }
697 }
698 }
699 }
700
701 return (err != target);
702}
703
704static bool
a93e255f
ACO		 705pnv_find_best_dpll(const intel_limit_t *limit,
706 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 707 int target, int refclk, intel_clock_t *match_clock,
708 intel_clock_t *best_clock)
79e53945 709{
a93e255f 710 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 711 struct drm_device *dev = crtc->base.dev;
79e53945 712 intel_clock_t clock;
79e53945
JB		 713 int err = target;
714
a93e255f 715 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 716 /*
a210b028
DV		 717 * For LVDS just rely on its current settings for dual-channel.
718 * We haven't figured out how to reliably set up different
719 * single/dual channel state, if we even can.
79e53945 720 */
1974cad0 721 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 722 clock.p2 = limit->p2.p2_fast;
723 else
724 clock.p2 = limit->p2.p2_slow;
725 } else {
726 if (target < limit->p2.dot_limit)
727 clock.p2 = limit->p2.p2_slow;
728 else
729 clock.p2 = limit->p2.p2_fast;
730 }
731
0206e353 732 memset(best_clock, 0, sizeof(*best_clock));
79e53945 733
42158660
ZY		 734 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
735 clock.m1++) {
736 for (clock.m2 = limit->m2.min;
737 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 738 for (clock.n = limit->n.min;
739 clock.n <= limit->n.max; clock.n++) {
740 for (clock.p1 = limit->p1.min;
741 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 742 int this_err;
743
ac58c3f0 744 pineview_clock(refclk, &clock);
1b894b59
CW		 745 if (!intel_PLL_is_valid(dev, limit,
746 &clock))
79e53945 747 continue;
cec2f356
SP		 748 if (match_clock &&
749 clock.p != match_clock->p)
750 continue;
79e53945
JB		 751
752 this_err = abs(clock.dot - target);
753 if (this_err < err) {
754 *best_clock = clock;
755 err = this_err;
756 }
757 }
758 }
759 }
760 }
761
762 return (err != target);
763}
764
d4906093 765static bool
a93e255f
ACO		 766g4x_find_best_dpll(const intel_limit_t *limit,
767 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 768 int target, int refclk, intel_clock_t *match_clock,
769 intel_clock_t *best_clock)
d4906093 770{
a93e255f 771 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 772 struct drm_device *dev = crtc->base.dev;
d4906093
ML		 773 intel_clock_t clock;
774 int max_n;
775 bool found;
6ba770dc
AJ		 776 /* approximately equals target * 0.00585 */
777 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 778 found = false;
779
a93e255f 780 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 781 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 782 clock.p2 = limit->p2.p2_fast;
783 else
784 clock.p2 = limit->p2.p2_slow;
785 } else {
786 if (target < limit->p2.dot_limit)
787 clock.p2 = limit->p2.p2_slow;
788 else
789 clock.p2 = limit->p2.p2_fast;
790 }
791
792 memset(best_clock, 0, sizeof(*best_clock));
793 max_n = limit->n.max;
f77f13e2 794 /* based on hardware requirement, prefer smaller n to precision */
d4906093 795 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 796 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 797 for (clock.m1 = limit->m1.max;
798 clock.m1 >= limit->m1.min; clock.m1--) {
799 for (clock.m2 = limit->m2.max;
800 clock.m2 >= limit->m2.min; clock.m2--) {
801 for (clock.p1 = limit->p1.max;
802 clock.p1 >= limit->p1.min; clock.p1--) {
803 int this_err;
804
ac58c3f0 805 i9xx_clock(refclk, &clock);
1b894b59
CW		 806 if (!intel_PLL_is_valid(dev, limit,
807 &clock))
d4906093 808 continue;
1b894b59
CW		 809
810 this_err = abs(clock.dot - target);
d4906093
ML		 811 if (this_err < err_most) {
812 *best_clock = clock;
813 err_most = this_err;
814 max_n = clock.n;
815 found = true;
816 }
817 }
818 }
819 }
820 }
2c07245f
ZW		 821 return found;
822}
823
d5dd62bd
ID		 824/*
825 * Check if the calculated PLL configuration is more optimal compared to the
826 * best configuration and error found so far. Return the calculated error.
827 */
828static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
829 const intel_clock_t *calculated_clock,
830 const intel_clock_t *best_clock,
831 unsigned int best_error_ppm,
832 unsigned int *error_ppm)
833{
9ca3ba01
ID		 834 /*
835 * For CHV ignore the error and consider only the P value.
836 * Prefer a bigger P value based on HW requirements.
837 */
838 if (IS_CHERRYVIEW(dev)) {
839 *error_ppm = 0;
840
841 return calculated_clock->p > best_clock->p;
842 }
843
24be4e46
ID		 844 if (WARN_ON_ONCE(!target_freq))
845 return false;
846
d5dd62bd
ID		 847 *error_ppm = div_u64(1000000ULL *
848 abs(target_freq - calculated_clock->dot),
849 target_freq);
850 /*
851 * Prefer a better P value over a better (smaller) error if the error
852 * is small. Ensure this preference for future configurations too by
853 * setting the error to 0.
854 */
855 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
856 *error_ppm = 0;
857
858 return true;
859 }
860
861 return *error_ppm + 10 < best_error_ppm;
862}
863
a0c4da24 864static bool
a93e255f
ACO		 865vlv_find_best_dpll(const intel_limit_t *limit,
866 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 867 int target, int refclk, intel_clock_t *match_clock,
868 intel_clock_t *best_clock)
a0c4da24 869{
a93e255f 870 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 871 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 872 intel_clock_t clock;
69e4f900 873 unsigned int bestppm = 1000000;
27e639bf
VS		 874 /* min update 19.2 MHz */
875 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 876 bool found = false;
a0c4da24 877
6b4bf1c4
VS		 878 target *= 5; /* fast clock */
879
880 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 881
882 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 883 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 884 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 885 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 886 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 887 clock.p = clock.p1 * clock.p2;
a0c4da24 888 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 889 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 890 unsigned int ppm;
69e4f900 891
6b4bf1c4
VS		 892 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
893 refclk * clock.m1);
894
895 vlv_clock(refclk, &clock);
43b0ac53 896
f01b7962
VS		 897 if (!intel_PLL_is_valid(dev, limit,
898 &clock))
43b0ac53
VS		 899 continue;
900
d5dd62bd
ID		 901 if (!vlv_PLL_is_optimal(dev, target,
902 &clock,
903 best_clock,
904 bestppm, &ppm))
905 continue;
6b4bf1c4 906
d5dd62bd
ID		 907 *best_clock = clock;
908 bestppm = ppm;
909 found = true;
a0c4da24
JB		 910 }
911 }
912 }
913 }
a0c4da24 914
49e497ef 915 return found;
a0c4da24 916}
a4fc5ed6 917
ef9348c8 918static bool
a93e255f
ACO		 919chv_find_best_dpll(const intel_limit_t *limit,
920 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 921 int target, int refclk, intel_clock_t *match_clock,
922 intel_clock_t *best_clock)
923{
a93e255f 924 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 925 struct drm_device *dev = crtc->base.dev;
9ca3ba01 926 unsigned int best_error_ppm;
ef9348c8
CML		 927 intel_clock_t clock;
928 uint64_t m2;
929 int found = false;
930
931 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 932 best_error_ppm = 1000000;
ef9348c8
CML		 933
934 /*
935 * Based on hardware doc, the n always set to 1, and m1 always
936 * set to 2. If requires to support 200Mhz refclk, we need to
937 * revisit this because n may not 1 anymore.
938 */
939 clock.n = 1, clock.m1 = 2;
940 target *= 5; /* fast clock */
941
942 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
943 for (clock.p2 = limit->p2.p2_fast;
944 clock.p2 >= limit->p2.p2_slow;
945 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 946 unsigned int error_ppm;
ef9348c8
CML		 947
948 clock.p = clock.p1 * clock.p2;
949
950 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
951 clock.n) << 22, refclk * clock.m1);
952
953 if (m2 > INT_MAX/clock.m1)
954 continue;
955
956 clock.m2 = m2;
957
958 chv_clock(refclk, &clock);
959
960 if (!intel_PLL_is_valid(dev, limit, &clock))
961 continue;
962
9ca3ba01
ID		 963 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
964 best_error_ppm, &error_ppm))
965 continue;
966
967 *best_clock = clock;
968 best_error_ppm = error_ppm;
969 found = true;
ef9348c8
CML		 970 }
971 }
972
973 return found;
974}
975
5ab7b0b7
ID		 976bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
977 intel_clock_t *best_clock)
978{
979 int refclk = i9xx_get_refclk(crtc_state, 0);
980
981 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
982 target_clock, refclk, NULL, best_clock);
983}
984
20ddf665
VS		 985bool intel_crtc_active(struct drm_crtc *crtc)
986{
987 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
988
989 /* Be paranoid as we can arrive here with only partial
990 * state retrieved from the hardware during setup.
991 *
241bfc38 992 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 993 * as Haswell has gained clock readout/fastboot support.
994 *
66e514c1 995 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 996 * properly reconstruct framebuffers.
c3d1f436
MR		 997 *
998 * FIXME: The intel_crtc->active here should be switched to
999 * crtc->state->active once we have proper CRTC states wired up
1000 * for atomic.
20ddf665 1001 */
c3d1f436 1002 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 1003 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 1004}
1005
a5c961d1
PZ		 1006enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1007 enum pipe pipe)
1008{
1009 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011
6e3c9717 1012 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 1013}
1014
fbf49ea2
VS		 1015static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1016{
1017 struct drm_i915_private *dev_priv = dev->dev_private;
1018 u32 reg = PIPEDSL(pipe);
1019 u32 line1, line2;
1020 u32 line_mask;
1021
1022 if (IS_GEN2(dev))
1023 line_mask = DSL_LINEMASK_GEN2;
1024 else
1025 line_mask = DSL_LINEMASK_GEN3;
1026
1027 line1 = I915_READ(reg) & line_mask;
1028 mdelay(5);
1029 line2 = I915_READ(reg) & line_mask;
1030
1031 return line1 == line2;
1032}
1033
ab7ad7f6
KP		 1034/*
1035 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1036 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1037 *
1038 * After disabling a pipe, we can't wait for vblank in the usual way,
1039 * spinning on the vblank interrupt status bit, since we won't actually
1040 * see an interrupt when the pipe is disabled.
1041 *
ab7ad7f6
KP		 1042 * On Gen4 and above:
1043 * wait for the pipe register state bit to turn off
1044 *
1045 * Otherwise:
1046 * wait for the display line value to settle (it usually
1047 * ends up stopping at the start of the next frame).
58e10eb9 1048 *
9d0498a2 1049 */
575f7ab7 1050static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1051{
575f7ab7 1052 struct drm_device *dev = crtc->base.dev;
9d0498a2 1053 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1054 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1055 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1056
1057 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1058 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1059
1060 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1061 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1062 100))
284637d9 1063 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1064 } else {
ab7ad7f6 1065 /* Wait for the display line to settle */
fbf49ea2 1066 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1067 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1068 }
79e53945
JB		 1069}
1070
b0ea7d37
DL		 1071/*
1072 * ibx_digital_port_connected - is the specified port connected?
1073 * @dev_priv: i915 private structure
1074 * @port: the port to test
1075 *
1076 * Returns true if @port is connected, false otherwise.
1077 */
1078bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1079 struct intel_digital_port *port)
1080{
1081 u32 bit;
1082
c36346e3 1083 if (HAS_PCH_IBX(dev_priv->dev)) {
eba905b2 1084 switch (port->port) {
c36346e3
DL		 1085 case PORT_B:
1086 bit = SDE_PORTB_HOTPLUG;
1087 break;
1088 case PORT_C:
1089 bit = SDE_PORTC_HOTPLUG;
1090 break;
1091 case PORT_D:
1092 bit = SDE_PORTD_HOTPLUG;
1093 break;
1094 default:
1095 return true;
1096 }
1097 } else {
eba905b2 1098 switch (port->port) {
c36346e3
DL		 1099 case PORT_B:
1100 bit = SDE_PORTB_HOTPLUG_CPT;
1101 break;
1102 case PORT_C:
1103 bit = SDE_PORTC_HOTPLUG_CPT;
1104 break;
1105 case PORT_D:
1106 bit = SDE_PORTD_HOTPLUG_CPT;
1107 break;
1108 default:
1109 return true;
1110 }
b0ea7d37
DL		 1111 }
1112
1113 return I915_READ(SDEISR) & bit;
1114}
1115
b24e7179
JB		 1116static const char *state_string(bool enabled)
1117{
1118 return enabled ? "on" : "off";
1119}
1120
1121/* Only for pre-ILK configs */
55607e8a
DV		 1122void assert_pll(struct drm_i915_private *dev_priv,
1123 enum pipe pipe, bool state)
b24e7179
JB		 1124{
1125 int reg;
1126 u32 val;
1127 bool cur_state;
1128
1129 reg = DPLL(pipe);
1130 val = I915_READ(reg);
1131 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1132 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1133 "PLL state assertion failure (expected %s, current %s)\n",
1134 state_string(state), state_string(cur_state));
1135}
b24e7179 1136
23538ef1
JN		 1137/* XXX: the dsi pll is shared between MIPI DSI ports */
1138static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1139{
1140 u32 val;
1141 bool cur_state;
1142
a580516d 1143 mutex_lock(&dev_priv->sb_lock);
23538ef1 1144 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
a580516d 1145 mutex_unlock(&dev_priv->sb_lock);
23538ef1
JN		 1146
1147 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1148 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1149 "DSI PLL state assertion failure (expected %s, current %s)\n",
1150 state_string(state), state_string(cur_state));
1151}
1152#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1153#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1154
55607e8a 1155struct intel_shared_dpll *
e2b78267
DV		 1156intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1157{
1158 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1159
6e3c9717 1160 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1161 return NULL;
1162
6e3c9717 1163 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1164}
1165
040484af 1166/* For ILK+ */
55607e8a
DV		 1167void assert_shared_dpll(struct drm_i915_private *dev_priv,
1168 struct intel_shared_dpll *pll,
1169 bool state)
040484af 1170{
040484af 1171 bool cur_state;
5358901f 1172 struct intel_dpll_hw_state hw_state;
040484af 1173
92b27b08 1174 if (WARN (!pll,
46edb027 1175 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1176 return;
ee7b9f93 1177
5358901f 1178 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1179 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1180 "%s assertion failure (expected %s, current %s)\n",
1181 pll->name, state_string(state), state_string(cur_state));
040484af 1182}
040484af
JB		 1183
1184static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1185 enum pipe pipe, bool state)
1186{
1187 int reg;
1188 u32 val;
1189 bool cur_state;
ad80a810
PZ		 1190 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1191 pipe);
040484af 1192
affa9354
PZ		 1193 if (HAS_DDI(dev_priv->dev)) {
1194 /* DDI does not have a specific FDI_TX register */
ad80a810 1195 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1196 val = I915_READ(reg);
ad80a810 1197 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1198 } else {
1199 reg = FDI_TX_CTL(pipe);
1200 val = I915_READ(reg);
1201 cur_state = !!(val & FDI_TX_ENABLE);
1202 }
e2c719b7 1203 I915_STATE_WARN(cur_state != state,
040484af
JB		 1204 "FDI TX state assertion failure (expected %s, current %s)\n",
1205 state_string(state), state_string(cur_state));
1206}
1207#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1208#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1209
1210static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1211 enum pipe pipe, bool state)
1212{
1213 int reg;
1214 u32 val;
1215 bool cur_state;
1216
d63fa0dc
PZ		 1217 reg = FDI_RX_CTL(pipe);
1218 val = I915_READ(reg);
1219 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1220 I915_STATE_WARN(cur_state != state,
040484af
JB		 1221 "FDI RX state assertion failure (expected %s, current %s)\n",
1222 state_string(state), state_string(cur_state));
1223}
1224#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1225#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1226
1227static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1228 enum pipe pipe)
1229{
1230 int reg;
1231 u32 val;
1232
1233 /* ILK FDI PLL is always enabled */
3d13ef2e 1234 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1235 return;
1236
bf507ef7 1237 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1238 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1239 return;
1240
040484af
JB		 1241 reg = FDI_TX_CTL(pipe);
1242 val = I915_READ(reg);
e2c719b7 1243 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1244}
1245
55607e8a
DV		 1246void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1247 enum pipe pipe, bool state)
040484af
JB		 1248{
1249 int reg;
1250 u32 val;
55607e8a 1251 bool cur_state;
040484af
JB		 1252
1253 reg = FDI_RX_CTL(pipe);
1254 val = I915_READ(reg);
55607e8a 1255 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1256 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1257 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1258 state_string(state), state_string(cur_state));
040484af
JB		 1259}
1260
b680c37a
DV		 1261void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1262 enum pipe pipe)
ea0760cf 1263{
bedd4dba
JN		 1264 struct drm_device *dev = dev_priv->dev;
1265 int pp_reg;
ea0760cf
JB		 1266 u32 val;
1267 enum pipe panel_pipe = PIPE_A;
0de3b485 1268 bool locked = true;
ea0760cf 1269
bedd4dba
JN		 1270 if (WARN_ON(HAS_DDI(dev)))
1271 return;
1272
1273 if (HAS_PCH_SPLIT(dev)) {
1274 u32 port_sel;
1275
ea0760cf 1276 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1277 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1278
1279 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1280 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1281 panel_pipe = PIPE_B;
1282 /* XXX: else fix for eDP */
1283 } else if (IS_VALLEYVIEW(dev)) {
1284 /* presumably write lock depends on pipe, not port select */
1285 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1286 panel_pipe = pipe;
ea0760cf
JB		 1287 } else {
1288 pp_reg = PP_CONTROL;
bedd4dba
JN		 1289 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1290 panel_pipe = PIPE_B;
ea0760cf
JB		 1291 }
1292
1293 val = I915_READ(pp_reg);
1294 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1295 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1296 locked = false;
1297
e2c719b7 1298 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1299 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1300 pipe_name(pipe));
ea0760cf
JB		 1301}
1302
93ce0ba6
JN		 1303static void assert_cursor(struct drm_i915_private *dev_priv,
1304 enum pipe pipe, bool state)
1305{
1306 struct drm_device *dev = dev_priv->dev;
1307 bool cur_state;
1308
d9d82081 1309 if (IS_845G(dev) || IS_I865G(dev))
93ce0ba6 1310 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
d9d82081 1311 else
5efb3e28 1312 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1313
e2c719b7 1314 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1315 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1316 pipe_name(pipe), state_string(state), state_string(cur_state));
1317}
1318#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1319#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1320
b840d907
JB		 1321void assert_pipe(struct drm_i915_private *dev_priv,
1322 enum pipe pipe, bool state)
b24e7179
JB		 1323{
1324 int reg;
1325 u32 val;
63d7bbe9 1326 bool cur_state;
702e7a56
PZ		 1327 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1328 pipe);
b24e7179 1329
b6b5d049
VS		 1330 /* if we need the pipe quirk it must be always on */
1331 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1332 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1333 state = true;
1334
f458ebbc 1335 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1336 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1337 cur_state = false;
1338 } else {
1339 reg = PIPECONF(cpu_transcoder);
1340 val = I915_READ(reg);
1341 cur_state = !!(val & PIPECONF_ENABLE);
1342 }
1343
e2c719b7 1344 I915_STATE_WARN(cur_state != state,
63d7bbe9 1345 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1346 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1347}
1348
931872fc
CW		 1349static void assert_plane(struct drm_i915_private *dev_priv,
1350 enum plane plane, bool state)
b24e7179
JB		 1351{
1352 int reg;
1353 u32 val;
931872fc 1354 bool cur_state;
b24e7179
JB		 1355
1356 reg = DSPCNTR(plane);
1357 val = I915_READ(reg);
931872fc 1358 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1359 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1360 "plane %c assertion failure (expected %s, current %s)\n",
1361 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1362}
1363
931872fc
CW		 1364#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1365#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1366
b24e7179
JB		 1367static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1368 enum pipe pipe)
1369{
653e1026 1370 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1371 int reg, i;
1372 u32 val;
1373 int cur_pipe;
1374
653e1026
VS		 1375 /* Primary planes are fixed to pipes on gen4+ */
1376 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1377 reg = DSPCNTR(pipe);
1378 val = I915_READ(reg);
e2c719b7 1379 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1380 "plane %c assertion failure, should be disabled but not\n",
1381 plane_name(pipe));
19ec1358 1382 return;
28c05794 1383 }
19ec1358 1384
b24e7179 1385 /* Need to check both planes against the pipe */
055e393f 1386 for_each_pipe(dev_priv, i) {
b24e7179
JB		 1387 reg = DSPCNTR(i);
1388 val = I915_READ(reg);
1389 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1390 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1391 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1392 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1393 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1394 }
1395}
1396
19332d7a
JB		 1397static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1398 enum pipe pipe)
1399{
20674eef 1400 struct drm_device *dev = dev_priv->dev;
1fe47785 1401 int reg, sprite;
19332d7a
JB		 1402 u32 val;
1403
7feb8b88 1404 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1405 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1406 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1407 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1408 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1409 sprite, pipe_name(pipe));
1410 }
1411 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1412 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1413 reg = SPCNTR(pipe, sprite);
20674eef 1414 val = I915_READ(reg);
e2c719b7 1415 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1416 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1417 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1418 }
1419 } else if (INTEL_INFO(dev)->gen >= 7) {
1420 reg = SPRCTL(pipe);
19332d7a 1421 val = I915_READ(reg);
e2c719b7 1422 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1423 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1424 plane_name(pipe), pipe_name(pipe));
1425 } else if (INTEL_INFO(dev)->gen >= 5) {
1426 reg = DVSCNTR(pipe);
19332d7a 1427 val = I915_READ(reg);
e2c719b7 1428 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1429 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1430 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1431 }
1432}
1433
08c71e5e
VS		 1434static void assert_vblank_disabled(struct drm_crtc *crtc)
1435{
e2c719b7 1436 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1437 drm_crtc_vblank_put(crtc);
1438}
1439
89eff4be 1440static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1441{
1442 u32 val;
1443 bool enabled;
1444
e2c719b7 1445 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1446
92f2584a
JB		 1447 val = I915_READ(PCH_DREF_CONTROL);
1448 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1449 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1450 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1451}
1452
ab9412ba
DV		 1453static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1454 enum pipe pipe)
92f2584a
JB		 1455{
1456 int reg;
1457 u32 val;
1458 bool enabled;
1459
ab9412ba 1460 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1461 val = I915_READ(reg);
1462 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1463 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1464 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1465 pipe_name(pipe));
92f2584a
JB		 1466}
1467
4e634389
KP		 1468static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1469 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1470{
1471 if ((val & DP_PORT_EN) == 0)
1472 return false;
1473
1474 if (HAS_PCH_CPT(dev_priv->dev)) {
1475 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1476 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1477 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1478 return false;
44f37d1f
CML		 1479 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1480 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1481 return false;
f0575e92
KP		 1482 } else {
1483 if ((val & DP_PIPE_MASK) != (pipe << 30))
1484 return false;
1485 }
1486 return true;
1487}
1488
1519b995
KP		 1489static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1490 enum pipe pipe, u32 val)
1491{
dc0fa718 1492 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1493 return false;
1494
1495 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1496 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1497 return false;
44f37d1f
CML		 1498 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1499 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1500 return false;
1519b995 1501 } else {
dc0fa718 1502 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1503 return false;
1504 }
1505 return true;
1506}
1507
1508static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1509 enum pipe pipe, u32 val)
1510{
1511 if ((val & LVDS_PORT_EN) == 0)
1512 return false;
1513
1514 if (HAS_PCH_CPT(dev_priv->dev)) {
1515 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1516 return false;
1517 } else {
1518 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1519 return false;
1520 }
1521 return true;
1522}
1523
1524static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1525 enum pipe pipe, u32 val)
1526{
1527 if ((val & ADPA_DAC_ENABLE) == 0)
1528 return false;
1529 if (HAS_PCH_CPT(dev_priv->dev)) {
1530 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1531 return false;
1532 } else {
1533 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1534 return false;
1535 }
1536 return true;
1537}
1538
291906f1 1539static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1540 enum pipe pipe, int reg, u32 port_sel)
291906f1 1541{
47a05eca 1542 u32 val = I915_READ(reg);
e2c719b7 1543 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1544 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1545 reg, pipe_name(pipe));
de9a35ab 1546
e2c719b7 1547 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1548 && (val & DP_PIPEB_SELECT),
de9a35ab 1549 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1550}
1551
1552static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1553 enum pipe pipe, int reg)
1554{
47a05eca 1555 u32 val = I915_READ(reg);
e2c719b7 1556 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1557 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1558 reg, pipe_name(pipe));
de9a35ab 1559
e2c719b7 1560 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1561 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1562 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1563}
1564
1565static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1566 enum pipe pipe)
1567{
1568 int reg;
1569 u32 val;
291906f1 1570
f0575e92
KP		 1571 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1572 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1573 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1574
1575 reg = PCH_ADPA;
1576 val = I915_READ(reg);
e2c719b7 1577 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1578 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1579 pipe_name(pipe));
291906f1
JB		 1580
1581 reg = PCH_LVDS;
1582 val = I915_READ(reg);
e2c719b7 1583 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1584 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1585 pipe_name(pipe));
291906f1 1586
e2debe91
PZ		 1587 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1588 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1589 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1590}
1591
40e9cf64
JB		 1592static void intel_init_dpio(struct drm_device *dev)
1593{
1594 struct drm_i915_private *dev_priv = dev->dev_private;
1595
1596 if (!IS_VALLEYVIEW(dev))
1597 return;
1598
a09caddd
CML		 1599 /*
1600 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1601 * CHV x1 PHY (DP/HDMI D)
1602 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1603 */
1604 if (IS_CHERRYVIEW(dev)) {
1605 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1606 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1607 } else {
1608 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1609 }
5382f5f3
JB		 1610}
1611
d288f65f 1612static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1613 const struct intel_crtc_state *pipe_config)
87442f73 1614{
426115cf
DV		 1615 struct drm_device *dev = crtc->base.dev;
1616 struct drm_i915_private *dev_priv = dev->dev_private;
1617 int reg = DPLL(crtc->pipe);
d288f65f 1618 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1619
426115cf 1620 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1621
1622 /* No really, not for ILK+ */
1623 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1624
1625 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1626 if (IS_MOBILE(dev_priv->dev))
426115cf 1627 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1628
426115cf
DV		 1629 I915_WRITE(reg, dpll);
1630 POSTING_READ(reg);
1631 udelay(150);
1632
1633 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1634 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1635
d288f65f 1636 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1637 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1638
1639 /* We do this three times for luck */
426115cf 1640 I915_WRITE(reg, dpll);
87442f73
DV		 1641 POSTING_READ(reg);
1642 udelay(150); /* wait for warmup */
426115cf 1643 I915_WRITE(reg, dpll);
87442f73
DV		 1644 POSTING_READ(reg);
1645 udelay(150); /* wait for warmup */
426115cf 1646 I915_WRITE(reg, dpll);
87442f73
DV		 1647 POSTING_READ(reg);
1648 udelay(150); /* wait for warmup */
1649}
1650
d288f65f 1651static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1652 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1653{
1654 struct drm_device *dev = crtc->base.dev;
1655 struct drm_i915_private *dev_priv = dev->dev_private;
1656 int pipe = crtc->pipe;
1657 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1658 u32 tmp;
1659
1660 assert_pipe_disabled(dev_priv, crtc->pipe);
1661
1662 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1663
a580516d 1664 mutex_lock(&dev_priv->sb_lock);
9d556c99
CML		 1665
1666 /* Enable back the 10bit clock to display controller */
1667 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1668 tmp |= DPIO_DCLKP_EN;
1669 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1670
54433e91
VS		 1671 mutex_unlock(&dev_priv->sb_lock);
1672
9d556c99
CML		 1673 /*
1674 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1675 */
1676 udelay(1);
1677
1678 /* Enable PLL */
d288f65f 1679 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1680
1681 /* Check PLL is locked */
a11b0703 1682 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1683 DRM_ERROR("PLL %d failed to lock\n", pipe);
1684
a11b0703 1685 /* not sure when this should be written */
d288f65f 1686 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703 1687 POSTING_READ(DPLL_MD(pipe));
9d556c99
CML		 1688}
1689
1c4e0274
VS		 1690static int intel_num_dvo_pipes(struct drm_device *dev)
1691{
1692 struct intel_crtc *crtc;
1693 int count = 0;
1694
1695 for_each_intel_crtc(dev, crtc)
1696 count += crtc->active &&
409ee761 1697 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1698
1699 return count;
1700}
1701
66e3d5c0 1702static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1703{
66e3d5c0
DV		 1704 struct drm_device *dev = crtc->base.dev;
1705 struct drm_i915_private *dev_priv = dev->dev_private;
1706 int reg = DPLL(crtc->pipe);
6e3c9717 1707 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1708
66e3d5c0 1709 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1710
63d7bbe9 1711 /* No really, not for ILK+ */
3d13ef2e 1712 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1713
1714 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1715 if (IS_MOBILE(dev) && !IS_I830(dev))
1716 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1717
1c4e0274
VS		 1718 /* Enable DVO 2x clock on both PLLs if necessary */
1719 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1720 /*
1721 * It appears to be important that we don't enable this
1722 * for the current pipe before otherwise configuring the
1723 * PLL. No idea how this should be handled if multiple
1724 * DVO outputs are enabled simultaneosly.
1725 */
1726 dpll |= DPLL_DVO_2X_MODE;
1727 I915_WRITE(DPLL(!crtc->pipe),
1728 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1729 }
66e3d5c0
DV		 1730
1731 /* Wait for the clocks to stabilize. */
1732 POSTING_READ(reg);
1733 udelay(150);
1734
1735 if (INTEL_INFO(dev)->gen >= 4) {
1736 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1737 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1738 } else {
1739 /* The pixel multiplier can only be updated once the
1740 * DPLL is enabled and the clocks are stable.
1741 *
1742 * So write it again.
1743 */
1744 I915_WRITE(reg, dpll);
1745 }
63d7bbe9
JB		 1746
1747 /* We do this three times for luck */
66e3d5c0 1748 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1749 POSTING_READ(reg);
1750 udelay(150); /* wait for warmup */
66e3d5c0 1751 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1752 POSTING_READ(reg);
1753 udelay(150); /* wait for warmup */
66e3d5c0 1754 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1755 POSTING_READ(reg);
1756 udelay(150); /* wait for warmup */
1757}
1758
1759/**
50b44a44 1760 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1761 * @dev_priv: i915 private structure
1762 * @pipe: pipe PLL to disable
1763 *
1764 * Disable the PLL for @pipe, making sure the pipe is off first.
1765 *
1766 * Note! This is for pre-ILK only.
1767 */
1c4e0274 1768static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1769{
1c4e0274
VS		 1770 struct drm_device *dev = crtc->base.dev;
1771 struct drm_i915_private *dev_priv = dev->dev_private;
1772 enum pipe pipe = crtc->pipe;
1773
1774 /* Disable DVO 2x clock on both PLLs if necessary */
1775 if (IS_I830(dev) &&
409ee761 1776 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1c4e0274
VS		 1777 intel_num_dvo_pipes(dev) == 1) {
1778 I915_WRITE(DPLL(PIPE_B),
1779 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1780 I915_WRITE(DPLL(PIPE_A),
1781 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1782 }
1783
b6b5d049
VS		 1784 /* Don't disable pipe or pipe PLLs if needed */
1785 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1786 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1787 return;
1788
1789 /* Make sure the pipe isn't still relying on us */
1790 assert_pipe_disabled(dev_priv, pipe);
1791
50b44a44
DV		 1792 I915_WRITE(DPLL(pipe), 0);
1793 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1794}
1795
f6071166
JB		 1796static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1797{
1798 u32 val = 0;
1799
1800 /* Make sure the pipe isn't still relying on us */
1801 assert_pipe_disabled(dev_priv, pipe);
1802
e5cbfbfb
ID		 1803 /*
1804 * Leave integrated clock source and reference clock enabled for pipe B.
1805 * The latter is needed for VGA hotplug / manual detection.
1806 */
f6071166 1807 if (pipe == PIPE_B)
e5cbfbfb 1808 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
f6071166
JB		 1809 I915_WRITE(DPLL(pipe), val);
1810 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1811
1812}
1813
1814static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1815{
d752048d 1816 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1817 u32 val;
1818
a11b0703
VS		 1819 /* Make sure the pipe isn't still relying on us */
1820 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1821
a11b0703 1822 /* Set PLL en = 0 */
d17ec4ce 1823 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
a11b0703
VS		 1824 if (pipe != PIPE_A)
1825 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1826 I915_WRITE(DPLL(pipe), val);
1827 POSTING_READ(DPLL(pipe));
d752048d 1828
a580516d 1829 mutex_lock(&dev_priv->sb_lock);
d752048d
VS		 1830
1831 /* Disable 10bit clock to display controller */
1832 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1833 val &= ~DPIO_DCLKP_EN;
1834 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1835
61407f6d
VS		 1836 /* disable left/right clock distribution */
1837 if (pipe != PIPE_B) {
1838 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1839 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1840 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1841 } else {
1842 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1843 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1844 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1845 }
1846
a580516d 1847 mutex_unlock(&dev_priv->sb_lock);
f6071166
JB		 1848}
1849
e4607fcf 1850void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
9b6de0a1
VS		 1851 struct intel_digital_port *dport,
1852 unsigned int expected_mask)
89b667f8
JB		 1853{
1854 u32 port_mask;
00fc31b7 1855 int dpll_reg;
89b667f8 1856
e4607fcf
CML		 1857 switch (dport->port) {
1858 case PORT_B:
89b667f8 1859 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1860 dpll_reg = DPLL(0);
e4607fcf
CML		 1861 break;
1862 case PORT_C:
89b667f8 1863 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7 1864 dpll_reg = DPLL(0);
9b6de0a1 1865 expected_mask <<= 4;
00fc31b7
CML		 1866 break;
1867 case PORT_D:
1868 port_mask = DPLL_PORTD_READY_MASK;
1869 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1870 break;
1871 default:
1872 BUG();
1873 }
89b667f8 1874
9b6de0a1
VS		 1875 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1876 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1877 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
89b667f8
JB		 1878}
1879
b14b1055
DV		 1880static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1881{
1882 struct drm_device *dev = crtc->base.dev;
1883 struct drm_i915_private *dev_priv = dev->dev_private;
1884 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1885
be19f0ff
CW		 1886 if (WARN_ON(pll == NULL))
1887 return;
1888
3e369b76 1889 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1890 if (pll->active == 0) {
1891 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1892 WARN_ON(pll->on);
1893 assert_shared_dpll_disabled(dev_priv, pll);
1894
1895 pll->mode_set(dev_priv, pll);
1896 }
1897}
1898
92f2584a 1899/**
85b3894f 1900 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1901 * @dev_priv: i915 private structure
1902 * @pipe: pipe PLL to enable
1903 *
1904 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1905 * drives the transcoder clock.
1906 */
85b3894f 1907static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1908{
3d13ef2e
DL		 1909 struct drm_device *dev = crtc->base.dev;
1910 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1911 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1912
87a875bb 1913 if (WARN_ON(pll == NULL))
48da64a8
CW		 1914 return;
1915
3e369b76 1916 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1917 return;
ee7b9f93 1918
74dd6928 1919 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1920 pll->name, pll->active, pll->on,
e2b78267 1921 crtc->base.base.id);
92f2584a 1922
cdbd2316
DV		 1923 if (pll->active++) {
1924 WARN_ON(!pll->on);
e9d6944e 1925 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1926 return;
1927 }
f4a091c7 1928 WARN_ON(pll->on);
ee7b9f93 1929
bd2bb1b9
PZ		 1930 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1931
46edb027 1932 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1933 pll->enable(dev_priv, pll);
ee7b9f93 1934 pll->on = true;
92f2584a
JB		 1935}
1936
f6daaec2 1937static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1938{
3d13ef2e
DL		 1939 struct drm_device *dev = crtc->base.dev;
1940 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1941 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1942
92f2584a 1943 /* PCH only available on ILK+ */
3d13ef2e 1944 BUG_ON(INTEL_INFO(dev)->gen < 5);
87a875bb 1945 if (WARN_ON(pll == NULL))
ee7b9f93 1946 return;
92f2584a 1947
3e369b76 1948 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1949 return;
7a419866 1950
46edb027
DV		 1951 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1952 pll->name, pll->active, pll->on,
e2b78267 1953 crtc->base.base.id);
7a419866 1954
48da64a8 1955 if (WARN_ON(pll->active == 0)) {
e9d6944e 1956 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1957 return;
1958 }
1959
e9d6944e 1960 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1961 WARN_ON(!pll->on);
cdbd2316 1962 if (--pll->active)
7a419866 1963 return;
ee7b9f93 1964
46edb027 1965 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1966 pll->disable(dev_priv, pll);
ee7b9f93 1967 pll->on = false;
bd2bb1b9
PZ		 1968
1969 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1970}
1971
b8a4f404
PZ		 1972static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1973 enum pipe pipe)
040484af 1974{
23670b32 1975 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1976 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1977 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1978 uint32_t reg, val, pipeconf_val;
040484af
JB		 1979
1980 /* PCH only available on ILK+ */
55522f37 1981 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1982
1983 /* Make sure PCH DPLL is enabled */
e72f9fbf 1984 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1985 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1986
1987 /* FDI must be feeding us bits for PCH ports */
1988 assert_fdi_tx_enabled(dev_priv, pipe);
1989 assert_fdi_rx_enabled(dev_priv, pipe);
1990
23670b32
DV		 1991 if (HAS_PCH_CPT(dev)) {
1992 /* Workaround: Set the timing override bit before enabling the
1993 * pch transcoder. */
1994 reg = TRANS_CHICKEN2(pipe);
1995 val = I915_READ(reg);
1996 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1997 I915_WRITE(reg, val);
59c859d6 1998 }
23670b32 1999
ab9412ba 2000 reg = PCH_TRANSCONF(pipe);
040484af 2001 val = I915_READ(reg);
5f7f726d 2002 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 2003
2004 if (HAS_PCH_IBX(dev_priv->dev)) {
2005 /*
2006 * make the BPC in transcoder be consistent with
2007 * that in pipeconf reg.
2008 */
dfd07d72
DV		 2009 val &= ~PIPECONF_BPC_MASK;
2010 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 2011 }
5f7f726d
PZ		 2012
2013 val &= ~TRANS_INTERLACE_MASK;
2014 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 2015 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 2016 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 2017 val |= TRANS_LEGACY_INTERLACED_ILK;
2018 else
2019 val |= TRANS_INTERLACED;
5f7f726d
PZ		 2020 else
2021 val |= TRANS_PROGRESSIVE;
2022
040484af
JB		 2023 I915_WRITE(reg, val | TRANS_ENABLE);
2024 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 2025 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 2026}
2027
8fb033d7 2028static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 2029 enum transcoder cpu_transcoder)
040484af 2030{
8fb033d7 2031 u32 val, pipeconf_val;
8fb033d7
PZ		 2032
2033 /* PCH only available on ILK+ */
55522f37 2034 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 2035
8fb033d7 2036 /* FDI must be feeding us bits for PCH ports */
1a240d4d 2037 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2038 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2039
223a6fdf
PZ		 2040 /* Workaround: set timing override bit. */
2041 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2042 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 2043 I915_WRITE(_TRANSA_CHICKEN2, val);
2044
25f3ef11 2045 val = TRANS_ENABLE;
937bb610 2046 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2047
9a76b1c6
PZ		 2048 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2049 PIPECONF_INTERLACED_ILK)
a35f2679 2050 val |= TRANS_INTERLACED;
8fb033d7
PZ		 2051 else
2052 val |= TRANS_PROGRESSIVE;
2053
ab9412ba
DV		 2054 I915_WRITE(LPT_TRANSCONF, val);
2055 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2056 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 2057}
2058
b8a4f404
PZ		 2059static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2060 enum pipe pipe)
040484af 2061{
23670b32
DV		 2062 struct drm_device *dev = dev_priv->dev;
2063 uint32_t reg, val;
040484af
JB		 2064
2065 /* FDI relies on the transcoder */
2066 assert_fdi_tx_disabled(dev_priv, pipe);
2067 assert_fdi_rx_disabled(dev_priv, pipe);
2068
291906f1
JB		 2069 /* Ports must be off as well */
2070 assert_pch_ports_disabled(dev_priv, pipe);
2071
ab9412ba 2072 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2073 val = I915_READ(reg);
2074 val &= ~TRANS_ENABLE;
2075 I915_WRITE(reg, val);
2076 /* wait for PCH transcoder off, transcoder state */
2077 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2078 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2079
2080 if (!HAS_PCH_IBX(dev)) {
2081 /* Workaround: Clear the timing override chicken bit again. */
2082 reg = TRANS_CHICKEN2(pipe);
2083 val = I915_READ(reg);
2084 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2085 I915_WRITE(reg, val);
2086 }
040484af
JB		 2087}
2088
ab4d966c 2089static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2090{
8fb033d7
PZ		 2091 u32 val;
2092
ab9412ba 2093 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2094 val &= ~TRANS_ENABLE;
ab9412ba 2095 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2096 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2097 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2098 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2099
2100 /* Workaround: clear timing override bit. */
2101 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2102 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 2103 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 2104}
2105
b24e7179 2106/**
309cfea8 2107 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2108 * @crtc: crtc responsible for the pipe
b24e7179 2109 *
0372264a 2110 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2111 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2112 */
e1fdc473 2113static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2114{
0372264a
PZ		 2115 struct drm_device *dev = crtc->base.dev;
2116 struct drm_i915_private *dev_priv = dev->dev_private;
2117 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2118 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2119 pipe);
1a240d4d 2120 enum pipe pch_transcoder;
b24e7179
JB		 2121 int reg;
2122 u32 val;
2123
58c6eaa2 2124 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2125 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2126 assert_sprites_disabled(dev_priv, pipe);
2127
681e5811 2128 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2129 pch_transcoder = TRANSCODER_A;
2130 else
2131 pch_transcoder = pipe;
2132
b24e7179
JB		 2133 /*
2134 * A pipe without a PLL won't actually be able to drive bits from
2135 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2136 * need the check.
2137 */
50360403 2138 if (HAS_GMCH_DISPLAY(dev_priv->dev))
409ee761 2139 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2140 assert_dsi_pll_enabled(dev_priv);
2141 else
2142 assert_pll_enabled(dev_priv, pipe);
040484af 2143 else {
6e3c9717 2144 if (crtc->config->has_pch_encoder) {
040484af 2145 /* if driving the PCH, we need FDI enabled */
cc391bbb 2146 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2147 assert_fdi_tx_pll_enabled(dev_priv,
2148 (enum pipe) cpu_transcoder);
040484af
JB		 2149 }
2150 /* FIXME: assert CPU port conditions for SNB+ */
2151 }
b24e7179 2152
702e7a56 2153 reg = PIPECONF(cpu_transcoder);
b24e7179 2154 val = I915_READ(reg);
7ad25d48 2155 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2156 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2157 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2158 return;
7ad25d48 2159 }
00d70b15
CW		 2160
2161 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2162 POSTING_READ(reg);
b24e7179
JB		 2163}
2164
2165/**
309cfea8 2166 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2167 * @crtc: crtc whose pipes is to be disabled
b24e7179 2168 *
575f7ab7
VS		 2169 * Disable the pipe of @crtc, making sure that various hardware
2170 * specific requirements are met, if applicable, e.g. plane
2171 * disabled, panel fitter off, etc.
b24e7179
JB		 2172 *
2173 * Will wait until the pipe has shut down before returning.
2174 */
575f7ab7 2175static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2176{
575f7ab7 2177 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2178 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2179 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2180 int reg;
2181 u32 val;
2182
2183 /*
2184 * Make sure planes won't keep trying to pump pixels to us,
2185 * or we might hang the display.
2186 */
2187 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2188 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2189 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2190
702e7a56 2191 reg = PIPECONF(cpu_transcoder);
b24e7179 2192 val = I915_READ(reg);
00d70b15
CW		 2193 if ((val & PIPECONF_ENABLE) == 0)
2194 return;
2195
67adc644
VS		 2196 /*
2197 * Double wide has implications for planes
2198 * so best keep it disabled when not needed.
2199 */
6e3c9717 2200 if (crtc->config->double_wide)
67adc644
VS		 2201 val &= ~PIPECONF_DOUBLE_WIDE;
2202
2203 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2204 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2205 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2206 val &= ~PIPECONF_ENABLE;
2207
2208 I915_WRITE(reg, val);
2209 if ((val & PIPECONF_ENABLE) == 0)
2210 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2211}
2212
2213/**
262ca2b0 2214 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
fdd508a6
VS		 2215 * @plane: plane to be enabled
2216 * @crtc: crtc for the plane
b24e7179 2217 *
fdd508a6 2218 * Enable @plane on @crtc, making sure that the pipe is running first.
b24e7179 2219 */
fdd508a6
VS		 2220static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2221 struct drm_crtc *crtc)
b24e7179 2222{
fdd508a6
VS		 2223 struct drm_device *dev = plane->dev;
2224 struct drm_i915_private *dev_priv = dev->dev_private;
2225 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b24e7179
JB		 2226
2227 /* If the pipe isn't enabled, we can't pump pixels and may hang */
fdd508a6 2228 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
b70709a6 2229 to_intel_plane_state(plane->state)->visible = true;
939c2fe8 2230
fdd508a6
VS		 2231 dev_priv->display.update_primary_plane(crtc, plane->fb,
2232 crtc->x, crtc->y);
b24e7179
JB		 2233}
2234
693db184
CW		 2235static bool need_vtd_wa(struct drm_device *dev)
2236{
2237#ifdef CONFIG_INTEL_IOMMU
2238 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2239 return true;
2240#endif
2241 return false;
2242}
2243
50470bb0 2244unsigned int
6761dd31
TU		 2245intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2246 uint64_t fb_format_modifier)
a57ce0b2 2247{
6761dd31
TU		 2248 unsigned int tile_height;
2249 uint32_t pixel_bytes;
a57ce0b2 2250
b5d0e9bf
DL		 2251 switch (fb_format_modifier) {
2252 case DRM_FORMAT_MOD_NONE:
2253 tile_height = 1;
2254 break;
2255 case I915_FORMAT_MOD_X_TILED:
2256 tile_height = IS_GEN2(dev) ? 16 : 8;
2257 break;
2258 case I915_FORMAT_MOD_Y_TILED:
2259 tile_height = 32;
2260 break;
2261 case I915_FORMAT_MOD_Yf_TILED:
6761dd31
TU		 2262 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2263 switch (pixel_bytes) {
b5d0e9bf 2264 default:
6761dd31 2265 case 1:
b5d0e9bf
DL		 2266 tile_height = 64;
2267 break;
6761dd31
TU		 2268 case 2:
2269 case 4:
b5d0e9bf
DL		 2270 tile_height = 32;
2271 break;
6761dd31 2272 case 8:
b5d0e9bf
DL		 2273 tile_height = 16;
2274 break;
6761dd31 2275 case 16:
b5d0e9bf
DL		 2276 WARN_ONCE(1,
2277 "128-bit pixels are not supported for display!");
2278 tile_height = 16;
2279 break;
2280 }
2281 break;
2282 default:
2283 MISSING_CASE(fb_format_modifier);
2284 tile_height = 1;
2285 break;
2286 }
091df6cb 2287
6761dd31
TU		 2288 return tile_height;
2289}
2290
2291unsigned int
2292intel_fb_align_height(struct drm_device *dev, unsigned int height,
2293 uint32_t pixel_format, uint64_t fb_format_modifier)
2294{
2295 return ALIGN(height, intel_tile_height(dev, pixel_format,
2296 fb_format_modifier));
a57ce0b2
JB		 2297}
2298
f64b98cd
TU		 2299static int
2300intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2301 const struct drm_plane_state *plane_state)
2302{
50470bb0 2303 struct intel_rotation_info *info = &view->rotation_info;
50470bb0 2304
f64b98cd
TU		 2305 *view = i915_ggtt_view_normal;
2306
50470bb0
TU		 2307 if (!plane_state)
2308 return 0;
2309
121920fa 2310 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2311 return 0;
2312
9abc4648 2313 *view = i915_ggtt_view_rotated;
50470bb0
TU		 2314
2315 info->height = fb->height;
2316 info->pixel_format = fb->pixel_format;
2317 info->pitch = fb->pitches[0];
2318 info->fb_modifier = fb->modifier[0];
2319
f64b98cd
TU		 2320 return 0;
2321}
2322
127bd2ac 2323int
850c4cdc
TU		 2324intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2325 struct drm_framebuffer *fb,
82bc3b2d 2326 const struct drm_plane_state *plane_state,
a4872ba6 2327 struct intel_engine_cs *pipelined)
6b95a207 2328{
850c4cdc 2329 struct drm_device *dev = fb->dev;
ce453d81 2330 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2331 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2332 struct i915_ggtt_view view;
6b95a207
KH		 2333 u32 alignment;
2334 int ret;
2335
ebcdd39e
MR		 2336 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2337
7b911adc
TU		 2338 switch (fb->modifier[0]) {
2339 case DRM_FORMAT_MOD_NONE:
1fada4cc
DL		 2340 if (INTEL_INFO(dev)->gen >= 9)
2341 alignment = 256 * 1024;
2342 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
534843da 2343 alignment = 128 * 1024;
a6c45cf0 2344 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 2345 alignment = 4 * 1024;
2346 else
2347 alignment = 64 * 1024;
6b95a207 2348 break;
7b911adc 2349 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2350 if (INTEL_INFO(dev)->gen >= 9)
2351 alignment = 256 * 1024;
2352 else {
2353 /* pin() will align the object as required by fence */
2354 alignment = 0;
2355 }
6b95a207 2356 break;
7b911adc 2357 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2358 case I915_FORMAT_MOD_Yf_TILED:
2359 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2360 "Y tiling bo slipped through, driver bug!\n"))
2361 return -EINVAL;
2362 alignment = 1 * 1024 * 1024;
2363 break;
6b95a207 2364 default:
7b911adc
TU		 2365 MISSING_CASE(fb->modifier[0]);
2366 return -EINVAL;
6b95a207
KH		 2367 }
2368
f64b98cd
TU		 2369 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2370 if (ret)
2371 return ret;
2372
693db184
CW		 2373 /* Note that the w/a also requires 64 PTE of padding following the
2374 * bo. We currently fill all unused PTE with the shadow page and so
2375 * we should always have valid PTE following the scanout preventing
2376 * the VT-d warning.
2377 */
2378 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2379 alignment = 256 * 1024;
2380
d6dd6843
PZ		 2381 /*
2382 * Global gtt pte registers are special registers which actually forward
2383 * writes to a chunk of system memory. Which means that there is no risk
2384 * that the register values disappear as soon as we call
2385 * intel_runtime_pm_put(), so it is correct to wrap only the
2386 * pin/unpin/fence and not more.
2387 */
2388 intel_runtime_pm_get(dev_priv);
2389
ce453d81 2390 dev_priv->mm.interruptible = false;
e6617330 2391 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
f64b98cd 2392 &view);
48b956c5 2393 if (ret)
ce453d81 2394 goto err_interruptible;
6b95a207
KH		 2395
2396 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2397 * fence, whereas 965+ only requires a fence if using
2398 * framebuffer compression. For simplicity, we always install
2399 * a fence as the cost is not that onerous.
2400 */
06d98131 2401 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2402 if (ret)
2403 goto err_unpin;
1690e1eb 2404
9a5a53b3 2405 i915_gem_object_pin_fence(obj);
6b95a207 2406
ce453d81 2407 dev_priv->mm.interruptible = true;
d6dd6843 2408 intel_runtime_pm_put(dev_priv);
6b95a207 2409 return 0;
48b956c5
CW		 2410
2411err_unpin:
f64b98cd 2412 i915_gem_object_unpin_from_display_plane(obj, &view);
ce453d81
CW		 2413err_interruptible:
2414 dev_priv->mm.interruptible = true;
d6dd6843 2415 intel_runtime_pm_put(dev_priv);
48b956c5 2416 return ret;
6b95a207
KH		 2417}
2418
82bc3b2d
TU		 2419static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2420 const struct drm_plane_state *plane_state)
1690e1eb 2421{
82bc3b2d 2422 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2423 struct i915_ggtt_view view;
2424 int ret;
82bc3b2d 2425
ebcdd39e
MR		 2426 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2427
f64b98cd
TU		 2428 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2429 WARN_ONCE(ret, "Couldn't get view from plane state!");
2430
1690e1eb 2431 i915_gem_object_unpin_fence(obj);
f64b98cd 2432 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2433}
2434
c2c75131
DV		 2435/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2436 * is assumed to be a power-of-two. */
bc752862
CW		 2437unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2438 unsigned int tiling_mode,
2439 unsigned int cpp,
2440 unsigned int pitch)
c2c75131 2441{
bc752862
CW		 2442 if (tiling_mode != I915_TILING_NONE) {
2443 unsigned int tile_rows, tiles;
c2c75131 2444
bc752862
CW		 2445 tile_rows = *y / 8;
2446 *y %= 8;
c2c75131 2447
bc752862
CW		 2448 tiles = *x / (512/cpp);
2449 *x %= 512/cpp;
2450
2451 return tile_rows * pitch * 8 + tiles * 4096;
2452 } else {
2453 unsigned int offset;
2454
2455 offset = *y * pitch + *x * cpp;
2456 *y = 0;
2457 *x = (offset & 4095) / cpp;
2458 return offset & -4096;
2459 }
c2c75131
DV		 2460}
2461
b35d63fa 2462static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2463{
2464 switch (format) {
2465 case DISPPLANE_8BPP:
2466 return DRM_FORMAT_C8;
2467 case DISPPLANE_BGRX555:
2468 return DRM_FORMAT_XRGB1555;
2469 case DISPPLANE_BGRX565:
2470 return DRM_FORMAT_RGB565;
2471 default:
2472 case DISPPLANE_BGRX888:
2473 return DRM_FORMAT_XRGB8888;
2474 case DISPPLANE_RGBX888:
2475 return DRM_FORMAT_XBGR8888;
2476 case DISPPLANE_BGRX101010:
2477 return DRM_FORMAT_XRGB2101010;
2478 case DISPPLANE_RGBX101010:
2479 return DRM_FORMAT_XBGR2101010;
2480 }
2481}
2482
bc8d7dff
DL		 2483static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2484{
2485 switch (format) {
2486 case PLANE_CTL_FORMAT_RGB_565:
2487 return DRM_FORMAT_RGB565;
2488 default:
2489 case PLANE_CTL_FORMAT_XRGB_8888:
2490 if (rgb_order) {
2491 if (alpha)
2492 return DRM_FORMAT_ABGR8888;
2493 else
2494 return DRM_FORMAT_XBGR8888;
2495 } else {
2496 if (alpha)
2497 return DRM_FORMAT_ARGB8888;
2498 else
2499 return DRM_FORMAT_XRGB8888;
2500 }
2501 case PLANE_CTL_FORMAT_XRGB_2101010:
2502 if (rgb_order)
2503 return DRM_FORMAT_XBGR2101010;
2504 else
2505 return DRM_FORMAT_XRGB2101010;
2506 }
2507}
2508
5724dbd1 2509static bool
f6936e29
DV		 2510intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2511 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2512{
2513 struct drm_device *dev = crtc->base.dev;
2514 struct drm_i915_gem_object *obj = NULL;
2515 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2516 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2517 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2518 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2519 PAGE_SIZE);
2520
2521 size_aligned -= base_aligned;
46f297fb 2522
ff2652ea
CW		 2523 if (plane_config->size == 0)
2524 return false;
2525
f37b5c2b
DV		 2526 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2527 base_aligned,
2528 base_aligned,
2529 size_aligned);
46f297fb 2530 if (!obj)
484b41dd 2531 return false;
46f297fb 2532
49af449b
DL		 2533 obj->tiling_mode = plane_config->tiling;
2534 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2535 obj->stride = fb->pitches[0];
46f297fb 2536
6bf129df
DL		 2537 mode_cmd.pixel_format = fb->pixel_format;
2538 mode_cmd.width = fb->width;
2539 mode_cmd.height = fb->height;
2540 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2541 mode_cmd.modifier[0] = fb->modifier[0];
2542 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2543
2544 mutex_lock(&dev->struct_mutex);
6bf129df 2545 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2546 &mode_cmd, obj)) {
46f297fb
JB		 2547 DRM_DEBUG_KMS("intel fb init failed\n");
2548 goto out_unref_obj;
2549 }
46f297fb 2550 mutex_unlock(&dev->struct_mutex);
484b41dd 2551
f6936e29 2552 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2553 return true;
46f297fb
JB		 2554
2555out_unref_obj:
2556 drm_gem_object_unreference(&obj->base);
2557 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2558 return false;
2559}
2560
afd65eb4
MR		 2561/* Update plane->state->fb to match plane->fb after driver-internal updates */
2562static void
2563update_state_fb(struct drm_plane *plane)
2564{
2565 if (plane->fb == plane->state->fb)
2566 return;
2567
2568 if (plane->state->fb)
2569 drm_framebuffer_unreference(plane->state->fb);
2570 plane->state->fb = plane->fb;
2571 if (plane->state->fb)
2572 drm_framebuffer_reference(plane->state->fb);
2573}
2574
5724dbd1 2575static void
f6936e29
DV		 2576intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2577 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2578{
2579 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2580 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2581 struct drm_crtc *c;
2582 struct intel_crtc *i;
2ff8fde1 2583 struct drm_i915_gem_object *obj;
88595ac9
DV		 2584 struct drm_plane *primary = intel_crtc->base.primary;
2585 struct drm_framebuffer *fb;
484b41dd 2586
2d14030b 2587 if (!plane_config->fb)
484b41dd
JB		 2588 return;
2589
f6936e29 2590 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2591 fb = &plane_config->fb->base;
2592 goto valid_fb;
f55548b5 2593 }
484b41dd 2594
2d14030b 2595 kfree(plane_config->fb);
484b41dd
JB		 2596
2597 /*
2598 * Failed to alloc the obj, check to see if we should share
2599 * an fb with another CRTC instead
2600 */
70e1e0ec 2601 for_each_crtc(dev, c) {
484b41dd
JB		 2602 i = to_intel_crtc(c);
2603
2604 if (c == &intel_crtc->base)
2605 continue;
2606
2ff8fde1
MR		 2607 if (!i->active)
2608 continue;
2609
88595ac9
DV		 2610 fb = c->primary->fb;
2611 if (!fb)
484b41dd
JB		 2612 continue;
2613
88595ac9 2614 obj = intel_fb_obj(fb);
2ff8fde1 2615 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2616 drm_framebuffer_reference(fb);
2617 goto valid_fb;
484b41dd
JB		 2618 }
2619 }
88595ac9
DV		 2620
2621 return;
2622
2623valid_fb:
2624 obj = intel_fb_obj(fb);
2625 if (obj->tiling_mode != I915_TILING_NONE)
2626 dev_priv->preserve_bios_swizzle = true;
2627
2628 primary->fb = fb;
2629 primary->state->crtc = &intel_crtc->base;
2630 primary->crtc = &intel_crtc->base;
2631 update_state_fb(primary);
2632 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
46f297fb
JB		 2633}
2634
29b9bde6
DV		 2635static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2636 struct drm_framebuffer *fb,
2637 int x, int y)
81255565
JB		 2638{
2639 struct drm_device *dev = crtc->dev;
2640 struct drm_i915_private *dev_priv = dev->dev_private;
2641 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2642 struct drm_plane *primary = crtc->primary;
2643 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2644 struct drm_i915_gem_object *obj;
81255565 2645 int plane = intel_crtc->plane;
e506a0c6 2646 unsigned long linear_offset;
81255565 2647 u32 dspcntr;
f45651ba 2648 u32 reg = DSPCNTR(plane);
48404c1e 2649 int pixel_size;
f45651ba 2650
b70709a6 2651 if (!visible || !fb) {
fdd508a6
VS		 2652 I915_WRITE(reg, 0);
2653 if (INTEL_INFO(dev)->gen >= 4)
2654 I915_WRITE(DSPSURF(plane), 0);
2655 else
2656 I915_WRITE(DSPADDR(plane), 0);
2657 POSTING_READ(reg);
2658 return;
2659 }
2660
c9ba6fad
VS		 2661 obj = intel_fb_obj(fb);
2662 if (WARN_ON(obj == NULL))
2663 return;
2664
2665 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2666
f45651ba
VS		 2667 dspcntr = DISPPLANE_GAMMA_ENABLE;
2668
fdd508a6 2669 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2670
2671 if (INTEL_INFO(dev)->gen < 4) {
2672 if (intel_crtc->pipe == PIPE_B)
2673 dspcntr |= DISPPLANE_SEL_PIPE_B;
2674
2675 /* pipesrc and dspsize control the size that is scaled from,
2676 * which should always be the user's requested size.
2677 */
2678 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2679 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2680 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2681 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2682 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2683 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2684 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2685 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2686 I915_WRITE(PRIMPOS(plane), 0);
2687 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2688 }
81255565 2689
57779d06
VS		 2690 switch (fb->pixel_format) {
2691 case DRM_FORMAT_C8:
81255565
JB		 2692 dspcntr |= DISPPLANE_8BPP;
2693 break;
57779d06 2694 case DRM_FORMAT_XRGB1555:
57779d06 2695 dspcntr |= DISPPLANE_BGRX555;
81255565 2696 break;
57779d06
VS		 2697 case DRM_FORMAT_RGB565:
2698 dspcntr |= DISPPLANE_BGRX565;
2699 break;
2700 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2701 dspcntr |= DISPPLANE_BGRX888;
2702 break;
2703 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2704 dspcntr |= DISPPLANE_RGBX888;
2705 break;
2706 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2707 dspcntr |= DISPPLANE_BGRX101010;
2708 break;
2709 case DRM_FORMAT_XBGR2101010:
57779d06 2710 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2711 break;
2712 default:
baba133a 2713 BUG();
81255565 2714 }
57779d06 2715
f45651ba
VS		 2716 if (INTEL_INFO(dev)->gen >= 4 &&
2717 obj->tiling_mode != I915_TILING_NONE)
2718 dspcntr |= DISPPLANE_TILED;
81255565 2719
de1aa629
VS		 2720 if (IS_G4X(dev))
2721 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2722
b9897127 2723 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2724
c2c75131
DV		 2725 if (INTEL_INFO(dev)->gen >= 4) {
2726 intel_crtc->dspaddr_offset =
bc752862 2727 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2728 pixel_size,
bc752862 2729 fb->pitches[0]);
c2c75131
DV		 2730 linear_offset -= intel_crtc->dspaddr_offset;
2731 } else {
e506a0c6 2732 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2733 }
e506a0c6 2734
8e7d688b 2735 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2736 dspcntr |= DISPPLANE_ROTATE_180;
2737
6e3c9717
ACO		 2738 x += (intel_crtc->config->pipe_src_w - 1);
2739 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2740
2741 /* Finding the last pixel of the last line of the display
2742 data and adding to linear_offset*/
2743 linear_offset +=
6e3c9717
ACO		 2744 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2745 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2746 }
2747
2748 I915_WRITE(reg, dspcntr);
2749
01f2c773 2750 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2751 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2752 I915_WRITE(DSPSURF(plane),
2753 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2754 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2755 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2756 } else
f343c5f6 2757 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2758 POSTING_READ(reg);
17638cd6
JB		 2759}
2760
29b9bde6
DV		 2761static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2762 struct drm_framebuffer *fb,
2763 int x, int y)
17638cd6
JB		 2764{
2765 struct drm_device *dev = crtc->dev;
2766 struct drm_i915_private *dev_priv = dev->dev_private;
2767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2768 struct drm_plane *primary = crtc->primary;
2769 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2770 struct drm_i915_gem_object *obj;
17638cd6 2771 int plane = intel_crtc->plane;
e506a0c6 2772 unsigned long linear_offset;
17638cd6 2773 u32 dspcntr;
f45651ba 2774 u32 reg = DSPCNTR(plane);
48404c1e 2775 int pixel_size;
f45651ba 2776
b70709a6 2777 if (!visible || !fb) {
fdd508a6
VS		 2778 I915_WRITE(reg, 0);
2779 I915_WRITE(DSPSURF(plane), 0);
2780 POSTING_READ(reg);
2781 return;
2782 }
2783
c9ba6fad
VS		 2784 obj = intel_fb_obj(fb);
2785 if (WARN_ON(obj == NULL))
2786 return;
2787
2788 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2789
f45651ba
VS		 2790 dspcntr = DISPPLANE_GAMMA_ENABLE;
2791
fdd508a6 2792 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2793
2794 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2795 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2796
57779d06
VS		 2797 switch (fb->pixel_format) {
2798 case DRM_FORMAT_C8:
17638cd6
JB		 2799 dspcntr |= DISPPLANE_8BPP;
2800 break;
57779d06
VS		 2801 case DRM_FORMAT_RGB565:
2802 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2803 break;
57779d06 2804 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2805 dspcntr |= DISPPLANE_BGRX888;
2806 break;
2807 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2808 dspcntr |= DISPPLANE_RGBX888;
2809 break;
2810 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2811 dspcntr |= DISPPLANE_BGRX101010;
2812 break;
2813 case DRM_FORMAT_XBGR2101010:
57779d06 2814 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2815 break;
2816 default:
baba133a 2817 BUG();
17638cd6
JB		 2818 }
2819
2820 if (obj->tiling_mode != I915_TILING_NONE)
2821 dspcntr |= DISPPLANE_TILED;
17638cd6 2822
f45651ba 2823 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2824 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2825
b9897127 2826 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2827 intel_crtc->dspaddr_offset =
bc752862 2828 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2829 pixel_size,
bc752862 2830 fb->pitches[0]);
c2c75131 2831 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2832 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2833 dspcntr |= DISPPLANE_ROTATE_180;
2834
2835 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2836 x += (intel_crtc->config->pipe_src_w - 1);
2837 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2838
2839 /* Finding the last pixel of the last line of the display
2840 data and adding to linear_offset*/
2841 linear_offset +=
6e3c9717
ACO		 2842 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2843 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2844 }
2845 }
2846
2847 I915_WRITE(reg, dspcntr);
17638cd6 2848
01f2c773 2849 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2850 I915_WRITE(DSPSURF(plane),
2851 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2852 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2853 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2854 } else {
2855 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2856 I915_WRITE(DSPLINOFF(plane), linear_offset);
2857 }
17638cd6 2858 POSTING_READ(reg);
17638cd6
JB		 2859}
2860
b321803d
DL		 2861u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2862 uint32_t pixel_format)
2863{
2864 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2865
2866 /*
2867 * The stride is either expressed as a multiple of 64 bytes
2868 * chunks for linear buffers or in number of tiles for tiled
2869 * buffers.
2870 */
2871 switch (fb_modifier) {
2872 case DRM_FORMAT_MOD_NONE:
2873 return 64;
2874 case I915_FORMAT_MOD_X_TILED:
2875 if (INTEL_INFO(dev)->gen == 2)
2876 return 128;
2877 return 512;
2878 case I915_FORMAT_MOD_Y_TILED:
2879 /* No need to check for old gens and Y tiling since this is
2880 * about the display engine and those will be blocked before
2881 * we get here.
2882 */
2883 return 128;
2884 case I915_FORMAT_MOD_Yf_TILED:
2885 if (bits_per_pixel == 8)
2886 return 64;
2887 else
2888 return 128;
2889 default:
2890 MISSING_CASE(fb_modifier);
2891 return 64;
2892 }
2893}
2894
121920fa
TU		 2895unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2896 struct drm_i915_gem_object *obj)
2897{
9abc4648 2898 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
121920fa
TU		 2899
2900 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2901 view = &i915_ggtt_view_rotated;
121920fa
TU		 2902
2903 return i915_gem_obj_ggtt_offset_view(obj, view);
2904}
2905
a1b2278e
CK		 2906/*
2907 * This function detaches (aka. unbinds) unused scalers in hardware
2908 */
2909void skl_detach_scalers(struct intel_crtc *intel_crtc)
2910{
2911 struct drm_device *dev;
2912 struct drm_i915_private *dev_priv;
2913 struct intel_crtc_scaler_state *scaler_state;
2914 int i;
2915
2916 if (!intel_crtc || !intel_crtc->config)
2917 return;
2918
2919 dev = intel_crtc->base.dev;
2920 dev_priv = dev->dev_private;
2921 scaler_state = &intel_crtc->config->scaler_state;
2922
2923 /* loop through and disable scalers that aren't in use */
2924 for (i = 0; i < intel_crtc->num_scalers; i++) {
2925 if (!scaler_state->scalers[i].in_use) {
2926 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2927 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2928 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2929 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2930 intel_crtc->base.base.id, intel_crtc->pipe, i);
2931 }
2932 }
2933}
2934
6156a456 2935u32 skl_plane_ctl_format(uint32_t pixel_format)
70d21f0e 2936{
6156a456 2937 switch (pixel_format) {
d161cf7a 2938 case DRM_FORMAT_C8:
c34ce3d1 2939 return PLANE_CTL_FORMAT_INDEXED;
70d21f0e 2940 case DRM_FORMAT_RGB565:
c34ce3d1 2941 return PLANE_CTL_FORMAT_RGB_565;
70d21f0e 2942 case DRM_FORMAT_XBGR8888:
c34ce3d1 2943 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
6156a456 2944 case DRM_FORMAT_XRGB8888:
c34ce3d1 2945 return PLANE_CTL_FORMAT_XRGB_8888;
6156a456
CK		 2946 /*
2947 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2948 * to be already pre-multiplied. We need to add a knob (or a different
2949 * DRM_FORMAT) for user-space to configure that.
2950 */
f75fb42a 2951 case DRM_FORMAT_ABGR8888:
c34ce3d1 2952 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
6156a456 2953 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
6156a456 2954 case DRM_FORMAT_ARGB8888:
c34ce3d1 2955 return PLANE_CTL_FORMAT_XRGB_8888 |
6156a456 2956 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
70d21f0e 2957 case DRM_FORMAT_XRGB2101010:
c34ce3d1 2958 return PLANE_CTL_FORMAT_XRGB_2101010;
70d21f0e 2959 case DRM_FORMAT_XBGR2101010:
c34ce3d1 2960 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
6156a456 2961 case DRM_FORMAT_YUYV:
c34ce3d1 2962 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
6156a456 2963 case DRM_FORMAT_YVYU:
c34ce3d1 2964 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
6156a456 2965 case DRM_FORMAT_UYVY:
c34ce3d1 2966 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
6156a456 2967 case DRM_FORMAT_VYUY:
c34ce3d1 2968 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
70d21f0e 2969 default:
4249eeef 2970 MISSING_CASE(pixel_format);
70d21f0e 2971 }
8cfcba41 2972
c34ce3d1 2973 return 0;
6156a456 2974}
70d21f0e 2975
6156a456
CK		 2976u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2977{
6156a456 2978 switch (fb_modifier) {
30af77c4 2979 case DRM_FORMAT_MOD_NONE:
70d21f0e 2980 break;
30af77c4 2981 case I915_FORMAT_MOD_X_TILED:
c34ce3d1 2982 return PLANE_CTL_TILED_X;
b321803d 2983 case I915_FORMAT_MOD_Y_TILED:
c34ce3d1 2984 return PLANE_CTL_TILED_Y;
b321803d 2985 case I915_FORMAT_MOD_Yf_TILED:
c34ce3d1 2986 return PLANE_CTL_TILED_YF;
70d21f0e 2987 default:
6156a456 2988 MISSING_CASE(fb_modifier);
70d21f0e 2989 }
8cfcba41 2990
c34ce3d1 2991 return 0;
6156a456 2992}
70d21f0e 2993
6156a456
CK		 2994u32 skl_plane_ctl_rotation(unsigned int rotation)
2995{
3b7a5119 2996 switch (rotation) {
6156a456
CK		 2997 case BIT(DRM_ROTATE_0):
2998 break;
1e8df167
SJ		 2999 /*
3000 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3001 * while i915 HW rotation is clockwise, thats why this swapping.
3002 */
3b7a5119 3003 case BIT(DRM_ROTATE_90):
1e8df167 3004 return PLANE_CTL_ROTATE_270;
3b7a5119 3005 case BIT(DRM_ROTATE_180):
c34ce3d1 3006 return PLANE_CTL_ROTATE_180;
3b7a5119 3007 case BIT(DRM_ROTATE_270):
1e8df167 3008 return PLANE_CTL_ROTATE_90;
6156a456
CK		 3009 default:
3010 MISSING_CASE(rotation);
3011 }
3012
c34ce3d1 3013 return 0;
6156a456
CK		 3014}
3015
3016static void skylake_update_primary_plane(struct drm_crtc *crtc,
3017 struct drm_framebuffer *fb,
3018 int x, int y)
3019{
3020 struct drm_device *dev = crtc->dev;
3021 struct drm_i915_private *dev_priv = dev->dev_private;
3022 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 3023 struct drm_plane *plane = crtc->primary;
3024 bool visible = to_intel_plane_state(plane->state)->visible;
6156a456
CK		 3025 struct drm_i915_gem_object *obj;
3026 int pipe = intel_crtc->pipe;
3027 u32 plane_ctl, stride_div, stride;
3028 u32 tile_height, plane_offset, plane_size;
3029 unsigned int rotation;
3030 int x_offset, y_offset;
3031 unsigned long surf_addr;
6156a456
CK		 3032 struct intel_crtc_state *crtc_state = intel_crtc->config;
3033 struct intel_plane_state *plane_state;
3034 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3035 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3036 int scaler_id = -1;
3037
6156a456
CK		 3038 plane_state = to_intel_plane_state(plane->state);
3039
b70709a6 3040 if (!visible || !fb) {
6156a456
CK		 3041 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3042 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3043 POSTING_READ(PLANE_CTL(pipe, 0));
3044 return;
3b7a5119 3045 }
70d21f0e 3046
6156a456
CK		 3047 plane_ctl = PLANE_CTL_ENABLE |
3048 PLANE_CTL_PIPE_GAMMA_ENABLE |
3049 PLANE_CTL_PIPE_CSC_ENABLE;
3050
3051 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3052 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3053 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3054
3055 rotation = plane->state->rotation;
3056 plane_ctl |= skl_plane_ctl_rotation(rotation);
3057
b321803d
DL		 3058 obj = intel_fb_obj(fb);
3059 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3060 fb->pixel_format);
3b7a5119
SJ		 3061 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3062
6156a456
CK		 3063 /*
3064 * FIXME: intel_plane_state->src, dst aren't set when transitional
3065 * update_plane helpers are called from legacy paths.
3066 * Once full atomic crtc is available, below check can be avoided.
3067 */
3068 if (drm_rect_width(&plane_state->src)) {
3069 scaler_id = plane_state->scaler_id;
3070 src_x = plane_state->src.x1 >> 16;
3071 src_y = plane_state->src.y1 >> 16;
3072 src_w = drm_rect_width(&plane_state->src) >> 16;
3073 src_h = drm_rect_height(&plane_state->src) >> 16;
3074 dst_x = plane_state->dst.x1;
3075 dst_y = plane_state->dst.y1;
3076 dst_w = drm_rect_width(&plane_state->dst);
3077 dst_h = drm_rect_height(&plane_state->dst);
3078
3079 WARN_ON(x != src_x || y != src_y);
3080 } else {
3081 src_w = intel_crtc->config->pipe_src_w;
3082 src_h = intel_crtc->config->pipe_src_h;
3083 }
3084
3b7a5119
SJ		 3085 if (intel_rotation_90_or_270(rotation)) {
3086 /* stride = Surface height in tiles */
2614f17d 3087 tile_height = intel_tile_height(dev, fb->pixel_format,
3b7a5119
SJ		 3088 fb->modifier[0]);
3089 stride = DIV_ROUND_UP(fb->height, tile_height);
6156a456 3090 x_offset = stride * tile_height - y - src_h;
3b7a5119 3091 y_offset = x;
6156a456 3092 plane_size = (src_w - 1) << 16 | (src_h - 1);
3b7a5119
SJ		 3093 } else {
3094 stride = fb->pitches[0] / stride_div;
3095 x_offset = x;
3096 y_offset = y;
6156a456 3097 plane_size = (src_h - 1) << 16 | (src_w - 1);
3b7a5119
SJ		 3098 }
3099 plane_offset = y_offset << 16 | x_offset;
b321803d 3100
70d21f0e 3101 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3b7a5119
SJ		 3102 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3103 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3104 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
6156a456
CK		 3105
3106 if (scaler_id >= 0) {
3107 uint32_t ps_ctrl = 0;
3108
3109 WARN_ON(!dst_w || !dst_h);
3110 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3111 crtc_state->scaler_state.scalers[scaler_id].mode;
3112 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3113 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3114 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3115 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3116 I915_WRITE(PLANE_POS(pipe, 0), 0);
3117 } else {
3118 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3119 }
3120
121920fa 3121 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3122
3123 POSTING_READ(PLANE_SURF(pipe, 0));
3124}
3125
17638cd6
JB		 3126/* Assume fb object is pinned & idle & fenced and just update base pointers */
3127static int
3128intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3129 int x, int y, enum mode_set_atomic state)
3130{
3131 struct drm_device *dev = crtc->dev;
3132 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3133
6b8e6ed0
CW		 3134 if (dev_priv->display.disable_fbc)
3135 dev_priv->display.disable_fbc(dev);
81255565 3136
29b9bde6
DV		 3137 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3138
3139 return 0;
81255565
JB		 3140}
3141
7514747d 3142static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3143{
96a02917
VS		 3144 struct drm_crtc *crtc;
3145
70e1e0ec 3146 for_each_crtc(dev, crtc) {
96a02917
VS		 3147 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3148 enum plane plane = intel_crtc->plane;
3149
3150 intel_prepare_page_flip(dev, plane);
3151 intel_finish_page_flip_plane(dev, plane);
3152 }
7514747d
VS		 3153}
3154
3155static void intel_update_primary_planes(struct drm_device *dev)
3156{
3157 struct drm_i915_private *dev_priv = dev->dev_private;
3158 struct drm_crtc *crtc;
96a02917 3159
70e1e0ec 3160 for_each_crtc(dev, crtc) {
96a02917
VS		 3161 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3162
51fd371b 3163 drm_modeset_lock(&crtc->mutex, NULL);
947fdaad
CW		 3164 /*
3165 * FIXME: Once we have proper support for primary planes (and
3166 * disabling them without disabling the entire crtc) allow again
66e514c1 3167 * a NULL crtc->primary->fb.
947fdaad 3168 */
f4510a27 3169 if (intel_crtc->active && crtc->primary->fb)
262ca2b0 3170 dev_priv->display.update_primary_plane(crtc,
66e514c1 3171 crtc->primary->fb,
262ca2b0
MR		 3172 crtc->x,
3173 crtc->y);
51fd371b 3174 drm_modeset_unlock(&crtc->mutex);
96a02917
VS		 3175 }
3176}
3177
ce22dba9
ML		 3178void intel_crtc_reset(struct intel_crtc *crtc)
3179{
3180 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3181
3182 if (!crtc->active)
3183 return;
3184
3185 intel_crtc_disable_planes(&crtc->base);
3186 dev_priv->display.crtc_disable(&crtc->base);
3187 dev_priv->display.crtc_enable(&crtc->base);
3188 intel_crtc_enable_planes(&crtc->base);
3189}
3190
7514747d
VS		 3191void intel_prepare_reset(struct drm_device *dev)
3192{
f98ce92f
VS		 3193 struct drm_i915_private *dev_priv = to_i915(dev);
3194 struct intel_crtc *crtc;
3195
7514747d
VS		 3196 /* no reset support for gen2 */
3197 if (IS_GEN2(dev))
3198 return;
3199
3200 /* reset doesn't touch the display */
3201 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3202 return;
3203
3204 drm_modeset_lock_all(dev);
f98ce92f
VS		 3205
3206 /*
3207 * Disabling the crtcs gracefully seems nicer. Also the
3208 * g33 docs say we should at least disable all the planes.
3209 */
3210 for_each_intel_crtc(dev, crtc) {
ce22dba9
ML		 3211 if (!crtc->active)
3212 continue;
3213
3214 intel_crtc_disable_planes(&crtc->base);
3215 dev_priv->display.crtc_disable(&crtc->base);
f98ce92f 3216 }
7514747d
VS		 3217}
3218
3219void intel_finish_reset(struct drm_device *dev)
3220{
3221 struct drm_i915_private *dev_priv = to_i915(dev);
3222
3223 /*
3224 * Flips in the rings will be nuked by the reset,
3225 * so complete all pending flips so that user space
3226 * will get its events and not get stuck.
3227 */
3228 intel_complete_page_flips(dev);
3229
3230 /* no reset support for gen2 */
3231 if (IS_GEN2(dev))
3232 return;
3233
3234 /* reset doesn't touch the display */
3235 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3236 /*
3237 * Flips in the rings have been nuked by the reset,
3238 * so update the base address of all primary
3239 * planes to the the last fb to make sure we're
3240 * showing the correct fb after a reset.
3241 */
3242 intel_update_primary_planes(dev);
3243 return;
3244 }
3245
3246 /*
3247 * The display has been reset as well,
3248 * so need a full re-initialization.
3249 */
3250 intel_runtime_pm_disable_interrupts(dev_priv);
3251 intel_runtime_pm_enable_interrupts(dev_priv);
3252
3253 intel_modeset_init_hw(dev);
3254
3255 spin_lock_irq(&dev_priv->irq_lock);
3256 if (dev_priv->display.hpd_irq_setup)
3257 dev_priv->display.hpd_irq_setup(dev);
3258 spin_unlock_irq(&dev_priv->irq_lock);
3259
3260 intel_modeset_setup_hw_state(dev, true);
3261
3262 intel_hpd_init(dev_priv);
3263
3264 drm_modeset_unlock_all(dev);
3265}
3266
2e2f351d 3267static void
14667a4b
CW		 3268intel_finish_fb(struct drm_framebuffer *old_fb)
3269{
2ff8fde1 3270 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2e2f351d 3271 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14667a4b
CW		 3272 bool was_interruptible = dev_priv->mm.interruptible;
3273 int ret;
3274
14667a4b
CW		 3275 /* Big Hammer, we also need to ensure that any pending
3276 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3277 * current scanout is retired before unpinning the old
2e2f351d
CW		 3278 * framebuffer. Note that we rely on userspace rendering
3279 * into the buffer attached to the pipe they are waiting
3280 * on. If not, userspace generates a GPU hang with IPEHR
3281 * point to the MI_WAIT_FOR_EVENT.
14667a4b
CW		 3282 *
3283 * This should only fail upon a hung GPU, in which case we
3284 * can safely continue.
3285 */
3286 dev_priv->mm.interruptible = false;
2e2f351d 3287 ret = i915_gem_object_wait_rendering(obj, true);
14667a4b
CW		 3288 dev_priv->mm.interruptible = was_interruptible;
3289
2e2f351d 3290 WARN_ON(ret);
14667a4b
CW		 3291}
3292
7d5e3799
CW		 3293static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3294{
3295 struct drm_device *dev = crtc->dev;
3296 struct drm_i915_private *dev_priv = dev->dev_private;
3297 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3298 bool pending;
3299
3300 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3301 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3302 return false;
3303
5e2d7afc 3304 spin_lock_irq(&dev->event_lock);
7d5e3799 3305 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3306 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3307
3308 return pending;
3309}
3310
e30e8f75
GP		 3311static void intel_update_pipe_size(struct intel_crtc *crtc)
3312{
3313 struct drm_device *dev = crtc->base.dev;
3314 struct drm_i915_private *dev_priv = dev->dev_private;
3315 const struct drm_display_mode *adjusted_mode;
3316
3317 if (!i915.fastboot)
3318 return;
3319
3320 /*
3321 * Update pipe size and adjust fitter if needed: the reason for this is
3322 * that in compute_mode_changes we check the native mode (not the pfit
3323 * mode) to see if we can flip rather than do a full mode set. In the
3324 * fastboot case, we'll flip, but if we don't update the pipesrc and
3325 * pfit state, we'll end up with a big fb scanned out into the wrong
3326 * sized surface.
3327 *
3328 * To fix this properly, we need to hoist the checks up into
3329 * compute_mode_changes (or above), check the actual pfit state and
3330 * whether the platform allows pfit disable with pipe active, and only
3331 * then update the pipesrc and pfit state, even on the flip path.
3332 */
3333
6e3c9717 3334 adjusted_mode = &crtc->config->base.adjusted_mode;
e30e8f75
GP		 3335
3336 I915_WRITE(PIPESRC(crtc->pipe),
3337 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3338 (adjusted_mode->crtc_vdisplay - 1));
6e3c9717 3339 if (!crtc->config->pch_pfit.enabled &&
409ee761
ACO		 3340 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3341 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
e30e8f75
GP		 3342 I915_WRITE(PF_CTL(crtc->pipe), 0);
3343 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3344 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3345 }
6e3c9717
ACO		 3346 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3347 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
e30e8f75
GP		 3348}
3349
5e84e1a4
ZW		 3350static void intel_fdi_normal_train(struct drm_crtc *crtc)
3351{
3352 struct drm_device *dev = crtc->dev;
3353 struct drm_i915_private *dev_priv = dev->dev_private;
3354 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3355 int pipe = intel_crtc->pipe;
3356 u32 reg, temp;
3357
3358 /* enable normal train */
3359 reg = FDI_TX_CTL(pipe);
3360 temp = I915_READ(reg);
61e499bf 3361 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3362 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3363 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3364 } else {
3365 temp &= ~FDI_LINK_TRAIN_NONE;
3366 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3367 }
5e84e1a4
ZW		 3368 I915_WRITE(reg, temp);
3369
3370 reg = FDI_RX_CTL(pipe);
3371 temp = I915_READ(reg);
3372 if (HAS_PCH_CPT(dev)) {
3373 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3374 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3375 } else {
3376 temp &= ~FDI_LINK_TRAIN_NONE;
3377 temp |= FDI_LINK_TRAIN_NONE;
3378 }
3379 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3380
3381 /* wait one idle pattern time */
3382 POSTING_READ(reg);
3383 udelay(1000);
357555c0
JB		 3384
3385 /* IVB wants error correction enabled */
3386 if (IS_IVYBRIDGE(dev))
3387 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3388 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3389}
3390
8db9d77b
ZW		 3391/* The FDI link training functions for ILK/Ibexpeak. */
3392static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3393{
3394 struct drm_device *dev = crtc->dev;
3395 struct drm_i915_private *dev_priv = dev->dev_private;
3396 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3397 int pipe = intel_crtc->pipe;
5eddb70b 3398 u32 reg, temp, tries;
8db9d77b 3399
1c8562f6 3400 /* FDI needs bits from pipe first */
0fc932b8 3401 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3402
e1a44743
AJ		 3403 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3404 for train result */
5eddb70b
CW		 3405 reg = FDI_RX_IMR(pipe);
3406 temp = I915_READ(reg);
e1a44743
AJ		 3407 temp &= ~FDI_RX_SYMBOL_LOCK;
3408 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3409 I915_WRITE(reg, temp);
3410 I915_READ(reg);
e1a44743
AJ		 3411 udelay(150);
3412
8db9d77b 3413 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3414 reg = FDI_TX_CTL(pipe);
3415 temp = I915_READ(reg);
627eb5a3 3416 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3417 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3418 temp &= ~FDI_LINK_TRAIN_NONE;
3419 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3420 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3421
5eddb70b
CW		 3422 reg = FDI_RX_CTL(pipe);
3423 temp = I915_READ(reg);
8db9d77b
ZW		 3424 temp &= ~FDI_LINK_TRAIN_NONE;
3425 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3426 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3427
3428 POSTING_READ(reg);
8db9d77b
ZW		 3429 udelay(150);
3430
5b2adf89 3431 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3432 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3433 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3434 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3435
5eddb70b 3436 reg = FDI_RX_IIR(pipe);
e1a44743 3437 for (tries = 0; tries < 5; tries++) {
5eddb70b 3438 temp = I915_READ(reg);
8db9d77b
ZW		 3439 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3440
3441 if ((temp & FDI_RX_BIT_LOCK)) {
3442 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3443 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3444 break;
3445 }
8db9d77b 3446 }
e1a44743 3447 if (tries == 5)
5eddb70b 3448 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3449
3450 /* Train 2 */
5eddb70b
CW		 3451 reg = FDI_TX_CTL(pipe);
3452 temp = I915_READ(reg);
8db9d77b
ZW		 3453 temp &= ~FDI_LINK_TRAIN_NONE;
3454 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3455 I915_WRITE(reg, temp);
8db9d77b 3456
5eddb70b
CW		 3457 reg = FDI_RX_CTL(pipe);
3458 temp = I915_READ(reg);
8db9d77b
ZW		 3459 temp &= ~FDI_LINK_TRAIN_NONE;
3460 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3461 I915_WRITE(reg, temp);
8db9d77b 3462
5eddb70b
CW		 3463 POSTING_READ(reg);
3464 udelay(150);
8db9d77b 3465
5eddb70b 3466 reg = FDI_RX_IIR(pipe);
e1a44743 3467 for (tries = 0; tries < 5; tries++) {
5eddb70b 3468 temp = I915_READ(reg);
8db9d77b
ZW		 3469 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3470
3471 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3472 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3473 DRM_DEBUG_KMS("FDI train 2 done.\n");
3474 break;
3475 }
8db9d77b 3476 }
e1a44743 3477 if (tries == 5)
5eddb70b 3478 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3479
3480 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3481
8db9d77b
ZW		 3482}
3483
0206e353 3484static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3485 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3486 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3487 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3488 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3489};
3490
3491/* The FDI link training functions for SNB/Cougarpoint. */
3492static void gen6_fdi_link_train(struct drm_crtc *crtc)
3493{
3494 struct drm_device *dev = crtc->dev;
3495 struct drm_i915_private *dev_priv = dev->dev_private;
3496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3497 int pipe = intel_crtc->pipe;
fa37d39e 3498 u32 reg, temp, i, retry;
8db9d77b 3499
e1a44743
AJ		 3500 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3501 for train result */
5eddb70b
CW		 3502 reg = FDI_RX_IMR(pipe);
3503 temp = I915_READ(reg);
e1a44743
AJ		 3504 temp &= ~FDI_RX_SYMBOL_LOCK;
3505 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3506 I915_WRITE(reg, temp);
3507
3508 POSTING_READ(reg);
e1a44743
AJ		 3509 udelay(150);
3510
8db9d77b 3511 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3512 reg = FDI_TX_CTL(pipe);
3513 temp = I915_READ(reg);
627eb5a3 3514 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3515 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3516 temp &= ~FDI_LINK_TRAIN_NONE;
3517 temp |= FDI_LINK_TRAIN_PATTERN_1;
3518 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3519 /* SNB-B */
3520 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3521 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3522
d74cf324
DV		 3523 I915_WRITE(FDI_RX_MISC(pipe),
3524 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3525
5eddb70b
CW		 3526 reg = FDI_RX_CTL(pipe);
3527 temp = I915_READ(reg);
8db9d77b
ZW		 3528 if (HAS_PCH_CPT(dev)) {
3529 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3530 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3531 } else {
3532 temp &= ~FDI_LINK_TRAIN_NONE;
3533 temp |= FDI_LINK_TRAIN_PATTERN_1;
3534 }
5eddb70b
CW		 3535 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3536
3537 POSTING_READ(reg);
8db9d77b
ZW		 3538 udelay(150);
3539
0206e353 3540 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3541 reg = FDI_TX_CTL(pipe);
3542 temp = I915_READ(reg);
8db9d77b
ZW		 3543 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3544 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3545 I915_WRITE(reg, temp);
3546
3547 POSTING_READ(reg);
8db9d77b
ZW		 3548 udelay(500);
3549
fa37d39e
SP		 3550 for (retry = 0; retry < 5; retry++) {
3551 reg = FDI_RX_IIR(pipe);
3552 temp = I915_READ(reg);
3553 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3554 if (temp & FDI_RX_BIT_LOCK) {
3555 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3556 DRM_DEBUG_KMS("FDI train 1 done.\n");
3557 break;
3558 }
3559 udelay(50);
8db9d77b 3560 }
fa37d39e
SP		 3561 if (retry < 5)
3562 break;
8db9d77b
ZW		 3563 }
3564 if (i == 4)
5eddb70b 3565 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3566
3567 /* Train 2 */
5eddb70b
CW		 3568 reg = FDI_TX_CTL(pipe);
3569 temp = I915_READ(reg);
8db9d77b
ZW		 3570 temp &= ~FDI_LINK_TRAIN_NONE;
3571 temp |= FDI_LINK_TRAIN_PATTERN_2;
3572 if (IS_GEN6(dev)) {
3573 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3574 /* SNB-B */
3575 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3576 }
5eddb70b 3577 I915_WRITE(reg, temp);
8db9d77b 3578
5eddb70b
CW		 3579 reg = FDI_RX_CTL(pipe);
3580 temp = I915_READ(reg);
8db9d77b
ZW		 3581 if (HAS_PCH_CPT(dev)) {
3582 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3583 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3584 } else {
3585 temp &= ~FDI_LINK_TRAIN_NONE;
3586 temp |= FDI_LINK_TRAIN_PATTERN_2;
3587 }
5eddb70b
CW		 3588 I915_WRITE(reg, temp);
3589
3590 POSTING_READ(reg);
8db9d77b
ZW		 3591 udelay(150);
3592
0206e353 3593 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3594 reg = FDI_TX_CTL(pipe);
3595 temp = I915_READ(reg);
8db9d77b
ZW		 3596 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3597 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3598 I915_WRITE(reg, temp);
3599
3600 POSTING_READ(reg);
8db9d77b
ZW		 3601 udelay(500);
3602
fa37d39e
SP		 3603 for (retry = 0; retry < 5; retry++) {
3604 reg = FDI_RX_IIR(pipe);
3605 temp = I915_READ(reg);
3606 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3607 if (temp & FDI_RX_SYMBOL_LOCK) {
3608 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3609 DRM_DEBUG_KMS("FDI train 2 done.\n");
3610 break;
3611 }
3612 udelay(50);
8db9d77b 3613 }
fa37d39e
SP		 3614 if (retry < 5)
3615 break;
8db9d77b
ZW		 3616 }
3617 if (i == 4)
5eddb70b 3618 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3619
3620 DRM_DEBUG_KMS("FDI train done.\n");
3621}
3622
357555c0
JB		 3623/* Manual link training for Ivy Bridge A0 parts */
3624static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3625{
3626 struct drm_device *dev = crtc->dev;
3627 struct drm_i915_private *dev_priv = dev->dev_private;
3628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3629 int pipe = intel_crtc->pipe;
139ccd3f 3630 u32 reg, temp, i, j;
357555c0
JB		 3631
3632 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3633 for train result */
3634 reg = FDI_RX_IMR(pipe);
3635 temp = I915_READ(reg);
3636 temp &= ~FDI_RX_SYMBOL_LOCK;
3637 temp &= ~FDI_RX_BIT_LOCK;
3638 I915_WRITE(reg, temp);
3639
3640 POSTING_READ(reg);
3641 udelay(150);
3642
01a415fd
DV		 3643 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3644 I915_READ(FDI_RX_IIR(pipe)));
3645
139ccd3f
JB		 3646 /* Try each vswing and preemphasis setting twice before moving on */
3647 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3648 /* disable first in case we need to retry */
3649 reg = FDI_TX_CTL(pipe);
3650 temp = I915_READ(reg);
3651 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3652 temp &= ~FDI_TX_ENABLE;
3653 I915_WRITE(reg, temp);
357555c0 3654
139ccd3f
JB		 3655 reg = FDI_RX_CTL(pipe);
3656 temp = I915_READ(reg);
3657 temp &= ~FDI_LINK_TRAIN_AUTO;
3658 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3659 temp &= ~FDI_RX_ENABLE;
3660 I915_WRITE(reg, temp);
357555c0 3661
139ccd3f 3662 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3663 reg = FDI_TX_CTL(pipe);
3664 temp = I915_READ(reg);
139ccd3f 3665 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3666 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3667 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3668 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3669 temp |= snb_b_fdi_train_param[j/2];
3670 temp |= FDI_COMPOSITE_SYNC;
3671 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3672
139ccd3f
JB		 3673 I915_WRITE(FDI_RX_MISC(pipe),
3674 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3675
139ccd3f 3676 reg = FDI_RX_CTL(pipe);
357555c0 3677 temp = I915_READ(reg);
139ccd3f
JB		 3678 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3679 temp |= FDI_COMPOSITE_SYNC;
3680 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3681
139ccd3f
JB		 3682 POSTING_READ(reg);
3683 udelay(1); /* should be 0.5us */
357555c0 3684
139ccd3f
JB		 3685 for (i = 0; i < 4; i++) {
3686 reg = FDI_RX_IIR(pipe);
3687 temp = I915_READ(reg);
3688 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3689
139ccd3f
JB		 3690 if (temp & FDI_RX_BIT_LOCK ||
3691 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3692 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3693 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3694 i);
3695 break;
3696 }
3697 udelay(1); /* should be 0.5us */
3698 }
3699 if (i == 4) {
3700 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3701 continue;
3702 }
357555c0 3703
139ccd3f 3704 /* Train 2 */
357555c0
JB		 3705 reg = FDI_TX_CTL(pipe);
3706 temp = I915_READ(reg);
139ccd3f
JB		 3707 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3708 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3709 I915_WRITE(reg, temp);
3710
3711 reg = FDI_RX_CTL(pipe);
3712 temp = I915_READ(reg);
3713 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3714 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3715 I915_WRITE(reg, temp);
3716
3717 POSTING_READ(reg);
139ccd3f 3718 udelay(2); /* should be 1.5us */
357555c0 3719
139ccd3f
JB		 3720 for (i = 0; i < 4; i++) {
3721 reg = FDI_RX_IIR(pipe);
3722 temp = I915_READ(reg);
3723 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3724
139ccd3f
JB		 3725 if (temp & FDI_RX_SYMBOL_LOCK ||
3726 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3727 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3728 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3729 i);
3730 goto train_done;
3731 }
3732 udelay(2); /* should be 1.5us */
357555c0 3733 }
139ccd3f
JB		 3734 if (i == 4)
3735 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3736 }
357555c0 3737
139ccd3f 3738train_done:
357555c0
JB		 3739 DRM_DEBUG_KMS("FDI train done.\n");
3740}
3741
88cefb6c 3742static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3743{
88cefb6c 3744 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3745 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3746 int pipe = intel_crtc->pipe;
5eddb70b 3747 u32 reg, temp;
79e53945 3748
c64e311e 3749
c98e9dcf 3750 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3751 reg = FDI_RX_CTL(pipe);
3752 temp = I915_READ(reg);
627eb5a3 3753 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3754 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3755 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3756 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3757
3758 POSTING_READ(reg);
c98e9dcf
JB		 3759 udelay(200);
3760
3761 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3762 temp = I915_READ(reg);
3763 I915_WRITE(reg, temp | FDI_PCDCLK);
3764
3765 POSTING_READ(reg);
c98e9dcf
JB		 3766 udelay(200);
3767
20749730
PZ		 3768 /* Enable CPU FDI TX PLL, always on for Ironlake */
3769 reg = FDI_TX_CTL(pipe);
3770 temp = I915_READ(reg);
3771 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3772 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3773
20749730
PZ		 3774 POSTING_READ(reg);
3775 udelay(100);
6be4a607 3776 }
0e23b99d
JB		 3777}
3778
88cefb6c
DV		 3779static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3780{
3781 struct drm_device *dev = intel_crtc->base.dev;
3782 struct drm_i915_private *dev_priv = dev->dev_private;
3783 int pipe = intel_crtc->pipe;
3784 u32 reg, temp;
3785
3786 /* Switch from PCDclk to Rawclk */
3787 reg = FDI_RX_CTL(pipe);
3788 temp = I915_READ(reg);
3789 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3790
3791 /* Disable CPU FDI TX PLL */
3792 reg = FDI_TX_CTL(pipe);
3793 temp = I915_READ(reg);
3794 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3795
3796 POSTING_READ(reg);
3797 udelay(100);
3798
3799 reg = FDI_RX_CTL(pipe);
3800 temp = I915_READ(reg);
3801 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3802
3803 /* Wait for the clocks to turn off. */
3804 POSTING_READ(reg);
3805 udelay(100);
3806}
3807
0fc932b8
JB		 3808static void ironlake_fdi_disable(struct drm_crtc *crtc)
3809{
3810 struct drm_device *dev = crtc->dev;
3811 struct drm_i915_private *dev_priv = dev->dev_private;
3812 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3813 int pipe = intel_crtc->pipe;
3814 u32 reg, temp;
3815
3816 /* disable CPU FDI tx and PCH FDI rx */
3817 reg = FDI_TX_CTL(pipe);
3818 temp = I915_READ(reg);
3819 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3820 POSTING_READ(reg);
3821
3822 reg = FDI_RX_CTL(pipe);
3823 temp = I915_READ(reg);
3824 temp &= ~(0x7 << 16);
dfd07d72 3825 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3826 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3827
3828 POSTING_READ(reg);
3829 udelay(100);
3830
3831 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3832 if (HAS_PCH_IBX(dev))
6f06ce18 3833 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3834
3835 /* still set train pattern 1 */
3836 reg = FDI_TX_CTL(pipe);
3837 temp = I915_READ(reg);
3838 temp &= ~FDI_LINK_TRAIN_NONE;
3839 temp |= FDI_LINK_TRAIN_PATTERN_1;
3840 I915_WRITE(reg, temp);
3841
3842 reg = FDI_RX_CTL(pipe);
3843 temp = I915_READ(reg);
3844 if (HAS_PCH_CPT(dev)) {
3845 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3846 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3847 } else {
3848 temp &= ~FDI_LINK_TRAIN_NONE;
3849 temp |= FDI_LINK_TRAIN_PATTERN_1;
3850 }
3851 /* BPC in FDI rx is consistent with that in PIPECONF */
3852 temp &= ~(0x07 << 16);
dfd07d72 3853 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3854 I915_WRITE(reg, temp);
3855
3856 POSTING_READ(reg);
3857 udelay(100);
3858}
3859
5dce5b93
CW		 3860bool intel_has_pending_fb_unpin(struct drm_device *dev)
3861{
3862 struct intel_crtc *crtc;
3863
3864 /* Note that we don't need to be called with mode_config.lock here
3865 * as our list of CRTC objects is static for the lifetime of the
3866 * device and so cannot disappear as we iterate. Similarly, we can
3867 * happily treat the predicates as racy, atomic checks as userspace
3868 * cannot claim and pin a new fb without at least acquring the
3869 * struct_mutex and so serialising with us.
3870 */
d3fcc808 3871 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3872 if (atomic_read(&crtc->unpin_work_count) == 0)
3873 continue;
3874
3875 if (crtc->unpin_work)
3876 intel_wait_for_vblank(dev, crtc->pipe);
3877
3878 return true;
3879 }
3880
3881 return false;
3882}
3883
d6bbafa1
CW		 3884static void page_flip_completed(struct intel_crtc *intel_crtc)
3885{
3886 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3887 struct intel_unpin_work *work = intel_crtc->unpin_work;
3888
3889 /* ensure that the unpin work is consistent wrt ->pending. */
3890 smp_rmb();
3891 intel_crtc->unpin_work = NULL;
3892
3893 if (work->event)
3894 drm_send_vblank_event(intel_crtc->base.dev,
3895 intel_crtc->pipe,
3896 work->event);
3897
3898 drm_crtc_vblank_put(&intel_crtc->base);
3899
3900 wake_up_all(&dev_priv->pending_flip_queue);
3901 queue_work(dev_priv->wq, &work->work);
3902
3903 trace_i915_flip_complete(intel_crtc->plane,
3904 work->pending_flip_obj);
3905}
3906
46a55d30 3907void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3908{
0f91128d 3909 struct drm_device *dev = crtc->dev;
5bb61643 3910 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3911
2c10d571 3912 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW		 3913 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3914 !intel_crtc_has_pending_flip(crtc),
3915 60*HZ) == 0)) {
3916 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3917
5e2d7afc 3918 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3919 if (intel_crtc->unpin_work) {
3920 WARN_ONCE(1, "Removing stuck page flip\n");
3921 page_flip_completed(intel_crtc);
3922 }
5e2d7afc 3923 spin_unlock_irq(&dev->event_lock);
9c787942 3924 }
5bb61643 3925
975d568a
CW		 3926 if (crtc->primary->fb) {
3927 mutex_lock(&dev->struct_mutex);
3928 intel_finish_fb(crtc->primary->fb);
3929 mutex_unlock(&dev->struct_mutex);
3930 }
e6c3a2a6
CW		 3931}
3932
e615efe4
ED		 3933/* Program iCLKIP clock to the desired frequency */
3934static void lpt_program_iclkip(struct drm_crtc *crtc)
3935{
3936 struct drm_device *dev = crtc->dev;
3937 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3938 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3939 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3940 u32 temp;
3941
a580516d 3942 mutex_lock(&dev_priv->sb_lock);
09153000 3943
e615efe4
ED		 3944 /* It is necessary to ungate the pixclk gate prior to programming
3945 * the divisors, and gate it back when it is done.
3946 */
3947 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3948
3949 /* Disable SSCCTL */
3950 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3951 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3952 SBI_SSCCTL_DISABLE,
3953 SBI_ICLK);
e615efe4
ED		 3954
3955 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3956 if (clock == 20000) {
e615efe4
ED		 3957 auxdiv = 1;
3958 divsel = 0x41;
3959 phaseinc = 0x20;
3960 } else {
3961 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3962 * but the adjusted_mode->crtc_clock in in KHz. To get the
3963 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3964 * convert the virtual clock precision to KHz here for higher
3965 * precision.
3966 */
3967 u32 iclk_virtual_root_freq = 172800 * 1000;
3968 u32 iclk_pi_range = 64;
3969 u32 desired_divisor, msb_divisor_value, pi_value;
3970
12d7ceed 3971 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3972 msb_divisor_value = desired_divisor / iclk_pi_range;
3973 pi_value = desired_divisor % iclk_pi_range;
3974
3975 auxdiv = 0;
3976 divsel = msb_divisor_value - 2;
3977 phaseinc = pi_value;
3978 }
3979
3980 /* This should not happen with any sane values */
3981 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3982 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3983 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3984 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3985
3986 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3987 clock,
e615efe4
ED		 3988 auxdiv,
3989 divsel,
3990 phasedir,
3991 phaseinc);
3992
3993 /* Program SSCDIVINTPHASE6 */
988d6ee8 3994 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3995 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3996 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3997 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3998 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3999 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4000 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 4001 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 4002
4003 /* Program SSCAUXDIV */
988d6ee8 4004 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 4005 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4006 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 4007 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 4008
4009 /* Enable modulator and associated divider */
988d6ee8 4010 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 4011 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 4012 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 4013
4014 /* Wait for initialization time */
4015 udelay(24);
4016
4017 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000 4018
a580516d 4019 mutex_unlock(&dev_priv->sb_lock);
e615efe4
ED		 4020}
4021
275f01b2
DV		 4022static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4023 enum pipe pch_transcoder)
4024{
4025 struct drm_device *dev = crtc->base.dev;
4026 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 4027 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 4028
4029 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4030 I915_READ(HTOTAL(cpu_transcoder)));
4031 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4032 I915_READ(HBLANK(cpu_transcoder)));
4033 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4034 I915_READ(HSYNC(cpu_transcoder)));
4035
4036 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4037 I915_READ(VTOTAL(cpu_transcoder)));
4038 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4039 I915_READ(VBLANK(cpu_transcoder)));
4040 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4041 I915_READ(VSYNC(cpu_transcoder)));
4042 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4043 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4044}
4045
003632d9 4046static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 4047{
4048 struct drm_i915_private *dev_priv = dev->dev_private;
4049 uint32_t temp;
4050
4051 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 4052 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 4053 return;
4054
4055 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4056 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4057
003632d9
ACO		 4058 temp &= ~FDI_BC_BIFURCATION_SELECT;
4059 if (enable)
4060 temp |= FDI_BC_BIFURCATION_SELECT;
4061
4062 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 4063 I915_WRITE(SOUTH_CHICKEN1, temp);
4064 POSTING_READ(SOUTH_CHICKEN1);
4065}
4066
4067static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4068{
4069 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 4070
4071 switch (intel_crtc->pipe) {
4072 case PIPE_A:
4073 break;
4074 case PIPE_B:
6e3c9717 4075 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4076 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4077 else
003632d9 4078 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4079
4080 break;
4081 case PIPE_C:
003632d9 4082 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4083
4084 break;
4085 default:
4086 BUG();
4087 }
4088}
4089
f67a559d
JB		 4090/*
4091 * Enable PCH resources required for PCH ports:
4092 * - PCH PLLs
4093 * - FDI training & RX/TX
4094 * - update transcoder timings
4095 * - DP transcoding bits
4096 * - transcoder
4097 */
4098static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 4099{
4100 struct drm_device *dev = crtc->dev;
4101 struct drm_i915_private *dev_priv = dev->dev_private;
4102 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4103 int pipe = intel_crtc->pipe;
ee7b9f93 4104 u32 reg, temp;
2c07245f 4105
ab9412ba 4106 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4107
1fbc0d78
DV		 4108 if (IS_IVYBRIDGE(dev))
4109 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4110
cd986abb
DV		 4111 /* Write the TU size bits before fdi link training, so that error
4112 * detection works. */
4113 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4114 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4115
c98e9dcf 4116 /* For PCH output, training FDI link */
674cf967 4117 dev_priv->display.fdi_link_train(crtc);
2c07245f 4118
3ad8a208
DV		 4119 /* We need to program the right clock selection before writing the pixel
4120 * mutliplier into the DPLL. */
303b81e0 4121 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4122 u32 sel;
4b645f14 4123
c98e9dcf 4124 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4125 temp |= TRANS_DPLL_ENABLE(pipe);
4126 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4127 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4128 temp |= sel;
4129 else
4130 temp &= ~sel;
c98e9dcf 4131 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4132 }
5eddb70b 4133
3ad8a208
DV		 4134 /* XXX: pch pll's can be enabled any time before we enable the PCH
4135 * transcoder, and we actually should do this to not upset any PCH
4136 * transcoder that already use the clock when we share it.
4137 *
4138 * Note that enable_shared_dpll tries to do the right thing, but
4139 * get_shared_dpll unconditionally resets the pll - we need that to have
4140 * the right LVDS enable sequence. */
85b3894f 4141 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4142
d9b6cb56
JB		 4143 /* set transcoder timing, panel must allow it */
4144 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4145 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4146
303b81e0 4147 intel_fdi_normal_train(crtc);
5e84e1a4 4148
c98e9dcf 4149 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4150 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4151 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4152 reg = TRANS_DP_CTL(pipe);
4153 temp = I915_READ(reg);
4154 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4155 TRANS_DP_SYNC_MASK |
4156 TRANS_DP_BPC_MASK);
e3ef4479 4157 temp |= TRANS_DP_OUTPUT_ENABLE;
9325c9f0 4158 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4159
4160 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4161 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4162 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4163 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4164
4165 switch (intel_trans_dp_port_sel(crtc)) {
4166 case PCH_DP_B:
5eddb70b 4167 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4168 break;
4169 case PCH_DP_C:
5eddb70b 4170 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4171 break;
4172 case PCH_DP_D:
5eddb70b 4173 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4174 break;
4175 default:
e95d41e1 4176 BUG();
32f9d658 4177 }
2c07245f 4178
5eddb70b 4179 I915_WRITE(reg, temp);
6be4a607 4180 }
b52eb4dc 4181
b8a4f404 4182 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4183}
4184
1507e5bd
PZ		 4185static void lpt_pch_enable(struct drm_crtc *crtc)
4186{
4187 struct drm_device *dev = crtc->dev;
4188 struct drm_i915_private *dev_priv = dev->dev_private;
4189 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4190 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4191
ab9412ba 4192 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4193
8c52b5e8 4194 lpt_program_iclkip(crtc);
1507e5bd 4195
0540e488 4196 /* Set transcoder timing. */
275f01b2 4197 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4198
937bb610 4199 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4200}
4201
716c2e55 4202void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 4203{
e2b78267 4204 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 4205
4206 if (pll == NULL)
4207 return;
4208
3e369b76 4209 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
1e6f2ddc 4210 WARN(1, "bad %s crtc mask\n", pll->name);
ee7b9f93
JB		 4211 return;
4212 }
4213
3e369b76
ACO		 4214 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4215 if (pll->config.crtc_mask == 0) {
f4a091c7
DV		 4216 WARN_ON(pll->on);
4217 WARN_ON(pll->active);
4218 }
4219
6e3c9717 4220 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 4221}
4222
190f68c5
ACO		 4223struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4224 struct intel_crtc_state *crtc_state)
ee7b9f93 4225{
e2b78267 4226 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4227 struct intel_shared_dpll *pll;
e2b78267 4228 enum intel_dpll_id i;
ee7b9f93 4229
98b6bd99
DV		 4230 if (HAS_PCH_IBX(dev_priv->dev)) {
4231 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4232 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4233 pll = &dev_priv->shared_dplls[i];
98b6bd99 4234
46edb027
DV		 4235 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4236 crtc->base.base.id, pll->name);
98b6bd99 4237
8bd31e67 4238 WARN_ON(pll->new_config->crtc_mask);
f2a69f44 4239
98b6bd99
DV		 4240 goto found;
4241 }
4242
bcddf610
S		 4243 if (IS_BROXTON(dev_priv->dev)) {
4244 /* PLL is attached to port in bxt */
4245 struct intel_encoder *encoder;
4246 struct intel_digital_port *intel_dig_port;
4247
4248 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4249 if (WARN_ON(!encoder))
4250 return NULL;
4251
4252 intel_dig_port = enc_to_dig_port(&encoder->base);
4253 /* 1:1 mapping between ports and PLLs */
4254 i = (enum intel_dpll_id)intel_dig_port->port;
4255 pll = &dev_priv->shared_dplls[i];
4256 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4257 crtc->base.base.id, pll->name);
4258 WARN_ON(pll->new_config->crtc_mask);
4259
4260 goto found;
4261 }
4262
e72f9fbf
DV		 4263 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4264 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4265
4266 /* Only want to check enabled timings first */
8bd31e67 4267 if (pll->new_config->crtc_mask == 0)
ee7b9f93
JB		 4268 continue;
4269
190f68c5 4270 if (memcmp(&crtc_state->dpll_hw_state,
8bd31e67
ACO		 4271 &pll->new_config->hw_state,
4272 sizeof(pll->new_config->hw_state)) == 0) {
4273 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4274 crtc->base.base.id, pll->name,
8bd31e67
ACO		 4275 pll->new_config->crtc_mask,
4276 pll->active);
ee7b9f93
JB		 4277 goto found;
4278 }
4279 }
4280
4281 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4282 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4283 pll = &dev_priv->shared_dplls[i];
8bd31e67 4284 if (pll->new_config->crtc_mask == 0) {
46edb027
DV		 4285 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4286 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4287 goto found;
4288 }
4289 }
4290
4291 return NULL;
4292
4293found:
8bd31e67 4294 if (pll->new_config->crtc_mask == 0)
190f68c5 4295 pll->new_config->hw_state = crtc_state->dpll_hw_state;
f2a69f44 4296
190f68c5 4297 crtc_state->shared_dpll = i;
46edb027
DV		 4298 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4299 pipe_name(crtc->pipe));
ee7b9f93 4300
8bd31e67 4301 pll->new_config->crtc_mask |= 1 << crtc->pipe;
e04c7350 4302
ee7b9f93
JB		 4303 return pll;
4304}
4305
8bd31e67
ACO		 4306/**
4307 * intel_shared_dpll_start_config - start a new PLL staged config
4308 * @dev_priv: DRM device
4309 * @clear_pipes: mask of pipes that will have their PLLs freed
4310 *
4311 * Starts a new PLL staged config, copying the current config but
4312 * releasing the references of pipes specified in clear_pipes.
4313 */
4314static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4315 unsigned clear_pipes)
4316{
4317 struct intel_shared_dpll *pll;
4318 enum intel_dpll_id i;
4319
4320 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4321 pll = &dev_priv->shared_dplls[i];
4322
4323 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4324 GFP_KERNEL);
4325 if (!pll->new_config)
4326 goto cleanup;
4327
4328 pll->new_config->crtc_mask &= ~clear_pipes;
4329 }
4330
4331 return 0;
4332
4333cleanup:
4334 while (--i >= 0) {
4335 pll = &dev_priv->shared_dplls[i];
f354d733 4336 kfree(pll->new_config);
8bd31e67
ACO		 4337 pll->new_config = NULL;
4338 }
4339
4340 return -ENOMEM;
4341}
4342
4343static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4344{
4345 struct intel_shared_dpll *pll;
4346 enum intel_dpll_id i;
4347
4348 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4349 pll = &dev_priv->shared_dplls[i];
4350
4351 WARN_ON(pll->new_config == &pll->config);
4352
4353 pll->config = *pll->new_config;
4354 kfree(pll->new_config);
4355 pll->new_config = NULL;
4356 }
4357}
4358
4359static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4360{
4361 struct intel_shared_dpll *pll;
4362 enum intel_dpll_id i;
4363
4364 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4365 pll = &dev_priv->shared_dplls[i];
4366
4367 WARN_ON(pll->new_config == &pll->config);
4368
4369 kfree(pll->new_config);
4370 pll->new_config = NULL;
4371 }
4372}
4373
a1520318 4374static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4375{
4376 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4377 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4378 u32 temp;
4379
4380 temp = I915_READ(dslreg);
4381 udelay(500);
4382 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4383 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4384 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4385 }
4386}
4387
a1b2278e
CK		 4388/**
4389 * skl_update_scaler_users - Stages update to crtc's scaler state
4390 * @intel_crtc: crtc
4391 * @crtc_state: crtc_state
4392 * @plane: plane (NULL indicates crtc is requesting update)
4393 * @plane_state: plane's state
4394 * @force_detach: request unconditional detachment of scaler
4395 *
4396 * This function updates scaler state for requested plane or crtc.
4397 * To request scaler usage update for a plane, caller shall pass plane pointer.
4398 * To request scaler usage update for crtc, caller shall pass plane pointer
4399 * as NULL.
4400 *
4401 * Return
4402 * 0 - scaler_usage updated successfully
4403 * error - requested scaling cannot be supported or other error condition
4404 */
4405int
4406skl_update_scaler_users(
4407 struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state,
4408 struct intel_plane *intel_plane, struct intel_plane_state *plane_state,
4409 int force_detach)
4410{
4411 int need_scaling;
4412 int idx;
4413 int src_w, src_h, dst_w, dst_h;
4414 int *scaler_id;
4415 struct drm_framebuffer *fb;
4416 struct intel_crtc_scaler_state *scaler_state;
6156a456 4417 unsigned int rotation;
a1b2278e
CK		 4418
4419 if (!intel_crtc || !crtc_state)
4420 return 0;
4421
4422 scaler_state = &crtc_state->scaler_state;
4423
4424 idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX;
4425 fb = intel_plane ? plane_state->base.fb : NULL;
4426
4427 if (intel_plane) {
4428 src_w = drm_rect_width(&plane_state->src) >> 16;
4429 src_h = drm_rect_height(&plane_state->src) >> 16;
4430 dst_w = drm_rect_width(&plane_state->dst);
4431 dst_h = drm_rect_height(&plane_state->dst);
4432 scaler_id = &plane_state->scaler_id;
6156a456 4433 rotation = plane_state->base.rotation;
a1b2278e
CK		 4434 } else {
4435 struct drm_display_mode *adjusted_mode =
4436 &crtc_state->base.adjusted_mode;
4437 src_w = crtc_state->pipe_src_w;
4438 src_h = crtc_state->pipe_src_h;
4439 dst_w = adjusted_mode->hdisplay;
4440 dst_h = adjusted_mode->vdisplay;
4441 scaler_id = &scaler_state->scaler_id;
6156a456 4442 rotation = DRM_ROTATE_0;
a1b2278e 4443 }
6156a456
CK		 4444
4445 need_scaling = intel_rotation_90_or_270(rotation) ?
4446 (src_h != dst_w || src_w != dst_h):
4447 (src_w != dst_w || src_h != dst_h);
a1b2278e
CK		 4448
4449 /*
4450 * if plane is being disabled or scaler is no more required or force detach
4451 * - free scaler binded to this plane/crtc
4452 * - in order to do this, update crtc->scaler_usage
4453 *
4454 * Here scaler state in crtc_state is set free so that
4455 * scaler can be assigned to other user. Actual register
4456 * update to free the scaler is done in plane/panel-fit programming.
4457 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4458 */
4459 if (force_detach || !need_scaling || (intel_plane &&
4460 (!fb || !plane_state->visible))) {
4461 if (*scaler_id >= 0) {
4462 scaler_state->scaler_users &= ~(1 << idx);
4463 scaler_state->scalers[*scaler_id].in_use = 0;
4464
4465 DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4466 "crtc_state = %p scaler_users = 0x%x\n",
4467 intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC",
4468 intel_plane ? intel_plane->base.base.id :
4469 intel_crtc->base.base.id, crtc_state,
4470 scaler_state->scaler_users);
4471 *scaler_id = -1;
4472 }
4473 return 0;
4474 }
4475
4476 /* range checks */
4477 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4478 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4479
4480 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4481 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4482 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4483 "size is out of scaler range\n",
4484 intel_plane ? "PLANE" : "CRTC",
4485 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4486 intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h);
4487 return -EINVAL;
4488 }
4489
4490 /* check colorkey */
225c228a
CK		 4491 if (WARN_ON(intel_plane &&
4492 intel_plane->ckey.flags != I915_SET_COLORKEY_NONE)) {
4493 DRM_DEBUG_KMS("PLANE:%d scaling %ux%u->%ux%u not allowed with colorkey",
4494 intel_plane->base.base.id, src_w, src_h, dst_w, dst_h);
a1b2278e
CK		 4495 return -EINVAL;
4496 }
4497
4498 /* Check src format */
4499 if (intel_plane) {
4500 switch (fb->pixel_format) {
4501 case DRM_FORMAT_RGB565:
4502 case DRM_FORMAT_XBGR8888:
4503 case DRM_FORMAT_XRGB8888:
4504 case DRM_FORMAT_ABGR8888:
4505 case DRM_FORMAT_ARGB8888:
4506 case DRM_FORMAT_XRGB2101010:
a1b2278e 4507 case DRM_FORMAT_XBGR2101010:
a1b2278e
CK		 4508 case DRM_FORMAT_YUYV:
4509 case DRM_FORMAT_YVYU:
4510 case DRM_FORMAT_UYVY:
4511 case DRM_FORMAT_VYUY:
4512 break;
4513 default:
4514 DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4515 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4516 return -EINVAL;
4517 }
4518 }
4519
4520 /* mark this plane as a scaler user in crtc_state */
4521 scaler_state->scaler_users |= (1 << idx);
4522 DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4523 "crtc_state = %p scaler_users = 0x%x\n",
4524 intel_plane ? "PLANE" : "CRTC",
4525 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4526 src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users);
4527 return 0;
4528}
4529
4530static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
bd2e244f
JB		 4531{
4532 struct drm_device *dev = crtc->base.dev;
4533 struct drm_i915_private *dev_priv = dev->dev_private;
4534 int pipe = crtc->pipe;
a1b2278e
CK		 4535 struct intel_crtc_scaler_state *scaler_state =
4536 &crtc->config->scaler_state;
4537
4538 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4539
4540 /* To update pfit, first update scaler state */
4541 skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable);
4542 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4543 skl_detach_scalers(crtc);
4544 if (!enable)
4545 return;
bd2e244f 4546
6e3c9717 4547 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK		 4548 int id;
4549
4550 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4551 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4552 return;
4553 }
4554
4555 id = scaler_state->scaler_id;
4556 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4557 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4558 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4559 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4560
4561 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB		 4562 }
4563}
4564
b074cec8
JB		 4565static void ironlake_pfit_enable(struct intel_crtc *crtc)
4566{
4567 struct drm_device *dev = crtc->base.dev;
4568 struct drm_i915_private *dev_priv = dev->dev_private;
4569 int pipe = crtc->pipe;
4570
6e3c9717 4571 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4572 /* Force use of hard-coded filter coefficients
4573 * as some pre-programmed values are broken,
4574 * e.g. x201.
4575 */
4576 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4577 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4578 PF_PIPE_SEL_IVB(pipe));
4579 else
4580 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4581 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4582 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4583 }
4584}
4585
4a3b8769 4586static void intel_enable_sprite_planes(struct drm_crtc *crtc)
bb53d4ae
VS		 4587{
4588 struct drm_device *dev = crtc->dev;
4589 enum pipe pipe = to_intel_crtc(crtc)->pipe;
af2b653b 4590 struct drm_plane *plane;
bb53d4ae
VS		 4591 struct intel_plane *intel_plane;
4592
af2b653b
MR		 4593 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4594 intel_plane = to_intel_plane(plane);
bb53d4ae
VS		 4595 if (intel_plane->pipe == pipe)
4596 intel_plane_restore(&intel_plane->base);
af2b653b 4597 }
bb53d4ae
VS		 4598}
4599
20bc8673 4600void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4601{
cea165c3
VS		 4602 struct drm_device *dev = crtc->base.dev;
4603 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4604
6e3c9717 4605 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4606 return;
4607
cea165c3
VS		 4608 /* We can only enable IPS after we enable a plane and wait for a vblank */
4609 intel_wait_for_vblank(dev, crtc->pipe);
4610
d77e4531 4611 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4612 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4613 mutex_lock(&dev_priv->rps.hw_lock);
4614 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4615 mutex_unlock(&dev_priv->rps.hw_lock);
4616 /* Quoting Art Runyan: "its not safe to expect any particular
4617 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4618 * mailbox." Moreover, the mailbox may return a bogus state,
4619 * so we need to just enable it and continue on.
2a114cc1
BW		 4620 */
4621 } else {
4622 I915_WRITE(IPS_CTL, IPS_ENABLE);
4623 /* The bit only becomes 1 in the next vblank, so this wait here
4624 * is essentially intel_wait_for_vblank. If we don't have this
4625 * and don't wait for vblanks until the end of crtc_enable, then
4626 * the HW state readout code will complain that the expected
4627 * IPS_CTL value is not the one we read. */
4628 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4629 DRM_ERROR("Timed out waiting for IPS enable\n");
4630 }
d77e4531
PZ		 4631}
4632
20bc8673 4633void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4634{
4635 struct drm_device *dev = crtc->base.dev;
4636 struct drm_i915_private *dev_priv = dev->dev_private;
4637
6e3c9717 4638 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4639 return;
4640
4641 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4642 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4643 mutex_lock(&dev_priv->rps.hw_lock);
4644 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4645 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4646 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4647 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4648 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4649 } else {
2a114cc1 4650 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4651 POSTING_READ(IPS_CTL);
4652 }
d77e4531
PZ		 4653
4654 /* We need to wait for a vblank before we can disable the plane. */
4655 intel_wait_for_vblank(dev, crtc->pipe);
4656}
4657
4658/** Loads the palette/gamma unit for the CRTC with the prepared values */
4659static void intel_crtc_load_lut(struct drm_crtc *crtc)
4660{
4661 struct drm_device *dev = crtc->dev;
4662 struct drm_i915_private *dev_priv = dev->dev_private;
4663 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4664 enum pipe pipe = intel_crtc->pipe;
4665 int palreg = PALETTE(pipe);
4666 int i;
4667 bool reenable_ips = false;
4668
4669 /* The clocks have to be on to load the palette. */
83d65738 4670 if (!crtc->state->enable || !intel_crtc->active)
d77e4531
PZ		 4671 return;
4672
50360403 4673 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
409ee761 4674 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4675 assert_dsi_pll_enabled(dev_priv);
4676 else
4677 assert_pll_enabled(dev_priv, pipe);
4678 }
4679
4680 /* use legacy palette for Ironlake */
7a1db49a 4681 if (!HAS_GMCH_DISPLAY(dev))
d77e4531
PZ		 4682 palreg = LGC_PALETTE(pipe);
4683
4684 /* Workaround : Do not read or write the pipe palette/gamma data while
4685 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4686 */
6e3c9717 4687 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4688 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4689 GAMMA_MODE_MODE_SPLIT)) {
4690 hsw_disable_ips(intel_crtc);
4691 reenable_ips = true;
4692 }
4693
4694 for (i = 0; i < 256; i++) {
4695 I915_WRITE(palreg + 4 * i,
4696 (intel_crtc->lut_r[i] << 16) |
4697 (intel_crtc->lut_g[i] << 8) |
4698 intel_crtc->lut_b[i]);
4699 }
4700
4701 if (reenable_ips)
4702 hsw_enable_ips(intel_crtc);
4703}
4704
7cac945f 4705static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
d3eedb1a 4706{
7cac945f 4707 if (intel_crtc->overlay) {
d3eedb1a
VS		 4708 struct drm_device *dev = intel_crtc->base.dev;
4709 struct drm_i915_private *dev_priv = dev->dev_private;
4710
4711 mutex_lock(&dev->struct_mutex);
4712 dev_priv->mm.interruptible = false;
4713 (void) intel_overlay_switch_off(intel_crtc->overlay);
4714 dev_priv->mm.interruptible = true;
4715 mutex_unlock(&dev->struct_mutex);
4716 }
4717
4718 /* Let userspace switch the overlay on again. In most cases userspace
4719 * has to recompute where to put it anyway.
4720 */
4721}
4722
87d4300a
ML		 4723/**
4724 * intel_post_enable_primary - Perform operations after enabling primary plane
4725 * @crtc: the CRTC whose primary plane was just enabled
4726 *
4727 * Performs potentially sleeping operations that must be done after the primary
4728 * plane is enabled, such as updating FBC and IPS. Note that this may be
4729 * called due to an explicit primary plane update, or due to an implicit
4730 * re-enable that is caused when a sprite plane is updated to no longer
4731 * completely hide the primary plane.
4732 */
4733static void
4734intel_post_enable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4735{
4736 struct drm_device *dev = crtc->dev;
87d4300a 4737 struct drm_i915_private *dev_priv = dev->dev_private;
a5c4d7bc
VS		 4738 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4739 int pipe = intel_crtc->pipe;
a5c4d7bc 4740
87d4300a
ML		 4741 /*
4742 * BDW signals flip done immediately if the plane
4743 * is disabled, even if the plane enable is already
4744 * armed to occur at the next vblank :(
4745 */
4746 if (IS_BROADWELL(dev))
4747 intel_wait_for_vblank(dev, pipe);
a5c4d7bc 4748
87d4300a
ML		 4749 /*
4750 * FIXME IPS should be fine as long as one plane is
4751 * enabled, but in practice it seems to have problems
4752 * when going from primary only to sprite only and vice
4753 * versa.
4754 */
a5c4d7bc
VS		 4755 hsw_enable_ips(intel_crtc);
4756
4757 mutex_lock(&dev->struct_mutex);
7ff0ebcc 4758 intel_fbc_update(dev);
a5c4d7bc 4759 mutex_unlock(&dev->struct_mutex);
f99d7069
DV		 4760
4761 /*
87d4300a
ML		 4762 * Gen2 reports pipe underruns whenever all planes are disabled.
4763 * So don't enable underrun reporting before at least some planes
4764 * are enabled.
4765 * FIXME: Need to fix the logic to work when we turn off all planes
4766 * but leave the pipe running.
f99d7069 4767 */
87d4300a
ML		 4768 if (IS_GEN2(dev))
4769 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4770
4771 /* Underruns don't raise interrupts, so check manually. */
4772 if (HAS_GMCH_DISPLAY(dev))
4773 i9xx_check_fifo_underruns(dev_priv);
a5c4d7bc
VS		 4774}
4775
87d4300a
ML		 4776/**
4777 * intel_pre_disable_primary - Perform operations before disabling primary plane
4778 * @crtc: the CRTC whose primary plane is to be disabled
4779 *
4780 * Performs potentially sleeping operations that must be done before the
4781 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4782 * be called due to an explicit primary plane update, or due to an implicit
4783 * disable that is caused when a sprite plane completely hides the primary
4784 * plane.
4785 */
4786static void
4787intel_pre_disable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4788{
4789 struct drm_device *dev = crtc->dev;
4790 struct drm_i915_private *dev_priv = dev->dev_private;
4791 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4792 int pipe = intel_crtc->pipe;
a5c4d7bc 4793
87d4300a
ML		 4794 /*
4795 * Gen2 reports pipe underruns whenever all planes are disabled.
4796 * So diasble underrun reporting before all the planes get disabled.
4797 * FIXME: Need to fix the logic to work when we turn off all planes
4798 * but leave the pipe running.
4799 */
4800 if (IS_GEN2(dev))
4801 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
a5c4d7bc 4802
87d4300a
ML		 4803 /*
4804 * Vblank time updates from the shadow to live plane control register
4805 * are blocked if the memory self-refresh mode is active at that
4806 * moment. So to make sure the plane gets truly disabled, disable
4807 * first the self-refresh mode. The self-refresh enable bit in turn
4808 * will be checked/applied by the HW only at the next frame start
4809 * event which is after the vblank start event, so we need to have a
4810 * wait-for-vblank between disabling the plane and the pipe.
4811 */
4812 if (HAS_GMCH_DISPLAY(dev))
4813 intel_set_memory_cxsr(dev_priv, false);
4814
4815 mutex_lock(&dev->struct_mutex);
e35fef21 4816 if (dev_priv->fbc.crtc == intel_crtc)
7ff0ebcc 4817 intel_fbc_disable(dev);
87d4300a 4818 mutex_unlock(&dev->struct_mutex);
a5c4d7bc 4819
87d4300a
ML		 4820 /*
4821 * FIXME IPS should be fine as long as one plane is
4822 * enabled, but in practice it seems to have problems
4823 * when going from primary only to sprite only and vice
4824 * versa.
4825 */
a5c4d7bc 4826 hsw_disable_ips(intel_crtc);
87d4300a
ML		 4827}
4828
4829static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4830{
2d847d45
RV		 4831 struct drm_device *dev = crtc->dev;
4832 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4833 int pipe = intel_crtc->pipe;
4834
87d4300a
ML		 4835 intel_enable_primary_hw_plane(crtc->primary, crtc);
4836 intel_enable_sprite_planes(crtc);
4837 intel_crtc_update_cursor(crtc, true);
87d4300a
ML		 4838
4839 intel_post_enable_primary(crtc);
2d847d45
RV		 4840
4841 /*
4842 * FIXME: Once we grow proper nuclear flip support out of this we need
4843 * to compute the mask of flip planes precisely. For the time being
4844 * consider this a flip to a NULL plane.
4845 */
4846 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
87d4300a
ML		 4847}
4848
4849static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4850{
4851 struct drm_device *dev = crtc->dev;
4852 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4853 struct intel_plane *intel_plane;
4854 int pipe = intel_crtc->pipe;
4855
4856 intel_crtc_wait_for_pending_flips(crtc);
4857
4858 intel_pre_disable_primary(crtc);
a5c4d7bc 4859
7cac945f 4860 intel_crtc_dpms_overlay_disable(intel_crtc);
27321ae8
ML		 4861 for_each_intel_plane(dev, intel_plane) {
4862 if (intel_plane->pipe == pipe) {
4863 struct drm_crtc *from = intel_plane->base.crtc;
4864
4865 intel_plane->disable_plane(&intel_plane->base,
4866 from ?: crtc, true);
4867 }
4868 }
f98551ae 4869
f99d7069
DV		 4870 /*
4871 * FIXME: Once we grow proper nuclear flip support out of this we need
4872 * to compute the mask of flip planes precisely. For the time being
4873 * consider this a flip to a NULL plane.
4874 */
4875 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4876}
4877
f67a559d
JB		 4878static void ironlake_crtc_enable(struct drm_crtc *crtc)
4879{
4880 struct drm_device *dev = crtc->dev;
4881 struct drm_i915_private *dev_priv = dev->dev_private;
4882 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4883 struct intel_encoder *encoder;
f67a559d 4884 int pipe = intel_crtc->pipe;
f67a559d 4885
83d65738 4886 WARN_ON(!crtc->state->enable);
08a48469 4887
f67a559d
JB		 4888 if (intel_crtc->active)
4889 return;
4890
6e3c9717 4891 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4892 intel_prepare_shared_dpll(intel_crtc);
4893
6e3c9717 4894 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4895 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4896
4897 intel_set_pipe_timings(intel_crtc);
4898
6e3c9717 4899 if (intel_crtc->config->has_pch_encoder) {
29407aab 4900 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4901 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4902 }
4903
4904 ironlake_set_pipeconf(crtc);
4905
f67a559d 4906 intel_crtc->active = true;
8664281b 4907
a72e4c9f
DV		 4908 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4909 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4910
f6736a1a 4911 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4912 if (encoder->pre_enable)
4913 encoder->pre_enable(encoder);
f67a559d 4914
6e3c9717 4915 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4916 /* Note: FDI PLL enabling _must_ be done before we enable the
4917 * cpu pipes, hence this is separate from all the other fdi/pch
4918 * enabling. */
88cefb6c 4919 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4920 } else {
4921 assert_fdi_tx_disabled(dev_priv, pipe);
4922 assert_fdi_rx_disabled(dev_priv, pipe);
4923 }
f67a559d 4924
b074cec8 4925 ironlake_pfit_enable(intel_crtc);
f67a559d 4926
9c54c0dd
JB		 4927 /*
4928 * On ILK+ LUT must be loaded before the pipe is running but with
4929 * clocks enabled
4930 */
4931 intel_crtc_load_lut(crtc);
4932
f37fcc2a 4933 intel_update_watermarks(crtc);
e1fdc473 4934 intel_enable_pipe(intel_crtc);
f67a559d 4935
6e3c9717 4936 if (intel_crtc->config->has_pch_encoder)
f67a559d 4937 ironlake_pch_enable(crtc);
c98e9dcf 4938
f9b61ff6
DV		 4939 assert_vblank_disabled(crtc);
4940 drm_crtc_vblank_on(crtc);
4941
fa5c73b1
DV		 4942 for_each_encoder_on_crtc(dev, crtc, encoder)
4943 encoder->enable(encoder);
61b77ddd
DV		 4944
4945 if (HAS_PCH_CPT(dev))
a1520318 4946 cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB		 4947}
4948
42db64ef
PZ		 4949/* IPS only exists on ULT machines and is tied to pipe A. */
4950static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4951{
f5adf94e 4952 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4953}
4954
e4916946
PZ		 4955/*
4956 * This implements the workaround described in the "notes" section of the mode
4957 * set sequence documentation. When going from no pipes or single pipe to
4958 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4959 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4960 */
4961static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4962{
4963 struct drm_device *dev = crtc->base.dev;
4964 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4965
4966 /* We want to get the other_active_crtc only if there's only 1 other
4967 * active crtc. */
d3fcc808 4968 for_each_intel_crtc(dev, crtc_it) {
e4916946
PZ		 4969 if (!crtc_it->active || crtc_it == crtc)
4970 continue;
4971
4972 if (other_active_crtc)
4973 return;
4974
4975 other_active_crtc = crtc_it;
4976 }
4977 if (!other_active_crtc)
4978 return;
4979
4980 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4981 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4982}
4983
4f771f10
PZ		 4984static void haswell_crtc_enable(struct drm_crtc *crtc)
4985{
4986 struct drm_device *dev = crtc->dev;
4987 struct drm_i915_private *dev_priv = dev->dev_private;
4988 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4989 struct intel_encoder *encoder;
4990 int pipe = intel_crtc->pipe;
4f771f10 4991
83d65738 4992 WARN_ON(!crtc->state->enable);
4f771f10
PZ		 4993
4994 if (intel_crtc->active)
4995 return;
4996
df8ad70c
DV		 4997 if (intel_crtc_to_shared_dpll(intel_crtc))
4998 intel_enable_shared_dpll(intel_crtc);
4999
6e3c9717 5000 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5001 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 5002
5003 intel_set_pipe_timings(intel_crtc);
5004
6e3c9717
ACO		 5005 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
5006 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
5007 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 5008 }
5009
6e3c9717 5010 if (intel_crtc->config->has_pch_encoder) {
229fca97 5011 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 5012 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 5013 }
5014
5015 haswell_set_pipeconf(crtc);
5016
5017 intel_set_pipe_csc(crtc);
5018
4f771f10 5019 intel_crtc->active = true;
8664281b 5020
a72e4c9f 5021 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ		 5022 for_each_encoder_on_crtc(dev, crtc, encoder)
5023 if (encoder->pre_enable)
5024 encoder->pre_enable(encoder);
5025
6e3c9717 5026 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 5027 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5028 true);
4fe9467d
ID		 5029 dev_priv->display.fdi_link_train(crtc);
5030 }
5031
1f544388 5032 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 5033
ff6d9f55 5034 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 5035 skylake_pfit_update(intel_crtc, 1);
ff6d9f55 5036 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5037 ironlake_pfit_enable(intel_crtc);
ff6d9f55
JB		 5038 else
5039 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10
PZ		 5040
5041 /*
5042 * On ILK+ LUT must be loaded before the pipe is running but with
5043 * clocks enabled
5044 */
5045 intel_crtc_load_lut(crtc);
5046
1f544388 5047 intel_ddi_set_pipe_settings(crtc);
8228c251 5048 intel_ddi_enable_transcoder_func(crtc);
4f771f10 5049
f37fcc2a 5050 intel_update_watermarks(crtc);
e1fdc473 5051 intel_enable_pipe(intel_crtc);
42db64ef 5052
6e3c9717 5053 if (intel_crtc->config->has_pch_encoder)
1507e5bd 5054 lpt_pch_enable(crtc);
4f771f10 5055
6e3c9717 5056 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA		 5057 intel_ddi_set_vc_payload_alloc(crtc, true);
5058
f9b61ff6
DV		 5059 assert_vblank_disabled(crtc);
5060 drm_crtc_vblank_on(crtc);
5061
8807e55b 5062 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 5063 encoder->enable(encoder);
8807e55b
JN		 5064 intel_opregion_notify_encoder(encoder, true);
5065 }
4f771f10 5066
e4916946
PZ		 5067 /* If we change the relative order between pipe/planes enabling, we need
5068 * to change the workaround. */
5069 haswell_mode_set_planes_workaround(intel_crtc);
4f771f10
PZ		 5070}
5071
3f8dce3a
DV		 5072static void ironlake_pfit_disable(struct intel_crtc *crtc)
5073{
5074 struct drm_device *dev = crtc->base.dev;
5075 struct drm_i915_private *dev_priv = dev->dev_private;
5076 int pipe = crtc->pipe;
5077
5078 /* To avoid upsetting the power well on haswell only disable the pfit if
5079 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 5080 if (crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 5081 I915_WRITE(PF_CTL(pipe), 0);
5082 I915_WRITE(PF_WIN_POS(pipe), 0);
5083 I915_WRITE(PF_WIN_SZ(pipe), 0);
5084 }
5085}
5086
6be4a607
JB		 5087static void ironlake_crtc_disable(struct drm_crtc *crtc)
5088{
5089 struct drm_device *dev = crtc->dev;
5090 struct drm_i915_private *dev_priv = dev->dev_private;
5091 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5092 struct intel_encoder *encoder;
6be4a607 5093 int pipe = intel_crtc->pipe;
5eddb70b 5094 u32 reg, temp;
b52eb4dc 5095
f7abfe8b
CW		 5096 if (!intel_crtc->active)
5097 return;
5098
ea9d758d
DV		 5099 for_each_encoder_on_crtc(dev, crtc, encoder)
5100 encoder->disable(encoder);
5101
f9b61ff6
DV		 5102 drm_crtc_vblank_off(crtc);
5103 assert_vblank_disabled(crtc);
5104
6e3c9717 5105 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 5106 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 5107
575f7ab7 5108 intel_disable_pipe(intel_crtc);
32f9d658 5109
3f8dce3a 5110 ironlake_pfit_disable(intel_crtc);
2c07245f 5111
5a74f70a
VS		 5112 if (intel_crtc->config->has_pch_encoder)
5113 ironlake_fdi_disable(crtc);
5114
bf49ec8c
DV		 5115 for_each_encoder_on_crtc(dev, crtc, encoder)
5116 if (encoder->post_disable)
5117 encoder->post_disable(encoder);
2c07245f 5118
6e3c9717 5119 if (intel_crtc->config->has_pch_encoder) {
d925c59a 5120 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 5121
d925c59a
DV		 5122 if (HAS_PCH_CPT(dev)) {
5123 /* disable TRANS_DP_CTL */
5124 reg = TRANS_DP_CTL(pipe);
5125 temp = I915_READ(reg);
5126 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5127 TRANS_DP_PORT_SEL_MASK);
5128 temp |= TRANS_DP_PORT_SEL_NONE;
5129 I915_WRITE(reg, temp);
5130
5131 /* disable DPLL_SEL */
5132 temp = I915_READ(PCH_DPLL_SEL);
11887397 5133 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 5134 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 5135 }
e3421a18 5136
d925c59a 5137 /* disable PCH DPLL */
e72f9fbf 5138 intel_disable_shared_dpll(intel_crtc);
8db9d77b 5139
d925c59a
DV		 5140 ironlake_fdi_pll_disable(intel_crtc);
5141 }
6b383a7f 5142
f7abfe8b 5143 intel_crtc->active = false;
46ba614c 5144 intel_update_watermarks(crtc);
d1ebd816
BW		 5145
5146 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5147 intel_fbc_update(dev);
d1ebd816 5148 mutex_unlock(&dev->struct_mutex);
6be4a607 5149}
1b3c7a47 5150
4f771f10 5151static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 5152{
4f771f10
PZ		 5153 struct drm_device *dev = crtc->dev;
5154 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5156 struct intel_encoder *encoder;
6e3c9717 5157 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 5158
4f771f10
PZ		 5159 if (!intel_crtc->active)
5160 return;
5161
8807e55b
JN		 5162 for_each_encoder_on_crtc(dev, crtc, encoder) {
5163 intel_opregion_notify_encoder(encoder, false);
4f771f10 5164 encoder->disable(encoder);
8807e55b 5165 }
4f771f10 5166
f9b61ff6
DV		 5167 drm_crtc_vblank_off(crtc);
5168 assert_vblank_disabled(crtc);
5169
6e3c9717 5170 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 5171 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5172 false);
575f7ab7 5173 intel_disable_pipe(intel_crtc);
4f771f10 5174
6e3c9717 5175 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 5176 intel_ddi_set_vc_payload_alloc(crtc, false);
5177
ad80a810 5178 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5179
ff6d9f55 5180 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 5181 skylake_pfit_update(intel_crtc, 0);
ff6d9f55 5182 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5183 ironlake_pfit_disable(intel_crtc);
ff6d9f55
JB		 5184 else
5185 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10 5186
1f544388 5187 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5188
6e3c9717 5189 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 5190 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 5191 intel_ddi_fdi_disable(crtc);
83616634 5192 }
4f771f10 5193
97b040aa
ID		 5194 for_each_encoder_on_crtc(dev, crtc, encoder)
5195 if (encoder->post_disable)
5196 encoder->post_disable(encoder);
5197
4f771f10 5198 intel_crtc->active = false;
46ba614c 5199 intel_update_watermarks(crtc);
4f771f10
PZ		 5200
5201 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5202 intel_fbc_update(dev);
4f771f10 5203 mutex_unlock(&dev->struct_mutex);
df8ad70c
DV		 5204
5205 if (intel_crtc_to_shared_dpll(intel_crtc))
5206 intel_disable_shared_dpll(intel_crtc);
4f771f10
PZ		 5207}
5208
ee7b9f93
JB		 5209static void ironlake_crtc_off(struct drm_crtc *crtc)
5210{
5211 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 5212 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 5213}
5214
6441ab5f 5215
2dd24552
JB		 5216static void i9xx_pfit_enable(struct intel_crtc *crtc)
5217{
5218 struct drm_device *dev = crtc->base.dev;
5219 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5220 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5221
681a8504 5222 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 5223 return;
5224
2dd24552 5225 /*
c0b03411
DV		 5226 * The panel fitter should only be adjusted whilst the pipe is disabled,
5227 * according to register description and PRM.
2dd24552 5228 */
c0b03411
DV		 5229 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5230 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5231
b074cec8
JB		 5232 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5233 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 5234
5235 /* Border color in case we don't scale up to the full screen. Black by
5236 * default, change to something else for debugging. */
5237 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 5238}
5239
d05410f9
DA		 5240static enum intel_display_power_domain port_to_power_domain(enum port port)
5241{
5242 switch (port) {
5243 case PORT_A:
5244 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5245 case PORT_B:
5246 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5247 case PORT_C:
5248 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5249 case PORT_D:
5250 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5251 default:
5252 WARN_ON_ONCE(1);
5253 return POWER_DOMAIN_PORT_OTHER;
5254 }
5255}
5256
77d22dca
ID		 5257#define for_each_power_domain(domain, mask) \
5258 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5259 if ((1 << (domain)) & (mask))
5260
319be8ae
ID		 5261enum intel_display_power_domain
5262intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5263{
5264 struct drm_device *dev = intel_encoder->base.dev;
5265 struct intel_digital_port *intel_dig_port;
5266
5267 switch (intel_encoder->type) {
5268 case INTEL_OUTPUT_UNKNOWN:
5269 /* Only DDI platforms should ever use this output type */
5270 WARN_ON_ONCE(!HAS_DDI(dev));
5271 case INTEL_OUTPUT_DISPLAYPORT:
5272 case INTEL_OUTPUT_HDMI:
5273 case INTEL_OUTPUT_EDP:
5274 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5275 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 5276 case INTEL_OUTPUT_DP_MST:
5277 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5278 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 5279 case INTEL_OUTPUT_ANALOG:
5280 return POWER_DOMAIN_PORT_CRT;
5281 case INTEL_OUTPUT_DSI:
5282 return POWER_DOMAIN_PORT_DSI;
5283 default:
5284 return POWER_DOMAIN_PORT_OTHER;
5285 }
5286}
5287
5288static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5289{
319be8ae
ID		 5290 struct drm_device *dev = crtc->dev;
5291 struct intel_encoder *intel_encoder;
5292 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5293 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 5294 unsigned long mask;
5295 enum transcoder transcoder;
5296
5297 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5298
5299 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5300 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 5301 if (intel_crtc->config->pch_pfit.enabled ||
5302 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 5303 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5304
319be8ae
ID		 5305 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5306 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5307
77d22dca
ID		 5308 return mask;
5309}
5310
679dacd4 5311static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
77d22dca 5312{
679dacd4 5313 struct drm_device *dev = state->dev;
77d22dca
ID		 5314 struct drm_i915_private *dev_priv = dev->dev_private;
5315 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5316 struct intel_crtc *crtc;
5317
5318 /*
5319 * First get all needed power domains, then put all unneeded, to avoid
5320 * any unnecessary toggling of the power wells.
5321 */
d3fcc808 5322 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5323 enum intel_display_power_domain domain;
5324
83d65738 5325 if (!crtc->base.state->enable)
77d22dca
ID		 5326 continue;
5327
319be8ae 5328 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
77d22dca
ID		 5329
5330 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5331 intel_display_power_get(dev_priv, domain);
5332 }
5333
50f6e502 5334 if (dev_priv->display.modeset_global_resources)
679dacd4 5335 dev_priv->display.modeset_global_resources(state);
50f6e502 5336
d3fcc808 5337 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5338 enum intel_display_power_domain domain;
5339
5340 for_each_power_domain(domain, crtc->enabled_power_domains)
5341 intel_display_power_put(dev_priv, domain);
5342
5343 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5344 }
5345
5346 intel_display_set_init_power(dev_priv, false);
5347}
5348
f8437dd1
VK		 5349void broxton_set_cdclk(struct drm_device *dev, int frequency)
5350{
5351 struct drm_i915_private *dev_priv = dev->dev_private;
5352 uint32_t divider;
5353 uint32_t ratio;
5354 uint32_t current_freq;
5355 int ret;
5356
5357 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5358 switch (frequency) {
5359 case 144000:
5360 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5361 ratio = BXT_DE_PLL_RATIO(60);
5362 break;
5363 case 288000:
5364 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5365 ratio = BXT_DE_PLL_RATIO(60);
5366 break;
5367 case 384000:
5368 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5369 ratio = BXT_DE_PLL_RATIO(60);
5370 break;
5371 case 576000:
5372 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5373 ratio = BXT_DE_PLL_RATIO(60);
5374 break;
5375 case 624000:
5376 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5377 ratio = BXT_DE_PLL_RATIO(65);
5378 break;
5379 case 19200:
5380 /*
5381 * Bypass frequency with DE PLL disabled. Init ratio, divider
5382 * to suppress GCC warning.
5383 */
5384 ratio = 0;
5385 divider = 0;
5386 break;
5387 default:
5388 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5389
5390 return;
5391 }
5392
5393 mutex_lock(&dev_priv->rps.hw_lock);
5394 /* Inform power controller of upcoming frequency change */
5395 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5396 0x80000000);
5397 mutex_unlock(&dev_priv->rps.hw_lock);
5398
5399 if (ret) {
5400 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5401 ret, frequency);
5402 return;
5403 }
5404
5405 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5406 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5407 current_freq = current_freq * 500 + 1000;
5408
5409 /*
5410 * DE PLL has to be disabled when
5411 * - setting to 19.2MHz (bypass, PLL isn't used)
5412 * - before setting to 624MHz (PLL needs toggling)
5413 * - before setting to any frequency from 624MHz (PLL needs toggling)
5414 */
5415 if (frequency == 19200 || frequency == 624000 ||
5416 current_freq == 624000) {
5417 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5418 /* Timeout 200us */
5419 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5420 1))
5421 DRM_ERROR("timout waiting for DE PLL unlock\n");
5422 }
5423
5424 if (frequency != 19200) {
5425 uint32_t val;
5426
5427 val = I915_READ(BXT_DE_PLL_CTL);
5428 val &= ~BXT_DE_PLL_RATIO_MASK;
5429 val |= ratio;
5430 I915_WRITE(BXT_DE_PLL_CTL, val);
5431
5432 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5433 /* Timeout 200us */
5434 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5435 DRM_ERROR("timeout waiting for DE PLL lock\n");
5436
5437 val = I915_READ(CDCLK_CTL);
5438 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5439 val |= divider;
5440 /*
5441 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5442 * enable otherwise.
5443 */
5444 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5445 if (frequency >= 500000)
5446 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5447
5448 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5449 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5450 val |= (frequency - 1000) / 500;
5451 I915_WRITE(CDCLK_CTL, val);
5452 }
5453
5454 mutex_lock(&dev_priv->rps.hw_lock);
5455 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5456 DIV_ROUND_UP(frequency, 25000));
5457 mutex_unlock(&dev_priv->rps.hw_lock);
5458
5459 if (ret) {
5460 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5461 ret, frequency);
5462 return;
5463 }
5464
5465 dev_priv->cdclk_freq = frequency;
5466}
5467
5468void broxton_init_cdclk(struct drm_device *dev)
5469{
5470 struct drm_i915_private *dev_priv = dev->dev_private;
5471 uint32_t val;
5472
5473 /*
5474 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5475 * or else the reset will hang because there is no PCH to respond.
5476 * Move the handshake programming to initialization sequence.
5477 * Previously was left up to BIOS.
5478 */
5479 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5480 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5481 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5482
5483 /* Enable PG1 for cdclk */
5484 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5485
5486 /* check if cd clock is enabled */
5487 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5488 DRM_DEBUG_KMS("Display already initialized\n");
5489 return;
5490 }
5491
5492 /*
5493 * FIXME:
5494 * - The initial CDCLK needs to be read from VBT.
5495 * Need to make this change after VBT has changes for BXT.
5496 * - check if setting the max (or any) cdclk freq is really necessary
5497 * here, it belongs to modeset time
5498 */
5499 broxton_set_cdclk(dev, 624000);
5500
5501 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
22e02c0b
VS		 5502 POSTING_READ(DBUF_CTL);
5503
f8437dd1
VK		 5504 udelay(10);
5505
5506 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5507 DRM_ERROR("DBuf power enable timeout!\n");
5508}
5509
5510void broxton_uninit_cdclk(struct drm_device *dev)
5511{
5512 struct drm_i915_private *dev_priv = dev->dev_private;
5513
5514 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
22e02c0b
VS		 5515 POSTING_READ(DBUF_CTL);
5516
f8437dd1
VK		 5517 udelay(10);
5518
5519 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5520 DRM_ERROR("DBuf power disable timeout!\n");
5521
5522 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5523 broxton_set_cdclk(dev, 19200);
5524
5525 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5526}
5527
5d96d8af
DL		 5528static const struct skl_cdclk_entry {
5529 unsigned int freq;
5530 unsigned int vco;
5531} skl_cdclk_frequencies[] = {
5532 { .freq = 308570, .vco = 8640 },
5533 { .freq = 337500, .vco = 8100 },
5534 { .freq = 432000, .vco = 8640 },
5535 { .freq = 450000, .vco = 8100 },
5536 { .freq = 540000, .vco = 8100 },
5537 { .freq = 617140, .vco = 8640 },
5538 { .freq = 675000, .vco = 8100 },
5539};
5540
5541static unsigned int skl_cdclk_decimal(unsigned int freq)
5542{
5543 return (freq - 1000) / 500;
5544}
5545
5546static unsigned int skl_cdclk_get_vco(unsigned int freq)
5547{
5548 unsigned int i;
5549
5550 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5551 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5552
5553 if (e->freq == freq)
5554 return e->vco;
5555 }
5556
5557 return 8100;
5558}
5559
5560static void
5561skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5562{
5563 unsigned int min_freq;
5564 u32 val;
5565
5566 /* select the minimum CDCLK before enabling DPLL 0 */
5567 val = I915_READ(CDCLK_CTL);
5568 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5569 val |= CDCLK_FREQ_337_308;
5570
5571 if (required_vco == 8640)
5572 min_freq = 308570;
5573 else
5574 min_freq = 337500;
5575
5576 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5577
5578 I915_WRITE(CDCLK_CTL, val);
5579 POSTING_READ(CDCLK_CTL);
5580
5581 /*
5582 * We always enable DPLL0 with the lowest link rate possible, but still
5583 * taking into account the VCO required to operate the eDP panel at the
5584 * desired frequency. The usual DP link rates operate with a VCO of
5585 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5586 * The modeset code is responsible for the selection of the exact link
5587 * rate later on, with the constraint of choosing a frequency that
5588 * works with required_vco.
5589 */
5590 val = I915_READ(DPLL_CTRL1);
5591
5592 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5593 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5594 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5595 if (required_vco == 8640)
5596 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5597 SKL_DPLL0);
5598 else
5599 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5600 SKL_DPLL0);
5601
5602 I915_WRITE(DPLL_CTRL1, val);
5603 POSTING_READ(DPLL_CTRL1);
5604
5605 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5606
5607 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5608 DRM_ERROR("DPLL0 not locked\n");
5609}
5610
5611static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5612{
5613 int ret;
5614 u32 val;
5615
5616 /* inform PCU we want to change CDCLK */
5617 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5618 mutex_lock(&dev_priv->rps.hw_lock);
5619 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5620 mutex_unlock(&dev_priv->rps.hw_lock);
5621
5622 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5623}
5624
5625static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5626{
5627 unsigned int i;
5628
5629 for (i = 0; i < 15; i++) {
5630 if (skl_cdclk_pcu_ready(dev_priv))
5631 return true;
5632 udelay(10);
5633 }
5634
5635 return false;
5636}
5637
5638static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5639{
5640 u32 freq_select, pcu_ack;
5641
5642 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5643
5644 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5645 DRM_ERROR("failed to inform PCU about cdclk change\n");
5646 return;
5647 }
5648
5649 /* set CDCLK_CTL */
5650 switch(freq) {
5651 case 450000:
5652 case 432000:
5653 freq_select = CDCLK_FREQ_450_432;
5654 pcu_ack = 1;
5655 break;
5656 case 540000:
5657 freq_select = CDCLK_FREQ_540;
5658 pcu_ack = 2;
5659 break;
5660 case 308570:
5661 case 337500:
5662 default:
5663 freq_select = CDCLK_FREQ_337_308;
5664 pcu_ack = 0;
5665 break;
5666 case 617140:
5667 case 675000:
5668 freq_select = CDCLK_FREQ_675_617;
5669 pcu_ack = 3;
5670 break;
5671 }
5672
5673 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5674 POSTING_READ(CDCLK_CTL);
5675
5676 /* inform PCU of the change */
5677 mutex_lock(&dev_priv->rps.hw_lock);
5678 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5679 mutex_unlock(&dev_priv->rps.hw_lock);
5680}
5681
5682void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5683{
5684 /* disable DBUF power */
5685 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5686 POSTING_READ(DBUF_CTL);
5687
5688 udelay(10);
5689
5690 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5691 DRM_ERROR("DBuf power disable timeout\n");
5692
5693 /* disable DPLL0 */
5694 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5695 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5696 DRM_ERROR("Couldn't disable DPLL0\n");
5697
5698 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5699}
5700
5701void skl_init_cdclk(struct drm_i915_private *dev_priv)
5702{
5703 u32 val;
5704 unsigned int required_vco;
5705
5706 /* enable PCH reset handshake */
5707 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5708 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5709
5710 /* enable PG1 and Misc I/O */
5711 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5712
5713 /* DPLL0 already enabed !? */
5714 if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5715 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5716 return;
5717 }
5718
5719 /* enable DPLL0 */
5720 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5721 skl_dpll0_enable(dev_priv, required_vco);
5722
5723 /* set CDCLK to the frequency the BIOS chose */
5724 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5725
5726 /* enable DBUF power */
5727 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5728 POSTING_READ(DBUF_CTL);
5729
5730 udelay(10);
5731
5732 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5733 DRM_ERROR("DBuf power enable timeout\n");
5734}
5735
dfcab17e 5736/* returns HPLL frequency in kHz */
f8bf63fd 5737static int valleyview_get_vco(struct drm_i915_private *dev_priv)
30a970c6 5738{
586f49dc 5739 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
30a970c6 5740
586f49dc 5741 /* Obtain SKU information */
a580516d 5742 mutex_lock(&dev_priv->sb_lock);
586f49dc
JB		 5743 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5744 CCK_FUSE_HPLL_FREQ_MASK;
a580516d 5745 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5746
dfcab17e 5747 return vco_freq[hpll_freq] * 1000;
30a970c6
JB		 5748}
5749
44913155
VS		 5750static void intel_update_max_cdclk(struct drm_device *dev)
5751{
5752 struct drm_i915_private *dev_priv = dev->dev_private;
5753
5754 if (IS_VALLEYVIEW(dev)) {
5755 dev_priv->max_cdclk_freq = 400000;
5756 } else {
5757 /* otherwise assume cdclk is fixed */
5758 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5759 }
5760
5761 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5762 dev_priv->max_cdclk_freq);
5763}
5764
b6283055 5765static void intel_update_cdclk(struct drm_device *dev)
f8bf63fd
VS		 5766{
5767 struct drm_i915_private *dev_priv = dev->dev_private;
5768
164dfd28 5769 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
43dc52c3 5770 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
164dfd28 5771 dev_priv->cdclk_freq);
f8bf63fd
VS		 5772
5773 /*
5774 * Program the gmbus_freq based on the cdclk frequency.
5775 * BSpec erroneously claims we should aim for 4MHz, but
5776 * in fact 1MHz is the correct frequency.
5777 */
b6283055
VS		 5778 if (IS_VALLEYVIEW(dev)) {
5779 /*
5780 * Program the gmbus_freq based on the cdclk frequency.
5781 * BSpec erroneously claims we should aim for 4MHz, but
5782 * in fact 1MHz is the correct frequency.
5783 */
5784 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5785 }
44913155
VS		 5786
5787 if (dev_priv->max_cdclk_freq == 0)
5788 intel_update_max_cdclk(dev);
f8bf63fd
VS		 5789}
5790
30a970c6
JB		 5791/* Adjust CDclk dividers to allow high res or save power if possible */
5792static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5793{
5794 struct drm_i915_private *dev_priv = dev->dev_private;
5795 u32 val, cmd;
5796
164dfd28
VK		 5797 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5798 != dev_priv->cdclk_freq);
d60c4473 5799
dfcab17e 5800 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5801 cmd = 2;
dfcab17e 5802 else if (cdclk == 266667)
30a970c6
JB		 5803 cmd = 1;
5804 else
5805 cmd = 0;
5806
5807 mutex_lock(&dev_priv->rps.hw_lock);
5808 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5809 val &= ~DSPFREQGUAR_MASK;
5810 val |= (cmd << DSPFREQGUAR_SHIFT);
5811 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5812 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5813 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5814 50)) {
5815 DRM_ERROR("timed out waiting for CDclk change\n");
5816 }
5817 mutex_unlock(&dev_priv->rps.hw_lock);
5818
54433e91
VS		 5819 mutex_lock(&dev_priv->sb_lock);
5820
dfcab17e 5821 if (cdclk == 400000) {
6bcda4f0 5822 u32 divider;
30a970c6 5823
6bcda4f0 5824 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6 5825
30a970c6
JB		 5826 /* adjust cdclk divider */
5827 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
9cf33db5 5828 val &= ~DISPLAY_FREQUENCY_VALUES;
30a970c6
JB		 5829 val |= divider;
5830 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5831
5832 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5833 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5834 50))
5835 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5836 }
5837
30a970c6
JB		 5838 /* adjust self-refresh exit latency value */
5839 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5840 val &= ~0x7f;
5841
5842 /*
5843 * For high bandwidth configs, we set a higher latency in the bunit
5844 * so that the core display fetch happens in time to avoid underruns.
5845 */
dfcab17e 5846 if (cdclk == 400000)
30a970c6
JB		 5847 val |= 4500 / 250; /* 4.5 usec */
5848 else
5849 val |= 3000 / 250; /* 3.0 usec */
5850 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
54433e91 5851
a580516d 5852 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5853
b6283055 5854 intel_update_cdclk(dev);
30a970c6
JB		 5855}
5856
383c5a6a
VS		 5857static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5858{
5859 struct drm_i915_private *dev_priv = dev->dev_private;
5860 u32 val, cmd;
5861
164dfd28
VK		 5862 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5863 != dev_priv->cdclk_freq);
383c5a6a
VS		 5864
5865 switch (cdclk) {
383c5a6a
VS		 5866 case 333333:
5867 case 320000:
383c5a6a 5868 case 266667:
383c5a6a 5869 case 200000:
383c5a6a
VS		 5870 break;
5871 default:
5f77eeb0 5872 MISSING_CASE(cdclk);
383c5a6a
VS		 5873 return;
5874 }
5875
9d0d3fda
VS		 5876 /*
5877 * Specs are full of misinformation, but testing on actual
5878 * hardware has shown that we just need to write the desired
5879 * CCK divider into the Punit register.
5880 */
5881 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5882
383c5a6a
VS		 5883 mutex_lock(&dev_priv->rps.hw_lock);
5884 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5885 val &= ~DSPFREQGUAR_MASK_CHV;
5886 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5887 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5888 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5889 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5890 50)) {
5891 DRM_ERROR("timed out waiting for CDclk change\n");
5892 }
5893 mutex_unlock(&dev_priv->rps.hw_lock);
5894
b6283055 5895 intel_update_cdclk(dev);
383c5a6a
VS		 5896}
5897
30a970c6
JB		 5898static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5899 int max_pixclk)
5900{
6bcda4f0 5901 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5902 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5903
30a970c6
JB		 5904 /*
5905 * Really only a few cases to deal with, as only 4 CDclks are supported:
5906 * 200MHz
5907 * 267MHz
29dc7ef3 5908 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5909 * 400MHz (VLV only)
5910 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5911 * of the lower bin and adjust if needed.
e37c67a1
VS		 5912 *
5913 * We seem to get an unstable or solid color picture at 200MHz.
5914 * Not sure what's wrong. For now use 200MHz only when all pipes
5915 * are off.
30a970c6 5916 */
6cca3195
VS		 5917 if (!IS_CHERRYVIEW(dev_priv) &&
5918 max_pixclk > freq_320*limit/100)
dfcab17e 5919 return 400000;
6cca3195 5920 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5921 return freq_320;
e37c67a1 5922 else if (max_pixclk > 0)
dfcab17e 5923 return 266667;
e37c67a1
VS		 5924 else
5925 return 200000;
30a970c6
JB		 5926}
5927
f8437dd1
VK		 5928static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5929 int max_pixclk)
5930{
5931 /*
5932 * FIXME:
5933 * - remove the guardband, it's not needed on BXT
5934 * - set 19.2MHz bypass frequency if there are no active pipes
5935 */
5936 if (max_pixclk > 576000*9/10)
5937 return 624000;
5938 else if (max_pixclk > 384000*9/10)
5939 return 576000;
5940 else if (max_pixclk > 288000*9/10)
5941 return 384000;
5942 else if (max_pixclk > 144000*9/10)
5943 return 288000;
5944 else
5945 return 144000;
5946}
5947
a821fc46
ACO		 5948/* Compute the max pixel clock for new configuration. Uses atomic state if
5949 * that's non-NULL, look at current state otherwise. */
5950static int intel_mode_max_pixclk(struct drm_device *dev,
5951 struct drm_atomic_state *state)
30a970c6 5952{
30a970c6 5953 struct intel_crtc *intel_crtc;
304603f4 5954 struct intel_crtc_state *crtc_state;
30a970c6
JB		 5955 int max_pixclk = 0;
5956
d3fcc808 5957 for_each_intel_crtc(dev, intel_crtc) {
a821fc46
ACO		 5958 if (state)
5959 crtc_state =
5960 intel_atomic_get_crtc_state(state, intel_crtc);
5961 else
5962 crtc_state = intel_crtc->config;
304603f4
ACO		 5963 if (IS_ERR(crtc_state))
5964 return PTR_ERR(crtc_state);
5965
5966 if (!crtc_state->base.enable)
5967 continue;
5968
5969 max_pixclk = max(max_pixclk,
5970 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5971 }
5972
5973 return max_pixclk;
5974}
5975
0a9ab303 5976static int valleyview_modeset_global_pipes(struct drm_atomic_state *state)
30a970c6 5977{
304603f4 5978 struct drm_i915_private *dev_priv = to_i915(state->dev);
0a9ab303
ACO		 5979 struct drm_crtc *crtc;
5980 struct drm_crtc_state *crtc_state;
a821fc46 5981 int max_pixclk = intel_mode_max_pixclk(state->dev, state);
0a9ab303 5982 int cdclk, i;
30a970c6 5983
304603f4
ACO		 5984 if (max_pixclk < 0)
5985 return max_pixclk;
30a970c6 5986
f8437dd1
VK		 5987 if (IS_VALLEYVIEW(dev_priv))
5988 cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5989 else
5990 cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
5991
5992 if (cdclk == dev_priv->cdclk_freq)
304603f4 5993 return 0;
30a970c6 5994
0a9ab303
ACO		 5995 /* add all active pipes to the state */
5996 for_each_crtc(state->dev, crtc) {
5997 if (!crtc->state->enable)
5998 continue;
5999
6000 crtc_state = drm_atomic_get_crtc_state(state, crtc);
6001 if (IS_ERR(crtc_state))
6002 return PTR_ERR(crtc_state);
6003 }
6004
2f2d7aa1 6005 /* disable/enable all currently active pipes while we change cdclk */
0a9ab303
ACO		 6006 for_each_crtc_in_state(state, crtc, crtc_state, i)
6007 if (crtc_state->enable)
6008 crtc_state->mode_changed = true;
304603f4
ACO		 6009
6010 return 0;
30a970c6
JB		 6011}
6012
1e69cd74
VS		 6013static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6014{
6015 unsigned int credits, default_credits;
6016
6017 if (IS_CHERRYVIEW(dev_priv))
6018 default_credits = PFI_CREDIT(12);
6019 else
6020 default_credits = PFI_CREDIT(8);
6021
164dfd28 6022 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
1e69cd74
VS		 6023 /* CHV suggested value is 31 or 63 */
6024 if (IS_CHERRYVIEW(dev_priv))
6025 credits = PFI_CREDIT_31;
6026 else
6027 credits = PFI_CREDIT(15);
6028 } else {
6029 credits = default_credits;
6030 }
6031
6032 /*
6033 * WA - write default credits before re-programming
6034 * FIXME: should we also set the resend bit here?
6035 */
6036 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6037 default_credits);
6038
6039 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6040 credits | PFI_CREDIT_RESEND);
6041
6042 /*
6043 * FIXME is this guaranteed to clear
6044 * immediately or should we poll for it?
6045 */
6046 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6047}
6048
a821fc46 6049static void valleyview_modeset_global_resources(struct drm_atomic_state *old_state)
30a970c6 6050{
a821fc46 6051 struct drm_device *dev = old_state->dev;
30a970c6 6052 struct drm_i915_private *dev_priv = dev->dev_private;
a821fc46 6053 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
304603f4
ACO		 6054 int req_cdclk;
6055
a821fc46
ACO		 6056 /* The path in intel_mode_max_pixclk() with a NULL atomic state should
6057 * never fail. */
304603f4
ACO		 6058 if (WARN_ON(max_pixclk < 0))
6059 return;
30a970c6 6060
304603f4 6061 req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
30a970c6 6062
164dfd28 6063 if (req_cdclk != dev_priv->cdclk_freq) {
738c05c0
ID		 6064 /*
6065 * FIXME: We can end up here with all power domains off, yet
6066 * with a CDCLK frequency other than the minimum. To account
6067 * for this take the PIPE-A power domain, which covers the HW
6068 * blocks needed for the following programming. This can be
6069 * removed once it's guaranteed that we get here either with
6070 * the minimum CDCLK set, or the required power domains
6071 * enabled.
6072 */
6073 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6074
383c5a6a
VS		 6075 if (IS_CHERRYVIEW(dev))
6076 cherryview_set_cdclk(dev, req_cdclk);
6077 else
6078 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 6079
1e69cd74
VS		 6080 vlv_program_pfi_credits(dev_priv);
6081
738c05c0 6082 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
383c5a6a 6083 }
30a970c6
JB		 6084}
6085
89b667f8
JB		 6086static void valleyview_crtc_enable(struct drm_crtc *crtc)
6087{
6088 struct drm_device *dev = crtc->dev;
a72e4c9f 6089 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 6090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6091 struct intel_encoder *encoder;
6092 int pipe = intel_crtc->pipe;
23538ef1 6093 bool is_dsi;
89b667f8 6094
83d65738 6095 WARN_ON(!crtc->state->enable);
89b667f8
JB		 6096
6097 if (intel_crtc->active)
6098 return;
6099
409ee761 6100 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 6101
1ae0d137
VS		 6102 if (!is_dsi) {
6103 if (IS_CHERRYVIEW(dev))
6e3c9717 6104 chv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 6105 else
6e3c9717 6106 vlv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 6107 }
5b18e57c 6108
6e3c9717 6109 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6110 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6111
6112 intel_set_pipe_timings(intel_crtc);
6113
c14b0485
VS		 6114 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6115 struct drm_i915_private *dev_priv = dev->dev_private;
6116
6117 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6118 I915_WRITE(CHV_CANVAS(pipe), 0);
6119 }
6120
5b18e57c
DV		 6121 i9xx_set_pipeconf(intel_crtc);
6122
89b667f8 6123 intel_crtc->active = true;
89b667f8 6124
a72e4c9f 6125 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6126
89b667f8
JB		 6127 for_each_encoder_on_crtc(dev, crtc, encoder)
6128 if (encoder->pre_pll_enable)
6129 encoder->pre_pll_enable(encoder);
6130
9d556c99
CML		 6131 if (!is_dsi) {
6132 if (IS_CHERRYVIEW(dev))
6e3c9717 6133 chv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6134 else
6e3c9717 6135 vlv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6136 }
89b667f8
JB		 6137
6138 for_each_encoder_on_crtc(dev, crtc, encoder)
6139 if (encoder->pre_enable)
6140 encoder->pre_enable(encoder);
6141
2dd24552
JB		 6142 i9xx_pfit_enable(intel_crtc);
6143
63cbb074
VS		 6144 intel_crtc_load_lut(crtc);
6145
f37fcc2a 6146 intel_update_watermarks(crtc);
e1fdc473 6147 intel_enable_pipe(intel_crtc);
be6a6f8e 6148
4b3a9526
VS		 6149 assert_vblank_disabled(crtc);
6150 drm_crtc_vblank_on(crtc);
6151
f9b61ff6
DV		 6152 for_each_encoder_on_crtc(dev, crtc, encoder)
6153 encoder->enable(encoder);
89b667f8
JB		 6154}
6155
f13c2ef3
DV		 6156static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6157{
6158 struct drm_device *dev = crtc->base.dev;
6159 struct drm_i915_private *dev_priv = dev->dev_private;
6160
6e3c9717
ACO		 6161 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6162 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 6163}
6164
0b8765c6 6165static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 6166{
6167 struct drm_device *dev = crtc->dev;
a72e4c9f 6168 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 6169 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6170 struct intel_encoder *encoder;
79e53945 6171 int pipe = intel_crtc->pipe;
79e53945 6172
83d65738 6173 WARN_ON(!crtc->state->enable);
08a48469 6174
f7abfe8b
CW		 6175 if (intel_crtc->active)
6176 return;
6177
f13c2ef3
DV		 6178 i9xx_set_pll_dividers(intel_crtc);
6179
6e3c9717 6180 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6181 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6182
6183 intel_set_pipe_timings(intel_crtc);
6184
5b18e57c
DV		 6185 i9xx_set_pipeconf(intel_crtc);
6186
f7abfe8b 6187 intel_crtc->active = true;
6b383a7f 6188
4a3436e8 6189 if (!IS_GEN2(dev))
a72e4c9f 6190 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6191
9d6d9f19
MK		 6192 for_each_encoder_on_crtc(dev, crtc, encoder)
6193 if (encoder->pre_enable)
6194 encoder->pre_enable(encoder);
6195
f6736a1a
DV		 6196 i9xx_enable_pll(intel_crtc);
6197
2dd24552
JB		 6198 i9xx_pfit_enable(intel_crtc);
6199
63cbb074
VS		 6200 intel_crtc_load_lut(crtc);
6201
f37fcc2a 6202 intel_update_watermarks(crtc);
e1fdc473 6203 intel_enable_pipe(intel_crtc);
be6a6f8e 6204
4b3a9526
VS		 6205 assert_vblank_disabled(crtc);
6206 drm_crtc_vblank_on(crtc);
6207
f9b61ff6
DV		 6208 for_each_encoder_on_crtc(dev, crtc, encoder)
6209 encoder->enable(encoder);
0b8765c6 6210}
79e53945 6211
87476d63
DV		 6212static void i9xx_pfit_disable(struct intel_crtc *crtc)
6213{
6214 struct drm_device *dev = crtc->base.dev;
6215 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 6216
6e3c9717 6217 if (!crtc->config->gmch_pfit.control)
328d8e82 6218 return;
87476d63 6219
328d8e82 6220 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 6221
328d8e82
DV		 6222 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6223 I915_READ(PFIT_CONTROL));
6224 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 6225}
6226
0b8765c6
JB		 6227static void i9xx_crtc_disable(struct drm_crtc *crtc)
6228{
6229 struct drm_device *dev = crtc->dev;
6230 struct drm_i915_private *dev_priv = dev->dev_private;
6231 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6232 struct intel_encoder *encoder;
0b8765c6 6233 int pipe = intel_crtc->pipe;
ef9c3aee 6234
f7abfe8b
CW		 6235 if (!intel_crtc->active)
6236 return;
6237
6304cd91
VS		 6238 /*
6239 * On gen2 planes are double buffered but the pipe isn't, so we must
6240 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 6241 * We also need to wait on all gmch platforms because of the
6242 * self-refresh mode constraint explained above.
6304cd91 6243 */
564ed191 6244 intel_wait_for_vblank(dev, pipe);
6304cd91 6245
4b3a9526
VS		 6246 for_each_encoder_on_crtc(dev, crtc, encoder)
6247 encoder->disable(encoder);
6248
f9b61ff6
DV		 6249 drm_crtc_vblank_off(crtc);
6250 assert_vblank_disabled(crtc);
6251
575f7ab7 6252 intel_disable_pipe(intel_crtc);
24a1f16d 6253
87476d63 6254 i9xx_pfit_disable(intel_crtc);
24a1f16d 6255
89b667f8
JB		 6256 for_each_encoder_on_crtc(dev, crtc, encoder)
6257 if (encoder->post_disable)
6258 encoder->post_disable(encoder);
6259
409ee761 6260 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 6261 if (IS_CHERRYVIEW(dev))
6262 chv_disable_pll(dev_priv, pipe);
6263 else if (IS_VALLEYVIEW(dev))
6264 vlv_disable_pll(dev_priv, pipe);
6265 else
1c4e0274 6266 i9xx_disable_pll(intel_crtc);
076ed3b2 6267 }
0b8765c6 6268
4a3436e8 6269 if (!IS_GEN2(dev))
a72e4c9f 6270 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4a3436e8 6271
f7abfe8b 6272 intel_crtc->active = false;
46ba614c 6273 intel_update_watermarks(crtc);
f37fcc2a 6274
efa9624e 6275 mutex_lock(&dev->struct_mutex);
7ff0ebcc 6276 intel_fbc_update(dev);
efa9624e 6277 mutex_unlock(&dev->struct_mutex);
0b8765c6
JB		 6278}
6279
ee7b9f93
JB		 6280static void i9xx_crtc_off(struct drm_crtc *crtc)
6281{
6282}
6283
b04c5bd6
BF		 6284/* Master function to enable/disable CRTC and corresponding power wells */
6285void intel_crtc_control(struct drm_crtc *crtc, bool enable)
976f8a20
DV		 6286{
6287 struct drm_device *dev = crtc->dev;
6288 struct drm_i915_private *dev_priv = dev->dev_private;
0e572fe7 6289 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
0e572fe7
DV		 6290 enum intel_display_power_domain domain;
6291 unsigned long domains;
976f8a20 6292
0e572fe7
DV		 6293 if (enable) {
6294 if (!intel_crtc->active) {
e1e9fb84
DV		 6295 domains = get_crtc_power_domains(crtc);
6296 for_each_power_domain(domain, domains)
6297 intel_display_power_get(dev_priv, domain);
6298 intel_crtc->enabled_power_domains = domains;
0e572fe7
DV		 6299
6300 dev_priv->display.crtc_enable(crtc);
ce22dba9 6301 intel_crtc_enable_planes(crtc);
0e572fe7
DV		 6302 }
6303 } else {
6304 if (intel_crtc->active) {
ce22dba9 6305 intel_crtc_disable_planes(crtc);
0e572fe7
DV		 6306 dev_priv->display.crtc_disable(crtc);
6307
e1e9fb84
DV		 6308 domains = intel_crtc->enabled_power_domains;
6309 for_each_power_domain(domain, domains)
6310 intel_display_power_put(dev_priv, domain);
6311 intel_crtc->enabled_power_domains = 0;
0e572fe7
DV		 6312 }
6313 }
b04c5bd6
BF		 6314}
6315
6316/**
6317 * Sets the power management mode of the pipe and plane.
6318 */
6319void intel_crtc_update_dpms(struct drm_crtc *crtc)
6320{
6321 struct drm_device *dev = crtc->dev;
6322 struct intel_encoder *intel_encoder;
6323 bool enable = false;
6324
6325 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6326 enable |= intel_encoder->connectors_active;
6327
6328 intel_crtc_control(crtc, enable);
0f63cca2
ACO		 6329
6330 crtc->state->active = enable;
976f8a20
DV		 6331}
6332
cdd59983
CW		 6333static void intel_crtc_disable(struct drm_crtc *crtc)
6334{
cdd59983 6335 struct drm_device *dev = crtc->dev;
976f8a20 6336 struct drm_connector *connector;
ee7b9f93 6337 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 6338
976f8a20 6339 /* crtc should still be enabled when we disable it. */
83d65738 6340 WARN_ON(!crtc->state->enable);
976f8a20 6341
ce22dba9 6342 intel_crtc_disable_planes(crtc);
976f8a20 6343 dev_priv->display.crtc_disable(crtc);
ee7b9f93
JB		 6344 dev_priv->display.off(crtc);
6345
70a101f8 6346 drm_plane_helper_disable(crtc->primary);
976f8a20
DV		 6347
6348 /* Update computed state. */
6349 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6350 if (!connector->encoder || !connector->encoder->crtc)
6351 continue;
6352
6353 if (connector->encoder->crtc != crtc)
6354 continue;
6355
6356 connector->dpms = DRM_MODE_DPMS_OFF;
6357 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 6358 }
6359}
6360
ea5b213a 6361void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 6362{
4ef69c7a 6363 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 6364
ea5b213a
CW		 6365 drm_encoder_cleanup(encoder);
6366 kfree(intel_encoder);
7e7d76c3
JB		 6367}
6368
9237329d 6369/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 6370 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6371 * state of the entire output pipe. */
9237329d 6372static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 6373{
5ab432ef
DV		 6374 if (mode == DRM_MODE_DPMS_ON) {
6375 encoder->connectors_active = true;
6376
b2cabb0e 6377 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 6378 } else {
6379 encoder->connectors_active = false;
6380
b2cabb0e 6381 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 6382 }
79e53945
JB		 6383}
6384
0a91ca29
DV		 6385/* Cross check the actual hw state with our own modeset state tracking (and it's
6386 * internal consistency). */
b980514c 6387static void intel_connector_check_state(struct intel_connector *connector)
79e53945 6388{
0a91ca29
DV		 6389 if (connector->get_hw_state(connector)) {
6390 struct intel_encoder *encoder = connector->encoder;
6391 struct drm_crtc *crtc;
6392 bool encoder_enabled;
6393 enum pipe pipe;
6394
6395 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6396 connector->base.base.id,
c23cc417 6397 connector->base.name);
0a91ca29 6398
0e32b39c
DA		 6399 /* there is no real hw state for MST connectors */
6400 if (connector->mst_port)
6401 return;
6402
e2c719b7 6403 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
0a91ca29 6404 "wrong connector dpms state\n");
e2c719b7 6405 I915_STATE_WARN(connector->base.encoder != &encoder->base,
0a91ca29 6406 "active connector not linked to encoder\n");
0a91ca29 6407
36cd7444 6408 if (encoder) {
e2c719b7 6409 I915_STATE_WARN(!encoder->connectors_active,
36cd7444
DA		 6410 "encoder->connectors_active not set\n");
6411
6412 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
e2c719b7
RC		 6413 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6414 if (I915_STATE_WARN_ON(!encoder->base.crtc))
36cd7444 6415 return;
0a91ca29 6416
36cd7444 6417 crtc = encoder->base.crtc;
0a91ca29 6418
83d65738
MR		 6419 I915_STATE_WARN(!crtc->state->enable,
6420 "crtc not enabled\n");
e2c719b7
RC		 6421 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6422 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
36cd7444
DA		 6423 "encoder active on the wrong pipe\n");
6424 }
0a91ca29 6425 }
79e53945
JB		 6426}
6427
08d9bc92
ACO		 6428int intel_connector_init(struct intel_connector *connector)
6429{
6430 struct drm_connector_state *connector_state;
6431
6432 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6433 if (!connector_state)
6434 return -ENOMEM;
6435
6436 connector->base.state = connector_state;
6437 return 0;
6438}
6439
6440struct intel_connector *intel_connector_alloc(void)
6441{
6442 struct intel_connector *connector;
6443
6444 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6445 if (!connector)
6446 return NULL;
6447
6448 if (intel_connector_init(connector) < 0) {
6449 kfree(connector);
6450 return NULL;
6451 }
6452
6453 return connector;
6454}
6455
5ab432ef
DV		 6456/* Even simpler default implementation, if there's really no special case to
6457 * consider. */
6458void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 6459{
5ab432ef
DV		 6460 /* All the simple cases only support two dpms states. */
6461 if (mode != DRM_MODE_DPMS_ON)
6462 mode = DRM_MODE_DPMS_OFF;
d4270e57 6463
5ab432ef
DV		 6464 if (mode == connector->dpms)
6465 return;
6466
6467 connector->dpms = mode;
6468
6469 /* Only need to change hw state when actually enabled */
c9976dcf
CW		 6470 if (connector->encoder)
6471 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
0a91ca29 6472
b980514c 6473 intel_modeset_check_state(connector->dev);
79e53945
JB		 6474}
6475
f0947c37
DV		 6476/* Simple connector->get_hw_state implementation for encoders that support only
6477 * one connector and no cloning and hence the encoder state determines the state
6478 * of the connector. */
6479bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 6480{
24929352 6481 enum pipe pipe = 0;
f0947c37 6482 struct intel_encoder *encoder = connector->encoder;
ea5b213a 6483
f0947c37 6484 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 6485}
6486
6d293983 6487static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 6488{
6d293983
ACO		 6489 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6490 return crtc_state->fdi_lanes;
d272ddfa
VS		 6491
6492 return 0;
6493}
6494
6d293983 6495static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6496 struct intel_crtc_state *pipe_config)
1857e1da 6497{
6d293983
ACO		 6498 struct drm_atomic_state *state = pipe_config->base.state;
6499 struct intel_crtc *other_crtc;
6500 struct intel_crtc_state *other_crtc_state;
6501
1857e1da
DV		 6502 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6503 pipe_name(pipe), pipe_config->fdi_lanes);
6504 if (pipe_config->fdi_lanes > 4) {
6505 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6506 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6507 return -EINVAL;
1857e1da
DV		 6508 }
6509
bafb6553 6510 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 6511 if (pipe_config->fdi_lanes > 2) {
6512 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6513 pipe_config->fdi_lanes);
6d293983 6514 return -EINVAL;
1857e1da 6515 } else {
6d293983 6516 return 0;
1857e1da
DV		 6517 }
6518 }
6519
6520 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 6521 return 0;
1857e1da
DV		 6522
6523 /* Ivybridge 3 pipe is really complicated */
6524 switch (pipe) {
6525 case PIPE_A:
6d293983 6526 return 0;
1857e1da 6527 case PIPE_B:
6d293983
ACO		 6528 if (pipe_config->fdi_lanes <= 2)
6529 return 0;
6530
6531 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6532 other_crtc_state =
6533 intel_atomic_get_crtc_state(state, other_crtc);
6534 if (IS_ERR(other_crtc_state))
6535 return PTR_ERR(other_crtc_state);
6536
6537 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV		 6538 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6539 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6540 return -EINVAL;
1857e1da 6541 }
6d293983 6542 return 0;
1857e1da 6543 case PIPE_C:
251cc67c
VS		 6544 if (pipe_config->fdi_lanes > 2) {
6545 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6546 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6547 return -EINVAL;
251cc67c 6548 }
6d293983
ACO		 6549
6550 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6551 other_crtc_state =
6552 intel_atomic_get_crtc_state(state, other_crtc);
6553 if (IS_ERR(other_crtc_state))
6554 return PTR_ERR(other_crtc_state);
6555
6556 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6557 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6558 return -EINVAL;
1857e1da 6559 }
6d293983 6560 return 0;
1857e1da
DV		 6561 default:
6562 BUG();
6563 }
6564}
6565
e29c22c0
DV		 6566#define RETRY 1
6567static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6568 struct intel_crtc_state *pipe_config)
877d48d5 6569{
1857e1da 6570 struct drm_device *dev = intel_crtc->base.dev;
2d112de7 6571 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 6572 int lane, link_bw, fdi_dotclock, ret;
6573 bool needs_recompute = false;
877d48d5 6574
e29c22c0 6575retry:
877d48d5
DV		 6576 /* FDI is a binary signal running at ~2.7GHz, encoding
6577 * each output octet as 10 bits. The actual frequency
6578 * is stored as a divider into a 100MHz clock, and the
6579 * mode pixel clock is stored in units of 1KHz.
6580 * Hence the bw of each lane in terms of the mode signal
6581 * is:
6582 */
6583 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6584
241bfc38 6585 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6586
2bd89a07 6587 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 6588 pipe_config->pipe_bpp);
6589
6590 pipe_config->fdi_lanes = lane;
6591
2bd89a07 6592 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6593 link_bw, &pipe_config->fdi_m_n);
1857e1da 6594
6d293983
ACO		 6595 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6596 intel_crtc->pipe, pipe_config);
6597 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV		 6598 pipe_config->pipe_bpp -= 2*3;
6599 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6600 pipe_config->pipe_bpp);
6601 needs_recompute = true;
6602 pipe_config->bw_constrained = true;
6603
6604 goto retry;
6605 }
6606
6607 if (needs_recompute)
6608 return RETRY;
6609
6d293983 6610 return ret;
877d48d5
DV		 6611}
6612
42db64ef 6613static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6614 struct intel_crtc_state *pipe_config)
42db64ef 6615{
d330a953 6616 pipe_config->ips_enabled = i915.enable_ips &&
3c4ca58c 6617 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 6618 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 6619}
6620
a43f6e0f 6621static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6622 struct intel_crtc_state *pipe_config)
79e53945 6623{
a43f6e0f 6624 struct drm_device *dev = crtc->base.dev;
8bd31e67 6625 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 6626 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
d03c93d4 6627 int ret;
89749350 6628
ad3a4479 6629 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 6630 if (INTEL_INFO(dev)->gen < 4) {
44913155 6631 int clock_limit = dev_priv->max_cdclk_freq;
cf532bb2
VS		 6632
6633 /*
6634 * Enable pixel doubling when the dot clock
6635 * is > 90% of the (display) core speed.
6636 *
b397c96b
VS		 6637 * GDG double wide on either pipe,
6638 * otherwise pipe A only.
cf532bb2 6639 */
b397c96b 6640 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 6641 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 6642 clock_limit *= 2;
cf532bb2 6643 pipe_config->double_wide = true;
ad3a4479
VS		 6644 }
6645
241bfc38 6646 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 6647 return -EINVAL;
2c07245f 6648 }
89749350 6649
1d1d0e27
VS		 6650 /*
6651 * Pipe horizontal size must be even in:
6652 * - DVO ganged mode
6653 * - LVDS dual channel mode
6654 * - Double wide pipe
6655 */
a93e255f 6656 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 6657 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6658 pipe_config->pipe_src_w &= ~1;
6659
8693a824
DL		 6660 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6661 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 6662 */
6663 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6664 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 6665 return -EINVAL;
44f46b42 6666
f5adf94e 6667 if (HAS_IPS(dev))
a43f6e0f
DV		 6668 hsw_compute_ips_config(crtc, pipe_config);
6669
877d48d5 6670 if (pipe_config->has_pch_encoder)
a43f6e0f 6671 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6672
d03c93d4
CK		 6673 /* FIXME: remove below call once atomic mode set is place and all crtc
6674 * related checks called from atomic_crtc_check function */
6675 ret = 0;
6676 DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6677 crtc, pipe_config->base.state);
6678 ret = intel_atomic_setup_scalers(dev, crtc, pipe_config);
6679
6680 return ret;
79e53945
JB		 6681}
6682
1652d19e
VS		 6683static int skylake_get_display_clock_speed(struct drm_device *dev)
6684{
6685 struct drm_i915_private *dev_priv = to_i915(dev);
6686 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6687 uint32_t cdctl = I915_READ(CDCLK_CTL);
6688 uint32_t linkrate;
6689
6690 if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
6691 WARN(1, "LCPLL1 not enabled\n");
6692 return 24000; /* 24MHz is the cd freq with NSSC ref */
6693 }
6694
6695 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6696 return 540000;
6697
6698 linkrate = (I915_READ(DPLL_CTRL1) &
71cd8423 6699 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1652d19e 6700
71cd8423
DL		 6701 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6702 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
1652d19e
VS		 6703 /* vco 8640 */
6704 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6705 case CDCLK_FREQ_450_432:
6706 return 432000;
6707 case CDCLK_FREQ_337_308:
6708 return 308570;
6709 case CDCLK_FREQ_675_617:
6710 return 617140;
6711 default:
6712 WARN(1, "Unknown cd freq selection\n");
6713 }
6714 } else {
6715 /* vco 8100 */
6716 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6717 case CDCLK_FREQ_450_432:
6718 return 450000;
6719 case CDCLK_FREQ_337_308:
6720 return 337500;
6721 case CDCLK_FREQ_675_617:
6722 return 675000;
6723 default:
6724 WARN(1, "Unknown cd freq selection\n");
6725 }
6726 }
6727
6728 /* error case, do as if DPLL0 isn't enabled */
6729 return 24000;
6730}
6731
6732static int broadwell_get_display_clock_speed(struct drm_device *dev)
6733{
6734 struct drm_i915_private *dev_priv = dev->dev_private;
6735 uint32_t lcpll = I915_READ(LCPLL_CTL);
6736 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6737
6738 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6739 return 800000;
6740 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6741 return 450000;
6742 else if (freq == LCPLL_CLK_FREQ_450)
6743 return 450000;
6744 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6745 return 540000;
6746 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6747 return 337500;
6748 else
6749 return 675000;
6750}
6751
6752static int haswell_get_display_clock_speed(struct drm_device *dev)
6753{
6754 struct drm_i915_private *dev_priv = dev->dev_private;
6755 uint32_t lcpll = I915_READ(LCPLL_CTL);
6756 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6757
6758 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6759 return 800000;
6760 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6761 return 450000;
6762 else if (freq == LCPLL_CLK_FREQ_450)
6763 return 450000;
6764 else if (IS_HSW_ULT(dev))
6765 return 337500;
6766 else
6767 return 540000;
79e53945
JB		 6768}
6769
25eb05fc
JB		 6770static int valleyview_get_display_clock_speed(struct drm_device *dev)
6771{
d197b7d3 6772 struct drm_i915_private *dev_priv = dev->dev_private;
d197b7d3
VS		 6773 u32 val;
6774 int divider;
6775
6bcda4f0
VS		 6776 if (dev_priv->hpll_freq == 0)
6777 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6778
a580516d 6779 mutex_lock(&dev_priv->sb_lock);
d197b7d3 6780 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
a580516d 6781 mutex_unlock(&dev_priv->sb_lock);
d197b7d3
VS		 6782
6783 divider = val & DISPLAY_FREQUENCY_VALUES;
6784
7d007f40
VS		 6785 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6786 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6787 "cdclk change in progress\n");
6788
6bcda4f0 6789 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
25eb05fc
JB		 6790}
6791
b37a6434
VS		 6792static int ilk_get_display_clock_speed(struct drm_device *dev)
6793{
6794 return 450000;
6795}
6796
e70236a8
JB		 6797static int i945_get_display_clock_speed(struct drm_device *dev)
6798{
6799 return 400000;
6800}
79e53945 6801
e70236a8 6802static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6803{
e907f170 6804 return 333333;
e70236a8 6805}
79e53945 6806
e70236a8
JB		 6807static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6808{
6809 return 200000;
6810}
79e53945 6811
257a7ffc
DV		 6812static int pnv_get_display_clock_speed(struct drm_device *dev)
6813{
6814 u16 gcfgc = 0;
6815
6816 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6817
6818 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6819 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6820 return 266667;
257a7ffc 6821 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6822 return 333333;
257a7ffc 6823 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6824 return 444444;
257a7ffc
DV		 6825 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6826 return 200000;
6827 default:
6828 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6829 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6830 return 133333;
257a7ffc 6831 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6832 return 166667;
257a7ffc
DV		 6833 }
6834}
6835
e70236a8
JB		 6836static int i915gm_get_display_clock_speed(struct drm_device *dev)
6837{
6838 u16 gcfgc = 0;
79e53945 6839
e70236a8
JB		 6840 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6841
6842 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6843 return 133333;
e70236a8
JB		 6844 else {
6845 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6846 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6847 return 333333;
e70236a8
JB		 6848 default:
6849 case GC_DISPLAY_CLOCK_190_200_MHZ:
6850 return 190000;
79e53945 6851 }
e70236a8
JB		 6852 }
6853}
6854
6855static int i865_get_display_clock_speed(struct drm_device *dev)
6856{
e907f170 6857 return 266667;
e70236a8
JB		 6858}
6859
1b1d2716 6860static int i85x_get_display_clock_speed(struct drm_device *dev)
e70236a8
JB		 6861{
6862 u16 hpllcc = 0;
1b1d2716 6863
65cd2b3f
VS		 6864 /*
6865 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6866 * encoding is different :(
6867 * FIXME is this the right way to detect 852GM/852GMV?
6868 */
6869 if (dev->pdev->revision == 0x1)
6870 return 133333;
6871
1b1d2716
VS		 6872 pci_bus_read_config_word(dev->pdev->bus,
6873 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6874
e70236a8
JB		 6875 /* Assume that the hardware is in the high speed state. This
6876 * should be the default.
6877 */
6878 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6879 case GC_CLOCK_133_200:
1b1d2716 6880 case GC_CLOCK_133_200_2:
e70236a8
JB		 6881 case GC_CLOCK_100_200:
6882 return 200000;
6883 case GC_CLOCK_166_250:
6884 return 250000;
6885 case GC_CLOCK_100_133:
e907f170 6886 return 133333;
1b1d2716
VS		 6887 case GC_CLOCK_133_266:
6888 case GC_CLOCK_133_266_2:
6889 case GC_CLOCK_166_266:
6890 return 266667;
e70236a8 6891 }
79e53945 6892
e70236a8
JB		 6893 /* Shouldn't happen */
6894 return 0;
6895}
79e53945 6896
e70236a8
JB		 6897static int i830_get_display_clock_speed(struct drm_device *dev)
6898{
e907f170 6899 return 133333;
79e53945
JB		 6900}
6901
34edce2f
VS		 6902static unsigned int intel_hpll_vco(struct drm_device *dev)
6903{
6904 struct drm_i915_private *dev_priv = dev->dev_private;
6905 static const unsigned int blb_vco[8] = {
6906 [0] = 3200000,
6907 [1] = 4000000,
6908 [2] = 5333333,
6909 [3] = 4800000,
6910 [4] = 6400000,
6911 };
6912 static const unsigned int pnv_vco[8] = {
6913 [0] = 3200000,
6914 [1] = 4000000,
6915 [2] = 5333333,
6916 [3] = 4800000,
6917 [4] = 2666667,
6918 };
6919 static const unsigned int cl_vco[8] = {
6920 [0] = 3200000,
6921 [1] = 4000000,
6922 [2] = 5333333,
6923 [3] = 6400000,
6924 [4] = 3333333,
6925 [5] = 3566667,
6926 [6] = 4266667,
6927 };
6928 static const unsigned int elk_vco[8] = {
6929 [0] = 3200000,
6930 [1] = 4000000,
6931 [2] = 5333333,
6932 [3] = 4800000,
6933 };
6934 static const unsigned int ctg_vco[8] = {
6935 [0] = 3200000,
6936 [1] = 4000000,
6937 [2] = 5333333,
6938 [3] = 6400000,
6939 [4] = 2666667,
6940 [5] = 4266667,
6941 };
6942 const unsigned int *vco_table;
6943 unsigned int vco;
6944 uint8_t tmp = 0;
6945
6946 /* FIXME other chipsets? */
6947 if (IS_GM45(dev))
6948 vco_table = ctg_vco;
6949 else if (IS_G4X(dev))
6950 vco_table = elk_vco;
6951 else if (IS_CRESTLINE(dev))
6952 vco_table = cl_vco;
6953 else if (IS_PINEVIEW(dev))
6954 vco_table = pnv_vco;
6955 else if (IS_G33(dev))
6956 vco_table = blb_vco;
6957 else
6958 return 0;
6959
6960 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6961
6962 vco = vco_table[tmp & 0x7];
6963 if (vco == 0)
6964 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6965 else
6966 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6967
6968 return vco;
6969}
6970
6971static int gm45_get_display_clock_speed(struct drm_device *dev)
6972{
6973 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6974 uint16_t tmp = 0;
6975
6976 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6977
6978 cdclk_sel = (tmp >> 12) & 0x1;
6979
6980 switch (vco) {
6981 case 2666667:
6982 case 4000000:
6983 case 5333333:
6984 return cdclk_sel ? 333333 : 222222;
6985 case 3200000:
6986 return cdclk_sel ? 320000 : 228571;
6987 default:
6988 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6989 return 222222;
6990 }
6991}
6992
6993static int i965gm_get_display_clock_speed(struct drm_device *dev)
6994{
6995 static const uint8_t div_3200[] = { 16, 10, 8 };
6996 static const uint8_t div_4000[] = { 20, 12, 10 };
6997 static const uint8_t div_5333[] = { 24, 16, 14 };
6998 const uint8_t *div_table;
6999 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7000 uint16_t tmp = 0;
7001
7002 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7003
7004 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7005
7006 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7007 goto fail;
7008
7009 switch (vco) {
7010 case 3200000:
7011 div_table = div_3200;
7012 break;
7013 case 4000000:
7014 div_table = div_4000;
7015 break;
7016 case 5333333:
7017 div_table = div_5333;
7018 break;
7019 default:
7020 goto fail;
7021 }
7022
7023 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7024
7025 fail:
7026 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7027 return 200000;
7028}
7029
7030static int g33_get_display_clock_speed(struct drm_device *dev)
7031{
7032 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7033 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7034 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7035 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7036 const uint8_t *div_table;
7037 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7038 uint16_t tmp = 0;
7039
7040 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7041
7042 cdclk_sel = (tmp >> 4) & 0x7;
7043
7044 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7045 goto fail;
7046
7047 switch (vco) {
7048 case 3200000:
7049 div_table = div_3200;
7050 break;
7051 case 4000000:
7052 div_table = div_4000;
7053 break;
7054 case 4800000:
7055 div_table = div_4800;
7056 break;
7057 case 5333333:
7058 div_table = div_5333;
7059 break;
7060 default:
7061 goto fail;
7062 }
7063
7064 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7065
7066 fail:
7067 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7068 return 190476;
7069}
7070
2c07245f 7071static void
a65851af 7072intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 7073{
a65851af
VS		 7074 while (*num > DATA_LINK_M_N_MASK ||
7075 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 7076 *num >>= 1;
7077 *den >>= 1;
7078 }
7079}
7080
a65851af
VS		 7081static void compute_m_n(unsigned int m, unsigned int n,
7082 uint32_t *ret_m, uint32_t *ret_n)
7083{
7084 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7085 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7086 intel_reduce_m_n_ratio(ret_m, ret_n);
7087}
7088
e69d0bc1
DV		 7089void
7090intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7091 int pixel_clock, int link_clock,
7092 struct intel_link_m_n *m_n)
2c07245f 7093{
e69d0bc1 7094 m_n->tu = 64;
a65851af
VS		 7095
7096 compute_m_n(bits_per_pixel * pixel_clock,
7097 link_clock * nlanes * 8,
7098 &m_n->gmch_m, &m_n->gmch_n);
7099
7100 compute_m_n(pixel_clock, link_clock,
7101 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 7102}
7103
a7615030
CW		 7104static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7105{
d330a953
JN		 7106 if (i915.panel_use_ssc >= 0)
7107 return i915.panel_use_ssc != 0;
41aa3448 7108 return dev_priv->vbt.lvds_use_ssc
435793df 7109 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 7110}
7111
a93e255f
ACO		 7112static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7113 int num_connectors)
c65d77d8 7114{
a93e255f 7115 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 7116 struct drm_i915_private *dev_priv = dev->dev_private;
7117 int refclk;
7118
a93e255f
ACO		 7119 WARN_ON(!crtc_state->base.state);
7120
5ab7b0b7 7121 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
9a0ea498 7122 refclk = 100000;
a93e255f 7123 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 7124 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 7125 refclk = dev_priv->vbt.lvds_ssc_freq;
7126 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 7127 } else if (!IS_GEN2(dev)) {
7128 refclk = 96000;
7129 } else {
7130 refclk = 48000;
7131 }
7132
7133 return refclk;
7134}
7135
7429e9d4 7136static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 7137{
7df00d7a 7138 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 7139}
f47709a9 7140
7429e9d4
DV		 7141static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7142{
7143 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 7144}
7145
f47709a9 7146static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 7147 struct intel_crtc_state *crtc_state,
a7516a05
JB		 7148 intel_clock_t *reduced_clock)
7149{
f47709a9 7150 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 7151 u32 fp, fp2 = 0;
7152
7153 if (IS_PINEVIEW(dev)) {
190f68c5 7154 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7155 if (reduced_clock)
7429e9d4 7156 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 7157 } else {
190f68c5 7158 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7159 if (reduced_clock)
7429e9d4 7160 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 7161 }
7162
190f68c5 7163 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 7164
f47709a9 7165 crtc->lowfreq_avail = false;
a93e255f 7166 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 7167 reduced_clock) {
190f68c5 7168 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 7169 crtc->lowfreq_avail = true;
a7516a05 7170 } else {
190f68c5 7171 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 7172 }
7173}
7174
5e69f97f
CML		 7175static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7176 pipe)
89b667f8
JB		 7177{
7178 u32 reg_val;
7179
7180 /*
7181 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7182 * and set it to a reasonable value instead.
7183 */
ab3c759a 7184 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 7185 reg_val &= 0xffffff00;
7186 reg_val |= 0x00000030;
ab3c759a 7187 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7188
ab3c759a 7189 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7190 reg_val &= 0x8cffffff;
7191 reg_val = 0x8c000000;
ab3c759a 7192 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 7193
ab3c759a 7194 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 7195 reg_val &= 0xffffff00;
ab3c759a 7196 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7197
ab3c759a 7198 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7199 reg_val &= 0x00ffffff;
7200 reg_val |= 0xb0000000;
ab3c759a 7201 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 7202}
7203
b551842d
DV		 7204static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7205 struct intel_link_m_n *m_n)
7206{
7207 struct drm_device *dev = crtc->base.dev;
7208 struct drm_i915_private *dev_priv = dev->dev_private;
7209 int pipe = crtc->pipe;
7210
e3b95f1e
DV		 7211 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7212 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7213 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7214 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 7215}
7216
7217static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 7218 struct intel_link_m_n *m_n,
7219 struct intel_link_m_n *m2_n2)
b551842d
DV		 7220{
7221 struct drm_device *dev = crtc->base.dev;
7222 struct drm_i915_private *dev_priv = dev->dev_private;
7223 int pipe = crtc->pipe;
6e3c9717 7224 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 7225
7226 if (INTEL_INFO(dev)->gen >= 5) {
7227 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7228 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7229 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7230 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 7231 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7232 * for gen < 8) and if DRRS is supported (to make sure the
7233 * registers are not unnecessarily accessed).
7234 */
44395bfe 7235 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 7236 crtc->config->has_drrs) {
f769cd24
VK		 7237 I915_WRITE(PIPE_DATA_M2(transcoder),
7238 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7239 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7240 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7241 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7242 }
b551842d 7243 } else {
e3b95f1e
DV		 7244 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7245 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7246 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7247 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 7248 }
7249}
7250
fe3cd48d 7251void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 7252{
fe3cd48d
R		 7253 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7254
7255 if (m_n == M1_N1) {
7256 dp_m_n = &crtc->config->dp_m_n;
7257 dp_m2_n2 = &crtc->config->dp_m2_n2;
7258 } else if (m_n == M2_N2) {
7259
7260 /*
7261 * M2_N2 registers are not supported. Hence m2_n2 divider value
7262 * needs to be programmed into M1_N1.
7263 */
7264 dp_m_n = &crtc->config->dp_m2_n2;
7265 } else {
7266 DRM_ERROR("Unsupported divider value\n");
7267 return;
7268 }
7269
6e3c9717
ACO		 7270 if (crtc->config->has_pch_encoder)
7271 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 7272 else
fe3cd48d 7273 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 7274}
7275
d288f65f 7276static void vlv_update_pll(struct intel_crtc *crtc,
5cec258b 7277 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 7278{
7279 u32 dpll, dpll_md;
7280
7281 /*
7282 * Enable DPIO clock input. We should never disable the reference
7283 * clock for pipe B, since VGA hotplug / manual detection depends
7284 * on it.
7285 */
7286 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
7287 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
7288 /* We should never disable this, set it here for state tracking */
7289 if (crtc->pipe == PIPE_B)
7290 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7291 dpll |= DPLL_VCO_ENABLE;
d288f65f 7292 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 7293
d288f65f 7294 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 7295 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 7296 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 7297}
7298
d288f65f 7299static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7300 const struct intel_crtc_state *pipe_config)
a0c4da24 7301{
f47709a9 7302 struct drm_device *dev = crtc->base.dev;
a0c4da24 7303 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 7304 int pipe = crtc->pipe;
bdd4b6a6 7305 u32 mdiv;
a0c4da24 7306 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 7307 u32 coreclk, reg_val;
a0c4da24 7308
a580516d 7309 mutex_lock(&dev_priv->sb_lock);
09153000 7310
d288f65f
VS		 7311 bestn = pipe_config->dpll.n;
7312 bestm1 = pipe_config->dpll.m1;
7313 bestm2 = pipe_config->dpll.m2;
7314 bestp1 = pipe_config->dpll.p1;
7315 bestp2 = pipe_config->dpll.p2;
a0c4da24 7316
89b667f8
JB		 7317 /* See eDP HDMI DPIO driver vbios notes doc */
7318
7319 /* PLL B needs special handling */
bdd4b6a6 7320 if (pipe == PIPE_B)
5e69f97f 7321 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 7322
7323 /* Set up Tx target for periodic Rcomp update */
ab3c759a 7324 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 7325
7326 /* Disable target IRef on PLL */
ab3c759a 7327 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 7328 reg_val &= 0x00ffffff;
ab3c759a 7329 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 7330
7331 /* Disable fast lock */
ab3c759a 7332 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 7333
7334 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 7335 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7336 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7337 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 7338 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 7339
7340 /*
7341 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7342 * but we don't support that).
7343 * Note: don't use the DAC post divider as it seems unstable.
7344 */
7345 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 7346 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7347
a0c4da24 7348 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 7349 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7350
89b667f8 7351 /* Set HBR and RBR LPF coefficients */
d288f65f 7352 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 7353 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7354 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 7355 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 7356 0x009f0003);
89b667f8 7357 else
ab3c759a 7358 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 7359 0x00d0000f);
7360
681a8504 7361 if (pipe_config->has_dp_encoder) {
89b667f8 7362 /* Use SSC source */
bdd4b6a6 7363 if (pipe == PIPE_A)
ab3c759a 7364 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7365 0x0df40000);
7366 else
ab3c759a 7367 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7368 0x0df70000);
7369 } else { /* HDMI or VGA */
7370 /* Use bend source */
bdd4b6a6 7371 if (pipe == PIPE_A)
ab3c759a 7372 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7373 0x0df70000);
7374 else
ab3c759a 7375 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7376 0x0df40000);
7377 }
a0c4da24 7378
ab3c759a 7379 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 7380 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 7381 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7382 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 7383 coreclk |= 0x01000000;
ab3c759a 7384 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 7385
ab3c759a 7386 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
a580516d 7387 mutex_unlock(&dev_priv->sb_lock);
a0c4da24
JB		 7388}
7389
d288f65f 7390static void chv_update_pll(struct intel_crtc *crtc,
5cec258b 7391 struct intel_crtc_state *pipe_config)
1ae0d137 7392{
d288f65f 7393 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
1ae0d137
VS		 7394 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7395 DPLL_VCO_ENABLE;
7396 if (crtc->pipe != PIPE_A)
d288f65f 7397 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 7398
d288f65f
VS		 7399 pipe_config->dpll_hw_state.dpll_md =
7400 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 7401}
7402
d288f65f 7403static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7404 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 7405{
7406 struct drm_device *dev = crtc->base.dev;
7407 struct drm_i915_private *dev_priv = dev->dev_private;
7408 int pipe = crtc->pipe;
7409 int dpll_reg = DPLL(crtc->pipe);
7410 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 7411 u32 loopfilter, tribuf_calcntr;
9d556c99 7412 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 7413 u32 dpio_val;
9cbe40c1 7414 int vco;
9d556c99 7415
d288f65f
VS		 7416 bestn = pipe_config->dpll.n;
7417 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7418 bestm1 = pipe_config->dpll.m1;
7419 bestm2 = pipe_config->dpll.m2 >> 22;
7420 bestp1 = pipe_config->dpll.p1;
7421 bestp2 = pipe_config->dpll.p2;
9cbe40c1 7422 vco = pipe_config->dpll.vco;
a945ce7e 7423 dpio_val = 0;
9cbe40c1 7424 loopfilter = 0;
9d556c99
CML		 7425
7426 /*
7427 * Enable Refclk and SSC
7428 */
a11b0703 7429 I915_WRITE(dpll_reg,
d288f65f 7430 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703 7431
a580516d 7432 mutex_lock(&dev_priv->sb_lock);
9d556c99 7433
9d556c99
CML		 7434 /* p1 and p2 divider */
7435 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7436 5 << DPIO_CHV_S1_DIV_SHIFT |
7437 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7438 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7439 1 << DPIO_CHV_K_DIV_SHIFT);
7440
7441 /* Feedback post-divider - m2 */
7442 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7443
7444 /* Feedback refclk divider - n and m1 */
7445 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7446 DPIO_CHV_M1_DIV_BY_2 |
7447 1 << DPIO_CHV_N_DIV_SHIFT);
7448
7449 /* M2 fraction division */
a945ce7e
VP		 7450 if (bestm2_frac)
7451 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 7452
7453 /* M2 fraction division enable */
a945ce7e
VP		 7454 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7455 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7456 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7457 if (bestm2_frac)
7458 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7459 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 7460
de3a0fde
VP		 7461 /* Program digital lock detect threshold */
7462 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7463 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7464 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7465 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7466 if (!bestm2_frac)
7467 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7468 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7469
9d556c99 7470 /* Loop filter */
9cbe40c1
VP		 7471 if (vco == 5400000) {
7472 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7473 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7474 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7475 tribuf_calcntr = 0x9;
7476 } else if (vco <= 6200000) {
7477 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7478 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7479 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7480 tribuf_calcntr = 0x9;
7481 } else if (vco <= 6480000) {
7482 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7483 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7484 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7485 tribuf_calcntr = 0x8;
7486 } else {
7487 /* Not supported. Apply the same limits as in the max case */
7488 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7489 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7490 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7491 tribuf_calcntr = 0;
7492 }
9d556c99
CML		 7493 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7494
968040b2 7495 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 7496 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7497 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7498 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7499
9d556c99
CML		 7500 /* AFC Recal */
7501 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7502 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7503 DPIO_AFC_RECAL);
7504
a580516d 7505 mutex_unlock(&dev_priv->sb_lock);
9d556c99
CML		 7506}
7507
d288f65f
VS		 7508/**
7509 * vlv_force_pll_on - forcibly enable just the PLL
7510 * @dev_priv: i915 private structure
7511 * @pipe: pipe PLL to enable
7512 * @dpll: PLL configuration
7513 *
7514 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7515 * in cases where we need the PLL enabled even when @pipe is not going to
7516 * be enabled.
7517 */
7518void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7519 const struct dpll *dpll)
7520{
7521 struct intel_crtc *crtc =
7522 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 7523 struct intel_crtc_state pipe_config = {
a93e255f 7524 .base.crtc = &crtc->base,
d288f65f
VS		 7525 .pixel_multiplier = 1,
7526 .dpll = *dpll,
7527 };
7528
7529 if (IS_CHERRYVIEW(dev)) {
7530 chv_update_pll(crtc, &pipe_config);
7531 chv_prepare_pll(crtc, &pipe_config);
7532 chv_enable_pll(crtc, &pipe_config);
7533 } else {
7534 vlv_update_pll(crtc, &pipe_config);
7535 vlv_prepare_pll(crtc, &pipe_config);
7536 vlv_enable_pll(crtc, &pipe_config);
7537 }
7538}
7539
7540/**
7541 * vlv_force_pll_off - forcibly disable just the PLL
7542 * @dev_priv: i915 private structure
7543 * @pipe: pipe PLL to disable
7544 *
7545 * Disable the PLL for @pipe. To be used in cases where we need
7546 * the PLL enabled even when @pipe is not going to be enabled.
7547 */
7548void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7549{
7550 if (IS_CHERRYVIEW(dev))
7551 chv_disable_pll(to_i915(dev), pipe);
7552 else
7553 vlv_disable_pll(to_i915(dev), pipe);
7554}
7555
f47709a9 7556static void i9xx_update_pll(struct intel_crtc *crtc,
190f68c5 7557 struct intel_crtc_state *crtc_state,
f47709a9 7558 intel_clock_t *reduced_clock,
eb1cbe48
DV		 7559 int num_connectors)
7560{
f47709a9 7561 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7562 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 7563 u32 dpll;
7564 bool is_sdvo;
190f68c5 7565 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7566
190f68c5 7567 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7568
a93e255f
ACO		 7569 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7570 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 7571
7572 dpll = DPLL_VGA_MODE_DIS;
7573
a93e255f 7574 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 7575 dpll |= DPLLB_MODE_LVDS;
7576 else
7577 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 7578
ef1b460d 7579 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 7580 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 7581 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 7582 }
198a037f
DV		 7583
7584 if (is_sdvo)
4a33e48d 7585 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 7586
190f68c5 7587 if (crtc_state->has_dp_encoder)
4a33e48d 7588 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 7589
7590 /* compute bitmask from p1 value */
7591 if (IS_PINEVIEW(dev))
7592 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7593 else {
7594 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7595 if (IS_G4X(dev) && reduced_clock)
7596 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7597 }
7598 switch (clock->p2) {
7599 case 5:
7600 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7601 break;
7602 case 7:
7603 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7604 break;
7605 case 10:
7606 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7607 break;
7608 case 14:
7609 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7610 break;
7611 }
7612 if (INTEL_INFO(dev)->gen >= 4)
7613 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7614
190f68c5 7615 if (crtc_state->sdvo_tv_clock)
eb1cbe48 7616 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 7617 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7618 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7619 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7620 else
7621 dpll |= PLL_REF_INPUT_DREFCLK;
7622
7623 dpll |= DPLL_VCO_ENABLE;
190f68c5 7624 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 7625
eb1cbe48 7626 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 7627 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 7628 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 7629 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 7630 }
7631}
7632
f47709a9 7633static void i8xx_update_pll(struct intel_crtc *crtc,
190f68c5 7634 struct intel_crtc_state *crtc_state,
f47709a9 7635 intel_clock_t *reduced_clock,
eb1cbe48
DV		 7636 int num_connectors)
7637{
f47709a9 7638 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7639 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 7640 u32 dpll;
190f68c5 7641 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7642
190f68c5 7643 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7644
eb1cbe48
DV		 7645 dpll = DPLL_VGA_MODE_DIS;
7646
a93e255f 7647 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 7648 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7649 } else {
7650 if (clock->p1 == 2)
7651 dpll |= PLL_P1_DIVIDE_BY_TWO;
7652 else
7653 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7654 if (clock->p2 == 4)
7655 dpll |= PLL_P2_DIVIDE_BY_4;
7656 }
7657
a93e255f 7658 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 7659 dpll |= DPLL_DVO_2X_MODE;
7660
a93e255f 7661 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7662 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7663 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7664 else
7665 dpll |= PLL_REF_INPUT_DREFCLK;
7666
7667 dpll |= DPLL_VCO_ENABLE;
190f68c5 7668 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 7669}
7670
8a654f3b 7671static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 7672{
7673 struct drm_device *dev = intel_crtc->base.dev;
7674 struct drm_i915_private *dev_priv = dev->dev_private;
7675 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7676 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8a654f3b 7677 struct drm_display_mode *adjusted_mode =
6e3c9717 7678 &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 7679 uint32_t crtc_vtotal, crtc_vblank_end;
7680 int vsyncshift = 0;
4d8a62ea
DV		 7681
7682 /* We need to be careful not to changed the adjusted mode, for otherwise
7683 * the hw state checker will get angry at the mismatch. */
7684 crtc_vtotal = adjusted_mode->crtc_vtotal;
7685 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 7686
609aeaca 7687 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 7688 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 7689 crtc_vtotal -= 1;
7690 crtc_vblank_end -= 1;
609aeaca 7691
409ee761 7692 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 7693 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7694 else
7695 vsyncshift = adjusted_mode->crtc_hsync_start -
7696 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 7697 if (vsyncshift < 0)
7698 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 7699 }
7700
7701 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 7702 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 7703
fe2b8f9d 7704 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 7705 (adjusted_mode->crtc_hdisplay - 1) |
7706 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 7707 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 7708 (adjusted_mode->crtc_hblank_start - 1) |
7709 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 7710 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 7711 (adjusted_mode->crtc_hsync_start - 1) |
7712 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7713
fe2b8f9d 7714 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 7715 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 7716 ((crtc_vtotal - 1) << 16));
fe2b8f9d 7717 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 7718 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 7719 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 7720 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 7721 (adjusted_mode->crtc_vsync_start - 1) |
7722 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7723
b5e508d4
PZ		 7724 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7725 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7726 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7727 * bits. */
7728 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7729 (pipe == PIPE_B || pipe == PIPE_C))
7730 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7731
b0e77b9c
PZ		 7732 /* pipesrc controls the size that is scaled from, which should
7733 * always be the user's requested size.
7734 */
7735 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 7736 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7737 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 7738}
7739
1bd1bd80 7740static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7741 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 7742{
7743 struct drm_device *dev = crtc->base.dev;
7744 struct drm_i915_private *dev_priv = dev->dev_private;
7745 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7746 uint32_t tmp;
7747
7748 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 7749 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7750 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7751 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 7752 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7753 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7754 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 7755 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7756 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7757
7758 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 7759 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7760 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7761 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 7762 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7763 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7764 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 7765 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7766 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7767
7768 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 7769 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7770 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7771 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 7772 }
7773
7774 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 7775 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7776 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7777
2d112de7
ACO		 7778 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7779 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 7780}
7781
f6a83288 7782void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7783 struct intel_crtc_state *pipe_config)
babea61d 7784{
2d112de7
ACO		 7785 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7786 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7787 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7788 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7789
2d112de7
ACO		 7790 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7791 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7792 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7793 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7794
2d112de7 7795 mode->flags = pipe_config->base.adjusted_mode.flags;
babea61d 7796
2d112de7
ACO		 7797 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7798 mode->flags |= pipe_config->base.adjusted_mode.flags;
babea61d
JB		 7799}
7800
84b046f3
DV		 7801static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7802{
7803 struct drm_device *dev = intel_crtc->base.dev;
7804 struct drm_i915_private *dev_priv = dev->dev_private;
7805 uint32_t pipeconf;
7806
9f11a9e4 7807 pipeconf = 0;
84b046f3 7808
b6b5d049
VS		 7809 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7810 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7811 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7812
6e3c9717 7813 if (intel_crtc->config->double_wide)
cf532bb2 7814 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7815
ff9ce46e
DV		 7816 /* only g4x and later have fancy bpc/dither controls */
7817 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 7818 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7819 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7820 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7821 PIPECONF_DITHER_TYPE_SP;
84b046f3 7822
6e3c9717 7823 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 7824 case 18:
7825 pipeconf |= PIPECONF_6BPC;
7826 break;
7827 case 24:
7828 pipeconf |= PIPECONF_8BPC;
7829 break;
7830 case 30:
7831 pipeconf |= PIPECONF_10BPC;
7832 break;
7833 default:
7834 /* Case prevented by intel_choose_pipe_bpp_dither. */
7835 BUG();
84b046f3
DV		 7836 }
7837 }
7838
7839 if (HAS_PIPE_CXSR(dev)) {
7840 if (intel_crtc->lowfreq_avail) {
7841 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7842 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7843 } else {
7844 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 7845 }
7846 }
7847
6e3c9717 7848 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7849 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7850 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 7851 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7852 else
7853 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7854 } else
84b046f3
DV		 7855 pipeconf |= PIPECONF_PROGRESSIVE;
7856
6e3c9717 7857 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 7858 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7859
84b046f3
DV		 7860 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7861 POSTING_READ(PIPECONF(intel_crtc->pipe));
7862}
7863
190f68c5
ACO		 7864static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7865 struct intel_crtc_state *crtc_state)
79e53945 7866{
c7653199 7867 struct drm_device *dev = crtc->base.dev;
79e53945 7868 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 7869 int refclk, num_connectors = 0;
652c393a 7870 intel_clock_t clock, reduced_clock;
a16af721 7871 bool ok, has_reduced_clock = false;
e9fd1c02 7872 bool is_lvds = false, is_dsi = false;
5eddb70b 7873 struct intel_encoder *encoder;
d4906093 7874 const intel_limit_t *limit;
55bb9992 7875 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 7876 struct drm_connector *connector;
55bb9992
ACO		 7877 struct drm_connector_state *connector_state;
7878 int i;
79e53945 7879
dd3cd74a
ACO		 7880 memset(&crtc_state->dpll_hw_state, 0,
7881 sizeof(crtc_state->dpll_hw_state));
7882
da3ced29 7883 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 7884 if (connector_state->crtc != &crtc->base)
7885 continue;
7886
7887 encoder = to_intel_encoder(connector_state->best_encoder);
7888
5eddb70b 7889 switch (encoder->type) {
79e53945
JB		 7890 case INTEL_OUTPUT_LVDS:
7891 is_lvds = true;
7892 break;
e9fd1c02
JN		 7893 case INTEL_OUTPUT_DSI:
7894 is_dsi = true;
7895 break;
6847d71b
PZ		 7896 default:
7897 break;
79e53945 7898 }
43565a06 7899
c751ce4f 7900 num_connectors++;
79e53945
JB		 7901 }
7902
f2335330 7903 if (is_dsi)
5b18e57c 7904 return 0;
f2335330 7905
190f68c5 7906 if (!crtc_state->clock_set) {
a93e255f 7907 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 7908
e9fd1c02
JN		 7909 /*
7910 * Returns a set of divisors for the desired target clock with
7911 * the given refclk, or FALSE. The returned values represent
7912 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7913 * 2) / p1 / p2.
7914 */
a93e255f
ACO		 7915 limit = intel_limit(crtc_state, refclk);
7916 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7917 crtc_state->port_clock,
e9fd1c02 7918 refclk, NULL, &clock);
f2335330 7919 if (!ok) {
e9fd1c02
JN		 7920 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7921 return -EINVAL;
7922 }
79e53945 7923
f2335330
JN		 7924 if (is_lvds && dev_priv->lvds_downclock_avail) {
7925 /*
7926 * Ensure we match the reduced clock's P to the target
7927 * clock. If the clocks don't match, we can't switch
7928 * the display clock by using the FP0/FP1. In such case
7929 * we will disable the LVDS downclock feature.
7930 */
7931 has_reduced_clock =
a93e255f 7932 dev_priv->display.find_dpll(limit, crtc_state,
f2335330
JN		 7933 dev_priv->lvds_downclock,
7934 refclk, &clock,
7935 &reduced_clock);
7936 }
7937 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7938 crtc_state->dpll.n = clock.n;
7939 crtc_state->dpll.m1 = clock.m1;
7940 crtc_state->dpll.m2 = clock.m2;
7941 crtc_state->dpll.p1 = clock.p1;
7942 crtc_state->dpll.p2 = clock.p2;
f47709a9 7943 }
7026d4ac 7944
e9fd1c02 7945 if (IS_GEN2(dev)) {
190f68c5 7946 i8xx_update_pll(crtc, crtc_state,
2a8f64ca
VP		 7947 has_reduced_clock ? &reduced_clock : NULL,
7948 num_connectors);
9d556c99 7949 } else if (IS_CHERRYVIEW(dev)) {
190f68c5 7950 chv_update_pll(crtc, crtc_state);
e9fd1c02 7951 } else if (IS_VALLEYVIEW(dev)) {
190f68c5 7952 vlv_update_pll(crtc, crtc_state);
e9fd1c02 7953 } else {
190f68c5 7954 i9xx_update_pll(crtc, crtc_state,
eb1cbe48 7955 has_reduced_clock ? &reduced_clock : NULL,
eba905b2 7956 num_connectors);
e9fd1c02 7957 }
79e53945 7958
c8f7a0db 7959 return 0;
f564048e
EA		 7960}
7961
2fa2fe9a 7962static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7963 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 7964{
7965 struct drm_device *dev = crtc->base.dev;
7966 struct drm_i915_private *dev_priv = dev->dev_private;
7967 uint32_t tmp;
7968
dc9e7dec
VS		 7969 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7970 return;
7971
2fa2fe9a 7972 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 7973 if (!(tmp & PFIT_ENABLE))
7974 return;
2fa2fe9a 7975
06922821 7976 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 7977 if (INTEL_INFO(dev)->gen < 4) {
7978 if (crtc->pipe != PIPE_B)
7979 return;
2fa2fe9a
DV		 7980 } else {
7981 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7982 return;
7983 }
7984
06922821 7985 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 7986 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7987 if (INTEL_INFO(dev)->gen < 5)
7988 pipe_config->gmch_pfit.lvds_border_bits =
7989 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7990}
7991
acbec814 7992static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7993 struct intel_crtc_state *pipe_config)
acbec814
JB		 7994{
7995 struct drm_device *dev = crtc->base.dev;
7996 struct drm_i915_private *dev_priv = dev->dev_private;
7997 int pipe = pipe_config->cpu_transcoder;
7998 intel_clock_t clock;
7999 u32 mdiv;
662c6ecb 8000 int refclk = 100000;
acbec814 8001
f573de5a
SK		 8002 /* In case of MIPI DPLL will not even be used */
8003 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
8004 return;
8005
a580516d 8006 mutex_lock(&dev_priv->sb_lock);
ab3c759a 8007 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
a580516d 8008 mutex_unlock(&dev_priv->sb_lock);
acbec814
JB		 8009
8010 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8011 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8012 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8013 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8014 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8015
f646628b 8016 vlv_clock(refclk, &clock);
acbec814 8017
f646628b
VS		 8018 /* clock.dot is the fast clock */
8019 pipe_config->port_clock = clock.dot / 5;
acbec814
JB		 8020}
8021
5724dbd1
DL		 8022static void
8023i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8024 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 8025{
8026 struct drm_device *dev = crtc->base.dev;
8027 struct drm_i915_private *dev_priv = dev->dev_private;
8028 u32 val, base, offset;
8029 int pipe = crtc->pipe, plane = crtc->plane;
8030 int fourcc, pixel_format;
6761dd31 8031 unsigned int aligned_height;
b113d5ee 8032 struct drm_framebuffer *fb;
1b842c89 8033 struct intel_framebuffer *intel_fb;
1ad292b5 8034
42a7b088
DL		 8035 val = I915_READ(DSPCNTR(plane));
8036 if (!(val & DISPLAY_PLANE_ENABLE))
8037 return;
8038
d9806c9f 8039 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8040 if (!intel_fb) {
1ad292b5
JB		 8041 DRM_DEBUG_KMS("failed to alloc fb\n");
8042 return;
8043 }
8044
1b842c89
DL		 8045 fb = &intel_fb->base;
8046
18c5247e
DV		 8047 if (INTEL_INFO(dev)->gen >= 4) {
8048 if (val & DISPPLANE_TILED) {
49af449b 8049 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 8050 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8051 }
8052 }
1ad292b5
JB		 8053
8054 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 8055 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 8056 fb->pixel_format = fourcc;
8057 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 8058
8059 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 8060 if (plane_config->tiling)
1ad292b5
JB		 8061 offset = I915_READ(DSPTILEOFF(plane));
8062 else
8063 offset = I915_READ(DSPLINOFF(plane));
8064 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8065 } else {
8066 base = I915_READ(DSPADDR(plane));
8067 }
8068 plane_config->base = base;
8069
8070 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 8071 fb->width = ((val >> 16) & 0xfff) + 1;
8072 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 8073
8074 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 8075 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 8076
b113d5ee 8077 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8078 fb->pixel_format,
8079 fb->modifier[0]);
1ad292b5 8080
f37b5c2b 8081 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 8082
2844a921
DL		 8083 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8084 pipe_name(pipe), plane, fb->width, fb->height,
8085 fb->bits_per_pixel, base, fb->pitches[0],
8086 plane_config->size);
1ad292b5 8087
2d14030b 8088 plane_config->fb = intel_fb;
1ad292b5
JB		 8089}
8090
70b23a98 8091static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 8092 struct intel_crtc_state *pipe_config)
70b23a98
VS		 8093{
8094 struct drm_device *dev = crtc->base.dev;
8095 struct drm_i915_private *dev_priv = dev->dev_private;
8096 int pipe = pipe_config->cpu_transcoder;
8097 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8098 intel_clock_t clock;
8099 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
8100 int refclk = 100000;
8101
a580516d 8102 mutex_lock(&dev_priv->sb_lock);
70b23a98
VS		 8103 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8104 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8105 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8106 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
a580516d 8107 mutex_unlock(&dev_priv->sb_lock);
70b23a98
VS		 8108
8109 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8110 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
8111 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8112 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8113 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8114
8115 chv_clock(refclk, &clock);
8116
8117 /* clock.dot is the fast clock */
8118 pipe_config->port_clock = clock.dot / 5;
8119}
8120
0e8ffe1b 8121static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8122 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8123{
8124 struct drm_device *dev = crtc->base.dev;
8125 struct drm_i915_private *dev_priv = dev->dev_private;
8126 uint32_t tmp;
8127
f458ebbc
DV		 8128 if (!intel_display_power_is_enabled(dev_priv,
8129 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 8130 return false;
8131
e143a21c 8132 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8133 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8134
0e8ffe1b
DV		 8135 tmp = I915_READ(PIPECONF(crtc->pipe));
8136 if (!(tmp & PIPECONF_ENABLE))
8137 return false;
8138
42571aef
VS		 8139 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8140 switch (tmp & PIPECONF_BPC_MASK) {
8141 case PIPECONF_6BPC:
8142 pipe_config->pipe_bpp = 18;
8143 break;
8144 case PIPECONF_8BPC:
8145 pipe_config->pipe_bpp = 24;
8146 break;
8147 case PIPECONF_10BPC:
8148 pipe_config->pipe_bpp = 30;
8149 break;
8150 default:
8151 break;
8152 }
8153 }
8154
b5a9fa09
DV		 8155 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8156 pipe_config->limited_color_range = true;
8157
282740f7
VS		 8158 if (INTEL_INFO(dev)->gen < 4)
8159 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8160
1bd1bd80
DV		 8161 intel_get_pipe_timings(crtc, pipe_config);
8162
2fa2fe9a
DV		 8163 i9xx_get_pfit_config(crtc, pipe_config);
8164
6c49f241
DV		 8165 if (INTEL_INFO(dev)->gen >= 4) {
8166 tmp = I915_READ(DPLL_MD(crtc->pipe));
8167 pipe_config->pixel_multiplier =
8168 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8169 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 8170 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 8171 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8172 tmp = I915_READ(DPLL(crtc->pipe));
8173 pipe_config->pixel_multiplier =
8174 ((tmp & SDVO_MULTIPLIER_MASK)
8175 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8176 } else {
8177 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8178 * port and will be fixed up in the encoder->get_config
8179 * function. */
8180 pipe_config->pixel_multiplier = 1;
8181 }
8bcc2795
DV		 8182 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8183 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 8184 /*
8185 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8186 * on 830. Filter it out here so that we don't
8187 * report errors due to that.
8188 */
8189 if (IS_I830(dev))
8190 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8191
8bcc2795
DV		 8192 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8193 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 8194 } else {
8195 /* Mask out read-only status bits. */
8196 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8197 DPLL_PORTC_READY_MASK |
8198 DPLL_PORTB_READY_MASK);
8bcc2795 8199 }
6c49f241 8200
70b23a98
VS		 8201 if (IS_CHERRYVIEW(dev))
8202 chv_crtc_clock_get(crtc, pipe_config);
8203 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 8204 vlv_crtc_clock_get(crtc, pipe_config);
8205 else
8206 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 8207
0e8ffe1b
DV		 8208 return true;
8209}
8210
dde86e2d 8211static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 8212{
8213 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 8214 struct intel_encoder *encoder;
74cfd7ac 8215 u32 val, final;
13d83a67 8216 bool has_lvds = false;
199e5d79 8217 bool has_cpu_edp = false;
199e5d79 8218 bool has_panel = false;
99eb6a01
KP		 8219 bool has_ck505 = false;
8220 bool can_ssc = false;
13d83a67
JB		 8221
8222 /* We need to take the global config into account */
b2784e15 8223 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 8224 switch (encoder->type) {
8225 case INTEL_OUTPUT_LVDS:
8226 has_panel = true;
8227 has_lvds = true;
8228 break;
8229 case INTEL_OUTPUT_EDP:
8230 has_panel = true;
2de6905f 8231 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 8232 has_cpu_edp = true;
8233 break;
6847d71b
PZ		 8234 default:
8235 break;
13d83a67
JB		 8236 }
8237 }
8238
99eb6a01 8239 if (HAS_PCH_IBX(dev)) {
41aa3448 8240 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 8241 can_ssc = has_ck505;
8242 } else {
8243 has_ck505 = false;
8244 can_ssc = true;
8245 }
8246
2de6905f
ID		 8247 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8248 has_panel, has_lvds, has_ck505);
13d83a67
JB		 8249
8250 /* Ironlake: try to setup display ref clock before DPLL
8251 * enabling. This is only under driver's control after
8252 * PCH B stepping, previous chipset stepping should be
8253 * ignoring this setting.
8254 */
74cfd7ac
CW		 8255 val = I915_READ(PCH_DREF_CONTROL);
8256
8257 /* As we must carefully and slowly disable/enable each source in turn,
8258 * compute the final state we want first and check if we need to
8259 * make any changes at all.
8260 */
8261 final = val;
8262 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8263 if (has_ck505)
8264 final |= DREF_NONSPREAD_CK505_ENABLE;
8265 else
8266 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8267
8268 final &= ~DREF_SSC_SOURCE_MASK;
8269 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8270 final &= ~DREF_SSC1_ENABLE;
8271
8272 if (has_panel) {
8273 final |= DREF_SSC_SOURCE_ENABLE;
8274
8275 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8276 final |= DREF_SSC1_ENABLE;
8277
8278 if (has_cpu_edp) {
8279 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8280 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8281 else
8282 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8283 } else
8284 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8285 } else {
8286 final |= DREF_SSC_SOURCE_DISABLE;
8287 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8288 }
8289
8290 if (final == val)
8291 return;
8292
13d83a67 8293 /* Always enable nonspread source */
74cfd7ac 8294 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 8295
99eb6a01 8296 if (has_ck505)
74cfd7ac 8297 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 8298 else
74cfd7ac 8299 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 8300
199e5d79 8301 if (has_panel) {
74cfd7ac
CW		 8302 val &= ~DREF_SSC_SOURCE_MASK;
8303 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 8304
199e5d79 8305 /* SSC must be turned on before enabling the CPU output */
99eb6a01 8306 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8307 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 8308 val |= DREF_SSC1_ENABLE;
e77166b5 8309 } else
74cfd7ac 8310 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 8311
8312 /* Get SSC going before enabling the outputs */
74cfd7ac 8313 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8314 POSTING_READ(PCH_DREF_CONTROL);
8315 udelay(200);
8316
74cfd7ac 8317 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 8318
8319 /* Enable CPU source on CPU attached eDP */
199e5d79 8320 if (has_cpu_edp) {
99eb6a01 8321 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8322 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 8323 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 8324 } else
74cfd7ac 8325 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 8326 } else
74cfd7ac 8327 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8328
74cfd7ac 8329 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8330 POSTING_READ(PCH_DREF_CONTROL);
8331 udelay(200);
8332 } else {
8333 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8334
74cfd7ac 8335 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 8336
8337 /* Turn off CPU output */
74cfd7ac 8338 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8339
74cfd7ac 8340 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8341 POSTING_READ(PCH_DREF_CONTROL);
8342 udelay(200);
8343
8344 /* Turn off the SSC source */
74cfd7ac
CW		 8345 val &= ~DREF_SSC_SOURCE_MASK;
8346 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 8347
8348 /* Turn off SSC1 */
74cfd7ac 8349 val &= ~DREF_SSC1_ENABLE;
199e5d79 8350
74cfd7ac 8351 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 8352 POSTING_READ(PCH_DREF_CONTROL);
8353 udelay(200);
8354 }
74cfd7ac
CW		 8355
8356 BUG_ON(val != final);
13d83a67
JB		 8357}
8358
f31f2d55 8359static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 8360{
f31f2d55 8361 uint32_t tmp;
dde86e2d 8362
0ff066a9
PZ		 8363 tmp = I915_READ(SOUTH_CHICKEN2);
8364 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8365 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8366
0ff066a9
PZ		 8367 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8368 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8369 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 8370
0ff066a9
PZ		 8371 tmp = I915_READ(SOUTH_CHICKEN2);
8372 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8373 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8374
0ff066a9
PZ		 8375 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8376 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8377 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 8378}
8379
8380/* WaMPhyProgramming:hsw */
8381static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8382{
8383 uint32_t tmp;
dde86e2d
PZ		 8384
8385 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8386 tmp &= ~(0xFF << 24);
8387 tmp |= (0x12 << 24);
8388 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8389
dde86e2d
PZ		 8390 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8391 tmp |= (1 << 11);
8392 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8393
8394 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8395 tmp |= (1 << 11);
8396 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8397
dde86e2d
PZ		 8398 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8399 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8400 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8401
8402 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8403 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8404 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8405
0ff066a9
PZ		 8406 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8407 tmp &= ~(7 << 13);
8408 tmp |= (5 << 13);
8409 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 8410
0ff066a9
PZ		 8411 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8412 tmp &= ~(7 << 13);
8413 tmp |= (5 << 13);
8414 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 8415
8416 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8417 tmp &= ~0xFF;
8418 tmp |= 0x1C;
8419 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8420
8421 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8422 tmp &= ~0xFF;
8423 tmp |= 0x1C;
8424 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8425
8426 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8427 tmp &= ~(0xFF << 16);
8428 tmp |= (0x1C << 16);
8429 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8430
8431 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8432 tmp &= ~(0xFF << 16);
8433 tmp |= (0x1C << 16);
8434 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8435
0ff066a9
PZ		 8436 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8437 tmp |= (1 << 27);
8438 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 8439
0ff066a9
PZ		 8440 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8441 tmp |= (1 << 27);
8442 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 8443
0ff066a9
PZ		 8444 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8445 tmp &= ~(0xF << 28);
8446 tmp |= (4 << 28);
8447 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 8448
0ff066a9
PZ		 8449 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8450 tmp &= ~(0xF << 28);
8451 tmp |= (4 << 28);
8452 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 8453}
8454
2fa86a1f
PZ		 8455/* Implements 3 different sequences from BSpec chapter "Display iCLK
8456 * Programming" based on the parameters passed:
8457 * - Sequence to enable CLKOUT_DP
8458 * - Sequence to enable CLKOUT_DP without spread
8459 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8460 */
8461static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8462 bool with_fdi)
f31f2d55
PZ		 8463{
8464 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 8465 uint32_t reg, tmp;
8466
8467 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8468 with_spread = true;
8469 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8470 with_fdi, "LP PCH doesn't have FDI\n"))
8471 with_fdi = false;
f31f2d55 8472
a580516d 8473 mutex_lock(&dev_priv->sb_lock);
f31f2d55
PZ		 8474
8475 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8476 tmp &= ~SBI_SSCCTL_DISABLE;
8477 tmp |= SBI_SSCCTL_PATHALT;
8478 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8479
8480 udelay(24);
8481
2fa86a1f
PZ		 8482 if (with_spread) {
8483 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8484 tmp &= ~SBI_SSCCTL_PATHALT;
8485 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 8486
2fa86a1f
PZ		 8487 if (with_fdi) {
8488 lpt_reset_fdi_mphy(dev_priv);
8489 lpt_program_fdi_mphy(dev_priv);
8490 }
8491 }
dde86e2d 8492
2fa86a1f
PZ		 8493 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8494 SBI_GEN0 : SBI_DBUFF0;
8495 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8496 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8497 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246 8498
a580516d 8499 mutex_unlock(&dev_priv->sb_lock);
dde86e2d
PZ		 8500}
8501
47701c3b
PZ		 8502/* Sequence to disable CLKOUT_DP */
8503static void lpt_disable_clkout_dp(struct drm_device *dev)
8504{
8505 struct drm_i915_private *dev_priv = dev->dev_private;
8506 uint32_t reg, tmp;
8507
a580516d 8508 mutex_lock(&dev_priv->sb_lock);
47701c3b
PZ		 8509
8510 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8511 SBI_GEN0 : SBI_DBUFF0;
8512 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8513 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8514 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8515
8516 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8517 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8518 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8519 tmp |= SBI_SSCCTL_PATHALT;
8520 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8521 udelay(32);
8522 }
8523 tmp |= SBI_SSCCTL_DISABLE;
8524 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8525 }
8526
a580516d 8527 mutex_unlock(&dev_priv->sb_lock);
47701c3b
PZ		 8528}
8529
bf8fa3d3
PZ		 8530static void lpt_init_pch_refclk(struct drm_device *dev)
8531{
bf8fa3d3
PZ		 8532 struct intel_encoder *encoder;
8533 bool has_vga = false;
8534
b2784e15 8535 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 8536 switch (encoder->type) {
8537 case INTEL_OUTPUT_ANALOG:
8538 has_vga = true;
8539 break;
6847d71b
PZ		 8540 default:
8541 break;
bf8fa3d3
PZ		 8542 }
8543 }
8544
47701c3b
PZ		 8545 if (has_vga)
8546 lpt_enable_clkout_dp(dev, true, true);
8547 else
8548 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 8549}
8550
dde86e2d
PZ		 8551/*
8552 * Initialize reference clocks when the driver loads
8553 */
8554void intel_init_pch_refclk(struct drm_device *dev)
8555{
8556 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8557 ironlake_init_pch_refclk(dev);
8558 else if (HAS_PCH_LPT(dev))
8559 lpt_init_pch_refclk(dev);
8560}
8561
55bb9992 8562static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 8563{
55bb9992 8564 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 8565 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8566 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8567 struct drm_connector *connector;
55bb9992 8568 struct drm_connector_state *connector_state;
d9d444cb 8569 struct intel_encoder *encoder;
55bb9992 8570 int num_connectors = 0, i;
d9d444cb
JB		 8571 bool is_lvds = false;
8572
da3ced29 8573 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8574 if (connector_state->crtc != crtc_state->base.crtc)
8575 continue;
8576
8577 encoder = to_intel_encoder(connector_state->best_encoder);
8578
d9d444cb
JB		 8579 switch (encoder->type) {
8580 case INTEL_OUTPUT_LVDS:
8581 is_lvds = true;
8582 break;
6847d71b
PZ		 8583 default:
8584 break;
d9d444cb
JB		 8585 }
8586 num_connectors++;
8587 }
8588
8589 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 8590 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 8591 dev_priv->vbt.lvds_ssc_freq);
e91e941b 8592 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 8593 }
8594
8595 return 120000;
8596}
8597
6ff93609 8598static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 8599{
c8203565 8600 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 8601 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8602 int pipe = intel_crtc->pipe;
c8203565
PZ		 8603 uint32_t val;
8604
78114071 8605 val = 0;
c8203565 8606
6e3c9717 8607 switch (intel_crtc->config->pipe_bpp) {
c8203565 8608 case 18:
dfd07d72 8609 val |= PIPECONF_6BPC;
c8203565
PZ		 8610 break;
8611 case 24:
dfd07d72 8612 val |= PIPECONF_8BPC;
c8203565
PZ		 8613 break;
8614 case 30:
dfd07d72 8615 val |= PIPECONF_10BPC;
c8203565
PZ		 8616 break;
8617 case 36:
dfd07d72 8618 val |= PIPECONF_12BPC;
c8203565
PZ		 8619 break;
8620 default:
cc769b62
PZ		 8621 /* Case prevented by intel_choose_pipe_bpp_dither. */
8622 BUG();
c8203565
PZ		 8623 }
8624
6e3c9717 8625 if (intel_crtc->config->dither)
c8203565
PZ		 8626 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8627
6e3c9717 8628 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 8629 val |= PIPECONF_INTERLACED_ILK;
8630 else
8631 val |= PIPECONF_PROGRESSIVE;
8632
6e3c9717 8633 if (intel_crtc->config->limited_color_range)
3685a8f3 8634 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 8635
c8203565
PZ		 8636 I915_WRITE(PIPECONF(pipe), val);
8637 POSTING_READ(PIPECONF(pipe));
8638}
8639
86d3efce
VS		 8640/*
8641 * Set up the pipe CSC unit.
8642 *
8643 * Currently only full range RGB to limited range RGB conversion
8644 * is supported, but eventually this should handle various
8645 * RGB<->YCbCr scenarios as well.
8646 */
50f3b016 8647static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 8648{
8649 struct drm_device *dev = crtc->dev;
8650 struct drm_i915_private *dev_priv = dev->dev_private;
8651 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8652 int pipe = intel_crtc->pipe;
8653 uint16_t coeff = 0x7800; /* 1.0 */
8654
8655 /*
8656 * TODO: Check what kind of values actually come out of the pipe
8657 * with these coeff/postoff values and adjust to get the best
8658 * accuracy. Perhaps we even need to take the bpc value into
8659 * consideration.
8660 */
8661
6e3c9717 8662 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8663 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8664
8665 /*
8666 * GY/GU and RY/RU should be the other way around according
8667 * to BSpec, but reality doesn't agree. Just set them up in
8668 * a way that results in the correct picture.
8669 */
8670 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8671 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8672
8673 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8674 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8675
8676 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8677 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8678
8679 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8680 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8681 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8682
8683 if (INTEL_INFO(dev)->gen > 6) {
8684 uint16_t postoff = 0;
8685
6e3c9717 8686 if (intel_crtc->config->limited_color_range)
32cf0cb0 8687 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 8688
8689 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8690 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8691 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8692
8693 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8694 } else {
8695 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8696
6e3c9717 8697 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8698 mode |= CSC_BLACK_SCREEN_OFFSET;
8699
8700 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8701 }
8702}
8703
6ff93609 8704static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8705{
756f85cf
PZ		 8706 struct drm_device *dev = crtc->dev;
8707 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 8708 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8709 enum pipe pipe = intel_crtc->pipe;
6e3c9717 8710 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 8711 uint32_t val;
8712
3eff4faa 8713 val = 0;
ee2b0b38 8714
6e3c9717 8715 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 8716 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8717
6e3c9717 8718 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 8719 val |= PIPECONF_INTERLACED_ILK;
8720 else
8721 val |= PIPECONF_PROGRESSIVE;
8722
702e7a56
PZ		 8723 I915_WRITE(PIPECONF(cpu_transcoder), val);
8724 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 8725
8726 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8727 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 8728
3cdf122c 8729 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 8730 val = 0;
8731
6e3c9717 8732 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 8733 case 18:
8734 val |= PIPEMISC_DITHER_6_BPC;
8735 break;
8736 case 24:
8737 val |= PIPEMISC_DITHER_8_BPC;
8738 break;
8739 case 30:
8740 val |= PIPEMISC_DITHER_10_BPC;
8741 break;
8742 case 36:
8743 val |= PIPEMISC_DITHER_12_BPC;
8744 break;
8745 default:
8746 /* Case prevented by pipe_config_set_bpp. */
8747 BUG();
8748 }
8749
6e3c9717 8750 if (intel_crtc->config->dither)
756f85cf
PZ		 8751 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8752
8753 I915_WRITE(PIPEMISC(pipe), val);
8754 }
ee2b0b38
PZ		 8755}
8756
6591c6e4 8757static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 8758 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 8759 intel_clock_t *clock,
8760 bool *has_reduced_clock,
8761 intel_clock_t *reduced_clock)
8762{
8763 struct drm_device *dev = crtc->dev;
8764 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 8765 int refclk;
d4906093 8766 const intel_limit_t *limit;
a16af721 8767 bool ret, is_lvds = false;
79e53945 8768
a93e255f 8769 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
79e53945 8770
55bb9992 8771 refclk = ironlake_get_refclk(crtc_state);
79e53945 8772
d4906093
ML		 8773 /*
8774 * Returns a set of divisors for the desired target clock with the given
8775 * refclk, or FALSE. The returned values represent the clock equation:
8776 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8777 */
a93e255f
ACO		 8778 limit = intel_limit(crtc_state, refclk);
8779 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 8780 crtc_state->port_clock,
ee9300bb 8781 refclk, NULL, clock);
6591c6e4
PZ		 8782 if (!ret)
8783 return false;
cda4b7d3 8784
ddc9003c 8785 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 8786 /*
8787 * Ensure we match the reduced clock's P to the target clock.
8788 * If the clocks don't match, we can't switch the display clock
8789 * by using the FP0/FP1. In such case we will disable the LVDS
8790 * downclock feature.
8791 */
ee9300bb 8792 *has_reduced_clock =
a93e255f 8793 dev_priv->display.find_dpll(limit, crtc_state,
ee9300bb
DV		 8794 dev_priv->lvds_downclock,
8795 refclk, clock,
8796 reduced_clock);
652c393a 8797 }
61e9653f 8798
6591c6e4
PZ		 8799 return true;
8800}
8801
d4b1931c
PZ		 8802int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8803{
8804 /*
8805 * Account for spread spectrum to avoid
8806 * oversubscribing the link. Max center spread
8807 * is 2.5%; use 5% for safety's sake.
8808 */
8809 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8810 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 8811}
8812
7429e9d4 8813static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8814{
7429e9d4 8815 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 8816}
8817
de13a2e3 8818static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 8819 struct intel_crtc_state *crtc_state,
7429e9d4 8820 u32 *fp,
9a7c7890 8821 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 8822{
de13a2e3 8823 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 8824 struct drm_device *dev = crtc->dev;
8825 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8826 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8827 struct drm_connector *connector;
55bb9992
ACO		 8828 struct drm_connector_state *connector_state;
8829 struct intel_encoder *encoder;
de13a2e3 8830 uint32_t dpll;
55bb9992 8831 int factor, num_connectors = 0, i;
09ede541 8832 bool is_lvds = false, is_sdvo = false;
79e53945 8833
da3ced29 8834 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8835 if (connector_state->crtc != crtc_state->base.crtc)
8836 continue;
8837
8838 encoder = to_intel_encoder(connector_state->best_encoder);
8839
8840 switch (encoder->type) {
79e53945
JB		 8841 case INTEL_OUTPUT_LVDS:
8842 is_lvds = true;
8843 break;
8844 case INTEL_OUTPUT_SDVO:
7d57382e 8845 case INTEL_OUTPUT_HDMI:
79e53945 8846 is_sdvo = true;
79e53945 8847 break;
6847d71b
PZ		 8848 default:
8849 break;
79e53945 8850 }
43565a06 8851
c751ce4f 8852 num_connectors++;
79e53945 8853 }
79e53945 8854
c1858123 8855 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 8856 factor = 21;
8857 if (is_lvds) {
8858 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8859 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8860 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8861 factor = 25;
190f68c5 8862 } else if (crtc_state->sdvo_tv_clock)
8febb297 8863 factor = 20;
c1858123 8864
190f68c5 8865 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 8866 *fp |= FP_CB_TUNE;
2c07245f 8867
9a7c7890
DV		 8868 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8869 *fp2 |= FP_CB_TUNE;
8870
5eddb70b 8871 dpll = 0;
2c07245f 8872
a07d6787
EA		 8873 if (is_lvds)
8874 dpll |= DPLLB_MODE_LVDS;
8875 else
8876 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8877
190f68c5 8878 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8879 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 8880
8881 if (is_sdvo)
4a33e48d 8882 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8883 if (crtc_state->has_dp_encoder)
4a33e48d 8884 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8885
a07d6787 8886 /* compute bitmask from p1 value */
190f68c5 8887 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8888 /* also FPA1 */
190f68c5 8889 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8890
190f68c5 8891 switch (crtc_state->dpll.p2) {
a07d6787
EA		 8892 case 5:
8893 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8894 break;
8895 case 7:
8896 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8897 break;
8898 case 10:
8899 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8900 break;
8901 case 14:
8902 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8903 break;
79e53945
JB		 8904 }
8905
b4c09f3b 8906 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 8907 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 8908 else
8909 dpll |= PLL_REF_INPUT_DREFCLK;
8910
959e16d6 8911 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 8912}
8913
190f68c5
ACO		 8914static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8915 struct intel_crtc_state *crtc_state)
de13a2e3 8916{
c7653199 8917 struct drm_device *dev = crtc->base.dev;
de13a2e3 8918 intel_clock_t clock, reduced_clock;
cbbab5bd 8919 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 8920 bool ok, has_reduced_clock = false;
8b47047b 8921 bool is_lvds = false;
e2b78267 8922 struct intel_shared_dpll *pll;
de13a2e3 8923
dd3cd74a
ACO		 8924 memset(&crtc_state->dpll_hw_state, 0,
8925 sizeof(crtc_state->dpll_hw_state));
8926
409ee761 8927 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 8928
5dc5298b
PZ		 8929 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8930 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 8931
190f68c5 8932 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 8933 &has_reduced_clock, &reduced_clock);
190f68c5 8934 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 8935 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8936 return -EINVAL;
79e53945 8937 }
f47709a9 8938 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 8939 if (!crtc_state->clock_set) {
8940 crtc_state->dpll.n = clock.n;
8941 crtc_state->dpll.m1 = clock.m1;
8942 crtc_state->dpll.m2 = clock.m2;
8943 crtc_state->dpll.p1 = clock.p1;
8944 crtc_state->dpll.p2 = clock.p2;
f47709a9 8945 }
79e53945 8946
5dc5298b 8947 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 8948 if (crtc_state->has_pch_encoder) {
8949 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 8950 if (has_reduced_clock)
7429e9d4 8951 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 8952
190f68c5 8953 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 8954 &fp, &reduced_clock,
8955 has_reduced_clock ? &fp2 : NULL);
8956
190f68c5
ACO		 8957 crtc_state->dpll_hw_state.dpll = dpll;
8958 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 8959 if (has_reduced_clock)
190f68c5 8960 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 8961 else
190f68c5 8962 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 8963
190f68c5 8964 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 8965 if (pll == NULL) {
84f44ce7 8966 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 8967 pipe_name(crtc->pipe));
4b645f14
JB		 8968 return -EINVAL;
8969 }
3fb37703 8970 }
79e53945 8971
ab585dea 8972 if (is_lvds && has_reduced_clock)
c7653199 8973 crtc->lowfreq_avail = true;
bcd644e0 8974 else
c7653199 8975 crtc->lowfreq_avail = false;
e2b78267 8976
c8f7a0db 8977 return 0;
79e53945
JB		 8978}
8979
eb14cb74
VS		 8980static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8981 struct intel_link_m_n *m_n)
8982{
8983 struct drm_device *dev = crtc->base.dev;
8984 struct drm_i915_private *dev_priv = dev->dev_private;
8985 enum pipe pipe = crtc->pipe;
8986
8987 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8988 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8989 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8990 & ~TU_SIZE_MASK;
8991 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8992 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8993 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8994}
8995
8996static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8997 enum transcoder transcoder,
b95af8be
VK		 8998 struct intel_link_m_n *m_n,
8999 struct intel_link_m_n *m2_n2)
72419203
DV		 9000{
9001 struct drm_device *dev = crtc->base.dev;
9002 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 9003 enum pipe pipe = crtc->pipe;
72419203 9004
eb14cb74
VS		 9005 if (INTEL_INFO(dev)->gen >= 5) {
9006 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9007 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9008 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9009 & ~TU_SIZE_MASK;
9010 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9011 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9012 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 9013 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9014 * gen < 8) and if DRRS is supported (to make sure the
9015 * registers are not unnecessarily read).
9016 */
9017 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 9018 crtc->config->has_drrs) {
b95af8be
VK		 9019 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9020 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9021 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9022 & ~TU_SIZE_MASK;
9023 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9024 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9025 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9026 }
eb14cb74
VS		 9027 } else {
9028 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9029 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9030 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9031 & ~TU_SIZE_MASK;
9032 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9033 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9034 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9035 }
9036}
9037
9038void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 9039 struct intel_crtc_state *pipe_config)
eb14cb74 9040{
681a8504 9041 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 9042 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9043 else
9044 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 9045 &pipe_config->dp_m_n,
9046 &pipe_config->dp_m2_n2);
eb14cb74 9047}
72419203 9048
eb14cb74 9049static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 9050 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 9051{
9052 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 9053 &pipe_config->fdi_m_n, NULL);
72419203
DV		 9054}
9055
bd2e244f 9056static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9057 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 9058{
9059 struct drm_device *dev = crtc->base.dev;
9060 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK		 9061 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9062 uint32_t ps_ctrl = 0;
9063 int id = -1;
9064 int i;
bd2e244f 9065
a1b2278e
CK		 9066 /* find scaler attached to this pipe */
9067 for (i = 0; i < crtc->num_scalers; i++) {
9068 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9069 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9070 id = i;
9071 pipe_config->pch_pfit.enabled = true;
9072 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9073 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9074 break;
9075 }
9076 }
bd2e244f 9077
a1b2278e
CK		 9078 scaler_state->scaler_id = id;
9079 if (id >= 0) {
9080 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9081 } else {
9082 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB		 9083 }
9084}
9085
5724dbd1
DL		 9086static void
9087skylake_get_initial_plane_config(struct intel_crtc *crtc,
9088 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 9089{
9090 struct drm_device *dev = crtc->base.dev;
9091 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 9092 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 9093 int pipe = crtc->pipe;
9094 int fourcc, pixel_format;
6761dd31 9095 unsigned int aligned_height;
bc8d7dff 9096 struct drm_framebuffer *fb;
1b842c89 9097 struct intel_framebuffer *intel_fb;
bc8d7dff 9098
d9806c9f 9099 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9100 if (!intel_fb) {
bc8d7dff
DL		 9101 DRM_DEBUG_KMS("failed to alloc fb\n");
9102 return;
9103 }
9104
1b842c89
DL		 9105 fb = &intel_fb->base;
9106
bc8d7dff 9107 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 9108 if (!(val & PLANE_CTL_ENABLE))
9109 goto error;
9110
bc8d7dff
DL		 9111 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9112 fourcc = skl_format_to_fourcc(pixel_format,
9113 val & PLANE_CTL_ORDER_RGBX,
9114 val & PLANE_CTL_ALPHA_MASK);
9115 fb->pixel_format = fourcc;
9116 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9117
40f46283
DL		 9118 tiling = val & PLANE_CTL_TILED_MASK;
9119 switch (tiling) {
9120 case PLANE_CTL_TILED_LINEAR:
9121 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9122 break;
9123 case PLANE_CTL_TILED_X:
9124 plane_config->tiling = I915_TILING_X;
9125 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9126 break;
9127 case PLANE_CTL_TILED_Y:
9128 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9129 break;
9130 case PLANE_CTL_TILED_YF:
9131 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9132 break;
9133 default:
9134 MISSING_CASE(tiling);
9135 goto error;
9136 }
9137
bc8d7dff
DL		 9138 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9139 plane_config->base = base;
9140
9141 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9142
9143 val = I915_READ(PLANE_SIZE(pipe, 0));
9144 fb->height = ((val >> 16) & 0xfff) + 1;
9145 fb->width = ((val >> 0) & 0x1fff) + 1;
9146
9147 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 9148 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9149 fb->pixel_format);
bc8d7dff
DL		 9150 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9151
9152 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9153 fb->pixel_format,
9154 fb->modifier[0]);
bc8d7dff 9155
f37b5c2b 9156 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 9157
9158 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9159 pipe_name(pipe), fb->width, fb->height,
9160 fb->bits_per_pixel, base, fb->pitches[0],
9161 plane_config->size);
9162
2d14030b 9163 plane_config->fb = intel_fb;
bc8d7dff
DL		 9164 return;
9165
9166error:
9167 kfree(fb);
9168}
9169
2fa2fe9a 9170static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9171 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 9172{
9173 struct drm_device *dev = crtc->base.dev;
9174 struct drm_i915_private *dev_priv = dev->dev_private;
9175 uint32_t tmp;
9176
9177 tmp = I915_READ(PF_CTL(crtc->pipe));
9178
9179 if (tmp & PF_ENABLE) {
fd4daa9c 9180 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 9181 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9182 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 9183
9184 /* We currently do not free assignements of panel fitters on
9185 * ivb/hsw (since we don't use the higher upscaling modes which
9186 * differentiates them) so just WARN about this case for now. */
9187 if (IS_GEN7(dev)) {
9188 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9189 PF_PIPE_SEL_IVB(crtc->pipe));
9190 }
2fa2fe9a 9191 }
79e53945
JB		 9192}
9193
5724dbd1
DL		 9194static void
9195ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9196 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 9197{
9198 struct drm_device *dev = crtc->base.dev;
9199 struct drm_i915_private *dev_priv = dev->dev_private;
9200 u32 val, base, offset;
aeee5a49 9201 int pipe = crtc->pipe;
4c6baa59 9202 int fourcc, pixel_format;
6761dd31 9203 unsigned int aligned_height;
b113d5ee 9204 struct drm_framebuffer *fb;
1b842c89 9205 struct intel_framebuffer *intel_fb;
4c6baa59 9206
42a7b088
DL		 9207 val = I915_READ(DSPCNTR(pipe));
9208 if (!(val & DISPLAY_PLANE_ENABLE))
9209 return;
9210
d9806c9f 9211 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9212 if (!intel_fb) {
4c6baa59
JB		 9213 DRM_DEBUG_KMS("failed to alloc fb\n");
9214 return;
9215 }
9216
1b842c89
DL		 9217 fb = &intel_fb->base;
9218
18c5247e
DV		 9219 if (INTEL_INFO(dev)->gen >= 4) {
9220 if (val & DISPPLANE_TILED) {
49af449b 9221 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 9222 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9223 }
9224 }
4c6baa59
JB		 9225
9226 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 9227 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 9228 fb->pixel_format = fourcc;
9229 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 9230
aeee5a49 9231 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 9232 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 9233 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 9234 } else {
49af449b 9235 if (plane_config->tiling)
aeee5a49 9236 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 9237 else
aeee5a49 9238 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 9239 }
9240 plane_config->base = base;
9241
9242 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 9243 fb->width = ((val >> 16) & 0xfff) + 1;
9244 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 9245
9246 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 9247 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 9248
b113d5ee 9249 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9250 fb->pixel_format,
9251 fb->modifier[0]);
4c6baa59 9252
f37b5c2b 9253 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 9254
2844a921
DL		 9255 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9256 pipe_name(pipe), fb->width, fb->height,
9257 fb->bits_per_pixel, base, fb->pitches[0],
9258 plane_config->size);
b113d5ee 9259
2d14030b 9260 plane_config->fb = intel_fb;
4c6baa59
JB		 9261}
9262
0e8ffe1b 9263static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9264 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9265{
9266 struct drm_device *dev = crtc->base.dev;
9267 struct drm_i915_private *dev_priv = dev->dev_private;
9268 uint32_t tmp;
9269
f458ebbc
DV		 9270 if (!intel_display_power_is_enabled(dev_priv,
9271 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 9272 return false;
9273
e143a21c 9274 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 9275 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 9276
0e8ffe1b
DV		 9277 tmp = I915_READ(PIPECONF(crtc->pipe));
9278 if (!(tmp & PIPECONF_ENABLE))
9279 return false;
9280
42571aef
VS		 9281 switch (tmp & PIPECONF_BPC_MASK) {
9282 case PIPECONF_6BPC:
9283 pipe_config->pipe_bpp = 18;
9284 break;
9285 case PIPECONF_8BPC:
9286 pipe_config->pipe_bpp = 24;
9287 break;
9288 case PIPECONF_10BPC:
9289 pipe_config->pipe_bpp = 30;
9290 break;
9291 case PIPECONF_12BPC:
9292 pipe_config->pipe_bpp = 36;
9293 break;
9294 default:
9295 break;
9296 }
9297
b5a9fa09
DV		 9298 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9299 pipe_config->limited_color_range = true;
9300
ab9412ba 9301 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 9302 struct intel_shared_dpll *pll;
9303
88adfff1
DV		 9304 pipe_config->has_pch_encoder = true;
9305
627eb5a3
DV		 9306 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9307 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9308 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 9309
9310 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 9311
c0d43d62 9312 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 9313 pipe_config->shared_dpll =
9314 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 9315 } else {
9316 tmp = I915_READ(PCH_DPLL_SEL);
9317 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9318 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9319 else
9320 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9321 }
66e985c0
DV		 9322
9323 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9324
9325 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9326 &pipe_config->dpll_hw_state));
c93f54cf
DV		 9327
9328 tmp = pipe_config->dpll_hw_state.dpll;
9329 pipe_config->pixel_multiplier =
9330 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9331 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 9332
9333 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 9334 } else {
9335 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 9336 }
9337
1bd1bd80
DV		 9338 intel_get_pipe_timings(crtc, pipe_config);
9339
2fa2fe9a
DV		 9340 ironlake_get_pfit_config(crtc, pipe_config);
9341
0e8ffe1b
DV		 9342 return true;
9343}
9344
be256dc7
PZ		 9345static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9346{
9347 struct drm_device *dev = dev_priv->dev;
be256dc7 9348 struct intel_crtc *crtc;
be256dc7 9349
d3fcc808 9350 for_each_intel_crtc(dev, crtc)
e2c719b7 9351 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 9352 pipe_name(crtc->pipe));
9353
e2c719b7
RC		 9354 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9355 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9356 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9357 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9358 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9359 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 9360 "CPU PWM1 enabled\n");
c5107b87 9361 if (IS_HASWELL(dev))
e2c719b7 9362 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 9363 "CPU PWM2 enabled\n");
e2c719b7 9364 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 9365 "PCH PWM1 enabled\n");
e2c719b7 9366 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 9367 "Utility pin enabled\n");
e2c719b7 9368 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 9369
9926ada1
PZ		 9370 /*
9371 * In theory we can still leave IRQs enabled, as long as only the HPD
9372 * interrupts remain enabled. We used to check for that, but since it's
9373 * gen-specific and since we only disable LCPLL after we fully disable
9374 * the interrupts, the check below should be enough.
9375 */
e2c719b7 9376 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 9377}
9378
9ccd5aeb
PZ		 9379static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9380{
9381 struct drm_device *dev = dev_priv->dev;
9382
9383 if (IS_HASWELL(dev))
9384 return I915_READ(D_COMP_HSW);
9385 else
9386 return I915_READ(D_COMP_BDW);
9387}
9388
3c4c9b81
PZ		 9389static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9390{
9391 struct drm_device *dev = dev_priv->dev;
9392
9393 if (IS_HASWELL(dev)) {
9394 mutex_lock(&dev_priv->rps.hw_lock);
9395 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9396 val))
f475dadf 9397 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 9398 mutex_unlock(&dev_priv->rps.hw_lock);
9399 } else {
9ccd5aeb
PZ		 9400 I915_WRITE(D_COMP_BDW, val);
9401 POSTING_READ(D_COMP_BDW);
3c4c9b81 9402 }
be256dc7
PZ		 9403}
9404
9405/*
9406 * This function implements pieces of two sequences from BSpec:
9407 * - Sequence for display software to disable LCPLL
9408 * - Sequence for display software to allow package C8+
9409 * The steps implemented here are just the steps that actually touch the LCPLL
9410 * register. Callers should take care of disabling all the display engine
9411 * functions, doing the mode unset, fixing interrupts, etc.
9412 */
6ff58d53
PZ		 9413static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9414 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 9415{
9416 uint32_t val;
9417
9418 assert_can_disable_lcpll(dev_priv);
9419
9420 val = I915_READ(LCPLL_CTL);
9421
9422 if (switch_to_fclk) {
9423 val |= LCPLL_CD_SOURCE_FCLK;
9424 I915_WRITE(LCPLL_CTL, val);
9425
9426 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9427 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9428 DRM_ERROR("Switching to FCLK failed\n");
9429
9430 val = I915_READ(LCPLL_CTL);
9431 }
9432
9433 val |= LCPLL_PLL_DISABLE;
9434 I915_WRITE(LCPLL_CTL, val);
9435 POSTING_READ(LCPLL_CTL);
9436
9437 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9438 DRM_ERROR("LCPLL still locked\n");
9439
9ccd5aeb 9440 val = hsw_read_dcomp(dev_priv);
be256dc7 9441 val |= D_COMP_COMP_DISABLE;
3c4c9b81 9442 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9443 ndelay(100);
9444
9ccd5aeb
PZ		 9445 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9446 1))
be256dc7
PZ		 9447 DRM_ERROR("D_COMP RCOMP still in progress\n");
9448
9449 if (allow_power_down) {
9450 val = I915_READ(LCPLL_CTL);
9451 val |= LCPLL_POWER_DOWN_ALLOW;
9452 I915_WRITE(LCPLL_CTL, val);
9453 POSTING_READ(LCPLL_CTL);
9454 }
9455}
9456
9457/*
9458 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9459 * source.
9460 */
6ff58d53 9461static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 9462{
9463 uint32_t val;
9464
9465 val = I915_READ(LCPLL_CTL);
9466
9467 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9468 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9469 return;
9470
a8a8bd54
PZ		 9471 /*
9472 * Make sure we're not on PC8 state before disabling PC8, otherwise
9473 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 9474 */
59bad947 9475 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 9476
be256dc7
PZ		 9477 if (val & LCPLL_POWER_DOWN_ALLOW) {
9478 val &= ~LCPLL_POWER_DOWN_ALLOW;
9479 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 9480 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 9481 }
9482
9ccd5aeb 9483 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 9484 val |= D_COMP_COMP_FORCE;
9485 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 9486 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9487
9488 val = I915_READ(LCPLL_CTL);
9489 val &= ~LCPLL_PLL_DISABLE;
9490 I915_WRITE(LCPLL_CTL, val);
9491
9492 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9493 DRM_ERROR("LCPLL not locked yet\n");
9494
9495 if (val & LCPLL_CD_SOURCE_FCLK) {
9496 val = I915_READ(LCPLL_CTL);
9497 val &= ~LCPLL_CD_SOURCE_FCLK;
9498 I915_WRITE(LCPLL_CTL, val);
9499
9500 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9501 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9502 DRM_ERROR("Switching back to LCPLL failed\n");
9503 }
215733fa 9504
59bad947 9505 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b6283055 9506 intel_update_cdclk(dev_priv->dev);
be256dc7
PZ		 9507}
9508
765dab67
PZ		 9509/*
9510 * Package states C8 and deeper are really deep PC states that can only be
9511 * reached when all the devices on the system allow it, so even if the graphics
9512 * device allows PC8+, it doesn't mean the system will actually get to these
9513 * states. Our driver only allows PC8+ when going into runtime PM.
9514 *
9515 * The requirements for PC8+ are that all the outputs are disabled, the power
9516 * well is disabled and most interrupts are disabled, and these are also
9517 * requirements for runtime PM. When these conditions are met, we manually do
9518 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9519 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9520 * hang the machine.
9521 *
9522 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9523 * the state of some registers, so when we come back from PC8+ we need to
9524 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9525 * need to take care of the registers kept by RC6. Notice that this happens even
9526 * if we don't put the device in PCI D3 state (which is what currently happens
9527 * because of the runtime PM support).
9528 *
9529 * For more, read "Display Sequences for Package C8" on the hardware
9530 * documentation.
9531 */
a14cb6fc 9532void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 9533{
c67a470b
PZ		 9534 struct drm_device *dev = dev_priv->dev;
9535 uint32_t val;
9536
c67a470b
PZ		 9537 DRM_DEBUG_KMS("Enabling package C8+\n");
9538
c67a470b
PZ		 9539 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9540 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9541 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9542 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9543 }
9544
9545 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 9546 hsw_disable_lcpll(dev_priv, true, true);
9547}
9548
a14cb6fc 9549void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 9550{
9551 struct drm_device *dev = dev_priv->dev;
9552 uint32_t val;
9553
c67a470b
PZ		 9554 DRM_DEBUG_KMS("Disabling package C8+\n");
9555
9556 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 9557 lpt_init_pch_refclk(dev);
9558
9559 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9560 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9561 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9562 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9563 }
9564
9565 intel_prepare_ddi(dev);
c67a470b
PZ		 9566}
9567
a821fc46 9568static void broxton_modeset_global_resources(struct drm_atomic_state *old_state)
f8437dd1 9569{
a821fc46 9570 struct drm_device *dev = old_state->dev;
f8437dd1 9571 struct drm_i915_private *dev_priv = dev->dev_private;
a821fc46 9572 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
f8437dd1
VK		 9573 int req_cdclk;
9574
9575 /* see the comment in valleyview_modeset_global_resources */
9576 if (WARN_ON(max_pixclk < 0))
9577 return;
9578
9579 req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
9580
9581 if (req_cdclk != dev_priv->cdclk_freq)
9582 broxton_set_cdclk(dev, req_cdclk);
9583}
9584
190f68c5
ACO		 9585static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9586 struct intel_crtc_state *crtc_state)
09b4ddf9 9587{
190f68c5 9588 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 9589 return -EINVAL;
716c2e55 9590
c7653199 9591 crtc->lowfreq_avail = false;
644cef34 9592
c8f7a0db 9593 return 0;
79e53945
JB		 9594}
9595
3760b59c
S		 9596static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9597 enum port port,
9598 struct intel_crtc_state *pipe_config)
9599{
9600 switch (port) {
9601 case PORT_A:
9602 pipe_config->ddi_pll_sel = SKL_DPLL0;
9603 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9604 break;
9605 case PORT_B:
9606 pipe_config->ddi_pll_sel = SKL_DPLL1;
9607 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9608 break;
9609 case PORT_C:
9610 pipe_config->ddi_pll_sel = SKL_DPLL2;
9611 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9612 break;
9613 default:
9614 DRM_ERROR("Incorrect port type\n");
9615 }
9616}
9617
96b7dfb7
S		 9618static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9619 enum port port,
5cec258b 9620 struct intel_crtc_state *pipe_config)
96b7dfb7 9621{
3148ade7 9622 u32 temp, dpll_ctl1;
96b7dfb7
S		 9623
9624 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9625 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9626
9627 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 9628 case SKL_DPLL0:
9629 /*
9630 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9631 * of the shared DPLL framework and thus needs to be read out
9632 * separately
9633 */
9634 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9635 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9636 break;
96b7dfb7
S		 9637 case SKL_DPLL1:
9638 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9639 break;
9640 case SKL_DPLL2:
9641 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9642 break;
9643 case SKL_DPLL3:
9644 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9645 break;
96b7dfb7
S		 9646 }
9647}
9648
7d2c8175
DL		 9649static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9650 enum port port,
5cec258b 9651 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 9652{
9653 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9654
9655 switch (pipe_config->ddi_pll_sel) {
9656 case PORT_CLK_SEL_WRPLL1:
9657 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9658 break;
9659 case PORT_CLK_SEL_WRPLL2:
9660 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9661 break;
9662 }
9663}
9664
26804afd 9665static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 9666 struct intel_crtc_state *pipe_config)
26804afd
DV		 9667{
9668 struct drm_device *dev = crtc->base.dev;
9669 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 9670 struct intel_shared_dpll *pll;
26804afd
DV		 9671 enum port port;
9672 uint32_t tmp;
9673
9674 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9675
9676 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9677
96b7dfb7
S		 9678 if (IS_SKYLAKE(dev))
9679 skylake_get_ddi_pll(dev_priv, port, pipe_config);
3760b59c
S		 9680 else if (IS_BROXTON(dev))
9681 bxt_get_ddi_pll(dev_priv, port, pipe_config);
96b7dfb7
S		 9682 else
9683 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 9684
d452c5b6
DV		 9685 if (pipe_config->shared_dpll >= 0) {
9686 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9687
9688 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9689 &pipe_config->dpll_hw_state));
9690 }
9691
26804afd
DV		 9692 /*
9693 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9694 * DDI E. So just check whether this pipe is wired to DDI E and whether
9695 * the PCH transcoder is on.
9696 */
ca370455
DL		 9697 if (INTEL_INFO(dev)->gen < 9 &&
9698 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 9699 pipe_config->has_pch_encoder = true;
9700
9701 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9702 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9703 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9704
9705 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9706 }
9707}
9708
0e8ffe1b 9709static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9710 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9711{
9712 struct drm_device *dev = crtc->base.dev;
9713 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 9714 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 9715 uint32_t tmp;
9716
f458ebbc 9717 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 9718 POWER_DOMAIN_PIPE(crtc->pipe)))
9719 return false;
9720
e143a21c 9721 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 9722 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9723
eccb140b
DV		 9724 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9725 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9726 enum pipe trans_edp_pipe;
9727 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9728 default:
9729 WARN(1, "unknown pipe linked to edp transcoder\n");
9730 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9731 case TRANS_DDI_EDP_INPUT_A_ON:
9732 trans_edp_pipe = PIPE_A;
9733 break;
9734 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9735 trans_edp_pipe = PIPE_B;
9736 break;
9737 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9738 trans_edp_pipe = PIPE_C;
9739 break;
9740 }
9741
9742 if (trans_edp_pipe == crtc->pipe)
9743 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9744 }
9745
f458ebbc 9746 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 9747 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 9748 return false;
9749
eccb140b 9750 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 9751 if (!(tmp & PIPECONF_ENABLE))
9752 return false;
9753
26804afd 9754 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 9755
1bd1bd80
DV		 9756 intel_get_pipe_timings(crtc, pipe_config);
9757
a1b2278e
CK		 9758 if (INTEL_INFO(dev)->gen >= 9) {
9759 skl_init_scalers(dev, crtc, pipe_config);
9760 }
9761
2fa2fe9a 9762 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
af99ceda
CK		 9763
9764 if (INTEL_INFO(dev)->gen >= 9) {
9765 pipe_config->scaler_state.scaler_id = -1;
9766 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9767 }
9768
bd2e244f 9769 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
ff6d9f55 9770 if (INTEL_INFO(dev)->gen == 9)
bd2e244f 9771 skylake_get_pfit_config(crtc, pipe_config);
ff6d9f55 9772 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 9773 ironlake_get_pfit_config(crtc, pipe_config);
ff6d9f55
JB		 9774 else
9775 MISSING_CASE(INTEL_INFO(dev)->gen);
bd2e244f 9776 }
88adfff1 9777
e59150dc
JB		 9778 if (IS_HASWELL(dev))
9779 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9780 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 9781
ebb69c95
CT		 9782 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9783 pipe_config->pixel_multiplier =
9784 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9785 } else {
9786 pipe_config->pixel_multiplier = 1;
9787 }
6c49f241 9788
0e8ffe1b
DV		 9789 return true;
9790}
9791
560b85bb
CW		 9792static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9793{
9794 struct drm_device *dev = crtc->dev;
9795 struct drm_i915_private *dev_priv = dev->dev_private;
9796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 9797 uint32_t cntl = 0, size = 0;
560b85bb 9798
dc41c154 9799 if (base) {
3dd512fb
MR		 9800 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9801 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 9802 unsigned int stride = roundup_pow_of_two(width) * 4;
9803
9804 switch (stride) {
9805 default:
9806 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9807 width, stride);
9808 stride = 256;
9809 /* fallthrough */
9810 case 256:
9811 case 512:
9812 case 1024:
9813 case 2048:
9814 break;
4b0e333e
CW		 9815 }
9816
dc41c154
VS		 9817 cntl |= CURSOR_ENABLE |
9818 CURSOR_GAMMA_ENABLE |
9819 CURSOR_FORMAT_ARGB |
9820 CURSOR_STRIDE(stride);
9821
9822 size = (height << 12) | width;
4b0e333e 9823 }
560b85bb 9824
dc41c154
VS		 9825 if (intel_crtc->cursor_cntl != 0 &&
9826 (intel_crtc->cursor_base != base ||
9827 intel_crtc->cursor_size != size ||
9828 intel_crtc->cursor_cntl != cntl)) {
9829 /* On these chipsets we can only modify the base/size/stride
9830 * whilst the cursor is disabled.
9831 */
9832 I915_WRITE(_CURACNTR, 0);
4b0e333e 9833 POSTING_READ(_CURACNTR);
dc41c154 9834 intel_crtc->cursor_cntl = 0;
4b0e333e 9835 }
560b85bb 9836
99d1f387 9837 if (intel_crtc->cursor_base != base) {
9db4a9c7 9838 I915_WRITE(_CURABASE, base);
99d1f387
VS		 9839 intel_crtc->cursor_base = base;
9840 }
4726e0b0 9841
dc41c154
VS		 9842 if (intel_crtc->cursor_size != size) {
9843 I915_WRITE(CURSIZE, size);
9844 intel_crtc->cursor_size = size;
4b0e333e 9845 }
560b85bb 9846
4b0e333e 9847 if (intel_crtc->cursor_cntl != cntl) {
4b0e333e
CW		 9848 I915_WRITE(_CURACNTR, cntl);
9849 POSTING_READ(_CURACNTR);
4b0e333e 9850 intel_crtc->cursor_cntl = cntl;
560b85bb 9851 }
560b85bb
CW		 9852}
9853
560b85bb 9854static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 9855{
9856 struct drm_device *dev = crtc->dev;
9857 struct drm_i915_private *dev_priv = dev->dev_private;
9858 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9859 int pipe = intel_crtc->pipe;
4b0e333e
CW		 9860 uint32_t cntl;
9861
9862 cntl = 0;
9863 if (base) {
9864 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 9865 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 9866 case 64:
9867 cntl |= CURSOR_MODE_64_ARGB_AX;
9868 break;
9869 case 128:
9870 cntl |= CURSOR_MODE_128_ARGB_AX;
9871 break;
9872 case 256:
9873 cntl |= CURSOR_MODE_256_ARGB_AX;
9874 break;
9875 default:
3dd512fb 9876 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 9877 return;
65a21cd6 9878 }
4b0e333e 9879 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS		 9880
9881 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9882 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 9883 }
65a21cd6 9884
8e7d688b 9885 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 9886 cntl |= CURSOR_ROTATE_180;
9887
4b0e333e
CW		 9888 if (intel_crtc->cursor_cntl != cntl) {
9889 I915_WRITE(CURCNTR(pipe), cntl);
9890 POSTING_READ(CURCNTR(pipe));
9891 intel_crtc->cursor_cntl = cntl;
65a21cd6 9892 }
4b0e333e 9893
65a21cd6 9894 /* and commit changes on next vblank */
5efb3e28
VS		 9895 I915_WRITE(CURBASE(pipe), base);
9896 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 9897
9898 intel_crtc->cursor_base = base;
65a21cd6
JB		 9899}
9900
cda4b7d3 9901/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 9902static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9903 bool on)
cda4b7d3
CW		 9904{
9905 struct drm_device *dev = crtc->dev;
9906 struct drm_i915_private *dev_priv = dev->dev_private;
9907 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9908 int pipe = intel_crtc->pipe;
3d7d6510
MR		 9909 int x = crtc->cursor_x;
9910 int y = crtc->cursor_y;
d6e4db15 9911 u32 base = 0, pos = 0;
cda4b7d3 9912
d6e4db15 9913 if (on)
cda4b7d3 9914 base = intel_crtc->cursor_addr;
cda4b7d3 9915
6e3c9717 9916 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 9917 base = 0;
9918
6e3c9717 9919 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 9920 base = 0;
9921
9922 if (x < 0) {
3dd512fb 9923 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
cda4b7d3
CW		 9924 base = 0;
9925
9926 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9927 x = -x;
9928 }
9929 pos |= x << CURSOR_X_SHIFT;
9930
9931 if (y < 0) {
3dd512fb 9932 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
cda4b7d3
CW		 9933 base = 0;
9934
9935 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9936 y = -y;
9937 }
9938 pos |= y << CURSOR_Y_SHIFT;
9939
4b0e333e 9940 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 9941 return;
9942
5efb3e28
VS		 9943 I915_WRITE(CURPOS(pipe), pos);
9944
4398ad45
VS		 9945 /* ILK+ do this automagically */
9946 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 9947 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
3dd512fb
MR		 9948 base += (intel_crtc->base.cursor->state->crtc_h *
9949 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
4398ad45
VS		 9950 }
9951
8ac54669 9952 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 9953 i845_update_cursor(crtc, base);
9954 else
9955 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 9956}
9957
dc41c154
VS		 9958static bool cursor_size_ok(struct drm_device *dev,
9959 uint32_t width, uint32_t height)
9960{
9961 if (width == 0 || height == 0)
9962 return false;
9963
9964 /*
9965 * 845g/865g are special in that they are only limited by
9966 * the width of their cursors, the height is arbitrary up to
9967 * the precision of the register. Everything else requires
9968 * square cursors, limited to a few power-of-two sizes.
9969 */
9970 if (IS_845G(dev) || IS_I865G(dev)) {
9971 if ((width & 63) != 0)
9972 return false;
9973
9974 if (width > (IS_845G(dev) ? 64 : 512))
9975 return false;
9976
9977 if (height > 1023)
9978 return false;
9979 } else {
9980 switch (width | height) {
9981 case 256:
9982 case 128:
9983 if (IS_GEN2(dev))
9984 return false;
9985 case 64:
9986 break;
9987 default:
9988 return false;
9989 }
9990 }
9991
9992 return true;
9993}
9994
79e53945 9995static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 9996 u16 *blue, uint32_t start, uint32_t size)
79e53945 9997{
7203425a 9998 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 9999 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 10000
7203425a 10001 for (i = start; i < end; i++) {
79e53945
JB		 10002 intel_crtc->lut_r[i] = red[i] >> 8;
10003 intel_crtc->lut_g[i] = green[i] >> 8;
10004 intel_crtc->lut_b[i] = blue[i] >> 8;
10005 }
10006
10007 intel_crtc_load_lut(crtc);
10008}
10009
79e53945
JB		 10010/* VESA 640x480x72Hz mode to set on the pipe */
10011static struct drm_display_mode load_detect_mode = {
10012 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10013 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10014};
10015
a8bb6818
DV		 10016struct drm_framebuffer *
10017__intel_framebuffer_create(struct drm_device *dev,
10018 struct drm_mode_fb_cmd2 *mode_cmd,
10019 struct drm_i915_gem_object *obj)
d2dff872
CW		 10020{
10021 struct intel_framebuffer *intel_fb;
10022 int ret;
10023
10024 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10025 if (!intel_fb) {
6ccb81f2 10026 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 10027 return ERR_PTR(-ENOMEM);
10028 }
10029
10030 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 10031 if (ret)
10032 goto err;
d2dff872
CW		 10033
10034 return &intel_fb->base;
dd4916c5 10035err:
6ccb81f2 10036 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 10037 kfree(intel_fb);
10038
10039 return ERR_PTR(ret);
d2dff872
CW		 10040}
10041
b5ea642a 10042static struct drm_framebuffer *
a8bb6818
DV		 10043intel_framebuffer_create(struct drm_device *dev,
10044 struct drm_mode_fb_cmd2 *mode_cmd,
10045 struct drm_i915_gem_object *obj)
10046{
10047 struct drm_framebuffer *fb;
10048 int ret;
10049
10050 ret = i915_mutex_lock_interruptible(dev);
10051 if (ret)
10052 return ERR_PTR(ret);
10053 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10054 mutex_unlock(&dev->struct_mutex);
10055
10056 return fb;
10057}
10058
d2dff872
CW		 10059static u32
10060intel_framebuffer_pitch_for_width(int width, int bpp)
10061{
10062 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10063 return ALIGN(pitch, 64);
10064}
10065
10066static u32
10067intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10068{
10069 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 10070 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 10071}
10072
10073static struct drm_framebuffer *
10074intel_framebuffer_create_for_mode(struct drm_device *dev,
10075 struct drm_display_mode *mode,
10076 int depth, int bpp)
10077{
10078 struct drm_i915_gem_object *obj;
0fed39bd 10079 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 10080
10081 obj = i915_gem_alloc_object(dev,
10082 intel_framebuffer_size_for_mode(mode, bpp));
10083 if (obj == NULL)
10084 return ERR_PTR(-ENOMEM);
10085
10086 mode_cmd.width = mode->hdisplay;
10087 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 10088 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10089 bpp);
5ca0c34a 10090 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 10091
10092 return intel_framebuffer_create(dev, &mode_cmd, obj);
10093}
10094
10095static struct drm_framebuffer *
10096mode_fits_in_fbdev(struct drm_device *dev,
10097 struct drm_display_mode *mode)
10098{
4520f53a 10099#ifdef CONFIG_DRM_I915_FBDEV
d2dff872
CW		 10100 struct drm_i915_private *dev_priv = dev->dev_private;
10101 struct drm_i915_gem_object *obj;
10102 struct drm_framebuffer *fb;
10103
4c0e5528 10104 if (!dev_priv->fbdev)
d2dff872
CW		 10105 return NULL;
10106
4c0e5528 10107 if (!dev_priv->fbdev->fb)
d2dff872
CW		 10108 return NULL;
10109
4c0e5528
DV		 10110 obj = dev_priv->fbdev->fb->obj;
10111 BUG_ON(!obj);
10112
8bcd4553 10113 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 10114 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10115 fb->bits_per_pixel))
d2dff872
CW		 10116 return NULL;
10117
01f2c773 10118 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 10119 return NULL;
10120
10121 return fb;
4520f53a
DV		 10122#else
10123 return NULL;
10124#endif
d2dff872
CW		 10125}
10126
d3a40d1b
ACO		 10127static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10128 struct drm_crtc *crtc,
10129 struct drm_display_mode *mode,
10130 struct drm_framebuffer *fb,
10131 int x, int y)
10132{
10133 struct drm_plane_state *plane_state;
10134 int hdisplay, vdisplay;
10135 int ret;
10136
10137 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10138 if (IS_ERR(plane_state))
10139 return PTR_ERR(plane_state);
10140
10141 if (mode)
10142 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10143 else
10144 hdisplay = vdisplay = 0;
10145
10146 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10147 if (ret)
10148 return ret;
10149 drm_atomic_set_fb_for_plane(plane_state, fb);
10150 plane_state->crtc_x = 0;
10151 plane_state->crtc_y = 0;
10152 plane_state->crtc_w = hdisplay;
10153 plane_state->crtc_h = vdisplay;
10154 plane_state->src_x = x << 16;
10155 plane_state->src_y = y << 16;
10156 plane_state->src_w = hdisplay << 16;
10157 plane_state->src_h = vdisplay << 16;
10158
10159 return 0;
10160}
10161
d2434ab7 10162bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 10163 struct drm_display_mode *mode,
51fd371b
RC		 10164 struct intel_load_detect_pipe *old,
10165 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 10166{
10167 struct intel_crtc *intel_crtc;
d2434ab7
DV		 10168 struct intel_encoder *intel_encoder =
10169 intel_attached_encoder(connector);
79e53945 10170 struct drm_crtc *possible_crtc;
4ef69c7a 10171 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 10172 struct drm_crtc *crtc = NULL;
10173 struct drm_device *dev = encoder->dev;
94352cf9 10174 struct drm_framebuffer *fb;
51fd371b 10175 struct drm_mode_config *config = &dev->mode_config;
83a57153 10176 struct drm_atomic_state *state = NULL;
944b0c76 10177 struct drm_connector_state *connector_state;
4be07317 10178 struct intel_crtc_state *crtc_state;
51fd371b 10179 int ret, i = -1;
79e53945 10180
d2dff872 10181 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10182 connector->base.id, connector->name,
8e329a03 10183 encoder->base.id, encoder->name);
d2dff872 10184
51fd371b
RC		 10185retry:
10186 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10187 if (ret)
10188 goto fail_unlock;
6e9f798d 10189
79e53945
JB		 10190 /*
10191 * Algorithm gets a little messy:
7a5e4805 10192 *
79e53945
JB		 10193 * - if the connector already has an assigned crtc, use it (but make
10194 * sure it's on first)
7a5e4805 10195 *
79e53945
JB		 10196 * - try to find the first unused crtc that can drive this connector,
10197 * and use that if we find one
79e53945
JB		 10198 */
10199
10200 /* See if we already have a CRTC for this connector */
10201 if (encoder->crtc) {
10202 crtc = encoder->crtc;
8261b191 10203
51fd371b 10204 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de
DV		 10205 if (ret)
10206 goto fail_unlock;
10207 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b
RC		 10208 if (ret)
10209 goto fail_unlock;
7b24056b 10210
24218aac 10211 old->dpms_mode = connector->dpms;
8261b191
CW		 10212 old->load_detect_temp = false;
10213
10214 /* Make sure the crtc and connector are running */
24218aac
DV		 10215 if (connector->dpms != DRM_MODE_DPMS_ON)
10216 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 10217
7173188d 10218 return true;
79e53945
JB		 10219 }
10220
10221 /* Find an unused one (if possible) */
70e1e0ec 10222 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 10223 i++;
10224 if (!(encoder->possible_crtcs & (1 << i)))
10225 continue;
83d65738 10226 if (possible_crtc->state->enable)
a459249c
VS		 10227 continue;
10228 /* This can occur when applying the pipe A quirk on resume. */
10229 if (to_intel_crtc(possible_crtc)->new_enabled)
10230 continue;
10231
10232 crtc = possible_crtc;
10233 break;
79e53945
JB		 10234 }
10235
10236 /*
10237 * If we didn't find an unused CRTC, don't use any.
10238 */
10239 if (!crtc) {
7173188d 10240 DRM_DEBUG_KMS("no pipe available for load-detect\n");
51fd371b 10241 goto fail_unlock;
79e53945
JB		 10242 }
10243
51fd371b
RC		 10244 ret = drm_modeset_lock(&crtc->mutex, ctx);
10245 if (ret)
4d02e2de
DV		 10246 goto fail_unlock;
10247 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10248 if (ret)
51fd371b 10249 goto fail_unlock;
fc303101
DV		 10250 intel_encoder->new_crtc = to_intel_crtc(crtc);
10251 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 10252
10253 intel_crtc = to_intel_crtc(crtc);
412b61d8 10254 intel_crtc->new_enabled = true;
24218aac 10255 old->dpms_mode = connector->dpms;
8261b191 10256 old->load_detect_temp = true;
d2dff872 10257 old->release_fb = NULL;
79e53945 10258
83a57153
ACO		 10259 state = drm_atomic_state_alloc(dev);
10260 if (!state)
10261 return false;
10262
10263 state->acquire_ctx = ctx;
10264
944b0c76
ACO		 10265 connector_state = drm_atomic_get_connector_state(state, connector);
10266 if (IS_ERR(connector_state)) {
10267 ret = PTR_ERR(connector_state);
10268 goto fail;
10269 }
10270
10271 connector_state->crtc = crtc;
10272 connector_state->best_encoder = &intel_encoder->base;
10273
4be07317
ACO		 10274 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10275 if (IS_ERR(crtc_state)) {
10276 ret = PTR_ERR(crtc_state);
10277 goto fail;
10278 }
10279
49d6fa21 10280 crtc_state->base.active = crtc_state->base.enable = true;
4be07317 10281
6492711d
CW		 10282 if (!mode)
10283 mode = &load_detect_mode;
79e53945 10284
d2dff872
CW		 10285 /* We need a framebuffer large enough to accommodate all accesses
10286 * that the plane may generate whilst we perform load detection.
10287 * We can not rely on the fbcon either being present (we get called
10288 * during its initialisation to detect all boot displays, or it may
10289 * not even exist) or that it is large enough to satisfy the
10290 * requested mode.
10291 */
94352cf9
DV		 10292 fb = mode_fits_in_fbdev(dev, mode);
10293 if (fb == NULL) {
d2dff872 10294 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 10295 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10296 old->release_fb = fb;
d2dff872
CW		 10297 } else
10298 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 10299 if (IS_ERR(fb)) {
d2dff872 10300 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 10301 goto fail;
79e53945 10302 }
79e53945 10303
d3a40d1b
ACO		 10304 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10305 if (ret)
10306 goto fail;
10307
8c7b5ccb
ACO		 10308 drm_mode_copy(&crtc_state->base.mode, mode);
10309
10310 if (intel_set_mode(crtc, state)) {
6492711d 10311 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 10312 if (old->release_fb)
10313 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 10314 goto fail;
79e53945 10315 }
9128b040 10316 crtc->primary->crtc = crtc;
7173188d 10317
79e53945 10318 /* let the connector get through one full cycle before testing */
9d0498a2 10319 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 10320 return true;
412b61d8
VS		 10321
10322 fail:
83d65738 10323 intel_crtc->new_enabled = crtc->state->enable;
51fd371b 10324fail_unlock:
e5d958ef
ACO		 10325 drm_atomic_state_free(state);
10326 state = NULL;
83a57153 10327
51fd371b
RC		 10328 if (ret == -EDEADLK) {
10329 drm_modeset_backoff(ctx);
10330 goto retry;
10331 }
10332
412b61d8 10333 return false;
79e53945
JB		 10334}
10335
d2434ab7 10336void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 10337 struct intel_load_detect_pipe *old,
10338 struct drm_modeset_acquire_ctx *ctx)
79e53945 10339{
83a57153 10340 struct drm_device *dev = connector->dev;
d2434ab7
DV		 10341 struct intel_encoder *intel_encoder =
10342 intel_attached_encoder(connector);
4ef69c7a 10343 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 10344 struct drm_crtc *crtc = encoder->crtc;
412b61d8 10345 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 10346 struct drm_atomic_state *state;
944b0c76 10347 struct drm_connector_state *connector_state;
4be07317 10348 struct intel_crtc_state *crtc_state;
d3a40d1b 10349 int ret;
79e53945 10350
d2dff872 10351 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10352 connector->base.id, connector->name,
8e329a03 10353 encoder->base.id, encoder->name);
d2dff872 10354
8261b191 10355 if (old->load_detect_temp) {
83a57153 10356 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 10357 if (!state)
10358 goto fail;
83a57153
ACO		 10359
10360 state->acquire_ctx = ctx;
10361
944b0c76
ACO		 10362 connector_state = drm_atomic_get_connector_state(state, connector);
10363 if (IS_ERR(connector_state))
10364 goto fail;
10365
4be07317
ACO		 10366 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10367 if (IS_ERR(crtc_state))
10368 goto fail;
10369
fc303101
DV		 10370 to_intel_connector(connector)->new_encoder = NULL;
10371 intel_encoder->new_crtc = NULL;
412b61d8 10372 intel_crtc->new_enabled = false;
944b0c76
ACO		 10373
10374 connector_state->best_encoder = NULL;
10375 connector_state->crtc = NULL;
10376
49d6fa21 10377 crtc_state->base.enable = crtc_state->base.active = false;
4be07317 10378
d3a40d1b
ACO		 10379 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10380 0, 0);
10381 if (ret)
10382 goto fail;
10383
2bfb4627
ACO		 10384 ret = intel_set_mode(crtc, state);
10385 if (ret)
10386 goto fail;
d2dff872 10387
36206361
DV		 10388 if (old->release_fb) {
10389 drm_framebuffer_unregister_private(old->release_fb);
10390 drm_framebuffer_unreference(old->release_fb);
10391 }
d2dff872 10392
0622a53c 10393 return;
79e53945
JB		 10394 }
10395
c751ce4f 10396 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 10397 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10398 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 10399
10400 return;
10401fail:
10402 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10403 drm_atomic_state_free(state);
79e53945
JB		 10404}
10405
da4a1efa 10406static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 10407 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 10408{
10409 struct drm_i915_private *dev_priv = dev->dev_private;
10410 u32 dpll = pipe_config->dpll_hw_state.dpll;
10411
10412 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 10413 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 10414 else if (HAS_PCH_SPLIT(dev))
10415 return 120000;
10416 else if (!IS_GEN2(dev))
10417 return 96000;
10418 else
10419 return 48000;
10420}
10421
79e53945 10422/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 10423static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 10424 struct intel_crtc_state *pipe_config)
79e53945 10425{
f1f644dc 10426 struct drm_device *dev = crtc->base.dev;
79e53945 10427 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 10428 int pipe = pipe_config->cpu_transcoder;
293623f7 10429 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 10430 u32 fp;
10431 intel_clock_t clock;
da4a1efa 10432 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 10433
10434 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 10435 fp = pipe_config->dpll_hw_state.fp0;
79e53945 10436 else
293623f7 10437 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 10438
10439 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 10440 if (IS_PINEVIEW(dev)) {
10441 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10442 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 10443 } else {
10444 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10445 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10446 }
10447
a6c45cf0 10448 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 10449 if (IS_PINEVIEW(dev))
10450 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10451 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 10452 else
10453 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 10454 DPLL_FPA01_P1_POST_DIV_SHIFT);
10455
10456 switch (dpll & DPLL_MODE_MASK) {
10457 case DPLLB_MODE_DAC_SERIAL:
10458 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10459 5 : 10;
10460 break;
10461 case DPLLB_MODE_LVDS:
10462 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10463 7 : 14;
10464 break;
10465 default:
28c97730 10466 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 10467 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 10468 return;
79e53945
JB		 10469 }
10470
ac58c3f0 10471 if (IS_PINEVIEW(dev))
da4a1efa 10472 pineview_clock(refclk, &clock);
ac58c3f0 10473 else
da4a1efa 10474 i9xx_clock(refclk, &clock);
79e53945 10475 } else {
0fb58223 10476 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 10477 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 10478
10479 if (is_lvds) {
10480 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10481 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 10482
10483 if (lvds & LVDS_CLKB_POWER_UP)
10484 clock.p2 = 7;
10485 else
10486 clock.p2 = 14;
79e53945
JB		 10487 } else {
10488 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10489 clock.p1 = 2;
10490 else {
10491 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10492 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10493 }
10494 if (dpll & PLL_P2_DIVIDE_BY_4)
10495 clock.p2 = 4;
10496 else
10497 clock.p2 = 2;
79e53945 10498 }
da4a1efa
VS		 10499
10500 i9xx_clock(refclk, &clock);
79e53945
JB		 10501 }
10502
18442d08
VS		 10503 /*
10504 * This value includes pixel_multiplier. We will use
241bfc38 10505 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 10506 * encoder's get_config() function.
10507 */
10508 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 10509}
10510
6878da05
VS		 10511int intel_dotclock_calculate(int link_freq,
10512 const struct intel_link_m_n *m_n)
f1f644dc 10513{
f1f644dc
JB		 10514 /*
10515 * The calculation for the data clock is:
1041a02f 10516 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 10517 * But we want to avoid losing precison if possible, so:
1041a02f 10518 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 10519 *
10520 * and the link clock is simpler:
1041a02f 10521 * link_clock = (m * link_clock) / n
f1f644dc
JB		 10522 */
10523
6878da05
VS		 10524 if (!m_n->link_n)
10525 return 0;
f1f644dc 10526
6878da05
VS		 10527 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10528}
f1f644dc 10529
18442d08 10530static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 10531 struct intel_crtc_state *pipe_config)
6878da05
VS		 10532{
10533 struct drm_device *dev = crtc->base.dev;
79e53945 10534
18442d08
VS		 10535 /* read out port_clock from the DPLL */
10536 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 10537
f1f644dc 10538 /*
18442d08 10539 * This value does not include pixel_multiplier.
241bfc38 10540 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 10541 * agree once we know their relationship in the encoder's
10542 * get_config() function.
79e53945 10543 */
2d112de7 10544 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 10545 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10546 &pipe_config->fdi_m_n);
79e53945
JB		 10547}
10548
10549/** Returns the currently programmed mode of the given pipe. */
10550struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10551 struct drm_crtc *crtc)
10552{
548f245b 10553 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 10554 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 10555 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 10556 struct drm_display_mode *mode;
5cec258b 10557 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 10558 int htot = I915_READ(HTOTAL(cpu_transcoder));
10559 int hsync = I915_READ(HSYNC(cpu_transcoder));
10560 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10561 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 10562 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 10563
10564 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10565 if (!mode)
10566 return NULL;
10567
f1f644dc
JB		 10568 /*
10569 * Construct a pipe_config sufficient for getting the clock info
10570 * back out of crtc_clock_get.
10571 *
10572 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10573 * to use a real value here instead.
10574 */
293623f7 10575 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 10576 pipe_config.pixel_multiplier = 1;
293623f7
VS		 10577 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10578 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10579 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 10580 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10581
773ae034 10582 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 10583 mode->hdisplay = (htot & 0xffff) + 1;
10584 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10585 mode->hsync_start = (hsync & 0xffff) + 1;
10586 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10587 mode->vdisplay = (vtot & 0xffff) + 1;
10588 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10589 mode->vsync_start = (vsync & 0xffff) + 1;
10590 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10591
10592 drm_mode_set_name(mode);
79e53945
JB		 10593
10594 return mode;
10595}
10596
652c393a
JB		 10597static void intel_decrease_pllclock(struct drm_crtc *crtc)
10598{
10599 struct drm_device *dev = crtc->dev;
fbee40df 10600 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10601 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 10602
baff296c 10603 if (!HAS_GMCH_DISPLAY(dev))
652c393a
JB		 10604 return;
10605
10606 if (!dev_priv->lvds_downclock_avail)
10607 return;
10608
10609 /*
10610 * Since this is called by a timer, we should never get here in
10611 * the manual case.
10612 */
10613 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 10614 int pipe = intel_crtc->pipe;
10615 int dpll_reg = DPLL(pipe);
10616 int dpll;
f6e5b160 10617
44d98a61 10618 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 10619
8ac5a6d5 10620 assert_panel_unlocked(dev_priv, pipe);
652c393a 10621
dc257cf1 10622 dpll = I915_READ(dpll_reg);
652c393a
JB		 10623 dpll |= DISPLAY_RATE_SELECT_FPA1;
10624 I915_WRITE(dpll_reg, dpll);
9d0498a2 10625 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 10626 dpll = I915_READ(dpll_reg);
10627 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 10628 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 10629 }
10630
10631}
10632
f047e395
CW		 10633void intel_mark_busy(struct drm_device *dev)
10634{
c67a470b
PZ		 10635 struct drm_i915_private *dev_priv = dev->dev_private;
10636
f62a0076
CW		 10637 if (dev_priv->mm.busy)
10638 return;
10639
43694d69 10640 intel_runtime_pm_get(dev_priv);
c67a470b 10641 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 10642 if (INTEL_INFO(dev)->gen >= 6)
10643 gen6_rps_busy(dev_priv);
f62a0076 10644 dev_priv->mm.busy = true;
f047e395
CW		 10645}
10646
10647void intel_mark_idle(struct drm_device *dev)
652c393a 10648{
c67a470b 10649 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10650 struct drm_crtc *crtc;
652c393a 10651
f62a0076
CW		 10652 if (!dev_priv->mm.busy)
10653 return;
10654
10655 dev_priv->mm.busy = false;
10656
70e1e0ec 10657 for_each_crtc(dev, crtc) {
f4510a27 10658 if (!crtc->primary->fb)
652c393a
JB		 10659 continue;
10660
725a5b54 10661 intel_decrease_pllclock(crtc);
652c393a 10662 }
b29c19b6 10663
3d13ef2e 10664 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 10665 gen6_rps_idle(dev->dev_private);
bb4cdd53 10666
43694d69 10667 intel_runtime_pm_put(dev_priv);
652c393a
JB		 10668}
10669
79e53945
JB		 10670static void intel_crtc_destroy(struct drm_crtc *crtc)
10671{
10672 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 10673 struct drm_device *dev = crtc->dev;
10674 struct intel_unpin_work *work;
67e77c5a 10675
5e2d7afc 10676 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 10677 work = intel_crtc->unpin_work;
10678 intel_crtc->unpin_work = NULL;
5e2d7afc 10679 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 10680
10681 if (work) {
10682 cancel_work_sync(&work->work);
10683 kfree(work);
10684 }
79e53945
JB		 10685
10686 drm_crtc_cleanup(crtc);
67e77c5a 10687
79e53945
JB		 10688 kfree(intel_crtc);
10689}
10690
6b95a207
KH		 10691static void intel_unpin_work_fn(struct work_struct *__work)
10692{
10693 struct intel_unpin_work *work =
10694 container_of(__work, struct intel_unpin_work, work);
b4a98e57 10695 struct drm_device *dev = work->crtc->dev;
f99d7069 10696 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
6b95a207 10697
b4a98e57 10698 mutex_lock(&dev->struct_mutex);
82bc3b2d 10699 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
05394f39 10700 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 10701
7ff0ebcc 10702 intel_fbc_update(dev);
f06cc1b9
JH		 10703
10704 if (work->flip_queued_req)
146d84f0 10705 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 10706 mutex_unlock(&dev->struct_mutex);
10707
f99d7069 10708 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
89ed88ba 10709 drm_framebuffer_unreference(work->old_fb);
f99d7069 10710
b4a98e57
CW		 10711 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10712 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10713
6b95a207
KH		 10714 kfree(work);
10715}
10716
1afe3e9d 10717static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 10718 struct drm_crtc *crtc)
6b95a207 10719{
6b95a207
KH		 10720 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10721 struct intel_unpin_work *work;
6b95a207
KH		 10722 unsigned long flags;
10723
10724 /* Ignore early vblank irqs */
10725 if (intel_crtc == NULL)
10726 return;
10727
f326038a
DV		 10728 /*
10729 * This is called both by irq handlers and the reset code (to complete
10730 * lost pageflips) so needs the full irqsave spinlocks.
10731 */
6b95a207
KH		 10732 spin_lock_irqsave(&dev->event_lock, flags);
10733 work = intel_crtc->unpin_work;
e7d841ca
CW		 10734
10735 /* Ensure we don't miss a work->pending update ... */
10736 smp_rmb();
10737
10738 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 10739 spin_unlock_irqrestore(&dev->event_lock, flags);
10740 return;
10741 }
10742
d6bbafa1 10743 page_flip_completed(intel_crtc);
0af7e4df 10744
6b95a207 10745 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 10746}
10747
1afe3e9d
JB		 10748void intel_finish_page_flip(struct drm_device *dev, int pipe)
10749{
fbee40df 10750 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10751 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10752
49b14a5c 10753 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10754}
10755
10756void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10757{
fbee40df 10758 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10759 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10760
49b14a5c 10761 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10762}
10763
75f7f3ec
VS		 10764/* Is 'a' after or equal to 'b'? */
10765static bool g4x_flip_count_after_eq(u32 a, u32 b)
10766{
10767 return !((a - b) & 0x80000000);
10768}
10769
10770static bool page_flip_finished(struct intel_crtc *crtc)
10771{
10772 struct drm_device *dev = crtc->base.dev;
10773 struct drm_i915_private *dev_priv = dev->dev_private;
10774
bdfa7542
VS		 10775 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10776 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10777 return true;
10778
75f7f3ec
VS		 10779 /*
10780 * The relevant registers doen't exist on pre-ctg.
10781 * As the flip done interrupt doesn't trigger for mmio
10782 * flips on gmch platforms, a flip count check isn't
10783 * really needed there. But since ctg has the registers,
10784 * include it in the check anyway.
10785 */
10786 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10787 return true;
10788
10789 /*
10790 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10791 * used the same base address. In that case the mmio flip might
10792 * have completed, but the CS hasn't even executed the flip yet.
10793 *
10794 * A flip count check isn't enough as the CS might have updated
10795 * the base address just after start of vblank, but before we
10796 * managed to process the interrupt. This means we'd complete the
10797 * CS flip too soon.
10798 *
10799 * Combining both checks should get us a good enough result. It may
10800 * still happen that the CS flip has been executed, but has not
10801 * yet actually completed. But in case the base address is the same
10802 * anyway, we don't really care.
10803 */
10804 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10805 crtc->unpin_work->gtt_offset &&
10806 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10807 crtc->unpin_work->flip_count);
10808}
10809
6b95a207
KH		 10810void intel_prepare_page_flip(struct drm_device *dev, int plane)
10811{
fbee40df 10812 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 10813 struct intel_crtc *intel_crtc =
10814 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10815 unsigned long flags;
10816
f326038a
DV		 10817
10818 /*
10819 * This is called both by irq handlers and the reset code (to complete
10820 * lost pageflips) so needs the full irqsave spinlocks.
10821 *
10822 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 10823 * generate a page-flip completion irq, i.e. every modeset
10824 * is also accompanied by a spurious intel_prepare_page_flip().
10825 */
6b95a207 10826 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 10827 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 10828 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 10829 spin_unlock_irqrestore(&dev->event_lock, flags);
10830}
10831
eba905b2 10832static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW		 10833{
10834 /* Ensure that the work item is consistent when activating it ... */
10835 smp_wmb();
10836 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10837 /* and that it is marked active as soon as the irq could fire. */
10838 smp_wmb();
10839}
10840
8c9f3aaf
JB		 10841static int intel_gen2_queue_flip(struct drm_device *dev,
10842 struct drm_crtc *crtc,
10843 struct drm_framebuffer *fb,
ed8d1975 10844 struct drm_i915_gem_object *obj,
a4872ba6 10845 struct intel_engine_cs *ring,
ed8d1975 10846 uint32_t flags)
8c9f3aaf 10847{
8c9f3aaf 10848 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10849 u32 flip_mask;
10850 int ret;
10851
6d90c952 10852 ret = intel_ring_begin(ring, 6);
8c9f3aaf 10853 if (ret)
4fa62c89 10854 return ret;
8c9f3aaf
JB		 10855
10856 /* Can't queue multiple flips, so wait for the previous
10857 * one to finish before executing the next.
10858 */
10859 if (intel_crtc->plane)
10860 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10861 else
10862 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10863 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10864 intel_ring_emit(ring, MI_NOOP);
10865 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10866 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10867 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10868 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 10869 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 10870
10871 intel_mark_page_flip_active(intel_crtc);
09246732 10872 __intel_ring_advance(ring);
83d4092b 10873 return 0;
8c9f3aaf
JB		 10874}
10875
10876static int intel_gen3_queue_flip(struct drm_device *dev,
10877 struct drm_crtc *crtc,
10878 struct drm_framebuffer *fb,
ed8d1975 10879 struct drm_i915_gem_object *obj,
a4872ba6 10880 struct intel_engine_cs *ring,
ed8d1975 10881 uint32_t flags)
8c9f3aaf 10882{
8c9f3aaf 10883 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10884 u32 flip_mask;
10885 int ret;
10886
6d90c952 10887 ret = intel_ring_begin(ring, 6);
8c9f3aaf 10888 if (ret)
4fa62c89 10889 return ret;
8c9f3aaf
JB		 10890
10891 if (intel_crtc->plane)
10892 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10893 else
10894 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10895 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10896 intel_ring_emit(ring, MI_NOOP);
10897 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10898 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10899 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10900 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 10901 intel_ring_emit(ring, MI_NOOP);
10902
e7d841ca 10903 intel_mark_page_flip_active(intel_crtc);
09246732 10904 __intel_ring_advance(ring);
83d4092b 10905 return 0;
8c9f3aaf
JB		 10906}
10907
10908static int intel_gen4_queue_flip(struct drm_device *dev,
10909 struct drm_crtc *crtc,
10910 struct drm_framebuffer *fb,
ed8d1975 10911 struct drm_i915_gem_object *obj,
a4872ba6 10912 struct intel_engine_cs *ring,
ed8d1975 10913 uint32_t flags)
8c9f3aaf
JB		 10914{
10915 struct drm_i915_private *dev_priv = dev->dev_private;
10916 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10917 uint32_t pf, pipesrc;
10918 int ret;
10919
6d90c952 10920 ret = intel_ring_begin(ring, 4);
8c9f3aaf 10921 if (ret)
4fa62c89 10922 return ret;
8c9f3aaf
JB		 10923
10924 /* i965+ uses the linear or tiled offsets from the
10925 * Display Registers (which do not change across a page-flip)
10926 * so we need only reprogram the base address.
10927 */
6d90c952
DV		 10928 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10929 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10930 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10931 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 10932 obj->tiling_mode);
8c9f3aaf
JB		 10933
10934 /* XXX Enabling the panel-fitter across page-flip is so far
10935 * untested on non-native modes, so ignore it for now.
10936 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10937 */
10938 pf = 0;
10939 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10940 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10941
10942 intel_mark_page_flip_active(intel_crtc);
09246732 10943 __intel_ring_advance(ring);
83d4092b 10944 return 0;
8c9f3aaf
JB		 10945}
10946
10947static int intel_gen6_queue_flip(struct drm_device *dev,
10948 struct drm_crtc *crtc,
10949 struct drm_framebuffer *fb,
ed8d1975 10950 struct drm_i915_gem_object *obj,
a4872ba6 10951 struct intel_engine_cs *ring,
ed8d1975 10952 uint32_t flags)
8c9f3aaf
JB		 10953{
10954 struct drm_i915_private *dev_priv = dev->dev_private;
10955 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10956 uint32_t pf, pipesrc;
10957 int ret;
10958
6d90c952 10959 ret = intel_ring_begin(ring, 4);
8c9f3aaf 10960 if (ret)
4fa62c89 10961 return ret;
8c9f3aaf 10962
6d90c952
DV		 10963 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10964 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10965 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 10966 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 10967
dc257cf1
DV		 10968 /* Contrary to the suggestions in the documentation,
10969 * "Enable Panel Fitter" does not seem to be required when page
10970 * flipping with a non-native mode, and worse causes a normal
10971 * modeset to fail.
10972 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10973 */
10974 pf = 0;
8c9f3aaf 10975 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10976 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10977
10978 intel_mark_page_flip_active(intel_crtc);
09246732 10979 __intel_ring_advance(ring);
83d4092b 10980 return 0;
8c9f3aaf
JB		 10981}
10982
7c9017e5
JB		 10983static int intel_gen7_queue_flip(struct drm_device *dev,
10984 struct drm_crtc *crtc,
10985 struct drm_framebuffer *fb,
ed8d1975 10986 struct drm_i915_gem_object *obj,
a4872ba6 10987 struct intel_engine_cs *ring,
ed8d1975 10988 uint32_t flags)
7c9017e5 10989{
7c9017e5 10990 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 10991 uint32_t plane_bit = 0;
ffe74d75
CW		 10992 int len, ret;
10993
eba905b2 10994 switch (intel_crtc->plane) {
cb05d8de
DV		 10995 case PLANE_A:
10996 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10997 break;
10998 case PLANE_B:
10999 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11000 break;
11001 case PLANE_C:
11002 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11003 break;
11004 default:
11005 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 11006 return -ENODEV;
cb05d8de
DV		 11007 }
11008
ffe74d75 11009 len = 4;
f476828a 11010 if (ring->id == RCS) {
ffe74d75 11011 len += 6;
f476828a
DL		 11012 /*
11013 * On Gen 8, SRM is now taking an extra dword to accommodate
11014 * 48bits addresses, and we need a NOOP for the batch size to
11015 * stay even.
11016 */
11017 if (IS_GEN8(dev))
11018 len += 2;
11019 }
ffe74d75 11020
f66fab8e
VS		 11021 /*
11022 * BSpec MI_DISPLAY_FLIP for IVB:
11023 * "The full packet must be contained within the same cache line."
11024 *
11025 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11026 * cacheline, if we ever start emitting more commands before
11027 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11028 * then do the cacheline alignment, and finally emit the
11029 * MI_DISPLAY_FLIP.
11030 */
11031 ret = intel_ring_cacheline_align(ring);
11032 if (ret)
4fa62c89 11033 return ret;
f66fab8e 11034
ffe74d75 11035 ret = intel_ring_begin(ring, len);
7c9017e5 11036 if (ret)
4fa62c89 11037 return ret;
7c9017e5 11038
ffe74d75
CW		 11039 /* Unmask the flip-done completion message. Note that the bspec says that
11040 * we should do this for both the BCS and RCS, and that we must not unmask
11041 * more than one flip event at any time (or ensure that one flip message
11042 * can be sent by waiting for flip-done prior to queueing new flips).
11043 * Experimentation says that BCS works despite DERRMR masking all
11044 * flip-done completion events and that unmasking all planes at once
11045 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11046 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11047 */
11048 if (ring->id == RCS) {
11049 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11050 intel_ring_emit(ring, DERRMR);
11051 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11052 DERRMR_PIPEB_PRI_FLIP_DONE |
11053 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a
DL		 11054 if (IS_GEN8(dev))
11055 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11056 MI_SRM_LRM_GLOBAL_GTT);
11057 else
11058 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11059 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 11060 intel_ring_emit(ring, DERRMR);
11061 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 11062 if (IS_GEN8(dev)) {
11063 intel_ring_emit(ring, 0);
11064 intel_ring_emit(ring, MI_NOOP);
11065 }
ffe74d75
CW		 11066 }
11067
cb05d8de 11068 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 11069 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 11070 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 11071 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 11072
11073 intel_mark_page_flip_active(intel_crtc);
09246732 11074 __intel_ring_advance(ring);
83d4092b 11075 return 0;
7c9017e5
JB		 11076}
11077
84c33a64
SG		 11078static bool use_mmio_flip(struct intel_engine_cs *ring,
11079 struct drm_i915_gem_object *obj)
11080{
11081 /*
11082 * This is not being used for older platforms, because
11083 * non-availability of flip done interrupt forces us to use
11084 * CS flips. Older platforms derive flip done using some clever
11085 * tricks involving the flip_pending status bits and vblank irqs.
11086 * So using MMIO flips there would disrupt this mechanism.
11087 */
11088
8e09bf83
CW		 11089 if (ring == NULL)
11090 return true;
11091
84c33a64
SG		 11092 if (INTEL_INFO(ring->dev)->gen < 5)
11093 return false;
11094
11095 if (i915.use_mmio_flip < 0)
11096 return false;
11097 else if (i915.use_mmio_flip > 0)
11098 return true;
14bf993e
OM		 11099 else if (i915.enable_execlists)
11100 return true;
84c33a64 11101 else
b4716185 11102 return ring != i915_gem_request_get_ring(obj->last_write_req);
84c33a64
SG		 11103}
11104
ff944564
DL		 11105static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11106{
11107 struct drm_device *dev = intel_crtc->base.dev;
11108 struct drm_i915_private *dev_priv = dev->dev_private;
11109 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
ff944564
DL		 11110 const enum pipe pipe = intel_crtc->pipe;
11111 u32 ctl, stride;
11112
11113 ctl = I915_READ(PLANE_CTL(pipe, 0));
11114 ctl &= ~PLANE_CTL_TILED_MASK;
2ebef630
TU		 11115 switch (fb->modifier[0]) {
11116 case DRM_FORMAT_MOD_NONE:
11117 break;
11118 case I915_FORMAT_MOD_X_TILED:
ff944564 11119 ctl |= PLANE_CTL_TILED_X;
2ebef630
TU		 11120 break;
11121 case I915_FORMAT_MOD_Y_TILED:
11122 ctl |= PLANE_CTL_TILED_Y;
11123 break;
11124 case I915_FORMAT_MOD_Yf_TILED:
11125 ctl |= PLANE_CTL_TILED_YF;
11126 break;
11127 default:
11128 MISSING_CASE(fb->modifier[0]);
11129 }
ff944564
DL		 11130
11131 /*
11132 * The stride is either expressed as a multiple of 64 bytes chunks for
11133 * linear buffers or in number of tiles for tiled buffers.
11134 */
2ebef630
TU		 11135 stride = fb->pitches[0] /
11136 intel_fb_stride_alignment(dev, fb->modifier[0],
11137 fb->pixel_format);
ff944564
DL		 11138
11139 /*
11140 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11141 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11142 */
11143 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11144 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11145
11146 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11147 POSTING_READ(PLANE_SURF(pipe, 0));
11148}
11149
11150static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG		 11151{
11152 struct drm_device *dev = intel_crtc->base.dev;
11153 struct drm_i915_private *dev_priv = dev->dev_private;
11154 struct intel_framebuffer *intel_fb =
11155 to_intel_framebuffer(intel_crtc->base.primary->fb);
11156 struct drm_i915_gem_object *obj = intel_fb->obj;
11157 u32 dspcntr;
11158 u32 reg;
11159
84c33a64
SG		 11160 reg = DSPCNTR(intel_crtc->plane);
11161 dspcntr = I915_READ(reg);
11162
c5d97472
DL		 11163 if (obj->tiling_mode != I915_TILING_NONE)
11164 dspcntr |= DISPPLANE_TILED;
11165 else
11166 dspcntr &= ~DISPPLANE_TILED;
11167
84c33a64
SG		 11168 I915_WRITE(reg, dspcntr);
11169
11170 I915_WRITE(DSPSURF(intel_crtc->plane),
11171 intel_crtc->unpin_work->gtt_offset);
11172 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 11173
ff944564
DL		 11174}
11175
11176/*
11177 * XXX: This is the temporary way to update the plane registers until we get
11178 * around to using the usual plane update functions for MMIO flips
11179 */
11180static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11181{
11182 struct drm_device *dev = intel_crtc->base.dev;
11183 bool atomic_update;
11184 u32 start_vbl_count;
11185
11186 intel_mark_page_flip_active(intel_crtc);
11187
11188 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
11189
11190 if (INTEL_INFO(dev)->gen >= 9)
11191 skl_do_mmio_flip(intel_crtc);
11192 else
11193 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11194 ilk_do_mmio_flip(intel_crtc);
11195
9362c7c5
ACO		 11196 if (atomic_update)
11197 intel_pipe_update_end(intel_crtc, start_vbl_count);
84c33a64
SG		 11198}
11199
9362c7c5 11200static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 11201{
b2cfe0ab
CW		 11202 struct intel_mmio_flip *mmio_flip =
11203 container_of(work, struct intel_mmio_flip, work);
84c33a64 11204
eed29a5b
DV		 11205 if (mmio_flip->req)
11206 WARN_ON(__i915_wait_request(mmio_flip->req,
b2cfe0ab 11207 mmio_flip->crtc->reset_counter,
bcafc4e3
CW		 11208 false, NULL,
11209 &mmio_flip->i915->rps.mmioflips));
84c33a64 11210
b2cfe0ab
CW		 11211 intel_do_mmio_flip(mmio_flip->crtc);
11212
eed29a5b 11213 i915_gem_request_unreference__unlocked(mmio_flip->req);
b2cfe0ab 11214 kfree(mmio_flip);
84c33a64
SG		 11215}
11216
11217static int intel_queue_mmio_flip(struct drm_device *dev,
11218 struct drm_crtc *crtc,
11219 struct drm_framebuffer *fb,
11220 struct drm_i915_gem_object *obj,
11221 struct intel_engine_cs *ring,
11222 uint32_t flags)
11223{
b2cfe0ab
CW		 11224 struct intel_mmio_flip *mmio_flip;
11225
11226 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11227 if (mmio_flip == NULL)
11228 return -ENOMEM;
84c33a64 11229
bcafc4e3 11230 mmio_flip->i915 = to_i915(dev);
eed29a5b 11231 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
b2cfe0ab 11232 mmio_flip->crtc = to_intel_crtc(crtc);
536f5b5e 11233
b2cfe0ab
CW		 11234 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11235 schedule_work(&mmio_flip->work);
84c33a64 11236
84c33a64
SG		 11237 return 0;
11238}
11239
8c9f3aaf
JB		 11240static int intel_default_queue_flip(struct drm_device *dev,
11241 struct drm_crtc *crtc,
11242 struct drm_framebuffer *fb,
ed8d1975 11243 struct drm_i915_gem_object *obj,
a4872ba6 11244 struct intel_engine_cs *ring,
ed8d1975 11245 uint32_t flags)
8c9f3aaf
JB		 11246{
11247 return -ENODEV;
11248}
11249
d6bbafa1
CW		 11250static bool __intel_pageflip_stall_check(struct drm_device *dev,
11251 struct drm_crtc *crtc)
11252{
11253 struct drm_i915_private *dev_priv = dev->dev_private;
11254 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11255 struct intel_unpin_work *work = intel_crtc->unpin_work;
11256 u32 addr;
11257
11258 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11259 return true;
11260
11261 if (!work->enable_stall_check)
11262 return false;
11263
11264 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 11265 if (work->flip_queued_req &&
11266 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 11267 return false;
11268
1e3feefd 11269 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 11270 }
11271
1e3feefd 11272 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 11273 return false;
11274
11275 /* Potential stall - if we see that the flip has happened,
11276 * assume a missed interrupt. */
11277 if (INTEL_INFO(dev)->gen >= 4)
11278 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11279 else
11280 addr = I915_READ(DSPADDR(intel_crtc->plane));
11281
11282 /* There is a potential issue here with a false positive after a flip
11283 * to the same address. We could address this by checking for a
11284 * non-incrementing frame counter.
11285 */
11286 return addr == work->gtt_offset;
11287}
11288
11289void intel_check_page_flip(struct drm_device *dev, int pipe)
11290{
11291 struct drm_i915_private *dev_priv = dev->dev_private;
11292 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11293 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 11294 struct intel_unpin_work *work;
f326038a 11295
6c51d46f 11296 WARN_ON(!in_interrupt());
d6bbafa1
CW		 11297
11298 if (crtc == NULL)
11299 return;
11300
f326038a 11301 spin_lock(&dev->event_lock);
6ad790c0
CW		 11302 work = intel_crtc->unpin_work;
11303 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 11304 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 11305 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 11306 page_flip_completed(intel_crtc);
6ad790c0 11307 work = NULL;
d6bbafa1 11308 }
6ad790c0
CW		 11309 if (work != NULL &&
11310 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11311 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 11312 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 11313}
11314
6b95a207
KH		 11315static int intel_crtc_page_flip(struct drm_crtc *crtc,
11316 struct drm_framebuffer *fb,
ed8d1975
KP		 11317 struct drm_pending_vblank_event *event,
11318 uint32_t page_flip_flags)
6b95a207
KH		 11319{
11320 struct drm_device *dev = crtc->dev;
11321 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 11322 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 11323 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 11324 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 11325 struct drm_plane *primary = crtc->primary;
a071fa00 11326 enum pipe pipe = intel_crtc->pipe;
6b95a207 11327 struct intel_unpin_work *work;
a4872ba6 11328 struct intel_engine_cs *ring;
cf5d8a46 11329 bool mmio_flip;
52e68630 11330 int ret;
6b95a207 11331
2ff8fde1
MR		 11332 /*
11333 * drm_mode_page_flip_ioctl() should already catch this, but double
11334 * check to be safe. In the future we may enable pageflipping from
11335 * a disabled primary plane.
11336 */
11337 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11338 return -EBUSY;
11339
e6a595d2 11340 /* Can't change pixel format via MI display flips. */
f4510a27 11341 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 11342 return -EINVAL;
11343
11344 /*
11345 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11346 * Note that pitch changes could also affect these register.
11347 */
11348 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 11349 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11350 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 11351 return -EINVAL;
11352
f900db47
CW		 11353 if (i915_terminally_wedged(&dev_priv->gpu_error))
11354 goto out_hang;
11355
b14c5679 11356 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 11357 if (work == NULL)
11358 return -ENOMEM;
11359
6b95a207 11360 work->event = event;
b4a98e57 11361 work->crtc = crtc;
ab8d6675 11362 work->old_fb = old_fb;
6b95a207
KH		 11363 INIT_WORK(&work->work, intel_unpin_work_fn);
11364
87b6b101 11365 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 11366 if (ret)
11367 goto free_work;
11368
6b95a207 11369 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 11370 spin_lock_irq(&dev->event_lock);
6b95a207 11371 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 11372 /* Before declaring the flip queue wedged, check if
11373 * the hardware completed the operation behind our backs.
11374 */
11375 if (__intel_pageflip_stall_check(dev, crtc)) {
11376 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11377 page_flip_completed(intel_crtc);
11378 } else {
11379 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 11380 spin_unlock_irq(&dev->event_lock);
468f0b44 11381
d6bbafa1
CW		 11382 drm_crtc_vblank_put(crtc);
11383 kfree(work);
11384 return -EBUSY;
11385 }
6b95a207
KH		 11386 }
11387 intel_crtc->unpin_work = work;
5e2d7afc 11388 spin_unlock_irq(&dev->event_lock);
6b95a207 11389
b4a98e57
CW		 11390 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11391 flush_workqueue(dev_priv->wq);
11392
75dfca80 11393 /* Reference the objects for the scheduled work. */
ab8d6675 11394 drm_framebuffer_reference(work->old_fb);
05394f39 11395 drm_gem_object_reference(&obj->base);
6b95a207 11396
f4510a27 11397 crtc->primary->fb = fb;
afd65eb4 11398 update_state_fb(crtc->primary);
1ed1f968 11399
e1f99ce6 11400 work->pending_flip_obj = obj;
e1f99ce6 11401
89ed88ba
CW		 11402 ret = i915_mutex_lock_interruptible(dev);
11403 if (ret)
11404 goto cleanup;
11405
b4a98e57 11406 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 11407 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 11408
75f7f3ec 11409 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 11410 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 11411
4fa62c89
VS		 11412 if (IS_VALLEYVIEW(dev)) {
11413 ring = &dev_priv->ring[BCS];
ab8d6675 11414 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 11415 /* vlv: DISPLAY_FLIP fails to change tiling */
11416 ring = NULL;
48bf5b2d 11417 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 11418 ring = &dev_priv->ring[BCS];
4fa62c89 11419 } else if (INTEL_INFO(dev)->gen >= 7) {
b4716185 11420 ring = i915_gem_request_get_ring(obj->last_write_req);
4fa62c89
VS		 11421 if (ring == NULL || ring->id != RCS)
11422 ring = &dev_priv->ring[BCS];
11423 } else {
11424 ring = &dev_priv->ring[RCS];
11425 }
11426
cf5d8a46
CW		 11427 mmio_flip = use_mmio_flip(ring, obj);
11428
11429 /* When using CS flips, we want to emit semaphores between rings.
11430 * However, when using mmio flips we will create a task to do the
11431 * synchronisation, so all we want here is to pin the framebuffer
11432 * into the display plane and skip any waits.
11433 */
82bc3b2d 11434 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
cf5d8a46 11435 crtc->primary->state,
b4716185 11436 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring);
8c9f3aaf
JB		 11437 if (ret)
11438 goto cleanup_pending;
6b95a207 11439
121920fa
TU		 11440 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11441 + intel_crtc->dspaddr_offset;
4fa62c89 11442
cf5d8a46 11443 if (mmio_flip) {
84c33a64
SG		 11444 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11445 page_flip_flags);
d6bbafa1
CW		 11446 if (ret)
11447 goto cleanup_unpin;
11448
f06cc1b9
JH		 11449 i915_gem_request_assign(&work->flip_queued_req,
11450 obj->last_write_req);
d6bbafa1 11451 } else {
d94b5030
CW		 11452 if (obj->last_write_req) {
11453 ret = i915_gem_check_olr(obj->last_write_req);
11454 if (ret)
11455 goto cleanup_unpin;
11456 }
11457
84c33a64 11458 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
d6bbafa1
CW		 11459 page_flip_flags);
11460 if (ret)
11461 goto cleanup_unpin;
11462
f06cc1b9
JH		 11463 i915_gem_request_assign(&work->flip_queued_req,
11464 intel_ring_get_request(ring));
d6bbafa1
CW		 11465 }
11466
1e3feefd 11467 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 11468 work->enable_stall_check = true;
4fa62c89 11469
ab8d6675 11470 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a071fa00
DV		 11471 INTEL_FRONTBUFFER_PRIMARY(pipe));
11472
7ff0ebcc 11473 intel_fbc_disable(dev);
f99d7069 11474 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
6b95a207
KH		 11475 mutex_unlock(&dev->struct_mutex);
11476
e5510fac
JB		 11477 trace_i915_flip_request(intel_crtc->plane, obj);
11478
6b95a207 11479 return 0;
96b099fd 11480
4fa62c89 11481cleanup_unpin:
82bc3b2d 11482 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 11483cleanup_pending:
b4a98e57 11484 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 11485 mutex_unlock(&dev->struct_mutex);
11486cleanup:
f4510a27 11487 crtc->primary->fb = old_fb;
afd65eb4 11488 update_state_fb(crtc->primary);
89ed88ba
CW		 11489
11490 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 11491 drm_framebuffer_unreference(work->old_fb);
96b099fd 11492
5e2d7afc 11493 spin_lock_irq(&dev->event_lock);
96b099fd 11494 intel_crtc->unpin_work = NULL;
5e2d7afc 11495 spin_unlock_irq(&dev->event_lock);
96b099fd 11496
87b6b101 11497 drm_crtc_vblank_put(crtc);
7317c75e 11498free_work:
96b099fd
CW		 11499 kfree(work);
11500
f900db47
CW		 11501 if (ret == -EIO) {
11502out_hang:
53a366b9 11503 ret = intel_plane_restore(primary);
f0d3dad3 11504 if (ret == 0 && event) {
5e2d7afc 11505 spin_lock_irq(&dev->event_lock);
a071fa00 11506 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 11507 spin_unlock_irq(&dev->event_lock);
f0d3dad3 11508 }
f900db47 11509 }
96b099fd 11510 return ret;
6b95a207
KH		 11511}
11512
65b38e0d 11513static const struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 11514 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11515 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 11516 .atomic_begin = intel_begin_crtc_commit,
11517 .atomic_flush = intel_finish_crtc_commit,
f6e5b160
CW		 11518};
11519
9a935856
DV		 11520/**
11521 * intel_modeset_update_staged_output_state
11522 *
11523 * Updates the staged output configuration state, e.g. after we've read out the
11524 * current hw state.
11525 */
11526static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 11527{
7668851f 11528 struct intel_crtc *crtc;
9a935856
DV		 11529 struct intel_encoder *encoder;
11530 struct intel_connector *connector;
f6e5b160 11531
3a3371ff 11532 for_each_intel_connector(dev, connector) {
9a935856
DV		 11533 connector->new_encoder =
11534 to_intel_encoder(connector->base.encoder);
11535 }
f6e5b160 11536
b2784e15 11537 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 11538 encoder->new_crtc =
11539 to_intel_crtc(encoder->base.crtc);
11540 }
7668851f 11541
d3fcc808 11542 for_each_intel_crtc(dev, crtc) {
83d65738 11543 crtc->new_enabled = crtc->base.state->enable;
7668851f 11544 }
f6e5b160
CW		 11545}
11546
d29b2f9d
ACO		 11547/* Transitional helper to copy current connector/encoder state to
11548 * connector->state. This is needed so that code that is partially
11549 * converted to atomic does the right thing.
11550 */
11551static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11552{
11553 struct intel_connector *connector;
11554
11555 for_each_intel_connector(dev, connector) {
11556 if (connector->base.encoder) {
11557 connector->base.state->best_encoder =
11558 connector->base.encoder;
11559 connector->base.state->crtc =
11560 connector->base.encoder->crtc;
11561 } else {
11562 connector->base.state->best_encoder = NULL;
11563 connector->base.state->crtc = NULL;
11564 }
11565 }
11566}
11567
a821fc46 11568/* Fixup legacy state after an atomic state swap.
9a935856 11569 */
a821fc46 11570static void intel_modeset_fixup_state(struct drm_atomic_state *state)
9a935856 11571{
a821fc46 11572 struct intel_crtc *crtc;
9a935856 11573 struct intel_encoder *encoder;
a821fc46 11574 struct intel_connector *connector;
d5432a9d 11575
a821fc46
ACO		 11576 for_each_intel_connector(state->dev, connector) {
11577 connector->base.encoder = connector->base.state->best_encoder;
11578 if (connector->base.encoder)
11579 connector->base.encoder->crtc =
11580 connector->base.state->crtc;
9a935856 11581 }
f6e5b160 11582
d5432a9d
ACO		 11583 /* Update crtc of disabled encoders */
11584 for_each_intel_encoder(state->dev, encoder) {
11585 int num_connectors = 0;
11586
a821fc46
ACO		 11587 for_each_intel_connector(state->dev, connector)
11588 if (connector->base.encoder == &encoder->base)
d5432a9d
ACO		 11589 num_connectors++;
11590
11591 if (num_connectors == 0)
11592 encoder->base.crtc = NULL;
9a935856 11593 }
7668851f 11594
a821fc46
ACO		 11595 for_each_intel_crtc(state->dev, crtc) {
11596 crtc->base.enabled = crtc->base.state->enable;
11597 crtc->config = to_intel_crtc_state(crtc->base.state);
7668851f 11598 }
d29b2f9d 11599
d5432a9d
ACO		 11600 /* Copy the new configuration to the staged state, to keep the few
11601 * pieces of code that haven't been converted yet happy */
11602 intel_modeset_update_staged_output_state(state->dev);
9a935856
DV		 11603}
11604
050f7aeb 11605static void
eba905b2 11606connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 11607 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 11608{
11609 int bpp = pipe_config->pipe_bpp;
11610
11611 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11612 connector->base.base.id,
c23cc417 11613 connector->base.name);
050f7aeb
DV		 11614
11615 /* Don't use an invalid EDID bpc value */
11616 if (connector->base.display_info.bpc &&
11617 connector->base.display_info.bpc * 3 < bpp) {
11618 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11619 bpp, connector->base.display_info.bpc*3);
11620 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11621 }
11622
11623 /* Clamp bpp to 8 on screens without EDID 1.4 */
11624 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11625 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11626 bpp);
11627 pipe_config->pipe_bpp = 24;
11628 }
11629}
11630
4e53c2e0 11631static int
050f7aeb 11632compute_baseline_pipe_bpp(struct intel_crtc *crtc,
5cec258b 11633 struct intel_crtc_state *pipe_config)
4e53c2e0 11634{
050f7aeb 11635 struct drm_device *dev = crtc->base.dev;
1486017f 11636 struct drm_atomic_state *state;
da3ced29
ACO		 11637 struct drm_connector *connector;
11638 struct drm_connector_state *connector_state;
1486017f 11639 int bpp, i;
4e53c2e0 11640
d328c9d7 11641 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
4e53c2e0 11642 bpp = 10*3;
d328c9d7
DV		 11643 else if (INTEL_INFO(dev)->gen >= 5)
11644 bpp = 12*3;
11645 else
11646 bpp = 8*3;
11647
4e53c2e0 11648
4e53c2e0
DV		 11649 pipe_config->pipe_bpp = bpp;
11650
1486017f
ACO		 11651 state = pipe_config->base.state;
11652
4e53c2e0 11653 /* Clamp display bpp to EDID value */
da3ced29
ACO		 11654 for_each_connector_in_state(state, connector, connector_state, i) {
11655 if (connector_state->crtc != &crtc->base)
4e53c2e0
DV		 11656 continue;
11657
da3ced29
ACO		 11658 connected_sink_compute_bpp(to_intel_connector(connector),
11659 pipe_config);
4e53c2e0
DV		 11660 }
11661
11662 return bpp;
11663}
11664
644db711
DV		 11665static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11666{
11667 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11668 "type: 0x%x flags: 0x%x\n",
1342830c 11669 mode->crtc_clock,
644db711
DV		 11670 mode->crtc_hdisplay, mode->crtc_hsync_start,
11671 mode->crtc_hsync_end, mode->crtc_htotal,
11672 mode->crtc_vdisplay, mode->crtc_vsync_start,
11673 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11674}
11675
c0b03411 11676static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 11677 struct intel_crtc_state *pipe_config,
c0b03411
DV		 11678 const char *context)
11679{
6a60cd87
CK		 11680 struct drm_device *dev = crtc->base.dev;
11681 struct drm_plane *plane;
11682 struct intel_plane *intel_plane;
11683 struct intel_plane_state *state;
11684 struct drm_framebuffer *fb;
11685
11686 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11687 context, pipe_config, pipe_name(crtc->pipe));
c0b03411
DV		 11688
11689 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11690 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11691 pipe_config->pipe_bpp, pipe_config->dither);
11692 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11693 pipe_config->has_pch_encoder,
11694 pipe_config->fdi_lanes,
11695 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11696 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11697 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 11698 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11699 pipe_config->has_dp_encoder,
11700 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11701 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11702 pipe_config->dp_m_n.tu);
b95af8be
VK		 11703
11704 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11705 pipe_config->has_dp_encoder,
11706 pipe_config->dp_m2_n2.gmch_m,
11707 pipe_config->dp_m2_n2.gmch_n,
11708 pipe_config->dp_m2_n2.link_m,
11709 pipe_config->dp_m2_n2.link_n,
11710 pipe_config->dp_m2_n2.tu);
11711
55072d19
DV		 11712 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11713 pipe_config->has_audio,
11714 pipe_config->has_infoframe);
11715
c0b03411 11716 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 11717 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 11718 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 11719 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11720 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 11721 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 11722 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11723 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
0ec463d3
TU		 11724 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11725 crtc->num_scalers,
11726 pipe_config->scaler_state.scaler_users,
11727 pipe_config->scaler_state.scaler_id);
c0b03411
DV		 11728 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11729 pipe_config->gmch_pfit.control,
11730 pipe_config->gmch_pfit.pgm_ratios,
11731 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 11732 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 11733 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 11734 pipe_config->pch_pfit.size,
11735 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 11736 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 11737 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87 11738
415ff0f6
TU		 11739 if (IS_BROXTON(dev)) {
11740 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, "
11741 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11742 "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n",
11743 pipe_config->ddi_pll_sel,
11744 pipe_config->dpll_hw_state.ebb0,
11745 pipe_config->dpll_hw_state.pll0,
11746 pipe_config->dpll_hw_state.pll1,
11747 pipe_config->dpll_hw_state.pll2,
11748 pipe_config->dpll_hw_state.pll3,
11749 pipe_config->dpll_hw_state.pll6,
11750 pipe_config->dpll_hw_state.pll8,
11751 pipe_config->dpll_hw_state.pcsdw12);
11752 } else if (IS_SKYLAKE(dev)) {
11753 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11754 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11755 pipe_config->ddi_pll_sel,
11756 pipe_config->dpll_hw_state.ctrl1,
11757 pipe_config->dpll_hw_state.cfgcr1,
11758 pipe_config->dpll_hw_state.cfgcr2);
11759 } else if (HAS_DDI(dev)) {
11760 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11761 pipe_config->ddi_pll_sel,
11762 pipe_config->dpll_hw_state.wrpll);
11763 } else {
11764 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11765 "fp0: 0x%x, fp1: 0x%x\n",
11766 pipe_config->dpll_hw_state.dpll,
11767 pipe_config->dpll_hw_state.dpll_md,
11768 pipe_config->dpll_hw_state.fp0,
11769 pipe_config->dpll_hw_state.fp1);
11770 }
11771
6a60cd87
CK		 11772 DRM_DEBUG_KMS("planes on this crtc\n");
11773 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11774 intel_plane = to_intel_plane(plane);
11775 if (intel_plane->pipe != crtc->pipe)
11776 continue;
11777
11778 state = to_intel_plane_state(plane->state);
11779 fb = state->base.fb;
11780 if (!fb) {
11781 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11782 "disabled, scaler_id = %d\n",
11783 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11784 plane->base.id, intel_plane->pipe,
11785 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11786 drm_plane_index(plane), state->scaler_id);
11787 continue;
11788 }
11789
11790 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11791 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11792 plane->base.id, intel_plane->pipe,
11793 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11794 drm_plane_index(plane));
11795 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11796 fb->base.id, fb->width, fb->height, fb->pixel_format);
11797 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11798 state->scaler_id,
11799 state->src.x1 >> 16, state->src.y1 >> 16,
11800 drm_rect_width(&state->src) >> 16,
11801 drm_rect_height(&state->src) >> 16,
11802 state->dst.x1, state->dst.y1,
11803 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11804 }
c0b03411
DV		 11805}
11806
bc079e8b
VS		 11807static bool encoders_cloneable(const struct intel_encoder *a,
11808 const struct intel_encoder *b)
accfc0c5 11809{
bc079e8b
VS		 11810 /* masks could be asymmetric, so check both ways */
11811 return a == b || (a->cloneable & (1 << b->type) &&
11812 b->cloneable & (1 << a->type));
11813}
11814
98a221da
ACO		 11815static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11816 struct intel_crtc *crtc,
bc079e8b
VS		 11817 struct intel_encoder *encoder)
11818{
bc079e8b 11819 struct intel_encoder *source_encoder;
da3ced29 11820 struct drm_connector *connector;
98a221da
ACO		 11821 struct drm_connector_state *connector_state;
11822 int i;
bc079e8b 11823
da3ced29 11824 for_each_connector_in_state(state, connector, connector_state, i) {
98a221da 11825 if (connector_state->crtc != &crtc->base)
bc079e8b
VS		 11826 continue;
11827
98a221da
ACO		 11828 source_encoder =
11829 to_intel_encoder(connector_state->best_encoder);
bc079e8b
VS		 11830 if (!encoders_cloneable(encoder, source_encoder))
11831 return false;
11832 }
11833
11834 return true;
11835}
11836
98a221da
ACO		 11837static bool check_encoder_cloning(struct drm_atomic_state *state,
11838 struct intel_crtc *crtc)
bc079e8b 11839{
accfc0c5 11840 struct intel_encoder *encoder;
da3ced29 11841 struct drm_connector *connector;
98a221da
ACO		 11842 struct drm_connector_state *connector_state;
11843 int i;
accfc0c5 11844
da3ced29 11845 for_each_connector_in_state(state, connector, connector_state, i) {
98a221da
ACO		 11846 if (connector_state->crtc != &crtc->base)
11847 continue;
11848
11849 encoder = to_intel_encoder(connector_state->best_encoder);
11850 if (!check_single_encoder_cloning(state, crtc, encoder))
bc079e8b 11851 return false;
accfc0c5
DV		 11852 }
11853
bc079e8b 11854 return true;
accfc0c5
DV		 11855}
11856
5448a00d 11857static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 11858{
5448a00d
ACO		 11859 struct drm_device *dev = state->dev;
11860 struct intel_encoder *encoder;
da3ced29 11861 struct drm_connector *connector;
5448a00d 11862 struct drm_connector_state *connector_state;
00f0b378 11863 unsigned int used_ports = 0;
5448a00d 11864 int i;
00f0b378
VS		 11865
11866 /*
11867 * Walk the connector list instead of the encoder
11868 * list to detect the problem on ddi platforms
11869 * where there's just one encoder per digital port.
11870 */
da3ced29 11871 for_each_connector_in_state(state, connector, connector_state, i) {
5448a00d 11872 if (!connector_state->best_encoder)
00f0b378
VS		 11873 continue;
11874
5448a00d
ACO		 11875 encoder = to_intel_encoder(connector_state->best_encoder);
11876
11877 WARN_ON(!connector_state->crtc);
00f0b378
VS		 11878
11879 switch (encoder->type) {
11880 unsigned int port_mask;
11881 case INTEL_OUTPUT_UNKNOWN:
11882 if (WARN_ON(!HAS_DDI(dev)))
11883 break;
11884 case INTEL_OUTPUT_DISPLAYPORT:
11885 case INTEL_OUTPUT_HDMI:
11886 case INTEL_OUTPUT_EDP:
11887 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11888
11889 /* the same port mustn't appear more than once */
11890 if (used_ports & port_mask)
11891 return false;
11892
11893 used_ports |= port_mask;
11894 default:
11895 break;
11896 }
11897 }
11898
11899 return true;
11900}
11901
83a57153
ACO		 11902static void
11903clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11904{
11905 struct drm_crtc_state tmp_state;
663a3640 11906 struct intel_crtc_scaler_state scaler_state;
4978cc93
ACO		 11907 struct intel_dpll_hw_state dpll_hw_state;
11908 enum intel_dpll_id shared_dpll;
8504c74c 11909 uint32_t ddi_pll_sel;
83a57153 11910
7546a384
ACO		 11911 /* FIXME: before the switch to atomic started, a new pipe_config was
11912 * kzalloc'd. Code that depends on any field being zero should be
11913 * fixed, so that the crtc_state can be safely duplicated. For now,
11914 * only fields that are know to not cause problems are preserved. */
11915
83a57153 11916 tmp_state = crtc_state->base;
663a3640 11917 scaler_state = crtc_state->scaler_state;
4978cc93
ACO		 11918 shared_dpll = crtc_state->shared_dpll;
11919 dpll_hw_state = crtc_state->dpll_hw_state;
8504c74c 11920 ddi_pll_sel = crtc_state->ddi_pll_sel;
4978cc93 11921
83a57153 11922 memset(crtc_state, 0, sizeof *crtc_state);
4978cc93 11923
83a57153 11924 crtc_state->base = tmp_state;
663a3640 11925 crtc_state->scaler_state = scaler_state;
4978cc93
ACO		 11926 crtc_state->shared_dpll = shared_dpll;
11927 crtc_state->dpll_hw_state = dpll_hw_state;
8504c74c 11928 crtc_state->ddi_pll_sel = ddi_pll_sel;
83a57153
ACO		 11929}
11930
548ee15b 11931static int
b8cecdf5 11932intel_modeset_pipe_config(struct drm_crtc *crtc,
548ee15b
ACO		 11933 struct drm_atomic_state *state,
11934 struct intel_crtc_state *pipe_config)
ee7b9f93 11935{
7758a113 11936 struct intel_encoder *encoder;
da3ced29 11937 struct drm_connector *connector;
0b901879 11938 struct drm_connector_state *connector_state;
d328c9d7 11939 int base_bpp, ret = -EINVAL;
0b901879 11940 int i;
e29c22c0 11941 bool retry = true;
ee7b9f93 11942
98a221da 11943 if (!check_encoder_cloning(state, to_intel_crtc(crtc))) {
accfc0c5 11944 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
548ee15b 11945 return -EINVAL;
accfc0c5
DV		 11946 }
11947
5448a00d 11948 if (!check_digital_port_conflicts(state)) {
00f0b378 11949 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
548ee15b 11950 return -EINVAL;
00f0b378
VS		 11951 }
11952
83a57153 11953 clear_intel_crtc_state(pipe_config);
7758a113 11954
e143a21c
DV		 11955 pipe_config->cpu_transcoder =
11956 (enum transcoder) to_intel_crtc(crtc)->pipe;
b8cecdf5 11957
2960bc9c
ID		 11958 /*
11959 * Sanitize sync polarity flags based on requested ones. If neither
11960 * positive or negative polarity is requested, treat this as meaning
11961 * negative polarity.
11962 */
2d112de7 11963 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 11964 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 11965 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 11966
2d112de7 11967 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 11968 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 11969 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 11970
050f7aeb
DV		 11971 /* Compute a starting value for pipe_config->pipe_bpp taking the source
11972 * plane pixel format and any sink constraints into account. Returns the
11973 * source plane bpp so that dithering can be selected on mismatches
11974 * after encoders and crtc also have had their say. */
d328c9d7
DV		 11975 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11976 pipe_config);
11977 if (base_bpp < 0)
4e53c2e0
DV		 11978 goto fail;
11979
e41a56be
VS		 11980 /*
11981 * Determine the real pipe dimensions. Note that stereo modes can
11982 * increase the actual pipe size due to the frame doubling and
11983 * insertion of additional space for blanks between the frame. This
11984 * is stored in the crtc timings. We use the requested mode to do this
11985 * computation to clearly distinguish it from the adjusted mode, which
11986 * can be changed by the connectors in the below retry loop.
11987 */
2d112de7 11988 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 11989 &pipe_config->pipe_src_w,
11990 &pipe_config->pipe_src_h);
e41a56be 11991
e29c22c0 11992encoder_retry:
ef1b460d 11993 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 11994 pipe_config->port_clock = 0;
ef1b460d 11995 pipe_config->pixel_multiplier = 1;
ff9a6750 11996
135c81b8 11997 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 11998 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11999 CRTC_STEREO_DOUBLE);
135c81b8 12000
7758a113
DV		 12001 /* Pass our mode to the connectors and the CRTC to give them a chance to
12002 * adjust it according to limitations or connector properties, and also
12003 * a chance to reject the mode entirely.
47f1c6c9 12004 */
da3ced29 12005 for_each_connector_in_state(state, connector, connector_state, i) {
0b901879 12006 if (connector_state->crtc != crtc)
7758a113 12007 continue;
7ae89233 12008
0b901879
ACO		 12009 encoder = to_intel_encoder(connector_state->best_encoder);
12010
efea6e8e
DV		 12011 if (!(encoder->compute_config(encoder, pipe_config))) {
12012 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 12013 goto fail;
12014 }
ee7b9f93 12015 }
47f1c6c9 12016
ff9a6750
DV		 12017 /* Set default port clock if not overwritten by the encoder. Needs to be
12018 * done afterwards in case the encoder adjusts the mode. */
12019 if (!pipe_config->port_clock)
2d112de7 12020 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 12021 * pipe_config->pixel_multiplier;
ff9a6750 12022
a43f6e0f 12023 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 12024 if (ret < 0) {
7758a113
DV		 12025 DRM_DEBUG_KMS("CRTC fixup failed\n");
12026 goto fail;
ee7b9f93 12027 }
e29c22c0
DV		 12028
12029 if (ret == RETRY) {
12030 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12031 ret = -EINVAL;
12032 goto fail;
12033 }
12034
12035 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12036 retry = false;
12037 goto encoder_retry;
12038 }
12039
d328c9d7 12040 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
4e53c2e0 12041 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
d328c9d7 12042 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
4e53c2e0 12043
548ee15b 12044 return 0;
7758a113 12045fail:
548ee15b 12046 return ret;
ee7b9f93 12047}
47f1c6c9 12048
ea9d758d 12049static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 12050{
ea9d758d 12051 struct drm_encoder *encoder;
f6e5b160 12052 struct drm_device *dev = crtc->dev;
f6e5b160 12053
ea9d758d
DV		 12054 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
12055 if (encoder->crtc == crtc)
12056 return true;
12057
12058 return false;
12059}
12060
0a9ab303
ACO		 12061static bool
12062needs_modeset(struct drm_crtc_state *state)
12063{
12064 return state->mode_changed || state->active_changed;
12065}
12066
ea9d758d 12067static void
0a9ab303 12068intel_modeset_update_state(struct drm_atomic_state *state)
ea9d758d 12069{
0a9ab303 12070 struct drm_device *dev = state->dev;
ba41c0de 12071 struct drm_i915_private *dev_priv = dev->dev_private;
ea9d758d 12072 struct intel_encoder *intel_encoder;
0a9ab303
ACO		 12073 struct drm_crtc *crtc;
12074 struct drm_crtc_state *crtc_state;
ea9d758d 12075 struct drm_connector *connector;
0a9ab303 12076 int i;
ea9d758d 12077
ba41c0de
DV		 12078 intel_shared_dpll_commit(dev_priv);
12079
b2784e15 12080 for_each_intel_encoder(dev, intel_encoder) {
ea9d758d
DV		 12081 if (!intel_encoder->base.crtc)
12082 continue;
12083
bd4b4827
ACO		 12084 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12085 if (crtc != intel_encoder->base.crtc)
12086 continue;
0a9ab303 12087
bd4b4827
ACO		 12088 if (crtc_state->enable && needs_modeset(crtc_state))
12089 intel_encoder->connectors_active = false;
ea9d758d 12090
bd4b4827
ACO		 12091 break;
12092 }
ea9d758d
DV		 12093 }
12094
a821fc46
ACO		 12095 drm_atomic_helper_swap_state(state->dev, state);
12096 intel_modeset_fixup_state(state);
ea9d758d 12097
7668851f 12098 /* Double check state. */
0a9ab303
ACO		 12099 for_each_crtc(dev, crtc) {
12100 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
ea9d758d
DV		 12101 }
12102
12103 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12104 if (!connector->encoder || !connector->encoder->crtc)
12105 continue;
12106
bd4b4827
ACO		 12107 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12108 if (crtc != connector->encoder->crtc)
12109 continue;
0a9ab303 12110
bd4b4827
ACO		 12111 if (crtc->state->enable && needs_modeset(crtc->state)) {
12112 struct drm_property *dpms_property =
12113 dev->mode_config.dpms_property;
ea9d758d 12114
bd4b4827
ACO		 12115 connector->dpms = DRM_MODE_DPMS_ON;
12116 drm_object_property_set_value(&connector->base,
12117 dpms_property,
12118 DRM_MODE_DPMS_ON);
68d34720 12119
bd4b4827
ACO		 12120 intel_encoder = to_intel_encoder(connector->encoder);
12121 intel_encoder->connectors_active = true;
12122 }
ea9d758d 12123
bd4b4827 12124 break;
ea9d758d
DV		 12125 }
12126 }
12127
12128}
12129
3bd26263 12130static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 12131{
3bd26263 12132 int diff;
f1f644dc
JB		 12133
12134 if (clock1 == clock2)
12135 return true;
12136
12137 if (!clock1 || !clock2)
12138 return false;
12139
12140 diff = abs(clock1 - clock2);
12141
12142 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12143 return true;
12144
12145 return false;
12146}
12147
25c5b266
DV		 12148#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12149 list_for_each_entry((intel_crtc), \
12150 &(dev)->mode_config.crtc_list, \
12151 base.head) \
0973f18f 12152 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 12153
0e8ffe1b 12154static bool
2fa2fe9a 12155intel_pipe_config_compare(struct drm_device *dev,
5cec258b
ACO		 12156 struct intel_crtc_state *current_config,
12157 struct intel_crtc_state *pipe_config)
0e8ffe1b 12158{
66e985c0
DV		 12159#define PIPE_CONF_CHECK_X(name) \
12160 if (current_config->name != pipe_config->name) { \
12161 DRM_ERROR("mismatch in " #name " " \
12162 "(expected 0x%08x, found 0x%08x)\n", \
12163 current_config->name, \
12164 pipe_config->name); \
12165 return false; \
12166 }
12167
08a24034
DV		 12168#define PIPE_CONF_CHECK_I(name) \
12169 if (current_config->name != pipe_config->name) { \
12170 DRM_ERROR("mismatch in " #name " " \
12171 "(expected %i, found %i)\n", \
12172 current_config->name, \
12173 pipe_config->name); \
12174 return false; \
88adfff1
DV		 12175 }
12176
b95af8be
VK		 12177/* This is required for BDW+ where there is only one set of registers for
12178 * switching between high and low RR.
12179 * This macro can be used whenever a comparison has to be made between one
12180 * hw state and multiple sw state variables.
12181 */
12182#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12183 if ((current_config->name != pipe_config->name) && \
12184 (current_config->alt_name != pipe_config->name)) { \
12185 DRM_ERROR("mismatch in " #name " " \
12186 "(expected %i or %i, found %i)\n", \
12187 current_config->name, \
12188 current_config->alt_name, \
12189 pipe_config->name); \
12190 return false; \
12191 }
12192
1bd1bd80
DV		 12193#define PIPE_CONF_CHECK_FLAGS(name, mask) \
12194 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 12195 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 12196 "(expected %i, found %i)\n", \
12197 current_config->name & (mask), \
12198 pipe_config->name & (mask)); \
12199 return false; \
12200 }
12201
5e550656
VS		 12202#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12203 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12204 DRM_ERROR("mismatch in " #name " " \
12205 "(expected %i, found %i)\n", \
12206 current_config->name, \
12207 pipe_config->name); \
12208 return false; \
12209 }
12210
bb760063
DV		 12211#define PIPE_CONF_QUIRK(quirk) \
12212 ((current_config->quirks | pipe_config->quirks) & (quirk))
12213
eccb140b
DV		 12214 PIPE_CONF_CHECK_I(cpu_transcoder);
12215
08a24034
DV		 12216 PIPE_CONF_CHECK_I(has_pch_encoder);
12217 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 12218 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
12219 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
12220 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
12221 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
12222 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 12223
eb14cb74 12224 PIPE_CONF_CHECK_I(has_dp_encoder);
b95af8be
VK		 12225
12226 if (INTEL_INFO(dev)->gen < 8) {
12227 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
12228 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
12229 PIPE_CONF_CHECK_I(dp_m_n.link_m);
12230 PIPE_CONF_CHECK_I(dp_m_n.link_n);
12231 PIPE_CONF_CHECK_I(dp_m_n.tu);
12232
12233 if (current_config->has_drrs) {
12234 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
12235 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
12236 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
12237 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
12238 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
12239 }
12240 } else {
12241 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
12242 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
12243 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
12244 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
12245 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
12246 }
eb14cb74 12247
2d112de7
ACO		 12248 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12249 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12250 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12251 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12252 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12253 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 12254
2d112de7
ACO		 12255 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12256 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12257 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12258 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12259 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12260 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 12261
c93f54cf 12262 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 12263 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 12264 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12265 IS_VALLEYVIEW(dev))
12266 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 12267 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 12268
9ed109a7
DV		 12269 PIPE_CONF_CHECK_I(has_audio);
12270
2d112de7 12271 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 12272 DRM_MODE_FLAG_INTERLACE);
12273
bb760063 12274 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 12275 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12276 DRM_MODE_FLAG_PHSYNC);
2d112de7 12277 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12278 DRM_MODE_FLAG_NHSYNC);
2d112de7 12279 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12280 DRM_MODE_FLAG_PVSYNC);
2d112de7 12281 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 12282 DRM_MODE_FLAG_NVSYNC);
12283 }
045ac3b5 12284
37327abd
VS		 12285 PIPE_CONF_CHECK_I(pipe_src_w);
12286 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 12287
9953599b
DV		 12288 /*
12289 * FIXME: BIOS likes to set up a cloned config with lvds+external
12290 * screen. Since we don't yet re-compute the pipe config when moving
12291 * just the lvds port away to another pipe the sw tracking won't match.
12292 *
12293 * Proper atomic modesets with recomputed global state will fix this.
12294 * Until then just don't check gmch state for inherited modes.
12295 */
12296 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
12297 PIPE_CONF_CHECK_I(gmch_pfit.control);
12298 /* pfit ratios are autocomputed by the hw on gen4+ */
12299 if (INTEL_INFO(dev)->gen < 4)
12300 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12301 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12302 }
12303
fd4daa9c
CW		 12304 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12305 if (current_config->pch_pfit.enabled) {
12306 PIPE_CONF_CHECK_I(pch_pfit.pos);
12307 PIPE_CONF_CHECK_I(pch_pfit.size);
12308 }
2fa2fe9a 12309
a1b2278e
CK		 12310 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12311
e59150dc
JB		 12312 /* BDW+ don't expose a synchronous way to read the state */
12313 if (IS_HASWELL(dev))
12314 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 12315
282740f7
VS		 12316 PIPE_CONF_CHECK_I(double_wide);
12317
26804afd
DV		 12318 PIPE_CONF_CHECK_X(ddi_pll_sel);
12319
c0d43d62 12320 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 12321 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 12322 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 12323 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12324 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 12325 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 12326 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12327 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12328 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 12329
42571aef
VS		 12330 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12331 PIPE_CONF_CHECK_I(pipe_bpp);
12332
2d112de7 12333 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 12334 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 12335
66e985c0 12336#undef PIPE_CONF_CHECK_X
08a24034 12337#undef PIPE_CONF_CHECK_I
b95af8be 12338#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 12339#undef PIPE_CONF_CHECK_FLAGS
5e550656 12340#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 12341#undef PIPE_CONF_QUIRK
88adfff1 12342
0e8ffe1b
DV		 12343 return true;
12344}
12345
08db6652
DL		 12346static void check_wm_state(struct drm_device *dev)
12347{
12348 struct drm_i915_private *dev_priv = dev->dev_private;
12349 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12350 struct intel_crtc *intel_crtc;
12351 int plane;
12352
12353 if (INTEL_INFO(dev)->gen < 9)
12354 return;
12355
12356 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12357 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12358
12359 for_each_intel_crtc(dev, intel_crtc) {
12360 struct skl_ddb_entry *hw_entry, *sw_entry;
12361 const enum pipe pipe = intel_crtc->pipe;
12362
12363 if (!intel_crtc->active)
12364 continue;
12365
12366 /* planes */
dd740780 12367 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 12368 hw_entry = &hw_ddb.plane[pipe][plane];
12369 sw_entry = &sw_ddb->plane[pipe][plane];
12370
12371 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12372 continue;
12373
12374 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12375 "(expected (%u,%u), found (%u,%u))\n",
12376 pipe_name(pipe), plane + 1,
12377 sw_entry->start, sw_entry->end,
12378 hw_entry->start, hw_entry->end);
12379 }
12380
12381 /* cursor */
12382 hw_entry = &hw_ddb.cursor[pipe];
12383 sw_entry = &sw_ddb->cursor[pipe];
12384
12385 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12386 continue;
12387
12388 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12389 "(expected (%u,%u), found (%u,%u))\n",
12390 pipe_name(pipe),
12391 sw_entry->start, sw_entry->end,
12392 hw_entry->start, hw_entry->end);
12393 }
12394}
12395
91d1b4bd
DV		 12396static void
12397check_connector_state(struct drm_device *dev)
8af6cf88 12398{
8af6cf88
DV		 12399 struct intel_connector *connector;
12400
3a3371ff 12401 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 12402 /* This also checks the encoder/connector hw state with the
12403 * ->get_hw_state callbacks. */
12404 intel_connector_check_state(connector);
12405
e2c719b7 12406 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
8af6cf88
DV		 12407 "connector's staged encoder doesn't match current encoder\n");
12408 }
91d1b4bd
DV		 12409}
12410
12411static void
12412check_encoder_state(struct drm_device *dev)
12413{
12414 struct intel_encoder *encoder;
12415 struct intel_connector *connector;
8af6cf88 12416
b2784e15 12417 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 12418 bool enabled = false;
12419 bool active = false;
12420 enum pipe pipe, tracked_pipe;
12421
12422 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12423 encoder->base.base.id,
8e329a03 12424 encoder->base.name);
8af6cf88 12425
e2c719b7 12426 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
8af6cf88 12427 "encoder's stage crtc doesn't match current crtc\n");
e2c719b7 12428 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
8af6cf88
DV		 12429 "encoder's active_connectors set, but no crtc\n");
12430
3a3371ff 12431 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 12432 if (connector->base.encoder != &encoder->base)
12433 continue;
12434 enabled = true;
12435 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12436 active = true;
12437 }
0e32b39c
DA		 12438 /*
12439 * for MST connectors if we unplug the connector is gone
12440 * away but the encoder is still connected to a crtc
12441 * until a modeset happens in response to the hotplug.
12442 */
12443 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12444 continue;
12445
e2c719b7 12446 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 12447 "encoder's enabled state mismatch "
12448 "(expected %i, found %i)\n",
12449 !!encoder->base.crtc, enabled);
e2c719b7 12450 I915_STATE_WARN(active && !encoder->base.crtc,
8af6cf88
DV		 12451 "active encoder with no crtc\n");
12452
e2c719b7 12453 I915_STATE_WARN(encoder->connectors_active != active,
8af6cf88
DV		 12454 "encoder's computed active state doesn't match tracked active state "
12455 "(expected %i, found %i)\n", active, encoder->connectors_active);
12456
12457 active = encoder->get_hw_state(encoder, &pipe);
e2c719b7 12458 I915_STATE_WARN(active != encoder->connectors_active,
8af6cf88
DV		 12459 "encoder's hw state doesn't match sw tracking "
12460 "(expected %i, found %i)\n",
12461 encoder->connectors_active, active);
12462
12463 if (!encoder->base.crtc)
12464 continue;
12465
12466 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
e2c719b7 12467 I915_STATE_WARN(active && pipe != tracked_pipe,
8af6cf88
DV		 12468 "active encoder's pipe doesn't match"
12469 "(expected %i, found %i)\n",
12470 tracked_pipe, pipe);
12471
12472 }
91d1b4bd
DV		 12473}
12474
12475static void
12476check_crtc_state(struct drm_device *dev)
12477{
fbee40df 12478 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12479 struct intel_crtc *crtc;
12480 struct intel_encoder *encoder;
5cec258b 12481 struct intel_crtc_state pipe_config;
8af6cf88 12482
d3fcc808 12483 for_each_intel_crtc(dev, crtc) {
8af6cf88
DV		 12484 bool enabled = false;
12485 bool active = false;
12486
045ac3b5
JB		 12487 memset(&pipe_config, 0, sizeof(pipe_config));
12488
8af6cf88
DV		 12489 DRM_DEBUG_KMS("[CRTC:%d]\n",
12490 crtc->base.base.id);
12491
83d65738 12492 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
8af6cf88
DV		 12493 "active crtc, but not enabled in sw tracking\n");
12494
b2784e15 12495 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 12496 if (encoder->base.crtc != &crtc->base)
12497 continue;
12498 enabled = true;
12499 if (encoder->connectors_active)
12500 active = true;
12501 }
6c49f241 12502
e2c719b7 12503 I915_STATE_WARN(active != crtc->active,
8af6cf88
DV		 12504 "crtc's computed active state doesn't match tracked active state "
12505 "(expected %i, found %i)\n", active, crtc->active);
83d65738 12506 I915_STATE_WARN(enabled != crtc->base.state->enable,
8af6cf88 12507 "crtc's computed enabled state doesn't match tracked enabled state "
83d65738
MR		 12508 "(expected %i, found %i)\n", enabled,
12509 crtc->base.state->enable);
8af6cf88 12510
0e8ffe1b
DV		 12511 active = dev_priv->display.get_pipe_config(crtc,
12512 &pipe_config);
d62cf62a 12513
b6b5d049
VS		 12514 /* hw state is inconsistent with the pipe quirk */
12515 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12516 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
d62cf62a
DV		 12517 active = crtc->active;
12518
b2784e15 12519 for_each_intel_encoder(dev, encoder) {
3eaba51c 12520 enum pipe pipe;
6c49f241
DV		 12521 if (encoder->base.crtc != &crtc->base)
12522 continue;
1d37b689 12523 if (encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 12524 encoder->get_config(encoder, &pipe_config);
12525 }
12526
e2c719b7 12527 I915_STATE_WARN(crtc->active != active,
0e8ffe1b
DV		 12528 "crtc active state doesn't match with hw state "
12529 "(expected %i, found %i)\n", crtc->active, active);
12530
c0b03411 12531 if (active &&
6e3c9717 12532 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
e2c719b7 12533 I915_STATE_WARN(1, "pipe state doesn't match!\n");
c0b03411
DV		 12534 intel_dump_pipe_config(crtc, &pipe_config,
12535 "[hw state]");
6e3c9717 12536 intel_dump_pipe_config(crtc, crtc->config,
c0b03411
DV		 12537 "[sw state]");
12538 }
8af6cf88
DV		 12539 }
12540}
12541
91d1b4bd
DV		 12542static void
12543check_shared_dpll_state(struct drm_device *dev)
12544{
fbee40df 12545 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12546 struct intel_crtc *crtc;
12547 struct intel_dpll_hw_state dpll_hw_state;
12548 int i;
5358901f
DV		 12549
12550 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12551 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12552 int enabled_crtcs = 0, active_crtcs = 0;
12553 bool active;
12554
12555 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12556
12557 DRM_DEBUG_KMS("%s\n", pll->name);
12558
12559 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12560
e2c719b7 12561 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 12562 "more active pll users than references: %i vs %i\n",
3e369b76 12563 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 12564 I915_STATE_WARN(pll->active && !pll->on,
5358901f 12565 "pll in active use but not on in sw tracking\n");
e2c719b7 12566 I915_STATE_WARN(pll->on && !pll->active,
35c95375 12567 "pll in on but not on in use in sw tracking\n");
e2c719b7 12568 I915_STATE_WARN(pll->on != active,
5358901f
DV		 12569 "pll on state mismatch (expected %i, found %i)\n",
12570 pll->on, active);
12571
d3fcc808 12572 for_each_intel_crtc(dev, crtc) {
83d65738 12573 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 12574 enabled_crtcs++;
12575 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12576 active_crtcs++;
12577 }
e2c719b7 12578 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 12579 "pll active crtcs mismatch (expected %i, found %i)\n",
12580 pll->active, active_crtcs);
e2c719b7 12581 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 12582 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 12583 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 12584
e2c719b7 12585 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 12586 sizeof(dpll_hw_state)),
12587 "pll hw state mismatch\n");
5358901f 12588 }
8af6cf88
DV		 12589}
12590
91d1b4bd
DV		 12591void
12592intel_modeset_check_state(struct drm_device *dev)
12593{
08db6652 12594 check_wm_state(dev);
91d1b4bd
DV		 12595 check_connector_state(dev);
12596 check_encoder_state(dev);
12597 check_crtc_state(dev);
12598 check_shared_dpll_state(dev);
12599}
12600
5cec258b 12601void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 12602 int dotclock)
12603{
12604 /*
12605 * FDI already provided one idea for the dotclock.
12606 * Yell if the encoder disagrees.
12607 */
2d112de7 12608 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 12609 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 12610 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 12611}
12612
80715b2f
VS		 12613static void update_scanline_offset(struct intel_crtc *crtc)
12614{
12615 struct drm_device *dev = crtc->base.dev;
12616
12617 /*
12618 * The scanline counter increments at the leading edge of hsync.
12619 *
12620 * On most platforms it starts counting from vtotal-1 on the
12621 * first active line. That means the scanline counter value is
12622 * always one less than what we would expect. Ie. just after
12623 * start of vblank, which also occurs at start of hsync (on the
12624 * last active line), the scanline counter will read vblank_start-1.
12625 *
12626 * On gen2 the scanline counter starts counting from 1 instead
12627 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12628 * to keep the value positive), instead of adding one.
12629 *
12630 * On HSW+ the behaviour of the scanline counter depends on the output
12631 * type. For DP ports it behaves like most other platforms, but on HDMI
12632 * there's an extra 1 line difference. So we need to add two instead of
12633 * one to the value.
12634 */
12635 if (IS_GEN2(dev)) {
6e3c9717 12636 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 12637 int vtotal;
12638
12639 vtotal = mode->crtc_vtotal;
12640 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12641 vtotal /= 2;
12642
12643 crtc->scanline_offset = vtotal - 1;
12644 } else if (HAS_DDI(dev) &&
409ee761 12645 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 12646 crtc->scanline_offset = 2;
12647 } else
12648 crtc->scanline_offset = 1;
12649}
12650
5cec258b 12651static struct intel_crtc_state *
7f27126e 12652intel_modeset_compute_config(struct drm_crtc *crtc,
0a9ab303 12653 struct drm_atomic_state *state)
7f27126e 12654{
548ee15b 12655 struct intel_crtc_state *pipe_config;
0b901879
ACO		 12656 int ret = 0;
12657
12658 ret = drm_atomic_add_affected_connectors(state, crtc);
12659 if (ret)
12660 return ERR_PTR(ret);
7f27126e 12661
8c7b5ccb
ACO		 12662 ret = drm_atomic_helper_check_modeset(state->dev, state);
12663 if (ret)
12664 return ERR_PTR(ret);
7f27126e 12665
7f27126e
JB		 12666 /*
12667 * Note this needs changes when we start tracking multiple modes
12668 * and crtcs. At that point we'll need to compute the whole config
12669 * (i.e. one pipe_config for each crtc) rather than just the one
12670 * for this crtc.
12671 */
548ee15b
ACO		 12672 pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
12673 if (IS_ERR(pipe_config))
12674 return pipe_config;
83a57153 12675
4fed33f6 12676 if (!pipe_config->base.enable)
548ee15b 12677 return pipe_config;
7f27126e 12678
8c7b5ccb 12679 ret = intel_modeset_pipe_config(crtc, state, pipe_config);
548ee15b
ACO		 12680 if (ret)
12681 return ERR_PTR(ret);
12682
8d8c9b51
ACO		 12683 /* Check things that can only be changed through modeset */
12684 if (pipe_config->has_audio !=
12685 to_intel_crtc(crtc)->config->has_audio)
12686 pipe_config->base.mode_changed = true;
12687
12688 /*
12689 * Note we have an issue here with infoframes: current code
12690 * only updates them on the full mode set path per hw
12691 * requirements. So here we should be checking for any
12692 * required changes and forcing a mode set.
12693 */
12694
548ee15b 12695 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,"[modeset]");
db7542dd 12696
8c7b5ccb
ACO		 12697 ret = drm_atomic_helper_check_planes(state->dev, state);
12698 if (ret)
12699 return ERR_PTR(ret);
12700
548ee15b 12701 return pipe_config;
7f27126e
JB		 12702}
12703
0a9ab303 12704static int __intel_set_mode_setup_plls(struct drm_atomic_state *state)
ed6739ef 12705{
225da59b 12706 struct drm_device *dev = state->dev;
ed6739ef 12707 struct drm_i915_private *dev_priv = to_i915(dev);
0a9ab303 12708 unsigned clear_pipes = 0;
ed6739ef 12709 struct intel_crtc *intel_crtc;
0a9ab303
ACO		 12710 struct intel_crtc_state *intel_crtc_state;
12711 struct drm_crtc *crtc;
12712 struct drm_crtc_state *crtc_state;
ed6739ef 12713 int ret = 0;
0a9ab303 12714 int i;
ed6739ef
ACO		 12715
12716 if (!dev_priv->display.crtc_compute_clock)
12717 return 0;
12718
0a9ab303
ACO		 12719 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12720 intel_crtc = to_intel_crtc(crtc);
4978cc93 12721 intel_crtc_state = to_intel_crtc_state(crtc_state);
0a9ab303 12722
4978cc93 12723 if (needs_modeset(crtc_state)) {
0a9ab303 12724 clear_pipes |= 1 << intel_crtc->pipe;
4978cc93 12725 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
4978cc93 12726 }
0a9ab303
ACO		 12727 }
12728
ed6739ef
ACO		 12729 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
12730 if (ret)
12731 goto done;
12732
0a9ab303
ACO		 12733 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12734 if (!needs_modeset(crtc_state) || !crtc_state->enable)
225da59b
ACO		 12735 continue;
12736
0a9ab303
ACO		 12737 intel_crtc = to_intel_crtc(crtc);
12738 intel_crtc_state = to_intel_crtc_state(crtc_state);
12739
ed6739ef 12740 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
0a9ab303 12741 intel_crtc_state);
ed6739ef
ACO		 12742 if (ret) {
12743 intel_shared_dpll_abort_config(dev_priv);
12744 goto done;
12745 }
12746 }
12747
12748done:
12749 return ret;
12750}
12751
054518dd
ACO		 12752/* Code that should eventually be part of atomic_check() */
12753static int __intel_set_mode_checks(struct drm_atomic_state *state)
12754{
12755 struct drm_device *dev = state->dev;
12756 int ret;
12757
12758 /*
12759 * See if the config requires any additional preparation, e.g.
12760 * to adjust global state with pipes off. We need to do this
12761 * here so we can get the modeset_pipe updated config for the new
12762 * mode set on this crtc. For other crtcs we need to use the
12763 * adjusted_mode bits in the crtc directly.
12764 */
12765 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
12766 ret = valleyview_modeset_global_pipes(state);
12767 if (ret)
12768 return ret;
12769 }
12770
12771 ret = __intel_set_mode_setup_plls(state);
12772 if (ret)
12773 return ret;
12774
12775 return 0;
12776}
12777
0a9ab303 12778static int __intel_set_mode(struct drm_crtc *modeset_crtc,
0a9ab303 12779 struct intel_crtc_state *pipe_config)
a6778b3c 12780{
0a9ab303 12781 struct drm_device *dev = modeset_crtc->dev;
fbee40df 12782 struct drm_i915_private *dev_priv = dev->dev_private;
304603f4 12783 struct drm_atomic_state *state = pipe_config->base.state;
0a9ab303
ACO		 12784 struct drm_crtc *crtc;
12785 struct drm_crtc_state *crtc_state;
c0c36b94 12786 int ret = 0;
0a9ab303 12787 int i;
a6778b3c 12788
054518dd
ACO		 12789 ret = __intel_set_mode_checks(state);
12790 if (ret < 0)
12791 return ret;
12792
d4afb8cc
ACO		 12793 ret = drm_atomic_helper_prepare_planes(dev, state);
12794 if (ret)
12795 return ret;
12796
0a9ab303
ACO		 12797 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12798 if (!needs_modeset(crtc_state))
12799 continue;
460da916 12800
0a9ab303
ACO		 12801 if (!crtc_state->enable) {
12802 intel_crtc_disable(crtc);
12803 } else if (crtc->state->enable) {
12804 intel_crtc_disable_planes(crtc);
12805 dev_priv->display.crtc_disable(crtc);
ce22dba9 12806 }
ea9d758d 12807 }
a6778b3c 12808
6c4c86f5
DV		 12809 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
12810 * to set it here already despite that we pass it down the callchain.
7f27126e
JB		 12811 *
12812 * Note we'll need to fix this up when we start tracking multiple
12813 * pipes; here we assume a single modeset_pipe and only track the
12814 * single crtc and mode.
f6e5b160 12815 */
0a9ab303 12816 if (pipe_config->base.enable && needs_modeset(&pipe_config->base)) {
8c7b5ccb 12817 modeset_crtc->mode = pipe_config->base.mode;
c326c0a9
VS		 12818
12819 /*
12820 * Calculate and store various constants which
12821 * are later needed by vblank and swap-completion
12822 * timestamping. They are derived from true hwmode.
12823 */
0a9ab303 12824 drm_calc_timestamping_constants(modeset_crtc,
2d112de7 12825 &pipe_config->base.adjusted_mode);
b8cecdf5 12826 }
7758a113 12827
ea9d758d
DV		 12828 /* Only after disabling all output pipelines that will be changed can we
12829 * update the the output configuration. */
0a9ab303 12830 intel_modeset_update_state(state);
f6e5b160 12831
a821fc46
ACO		 12832 /* The state has been swaped above, so state actually contains the
12833 * old state now. */
12834
304603f4 12835 modeset_update_crtc_power_domains(state);
47fab737 12836
d4afb8cc 12837 drm_atomic_helper_commit_planes(dev, state);
a6778b3c
DV		 12838
12839 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
0a9ab303 12840 for_each_crtc_in_state(state, crtc, crtc_state, i) {
a821fc46 12841 if (!needs_modeset(crtc->state) || !crtc->state->enable)
0a9ab303
ACO		 12842 continue;
12843
12844 update_scanline_offset(to_intel_crtc(crtc));
80715b2f 12845
0a9ab303
ACO		 12846 dev_priv->display.crtc_enable(crtc);
12847 intel_crtc_enable_planes(crtc);
80715b2f 12848 }
a6778b3c 12849
a6778b3c 12850 /* FIXME: add subpixel order */
83a57153 12851
d4afb8cc
ACO		 12852 drm_atomic_helper_cleanup_planes(dev, state);
12853
2bfb4627
ACO		 12854 drm_atomic_state_free(state);
12855
9eb45f22 12856 return 0;
f6e5b160
CW		 12857}
12858
0a9ab303 12859static int intel_set_mode_with_config(struct drm_crtc *crtc,
0a9ab303 12860 struct intel_crtc_state *pipe_config)
f30da187
DV		 12861{
12862 int ret;
12863
8c7b5ccb 12864 ret = __intel_set_mode(crtc, pipe_config);
f30da187
DV		 12865
12866 if (ret == 0)
12867 intel_modeset_check_state(crtc->dev);
12868
12869 return ret;
12870}
12871
7f27126e 12872static int intel_set_mode(struct drm_crtc *crtc,
83a57153 12873 struct drm_atomic_state *state)
7f27126e 12874{
5cec258b 12875 struct intel_crtc_state *pipe_config;
83a57153 12876 int ret = 0;
7f27126e 12877
8c7b5ccb 12878 pipe_config = intel_modeset_compute_config(crtc, state);
83a57153
ACO		 12879 if (IS_ERR(pipe_config)) {
12880 ret = PTR_ERR(pipe_config);
12881 goto out;
12882 }
12883
8c7b5ccb 12884 ret = intel_set_mode_with_config(crtc, pipe_config);
83a57153
ACO		 12885 if (ret)
12886 goto out;
7f27126e 12887
83a57153
ACO		 12888out:
12889 return ret;
7f27126e
JB		 12890}
12891
c0c36b94
CW		 12892void intel_crtc_restore_mode(struct drm_crtc *crtc)
12893{
83a57153
ACO		 12894 struct drm_device *dev = crtc->dev;
12895 struct drm_atomic_state *state;
4be07317 12896 struct intel_crtc *intel_crtc;
83a57153
ACO		 12897 struct intel_encoder *encoder;
12898 struct intel_connector *connector;
12899 struct drm_connector_state *connector_state;
4be07317 12900 struct intel_crtc_state *crtc_state;
2bfb4627 12901 int ret;
83a57153
ACO		 12902
12903 state = drm_atomic_state_alloc(dev);
12904 if (!state) {
12905 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
12906 crtc->base.id);
12907 return;
12908 }
12909
12910 state->acquire_ctx = dev->mode_config.acquire_ctx;
12911
12912 /* The force restore path in the HW readout code relies on the staged
12913 * config still keeping the user requested config while the actual
12914 * state has been overwritten by the configuration read from HW. We
12915 * need to copy the staged config to the atomic state, otherwise the
12916 * mode set will just reapply the state the HW is already in. */
12917 for_each_intel_encoder(dev, encoder) {
12918 if (&encoder->new_crtc->base != crtc)
12919 continue;
12920
12921 for_each_intel_connector(dev, connector) {
12922 if (connector->new_encoder != encoder)
12923 continue;
12924
12925 connector_state = drm_atomic_get_connector_state(state, &connector->base);
12926 if (IS_ERR(connector_state)) {
12927 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
12928 connector->base.base.id,
12929 connector->base.name,
12930 PTR_ERR(connector_state));
12931 continue;
12932 }
12933
12934 connector_state->crtc = crtc;
12935 connector_state->best_encoder = &encoder->base;
12936 }
12937 }
12938
4be07317
ACO		 12939 for_each_intel_crtc(dev, intel_crtc) {
12940 if (intel_crtc->new_enabled == intel_crtc->base.enabled)
12941 continue;
12942
12943 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
12944 if (IS_ERR(crtc_state)) {
12945 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
12946 intel_crtc->base.base.id,
12947 PTR_ERR(crtc_state));
12948 continue;
12949 }
12950
49d6fa21
ML		 12951 crtc_state->base.active = crtc_state->base.enable =
12952 intel_crtc->new_enabled;
8c7b5ccb
ACO		 12953
12954 if (&intel_crtc->base == crtc)
12955 drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
4be07317
ACO		 12956 }
12957
d3a40d1b
ACO		 12958 intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
12959 crtc->primary->fb, crtc->x, crtc->y);
12960
2bfb4627
ACO		 12961 ret = intel_set_mode(crtc, state);
12962 if (ret)
12963 drm_atomic_state_free(state);
c0c36b94
CW		 12964}
12965
25c5b266
DV		 12966#undef for_each_intel_crtc_masked
12967
b7885264
ACO		 12968static bool intel_connector_in_mode_set(struct intel_connector *connector,
12969 struct drm_mode_set *set)
12970{
12971 int ro;
12972
12973 for (ro = 0; ro < set->num_connectors; ro++)
12974 if (set->connectors[ro] == &connector->base)
12975 return true;
12976
12977 return false;
12978}
12979
2e431051 12980static int
9a935856
DV		 12981intel_modeset_stage_output_state(struct drm_device *dev,
12982 struct drm_mode_set *set,
944b0c76 12983 struct drm_atomic_state *state)
50f56119 12984{
9a935856 12985 struct intel_connector *connector;
d5432a9d 12986 struct drm_connector *drm_connector;
944b0c76 12987 struct drm_connector_state *connector_state;
d5432a9d
ACO		 12988 struct drm_crtc *crtc;
12989 struct drm_crtc_state *crtc_state;
12990 int i, ret;
50f56119 12991
9abdda74 12992 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 12993 * of connectors. For paranoia, double-check this. */
12994 WARN_ON(!set->fb && (set->num_connectors != 0));
12995 WARN_ON(set->fb && (set->num_connectors == 0));
12996
3a3371ff 12997 for_each_intel_connector(dev, connector) {
b7885264
ACO		 12998 bool in_mode_set = intel_connector_in_mode_set(connector, set);
12999
d5432a9d
ACO		 13000 if (!in_mode_set && connector->base.state->crtc != set->crtc)
13001 continue;
13002
13003 connector_state =
13004 drm_atomic_get_connector_state(state, &connector->base);
13005 if (IS_ERR(connector_state))
13006 return PTR_ERR(connector_state);
13007
b7885264
ACO		 13008 if (in_mode_set) {
13009 int pipe = to_intel_crtc(set->crtc)->pipe;
d5432a9d
ACO		 13010 connector_state->best_encoder =
13011 &intel_find_encoder(connector, pipe)->base;
50f56119
DV		 13012 }
13013
d5432a9d 13014 if (connector->base.state->crtc != set->crtc)
b7885264
ACO		 13015 continue;
13016
9a935856
DV		 13017 /* If we disable the crtc, disable all its connectors. Also, if
13018 * the connector is on the changing crtc but not on the new
13019 * connector list, disable it. */
b7885264 13020 if (!set->fb || !in_mode_set) {
d5432a9d 13021 connector_state->best_encoder = NULL;
9a935856
DV		 13022
13023 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
13024 connector->base.base.id,
c23cc417 13025 connector->base.name);
9a935856 13026 }
50f56119 13027 }
9a935856 13028 /* connector->new_encoder is now updated for all connectors. */
50f56119 13029
d5432a9d
ACO		 13030 for_each_connector_in_state(state, drm_connector, connector_state, i) {
13031 connector = to_intel_connector(drm_connector);
13032
13033 if (!connector_state->best_encoder) {
13034 ret = drm_atomic_set_crtc_for_connector(connector_state,
13035 NULL);
13036 if (ret)
13037 return ret;
7668851f 13038
50f56119 13039 continue;
d5432a9d 13040 }
50f56119 13041
d5432a9d
ACO		 13042 if (intel_connector_in_mode_set(connector, set)) {
13043 struct drm_crtc *crtc = connector->base.state->crtc;
13044
13045 /* If this connector was in a previous crtc, add it
13046 * to the state. We might need to disable it. */
13047 if (crtc) {
13048 crtc_state =
13049 drm_atomic_get_crtc_state(state, crtc);
13050 if (IS_ERR(crtc_state))
13051 return PTR_ERR(crtc_state);
13052 }
13053
13054 ret = drm_atomic_set_crtc_for_connector(connector_state,
13055 set->crtc);
13056 if (ret)
13057 return ret;
13058 }
50f56119
DV		 13059
13060 /* Make sure the new CRTC will work with the encoder */
d5432a9d
ACO		 13061 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
13062 connector_state->crtc)) {
5e2b584e 13063 return -EINVAL;
50f56119 13064 }
944b0c76 13065
9a935856
DV		 13066 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
13067 connector->base.base.id,
c23cc417 13068 connector->base.name,
d5432a9d 13069 connector_state->crtc->base.id);
944b0c76 13070
d5432a9d
ACO		 13071 if (connector_state->best_encoder != &connector->encoder->base)
13072 connector->encoder =
13073 to_intel_encoder(connector_state->best_encoder);
0e32b39c 13074 }
7668851f 13075
d5432a9d 13076 for_each_crtc_in_state(state, crtc, crtc_state, i) {
49d6fa21
ML		 13077 bool has_connectors;
13078
d5432a9d
ACO		 13079 ret = drm_atomic_add_affected_connectors(state, crtc);
13080 if (ret)
13081 return ret;
4be07317 13082
49d6fa21
ML		 13083 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
13084 if (has_connectors != crtc_state->enable)
13085 crtc_state->enable =
13086 crtc_state->active = has_connectors;
7668851f
VS		 13087 }
13088
8c7b5ccb
ACO		 13089 ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
13090 set->fb, set->x, set->y);
13091 if (ret)
13092 return ret;
13093
13094 crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
13095 if (IS_ERR(crtc_state))
13096 return PTR_ERR(crtc_state);
13097
13098 if (set->mode)
13099 drm_mode_copy(&crtc_state->mode, set->mode);
13100
13101 if (set->num_connectors)
13102 crtc_state->active = true;
13103
2e431051
DV		 13104 return 0;
13105}
13106
bb546623
ACO		 13107static bool primary_plane_visible(struct drm_crtc *crtc)
13108{
13109 struct intel_plane_state *plane_state =
13110 to_intel_plane_state(crtc->primary->state);
13111
13112 return plane_state->visible;
13113}
13114
2e431051
DV		 13115static int intel_crtc_set_config(struct drm_mode_set *set)
13116{
13117 struct drm_device *dev;
83a57153 13118 struct drm_atomic_state *state = NULL;
5cec258b 13119 struct intel_crtc_state *pipe_config;
bb546623 13120 bool primary_plane_was_visible;
2e431051 13121 int ret;
2e431051 13122
8d3e375e
DV		 13123 BUG_ON(!set);
13124 BUG_ON(!set->crtc);
13125 BUG_ON(!set->crtc->helper_private);
2e431051 13126
7e53f3a4
DV		 13127 /* Enforce sane interface api - has been abused by the fb helper. */
13128 BUG_ON(!set->mode && set->fb);
13129 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 13130
2e431051
DV		 13131 if (set->fb) {
13132 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
13133 set->crtc->base.id, set->fb->base.id,
13134 (int)set->num_connectors, set->x, set->y);
13135 } else {
13136 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 13137 }
13138
13139 dev = set->crtc->dev;
13140
83a57153 13141 state = drm_atomic_state_alloc(dev);
7cbf41d6
ACO		 13142 if (!state)
13143 return -ENOMEM;
83a57153
ACO		 13144
13145 state->acquire_ctx = dev->mode_config.acquire_ctx;
13146
462a425a 13147 ret = intel_modeset_stage_output_state(dev, set, state);
2e431051 13148 if (ret)
7cbf41d6 13149 goto out;
2e431051 13150
8c7b5ccb 13151 pipe_config = intel_modeset_compute_config(set->crtc, state);
20664591 13152 if (IS_ERR(pipe_config)) {
6ac0483b 13153 ret = PTR_ERR(pipe_config);
7cbf41d6 13154 goto out;
20664591 13155 }
50f52756 13156
1f9954d0
JB		 13157 intel_update_pipe_size(to_intel_crtc(set->crtc));
13158
bb546623
ACO		 13159 primary_plane_was_visible = primary_plane_visible(set->crtc);
13160
8c7b5ccb 13161 ret = intel_set_mode_with_config(set->crtc, pipe_config);
bb546623
ACO		 13162
13163 if (ret == 0 &&
13164 pipe_config->base.enable &&
13165 pipe_config->base.planes_changed &&
13166 !needs_modeset(&pipe_config->base)) {
3b150f08 13167 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
3b150f08
MR		 13168
13169 /*
13170 * We need to make sure the primary plane is re-enabled if it
13171 * has previously been turned off.
13172 */
bb546623
ACO		 13173 if (ret == 0 && !primary_plane_was_visible &&
13174 primary_plane_visible(set->crtc)) {
3b150f08 13175 WARN_ON(!intel_crtc->active);
87d4300a 13176 intel_post_enable_primary(set->crtc);
3b150f08
MR		 13177 }
13178
7ca51a3a
JB		 13179 /*
13180 * In the fastboot case this may be our only check of the
13181 * state after boot. It would be better to only do it on
13182 * the first update, but we don't have a nice way of doing that
13183 * (and really, set_config isn't used much for high freq page
13184 * flipping, so increasing its cost here shouldn't be a big
13185 * deal).
13186 */
d330a953 13187 if (i915.fastboot && ret == 0)
7ca51a3a 13188 intel_modeset_check_state(set->crtc->dev);
50f56119
DV		 13189 }
13190
2d05eae1 13191 if (ret) {
bf67dfeb
DV		 13192 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
13193 set->crtc->base.id, ret);
2d05eae1 13194 }
50f56119 13195
7cbf41d6 13196out:
2bfb4627
ACO		 13197 if (ret)
13198 drm_atomic_state_free(state);
50f56119
DV		 13199 return ret;
13200}
f6e5b160
CW		 13201
13202static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 13203 .gamma_set = intel_crtc_gamma_set,
50f56119 13204 .set_config = intel_crtc_set_config,
f6e5b160
CW		 13205 .destroy = intel_crtc_destroy,
13206 .page_flip = intel_crtc_page_flip,
1356837e
MR		 13207 .atomic_duplicate_state = intel_crtc_duplicate_state,
13208 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 13209};
13210
5358901f
DV		 13211static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13212 struct intel_shared_dpll *pll,
13213 struct intel_dpll_hw_state *hw_state)
ee7b9f93 13214{
5358901f 13215 uint32_t val;
ee7b9f93 13216
f458ebbc 13217 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 13218 return false;
13219
5358901f 13220 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 13221 hw_state->dpll = val;
13222 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13223 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 13224
13225 return val & DPLL_VCO_ENABLE;
13226}
13227
15bdd4cf
DV		 13228static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13229 struct intel_shared_dpll *pll)
13230{
3e369b76
ACO		 13231 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13232 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 13233}
13234
e7b903d2
DV		 13235static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13236 struct intel_shared_dpll *pll)
13237{
e7b903d2 13238 /* PCH refclock must be enabled first */
89eff4be 13239 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 13240
3e369b76 13241 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 13242
13243 /* Wait for the clocks to stabilize. */
13244 POSTING_READ(PCH_DPLL(pll->id));
13245 udelay(150);
13246
13247 /* The pixel multiplier can only be updated once the
13248 * DPLL is enabled and the clocks are stable.
13249 *
13250 * So write it again.
13251 */
3e369b76 13252 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 13253 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13254 udelay(200);
13255}
13256
13257static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13258 struct intel_shared_dpll *pll)
13259{
13260 struct drm_device *dev = dev_priv->dev;
13261 struct intel_crtc *crtc;
e7b903d2
DV		 13262
13263 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 13264 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 13265 if (intel_crtc_to_shared_dpll(crtc) == pll)
13266 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 13267 }
13268
15bdd4cf
DV		 13269 I915_WRITE(PCH_DPLL(pll->id), 0);
13270 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13271 udelay(200);
13272}
13273
46edb027
DV		 13274static char *ibx_pch_dpll_names[] = {
13275 "PCH DPLL A",
13276 "PCH DPLL B",
13277};
13278
7c74ade1 13279static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 13280{
e7b903d2 13281 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 13282 int i;
13283
7c74ade1 13284 dev_priv->num_shared_dpll = 2;
ee7b9f93 13285
e72f9fbf 13286 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 13287 dev_priv->shared_dplls[i].id = i;
13288 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 13289 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 13290 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13291 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 13292 dev_priv->shared_dplls[i].get_hw_state =
13293 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 13294 }
13295}
13296
7c74ade1
DV		 13297static void intel_shared_dpll_init(struct drm_device *dev)
13298{
e7b903d2 13299 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 13300
b6283055
VS		 13301 intel_update_cdclk(dev);
13302
9cd86933
DV		 13303 if (HAS_DDI(dev))
13304 intel_ddi_pll_init(dev);
13305 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 13306 ibx_pch_dpll_init(dev);
13307 else
13308 dev_priv->num_shared_dpll = 0;
13309
13310 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 13311}
13312
1fc0a8f7
TU		 13313/**
13314 * intel_wm_need_update - Check whether watermarks need updating
13315 * @plane: drm plane
13316 * @state: new plane state
13317 *
13318 * Check current plane state versus the new one to determine whether
13319 * watermarks need to be recalculated.
13320 *
13321 * Returns true or false.
13322 */
13323bool intel_wm_need_update(struct drm_plane *plane,
13324 struct drm_plane_state *state)
13325{
13326 /* Update watermarks on tiling changes. */
13327 if (!plane->state->fb || !state->fb ||
13328 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
13329 plane->state->rotation != state->rotation)
13330 return true;
13331
13332 return false;
13333}
13334
6beb8c23
MR		 13335/**
13336 * intel_prepare_plane_fb - Prepare fb for usage on plane
13337 * @plane: drm plane to prepare for
13338 * @fb: framebuffer to prepare for presentation
13339 *
13340 * Prepares a framebuffer for usage on a display plane. Generally this
13341 * involves pinning the underlying object and updating the frontbuffer tracking
13342 * bits. Some older platforms need special physical address handling for
13343 * cursor planes.
13344 *
13345 * Returns 0 on success, negative error code on failure.
13346 */
13347int
13348intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13349 struct drm_framebuffer *fb,
13350 const struct drm_plane_state *new_state)
465c120c
MR		 13351{
13352 struct drm_device *dev = plane->dev;
6beb8c23
MR		 13353 struct intel_plane *intel_plane = to_intel_plane(plane);
13354 enum pipe pipe = intel_plane->pipe;
13355 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13356 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13357 unsigned frontbuffer_bits = 0;
13358 int ret = 0;
465c120c 13359
ea2c67bb 13360 if (!obj)
465c120c
MR		 13361 return 0;
13362
6beb8c23
MR		 13363 switch (plane->type) {
13364 case DRM_PLANE_TYPE_PRIMARY:
13365 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
13366 break;
13367 case DRM_PLANE_TYPE_CURSOR:
13368 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
13369 break;
13370 case DRM_PLANE_TYPE_OVERLAY:
13371 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
13372 break;
13373 }
465c120c 13374
6beb8c23 13375 mutex_lock(&dev->struct_mutex);
465c120c 13376
6beb8c23
MR		 13377 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13378 INTEL_INFO(dev)->cursor_needs_physical) {
13379 int align = IS_I830(dev) ? 16 * 1024 : 256;
13380 ret = i915_gem_object_attach_phys(obj, align);
13381 if (ret)
13382 DRM_DEBUG_KMS("failed to attach phys object\n");
13383 } else {
82bc3b2d 13384 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
6beb8c23 13385 }
465c120c 13386
6beb8c23
MR		 13387 if (ret == 0)
13388 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
fdd508a6 13389
4c34574f 13390 mutex_unlock(&dev->struct_mutex);
465c120c 13391
6beb8c23
MR		 13392 return ret;
13393}
13394
38f3ce3a
MR		 13395/**
13396 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13397 * @plane: drm plane to clean up for
13398 * @fb: old framebuffer that was on plane
13399 *
13400 * Cleans up a framebuffer that has just been removed from a plane.
13401 */
13402void
13403intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13404 struct drm_framebuffer *fb,
13405 const struct drm_plane_state *old_state)
38f3ce3a
MR		 13406{
13407 struct drm_device *dev = plane->dev;
13408 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13409
13410 if (WARN_ON(!obj))
13411 return;
13412
13413 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13414 !INTEL_INFO(dev)->cursor_needs_physical) {
13415 mutex_lock(&dev->struct_mutex);
82bc3b2d 13416 intel_unpin_fb_obj(fb, old_state);
38f3ce3a
MR		 13417 mutex_unlock(&dev->struct_mutex);
13418 }
465c120c
MR		 13419}
13420
6156a456
CK		 13421int
13422skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13423{
13424 int max_scale;
13425 struct drm_device *dev;
13426 struct drm_i915_private *dev_priv;
13427 int crtc_clock, cdclk;
13428
13429 if (!intel_crtc || !crtc_state)
13430 return DRM_PLANE_HELPER_NO_SCALING;
13431
13432 dev = intel_crtc->base.dev;
13433 dev_priv = dev->dev_private;
13434 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13435 cdclk = dev_priv->display.get_display_clock_speed(dev);
13436
13437 if (!crtc_clock || !cdclk)
13438 return DRM_PLANE_HELPER_NO_SCALING;
13439
13440 /*
13441 * skl max scale is lower of:
13442 * close to 3 but not 3, -1 is for that purpose
13443 * or
13444 * cdclk/crtc_clock
13445 */
13446 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13447
13448 return max_scale;
13449}
13450
465c120c 13451static int
3c692a41
GP		 13452intel_check_primary_plane(struct drm_plane *plane,
13453 struct intel_plane_state *state)
13454{
32b7eeec
MR		 13455 struct drm_device *dev = plane->dev;
13456 struct drm_i915_private *dev_priv = dev->dev_private;
2b875c22 13457 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 13458 struct intel_crtc *intel_crtc;
6156a456 13459 struct intel_crtc_state *crtc_state;
2b875c22 13460 struct drm_framebuffer *fb = state->base.fb;
3c692a41
GP		 13461 struct drm_rect *dest = &state->dst;
13462 struct drm_rect *src = &state->src;
13463 const struct drm_rect *clip = &state->clip;
d8106366 13464 bool can_position = false;
6156a456
CK		 13465 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13466 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
465c120c
MR		 13467 int ret;
13468
ea2c67bb
MR		 13469 crtc = crtc ? crtc : plane->crtc;
13470 intel_crtc = to_intel_crtc(crtc);
6156a456
CK		 13471 crtc_state = state->base.state ?
13472 intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL;
ea2c67bb 13473
6156a456 13474 if (INTEL_INFO(dev)->gen >= 9) {
225c228a
CK		 13475 /* use scaler when colorkey is not required */
13476 if (to_intel_plane(plane)->ckey.flags == I915_SET_COLORKEY_NONE) {
13477 min_scale = 1;
13478 max_scale = skl_max_scale(intel_crtc, crtc_state);
13479 }
d8106366 13480 can_position = true;
6156a456 13481 }
d8106366 13482
c59cb179
MR		 13483 ret = drm_plane_helper_check_update(plane, crtc, fb,
13484 src, dest, clip,
6156a456
CK		 13485 min_scale,
13486 max_scale,
d8106366
SJ		 13487 can_position, true,
13488 &state->visible);
c59cb179
MR		 13489 if (ret)
13490 return ret;
465c120c 13491
32b7eeec 13492 if (intel_crtc->active) {
b70709a6
ML		 13493 struct intel_plane_state *old_state =
13494 to_intel_plane_state(plane->state);
13495
32b7eeec
MR		 13496 intel_crtc->atomic.wait_for_flips = true;
13497
13498 /*
13499 * FBC does not work on some platforms for rotated
13500 * planes, so disable it when rotation is not 0 and
13501 * update it when rotation is set back to 0.
13502 *
13503 * FIXME: This is redundant with the fbc update done in
13504 * the primary plane enable function except that that
13505 * one is done too late. We eventually need to unify
13506 * this.
13507 */
b70709a6 13508 if (state->visible &&
32b7eeec 13509 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
e35fef21 13510 dev_priv->fbc.crtc == intel_crtc &&
8e7d688b 13511 state->base.rotation != BIT(DRM_ROTATE_0)) {
32b7eeec
MR		 13512 intel_crtc->atomic.disable_fbc = true;
13513 }
13514
b70709a6 13515 if (state->visible && !old_state->visible) {
32b7eeec
MR		 13516 /*
13517 * BDW signals flip done immediately if the plane
13518 * is disabled, even if the plane enable is already
13519 * armed to occur at the next vblank :(
13520 */
b70709a6 13521 if (IS_BROADWELL(dev))
32b7eeec
MR		 13522 intel_crtc->atomic.wait_vblank = true;
13523 }
13524
13525 intel_crtc->atomic.fb_bits |=
13526 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
13527
13528 intel_crtc->atomic.update_fbc = true;
0fda6568 13529
1fc0a8f7 13530 if (intel_wm_need_update(plane, &state->base))
0fda6568 13531 intel_crtc->atomic.update_wm = true;
ccc759dc
GP		 13532 }
13533
6156a456
CK		 13534 if (INTEL_INFO(dev)->gen >= 9) {
13535 ret = skl_update_scaler_users(intel_crtc, crtc_state,
13536 to_intel_plane(plane), state, 0);
13537 if (ret)
13538 return ret;
13539 }
13540
14af293f
GP		 13541 return 0;
13542}
13543
13544static void
13545intel_commit_primary_plane(struct drm_plane *plane,
13546 struct intel_plane_state *state)
13547{
2b875c22
MR		 13548 struct drm_crtc *crtc = state->base.crtc;
13549 struct drm_framebuffer *fb = state->base.fb;
13550 struct drm_device *dev = plane->dev;
14af293f 13551 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 13552 struct intel_crtc *intel_crtc;
14af293f
GP		 13553 struct drm_rect *src = &state->src;
13554
ea2c67bb
MR		 13555 crtc = crtc ? crtc : plane->crtc;
13556 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR		 13557
13558 plane->fb = fb;
9dc806fc
MR		 13559 crtc->x = src->x1 >> 16;
13560 crtc->y = src->y1 >> 16;
ccc759dc 13561
ccc759dc 13562 if (intel_crtc->active) {
27321ae8 13563 if (state->visible)
ccc759dc
GP		 13564 /* FIXME: kill this fastboot hack */
13565 intel_update_pipe_size(intel_crtc);
465c120c 13566
27321ae8
ML		 13567 dev_priv->display.update_primary_plane(crtc, plane->fb,
13568 crtc->x, crtc->y);
ccc759dc 13569 }
465c120c
MR		 13570}
13571
a8ad0d8e
ML		 13572static void
13573intel_disable_primary_plane(struct drm_plane *plane,
13574 struct drm_crtc *crtc,
13575 bool force)
13576{
13577 struct drm_device *dev = plane->dev;
13578 struct drm_i915_private *dev_priv = dev->dev_private;
13579
a8ad0d8e
ML		 13580 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13581}
13582
32b7eeec 13583static void intel_begin_crtc_commit(struct drm_crtc *crtc)
3c692a41 13584{
32b7eeec 13585 struct drm_device *dev = crtc->dev;
140fd38d 13586 struct drm_i915_private *dev_priv = dev->dev_private;
3c692a41 13587 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ea2c67bb
MR		 13588 struct intel_plane *intel_plane;
13589 struct drm_plane *p;
13590 unsigned fb_bits = 0;
13591
13592 /* Track fb's for any planes being disabled */
13593 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
13594 intel_plane = to_intel_plane(p);
13595
13596 if (intel_crtc->atomic.disabled_planes &
13597 (1 << drm_plane_index(p))) {
13598 switch (p->type) {
13599 case DRM_PLANE_TYPE_PRIMARY:
13600 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
13601 break;
13602 case DRM_PLANE_TYPE_CURSOR:
13603 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
13604 break;
13605 case DRM_PLANE_TYPE_OVERLAY:
13606 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
13607 break;
13608 }
3c692a41 13609
ea2c67bb
MR		 13610 mutex_lock(&dev->struct_mutex);
13611 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
13612 mutex_unlock(&dev->struct_mutex);
13613 }
13614 }
3c692a41 13615
32b7eeec
MR		 13616 if (intel_crtc->atomic.wait_for_flips)
13617 intel_crtc_wait_for_pending_flips(crtc);
3c692a41 13618
32b7eeec
MR		 13619 if (intel_crtc->atomic.disable_fbc)
13620 intel_fbc_disable(dev);
3c692a41 13621
32b7eeec
MR		 13622 if (intel_crtc->atomic.pre_disable_primary)
13623 intel_pre_disable_primary(crtc);
3c692a41 13624
32b7eeec
MR		 13625 if (intel_crtc->atomic.update_wm)
13626 intel_update_watermarks(crtc);
3c692a41 13627
32b7eeec 13628 intel_runtime_pm_get(dev_priv);
3c692a41 13629
c34c9ee4
MR		 13630 /* Perform vblank evasion around commit operation */
13631 if (intel_crtc->active)
13632 intel_crtc->atomic.evade =
13633 intel_pipe_update_start(intel_crtc,
13634 &intel_crtc->atomic.start_vbl_count);
32b7eeec
MR		 13635}
13636
13637static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13638{
13639 struct drm_device *dev = crtc->dev;
13640 struct drm_i915_private *dev_priv = dev->dev_private;
13641 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13642 struct drm_plane *p;
13643
c34c9ee4
MR		 13644 if (intel_crtc->atomic.evade)
13645 intel_pipe_update_end(intel_crtc,
13646 intel_crtc->atomic.start_vbl_count);
3c692a41 13647
140fd38d 13648 intel_runtime_pm_put(dev_priv);
3c692a41 13649
32b7eeec
MR		 13650 if (intel_crtc->atomic.wait_vblank)
13651 intel_wait_for_vblank(dev, intel_crtc->pipe);
13652
13653 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
13654
13655 if (intel_crtc->atomic.update_fbc) {
ccc759dc 13656 mutex_lock(&dev->struct_mutex);
7ff0ebcc 13657 intel_fbc_update(dev);
ccc759dc 13658 mutex_unlock(&dev->struct_mutex);
38f3ce3a 13659 }
3c692a41 13660
32b7eeec
MR		 13661 if (intel_crtc->atomic.post_enable_primary)
13662 intel_post_enable_primary(crtc);
3c692a41 13663
32b7eeec
MR		 13664 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
13665 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
13666 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
13667 false, false);
13668
13669 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
3c692a41
GP		 13670}
13671
cf4c7c12 13672/**
4a3b8769
MR		 13673 * intel_plane_destroy - destroy a plane
13674 * @plane: plane to destroy
cf4c7c12 13675 *
4a3b8769
MR		 13676 * Common destruction function for all types of planes (primary, cursor,
13677 * sprite).
cf4c7c12 13678 */
4a3b8769 13679void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 13680{
13681 struct intel_plane *intel_plane = to_intel_plane(plane);
13682 drm_plane_cleanup(plane);
13683 kfree(intel_plane);
13684}
13685
65a3fea0 13686const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR		 13687 .update_plane = drm_atomic_helper_update_plane,
13688 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13689 .destroy = intel_plane_destroy,
c196e1d6 13690 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 13691 .atomic_get_property = intel_plane_atomic_get_property,
13692 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 13693 .atomic_duplicate_state = intel_plane_duplicate_state,
13694 .atomic_destroy_state = intel_plane_destroy_state,
13695
465c120c
MR		 13696};
13697
13698static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13699 int pipe)
13700{
13701 struct intel_plane *primary;
8e7d688b 13702 struct intel_plane_state *state;
465c120c
MR		 13703 const uint32_t *intel_primary_formats;
13704 int num_formats;
13705
13706 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13707 if (primary == NULL)
13708 return NULL;
13709
8e7d688b
MR		 13710 state = intel_create_plane_state(&primary->base);
13711 if (!state) {
ea2c67bb
MR		 13712 kfree(primary);
13713 return NULL;
13714 }
8e7d688b 13715 primary->base.state = &state->base;
ea2c67bb 13716
465c120c
MR		 13717 primary->can_scale = false;
13718 primary->max_downscale = 1;
6156a456
CK		 13719 if (INTEL_INFO(dev)->gen >= 9) {
13720 primary->can_scale = true;
af99ceda 13721 state->scaler_id = -1;
6156a456 13722 }
465c120c
MR		 13723 primary->pipe = pipe;
13724 primary->plane = pipe;
c59cb179
MR		 13725 primary->check_plane = intel_check_primary_plane;
13726 primary->commit_plane = intel_commit_primary_plane;
a8ad0d8e 13727 primary->disable_plane = intel_disable_primary_plane;
08e221fb 13728 primary->ckey.flags = I915_SET_COLORKEY_NONE;
465c120c
MR		 13729 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13730 primary->plane = !pipe;
13731
6c0fd451
DL		 13732 if (INTEL_INFO(dev)->gen >= 9) {
13733 intel_primary_formats = skl_primary_formats;
13734 num_formats = ARRAY_SIZE(skl_primary_formats);
13735 } else if (INTEL_INFO(dev)->gen >= 4) {
568db4f2
DL		 13736 intel_primary_formats = i965_primary_formats;
13737 num_formats = ARRAY_SIZE(i965_primary_formats);
6c0fd451
DL		 13738 } else {
13739 intel_primary_formats = i8xx_primary_formats;
13740 num_formats = ARRAY_SIZE(i8xx_primary_formats);
465c120c
MR		 13741 }
13742
13743 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 13744 &intel_plane_funcs,
465c120c
MR		 13745 intel_primary_formats, num_formats,
13746 DRM_PLANE_TYPE_PRIMARY);
48404c1e 13747
3b7a5119
SJ		 13748 if (INTEL_INFO(dev)->gen >= 4)
13749 intel_create_rotation_property(dev, primary);
48404c1e 13750
ea2c67bb
MR		 13751 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13752
465c120c
MR		 13753 return &primary->base;
13754}
13755
3b7a5119
SJ		 13756void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13757{
13758 if (!dev->mode_config.rotation_property) {
13759 unsigned long flags = BIT(DRM_ROTATE_0) |
13760 BIT(DRM_ROTATE_180);
13761
13762 if (INTEL_INFO(dev)->gen >= 9)
13763 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13764
13765 dev->mode_config.rotation_property =
13766 drm_mode_create_rotation_property(dev, flags);
13767 }
13768 if (dev->mode_config.rotation_property)
13769 drm_object_attach_property(&plane->base.base,
13770 dev->mode_config.rotation_property,
13771 plane->base.state->rotation);
13772}
13773
3d7d6510 13774static int
852e787c
GP		 13775intel_check_cursor_plane(struct drm_plane *plane,
13776 struct intel_plane_state *state)
3d7d6510 13777{
2b875c22 13778 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 13779 struct drm_device *dev = plane->dev;
2b875c22 13780 struct drm_framebuffer *fb = state->base.fb;
852e787c
GP		 13781 struct drm_rect *dest = &state->dst;
13782 struct drm_rect *src = &state->src;
13783 const struct drm_rect *clip = &state->clip;
757f9a3e 13784 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
ea2c67bb 13785 struct intel_crtc *intel_crtc;
757f9a3e
GP		 13786 unsigned stride;
13787 int ret;
3d7d6510 13788
ea2c67bb
MR		 13789 crtc = crtc ? crtc : plane->crtc;
13790 intel_crtc = to_intel_crtc(crtc);
13791
757f9a3e 13792 ret = drm_plane_helper_check_update(plane, crtc, fb,
852e787c 13793 src, dest, clip,
3d7d6510
MR		 13794 DRM_PLANE_HELPER_NO_SCALING,
13795 DRM_PLANE_HELPER_NO_SCALING,
852e787c 13796 true, true, &state->visible);
757f9a3e
GP		 13797 if (ret)
13798 return ret;
13799
13800
13801 /* if we want to turn off the cursor ignore width and height */
13802 if (!obj)
32b7eeec 13803 goto finish;
757f9a3e 13804
757f9a3e 13805 /* Check for which cursor types we support */
ea2c67bb
MR		 13806 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
13807 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13808 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 13809 return -EINVAL;
13810 }
13811
ea2c67bb
MR		 13812 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13813 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 13814 DRM_DEBUG_KMS("buffer is too small\n");
13815 return -ENOMEM;
13816 }
13817
3a656b54 13818 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e
GP		 13819 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13820 ret = -EINVAL;
13821 }
757f9a3e 13822
32b7eeec
MR		 13823finish:
13824 if (intel_crtc->active) {
3749f463 13825 if (plane->state->crtc_w != state->base.crtc_w)
32b7eeec
MR		 13826 intel_crtc->atomic.update_wm = true;
13827
13828 intel_crtc->atomic.fb_bits |=
13829 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
13830 }
13831
757f9a3e 13832 return ret;
852e787c 13833}
3d7d6510 13834
a8ad0d8e
ML		 13835static void
13836intel_disable_cursor_plane(struct drm_plane *plane,
13837 struct drm_crtc *crtc,
13838 bool force)
13839{
13840 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13841
13842 if (!force) {
13843 plane->fb = NULL;
13844 intel_crtc->cursor_bo = NULL;
13845 intel_crtc->cursor_addr = 0;
13846 }
13847
13848 intel_crtc_update_cursor(crtc, false);
13849}
13850
f4a2cf29 13851static void
852e787c
GP		 13852intel_commit_cursor_plane(struct drm_plane *plane,
13853 struct intel_plane_state *state)
13854{
2b875c22 13855 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 13856 struct drm_device *dev = plane->dev;
13857 struct intel_crtc *intel_crtc;
2b875c22 13858 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 13859 uint32_t addr;
852e787c 13860
ea2c67bb
MR		 13861 crtc = crtc ? crtc : plane->crtc;
13862 intel_crtc = to_intel_crtc(crtc);
13863
2b875c22 13864 plane->fb = state->base.fb;
ea2c67bb
MR		 13865 crtc->cursor_x = state->base.crtc_x;
13866 crtc->cursor_y = state->base.crtc_y;
13867
a912f12f
GP		 13868 if (intel_crtc->cursor_bo == obj)
13869 goto update;
4ed91096 13870
f4a2cf29 13871 if (!obj)
a912f12f 13872 addr = 0;
f4a2cf29 13873 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 13874 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 13875 else
a912f12f 13876 addr = obj->phys_handle->busaddr;
852e787c 13877
a912f12f
GP		 13878 intel_crtc->cursor_addr = addr;
13879 intel_crtc->cursor_bo = obj;
13880update:
852e787c 13881
32b7eeec 13882 if (intel_crtc->active)
a912f12f 13883 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 13884}
13885
3d7d6510
MR		 13886static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13887 int pipe)
13888{
13889 struct intel_plane *cursor;
8e7d688b 13890 struct intel_plane_state *state;
3d7d6510
MR		 13891
13892 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13893 if (cursor == NULL)
13894 return NULL;
13895
8e7d688b
MR		 13896 state = intel_create_plane_state(&cursor->base);
13897 if (!state) {
ea2c67bb
MR		 13898 kfree(cursor);
13899 return NULL;
13900 }
8e7d688b 13901 cursor->base.state = &state->base;
ea2c67bb 13902
3d7d6510
MR		 13903 cursor->can_scale = false;
13904 cursor->max_downscale = 1;
13905 cursor->pipe = pipe;
13906 cursor->plane = pipe;
c59cb179
MR		 13907 cursor->check_plane = intel_check_cursor_plane;
13908 cursor->commit_plane = intel_commit_cursor_plane;
a8ad0d8e 13909 cursor->disable_plane = intel_disable_cursor_plane;
3d7d6510
MR		 13910
13911 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 13912 &intel_plane_funcs,
3d7d6510
MR		 13913 intel_cursor_formats,
13914 ARRAY_SIZE(intel_cursor_formats),
13915 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 13916
13917 if (INTEL_INFO(dev)->gen >= 4) {
13918 if (!dev->mode_config.rotation_property)
13919 dev->mode_config.rotation_property =
13920 drm_mode_create_rotation_property(dev,
13921 BIT(DRM_ROTATE_0) |
13922 BIT(DRM_ROTATE_180));
13923 if (dev->mode_config.rotation_property)
13924 drm_object_attach_property(&cursor->base.base,
13925 dev->mode_config.rotation_property,
8e7d688b 13926 state->base.rotation);
4398ad45
VS		 13927 }
13928
af99ceda
CK		 13929 if (INTEL_INFO(dev)->gen >=9)
13930 state->scaler_id = -1;
13931
ea2c67bb
MR		 13932 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13933
3d7d6510
MR		 13934 return &cursor->base;
13935}
13936
549e2bfb
CK		 13937static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13938 struct intel_crtc_state *crtc_state)
13939{
13940 int i;
13941 struct intel_scaler *intel_scaler;
13942 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13943
13944 for (i = 0; i < intel_crtc->num_scalers; i++) {
13945 intel_scaler = &scaler_state->scalers[i];
13946 intel_scaler->in_use = 0;
13947 intel_scaler->id = i;
13948
13949 intel_scaler->mode = PS_SCALER_MODE_DYN;
13950 }
13951
13952 scaler_state->scaler_id = -1;
13953}
13954
b358d0a6 13955static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 13956{
fbee40df 13957 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 13958 struct intel_crtc *intel_crtc;
f5de6e07 13959 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 13960 struct drm_plane *primary = NULL;
13961 struct drm_plane *cursor = NULL;
465c120c 13962 int i, ret;
79e53945 13963
955382f3 13964 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 13965 if (intel_crtc == NULL)
13966 return;
13967
f5de6e07
ACO		 13968 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13969 if (!crtc_state)
13970 goto fail;
550acefd
ACO		 13971 intel_crtc->config = crtc_state;
13972 intel_crtc->base.state = &crtc_state->base;
07878248 13973 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 13974
549e2bfb
CK		 13975 /* initialize shared scalers */
13976 if (INTEL_INFO(dev)->gen >= 9) {
13977 if (pipe == PIPE_C)
13978 intel_crtc->num_scalers = 1;
13979 else
13980 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13981
13982 skl_init_scalers(dev, intel_crtc, crtc_state);
13983 }
13984
465c120c 13985 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 13986 if (!primary)
13987 goto fail;
13988
13989 cursor = intel_cursor_plane_create(dev, pipe);
13990 if (!cursor)
13991 goto fail;
13992
465c120c 13993 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 13994 cursor, &intel_crtc_funcs);
13995 if (ret)
13996 goto fail;
79e53945
JB		 13997
13998 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 13999 for (i = 0; i < 256; i++) {
14000 intel_crtc->lut_r[i] = i;
14001 intel_crtc->lut_g[i] = i;
14002 intel_crtc->lut_b[i] = i;
14003 }
14004
1f1c2e24
VS		 14005 /*
14006 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 14007 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 14008 */
80824003
JB		 14009 intel_crtc->pipe = pipe;
14010 intel_crtc->plane = pipe;
3a77c4c4 14011 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 14012 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 14013 intel_crtc->plane = !pipe;
80824003
JB		 14014 }
14015
4b0e333e
CW		 14016 intel_crtc->cursor_base = ~0;
14017 intel_crtc->cursor_cntl = ~0;
dc41c154 14018 intel_crtc->cursor_size = ~0;
8d7849db 14019
22fd0fab
JB		 14020 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14021 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14022 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14023 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14024
79e53945 14025 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 14026
14027 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 14028 return;
14029
14030fail:
14031 if (primary)
14032 drm_plane_cleanup(primary);
14033 if (cursor)
14034 drm_plane_cleanup(cursor);
f5de6e07 14035 kfree(crtc_state);
3d7d6510 14036 kfree(intel_crtc);
79e53945
JB		 14037}
14038
752aa88a
JB		 14039enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14040{
14041 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 14042 struct drm_device *dev = connector->base.dev;
752aa88a 14043
51fd371b 14044 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 14045
d3babd3f 14046 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 14047 return INVALID_PIPE;
14048
14049 return to_intel_crtc(encoder->crtc)->pipe;
14050}
14051
08d7b3d1 14052int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 14053 struct drm_file *file)
08d7b3d1 14054{
08d7b3d1 14055 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 14056 struct drm_crtc *drmmode_crtc;
c05422d5 14057 struct intel_crtc *crtc;
08d7b3d1 14058
7707e653 14059 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 14060
7707e653 14061 if (!drmmode_crtc) {
08d7b3d1 14062 DRM_ERROR("no such CRTC id\n");
3f2c2057 14063 return -ENOENT;
08d7b3d1
CW		 14064 }
14065
7707e653 14066 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 14067 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 14068
c05422d5 14069 return 0;
08d7b3d1
CW		 14070}
14071
66a9278e 14072static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 14073{
66a9278e
DV		 14074 struct drm_device *dev = encoder->base.dev;
14075 struct intel_encoder *source_encoder;
79e53945 14076 int index_mask = 0;
79e53945
JB		 14077 int entry = 0;
14078
b2784e15 14079 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 14080 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 14081 index_mask |= (1 << entry);
14082
79e53945
JB		 14083 entry++;
14084 }
4ef69c7a 14085
79e53945
JB		 14086 return index_mask;
14087}
14088
4d302442
CW		 14089static bool has_edp_a(struct drm_device *dev)
14090{
14091 struct drm_i915_private *dev_priv = dev->dev_private;
14092
14093 if (!IS_MOBILE(dev))
14094 return false;
14095
14096 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14097 return false;
14098
e3589908 14099 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 14100 return false;
14101
14102 return true;
14103}
14104
84b4e042
JB		 14105static bool intel_crt_present(struct drm_device *dev)
14106{
14107 struct drm_i915_private *dev_priv = dev->dev_private;
14108
884497ed
DL		 14109 if (INTEL_INFO(dev)->gen >= 9)
14110 return false;
14111
cf404ce4 14112 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 14113 return false;
14114
14115 if (IS_CHERRYVIEW(dev))
14116 return false;
14117
14118 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14119 return false;
14120
14121 return true;
14122}
14123
79e53945
JB		 14124static void intel_setup_outputs(struct drm_device *dev)
14125{
725e30ad 14126 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 14127 struct intel_encoder *encoder;
cb0953d7 14128 bool dpd_is_edp = false;
79e53945 14129
c9093354 14130 intel_lvds_init(dev);
79e53945 14131
84b4e042 14132 if (intel_crt_present(dev))
79935fca 14133 intel_crt_init(dev);
cb0953d7 14134
c776eb2e
VK		 14135 if (IS_BROXTON(dev)) {
14136 /*
14137 * FIXME: Broxton doesn't support port detection via the
14138 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14139 * detect the ports.
14140 */
14141 intel_ddi_init(dev, PORT_A);
14142 intel_ddi_init(dev, PORT_B);
14143 intel_ddi_init(dev, PORT_C);
14144 } else if (HAS_DDI(dev)) {
0e72a5b5
ED		 14145 int found;
14146
de31facd
JB		 14147 /*
14148 * Haswell uses DDI functions to detect digital outputs.
14149 * On SKL pre-D0 the strap isn't connected, so we assume
14150 * it's there.
14151 */
0e72a5b5 14152 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
de31facd
JB		 14153 /* WaIgnoreDDIAStrap: skl */
14154 if (found ||
14155 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
0e72a5b5
ED		 14156 intel_ddi_init(dev, PORT_A);
14157
14158 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14159 * register */
14160 found = I915_READ(SFUSE_STRAP);
14161
14162 if (found & SFUSE_STRAP_DDIB_DETECTED)
14163 intel_ddi_init(dev, PORT_B);
14164 if (found & SFUSE_STRAP_DDIC_DETECTED)
14165 intel_ddi_init(dev, PORT_C);
14166 if (found & SFUSE_STRAP_DDID_DETECTED)
14167 intel_ddi_init(dev, PORT_D);
14168 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 14169 int found;
5d8a7752 14170 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 14171
14172 if (has_edp_a(dev))
14173 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 14174
dc0fa718 14175 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 14176 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 14177 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 14178 if (!found)
e2debe91 14179 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 14180 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 14181 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 14182 }
14183
dc0fa718 14184 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 14185 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 14186
dc0fa718 14187 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 14188 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 14189
5eb08b69 14190 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 14191 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 14192
270b3042 14193 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 14194 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 14195 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 14196 /*
14197 * The DP_DETECTED bit is the latched state of the DDC
14198 * SDA pin at boot. However since eDP doesn't require DDC
14199 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14200 * eDP ports may have been muxed to an alternate function.
14201 * Thus we can't rely on the DP_DETECTED bit alone to detect
14202 * eDP ports. Consult the VBT as well as DP_DETECTED to
14203 * detect eDP ports.
14204 */
d2182a66
VS		 14205 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14206 !intel_dp_is_edp(dev, PORT_B))
585a94b8
AB		 14207 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14208 PORT_B);
e17ac6db
VS		 14209 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14210 intel_dp_is_edp(dev, PORT_B))
14211 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
585a94b8 14212
d2182a66
VS		 14213 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14214 !intel_dp_is_edp(dev, PORT_C))
6f6005a5
JB		 14215 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14216 PORT_C);
e17ac6db
VS		 14217 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14218 intel_dp_is_edp(dev, PORT_C))
14219 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 14220
9418c1f1 14221 if (IS_CHERRYVIEW(dev)) {
e17ac6db 14222 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
9418c1f1
VS		 14223 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14224 PORT_D);
e17ac6db
VS		 14225 /* eDP not supported on port D, so don't check VBT */
14226 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14227 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
9418c1f1
VS		 14228 }
14229
3cfca973 14230 intel_dsi_init(dev);
103a196f 14231 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 14232 bool found = false;
7d57382e 14233
e2debe91 14234 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14235 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 14236 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 14237 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
14238 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 14239 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 14240 }
27185ae1 14241
e7281eab 14242 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 14243 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 14244 }
13520b05
KH		 14245
14246 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 14247
e2debe91 14248 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14249 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 14250 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 14251 }
27185ae1 14252
e2debe91 14253 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 14254
b01f2c3a
JB		 14255 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
14256 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 14257 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 14258 }
e7281eab 14259 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 14260 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 14261 }
27185ae1 14262
b01f2c3a 14263 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 14264 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 14265 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 14266 } else if (IS_GEN2(dev))
79e53945
JB		 14267 intel_dvo_init(dev);
14268
103a196f 14269 if (SUPPORTS_TV(dev))
79e53945
JB		 14270 intel_tv_init(dev);
14271
0bc12bcb 14272 intel_psr_init(dev);
7c8f8a70 14273
b2784e15 14274 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 14275 encoder->base.possible_crtcs = encoder->crtc_mask;
14276 encoder->base.possible_clones =
66a9278e 14277 intel_encoder_clones(encoder);
79e53945 14278 }
47356eb6 14279
dde86e2d 14280 intel_init_pch_refclk(dev);
270b3042
DV		 14281
14282 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 14283}
14284
14285static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14286{
60a5ca01 14287 struct drm_device *dev = fb->dev;
79e53945 14288 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 14289
ef2d633e 14290 drm_framebuffer_cleanup(fb);
60a5ca01 14291 mutex_lock(&dev->struct_mutex);
ef2d633e 14292 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 14293 drm_gem_object_unreference(&intel_fb->obj->base);
14294 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 14295 kfree(intel_fb);
14296}
14297
14298static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 14299 struct drm_file *file,
79e53945
JB		 14300 unsigned int *handle)
14301{
14302 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 14303 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 14304
05394f39 14305 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 14306}
14307
14308static const struct drm_framebuffer_funcs intel_fb_funcs = {
14309 .destroy = intel_user_framebuffer_destroy,
14310 .create_handle = intel_user_framebuffer_create_handle,
14311};
14312
b321803d
DL		 14313static
14314u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14315 uint32_t pixel_format)
14316{
14317 u32 gen = INTEL_INFO(dev)->gen;
14318
14319 if (gen >= 9) {
14320 /* "The stride in bytes must not exceed the of the size of 8K
14321 * pixels and 32K bytes."
14322 */
14323 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14324 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14325 return 32*1024;
14326 } else if (gen >= 4) {
14327 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14328 return 16*1024;
14329 else
14330 return 32*1024;
14331 } else if (gen >= 3) {
14332 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14333 return 8*1024;
14334 else
14335 return 16*1024;
14336 } else {
14337 /* XXX DSPC is limited to 4k tiled */
14338 return 8*1024;
14339 }
14340}
14341
b5ea642a
DV		 14342static int intel_framebuffer_init(struct drm_device *dev,
14343 struct intel_framebuffer *intel_fb,
14344 struct drm_mode_fb_cmd2 *mode_cmd,
14345 struct drm_i915_gem_object *obj)
79e53945 14346{
6761dd31 14347 unsigned int aligned_height;
79e53945 14348 int ret;
b321803d 14349 u32 pitch_limit, stride_alignment;
79e53945 14350
dd4916c5
DV		 14351 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14352
2a80eada
DV		 14353 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14354 /* Enforce that fb modifier and tiling mode match, but only for
14355 * X-tiled. This is needed for FBC. */
14356 if (!!(obj->tiling_mode == I915_TILING_X) !=
14357 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14358 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14359 return -EINVAL;
14360 }
14361 } else {
14362 if (obj->tiling_mode == I915_TILING_X)
14363 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14364 else if (obj->tiling_mode == I915_TILING_Y) {
14365 DRM_DEBUG("No Y tiling for legacy addfb\n");
14366 return -EINVAL;
14367 }
14368 }
14369
9a8f0a12
TU		 14370 /* Passed in modifier sanity checking. */
14371 switch (mode_cmd->modifier[0]) {
14372 case I915_FORMAT_MOD_Y_TILED:
14373 case I915_FORMAT_MOD_Yf_TILED:
14374 if (INTEL_INFO(dev)->gen < 9) {
14375 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14376 mode_cmd->modifier[0]);
14377 return -EINVAL;
14378 }
14379 case DRM_FORMAT_MOD_NONE:
14380 case I915_FORMAT_MOD_X_TILED:
14381 break;
14382 default:
c0f40428
JB		 14383 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14384 mode_cmd->modifier[0]);
57cd6508 14385 return -EINVAL;
c16ed4be 14386 }
57cd6508 14387
b321803d
DL		 14388 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14389 mode_cmd->pixel_format);
14390 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14391 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14392 mode_cmd->pitches[0], stride_alignment);
57cd6508 14393 return -EINVAL;
c16ed4be 14394 }
57cd6508 14395
b321803d
DL		 14396 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14397 mode_cmd->pixel_format);
a35cdaa0 14398 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 14399 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14400 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 14401 "tiled" : "linear",
a35cdaa0 14402 mode_cmd->pitches[0], pitch_limit);
5d7bd705 14403 return -EINVAL;
c16ed4be 14404 }
5d7bd705 14405
2a80eada 14406 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 14407 mode_cmd->pitches[0] != obj->stride) {
14408 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14409 mode_cmd->pitches[0], obj->stride);
5d7bd705 14410 return -EINVAL;
c16ed4be 14411 }
5d7bd705 14412
57779d06 14413 /* Reject formats not supported by any plane early. */
308e5bcb 14414 switch (mode_cmd->pixel_format) {
57779d06 14415 case DRM_FORMAT_C8:
04b3924d
VS		 14416 case DRM_FORMAT_RGB565:
14417 case DRM_FORMAT_XRGB8888:
14418 case DRM_FORMAT_ARGB8888:
57779d06
VS		 14419 break;
14420 case DRM_FORMAT_XRGB1555:
c16ed4be 14421 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 14422 DRM_DEBUG("unsupported pixel format: %s\n",
14423 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14424 return -EINVAL;
c16ed4be 14425 }
57779d06 14426 break;
57779d06 14427 case DRM_FORMAT_ABGR8888:
6c0fd451
DL		 14428 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14429 DRM_DEBUG("unsupported pixel format: %s\n",
14430 drm_get_format_name(mode_cmd->pixel_format));
14431 return -EINVAL;
14432 }
14433 break;
14434 case DRM_FORMAT_XBGR8888:
04b3924d 14435 case DRM_FORMAT_XRGB2101010:
57779d06 14436 case DRM_FORMAT_XBGR2101010:
c16ed4be 14437 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 14438 DRM_DEBUG("unsupported pixel format: %s\n",
14439 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14440 return -EINVAL;
c16ed4be 14441 }
b5626747 14442 break;
7531208b
DL		 14443 case DRM_FORMAT_ABGR2101010:
14444 if (!IS_VALLEYVIEW(dev)) {
14445 DRM_DEBUG("unsupported pixel format: %s\n",
14446 drm_get_format_name(mode_cmd->pixel_format));
14447 return -EINVAL;
14448 }
14449 break;
04b3924d
VS		 14450 case DRM_FORMAT_YUYV:
14451 case DRM_FORMAT_UYVY:
14452 case DRM_FORMAT_YVYU:
14453 case DRM_FORMAT_VYUY:
c16ed4be 14454 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 14455 DRM_DEBUG("unsupported pixel format: %s\n",
14456 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14457 return -EINVAL;
c16ed4be 14458 }
57cd6508
CW		 14459 break;
14460 default:
4ee62c76
VS		 14461 DRM_DEBUG("unsupported pixel format: %s\n",
14462 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 14463 return -EINVAL;
14464 }
14465
90f9a336
VS		 14466 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14467 if (mode_cmd->offsets[0] != 0)
14468 return -EINVAL;
14469
ec2c981e 14470 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 14471 mode_cmd->pixel_format,
14472 mode_cmd->modifier[0]);
53155c0a
DV		 14473 /* FIXME drm helper for size checks (especially planar formats)? */
14474 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14475 return -EINVAL;
14476
c7d73f6a
DV		 14477 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14478 intel_fb->obj = obj;
80075d49 14479 intel_fb->obj->framebuffer_references++;
c7d73f6a 14480
79e53945
JB		 14481 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14482 if (ret) {
14483 DRM_ERROR("framebuffer init failed %d\n", ret);
14484 return ret;
14485 }
14486
79e53945
JB		 14487 return 0;
14488}
14489
79e53945
JB		 14490static struct drm_framebuffer *
14491intel_user_framebuffer_create(struct drm_device *dev,
14492 struct drm_file *filp,
308e5bcb 14493 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 14494{
05394f39 14495 struct drm_i915_gem_object *obj;
79e53945 14496
308e5bcb
JB		 14497 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14498 mode_cmd->handles[0]));
c8725226 14499 if (&obj->base == NULL)
cce13ff7 14500 return ERR_PTR(-ENOENT);
79e53945 14501
d2dff872 14502 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 14503}
14504
4520f53a 14505#ifndef CONFIG_DRM_I915_FBDEV
0632fef6 14506static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 14507{
14508}
14509#endif
14510
79e53945 14511static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 14512 .fb_create = intel_user_framebuffer_create,
0632fef6 14513 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 14514 .atomic_check = intel_atomic_check,
14515 .atomic_commit = intel_atomic_commit,
79e53945
JB		 14516};
14517
e70236a8
JB		 14518/* Set up chip specific display functions */
14519static void intel_init_display(struct drm_device *dev)
14520{
14521 struct drm_i915_private *dev_priv = dev->dev_private;
14522
ee9300bb
DV		 14523 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14524 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 14525 else if (IS_CHERRYVIEW(dev))
14526 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 14527 else if (IS_VALLEYVIEW(dev))
14528 dev_priv->display.find_dpll = vlv_find_best_dpll;
14529 else if (IS_PINEVIEW(dev))
14530 dev_priv->display.find_dpll = pnv_find_best_dpll;
14531 else
14532 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14533
bc8d7dff
DL		 14534 if (INTEL_INFO(dev)->gen >= 9) {
14535 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14536 dev_priv->display.get_initial_plane_config =
14537 skylake_get_initial_plane_config;
bc8d7dff
DL		 14538 dev_priv->display.crtc_compute_clock =
14539 haswell_crtc_compute_clock;
14540 dev_priv->display.crtc_enable = haswell_crtc_enable;
14541 dev_priv->display.crtc_disable = haswell_crtc_disable;
14542 dev_priv->display.off = ironlake_crtc_off;
14543 dev_priv->display.update_primary_plane =
14544 skylake_update_primary_plane;
14545 } else if (HAS_DDI(dev)) {
0e8ffe1b 14546 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14547 dev_priv->display.get_initial_plane_config =
14548 ironlake_get_initial_plane_config;
797d0259
ACO		 14549 dev_priv->display.crtc_compute_clock =
14550 haswell_crtc_compute_clock;
4f771f10
PZ		 14551 dev_priv->display.crtc_enable = haswell_crtc_enable;
14552 dev_priv->display.crtc_disable = haswell_crtc_disable;
df8ad70c 14553 dev_priv->display.off = ironlake_crtc_off;
bc8d7dff
DL		 14554 dev_priv->display.update_primary_plane =
14555 ironlake_update_primary_plane;
09b4ddf9 14556 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 14557 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 14558 dev_priv->display.get_initial_plane_config =
14559 ironlake_get_initial_plane_config;
3fb37703
ACO		 14560 dev_priv->display.crtc_compute_clock =
14561 ironlake_crtc_compute_clock;
76e5a89c
DV		 14562 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14563 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 14564 dev_priv->display.off = ironlake_crtc_off;
262ca2b0
MR		 14565 dev_priv->display.update_primary_plane =
14566 ironlake_update_primary_plane;
89b667f8
JB		 14567 } else if (IS_VALLEYVIEW(dev)) {
14568 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14569 dev_priv->display.get_initial_plane_config =
14570 i9xx_get_initial_plane_config;
d6dfee7a 14571 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 14572 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14573 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14574 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR		 14575 dev_priv->display.update_primary_plane =
14576 i9xx_update_primary_plane;
f564048e 14577 } else {
0e8ffe1b 14578 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14579 dev_priv->display.get_initial_plane_config =
14580 i9xx_get_initial_plane_config;
d6dfee7a 14581 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 14582 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14583 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 14584 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR		 14585 dev_priv->display.update_primary_plane =
14586 i9xx_update_primary_plane;
f564048e 14587 }
e70236a8 14588
e70236a8 14589 /* Returns the core display clock speed */
1652d19e
VS		 14590 if (IS_SKYLAKE(dev))
14591 dev_priv->display.get_display_clock_speed =
14592 skylake_get_display_clock_speed;
14593 else if (IS_BROADWELL(dev))
14594 dev_priv->display.get_display_clock_speed =
14595 broadwell_get_display_clock_speed;
14596 else if (IS_HASWELL(dev))
14597 dev_priv->display.get_display_clock_speed =
14598 haswell_get_display_clock_speed;
14599 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB		 14600 dev_priv->display.get_display_clock_speed =
14601 valleyview_get_display_clock_speed;
b37a6434
VS		 14602 else if (IS_GEN5(dev))
14603 dev_priv->display.get_display_clock_speed =
14604 ilk_get_display_clock_speed;
a7c66cd8 14605 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
34edce2f 14606 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
e70236a8
JB		 14607 dev_priv->display.get_display_clock_speed =
14608 i945_get_display_clock_speed;
34edce2f
VS		 14609 else if (IS_GM45(dev))
14610 dev_priv->display.get_display_clock_speed =
14611 gm45_get_display_clock_speed;
14612 else if (IS_CRESTLINE(dev))
14613 dev_priv->display.get_display_clock_speed =
14614 i965gm_get_display_clock_speed;
14615 else if (IS_PINEVIEW(dev))
14616 dev_priv->display.get_display_clock_speed =
14617 pnv_get_display_clock_speed;
14618 else if (IS_G33(dev) || IS_G4X(dev))
14619 dev_priv->display.get_display_clock_speed =
14620 g33_get_display_clock_speed;
e70236a8
JB		 14621 else if (IS_I915G(dev))
14622 dev_priv->display.get_display_clock_speed =
14623 i915_get_display_clock_speed;
257a7ffc 14624 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 14625 dev_priv->display.get_display_clock_speed =
14626 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 14627 else if (IS_PINEVIEW(dev))
14628 dev_priv->display.get_display_clock_speed =
14629 pnv_get_display_clock_speed;
e70236a8
JB		 14630 else if (IS_I915GM(dev))
14631 dev_priv->display.get_display_clock_speed =
14632 i915gm_get_display_clock_speed;
14633 else if (IS_I865G(dev))
14634 dev_priv->display.get_display_clock_speed =
14635 i865_get_display_clock_speed;
f0f8a9ce 14636 else if (IS_I85X(dev))
e70236a8 14637 dev_priv->display.get_display_clock_speed =
1b1d2716 14638 i85x_get_display_clock_speed;
623e01e5
VS		 14639 else { /* 830 */
14640 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
e70236a8
JB		 14641 dev_priv->display.get_display_clock_speed =
14642 i830_get_display_clock_speed;
623e01e5 14643 }
e70236a8 14644
7c10a2b5 14645 if (IS_GEN5(dev)) {
3bb11b53 14646 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 14647 } else if (IS_GEN6(dev)) {
14648 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 14649 } else if (IS_IVYBRIDGE(dev)) {
14650 /* FIXME: detect B0+ stepping and use auto training */
14651 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 14652 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 14653 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
30a970c6
JB		 14654 } else if (IS_VALLEYVIEW(dev)) {
14655 dev_priv->display.modeset_global_resources =
14656 valleyview_modeset_global_resources;
f8437dd1
VK		 14657 } else if (IS_BROXTON(dev)) {
14658 dev_priv->display.modeset_global_resources =
14659 broxton_modeset_global_resources;
e70236a8 14660 }
8c9f3aaf 14661
8c9f3aaf
JB		 14662 switch (INTEL_INFO(dev)->gen) {
14663 case 2:
14664 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14665 break;
14666
14667 case 3:
14668 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14669 break;
14670
14671 case 4:
14672 case 5:
14673 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14674 break;
14675
14676 case 6:
14677 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14678 break;
7c9017e5 14679 case 7:
4e0bbc31 14680 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 14681 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14682 break;
830c81db 14683 case 9:
ba343e02
TU		 14684 /* Drop through - unsupported since execlist only. */
14685 default:
14686 /* Default just returns -ENODEV to indicate unsupported */
14687 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 14688 }
7bd688cd
JN		 14689
14690 intel_panel_init_backlight_funcs(dev);
e39b999a
VS		 14691
14692 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 14693}
14694
b690e96c
JB		 14695/*
14696 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14697 * resume, or other times. This quirk makes sure that's the case for
14698 * affected systems.
14699 */
0206e353 14700static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 14701{
14702 struct drm_i915_private *dev_priv = dev->dev_private;
14703
14704 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 14705 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 14706}
14707
b6b5d049
VS		 14708static void quirk_pipeb_force(struct drm_device *dev)
14709{
14710 struct drm_i915_private *dev_priv = dev->dev_private;
14711
14712 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14713 DRM_INFO("applying pipe b force quirk\n");
14714}
14715
435793df
KP		 14716/*
14717 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14718 */
14719static void quirk_ssc_force_disable(struct drm_device *dev)
14720{
14721 struct drm_i915_private *dev_priv = dev->dev_private;
14722 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 14723 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 14724}
14725
4dca20ef 14726/*
5a15ab5b
CE		 14727 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14728 * brightness value
4dca20ef
CE		 14729 */
14730static void quirk_invert_brightness(struct drm_device *dev)
14731{
14732 struct drm_i915_private *dev_priv = dev->dev_private;
14733 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 14734 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 14735}
14736
9c72cc6f
SD		 14737/* Some VBT's incorrectly indicate no backlight is present */
14738static void quirk_backlight_present(struct drm_device *dev)
14739{
14740 struct drm_i915_private *dev_priv = dev->dev_private;
14741 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14742 DRM_INFO("applying backlight present quirk\n");
14743}
14744
b690e96c
JB		 14745struct intel_quirk {
14746 int device;
14747 int subsystem_vendor;
14748 int subsystem_device;
14749 void (*hook)(struct drm_device *dev);
14750};
14751
5f85f176
EE		 14752/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14753struct intel_dmi_quirk {
14754 void (*hook)(struct drm_device *dev);
14755 const struct dmi_system_id (*dmi_id_list)[];
14756};
14757
14758static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14759{
14760 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14761 return 1;
14762}
14763
14764static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14765 {
14766 .dmi_id_list = &(const struct dmi_system_id[]) {
14767 {
14768 .callback = intel_dmi_reverse_brightness,
14769 .ident = "NCR Corporation",
14770 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14771 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14772 },
14773 },
14774 { } /* terminating entry */
14775 },
14776 .hook = quirk_invert_brightness,
14777 },
14778};
14779
c43b5634 14780static struct intel_quirk intel_quirks[] = {
b690e96c
JB		 14781 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14782 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14783
b690e96c
JB		 14784 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14785 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14786
5f080c0f
VS		 14787 /* 830 needs to leave pipe A & dpll A up */
14788 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14789
b6b5d049
VS		 14790 /* 830 needs to leave pipe B & dpll B up */
14791 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14792
435793df
KP		 14793 /* Lenovo U160 cannot use SSC on LVDS */
14794 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 14795
14796 /* Sony Vaio Y cannot use SSC on LVDS */
14797 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 14798
be505f64
AH		 14799 /* Acer Aspire 5734Z must invert backlight brightness */
14800 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14801
14802 /* Acer/eMachines G725 */
14803 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14804
14805 /* Acer/eMachines e725 */
14806 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14807
14808 /* Acer/Packard Bell NCL20 */
14809 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14810
14811 /* Acer Aspire 4736Z */
14812 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 14813
14814 /* Acer Aspire 5336 */
14815 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 14816
14817 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14818 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 14819
dfb3d47b
SD		 14820 /* Acer C720 Chromebook (Core i3 4005U) */
14821 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14822
b2a9601c 14823 /* Apple Macbook 2,1 (Core 2 T7400) */
14824 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14825
d4967d8c
SD		 14826 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14827 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 14828
14829 /* HP Chromebook 14 (Celeron 2955U) */
14830 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 14831
14832 /* Dell Chromebook 11 */
14833 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 14834};
14835
14836static void intel_init_quirks(struct drm_device *dev)
14837{
14838 struct pci_dev *d = dev->pdev;
14839 int i;
14840
14841 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14842 struct intel_quirk *q = &intel_quirks[i];
14843
14844 if (d->device == q->device &&
14845 (d->subsystem_vendor == q->subsystem_vendor ||
14846 q->subsystem_vendor == PCI_ANY_ID) &&
14847 (d->subsystem_device == q->subsystem_device ||
14848 q->subsystem_device == PCI_ANY_ID))
14849 q->hook(dev);
14850 }
5f85f176
EE		 14851 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14852 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14853 intel_dmi_quirks[i].hook(dev);
14854 }
b690e96c
JB		 14855}
14856
9cce37f4
JB		 14857/* Disable the VGA plane that we never use */
14858static void i915_disable_vga(struct drm_device *dev)
14859{
14860 struct drm_i915_private *dev_priv = dev->dev_private;
14861 u8 sr1;
766aa1c4 14862 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 14863
2b37c616 14864 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 14865 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 14866 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 14867 sr1 = inb(VGA_SR_DATA);
14868 outb(sr1 | 1<<5, VGA_SR_DATA);
14869 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14870 udelay(300);
14871
01f5a626 14872 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 14873 POSTING_READ(vga_reg);
14874}
14875
f817586c
DV		 14876void intel_modeset_init_hw(struct drm_device *dev)
14877{
b6283055 14878 intel_update_cdclk(dev);
a8f78b58 14879 intel_prepare_ddi(dev);
f817586c 14880 intel_init_clock_gating(dev);
8090c6b9 14881 intel_enable_gt_powersave(dev);
f817586c
DV		 14882}
14883
79e53945
JB		 14884void intel_modeset_init(struct drm_device *dev)
14885{
652c393a 14886 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 14887 int sprite, ret;
8cc87b75 14888 enum pipe pipe;
46f297fb 14889 struct intel_crtc *crtc;
79e53945
JB		 14890
14891 drm_mode_config_init(dev);
14892
14893 dev->mode_config.min_width = 0;
14894 dev->mode_config.min_height = 0;
14895
019d96cb
DA		 14896 dev->mode_config.preferred_depth = 24;
14897 dev->mode_config.prefer_shadow = 1;
14898
25bab385
TU		 14899 dev->mode_config.allow_fb_modifiers = true;
14900
e6ecefaa 14901 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 14902
b690e96c
JB		 14903 intel_init_quirks(dev);
14904
1fa61106
ED		 14905 intel_init_pm(dev);
14906
e3c74757
BW		 14907 if (INTEL_INFO(dev)->num_pipes == 0)
14908 return;
14909
e70236a8 14910 intel_init_display(dev);
7c10a2b5 14911 intel_init_audio(dev);
e70236a8 14912
a6c45cf0
CW		 14913 if (IS_GEN2(dev)) {
14914 dev->mode_config.max_width = 2048;
14915 dev->mode_config.max_height = 2048;
14916 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 14917 dev->mode_config.max_width = 4096;
14918 dev->mode_config.max_height = 4096;
79e53945 14919 } else {
a6c45cf0
CW		 14920 dev->mode_config.max_width = 8192;
14921 dev->mode_config.max_height = 8192;
79e53945 14922 }
068be561 14923
dc41c154
VS		 14924 if (IS_845G(dev) || IS_I865G(dev)) {
14925 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14926 dev->mode_config.cursor_height = 1023;
14927 } else if (IS_GEN2(dev)) {
068be561
DL		 14928 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14929 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14930 } else {
14931 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14932 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14933 }
14934
5d4545ae 14935 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 14936
28c97730 14937 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 14938 INTEL_INFO(dev)->num_pipes,
14939 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 14940
055e393f 14941 for_each_pipe(dev_priv, pipe) {
8cc87b75 14942 intel_crtc_init(dev, pipe);
3bdcfc0c 14943 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 14944 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 14945 if (ret)
06da8da2 14946 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 14947 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 14948 }
79e53945
JB		 14949 }
14950
f42bb70d
JB		 14951 intel_init_dpio(dev);
14952
e72f9fbf 14953 intel_shared_dpll_init(dev);
ee7b9f93 14954
9cce37f4
JB		 14955 /* Just disable it once at startup */
14956 i915_disable_vga(dev);
79e53945 14957 intel_setup_outputs(dev);
11be49eb
CW		 14958
14959 /* Just in case the BIOS is doing something questionable. */
7ff0ebcc 14960 intel_fbc_disable(dev);
fa9fa083 14961
6e9f798d 14962 drm_modeset_lock_all(dev);
fa9fa083 14963 intel_modeset_setup_hw_state(dev, false);
6e9f798d 14964 drm_modeset_unlock_all(dev);
46f297fb 14965
d3fcc808 14966 for_each_intel_crtc(dev, crtc) {
46f297fb
JB		 14967 if (!crtc->active)
14968 continue;
14969
46f297fb 14970 /*
46f297fb
JB		 14971 * Note that reserving the BIOS fb up front prevents us
14972 * from stuffing other stolen allocations like the ring
14973 * on top. This prevents some ugliness at boot time, and
14974 * can even allow for smooth boot transitions if the BIOS
14975 * fb is large enough for the active pipe configuration.
14976 */
5724dbd1
DL		 14977 if (dev_priv->display.get_initial_plane_config) {
14978 dev_priv->display.get_initial_plane_config(crtc,
46f297fb
JB		 14979 &crtc->plane_config);
14980 /*
14981 * If the fb is shared between multiple heads, we'll
14982 * just get the first one.
14983 */
f6936e29 14984 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
46f297fb 14985 }
46f297fb 14986 }
2c7111db
CW		 14987}
14988
7fad798e
DV		 14989static void intel_enable_pipe_a(struct drm_device *dev)
14990{
14991 struct intel_connector *connector;
14992 struct drm_connector *crt = NULL;
14993 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 14994 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 14995
14996 /* We can't just switch on the pipe A, we need to set things up with a
14997 * proper mode and output configuration. As a gross hack, enable pipe A
14998 * by enabling the load detect pipe once. */
3a3371ff 14999 for_each_intel_connector(dev, connector) {
7fad798e
DV		 15000 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15001 crt = &connector->base;
15002 break;
15003 }
15004 }
15005
15006 if (!crt)
15007 return;
15008
208bf9fd 15009 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 15010 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 15011}
15012
fa555837
DV		 15013static bool
15014intel_check_plane_mapping(struct intel_crtc *crtc)
15015{
7eb552ae
BW		 15016 struct drm_device *dev = crtc->base.dev;
15017 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 15018 u32 reg, val;
15019
7eb552ae 15020 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 15021 return true;
15022
15023 reg = DSPCNTR(!crtc->plane);
15024 val = I915_READ(reg);
15025
15026 if ((val & DISPLAY_PLANE_ENABLE) &&
15027 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15028 return false;
15029
15030 return true;
15031}
15032
24929352
DV		 15033static void intel_sanitize_crtc(struct intel_crtc *crtc)
15034{
15035 struct drm_device *dev = crtc->base.dev;
15036 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 15037 u32 reg;
24929352 15038
24929352 15039 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 15040 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 15041 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15042
d3eaf884 15043 /* restore vblank interrupts to correct state */
9625604c 15044 drm_crtc_vblank_reset(&crtc->base);
d297e103
VS		 15045 if (crtc->active) {
15046 update_scanline_offset(crtc);
9625604c
DV		 15047 drm_crtc_vblank_on(&crtc->base);
15048 }
d3eaf884 15049
24929352 15050 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 15051 * disable the crtc (and hence change the state) if it is wrong. Note
15052 * that gen4+ has a fixed plane -> pipe mapping. */
15053 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 15054 struct intel_connector *connector;
15055 bool plane;
15056
24929352
DV		 15057 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15058 crtc->base.base.id);
15059
15060 /* Pipe has the wrong plane attached and the plane is active.
15061 * Temporarily change the plane mapping and disable everything
15062 * ... */
15063 plane = crtc->plane;
b70709a6 15064 to_intel_plane_state(crtc->base.primary->state)->visible = true;
24929352 15065 crtc->plane = !plane;
ce22dba9 15066 intel_crtc_disable_planes(&crtc->base);
24929352
DV		 15067 dev_priv->display.crtc_disable(&crtc->base);
15068 crtc->plane = plane;
15069
15070 /* ... and break all links. */
3a3371ff 15071 for_each_intel_connector(dev, connector) {
24929352
DV		 15072 if (connector->encoder->base.crtc != &crtc->base)
15073 continue;
15074
7f1950fb
EE		 15075 connector->base.dpms = DRM_MODE_DPMS_OFF;
15076 connector->base.encoder = NULL;
24929352 15077 }
7f1950fb
EE		 15078 /* multiple connectors may have the same encoder:
15079 * handle them and break crtc link separately */
3a3371ff 15080 for_each_intel_connector(dev, connector)
7f1950fb
EE		 15081 if (connector->encoder->base.crtc == &crtc->base) {
15082 connector->encoder->base.crtc = NULL;
15083 connector->encoder->connectors_active = false;
15084 }
24929352
DV		 15085
15086 WARN_ON(crtc->active);
83d65738 15087 crtc->base.state->enable = false;
49d6fa21 15088 crtc->base.state->active = false;
24929352
DV		 15089 crtc->base.enabled = false;
15090 }
24929352 15091
7fad798e
DV		 15092 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15093 crtc->pipe == PIPE_A && !crtc->active) {
15094 /* BIOS forgot to enable pipe A, this mostly happens after
15095 * resume. Force-enable the pipe to fix this, the update_dpms
15096 * call below we restore the pipe to the right state, but leave
15097 * the required bits on. */
15098 intel_enable_pipe_a(dev);
15099 }
15100
24929352
DV		 15101 /* Adjust the state of the output pipe according to whether we
15102 * have active connectors/encoders. */
15103 intel_crtc_update_dpms(&crtc->base);
15104
83d65738 15105 if (crtc->active != crtc->base.state->enable) {
24929352
DV		 15106 struct intel_encoder *encoder;
15107
15108 /* This can happen either due to bugs in the get_hw_state
15109 * functions or because the pipe is force-enabled due to the
15110 * pipe A quirk. */
15111 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15112 crtc->base.base.id,
83d65738 15113 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 15114 crtc->active ? "enabled" : "disabled");
15115
83d65738 15116 crtc->base.state->enable = crtc->active;
49d6fa21 15117 crtc->base.state->active = crtc->active;
24929352
DV		 15118 crtc->base.enabled = crtc->active;
15119
15120 /* Because we only establish the connector -> encoder ->
15121 * crtc links if something is active, this means the
15122 * crtc is now deactivated. Break the links. connector
15123 * -> encoder links are only establish when things are
15124 * actually up, hence no need to break them. */
15125 WARN_ON(crtc->active);
15126
15127 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
15128 WARN_ON(encoder->connectors_active);
15129 encoder->base.crtc = NULL;
15130 }
15131 }
c5ab3bc0 15132
a3ed6aad 15133 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 15134 /*
15135 * We start out with underrun reporting disabled to avoid races.
15136 * For correct bookkeeping mark this on active crtcs.
15137 *
c5ab3bc0
DV		 15138 * Also on gmch platforms we dont have any hardware bits to
15139 * disable the underrun reporting. Which means we need to start
15140 * out with underrun reporting disabled also on inactive pipes,
15141 * since otherwise we'll complain about the garbage we read when
15142 * e.g. coming up after runtime pm.
15143 *
4cc31489
DV		 15144 * No protection against concurrent access is required - at
15145 * worst a fifo underrun happens which also sets this to false.
15146 */
15147 crtc->cpu_fifo_underrun_disabled = true;
15148 crtc->pch_fifo_underrun_disabled = true;
15149 }
24929352
DV		 15150}
15151
15152static void intel_sanitize_encoder(struct intel_encoder *encoder)
15153{
15154 struct intel_connector *connector;
15155 struct drm_device *dev = encoder->base.dev;
15156
15157 /* We need to check both for a crtc link (meaning that the
15158 * encoder is active and trying to read from a pipe) and the
15159 * pipe itself being active. */
15160 bool has_active_crtc = encoder->base.crtc &&
15161 to_intel_crtc(encoder->base.crtc)->active;
15162
15163 if (encoder->connectors_active && !has_active_crtc) {
15164 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15165 encoder->base.base.id,
8e329a03 15166 encoder->base.name);
24929352
DV		 15167
15168 /* Connector is active, but has no active pipe. This is
15169 * fallout from our resume register restoring. Disable
15170 * the encoder manually again. */
15171 if (encoder->base.crtc) {
15172 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15173 encoder->base.base.id,
8e329a03 15174 encoder->base.name);
24929352 15175 encoder->disable(encoder);
a62d1497
VS		 15176 if (encoder->post_disable)
15177 encoder->post_disable(encoder);
24929352 15178 }
7f1950fb
EE		 15179 encoder->base.crtc = NULL;
15180 encoder->connectors_active = false;
24929352
DV		 15181
15182 /* Inconsistent output/port/pipe state happens presumably due to
15183 * a bug in one of the get_hw_state functions. Or someplace else
15184 * in our code, like the register restore mess on resume. Clamp
15185 * things to off as a safer default. */
3a3371ff 15186 for_each_intel_connector(dev, connector) {
24929352
DV		 15187 if (connector->encoder != encoder)
15188 continue;
7f1950fb
EE		 15189 connector->base.dpms = DRM_MODE_DPMS_OFF;
15190 connector->base.encoder = NULL;
24929352
DV		 15191 }
15192 }
15193 /* Enabled encoders without active connectors will be fixed in
15194 * the crtc fixup. */
15195}
15196
04098753 15197void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 15198{
15199 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 15200 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 15201
04098753
ID		 15202 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15203 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15204 i915_disable_vga(dev);
15205 }
15206}
15207
15208void i915_redisable_vga(struct drm_device *dev)
15209{
15210 struct drm_i915_private *dev_priv = dev->dev_private;
15211
8dc8a27c
PZ		 15212 /* This function can be called both from intel_modeset_setup_hw_state or
15213 * at a very early point in our resume sequence, where the power well
15214 * structures are not yet restored. Since this function is at a very
15215 * paranoid "someone might have enabled VGA while we were not looking"
15216 * level, just check if the power well is enabled instead of trying to
15217 * follow the "don't touch the power well if we don't need it" policy
15218 * the rest of the driver uses. */
f458ebbc 15219 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 15220 return;
15221
04098753 15222 i915_redisable_vga_power_on(dev);
0fde901f
KM		 15223}
15224
98ec7739
VS		 15225static bool primary_get_hw_state(struct intel_crtc *crtc)
15226{
15227 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15228
15229 if (!crtc->active)
15230 return false;
15231
15232 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
15233}
15234
30e984df 15235static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 15236{
15237 struct drm_i915_private *dev_priv = dev->dev_private;
15238 enum pipe pipe;
24929352
DV		 15239 struct intel_crtc *crtc;
15240 struct intel_encoder *encoder;
15241 struct intel_connector *connector;
5358901f 15242 int i;
24929352 15243
d3fcc808 15244 for_each_intel_crtc(dev, crtc) {
b70709a6
ML		 15245 struct drm_plane *primary = crtc->base.primary;
15246 struct intel_plane_state *plane_state;
15247
6e3c9717 15248 memset(crtc->config, 0, sizeof(*crtc->config));
3b117c8f 15249
6e3c9717 15250 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
9953599b 15251
0e8ffe1b 15252 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 15253 crtc->config);
24929352 15254
83d65738 15255 crtc->base.state->enable = crtc->active;
49d6fa21 15256 crtc->base.state->active = crtc->active;
24929352 15257 crtc->base.enabled = crtc->active;
b70709a6
ML		 15258
15259 plane_state = to_intel_plane_state(primary->state);
15260 plane_state->visible = primary_get_hw_state(crtc);
24929352
DV		 15261
15262 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15263 crtc->base.base.id,
15264 crtc->active ? "enabled" : "disabled");
15265 }
15266
5358901f
DV		 15267 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15268 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15269
3e369b76
ACO		 15270 pll->on = pll->get_hw_state(dev_priv, pll,
15271 &pll->config.hw_state);
5358901f 15272 pll->active = 0;
3e369b76 15273 pll->config.crtc_mask = 0;
d3fcc808 15274 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 15275 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 15276 pll->active++;
3e369b76 15277 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 15278 }
5358901f 15279 }
5358901f 15280
1e6f2ddc 15281 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 15282 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 15283
3e369b76 15284 if (pll->config.crtc_mask)
bd2bb1b9 15285 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 15286 }
15287
b2784e15 15288 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15289 pipe = 0;
15290
15291 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 15292 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15293 encoder->base.crtc = &crtc->base;
6e3c9717 15294 encoder->get_config(encoder, crtc->config);
24929352
DV		 15295 } else {
15296 encoder->base.crtc = NULL;
15297 }
15298
15299 encoder->connectors_active = false;
6f2bcceb 15300 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 15301 encoder->base.base.id,
8e329a03 15302 encoder->base.name,
24929352 15303 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 15304 pipe_name(pipe));
24929352
DV		 15305 }
15306
3a3371ff 15307 for_each_intel_connector(dev, connector) {
24929352
DV		 15308 if (connector->get_hw_state(connector)) {
15309 connector->base.dpms = DRM_MODE_DPMS_ON;
15310 connector->encoder->connectors_active = true;
15311 connector->base.encoder = &connector->encoder->base;
15312 } else {
15313 connector->base.dpms = DRM_MODE_DPMS_OFF;
15314 connector->base.encoder = NULL;
15315 }
15316 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15317 connector->base.base.id,
c23cc417 15318 connector->base.name,
24929352
DV		 15319 connector->base.encoder ? "enabled" : "disabled");
15320 }
30e984df
DV		 15321}
15322
15323/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15324 * and i915 state tracking structures. */
15325void intel_modeset_setup_hw_state(struct drm_device *dev,
15326 bool force_restore)
15327{
15328 struct drm_i915_private *dev_priv = dev->dev_private;
15329 enum pipe pipe;
30e984df
DV		 15330 struct intel_crtc *crtc;
15331 struct intel_encoder *encoder;
35c95375 15332 int i;
30e984df
DV		 15333
15334 intel_modeset_readout_hw_state(dev);
24929352 15335
babea61d
JB		 15336 /*
15337 * Now that we have the config, copy it to each CRTC struct
15338 * Note that this could go away if we move to using crtc_config
15339 * checking everywhere.
15340 */
d3fcc808 15341 for_each_intel_crtc(dev, crtc) {
d330a953 15342 if (crtc->active && i915.fastboot) {
6e3c9717
ACO		 15343 intel_mode_from_pipe_config(&crtc->base.mode,
15344 crtc->config);
babea61d
JB		 15345 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15346 crtc->base.base.id);
15347 drm_mode_debug_printmodeline(&crtc->base.mode);
15348 }
15349 }
15350
24929352 15351 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 15352 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15353 intel_sanitize_encoder(encoder);
15354 }
15355
055e393f 15356 for_each_pipe(dev_priv, pipe) {
24929352
DV		 15357 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15358 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 15359 intel_dump_pipe_config(crtc, crtc->config,
15360 "[setup_hw_state]");
24929352 15361 }
9a935856 15362
d29b2f9d
ACO		 15363 intel_modeset_update_connector_atomic_state(dev);
15364
35c95375
DV		 15365 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15366 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15367
15368 if (!pll->on || pll->active)
15369 continue;
15370
15371 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15372
15373 pll->disable(dev_priv, pll);
15374 pll->on = false;
15375 }
15376
3078999f
PB		 15377 if (IS_GEN9(dev))
15378 skl_wm_get_hw_state(dev);
15379 else if (HAS_PCH_SPLIT(dev))
243e6a44
VS		 15380 ilk_wm_get_hw_state(dev);
15381
45e2b5f6 15382 if (force_restore) {
7d0bc1ea
VS		 15383 i915_redisable_vga(dev);
15384
f30da187
DV		 15385 /*
15386 * We need to use raw interfaces for restoring state to avoid
15387 * checking (bogus) intermediate states.
15388 */
055e393f 15389 for_each_pipe(dev_priv, pipe) {
b5644d05
JB		 15390 struct drm_crtc *crtc =
15391 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187 15392
83a57153 15393 intel_crtc_restore_mode(crtc);
45e2b5f6
DV		 15394 }
15395 } else {
15396 intel_modeset_update_staged_output_state(dev);
15397 }
8af6cf88
DV		 15398
15399 intel_modeset_check_state(dev);
2c7111db
CW		 15400}
15401
15402void intel_modeset_gem_init(struct drm_device *dev)
15403{
92122789 15404 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd 15405 struct drm_crtc *c;
2ff8fde1 15406 struct drm_i915_gem_object *obj;
e0d6149b 15407 int ret;
484b41dd 15408
ae48434c
ID		 15409 mutex_lock(&dev->struct_mutex);
15410 intel_init_gt_powersave(dev);
15411 mutex_unlock(&dev->struct_mutex);
15412
92122789
JB		 15413 /*
15414 * There may be no VBT; and if the BIOS enabled SSC we can
15415 * just keep using it to avoid unnecessary flicker. Whereas if the
15416 * BIOS isn't using it, don't assume it will work even if the VBT
15417 * indicates as much.
15418 */
15419 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15420 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15421 DREF_SSC1_ENABLE);
15422
1833b134 15423 intel_modeset_init_hw(dev);
02e792fb
DV		 15424
15425 intel_setup_overlay(dev);
484b41dd
JB		 15426
15427 /*
15428 * Make sure any fbs we allocated at startup are properly
15429 * pinned & fenced. When we do the allocation it's too early
15430 * for this.
15431 */
70e1e0ec 15432 for_each_crtc(dev, c) {
2ff8fde1
MR		 15433 obj = intel_fb_obj(c->primary->fb);
15434 if (obj == NULL)
484b41dd
JB		 15435 continue;
15436
e0d6149b
TU		 15437 mutex_lock(&dev->struct_mutex);
15438 ret = intel_pin_and_fence_fb_obj(c->primary,
15439 c->primary->fb,
15440 c->primary->state,
15441 NULL);
15442 mutex_unlock(&dev->struct_mutex);
15443 if (ret) {
484b41dd
JB		 15444 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15445 to_intel_crtc(c)->pipe);
66e514c1
DA		 15446 drm_framebuffer_unreference(c->primary->fb);
15447 c->primary->fb = NULL;
afd65eb4 15448 update_state_fb(c->primary);
484b41dd
JB		 15449 }
15450 }
0962c3c9
VS		 15451
15452 intel_backlight_register(dev);
79e53945
JB		 15453}
15454
4932e2c3
ID		 15455void intel_connector_unregister(struct intel_connector *intel_connector)
15456{
15457 struct drm_connector *connector = &intel_connector->base;
15458
15459 intel_panel_destroy_backlight(connector);
34ea3d38 15460 drm_connector_unregister(connector);
4932e2c3
ID		 15461}
15462
79e53945
JB		 15463void intel_modeset_cleanup(struct drm_device *dev)
15464{
652c393a 15465 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 15466 struct drm_connector *connector;
652c393a 15467
2eb5252e
ID		 15468 intel_disable_gt_powersave(dev);
15469
0962c3c9
VS		 15470 intel_backlight_unregister(dev);
15471
fd0c0642
DV		 15472 /*
15473 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 15474 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 15475 * experience fancy races otherwise.
15476 */
2aeb7d3a 15477 intel_irq_uninstall(dev_priv);
eb21b92b 15478
fd0c0642
DV		 15479 /*
15480 * Due to the hpd irq storm handling the hotplug work can re-arm the
15481 * poll handlers. Hence disable polling after hpd handling is shut down.
15482 */
f87ea761 15483 drm_kms_helper_poll_fini(dev);
fd0c0642 15484
652c393a
JB		 15485 mutex_lock(&dev->struct_mutex);
15486
723bfd70
JB		 15487 intel_unregister_dsm_handler();
15488
7ff0ebcc 15489 intel_fbc_disable(dev);
e70236a8 15490
69341a5e
KH		 15491 mutex_unlock(&dev->struct_mutex);
15492
1630fe75
CW		 15493 /* flush any delayed tasks or pending work */
15494 flush_scheduled_work();
15495
db31af1d
JN		 15496 /* destroy the backlight and sysfs files before encoders/connectors */
15497 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 15498 struct intel_connector *intel_connector;
15499
15500 intel_connector = to_intel_connector(connector);
15501 intel_connector->unregister(intel_connector);
db31af1d 15502 }
d9255d57 15503
79e53945 15504 drm_mode_config_cleanup(dev);
4d7bb011
DV		 15505
15506 intel_cleanup_overlay(dev);
ae48434c
ID		 15507
15508 mutex_lock(&dev->struct_mutex);
15509 intel_cleanup_gt_powersave(dev);
15510 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 15511}
15512
f1c79df3
ZW		 15513/*
15514 * Return which encoder is currently attached for connector.
15515 */
df0e9248 15516struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 15517{
df0e9248
CW		 15518 return &intel_attached_encoder(connector)->base;
15519}
f1c79df3 15520
df0e9248
CW		 15521void intel_connector_attach_encoder(struct intel_connector *connector,
15522 struct intel_encoder *encoder)
15523{
15524 connector->encoder = encoder;
15525 drm_mode_connector_attach_encoder(&connector->base,
15526 &encoder->base);
79e53945 15527}
28d52043
DA		 15528
15529/*
15530 * set vga decode state - true == enable VGA decode
15531 */
15532int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15533{
15534 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 15535 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 15536 u16 gmch_ctrl;
15537
75fa041d
CW		 15538 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15539 DRM_ERROR("failed to read control word\n");
15540 return -EIO;
15541 }
15542
c0cc8a55
CW		 15543 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15544 return 0;
15545
28d52043
DA		 15546 if (state)
15547 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15548 else
15549 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 15550
15551 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15552 DRM_ERROR("failed to write control word\n");
15553 return -EIO;
15554 }
15555
28d52043
DA		 15556 return 0;
15557}
c4a1d9e4 15558
c4a1d9e4 15559struct intel_display_error_state {
ff57f1b0
PZ		 15560
15561 u32 power_well_driver;
15562
63b66e5b
CW		 15563 int num_transcoders;
15564
c4a1d9e4
CW		 15565 struct intel_cursor_error_state {
15566 u32 control;
15567 u32 position;
15568 u32 base;
15569 u32 size;
52331309 15570 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 15571
15572 struct intel_pipe_error_state {
ddf9c536 15573 bool power_domain_on;
c4a1d9e4 15574 u32 source;
f301b1e1 15575 u32 stat;
52331309 15576 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 15577
15578 struct intel_plane_error_state {
15579 u32 control;
15580 u32 stride;
15581 u32 size;
15582 u32 pos;
15583 u32 addr;
15584 u32 surface;
15585 u32 tile_offset;
52331309 15586 } plane[I915_MAX_PIPES];
63b66e5b
CW		 15587
15588 struct intel_transcoder_error_state {
ddf9c536 15589 bool power_domain_on;
63b66e5b
CW		 15590 enum transcoder cpu_transcoder;
15591
15592 u32 conf;
15593
15594 u32 htotal;
15595 u32 hblank;
15596 u32 hsync;
15597 u32 vtotal;
15598 u32 vblank;
15599 u32 vsync;
15600 } transcoder[4];
c4a1d9e4
CW		 15601};
15602
15603struct intel_display_error_state *
15604intel_display_capture_error_state(struct drm_device *dev)
15605{
fbee40df 15606 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 15607 struct intel_display_error_state *error;
63b66e5b
CW		 15608 int transcoders[] = {
15609 TRANSCODER_A,
15610 TRANSCODER_B,
15611 TRANSCODER_C,
15612 TRANSCODER_EDP,
15613 };
c4a1d9e4
CW		 15614 int i;
15615
63b66e5b
CW		 15616 if (INTEL_INFO(dev)->num_pipes == 0)
15617 return NULL;
15618
9d1cb914 15619 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 15620 if (error == NULL)
15621 return NULL;
15622
190be112 15623 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 15624 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15625
055e393f 15626 for_each_pipe(dev_priv, i) {
ddf9c536 15627 error->pipe[i].power_domain_on =
f458ebbc
DV		 15628 __intel_display_power_is_enabled(dev_priv,
15629 POWER_DOMAIN_PIPE(i));
ddf9c536 15630 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 15631 continue;
15632
5efb3e28
VS		 15633 error->cursor[i].control = I915_READ(CURCNTR(i));
15634 error->cursor[i].position = I915_READ(CURPOS(i));
15635 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 15636
15637 error->plane[i].control = I915_READ(DSPCNTR(i));
15638 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 15639 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 15640 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 15641 error->plane[i].pos = I915_READ(DSPPOS(i));
15642 }
ca291363
PZ		 15643 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15644 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 15645 if (INTEL_INFO(dev)->gen >= 4) {
15646 error->plane[i].surface = I915_READ(DSPSURF(i));
15647 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15648 }
15649
c4a1d9e4 15650 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 15651
3abfce77 15652 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 15653 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 15654 }
15655
15656 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15657 if (HAS_DDI(dev_priv->dev))
15658 error->num_transcoders++; /* Account for eDP. */
15659
15660 for (i = 0; i < error->num_transcoders; i++) {
15661 enum transcoder cpu_transcoder = transcoders[i];
15662
ddf9c536 15663 error->transcoder[i].power_domain_on =
f458ebbc 15664 __intel_display_power_is_enabled(dev_priv,
38cc1daf 15665 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 15666 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 15667 continue;
15668
63b66e5b
CW		 15669 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15670
15671 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15672 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15673 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15674 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15675 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15676 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15677 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 15678 }
15679
15680 return error;
15681}
15682
edc3d884
MK		 15683#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15684
c4a1d9e4 15685void
edc3d884 15686intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 15687 struct drm_device *dev,
15688 struct intel_display_error_state *error)
15689{
055e393f 15690 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 15691 int i;
15692
63b66e5b
CW		 15693 if (!error)
15694 return;
15695
edc3d884 15696 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 15697 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 15698 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 15699 error->power_well_driver);
055e393f 15700 for_each_pipe(dev_priv, i) {
edc3d884 15701 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 15702 err_printf(m, " Power: %s\n",
15703 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 15704 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 15705 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 15706
15707 err_printf(m, "Plane [%d]:\n", i);
15708 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15709 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 15710 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 15711 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15712 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 15713 }
4b71a570 15714 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 15715 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 15716 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 15717 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15718 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 15719 }
15720
edc3d884
MK		 15721 err_printf(m, "Cursor [%d]:\n", i);
15722 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15723 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15724 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 15725 }
63b66e5b
CW		 15726
15727 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 15728 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 15729 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 15730 err_printf(m, " Power: %s\n",
15731 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 15732 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15733 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15734 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15735 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15736 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15737 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15738 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15739 }
c4a1d9e4 15740}
e2fcdaa9
VS		 15741
15742void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15743{
15744 struct intel_crtc *crtc;
15745
15746 for_each_intel_crtc(dev, crtc) {
15747 struct intel_unpin_work *work;
e2fcdaa9 15748
5e2d7afc 15749 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 15750
15751 work = crtc->unpin_work;
15752
15753 if (work && work->event &&
15754 work->event->base.file_priv == file) {
15755 kfree(work->event);
15756 work->event = NULL;
15757 }
15758
5e2d7afc 15759 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 15760 }
15761}
Linux kernel - Deliverables
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