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drm/i915/bxt: clear hpd status sticky bits earlier
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c 48/* Primary plane formats for gen <= 3 */
568db4f2 49static const uint32_t i8xx_primary_formats[] = {
67fe7dc5
DL		 50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
465c120c 52 DRM_FORMAT_XRGB1555,
67fe7dc5 53 DRM_FORMAT_XRGB8888,
465c120c
MR		 54};
55
56/* Primary plane formats for gen >= 4 */
568db4f2 57static const uint32_t i965_primary_formats[] = {
6c0fd451
DL		 58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64};
65
66static const uint32_t skl_primary_formats[] = {
67fe7dc5
DL		 67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
465c120c 70 DRM_FORMAT_XBGR8888,
67fe7dc5 71 DRM_FORMAT_ARGB8888,
465c120c
MR		 72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
465c120c 74 DRM_FORMAT_XBGR2101010,
465c120c
MR		 75};
76
3d7d6510
MR		 77/* Cursor formats */
78static const uint32_t intel_cursor_formats[] = {
79 DRM_FORMAT_ARGB8888,
80};
81
6b383a7f 82static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 83
f1f644dc 84static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 85 struct intel_crtc_state *pipe_config);
18442d08 86static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 87 struct intel_crtc_state *pipe_config);
f1f644dc 88
8c7b5ccb 89static int intel_set_mode(struct drm_crtc *crtc,
83a57153 90 struct drm_atomic_state *state);
eb1bfe80
JB		 91static int intel_framebuffer_init(struct drm_device *dev,
92 struct intel_framebuffer *ifb,
93 struct drm_mode_fb_cmd2 *mode_cmd,
94 struct drm_i915_gem_object *obj);
5b18e57c
DV		 95static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
96static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 97static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 98 struct intel_link_m_n *m_n,
99 struct intel_link_m_n *m2_n2);
29407aab 100static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 101static void haswell_set_pipeconf(struct drm_crtc *crtc);
102static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 103static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 104 const struct intel_crtc_state *pipe_config);
d288f65f 105static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 106 const struct intel_crtc_state *pipe_config);
ea2c67bb
MR		 107static void intel_begin_crtc_commit(struct drm_crtc *crtc);
108static void intel_finish_crtc_commit(struct drm_crtc *crtc);
549e2bfb
CK		 109static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
110 struct intel_crtc_state *crtc_state);
5ab7b0b7
ID		 111static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
112 int num_connectors);
ce22dba9
ML		 113static void intel_crtc_enable_planes(struct drm_crtc *crtc);
114static void intel_crtc_disable_planes(struct drm_crtc *crtc);
e7457a9a 115
0e32b39c
DA		 116static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
117{
118 if (!connector->mst_port)
119 return connector->encoder;
120 else
121 return &connector->mst_port->mst_encoders[pipe]->base;
122}
123
79e53945 124typedef struct {
0206e353 125 int min, max;
79e53945
JB		 126} intel_range_t;
127
128typedef struct {
0206e353
AJ		 129 int dot_limit;
130 int p2_slow, p2_fast;
79e53945
JB		 131} intel_p2_t;
132
d4906093
ML		 133typedef struct intel_limit intel_limit_t;
134struct intel_limit {
0206e353
AJ		 135 intel_range_t dot, vco, n, m, m1, m2, p, p1;
136 intel_p2_t p2;
d4906093 137};
79e53945 138
d2acd215
DV		 139int
140intel_pch_rawclk(struct drm_device *dev)
141{
142 struct drm_i915_private *dev_priv = dev->dev_private;
143
144 WARN_ON(!HAS_PCH_SPLIT(dev));
145
146 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
147}
148
021357ac
CW		 149static inline u32 /* units of 100MHz */
150intel_fdi_link_freq(struct drm_device *dev)
151{
8b99e68c
CW		 152 if (IS_GEN5(dev)) {
153 struct drm_i915_private *dev_priv = dev->dev_private;
154 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
155 } else
156 return 27;
021357ac
CW		 157}
158
5d536e28 159static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 160 .dot = { .min = 25000, .max = 350000 },
9c333719 161 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 162 .n = { .min = 2, .max = 16 },
0206e353
AJ		 163 .m = { .min = 96, .max = 140 },
164 .m1 = { .min = 18, .max = 26 },
165 .m2 = { .min = 6, .max = 16 },
166 .p = { .min = 4, .max = 128 },
167 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 168 .p2 = { .dot_limit = 165000,
169 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 170};
171
5d536e28
DV		 172static const intel_limit_t intel_limits_i8xx_dvo = {
173 .dot = { .min = 25000, .max = 350000 },
9c333719 174 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 175 .n = { .min = 2, .max = 16 },
5d536e28
DV		 176 .m = { .min = 96, .max = 140 },
177 .m1 = { .min = 18, .max = 26 },
178 .m2 = { .min = 6, .max = 16 },
179 .p = { .min = 4, .max = 128 },
180 .p1 = { .min = 2, .max = 33 },
181 .p2 = { .dot_limit = 165000,
182 .p2_slow = 4, .p2_fast = 4 },
183};
184
e4b36699 185static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 186 .dot = { .min = 25000, .max = 350000 },
9c333719 187 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 188 .n = { .min = 2, .max = 16 },
0206e353
AJ		 189 .m = { .min = 96, .max = 140 },
190 .m1 = { .min = 18, .max = 26 },
191 .m2 = { .min = 6, .max = 16 },
192 .p = { .min = 4, .max = 128 },
193 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 194 .p2 = { .dot_limit = 165000,
195 .p2_slow = 14, .p2_fast = 7 },
e4b36699 196};
273e27ca 197
e4b36699 198static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 199 .dot = { .min = 20000, .max = 400000 },
200 .vco = { .min = 1400000, .max = 2800000 },
201 .n = { .min = 1, .max = 6 },
202 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 203 .m1 = { .min = 8, .max = 18 },
204 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 205 .p = { .min = 5, .max = 80 },
206 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 207 .p2 = { .dot_limit = 200000,
208 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 209};
210
211static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 212 .dot = { .min = 20000, .max = 400000 },
213 .vco = { .min = 1400000, .max = 2800000 },
214 .n = { .min = 1, .max = 6 },
215 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 216 .m1 = { .min = 8, .max = 18 },
217 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 218 .p = { .min = 7, .max = 98 },
219 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 220 .p2 = { .dot_limit = 112000,
221 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 222};
223
273e27ca 224
e4b36699 225static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 226 .dot = { .min = 25000, .max = 270000 },
227 .vco = { .min = 1750000, .max = 3500000},
228 .n = { .min = 1, .max = 4 },
229 .m = { .min = 104, .max = 138 },
230 .m1 = { .min = 17, .max = 23 },
231 .m2 = { .min = 5, .max = 11 },
232 .p = { .min = 10, .max = 30 },
233 .p1 = { .min = 1, .max = 3},
234 .p2 = { .dot_limit = 270000,
235 .p2_slow = 10,
236 .p2_fast = 10
044c7c41 237 },
e4b36699
KP		 238};
239
240static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 241 .dot = { .min = 22000, .max = 400000 },
242 .vco = { .min = 1750000, .max = 3500000},
243 .n = { .min = 1, .max = 4 },
244 .m = { .min = 104, .max = 138 },
245 .m1 = { .min = 16, .max = 23 },
246 .m2 = { .min = 5, .max = 11 },
247 .p = { .min = 5, .max = 80 },
248 .p1 = { .min = 1, .max = 8},
249 .p2 = { .dot_limit = 165000,
250 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 251};
252
253static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 254 .dot = { .min = 20000, .max = 115000 },
255 .vco = { .min = 1750000, .max = 3500000 },
256 .n = { .min = 1, .max = 3 },
257 .m = { .min = 104, .max = 138 },
258 .m1 = { .min = 17, .max = 23 },
259 .m2 = { .min = 5, .max = 11 },
260 .p = { .min = 28, .max = 112 },
261 .p1 = { .min = 2, .max = 8 },
262 .p2 = { .dot_limit = 0,
263 .p2_slow = 14, .p2_fast = 14
044c7c41 264 },
e4b36699
KP		 265};
266
267static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 268 .dot = { .min = 80000, .max = 224000 },
269 .vco = { .min = 1750000, .max = 3500000 },
270 .n = { .min = 1, .max = 3 },
271 .m = { .min = 104, .max = 138 },
272 .m1 = { .min = 17, .max = 23 },
273 .m2 = { .min = 5, .max = 11 },
274 .p = { .min = 14, .max = 42 },
275 .p1 = { .min = 2, .max = 6 },
276 .p2 = { .dot_limit = 0,
277 .p2_slow = 7, .p2_fast = 7
044c7c41 278 },
e4b36699
KP		 279};
280
f2b115e6 281static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 282 .dot = { .min = 20000, .max = 400000},
283 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 284 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 285 .n = { .min = 3, .max = 6 },
286 .m = { .min = 2, .max = 256 },
273e27ca 287 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 288 .m1 = { .min = 0, .max = 0 },
289 .m2 = { .min = 0, .max = 254 },
290 .p = { .min = 5, .max = 80 },
291 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 292 .p2 = { .dot_limit = 200000,
293 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 294};
295
f2b115e6 296static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 297 .dot = { .min = 20000, .max = 400000 },
298 .vco = { .min = 1700000, .max = 3500000 },
299 .n = { .min = 3, .max = 6 },
300 .m = { .min = 2, .max = 256 },
301 .m1 = { .min = 0, .max = 0 },
302 .m2 = { .min = 0, .max = 254 },
303 .p = { .min = 7, .max = 112 },
304 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 305 .p2 = { .dot_limit = 112000,
306 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 307};
308
273e27ca
EA		 309/* Ironlake / Sandybridge
310 *
311 * We calculate clock using (register_value + 2) for N/M1/M2, so here
312 * the range value for them is (actual_value - 2).
313 */
b91ad0ec 314static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 315 .dot = { .min = 25000, .max = 350000 },
316 .vco = { .min = 1760000, .max = 3510000 },
317 .n = { .min = 1, .max = 5 },
318 .m = { .min = 79, .max = 127 },
319 .m1 = { .min = 12, .max = 22 },
320 .m2 = { .min = 5, .max = 9 },
321 .p = { .min = 5, .max = 80 },
322 .p1 = { .min = 1, .max = 8 },
323 .p2 = { .dot_limit = 225000,
324 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 325};
326
b91ad0ec 327static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 328 .dot = { .min = 25000, .max = 350000 },
329 .vco = { .min = 1760000, .max = 3510000 },
330 .n = { .min = 1, .max = 3 },
331 .m = { .min = 79, .max = 118 },
332 .m1 = { .min = 12, .max = 22 },
333 .m2 = { .min = 5, .max = 9 },
334 .p = { .min = 28, .max = 112 },
335 .p1 = { .min = 2, .max = 8 },
336 .p2 = { .dot_limit = 225000,
337 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 338};
339
340static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 341 .dot = { .min = 25000, .max = 350000 },
342 .vco = { .min = 1760000, .max = 3510000 },
343 .n = { .min = 1, .max = 3 },
344 .m = { .min = 79, .max = 127 },
345 .m1 = { .min = 12, .max = 22 },
346 .m2 = { .min = 5, .max = 9 },
347 .p = { .min = 14, .max = 56 },
348 .p1 = { .min = 2, .max = 8 },
349 .p2 = { .dot_limit = 225000,
350 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 351};
352
273e27ca 353/* LVDS 100mhz refclk limits. */
b91ad0ec 354static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 355 .dot = { .min = 25000, .max = 350000 },
356 .vco = { .min = 1760000, .max = 3510000 },
357 .n = { .min = 1, .max = 2 },
358 .m = { .min = 79, .max = 126 },
359 .m1 = { .min = 12, .max = 22 },
360 .m2 = { .min = 5, .max = 9 },
361 .p = { .min = 28, .max = 112 },
0206e353 362 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 363 .p2 = { .dot_limit = 225000,
364 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 365};
366
367static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 368 .dot = { .min = 25000, .max = 350000 },
369 .vco = { .min = 1760000, .max = 3510000 },
370 .n = { .min = 1, .max = 3 },
371 .m = { .min = 79, .max = 126 },
372 .m1 = { .min = 12, .max = 22 },
373 .m2 = { .min = 5, .max = 9 },
374 .p = { .min = 14, .max = 42 },
0206e353 375 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 376 .p2 = { .dot_limit = 225000,
377 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 378};
379
dc730512 380static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 381 /*
382 * These are the data rate limits (measured in fast clocks)
383 * since those are the strictest limits we have. The fast
384 * clock and actual rate limits are more relaxed, so checking
385 * them would make no difference.
386 */
387 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 388 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 389 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 390 .m1 = { .min = 2, .max = 3 },
391 .m2 = { .min = 11, .max = 156 },
b99ab663 392 .p1 = { .min = 2, .max = 3 },
5fdc9c49 393 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 394};
395
ef9348c8
CML		 396static const intel_limit_t intel_limits_chv = {
397 /*
398 * These are the data rate limits (measured in fast clocks)
399 * since those are the strictest limits we have. The fast
400 * clock and actual rate limits are more relaxed, so checking
401 * them would make no difference.
402 */
403 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 404 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 405 .n = { .min = 1, .max = 1 },
406 .m1 = { .min = 2, .max = 2 },
407 .m2 = { .min = 24 << 22, .max = 175 << 22 },
408 .p1 = { .min = 2, .max = 4 },
409 .p2 = { .p2_slow = 1, .p2_fast = 14 },
410};
411
5ab7b0b7
ID		 412static const intel_limit_t intel_limits_bxt = {
413 /* FIXME: find real dot limits */
414 .dot = { .min = 0, .max = INT_MAX },
415 .vco = { .min = 4800000, .max = 6480000 },
416 .n = { .min = 1, .max = 1 },
417 .m1 = { .min = 2, .max = 2 },
418 /* FIXME: find real m2 limits */
419 .m2 = { .min = 2 << 22, .max = 255 << 22 },
420 .p1 = { .min = 2, .max = 4 },
421 .p2 = { .p2_slow = 1, .p2_fast = 20 },
422};
423
6b4bf1c4
VS		 424static void vlv_clock(int refclk, intel_clock_t *clock)
425{
426 clock->m = clock->m1 * clock->m2;
427 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 428 if (WARN_ON(clock->n == 0 || clock->p == 0))
429 return;
fb03ac01
VS		 430 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
431 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
6b4bf1c4
VS		 432}
433
e0638cdf
PZ		 434/**
435 * Returns whether any output on the specified pipe is of the specified type
436 */
4093561b 437bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 438{
409ee761 439 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 440 struct intel_encoder *encoder;
441
409ee761 442 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 443 if (encoder->type == type)
444 return true;
445
446 return false;
447}
448
d0737e1d
ACO		 449/**
450 * Returns whether any output on the specified pipe will have the specified
451 * type after a staged modeset is complete, i.e., the same as
452 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
453 * encoder->crtc.
454 */
a93e255f
ACO		 455static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
456 int type)
d0737e1d 457{
a93e255f 458 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 459 struct drm_connector *connector;
a93e255f 460 struct drm_connector_state *connector_state;
d0737e1d 461 struct intel_encoder *encoder;
a93e255f
ACO		 462 int i, num_connectors = 0;
463
da3ced29 464 for_each_connector_in_state(state, connector, connector_state, i) {
a93e255f
ACO		 465 if (connector_state->crtc != crtc_state->base.crtc)
466 continue;
467
468 num_connectors++;
d0737e1d 469
a93e255f
ACO		 470 encoder = to_intel_encoder(connector_state->best_encoder);
471 if (encoder->type == type)
d0737e1d 472 return true;
a93e255f
ACO		 473 }
474
475 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 476
477 return false;
478}
479
a93e255f
ACO		 480static const intel_limit_t *
481intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 482{
a93e255f 483 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 484 const intel_limit_t *limit;
b91ad0ec 485
a93e255f 486 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 487 if (intel_is_dual_link_lvds(dev)) {
1b894b59 488 if (refclk == 100000)
b91ad0ec
ZW		 489 limit = &intel_limits_ironlake_dual_lvds_100m;
490 else
491 limit = &intel_limits_ironlake_dual_lvds;
492 } else {
1b894b59 493 if (refclk == 100000)
b91ad0ec
ZW		 494 limit = &intel_limits_ironlake_single_lvds_100m;
495 else
496 limit = &intel_limits_ironlake_single_lvds;
497 }
c6bb3538 498 } else
b91ad0ec 499 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 500
501 return limit;
502}
503
a93e255f
ACO		 504static const intel_limit_t *
505intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 506{
a93e255f 507 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 508 const intel_limit_t *limit;
509
a93e255f 510 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 511 if (intel_is_dual_link_lvds(dev))
e4b36699 512 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 513 else
e4b36699 514 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 515 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
516 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 517 limit = &intel_limits_g4x_hdmi;
a93e255f 518 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 519 limit = &intel_limits_g4x_sdvo;
044c7c41 520 } else /* The option is for other outputs */
e4b36699 521 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 522
523 return limit;
524}
525
a93e255f
ACO		 526static const intel_limit_t *
527intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 528{
a93e255f 529 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 530 const intel_limit_t *limit;
531
5ab7b0b7
ID		 532 if (IS_BROXTON(dev))
533 limit = &intel_limits_bxt;
534 else if (HAS_PCH_SPLIT(dev))
a93e255f 535 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 536 else if (IS_G4X(dev)) {
a93e255f 537 limit = intel_g4x_limit(crtc_state);
f2b115e6 538 } else if (IS_PINEVIEW(dev)) {
a93e255f 539 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 540 limit = &intel_limits_pineview_lvds;
2177832f 541 else
f2b115e6 542 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 543 } else if (IS_CHERRYVIEW(dev)) {
544 limit = &intel_limits_chv;
a0c4da24 545 } else if (IS_VALLEYVIEW(dev)) {
dc730512 546 limit = &intel_limits_vlv;
a6c45cf0 547 } else if (!IS_GEN2(dev)) {
a93e255f 548 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 549 limit = &intel_limits_i9xx_lvds;
550 else
551 limit = &intel_limits_i9xx_sdvo;
79e53945 552 } else {
a93e255f 553 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 554 limit = &intel_limits_i8xx_lvds;
a93e255f 555 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 556 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 557 else
558 limit = &intel_limits_i8xx_dac;
79e53945
JB		 559 }
560 return limit;
561}
562
f2b115e6
AJ		 563/* m1 is reserved as 0 in Pineview, n is a ring counter */
564static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 565{
2177832f
SL		 566 clock->m = clock->m2 + 2;
567 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 568 if (WARN_ON(clock->n == 0 || clock->p == 0))
569 return;
fb03ac01
VS		 570 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
571 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
2177832f
SL		 572}
573
7429e9d4
DV		 574static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
575{
576 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
577}
578
ac58c3f0 579static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 580{
7429e9d4 581 clock->m = i9xx_dpll_compute_m(clock);
79e53945 582 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 583 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
584 return;
fb03ac01
VS		 585 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
586 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
79e53945
JB		 587}
588
ef9348c8
CML		 589static void chv_clock(int refclk, intel_clock_t *clock)
590{
591 clock->m = clock->m1 * clock->m2;
592 clock->p = clock->p1 * clock->p2;
593 if (WARN_ON(clock->n == 0 || clock->p == 0))
594 return;
595 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
596 clock->n << 22);
597 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
598}
599
7c04d1d9 600#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 601/**
602 * Returns whether the given set of divisors are valid for a given refclk with
603 * the given connectors.
604 */
605
1b894b59
CW		 606static bool intel_PLL_is_valid(struct drm_device *dev,
607 const intel_limit_t *limit,
608 const intel_clock_t *clock)
79e53945 609{
f01b7962
VS		 610 if (clock->n < limit->n.min || limit->n.max < clock->n)
611 INTELPllInvalid("n out of range\n");
79e53945 612 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 613 INTELPllInvalid("p1 out of range\n");
79e53945 614 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 615 INTELPllInvalid("m2 out of range\n");
79e53945 616 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 617 INTELPllInvalid("m1 out of range\n");
f01b7962 618
5ab7b0b7 619 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
f01b7962
VS		 620 if (clock->m1 <= clock->m2)
621 INTELPllInvalid("m1 <= m2\n");
622
5ab7b0b7 623 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
f01b7962
VS		 624 if (clock->p < limit->p.min || limit->p.max < clock->p)
625 INTELPllInvalid("p out of range\n");
626 if (clock->m < limit->m.min || limit->m.max < clock->m)
627 INTELPllInvalid("m out of range\n");
628 }
629
79e53945 630 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 631 INTELPllInvalid("vco out of range\n");
79e53945
JB		 632 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
633 * connector, etc., rather than just a single range.
634 */
635 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 636 INTELPllInvalid("dot out of range\n");
79e53945
JB		 637
638 return true;
639}
640
d4906093 641static bool
a93e255f
ACO		 642i9xx_find_best_dpll(const intel_limit_t *limit,
643 struct intel_crtc_state *crtc_state,
cec2f356
SP		 644 int target, int refclk, intel_clock_t *match_clock,
645 intel_clock_t *best_clock)
79e53945 646{
a93e255f 647 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 648 struct drm_device *dev = crtc->base.dev;
79e53945 649 intel_clock_t clock;
79e53945
JB		 650 int err = target;
651
a93e255f 652 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 653 /*
a210b028
DV		 654 * For LVDS just rely on its current settings for dual-channel.
655 * We haven't figured out how to reliably set up different
656 * single/dual channel state, if we even can.
79e53945 657 */
1974cad0 658 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 659 clock.p2 = limit->p2.p2_fast;
660 else
661 clock.p2 = limit->p2.p2_slow;
662 } else {
663 if (target < limit->p2.dot_limit)
664 clock.p2 = limit->p2.p2_slow;
665 else
666 clock.p2 = limit->p2.p2_fast;
667 }
668
0206e353 669 memset(best_clock, 0, sizeof(*best_clock));
79e53945 670
42158660
ZY		 671 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
672 clock.m1++) {
673 for (clock.m2 = limit->m2.min;
674 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 675 if (clock.m2 >= clock.m1)
42158660
ZY		 676 break;
677 for (clock.n = limit->n.min;
678 clock.n <= limit->n.max; clock.n++) {
679 for (clock.p1 = limit->p1.min;
680 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 681 int this_err;
682
ac58c3f0
DV		 683 i9xx_clock(refclk, &clock);
684 if (!intel_PLL_is_valid(dev, limit,
685 &clock))
686 continue;
687 if (match_clock &&
688 clock.p != match_clock->p)
689 continue;
690
691 this_err = abs(clock.dot - target);
692 if (this_err < err) {
693 *best_clock = clock;
694 err = this_err;
695 }
696 }
697 }
698 }
699 }
700
701 return (err != target);
702}
703
704static bool
a93e255f
ACO		 705pnv_find_best_dpll(const intel_limit_t *limit,
706 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 707 int target, int refclk, intel_clock_t *match_clock,
708 intel_clock_t *best_clock)
79e53945 709{
a93e255f 710 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 711 struct drm_device *dev = crtc->base.dev;
79e53945 712 intel_clock_t clock;
79e53945
JB		 713 int err = target;
714
a93e255f 715 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 716 /*
a210b028
DV		 717 * For LVDS just rely on its current settings for dual-channel.
718 * We haven't figured out how to reliably set up different
719 * single/dual channel state, if we even can.
79e53945 720 */
1974cad0 721 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 722 clock.p2 = limit->p2.p2_fast;
723 else
724 clock.p2 = limit->p2.p2_slow;
725 } else {
726 if (target < limit->p2.dot_limit)
727 clock.p2 = limit->p2.p2_slow;
728 else
729 clock.p2 = limit->p2.p2_fast;
730 }
731
0206e353 732 memset(best_clock, 0, sizeof(*best_clock));
79e53945 733
42158660
ZY		 734 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
735 clock.m1++) {
736 for (clock.m2 = limit->m2.min;
737 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 738 for (clock.n = limit->n.min;
739 clock.n <= limit->n.max; clock.n++) {
740 for (clock.p1 = limit->p1.min;
741 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 742 int this_err;
743
ac58c3f0 744 pineview_clock(refclk, &clock);
1b894b59
CW		 745 if (!intel_PLL_is_valid(dev, limit,
746 &clock))
79e53945 747 continue;
cec2f356
SP		 748 if (match_clock &&
749 clock.p != match_clock->p)
750 continue;
79e53945
JB		 751
752 this_err = abs(clock.dot - target);
753 if (this_err < err) {
754 *best_clock = clock;
755 err = this_err;
756 }
757 }
758 }
759 }
760 }
761
762 return (err != target);
763}
764
d4906093 765static bool
a93e255f
ACO		 766g4x_find_best_dpll(const intel_limit_t *limit,
767 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 768 int target, int refclk, intel_clock_t *match_clock,
769 intel_clock_t *best_clock)
d4906093 770{
a93e255f 771 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 772 struct drm_device *dev = crtc->base.dev;
d4906093
ML		 773 intel_clock_t clock;
774 int max_n;
775 bool found;
6ba770dc
AJ		 776 /* approximately equals target * 0.00585 */
777 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 778 found = false;
779
a93e255f 780 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 781 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 782 clock.p2 = limit->p2.p2_fast;
783 else
784 clock.p2 = limit->p2.p2_slow;
785 } else {
786 if (target < limit->p2.dot_limit)
787 clock.p2 = limit->p2.p2_slow;
788 else
789 clock.p2 = limit->p2.p2_fast;
790 }
791
792 memset(best_clock, 0, sizeof(*best_clock));
793 max_n = limit->n.max;
f77f13e2 794 /* based on hardware requirement, prefer smaller n to precision */
d4906093 795 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 796 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 797 for (clock.m1 = limit->m1.max;
798 clock.m1 >= limit->m1.min; clock.m1--) {
799 for (clock.m2 = limit->m2.max;
800 clock.m2 >= limit->m2.min; clock.m2--) {
801 for (clock.p1 = limit->p1.max;
802 clock.p1 >= limit->p1.min; clock.p1--) {
803 int this_err;
804
ac58c3f0 805 i9xx_clock(refclk, &clock);
1b894b59
CW		 806 if (!intel_PLL_is_valid(dev, limit,
807 &clock))
d4906093 808 continue;
1b894b59
CW		 809
810 this_err = abs(clock.dot - target);
d4906093
ML		 811 if (this_err < err_most) {
812 *best_clock = clock;
813 err_most = this_err;
814 max_n = clock.n;
815 found = true;
816 }
817 }
818 }
819 }
820 }
2c07245f
ZW		 821 return found;
822}
823
d5dd62bd
ID		 824/*
825 * Check if the calculated PLL configuration is more optimal compared to the
826 * best configuration and error found so far. Return the calculated error.
827 */
828static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
829 const intel_clock_t *calculated_clock,
830 const intel_clock_t *best_clock,
831 unsigned int best_error_ppm,
832 unsigned int *error_ppm)
833{
9ca3ba01
ID		 834 /*
835 * For CHV ignore the error and consider only the P value.
836 * Prefer a bigger P value based on HW requirements.
837 */
838 if (IS_CHERRYVIEW(dev)) {
839 *error_ppm = 0;
840
841 return calculated_clock->p > best_clock->p;
842 }
843
24be4e46
ID		 844 if (WARN_ON_ONCE(!target_freq))
845 return false;
846
d5dd62bd
ID		 847 *error_ppm = div_u64(1000000ULL *
848 abs(target_freq - calculated_clock->dot),
849 target_freq);
850 /*
851 * Prefer a better P value over a better (smaller) error if the error
852 * is small. Ensure this preference for future configurations too by
853 * setting the error to 0.
854 */
855 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
856 *error_ppm = 0;
857
858 return true;
859 }
860
861 return *error_ppm + 10 < best_error_ppm;
862}
863
a0c4da24 864static bool
a93e255f
ACO		 865vlv_find_best_dpll(const intel_limit_t *limit,
866 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 867 int target, int refclk, intel_clock_t *match_clock,
868 intel_clock_t *best_clock)
a0c4da24 869{
a93e255f 870 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 871 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 872 intel_clock_t clock;
69e4f900 873 unsigned int bestppm = 1000000;
27e639bf
VS		 874 /* min update 19.2 MHz */
875 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 876 bool found = false;
a0c4da24 877
6b4bf1c4
VS		 878 target *= 5; /* fast clock */
879
880 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 881
882 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 883 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 884 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 885 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 886 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 887 clock.p = clock.p1 * clock.p2;
a0c4da24 888 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 889 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 890 unsigned int ppm;
69e4f900 891
6b4bf1c4
VS		 892 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
893 refclk * clock.m1);
894
895 vlv_clock(refclk, &clock);
43b0ac53 896
f01b7962
VS		 897 if (!intel_PLL_is_valid(dev, limit,
898 &clock))
43b0ac53
VS		 899 continue;
900
d5dd62bd
ID		 901 if (!vlv_PLL_is_optimal(dev, target,
902 &clock,
903 best_clock,
904 bestppm, &ppm))
905 continue;
6b4bf1c4 906
d5dd62bd
ID		 907 *best_clock = clock;
908 bestppm = ppm;
909 found = true;
a0c4da24
JB		 910 }
911 }
912 }
913 }
a0c4da24 914
49e497ef 915 return found;
a0c4da24 916}
a4fc5ed6 917
ef9348c8 918static bool
a93e255f
ACO		 919chv_find_best_dpll(const intel_limit_t *limit,
920 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 921 int target, int refclk, intel_clock_t *match_clock,
922 intel_clock_t *best_clock)
923{
a93e255f 924 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 925 struct drm_device *dev = crtc->base.dev;
9ca3ba01 926 unsigned int best_error_ppm;
ef9348c8
CML		 927 intel_clock_t clock;
928 uint64_t m2;
929 int found = false;
930
931 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 932 best_error_ppm = 1000000;
ef9348c8
CML		 933
934 /*
935 * Based on hardware doc, the n always set to 1, and m1 always
936 * set to 2. If requires to support 200Mhz refclk, we need to
937 * revisit this because n may not 1 anymore.
938 */
939 clock.n = 1, clock.m1 = 2;
940 target *= 5; /* fast clock */
941
942 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
943 for (clock.p2 = limit->p2.p2_fast;
944 clock.p2 >= limit->p2.p2_slow;
945 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 946 unsigned int error_ppm;
ef9348c8
CML		 947
948 clock.p = clock.p1 * clock.p2;
949
950 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
951 clock.n) << 22, refclk * clock.m1);
952
953 if (m2 > INT_MAX/clock.m1)
954 continue;
955
956 clock.m2 = m2;
957
958 chv_clock(refclk, &clock);
959
960 if (!intel_PLL_is_valid(dev, limit, &clock))
961 continue;
962
9ca3ba01
ID		 963 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
964 best_error_ppm, &error_ppm))
965 continue;
966
967 *best_clock = clock;
968 best_error_ppm = error_ppm;
969 found = true;
ef9348c8
CML		 970 }
971 }
972
973 return found;
974}
975
5ab7b0b7
ID		 976bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
977 intel_clock_t *best_clock)
978{
979 int refclk = i9xx_get_refclk(crtc_state, 0);
980
981 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
982 target_clock, refclk, NULL, best_clock);
983}
984
20ddf665
VS		 985bool intel_crtc_active(struct drm_crtc *crtc)
986{
987 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
988
989 /* Be paranoid as we can arrive here with only partial
990 * state retrieved from the hardware during setup.
991 *
241bfc38 992 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 993 * as Haswell has gained clock readout/fastboot support.
994 *
66e514c1 995 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 996 * properly reconstruct framebuffers.
c3d1f436
MR		 997 *
998 * FIXME: The intel_crtc->active here should be switched to
999 * crtc->state->active once we have proper CRTC states wired up
1000 * for atomic.
20ddf665 1001 */
c3d1f436 1002 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 1003 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 1004}
1005
a5c961d1
PZ		 1006enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1007 enum pipe pipe)
1008{
1009 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011
6e3c9717 1012 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 1013}
1014
fbf49ea2
VS		 1015static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1016{
1017 struct drm_i915_private *dev_priv = dev->dev_private;
1018 u32 reg = PIPEDSL(pipe);
1019 u32 line1, line2;
1020 u32 line_mask;
1021
1022 if (IS_GEN2(dev))
1023 line_mask = DSL_LINEMASK_GEN2;
1024 else
1025 line_mask = DSL_LINEMASK_GEN3;
1026
1027 line1 = I915_READ(reg) & line_mask;
1028 mdelay(5);
1029 line2 = I915_READ(reg) & line_mask;
1030
1031 return line1 == line2;
1032}
1033
ab7ad7f6
KP		 1034/*
1035 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1036 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1037 *
1038 * After disabling a pipe, we can't wait for vblank in the usual way,
1039 * spinning on the vblank interrupt status bit, since we won't actually
1040 * see an interrupt when the pipe is disabled.
1041 *
ab7ad7f6
KP		 1042 * On Gen4 and above:
1043 * wait for the pipe register state bit to turn off
1044 *
1045 * Otherwise:
1046 * wait for the display line value to settle (it usually
1047 * ends up stopping at the start of the next frame).
58e10eb9 1048 *
9d0498a2 1049 */
575f7ab7 1050static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1051{
575f7ab7 1052 struct drm_device *dev = crtc->base.dev;
9d0498a2 1053 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1054 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1055 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1056
1057 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1058 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1059
1060 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1061 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1062 100))
284637d9 1063 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1064 } else {
ab7ad7f6 1065 /* Wait for the display line to settle */
fbf49ea2 1066 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1067 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1068 }
79e53945
JB		 1069}
1070
b0ea7d37
DL		 1071/*
1072 * ibx_digital_port_connected - is the specified port connected?
1073 * @dev_priv: i915 private structure
1074 * @port: the port to test
1075 *
1076 * Returns true if @port is connected, false otherwise.
1077 */
1078bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1079 struct intel_digital_port *port)
1080{
1081 u32 bit;
1082
c36346e3 1083 if (HAS_PCH_IBX(dev_priv->dev)) {
eba905b2 1084 switch (port->port) {
c36346e3
DL		 1085 case PORT_B:
1086 bit = SDE_PORTB_HOTPLUG;
1087 break;
1088 case PORT_C:
1089 bit = SDE_PORTC_HOTPLUG;
1090 break;
1091 case PORT_D:
1092 bit = SDE_PORTD_HOTPLUG;
1093 break;
1094 default:
1095 return true;
1096 }
1097 } else {
eba905b2 1098 switch (port->port) {
c36346e3
DL		 1099 case PORT_B:
1100 bit = SDE_PORTB_HOTPLUG_CPT;
1101 break;
1102 case PORT_C:
1103 bit = SDE_PORTC_HOTPLUG_CPT;
1104 break;
1105 case PORT_D:
1106 bit = SDE_PORTD_HOTPLUG_CPT;
1107 break;
1108 default:
1109 return true;
1110 }
b0ea7d37
DL		 1111 }
1112
1113 return I915_READ(SDEISR) & bit;
1114}
1115
b24e7179
JB		 1116static const char *state_string(bool enabled)
1117{
1118 return enabled ? "on" : "off";
1119}
1120
1121/* Only for pre-ILK configs */
55607e8a
DV		 1122void assert_pll(struct drm_i915_private *dev_priv,
1123 enum pipe pipe, bool state)
b24e7179
JB		 1124{
1125 int reg;
1126 u32 val;
1127 bool cur_state;
1128
1129 reg = DPLL(pipe);
1130 val = I915_READ(reg);
1131 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1132 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1133 "PLL state assertion failure (expected %s, current %s)\n",
1134 state_string(state), state_string(cur_state));
1135}
b24e7179 1136
23538ef1
JN		 1137/* XXX: the dsi pll is shared between MIPI DSI ports */
1138static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1139{
1140 u32 val;
1141 bool cur_state;
1142
a580516d 1143 mutex_lock(&dev_priv->sb_lock);
23538ef1 1144 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
a580516d 1145 mutex_unlock(&dev_priv->sb_lock);
23538ef1
JN		 1146
1147 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1148 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1149 "DSI PLL state assertion failure (expected %s, current %s)\n",
1150 state_string(state), state_string(cur_state));
1151}
1152#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1153#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1154
55607e8a 1155struct intel_shared_dpll *
e2b78267
DV		 1156intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1157{
1158 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1159
6e3c9717 1160 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1161 return NULL;
1162
6e3c9717 1163 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1164}
1165
040484af 1166/* For ILK+ */
55607e8a
DV		 1167void assert_shared_dpll(struct drm_i915_private *dev_priv,
1168 struct intel_shared_dpll *pll,
1169 bool state)
040484af 1170{
040484af 1171 bool cur_state;
5358901f 1172 struct intel_dpll_hw_state hw_state;
040484af 1173
92b27b08 1174 if (WARN (!pll,
46edb027 1175 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1176 return;
ee7b9f93 1177
5358901f 1178 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1179 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1180 "%s assertion failure (expected %s, current %s)\n",
1181 pll->name, state_string(state), state_string(cur_state));
040484af 1182}
040484af
JB		 1183
1184static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1185 enum pipe pipe, bool state)
1186{
1187 int reg;
1188 u32 val;
1189 bool cur_state;
ad80a810
PZ		 1190 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1191 pipe);
040484af 1192
affa9354
PZ		 1193 if (HAS_DDI(dev_priv->dev)) {
1194 /* DDI does not have a specific FDI_TX register */
ad80a810 1195 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1196 val = I915_READ(reg);
ad80a810 1197 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1198 } else {
1199 reg = FDI_TX_CTL(pipe);
1200 val = I915_READ(reg);
1201 cur_state = !!(val & FDI_TX_ENABLE);
1202 }
e2c719b7 1203 I915_STATE_WARN(cur_state != state,
040484af
JB		 1204 "FDI TX state assertion failure (expected %s, current %s)\n",
1205 state_string(state), state_string(cur_state));
1206}
1207#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1208#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1209
1210static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1211 enum pipe pipe, bool state)
1212{
1213 int reg;
1214 u32 val;
1215 bool cur_state;
1216
d63fa0dc
PZ		 1217 reg = FDI_RX_CTL(pipe);
1218 val = I915_READ(reg);
1219 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1220 I915_STATE_WARN(cur_state != state,
040484af
JB		 1221 "FDI RX state assertion failure (expected %s, current %s)\n",
1222 state_string(state), state_string(cur_state));
1223}
1224#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1225#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1226
1227static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1228 enum pipe pipe)
1229{
1230 int reg;
1231 u32 val;
1232
1233 /* ILK FDI PLL is always enabled */
3d13ef2e 1234 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1235 return;
1236
bf507ef7 1237 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1238 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1239 return;
1240
040484af
JB		 1241 reg = FDI_TX_CTL(pipe);
1242 val = I915_READ(reg);
e2c719b7 1243 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1244}
1245
55607e8a
DV		 1246void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1247 enum pipe pipe, bool state)
040484af
JB		 1248{
1249 int reg;
1250 u32 val;
55607e8a 1251 bool cur_state;
040484af
JB		 1252
1253 reg = FDI_RX_CTL(pipe);
1254 val = I915_READ(reg);
55607e8a 1255 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1256 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1257 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1258 state_string(state), state_string(cur_state));
040484af
JB		 1259}
1260
b680c37a
DV		 1261void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1262 enum pipe pipe)
ea0760cf 1263{
bedd4dba
JN		 1264 struct drm_device *dev = dev_priv->dev;
1265 int pp_reg;
ea0760cf
JB		 1266 u32 val;
1267 enum pipe panel_pipe = PIPE_A;
0de3b485 1268 bool locked = true;
ea0760cf 1269
bedd4dba
JN		 1270 if (WARN_ON(HAS_DDI(dev)))
1271 return;
1272
1273 if (HAS_PCH_SPLIT(dev)) {
1274 u32 port_sel;
1275
ea0760cf 1276 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1277 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1278
1279 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1280 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1281 panel_pipe = PIPE_B;
1282 /* XXX: else fix for eDP */
1283 } else if (IS_VALLEYVIEW(dev)) {
1284 /* presumably write lock depends on pipe, not port select */
1285 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1286 panel_pipe = pipe;
ea0760cf
JB		 1287 } else {
1288 pp_reg = PP_CONTROL;
bedd4dba
JN		 1289 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1290 panel_pipe = PIPE_B;
ea0760cf
JB		 1291 }
1292
1293 val = I915_READ(pp_reg);
1294 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1295 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1296 locked = false;
1297
e2c719b7 1298 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1299 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1300 pipe_name(pipe));
ea0760cf
JB		 1301}
1302
93ce0ba6
JN		 1303static void assert_cursor(struct drm_i915_private *dev_priv,
1304 enum pipe pipe, bool state)
1305{
1306 struct drm_device *dev = dev_priv->dev;
1307 bool cur_state;
1308
d9d82081 1309 if (IS_845G(dev) || IS_I865G(dev))
93ce0ba6 1310 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
d9d82081 1311 else
5efb3e28 1312 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1313
e2c719b7 1314 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1315 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1316 pipe_name(pipe), state_string(state), state_string(cur_state));
1317}
1318#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1319#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1320
b840d907
JB		 1321void assert_pipe(struct drm_i915_private *dev_priv,
1322 enum pipe pipe, bool state)
b24e7179
JB		 1323{
1324 int reg;
1325 u32 val;
63d7bbe9 1326 bool cur_state;
702e7a56
PZ		 1327 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1328 pipe);
b24e7179 1329
b6b5d049
VS		 1330 /* if we need the pipe quirk it must be always on */
1331 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1332 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1333 state = true;
1334
f458ebbc 1335 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1336 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1337 cur_state = false;
1338 } else {
1339 reg = PIPECONF(cpu_transcoder);
1340 val = I915_READ(reg);
1341 cur_state = !!(val & PIPECONF_ENABLE);
1342 }
1343
e2c719b7 1344 I915_STATE_WARN(cur_state != state,
63d7bbe9 1345 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1346 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1347}
1348
931872fc
CW		 1349static void assert_plane(struct drm_i915_private *dev_priv,
1350 enum plane plane, bool state)
b24e7179
JB		 1351{
1352 int reg;
1353 u32 val;
931872fc 1354 bool cur_state;
b24e7179
JB		 1355
1356 reg = DSPCNTR(plane);
1357 val = I915_READ(reg);
931872fc 1358 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1359 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1360 "plane %c assertion failure (expected %s, current %s)\n",
1361 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1362}
1363
931872fc
CW		 1364#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1365#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1366
b24e7179
JB		 1367static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1368 enum pipe pipe)
1369{
653e1026 1370 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1371 int reg, i;
1372 u32 val;
1373 int cur_pipe;
1374
653e1026
VS		 1375 /* Primary planes are fixed to pipes on gen4+ */
1376 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1377 reg = DSPCNTR(pipe);
1378 val = I915_READ(reg);
e2c719b7 1379 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1380 "plane %c assertion failure, should be disabled but not\n",
1381 plane_name(pipe));
19ec1358 1382 return;
28c05794 1383 }
19ec1358 1384
b24e7179 1385 /* Need to check both planes against the pipe */
055e393f 1386 for_each_pipe(dev_priv, i) {
b24e7179
JB		 1387 reg = DSPCNTR(i);
1388 val = I915_READ(reg);
1389 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1390 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1391 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1392 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1393 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1394 }
1395}
1396
19332d7a
JB		 1397static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1398 enum pipe pipe)
1399{
20674eef 1400 struct drm_device *dev = dev_priv->dev;
1fe47785 1401 int reg, sprite;
19332d7a
JB		 1402 u32 val;
1403
7feb8b88 1404 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1405 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1406 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1407 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1408 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1409 sprite, pipe_name(pipe));
1410 }
1411 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1412 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1413 reg = SPCNTR(pipe, sprite);
20674eef 1414 val = I915_READ(reg);
e2c719b7 1415 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1416 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1417 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1418 }
1419 } else if (INTEL_INFO(dev)->gen >= 7) {
1420 reg = SPRCTL(pipe);
19332d7a 1421 val = I915_READ(reg);
e2c719b7 1422 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1423 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1424 plane_name(pipe), pipe_name(pipe));
1425 } else if (INTEL_INFO(dev)->gen >= 5) {
1426 reg = DVSCNTR(pipe);
19332d7a 1427 val = I915_READ(reg);
e2c719b7 1428 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1429 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1430 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1431 }
1432}
1433
08c71e5e
VS		 1434static void assert_vblank_disabled(struct drm_crtc *crtc)
1435{
e2c719b7 1436 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1437 drm_crtc_vblank_put(crtc);
1438}
1439
89eff4be 1440static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1441{
1442 u32 val;
1443 bool enabled;
1444
e2c719b7 1445 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1446
92f2584a
JB		 1447 val = I915_READ(PCH_DREF_CONTROL);
1448 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1449 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1450 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1451}
1452
ab9412ba
DV		 1453static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1454 enum pipe pipe)
92f2584a
JB		 1455{
1456 int reg;
1457 u32 val;
1458 bool enabled;
1459
ab9412ba 1460 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1461 val = I915_READ(reg);
1462 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1463 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1464 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1465 pipe_name(pipe));
92f2584a
JB		 1466}
1467
4e634389
KP		 1468static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1469 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1470{
1471 if ((val & DP_PORT_EN) == 0)
1472 return false;
1473
1474 if (HAS_PCH_CPT(dev_priv->dev)) {
1475 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1476 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1477 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1478 return false;
44f37d1f
CML		 1479 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1480 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1481 return false;
f0575e92
KP		 1482 } else {
1483 if ((val & DP_PIPE_MASK) != (pipe << 30))
1484 return false;
1485 }
1486 return true;
1487}
1488
1519b995
KP		 1489static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1490 enum pipe pipe, u32 val)
1491{
dc0fa718 1492 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1493 return false;
1494
1495 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1496 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1497 return false;
44f37d1f
CML		 1498 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1499 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1500 return false;
1519b995 1501 } else {
dc0fa718 1502 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1503 return false;
1504 }
1505 return true;
1506}
1507
1508static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1509 enum pipe pipe, u32 val)
1510{
1511 if ((val & LVDS_PORT_EN) == 0)
1512 return false;
1513
1514 if (HAS_PCH_CPT(dev_priv->dev)) {
1515 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1516 return false;
1517 } else {
1518 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1519 return false;
1520 }
1521 return true;
1522}
1523
1524static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1525 enum pipe pipe, u32 val)
1526{
1527 if ((val & ADPA_DAC_ENABLE) == 0)
1528 return false;
1529 if (HAS_PCH_CPT(dev_priv->dev)) {
1530 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1531 return false;
1532 } else {
1533 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1534 return false;
1535 }
1536 return true;
1537}
1538
291906f1 1539static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1540 enum pipe pipe, int reg, u32 port_sel)
291906f1 1541{
47a05eca 1542 u32 val = I915_READ(reg);
e2c719b7 1543 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1544 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1545 reg, pipe_name(pipe));
de9a35ab 1546
e2c719b7 1547 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1548 && (val & DP_PIPEB_SELECT),
de9a35ab 1549 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1550}
1551
1552static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1553 enum pipe pipe, int reg)
1554{
47a05eca 1555 u32 val = I915_READ(reg);
e2c719b7 1556 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1557 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1558 reg, pipe_name(pipe));
de9a35ab 1559
e2c719b7 1560 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1561 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1562 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1563}
1564
1565static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1566 enum pipe pipe)
1567{
1568 int reg;
1569 u32 val;
291906f1 1570
f0575e92
KP		 1571 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1572 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1573 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1574
1575 reg = PCH_ADPA;
1576 val = I915_READ(reg);
e2c719b7 1577 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1578 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1579 pipe_name(pipe));
291906f1
JB		 1580
1581 reg = PCH_LVDS;
1582 val = I915_READ(reg);
e2c719b7 1583 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1584 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1585 pipe_name(pipe));
291906f1 1586
e2debe91
PZ		 1587 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1588 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1589 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1590}
1591
40e9cf64
JB		 1592static void intel_init_dpio(struct drm_device *dev)
1593{
1594 struct drm_i915_private *dev_priv = dev->dev_private;
1595
1596 if (!IS_VALLEYVIEW(dev))
1597 return;
1598
a09caddd
CML		 1599 /*
1600 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1601 * CHV x1 PHY (DP/HDMI D)
1602 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1603 */
1604 if (IS_CHERRYVIEW(dev)) {
1605 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1606 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1607 } else {
1608 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1609 }
5382f5f3
JB		 1610}
1611
d288f65f 1612static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1613 const struct intel_crtc_state *pipe_config)
87442f73 1614{
426115cf
DV		 1615 struct drm_device *dev = crtc->base.dev;
1616 struct drm_i915_private *dev_priv = dev->dev_private;
1617 int reg = DPLL(crtc->pipe);
d288f65f 1618 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1619
426115cf 1620 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1621
1622 /* No really, not for ILK+ */
1623 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1624
1625 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1626 if (IS_MOBILE(dev_priv->dev))
426115cf 1627 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1628
426115cf
DV		 1629 I915_WRITE(reg, dpll);
1630 POSTING_READ(reg);
1631 udelay(150);
1632
1633 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1634 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1635
d288f65f 1636 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1637 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1638
1639 /* We do this three times for luck */
426115cf 1640 I915_WRITE(reg, dpll);
87442f73
DV		 1641 POSTING_READ(reg);
1642 udelay(150); /* wait for warmup */
426115cf 1643 I915_WRITE(reg, dpll);
87442f73
DV		 1644 POSTING_READ(reg);
1645 udelay(150); /* wait for warmup */
426115cf 1646 I915_WRITE(reg, dpll);
87442f73
DV		 1647 POSTING_READ(reg);
1648 udelay(150); /* wait for warmup */
1649}
1650
d288f65f 1651static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1652 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1653{
1654 struct drm_device *dev = crtc->base.dev;
1655 struct drm_i915_private *dev_priv = dev->dev_private;
1656 int pipe = crtc->pipe;
1657 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1658 u32 tmp;
1659
1660 assert_pipe_disabled(dev_priv, crtc->pipe);
1661
1662 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1663
a580516d 1664 mutex_lock(&dev_priv->sb_lock);
9d556c99
CML		 1665
1666 /* Enable back the 10bit clock to display controller */
1667 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1668 tmp |= DPIO_DCLKP_EN;
1669 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1670
54433e91
VS		 1671 mutex_unlock(&dev_priv->sb_lock);
1672
9d556c99
CML		 1673 /*
1674 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1675 */
1676 udelay(1);
1677
1678 /* Enable PLL */
d288f65f 1679 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1680
1681 /* Check PLL is locked */
a11b0703 1682 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1683 DRM_ERROR("PLL %d failed to lock\n", pipe);
1684
a11b0703 1685 /* not sure when this should be written */
d288f65f 1686 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703 1687 POSTING_READ(DPLL_MD(pipe));
9d556c99
CML		 1688}
1689
1c4e0274
VS		 1690static int intel_num_dvo_pipes(struct drm_device *dev)
1691{
1692 struct intel_crtc *crtc;
1693 int count = 0;
1694
1695 for_each_intel_crtc(dev, crtc)
1696 count += crtc->active &&
409ee761 1697 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1698
1699 return count;
1700}
1701
66e3d5c0 1702static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1703{
66e3d5c0
DV		 1704 struct drm_device *dev = crtc->base.dev;
1705 struct drm_i915_private *dev_priv = dev->dev_private;
1706 int reg = DPLL(crtc->pipe);
6e3c9717 1707 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1708
66e3d5c0 1709 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1710
63d7bbe9 1711 /* No really, not for ILK+ */
3d13ef2e 1712 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1713
1714 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1715 if (IS_MOBILE(dev) && !IS_I830(dev))
1716 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1717
1c4e0274
VS		 1718 /* Enable DVO 2x clock on both PLLs if necessary */
1719 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1720 /*
1721 * It appears to be important that we don't enable this
1722 * for the current pipe before otherwise configuring the
1723 * PLL. No idea how this should be handled if multiple
1724 * DVO outputs are enabled simultaneosly.
1725 */
1726 dpll |= DPLL_DVO_2X_MODE;
1727 I915_WRITE(DPLL(!crtc->pipe),
1728 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1729 }
66e3d5c0
DV		 1730
1731 /* Wait for the clocks to stabilize. */
1732 POSTING_READ(reg);
1733 udelay(150);
1734
1735 if (INTEL_INFO(dev)->gen >= 4) {
1736 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1737 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1738 } else {
1739 /* The pixel multiplier can only be updated once the
1740 * DPLL is enabled and the clocks are stable.
1741 *
1742 * So write it again.
1743 */
1744 I915_WRITE(reg, dpll);
1745 }
63d7bbe9
JB		 1746
1747 /* We do this three times for luck */
66e3d5c0 1748 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1749 POSTING_READ(reg);
1750 udelay(150); /* wait for warmup */
66e3d5c0 1751 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1752 POSTING_READ(reg);
1753 udelay(150); /* wait for warmup */
66e3d5c0 1754 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1755 POSTING_READ(reg);
1756 udelay(150); /* wait for warmup */
1757}
1758
1759/**
50b44a44 1760 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1761 * @dev_priv: i915 private structure
1762 * @pipe: pipe PLL to disable
1763 *
1764 * Disable the PLL for @pipe, making sure the pipe is off first.
1765 *
1766 * Note! This is for pre-ILK only.
1767 */
1c4e0274 1768static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1769{
1c4e0274
VS		 1770 struct drm_device *dev = crtc->base.dev;
1771 struct drm_i915_private *dev_priv = dev->dev_private;
1772 enum pipe pipe = crtc->pipe;
1773
1774 /* Disable DVO 2x clock on both PLLs if necessary */
1775 if (IS_I830(dev) &&
409ee761 1776 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1c4e0274
VS		 1777 intel_num_dvo_pipes(dev) == 1) {
1778 I915_WRITE(DPLL(PIPE_B),
1779 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1780 I915_WRITE(DPLL(PIPE_A),
1781 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1782 }
1783
b6b5d049
VS		 1784 /* Don't disable pipe or pipe PLLs if needed */
1785 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1786 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1787 return;
1788
1789 /* Make sure the pipe isn't still relying on us */
1790 assert_pipe_disabled(dev_priv, pipe);
1791
50b44a44
DV		 1792 I915_WRITE(DPLL(pipe), 0);
1793 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1794}
1795
f6071166
JB		 1796static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1797{
1798 u32 val = 0;
1799
1800 /* Make sure the pipe isn't still relying on us */
1801 assert_pipe_disabled(dev_priv, pipe);
1802
e5cbfbfb
ID		 1803 /*
1804 * Leave integrated clock source and reference clock enabled for pipe B.
1805 * The latter is needed for VGA hotplug / manual detection.
1806 */
f6071166 1807 if (pipe == PIPE_B)
e5cbfbfb 1808 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
f6071166
JB		 1809 I915_WRITE(DPLL(pipe), val);
1810 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1811
1812}
1813
1814static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1815{
d752048d 1816 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1817 u32 val;
1818
a11b0703
VS		 1819 /* Make sure the pipe isn't still relying on us */
1820 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1821
a11b0703 1822 /* Set PLL en = 0 */
d17ec4ce 1823 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
a11b0703
VS		 1824 if (pipe != PIPE_A)
1825 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1826 I915_WRITE(DPLL(pipe), val);
1827 POSTING_READ(DPLL(pipe));
d752048d 1828
a580516d 1829 mutex_lock(&dev_priv->sb_lock);
d752048d
VS		 1830
1831 /* Disable 10bit clock to display controller */
1832 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1833 val &= ~DPIO_DCLKP_EN;
1834 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1835
61407f6d
VS		 1836 /* disable left/right clock distribution */
1837 if (pipe != PIPE_B) {
1838 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1839 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1840 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1841 } else {
1842 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1843 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1844 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1845 }
1846
a580516d 1847 mutex_unlock(&dev_priv->sb_lock);
f6071166
JB		 1848}
1849
e4607fcf 1850void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
9b6de0a1
VS		 1851 struct intel_digital_port *dport,
1852 unsigned int expected_mask)
89b667f8
JB		 1853{
1854 u32 port_mask;
00fc31b7 1855 int dpll_reg;
89b667f8 1856
e4607fcf
CML		 1857 switch (dport->port) {
1858 case PORT_B:
89b667f8 1859 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1860 dpll_reg = DPLL(0);
e4607fcf
CML		 1861 break;
1862 case PORT_C:
89b667f8 1863 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7 1864 dpll_reg = DPLL(0);
9b6de0a1 1865 expected_mask <<= 4;
00fc31b7
CML		 1866 break;
1867 case PORT_D:
1868 port_mask = DPLL_PORTD_READY_MASK;
1869 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1870 break;
1871 default:
1872 BUG();
1873 }
89b667f8 1874
9b6de0a1
VS		 1875 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1876 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1877 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
89b667f8
JB		 1878}
1879
b14b1055
DV		 1880static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1881{
1882 struct drm_device *dev = crtc->base.dev;
1883 struct drm_i915_private *dev_priv = dev->dev_private;
1884 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1885
be19f0ff
CW		 1886 if (WARN_ON(pll == NULL))
1887 return;
1888
3e369b76 1889 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1890 if (pll->active == 0) {
1891 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1892 WARN_ON(pll->on);
1893 assert_shared_dpll_disabled(dev_priv, pll);
1894
1895 pll->mode_set(dev_priv, pll);
1896 }
1897}
1898
92f2584a 1899/**
85b3894f 1900 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1901 * @dev_priv: i915 private structure
1902 * @pipe: pipe PLL to enable
1903 *
1904 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1905 * drives the transcoder clock.
1906 */
85b3894f 1907static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1908{
3d13ef2e
DL		 1909 struct drm_device *dev = crtc->base.dev;
1910 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1911 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1912
87a875bb 1913 if (WARN_ON(pll == NULL))
48da64a8
CW		 1914 return;
1915
3e369b76 1916 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1917 return;
ee7b9f93 1918
74dd6928 1919 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1920 pll->name, pll->active, pll->on,
e2b78267 1921 crtc->base.base.id);
92f2584a 1922
cdbd2316
DV		 1923 if (pll->active++) {
1924 WARN_ON(!pll->on);
e9d6944e 1925 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1926 return;
1927 }
f4a091c7 1928 WARN_ON(pll->on);
ee7b9f93 1929
bd2bb1b9
PZ		 1930 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1931
46edb027 1932 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1933 pll->enable(dev_priv, pll);
ee7b9f93 1934 pll->on = true;
92f2584a
JB		 1935}
1936
f6daaec2 1937static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1938{
3d13ef2e
DL		 1939 struct drm_device *dev = crtc->base.dev;
1940 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1941 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1942
92f2584a 1943 /* PCH only available on ILK+ */
3d13ef2e 1944 BUG_ON(INTEL_INFO(dev)->gen < 5);
87a875bb 1945 if (WARN_ON(pll == NULL))
ee7b9f93 1946 return;
92f2584a 1947
3e369b76 1948 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1949 return;
7a419866 1950
46edb027
DV		 1951 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1952 pll->name, pll->active, pll->on,
e2b78267 1953 crtc->base.base.id);
7a419866 1954
48da64a8 1955 if (WARN_ON(pll->active == 0)) {
e9d6944e 1956 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1957 return;
1958 }
1959
e9d6944e 1960 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1961 WARN_ON(!pll->on);
cdbd2316 1962 if (--pll->active)
7a419866 1963 return;
ee7b9f93 1964
46edb027 1965 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1966 pll->disable(dev_priv, pll);
ee7b9f93 1967 pll->on = false;
bd2bb1b9
PZ		 1968
1969 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1970}
1971
b8a4f404
PZ		 1972static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1973 enum pipe pipe)
040484af 1974{
23670b32 1975 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1976 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1977 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1978 uint32_t reg, val, pipeconf_val;
040484af
JB		 1979
1980 /* PCH only available on ILK+ */
55522f37 1981 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1982
1983 /* Make sure PCH DPLL is enabled */
e72f9fbf 1984 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1985 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1986
1987 /* FDI must be feeding us bits for PCH ports */
1988 assert_fdi_tx_enabled(dev_priv, pipe);
1989 assert_fdi_rx_enabled(dev_priv, pipe);
1990
23670b32
DV		 1991 if (HAS_PCH_CPT(dev)) {
1992 /* Workaround: Set the timing override bit before enabling the
1993 * pch transcoder. */
1994 reg = TRANS_CHICKEN2(pipe);
1995 val = I915_READ(reg);
1996 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1997 I915_WRITE(reg, val);
59c859d6 1998 }
23670b32 1999
ab9412ba 2000 reg = PCH_TRANSCONF(pipe);
040484af 2001 val = I915_READ(reg);
5f7f726d 2002 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 2003
2004 if (HAS_PCH_IBX(dev_priv->dev)) {
2005 /*
2006 * make the BPC in transcoder be consistent with
2007 * that in pipeconf reg.
2008 */
dfd07d72
DV		 2009 val &= ~PIPECONF_BPC_MASK;
2010 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 2011 }
5f7f726d
PZ		 2012
2013 val &= ~TRANS_INTERLACE_MASK;
2014 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 2015 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 2016 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 2017 val |= TRANS_LEGACY_INTERLACED_ILK;
2018 else
2019 val |= TRANS_INTERLACED;
5f7f726d
PZ		 2020 else
2021 val |= TRANS_PROGRESSIVE;
2022
040484af
JB		 2023 I915_WRITE(reg, val | TRANS_ENABLE);
2024 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 2025 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 2026}
2027
8fb033d7 2028static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 2029 enum transcoder cpu_transcoder)
040484af 2030{
8fb033d7 2031 u32 val, pipeconf_val;
8fb033d7
PZ		 2032
2033 /* PCH only available on ILK+ */
55522f37 2034 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 2035
8fb033d7 2036 /* FDI must be feeding us bits for PCH ports */
1a240d4d 2037 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2038 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2039
223a6fdf
PZ		 2040 /* Workaround: set timing override bit. */
2041 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2042 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 2043 I915_WRITE(_TRANSA_CHICKEN2, val);
2044
25f3ef11 2045 val = TRANS_ENABLE;
937bb610 2046 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2047
9a76b1c6
PZ		 2048 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2049 PIPECONF_INTERLACED_ILK)
a35f2679 2050 val |= TRANS_INTERLACED;
8fb033d7
PZ		 2051 else
2052 val |= TRANS_PROGRESSIVE;
2053
ab9412ba
DV		 2054 I915_WRITE(LPT_TRANSCONF, val);
2055 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2056 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 2057}
2058
b8a4f404
PZ		 2059static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2060 enum pipe pipe)
040484af 2061{
23670b32
DV		 2062 struct drm_device *dev = dev_priv->dev;
2063 uint32_t reg, val;
040484af
JB		 2064
2065 /* FDI relies on the transcoder */
2066 assert_fdi_tx_disabled(dev_priv, pipe);
2067 assert_fdi_rx_disabled(dev_priv, pipe);
2068
291906f1
JB		 2069 /* Ports must be off as well */
2070 assert_pch_ports_disabled(dev_priv, pipe);
2071
ab9412ba 2072 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2073 val = I915_READ(reg);
2074 val &= ~TRANS_ENABLE;
2075 I915_WRITE(reg, val);
2076 /* wait for PCH transcoder off, transcoder state */
2077 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2078 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2079
2080 if (!HAS_PCH_IBX(dev)) {
2081 /* Workaround: Clear the timing override chicken bit again. */
2082 reg = TRANS_CHICKEN2(pipe);
2083 val = I915_READ(reg);
2084 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2085 I915_WRITE(reg, val);
2086 }
040484af
JB		 2087}
2088
ab4d966c 2089static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2090{
8fb033d7
PZ		 2091 u32 val;
2092
ab9412ba 2093 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2094 val &= ~TRANS_ENABLE;
ab9412ba 2095 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2096 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2097 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2098 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2099
2100 /* Workaround: clear timing override bit. */
2101 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2102 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 2103 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 2104}
2105
b24e7179 2106/**
309cfea8 2107 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2108 * @crtc: crtc responsible for the pipe
b24e7179 2109 *
0372264a 2110 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2111 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2112 */
e1fdc473 2113static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2114{
0372264a
PZ		 2115 struct drm_device *dev = crtc->base.dev;
2116 struct drm_i915_private *dev_priv = dev->dev_private;
2117 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2118 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2119 pipe);
1a240d4d 2120 enum pipe pch_transcoder;
b24e7179
JB		 2121 int reg;
2122 u32 val;
2123
58c6eaa2 2124 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2125 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2126 assert_sprites_disabled(dev_priv, pipe);
2127
681e5811 2128 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2129 pch_transcoder = TRANSCODER_A;
2130 else
2131 pch_transcoder = pipe;
2132
b24e7179
JB		 2133 /*
2134 * A pipe without a PLL won't actually be able to drive bits from
2135 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2136 * need the check.
2137 */
50360403 2138 if (HAS_GMCH_DISPLAY(dev_priv->dev))
409ee761 2139 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2140 assert_dsi_pll_enabled(dev_priv);
2141 else
2142 assert_pll_enabled(dev_priv, pipe);
040484af 2143 else {
6e3c9717 2144 if (crtc->config->has_pch_encoder) {
040484af 2145 /* if driving the PCH, we need FDI enabled */
cc391bbb 2146 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2147 assert_fdi_tx_pll_enabled(dev_priv,
2148 (enum pipe) cpu_transcoder);
040484af
JB		 2149 }
2150 /* FIXME: assert CPU port conditions for SNB+ */
2151 }
b24e7179 2152
702e7a56 2153 reg = PIPECONF(cpu_transcoder);
b24e7179 2154 val = I915_READ(reg);
7ad25d48 2155 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2156 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2157 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2158 return;
7ad25d48 2159 }
00d70b15
CW		 2160
2161 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2162 POSTING_READ(reg);
b24e7179
JB		 2163}
2164
2165/**
309cfea8 2166 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2167 * @crtc: crtc whose pipes is to be disabled
b24e7179 2168 *
575f7ab7
VS		 2169 * Disable the pipe of @crtc, making sure that various hardware
2170 * specific requirements are met, if applicable, e.g. plane
2171 * disabled, panel fitter off, etc.
b24e7179
JB		 2172 *
2173 * Will wait until the pipe has shut down before returning.
2174 */
575f7ab7 2175static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2176{
575f7ab7 2177 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2178 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2179 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2180 int reg;
2181 u32 val;
2182
2183 /*
2184 * Make sure planes won't keep trying to pump pixels to us,
2185 * or we might hang the display.
2186 */
2187 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2188 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2189 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2190
702e7a56 2191 reg = PIPECONF(cpu_transcoder);
b24e7179 2192 val = I915_READ(reg);
00d70b15
CW		 2193 if ((val & PIPECONF_ENABLE) == 0)
2194 return;
2195
67adc644
VS		 2196 /*
2197 * Double wide has implications for planes
2198 * so best keep it disabled when not needed.
2199 */
6e3c9717 2200 if (crtc->config->double_wide)
67adc644
VS		 2201 val &= ~PIPECONF_DOUBLE_WIDE;
2202
2203 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2204 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2205 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2206 val &= ~PIPECONF_ENABLE;
2207
2208 I915_WRITE(reg, val);
2209 if ((val & PIPECONF_ENABLE) == 0)
2210 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2211}
2212
2213/**
262ca2b0 2214 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
fdd508a6
VS		 2215 * @plane: plane to be enabled
2216 * @crtc: crtc for the plane
b24e7179 2217 *
fdd508a6 2218 * Enable @plane on @crtc, making sure that the pipe is running first.
b24e7179 2219 */
fdd508a6
VS		 2220static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2221 struct drm_crtc *crtc)
b24e7179 2222{
fdd508a6
VS		 2223 struct drm_device *dev = plane->dev;
2224 struct drm_i915_private *dev_priv = dev->dev_private;
2225 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b24e7179
JB		 2226
2227 /* If the pipe isn't enabled, we can't pump pixels and may hang */
fdd508a6 2228 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
b70709a6 2229 to_intel_plane_state(plane->state)->visible = true;
939c2fe8 2230
fdd508a6
VS		 2231 dev_priv->display.update_primary_plane(crtc, plane->fb,
2232 crtc->x, crtc->y);
b24e7179
JB		 2233}
2234
693db184
CW		 2235static bool need_vtd_wa(struct drm_device *dev)
2236{
2237#ifdef CONFIG_INTEL_IOMMU
2238 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2239 return true;
2240#endif
2241 return false;
2242}
2243
50470bb0 2244unsigned int
6761dd31
TU		 2245intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2246 uint64_t fb_format_modifier)
a57ce0b2 2247{
6761dd31
TU		 2248 unsigned int tile_height;
2249 uint32_t pixel_bytes;
a57ce0b2 2250
b5d0e9bf
DL		 2251 switch (fb_format_modifier) {
2252 case DRM_FORMAT_MOD_NONE:
2253 tile_height = 1;
2254 break;
2255 case I915_FORMAT_MOD_X_TILED:
2256 tile_height = IS_GEN2(dev) ? 16 : 8;
2257 break;
2258 case I915_FORMAT_MOD_Y_TILED:
2259 tile_height = 32;
2260 break;
2261 case I915_FORMAT_MOD_Yf_TILED:
6761dd31
TU		 2262 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2263 switch (pixel_bytes) {
b5d0e9bf 2264 default:
6761dd31 2265 case 1:
b5d0e9bf
DL		 2266 tile_height = 64;
2267 break;
6761dd31
TU		 2268 case 2:
2269 case 4:
b5d0e9bf
DL		 2270 tile_height = 32;
2271 break;
6761dd31 2272 case 8:
b5d0e9bf
DL		 2273 tile_height = 16;
2274 break;
6761dd31 2275 case 16:
b5d0e9bf
DL		 2276 WARN_ONCE(1,
2277 "128-bit pixels are not supported for display!");
2278 tile_height = 16;
2279 break;
2280 }
2281 break;
2282 default:
2283 MISSING_CASE(fb_format_modifier);
2284 tile_height = 1;
2285 break;
2286 }
091df6cb 2287
6761dd31
TU		 2288 return tile_height;
2289}
2290
2291unsigned int
2292intel_fb_align_height(struct drm_device *dev, unsigned int height,
2293 uint32_t pixel_format, uint64_t fb_format_modifier)
2294{
2295 return ALIGN(height, intel_tile_height(dev, pixel_format,
2296 fb_format_modifier));
a57ce0b2
JB		 2297}
2298
f64b98cd
TU		 2299static int
2300intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2301 const struct drm_plane_state *plane_state)
2302{
50470bb0 2303 struct intel_rotation_info *info = &view->rotation_info;
50470bb0 2304
f64b98cd
TU		 2305 *view = i915_ggtt_view_normal;
2306
50470bb0
TU		 2307 if (!plane_state)
2308 return 0;
2309
121920fa 2310 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2311 return 0;
2312
9abc4648 2313 *view = i915_ggtt_view_rotated;
50470bb0
TU		 2314
2315 info->height = fb->height;
2316 info->pixel_format = fb->pixel_format;
2317 info->pitch = fb->pitches[0];
2318 info->fb_modifier = fb->modifier[0];
2319
f64b98cd
TU		 2320 return 0;
2321}
2322
127bd2ac 2323int
850c4cdc
TU		 2324intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2325 struct drm_framebuffer *fb,
82bc3b2d 2326 const struct drm_plane_state *plane_state,
a4872ba6 2327 struct intel_engine_cs *pipelined)
6b95a207 2328{
850c4cdc 2329 struct drm_device *dev = fb->dev;
ce453d81 2330 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2331 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2332 struct i915_ggtt_view view;
6b95a207
KH		 2333 u32 alignment;
2334 int ret;
2335
ebcdd39e
MR		 2336 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2337
7b911adc
TU		 2338 switch (fb->modifier[0]) {
2339 case DRM_FORMAT_MOD_NONE:
1fada4cc
DL		 2340 if (INTEL_INFO(dev)->gen >= 9)
2341 alignment = 256 * 1024;
2342 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
534843da 2343 alignment = 128 * 1024;
a6c45cf0 2344 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 2345 alignment = 4 * 1024;
2346 else
2347 alignment = 64 * 1024;
6b95a207 2348 break;
7b911adc 2349 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2350 if (INTEL_INFO(dev)->gen >= 9)
2351 alignment = 256 * 1024;
2352 else {
2353 /* pin() will align the object as required by fence */
2354 alignment = 0;
2355 }
6b95a207 2356 break;
7b911adc 2357 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2358 case I915_FORMAT_MOD_Yf_TILED:
2359 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2360 "Y tiling bo slipped through, driver bug!\n"))
2361 return -EINVAL;
2362 alignment = 1 * 1024 * 1024;
2363 break;
6b95a207 2364 default:
7b911adc
TU		 2365 MISSING_CASE(fb->modifier[0]);
2366 return -EINVAL;
6b95a207
KH		 2367 }
2368
f64b98cd
TU		 2369 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2370 if (ret)
2371 return ret;
2372
693db184
CW		 2373 /* Note that the w/a also requires 64 PTE of padding following the
2374 * bo. We currently fill all unused PTE with the shadow page and so
2375 * we should always have valid PTE following the scanout preventing
2376 * the VT-d warning.
2377 */
2378 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2379 alignment = 256 * 1024;
2380
d6dd6843
PZ		 2381 /*
2382 * Global gtt pte registers are special registers which actually forward
2383 * writes to a chunk of system memory. Which means that there is no risk
2384 * that the register values disappear as soon as we call
2385 * intel_runtime_pm_put(), so it is correct to wrap only the
2386 * pin/unpin/fence and not more.
2387 */
2388 intel_runtime_pm_get(dev_priv);
2389
ce453d81 2390 dev_priv->mm.interruptible = false;
e6617330 2391 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
f64b98cd 2392 &view);
48b956c5 2393 if (ret)
ce453d81 2394 goto err_interruptible;
6b95a207
KH		 2395
2396 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2397 * fence, whereas 965+ only requires a fence if using
2398 * framebuffer compression. For simplicity, we always install
2399 * a fence as the cost is not that onerous.
2400 */
06d98131 2401 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2402 if (ret)
2403 goto err_unpin;
1690e1eb 2404
9a5a53b3 2405 i915_gem_object_pin_fence(obj);
6b95a207 2406
ce453d81 2407 dev_priv->mm.interruptible = true;
d6dd6843 2408 intel_runtime_pm_put(dev_priv);
6b95a207 2409 return 0;
48b956c5
CW		 2410
2411err_unpin:
f64b98cd 2412 i915_gem_object_unpin_from_display_plane(obj, &view);
ce453d81
CW		 2413err_interruptible:
2414 dev_priv->mm.interruptible = true;
d6dd6843 2415 intel_runtime_pm_put(dev_priv);
48b956c5 2416 return ret;
6b95a207
KH		 2417}
2418
82bc3b2d
TU		 2419static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2420 const struct drm_plane_state *plane_state)
1690e1eb 2421{
82bc3b2d 2422 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2423 struct i915_ggtt_view view;
2424 int ret;
82bc3b2d 2425
ebcdd39e
MR		 2426 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2427
f64b98cd
TU		 2428 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2429 WARN_ONCE(ret, "Couldn't get view from plane state!");
2430
1690e1eb 2431 i915_gem_object_unpin_fence(obj);
f64b98cd 2432 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2433}
2434
c2c75131
DV		 2435/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2436 * is assumed to be a power-of-two. */
bc752862
CW		 2437unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2438 unsigned int tiling_mode,
2439 unsigned int cpp,
2440 unsigned int pitch)
c2c75131 2441{
bc752862
CW		 2442 if (tiling_mode != I915_TILING_NONE) {
2443 unsigned int tile_rows, tiles;
c2c75131 2444
bc752862
CW		 2445 tile_rows = *y / 8;
2446 *y %= 8;
c2c75131 2447
bc752862
CW		 2448 tiles = *x / (512/cpp);
2449 *x %= 512/cpp;
2450
2451 return tile_rows * pitch * 8 + tiles * 4096;
2452 } else {
2453 unsigned int offset;
2454
2455 offset = *y * pitch + *x * cpp;
2456 *y = 0;
2457 *x = (offset & 4095) / cpp;
2458 return offset & -4096;
2459 }
c2c75131
DV		 2460}
2461
b35d63fa 2462static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2463{
2464 switch (format) {
2465 case DISPPLANE_8BPP:
2466 return DRM_FORMAT_C8;
2467 case DISPPLANE_BGRX555:
2468 return DRM_FORMAT_XRGB1555;
2469 case DISPPLANE_BGRX565:
2470 return DRM_FORMAT_RGB565;
2471 default:
2472 case DISPPLANE_BGRX888:
2473 return DRM_FORMAT_XRGB8888;
2474 case DISPPLANE_RGBX888:
2475 return DRM_FORMAT_XBGR8888;
2476 case DISPPLANE_BGRX101010:
2477 return DRM_FORMAT_XRGB2101010;
2478 case DISPPLANE_RGBX101010:
2479 return DRM_FORMAT_XBGR2101010;
2480 }
2481}
2482
bc8d7dff
DL		 2483static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2484{
2485 switch (format) {
2486 case PLANE_CTL_FORMAT_RGB_565:
2487 return DRM_FORMAT_RGB565;
2488 default:
2489 case PLANE_CTL_FORMAT_XRGB_8888:
2490 if (rgb_order) {
2491 if (alpha)
2492 return DRM_FORMAT_ABGR8888;
2493 else
2494 return DRM_FORMAT_XBGR8888;
2495 } else {
2496 if (alpha)
2497 return DRM_FORMAT_ARGB8888;
2498 else
2499 return DRM_FORMAT_XRGB8888;
2500 }
2501 case PLANE_CTL_FORMAT_XRGB_2101010:
2502 if (rgb_order)
2503 return DRM_FORMAT_XBGR2101010;
2504 else
2505 return DRM_FORMAT_XRGB2101010;
2506 }
2507}
2508
5724dbd1 2509static bool
f6936e29
DV		 2510intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2511 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2512{
2513 struct drm_device *dev = crtc->base.dev;
2514 struct drm_i915_gem_object *obj = NULL;
2515 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2516 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2517 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2518 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2519 PAGE_SIZE);
2520
2521 size_aligned -= base_aligned;
46f297fb 2522
ff2652ea
CW		 2523 if (plane_config->size == 0)
2524 return false;
2525
f37b5c2b
DV		 2526 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2527 base_aligned,
2528 base_aligned,
2529 size_aligned);
46f297fb 2530 if (!obj)
484b41dd 2531 return false;
46f297fb 2532
49af449b
DL		 2533 obj->tiling_mode = plane_config->tiling;
2534 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2535 obj->stride = fb->pitches[0];
46f297fb 2536
6bf129df
DL		 2537 mode_cmd.pixel_format = fb->pixel_format;
2538 mode_cmd.width = fb->width;
2539 mode_cmd.height = fb->height;
2540 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2541 mode_cmd.modifier[0] = fb->modifier[0];
2542 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2543
2544 mutex_lock(&dev->struct_mutex);
6bf129df 2545 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2546 &mode_cmd, obj)) {
46f297fb
JB		 2547 DRM_DEBUG_KMS("intel fb init failed\n");
2548 goto out_unref_obj;
2549 }
46f297fb 2550 mutex_unlock(&dev->struct_mutex);
484b41dd 2551
f6936e29 2552 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2553 return true;
46f297fb
JB		 2554
2555out_unref_obj:
2556 drm_gem_object_unreference(&obj->base);
2557 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2558 return false;
2559}
2560
afd65eb4
MR		 2561/* Update plane->state->fb to match plane->fb after driver-internal updates */
2562static void
2563update_state_fb(struct drm_plane *plane)
2564{
2565 if (plane->fb == plane->state->fb)
2566 return;
2567
2568 if (plane->state->fb)
2569 drm_framebuffer_unreference(plane->state->fb);
2570 plane->state->fb = plane->fb;
2571 if (plane->state->fb)
2572 drm_framebuffer_reference(plane->state->fb);
2573}
2574
5724dbd1 2575static void
f6936e29
DV		 2576intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2577 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2578{
2579 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2580 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2581 struct drm_crtc *c;
2582 struct intel_crtc *i;
2ff8fde1 2583 struct drm_i915_gem_object *obj;
88595ac9
DV		 2584 struct drm_plane *primary = intel_crtc->base.primary;
2585 struct drm_framebuffer *fb;
484b41dd 2586
2d14030b 2587 if (!plane_config->fb)
484b41dd
JB		 2588 return;
2589
f6936e29 2590 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2591 fb = &plane_config->fb->base;
2592 goto valid_fb;
f55548b5 2593 }
484b41dd 2594
2d14030b 2595 kfree(plane_config->fb);
484b41dd
JB		 2596
2597 /*
2598 * Failed to alloc the obj, check to see if we should share
2599 * an fb with another CRTC instead
2600 */
70e1e0ec 2601 for_each_crtc(dev, c) {
484b41dd
JB		 2602 i = to_intel_crtc(c);
2603
2604 if (c == &intel_crtc->base)
2605 continue;
2606
2ff8fde1
MR		 2607 if (!i->active)
2608 continue;
2609
88595ac9
DV		 2610 fb = c->primary->fb;
2611 if (!fb)
484b41dd
JB		 2612 continue;
2613
88595ac9 2614 obj = intel_fb_obj(fb);
2ff8fde1 2615 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2616 drm_framebuffer_reference(fb);
2617 goto valid_fb;
484b41dd
JB		 2618 }
2619 }
88595ac9
DV		 2620
2621 return;
2622
2623valid_fb:
2624 obj = intel_fb_obj(fb);
2625 if (obj->tiling_mode != I915_TILING_NONE)
2626 dev_priv->preserve_bios_swizzle = true;
2627
2628 primary->fb = fb;
2629 primary->state->crtc = &intel_crtc->base;
2630 primary->crtc = &intel_crtc->base;
2631 update_state_fb(primary);
2632 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
46f297fb
JB		 2633}
2634
29b9bde6
DV		 2635static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2636 struct drm_framebuffer *fb,
2637 int x, int y)
81255565
JB		 2638{
2639 struct drm_device *dev = crtc->dev;
2640 struct drm_i915_private *dev_priv = dev->dev_private;
2641 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2642 struct drm_plane *primary = crtc->primary;
2643 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2644 struct drm_i915_gem_object *obj;
81255565 2645 int plane = intel_crtc->plane;
e506a0c6 2646 unsigned long linear_offset;
81255565 2647 u32 dspcntr;
f45651ba 2648 u32 reg = DSPCNTR(plane);
48404c1e 2649 int pixel_size;
f45651ba 2650
b70709a6 2651 if (!visible || !fb) {
fdd508a6
VS		 2652 I915_WRITE(reg, 0);
2653 if (INTEL_INFO(dev)->gen >= 4)
2654 I915_WRITE(DSPSURF(plane), 0);
2655 else
2656 I915_WRITE(DSPADDR(plane), 0);
2657 POSTING_READ(reg);
2658 return;
2659 }
2660
c9ba6fad
VS		 2661 obj = intel_fb_obj(fb);
2662 if (WARN_ON(obj == NULL))
2663 return;
2664
2665 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2666
f45651ba
VS		 2667 dspcntr = DISPPLANE_GAMMA_ENABLE;
2668
fdd508a6 2669 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2670
2671 if (INTEL_INFO(dev)->gen < 4) {
2672 if (intel_crtc->pipe == PIPE_B)
2673 dspcntr |= DISPPLANE_SEL_PIPE_B;
2674
2675 /* pipesrc and dspsize control the size that is scaled from,
2676 * which should always be the user's requested size.
2677 */
2678 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2679 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2680 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2681 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2682 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2683 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2684 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2685 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2686 I915_WRITE(PRIMPOS(plane), 0);
2687 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2688 }
81255565 2689
57779d06
VS		 2690 switch (fb->pixel_format) {
2691 case DRM_FORMAT_C8:
81255565
JB		 2692 dspcntr |= DISPPLANE_8BPP;
2693 break;
57779d06 2694 case DRM_FORMAT_XRGB1555:
57779d06 2695 dspcntr |= DISPPLANE_BGRX555;
81255565 2696 break;
57779d06
VS		 2697 case DRM_FORMAT_RGB565:
2698 dspcntr |= DISPPLANE_BGRX565;
2699 break;
2700 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2701 dspcntr |= DISPPLANE_BGRX888;
2702 break;
2703 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2704 dspcntr |= DISPPLANE_RGBX888;
2705 break;
2706 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2707 dspcntr |= DISPPLANE_BGRX101010;
2708 break;
2709 case DRM_FORMAT_XBGR2101010:
57779d06 2710 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2711 break;
2712 default:
baba133a 2713 BUG();
81255565 2714 }
57779d06 2715
f45651ba
VS		 2716 if (INTEL_INFO(dev)->gen >= 4 &&
2717 obj->tiling_mode != I915_TILING_NONE)
2718 dspcntr |= DISPPLANE_TILED;
81255565 2719
de1aa629
VS		 2720 if (IS_G4X(dev))
2721 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2722
b9897127 2723 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2724
c2c75131
DV		 2725 if (INTEL_INFO(dev)->gen >= 4) {
2726 intel_crtc->dspaddr_offset =
bc752862 2727 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2728 pixel_size,
bc752862 2729 fb->pitches[0]);
c2c75131
DV		 2730 linear_offset -= intel_crtc->dspaddr_offset;
2731 } else {
e506a0c6 2732 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2733 }
e506a0c6 2734
8e7d688b 2735 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2736 dspcntr |= DISPPLANE_ROTATE_180;
2737
6e3c9717
ACO		 2738 x += (intel_crtc->config->pipe_src_w - 1);
2739 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2740
2741 /* Finding the last pixel of the last line of the display
2742 data and adding to linear_offset*/
2743 linear_offset +=
6e3c9717
ACO		 2744 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2745 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2746 }
2747
2748 I915_WRITE(reg, dspcntr);
2749
01f2c773 2750 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2751 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2752 I915_WRITE(DSPSURF(plane),
2753 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2754 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2755 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2756 } else
f343c5f6 2757 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2758 POSTING_READ(reg);
17638cd6
JB		 2759}
2760
29b9bde6
DV		 2761static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2762 struct drm_framebuffer *fb,
2763 int x, int y)
17638cd6
JB		 2764{
2765 struct drm_device *dev = crtc->dev;
2766 struct drm_i915_private *dev_priv = dev->dev_private;
2767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2768 struct drm_plane *primary = crtc->primary;
2769 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2770 struct drm_i915_gem_object *obj;
17638cd6 2771 int plane = intel_crtc->plane;
e506a0c6 2772 unsigned long linear_offset;
17638cd6 2773 u32 dspcntr;
f45651ba 2774 u32 reg = DSPCNTR(plane);
48404c1e 2775 int pixel_size;
f45651ba 2776
b70709a6 2777 if (!visible || !fb) {
fdd508a6
VS		 2778 I915_WRITE(reg, 0);
2779 I915_WRITE(DSPSURF(plane), 0);
2780 POSTING_READ(reg);
2781 return;
2782 }
2783
c9ba6fad
VS		 2784 obj = intel_fb_obj(fb);
2785 if (WARN_ON(obj == NULL))
2786 return;
2787
2788 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2789
f45651ba
VS		 2790 dspcntr = DISPPLANE_GAMMA_ENABLE;
2791
fdd508a6 2792 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2793
2794 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2795 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2796
57779d06
VS		 2797 switch (fb->pixel_format) {
2798 case DRM_FORMAT_C8:
17638cd6
JB		 2799 dspcntr |= DISPPLANE_8BPP;
2800 break;
57779d06
VS		 2801 case DRM_FORMAT_RGB565:
2802 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2803 break;
57779d06 2804 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2805 dspcntr |= DISPPLANE_BGRX888;
2806 break;
2807 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2808 dspcntr |= DISPPLANE_RGBX888;
2809 break;
2810 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2811 dspcntr |= DISPPLANE_BGRX101010;
2812 break;
2813 case DRM_FORMAT_XBGR2101010:
57779d06 2814 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2815 break;
2816 default:
baba133a 2817 BUG();
17638cd6
JB		 2818 }
2819
2820 if (obj->tiling_mode != I915_TILING_NONE)
2821 dspcntr |= DISPPLANE_TILED;
17638cd6 2822
f45651ba 2823 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2824 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2825
b9897127 2826 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2827 intel_crtc->dspaddr_offset =
bc752862 2828 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2829 pixel_size,
bc752862 2830 fb->pitches[0]);
c2c75131 2831 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2832 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2833 dspcntr |= DISPPLANE_ROTATE_180;
2834
2835 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2836 x += (intel_crtc->config->pipe_src_w - 1);
2837 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2838
2839 /* Finding the last pixel of the last line of the display
2840 data and adding to linear_offset*/
2841 linear_offset +=
6e3c9717
ACO		 2842 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2843 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2844 }
2845 }
2846
2847 I915_WRITE(reg, dspcntr);
17638cd6 2848
01f2c773 2849 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2850 I915_WRITE(DSPSURF(plane),
2851 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2852 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2853 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2854 } else {
2855 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2856 I915_WRITE(DSPLINOFF(plane), linear_offset);
2857 }
17638cd6 2858 POSTING_READ(reg);
17638cd6
JB		 2859}
2860
b321803d
DL		 2861u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2862 uint32_t pixel_format)
2863{
2864 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2865
2866 /*
2867 * The stride is either expressed as a multiple of 64 bytes
2868 * chunks for linear buffers or in number of tiles for tiled
2869 * buffers.
2870 */
2871 switch (fb_modifier) {
2872 case DRM_FORMAT_MOD_NONE:
2873 return 64;
2874 case I915_FORMAT_MOD_X_TILED:
2875 if (INTEL_INFO(dev)->gen == 2)
2876 return 128;
2877 return 512;
2878 case I915_FORMAT_MOD_Y_TILED:
2879 /* No need to check for old gens and Y tiling since this is
2880 * about the display engine and those will be blocked before
2881 * we get here.
2882 */
2883 return 128;
2884 case I915_FORMAT_MOD_Yf_TILED:
2885 if (bits_per_pixel == 8)
2886 return 64;
2887 else
2888 return 128;
2889 default:
2890 MISSING_CASE(fb_modifier);
2891 return 64;
2892 }
2893}
2894
121920fa
TU		 2895unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2896 struct drm_i915_gem_object *obj)
2897{
9abc4648 2898 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
121920fa
TU		 2899
2900 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2901 view = &i915_ggtt_view_rotated;
121920fa
TU		 2902
2903 return i915_gem_obj_ggtt_offset_view(obj, view);
2904}
2905
a1b2278e
CK		 2906/*
2907 * This function detaches (aka. unbinds) unused scalers in hardware
2908 */
2909void skl_detach_scalers(struct intel_crtc *intel_crtc)
2910{
2911 struct drm_device *dev;
2912 struct drm_i915_private *dev_priv;
2913 struct intel_crtc_scaler_state *scaler_state;
2914 int i;
2915
2916 if (!intel_crtc || !intel_crtc->config)
2917 return;
2918
2919 dev = intel_crtc->base.dev;
2920 dev_priv = dev->dev_private;
2921 scaler_state = &intel_crtc->config->scaler_state;
2922
2923 /* loop through and disable scalers that aren't in use */
2924 for (i = 0; i < intel_crtc->num_scalers; i++) {
2925 if (!scaler_state->scalers[i].in_use) {
2926 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2927 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2928 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2929 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2930 intel_crtc->base.base.id, intel_crtc->pipe, i);
2931 }
2932 }
2933}
2934
6156a456 2935u32 skl_plane_ctl_format(uint32_t pixel_format)
70d21f0e 2936{
6156a456 2937 switch (pixel_format) {
d161cf7a 2938 case DRM_FORMAT_C8:
c34ce3d1 2939 return PLANE_CTL_FORMAT_INDEXED;
70d21f0e 2940 case DRM_FORMAT_RGB565:
c34ce3d1 2941 return PLANE_CTL_FORMAT_RGB_565;
70d21f0e 2942 case DRM_FORMAT_XBGR8888:
c34ce3d1 2943 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
6156a456 2944 case DRM_FORMAT_XRGB8888:
c34ce3d1 2945 return PLANE_CTL_FORMAT_XRGB_8888;
6156a456
CK		 2946 /*
2947 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2948 * to be already pre-multiplied. We need to add a knob (or a different
2949 * DRM_FORMAT) for user-space to configure that.
2950 */
f75fb42a 2951 case DRM_FORMAT_ABGR8888:
c34ce3d1 2952 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
6156a456 2953 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
6156a456 2954 case DRM_FORMAT_ARGB8888:
c34ce3d1 2955 return PLANE_CTL_FORMAT_XRGB_8888 |
6156a456 2956 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
70d21f0e 2957 case DRM_FORMAT_XRGB2101010:
c34ce3d1 2958 return PLANE_CTL_FORMAT_XRGB_2101010;
70d21f0e 2959 case DRM_FORMAT_XBGR2101010:
c34ce3d1 2960 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
6156a456 2961 case DRM_FORMAT_YUYV:
c34ce3d1 2962 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
6156a456 2963 case DRM_FORMAT_YVYU:
c34ce3d1 2964 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
6156a456 2965 case DRM_FORMAT_UYVY:
c34ce3d1 2966 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
6156a456 2967 case DRM_FORMAT_VYUY:
c34ce3d1 2968 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
70d21f0e 2969 default:
4249eeef 2970 MISSING_CASE(pixel_format);
70d21f0e 2971 }
8cfcba41 2972
c34ce3d1 2973 return 0;
6156a456 2974}
70d21f0e 2975
6156a456
CK		 2976u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2977{
6156a456 2978 switch (fb_modifier) {
30af77c4 2979 case DRM_FORMAT_MOD_NONE:
70d21f0e 2980 break;
30af77c4 2981 case I915_FORMAT_MOD_X_TILED:
c34ce3d1 2982 return PLANE_CTL_TILED_X;
b321803d 2983 case I915_FORMAT_MOD_Y_TILED:
c34ce3d1 2984 return PLANE_CTL_TILED_Y;
b321803d 2985 case I915_FORMAT_MOD_Yf_TILED:
c34ce3d1 2986 return PLANE_CTL_TILED_YF;
70d21f0e 2987 default:
6156a456 2988 MISSING_CASE(fb_modifier);
70d21f0e 2989 }
8cfcba41 2990
c34ce3d1 2991 return 0;
6156a456 2992}
70d21f0e 2993
6156a456
CK		 2994u32 skl_plane_ctl_rotation(unsigned int rotation)
2995{
3b7a5119 2996 switch (rotation) {
6156a456
CK		 2997 case BIT(DRM_ROTATE_0):
2998 break;
1e8df167
SJ		 2999 /*
3000 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3001 * while i915 HW rotation is clockwise, thats why this swapping.
3002 */
3b7a5119 3003 case BIT(DRM_ROTATE_90):
1e8df167 3004 return PLANE_CTL_ROTATE_270;
3b7a5119 3005 case BIT(DRM_ROTATE_180):
c34ce3d1 3006 return PLANE_CTL_ROTATE_180;
3b7a5119 3007 case BIT(DRM_ROTATE_270):
1e8df167 3008 return PLANE_CTL_ROTATE_90;
6156a456
CK		 3009 default:
3010 MISSING_CASE(rotation);
3011 }
3012
c34ce3d1 3013 return 0;
6156a456
CK		 3014}
3015
3016static void skylake_update_primary_plane(struct drm_crtc *crtc,
3017 struct drm_framebuffer *fb,
3018 int x, int y)
3019{
3020 struct drm_device *dev = crtc->dev;
3021 struct drm_i915_private *dev_priv = dev->dev_private;
3022 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 3023 struct drm_plane *plane = crtc->primary;
3024 bool visible = to_intel_plane_state(plane->state)->visible;
6156a456
CK		 3025 struct drm_i915_gem_object *obj;
3026 int pipe = intel_crtc->pipe;
3027 u32 plane_ctl, stride_div, stride;
3028 u32 tile_height, plane_offset, plane_size;
3029 unsigned int rotation;
3030 int x_offset, y_offset;
3031 unsigned long surf_addr;
6156a456
CK		 3032 struct intel_crtc_state *crtc_state = intel_crtc->config;
3033 struct intel_plane_state *plane_state;
3034 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3035 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3036 int scaler_id = -1;
3037
6156a456
CK		 3038 plane_state = to_intel_plane_state(plane->state);
3039
b70709a6 3040 if (!visible || !fb) {
6156a456
CK		 3041 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3042 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3043 POSTING_READ(PLANE_CTL(pipe, 0));
3044 return;
3b7a5119 3045 }
70d21f0e 3046
6156a456
CK		 3047 plane_ctl = PLANE_CTL_ENABLE |
3048 PLANE_CTL_PIPE_GAMMA_ENABLE |
3049 PLANE_CTL_PIPE_CSC_ENABLE;
3050
3051 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3052 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3053 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3054
3055 rotation = plane->state->rotation;
3056 plane_ctl |= skl_plane_ctl_rotation(rotation);
3057
b321803d
DL		 3058 obj = intel_fb_obj(fb);
3059 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3060 fb->pixel_format);
3b7a5119
SJ		 3061 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3062
6156a456
CK		 3063 /*
3064 * FIXME: intel_plane_state->src, dst aren't set when transitional
3065 * update_plane helpers are called from legacy paths.
3066 * Once full atomic crtc is available, below check can be avoided.
3067 */
3068 if (drm_rect_width(&plane_state->src)) {
3069 scaler_id = plane_state->scaler_id;
3070 src_x = plane_state->src.x1 >> 16;
3071 src_y = plane_state->src.y1 >> 16;
3072 src_w = drm_rect_width(&plane_state->src) >> 16;
3073 src_h = drm_rect_height(&plane_state->src) >> 16;
3074 dst_x = plane_state->dst.x1;
3075 dst_y = plane_state->dst.y1;
3076 dst_w = drm_rect_width(&plane_state->dst);
3077 dst_h = drm_rect_height(&plane_state->dst);
3078
3079 WARN_ON(x != src_x || y != src_y);
3080 } else {
3081 src_w = intel_crtc->config->pipe_src_w;
3082 src_h = intel_crtc->config->pipe_src_h;
3083 }
3084
3b7a5119
SJ		 3085 if (intel_rotation_90_or_270(rotation)) {
3086 /* stride = Surface height in tiles */
2614f17d 3087 tile_height = intel_tile_height(dev, fb->pixel_format,
3b7a5119
SJ		 3088 fb->modifier[0]);
3089 stride = DIV_ROUND_UP(fb->height, tile_height);
6156a456 3090 x_offset = stride * tile_height - y - src_h;
3b7a5119 3091 y_offset = x;
6156a456 3092 plane_size = (src_w - 1) << 16 | (src_h - 1);
3b7a5119
SJ		 3093 } else {
3094 stride = fb->pitches[0] / stride_div;
3095 x_offset = x;
3096 y_offset = y;
6156a456 3097 plane_size = (src_h - 1) << 16 | (src_w - 1);
3b7a5119
SJ		 3098 }
3099 plane_offset = y_offset << 16 | x_offset;
b321803d 3100
70d21f0e 3101 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3b7a5119
SJ		 3102 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3103 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3104 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
6156a456
CK		 3105
3106 if (scaler_id >= 0) {
3107 uint32_t ps_ctrl = 0;
3108
3109 WARN_ON(!dst_w || !dst_h);
3110 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3111 crtc_state->scaler_state.scalers[scaler_id].mode;
3112 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3113 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3114 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3115 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3116 I915_WRITE(PLANE_POS(pipe, 0), 0);
3117 } else {
3118 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3119 }
3120
121920fa 3121 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3122
3123 POSTING_READ(PLANE_SURF(pipe, 0));
3124}
3125
17638cd6
JB		 3126/* Assume fb object is pinned & idle & fenced and just update base pointers */
3127static int
3128intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3129 int x, int y, enum mode_set_atomic state)
3130{
3131 struct drm_device *dev = crtc->dev;
3132 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3133
6b8e6ed0
CW		 3134 if (dev_priv->display.disable_fbc)
3135 dev_priv->display.disable_fbc(dev);
81255565 3136
29b9bde6
DV		 3137 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3138
3139 return 0;
81255565
JB		 3140}
3141
7514747d 3142static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3143{
96a02917
VS		 3144 struct drm_crtc *crtc;
3145
70e1e0ec 3146 for_each_crtc(dev, crtc) {
96a02917
VS		 3147 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3148 enum plane plane = intel_crtc->plane;
3149
3150 intel_prepare_page_flip(dev, plane);
3151 intel_finish_page_flip_plane(dev, plane);
3152 }
7514747d
VS		 3153}
3154
3155static void intel_update_primary_planes(struct drm_device *dev)
3156{
3157 struct drm_i915_private *dev_priv = dev->dev_private;
3158 struct drm_crtc *crtc;
96a02917 3159
70e1e0ec 3160 for_each_crtc(dev, crtc) {
96a02917
VS		 3161 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3162
51fd371b 3163 drm_modeset_lock(&crtc->mutex, NULL);
947fdaad
CW		 3164 /*
3165 * FIXME: Once we have proper support for primary planes (and
3166 * disabling them without disabling the entire crtc) allow again
66e514c1 3167 * a NULL crtc->primary->fb.
947fdaad 3168 */
f4510a27 3169 if (intel_crtc->active && crtc->primary->fb)
262ca2b0 3170 dev_priv->display.update_primary_plane(crtc,
66e514c1 3171 crtc->primary->fb,
262ca2b0
MR		 3172 crtc->x,
3173 crtc->y);
51fd371b 3174 drm_modeset_unlock(&crtc->mutex);
96a02917
VS		 3175 }
3176}
3177
ce22dba9
ML		 3178void intel_crtc_reset(struct intel_crtc *crtc)
3179{
3180 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3181
3182 if (!crtc->active)
3183 return;
3184
3185 intel_crtc_disable_planes(&crtc->base);
3186 dev_priv->display.crtc_disable(&crtc->base);
3187 dev_priv->display.crtc_enable(&crtc->base);
3188 intel_crtc_enable_planes(&crtc->base);
3189}
3190
7514747d
VS		 3191void intel_prepare_reset(struct drm_device *dev)
3192{
f98ce92f
VS		 3193 struct drm_i915_private *dev_priv = to_i915(dev);
3194 struct intel_crtc *crtc;
3195
7514747d
VS		 3196 /* no reset support for gen2 */
3197 if (IS_GEN2(dev))
3198 return;
3199
3200 /* reset doesn't touch the display */
3201 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3202 return;
3203
3204 drm_modeset_lock_all(dev);
f98ce92f
VS		 3205
3206 /*
3207 * Disabling the crtcs gracefully seems nicer. Also the
3208 * g33 docs say we should at least disable all the planes.
3209 */
3210 for_each_intel_crtc(dev, crtc) {
ce22dba9
ML		 3211 if (!crtc->active)
3212 continue;
3213
3214 intel_crtc_disable_planes(&crtc->base);
3215 dev_priv->display.crtc_disable(&crtc->base);
f98ce92f 3216 }
7514747d
VS		 3217}
3218
3219void intel_finish_reset(struct drm_device *dev)
3220{
3221 struct drm_i915_private *dev_priv = to_i915(dev);
3222
3223 /*
3224 * Flips in the rings will be nuked by the reset,
3225 * so complete all pending flips so that user space
3226 * will get its events and not get stuck.
3227 */
3228 intel_complete_page_flips(dev);
3229
3230 /* no reset support for gen2 */
3231 if (IS_GEN2(dev))
3232 return;
3233
3234 /* reset doesn't touch the display */
3235 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3236 /*
3237 * Flips in the rings have been nuked by the reset,
3238 * so update the base address of all primary
3239 * planes to the the last fb to make sure we're
3240 * showing the correct fb after a reset.
3241 */
3242 intel_update_primary_planes(dev);
3243 return;
3244 }
3245
3246 /*
3247 * The display has been reset as well,
3248 * so need a full re-initialization.
3249 */
3250 intel_runtime_pm_disable_interrupts(dev_priv);
3251 intel_runtime_pm_enable_interrupts(dev_priv);
3252
3253 intel_modeset_init_hw(dev);
3254
3255 spin_lock_irq(&dev_priv->irq_lock);
3256 if (dev_priv->display.hpd_irq_setup)
3257 dev_priv->display.hpd_irq_setup(dev);
3258 spin_unlock_irq(&dev_priv->irq_lock);
3259
3260 intel_modeset_setup_hw_state(dev, true);
3261
3262 intel_hpd_init(dev_priv);
3263
3264 drm_modeset_unlock_all(dev);
3265}
3266
2e2f351d 3267static void
14667a4b
CW		 3268intel_finish_fb(struct drm_framebuffer *old_fb)
3269{
2ff8fde1 3270 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2e2f351d 3271 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14667a4b
CW		 3272 bool was_interruptible = dev_priv->mm.interruptible;
3273 int ret;
3274
14667a4b
CW		 3275 /* Big Hammer, we also need to ensure that any pending
3276 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3277 * current scanout is retired before unpinning the old
2e2f351d
CW		 3278 * framebuffer. Note that we rely on userspace rendering
3279 * into the buffer attached to the pipe they are waiting
3280 * on. If not, userspace generates a GPU hang with IPEHR
3281 * point to the MI_WAIT_FOR_EVENT.
14667a4b
CW		 3282 *
3283 * This should only fail upon a hung GPU, in which case we
3284 * can safely continue.
3285 */
3286 dev_priv->mm.interruptible = false;
2e2f351d 3287 ret = i915_gem_object_wait_rendering(obj, true);
14667a4b
CW		 3288 dev_priv->mm.interruptible = was_interruptible;
3289
2e2f351d 3290 WARN_ON(ret);
14667a4b
CW		 3291}
3292
7d5e3799
CW		 3293static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3294{
3295 struct drm_device *dev = crtc->dev;
3296 struct drm_i915_private *dev_priv = dev->dev_private;
3297 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3298 bool pending;
3299
3300 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3301 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3302 return false;
3303
5e2d7afc 3304 spin_lock_irq(&dev->event_lock);
7d5e3799 3305 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3306 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3307
3308 return pending;
3309}
3310
e30e8f75
GP		 3311static void intel_update_pipe_size(struct intel_crtc *crtc)
3312{
3313 struct drm_device *dev = crtc->base.dev;
3314 struct drm_i915_private *dev_priv = dev->dev_private;
3315 const struct drm_display_mode *adjusted_mode;
3316
3317 if (!i915.fastboot)
3318 return;
3319
3320 /*
3321 * Update pipe size and adjust fitter if needed: the reason for this is
3322 * that in compute_mode_changes we check the native mode (not the pfit
3323 * mode) to see if we can flip rather than do a full mode set. In the
3324 * fastboot case, we'll flip, but if we don't update the pipesrc and
3325 * pfit state, we'll end up with a big fb scanned out into the wrong
3326 * sized surface.
3327 *
3328 * To fix this properly, we need to hoist the checks up into
3329 * compute_mode_changes (or above), check the actual pfit state and
3330 * whether the platform allows pfit disable with pipe active, and only
3331 * then update the pipesrc and pfit state, even on the flip path.
3332 */
3333
6e3c9717 3334 adjusted_mode = &crtc->config->base.adjusted_mode;
e30e8f75
GP		 3335
3336 I915_WRITE(PIPESRC(crtc->pipe),
3337 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3338 (adjusted_mode->crtc_vdisplay - 1));
6e3c9717 3339 if (!crtc->config->pch_pfit.enabled &&
409ee761
ACO		 3340 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3341 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
e30e8f75
GP		 3342 I915_WRITE(PF_CTL(crtc->pipe), 0);
3343 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3344 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3345 }
6e3c9717
ACO		 3346 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3347 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
e30e8f75
GP		 3348}
3349
5e84e1a4
ZW		 3350static void intel_fdi_normal_train(struct drm_crtc *crtc)
3351{
3352 struct drm_device *dev = crtc->dev;
3353 struct drm_i915_private *dev_priv = dev->dev_private;
3354 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3355 int pipe = intel_crtc->pipe;
3356 u32 reg, temp;
3357
3358 /* enable normal train */
3359 reg = FDI_TX_CTL(pipe);
3360 temp = I915_READ(reg);
61e499bf 3361 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3362 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3363 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3364 } else {
3365 temp &= ~FDI_LINK_TRAIN_NONE;
3366 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3367 }
5e84e1a4
ZW		 3368 I915_WRITE(reg, temp);
3369
3370 reg = FDI_RX_CTL(pipe);
3371 temp = I915_READ(reg);
3372 if (HAS_PCH_CPT(dev)) {
3373 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3374 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3375 } else {
3376 temp &= ~FDI_LINK_TRAIN_NONE;
3377 temp |= FDI_LINK_TRAIN_NONE;
3378 }
3379 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3380
3381 /* wait one idle pattern time */
3382 POSTING_READ(reg);
3383 udelay(1000);
357555c0
JB		 3384
3385 /* IVB wants error correction enabled */
3386 if (IS_IVYBRIDGE(dev))
3387 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3388 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3389}
3390
8db9d77b
ZW		 3391/* The FDI link training functions for ILK/Ibexpeak. */
3392static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3393{
3394 struct drm_device *dev = crtc->dev;
3395 struct drm_i915_private *dev_priv = dev->dev_private;
3396 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3397 int pipe = intel_crtc->pipe;
5eddb70b 3398 u32 reg, temp, tries;
8db9d77b 3399
1c8562f6 3400 /* FDI needs bits from pipe first */
0fc932b8 3401 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3402
e1a44743
AJ		 3403 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3404 for train result */
5eddb70b
CW		 3405 reg = FDI_RX_IMR(pipe);
3406 temp = I915_READ(reg);
e1a44743
AJ		 3407 temp &= ~FDI_RX_SYMBOL_LOCK;
3408 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3409 I915_WRITE(reg, temp);
3410 I915_READ(reg);
e1a44743
AJ		 3411 udelay(150);
3412
8db9d77b 3413 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3414 reg = FDI_TX_CTL(pipe);
3415 temp = I915_READ(reg);
627eb5a3 3416 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3417 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3418 temp &= ~FDI_LINK_TRAIN_NONE;
3419 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3420 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3421
5eddb70b
CW		 3422 reg = FDI_RX_CTL(pipe);
3423 temp = I915_READ(reg);
8db9d77b
ZW		 3424 temp &= ~FDI_LINK_TRAIN_NONE;
3425 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3426 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3427
3428 POSTING_READ(reg);
8db9d77b
ZW		 3429 udelay(150);
3430
5b2adf89 3431 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3432 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3433 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3434 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3435
5eddb70b 3436 reg = FDI_RX_IIR(pipe);
e1a44743 3437 for (tries = 0; tries < 5; tries++) {
5eddb70b 3438 temp = I915_READ(reg);
8db9d77b
ZW		 3439 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3440
3441 if ((temp & FDI_RX_BIT_LOCK)) {
3442 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3443 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3444 break;
3445 }
8db9d77b 3446 }
e1a44743 3447 if (tries == 5)
5eddb70b 3448 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3449
3450 /* Train 2 */
5eddb70b
CW		 3451 reg = FDI_TX_CTL(pipe);
3452 temp = I915_READ(reg);
8db9d77b
ZW		 3453 temp &= ~FDI_LINK_TRAIN_NONE;
3454 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3455 I915_WRITE(reg, temp);
8db9d77b 3456
5eddb70b
CW		 3457 reg = FDI_RX_CTL(pipe);
3458 temp = I915_READ(reg);
8db9d77b
ZW		 3459 temp &= ~FDI_LINK_TRAIN_NONE;
3460 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3461 I915_WRITE(reg, temp);
8db9d77b 3462
5eddb70b
CW		 3463 POSTING_READ(reg);
3464 udelay(150);
8db9d77b 3465
5eddb70b 3466 reg = FDI_RX_IIR(pipe);
e1a44743 3467 for (tries = 0; tries < 5; tries++) {
5eddb70b 3468 temp = I915_READ(reg);
8db9d77b
ZW		 3469 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3470
3471 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3472 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3473 DRM_DEBUG_KMS("FDI train 2 done.\n");
3474 break;
3475 }
8db9d77b 3476 }
e1a44743 3477 if (tries == 5)
5eddb70b 3478 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3479
3480 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3481
8db9d77b
ZW		 3482}
3483
0206e353 3484static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3485 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3486 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3487 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3488 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3489};
3490
3491/* The FDI link training functions for SNB/Cougarpoint. */
3492static void gen6_fdi_link_train(struct drm_crtc *crtc)
3493{
3494 struct drm_device *dev = crtc->dev;
3495 struct drm_i915_private *dev_priv = dev->dev_private;
3496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3497 int pipe = intel_crtc->pipe;
fa37d39e 3498 u32 reg, temp, i, retry;
8db9d77b 3499
e1a44743
AJ		 3500 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3501 for train result */
5eddb70b
CW		 3502 reg = FDI_RX_IMR(pipe);
3503 temp = I915_READ(reg);
e1a44743
AJ		 3504 temp &= ~FDI_RX_SYMBOL_LOCK;
3505 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3506 I915_WRITE(reg, temp);
3507
3508 POSTING_READ(reg);
e1a44743
AJ		 3509 udelay(150);
3510
8db9d77b 3511 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3512 reg = FDI_TX_CTL(pipe);
3513 temp = I915_READ(reg);
627eb5a3 3514 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3515 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3516 temp &= ~FDI_LINK_TRAIN_NONE;
3517 temp |= FDI_LINK_TRAIN_PATTERN_1;
3518 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3519 /* SNB-B */
3520 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3521 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3522
d74cf324
DV		 3523 I915_WRITE(FDI_RX_MISC(pipe),
3524 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3525
5eddb70b
CW		 3526 reg = FDI_RX_CTL(pipe);
3527 temp = I915_READ(reg);
8db9d77b
ZW		 3528 if (HAS_PCH_CPT(dev)) {
3529 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3530 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3531 } else {
3532 temp &= ~FDI_LINK_TRAIN_NONE;
3533 temp |= FDI_LINK_TRAIN_PATTERN_1;
3534 }
5eddb70b
CW		 3535 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3536
3537 POSTING_READ(reg);
8db9d77b
ZW		 3538 udelay(150);
3539
0206e353 3540 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3541 reg = FDI_TX_CTL(pipe);
3542 temp = I915_READ(reg);
8db9d77b
ZW		 3543 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3544 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3545 I915_WRITE(reg, temp);
3546
3547 POSTING_READ(reg);
8db9d77b
ZW		 3548 udelay(500);
3549
fa37d39e
SP		 3550 for (retry = 0; retry < 5; retry++) {
3551 reg = FDI_RX_IIR(pipe);
3552 temp = I915_READ(reg);
3553 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3554 if (temp & FDI_RX_BIT_LOCK) {
3555 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3556 DRM_DEBUG_KMS("FDI train 1 done.\n");
3557 break;
3558 }
3559 udelay(50);
8db9d77b 3560 }
fa37d39e
SP		 3561 if (retry < 5)
3562 break;
8db9d77b
ZW		 3563 }
3564 if (i == 4)
5eddb70b 3565 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3566
3567 /* Train 2 */
5eddb70b
CW		 3568 reg = FDI_TX_CTL(pipe);
3569 temp = I915_READ(reg);
8db9d77b
ZW		 3570 temp &= ~FDI_LINK_TRAIN_NONE;
3571 temp |= FDI_LINK_TRAIN_PATTERN_2;
3572 if (IS_GEN6(dev)) {
3573 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3574 /* SNB-B */
3575 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3576 }
5eddb70b 3577 I915_WRITE(reg, temp);
8db9d77b 3578
5eddb70b
CW		 3579 reg = FDI_RX_CTL(pipe);
3580 temp = I915_READ(reg);
8db9d77b
ZW		 3581 if (HAS_PCH_CPT(dev)) {
3582 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3583 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3584 } else {
3585 temp &= ~FDI_LINK_TRAIN_NONE;
3586 temp |= FDI_LINK_TRAIN_PATTERN_2;
3587 }
5eddb70b
CW		 3588 I915_WRITE(reg, temp);
3589
3590 POSTING_READ(reg);
8db9d77b
ZW		 3591 udelay(150);
3592
0206e353 3593 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3594 reg = FDI_TX_CTL(pipe);
3595 temp = I915_READ(reg);
8db9d77b
ZW		 3596 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3597 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3598 I915_WRITE(reg, temp);
3599
3600 POSTING_READ(reg);
8db9d77b
ZW		 3601 udelay(500);
3602
fa37d39e
SP		 3603 for (retry = 0; retry < 5; retry++) {
3604 reg = FDI_RX_IIR(pipe);
3605 temp = I915_READ(reg);
3606 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3607 if (temp & FDI_RX_SYMBOL_LOCK) {
3608 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3609 DRM_DEBUG_KMS("FDI train 2 done.\n");
3610 break;
3611 }
3612 udelay(50);
8db9d77b 3613 }
fa37d39e
SP		 3614 if (retry < 5)
3615 break;
8db9d77b
ZW		 3616 }
3617 if (i == 4)
5eddb70b 3618 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3619
3620 DRM_DEBUG_KMS("FDI train done.\n");
3621}
3622
357555c0
JB		 3623/* Manual link training for Ivy Bridge A0 parts */
3624static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3625{
3626 struct drm_device *dev = crtc->dev;
3627 struct drm_i915_private *dev_priv = dev->dev_private;
3628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3629 int pipe = intel_crtc->pipe;
139ccd3f 3630 u32 reg, temp, i, j;
357555c0
JB		 3631
3632 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3633 for train result */
3634 reg = FDI_RX_IMR(pipe);
3635 temp = I915_READ(reg);
3636 temp &= ~FDI_RX_SYMBOL_LOCK;
3637 temp &= ~FDI_RX_BIT_LOCK;
3638 I915_WRITE(reg, temp);
3639
3640 POSTING_READ(reg);
3641 udelay(150);
3642
01a415fd
DV		 3643 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3644 I915_READ(FDI_RX_IIR(pipe)));
3645
139ccd3f
JB		 3646 /* Try each vswing and preemphasis setting twice before moving on */
3647 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3648 /* disable first in case we need to retry */
3649 reg = FDI_TX_CTL(pipe);
3650 temp = I915_READ(reg);
3651 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3652 temp &= ~FDI_TX_ENABLE;
3653 I915_WRITE(reg, temp);
357555c0 3654
139ccd3f
JB		 3655 reg = FDI_RX_CTL(pipe);
3656 temp = I915_READ(reg);
3657 temp &= ~FDI_LINK_TRAIN_AUTO;
3658 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3659 temp &= ~FDI_RX_ENABLE;
3660 I915_WRITE(reg, temp);
357555c0 3661
139ccd3f 3662 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3663 reg = FDI_TX_CTL(pipe);
3664 temp = I915_READ(reg);
139ccd3f 3665 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3666 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3667 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3668 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3669 temp |= snb_b_fdi_train_param[j/2];
3670 temp |= FDI_COMPOSITE_SYNC;
3671 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3672
139ccd3f
JB		 3673 I915_WRITE(FDI_RX_MISC(pipe),
3674 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3675
139ccd3f 3676 reg = FDI_RX_CTL(pipe);
357555c0 3677 temp = I915_READ(reg);
139ccd3f
JB		 3678 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3679 temp |= FDI_COMPOSITE_SYNC;
3680 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3681
139ccd3f
JB		 3682 POSTING_READ(reg);
3683 udelay(1); /* should be 0.5us */
357555c0 3684
139ccd3f
JB		 3685 for (i = 0; i < 4; i++) {
3686 reg = FDI_RX_IIR(pipe);
3687 temp = I915_READ(reg);
3688 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3689
139ccd3f
JB		 3690 if (temp & FDI_RX_BIT_LOCK ||
3691 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3692 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3693 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3694 i);
3695 break;
3696 }
3697 udelay(1); /* should be 0.5us */
3698 }
3699 if (i == 4) {
3700 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3701 continue;
3702 }
357555c0 3703
139ccd3f 3704 /* Train 2 */
357555c0
JB		 3705 reg = FDI_TX_CTL(pipe);
3706 temp = I915_READ(reg);
139ccd3f
JB		 3707 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3708 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3709 I915_WRITE(reg, temp);
3710
3711 reg = FDI_RX_CTL(pipe);
3712 temp = I915_READ(reg);
3713 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3714 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3715 I915_WRITE(reg, temp);
3716
3717 POSTING_READ(reg);
139ccd3f 3718 udelay(2); /* should be 1.5us */
357555c0 3719
139ccd3f
JB		 3720 for (i = 0; i < 4; i++) {
3721 reg = FDI_RX_IIR(pipe);
3722 temp = I915_READ(reg);
3723 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3724
139ccd3f
JB		 3725 if (temp & FDI_RX_SYMBOL_LOCK ||
3726 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3727 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3728 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3729 i);
3730 goto train_done;
3731 }
3732 udelay(2); /* should be 1.5us */
357555c0 3733 }
139ccd3f
JB		 3734 if (i == 4)
3735 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3736 }
357555c0 3737
139ccd3f 3738train_done:
357555c0
JB		 3739 DRM_DEBUG_KMS("FDI train done.\n");
3740}
3741
88cefb6c 3742static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3743{
88cefb6c 3744 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3745 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3746 int pipe = intel_crtc->pipe;
5eddb70b 3747 u32 reg, temp;
79e53945 3748
c64e311e 3749
c98e9dcf 3750 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3751 reg = FDI_RX_CTL(pipe);
3752 temp = I915_READ(reg);
627eb5a3 3753 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3754 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3755 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3756 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3757
3758 POSTING_READ(reg);
c98e9dcf
JB		 3759 udelay(200);
3760
3761 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3762 temp = I915_READ(reg);
3763 I915_WRITE(reg, temp | FDI_PCDCLK);
3764
3765 POSTING_READ(reg);
c98e9dcf
JB		 3766 udelay(200);
3767
20749730
PZ		 3768 /* Enable CPU FDI TX PLL, always on for Ironlake */
3769 reg = FDI_TX_CTL(pipe);
3770 temp = I915_READ(reg);
3771 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3772 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3773
20749730
PZ		 3774 POSTING_READ(reg);
3775 udelay(100);
6be4a607 3776 }
0e23b99d
JB		 3777}
3778
88cefb6c
DV		 3779static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3780{
3781 struct drm_device *dev = intel_crtc->base.dev;
3782 struct drm_i915_private *dev_priv = dev->dev_private;
3783 int pipe = intel_crtc->pipe;
3784 u32 reg, temp;
3785
3786 /* Switch from PCDclk to Rawclk */
3787 reg = FDI_RX_CTL(pipe);
3788 temp = I915_READ(reg);
3789 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3790
3791 /* Disable CPU FDI TX PLL */
3792 reg = FDI_TX_CTL(pipe);
3793 temp = I915_READ(reg);
3794 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3795
3796 POSTING_READ(reg);
3797 udelay(100);
3798
3799 reg = FDI_RX_CTL(pipe);
3800 temp = I915_READ(reg);
3801 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3802
3803 /* Wait for the clocks to turn off. */
3804 POSTING_READ(reg);
3805 udelay(100);
3806}
3807
0fc932b8
JB		 3808static void ironlake_fdi_disable(struct drm_crtc *crtc)
3809{
3810 struct drm_device *dev = crtc->dev;
3811 struct drm_i915_private *dev_priv = dev->dev_private;
3812 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3813 int pipe = intel_crtc->pipe;
3814 u32 reg, temp;
3815
3816 /* disable CPU FDI tx and PCH FDI rx */
3817 reg = FDI_TX_CTL(pipe);
3818 temp = I915_READ(reg);
3819 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3820 POSTING_READ(reg);
3821
3822 reg = FDI_RX_CTL(pipe);
3823 temp = I915_READ(reg);
3824 temp &= ~(0x7 << 16);
dfd07d72 3825 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3826 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3827
3828 POSTING_READ(reg);
3829 udelay(100);
3830
3831 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3832 if (HAS_PCH_IBX(dev))
6f06ce18 3833 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3834
3835 /* still set train pattern 1 */
3836 reg = FDI_TX_CTL(pipe);
3837 temp = I915_READ(reg);
3838 temp &= ~FDI_LINK_TRAIN_NONE;
3839 temp |= FDI_LINK_TRAIN_PATTERN_1;
3840 I915_WRITE(reg, temp);
3841
3842 reg = FDI_RX_CTL(pipe);
3843 temp = I915_READ(reg);
3844 if (HAS_PCH_CPT(dev)) {
3845 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3846 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3847 } else {
3848 temp &= ~FDI_LINK_TRAIN_NONE;
3849 temp |= FDI_LINK_TRAIN_PATTERN_1;
3850 }
3851 /* BPC in FDI rx is consistent with that in PIPECONF */
3852 temp &= ~(0x07 << 16);
dfd07d72 3853 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3854 I915_WRITE(reg, temp);
3855
3856 POSTING_READ(reg);
3857 udelay(100);
3858}
3859
5dce5b93
CW		 3860bool intel_has_pending_fb_unpin(struct drm_device *dev)
3861{
3862 struct intel_crtc *crtc;
3863
3864 /* Note that we don't need to be called with mode_config.lock here
3865 * as our list of CRTC objects is static for the lifetime of the
3866 * device and so cannot disappear as we iterate. Similarly, we can
3867 * happily treat the predicates as racy, atomic checks as userspace
3868 * cannot claim and pin a new fb without at least acquring the
3869 * struct_mutex and so serialising with us.
3870 */
d3fcc808 3871 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3872 if (atomic_read(&crtc->unpin_work_count) == 0)
3873 continue;
3874
3875 if (crtc->unpin_work)
3876 intel_wait_for_vblank(dev, crtc->pipe);
3877
3878 return true;
3879 }
3880
3881 return false;
3882}
3883
d6bbafa1
CW		 3884static void page_flip_completed(struct intel_crtc *intel_crtc)
3885{
3886 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3887 struct intel_unpin_work *work = intel_crtc->unpin_work;
3888
3889 /* ensure that the unpin work is consistent wrt ->pending. */
3890 smp_rmb();
3891 intel_crtc->unpin_work = NULL;
3892
3893 if (work->event)
3894 drm_send_vblank_event(intel_crtc->base.dev,
3895 intel_crtc->pipe,
3896 work->event);
3897
3898 drm_crtc_vblank_put(&intel_crtc->base);
3899
3900 wake_up_all(&dev_priv->pending_flip_queue);
3901 queue_work(dev_priv->wq, &work->work);
3902
3903 trace_i915_flip_complete(intel_crtc->plane,
3904 work->pending_flip_obj);
3905}
3906
46a55d30 3907void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3908{
0f91128d 3909 struct drm_device *dev = crtc->dev;
5bb61643 3910 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3911
2c10d571 3912 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW		 3913 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3914 !intel_crtc_has_pending_flip(crtc),
3915 60*HZ) == 0)) {
3916 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3917
5e2d7afc 3918 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3919 if (intel_crtc->unpin_work) {
3920 WARN_ONCE(1, "Removing stuck page flip\n");
3921 page_flip_completed(intel_crtc);
3922 }
5e2d7afc 3923 spin_unlock_irq(&dev->event_lock);
9c787942 3924 }
5bb61643 3925
975d568a
CW		 3926 if (crtc->primary->fb) {
3927 mutex_lock(&dev->struct_mutex);
3928 intel_finish_fb(crtc->primary->fb);
3929 mutex_unlock(&dev->struct_mutex);
3930 }
e6c3a2a6
CW		 3931}
3932
e615efe4
ED		 3933/* Program iCLKIP clock to the desired frequency */
3934static void lpt_program_iclkip(struct drm_crtc *crtc)
3935{
3936 struct drm_device *dev = crtc->dev;
3937 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3938 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3939 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3940 u32 temp;
3941
a580516d 3942 mutex_lock(&dev_priv->sb_lock);
09153000 3943
e615efe4
ED		 3944 /* It is necessary to ungate the pixclk gate prior to programming
3945 * the divisors, and gate it back when it is done.
3946 */
3947 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3948
3949 /* Disable SSCCTL */
3950 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3951 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3952 SBI_SSCCTL_DISABLE,
3953 SBI_ICLK);
e615efe4
ED		 3954
3955 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3956 if (clock == 20000) {
e615efe4
ED		 3957 auxdiv = 1;
3958 divsel = 0x41;
3959 phaseinc = 0x20;
3960 } else {
3961 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3962 * but the adjusted_mode->crtc_clock in in KHz. To get the
3963 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3964 * convert the virtual clock precision to KHz here for higher
3965 * precision.
3966 */
3967 u32 iclk_virtual_root_freq = 172800 * 1000;
3968 u32 iclk_pi_range = 64;
3969 u32 desired_divisor, msb_divisor_value, pi_value;
3970
12d7ceed 3971 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3972 msb_divisor_value = desired_divisor / iclk_pi_range;
3973 pi_value = desired_divisor % iclk_pi_range;
3974
3975 auxdiv = 0;
3976 divsel = msb_divisor_value - 2;
3977 phaseinc = pi_value;
3978 }
3979
3980 /* This should not happen with any sane values */
3981 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3982 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3983 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3984 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3985
3986 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3987 clock,
e615efe4
ED		 3988 auxdiv,
3989 divsel,
3990 phasedir,
3991 phaseinc);
3992
3993 /* Program SSCDIVINTPHASE6 */
988d6ee8 3994 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3995 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3996 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3997 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3998 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3999 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4000 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 4001 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 4002
4003 /* Program SSCAUXDIV */
988d6ee8 4004 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 4005 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4006 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 4007 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 4008
4009 /* Enable modulator and associated divider */
988d6ee8 4010 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 4011 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 4012 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 4013
4014 /* Wait for initialization time */
4015 udelay(24);
4016
4017 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000 4018
a580516d 4019 mutex_unlock(&dev_priv->sb_lock);
e615efe4
ED		 4020}
4021
275f01b2
DV		 4022static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4023 enum pipe pch_transcoder)
4024{
4025 struct drm_device *dev = crtc->base.dev;
4026 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 4027 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 4028
4029 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4030 I915_READ(HTOTAL(cpu_transcoder)));
4031 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4032 I915_READ(HBLANK(cpu_transcoder)));
4033 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4034 I915_READ(HSYNC(cpu_transcoder)));
4035
4036 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4037 I915_READ(VTOTAL(cpu_transcoder)));
4038 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4039 I915_READ(VBLANK(cpu_transcoder)));
4040 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4041 I915_READ(VSYNC(cpu_transcoder)));
4042 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4043 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4044}
4045
003632d9 4046static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 4047{
4048 struct drm_i915_private *dev_priv = dev->dev_private;
4049 uint32_t temp;
4050
4051 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 4052 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 4053 return;
4054
4055 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4056 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4057
003632d9
ACO		 4058 temp &= ~FDI_BC_BIFURCATION_SELECT;
4059 if (enable)
4060 temp |= FDI_BC_BIFURCATION_SELECT;
4061
4062 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 4063 I915_WRITE(SOUTH_CHICKEN1, temp);
4064 POSTING_READ(SOUTH_CHICKEN1);
4065}
4066
4067static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4068{
4069 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 4070
4071 switch (intel_crtc->pipe) {
4072 case PIPE_A:
4073 break;
4074 case PIPE_B:
6e3c9717 4075 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4076 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4077 else
003632d9 4078 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4079
4080 break;
4081 case PIPE_C:
003632d9 4082 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4083
4084 break;
4085 default:
4086 BUG();
4087 }
4088}
4089
f67a559d
JB		 4090/*
4091 * Enable PCH resources required for PCH ports:
4092 * - PCH PLLs
4093 * - FDI training & RX/TX
4094 * - update transcoder timings
4095 * - DP transcoding bits
4096 * - transcoder
4097 */
4098static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 4099{
4100 struct drm_device *dev = crtc->dev;
4101 struct drm_i915_private *dev_priv = dev->dev_private;
4102 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4103 int pipe = intel_crtc->pipe;
ee7b9f93 4104 u32 reg, temp;
2c07245f 4105
ab9412ba 4106 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4107
1fbc0d78
DV		 4108 if (IS_IVYBRIDGE(dev))
4109 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4110
cd986abb
DV		 4111 /* Write the TU size bits before fdi link training, so that error
4112 * detection works. */
4113 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4114 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4115
c98e9dcf 4116 /* For PCH output, training FDI link */
674cf967 4117 dev_priv->display.fdi_link_train(crtc);
2c07245f 4118
3ad8a208
DV		 4119 /* We need to program the right clock selection before writing the pixel
4120 * mutliplier into the DPLL. */
303b81e0 4121 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4122 u32 sel;
4b645f14 4123
c98e9dcf 4124 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4125 temp |= TRANS_DPLL_ENABLE(pipe);
4126 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4127 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4128 temp |= sel;
4129 else
4130 temp &= ~sel;
c98e9dcf 4131 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4132 }
5eddb70b 4133
3ad8a208
DV		 4134 /* XXX: pch pll's can be enabled any time before we enable the PCH
4135 * transcoder, and we actually should do this to not upset any PCH
4136 * transcoder that already use the clock when we share it.
4137 *
4138 * Note that enable_shared_dpll tries to do the right thing, but
4139 * get_shared_dpll unconditionally resets the pll - we need that to have
4140 * the right LVDS enable sequence. */
85b3894f 4141 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4142
d9b6cb56
JB		 4143 /* set transcoder timing, panel must allow it */
4144 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4145 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4146
303b81e0 4147 intel_fdi_normal_train(crtc);
5e84e1a4 4148
c98e9dcf 4149 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4150 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4151 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4152 reg = TRANS_DP_CTL(pipe);
4153 temp = I915_READ(reg);
4154 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4155 TRANS_DP_SYNC_MASK |
4156 TRANS_DP_BPC_MASK);
e3ef4479 4157 temp |= TRANS_DP_OUTPUT_ENABLE;
9325c9f0 4158 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4159
4160 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4161 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4162 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4163 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4164
4165 switch (intel_trans_dp_port_sel(crtc)) {
4166 case PCH_DP_B:
5eddb70b 4167 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4168 break;
4169 case PCH_DP_C:
5eddb70b 4170 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4171 break;
4172 case PCH_DP_D:
5eddb70b 4173 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4174 break;
4175 default:
e95d41e1 4176 BUG();
32f9d658 4177 }
2c07245f 4178
5eddb70b 4179 I915_WRITE(reg, temp);
6be4a607 4180 }
b52eb4dc 4181
b8a4f404 4182 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4183}
4184
1507e5bd
PZ		 4185static void lpt_pch_enable(struct drm_crtc *crtc)
4186{
4187 struct drm_device *dev = crtc->dev;
4188 struct drm_i915_private *dev_priv = dev->dev_private;
4189 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4190 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4191
ab9412ba 4192 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4193
8c52b5e8 4194 lpt_program_iclkip(crtc);
1507e5bd 4195
0540e488 4196 /* Set transcoder timing. */
275f01b2 4197 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4198
937bb610 4199 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4200}
4201
716c2e55 4202void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 4203{
e2b78267 4204 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 4205
4206 if (pll == NULL)
4207 return;
4208
3e369b76 4209 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
1e6f2ddc 4210 WARN(1, "bad %s crtc mask\n", pll->name);
ee7b9f93
JB		 4211 return;
4212 }
4213
3e369b76
ACO		 4214 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4215 if (pll->config.crtc_mask == 0) {
f4a091c7
DV		 4216 WARN_ON(pll->on);
4217 WARN_ON(pll->active);
4218 }
4219
6e3c9717 4220 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 4221}
4222
190f68c5
ACO		 4223struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4224 struct intel_crtc_state *crtc_state)
ee7b9f93 4225{
e2b78267 4226 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4227 struct intel_shared_dpll *pll;
e2b78267 4228 enum intel_dpll_id i;
ee7b9f93 4229
98b6bd99
DV		 4230 if (HAS_PCH_IBX(dev_priv->dev)) {
4231 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4232 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4233 pll = &dev_priv->shared_dplls[i];
98b6bd99 4234
46edb027
DV		 4235 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4236 crtc->base.base.id, pll->name);
98b6bd99 4237
8bd31e67 4238 WARN_ON(pll->new_config->crtc_mask);
f2a69f44 4239
98b6bd99
DV		 4240 goto found;
4241 }
4242
bcddf610
S		 4243 if (IS_BROXTON(dev_priv->dev)) {
4244 /* PLL is attached to port in bxt */
4245 struct intel_encoder *encoder;
4246 struct intel_digital_port *intel_dig_port;
4247
4248 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4249 if (WARN_ON(!encoder))
4250 return NULL;
4251
4252 intel_dig_port = enc_to_dig_port(&encoder->base);
4253 /* 1:1 mapping between ports and PLLs */
4254 i = (enum intel_dpll_id)intel_dig_port->port;
4255 pll = &dev_priv->shared_dplls[i];
4256 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4257 crtc->base.base.id, pll->name);
4258 WARN_ON(pll->new_config->crtc_mask);
4259
4260 goto found;
4261 }
4262
e72f9fbf
DV		 4263 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4264 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4265
4266 /* Only want to check enabled timings first */
8bd31e67 4267 if (pll->new_config->crtc_mask == 0)
ee7b9f93
JB		 4268 continue;
4269
190f68c5 4270 if (memcmp(&crtc_state->dpll_hw_state,
8bd31e67
ACO		 4271 &pll->new_config->hw_state,
4272 sizeof(pll->new_config->hw_state)) == 0) {
4273 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4274 crtc->base.base.id, pll->name,
8bd31e67
ACO		 4275 pll->new_config->crtc_mask,
4276 pll->active);
ee7b9f93
JB		 4277 goto found;
4278 }
4279 }
4280
4281 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4282 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4283 pll = &dev_priv->shared_dplls[i];
8bd31e67 4284 if (pll->new_config->crtc_mask == 0) {
46edb027
DV		 4285 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4286 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4287 goto found;
4288 }
4289 }
4290
4291 return NULL;
4292
4293found:
8bd31e67 4294 if (pll->new_config->crtc_mask == 0)
190f68c5 4295 pll->new_config->hw_state = crtc_state->dpll_hw_state;
f2a69f44 4296
190f68c5 4297 crtc_state->shared_dpll = i;
46edb027
DV		 4298 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4299 pipe_name(crtc->pipe));
ee7b9f93 4300
8bd31e67 4301 pll->new_config->crtc_mask |= 1 << crtc->pipe;
e04c7350 4302
ee7b9f93
JB		 4303 return pll;
4304}
4305
8bd31e67
ACO		 4306/**
4307 * intel_shared_dpll_start_config - start a new PLL staged config
4308 * @dev_priv: DRM device
4309 * @clear_pipes: mask of pipes that will have their PLLs freed
4310 *
4311 * Starts a new PLL staged config, copying the current config but
4312 * releasing the references of pipes specified in clear_pipes.
4313 */
4314static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4315 unsigned clear_pipes)
4316{
4317 struct intel_shared_dpll *pll;
4318 enum intel_dpll_id i;
4319
4320 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4321 pll = &dev_priv->shared_dplls[i];
4322
4323 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4324 GFP_KERNEL);
4325 if (!pll->new_config)
4326 goto cleanup;
4327
4328 pll->new_config->crtc_mask &= ~clear_pipes;
4329 }
4330
4331 return 0;
4332
4333cleanup:
4334 while (--i >= 0) {
4335 pll = &dev_priv->shared_dplls[i];
f354d733 4336 kfree(pll->new_config);
8bd31e67
ACO		 4337 pll->new_config = NULL;
4338 }
4339
4340 return -ENOMEM;
4341}
4342
4343static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4344{
4345 struct intel_shared_dpll *pll;
4346 enum intel_dpll_id i;
4347
4348 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4349 pll = &dev_priv->shared_dplls[i];
4350
4351 WARN_ON(pll->new_config == &pll->config);
4352
4353 pll->config = *pll->new_config;
4354 kfree(pll->new_config);
4355 pll->new_config = NULL;
4356 }
4357}
4358
4359static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4360{
4361 struct intel_shared_dpll *pll;
4362 enum intel_dpll_id i;
4363
4364 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4365 pll = &dev_priv->shared_dplls[i];
4366
4367 WARN_ON(pll->new_config == &pll->config);
4368
4369 kfree(pll->new_config);
4370 pll->new_config = NULL;
4371 }
4372}
4373
a1520318 4374static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4375{
4376 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4377 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4378 u32 temp;
4379
4380 temp = I915_READ(dslreg);
4381 udelay(500);
4382 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4383 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4384 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4385 }
4386}
4387
a1b2278e
CK		 4388/**
4389 * skl_update_scaler_users - Stages update to crtc's scaler state
4390 * @intel_crtc: crtc
4391 * @crtc_state: crtc_state
4392 * @plane: plane (NULL indicates crtc is requesting update)
4393 * @plane_state: plane's state
4394 * @force_detach: request unconditional detachment of scaler
4395 *
4396 * This function updates scaler state for requested plane or crtc.
4397 * To request scaler usage update for a plane, caller shall pass plane pointer.
4398 * To request scaler usage update for crtc, caller shall pass plane pointer
4399 * as NULL.
4400 *
4401 * Return
4402 * 0 - scaler_usage updated successfully
4403 * error - requested scaling cannot be supported or other error condition
4404 */
4405int
4406skl_update_scaler_users(
4407 struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state,
4408 struct intel_plane *intel_plane, struct intel_plane_state *plane_state,
4409 int force_detach)
4410{
4411 int need_scaling;
4412 int idx;
4413 int src_w, src_h, dst_w, dst_h;
4414 int *scaler_id;
4415 struct drm_framebuffer *fb;
4416 struct intel_crtc_scaler_state *scaler_state;
6156a456 4417 unsigned int rotation;
a1b2278e
CK		 4418
4419 if (!intel_crtc || !crtc_state)
4420 return 0;
4421
4422 scaler_state = &crtc_state->scaler_state;
4423
4424 idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX;
4425 fb = intel_plane ? plane_state->base.fb : NULL;
4426
4427 if (intel_plane) {
4428 src_w = drm_rect_width(&plane_state->src) >> 16;
4429 src_h = drm_rect_height(&plane_state->src) >> 16;
4430 dst_w = drm_rect_width(&plane_state->dst);
4431 dst_h = drm_rect_height(&plane_state->dst);
4432 scaler_id = &plane_state->scaler_id;
6156a456 4433 rotation = plane_state->base.rotation;
a1b2278e
CK		 4434 } else {
4435 struct drm_display_mode *adjusted_mode =
4436 &crtc_state->base.adjusted_mode;
4437 src_w = crtc_state->pipe_src_w;
4438 src_h = crtc_state->pipe_src_h;
4439 dst_w = adjusted_mode->hdisplay;
4440 dst_h = adjusted_mode->vdisplay;
4441 scaler_id = &scaler_state->scaler_id;
6156a456 4442 rotation = DRM_ROTATE_0;
a1b2278e 4443 }
6156a456
CK		 4444
4445 need_scaling = intel_rotation_90_or_270(rotation) ?
4446 (src_h != dst_w || src_w != dst_h):
4447 (src_w != dst_w || src_h != dst_h);
a1b2278e
CK		 4448
4449 /*
4450 * if plane is being disabled or scaler is no more required or force detach
4451 * - free scaler binded to this plane/crtc
4452 * - in order to do this, update crtc->scaler_usage
4453 *
4454 * Here scaler state in crtc_state is set free so that
4455 * scaler can be assigned to other user. Actual register
4456 * update to free the scaler is done in plane/panel-fit programming.
4457 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4458 */
4459 if (force_detach || !need_scaling || (intel_plane &&
4460 (!fb || !plane_state->visible))) {
4461 if (*scaler_id >= 0) {
4462 scaler_state->scaler_users &= ~(1 << idx);
4463 scaler_state->scalers[*scaler_id].in_use = 0;
4464
4465 DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4466 "crtc_state = %p scaler_users = 0x%x\n",
4467 intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC",
4468 intel_plane ? intel_plane->base.base.id :
4469 intel_crtc->base.base.id, crtc_state,
4470 scaler_state->scaler_users);
4471 *scaler_id = -1;
4472 }
4473 return 0;
4474 }
4475
4476 /* range checks */
4477 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4478 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4479
4480 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4481 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4482 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4483 "size is out of scaler range\n",
4484 intel_plane ? "PLANE" : "CRTC",
4485 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4486 intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h);
4487 return -EINVAL;
4488 }
4489
4490 /* check colorkey */
225c228a
CK		 4491 if (WARN_ON(intel_plane &&
4492 intel_plane->ckey.flags != I915_SET_COLORKEY_NONE)) {
4493 DRM_DEBUG_KMS("PLANE:%d scaling %ux%u->%ux%u not allowed with colorkey",
4494 intel_plane->base.base.id, src_w, src_h, dst_w, dst_h);
a1b2278e
CK		 4495 return -EINVAL;
4496 }
4497
4498 /* Check src format */
4499 if (intel_plane) {
4500 switch (fb->pixel_format) {
4501 case DRM_FORMAT_RGB565:
4502 case DRM_FORMAT_XBGR8888:
4503 case DRM_FORMAT_XRGB8888:
4504 case DRM_FORMAT_ABGR8888:
4505 case DRM_FORMAT_ARGB8888:
4506 case DRM_FORMAT_XRGB2101010:
a1b2278e 4507 case DRM_FORMAT_XBGR2101010:
a1b2278e
CK		 4508 case DRM_FORMAT_YUYV:
4509 case DRM_FORMAT_YVYU:
4510 case DRM_FORMAT_UYVY:
4511 case DRM_FORMAT_VYUY:
4512 break;
4513 default:
4514 DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4515 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4516 return -EINVAL;
4517 }
4518 }
4519
4520 /* mark this plane as a scaler user in crtc_state */
4521 scaler_state->scaler_users |= (1 << idx);
4522 DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4523 "crtc_state = %p scaler_users = 0x%x\n",
4524 intel_plane ? "PLANE" : "CRTC",
4525 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4526 src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users);
4527 return 0;
4528}
4529
4530static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
bd2e244f
JB		 4531{
4532 struct drm_device *dev = crtc->base.dev;
4533 struct drm_i915_private *dev_priv = dev->dev_private;
4534 int pipe = crtc->pipe;
a1b2278e
CK		 4535 struct intel_crtc_scaler_state *scaler_state =
4536 &crtc->config->scaler_state;
4537
4538 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4539
4540 /* To update pfit, first update scaler state */
4541 skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable);
4542 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4543 skl_detach_scalers(crtc);
4544 if (!enable)
4545 return;
bd2e244f 4546
6e3c9717 4547 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK		 4548 int id;
4549
4550 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4551 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4552 return;
4553 }
4554
4555 id = scaler_state->scaler_id;
4556 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4557 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4558 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4559 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4560
4561 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB		 4562 }
4563}
4564
b074cec8
JB		 4565static void ironlake_pfit_enable(struct intel_crtc *crtc)
4566{
4567 struct drm_device *dev = crtc->base.dev;
4568 struct drm_i915_private *dev_priv = dev->dev_private;
4569 int pipe = crtc->pipe;
4570
6e3c9717 4571 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4572 /* Force use of hard-coded filter coefficients
4573 * as some pre-programmed values are broken,
4574 * e.g. x201.
4575 */
4576 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4577 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4578 PF_PIPE_SEL_IVB(pipe));
4579 else
4580 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4581 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4582 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4583 }
4584}
4585
4a3b8769 4586static void intel_enable_sprite_planes(struct drm_crtc *crtc)
bb53d4ae
VS		 4587{
4588 struct drm_device *dev = crtc->dev;
4589 enum pipe pipe = to_intel_crtc(crtc)->pipe;
af2b653b 4590 struct drm_plane *plane;
bb53d4ae
VS		 4591 struct intel_plane *intel_plane;
4592
af2b653b
MR		 4593 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4594 intel_plane = to_intel_plane(plane);
bb53d4ae
VS		 4595 if (intel_plane->pipe == pipe)
4596 intel_plane_restore(&intel_plane->base);
af2b653b 4597 }
bb53d4ae
VS		 4598}
4599
20bc8673 4600void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4601{
cea165c3
VS		 4602 struct drm_device *dev = crtc->base.dev;
4603 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4604
6e3c9717 4605 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4606 return;
4607
cea165c3
VS		 4608 /* We can only enable IPS after we enable a plane and wait for a vblank */
4609 intel_wait_for_vblank(dev, crtc->pipe);
4610
d77e4531 4611 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4612 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4613 mutex_lock(&dev_priv->rps.hw_lock);
4614 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4615 mutex_unlock(&dev_priv->rps.hw_lock);
4616 /* Quoting Art Runyan: "its not safe to expect any particular
4617 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4618 * mailbox." Moreover, the mailbox may return a bogus state,
4619 * so we need to just enable it and continue on.
2a114cc1
BW		 4620 */
4621 } else {
4622 I915_WRITE(IPS_CTL, IPS_ENABLE);
4623 /* The bit only becomes 1 in the next vblank, so this wait here
4624 * is essentially intel_wait_for_vblank. If we don't have this
4625 * and don't wait for vblanks until the end of crtc_enable, then
4626 * the HW state readout code will complain that the expected
4627 * IPS_CTL value is not the one we read. */
4628 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4629 DRM_ERROR("Timed out waiting for IPS enable\n");
4630 }
d77e4531
PZ		 4631}
4632
20bc8673 4633void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4634{
4635 struct drm_device *dev = crtc->base.dev;
4636 struct drm_i915_private *dev_priv = dev->dev_private;
4637
6e3c9717 4638 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4639 return;
4640
4641 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4642 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4643 mutex_lock(&dev_priv->rps.hw_lock);
4644 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4645 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4646 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4647 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4648 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4649 } else {
2a114cc1 4650 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4651 POSTING_READ(IPS_CTL);
4652 }
d77e4531
PZ		 4653
4654 /* We need to wait for a vblank before we can disable the plane. */
4655 intel_wait_for_vblank(dev, crtc->pipe);
4656}
4657
4658/** Loads the palette/gamma unit for the CRTC with the prepared values */
4659static void intel_crtc_load_lut(struct drm_crtc *crtc)
4660{
4661 struct drm_device *dev = crtc->dev;
4662 struct drm_i915_private *dev_priv = dev->dev_private;
4663 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4664 enum pipe pipe = intel_crtc->pipe;
4665 int palreg = PALETTE(pipe);
4666 int i;
4667 bool reenable_ips = false;
4668
4669 /* The clocks have to be on to load the palette. */
83d65738 4670 if (!crtc->state->enable || !intel_crtc->active)
d77e4531
PZ		 4671 return;
4672
50360403 4673 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
409ee761 4674 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4675 assert_dsi_pll_enabled(dev_priv);
4676 else
4677 assert_pll_enabled(dev_priv, pipe);
4678 }
4679
4680 /* use legacy palette for Ironlake */
7a1db49a 4681 if (!HAS_GMCH_DISPLAY(dev))
d77e4531
PZ		 4682 palreg = LGC_PALETTE(pipe);
4683
4684 /* Workaround : Do not read or write the pipe palette/gamma data while
4685 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4686 */
6e3c9717 4687 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4688 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4689 GAMMA_MODE_MODE_SPLIT)) {
4690 hsw_disable_ips(intel_crtc);
4691 reenable_ips = true;
4692 }
4693
4694 for (i = 0; i < 256; i++) {
4695 I915_WRITE(palreg + 4 * i,
4696 (intel_crtc->lut_r[i] << 16) |
4697 (intel_crtc->lut_g[i] << 8) |
4698 intel_crtc->lut_b[i]);
4699 }
4700
4701 if (reenable_ips)
4702 hsw_enable_ips(intel_crtc);
4703}
4704
7cac945f 4705static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
d3eedb1a 4706{
7cac945f 4707 if (intel_crtc->overlay) {
d3eedb1a
VS		 4708 struct drm_device *dev = intel_crtc->base.dev;
4709 struct drm_i915_private *dev_priv = dev->dev_private;
4710
4711 mutex_lock(&dev->struct_mutex);
4712 dev_priv->mm.interruptible = false;
4713 (void) intel_overlay_switch_off(intel_crtc->overlay);
4714 dev_priv->mm.interruptible = true;
4715 mutex_unlock(&dev->struct_mutex);
4716 }
4717
4718 /* Let userspace switch the overlay on again. In most cases userspace
4719 * has to recompute where to put it anyway.
4720 */
4721}
4722
87d4300a
ML		 4723/**
4724 * intel_post_enable_primary - Perform operations after enabling primary plane
4725 * @crtc: the CRTC whose primary plane was just enabled
4726 *
4727 * Performs potentially sleeping operations that must be done after the primary
4728 * plane is enabled, such as updating FBC and IPS. Note that this may be
4729 * called due to an explicit primary plane update, or due to an implicit
4730 * re-enable that is caused when a sprite plane is updated to no longer
4731 * completely hide the primary plane.
4732 */
4733static void
4734intel_post_enable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4735{
4736 struct drm_device *dev = crtc->dev;
87d4300a 4737 struct drm_i915_private *dev_priv = dev->dev_private;
a5c4d7bc
VS		 4738 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4739 int pipe = intel_crtc->pipe;
a5c4d7bc 4740
87d4300a
ML		 4741 /*
4742 * BDW signals flip done immediately if the plane
4743 * is disabled, even if the plane enable is already
4744 * armed to occur at the next vblank :(
4745 */
4746 if (IS_BROADWELL(dev))
4747 intel_wait_for_vblank(dev, pipe);
a5c4d7bc 4748
87d4300a
ML		 4749 /*
4750 * FIXME IPS should be fine as long as one plane is
4751 * enabled, but in practice it seems to have problems
4752 * when going from primary only to sprite only and vice
4753 * versa.
4754 */
a5c4d7bc
VS		 4755 hsw_enable_ips(intel_crtc);
4756
4757 mutex_lock(&dev->struct_mutex);
7ff0ebcc 4758 intel_fbc_update(dev);
a5c4d7bc 4759 mutex_unlock(&dev->struct_mutex);
f99d7069
DV		 4760
4761 /*
87d4300a
ML		 4762 * Gen2 reports pipe underruns whenever all planes are disabled.
4763 * So don't enable underrun reporting before at least some planes
4764 * are enabled.
4765 * FIXME: Need to fix the logic to work when we turn off all planes
4766 * but leave the pipe running.
f99d7069 4767 */
87d4300a
ML		 4768 if (IS_GEN2(dev))
4769 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4770
4771 /* Underruns don't raise interrupts, so check manually. */
4772 if (HAS_GMCH_DISPLAY(dev))
4773 i9xx_check_fifo_underruns(dev_priv);
a5c4d7bc
VS		 4774}
4775
87d4300a
ML		 4776/**
4777 * intel_pre_disable_primary - Perform operations before disabling primary plane
4778 * @crtc: the CRTC whose primary plane is to be disabled
4779 *
4780 * Performs potentially sleeping operations that must be done before the
4781 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4782 * be called due to an explicit primary plane update, or due to an implicit
4783 * disable that is caused when a sprite plane completely hides the primary
4784 * plane.
4785 */
4786static void
4787intel_pre_disable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4788{
4789 struct drm_device *dev = crtc->dev;
4790 struct drm_i915_private *dev_priv = dev->dev_private;
4791 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4792 int pipe = intel_crtc->pipe;
a5c4d7bc 4793
87d4300a
ML		 4794 /*
4795 * Gen2 reports pipe underruns whenever all planes are disabled.
4796 * So diasble underrun reporting before all the planes get disabled.
4797 * FIXME: Need to fix the logic to work when we turn off all planes
4798 * but leave the pipe running.
4799 */
4800 if (IS_GEN2(dev))
4801 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
a5c4d7bc 4802
87d4300a
ML		 4803 /*
4804 * Vblank time updates from the shadow to live plane control register
4805 * are blocked if the memory self-refresh mode is active at that
4806 * moment. So to make sure the plane gets truly disabled, disable
4807 * first the self-refresh mode. The self-refresh enable bit in turn
4808 * will be checked/applied by the HW only at the next frame start
4809 * event which is after the vblank start event, so we need to have a
4810 * wait-for-vblank between disabling the plane and the pipe.
4811 */
4812 if (HAS_GMCH_DISPLAY(dev))
4813 intel_set_memory_cxsr(dev_priv, false);
4814
4815 mutex_lock(&dev->struct_mutex);
e35fef21 4816 if (dev_priv->fbc.crtc == intel_crtc)
7ff0ebcc 4817 intel_fbc_disable(dev);
87d4300a 4818 mutex_unlock(&dev->struct_mutex);
a5c4d7bc 4819
87d4300a
ML		 4820 /*
4821 * FIXME IPS should be fine as long as one plane is
4822 * enabled, but in practice it seems to have problems
4823 * when going from primary only to sprite only and vice
4824 * versa.
4825 */
a5c4d7bc 4826 hsw_disable_ips(intel_crtc);
87d4300a
ML		 4827}
4828
4829static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4830{
87d4300a
ML		 4831 intel_enable_primary_hw_plane(crtc->primary, crtc);
4832 intel_enable_sprite_planes(crtc);
4833 intel_crtc_update_cursor(crtc, true);
87d4300a
ML		 4834
4835 intel_post_enable_primary(crtc);
4836}
4837
4838static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4839{
4840 struct drm_device *dev = crtc->dev;
4841 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4842 struct intel_plane *intel_plane;
4843 int pipe = intel_crtc->pipe;
4844
4845 intel_crtc_wait_for_pending_flips(crtc);
4846
4847 intel_pre_disable_primary(crtc);
a5c4d7bc 4848
7cac945f 4849 intel_crtc_dpms_overlay_disable(intel_crtc);
27321ae8
ML		 4850 for_each_intel_plane(dev, intel_plane) {
4851 if (intel_plane->pipe == pipe) {
4852 struct drm_crtc *from = intel_plane->base.crtc;
4853
4854 intel_plane->disable_plane(&intel_plane->base,
4855 from ?: crtc, true);
4856 }
4857 }
f98551ae 4858
f99d7069
DV		 4859 /*
4860 * FIXME: Once we grow proper nuclear flip support out of this we need
4861 * to compute the mask of flip planes precisely. For the time being
4862 * consider this a flip to a NULL plane.
4863 */
4864 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4865}
4866
f67a559d
JB		 4867static void ironlake_crtc_enable(struct drm_crtc *crtc)
4868{
4869 struct drm_device *dev = crtc->dev;
4870 struct drm_i915_private *dev_priv = dev->dev_private;
4871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4872 struct intel_encoder *encoder;
f67a559d 4873 int pipe = intel_crtc->pipe;
f67a559d 4874
83d65738 4875 WARN_ON(!crtc->state->enable);
08a48469 4876
f67a559d
JB		 4877 if (intel_crtc->active)
4878 return;
4879
6e3c9717 4880 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4881 intel_prepare_shared_dpll(intel_crtc);
4882
6e3c9717 4883 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4884 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4885
4886 intel_set_pipe_timings(intel_crtc);
4887
6e3c9717 4888 if (intel_crtc->config->has_pch_encoder) {
29407aab 4889 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4890 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4891 }
4892
4893 ironlake_set_pipeconf(crtc);
4894
f67a559d 4895 intel_crtc->active = true;
8664281b 4896
a72e4c9f
DV		 4897 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4898 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4899
f6736a1a 4900 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4901 if (encoder->pre_enable)
4902 encoder->pre_enable(encoder);
f67a559d 4903
6e3c9717 4904 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4905 /* Note: FDI PLL enabling _must_ be done before we enable the
4906 * cpu pipes, hence this is separate from all the other fdi/pch
4907 * enabling. */
88cefb6c 4908 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4909 } else {
4910 assert_fdi_tx_disabled(dev_priv, pipe);
4911 assert_fdi_rx_disabled(dev_priv, pipe);
4912 }
f67a559d 4913
b074cec8 4914 ironlake_pfit_enable(intel_crtc);
f67a559d 4915
9c54c0dd
JB		 4916 /*
4917 * On ILK+ LUT must be loaded before the pipe is running but with
4918 * clocks enabled
4919 */
4920 intel_crtc_load_lut(crtc);
4921
f37fcc2a 4922 intel_update_watermarks(crtc);
e1fdc473 4923 intel_enable_pipe(intel_crtc);
f67a559d 4924
6e3c9717 4925 if (intel_crtc->config->has_pch_encoder)
f67a559d 4926 ironlake_pch_enable(crtc);
c98e9dcf 4927
f9b61ff6
DV		 4928 assert_vblank_disabled(crtc);
4929 drm_crtc_vblank_on(crtc);
4930
fa5c73b1
DV		 4931 for_each_encoder_on_crtc(dev, crtc, encoder)
4932 encoder->enable(encoder);
61b77ddd
DV		 4933
4934 if (HAS_PCH_CPT(dev))
a1520318 4935 cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB		 4936}
4937
42db64ef
PZ		 4938/* IPS only exists on ULT machines and is tied to pipe A. */
4939static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4940{
f5adf94e 4941 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4942}
4943
e4916946
PZ		 4944/*
4945 * This implements the workaround described in the "notes" section of the mode
4946 * set sequence documentation. When going from no pipes or single pipe to
4947 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4948 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4949 */
4950static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4951{
4952 struct drm_device *dev = crtc->base.dev;
4953 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4954
4955 /* We want to get the other_active_crtc only if there's only 1 other
4956 * active crtc. */
d3fcc808 4957 for_each_intel_crtc(dev, crtc_it) {
e4916946
PZ		 4958 if (!crtc_it->active || crtc_it == crtc)
4959 continue;
4960
4961 if (other_active_crtc)
4962 return;
4963
4964 other_active_crtc = crtc_it;
4965 }
4966 if (!other_active_crtc)
4967 return;
4968
4969 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4970 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4971}
4972
4f771f10
PZ		 4973static void haswell_crtc_enable(struct drm_crtc *crtc)
4974{
4975 struct drm_device *dev = crtc->dev;
4976 struct drm_i915_private *dev_priv = dev->dev_private;
4977 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4978 struct intel_encoder *encoder;
4979 int pipe = intel_crtc->pipe;
4f771f10 4980
83d65738 4981 WARN_ON(!crtc->state->enable);
4f771f10
PZ		 4982
4983 if (intel_crtc->active)
4984 return;
4985
df8ad70c
DV		 4986 if (intel_crtc_to_shared_dpll(intel_crtc))
4987 intel_enable_shared_dpll(intel_crtc);
4988
6e3c9717 4989 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4990 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 4991
4992 intel_set_pipe_timings(intel_crtc);
4993
6e3c9717
ACO		 4994 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4995 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4996 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 4997 }
4998
6e3c9717 4999 if (intel_crtc->config->has_pch_encoder) {
229fca97 5000 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 5001 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 5002 }
5003
5004 haswell_set_pipeconf(crtc);
5005
5006 intel_set_pipe_csc(crtc);
5007
4f771f10 5008 intel_crtc->active = true;
8664281b 5009
a72e4c9f 5010 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ		 5011 for_each_encoder_on_crtc(dev, crtc, encoder)
5012 if (encoder->pre_enable)
5013 encoder->pre_enable(encoder);
5014
6e3c9717 5015 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 5016 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5017 true);
4fe9467d
ID		 5018 dev_priv->display.fdi_link_train(crtc);
5019 }
5020
1f544388 5021 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 5022
ff6d9f55 5023 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 5024 skylake_pfit_update(intel_crtc, 1);
ff6d9f55 5025 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5026 ironlake_pfit_enable(intel_crtc);
ff6d9f55
JB		 5027 else
5028 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10
PZ		 5029
5030 /*
5031 * On ILK+ LUT must be loaded before the pipe is running but with
5032 * clocks enabled
5033 */
5034 intel_crtc_load_lut(crtc);
5035
1f544388 5036 intel_ddi_set_pipe_settings(crtc);
8228c251 5037 intel_ddi_enable_transcoder_func(crtc);
4f771f10 5038
f37fcc2a 5039 intel_update_watermarks(crtc);
e1fdc473 5040 intel_enable_pipe(intel_crtc);
42db64ef 5041
6e3c9717 5042 if (intel_crtc->config->has_pch_encoder)
1507e5bd 5043 lpt_pch_enable(crtc);
4f771f10 5044
6e3c9717 5045 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA		 5046 intel_ddi_set_vc_payload_alloc(crtc, true);
5047
f9b61ff6
DV		 5048 assert_vblank_disabled(crtc);
5049 drm_crtc_vblank_on(crtc);
5050
8807e55b 5051 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 5052 encoder->enable(encoder);
8807e55b
JN		 5053 intel_opregion_notify_encoder(encoder, true);
5054 }
4f771f10 5055
e4916946
PZ		 5056 /* If we change the relative order between pipe/planes enabling, we need
5057 * to change the workaround. */
5058 haswell_mode_set_planes_workaround(intel_crtc);
4f771f10
PZ		 5059}
5060
3f8dce3a
DV		 5061static void ironlake_pfit_disable(struct intel_crtc *crtc)
5062{
5063 struct drm_device *dev = crtc->base.dev;
5064 struct drm_i915_private *dev_priv = dev->dev_private;
5065 int pipe = crtc->pipe;
5066
5067 /* To avoid upsetting the power well on haswell only disable the pfit if
5068 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 5069 if (crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 5070 I915_WRITE(PF_CTL(pipe), 0);
5071 I915_WRITE(PF_WIN_POS(pipe), 0);
5072 I915_WRITE(PF_WIN_SZ(pipe), 0);
5073 }
5074}
5075
6be4a607
JB		 5076static void ironlake_crtc_disable(struct drm_crtc *crtc)
5077{
5078 struct drm_device *dev = crtc->dev;
5079 struct drm_i915_private *dev_priv = dev->dev_private;
5080 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5081 struct intel_encoder *encoder;
6be4a607 5082 int pipe = intel_crtc->pipe;
5eddb70b 5083 u32 reg, temp;
b52eb4dc 5084
f7abfe8b
CW		 5085 if (!intel_crtc->active)
5086 return;
5087
ea9d758d
DV		 5088 for_each_encoder_on_crtc(dev, crtc, encoder)
5089 encoder->disable(encoder);
5090
f9b61ff6
DV		 5091 drm_crtc_vblank_off(crtc);
5092 assert_vblank_disabled(crtc);
5093
6e3c9717 5094 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 5095 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 5096
575f7ab7 5097 intel_disable_pipe(intel_crtc);
32f9d658 5098
3f8dce3a 5099 ironlake_pfit_disable(intel_crtc);
2c07245f 5100
5a74f70a
VS		 5101 if (intel_crtc->config->has_pch_encoder)
5102 ironlake_fdi_disable(crtc);
5103
bf49ec8c
DV		 5104 for_each_encoder_on_crtc(dev, crtc, encoder)
5105 if (encoder->post_disable)
5106 encoder->post_disable(encoder);
2c07245f 5107
6e3c9717 5108 if (intel_crtc->config->has_pch_encoder) {
d925c59a 5109 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 5110
d925c59a
DV		 5111 if (HAS_PCH_CPT(dev)) {
5112 /* disable TRANS_DP_CTL */
5113 reg = TRANS_DP_CTL(pipe);
5114 temp = I915_READ(reg);
5115 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5116 TRANS_DP_PORT_SEL_MASK);
5117 temp |= TRANS_DP_PORT_SEL_NONE;
5118 I915_WRITE(reg, temp);
5119
5120 /* disable DPLL_SEL */
5121 temp = I915_READ(PCH_DPLL_SEL);
11887397 5122 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 5123 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 5124 }
e3421a18 5125
d925c59a 5126 /* disable PCH DPLL */
e72f9fbf 5127 intel_disable_shared_dpll(intel_crtc);
8db9d77b 5128
d925c59a
DV		 5129 ironlake_fdi_pll_disable(intel_crtc);
5130 }
6b383a7f 5131
f7abfe8b 5132 intel_crtc->active = false;
46ba614c 5133 intel_update_watermarks(crtc);
d1ebd816
BW		 5134
5135 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5136 intel_fbc_update(dev);
d1ebd816 5137 mutex_unlock(&dev->struct_mutex);
6be4a607 5138}
1b3c7a47 5139
4f771f10 5140static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 5141{
4f771f10
PZ		 5142 struct drm_device *dev = crtc->dev;
5143 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5144 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5145 struct intel_encoder *encoder;
6e3c9717 5146 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 5147
4f771f10
PZ		 5148 if (!intel_crtc->active)
5149 return;
5150
8807e55b
JN		 5151 for_each_encoder_on_crtc(dev, crtc, encoder) {
5152 intel_opregion_notify_encoder(encoder, false);
4f771f10 5153 encoder->disable(encoder);
8807e55b 5154 }
4f771f10 5155
f9b61ff6
DV		 5156 drm_crtc_vblank_off(crtc);
5157 assert_vblank_disabled(crtc);
5158
6e3c9717 5159 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 5160 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5161 false);
575f7ab7 5162 intel_disable_pipe(intel_crtc);
4f771f10 5163
6e3c9717 5164 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 5165 intel_ddi_set_vc_payload_alloc(crtc, false);
5166
ad80a810 5167 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5168
ff6d9f55 5169 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 5170 skylake_pfit_update(intel_crtc, 0);
ff6d9f55 5171 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5172 ironlake_pfit_disable(intel_crtc);
ff6d9f55
JB		 5173 else
5174 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10 5175
1f544388 5176 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5177
6e3c9717 5178 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 5179 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 5180 intel_ddi_fdi_disable(crtc);
83616634 5181 }
4f771f10 5182
97b040aa
ID		 5183 for_each_encoder_on_crtc(dev, crtc, encoder)
5184 if (encoder->post_disable)
5185 encoder->post_disable(encoder);
5186
4f771f10 5187 intel_crtc->active = false;
46ba614c 5188 intel_update_watermarks(crtc);
4f771f10
PZ		 5189
5190 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5191 intel_fbc_update(dev);
4f771f10 5192 mutex_unlock(&dev->struct_mutex);
df8ad70c
DV		 5193
5194 if (intel_crtc_to_shared_dpll(intel_crtc))
5195 intel_disable_shared_dpll(intel_crtc);
4f771f10
PZ		 5196}
5197
ee7b9f93
JB		 5198static void ironlake_crtc_off(struct drm_crtc *crtc)
5199{
5200 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 5201 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 5202}
5203
6441ab5f 5204
2dd24552
JB		 5205static void i9xx_pfit_enable(struct intel_crtc *crtc)
5206{
5207 struct drm_device *dev = crtc->base.dev;
5208 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5209 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5210
681a8504 5211 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 5212 return;
5213
2dd24552 5214 /*
c0b03411
DV		 5215 * The panel fitter should only be adjusted whilst the pipe is disabled,
5216 * according to register description and PRM.
2dd24552 5217 */
c0b03411
DV		 5218 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5219 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5220
b074cec8
JB		 5221 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5222 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 5223
5224 /* Border color in case we don't scale up to the full screen. Black by
5225 * default, change to something else for debugging. */
5226 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 5227}
5228
d05410f9
DA		 5229static enum intel_display_power_domain port_to_power_domain(enum port port)
5230{
5231 switch (port) {
5232 case PORT_A:
5233 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5234 case PORT_B:
5235 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5236 case PORT_C:
5237 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5238 case PORT_D:
5239 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5240 default:
5241 WARN_ON_ONCE(1);
5242 return POWER_DOMAIN_PORT_OTHER;
5243 }
5244}
5245
77d22dca
ID		 5246#define for_each_power_domain(domain, mask) \
5247 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5248 if ((1 << (domain)) & (mask))
5249
319be8ae
ID		 5250enum intel_display_power_domain
5251intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5252{
5253 struct drm_device *dev = intel_encoder->base.dev;
5254 struct intel_digital_port *intel_dig_port;
5255
5256 switch (intel_encoder->type) {
5257 case INTEL_OUTPUT_UNKNOWN:
5258 /* Only DDI platforms should ever use this output type */
5259 WARN_ON_ONCE(!HAS_DDI(dev));
5260 case INTEL_OUTPUT_DISPLAYPORT:
5261 case INTEL_OUTPUT_HDMI:
5262 case INTEL_OUTPUT_EDP:
5263 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5264 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 5265 case INTEL_OUTPUT_DP_MST:
5266 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5267 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 5268 case INTEL_OUTPUT_ANALOG:
5269 return POWER_DOMAIN_PORT_CRT;
5270 case INTEL_OUTPUT_DSI:
5271 return POWER_DOMAIN_PORT_DSI;
5272 default:
5273 return POWER_DOMAIN_PORT_OTHER;
5274 }
5275}
5276
5277static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5278{
319be8ae
ID		 5279 struct drm_device *dev = crtc->dev;
5280 struct intel_encoder *intel_encoder;
5281 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5282 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 5283 unsigned long mask;
5284 enum transcoder transcoder;
5285
5286 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5287
5288 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5289 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 5290 if (intel_crtc->config->pch_pfit.enabled ||
5291 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 5292 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5293
319be8ae
ID		 5294 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5295 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5296
77d22dca
ID		 5297 return mask;
5298}
5299
679dacd4 5300static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
77d22dca 5301{
679dacd4 5302 struct drm_device *dev = state->dev;
77d22dca
ID		 5303 struct drm_i915_private *dev_priv = dev->dev_private;
5304 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5305 struct intel_crtc *crtc;
5306
5307 /*
5308 * First get all needed power domains, then put all unneeded, to avoid
5309 * any unnecessary toggling of the power wells.
5310 */
d3fcc808 5311 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5312 enum intel_display_power_domain domain;
5313
83d65738 5314 if (!crtc->base.state->enable)
77d22dca
ID		 5315 continue;
5316
319be8ae 5317 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
77d22dca
ID		 5318
5319 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5320 intel_display_power_get(dev_priv, domain);
5321 }
5322
50f6e502 5323 if (dev_priv->display.modeset_global_resources)
679dacd4 5324 dev_priv->display.modeset_global_resources(state);
50f6e502 5325
d3fcc808 5326 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5327 enum intel_display_power_domain domain;
5328
5329 for_each_power_domain(domain, crtc->enabled_power_domains)
5330 intel_display_power_put(dev_priv, domain);
5331
5332 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5333 }
5334
5335 intel_display_set_init_power(dev_priv, false);
5336}
5337
f8437dd1
VK		 5338void broxton_set_cdclk(struct drm_device *dev, int frequency)
5339{
5340 struct drm_i915_private *dev_priv = dev->dev_private;
5341 uint32_t divider;
5342 uint32_t ratio;
5343 uint32_t current_freq;
5344 int ret;
5345
5346 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5347 switch (frequency) {
5348 case 144000:
5349 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5350 ratio = BXT_DE_PLL_RATIO(60);
5351 break;
5352 case 288000:
5353 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5354 ratio = BXT_DE_PLL_RATIO(60);
5355 break;
5356 case 384000:
5357 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5358 ratio = BXT_DE_PLL_RATIO(60);
5359 break;
5360 case 576000:
5361 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5362 ratio = BXT_DE_PLL_RATIO(60);
5363 break;
5364 case 624000:
5365 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5366 ratio = BXT_DE_PLL_RATIO(65);
5367 break;
5368 case 19200:
5369 /*
5370 * Bypass frequency with DE PLL disabled. Init ratio, divider
5371 * to suppress GCC warning.
5372 */
5373 ratio = 0;
5374 divider = 0;
5375 break;
5376 default:
5377 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5378
5379 return;
5380 }
5381
5382 mutex_lock(&dev_priv->rps.hw_lock);
5383 /* Inform power controller of upcoming frequency change */
5384 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5385 0x80000000);
5386 mutex_unlock(&dev_priv->rps.hw_lock);
5387
5388 if (ret) {
5389 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5390 ret, frequency);
5391 return;
5392 }
5393
5394 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5395 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5396 current_freq = current_freq * 500 + 1000;
5397
5398 /*
5399 * DE PLL has to be disabled when
5400 * - setting to 19.2MHz (bypass, PLL isn't used)
5401 * - before setting to 624MHz (PLL needs toggling)
5402 * - before setting to any frequency from 624MHz (PLL needs toggling)
5403 */
5404 if (frequency == 19200 || frequency == 624000 ||
5405 current_freq == 624000) {
5406 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5407 /* Timeout 200us */
5408 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5409 1))
5410 DRM_ERROR("timout waiting for DE PLL unlock\n");
5411 }
5412
5413 if (frequency != 19200) {
5414 uint32_t val;
5415
5416 val = I915_READ(BXT_DE_PLL_CTL);
5417 val &= ~BXT_DE_PLL_RATIO_MASK;
5418 val |= ratio;
5419 I915_WRITE(BXT_DE_PLL_CTL, val);
5420
5421 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5422 /* Timeout 200us */
5423 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5424 DRM_ERROR("timeout waiting for DE PLL lock\n");
5425
5426 val = I915_READ(CDCLK_CTL);
5427 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5428 val |= divider;
5429 /*
5430 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5431 * enable otherwise.
5432 */
5433 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5434 if (frequency >= 500000)
5435 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5436
5437 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5438 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5439 val |= (frequency - 1000) / 500;
5440 I915_WRITE(CDCLK_CTL, val);
5441 }
5442
5443 mutex_lock(&dev_priv->rps.hw_lock);
5444 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5445 DIV_ROUND_UP(frequency, 25000));
5446 mutex_unlock(&dev_priv->rps.hw_lock);
5447
5448 if (ret) {
5449 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5450 ret, frequency);
5451 return;
5452 }
5453
5454 dev_priv->cdclk_freq = frequency;
5455}
5456
5457void broxton_init_cdclk(struct drm_device *dev)
5458{
5459 struct drm_i915_private *dev_priv = dev->dev_private;
5460 uint32_t val;
5461
5462 /*
5463 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5464 * or else the reset will hang because there is no PCH to respond.
5465 * Move the handshake programming to initialization sequence.
5466 * Previously was left up to BIOS.
5467 */
5468 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5469 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5470 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5471
5472 /* Enable PG1 for cdclk */
5473 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5474
5475 /* check if cd clock is enabled */
5476 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5477 DRM_DEBUG_KMS("Display already initialized\n");
5478 return;
5479 }
5480
5481 /*
5482 * FIXME:
5483 * - The initial CDCLK needs to be read from VBT.
5484 * Need to make this change after VBT has changes for BXT.
5485 * - check if setting the max (or any) cdclk freq is really necessary
5486 * here, it belongs to modeset time
5487 */
5488 broxton_set_cdclk(dev, 624000);
5489
5490 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
22e02c0b
VS		 5491 POSTING_READ(DBUF_CTL);
5492
f8437dd1
VK		 5493 udelay(10);
5494
5495 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5496 DRM_ERROR("DBuf power enable timeout!\n");
5497}
5498
5499void broxton_uninit_cdclk(struct drm_device *dev)
5500{
5501 struct drm_i915_private *dev_priv = dev->dev_private;
5502
5503 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
22e02c0b
VS		 5504 POSTING_READ(DBUF_CTL);
5505
f8437dd1
VK		 5506 udelay(10);
5507
5508 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5509 DRM_ERROR("DBuf power disable timeout!\n");
5510
5511 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5512 broxton_set_cdclk(dev, 19200);
5513
5514 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5515}
5516
5d96d8af
DL		 5517static const struct skl_cdclk_entry {
5518 unsigned int freq;
5519 unsigned int vco;
5520} skl_cdclk_frequencies[] = {
5521 { .freq = 308570, .vco = 8640 },
5522 { .freq = 337500, .vco = 8100 },
5523 { .freq = 432000, .vco = 8640 },
5524 { .freq = 450000, .vco = 8100 },
5525 { .freq = 540000, .vco = 8100 },
5526 { .freq = 617140, .vco = 8640 },
5527 { .freq = 675000, .vco = 8100 },
5528};
5529
5530static unsigned int skl_cdclk_decimal(unsigned int freq)
5531{
5532 return (freq - 1000) / 500;
5533}
5534
5535static unsigned int skl_cdclk_get_vco(unsigned int freq)
5536{
5537 unsigned int i;
5538
5539 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5540 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5541
5542 if (e->freq == freq)
5543 return e->vco;
5544 }
5545
5546 return 8100;
5547}
5548
5549static void
5550skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5551{
5552 unsigned int min_freq;
5553 u32 val;
5554
5555 /* select the minimum CDCLK before enabling DPLL 0 */
5556 val = I915_READ(CDCLK_CTL);
5557 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5558 val |= CDCLK_FREQ_337_308;
5559
5560 if (required_vco == 8640)
5561 min_freq = 308570;
5562 else
5563 min_freq = 337500;
5564
5565 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5566
5567 I915_WRITE(CDCLK_CTL, val);
5568 POSTING_READ(CDCLK_CTL);
5569
5570 /*
5571 * We always enable DPLL0 with the lowest link rate possible, but still
5572 * taking into account the VCO required to operate the eDP panel at the
5573 * desired frequency. The usual DP link rates operate with a VCO of
5574 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5575 * The modeset code is responsible for the selection of the exact link
5576 * rate later on, with the constraint of choosing a frequency that
5577 * works with required_vco.
5578 */
5579 val = I915_READ(DPLL_CTRL1);
5580
5581 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5582 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5583 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5584 if (required_vco == 8640)
5585 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5586 SKL_DPLL0);
5587 else
5588 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5589 SKL_DPLL0);
5590
5591 I915_WRITE(DPLL_CTRL1, val);
5592 POSTING_READ(DPLL_CTRL1);
5593
5594 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5595
5596 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5597 DRM_ERROR("DPLL0 not locked\n");
5598}
5599
5600static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5601{
5602 int ret;
5603 u32 val;
5604
5605 /* inform PCU we want to change CDCLK */
5606 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5607 mutex_lock(&dev_priv->rps.hw_lock);
5608 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5609 mutex_unlock(&dev_priv->rps.hw_lock);
5610
5611 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5612}
5613
5614static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5615{
5616 unsigned int i;
5617
5618 for (i = 0; i < 15; i++) {
5619 if (skl_cdclk_pcu_ready(dev_priv))
5620 return true;
5621 udelay(10);
5622 }
5623
5624 return false;
5625}
5626
5627static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5628{
5629 u32 freq_select, pcu_ack;
5630
5631 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5632
5633 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5634 DRM_ERROR("failed to inform PCU about cdclk change\n");
5635 return;
5636 }
5637
5638 /* set CDCLK_CTL */
5639 switch(freq) {
5640 case 450000:
5641 case 432000:
5642 freq_select = CDCLK_FREQ_450_432;
5643 pcu_ack = 1;
5644 break;
5645 case 540000:
5646 freq_select = CDCLK_FREQ_540;
5647 pcu_ack = 2;
5648 break;
5649 case 308570:
5650 case 337500:
5651 default:
5652 freq_select = CDCLK_FREQ_337_308;
5653 pcu_ack = 0;
5654 break;
5655 case 617140:
5656 case 675000:
5657 freq_select = CDCLK_FREQ_675_617;
5658 pcu_ack = 3;
5659 break;
5660 }
5661
5662 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5663 POSTING_READ(CDCLK_CTL);
5664
5665 /* inform PCU of the change */
5666 mutex_lock(&dev_priv->rps.hw_lock);
5667 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5668 mutex_unlock(&dev_priv->rps.hw_lock);
5669}
5670
5671void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5672{
5673 /* disable DBUF power */
5674 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5675 POSTING_READ(DBUF_CTL);
5676
5677 udelay(10);
5678
5679 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5680 DRM_ERROR("DBuf power disable timeout\n");
5681
5682 /* disable DPLL0 */
5683 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5684 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5685 DRM_ERROR("Couldn't disable DPLL0\n");
5686
5687 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5688}
5689
5690void skl_init_cdclk(struct drm_i915_private *dev_priv)
5691{
5692 u32 val;
5693 unsigned int required_vco;
5694
5695 /* enable PCH reset handshake */
5696 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5697 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5698
5699 /* enable PG1 and Misc I/O */
5700 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5701
5702 /* DPLL0 already enabed !? */
5703 if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5704 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5705 return;
5706 }
5707
5708 /* enable DPLL0 */
5709 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5710 skl_dpll0_enable(dev_priv, required_vco);
5711
5712 /* set CDCLK to the frequency the BIOS chose */
5713 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5714
5715 /* enable DBUF power */
5716 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5717 POSTING_READ(DBUF_CTL);
5718
5719 udelay(10);
5720
5721 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5722 DRM_ERROR("DBuf power enable timeout\n");
5723}
5724
dfcab17e 5725/* returns HPLL frequency in kHz */
f8bf63fd 5726static int valleyview_get_vco(struct drm_i915_private *dev_priv)
30a970c6 5727{
586f49dc 5728 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
30a970c6 5729
586f49dc 5730 /* Obtain SKU information */
a580516d 5731 mutex_lock(&dev_priv->sb_lock);
586f49dc
JB		 5732 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5733 CCK_FUSE_HPLL_FREQ_MASK;
a580516d 5734 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5735
dfcab17e 5736 return vco_freq[hpll_freq] * 1000;
30a970c6
JB		 5737}
5738
f8bf63fd
VS		 5739static void vlv_update_cdclk(struct drm_device *dev)
5740{
5741 struct drm_i915_private *dev_priv = dev->dev_private;
5742
164dfd28 5743 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
43dc52c3 5744 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
164dfd28 5745 dev_priv->cdclk_freq);
f8bf63fd
VS		 5746
5747 /*
5748 * Program the gmbus_freq based on the cdclk frequency.
5749 * BSpec erroneously claims we should aim for 4MHz, but
5750 * in fact 1MHz is the correct frequency.
5751 */
164dfd28 5752 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
f8bf63fd
VS		 5753}
5754
30a970c6
JB		 5755/* Adjust CDclk dividers to allow high res or save power if possible */
5756static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5757{
5758 struct drm_i915_private *dev_priv = dev->dev_private;
5759 u32 val, cmd;
5760
164dfd28
VK		 5761 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5762 != dev_priv->cdclk_freq);
d60c4473 5763
dfcab17e 5764 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5765 cmd = 2;
dfcab17e 5766 else if (cdclk == 266667)
30a970c6
JB		 5767 cmd = 1;
5768 else
5769 cmd = 0;
5770
5771 mutex_lock(&dev_priv->rps.hw_lock);
5772 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5773 val &= ~DSPFREQGUAR_MASK;
5774 val |= (cmd << DSPFREQGUAR_SHIFT);
5775 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5776 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5777 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5778 50)) {
5779 DRM_ERROR("timed out waiting for CDclk change\n");
5780 }
5781 mutex_unlock(&dev_priv->rps.hw_lock);
5782
54433e91
VS		 5783 mutex_lock(&dev_priv->sb_lock);
5784
dfcab17e 5785 if (cdclk == 400000) {
6bcda4f0 5786 u32 divider;
30a970c6 5787
6bcda4f0 5788 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6 5789
30a970c6
JB		 5790 /* adjust cdclk divider */
5791 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
9cf33db5 5792 val &= ~DISPLAY_FREQUENCY_VALUES;
30a970c6
JB		 5793 val |= divider;
5794 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5795
5796 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5797 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5798 50))
5799 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5800 }
5801
30a970c6
JB		 5802 /* adjust self-refresh exit latency value */
5803 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5804 val &= ~0x7f;
5805
5806 /*
5807 * For high bandwidth configs, we set a higher latency in the bunit
5808 * so that the core display fetch happens in time to avoid underruns.
5809 */
dfcab17e 5810 if (cdclk == 400000)
30a970c6
JB		 5811 val |= 4500 / 250; /* 4.5 usec */
5812 else
5813 val |= 3000 / 250; /* 3.0 usec */
5814 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
54433e91 5815
a580516d 5816 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5817
f8bf63fd 5818 vlv_update_cdclk(dev);
30a970c6
JB		 5819}
5820
383c5a6a
VS		 5821static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5822{
5823 struct drm_i915_private *dev_priv = dev->dev_private;
5824 u32 val, cmd;
5825
164dfd28
VK		 5826 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5827 != dev_priv->cdclk_freq);
383c5a6a
VS		 5828
5829 switch (cdclk) {
383c5a6a
VS		 5830 case 333333:
5831 case 320000:
383c5a6a 5832 case 266667:
383c5a6a 5833 case 200000:
383c5a6a
VS		 5834 break;
5835 default:
5f77eeb0 5836 MISSING_CASE(cdclk);
383c5a6a
VS		 5837 return;
5838 }
5839
9d0d3fda
VS		 5840 /*
5841 * Specs are full of misinformation, but testing on actual
5842 * hardware has shown that we just need to write the desired
5843 * CCK divider into the Punit register.
5844 */
5845 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5846
383c5a6a
VS		 5847 mutex_lock(&dev_priv->rps.hw_lock);
5848 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5849 val &= ~DSPFREQGUAR_MASK_CHV;
5850 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5851 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5852 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5853 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5854 50)) {
5855 DRM_ERROR("timed out waiting for CDclk change\n");
5856 }
5857 mutex_unlock(&dev_priv->rps.hw_lock);
5858
5859 vlv_update_cdclk(dev);
5860}
5861
30a970c6
JB		 5862static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5863 int max_pixclk)
5864{
6bcda4f0 5865 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5866 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5867
30a970c6
JB		 5868 /*
5869 * Really only a few cases to deal with, as only 4 CDclks are supported:
5870 * 200MHz
5871 * 267MHz
29dc7ef3 5872 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5873 * 400MHz (VLV only)
5874 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5875 * of the lower bin and adjust if needed.
e37c67a1
VS		 5876 *
5877 * We seem to get an unstable or solid color picture at 200MHz.
5878 * Not sure what's wrong. For now use 200MHz only when all pipes
5879 * are off.
30a970c6 5880 */
6cca3195
VS		 5881 if (!IS_CHERRYVIEW(dev_priv) &&
5882 max_pixclk > freq_320*limit/100)
dfcab17e 5883 return 400000;
6cca3195 5884 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5885 return freq_320;
e37c67a1 5886 else if (max_pixclk > 0)
dfcab17e 5887 return 266667;
e37c67a1
VS		 5888 else
5889 return 200000;
30a970c6
JB		 5890}
5891
f8437dd1
VK		 5892static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5893 int max_pixclk)
5894{
5895 /*
5896 * FIXME:
5897 * - remove the guardband, it's not needed on BXT
5898 * - set 19.2MHz bypass frequency if there are no active pipes
5899 */
5900 if (max_pixclk > 576000*9/10)
5901 return 624000;
5902 else if (max_pixclk > 384000*9/10)
5903 return 576000;
5904 else if (max_pixclk > 288000*9/10)
5905 return 384000;
5906 else if (max_pixclk > 144000*9/10)
5907 return 288000;
5908 else
5909 return 144000;
5910}
5911
a821fc46
ACO		 5912/* Compute the max pixel clock for new configuration. Uses atomic state if
5913 * that's non-NULL, look at current state otherwise. */
5914static int intel_mode_max_pixclk(struct drm_device *dev,
5915 struct drm_atomic_state *state)
30a970c6 5916{
30a970c6 5917 struct intel_crtc *intel_crtc;
304603f4 5918 struct intel_crtc_state *crtc_state;
30a970c6
JB		 5919 int max_pixclk = 0;
5920
d3fcc808 5921 for_each_intel_crtc(dev, intel_crtc) {
a821fc46
ACO		 5922 if (state)
5923 crtc_state =
5924 intel_atomic_get_crtc_state(state, intel_crtc);
5925 else
5926 crtc_state = intel_crtc->config;
304603f4
ACO		 5927 if (IS_ERR(crtc_state))
5928 return PTR_ERR(crtc_state);
5929
5930 if (!crtc_state->base.enable)
5931 continue;
5932
5933 max_pixclk = max(max_pixclk,
5934 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5935 }
5936
5937 return max_pixclk;
5938}
5939
0a9ab303 5940static int valleyview_modeset_global_pipes(struct drm_atomic_state *state)
30a970c6 5941{
304603f4 5942 struct drm_i915_private *dev_priv = to_i915(state->dev);
0a9ab303
ACO		 5943 struct drm_crtc *crtc;
5944 struct drm_crtc_state *crtc_state;
a821fc46 5945 int max_pixclk = intel_mode_max_pixclk(state->dev, state);
0a9ab303 5946 int cdclk, i;
30a970c6 5947
304603f4
ACO		 5948 if (max_pixclk < 0)
5949 return max_pixclk;
30a970c6 5950
f8437dd1
VK		 5951 if (IS_VALLEYVIEW(dev_priv))
5952 cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5953 else
5954 cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
5955
5956 if (cdclk == dev_priv->cdclk_freq)
304603f4 5957 return 0;
30a970c6 5958
0a9ab303
ACO		 5959 /* add all active pipes to the state */
5960 for_each_crtc(state->dev, crtc) {
5961 if (!crtc->state->enable)
5962 continue;
5963
5964 crtc_state = drm_atomic_get_crtc_state(state, crtc);
5965 if (IS_ERR(crtc_state))
5966 return PTR_ERR(crtc_state);
5967 }
5968
2f2d7aa1 5969 /* disable/enable all currently active pipes while we change cdclk */
0a9ab303
ACO		 5970 for_each_crtc_in_state(state, crtc, crtc_state, i)
5971 if (crtc_state->enable)
5972 crtc_state->mode_changed = true;
304603f4
ACO		 5973
5974 return 0;
30a970c6
JB		 5975}
5976
1e69cd74
VS		 5977static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5978{
5979 unsigned int credits, default_credits;
5980
5981 if (IS_CHERRYVIEW(dev_priv))
5982 default_credits = PFI_CREDIT(12);
5983 else
5984 default_credits = PFI_CREDIT(8);
5985
164dfd28 5986 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
1e69cd74
VS		 5987 /* CHV suggested value is 31 or 63 */
5988 if (IS_CHERRYVIEW(dev_priv))
5989 credits = PFI_CREDIT_31;
5990 else
5991 credits = PFI_CREDIT(15);
5992 } else {
5993 credits = default_credits;
5994 }
5995
5996 /*
5997 * WA - write default credits before re-programming
5998 * FIXME: should we also set the resend bit here?
5999 */
6000 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6001 default_credits);
6002
6003 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6004 credits | PFI_CREDIT_RESEND);
6005
6006 /*
6007 * FIXME is this guaranteed to clear
6008 * immediately or should we poll for it?
6009 */
6010 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6011}
6012
a821fc46 6013static void valleyview_modeset_global_resources(struct drm_atomic_state *old_state)
30a970c6 6014{
a821fc46 6015 struct drm_device *dev = old_state->dev;
30a970c6 6016 struct drm_i915_private *dev_priv = dev->dev_private;
a821fc46 6017 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
304603f4
ACO		 6018 int req_cdclk;
6019
a821fc46
ACO		 6020 /* The path in intel_mode_max_pixclk() with a NULL atomic state should
6021 * never fail. */
304603f4
ACO		 6022 if (WARN_ON(max_pixclk < 0))
6023 return;
30a970c6 6024
304603f4 6025 req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
30a970c6 6026
164dfd28 6027 if (req_cdclk != dev_priv->cdclk_freq) {
738c05c0
ID		 6028 /*
6029 * FIXME: We can end up here with all power domains off, yet
6030 * with a CDCLK frequency other than the minimum. To account
6031 * for this take the PIPE-A power domain, which covers the HW
6032 * blocks needed for the following programming. This can be
6033 * removed once it's guaranteed that we get here either with
6034 * the minimum CDCLK set, or the required power domains
6035 * enabled.
6036 */
6037 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6038
383c5a6a
VS		 6039 if (IS_CHERRYVIEW(dev))
6040 cherryview_set_cdclk(dev, req_cdclk);
6041 else
6042 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 6043
1e69cd74
VS		 6044 vlv_program_pfi_credits(dev_priv);
6045
738c05c0 6046 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
383c5a6a 6047 }
30a970c6
JB		 6048}
6049
89b667f8
JB		 6050static void valleyview_crtc_enable(struct drm_crtc *crtc)
6051{
6052 struct drm_device *dev = crtc->dev;
a72e4c9f 6053 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 6054 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6055 struct intel_encoder *encoder;
6056 int pipe = intel_crtc->pipe;
23538ef1 6057 bool is_dsi;
89b667f8 6058
83d65738 6059 WARN_ON(!crtc->state->enable);
89b667f8
JB		 6060
6061 if (intel_crtc->active)
6062 return;
6063
409ee761 6064 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 6065
1ae0d137
VS		 6066 if (!is_dsi) {
6067 if (IS_CHERRYVIEW(dev))
6e3c9717 6068 chv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 6069 else
6e3c9717 6070 vlv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 6071 }
5b18e57c 6072
6e3c9717 6073 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6074 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6075
6076 intel_set_pipe_timings(intel_crtc);
6077
c14b0485
VS		 6078 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6079 struct drm_i915_private *dev_priv = dev->dev_private;
6080
6081 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6082 I915_WRITE(CHV_CANVAS(pipe), 0);
6083 }
6084
5b18e57c
DV		 6085 i9xx_set_pipeconf(intel_crtc);
6086
89b667f8 6087 intel_crtc->active = true;
89b667f8 6088
a72e4c9f 6089 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6090
89b667f8
JB		 6091 for_each_encoder_on_crtc(dev, crtc, encoder)
6092 if (encoder->pre_pll_enable)
6093 encoder->pre_pll_enable(encoder);
6094
9d556c99
CML		 6095 if (!is_dsi) {
6096 if (IS_CHERRYVIEW(dev))
6e3c9717 6097 chv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6098 else
6e3c9717 6099 vlv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6100 }
89b667f8
JB		 6101
6102 for_each_encoder_on_crtc(dev, crtc, encoder)
6103 if (encoder->pre_enable)
6104 encoder->pre_enable(encoder);
6105
2dd24552
JB		 6106 i9xx_pfit_enable(intel_crtc);
6107
63cbb074
VS		 6108 intel_crtc_load_lut(crtc);
6109
f37fcc2a 6110 intel_update_watermarks(crtc);
e1fdc473 6111 intel_enable_pipe(intel_crtc);
be6a6f8e 6112
4b3a9526
VS		 6113 assert_vblank_disabled(crtc);
6114 drm_crtc_vblank_on(crtc);
6115
f9b61ff6
DV		 6116 for_each_encoder_on_crtc(dev, crtc, encoder)
6117 encoder->enable(encoder);
89b667f8
JB		 6118}
6119
f13c2ef3
DV		 6120static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6121{
6122 struct drm_device *dev = crtc->base.dev;
6123 struct drm_i915_private *dev_priv = dev->dev_private;
6124
6e3c9717
ACO		 6125 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6126 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 6127}
6128
0b8765c6 6129static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 6130{
6131 struct drm_device *dev = crtc->dev;
a72e4c9f 6132 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 6133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6134 struct intel_encoder *encoder;
79e53945 6135 int pipe = intel_crtc->pipe;
79e53945 6136
83d65738 6137 WARN_ON(!crtc->state->enable);
08a48469 6138
f7abfe8b
CW		 6139 if (intel_crtc->active)
6140 return;
6141
f13c2ef3
DV		 6142 i9xx_set_pll_dividers(intel_crtc);
6143
6e3c9717 6144 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6145 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6146
6147 intel_set_pipe_timings(intel_crtc);
6148
5b18e57c
DV		 6149 i9xx_set_pipeconf(intel_crtc);
6150
f7abfe8b 6151 intel_crtc->active = true;
6b383a7f 6152
4a3436e8 6153 if (!IS_GEN2(dev))
a72e4c9f 6154 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6155
9d6d9f19
MK		 6156 for_each_encoder_on_crtc(dev, crtc, encoder)
6157 if (encoder->pre_enable)
6158 encoder->pre_enable(encoder);
6159
f6736a1a
DV		 6160 i9xx_enable_pll(intel_crtc);
6161
2dd24552
JB		 6162 i9xx_pfit_enable(intel_crtc);
6163
63cbb074
VS		 6164 intel_crtc_load_lut(crtc);
6165
f37fcc2a 6166 intel_update_watermarks(crtc);
e1fdc473 6167 intel_enable_pipe(intel_crtc);
be6a6f8e 6168
4b3a9526
VS		 6169 assert_vblank_disabled(crtc);
6170 drm_crtc_vblank_on(crtc);
6171
f9b61ff6
DV		 6172 for_each_encoder_on_crtc(dev, crtc, encoder)
6173 encoder->enable(encoder);
0b8765c6 6174}
79e53945 6175
87476d63
DV		 6176static void i9xx_pfit_disable(struct intel_crtc *crtc)
6177{
6178 struct drm_device *dev = crtc->base.dev;
6179 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 6180
6e3c9717 6181 if (!crtc->config->gmch_pfit.control)
328d8e82 6182 return;
87476d63 6183
328d8e82 6184 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 6185
328d8e82
DV		 6186 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6187 I915_READ(PFIT_CONTROL));
6188 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 6189}
6190
0b8765c6
JB		 6191static void i9xx_crtc_disable(struct drm_crtc *crtc)
6192{
6193 struct drm_device *dev = crtc->dev;
6194 struct drm_i915_private *dev_priv = dev->dev_private;
6195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6196 struct intel_encoder *encoder;
0b8765c6 6197 int pipe = intel_crtc->pipe;
ef9c3aee 6198
f7abfe8b
CW		 6199 if (!intel_crtc->active)
6200 return;
6201
6304cd91
VS		 6202 /*
6203 * On gen2 planes are double buffered but the pipe isn't, so we must
6204 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 6205 * We also need to wait on all gmch platforms because of the
6206 * self-refresh mode constraint explained above.
6304cd91 6207 */
564ed191 6208 intel_wait_for_vblank(dev, pipe);
6304cd91 6209
4b3a9526
VS		 6210 for_each_encoder_on_crtc(dev, crtc, encoder)
6211 encoder->disable(encoder);
6212
f9b61ff6
DV		 6213 drm_crtc_vblank_off(crtc);
6214 assert_vblank_disabled(crtc);
6215
575f7ab7 6216 intel_disable_pipe(intel_crtc);
24a1f16d 6217
87476d63 6218 i9xx_pfit_disable(intel_crtc);
24a1f16d 6219
89b667f8
JB		 6220 for_each_encoder_on_crtc(dev, crtc, encoder)
6221 if (encoder->post_disable)
6222 encoder->post_disable(encoder);
6223
409ee761 6224 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 6225 if (IS_CHERRYVIEW(dev))
6226 chv_disable_pll(dev_priv, pipe);
6227 else if (IS_VALLEYVIEW(dev))
6228 vlv_disable_pll(dev_priv, pipe);
6229 else
1c4e0274 6230 i9xx_disable_pll(intel_crtc);
076ed3b2 6231 }
0b8765c6 6232
4a3436e8 6233 if (!IS_GEN2(dev))
a72e4c9f 6234 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4a3436e8 6235
f7abfe8b 6236 intel_crtc->active = false;
46ba614c 6237 intel_update_watermarks(crtc);
f37fcc2a 6238
efa9624e 6239 mutex_lock(&dev->struct_mutex);
7ff0ebcc 6240 intel_fbc_update(dev);
efa9624e 6241 mutex_unlock(&dev->struct_mutex);
0b8765c6
JB		 6242}
6243
ee7b9f93
JB		 6244static void i9xx_crtc_off(struct drm_crtc *crtc)
6245{
6246}
6247
b04c5bd6
BF		 6248/* Master function to enable/disable CRTC and corresponding power wells */
6249void intel_crtc_control(struct drm_crtc *crtc, bool enable)
976f8a20
DV		 6250{
6251 struct drm_device *dev = crtc->dev;
6252 struct drm_i915_private *dev_priv = dev->dev_private;
0e572fe7 6253 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
0e572fe7
DV		 6254 enum intel_display_power_domain domain;
6255 unsigned long domains;
976f8a20 6256
0e572fe7
DV		 6257 if (enable) {
6258 if (!intel_crtc->active) {
e1e9fb84
DV		 6259 domains = get_crtc_power_domains(crtc);
6260 for_each_power_domain(domain, domains)
6261 intel_display_power_get(dev_priv, domain);
6262 intel_crtc->enabled_power_domains = domains;
0e572fe7
DV		 6263
6264 dev_priv->display.crtc_enable(crtc);
ce22dba9 6265 intel_crtc_enable_planes(crtc);
0e572fe7
DV		 6266 }
6267 } else {
6268 if (intel_crtc->active) {
ce22dba9 6269 intel_crtc_disable_planes(crtc);
0e572fe7
DV		 6270 dev_priv->display.crtc_disable(crtc);
6271
e1e9fb84
DV		 6272 domains = intel_crtc->enabled_power_domains;
6273 for_each_power_domain(domain, domains)
6274 intel_display_power_put(dev_priv, domain);
6275 intel_crtc->enabled_power_domains = 0;
0e572fe7
DV		 6276 }
6277 }
b04c5bd6
BF		 6278}
6279
6280/**
6281 * Sets the power management mode of the pipe and plane.
6282 */
6283void intel_crtc_update_dpms(struct drm_crtc *crtc)
6284{
6285 struct drm_device *dev = crtc->dev;
6286 struct intel_encoder *intel_encoder;
6287 bool enable = false;
6288
6289 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6290 enable |= intel_encoder->connectors_active;
6291
6292 intel_crtc_control(crtc, enable);
0f63cca2
ACO		 6293
6294 crtc->state->active = enable;
976f8a20
DV		 6295}
6296
cdd59983
CW		 6297static void intel_crtc_disable(struct drm_crtc *crtc)
6298{
cdd59983 6299 struct drm_device *dev = crtc->dev;
976f8a20 6300 struct drm_connector *connector;
ee7b9f93 6301 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 6302
976f8a20 6303 /* crtc should still be enabled when we disable it. */
83d65738 6304 WARN_ON(!crtc->state->enable);
976f8a20 6305
ce22dba9 6306 intel_crtc_disable_planes(crtc);
976f8a20 6307 dev_priv->display.crtc_disable(crtc);
ee7b9f93
JB		 6308 dev_priv->display.off(crtc);
6309
70a101f8 6310 drm_plane_helper_disable(crtc->primary);
976f8a20
DV		 6311
6312 /* Update computed state. */
6313 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6314 if (!connector->encoder || !connector->encoder->crtc)
6315 continue;
6316
6317 if (connector->encoder->crtc != crtc)
6318 continue;
6319
6320 connector->dpms = DRM_MODE_DPMS_OFF;
6321 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 6322 }
6323}
6324
ea5b213a 6325void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 6326{
4ef69c7a 6327 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 6328
ea5b213a
CW		 6329 drm_encoder_cleanup(encoder);
6330 kfree(intel_encoder);
7e7d76c3
JB		 6331}
6332
9237329d 6333/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 6334 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6335 * state of the entire output pipe. */
9237329d 6336static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 6337{
5ab432ef
DV		 6338 if (mode == DRM_MODE_DPMS_ON) {
6339 encoder->connectors_active = true;
6340
b2cabb0e 6341 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 6342 } else {
6343 encoder->connectors_active = false;
6344
b2cabb0e 6345 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 6346 }
79e53945
JB		 6347}
6348
0a91ca29
DV		 6349/* Cross check the actual hw state with our own modeset state tracking (and it's
6350 * internal consistency). */
b980514c 6351static void intel_connector_check_state(struct intel_connector *connector)
79e53945 6352{
0a91ca29
DV		 6353 if (connector->get_hw_state(connector)) {
6354 struct intel_encoder *encoder = connector->encoder;
6355 struct drm_crtc *crtc;
6356 bool encoder_enabled;
6357 enum pipe pipe;
6358
6359 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6360 connector->base.base.id,
c23cc417 6361 connector->base.name);
0a91ca29 6362
0e32b39c
DA		 6363 /* there is no real hw state for MST connectors */
6364 if (connector->mst_port)
6365 return;
6366
e2c719b7 6367 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
0a91ca29 6368 "wrong connector dpms state\n");
e2c719b7 6369 I915_STATE_WARN(connector->base.encoder != &encoder->base,
0a91ca29 6370 "active connector not linked to encoder\n");
0a91ca29 6371
36cd7444 6372 if (encoder) {
e2c719b7 6373 I915_STATE_WARN(!encoder->connectors_active,
36cd7444
DA		 6374 "encoder->connectors_active not set\n");
6375
6376 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
e2c719b7
RC		 6377 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6378 if (I915_STATE_WARN_ON(!encoder->base.crtc))
36cd7444 6379 return;
0a91ca29 6380
36cd7444 6381 crtc = encoder->base.crtc;
0a91ca29 6382
83d65738
MR		 6383 I915_STATE_WARN(!crtc->state->enable,
6384 "crtc not enabled\n");
e2c719b7
RC		 6385 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6386 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
36cd7444
DA		 6387 "encoder active on the wrong pipe\n");
6388 }
0a91ca29 6389 }
79e53945
JB		 6390}
6391
08d9bc92
ACO		 6392int intel_connector_init(struct intel_connector *connector)
6393{
6394 struct drm_connector_state *connector_state;
6395
6396 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6397 if (!connector_state)
6398 return -ENOMEM;
6399
6400 connector->base.state = connector_state;
6401 return 0;
6402}
6403
6404struct intel_connector *intel_connector_alloc(void)
6405{
6406 struct intel_connector *connector;
6407
6408 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6409 if (!connector)
6410 return NULL;
6411
6412 if (intel_connector_init(connector) < 0) {
6413 kfree(connector);
6414 return NULL;
6415 }
6416
6417 return connector;
6418}
6419
5ab432ef
DV		 6420/* Even simpler default implementation, if there's really no special case to
6421 * consider. */
6422void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 6423{
5ab432ef
DV		 6424 /* All the simple cases only support two dpms states. */
6425 if (mode != DRM_MODE_DPMS_ON)
6426 mode = DRM_MODE_DPMS_OFF;
d4270e57 6427
5ab432ef
DV		 6428 if (mode == connector->dpms)
6429 return;
6430
6431 connector->dpms = mode;
6432
6433 /* Only need to change hw state when actually enabled */
c9976dcf
CW		 6434 if (connector->encoder)
6435 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
0a91ca29 6436
b980514c 6437 intel_modeset_check_state(connector->dev);
79e53945
JB		 6438}
6439
f0947c37
DV		 6440/* Simple connector->get_hw_state implementation for encoders that support only
6441 * one connector and no cloning and hence the encoder state determines the state
6442 * of the connector. */
6443bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 6444{
24929352 6445 enum pipe pipe = 0;
f0947c37 6446 struct intel_encoder *encoder = connector->encoder;
ea5b213a 6447
f0947c37 6448 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 6449}
6450
6d293983 6451static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 6452{
6d293983
ACO		 6453 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6454 return crtc_state->fdi_lanes;
d272ddfa
VS		 6455
6456 return 0;
6457}
6458
6d293983 6459static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6460 struct intel_crtc_state *pipe_config)
1857e1da 6461{
6d293983
ACO		 6462 struct drm_atomic_state *state = pipe_config->base.state;
6463 struct intel_crtc *other_crtc;
6464 struct intel_crtc_state *other_crtc_state;
6465
1857e1da
DV		 6466 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6467 pipe_name(pipe), pipe_config->fdi_lanes);
6468 if (pipe_config->fdi_lanes > 4) {
6469 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6470 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6471 return -EINVAL;
1857e1da
DV		 6472 }
6473
bafb6553 6474 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 6475 if (pipe_config->fdi_lanes > 2) {
6476 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6477 pipe_config->fdi_lanes);
6d293983 6478 return -EINVAL;
1857e1da 6479 } else {
6d293983 6480 return 0;
1857e1da
DV		 6481 }
6482 }
6483
6484 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 6485 return 0;
1857e1da
DV		 6486
6487 /* Ivybridge 3 pipe is really complicated */
6488 switch (pipe) {
6489 case PIPE_A:
6d293983 6490 return 0;
1857e1da 6491 case PIPE_B:
6d293983
ACO		 6492 if (pipe_config->fdi_lanes <= 2)
6493 return 0;
6494
6495 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6496 other_crtc_state =
6497 intel_atomic_get_crtc_state(state, other_crtc);
6498 if (IS_ERR(other_crtc_state))
6499 return PTR_ERR(other_crtc_state);
6500
6501 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV		 6502 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6503 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6504 return -EINVAL;
1857e1da 6505 }
6d293983 6506 return 0;
1857e1da 6507 case PIPE_C:
251cc67c
VS		 6508 if (pipe_config->fdi_lanes > 2) {
6509 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6510 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6511 return -EINVAL;
251cc67c 6512 }
6d293983
ACO		 6513
6514 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6515 other_crtc_state =
6516 intel_atomic_get_crtc_state(state, other_crtc);
6517 if (IS_ERR(other_crtc_state))
6518 return PTR_ERR(other_crtc_state);
6519
6520 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6521 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6522 return -EINVAL;
1857e1da 6523 }
6d293983 6524 return 0;
1857e1da
DV		 6525 default:
6526 BUG();
6527 }
6528}
6529
e29c22c0
DV		 6530#define RETRY 1
6531static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6532 struct intel_crtc_state *pipe_config)
877d48d5 6533{
1857e1da 6534 struct drm_device *dev = intel_crtc->base.dev;
2d112de7 6535 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 6536 int lane, link_bw, fdi_dotclock, ret;
6537 bool needs_recompute = false;
877d48d5 6538
e29c22c0 6539retry:
877d48d5
DV		 6540 /* FDI is a binary signal running at ~2.7GHz, encoding
6541 * each output octet as 10 bits. The actual frequency
6542 * is stored as a divider into a 100MHz clock, and the
6543 * mode pixel clock is stored in units of 1KHz.
6544 * Hence the bw of each lane in terms of the mode signal
6545 * is:
6546 */
6547 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6548
241bfc38 6549 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6550
2bd89a07 6551 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 6552 pipe_config->pipe_bpp);
6553
6554 pipe_config->fdi_lanes = lane;
6555
2bd89a07 6556 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6557 link_bw, &pipe_config->fdi_m_n);
1857e1da 6558
6d293983
ACO		 6559 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6560 intel_crtc->pipe, pipe_config);
6561 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV		 6562 pipe_config->pipe_bpp -= 2*3;
6563 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6564 pipe_config->pipe_bpp);
6565 needs_recompute = true;
6566 pipe_config->bw_constrained = true;
6567
6568 goto retry;
6569 }
6570
6571 if (needs_recompute)
6572 return RETRY;
6573
6d293983 6574 return ret;
877d48d5
DV		 6575}
6576
42db64ef 6577static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6578 struct intel_crtc_state *pipe_config)
42db64ef 6579{
d330a953 6580 pipe_config->ips_enabled = i915.enable_ips &&
3c4ca58c 6581 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 6582 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 6583}
6584
a43f6e0f 6585static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6586 struct intel_crtc_state *pipe_config)
79e53945 6587{
a43f6e0f 6588 struct drm_device *dev = crtc->base.dev;
8bd31e67 6589 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 6590 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
d03c93d4 6591 int ret;
89749350 6592
ad3a4479 6593 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 6594 if (INTEL_INFO(dev)->gen < 4) {
cf532bb2
VS		 6595 int clock_limit =
6596 dev_priv->display.get_display_clock_speed(dev);
6597
6598 /*
6599 * Enable pixel doubling when the dot clock
6600 * is > 90% of the (display) core speed.
6601 *
b397c96b
VS		 6602 * GDG double wide on either pipe,
6603 * otherwise pipe A only.
cf532bb2 6604 */
b397c96b 6605 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 6606 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 6607 clock_limit *= 2;
cf532bb2 6608 pipe_config->double_wide = true;
ad3a4479
VS		 6609 }
6610
241bfc38 6611 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 6612 return -EINVAL;
2c07245f 6613 }
89749350 6614
1d1d0e27
VS		 6615 /*
6616 * Pipe horizontal size must be even in:
6617 * - DVO ganged mode
6618 * - LVDS dual channel mode
6619 * - Double wide pipe
6620 */
a93e255f 6621 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 6622 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6623 pipe_config->pipe_src_w &= ~1;
6624
8693a824
DL		 6625 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6626 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 6627 */
6628 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6629 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 6630 return -EINVAL;
44f46b42 6631
f5adf94e 6632 if (HAS_IPS(dev))
a43f6e0f
DV		 6633 hsw_compute_ips_config(crtc, pipe_config);
6634
877d48d5 6635 if (pipe_config->has_pch_encoder)
a43f6e0f 6636 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6637
d03c93d4
CK		 6638 /* FIXME: remove below call once atomic mode set is place and all crtc
6639 * related checks called from atomic_crtc_check function */
6640 ret = 0;
6641 DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6642 crtc, pipe_config->base.state);
6643 ret = intel_atomic_setup_scalers(dev, crtc, pipe_config);
6644
6645 return ret;
79e53945
JB		 6646}
6647
1652d19e
VS		 6648static int skylake_get_display_clock_speed(struct drm_device *dev)
6649{
6650 struct drm_i915_private *dev_priv = to_i915(dev);
6651 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6652 uint32_t cdctl = I915_READ(CDCLK_CTL);
6653 uint32_t linkrate;
6654
6655 if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
6656 WARN(1, "LCPLL1 not enabled\n");
6657 return 24000; /* 24MHz is the cd freq with NSSC ref */
6658 }
6659
6660 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6661 return 540000;
6662
6663 linkrate = (I915_READ(DPLL_CTRL1) &
71cd8423 6664 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1652d19e 6665
71cd8423
DL		 6666 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6667 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
1652d19e
VS		 6668 /* vco 8640 */
6669 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6670 case CDCLK_FREQ_450_432:
6671 return 432000;
6672 case CDCLK_FREQ_337_308:
6673 return 308570;
6674 case CDCLK_FREQ_675_617:
6675 return 617140;
6676 default:
6677 WARN(1, "Unknown cd freq selection\n");
6678 }
6679 } else {
6680 /* vco 8100 */
6681 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6682 case CDCLK_FREQ_450_432:
6683 return 450000;
6684 case CDCLK_FREQ_337_308:
6685 return 337500;
6686 case CDCLK_FREQ_675_617:
6687 return 675000;
6688 default:
6689 WARN(1, "Unknown cd freq selection\n");
6690 }
6691 }
6692
6693 /* error case, do as if DPLL0 isn't enabled */
6694 return 24000;
6695}
6696
6697static int broadwell_get_display_clock_speed(struct drm_device *dev)
6698{
6699 struct drm_i915_private *dev_priv = dev->dev_private;
6700 uint32_t lcpll = I915_READ(LCPLL_CTL);
6701 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6702
6703 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6704 return 800000;
6705 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6706 return 450000;
6707 else if (freq == LCPLL_CLK_FREQ_450)
6708 return 450000;
6709 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6710 return 540000;
6711 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6712 return 337500;
6713 else
6714 return 675000;
6715}
6716
6717static int haswell_get_display_clock_speed(struct drm_device *dev)
6718{
6719 struct drm_i915_private *dev_priv = dev->dev_private;
6720 uint32_t lcpll = I915_READ(LCPLL_CTL);
6721 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6722
6723 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6724 return 800000;
6725 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6726 return 450000;
6727 else if (freq == LCPLL_CLK_FREQ_450)
6728 return 450000;
6729 else if (IS_HSW_ULT(dev))
6730 return 337500;
6731 else
6732 return 540000;
79e53945
JB		 6733}
6734
25eb05fc
JB		 6735static int valleyview_get_display_clock_speed(struct drm_device *dev)
6736{
d197b7d3 6737 struct drm_i915_private *dev_priv = dev->dev_private;
d197b7d3
VS		 6738 u32 val;
6739 int divider;
6740
6bcda4f0
VS		 6741 if (dev_priv->hpll_freq == 0)
6742 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6743
a580516d 6744 mutex_lock(&dev_priv->sb_lock);
d197b7d3 6745 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
a580516d 6746 mutex_unlock(&dev_priv->sb_lock);
d197b7d3
VS		 6747
6748 divider = val & DISPLAY_FREQUENCY_VALUES;
6749
7d007f40
VS		 6750 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6751 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6752 "cdclk change in progress\n");
6753
6bcda4f0 6754 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
25eb05fc
JB		 6755}
6756
b37a6434
VS		 6757static int ilk_get_display_clock_speed(struct drm_device *dev)
6758{
6759 return 450000;
6760}
6761
e70236a8
JB		 6762static int i945_get_display_clock_speed(struct drm_device *dev)
6763{
6764 return 400000;
6765}
79e53945 6766
e70236a8 6767static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6768{
e907f170 6769 return 333333;
e70236a8 6770}
79e53945 6771
e70236a8
JB		 6772static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6773{
6774 return 200000;
6775}
79e53945 6776
257a7ffc
DV		 6777static int pnv_get_display_clock_speed(struct drm_device *dev)
6778{
6779 u16 gcfgc = 0;
6780
6781 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6782
6783 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6784 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6785 return 266667;
257a7ffc 6786 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6787 return 333333;
257a7ffc 6788 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6789 return 444444;
257a7ffc
DV		 6790 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6791 return 200000;
6792 default:
6793 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6794 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6795 return 133333;
257a7ffc 6796 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6797 return 166667;
257a7ffc
DV		 6798 }
6799}
6800
e70236a8
JB		 6801static int i915gm_get_display_clock_speed(struct drm_device *dev)
6802{
6803 u16 gcfgc = 0;
79e53945 6804
e70236a8
JB		 6805 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6806
6807 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6808 return 133333;
e70236a8
JB		 6809 else {
6810 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6811 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6812 return 333333;
e70236a8
JB		 6813 default:
6814 case GC_DISPLAY_CLOCK_190_200_MHZ:
6815 return 190000;
79e53945 6816 }
e70236a8
JB		 6817 }
6818}
6819
6820static int i865_get_display_clock_speed(struct drm_device *dev)
6821{
e907f170 6822 return 266667;
e70236a8
JB		 6823}
6824
1b1d2716 6825static int i85x_get_display_clock_speed(struct drm_device *dev)
e70236a8
JB		 6826{
6827 u16 hpllcc = 0;
1b1d2716 6828
65cd2b3f
VS		 6829 /*
6830 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6831 * encoding is different :(
6832 * FIXME is this the right way to detect 852GM/852GMV?
6833 */
6834 if (dev->pdev->revision == 0x1)
6835 return 133333;
6836
1b1d2716
VS		 6837 pci_bus_read_config_word(dev->pdev->bus,
6838 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6839
e70236a8
JB		 6840 /* Assume that the hardware is in the high speed state. This
6841 * should be the default.
6842 */
6843 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6844 case GC_CLOCK_133_200:
1b1d2716 6845 case GC_CLOCK_133_200_2:
e70236a8
JB		 6846 case GC_CLOCK_100_200:
6847 return 200000;
6848 case GC_CLOCK_166_250:
6849 return 250000;
6850 case GC_CLOCK_100_133:
e907f170 6851 return 133333;
1b1d2716
VS		 6852 case GC_CLOCK_133_266:
6853 case GC_CLOCK_133_266_2:
6854 case GC_CLOCK_166_266:
6855 return 266667;
e70236a8 6856 }
79e53945 6857
e70236a8
JB		 6858 /* Shouldn't happen */
6859 return 0;
6860}
79e53945 6861
e70236a8
JB		 6862static int i830_get_display_clock_speed(struct drm_device *dev)
6863{
e907f170 6864 return 133333;
79e53945
JB		 6865}
6866
34edce2f
VS		 6867static unsigned int intel_hpll_vco(struct drm_device *dev)
6868{
6869 struct drm_i915_private *dev_priv = dev->dev_private;
6870 static const unsigned int blb_vco[8] = {
6871 [0] = 3200000,
6872 [1] = 4000000,
6873 [2] = 5333333,
6874 [3] = 4800000,
6875 [4] = 6400000,
6876 };
6877 static const unsigned int pnv_vco[8] = {
6878 [0] = 3200000,
6879 [1] = 4000000,
6880 [2] = 5333333,
6881 [3] = 4800000,
6882 [4] = 2666667,
6883 };
6884 static const unsigned int cl_vco[8] = {
6885 [0] = 3200000,
6886 [1] = 4000000,
6887 [2] = 5333333,
6888 [3] = 6400000,
6889 [4] = 3333333,
6890 [5] = 3566667,
6891 [6] = 4266667,
6892 };
6893 static const unsigned int elk_vco[8] = {
6894 [0] = 3200000,
6895 [1] = 4000000,
6896 [2] = 5333333,
6897 [3] = 4800000,
6898 };
6899 static const unsigned int ctg_vco[8] = {
6900 [0] = 3200000,
6901 [1] = 4000000,
6902 [2] = 5333333,
6903 [3] = 6400000,
6904 [4] = 2666667,
6905 [5] = 4266667,
6906 };
6907 const unsigned int *vco_table;
6908 unsigned int vco;
6909 uint8_t tmp = 0;
6910
6911 /* FIXME other chipsets? */
6912 if (IS_GM45(dev))
6913 vco_table = ctg_vco;
6914 else if (IS_G4X(dev))
6915 vco_table = elk_vco;
6916 else if (IS_CRESTLINE(dev))
6917 vco_table = cl_vco;
6918 else if (IS_PINEVIEW(dev))
6919 vco_table = pnv_vco;
6920 else if (IS_G33(dev))
6921 vco_table = blb_vco;
6922 else
6923 return 0;
6924
6925 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6926
6927 vco = vco_table[tmp & 0x7];
6928 if (vco == 0)
6929 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6930 else
6931 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6932
6933 return vco;
6934}
6935
6936static int gm45_get_display_clock_speed(struct drm_device *dev)
6937{
6938 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6939 uint16_t tmp = 0;
6940
6941 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6942
6943 cdclk_sel = (tmp >> 12) & 0x1;
6944
6945 switch (vco) {
6946 case 2666667:
6947 case 4000000:
6948 case 5333333:
6949 return cdclk_sel ? 333333 : 222222;
6950 case 3200000:
6951 return cdclk_sel ? 320000 : 228571;
6952 default:
6953 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6954 return 222222;
6955 }
6956}
6957
6958static int i965gm_get_display_clock_speed(struct drm_device *dev)
6959{
6960 static const uint8_t div_3200[] = { 16, 10, 8 };
6961 static const uint8_t div_4000[] = { 20, 12, 10 };
6962 static const uint8_t div_5333[] = { 24, 16, 14 };
6963 const uint8_t *div_table;
6964 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6965 uint16_t tmp = 0;
6966
6967 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6968
6969 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6970
6971 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6972 goto fail;
6973
6974 switch (vco) {
6975 case 3200000:
6976 div_table = div_3200;
6977 break;
6978 case 4000000:
6979 div_table = div_4000;
6980 break;
6981 case 5333333:
6982 div_table = div_5333;
6983 break;
6984 default:
6985 goto fail;
6986 }
6987
6988 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6989
6990 fail:
6991 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6992 return 200000;
6993}
6994
6995static int g33_get_display_clock_speed(struct drm_device *dev)
6996{
6997 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6998 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6999 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7000 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7001 const uint8_t *div_table;
7002 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7003 uint16_t tmp = 0;
7004
7005 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7006
7007 cdclk_sel = (tmp >> 4) & 0x7;
7008
7009 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7010 goto fail;
7011
7012 switch (vco) {
7013 case 3200000:
7014 div_table = div_3200;
7015 break;
7016 case 4000000:
7017 div_table = div_4000;
7018 break;
7019 case 4800000:
7020 div_table = div_4800;
7021 break;
7022 case 5333333:
7023 div_table = div_5333;
7024 break;
7025 default:
7026 goto fail;
7027 }
7028
7029 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7030
7031 fail:
7032 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7033 return 190476;
7034}
7035
2c07245f 7036static void
a65851af 7037intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 7038{
a65851af
VS		 7039 while (*num > DATA_LINK_M_N_MASK ||
7040 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 7041 *num >>= 1;
7042 *den >>= 1;
7043 }
7044}
7045
a65851af
VS		 7046static void compute_m_n(unsigned int m, unsigned int n,
7047 uint32_t *ret_m, uint32_t *ret_n)
7048{
7049 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7050 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7051 intel_reduce_m_n_ratio(ret_m, ret_n);
7052}
7053
e69d0bc1
DV		 7054void
7055intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7056 int pixel_clock, int link_clock,
7057 struct intel_link_m_n *m_n)
2c07245f 7058{
e69d0bc1 7059 m_n->tu = 64;
a65851af
VS		 7060
7061 compute_m_n(bits_per_pixel * pixel_clock,
7062 link_clock * nlanes * 8,
7063 &m_n->gmch_m, &m_n->gmch_n);
7064
7065 compute_m_n(pixel_clock, link_clock,
7066 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 7067}
7068
a7615030
CW		 7069static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7070{
d330a953
JN		 7071 if (i915.panel_use_ssc >= 0)
7072 return i915.panel_use_ssc != 0;
41aa3448 7073 return dev_priv->vbt.lvds_use_ssc
435793df 7074 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 7075}
7076
a93e255f
ACO		 7077static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7078 int num_connectors)
c65d77d8 7079{
a93e255f 7080 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 7081 struct drm_i915_private *dev_priv = dev->dev_private;
7082 int refclk;
7083
a93e255f
ACO		 7084 WARN_ON(!crtc_state->base.state);
7085
5ab7b0b7 7086 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
9a0ea498 7087 refclk = 100000;
a93e255f 7088 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 7089 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 7090 refclk = dev_priv->vbt.lvds_ssc_freq;
7091 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 7092 } else if (!IS_GEN2(dev)) {
7093 refclk = 96000;
7094 } else {
7095 refclk = 48000;
7096 }
7097
7098 return refclk;
7099}
7100
7429e9d4 7101static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 7102{
7df00d7a 7103 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 7104}
f47709a9 7105
7429e9d4
DV		 7106static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7107{
7108 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 7109}
7110
f47709a9 7111static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 7112 struct intel_crtc_state *crtc_state,
a7516a05
JB		 7113 intel_clock_t *reduced_clock)
7114{
f47709a9 7115 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 7116 u32 fp, fp2 = 0;
7117
7118 if (IS_PINEVIEW(dev)) {
190f68c5 7119 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7120 if (reduced_clock)
7429e9d4 7121 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 7122 } else {
190f68c5 7123 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7124 if (reduced_clock)
7429e9d4 7125 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 7126 }
7127
190f68c5 7128 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 7129
f47709a9 7130 crtc->lowfreq_avail = false;
a93e255f 7131 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 7132 reduced_clock) {
190f68c5 7133 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 7134 crtc->lowfreq_avail = true;
a7516a05 7135 } else {
190f68c5 7136 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 7137 }
7138}
7139
5e69f97f
CML		 7140static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7141 pipe)
89b667f8
JB		 7142{
7143 u32 reg_val;
7144
7145 /*
7146 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7147 * and set it to a reasonable value instead.
7148 */
ab3c759a 7149 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 7150 reg_val &= 0xffffff00;
7151 reg_val |= 0x00000030;
ab3c759a 7152 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7153
ab3c759a 7154 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7155 reg_val &= 0x8cffffff;
7156 reg_val = 0x8c000000;
ab3c759a 7157 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 7158
ab3c759a 7159 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 7160 reg_val &= 0xffffff00;
ab3c759a 7161 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7162
ab3c759a 7163 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7164 reg_val &= 0x00ffffff;
7165 reg_val |= 0xb0000000;
ab3c759a 7166 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 7167}
7168
b551842d
DV		 7169static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7170 struct intel_link_m_n *m_n)
7171{
7172 struct drm_device *dev = crtc->base.dev;
7173 struct drm_i915_private *dev_priv = dev->dev_private;
7174 int pipe = crtc->pipe;
7175
e3b95f1e
DV		 7176 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7177 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7178 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7179 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 7180}
7181
7182static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 7183 struct intel_link_m_n *m_n,
7184 struct intel_link_m_n *m2_n2)
b551842d
DV		 7185{
7186 struct drm_device *dev = crtc->base.dev;
7187 struct drm_i915_private *dev_priv = dev->dev_private;
7188 int pipe = crtc->pipe;
6e3c9717 7189 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 7190
7191 if (INTEL_INFO(dev)->gen >= 5) {
7192 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7193 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7194 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7195 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 7196 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7197 * for gen < 8) and if DRRS is supported (to make sure the
7198 * registers are not unnecessarily accessed).
7199 */
44395bfe 7200 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 7201 crtc->config->has_drrs) {
f769cd24
VK		 7202 I915_WRITE(PIPE_DATA_M2(transcoder),
7203 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7204 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7205 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7206 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7207 }
b551842d 7208 } else {
e3b95f1e
DV		 7209 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7210 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7211 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7212 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 7213 }
7214}
7215
fe3cd48d 7216void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 7217{
fe3cd48d
R		 7218 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7219
7220 if (m_n == M1_N1) {
7221 dp_m_n = &crtc->config->dp_m_n;
7222 dp_m2_n2 = &crtc->config->dp_m2_n2;
7223 } else if (m_n == M2_N2) {
7224
7225 /*
7226 * M2_N2 registers are not supported. Hence m2_n2 divider value
7227 * needs to be programmed into M1_N1.
7228 */
7229 dp_m_n = &crtc->config->dp_m2_n2;
7230 } else {
7231 DRM_ERROR("Unsupported divider value\n");
7232 return;
7233 }
7234
6e3c9717
ACO		 7235 if (crtc->config->has_pch_encoder)
7236 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 7237 else
fe3cd48d 7238 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 7239}
7240
d288f65f 7241static void vlv_update_pll(struct intel_crtc *crtc,
5cec258b 7242 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 7243{
7244 u32 dpll, dpll_md;
7245
7246 /*
7247 * Enable DPIO clock input. We should never disable the reference
7248 * clock for pipe B, since VGA hotplug / manual detection depends
7249 * on it.
7250 */
7251 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
7252 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
7253 /* We should never disable this, set it here for state tracking */
7254 if (crtc->pipe == PIPE_B)
7255 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7256 dpll |= DPLL_VCO_ENABLE;
d288f65f 7257 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 7258
d288f65f 7259 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 7260 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 7261 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 7262}
7263
d288f65f 7264static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7265 const struct intel_crtc_state *pipe_config)
a0c4da24 7266{
f47709a9 7267 struct drm_device *dev = crtc->base.dev;
a0c4da24 7268 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 7269 int pipe = crtc->pipe;
bdd4b6a6 7270 u32 mdiv;
a0c4da24 7271 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 7272 u32 coreclk, reg_val;
a0c4da24 7273
a580516d 7274 mutex_lock(&dev_priv->sb_lock);
09153000 7275
d288f65f
VS		 7276 bestn = pipe_config->dpll.n;
7277 bestm1 = pipe_config->dpll.m1;
7278 bestm2 = pipe_config->dpll.m2;
7279 bestp1 = pipe_config->dpll.p1;
7280 bestp2 = pipe_config->dpll.p2;
a0c4da24 7281
89b667f8
JB		 7282 /* See eDP HDMI DPIO driver vbios notes doc */
7283
7284 /* PLL B needs special handling */
bdd4b6a6 7285 if (pipe == PIPE_B)
5e69f97f 7286 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 7287
7288 /* Set up Tx target for periodic Rcomp update */
ab3c759a 7289 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 7290
7291 /* Disable target IRef on PLL */
ab3c759a 7292 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 7293 reg_val &= 0x00ffffff;
ab3c759a 7294 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 7295
7296 /* Disable fast lock */
ab3c759a 7297 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 7298
7299 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 7300 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7301 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7302 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 7303 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 7304
7305 /*
7306 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7307 * but we don't support that).
7308 * Note: don't use the DAC post divider as it seems unstable.
7309 */
7310 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 7311 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7312
a0c4da24 7313 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 7314 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7315
89b667f8 7316 /* Set HBR and RBR LPF coefficients */
d288f65f 7317 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 7318 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7319 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 7320 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 7321 0x009f0003);
89b667f8 7322 else
ab3c759a 7323 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 7324 0x00d0000f);
7325
681a8504 7326 if (pipe_config->has_dp_encoder) {
89b667f8 7327 /* Use SSC source */
bdd4b6a6 7328 if (pipe == PIPE_A)
ab3c759a 7329 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7330 0x0df40000);
7331 else
ab3c759a 7332 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7333 0x0df70000);
7334 } else { /* HDMI or VGA */
7335 /* Use bend source */
bdd4b6a6 7336 if (pipe == PIPE_A)
ab3c759a 7337 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7338 0x0df70000);
7339 else
ab3c759a 7340 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7341 0x0df40000);
7342 }
a0c4da24 7343
ab3c759a 7344 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 7345 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 7346 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7347 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 7348 coreclk |= 0x01000000;
ab3c759a 7349 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 7350
ab3c759a 7351 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
a580516d 7352 mutex_unlock(&dev_priv->sb_lock);
a0c4da24
JB		 7353}
7354
d288f65f 7355static void chv_update_pll(struct intel_crtc *crtc,
5cec258b 7356 struct intel_crtc_state *pipe_config)
1ae0d137 7357{
d288f65f 7358 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
1ae0d137
VS		 7359 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7360 DPLL_VCO_ENABLE;
7361 if (crtc->pipe != PIPE_A)
d288f65f 7362 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 7363
d288f65f
VS		 7364 pipe_config->dpll_hw_state.dpll_md =
7365 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 7366}
7367
d288f65f 7368static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7369 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 7370{
7371 struct drm_device *dev = crtc->base.dev;
7372 struct drm_i915_private *dev_priv = dev->dev_private;
7373 int pipe = crtc->pipe;
7374 int dpll_reg = DPLL(crtc->pipe);
7375 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 7376 u32 loopfilter, tribuf_calcntr;
9d556c99 7377 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 7378 u32 dpio_val;
9cbe40c1 7379 int vco;
9d556c99 7380
d288f65f
VS		 7381 bestn = pipe_config->dpll.n;
7382 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7383 bestm1 = pipe_config->dpll.m1;
7384 bestm2 = pipe_config->dpll.m2 >> 22;
7385 bestp1 = pipe_config->dpll.p1;
7386 bestp2 = pipe_config->dpll.p2;
9cbe40c1 7387 vco = pipe_config->dpll.vco;
a945ce7e 7388 dpio_val = 0;
9cbe40c1 7389 loopfilter = 0;
9d556c99
CML		 7390
7391 /*
7392 * Enable Refclk and SSC
7393 */
a11b0703 7394 I915_WRITE(dpll_reg,
d288f65f 7395 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703 7396
a580516d 7397 mutex_lock(&dev_priv->sb_lock);
9d556c99 7398
9d556c99
CML		 7399 /* p1 and p2 divider */
7400 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7401 5 << DPIO_CHV_S1_DIV_SHIFT |
7402 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7403 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7404 1 << DPIO_CHV_K_DIV_SHIFT);
7405
7406 /* Feedback post-divider - m2 */
7407 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7408
7409 /* Feedback refclk divider - n and m1 */
7410 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7411 DPIO_CHV_M1_DIV_BY_2 |
7412 1 << DPIO_CHV_N_DIV_SHIFT);
7413
7414 /* M2 fraction division */
a945ce7e
VP		 7415 if (bestm2_frac)
7416 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 7417
7418 /* M2 fraction division enable */
a945ce7e
VP		 7419 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7420 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7421 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7422 if (bestm2_frac)
7423 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7424 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 7425
de3a0fde
VP		 7426 /* Program digital lock detect threshold */
7427 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7428 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7429 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7430 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7431 if (!bestm2_frac)
7432 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7433 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7434
9d556c99 7435 /* Loop filter */
9cbe40c1
VP		 7436 if (vco == 5400000) {
7437 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7438 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7439 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7440 tribuf_calcntr = 0x9;
7441 } else if (vco <= 6200000) {
7442 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7443 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7444 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7445 tribuf_calcntr = 0x9;
7446 } else if (vco <= 6480000) {
7447 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7448 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7449 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7450 tribuf_calcntr = 0x8;
7451 } else {
7452 /* Not supported. Apply the same limits as in the max case */
7453 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7454 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7455 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7456 tribuf_calcntr = 0;
7457 }
9d556c99
CML		 7458 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7459
968040b2 7460 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 7461 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7462 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7463 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7464
9d556c99
CML		 7465 /* AFC Recal */
7466 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7467 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7468 DPIO_AFC_RECAL);
7469
a580516d 7470 mutex_unlock(&dev_priv->sb_lock);
9d556c99
CML		 7471}
7472
d288f65f
VS		 7473/**
7474 * vlv_force_pll_on - forcibly enable just the PLL
7475 * @dev_priv: i915 private structure
7476 * @pipe: pipe PLL to enable
7477 * @dpll: PLL configuration
7478 *
7479 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7480 * in cases where we need the PLL enabled even when @pipe is not going to
7481 * be enabled.
7482 */
7483void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7484 const struct dpll *dpll)
7485{
7486 struct intel_crtc *crtc =
7487 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 7488 struct intel_crtc_state pipe_config = {
a93e255f 7489 .base.crtc = &crtc->base,
d288f65f
VS		 7490 .pixel_multiplier = 1,
7491 .dpll = *dpll,
7492 };
7493
7494 if (IS_CHERRYVIEW(dev)) {
7495 chv_update_pll(crtc, &pipe_config);
7496 chv_prepare_pll(crtc, &pipe_config);
7497 chv_enable_pll(crtc, &pipe_config);
7498 } else {
7499 vlv_update_pll(crtc, &pipe_config);
7500 vlv_prepare_pll(crtc, &pipe_config);
7501 vlv_enable_pll(crtc, &pipe_config);
7502 }
7503}
7504
7505/**
7506 * vlv_force_pll_off - forcibly disable just the PLL
7507 * @dev_priv: i915 private structure
7508 * @pipe: pipe PLL to disable
7509 *
7510 * Disable the PLL for @pipe. To be used in cases where we need
7511 * the PLL enabled even when @pipe is not going to be enabled.
7512 */
7513void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7514{
7515 if (IS_CHERRYVIEW(dev))
7516 chv_disable_pll(to_i915(dev), pipe);
7517 else
7518 vlv_disable_pll(to_i915(dev), pipe);
7519}
7520
f47709a9 7521static void i9xx_update_pll(struct intel_crtc *crtc,
190f68c5 7522 struct intel_crtc_state *crtc_state,
f47709a9 7523 intel_clock_t *reduced_clock,
eb1cbe48
DV		 7524 int num_connectors)
7525{
f47709a9 7526 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7527 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 7528 u32 dpll;
7529 bool is_sdvo;
190f68c5 7530 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7531
190f68c5 7532 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7533
a93e255f
ACO		 7534 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7535 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 7536
7537 dpll = DPLL_VGA_MODE_DIS;
7538
a93e255f 7539 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 7540 dpll |= DPLLB_MODE_LVDS;
7541 else
7542 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 7543
ef1b460d 7544 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 7545 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 7546 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 7547 }
198a037f
DV		 7548
7549 if (is_sdvo)
4a33e48d 7550 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 7551
190f68c5 7552 if (crtc_state->has_dp_encoder)
4a33e48d 7553 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 7554
7555 /* compute bitmask from p1 value */
7556 if (IS_PINEVIEW(dev))
7557 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7558 else {
7559 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7560 if (IS_G4X(dev) && reduced_clock)
7561 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7562 }
7563 switch (clock->p2) {
7564 case 5:
7565 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7566 break;
7567 case 7:
7568 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7569 break;
7570 case 10:
7571 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7572 break;
7573 case 14:
7574 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7575 break;
7576 }
7577 if (INTEL_INFO(dev)->gen >= 4)
7578 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7579
190f68c5 7580 if (crtc_state->sdvo_tv_clock)
eb1cbe48 7581 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 7582 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7583 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7584 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7585 else
7586 dpll |= PLL_REF_INPUT_DREFCLK;
7587
7588 dpll |= DPLL_VCO_ENABLE;
190f68c5 7589 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 7590
eb1cbe48 7591 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 7592 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 7593 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 7594 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 7595 }
7596}
7597
f47709a9 7598static void i8xx_update_pll(struct intel_crtc *crtc,
190f68c5 7599 struct intel_crtc_state *crtc_state,
f47709a9 7600 intel_clock_t *reduced_clock,
eb1cbe48
DV		 7601 int num_connectors)
7602{
f47709a9 7603 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7604 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 7605 u32 dpll;
190f68c5 7606 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7607
190f68c5 7608 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7609
eb1cbe48
DV		 7610 dpll = DPLL_VGA_MODE_DIS;
7611
a93e255f 7612 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 7613 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7614 } else {
7615 if (clock->p1 == 2)
7616 dpll |= PLL_P1_DIVIDE_BY_TWO;
7617 else
7618 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7619 if (clock->p2 == 4)
7620 dpll |= PLL_P2_DIVIDE_BY_4;
7621 }
7622
a93e255f 7623 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 7624 dpll |= DPLL_DVO_2X_MODE;
7625
a93e255f 7626 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7627 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7628 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7629 else
7630 dpll |= PLL_REF_INPUT_DREFCLK;
7631
7632 dpll |= DPLL_VCO_ENABLE;
190f68c5 7633 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 7634}
7635
8a654f3b 7636static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 7637{
7638 struct drm_device *dev = intel_crtc->base.dev;
7639 struct drm_i915_private *dev_priv = dev->dev_private;
7640 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7641 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8a654f3b 7642 struct drm_display_mode *adjusted_mode =
6e3c9717 7643 &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 7644 uint32_t crtc_vtotal, crtc_vblank_end;
7645 int vsyncshift = 0;
4d8a62ea
DV		 7646
7647 /* We need to be careful not to changed the adjusted mode, for otherwise
7648 * the hw state checker will get angry at the mismatch. */
7649 crtc_vtotal = adjusted_mode->crtc_vtotal;
7650 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 7651
609aeaca 7652 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 7653 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 7654 crtc_vtotal -= 1;
7655 crtc_vblank_end -= 1;
609aeaca 7656
409ee761 7657 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 7658 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7659 else
7660 vsyncshift = adjusted_mode->crtc_hsync_start -
7661 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 7662 if (vsyncshift < 0)
7663 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 7664 }
7665
7666 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 7667 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 7668
fe2b8f9d 7669 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 7670 (adjusted_mode->crtc_hdisplay - 1) |
7671 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 7672 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 7673 (adjusted_mode->crtc_hblank_start - 1) |
7674 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 7675 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 7676 (adjusted_mode->crtc_hsync_start - 1) |
7677 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7678
fe2b8f9d 7679 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 7680 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 7681 ((crtc_vtotal - 1) << 16));
fe2b8f9d 7682 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 7683 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 7684 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 7685 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 7686 (adjusted_mode->crtc_vsync_start - 1) |
7687 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7688
b5e508d4
PZ		 7689 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7690 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7691 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7692 * bits. */
7693 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7694 (pipe == PIPE_B || pipe == PIPE_C))
7695 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7696
b0e77b9c
PZ		 7697 /* pipesrc controls the size that is scaled from, which should
7698 * always be the user's requested size.
7699 */
7700 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 7701 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7702 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 7703}
7704
1bd1bd80 7705static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7706 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 7707{
7708 struct drm_device *dev = crtc->base.dev;
7709 struct drm_i915_private *dev_priv = dev->dev_private;
7710 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7711 uint32_t tmp;
7712
7713 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 7714 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7715 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7716 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 7717 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7718 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7719 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 7720 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7721 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7722
7723 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 7724 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7725 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7726 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 7727 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7728 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7729 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 7730 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7731 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7732
7733 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 7734 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7735 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7736 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 7737 }
7738
7739 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 7740 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7741 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7742
2d112de7
ACO		 7743 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7744 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 7745}
7746
f6a83288 7747void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7748 struct intel_crtc_state *pipe_config)
babea61d 7749{
2d112de7
ACO		 7750 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7751 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7752 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7753 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7754
2d112de7
ACO		 7755 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7756 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7757 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7758 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7759
2d112de7 7760 mode->flags = pipe_config->base.adjusted_mode.flags;
babea61d 7761
2d112de7
ACO		 7762 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7763 mode->flags |= pipe_config->base.adjusted_mode.flags;
babea61d
JB		 7764}
7765
84b046f3
DV		 7766static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7767{
7768 struct drm_device *dev = intel_crtc->base.dev;
7769 struct drm_i915_private *dev_priv = dev->dev_private;
7770 uint32_t pipeconf;
7771
9f11a9e4 7772 pipeconf = 0;
84b046f3 7773
b6b5d049
VS		 7774 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7775 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7776 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7777
6e3c9717 7778 if (intel_crtc->config->double_wide)
cf532bb2 7779 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7780
ff9ce46e
DV		 7781 /* only g4x and later have fancy bpc/dither controls */
7782 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 7783 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7784 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7785 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7786 PIPECONF_DITHER_TYPE_SP;
84b046f3 7787
6e3c9717 7788 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 7789 case 18:
7790 pipeconf |= PIPECONF_6BPC;
7791 break;
7792 case 24:
7793 pipeconf |= PIPECONF_8BPC;
7794 break;
7795 case 30:
7796 pipeconf |= PIPECONF_10BPC;
7797 break;
7798 default:
7799 /* Case prevented by intel_choose_pipe_bpp_dither. */
7800 BUG();
84b046f3
DV		 7801 }
7802 }
7803
7804 if (HAS_PIPE_CXSR(dev)) {
7805 if (intel_crtc->lowfreq_avail) {
7806 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7807 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7808 } else {
7809 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 7810 }
7811 }
7812
6e3c9717 7813 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7814 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7815 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 7816 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7817 else
7818 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7819 } else
84b046f3
DV		 7820 pipeconf |= PIPECONF_PROGRESSIVE;
7821
6e3c9717 7822 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 7823 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7824
84b046f3
DV		 7825 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7826 POSTING_READ(PIPECONF(intel_crtc->pipe));
7827}
7828
190f68c5
ACO		 7829static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7830 struct intel_crtc_state *crtc_state)
79e53945 7831{
c7653199 7832 struct drm_device *dev = crtc->base.dev;
79e53945 7833 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 7834 int refclk, num_connectors = 0;
652c393a 7835 intel_clock_t clock, reduced_clock;
a16af721 7836 bool ok, has_reduced_clock = false;
e9fd1c02 7837 bool is_lvds = false, is_dsi = false;
5eddb70b 7838 struct intel_encoder *encoder;
d4906093 7839 const intel_limit_t *limit;
55bb9992 7840 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 7841 struct drm_connector *connector;
55bb9992
ACO		 7842 struct drm_connector_state *connector_state;
7843 int i;
79e53945 7844
dd3cd74a
ACO		 7845 memset(&crtc_state->dpll_hw_state, 0,
7846 sizeof(crtc_state->dpll_hw_state));
7847
da3ced29 7848 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 7849 if (connector_state->crtc != &crtc->base)
7850 continue;
7851
7852 encoder = to_intel_encoder(connector_state->best_encoder);
7853
5eddb70b 7854 switch (encoder->type) {
79e53945
JB		 7855 case INTEL_OUTPUT_LVDS:
7856 is_lvds = true;
7857 break;
e9fd1c02
JN		 7858 case INTEL_OUTPUT_DSI:
7859 is_dsi = true;
7860 break;
6847d71b
PZ		 7861 default:
7862 break;
79e53945 7863 }
43565a06 7864
c751ce4f 7865 num_connectors++;
79e53945
JB		 7866 }
7867
f2335330 7868 if (is_dsi)
5b18e57c 7869 return 0;
f2335330 7870
190f68c5 7871 if (!crtc_state->clock_set) {
a93e255f 7872 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 7873
e9fd1c02
JN		 7874 /*
7875 * Returns a set of divisors for the desired target clock with
7876 * the given refclk, or FALSE. The returned values represent
7877 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7878 * 2) / p1 / p2.
7879 */
a93e255f
ACO		 7880 limit = intel_limit(crtc_state, refclk);
7881 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7882 crtc_state->port_clock,
e9fd1c02 7883 refclk, NULL, &clock);
f2335330 7884 if (!ok) {
e9fd1c02
JN		 7885 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7886 return -EINVAL;
7887 }
79e53945 7888
f2335330
JN		 7889 if (is_lvds && dev_priv->lvds_downclock_avail) {
7890 /*
7891 * Ensure we match the reduced clock's P to the target
7892 * clock. If the clocks don't match, we can't switch
7893 * the display clock by using the FP0/FP1. In such case
7894 * we will disable the LVDS downclock feature.
7895 */
7896 has_reduced_clock =
a93e255f 7897 dev_priv->display.find_dpll(limit, crtc_state,
f2335330
JN		 7898 dev_priv->lvds_downclock,
7899 refclk, &clock,
7900 &reduced_clock);
7901 }
7902 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7903 crtc_state->dpll.n = clock.n;
7904 crtc_state->dpll.m1 = clock.m1;
7905 crtc_state->dpll.m2 = clock.m2;
7906 crtc_state->dpll.p1 = clock.p1;
7907 crtc_state->dpll.p2 = clock.p2;
f47709a9 7908 }
7026d4ac 7909
e9fd1c02 7910 if (IS_GEN2(dev)) {
190f68c5 7911 i8xx_update_pll(crtc, crtc_state,
2a8f64ca
VP		 7912 has_reduced_clock ? &reduced_clock : NULL,
7913 num_connectors);
9d556c99 7914 } else if (IS_CHERRYVIEW(dev)) {
190f68c5 7915 chv_update_pll(crtc, crtc_state);
e9fd1c02 7916 } else if (IS_VALLEYVIEW(dev)) {
190f68c5 7917 vlv_update_pll(crtc, crtc_state);
e9fd1c02 7918 } else {
190f68c5 7919 i9xx_update_pll(crtc, crtc_state,
eb1cbe48 7920 has_reduced_clock ? &reduced_clock : NULL,
eba905b2 7921 num_connectors);
e9fd1c02 7922 }
79e53945 7923
c8f7a0db 7924 return 0;
f564048e
EA		 7925}
7926
2fa2fe9a 7927static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7928 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 7929{
7930 struct drm_device *dev = crtc->base.dev;
7931 struct drm_i915_private *dev_priv = dev->dev_private;
7932 uint32_t tmp;
7933
dc9e7dec
VS		 7934 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7935 return;
7936
2fa2fe9a 7937 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 7938 if (!(tmp & PFIT_ENABLE))
7939 return;
2fa2fe9a 7940
06922821 7941 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 7942 if (INTEL_INFO(dev)->gen < 4) {
7943 if (crtc->pipe != PIPE_B)
7944 return;
2fa2fe9a
DV		 7945 } else {
7946 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7947 return;
7948 }
7949
06922821 7950 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 7951 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7952 if (INTEL_INFO(dev)->gen < 5)
7953 pipe_config->gmch_pfit.lvds_border_bits =
7954 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7955}
7956
acbec814 7957static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7958 struct intel_crtc_state *pipe_config)
acbec814
JB		 7959{
7960 struct drm_device *dev = crtc->base.dev;
7961 struct drm_i915_private *dev_priv = dev->dev_private;
7962 int pipe = pipe_config->cpu_transcoder;
7963 intel_clock_t clock;
7964 u32 mdiv;
662c6ecb 7965 int refclk = 100000;
acbec814 7966
f573de5a
SK		 7967 /* In case of MIPI DPLL will not even be used */
7968 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7969 return;
7970
a580516d 7971 mutex_lock(&dev_priv->sb_lock);
ab3c759a 7972 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
a580516d 7973 mutex_unlock(&dev_priv->sb_lock);
acbec814
JB		 7974
7975 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7976 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7977 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7978 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7979 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7980
f646628b 7981 vlv_clock(refclk, &clock);
acbec814 7982
f646628b
VS		 7983 /* clock.dot is the fast clock */
7984 pipe_config->port_clock = clock.dot / 5;
acbec814
JB		 7985}
7986
5724dbd1
DL		 7987static void
7988i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7989 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 7990{
7991 struct drm_device *dev = crtc->base.dev;
7992 struct drm_i915_private *dev_priv = dev->dev_private;
7993 u32 val, base, offset;
7994 int pipe = crtc->pipe, plane = crtc->plane;
7995 int fourcc, pixel_format;
6761dd31 7996 unsigned int aligned_height;
b113d5ee 7997 struct drm_framebuffer *fb;
1b842c89 7998 struct intel_framebuffer *intel_fb;
1ad292b5 7999
42a7b088
DL		 8000 val = I915_READ(DSPCNTR(plane));
8001 if (!(val & DISPLAY_PLANE_ENABLE))
8002 return;
8003
d9806c9f 8004 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8005 if (!intel_fb) {
1ad292b5
JB		 8006 DRM_DEBUG_KMS("failed to alloc fb\n");
8007 return;
8008 }
8009
1b842c89
DL		 8010 fb = &intel_fb->base;
8011
18c5247e
DV		 8012 if (INTEL_INFO(dev)->gen >= 4) {
8013 if (val & DISPPLANE_TILED) {
49af449b 8014 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 8015 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8016 }
8017 }
1ad292b5
JB		 8018
8019 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 8020 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 8021 fb->pixel_format = fourcc;
8022 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 8023
8024 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 8025 if (plane_config->tiling)
1ad292b5
JB		 8026 offset = I915_READ(DSPTILEOFF(plane));
8027 else
8028 offset = I915_READ(DSPLINOFF(plane));
8029 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8030 } else {
8031 base = I915_READ(DSPADDR(plane));
8032 }
8033 plane_config->base = base;
8034
8035 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 8036 fb->width = ((val >> 16) & 0xfff) + 1;
8037 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 8038
8039 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 8040 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 8041
b113d5ee 8042 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8043 fb->pixel_format,
8044 fb->modifier[0]);
1ad292b5 8045
f37b5c2b 8046 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 8047
2844a921
DL		 8048 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8049 pipe_name(pipe), plane, fb->width, fb->height,
8050 fb->bits_per_pixel, base, fb->pitches[0],
8051 plane_config->size);
1ad292b5 8052
2d14030b 8053 plane_config->fb = intel_fb;
1ad292b5
JB		 8054}
8055
70b23a98 8056static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 8057 struct intel_crtc_state *pipe_config)
70b23a98
VS		 8058{
8059 struct drm_device *dev = crtc->base.dev;
8060 struct drm_i915_private *dev_priv = dev->dev_private;
8061 int pipe = pipe_config->cpu_transcoder;
8062 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8063 intel_clock_t clock;
8064 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
8065 int refclk = 100000;
8066
a580516d 8067 mutex_lock(&dev_priv->sb_lock);
70b23a98
VS		 8068 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8069 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8070 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8071 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
a580516d 8072 mutex_unlock(&dev_priv->sb_lock);
70b23a98
VS		 8073
8074 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8075 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
8076 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8077 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8078 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8079
8080 chv_clock(refclk, &clock);
8081
8082 /* clock.dot is the fast clock */
8083 pipe_config->port_clock = clock.dot / 5;
8084}
8085
0e8ffe1b 8086static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8087 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8088{
8089 struct drm_device *dev = crtc->base.dev;
8090 struct drm_i915_private *dev_priv = dev->dev_private;
8091 uint32_t tmp;
8092
f458ebbc
DV		 8093 if (!intel_display_power_is_enabled(dev_priv,
8094 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 8095 return false;
8096
e143a21c 8097 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8098 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8099
0e8ffe1b
DV		 8100 tmp = I915_READ(PIPECONF(crtc->pipe));
8101 if (!(tmp & PIPECONF_ENABLE))
8102 return false;
8103
42571aef
VS		 8104 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8105 switch (tmp & PIPECONF_BPC_MASK) {
8106 case PIPECONF_6BPC:
8107 pipe_config->pipe_bpp = 18;
8108 break;
8109 case PIPECONF_8BPC:
8110 pipe_config->pipe_bpp = 24;
8111 break;
8112 case PIPECONF_10BPC:
8113 pipe_config->pipe_bpp = 30;
8114 break;
8115 default:
8116 break;
8117 }
8118 }
8119
b5a9fa09
DV		 8120 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8121 pipe_config->limited_color_range = true;
8122
282740f7
VS		 8123 if (INTEL_INFO(dev)->gen < 4)
8124 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8125
1bd1bd80
DV		 8126 intel_get_pipe_timings(crtc, pipe_config);
8127
2fa2fe9a
DV		 8128 i9xx_get_pfit_config(crtc, pipe_config);
8129
6c49f241
DV		 8130 if (INTEL_INFO(dev)->gen >= 4) {
8131 tmp = I915_READ(DPLL_MD(crtc->pipe));
8132 pipe_config->pixel_multiplier =
8133 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8134 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 8135 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 8136 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8137 tmp = I915_READ(DPLL(crtc->pipe));
8138 pipe_config->pixel_multiplier =
8139 ((tmp & SDVO_MULTIPLIER_MASK)
8140 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8141 } else {
8142 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8143 * port and will be fixed up in the encoder->get_config
8144 * function. */
8145 pipe_config->pixel_multiplier = 1;
8146 }
8bcc2795
DV		 8147 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8148 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 8149 /*
8150 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8151 * on 830. Filter it out here so that we don't
8152 * report errors due to that.
8153 */
8154 if (IS_I830(dev))
8155 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8156
8bcc2795
DV		 8157 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8158 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 8159 } else {
8160 /* Mask out read-only status bits. */
8161 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8162 DPLL_PORTC_READY_MASK |
8163 DPLL_PORTB_READY_MASK);
8bcc2795 8164 }
6c49f241 8165
70b23a98
VS		 8166 if (IS_CHERRYVIEW(dev))
8167 chv_crtc_clock_get(crtc, pipe_config);
8168 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 8169 vlv_crtc_clock_get(crtc, pipe_config);
8170 else
8171 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 8172
0e8ffe1b
DV		 8173 return true;
8174}
8175
dde86e2d 8176static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 8177{
8178 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 8179 struct intel_encoder *encoder;
74cfd7ac 8180 u32 val, final;
13d83a67 8181 bool has_lvds = false;
199e5d79 8182 bool has_cpu_edp = false;
199e5d79 8183 bool has_panel = false;
99eb6a01
KP		 8184 bool has_ck505 = false;
8185 bool can_ssc = false;
13d83a67
JB		 8186
8187 /* We need to take the global config into account */
b2784e15 8188 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 8189 switch (encoder->type) {
8190 case INTEL_OUTPUT_LVDS:
8191 has_panel = true;
8192 has_lvds = true;
8193 break;
8194 case INTEL_OUTPUT_EDP:
8195 has_panel = true;
2de6905f 8196 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 8197 has_cpu_edp = true;
8198 break;
6847d71b
PZ		 8199 default:
8200 break;
13d83a67
JB		 8201 }
8202 }
8203
99eb6a01 8204 if (HAS_PCH_IBX(dev)) {
41aa3448 8205 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 8206 can_ssc = has_ck505;
8207 } else {
8208 has_ck505 = false;
8209 can_ssc = true;
8210 }
8211
2de6905f
ID		 8212 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8213 has_panel, has_lvds, has_ck505);
13d83a67
JB		 8214
8215 /* Ironlake: try to setup display ref clock before DPLL
8216 * enabling. This is only under driver's control after
8217 * PCH B stepping, previous chipset stepping should be
8218 * ignoring this setting.
8219 */
74cfd7ac
CW		 8220 val = I915_READ(PCH_DREF_CONTROL);
8221
8222 /* As we must carefully and slowly disable/enable each source in turn,
8223 * compute the final state we want first and check if we need to
8224 * make any changes at all.
8225 */
8226 final = val;
8227 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8228 if (has_ck505)
8229 final |= DREF_NONSPREAD_CK505_ENABLE;
8230 else
8231 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8232
8233 final &= ~DREF_SSC_SOURCE_MASK;
8234 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8235 final &= ~DREF_SSC1_ENABLE;
8236
8237 if (has_panel) {
8238 final |= DREF_SSC_SOURCE_ENABLE;
8239
8240 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8241 final |= DREF_SSC1_ENABLE;
8242
8243 if (has_cpu_edp) {
8244 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8245 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8246 else
8247 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8248 } else
8249 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8250 } else {
8251 final |= DREF_SSC_SOURCE_DISABLE;
8252 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8253 }
8254
8255 if (final == val)
8256 return;
8257
13d83a67 8258 /* Always enable nonspread source */
74cfd7ac 8259 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 8260
99eb6a01 8261 if (has_ck505)
74cfd7ac 8262 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 8263 else
74cfd7ac 8264 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 8265
199e5d79 8266 if (has_panel) {
74cfd7ac
CW		 8267 val &= ~DREF_SSC_SOURCE_MASK;
8268 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 8269
199e5d79 8270 /* SSC must be turned on before enabling the CPU output */
99eb6a01 8271 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8272 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 8273 val |= DREF_SSC1_ENABLE;
e77166b5 8274 } else
74cfd7ac 8275 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 8276
8277 /* Get SSC going before enabling the outputs */
74cfd7ac 8278 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8279 POSTING_READ(PCH_DREF_CONTROL);
8280 udelay(200);
8281
74cfd7ac 8282 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 8283
8284 /* Enable CPU source on CPU attached eDP */
199e5d79 8285 if (has_cpu_edp) {
99eb6a01 8286 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8287 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 8288 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 8289 } else
74cfd7ac 8290 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 8291 } else
74cfd7ac 8292 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8293
74cfd7ac 8294 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8295 POSTING_READ(PCH_DREF_CONTROL);
8296 udelay(200);
8297 } else {
8298 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8299
74cfd7ac 8300 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 8301
8302 /* Turn off CPU output */
74cfd7ac 8303 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8304
74cfd7ac 8305 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8306 POSTING_READ(PCH_DREF_CONTROL);
8307 udelay(200);
8308
8309 /* Turn off the SSC source */
74cfd7ac
CW		 8310 val &= ~DREF_SSC_SOURCE_MASK;
8311 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 8312
8313 /* Turn off SSC1 */
74cfd7ac 8314 val &= ~DREF_SSC1_ENABLE;
199e5d79 8315
74cfd7ac 8316 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 8317 POSTING_READ(PCH_DREF_CONTROL);
8318 udelay(200);
8319 }
74cfd7ac
CW		 8320
8321 BUG_ON(val != final);
13d83a67
JB		 8322}
8323
f31f2d55 8324static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 8325{
f31f2d55 8326 uint32_t tmp;
dde86e2d 8327
0ff066a9
PZ		 8328 tmp = I915_READ(SOUTH_CHICKEN2);
8329 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8330 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8331
0ff066a9
PZ		 8332 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8333 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8334 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 8335
0ff066a9
PZ		 8336 tmp = I915_READ(SOUTH_CHICKEN2);
8337 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8338 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8339
0ff066a9
PZ		 8340 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8341 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8342 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 8343}
8344
8345/* WaMPhyProgramming:hsw */
8346static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8347{
8348 uint32_t tmp;
dde86e2d
PZ		 8349
8350 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8351 tmp &= ~(0xFF << 24);
8352 tmp |= (0x12 << 24);
8353 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8354
dde86e2d
PZ		 8355 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8356 tmp |= (1 << 11);
8357 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8358
8359 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8360 tmp |= (1 << 11);
8361 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8362
dde86e2d
PZ		 8363 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8364 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8365 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8366
8367 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8368 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8369 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8370
0ff066a9
PZ		 8371 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8372 tmp &= ~(7 << 13);
8373 tmp |= (5 << 13);
8374 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 8375
0ff066a9
PZ		 8376 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8377 tmp &= ~(7 << 13);
8378 tmp |= (5 << 13);
8379 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 8380
8381 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8382 tmp &= ~0xFF;
8383 tmp |= 0x1C;
8384 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8385
8386 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8387 tmp &= ~0xFF;
8388 tmp |= 0x1C;
8389 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8390
8391 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8392 tmp &= ~(0xFF << 16);
8393 tmp |= (0x1C << 16);
8394 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8395
8396 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8397 tmp &= ~(0xFF << 16);
8398 tmp |= (0x1C << 16);
8399 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8400
0ff066a9
PZ		 8401 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8402 tmp |= (1 << 27);
8403 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 8404
0ff066a9
PZ		 8405 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8406 tmp |= (1 << 27);
8407 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 8408
0ff066a9
PZ		 8409 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8410 tmp &= ~(0xF << 28);
8411 tmp |= (4 << 28);
8412 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 8413
0ff066a9
PZ		 8414 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8415 tmp &= ~(0xF << 28);
8416 tmp |= (4 << 28);
8417 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 8418}
8419
2fa86a1f
PZ		 8420/* Implements 3 different sequences from BSpec chapter "Display iCLK
8421 * Programming" based on the parameters passed:
8422 * - Sequence to enable CLKOUT_DP
8423 * - Sequence to enable CLKOUT_DP without spread
8424 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8425 */
8426static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8427 bool with_fdi)
f31f2d55
PZ		 8428{
8429 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 8430 uint32_t reg, tmp;
8431
8432 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8433 with_spread = true;
8434 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8435 with_fdi, "LP PCH doesn't have FDI\n"))
8436 with_fdi = false;
f31f2d55 8437
a580516d 8438 mutex_lock(&dev_priv->sb_lock);
f31f2d55
PZ		 8439
8440 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8441 tmp &= ~SBI_SSCCTL_DISABLE;
8442 tmp |= SBI_SSCCTL_PATHALT;
8443 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8444
8445 udelay(24);
8446
2fa86a1f
PZ		 8447 if (with_spread) {
8448 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8449 tmp &= ~SBI_SSCCTL_PATHALT;
8450 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 8451
2fa86a1f
PZ		 8452 if (with_fdi) {
8453 lpt_reset_fdi_mphy(dev_priv);
8454 lpt_program_fdi_mphy(dev_priv);
8455 }
8456 }
dde86e2d 8457
2fa86a1f
PZ		 8458 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8459 SBI_GEN0 : SBI_DBUFF0;
8460 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8461 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8462 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246 8463
a580516d 8464 mutex_unlock(&dev_priv->sb_lock);
dde86e2d
PZ		 8465}
8466
47701c3b
PZ		 8467/* Sequence to disable CLKOUT_DP */
8468static void lpt_disable_clkout_dp(struct drm_device *dev)
8469{
8470 struct drm_i915_private *dev_priv = dev->dev_private;
8471 uint32_t reg, tmp;
8472
a580516d 8473 mutex_lock(&dev_priv->sb_lock);
47701c3b
PZ		 8474
8475 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8476 SBI_GEN0 : SBI_DBUFF0;
8477 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8478 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8479 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8480
8481 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8482 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8483 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8484 tmp |= SBI_SSCCTL_PATHALT;
8485 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8486 udelay(32);
8487 }
8488 tmp |= SBI_SSCCTL_DISABLE;
8489 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8490 }
8491
a580516d 8492 mutex_unlock(&dev_priv->sb_lock);
47701c3b
PZ		 8493}
8494
bf8fa3d3
PZ		 8495static void lpt_init_pch_refclk(struct drm_device *dev)
8496{
bf8fa3d3
PZ		 8497 struct intel_encoder *encoder;
8498 bool has_vga = false;
8499
b2784e15 8500 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 8501 switch (encoder->type) {
8502 case INTEL_OUTPUT_ANALOG:
8503 has_vga = true;
8504 break;
6847d71b
PZ		 8505 default:
8506 break;
bf8fa3d3
PZ		 8507 }
8508 }
8509
47701c3b
PZ		 8510 if (has_vga)
8511 lpt_enable_clkout_dp(dev, true, true);
8512 else
8513 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 8514}
8515
dde86e2d
PZ		 8516/*
8517 * Initialize reference clocks when the driver loads
8518 */
8519void intel_init_pch_refclk(struct drm_device *dev)
8520{
8521 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8522 ironlake_init_pch_refclk(dev);
8523 else if (HAS_PCH_LPT(dev))
8524 lpt_init_pch_refclk(dev);
8525}
8526
55bb9992 8527static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 8528{
55bb9992 8529 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 8530 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8531 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8532 struct drm_connector *connector;
55bb9992 8533 struct drm_connector_state *connector_state;
d9d444cb 8534 struct intel_encoder *encoder;
55bb9992 8535 int num_connectors = 0, i;
d9d444cb
JB		 8536 bool is_lvds = false;
8537
da3ced29 8538 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8539 if (connector_state->crtc != crtc_state->base.crtc)
8540 continue;
8541
8542 encoder = to_intel_encoder(connector_state->best_encoder);
8543
d9d444cb
JB		 8544 switch (encoder->type) {
8545 case INTEL_OUTPUT_LVDS:
8546 is_lvds = true;
8547 break;
6847d71b
PZ		 8548 default:
8549 break;
d9d444cb
JB		 8550 }
8551 num_connectors++;
8552 }
8553
8554 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 8555 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 8556 dev_priv->vbt.lvds_ssc_freq);
e91e941b 8557 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 8558 }
8559
8560 return 120000;
8561}
8562
6ff93609 8563static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 8564{
c8203565 8565 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 8566 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8567 int pipe = intel_crtc->pipe;
c8203565
PZ		 8568 uint32_t val;
8569
78114071 8570 val = 0;
c8203565 8571
6e3c9717 8572 switch (intel_crtc->config->pipe_bpp) {
c8203565 8573 case 18:
dfd07d72 8574 val |= PIPECONF_6BPC;
c8203565
PZ		 8575 break;
8576 case 24:
dfd07d72 8577 val |= PIPECONF_8BPC;
c8203565
PZ		 8578 break;
8579 case 30:
dfd07d72 8580 val |= PIPECONF_10BPC;
c8203565
PZ		 8581 break;
8582 case 36:
dfd07d72 8583 val |= PIPECONF_12BPC;
c8203565
PZ		 8584 break;
8585 default:
cc769b62
PZ		 8586 /* Case prevented by intel_choose_pipe_bpp_dither. */
8587 BUG();
c8203565
PZ		 8588 }
8589
6e3c9717 8590 if (intel_crtc->config->dither)
c8203565
PZ		 8591 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8592
6e3c9717 8593 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 8594 val |= PIPECONF_INTERLACED_ILK;
8595 else
8596 val |= PIPECONF_PROGRESSIVE;
8597
6e3c9717 8598 if (intel_crtc->config->limited_color_range)
3685a8f3 8599 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 8600
c8203565
PZ		 8601 I915_WRITE(PIPECONF(pipe), val);
8602 POSTING_READ(PIPECONF(pipe));
8603}
8604
86d3efce
VS		 8605/*
8606 * Set up the pipe CSC unit.
8607 *
8608 * Currently only full range RGB to limited range RGB conversion
8609 * is supported, but eventually this should handle various
8610 * RGB<->YCbCr scenarios as well.
8611 */
50f3b016 8612static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 8613{
8614 struct drm_device *dev = crtc->dev;
8615 struct drm_i915_private *dev_priv = dev->dev_private;
8616 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8617 int pipe = intel_crtc->pipe;
8618 uint16_t coeff = 0x7800; /* 1.0 */
8619
8620 /*
8621 * TODO: Check what kind of values actually come out of the pipe
8622 * with these coeff/postoff values and adjust to get the best
8623 * accuracy. Perhaps we even need to take the bpc value into
8624 * consideration.
8625 */
8626
6e3c9717 8627 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8628 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8629
8630 /*
8631 * GY/GU and RY/RU should be the other way around according
8632 * to BSpec, but reality doesn't agree. Just set them up in
8633 * a way that results in the correct picture.
8634 */
8635 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8636 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8637
8638 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8639 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8640
8641 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8642 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8643
8644 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8645 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8646 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8647
8648 if (INTEL_INFO(dev)->gen > 6) {
8649 uint16_t postoff = 0;
8650
6e3c9717 8651 if (intel_crtc->config->limited_color_range)
32cf0cb0 8652 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 8653
8654 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8655 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8656 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8657
8658 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8659 } else {
8660 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8661
6e3c9717 8662 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8663 mode |= CSC_BLACK_SCREEN_OFFSET;
8664
8665 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8666 }
8667}
8668
6ff93609 8669static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8670{
756f85cf
PZ		 8671 struct drm_device *dev = crtc->dev;
8672 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 8673 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8674 enum pipe pipe = intel_crtc->pipe;
6e3c9717 8675 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 8676 uint32_t val;
8677
3eff4faa 8678 val = 0;
ee2b0b38 8679
6e3c9717 8680 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 8681 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8682
6e3c9717 8683 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 8684 val |= PIPECONF_INTERLACED_ILK;
8685 else
8686 val |= PIPECONF_PROGRESSIVE;
8687
702e7a56
PZ		 8688 I915_WRITE(PIPECONF(cpu_transcoder), val);
8689 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 8690
8691 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8692 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 8693
3cdf122c 8694 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 8695 val = 0;
8696
6e3c9717 8697 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 8698 case 18:
8699 val |= PIPEMISC_DITHER_6_BPC;
8700 break;
8701 case 24:
8702 val |= PIPEMISC_DITHER_8_BPC;
8703 break;
8704 case 30:
8705 val |= PIPEMISC_DITHER_10_BPC;
8706 break;
8707 case 36:
8708 val |= PIPEMISC_DITHER_12_BPC;
8709 break;
8710 default:
8711 /* Case prevented by pipe_config_set_bpp. */
8712 BUG();
8713 }
8714
6e3c9717 8715 if (intel_crtc->config->dither)
756f85cf
PZ		 8716 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8717
8718 I915_WRITE(PIPEMISC(pipe), val);
8719 }
ee2b0b38
PZ		 8720}
8721
6591c6e4 8722static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 8723 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 8724 intel_clock_t *clock,
8725 bool *has_reduced_clock,
8726 intel_clock_t *reduced_clock)
8727{
8728 struct drm_device *dev = crtc->dev;
8729 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 8730 int refclk;
d4906093 8731 const intel_limit_t *limit;
a16af721 8732 bool ret, is_lvds = false;
79e53945 8733
a93e255f 8734 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
79e53945 8735
55bb9992 8736 refclk = ironlake_get_refclk(crtc_state);
79e53945 8737
d4906093
ML		 8738 /*
8739 * Returns a set of divisors for the desired target clock with the given
8740 * refclk, or FALSE. The returned values represent the clock equation:
8741 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8742 */
a93e255f
ACO		 8743 limit = intel_limit(crtc_state, refclk);
8744 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 8745 crtc_state->port_clock,
ee9300bb 8746 refclk, NULL, clock);
6591c6e4
PZ		 8747 if (!ret)
8748 return false;
cda4b7d3 8749
ddc9003c 8750 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 8751 /*
8752 * Ensure we match the reduced clock's P to the target clock.
8753 * If the clocks don't match, we can't switch the display clock
8754 * by using the FP0/FP1. In such case we will disable the LVDS
8755 * downclock feature.
8756 */
ee9300bb 8757 *has_reduced_clock =
a93e255f 8758 dev_priv->display.find_dpll(limit, crtc_state,
ee9300bb
DV		 8759 dev_priv->lvds_downclock,
8760 refclk, clock,
8761 reduced_clock);
652c393a 8762 }
61e9653f 8763
6591c6e4
PZ		 8764 return true;
8765}
8766
d4b1931c
PZ		 8767int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8768{
8769 /*
8770 * Account for spread spectrum to avoid
8771 * oversubscribing the link. Max center spread
8772 * is 2.5%; use 5% for safety's sake.
8773 */
8774 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8775 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 8776}
8777
7429e9d4 8778static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8779{
7429e9d4 8780 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 8781}
8782
de13a2e3 8783static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 8784 struct intel_crtc_state *crtc_state,
7429e9d4 8785 u32 *fp,
9a7c7890 8786 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 8787{
de13a2e3 8788 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 8789 struct drm_device *dev = crtc->dev;
8790 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8791 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8792 struct drm_connector *connector;
55bb9992
ACO		 8793 struct drm_connector_state *connector_state;
8794 struct intel_encoder *encoder;
de13a2e3 8795 uint32_t dpll;
55bb9992 8796 int factor, num_connectors = 0, i;
09ede541 8797 bool is_lvds = false, is_sdvo = false;
79e53945 8798
da3ced29 8799 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8800 if (connector_state->crtc != crtc_state->base.crtc)
8801 continue;
8802
8803 encoder = to_intel_encoder(connector_state->best_encoder);
8804
8805 switch (encoder->type) {
79e53945
JB		 8806 case INTEL_OUTPUT_LVDS:
8807 is_lvds = true;
8808 break;
8809 case INTEL_OUTPUT_SDVO:
7d57382e 8810 case INTEL_OUTPUT_HDMI:
79e53945 8811 is_sdvo = true;
79e53945 8812 break;
6847d71b
PZ		 8813 default:
8814 break;
79e53945 8815 }
43565a06 8816
c751ce4f 8817 num_connectors++;
79e53945 8818 }
79e53945 8819
c1858123 8820 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 8821 factor = 21;
8822 if (is_lvds) {
8823 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8824 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8825 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8826 factor = 25;
190f68c5 8827 } else if (crtc_state->sdvo_tv_clock)
8febb297 8828 factor = 20;
c1858123 8829
190f68c5 8830 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 8831 *fp |= FP_CB_TUNE;
2c07245f 8832
9a7c7890
DV		 8833 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8834 *fp2 |= FP_CB_TUNE;
8835
5eddb70b 8836 dpll = 0;
2c07245f 8837
a07d6787
EA		 8838 if (is_lvds)
8839 dpll |= DPLLB_MODE_LVDS;
8840 else
8841 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8842
190f68c5 8843 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8844 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 8845
8846 if (is_sdvo)
4a33e48d 8847 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8848 if (crtc_state->has_dp_encoder)
4a33e48d 8849 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8850
a07d6787 8851 /* compute bitmask from p1 value */
190f68c5 8852 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8853 /* also FPA1 */
190f68c5 8854 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8855
190f68c5 8856 switch (crtc_state->dpll.p2) {
a07d6787
EA		 8857 case 5:
8858 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8859 break;
8860 case 7:
8861 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8862 break;
8863 case 10:
8864 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8865 break;
8866 case 14:
8867 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8868 break;
79e53945
JB		 8869 }
8870
b4c09f3b 8871 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 8872 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 8873 else
8874 dpll |= PLL_REF_INPUT_DREFCLK;
8875
959e16d6 8876 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 8877}
8878
190f68c5
ACO		 8879static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8880 struct intel_crtc_state *crtc_state)
de13a2e3 8881{
c7653199 8882 struct drm_device *dev = crtc->base.dev;
de13a2e3 8883 intel_clock_t clock, reduced_clock;
cbbab5bd 8884 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 8885 bool ok, has_reduced_clock = false;
8b47047b 8886 bool is_lvds = false;
e2b78267 8887 struct intel_shared_dpll *pll;
de13a2e3 8888
dd3cd74a
ACO		 8889 memset(&crtc_state->dpll_hw_state, 0,
8890 sizeof(crtc_state->dpll_hw_state));
8891
409ee761 8892 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 8893
5dc5298b
PZ		 8894 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8895 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 8896
190f68c5 8897 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 8898 &has_reduced_clock, &reduced_clock);
190f68c5 8899 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 8900 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8901 return -EINVAL;
79e53945 8902 }
f47709a9 8903 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 8904 if (!crtc_state->clock_set) {
8905 crtc_state->dpll.n = clock.n;
8906 crtc_state->dpll.m1 = clock.m1;
8907 crtc_state->dpll.m2 = clock.m2;
8908 crtc_state->dpll.p1 = clock.p1;
8909 crtc_state->dpll.p2 = clock.p2;
f47709a9 8910 }
79e53945 8911
5dc5298b 8912 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 8913 if (crtc_state->has_pch_encoder) {
8914 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 8915 if (has_reduced_clock)
7429e9d4 8916 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 8917
190f68c5 8918 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 8919 &fp, &reduced_clock,
8920 has_reduced_clock ? &fp2 : NULL);
8921
190f68c5
ACO		 8922 crtc_state->dpll_hw_state.dpll = dpll;
8923 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 8924 if (has_reduced_clock)
190f68c5 8925 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 8926 else
190f68c5 8927 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 8928
190f68c5 8929 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 8930 if (pll == NULL) {
84f44ce7 8931 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 8932 pipe_name(crtc->pipe));
4b645f14
JB		 8933 return -EINVAL;
8934 }
3fb37703 8935 }
79e53945 8936
ab585dea 8937 if (is_lvds && has_reduced_clock)
c7653199 8938 crtc->lowfreq_avail = true;
bcd644e0 8939 else
c7653199 8940 crtc->lowfreq_avail = false;
e2b78267 8941
c8f7a0db 8942 return 0;
79e53945
JB		 8943}
8944
eb14cb74
VS		 8945static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8946 struct intel_link_m_n *m_n)
8947{
8948 struct drm_device *dev = crtc->base.dev;
8949 struct drm_i915_private *dev_priv = dev->dev_private;
8950 enum pipe pipe = crtc->pipe;
8951
8952 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8953 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8954 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8955 & ~TU_SIZE_MASK;
8956 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8957 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8958 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8959}
8960
8961static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8962 enum transcoder transcoder,
b95af8be
VK		 8963 struct intel_link_m_n *m_n,
8964 struct intel_link_m_n *m2_n2)
72419203
DV		 8965{
8966 struct drm_device *dev = crtc->base.dev;
8967 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 8968 enum pipe pipe = crtc->pipe;
72419203 8969
eb14cb74
VS		 8970 if (INTEL_INFO(dev)->gen >= 5) {
8971 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8972 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8973 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8974 & ~TU_SIZE_MASK;
8975 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8976 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8977 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 8978 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8979 * gen < 8) and if DRRS is supported (to make sure the
8980 * registers are not unnecessarily read).
8981 */
8982 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 8983 crtc->config->has_drrs) {
b95af8be
VK		 8984 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8985 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8986 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8987 & ~TU_SIZE_MASK;
8988 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8989 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8990 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8991 }
eb14cb74
VS		 8992 } else {
8993 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8994 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8995 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8996 & ~TU_SIZE_MASK;
8997 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8998 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8999 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9000 }
9001}
9002
9003void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 9004 struct intel_crtc_state *pipe_config)
eb14cb74 9005{
681a8504 9006 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 9007 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9008 else
9009 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 9010 &pipe_config->dp_m_n,
9011 &pipe_config->dp_m2_n2);
eb14cb74 9012}
72419203 9013
eb14cb74 9014static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 9015 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 9016{
9017 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 9018 &pipe_config->fdi_m_n, NULL);
72419203
DV		 9019}
9020
bd2e244f 9021static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9022 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 9023{
9024 struct drm_device *dev = crtc->base.dev;
9025 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK		 9026 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9027 uint32_t ps_ctrl = 0;
9028 int id = -1;
9029 int i;
bd2e244f 9030
a1b2278e
CK		 9031 /* find scaler attached to this pipe */
9032 for (i = 0; i < crtc->num_scalers; i++) {
9033 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9034 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9035 id = i;
9036 pipe_config->pch_pfit.enabled = true;
9037 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9038 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9039 break;
9040 }
9041 }
bd2e244f 9042
a1b2278e
CK		 9043 scaler_state->scaler_id = id;
9044 if (id >= 0) {
9045 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9046 } else {
9047 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB		 9048 }
9049}
9050
5724dbd1
DL		 9051static void
9052skylake_get_initial_plane_config(struct intel_crtc *crtc,
9053 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 9054{
9055 struct drm_device *dev = crtc->base.dev;
9056 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 9057 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 9058 int pipe = crtc->pipe;
9059 int fourcc, pixel_format;
6761dd31 9060 unsigned int aligned_height;
bc8d7dff 9061 struct drm_framebuffer *fb;
1b842c89 9062 struct intel_framebuffer *intel_fb;
bc8d7dff 9063
d9806c9f 9064 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9065 if (!intel_fb) {
bc8d7dff
DL		 9066 DRM_DEBUG_KMS("failed to alloc fb\n");
9067 return;
9068 }
9069
1b842c89
DL		 9070 fb = &intel_fb->base;
9071
bc8d7dff 9072 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 9073 if (!(val & PLANE_CTL_ENABLE))
9074 goto error;
9075
bc8d7dff
DL		 9076 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9077 fourcc = skl_format_to_fourcc(pixel_format,
9078 val & PLANE_CTL_ORDER_RGBX,
9079 val & PLANE_CTL_ALPHA_MASK);
9080 fb->pixel_format = fourcc;
9081 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9082
40f46283
DL		 9083 tiling = val & PLANE_CTL_TILED_MASK;
9084 switch (tiling) {
9085 case PLANE_CTL_TILED_LINEAR:
9086 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9087 break;
9088 case PLANE_CTL_TILED_X:
9089 plane_config->tiling = I915_TILING_X;
9090 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9091 break;
9092 case PLANE_CTL_TILED_Y:
9093 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9094 break;
9095 case PLANE_CTL_TILED_YF:
9096 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9097 break;
9098 default:
9099 MISSING_CASE(tiling);
9100 goto error;
9101 }
9102
bc8d7dff
DL		 9103 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9104 plane_config->base = base;
9105
9106 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9107
9108 val = I915_READ(PLANE_SIZE(pipe, 0));
9109 fb->height = ((val >> 16) & 0xfff) + 1;
9110 fb->width = ((val >> 0) & 0x1fff) + 1;
9111
9112 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 9113 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9114 fb->pixel_format);
bc8d7dff
DL		 9115 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9116
9117 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9118 fb->pixel_format,
9119 fb->modifier[0]);
bc8d7dff 9120
f37b5c2b 9121 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 9122
9123 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9124 pipe_name(pipe), fb->width, fb->height,
9125 fb->bits_per_pixel, base, fb->pitches[0],
9126 plane_config->size);
9127
2d14030b 9128 plane_config->fb = intel_fb;
bc8d7dff
DL		 9129 return;
9130
9131error:
9132 kfree(fb);
9133}
9134
2fa2fe9a 9135static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9136 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 9137{
9138 struct drm_device *dev = crtc->base.dev;
9139 struct drm_i915_private *dev_priv = dev->dev_private;
9140 uint32_t tmp;
9141
9142 tmp = I915_READ(PF_CTL(crtc->pipe));
9143
9144 if (tmp & PF_ENABLE) {
fd4daa9c 9145 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 9146 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9147 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 9148
9149 /* We currently do not free assignements of panel fitters on
9150 * ivb/hsw (since we don't use the higher upscaling modes which
9151 * differentiates them) so just WARN about this case for now. */
9152 if (IS_GEN7(dev)) {
9153 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9154 PF_PIPE_SEL_IVB(crtc->pipe));
9155 }
2fa2fe9a 9156 }
79e53945
JB		 9157}
9158
5724dbd1
DL		 9159static void
9160ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9161 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 9162{
9163 struct drm_device *dev = crtc->base.dev;
9164 struct drm_i915_private *dev_priv = dev->dev_private;
9165 u32 val, base, offset;
aeee5a49 9166 int pipe = crtc->pipe;
4c6baa59 9167 int fourcc, pixel_format;
6761dd31 9168 unsigned int aligned_height;
b113d5ee 9169 struct drm_framebuffer *fb;
1b842c89 9170 struct intel_framebuffer *intel_fb;
4c6baa59 9171
42a7b088
DL		 9172 val = I915_READ(DSPCNTR(pipe));
9173 if (!(val & DISPLAY_PLANE_ENABLE))
9174 return;
9175
d9806c9f 9176 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9177 if (!intel_fb) {
4c6baa59
JB		 9178 DRM_DEBUG_KMS("failed to alloc fb\n");
9179 return;
9180 }
9181
1b842c89
DL		 9182 fb = &intel_fb->base;
9183
18c5247e
DV		 9184 if (INTEL_INFO(dev)->gen >= 4) {
9185 if (val & DISPPLANE_TILED) {
49af449b 9186 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 9187 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9188 }
9189 }
4c6baa59
JB		 9190
9191 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 9192 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 9193 fb->pixel_format = fourcc;
9194 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 9195
aeee5a49 9196 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 9197 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 9198 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 9199 } else {
49af449b 9200 if (plane_config->tiling)
aeee5a49 9201 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 9202 else
aeee5a49 9203 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 9204 }
9205 plane_config->base = base;
9206
9207 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 9208 fb->width = ((val >> 16) & 0xfff) + 1;
9209 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 9210
9211 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 9212 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 9213
b113d5ee 9214 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9215 fb->pixel_format,
9216 fb->modifier[0]);
4c6baa59 9217
f37b5c2b 9218 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 9219
2844a921
DL		 9220 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9221 pipe_name(pipe), fb->width, fb->height,
9222 fb->bits_per_pixel, base, fb->pitches[0],
9223 plane_config->size);
b113d5ee 9224
2d14030b 9225 plane_config->fb = intel_fb;
4c6baa59
JB		 9226}
9227
0e8ffe1b 9228static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9229 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9230{
9231 struct drm_device *dev = crtc->base.dev;
9232 struct drm_i915_private *dev_priv = dev->dev_private;
9233 uint32_t tmp;
9234
f458ebbc
DV		 9235 if (!intel_display_power_is_enabled(dev_priv,
9236 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 9237 return false;
9238
e143a21c 9239 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 9240 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 9241
0e8ffe1b
DV		 9242 tmp = I915_READ(PIPECONF(crtc->pipe));
9243 if (!(tmp & PIPECONF_ENABLE))
9244 return false;
9245
42571aef
VS		 9246 switch (tmp & PIPECONF_BPC_MASK) {
9247 case PIPECONF_6BPC:
9248 pipe_config->pipe_bpp = 18;
9249 break;
9250 case PIPECONF_8BPC:
9251 pipe_config->pipe_bpp = 24;
9252 break;
9253 case PIPECONF_10BPC:
9254 pipe_config->pipe_bpp = 30;
9255 break;
9256 case PIPECONF_12BPC:
9257 pipe_config->pipe_bpp = 36;
9258 break;
9259 default:
9260 break;
9261 }
9262
b5a9fa09
DV		 9263 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9264 pipe_config->limited_color_range = true;
9265
ab9412ba 9266 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 9267 struct intel_shared_dpll *pll;
9268
88adfff1
DV		 9269 pipe_config->has_pch_encoder = true;
9270
627eb5a3
DV		 9271 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9272 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9273 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 9274
9275 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 9276
c0d43d62 9277 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 9278 pipe_config->shared_dpll =
9279 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 9280 } else {
9281 tmp = I915_READ(PCH_DPLL_SEL);
9282 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9283 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9284 else
9285 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9286 }
66e985c0
DV		 9287
9288 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9289
9290 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9291 &pipe_config->dpll_hw_state));
c93f54cf
DV		 9292
9293 tmp = pipe_config->dpll_hw_state.dpll;
9294 pipe_config->pixel_multiplier =
9295 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9296 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 9297
9298 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 9299 } else {
9300 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 9301 }
9302
1bd1bd80
DV		 9303 intel_get_pipe_timings(crtc, pipe_config);
9304
2fa2fe9a
DV		 9305 ironlake_get_pfit_config(crtc, pipe_config);
9306
0e8ffe1b
DV		 9307 return true;
9308}
9309
be256dc7
PZ		 9310static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9311{
9312 struct drm_device *dev = dev_priv->dev;
be256dc7 9313 struct intel_crtc *crtc;
be256dc7 9314
d3fcc808 9315 for_each_intel_crtc(dev, crtc)
e2c719b7 9316 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 9317 pipe_name(crtc->pipe));
9318
e2c719b7
RC		 9319 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9320 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9321 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9322 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9323 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9324 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 9325 "CPU PWM1 enabled\n");
c5107b87 9326 if (IS_HASWELL(dev))
e2c719b7 9327 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 9328 "CPU PWM2 enabled\n");
e2c719b7 9329 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 9330 "PCH PWM1 enabled\n");
e2c719b7 9331 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 9332 "Utility pin enabled\n");
e2c719b7 9333 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 9334
9926ada1
PZ		 9335 /*
9336 * In theory we can still leave IRQs enabled, as long as only the HPD
9337 * interrupts remain enabled. We used to check for that, but since it's
9338 * gen-specific and since we only disable LCPLL after we fully disable
9339 * the interrupts, the check below should be enough.
9340 */
e2c719b7 9341 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 9342}
9343
9ccd5aeb
PZ		 9344static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9345{
9346 struct drm_device *dev = dev_priv->dev;
9347
9348 if (IS_HASWELL(dev))
9349 return I915_READ(D_COMP_HSW);
9350 else
9351 return I915_READ(D_COMP_BDW);
9352}
9353
3c4c9b81
PZ		 9354static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9355{
9356 struct drm_device *dev = dev_priv->dev;
9357
9358 if (IS_HASWELL(dev)) {
9359 mutex_lock(&dev_priv->rps.hw_lock);
9360 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9361 val))
f475dadf 9362 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 9363 mutex_unlock(&dev_priv->rps.hw_lock);
9364 } else {
9ccd5aeb
PZ		 9365 I915_WRITE(D_COMP_BDW, val);
9366 POSTING_READ(D_COMP_BDW);
3c4c9b81 9367 }
be256dc7
PZ		 9368}
9369
9370/*
9371 * This function implements pieces of two sequences from BSpec:
9372 * - Sequence for display software to disable LCPLL
9373 * - Sequence for display software to allow package C8+
9374 * The steps implemented here are just the steps that actually touch the LCPLL
9375 * register. Callers should take care of disabling all the display engine
9376 * functions, doing the mode unset, fixing interrupts, etc.
9377 */
6ff58d53
PZ		 9378static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9379 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 9380{
9381 uint32_t val;
9382
9383 assert_can_disable_lcpll(dev_priv);
9384
9385 val = I915_READ(LCPLL_CTL);
9386
9387 if (switch_to_fclk) {
9388 val |= LCPLL_CD_SOURCE_FCLK;
9389 I915_WRITE(LCPLL_CTL, val);
9390
9391 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9392 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9393 DRM_ERROR("Switching to FCLK failed\n");
9394
9395 val = I915_READ(LCPLL_CTL);
9396 }
9397
9398 val |= LCPLL_PLL_DISABLE;
9399 I915_WRITE(LCPLL_CTL, val);
9400 POSTING_READ(LCPLL_CTL);
9401
9402 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9403 DRM_ERROR("LCPLL still locked\n");
9404
9ccd5aeb 9405 val = hsw_read_dcomp(dev_priv);
be256dc7 9406 val |= D_COMP_COMP_DISABLE;
3c4c9b81 9407 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9408 ndelay(100);
9409
9ccd5aeb
PZ		 9410 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9411 1))
be256dc7
PZ		 9412 DRM_ERROR("D_COMP RCOMP still in progress\n");
9413
9414 if (allow_power_down) {
9415 val = I915_READ(LCPLL_CTL);
9416 val |= LCPLL_POWER_DOWN_ALLOW;
9417 I915_WRITE(LCPLL_CTL, val);
9418 POSTING_READ(LCPLL_CTL);
9419 }
9420}
9421
9422/*
9423 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9424 * source.
9425 */
6ff58d53 9426static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 9427{
9428 uint32_t val;
9429
9430 val = I915_READ(LCPLL_CTL);
9431
9432 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9433 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9434 return;
9435
a8a8bd54
PZ		 9436 /*
9437 * Make sure we're not on PC8 state before disabling PC8, otherwise
9438 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 9439 */
59bad947 9440 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 9441
be256dc7
PZ		 9442 if (val & LCPLL_POWER_DOWN_ALLOW) {
9443 val &= ~LCPLL_POWER_DOWN_ALLOW;
9444 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 9445 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 9446 }
9447
9ccd5aeb 9448 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 9449 val |= D_COMP_COMP_FORCE;
9450 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 9451 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9452
9453 val = I915_READ(LCPLL_CTL);
9454 val &= ~LCPLL_PLL_DISABLE;
9455 I915_WRITE(LCPLL_CTL, val);
9456
9457 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9458 DRM_ERROR("LCPLL not locked yet\n");
9459
9460 if (val & LCPLL_CD_SOURCE_FCLK) {
9461 val = I915_READ(LCPLL_CTL);
9462 val &= ~LCPLL_CD_SOURCE_FCLK;
9463 I915_WRITE(LCPLL_CTL, val);
9464
9465 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9466 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9467 DRM_ERROR("Switching back to LCPLL failed\n");
9468 }
215733fa 9469
59bad947 9470 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
be256dc7
PZ		 9471}
9472
765dab67
PZ		 9473/*
9474 * Package states C8 and deeper are really deep PC states that can only be
9475 * reached when all the devices on the system allow it, so even if the graphics
9476 * device allows PC8+, it doesn't mean the system will actually get to these
9477 * states. Our driver only allows PC8+ when going into runtime PM.
9478 *
9479 * The requirements for PC8+ are that all the outputs are disabled, the power
9480 * well is disabled and most interrupts are disabled, and these are also
9481 * requirements for runtime PM. When these conditions are met, we manually do
9482 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9483 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9484 * hang the machine.
9485 *
9486 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9487 * the state of some registers, so when we come back from PC8+ we need to
9488 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9489 * need to take care of the registers kept by RC6. Notice that this happens even
9490 * if we don't put the device in PCI D3 state (which is what currently happens
9491 * because of the runtime PM support).
9492 *
9493 * For more, read "Display Sequences for Package C8" on the hardware
9494 * documentation.
9495 */
a14cb6fc 9496void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 9497{
c67a470b
PZ		 9498 struct drm_device *dev = dev_priv->dev;
9499 uint32_t val;
9500
c67a470b
PZ		 9501 DRM_DEBUG_KMS("Enabling package C8+\n");
9502
c67a470b
PZ		 9503 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9504 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9505 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9506 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9507 }
9508
9509 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 9510 hsw_disable_lcpll(dev_priv, true, true);
9511}
9512
a14cb6fc 9513void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 9514{
9515 struct drm_device *dev = dev_priv->dev;
9516 uint32_t val;
9517
c67a470b
PZ		 9518 DRM_DEBUG_KMS("Disabling package C8+\n");
9519
9520 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 9521 lpt_init_pch_refclk(dev);
9522
9523 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9524 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9525 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9526 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9527 }
9528
9529 intel_prepare_ddi(dev);
c67a470b
PZ		 9530}
9531
a821fc46 9532static void broxton_modeset_global_resources(struct drm_atomic_state *old_state)
f8437dd1 9533{
a821fc46 9534 struct drm_device *dev = old_state->dev;
f8437dd1 9535 struct drm_i915_private *dev_priv = dev->dev_private;
a821fc46 9536 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
f8437dd1
VK		 9537 int req_cdclk;
9538
9539 /* see the comment in valleyview_modeset_global_resources */
9540 if (WARN_ON(max_pixclk < 0))
9541 return;
9542
9543 req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
9544
9545 if (req_cdclk != dev_priv->cdclk_freq)
9546 broxton_set_cdclk(dev, req_cdclk);
9547}
9548
190f68c5
ACO		 9549static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9550 struct intel_crtc_state *crtc_state)
09b4ddf9 9551{
190f68c5 9552 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 9553 return -EINVAL;
716c2e55 9554
c7653199 9555 crtc->lowfreq_avail = false;
644cef34 9556
c8f7a0db 9557 return 0;
79e53945
JB		 9558}
9559
3760b59c
S		 9560static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9561 enum port port,
9562 struct intel_crtc_state *pipe_config)
9563{
9564 switch (port) {
9565 case PORT_A:
9566 pipe_config->ddi_pll_sel = SKL_DPLL0;
9567 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9568 break;
9569 case PORT_B:
9570 pipe_config->ddi_pll_sel = SKL_DPLL1;
9571 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9572 break;
9573 case PORT_C:
9574 pipe_config->ddi_pll_sel = SKL_DPLL2;
9575 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9576 break;
9577 default:
9578 DRM_ERROR("Incorrect port type\n");
9579 }
9580}
9581
96b7dfb7
S		 9582static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9583 enum port port,
5cec258b 9584 struct intel_crtc_state *pipe_config)
96b7dfb7 9585{
3148ade7 9586 u32 temp, dpll_ctl1;
96b7dfb7
S		 9587
9588 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9589 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9590
9591 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 9592 case SKL_DPLL0:
9593 /*
9594 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9595 * of the shared DPLL framework and thus needs to be read out
9596 * separately
9597 */
9598 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9599 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9600 break;
96b7dfb7
S		 9601 case SKL_DPLL1:
9602 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9603 break;
9604 case SKL_DPLL2:
9605 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9606 break;
9607 case SKL_DPLL3:
9608 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9609 break;
96b7dfb7
S		 9610 }
9611}
9612
7d2c8175
DL		 9613static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9614 enum port port,
5cec258b 9615 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 9616{
9617 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9618
9619 switch (pipe_config->ddi_pll_sel) {
9620 case PORT_CLK_SEL_WRPLL1:
9621 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9622 break;
9623 case PORT_CLK_SEL_WRPLL2:
9624 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9625 break;
9626 }
9627}
9628
26804afd 9629static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 9630 struct intel_crtc_state *pipe_config)
26804afd
DV		 9631{
9632 struct drm_device *dev = crtc->base.dev;
9633 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 9634 struct intel_shared_dpll *pll;
26804afd
DV		 9635 enum port port;
9636 uint32_t tmp;
9637
9638 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9639
9640 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9641
96b7dfb7
S		 9642 if (IS_SKYLAKE(dev))
9643 skylake_get_ddi_pll(dev_priv, port, pipe_config);
3760b59c
S		 9644 else if (IS_BROXTON(dev))
9645 bxt_get_ddi_pll(dev_priv, port, pipe_config);
96b7dfb7
S		 9646 else
9647 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 9648
d452c5b6
DV		 9649 if (pipe_config->shared_dpll >= 0) {
9650 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9651
9652 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9653 &pipe_config->dpll_hw_state));
9654 }
9655
26804afd
DV		 9656 /*
9657 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9658 * DDI E. So just check whether this pipe is wired to DDI E and whether
9659 * the PCH transcoder is on.
9660 */
ca370455
DL		 9661 if (INTEL_INFO(dev)->gen < 9 &&
9662 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 9663 pipe_config->has_pch_encoder = true;
9664
9665 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9666 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9667 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9668
9669 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9670 }
9671}
9672
0e8ffe1b 9673static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9674 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9675{
9676 struct drm_device *dev = crtc->base.dev;
9677 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 9678 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 9679 uint32_t tmp;
9680
f458ebbc 9681 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 9682 POWER_DOMAIN_PIPE(crtc->pipe)))
9683 return false;
9684
e143a21c 9685 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 9686 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9687
eccb140b
DV		 9688 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9689 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9690 enum pipe trans_edp_pipe;
9691 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9692 default:
9693 WARN(1, "unknown pipe linked to edp transcoder\n");
9694 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9695 case TRANS_DDI_EDP_INPUT_A_ON:
9696 trans_edp_pipe = PIPE_A;
9697 break;
9698 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9699 trans_edp_pipe = PIPE_B;
9700 break;
9701 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9702 trans_edp_pipe = PIPE_C;
9703 break;
9704 }
9705
9706 if (trans_edp_pipe == crtc->pipe)
9707 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9708 }
9709
f458ebbc 9710 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 9711 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 9712 return false;
9713
eccb140b 9714 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 9715 if (!(tmp & PIPECONF_ENABLE))
9716 return false;
9717
26804afd 9718 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 9719
1bd1bd80
DV		 9720 intel_get_pipe_timings(crtc, pipe_config);
9721
a1b2278e
CK		 9722 if (INTEL_INFO(dev)->gen >= 9) {
9723 skl_init_scalers(dev, crtc, pipe_config);
9724 }
9725
2fa2fe9a 9726 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
af99ceda
CK		 9727
9728 if (INTEL_INFO(dev)->gen >= 9) {
9729 pipe_config->scaler_state.scaler_id = -1;
9730 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9731 }
9732
bd2e244f 9733 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
ff6d9f55 9734 if (INTEL_INFO(dev)->gen == 9)
bd2e244f 9735 skylake_get_pfit_config(crtc, pipe_config);
ff6d9f55 9736 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 9737 ironlake_get_pfit_config(crtc, pipe_config);
ff6d9f55
JB		 9738 else
9739 MISSING_CASE(INTEL_INFO(dev)->gen);
bd2e244f 9740 }
88adfff1 9741
e59150dc
JB		 9742 if (IS_HASWELL(dev))
9743 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9744 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 9745
ebb69c95
CT		 9746 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9747 pipe_config->pixel_multiplier =
9748 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9749 } else {
9750 pipe_config->pixel_multiplier = 1;
9751 }
6c49f241 9752
0e8ffe1b
DV		 9753 return true;
9754}
9755
560b85bb
CW		 9756static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9757{
9758 struct drm_device *dev = crtc->dev;
9759 struct drm_i915_private *dev_priv = dev->dev_private;
9760 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 9761 uint32_t cntl = 0, size = 0;
560b85bb 9762
dc41c154 9763 if (base) {
3dd512fb
MR		 9764 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9765 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 9766 unsigned int stride = roundup_pow_of_two(width) * 4;
9767
9768 switch (stride) {
9769 default:
9770 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9771 width, stride);
9772 stride = 256;
9773 /* fallthrough */
9774 case 256:
9775 case 512:
9776 case 1024:
9777 case 2048:
9778 break;
4b0e333e
CW		 9779 }
9780
dc41c154
VS		 9781 cntl |= CURSOR_ENABLE |
9782 CURSOR_GAMMA_ENABLE |
9783 CURSOR_FORMAT_ARGB |
9784 CURSOR_STRIDE(stride);
9785
9786 size = (height << 12) | width;
4b0e333e 9787 }
560b85bb 9788
dc41c154
VS		 9789 if (intel_crtc->cursor_cntl != 0 &&
9790 (intel_crtc->cursor_base != base ||
9791 intel_crtc->cursor_size != size ||
9792 intel_crtc->cursor_cntl != cntl)) {
9793 /* On these chipsets we can only modify the base/size/stride
9794 * whilst the cursor is disabled.
9795 */
9796 I915_WRITE(_CURACNTR, 0);
4b0e333e 9797 POSTING_READ(_CURACNTR);
dc41c154 9798 intel_crtc->cursor_cntl = 0;
4b0e333e 9799 }
560b85bb 9800
99d1f387 9801 if (intel_crtc->cursor_base != base) {
9db4a9c7 9802 I915_WRITE(_CURABASE, base);
99d1f387
VS		 9803 intel_crtc->cursor_base = base;
9804 }
4726e0b0 9805
dc41c154
VS		 9806 if (intel_crtc->cursor_size != size) {
9807 I915_WRITE(CURSIZE, size);
9808 intel_crtc->cursor_size = size;
4b0e333e 9809 }
560b85bb 9810
4b0e333e 9811 if (intel_crtc->cursor_cntl != cntl) {
4b0e333e
CW		 9812 I915_WRITE(_CURACNTR, cntl);
9813 POSTING_READ(_CURACNTR);
4b0e333e 9814 intel_crtc->cursor_cntl = cntl;
560b85bb 9815 }
560b85bb
CW		 9816}
9817
560b85bb 9818static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 9819{
9820 struct drm_device *dev = crtc->dev;
9821 struct drm_i915_private *dev_priv = dev->dev_private;
9822 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9823 int pipe = intel_crtc->pipe;
4b0e333e
CW		 9824 uint32_t cntl;
9825
9826 cntl = 0;
9827 if (base) {
9828 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 9829 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 9830 case 64:
9831 cntl |= CURSOR_MODE_64_ARGB_AX;
9832 break;
9833 case 128:
9834 cntl |= CURSOR_MODE_128_ARGB_AX;
9835 break;
9836 case 256:
9837 cntl |= CURSOR_MODE_256_ARGB_AX;
9838 break;
9839 default:
3dd512fb 9840 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 9841 return;
65a21cd6 9842 }
4b0e333e 9843 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS		 9844
9845 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9846 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 9847 }
65a21cd6 9848
8e7d688b 9849 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 9850 cntl |= CURSOR_ROTATE_180;
9851
4b0e333e
CW		 9852 if (intel_crtc->cursor_cntl != cntl) {
9853 I915_WRITE(CURCNTR(pipe), cntl);
9854 POSTING_READ(CURCNTR(pipe));
9855 intel_crtc->cursor_cntl = cntl;
65a21cd6 9856 }
4b0e333e 9857
65a21cd6 9858 /* and commit changes on next vblank */
5efb3e28
VS		 9859 I915_WRITE(CURBASE(pipe), base);
9860 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 9861
9862 intel_crtc->cursor_base = base;
65a21cd6
JB		 9863}
9864
cda4b7d3 9865/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 9866static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9867 bool on)
cda4b7d3
CW		 9868{
9869 struct drm_device *dev = crtc->dev;
9870 struct drm_i915_private *dev_priv = dev->dev_private;
9871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9872 int pipe = intel_crtc->pipe;
3d7d6510
MR		 9873 int x = crtc->cursor_x;
9874 int y = crtc->cursor_y;
d6e4db15 9875 u32 base = 0, pos = 0;
cda4b7d3 9876
d6e4db15 9877 if (on)
cda4b7d3 9878 base = intel_crtc->cursor_addr;
cda4b7d3 9879
6e3c9717 9880 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 9881 base = 0;
9882
6e3c9717 9883 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 9884 base = 0;
9885
9886 if (x < 0) {
3dd512fb 9887 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
cda4b7d3
CW		 9888 base = 0;
9889
9890 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9891 x = -x;
9892 }
9893 pos |= x << CURSOR_X_SHIFT;
9894
9895 if (y < 0) {
3dd512fb 9896 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
cda4b7d3
CW		 9897 base = 0;
9898
9899 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9900 y = -y;
9901 }
9902 pos |= y << CURSOR_Y_SHIFT;
9903
4b0e333e 9904 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 9905 return;
9906
5efb3e28
VS		 9907 I915_WRITE(CURPOS(pipe), pos);
9908
4398ad45
VS		 9909 /* ILK+ do this automagically */
9910 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 9911 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
3dd512fb
MR		 9912 base += (intel_crtc->base.cursor->state->crtc_h *
9913 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
4398ad45
VS		 9914 }
9915
8ac54669 9916 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 9917 i845_update_cursor(crtc, base);
9918 else
9919 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 9920}
9921
dc41c154
VS		 9922static bool cursor_size_ok(struct drm_device *dev,
9923 uint32_t width, uint32_t height)
9924{
9925 if (width == 0 || height == 0)
9926 return false;
9927
9928 /*
9929 * 845g/865g are special in that they are only limited by
9930 * the width of their cursors, the height is arbitrary up to
9931 * the precision of the register. Everything else requires
9932 * square cursors, limited to a few power-of-two sizes.
9933 */
9934 if (IS_845G(dev) || IS_I865G(dev)) {
9935 if ((width & 63) != 0)
9936 return false;
9937
9938 if (width > (IS_845G(dev) ? 64 : 512))
9939 return false;
9940
9941 if (height > 1023)
9942 return false;
9943 } else {
9944 switch (width | height) {
9945 case 256:
9946 case 128:
9947 if (IS_GEN2(dev))
9948 return false;
9949 case 64:
9950 break;
9951 default:
9952 return false;
9953 }
9954 }
9955
9956 return true;
9957}
9958
79e53945 9959static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 9960 u16 *blue, uint32_t start, uint32_t size)
79e53945 9961{
7203425a 9962 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 9963 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 9964
7203425a 9965 for (i = start; i < end; i++) {
79e53945
JB		 9966 intel_crtc->lut_r[i] = red[i] >> 8;
9967 intel_crtc->lut_g[i] = green[i] >> 8;
9968 intel_crtc->lut_b[i] = blue[i] >> 8;
9969 }
9970
9971 intel_crtc_load_lut(crtc);
9972}
9973
79e53945
JB		 9974/* VESA 640x480x72Hz mode to set on the pipe */
9975static struct drm_display_mode load_detect_mode = {
9976 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9977 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9978};
9979
a8bb6818
DV		 9980struct drm_framebuffer *
9981__intel_framebuffer_create(struct drm_device *dev,
9982 struct drm_mode_fb_cmd2 *mode_cmd,
9983 struct drm_i915_gem_object *obj)
d2dff872
CW		 9984{
9985 struct intel_framebuffer *intel_fb;
9986 int ret;
9987
9988 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9989 if (!intel_fb) {
6ccb81f2 9990 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 9991 return ERR_PTR(-ENOMEM);
9992 }
9993
9994 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 9995 if (ret)
9996 goto err;
d2dff872
CW		 9997
9998 return &intel_fb->base;
dd4916c5 9999err:
6ccb81f2 10000 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 10001 kfree(intel_fb);
10002
10003 return ERR_PTR(ret);
d2dff872
CW		 10004}
10005
b5ea642a 10006static struct drm_framebuffer *
a8bb6818
DV		 10007intel_framebuffer_create(struct drm_device *dev,
10008 struct drm_mode_fb_cmd2 *mode_cmd,
10009 struct drm_i915_gem_object *obj)
10010{
10011 struct drm_framebuffer *fb;
10012 int ret;
10013
10014 ret = i915_mutex_lock_interruptible(dev);
10015 if (ret)
10016 return ERR_PTR(ret);
10017 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10018 mutex_unlock(&dev->struct_mutex);
10019
10020 return fb;
10021}
10022
d2dff872
CW		 10023static u32
10024intel_framebuffer_pitch_for_width(int width, int bpp)
10025{
10026 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10027 return ALIGN(pitch, 64);
10028}
10029
10030static u32
10031intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10032{
10033 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 10034 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 10035}
10036
10037static struct drm_framebuffer *
10038intel_framebuffer_create_for_mode(struct drm_device *dev,
10039 struct drm_display_mode *mode,
10040 int depth, int bpp)
10041{
10042 struct drm_i915_gem_object *obj;
0fed39bd 10043 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 10044
10045 obj = i915_gem_alloc_object(dev,
10046 intel_framebuffer_size_for_mode(mode, bpp));
10047 if (obj == NULL)
10048 return ERR_PTR(-ENOMEM);
10049
10050 mode_cmd.width = mode->hdisplay;
10051 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 10052 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10053 bpp);
5ca0c34a 10054 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 10055
10056 return intel_framebuffer_create(dev, &mode_cmd, obj);
10057}
10058
10059static struct drm_framebuffer *
10060mode_fits_in_fbdev(struct drm_device *dev,
10061 struct drm_display_mode *mode)
10062{
4520f53a 10063#ifdef CONFIG_DRM_I915_FBDEV
d2dff872
CW		 10064 struct drm_i915_private *dev_priv = dev->dev_private;
10065 struct drm_i915_gem_object *obj;
10066 struct drm_framebuffer *fb;
10067
4c0e5528 10068 if (!dev_priv->fbdev)
d2dff872
CW		 10069 return NULL;
10070
4c0e5528 10071 if (!dev_priv->fbdev->fb)
d2dff872
CW		 10072 return NULL;
10073
4c0e5528
DV		 10074 obj = dev_priv->fbdev->fb->obj;
10075 BUG_ON(!obj);
10076
8bcd4553 10077 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 10078 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10079 fb->bits_per_pixel))
d2dff872
CW		 10080 return NULL;
10081
01f2c773 10082 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 10083 return NULL;
10084
10085 return fb;
4520f53a
DV		 10086#else
10087 return NULL;
10088#endif
d2dff872
CW		 10089}
10090
d3a40d1b
ACO		 10091static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10092 struct drm_crtc *crtc,
10093 struct drm_display_mode *mode,
10094 struct drm_framebuffer *fb,
10095 int x, int y)
10096{
10097 struct drm_plane_state *plane_state;
10098 int hdisplay, vdisplay;
10099 int ret;
10100
10101 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10102 if (IS_ERR(plane_state))
10103 return PTR_ERR(plane_state);
10104
10105 if (mode)
10106 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10107 else
10108 hdisplay = vdisplay = 0;
10109
10110 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10111 if (ret)
10112 return ret;
10113 drm_atomic_set_fb_for_plane(plane_state, fb);
10114 plane_state->crtc_x = 0;
10115 plane_state->crtc_y = 0;
10116 plane_state->crtc_w = hdisplay;
10117 plane_state->crtc_h = vdisplay;
10118 plane_state->src_x = x << 16;
10119 plane_state->src_y = y << 16;
10120 plane_state->src_w = hdisplay << 16;
10121 plane_state->src_h = vdisplay << 16;
10122
10123 return 0;
10124}
10125
d2434ab7 10126bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 10127 struct drm_display_mode *mode,
51fd371b
RC		 10128 struct intel_load_detect_pipe *old,
10129 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 10130{
10131 struct intel_crtc *intel_crtc;
d2434ab7
DV		 10132 struct intel_encoder *intel_encoder =
10133 intel_attached_encoder(connector);
79e53945 10134 struct drm_crtc *possible_crtc;
4ef69c7a 10135 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 10136 struct drm_crtc *crtc = NULL;
10137 struct drm_device *dev = encoder->dev;
94352cf9 10138 struct drm_framebuffer *fb;
51fd371b 10139 struct drm_mode_config *config = &dev->mode_config;
83a57153 10140 struct drm_atomic_state *state = NULL;
944b0c76 10141 struct drm_connector_state *connector_state;
4be07317 10142 struct intel_crtc_state *crtc_state;
51fd371b 10143 int ret, i = -1;
79e53945 10144
d2dff872 10145 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10146 connector->base.id, connector->name,
8e329a03 10147 encoder->base.id, encoder->name);
d2dff872 10148
51fd371b
RC		 10149retry:
10150 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10151 if (ret)
10152 goto fail_unlock;
6e9f798d 10153
79e53945
JB		 10154 /*
10155 * Algorithm gets a little messy:
7a5e4805 10156 *
79e53945
JB		 10157 * - if the connector already has an assigned crtc, use it (but make
10158 * sure it's on first)
7a5e4805 10159 *
79e53945
JB		 10160 * - try to find the first unused crtc that can drive this connector,
10161 * and use that if we find one
79e53945
JB		 10162 */
10163
10164 /* See if we already have a CRTC for this connector */
10165 if (encoder->crtc) {
10166 crtc = encoder->crtc;
8261b191 10167
51fd371b 10168 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de
DV		 10169 if (ret)
10170 goto fail_unlock;
10171 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b
RC		 10172 if (ret)
10173 goto fail_unlock;
7b24056b 10174
24218aac 10175 old->dpms_mode = connector->dpms;
8261b191
CW		 10176 old->load_detect_temp = false;
10177
10178 /* Make sure the crtc and connector are running */
24218aac
DV		 10179 if (connector->dpms != DRM_MODE_DPMS_ON)
10180 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 10181
7173188d 10182 return true;
79e53945
JB		 10183 }
10184
10185 /* Find an unused one (if possible) */
70e1e0ec 10186 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 10187 i++;
10188 if (!(encoder->possible_crtcs & (1 << i)))
10189 continue;
83d65738 10190 if (possible_crtc->state->enable)
a459249c
VS		 10191 continue;
10192 /* This can occur when applying the pipe A quirk on resume. */
10193 if (to_intel_crtc(possible_crtc)->new_enabled)
10194 continue;
10195
10196 crtc = possible_crtc;
10197 break;
79e53945
JB		 10198 }
10199
10200 /*
10201 * If we didn't find an unused CRTC, don't use any.
10202 */
10203 if (!crtc) {
7173188d 10204 DRM_DEBUG_KMS("no pipe available for load-detect\n");
51fd371b 10205 goto fail_unlock;
79e53945
JB		 10206 }
10207
51fd371b
RC		 10208 ret = drm_modeset_lock(&crtc->mutex, ctx);
10209 if (ret)
4d02e2de
DV		 10210 goto fail_unlock;
10211 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10212 if (ret)
51fd371b 10213 goto fail_unlock;
fc303101
DV		 10214 intel_encoder->new_crtc = to_intel_crtc(crtc);
10215 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 10216
10217 intel_crtc = to_intel_crtc(crtc);
412b61d8 10218 intel_crtc->new_enabled = true;
24218aac 10219 old->dpms_mode = connector->dpms;
8261b191 10220 old->load_detect_temp = true;
d2dff872 10221 old->release_fb = NULL;
79e53945 10222
83a57153
ACO		 10223 state = drm_atomic_state_alloc(dev);
10224 if (!state)
10225 return false;
10226
10227 state->acquire_ctx = ctx;
10228
944b0c76
ACO		 10229 connector_state = drm_atomic_get_connector_state(state, connector);
10230 if (IS_ERR(connector_state)) {
10231 ret = PTR_ERR(connector_state);
10232 goto fail;
10233 }
10234
10235 connector_state->crtc = crtc;
10236 connector_state->best_encoder = &intel_encoder->base;
10237
4be07317
ACO		 10238 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10239 if (IS_ERR(crtc_state)) {
10240 ret = PTR_ERR(crtc_state);
10241 goto fail;
10242 }
10243
49d6fa21 10244 crtc_state->base.active = crtc_state->base.enable = true;
4be07317 10245
6492711d
CW		 10246 if (!mode)
10247 mode = &load_detect_mode;
79e53945 10248
d2dff872
CW		 10249 /* We need a framebuffer large enough to accommodate all accesses
10250 * that the plane may generate whilst we perform load detection.
10251 * We can not rely on the fbcon either being present (we get called
10252 * during its initialisation to detect all boot displays, or it may
10253 * not even exist) or that it is large enough to satisfy the
10254 * requested mode.
10255 */
94352cf9
DV		 10256 fb = mode_fits_in_fbdev(dev, mode);
10257 if (fb == NULL) {
d2dff872 10258 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 10259 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10260 old->release_fb = fb;
d2dff872
CW		 10261 } else
10262 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 10263 if (IS_ERR(fb)) {
d2dff872 10264 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 10265 goto fail;
79e53945 10266 }
79e53945 10267
d3a40d1b
ACO		 10268 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10269 if (ret)
10270 goto fail;
10271
8c7b5ccb
ACO		 10272 drm_mode_copy(&crtc_state->base.mode, mode);
10273
10274 if (intel_set_mode(crtc, state)) {
6492711d 10275 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 10276 if (old->release_fb)
10277 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 10278 goto fail;
79e53945 10279 }
9128b040 10280 crtc->primary->crtc = crtc;
7173188d 10281
79e53945 10282 /* let the connector get through one full cycle before testing */
9d0498a2 10283 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 10284 return true;
412b61d8
VS		 10285
10286 fail:
83d65738 10287 intel_crtc->new_enabled = crtc->state->enable;
51fd371b 10288fail_unlock:
e5d958ef
ACO		 10289 drm_atomic_state_free(state);
10290 state = NULL;
83a57153 10291
51fd371b
RC		 10292 if (ret == -EDEADLK) {
10293 drm_modeset_backoff(ctx);
10294 goto retry;
10295 }
10296
412b61d8 10297 return false;
79e53945
JB		 10298}
10299
d2434ab7 10300void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 10301 struct intel_load_detect_pipe *old,
10302 struct drm_modeset_acquire_ctx *ctx)
79e53945 10303{
83a57153 10304 struct drm_device *dev = connector->dev;
d2434ab7
DV		 10305 struct intel_encoder *intel_encoder =
10306 intel_attached_encoder(connector);
4ef69c7a 10307 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 10308 struct drm_crtc *crtc = encoder->crtc;
412b61d8 10309 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 10310 struct drm_atomic_state *state;
944b0c76 10311 struct drm_connector_state *connector_state;
4be07317 10312 struct intel_crtc_state *crtc_state;
d3a40d1b 10313 int ret;
79e53945 10314
d2dff872 10315 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10316 connector->base.id, connector->name,
8e329a03 10317 encoder->base.id, encoder->name);
d2dff872 10318
8261b191 10319 if (old->load_detect_temp) {
83a57153 10320 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 10321 if (!state)
10322 goto fail;
83a57153
ACO		 10323
10324 state->acquire_ctx = ctx;
10325
944b0c76
ACO		 10326 connector_state = drm_atomic_get_connector_state(state, connector);
10327 if (IS_ERR(connector_state))
10328 goto fail;
10329
4be07317
ACO		 10330 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10331 if (IS_ERR(crtc_state))
10332 goto fail;
10333
fc303101
DV		 10334 to_intel_connector(connector)->new_encoder = NULL;
10335 intel_encoder->new_crtc = NULL;
412b61d8 10336 intel_crtc->new_enabled = false;
944b0c76
ACO		 10337
10338 connector_state->best_encoder = NULL;
10339 connector_state->crtc = NULL;
10340
49d6fa21 10341 crtc_state->base.enable = crtc_state->base.active = false;
4be07317 10342
d3a40d1b
ACO		 10343 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10344 0, 0);
10345 if (ret)
10346 goto fail;
10347
2bfb4627
ACO		 10348 ret = intel_set_mode(crtc, state);
10349 if (ret)
10350 goto fail;
d2dff872 10351
36206361
DV		 10352 if (old->release_fb) {
10353 drm_framebuffer_unregister_private(old->release_fb);
10354 drm_framebuffer_unreference(old->release_fb);
10355 }
d2dff872 10356
0622a53c 10357 return;
79e53945
JB		 10358 }
10359
c751ce4f 10360 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 10361 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10362 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 10363
10364 return;
10365fail:
10366 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10367 drm_atomic_state_free(state);
79e53945
JB		 10368}
10369
da4a1efa 10370static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 10371 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 10372{
10373 struct drm_i915_private *dev_priv = dev->dev_private;
10374 u32 dpll = pipe_config->dpll_hw_state.dpll;
10375
10376 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 10377 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 10378 else if (HAS_PCH_SPLIT(dev))
10379 return 120000;
10380 else if (!IS_GEN2(dev))
10381 return 96000;
10382 else
10383 return 48000;
10384}
10385
79e53945 10386/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 10387static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 10388 struct intel_crtc_state *pipe_config)
79e53945 10389{
f1f644dc 10390 struct drm_device *dev = crtc->base.dev;
79e53945 10391 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 10392 int pipe = pipe_config->cpu_transcoder;
293623f7 10393 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 10394 u32 fp;
10395 intel_clock_t clock;
da4a1efa 10396 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 10397
10398 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 10399 fp = pipe_config->dpll_hw_state.fp0;
79e53945 10400 else
293623f7 10401 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 10402
10403 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 10404 if (IS_PINEVIEW(dev)) {
10405 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10406 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 10407 } else {
10408 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10409 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10410 }
10411
a6c45cf0 10412 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 10413 if (IS_PINEVIEW(dev))
10414 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10415 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 10416 else
10417 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 10418 DPLL_FPA01_P1_POST_DIV_SHIFT);
10419
10420 switch (dpll & DPLL_MODE_MASK) {
10421 case DPLLB_MODE_DAC_SERIAL:
10422 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10423 5 : 10;
10424 break;
10425 case DPLLB_MODE_LVDS:
10426 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10427 7 : 14;
10428 break;
10429 default:
28c97730 10430 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 10431 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 10432 return;
79e53945
JB		 10433 }
10434
ac58c3f0 10435 if (IS_PINEVIEW(dev))
da4a1efa 10436 pineview_clock(refclk, &clock);
ac58c3f0 10437 else
da4a1efa 10438 i9xx_clock(refclk, &clock);
79e53945 10439 } else {
0fb58223 10440 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 10441 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 10442
10443 if (is_lvds) {
10444 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10445 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 10446
10447 if (lvds & LVDS_CLKB_POWER_UP)
10448 clock.p2 = 7;
10449 else
10450 clock.p2 = 14;
79e53945
JB		 10451 } else {
10452 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10453 clock.p1 = 2;
10454 else {
10455 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10456 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10457 }
10458 if (dpll & PLL_P2_DIVIDE_BY_4)
10459 clock.p2 = 4;
10460 else
10461 clock.p2 = 2;
79e53945 10462 }
da4a1efa
VS		 10463
10464 i9xx_clock(refclk, &clock);
79e53945
JB		 10465 }
10466
18442d08
VS		 10467 /*
10468 * This value includes pixel_multiplier. We will use
241bfc38 10469 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 10470 * encoder's get_config() function.
10471 */
10472 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 10473}
10474
6878da05
VS		 10475int intel_dotclock_calculate(int link_freq,
10476 const struct intel_link_m_n *m_n)
f1f644dc 10477{
f1f644dc
JB		 10478 /*
10479 * The calculation for the data clock is:
1041a02f 10480 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 10481 * But we want to avoid losing precison if possible, so:
1041a02f 10482 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 10483 *
10484 * and the link clock is simpler:
1041a02f 10485 * link_clock = (m * link_clock) / n
f1f644dc
JB		 10486 */
10487
6878da05
VS		 10488 if (!m_n->link_n)
10489 return 0;
f1f644dc 10490
6878da05
VS		 10491 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10492}
f1f644dc 10493
18442d08 10494static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 10495 struct intel_crtc_state *pipe_config)
6878da05
VS		 10496{
10497 struct drm_device *dev = crtc->base.dev;
79e53945 10498
18442d08
VS		 10499 /* read out port_clock from the DPLL */
10500 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 10501
f1f644dc 10502 /*
18442d08 10503 * This value does not include pixel_multiplier.
241bfc38 10504 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 10505 * agree once we know their relationship in the encoder's
10506 * get_config() function.
79e53945 10507 */
2d112de7 10508 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 10509 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10510 &pipe_config->fdi_m_n);
79e53945
JB		 10511}
10512
10513/** Returns the currently programmed mode of the given pipe. */
10514struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10515 struct drm_crtc *crtc)
10516{
548f245b 10517 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 10518 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 10519 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 10520 struct drm_display_mode *mode;
5cec258b 10521 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 10522 int htot = I915_READ(HTOTAL(cpu_transcoder));
10523 int hsync = I915_READ(HSYNC(cpu_transcoder));
10524 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10525 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 10526 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 10527
10528 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10529 if (!mode)
10530 return NULL;
10531
f1f644dc
JB		 10532 /*
10533 * Construct a pipe_config sufficient for getting the clock info
10534 * back out of crtc_clock_get.
10535 *
10536 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10537 * to use a real value here instead.
10538 */
293623f7 10539 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 10540 pipe_config.pixel_multiplier = 1;
293623f7
VS		 10541 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10542 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10543 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 10544 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10545
773ae034 10546 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 10547 mode->hdisplay = (htot & 0xffff) + 1;
10548 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10549 mode->hsync_start = (hsync & 0xffff) + 1;
10550 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10551 mode->vdisplay = (vtot & 0xffff) + 1;
10552 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10553 mode->vsync_start = (vsync & 0xffff) + 1;
10554 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10555
10556 drm_mode_set_name(mode);
79e53945
JB		 10557
10558 return mode;
10559}
10560
652c393a
JB		 10561static void intel_decrease_pllclock(struct drm_crtc *crtc)
10562{
10563 struct drm_device *dev = crtc->dev;
fbee40df 10564 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10565 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 10566
baff296c 10567 if (!HAS_GMCH_DISPLAY(dev))
652c393a
JB		 10568 return;
10569
10570 if (!dev_priv->lvds_downclock_avail)
10571 return;
10572
10573 /*
10574 * Since this is called by a timer, we should never get here in
10575 * the manual case.
10576 */
10577 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 10578 int pipe = intel_crtc->pipe;
10579 int dpll_reg = DPLL(pipe);
10580 int dpll;
f6e5b160 10581
44d98a61 10582 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 10583
8ac5a6d5 10584 assert_panel_unlocked(dev_priv, pipe);
652c393a 10585
dc257cf1 10586 dpll = I915_READ(dpll_reg);
652c393a
JB		 10587 dpll |= DISPLAY_RATE_SELECT_FPA1;
10588 I915_WRITE(dpll_reg, dpll);
9d0498a2 10589 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 10590 dpll = I915_READ(dpll_reg);
10591 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 10592 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 10593 }
10594
10595}
10596
f047e395
CW		 10597void intel_mark_busy(struct drm_device *dev)
10598{
c67a470b
PZ		 10599 struct drm_i915_private *dev_priv = dev->dev_private;
10600
f62a0076
CW		 10601 if (dev_priv->mm.busy)
10602 return;
10603
43694d69 10604 intel_runtime_pm_get(dev_priv);
c67a470b 10605 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 10606 if (INTEL_INFO(dev)->gen >= 6)
10607 gen6_rps_busy(dev_priv);
f62a0076 10608 dev_priv->mm.busy = true;
f047e395
CW		 10609}
10610
10611void intel_mark_idle(struct drm_device *dev)
652c393a 10612{
c67a470b 10613 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10614 struct drm_crtc *crtc;
652c393a 10615
f62a0076
CW		 10616 if (!dev_priv->mm.busy)
10617 return;
10618
10619 dev_priv->mm.busy = false;
10620
70e1e0ec 10621 for_each_crtc(dev, crtc) {
f4510a27 10622 if (!crtc->primary->fb)
652c393a
JB		 10623 continue;
10624
725a5b54 10625 intel_decrease_pllclock(crtc);
652c393a 10626 }
b29c19b6 10627
3d13ef2e 10628 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 10629 gen6_rps_idle(dev->dev_private);
bb4cdd53 10630
43694d69 10631 intel_runtime_pm_put(dev_priv);
652c393a
JB		 10632}
10633
79e53945
JB		 10634static void intel_crtc_destroy(struct drm_crtc *crtc)
10635{
10636 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 10637 struct drm_device *dev = crtc->dev;
10638 struct intel_unpin_work *work;
67e77c5a 10639
5e2d7afc 10640 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 10641 work = intel_crtc->unpin_work;
10642 intel_crtc->unpin_work = NULL;
5e2d7afc 10643 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 10644
10645 if (work) {
10646 cancel_work_sync(&work->work);
10647 kfree(work);
10648 }
79e53945
JB		 10649
10650 drm_crtc_cleanup(crtc);
67e77c5a 10651
79e53945
JB		 10652 kfree(intel_crtc);
10653}
10654
6b95a207
KH		 10655static void intel_unpin_work_fn(struct work_struct *__work)
10656{
10657 struct intel_unpin_work *work =
10658 container_of(__work, struct intel_unpin_work, work);
b4a98e57 10659 struct drm_device *dev = work->crtc->dev;
f99d7069 10660 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
6b95a207 10661
b4a98e57 10662 mutex_lock(&dev->struct_mutex);
82bc3b2d 10663 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
05394f39 10664 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 10665
7ff0ebcc 10666 intel_fbc_update(dev);
f06cc1b9
JH		 10667
10668 if (work->flip_queued_req)
146d84f0 10669 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 10670 mutex_unlock(&dev->struct_mutex);
10671
f99d7069 10672 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
89ed88ba 10673 drm_framebuffer_unreference(work->old_fb);
f99d7069 10674
b4a98e57
CW		 10675 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10676 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10677
6b95a207
KH		 10678 kfree(work);
10679}
10680
1afe3e9d 10681static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 10682 struct drm_crtc *crtc)
6b95a207 10683{
6b95a207
KH		 10684 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10685 struct intel_unpin_work *work;
6b95a207
KH		 10686 unsigned long flags;
10687
10688 /* Ignore early vblank irqs */
10689 if (intel_crtc == NULL)
10690 return;
10691
f326038a
DV		 10692 /*
10693 * This is called both by irq handlers and the reset code (to complete
10694 * lost pageflips) so needs the full irqsave spinlocks.
10695 */
6b95a207
KH		 10696 spin_lock_irqsave(&dev->event_lock, flags);
10697 work = intel_crtc->unpin_work;
e7d841ca
CW		 10698
10699 /* Ensure we don't miss a work->pending update ... */
10700 smp_rmb();
10701
10702 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 10703 spin_unlock_irqrestore(&dev->event_lock, flags);
10704 return;
10705 }
10706
d6bbafa1 10707 page_flip_completed(intel_crtc);
0af7e4df 10708
6b95a207 10709 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 10710}
10711
1afe3e9d
JB		 10712void intel_finish_page_flip(struct drm_device *dev, int pipe)
10713{
fbee40df 10714 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10715 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10716
49b14a5c 10717 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10718}
10719
10720void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10721{
fbee40df 10722 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10723 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10724
49b14a5c 10725 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10726}
10727
75f7f3ec
VS		 10728/* Is 'a' after or equal to 'b'? */
10729static bool g4x_flip_count_after_eq(u32 a, u32 b)
10730{
10731 return !((a - b) & 0x80000000);
10732}
10733
10734static bool page_flip_finished(struct intel_crtc *crtc)
10735{
10736 struct drm_device *dev = crtc->base.dev;
10737 struct drm_i915_private *dev_priv = dev->dev_private;
10738
bdfa7542
VS		 10739 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10740 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10741 return true;
10742
75f7f3ec
VS		 10743 /*
10744 * The relevant registers doen't exist on pre-ctg.
10745 * As the flip done interrupt doesn't trigger for mmio
10746 * flips on gmch platforms, a flip count check isn't
10747 * really needed there. But since ctg has the registers,
10748 * include it in the check anyway.
10749 */
10750 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10751 return true;
10752
10753 /*
10754 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10755 * used the same base address. In that case the mmio flip might
10756 * have completed, but the CS hasn't even executed the flip yet.
10757 *
10758 * A flip count check isn't enough as the CS might have updated
10759 * the base address just after start of vblank, but before we
10760 * managed to process the interrupt. This means we'd complete the
10761 * CS flip too soon.
10762 *
10763 * Combining both checks should get us a good enough result. It may
10764 * still happen that the CS flip has been executed, but has not
10765 * yet actually completed. But in case the base address is the same
10766 * anyway, we don't really care.
10767 */
10768 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10769 crtc->unpin_work->gtt_offset &&
10770 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10771 crtc->unpin_work->flip_count);
10772}
10773
6b95a207
KH		 10774void intel_prepare_page_flip(struct drm_device *dev, int plane)
10775{
fbee40df 10776 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 10777 struct intel_crtc *intel_crtc =
10778 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10779 unsigned long flags;
10780
f326038a
DV		 10781
10782 /*
10783 * This is called both by irq handlers and the reset code (to complete
10784 * lost pageflips) so needs the full irqsave spinlocks.
10785 *
10786 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 10787 * generate a page-flip completion irq, i.e. every modeset
10788 * is also accompanied by a spurious intel_prepare_page_flip().
10789 */
6b95a207 10790 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 10791 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 10792 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 10793 spin_unlock_irqrestore(&dev->event_lock, flags);
10794}
10795
eba905b2 10796static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW		 10797{
10798 /* Ensure that the work item is consistent when activating it ... */
10799 smp_wmb();
10800 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10801 /* and that it is marked active as soon as the irq could fire. */
10802 smp_wmb();
10803}
10804
8c9f3aaf
JB		 10805static int intel_gen2_queue_flip(struct drm_device *dev,
10806 struct drm_crtc *crtc,
10807 struct drm_framebuffer *fb,
ed8d1975 10808 struct drm_i915_gem_object *obj,
a4872ba6 10809 struct intel_engine_cs *ring,
ed8d1975 10810 uint32_t flags)
8c9f3aaf 10811{
8c9f3aaf 10812 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10813 u32 flip_mask;
10814 int ret;
10815
6d90c952 10816 ret = intel_ring_begin(ring, 6);
8c9f3aaf 10817 if (ret)
4fa62c89 10818 return ret;
8c9f3aaf
JB		 10819
10820 /* Can't queue multiple flips, so wait for the previous
10821 * one to finish before executing the next.
10822 */
10823 if (intel_crtc->plane)
10824 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10825 else
10826 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10827 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10828 intel_ring_emit(ring, MI_NOOP);
10829 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10830 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10831 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10832 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 10833 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 10834
10835 intel_mark_page_flip_active(intel_crtc);
09246732 10836 __intel_ring_advance(ring);
83d4092b 10837 return 0;
8c9f3aaf
JB		 10838}
10839
10840static int intel_gen3_queue_flip(struct drm_device *dev,
10841 struct drm_crtc *crtc,
10842 struct drm_framebuffer *fb,
ed8d1975 10843 struct drm_i915_gem_object *obj,
a4872ba6 10844 struct intel_engine_cs *ring,
ed8d1975 10845 uint32_t flags)
8c9f3aaf 10846{
8c9f3aaf 10847 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10848 u32 flip_mask;
10849 int ret;
10850
6d90c952 10851 ret = intel_ring_begin(ring, 6);
8c9f3aaf 10852 if (ret)
4fa62c89 10853 return ret;
8c9f3aaf
JB		 10854
10855 if (intel_crtc->plane)
10856 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10857 else
10858 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10859 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10860 intel_ring_emit(ring, MI_NOOP);
10861 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10862 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10863 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10864 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 10865 intel_ring_emit(ring, MI_NOOP);
10866
e7d841ca 10867 intel_mark_page_flip_active(intel_crtc);
09246732 10868 __intel_ring_advance(ring);
83d4092b 10869 return 0;
8c9f3aaf
JB		 10870}
10871
10872static int intel_gen4_queue_flip(struct drm_device *dev,
10873 struct drm_crtc *crtc,
10874 struct drm_framebuffer *fb,
ed8d1975 10875 struct drm_i915_gem_object *obj,
a4872ba6 10876 struct intel_engine_cs *ring,
ed8d1975 10877 uint32_t flags)
8c9f3aaf
JB		 10878{
10879 struct drm_i915_private *dev_priv = dev->dev_private;
10880 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10881 uint32_t pf, pipesrc;
10882 int ret;
10883
6d90c952 10884 ret = intel_ring_begin(ring, 4);
8c9f3aaf 10885 if (ret)
4fa62c89 10886 return ret;
8c9f3aaf
JB		 10887
10888 /* i965+ uses the linear or tiled offsets from the
10889 * Display Registers (which do not change across a page-flip)
10890 * so we need only reprogram the base address.
10891 */
6d90c952
DV		 10892 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10893 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10894 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10895 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 10896 obj->tiling_mode);
8c9f3aaf
JB		 10897
10898 /* XXX Enabling the panel-fitter across page-flip is so far
10899 * untested on non-native modes, so ignore it for now.
10900 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10901 */
10902 pf = 0;
10903 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10904 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10905
10906 intel_mark_page_flip_active(intel_crtc);
09246732 10907 __intel_ring_advance(ring);
83d4092b 10908 return 0;
8c9f3aaf
JB		 10909}
10910
10911static int intel_gen6_queue_flip(struct drm_device *dev,
10912 struct drm_crtc *crtc,
10913 struct drm_framebuffer *fb,
ed8d1975 10914 struct drm_i915_gem_object *obj,
a4872ba6 10915 struct intel_engine_cs *ring,
ed8d1975 10916 uint32_t flags)
8c9f3aaf
JB		 10917{
10918 struct drm_i915_private *dev_priv = dev->dev_private;
10919 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10920 uint32_t pf, pipesrc;
10921 int ret;
10922
6d90c952 10923 ret = intel_ring_begin(ring, 4);
8c9f3aaf 10924 if (ret)
4fa62c89 10925 return ret;
8c9f3aaf 10926
6d90c952
DV		 10927 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10928 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10929 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 10930 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 10931
dc257cf1
DV		 10932 /* Contrary to the suggestions in the documentation,
10933 * "Enable Panel Fitter" does not seem to be required when page
10934 * flipping with a non-native mode, and worse causes a normal
10935 * modeset to fail.
10936 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10937 */
10938 pf = 0;
8c9f3aaf 10939 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10940 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10941
10942 intel_mark_page_flip_active(intel_crtc);
09246732 10943 __intel_ring_advance(ring);
83d4092b 10944 return 0;
8c9f3aaf
JB		 10945}
10946
7c9017e5
JB		 10947static int intel_gen7_queue_flip(struct drm_device *dev,
10948 struct drm_crtc *crtc,
10949 struct drm_framebuffer *fb,
ed8d1975 10950 struct drm_i915_gem_object *obj,
a4872ba6 10951 struct intel_engine_cs *ring,
ed8d1975 10952 uint32_t flags)
7c9017e5 10953{
7c9017e5 10954 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 10955 uint32_t plane_bit = 0;
ffe74d75
CW		 10956 int len, ret;
10957
eba905b2 10958 switch (intel_crtc->plane) {
cb05d8de
DV		 10959 case PLANE_A:
10960 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10961 break;
10962 case PLANE_B:
10963 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10964 break;
10965 case PLANE_C:
10966 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10967 break;
10968 default:
10969 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 10970 return -ENODEV;
cb05d8de
DV		 10971 }
10972
ffe74d75 10973 len = 4;
f476828a 10974 if (ring->id == RCS) {
ffe74d75 10975 len += 6;
f476828a
DL		 10976 /*
10977 * On Gen 8, SRM is now taking an extra dword to accommodate
10978 * 48bits addresses, and we need a NOOP for the batch size to
10979 * stay even.
10980 */
10981 if (IS_GEN8(dev))
10982 len += 2;
10983 }
ffe74d75 10984
f66fab8e
VS		 10985 /*
10986 * BSpec MI_DISPLAY_FLIP for IVB:
10987 * "The full packet must be contained within the same cache line."
10988 *
10989 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10990 * cacheline, if we ever start emitting more commands before
10991 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10992 * then do the cacheline alignment, and finally emit the
10993 * MI_DISPLAY_FLIP.
10994 */
10995 ret = intel_ring_cacheline_align(ring);
10996 if (ret)
4fa62c89 10997 return ret;
f66fab8e 10998
ffe74d75 10999 ret = intel_ring_begin(ring, len);
7c9017e5 11000 if (ret)
4fa62c89 11001 return ret;
7c9017e5 11002
ffe74d75
CW		 11003 /* Unmask the flip-done completion message. Note that the bspec says that
11004 * we should do this for both the BCS and RCS, and that we must not unmask
11005 * more than one flip event at any time (or ensure that one flip message
11006 * can be sent by waiting for flip-done prior to queueing new flips).
11007 * Experimentation says that BCS works despite DERRMR masking all
11008 * flip-done completion events and that unmasking all planes at once
11009 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11010 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11011 */
11012 if (ring->id == RCS) {
11013 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11014 intel_ring_emit(ring, DERRMR);
11015 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11016 DERRMR_PIPEB_PRI_FLIP_DONE |
11017 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a
DL		 11018 if (IS_GEN8(dev))
11019 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11020 MI_SRM_LRM_GLOBAL_GTT);
11021 else
11022 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11023 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 11024 intel_ring_emit(ring, DERRMR);
11025 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 11026 if (IS_GEN8(dev)) {
11027 intel_ring_emit(ring, 0);
11028 intel_ring_emit(ring, MI_NOOP);
11029 }
ffe74d75
CW		 11030 }
11031
cb05d8de 11032 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 11033 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 11034 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 11035 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 11036
11037 intel_mark_page_flip_active(intel_crtc);
09246732 11038 __intel_ring_advance(ring);
83d4092b 11039 return 0;
7c9017e5
JB		 11040}
11041
84c33a64
SG		 11042static bool use_mmio_flip(struct intel_engine_cs *ring,
11043 struct drm_i915_gem_object *obj)
11044{
11045 /*
11046 * This is not being used for older platforms, because
11047 * non-availability of flip done interrupt forces us to use
11048 * CS flips. Older platforms derive flip done using some clever
11049 * tricks involving the flip_pending status bits and vblank irqs.
11050 * So using MMIO flips there would disrupt this mechanism.
11051 */
11052
8e09bf83
CW		 11053 if (ring == NULL)
11054 return true;
11055
84c33a64
SG		 11056 if (INTEL_INFO(ring->dev)->gen < 5)
11057 return false;
11058
11059 if (i915.use_mmio_flip < 0)
11060 return false;
11061 else if (i915.use_mmio_flip > 0)
11062 return true;
14bf993e
OM		 11063 else if (i915.enable_execlists)
11064 return true;
84c33a64 11065 else
b4716185 11066 return ring != i915_gem_request_get_ring(obj->last_write_req);
84c33a64
SG		 11067}
11068
ff944564
DL		 11069static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11070{
11071 struct drm_device *dev = intel_crtc->base.dev;
11072 struct drm_i915_private *dev_priv = dev->dev_private;
11073 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
ff944564
DL		 11074 const enum pipe pipe = intel_crtc->pipe;
11075 u32 ctl, stride;
11076
11077 ctl = I915_READ(PLANE_CTL(pipe, 0));
11078 ctl &= ~PLANE_CTL_TILED_MASK;
2ebef630
TU		 11079 switch (fb->modifier[0]) {
11080 case DRM_FORMAT_MOD_NONE:
11081 break;
11082 case I915_FORMAT_MOD_X_TILED:
ff944564 11083 ctl |= PLANE_CTL_TILED_X;
2ebef630
TU		 11084 break;
11085 case I915_FORMAT_MOD_Y_TILED:
11086 ctl |= PLANE_CTL_TILED_Y;
11087 break;
11088 case I915_FORMAT_MOD_Yf_TILED:
11089 ctl |= PLANE_CTL_TILED_YF;
11090 break;
11091 default:
11092 MISSING_CASE(fb->modifier[0]);
11093 }
ff944564
DL		 11094
11095 /*
11096 * The stride is either expressed as a multiple of 64 bytes chunks for
11097 * linear buffers or in number of tiles for tiled buffers.
11098 */
2ebef630
TU		 11099 stride = fb->pitches[0] /
11100 intel_fb_stride_alignment(dev, fb->modifier[0],
11101 fb->pixel_format);
ff944564
DL		 11102
11103 /*
11104 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11105 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11106 */
11107 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11108 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11109
11110 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11111 POSTING_READ(PLANE_SURF(pipe, 0));
11112}
11113
11114static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG		 11115{
11116 struct drm_device *dev = intel_crtc->base.dev;
11117 struct drm_i915_private *dev_priv = dev->dev_private;
11118 struct intel_framebuffer *intel_fb =
11119 to_intel_framebuffer(intel_crtc->base.primary->fb);
11120 struct drm_i915_gem_object *obj = intel_fb->obj;
11121 u32 dspcntr;
11122 u32 reg;
11123
84c33a64
SG		 11124 reg = DSPCNTR(intel_crtc->plane);
11125 dspcntr = I915_READ(reg);
11126
c5d97472
DL		 11127 if (obj->tiling_mode != I915_TILING_NONE)
11128 dspcntr |= DISPPLANE_TILED;
11129 else
11130 dspcntr &= ~DISPPLANE_TILED;
11131
84c33a64
SG		 11132 I915_WRITE(reg, dspcntr);
11133
11134 I915_WRITE(DSPSURF(intel_crtc->plane),
11135 intel_crtc->unpin_work->gtt_offset);
11136 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 11137
ff944564
DL		 11138}
11139
11140/*
11141 * XXX: This is the temporary way to update the plane registers until we get
11142 * around to using the usual plane update functions for MMIO flips
11143 */
11144static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11145{
11146 struct drm_device *dev = intel_crtc->base.dev;
11147 bool atomic_update;
11148 u32 start_vbl_count;
11149
11150 intel_mark_page_flip_active(intel_crtc);
11151
11152 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
11153
11154 if (INTEL_INFO(dev)->gen >= 9)
11155 skl_do_mmio_flip(intel_crtc);
11156 else
11157 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11158 ilk_do_mmio_flip(intel_crtc);
11159
9362c7c5
ACO		 11160 if (atomic_update)
11161 intel_pipe_update_end(intel_crtc, start_vbl_count);
84c33a64
SG		 11162}
11163
9362c7c5 11164static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 11165{
b2cfe0ab
CW		 11166 struct intel_mmio_flip *mmio_flip =
11167 container_of(work, struct intel_mmio_flip, work);
84c33a64 11168
eed29a5b
DV		 11169 if (mmio_flip->req)
11170 WARN_ON(__i915_wait_request(mmio_flip->req,
b2cfe0ab 11171 mmio_flip->crtc->reset_counter,
bcafc4e3
CW		 11172 false, NULL,
11173 &mmio_flip->i915->rps.mmioflips));
84c33a64 11174
b2cfe0ab
CW		 11175 intel_do_mmio_flip(mmio_flip->crtc);
11176
eed29a5b 11177 i915_gem_request_unreference__unlocked(mmio_flip->req);
b2cfe0ab 11178 kfree(mmio_flip);
84c33a64
SG		 11179}
11180
11181static int intel_queue_mmio_flip(struct drm_device *dev,
11182 struct drm_crtc *crtc,
11183 struct drm_framebuffer *fb,
11184 struct drm_i915_gem_object *obj,
11185 struct intel_engine_cs *ring,
11186 uint32_t flags)
11187{
b2cfe0ab
CW		 11188 struct intel_mmio_flip *mmio_flip;
11189
11190 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11191 if (mmio_flip == NULL)
11192 return -ENOMEM;
84c33a64 11193
bcafc4e3 11194 mmio_flip->i915 = to_i915(dev);
eed29a5b 11195 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
b2cfe0ab 11196 mmio_flip->crtc = to_intel_crtc(crtc);
536f5b5e 11197
b2cfe0ab
CW		 11198 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11199 schedule_work(&mmio_flip->work);
84c33a64 11200
84c33a64
SG		 11201 return 0;
11202}
11203
8c9f3aaf
JB		 11204static int intel_default_queue_flip(struct drm_device *dev,
11205 struct drm_crtc *crtc,
11206 struct drm_framebuffer *fb,
ed8d1975 11207 struct drm_i915_gem_object *obj,
a4872ba6 11208 struct intel_engine_cs *ring,
ed8d1975 11209 uint32_t flags)
8c9f3aaf
JB		 11210{
11211 return -ENODEV;
11212}
11213
d6bbafa1
CW		 11214static bool __intel_pageflip_stall_check(struct drm_device *dev,
11215 struct drm_crtc *crtc)
11216{
11217 struct drm_i915_private *dev_priv = dev->dev_private;
11218 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11219 struct intel_unpin_work *work = intel_crtc->unpin_work;
11220 u32 addr;
11221
11222 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11223 return true;
11224
11225 if (!work->enable_stall_check)
11226 return false;
11227
11228 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 11229 if (work->flip_queued_req &&
11230 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 11231 return false;
11232
1e3feefd 11233 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 11234 }
11235
1e3feefd 11236 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 11237 return false;
11238
11239 /* Potential stall - if we see that the flip has happened,
11240 * assume a missed interrupt. */
11241 if (INTEL_INFO(dev)->gen >= 4)
11242 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11243 else
11244 addr = I915_READ(DSPADDR(intel_crtc->plane));
11245
11246 /* There is a potential issue here with a false positive after a flip
11247 * to the same address. We could address this by checking for a
11248 * non-incrementing frame counter.
11249 */
11250 return addr == work->gtt_offset;
11251}
11252
11253void intel_check_page_flip(struct drm_device *dev, int pipe)
11254{
11255 struct drm_i915_private *dev_priv = dev->dev_private;
11256 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11257 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 11258 struct intel_unpin_work *work;
f326038a 11259
6c51d46f 11260 WARN_ON(!in_interrupt());
d6bbafa1
CW		 11261
11262 if (crtc == NULL)
11263 return;
11264
f326038a 11265 spin_lock(&dev->event_lock);
6ad790c0
CW		 11266 work = intel_crtc->unpin_work;
11267 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 11268 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 11269 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 11270 page_flip_completed(intel_crtc);
6ad790c0 11271 work = NULL;
d6bbafa1 11272 }
6ad790c0
CW		 11273 if (work != NULL &&
11274 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11275 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 11276 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 11277}
11278
6b95a207
KH		 11279static int intel_crtc_page_flip(struct drm_crtc *crtc,
11280 struct drm_framebuffer *fb,
ed8d1975
KP		 11281 struct drm_pending_vblank_event *event,
11282 uint32_t page_flip_flags)
6b95a207
KH		 11283{
11284 struct drm_device *dev = crtc->dev;
11285 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 11286 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 11287 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 11288 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 11289 struct drm_plane *primary = crtc->primary;
a071fa00 11290 enum pipe pipe = intel_crtc->pipe;
6b95a207 11291 struct intel_unpin_work *work;
a4872ba6 11292 struct intel_engine_cs *ring;
cf5d8a46 11293 bool mmio_flip;
52e68630 11294 int ret;
6b95a207 11295
2ff8fde1
MR		 11296 /*
11297 * drm_mode_page_flip_ioctl() should already catch this, but double
11298 * check to be safe. In the future we may enable pageflipping from
11299 * a disabled primary plane.
11300 */
11301 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11302 return -EBUSY;
11303
e6a595d2 11304 /* Can't change pixel format via MI display flips. */
f4510a27 11305 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 11306 return -EINVAL;
11307
11308 /*
11309 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11310 * Note that pitch changes could also affect these register.
11311 */
11312 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 11313 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11314 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 11315 return -EINVAL;
11316
f900db47
CW		 11317 if (i915_terminally_wedged(&dev_priv->gpu_error))
11318 goto out_hang;
11319
b14c5679 11320 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 11321 if (work == NULL)
11322 return -ENOMEM;
11323
6b95a207 11324 work->event = event;
b4a98e57 11325 work->crtc = crtc;
ab8d6675 11326 work->old_fb = old_fb;
6b95a207
KH		 11327 INIT_WORK(&work->work, intel_unpin_work_fn);
11328
87b6b101 11329 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 11330 if (ret)
11331 goto free_work;
11332
6b95a207 11333 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 11334 spin_lock_irq(&dev->event_lock);
6b95a207 11335 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 11336 /* Before declaring the flip queue wedged, check if
11337 * the hardware completed the operation behind our backs.
11338 */
11339 if (__intel_pageflip_stall_check(dev, crtc)) {
11340 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11341 page_flip_completed(intel_crtc);
11342 } else {
11343 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 11344 spin_unlock_irq(&dev->event_lock);
468f0b44 11345
d6bbafa1
CW		 11346 drm_crtc_vblank_put(crtc);
11347 kfree(work);
11348 return -EBUSY;
11349 }
6b95a207
KH		 11350 }
11351 intel_crtc->unpin_work = work;
5e2d7afc 11352 spin_unlock_irq(&dev->event_lock);
6b95a207 11353
b4a98e57
CW		 11354 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11355 flush_workqueue(dev_priv->wq);
11356
75dfca80 11357 /* Reference the objects for the scheduled work. */
ab8d6675 11358 drm_framebuffer_reference(work->old_fb);
05394f39 11359 drm_gem_object_reference(&obj->base);
6b95a207 11360
f4510a27 11361 crtc->primary->fb = fb;
afd65eb4 11362 update_state_fb(crtc->primary);
1ed1f968 11363
e1f99ce6 11364 work->pending_flip_obj = obj;
e1f99ce6 11365
89ed88ba
CW		 11366 ret = i915_mutex_lock_interruptible(dev);
11367 if (ret)
11368 goto cleanup;
11369
b4a98e57 11370 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 11371 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 11372
75f7f3ec 11373 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 11374 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 11375
4fa62c89
VS		 11376 if (IS_VALLEYVIEW(dev)) {
11377 ring = &dev_priv->ring[BCS];
ab8d6675 11378 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 11379 /* vlv: DISPLAY_FLIP fails to change tiling */
11380 ring = NULL;
48bf5b2d 11381 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 11382 ring = &dev_priv->ring[BCS];
4fa62c89 11383 } else if (INTEL_INFO(dev)->gen >= 7) {
b4716185 11384 ring = i915_gem_request_get_ring(obj->last_write_req);
4fa62c89
VS		 11385 if (ring == NULL || ring->id != RCS)
11386 ring = &dev_priv->ring[BCS];
11387 } else {
11388 ring = &dev_priv->ring[RCS];
11389 }
11390
cf5d8a46
CW		 11391 mmio_flip = use_mmio_flip(ring, obj);
11392
11393 /* When using CS flips, we want to emit semaphores between rings.
11394 * However, when using mmio flips we will create a task to do the
11395 * synchronisation, so all we want here is to pin the framebuffer
11396 * into the display plane and skip any waits.
11397 */
82bc3b2d 11398 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
cf5d8a46 11399 crtc->primary->state,
b4716185 11400 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring);
8c9f3aaf
JB		 11401 if (ret)
11402 goto cleanup_pending;
6b95a207 11403
121920fa
TU		 11404 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11405 + intel_crtc->dspaddr_offset;
4fa62c89 11406
cf5d8a46 11407 if (mmio_flip) {
84c33a64
SG		 11408 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11409 page_flip_flags);
d6bbafa1
CW		 11410 if (ret)
11411 goto cleanup_unpin;
11412
f06cc1b9
JH		 11413 i915_gem_request_assign(&work->flip_queued_req,
11414 obj->last_write_req);
d6bbafa1 11415 } else {
d94b5030
CW		 11416 if (obj->last_write_req) {
11417 ret = i915_gem_check_olr(obj->last_write_req);
11418 if (ret)
11419 goto cleanup_unpin;
11420 }
11421
84c33a64 11422 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
d6bbafa1
CW		 11423 page_flip_flags);
11424 if (ret)
11425 goto cleanup_unpin;
11426
f06cc1b9
JH		 11427 i915_gem_request_assign(&work->flip_queued_req,
11428 intel_ring_get_request(ring));
d6bbafa1
CW		 11429 }
11430
1e3feefd 11431 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 11432 work->enable_stall_check = true;
4fa62c89 11433
ab8d6675 11434 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a071fa00
DV		 11435 INTEL_FRONTBUFFER_PRIMARY(pipe));
11436
7ff0ebcc 11437 intel_fbc_disable(dev);
f99d7069 11438 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
6b95a207
KH		 11439 mutex_unlock(&dev->struct_mutex);
11440
e5510fac
JB		 11441 trace_i915_flip_request(intel_crtc->plane, obj);
11442
6b95a207 11443 return 0;
96b099fd 11444
4fa62c89 11445cleanup_unpin:
82bc3b2d 11446 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 11447cleanup_pending:
b4a98e57 11448 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 11449 mutex_unlock(&dev->struct_mutex);
11450cleanup:
f4510a27 11451 crtc->primary->fb = old_fb;
afd65eb4 11452 update_state_fb(crtc->primary);
89ed88ba
CW		 11453
11454 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 11455 drm_framebuffer_unreference(work->old_fb);
96b099fd 11456
5e2d7afc 11457 spin_lock_irq(&dev->event_lock);
96b099fd 11458 intel_crtc->unpin_work = NULL;
5e2d7afc 11459 spin_unlock_irq(&dev->event_lock);
96b099fd 11460
87b6b101 11461 drm_crtc_vblank_put(crtc);
7317c75e 11462free_work:
96b099fd
CW		 11463 kfree(work);
11464
f900db47
CW		 11465 if (ret == -EIO) {
11466out_hang:
53a366b9 11467 ret = intel_plane_restore(primary);
f0d3dad3 11468 if (ret == 0 && event) {
5e2d7afc 11469 spin_lock_irq(&dev->event_lock);
a071fa00 11470 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 11471 spin_unlock_irq(&dev->event_lock);
f0d3dad3 11472 }
f900db47 11473 }
96b099fd 11474 return ret;
6b95a207
KH		 11475}
11476
65b38e0d 11477static const struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 11478 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11479 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 11480 .atomic_begin = intel_begin_crtc_commit,
11481 .atomic_flush = intel_finish_crtc_commit,
f6e5b160
CW		 11482};
11483
9a935856
DV		 11484/**
11485 * intel_modeset_update_staged_output_state
11486 *
11487 * Updates the staged output configuration state, e.g. after we've read out the
11488 * current hw state.
11489 */
11490static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 11491{
7668851f 11492 struct intel_crtc *crtc;
9a935856
DV		 11493 struct intel_encoder *encoder;
11494 struct intel_connector *connector;
f6e5b160 11495
3a3371ff 11496 for_each_intel_connector(dev, connector) {
9a935856
DV		 11497 connector->new_encoder =
11498 to_intel_encoder(connector->base.encoder);
11499 }
f6e5b160 11500
b2784e15 11501 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 11502 encoder->new_crtc =
11503 to_intel_crtc(encoder->base.crtc);
11504 }
7668851f 11505
d3fcc808 11506 for_each_intel_crtc(dev, crtc) {
83d65738 11507 crtc->new_enabled = crtc->base.state->enable;
7668851f 11508 }
f6e5b160
CW		 11509}
11510
d29b2f9d
ACO		 11511/* Transitional helper to copy current connector/encoder state to
11512 * connector->state. This is needed so that code that is partially
11513 * converted to atomic does the right thing.
11514 */
11515static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11516{
11517 struct intel_connector *connector;
11518
11519 for_each_intel_connector(dev, connector) {
11520 if (connector->base.encoder) {
11521 connector->base.state->best_encoder =
11522 connector->base.encoder;
11523 connector->base.state->crtc =
11524 connector->base.encoder->crtc;
11525 } else {
11526 connector->base.state->best_encoder = NULL;
11527 connector->base.state->crtc = NULL;
11528 }
11529 }
11530}
11531
a821fc46 11532/* Fixup legacy state after an atomic state swap.
9a935856 11533 */
a821fc46 11534static void intel_modeset_fixup_state(struct drm_atomic_state *state)
9a935856 11535{
a821fc46 11536 struct intel_crtc *crtc;
9a935856 11537 struct intel_encoder *encoder;
a821fc46 11538 struct intel_connector *connector;
d5432a9d 11539
a821fc46
ACO		 11540 for_each_intel_connector(state->dev, connector) {
11541 connector->base.encoder = connector->base.state->best_encoder;
11542 if (connector->base.encoder)
11543 connector->base.encoder->crtc =
11544 connector->base.state->crtc;
9a935856 11545 }
f6e5b160 11546
d5432a9d
ACO		 11547 /* Update crtc of disabled encoders */
11548 for_each_intel_encoder(state->dev, encoder) {
11549 int num_connectors = 0;
11550
a821fc46
ACO		 11551 for_each_intel_connector(state->dev, connector)
11552 if (connector->base.encoder == &encoder->base)
d5432a9d
ACO		 11553 num_connectors++;
11554
11555 if (num_connectors == 0)
11556 encoder->base.crtc = NULL;
9a935856 11557 }
7668851f 11558
a821fc46
ACO		 11559 for_each_intel_crtc(state->dev, crtc) {
11560 crtc->base.enabled = crtc->base.state->enable;
11561 crtc->config = to_intel_crtc_state(crtc->base.state);
7668851f 11562 }
d29b2f9d 11563
d5432a9d
ACO		 11564 /* Copy the new configuration to the staged state, to keep the few
11565 * pieces of code that haven't been converted yet happy */
11566 intel_modeset_update_staged_output_state(state->dev);
9a935856
DV		 11567}
11568
050f7aeb 11569static void
eba905b2 11570connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 11571 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 11572{
11573 int bpp = pipe_config->pipe_bpp;
11574
11575 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11576 connector->base.base.id,
c23cc417 11577 connector->base.name);
050f7aeb
DV		 11578
11579 /* Don't use an invalid EDID bpc value */
11580 if (connector->base.display_info.bpc &&
11581 connector->base.display_info.bpc * 3 < bpp) {
11582 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11583 bpp, connector->base.display_info.bpc*3);
11584 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11585 }
11586
11587 /* Clamp bpp to 8 on screens without EDID 1.4 */
11588 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11589 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11590 bpp);
11591 pipe_config->pipe_bpp = 24;
11592 }
11593}
11594
4e53c2e0 11595static int
050f7aeb 11596compute_baseline_pipe_bpp(struct intel_crtc *crtc,
5cec258b 11597 struct intel_crtc_state *pipe_config)
4e53c2e0 11598{
050f7aeb 11599 struct drm_device *dev = crtc->base.dev;
1486017f 11600 struct drm_atomic_state *state;
da3ced29
ACO		 11601 struct drm_connector *connector;
11602 struct drm_connector_state *connector_state;
1486017f 11603 int bpp, i;
4e53c2e0 11604
d328c9d7 11605 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
4e53c2e0 11606 bpp = 10*3;
d328c9d7
DV		 11607 else if (INTEL_INFO(dev)->gen >= 5)
11608 bpp = 12*3;
11609 else
11610 bpp = 8*3;
11611
4e53c2e0 11612
4e53c2e0
DV		 11613 pipe_config->pipe_bpp = bpp;
11614
1486017f
ACO		 11615 state = pipe_config->base.state;
11616
4e53c2e0 11617 /* Clamp display bpp to EDID value */
da3ced29
ACO		 11618 for_each_connector_in_state(state, connector, connector_state, i) {
11619 if (connector_state->crtc != &crtc->base)
4e53c2e0
DV		 11620 continue;
11621
da3ced29
ACO		 11622 connected_sink_compute_bpp(to_intel_connector(connector),
11623 pipe_config);
4e53c2e0
DV		 11624 }
11625
11626 return bpp;
11627}
11628
644db711
DV		 11629static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11630{
11631 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11632 "type: 0x%x flags: 0x%x\n",
1342830c 11633 mode->crtc_clock,
644db711
DV		 11634 mode->crtc_hdisplay, mode->crtc_hsync_start,
11635 mode->crtc_hsync_end, mode->crtc_htotal,
11636 mode->crtc_vdisplay, mode->crtc_vsync_start,
11637 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11638}
11639
c0b03411 11640static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 11641 struct intel_crtc_state *pipe_config,
c0b03411
DV		 11642 const char *context)
11643{
6a60cd87
CK		 11644 struct drm_device *dev = crtc->base.dev;
11645 struct drm_plane *plane;
11646 struct intel_plane *intel_plane;
11647 struct intel_plane_state *state;
11648 struct drm_framebuffer *fb;
11649
11650 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11651 context, pipe_config, pipe_name(crtc->pipe));
c0b03411
DV		 11652
11653 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11654 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11655 pipe_config->pipe_bpp, pipe_config->dither);
11656 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11657 pipe_config->has_pch_encoder,
11658 pipe_config->fdi_lanes,
11659 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11660 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11661 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 11662 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11663 pipe_config->has_dp_encoder,
11664 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11665 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11666 pipe_config->dp_m_n.tu);
b95af8be
VK		 11667
11668 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11669 pipe_config->has_dp_encoder,
11670 pipe_config->dp_m2_n2.gmch_m,
11671 pipe_config->dp_m2_n2.gmch_n,
11672 pipe_config->dp_m2_n2.link_m,
11673 pipe_config->dp_m2_n2.link_n,
11674 pipe_config->dp_m2_n2.tu);
11675
55072d19
DV		 11676 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11677 pipe_config->has_audio,
11678 pipe_config->has_infoframe);
11679
c0b03411 11680 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 11681 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 11682 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 11683 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11684 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 11685 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 11686 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11687 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
0ec463d3
TU		 11688 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11689 crtc->num_scalers,
11690 pipe_config->scaler_state.scaler_users,
11691 pipe_config->scaler_state.scaler_id);
c0b03411
DV		 11692 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11693 pipe_config->gmch_pfit.control,
11694 pipe_config->gmch_pfit.pgm_ratios,
11695 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 11696 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 11697 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 11698 pipe_config->pch_pfit.size,
11699 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 11700 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 11701 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87 11702
415ff0f6
TU		 11703 if (IS_BROXTON(dev)) {
11704 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, "
11705 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11706 "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n",
11707 pipe_config->ddi_pll_sel,
11708 pipe_config->dpll_hw_state.ebb0,
11709 pipe_config->dpll_hw_state.pll0,
11710 pipe_config->dpll_hw_state.pll1,
11711 pipe_config->dpll_hw_state.pll2,
11712 pipe_config->dpll_hw_state.pll3,
11713 pipe_config->dpll_hw_state.pll6,
11714 pipe_config->dpll_hw_state.pll8,
11715 pipe_config->dpll_hw_state.pcsdw12);
11716 } else if (IS_SKYLAKE(dev)) {
11717 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11718 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11719 pipe_config->ddi_pll_sel,
11720 pipe_config->dpll_hw_state.ctrl1,
11721 pipe_config->dpll_hw_state.cfgcr1,
11722 pipe_config->dpll_hw_state.cfgcr2);
11723 } else if (HAS_DDI(dev)) {
11724 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11725 pipe_config->ddi_pll_sel,
11726 pipe_config->dpll_hw_state.wrpll);
11727 } else {
11728 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11729 "fp0: 0x%x, fp1: 0x%x\n",
11730 pipe_config->dpll_hw_state.dpll,
11731 pipe_config->dpll_hw_state.dpll_md,
11732 pipe_config->dpll_hw_state.fp0,
11733 pipe_config->dpll_hw_state.fp1);
11734 }
11735
6a60cd87
CK		 11736 DRM_DEBUG_KMS("planes on this crtc\n");
11737 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11738 intel_plane = to_intel_plane(plane);
11739 if (intel_plane->pipe != crtc->pipe)
11740 continue;
11741
11742 state = to_intel_plane_state(plane->state);
11743 fb = state->base.fb;
11744 if (!fb) {
11745 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11746 "disabled, scaler_id = %d\n",
11747 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11748 plane->base.id, intel_plane->pipe,
11749 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11750 drm_plane_index(plane), state->scaler_id);
11751 continue;
11752 }
11753
11754 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11755 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11756 plane->base.id, intel_plane->pipe,
11757 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11758 drm_plane_index(plane));
11759 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11760 fb->base.id, fb->width, fb->height, fb->pixel_format);
11761 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11762 state->scaler_id,
11763 state->src.x1 >> 16, state->src.y1 >> 16,
11764 drm_rect_width(&state->src) >> 16,
11765 drm_rect_height(&state->src) >> 16,
11766 state->dst.x1, state->dst.y1,
11767 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11768 }
c0b03411
DV		 11769}
11770
bc079e8b
VS		 11771static bool encoders_cloneable(const struct intel_encoder *a,
11772 const struct intel_encoder *b)
accfc0c5 11773{
bc079e8b
VS		 11774 /* masks could be asymmetric, so check both ways */
11775 return a == b || (a->cloneable & (1 << b->type) &&
11776 b->cloneable & (1 << a->type));
11777}
11778
98a221da
ACO		 11779static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11780 struct intel_crtc *crtc,
bc079e8b
VS		 11781 struct intel_encoder *encoder)
11782{
bc079e8b 11783 struct intel_encoder *source_encoder;
da3ced29 11784 struct drm_connector *connector;
98a221da
ACO		 11785 struct drm_connector_state *connector_state;
11786 int i;
bc079e8b 11787
da3ced29 11788 for_each_connector_in_state(state, connector, connector_state, i) {
98a221da 11789 if (connector_state->crtc != &crtc->base)
bc079e8b
VS		 11790 continue;
11791
98a221da
ACO		 11792 source_encoder =
11793 to_intel_encoder(connector_state->best_encoder);
bc079e8b
VS		 11794 if (!encoders_cloneable(encoder, source_encoder))
11795 return false;
11796 }
11797
11798 return true;
11799}
11800
98a221da
ACO		 11801static bool check_encoder_cloning(struct drm_atomic_state *state,
11802 struct intel_crtc *crtc)
bc079e8b 11803{
accfc0c5 11804 struct intel_encoder *encoder;
da3ced29 11805 struct drm_connector *connector;
98a221da
ACO		 11806 struct drm_connector_state *connector_state;
11807 int i;
accfc0c5 11808
da3ced29 11809 for_each_connector_in_state(state, connector, connector_state, i) {
98a221da
ACO		 11810 if (connector_state->crtc != &crtc->base)
11811 continue;
11812
11813 encoder = to_intel_encoder(connector_state->best_encoder);
11814 if (!check_single_encoder_cloning(state, crtc, encoder))
bc079e8b 11815 return false;
accfc0c5
DV		 11816 }
11817
bc079e8b 11818 return true;
accfc0c5
DV		 11819}
11820
5448a00d 11821static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 11822{
5448a00d
ACO		 11823 struct drm_device *dev = state->dev;
11824 struct intel_encoder *encoder;
da3ced29 11825 struct drm_connector *connector;
5448a00d 11826 struct drm_connector_state *connector_state;
00f0b378 11827 unsigned int used_ports = 0;
5448a00d 11828 int i;
00f0b378
VS		 11829
11830 /*
11831 * Walk the connector list instead of the encoder
11832 * list to detect the problem on ddi platforms
11833 * where there's just one encoder per digital port.
11834 */
da3ced29 11835 for_each_connector_in_state(state, connector, connector_state, i) {
5448a00d 11836 if (!connector_state->best_encoder)
00f0b378
VS		 11837 continue;
11838
5448a00d
ACO		 11839 encoder = to_intel_encoder(connector_state->best_encoder);
11840
11841 WARN_ON(!connector_state->crtc);
00f0b378
VS		 11842
11843 switch (encoder->type) {
11844 unsigned int port_mask;
11845 case INTEL_OUTPUT_UNKNOWN:
11846 if (WARN_ON(!HAS_DDI(dev)))
11847 break;
11848 case INTEL_OUTPUT_DISPLAYPORT:
11849 case INTEL_OUTPUT_HDMI:
11850 case INTEL_OUTPUT_EDP:
11851 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11852
11853 /* the same port mustn't appear more than once */
11854 if (used_ports & port_mask)
11855 return false;
11856
11857 used_ports |= port_mask;
11858 default:
11859 break;
11860 }
11861 }
11862
11863 return true;
11864}
11865
83a57153
ACO		 11866static void
11867clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11868{
11869 struct drm_crtc_state tmp_state;
663a3640 11870 struct intel_crtc_scaler_state scaler_state;
4978cc93
ACO		 11871 struct intel_dpll_hw_state dpll_hw_state;
11872 enum intel_dpll_id shared_dpll;
8504c74c 11873 uint32_t ddi_pll_sel;
83a57153 11874
7546a384
ACO		 11875 /* FIXME: before the switch to atomic started, a new pipe_config was
11876 * kzalloc'd. Code that depends on any field being zero should be
11877 * fixed, so that the crtc_state can be safely duplicated. For now,
11878 * only fields that are know to not cause problems are preserved. */
11879
83a57153 11880 tmp_state = crtc_state->base;
663a3640 11881 scaler_state = crtc_state->scaler_state;
4978cc93
ACO		 11882 shared_dpll = crtc_state->shared_dpll;
11883 dpll_hw_state = crtc_state->dpll_hw_state;
8504c74c 11884 ddi_pll_sel = crtc_state->ddi_pll_sel;
4978cc93 11885
83a57153 11886 memset(crtc_state, 0, sizeof *crtc_state);
4978cc93 11887
83a57153 11888 crtc_state->base = tmp_state;
663a3640 11889 crtc_state->scaler_state = scaler_state;
4978cc93
ACO		 11890 crtc_state->shared_dpll = shared_dpll;
11891 crtc_state->dpll_hw_state = dpll_hw_state;
8504c74c 11892 crtc_state->ddi_pll_sel = ddi_pll_sel;
83a57153
ACO		 11893}
11894
548ee15b 11895static int
b8cecdf5 11896intel_modeset_pipe_config(struct drm_crtc *crtc,
548ee15b
ACO		 11897 struct drm_atomic_state *state,
11898 struct intel_crtc_state *pipe_config)
ee7b9f93 11899{
7758a113 11900 struct intel_encoder *encoder;
da3ced29 11901 struct drm_connector *connector;
0b901879 11902 struct drm_connector_state *connector_state;
d328c9d7 11903 int base_bpp, ret = -EINVAL;
0b901879 11904 int i;
e29c22c0 11905 bool retry = true;
ee7b9f93 11906
98a221da 11907 if (!check_encoder_cloning(state, to_intel_crtc(crtc))) {
accfc0c5 11908 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
548ee15b 11909 return -EINVAL;
accfc0c5
DV		 11910 }
11911
5448a00d 11912 if (!check_digital_port_conflicts(state)) {
00f0b378 11913 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
548ee15b 11914 return -EINVAL;
00f0b378
VS		 11915 }
11916
83a57153 11917 clear_intel_crtc_state(pipe_config);
7758a113 11918
e143a21c
DV		 11919 pipe_config->cpu_transcoder =
11920 (enum transcoder) to_intel_crtc(crtc)->pipe;
b8cecdf5 11921
2960bc9c
ID		 11922 /*
11923 * Sanitize sync polarity flags based on requested ones. If neither
11924 * positive or negative polarity is requested, treat this as meaning
11925 * negative polarity.
11926 */
2d112de7 11927 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 11928 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 11929 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 11930
2d112de7 11931 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 11932 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 11933 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 11934
050f7aeb
DV		 11935 /* Compute a starting value for pipe_config->pipe_bpp taking the source
11936 * plane pixel format and any sink constraints into account. Returns the
11937 * source plane bpp so that dithering can be selected on mismatches
11938 * after encoders and crtc also have had their say. */
d328c9d7
DV		 11939 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11940 pipe_config);
11941 if (base_bpp < 0)
4e53c2e0
DV		 11942 goto fail;
11943
e41a56be
VS		 11944 /*
11945 * Determine the real pipe dimensions. Note that stereo modes can
11946 * increase the actual pipe size due to the frame doubling and
11947 * insertion of additional space for blanks between the frame. This
11948 * is stored in the crtc timings. We use the requested mode to do this
11949 * computation to clearly distinguish it from the adjusted mode, which
11950 * can be changed by the connectors in the below retry loop.
11951 */
2d112de7 11952 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 11953 &pipe_config->pipe_src_w,
11954 &pipe_config->pipe_src_h);
e41a56be 11955
e29c22c0 11956encoder_retry:
ef1b460d 11957 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 11958 pipe_config->port_clock = 0;
ef1b460d 11959 pipe_config->pixel_multiplier = 1;
ff9a6750 11960
135c81b8 11961 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 11962 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11963 CRTC_STEREO_DOUBLE);
135c81b8 11964
7758a113
DV		 11965 /* Pass our mode to the connectors and the CRTC to give them a chance to
11966 * adjust it according to limitations or connector properties, and also
11967 * a chance to reject the mode entirely.
47f1c6c9 11968 */
da3ced29 11969 for_each_connector_in_state(state, connector, connector_state, i) {
0b901879 11970 if (connector_state->crtc != crtc)
7758a113 11971 continue;
7ae89233 11972
0b901879
ACO		 11973 encoder = to_intel_encoder(connector_state->best_encoder);
11974
efea6e8e
DV		 11975 if (!(encoder->compute_config(encoder, pipe_config))) {
11976 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 11977 goto fail;
11978 }
ee7b9f93 11979 }
47f1c6c9 11980
ff9a6750
DV		 11981 /* Set default port clock if not overwritten by the encoder. Needs to be
11982 * done afterwards in case the encoder adjusts the mode. */
11983 if (!pipe_config->port_clock)
2d112de7 11984 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 11985 * pipe_config->pixel_multiplier;
ff9a6750 11986
a43f6e0f 11987 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 11988 if (ret < 0) {
7758a113
DV		 11989 DRM_DEBUG_KMS("CRTC fixup failed\n");
11990 goto fail;
ee7b9f93 11991 }
e29c22c0
DV		 11992
11993 if (ret == RETRY) {
11994 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11995 ret = -EINVAL;
11996 goto fail;
11997 }
11998
11999 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12000 retry = false;
12001 goto encoder_retry;
12002 }
12003
d328c9d7 12004 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
4e53c2e0 12005 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
d328c9d7 12006 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
4e53c2e0 12007
548ee15b 12008 return 0;
7758a113 12009fail:
548ee15b 12010 return ret;
ee7b9f93 12011}
47f1c6c9 12012
ea9d758d 12013static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 12014{
ea9d758d 12015 struct drm_encoder *encoder;
f6e5b160 12016 struct drm_device *dev = crtc->dev;
f6e5b160 12017
ea9d758d
DV		 12018 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
12019 if (encoder->crtc == crtc)
12020 return true;
12021
12022 return false;
12023}
12024
0a9ab303
ACO		 12025static bool
12026needs_modeset(struct drm_crtc_state *state)
12027{
12028 return state->mode_changed || state->active_changed;
12029}
12030
ea9d758d 12031static void
0a9ab303 12032intel_modeset_update_state(struct drm_atomic_state *state)
ea9d758d 12033{
0a9ab303 12034 struct drm_device *dev = state->dev;
ba41c0de 12035 struct drm_i915_private *dev_priv = dev->dev_private;
ea9d758d 12036 struct intel_encoder *intel_encoder;
0a9ab303
ACO		 12037 struct drm_crtc *crtc;
12038 struct drm_crtc_state *crtc_state;
ea9d758d 12039 struct drm_connector *connector;
0a9ab303 12040 int i;
ea9d758d 12041
ba41c0de
DV		 12042 intel_shared_dpll_commit(dev_priv);
12043
b2784e15 12044 for_each_intel_encoder(dev, intel_encoder) {
ea9d758d
DV		 12045 if (!intel_encoder->base.crtc)
12046 continue;
12047
0a9ab303
ACO		 12048 for_each_crtc_in_state(state, crtc, crtc_state, i)
12049 if (crtc == intel_encoder->base.crtc)
12050 break;
12051
12052 if (crtc != intel_encoder->base.crtc)
12053 continue;
ea9d758d 12054
0a9ab303 12055 if (crtc_state->enable && needs_modeset(crtc_state))
ea9d758d
DV		 12056 intel_encoder->connectors_active = false;
12057 }
12058
a821fc46
ACO		 12059 drm_atomic_helper_swap_state(state->dev, state);
12060 intel_modeset_fixup_state(state);
ea9d758d 12061
7668851f 12062 /* Double check state. */
0a9ab303
ACO		 12063 for_each_crtc(dev, crtc) {
12064 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
ea9d758d
DV		 12065 }
12066
12067 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12068 if (!connector->encoder || !connector->encoder->crtc)
12069 continue;
12070
0a9ab303
ACO		 12071 for_each_crtc_in_state(state, crtc, crtc_state, i)
12072 if (crtc == connector->encoder->crtc)
12073 break;
12074
12075 if (crtc != connector->encoder->crtc)
12076 continue;
ea9d758d 12077
a821fc46 12078 if (crtc->state->enable && needs_modeset(crtc->state)) {
68d34720
DV		 12079 struct drm_property *dpms_property =
12080 dev->mode_config.dpms_property;
12081
ea9d758d 12082 connector->dpms = DRM_MODE_DPMS_ON;
662595df 12083 drm_object_property_set_value(&connector->base,
68d34720
DV		 12084 dpms_property,
12085 DRM_MODE_DPMS_ON);
ea9d758d
DV		 12086
12087 intel_encoder = to_intel_encoder(connector->encoder);
12088 intel_encoder->connectors_active = true;
12089 }
12090 }
12091
12092}
12093
3bd26263 12094static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 12095{
3bd26263 12096 int diff;
f1f644dc
JB		 12097
12098 if (clock1 == clock2)
12099 return true;
12100
12101 if (!clock1 || !clock2)
12102 return false;
12103
12104 diff = abs(clock1 - clock2);
12105
12106 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12107 return true;
12108
12109 return false;
12110}
12111
25c5b266
DV		 12112#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12113 list_for_each_entry((intel_crtc), \
12114 &(dev)->mode_config.crtc_list, \
12115 base.head) \
0973f18f 12116 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 12117
0e8ffe1b 12118static bool
2fa2fe9a 12119intel_pipe_config_compare(struct drm_device *dev,
5cec258b
ACO		 12120 struct intel_crtc_state *current_config,
12121 struct intel_crtc_state *pipe_config)
0e8ffe1b 12122{
66e985c0
DV		 12123#define PIPE_CONF_CHECK_X(name) \
12124 if (current_config->name != pipe_config->name) { \
12125 DRM_ERROR("mismatch in " #name " " \
12126 "(expected 0x%08x, found 0x%08x)\n", \
12127 current_config->name, \
12128 pipe_config->name); \
12129 return false; \
12130 }
12131
08a24034
DV		 12132#define PIPE_CONF_CHECK_I(name) \
12133 if (current_config->name != pipe_config->name) { \
12134 DRM_ERROR("mismatch in " #name " " \
12135 "(expected %i, found %i)\n", \
12136 current_config->name, \
12137 pipe_config->name); \
12138 return false; \
88adfff1
DV		 12139 }
12140
b95af8be
VK		 12141/* This is required for BDW+ where there is only one set of registers for
12142 * switching between high and low RR.
12143 * This macro can be used whenever a comparison has to be made between one
12144 * hw state and multiple sw state variables.
12145 */
12146#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12147 if ((current_config->name != pipe_config->name) && \
12148 (current_config->alt_name != pipe_config->name)) { \
12149 DRM_ERROR("mismatch in " #name " " \
12150 "(expected %i or %i, found %i)\n", \
12151 current_config->name, \
12152 current_config->alt_name, \
12153 pipe_config->name); \
12154 return false; \
12155 }
12156
1bd1bd80
DV		 12157#define PIPE_CONF_CHECK_FLAGS(name, mask) \
12158 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 12159 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 12160 "(expected %i, found %i)\n", \
12161 current_config->name & (mask), \
12162 pipe_config->name & (mask)); \
12163 return false; \
12164 }
12165
5e550656
VS		 12166#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12167 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12168 DRM_ERROR("mismatch in " #name " " \
12169 "(expected %i, found %i)\n", \
12170 current_config->name, \
12171 pipe_config->name); \
12172 return false; \
12173 }
12174
bb760063
DV		 12175#define PIPE_CONF_QUIRK(quirk) \
12176 ((current_config->quirks | pipe_config->quirks) & (quirk))
12177
eccb140b
DV		 12178 PIPE_CONF_CHECK_I(cpu_transcoder);
12179
08a24034
DV		 12180 PIPE_CONF_CHECK_I(has_pch_encoder);
12181 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 12182 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
12183 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
12184 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
12185 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
12186 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 12187
eb14cb74 12188 PIPE_CONF_CHECK_I(has_dp_encoder);
b95af8be
VK		 12189
12190 if (INTEL_INFO(dev)->gen < 8) {
12191 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
12192 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
12193 PIPE_CONF_CHECK_I(dp_m_n.link_m);
12194 PIPE_CONF_CHECK_I(dp_m_n.link_n);
12195 PIPE_CONF_CHECK_I(dp_m_n.tu);
12196
12197 if (current_config->has_drrs) {
12198 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
12199 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
12200 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
12201 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
12202 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
12203 }
12204 } else {
12205 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
12206 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
12207 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
12208 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
12209 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
12210 }
eb14cb74 12211
2d112de7
ACO		 12212 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12213 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12214 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12215 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12216 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12217 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 12218
2d112de7
ACO		 12219 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12220 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12221 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12222 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12223 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12224 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 12225
c93f54cf 12226 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 12227 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 12228 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12229 IS_VALLEYVIEW(dev))
12230 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 12231 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 12232
9ed109a7
DV		 12233 PIPE_CONF_CHECK_I(has_audio);
12234
2d112de7 12235 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 12236 DRM_MODE_FLAG_INTERLACE);
12237
bb760063 12238 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 12239 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12240 DRM_MODE_FLAG_PHSYNC);
2d112de7 12241 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12242 DRM_MODE_FLAG_NHSYNC);
2d112de7 12243 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12244 DRM_MODE_FLAG_PVSYNC);
2d112de7 12245 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 12246 DRM_MODE_FLAG_NVSYNC);
12247 }
045ac3b5 12248
37327abd
VS		 12249 PIPE_CONF_CHECK_I(pipe_src_w);
12250 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 12251
9953599b
DV		 12252 /*
12253 * FIXME: BIOS likes to set up a cloned config with lvds+external
12254 * screen. Since we don't yet re-compute the pipe config when moving
12255 * just the lvds port away to another pipe the sw tracking won't match.
12256 *
12257 * Proper atomic modesets with recomputed global state will fix this.
12258 * Until then just don't check gmch state for inherited modes.
12259 */
12260 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
12261 PIPE_CONF_CHECK_I(gmch_pfit.control);
12262 /* pfit ratios are autocomputed by the hw on gen4+ */
12263 if (INTEL_INFO(dev)->gen < 4)
12264 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12265 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12266 }
12267
fd4daa9c
CW		 12268 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12269 if (current_config->pch_pfit.enabled) {
12270 PIPE_CONF_CHECK_I(pch_pfit.pos);
12271 PIPE_CONF_CHECK_I(pch_pfit.size);
12272 }
2fa2fe9a 12273
a1b2278e
CK		 12274 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12275
e59150dc
JB		 12276 /* BDW+ don't expose a synchronous way to read the state */
12277 if (IS_HASWELL(dev))
12278 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 12279
282740f7
VS		 12280 PIPE_CONF_CHECK_I(double_wide);
12281
26804afd
DV		 12282 PIPE_CONF_CHECK_X(ddi_pll_sel);
12283
c0d43d62 12284 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 12285 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 12286 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 12287 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12288 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 12289 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 12290 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12291 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12292 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 12293
42571aef
VS		 12294 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12295 PIPE_CONF_CHECK_I(pipe_bpp);
12296
2d112de7 12297 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 12298 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 12299
66e985c0 12300#undef PIPE_CONF_CHECK_X
08a24034 12301#undef PIPE_CONF_CHECK_I
b95af8be 12302#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 12303#undef PIPE_CONF_CHECK_FLAGS
5e550656 12304#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 12305#undef PIPE_CONF_QUIRK
88adfff1 12306
0e8ffe1b
DV		 12307 return true;
12308}
12309
08db6652
DL		 12310static void check_wm_state(struct drm_device *dev)
12311{
12312 struct drm_i915_private *dev_priv = dev->dev_private;
12313 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12314 struct intel_crtc *intel_crtc;
12315 int plane;
12316
12317 if (INTEL_INFO(dev)->gen < 9)
12318 return;
12319
12320 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12321 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12322
12323 for_each_intel_crtc(dev, intel_crtc) {
12324 struct skl_ddb_entry *hw_entry, *sw_entry;
12325 const enum pipe pipe = intel_crtc->pipe;
12326
12327 if (!intel_crtc->active)
12328 continue;
12329
12330 /* planes */
dd740780 12331 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 12332 hw_entry = &hw_ddb.plane[pipe][plane];
12333 sw_entry = &sw_ddb->plane[pipe][plane];
12334
12335 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12336 continue;
12337
12338 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12339 "(expected (%u,%u), found (%u,%u))\n",
12340 pipe_name(pipe), plane + 1,
12341 sw_entry->start, sw_entry->end,
12342 hw_entry->start, hw_entry->end);
12343 }
12344
12345 /* cursor */
12346 hw_entry = &hw_ddb.cursor[pipe];
12347 sw_entry = &sw_ddb->cursor[pipe];
12348
12349 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12350 continue;
12351
12352 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12353 "(expected (%u,%u), found (%u,%u))\n",
12354 pipe_name(pipe),
12355 sw_entry->start, sw_entry->end,
12356 hw_entry->start, hw_entry->end);
12357 }
12358}
12359
91d1b4bd
DV		 12360static void
12361check_connector_state(struct drm_device *dev)
8af6cf88 12362{
8af6cf88
DV		 12363 struct intel_connector *connector;
12364
3a3371ff 12365 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 12366 /* This also checks the encoder/connector hw state with the
12367 * ->get_hw_state callbacks. */
12368 intel_connector_check_state(connector);
12369
e2c719b7 12370 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
8af6cf88
DV		 12371 "connector's staged encoder doesn't match current encoder\n");
12372 }
91d1b4bd
DV		 12373}
12374
12375static void
12376check_encoder_state(struct drm_device *dev)
12377{
12378 struct intel_encoder *encoder;
12379 struct intel_connector *connector;
8af6cf88 12380
b2784e15 12381 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 12382 bool enabled = false;
12383 bool active = false;
12384 enum pipe pipe, tracked_pipe;
12385
12386 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12387 encoder->base.base.id,
8e329a03 12388 encoder->base.name);
8af6cf88 12389
e2c719b7 12390 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
8af6cf88 12391 "encoder's stage crtc doesn't match current crtc\n");
e2c719b7 12392 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
8af6cf88
DV		 12393 "encoder's active_connectors set, but no crtc\n");
12394
3a3371ff 12395 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 12396 if (connector->base.encoder != &encoder->base)
12397 continue;
12398 enabled = true;
12399 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12400 active = true;
12401 }
0e32b39c
DA		 12402 /*
12403 * for MST connectors if we unplug the connector is gone
12404 * away but the encoder is still connected to a crtc
12405 * until a modeset happens in response to the hotplug.
12406 */
12407 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12408 continue;
12409
e2c719b7 12410 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 12411 "encoder's enabled state mismatch "
12412 "(expected %i, found %i)\n",
12413 !!encoder->base.crtc, enabled);
e2c719b7 12414 I915_STATE_WARN(active && !encoder->base.crtc,
8af6cf88
DV		 12415 "active encoder with no crtc\n");
12416
e2c719b7 12417 I915_STATE_WARN(encoder->connectors_active != active,
8af6cf88
DV		 12418 "encoder's computed active state doesn't match tracked active state "
12419 "(expected %i, found %i)\n", active, encoder->connectors_active);
12420
12421 active = encoder->get_hw_state(encoder, &pipe);
e2c719b7 12422 I915_STATE_WARN(active != encoder->connectors_active,
8af6cf88
DV		 12423 "encoder's hw state doesn't match sw tracking "
12424 "(expected %i, found %i)\n",
12425 encoder->connectors_active, active);
12426
12427 if (!encoder->base.crtc)
12428 continue;
12429
12430 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
e2c719b7 12431 I915_STATE_WARN(active && pipe != tracked_pipe,
8af6cf88
DV		 12432 "active encoder's pipe doesn't match"
12433 "(expected %i, found %i)\n",
12434 tracked_pipe, pipe);
12435
12436 }
91d1b4bd
DV		 12437}
12438
12439static void
12440check_crtc_state(struct drm_device *dev)
12441{
fbee40df 12442 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12443 struct intel_crtc *crtc;
12444 struct intel_encoder *encoder;
5cec258b 12445 struct intel_crtc_state pipe_config;
8af6cf88 12446
d3fcc808 12447 for_each_intel_crtc(dev, crtc) {
8af6cf88
DV		 12448 bool enabled = false;
12449 bool active = false;
12450
045ac3b5
JB		 12451 memset(&pipe_config, 0, sizeof(pipe_config));
12452
8af6cf88
DV		 12453 DRM_DEBUG_KMS("[CRTC:%d]\n",
12454 crtc->base.base.id);
12455
83d65738 12456 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
8af6cf88
DV		 12457 "active crtc, but not enabled in sw tracking\n");
12458
b2784e15 12459 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 12460 if (encoder->base.crtc != &crtc->base)
12461 continue;
12462 enabled = true;
12463 if (encoder->connectors_active)
12464 active = true;
12465 }
6c49f241 12466
e2c719b7 12467 I915_STATE_WARN(active != crtc->active,
8af6cf88
DV		 12468 "crtc's computed active state doesn't match tracked active state "
12469 "(expected %i, found %i)\n", active, crtc->active);
83d65738 12470 I915_STATE_WARN(enabled != crtc->base.state->enable,
8af6cf88 12471 "crtc's computed enabled state doesn't match tracked enabled state "
83d65738
MR		 12472 "(expected %i, found %i)\n", enabled,
12473 crtc->base.state->enable);
8af6cf88 12474
0e8ffe1b
DV		 12475 active = dev_priv->display.get_pipe_config(crtc,
12476 &pipe_config);
d62cf62a 12477
b6b5d049
VS		 12478 /* hw state is inconsistent with the pipe quirk */
12479 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12480 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
d62cf62a
DV		 12481 active = crtc->active;
12482
b2784e15 12483 for_each_intel_encoder(dev, encoder) {
3eaba51c 12484 enum pipe pipe;
6c49f241
DV		 12485 if (encoder->base.crtc != &crtc->base)
12486 continue;
1d37b689 12487 if (encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 12488 encoder->get_config(encoder, &pipe_config);
12489 }
12490
e2c719b7 12491 I915_STATE_WARN(crtc->active != active,
0e8ffe1b
DV		 12492 "crtc active state doesn't match with hw state "
12493 "(expected %i, found %i)\n", crtc->active, active);
12494
c0b03411 12495 if (active &&
6e3c9717 12496 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
e2c719b7 12497 I915_STATE_WARN(1, "pipe state doesn't match!\n");
c0b03411
DV		 12498 intel_dump_pipe_config(crtc, &pipe_config,
12499 "[hw state]");
6e3c9717 12500 intel_dump_pipe_config(crtc, crtc->config,
c0b03411
DV		 12501 "[sw state]");
12502 }
8af6cf88
DV		 12503 }
12504}
12505
91d1b4bd
DV		 12506static void
12507check_shared_dpll_state(struct drm_device *dev)
12508{
fbee40df 12509 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12510 struct intel_crtc *crtc;
12511 struct intel_dpll_hw_state dpll_hw_state;
12512 int i;
5358901f
DV		 12513
12514 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12515 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12516 int enabled_crtcs = 0, active_crtcs = 0;
12517 bool active;
12518
12519 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12520
12521 DRM_DEBUG_KMS("%s\n", pll->name);
12522
12523 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12524
e2c719b7 12525 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 12526 "more active pll users than references: %i vs %i\n",
3e369b76 12527 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 12528 I915_STATE_WARN(pll->active && !pll->on,
5358901f 12529 "pll in active use but not on in sw tracking\n");
e2c719b7 12530 I915_STATE_WARN(pll->on && !pll->active,
35c95375 12531 "pll in on but not on in use in sw tracking\n");
e2c719b7 12532 I915_STATE_WARN(pll->on != active,
5358901f
DV		 12533 "pll on state mismatch (expected %i, found %i)\n",
12534 pll->on, active);
12535
d3fcc808 12536 for_each_intel_crtc(dev, crtc) {
83d65738 12537 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 12538 enabled_crtcs++;
12539 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12540 active_crtcs++;
12541 }
e2c719b7 12542 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 12543 "pll active crtcs mismatch (expected %i, found %i)\n",
12544 pll->active, active_crtcs);
e2c719b7 12545 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 12546 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 12547 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 12548
e2c719b7 12549 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 12550 sizeof(dpll_hw_state)),
12551 "pll hw state mismatch\n");
5358901f 12552 }
8af6cf88
DV		 12553}
12554
91d1b4bd
DV		 12555void
12556intel_modeset_check_state(struct drm_device *dev)
12557{
08db6652 12558 check_wm_state(dev);
91d1b4bd
DV		 12559 check_connector_state(dev);
12560 check_encoder_state(dev);
12561 check_crtc_state(dev);
12562 check_shared_dpll_state(dev);
12563}
12564
5cec258b 12565void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 12566 int dotclock)
12567{
12568 /*
12569 * FDI already provided one idea for the dotclock.
12570 * Yell if the encoder disagrees.
12571 */
2d112de7 12572 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 12573 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 12574 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 12575}
12576
80715b2f
VS		 12577static void update_scanline_offset(struct intel_crtc *crtc)
12578{
12579 struct drm_device *dev = crtc->base.dev;
12580
12581 /*
12582 * The scanline counter increments at the leading edge of hsync.
12583 *
12584 * On most platforms it starts counting from vtotal-1 on the
12585 * first active line. That means the scanline counter value is
12586 * always one less than what we would expect. Ie. just after
12587 * start of vblank, which also occurs at start of hsync (on the
12588 * last active line), the scanline counter will read vblank_start-1.
12589 *
12590 * On gen2 the scanline counter starts counting from 1 instead
12591 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12592 * to keep the value positive), instead of adding one.
12593 *
12594 * On HSW+ the behaviour of the scanline counter depends on the output
12595 * type. For DP ports it behaves like most other platforms, but on HDMI
12596 * there's an extra 1 line difference. So we need to add two instead of
12597 * one to the value.
12598 */
12599 if (IS_GEN2(dev)) {
6e3c9717 12600 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 12601 int vtotal;
12602
12603 vtotal = mode->crtc_vtotal;
12604 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12605 vtotal /= 2;
12606
12607 crtc->scanline_offset = vtotal - 1;
12608 } else if (HAS_DDI(dev) &&
409ee761 12609 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 12610 crtc->scanline_offset = 2;
12611 } else
12612 crtc->scanline_offset = 1;
12613}
12614
5cec258b 12615static struct intel_crtc_state *
7f27126e 12616intel_modeset_compute_config(struct drm_crtc *crtc,
0a9ab303 12617 struct drm_atomic_state *state)
7f27126e 12618{
548ee15b 12619 struct intel_crtc_state *pipe_config;
0b901879
ACO		 12620 int ret = 0;
12621
12622 ret = drm_atomic_add_affected_connectors(state, crtc);
12623 if (ret)
12624 return ERR_PTR(ret);
7f27126e 12625
8c7b5ccb
ACO		 12626 ret = drm_atomic_helper_check_modeset(state->dev, state);
12627 if (ret)
12628 return ERR_PTR(ret);
7f27126e 12629
7f27126e
JB		 12630 /*
12631 * Note this needs changes when we start tracking multiple modes
12632 * and crtcs. At that point we'll need to compute the whole config
12633 * (i.e. one pipe_config for each crtc) rather than just the one
12634 * for this crtc.
12635 */
548ee15b
ACO		 12636 pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
12637 if (IS_ERR(pipe_config))
12638 return pipe_config;
83a57153 12639
4fed33f6 12640 if (!pipe_config->base.enable)
548ee15b 12641 return pipe_config;
7f27126e 12642
8c7b5ccb 12643 ret = intel_modeset_pipe_config(crtc, state, pipe_config);
548ee15b
ACO		 12644 if (ret)
12645 return ERR_PTR(ret);
12646
8d8c9b51
ACO		 12647 /* Check things that can only be changed through modeset */
12648 if (pipe_config->has_audio !=
12649 to_intel_crtc(crtc)->config->has_audio)
12650 pipe_config->base.mode_changed = true;
12651
12652 /*
12653 * Note we have an issue here with infoframes: current code
12654 * only updates them on the full mode set path per hw
12655 * requirements. So here we should be checking for any
12656 * required changes and forcing a mode set.
12657 */
12658
548ee15b 12659 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,"[modeset]");
db7542dd 12660
8c7b5ccb
ACO		 12661 ret = drm_atomic_helper_check_planes(state->dev, state);
12662 if (ret)
12663 return ERR_PTR(ret);
12664
548ee15b 12665 return pipe_config;
7f27126e
JB		 12666}
12667
0a9ab303 12668static int __intel_set_mode_setup_plls(struct drm_atomic_state *state)
ed6739ef 12669{
225da59b 12670 struct drm_device *dev = state->dev;
ed6739ef 12671 struct drm_i915_private *dev_priv = to_i915(dev);
0a9ab303 12672 unsigned clear_pipes = 0;
ed6739ef 12673 struct intel_crtc *intel_crtc;
0a9ab303
ACO		 12674 struct intel_crtc_state *intel_crtc_state;
12675 struct drm_crtc *crtc;
12676 struct drm_crtc_state *crtc_state;
ed6739ef 12677 int ret = 0;
0a9ab303 12678 int i;
ed6739ef
ACO		 12679
12680 if (!dev_priv->display.crtc_compute_clock)
12681 return 0;
12682
0a9ab303
ACO		 12683 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12684 intel_crtc = to_intel_crtc(crtc);
4978cc93 12685 intel_crtc_state = to_intel_crtc_state(crtc_state);
0a9ab303 12686
4978cc93 12687 if (needs_modeset(crtc_state)) {
0a9ab303 12688 clear_pipes |= 1 << intel_crtc->pipe;
4978cc93 12689 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
4978cc93 12690 }
0a9ab303
ACO		 12691 }
12692
ed6739ef
ACO		 12693 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
12694 if (ret)
12695 goto done;
12696
0a9ab303
ACO		 12697 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12698 if (!needs_modeset(crtc_state) || !crtc_state->enable)
225da59b
ACO		 12699 continue;
12700
0a9ab303
ACO		 12701 intel_crtc = to_intel_crtc(crtc);
12702 intel_crtc_state = to_intel_crtc_state(crtc_state);
12703
ed6739ef 12704 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
0a9ab303 12705 intel_crtc_state);
ed6739ef
ACO		 12706 if (ret) {
12707 intel_shared_dpll_abort_config(dev_priv);
12708 goto done;
12709 }
12710 }
12711
12712done:
12713 return ret;
12714}
12715
054518dd
ACO		 12716/* Code that should eventually be part of atomic_check() */
12717static int __intel_set_mode_checks(struct drm_atomic_state *state)
12718{
12719 struct drm_device *dev = state->dev;
12720 int ret;
12721
12722 /*
12723 * See if the config requires any additional preparation, e.g.
12724 * to adjust global state with pipes off. We need to do this
12725 * here so we can get the modeset_pipe updated config for the new
12726 * mode set on this crtc. For other crtcs we need to use the
12727 * adjusted_mode bits in the crtc directly.
12728 */
12729 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
12730 ret = valleyview_modeset_global_pipes(state);
12731 if (ret)
12732 return ret;
12733 }
12734
12735 ret = __intel_set_mode_setup_plls(state);
12736 if (ret)
12737 return ret;
12738
12739 return 0;
12740}
12741
0a9ab303 12742static int __intel_set_mode(struct drm_crtc *modeset_crtc,
0a9ab303 12743 struct intel_crtc_state *pipe_config)
a6778b3c 12744{
0a9ab303 12745 struct drm_device *dev = modeset_crtc->dev;
fbee40df 12746 struct drm_i915_private *dev_priv = dev->dev_private;
304603f4 12747 struct drm_atomic_state *state = pipe_config->base.state;
0a9ab303
ACO		 12748 struct drm_crtc *crtc;
12749 struct drm_crtc_state *crtc_state;
c0c36b94 12750 int ret = 0;
0a9ab303 12751 int i;
a6778b3c 12752
054518dd
ACO		 12753 ret = __intel_set_mode_checks(state);
12754 if (ret < 0)
12755 return ret;
12756
d4afb8cc
ACO		 12757 ret = drm_atomic_helper_prepare_planes(dev, state);
12758 if (ret)
12759 return ret;
12760
0a9ab303
ACO		 12761 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12762 if (!needs_modeset(crtc_state))
12763 continue;
460da916 12764
0a9ab303
ACO		 12765 if (!crtc_state->enable) {
12766 intel_crtc_disable(crtc);
12767 } else if (crtc->state->enable) {
12768 intel_crtc_disable_planes(crtc);
12769 dev_priv->display.crtc_disable(crtc);
ce22dba9 12770 }
ea9d758d 12771 }
a6778b3c 12772
6c4c86f5
DV		 12773 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
12774 * to set it here already despite that we pass it down the callchain.
7f27126e
JB		 12775 *
12776 * Note we'll need to fix this up when we start tracking multiple
12777 * pipes; here we assume a single modeset_pipe and only track the
12778 * single crtc and mode.
f6e5b160 12779 */
0a9ab303 12780 if (pipe_config->base.enable && needs_modeset(&pipe_config->base)) {
8c7b5ccb 12781 modeset_crtc->mode = pipe_config->base.mode;
c326c0a9
VS		 12782
12783 /*
12784 * Calculate and store various constants which
12785 * are later needed by vblank and swap-completion
12786 * timestamping. They are derived from true hwmode.
12787 */
0a9ab303 12788 drm_calc_timestamping_constants(modeset_crtc,
2d112de7 12789 &pipe_config->base.adjusted_mode);
b8cecdf5 12790 }
7758a113 12791
ea9d758d
DV		 12792 /* Only after disabling all output pipelines that will be changed can we
12793 * update the the output configuration. */
0a9ab303 12794 intel_modeset_update_state(state);
f6e5b160 12795
a821fc46
ACO		 12796 /* The state has been swaped above, so state actually contains the
12797 * old state now. */
12798
304603f4 12799 modeset_update_crtc_power_domains(state);
47fab737 12800
d4afb8cc 12801 drm_atomic_helper_commit_planes(dev, state);
a6778b3c
DV		 12802
12803 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
0a9ab303 12804 for_each_crtc_in_state(state, crtc, crtc_state, i) {
a821fc46 12805 if (!needs_modeset(crtc->state) || !crtc->state->enable)
0a9ab303
ACO		 12806 continue;
12807
12808 update_scanline_offset(to_intel_crtc(crtc));
80715b2f 12809
0a9ab303
ACO		 12810 dev_priv->display.crtc_enable(crtc);
12811 intel_crtc_enable_planes(crtc);
80715b2f 12812 }
a6778b3c 12813
a6778b3c 12814 /* FIXME: add subpixel order */
83a57153 12815
d4afb8cc
ACO		 12816 drm_atomic_helper_cleanup_planes(dev, state);
12817
2bfb4627
ACO		 12818 drm_atomic_state_free(state);
12819
9eb45f22 12820 return 0;
f6e5b160
CW		 12821}
12822
0a9ab303 12823static int intel_set_mode_with_config(struct drm_crtc *crtc,
0a9ab303 12824 struct intel_crtc_state *pipe_config)
f30da187
DV		 12825{
12826 int ret;
12827
8c7b5ccb 12828 ret = __intel_set_mode(crtc, pipe_config);
f30da187
DV		 12829
12830 if (ret == 0)
12831 intel_modeset_check_state(crtc->dev);
12832
12833 return ret;
12834}
12835
7f27126e 12836static int intel_set_mode(struct drm_crtc *crtc,
83a57153 12837 struct drm_atomic_state *state)
7f27126e 12838{
5cec258b 12839 struct intel_crtc_state *pipe_config;
83a57153 12840 int ret = 0;
7f27126e 12841
8c7b5ccb 12842 pipe_config = intel_modeset_compute_config(crtc, state);
83a57153
ACO		 12843 if (IS_ERR(pipe_config)) {
12844 ret = PTR_ERR(pipe_config);
12845 goto out;
12846 }
12847
8c7b5ccb 12848 ret = intel_set_mode_with_config(crtc, pipe_config);
83a57153
ACO		 12849 if (ret)
12850 goto out;
7f27126e 12851
83a57153
ACO		 12852out:
12853 return ret;
7f27126e
JB		 12854}
12855
c0c36b94
CW		 12856void intel_crtc_restore_mode(struct drm_crtc *crtc)
12857{
83a57153
ACO		 12858 struct drm_device *dev = crtc->dev;
12859 struct drm_atomic_state *state;
4be07317 12860 struct intel_crtc *intel_crtc;
83a57153
ACO		 12861 struct intel_encoder *encoder;
12862 struct intel_connector *connector;
12863 struct drm_connector_state *connector_state;
4be07317 12864 struct intel_crtc_state *crtc_state;
2bfb4627 12865 int ret;
83a57153
ACO		 12866
12867 state = drm_atomic_state_alloc(dev);
12868 if (!state) {
12869 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
12870 crtc->base.id);
12871 return;
12872 }
12873
12874 state->acquire_ctx = dev->mode_config.acquire_ctx;
12875
12876 /* The force restore path in the HW readout code relies on the staged
12877 * config still keeping the user requested config while the actual
12878 * state has been overwritten by the configuration read from HW. We
12879 * need to copy the staged config to the atomic state, otherwise the
12880 * mode set will just reapply the state the HW is already in. */
12881 for_each_intel_encoder(dev, encoder) {
12882 if (&encoder->new_crtc->base != crtc)
12883 continue;
12884
12885 for_each_intel_connector(dev, connector) {
12886 if (connector->new_encoder != encoder)
12887 continue;
12888
12889 connector_state = drm_atomic_get_connector_state(state, &connector->base);
12890 if (IS_ERR(connector_state)) {
12891 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
12892 connector->base.base.id,
12893 connector->base.name,
12894 PTR_ERR(connector_state));
12895 continue;
12896 }
12897
12898 connector_state->crtc = crtc;
12899 connector_state->best_encoder = &encoder->base;
12900 }
12901 }
12902
4be07317
ACO		 12903 for_each_intel_crtc(dev, intel_crtc) {
12904 if (intel_crtc->new_enabled == intel_crtc->base.enabled)
12905 continue;
12906
12907 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
12908 if (IS_ERR(crtc_state)) {
12909 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
12910 intel_crtc->base.base.id,
12911 PTR_ERR(crtc_state));
12912 continue;
12913 }
12914
49d6fa21
ML		 12915 crtc_state->base.active = crtc_state->base.enable =
12916 intel_crtc->new_enabled;
8c7b5ccb
ACO		 12917
12918 if (&intel_crtc->base == crtc)
12919 drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
4be07317
ACO		 12920 }
12921
d3a40d1b
ACO		 12922 intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
12923 crtc->primary->fb, crtc->x, crtc->y);
12924
2bfb4627
ACO		 12925 ret = intel_set_mode(crtc, state);
12926 if (ret)
12927 drm_atomic_state_free(state);
c0c36b94
CW		 12928}
12929
25c5b266
DV		 12930#undef for_each_intel_crtc_masked
12931
b7885264
ACO		 12932static bool intel_connector_in_mode_set(struct intel_connector *connector,
12933 struct drm_mode_set *set)
12934{
12935 int ro;
12936
12937 for (ro = 0; ro < set->num_connectors; ro++)
12938 if (set->connectors[ro] == &connector->base)
12939 return true;
12940
12941 return false;
12942}
12943
2e431051 12944static int
9a935856
DV		 12945intel_modeset_stage_output_state(struct drm_device *dev,
12946 struct drm_mode_set *set,
944b0c76 12947 struct drm_atomic_state *state)
50f56119 12948{
9a935856 12949 struct intel_connector *connector;
d5432a9d 12950 struct drm_connector *drm_connector;
944b0c76 12951 struct drm_connector_state *connector_state;
d5432a9d
ACO		 12952 struct drm_crtc *crtc;
12953 struct drm_crtc_state *crtc_state;
12954 int i, ret;
50f56119 12955
9abdda74 12956 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 12957 * of connectors. For paranoia, double-check this. */
12958 WARN_ON(!set->fb && (set->num_connectors != 0));
12959 WARN_ON(set->fb && (set->num_connectors == 0));
12960
3a3371ff 12961 for_each_intel_connector(dev, connector) {
b7885264
ACO		 12962 bool in_mode_set = intel_connector_in_mode_set(connector, set);
12963
d5432a9d
ACO		 12964 if (!in_mode_set && connector->base.state->crtc != set->crtc)
12965 continue;
12966
12967 connector_state =
12968 drm_atomic_get_connector_state(state, &connector->base);
12969 if (IS_ERR(connector_state))
12970 return PTR_ERR(connector_state);
12971
b7885264
ACO		 12972 if (in_mode_set) {
12973 int pipe = to_intel_crtc(set->crtc)->pipe;
d5432a9d
ACO		 12974 connector_state->best_encoder =
12975 &intel_find_encoder(connector, pipe)->base;
50f56119
DV		 12976 }
12977
d5432a9d 12978 if (connector->base.state->crtc != set->crtc)
b7885264
ACO		 12979 continue;
12980
9a935856
DV		 12981 /* If we disable the crtc, disable all its connectors. Also, if
12982 * the connector is on the changing crtc but not on the new
12983 * connector list, disable it. */
b7885264 12984 if (!set->fb || !in_mode_set) {
d5432a9d 12985 connector_state->best_encoder = NULL;
9a935856
DV		 12986
12987 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
12988 connector->base.base.id,
c23cc417 12989 connector->base.name);
9a935856 12990 }
50f56119 12991 }
9a935856 12992 /* connector->new_encoder is now updated for all connectors. */
50f56119 12993
d5432a9d
ACO		 12994 for_each_connector_in_state(state, drm_connector, connector_state, i) {
12995 connector = to_intel_connector(drm_connector);
12996
12997 if (!connector_state->best_encoder) {
12998 ret = drm_atomic_set_crtc_for_connector(connector_state,
12999 NULL);
13000 if (ret)
13001 return ret;
7668851f 13002
50f56119 13003 continue;
d5432a9d 13004 }
50f56119 13005
d5432a9d
ACO		 13006 if (intel_connector_in_mode_set(connector, set)) {
13007 struct drm_crtc *crtc = connector->base.state->crtc;
13008
13009 /* If this connector was in a previous crtc, add it
13010 * to the state. We might need to disable it. */
13011 if (crtc) {
13012 crtc_state =
13013 drm_atomic_get_crtc_state(state, crtc);
13014 if (IS_ERR(crtc_state))
13015 return PTR_ERR(crtc_state);
13016 }
13017
13018 ret = drm_atomic_set_crtc_for_connector(connector_state,
13019 set->crtc);
13020 if (ret)
13021 return ret;
13022 }
50f56119
DV		 13023
13024 /* Make sure the new CRTC will work with the encoder */
d5432a9d
ACO		 13025 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
13026 connector_state->crtc)) {
5e2b584e 13027 return -EINVAL;
50f56119 13028 }
944b0c76 13029
9a935856
DV		 13030 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
13031 connector->base.base.id,
c23cc417 13032 connector->base.name,
d5432a9d 13033 connector_state->crtc->base.id);
944b0c76 13034
d5432a9d
ACO		 13035 if (connector_state->best_encoder != &connector->encoder->base)
13036 connector->encoder =
13037 to_intel_encoder(connector_state->best_encoder);
0e32b39c 13038 }
7668851f 13039
d5432a9d 13040 for_each_crtc_in_state(state, crtc, crtc_state, i) {
49d6fa21
ML		 13041 bool has_connectors;
13042
d5432a9d
ACO		 13043 ret = drm_atomic_add_affected_connectors(state, crtc);
13044 if (ret)
13045 return ret;
4be07317 13046
49d6fa21
ML		 13047 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
13048 if (has_connectors != crtc_state->enable)
13049 crtc_state->enable =
13050 crtc_state->active = has_connectors;
7668851f
VS		 13051 }
13052
8c7b5ccb
ACO		 13053 ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
13054 set->fb, set->x, set->y);
13055 if (ret)
13056 return ret;
13057
13058 crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
13059 if (IS_ERR(crtc_state))
13060 return PTR_ERR(crtc_state);
13061
13062 if (set->mode)
13063 drm_mode_copy(&crtc_state->mode, set->mode);
13064
13065 if (set->num_connectors)
13066 crtc_state->active = true;
13067
2e431051
DV		 13068 return 0;
13069}
13070
bb546623
ACO		 13071static bool primary_plane_visible(struct drm_crtc *crtc)
13072{
13073 struct intel_plane_state *plane_state =
13074 to_intel_plane_state(crtc->primary->state);
13075
13076 return plane_state->visible;
13077}
13078
2e431051
DV		 13079static int intel_crtc_set_config(struct drm_mode_set *set)
13080{
13081 struct drm_device *dev;
83a57153 13082 struct drm_atomic_state *state = NULL;
5cec258b 13083 struct intel_crtc_state *pipe_config;
bb546623 13084 bool primary_plane_was_visible;
2e431051 13085 int ret;
2e431051 13086
8d3e375e
DV		 13087 BUG_ON(!set);
13088 BUG_ON(!set->crtc);
13089 BUG_ON(!set->crtc->helper_private);
2e431051 13090
7e53f3a4
DV		 13091 /* Enforce sane interface api - has been abused by the fb helper. */
13092 BUG_ON(!set->mode && set->fb);
13093 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 13094
2e431051
DV		 13095 if (set->fb) {
13096 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
13097 set->crtc->base.id, set->fb->base.id,
13098 (int)set->num_connectors, set->x, set->y);
13099 } else {
13100 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 13101 }
13102
13103 dev = set->crtc->dev;
13104
83a57153 13105 state = drm_atomic_state_alloc(dev);
7cbf41d6
ACO		 13106 if (!state)
13107 return -ENOMEM;
83a57153
ACO		 13108
13109 state->acquire_ctx = dev->mode_config.acquire_ctx;
13110
462a425a 13111 ret = intel_modeset_stage_output_state(dev, set, state);
2e431051 13112 if (ret)
7cbf41d6 13113 goto out;
2e431051 13114
8c7b5ccb 13115 pipe_config = intel_modeset_compute_config(set->crtc, state);
20664591 13116 if (IS_ERR(pipe_config)) {
6ac0483b 13117 ret = PTR_ERR(pipe_config);
7cbf41d6 13118 goto out;
20664591 13119 }
50f52756 13120
1f9954d0
JB		 13121 intel_update_pipe_size(to_intel_crtc(set->crtc));
13122
bb546623
ACO		 13123 primary_plane_was_visible = primary_plane_visible(set->crtc);
13124
8c7b5ccb 13125 ret = intel_set_mode_with_config(set->crtc, pipe_config);
bb546623
ACO		 13126
13127 if (ret == 0 &&
13128 pipe_config->base.enable &&
13129 pipe_config->base.planes_changed &&
13130 !needs_modeset(&pipe_config->base)) {
3b150f08 13131 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
3b150f08
MR		 13132
13133 /*
13134 * We need to make sure the primary plane is re-enabled if it
13135 * has previously been turned off.
13136 */
bb546623
ACO		 13137 if (ret == 0 && !primary_plane_was_visible &&
13138 primary_plane_visible(set->crtc)) {
3b150f08 13139 WARN_ON(!intel_crtc->active);
87d4300a 13140 intel_post_enable_primary(set->crtc);
3b150f08
MR		 13141 }
13142
7ca51a3a
JB		 13143 /*
13144 * In the fastboot case this may be our only check of the
13145 * state after boot. It would be better to only do it on
13146 * the first update, but we don't have a nice way of doing that
13147 * (and really, set_config isn't used much for high freq page
13148 * flipping, so increasing its cost here shouldn't be a big
13149 * deal).
13150 */
d330a953 13151 if (i915.fastboot && ret == 0)
7ca51a3a 13152 intel_modeset_check_state(set->crtc->dev);
50f56119
DV		 13153 }
13154
2d05eae1 13155 if (ret) {
bf67dfeb
DV		 13156 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
13157 set->crtc->base.id, ret);
2d05eae1 13158 }
50f56119 13159
7cbf41d6 13160out:
2bfb4627
ACO		 13161 if (ret)
13162 drm_atomic_state_free(state);
50f56119
DV		 13163 return ret;
13164}
f6e5b160
CW		 13165
13166static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 13167 .gamma_set = intel_crtc_gamma_set,
50f56119 13168 .set_config = intel_crtc_set_config,
f6e5b160
CW		 13169 .destroy = intel_crtc_destroy,
13170 .page_flip = intel_crtc_page_flip,
1356837e
MR		 13171 .atomic_duplicate_state = intel_crtc_duplicate_state,
13172 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 13173};
13174
5358901f
DV		 13175static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13176 struct intel_shared_dpll *pll,
13177 struct intel_dpll_hw_state *hw_state)
ee7b9f93 13178{
5358901f 13179 uint32_t val;
ee7b9f93 13180
f458ebbc 13181 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 13182 return false;
13183
5358901f 13184 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 13185 hw_state->dpll = val;
13186 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13187 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 13188
13189 return val & DPLL_VCO_ENABLE;
13190}
13191
15bdd4cf
DV		 13192static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13193 struct intel_shared_dpll *pll)
13194{
3e369b76
ACO		 13195 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13196 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 13197}
13198
e7b903d2
DV		 13199static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13200 struct intel_shared_dpll *pll)
13201{
e7b903d2 13202 /* PCH refclock must be enabled first */
89eff4be 13203 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 13204
3e369b76 13205 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 13206
13207 /* Wait for the clocks to stabilize. */
13208 POSTING_READ(PCH_DPLL(pll->id));
13209 udelay(150);
13210
13211 /* The pixel multiplier can only be updated once the
13212 * DPLL is enabled and the clocks are stable.
13213 *
13214 * So write it again.
13215 */
3e369b76 13216 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 13217 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13218 udelay(200);
13219}
13220
13221static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13222 struct intel_shared_dpll *pll)
13223{
13224 struct drm_device *dev = dev_priv->dev;
13225 struct intel_crtc *crtc;
e7b903d2
DV		 13226
13227 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 13228 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 13229 if (intel_crtc_to_shared_dpll(crtc) == pll)
13230 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 13231 }
13232
15bdd4cf
DV		 13233 I915_WRITE(PCH_DPLL(pll->id), 0);
13234 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13235 udelay(200);
13236}
13237
46edb027
DV		 13238static char *ibx_pch_dpll_names[] = {
13239 "PCH DPLL A",
13240 "PCH DPLL B",
13241};
13242
7c74ade1 13243static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 13244{
e7b903d2 13245 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 13246 int i;
13247
7c74ade1 13248 dev_priv->num_shared_dpll = 2;
ee7b9f93 13249
e72f9fbf 13250 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 13251 dev_priv->shared_dplls[i].id = i;
13252 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 13253 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 13254 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13255 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 13256 dev_priv->shared_dplls[i].get_hw_state =
13257 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 13258 }
13259}
13260
7c74ade1
DV		 13261static void intel_shared_dpll_init(struct drm_device *dev)
13262{
e7b903d2 13263 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 13264
9cd86933
DV		 13265 if (HAS_DDI(dev))
13266 intel_ddi_pll_init(dev);
13267 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 13268 ibx_pch_dpll_init(dev);
13269 else
13270 dev_priv->num_shared_dpll = 0;
13271
13272 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 13273}
13274
1fc0a8f7
TU		 13275/**
13276 * intel_wm_need_update - Check whether watermarks need updating
13277 * @plane: drm plane
13278 * @state: new plane state
13279 *
13280 * Check current plane state versus the new one to determine whether
13281 * watermarks need to be recalculated.
13282 *
13283 * Returns true or false.
13284 */
13285bool intel_wm_need_update(struct drm_plane *plane,
13286 struct drm_plane_state *state)
13287{
13288 /* Update watermarks on tiling changes. */
13289 if (!plane->state->fb || !state->fb ||
13290 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
13291 plane->state->rotation != state->rotation)
13292 return true;
13293
13294 return false;
13295}
13296
6beb8c23
MR		 13297/**
13298 * intel_prepare_plane_fb - Prepare fb for usage on plane
13299 * @plane: drm plane to prepare for
13300 * @fb: framebuffer to prepare for presentation
13301 *
13302 * Prepares a framebuffer for usage on a display plane. Generally this
13303 * involves pinning the underlying object and updating the frontbuffer tracking
13304 * bits. Some older platforms need special physical address handling for
13305 * cursor planes.
13306 *
13307 * Returns 0 on success, negative error code on failure.
13308 */
13309int
13310intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13311 struct drm_framebuffer *fb,
13312 const struct drm_plane_state *new_state)
465c120c
MR		 13313{
13314 struct drm_device *dev = plane->dev;
6beb8c23
MR		 13315 struct intel_plane *intel_plane = to_intel_plane(plane);
13316 enum pipe pipe = intel_plane->pipe;
13317 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13318 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13319 unsigned frontbuffer_bits = 0;
13320 int ret = 0;
465c120c 13321
ea2c67bb 13322 if (!obj)
465c120c
MR		 13323 return 0;
13324
6beb8c23
MR		 13325 switch (plane->type) {
13326 case DRM_PLANE_TYPE_PRIMARY:
13327 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
13328 break;
13329 case DRM_PLANE_TYPE_CURSOR:
13330 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
13331 break;
13332 case DRM_PLANE_TYPE_OVERLAY:
13333 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
13334 break;
13335 }
465c120c 13336
6beb8c23 13337 mutex_lock(&dev->struct_mutex);
465c120c 13338
6beb8c23
MR		 13339 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13340 INTEL_INFO(dev)->cursor_needs_physical) {
13341 int align = IS_I830(dev) ? 16 * 1024 : 256;
13342 ret = i915_gem_object_attach_phys(obj, align);
13343 if (ret)
13344 DRM_DEBUG_KMS("failed to attach phys object\n");
13345 } else {
82bc3b2d 13346 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
6beb8c23 13347 }
465c120c 13348
6beb8c23
MR		 13349 if (ret == 0)
13350 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
fdd508a6 13351
4c34574f 13352 mutex_unlock(&dev->struct_mutex);
465c120c 13353
6beb8c23
MR		 13354 return ret;
13355}
13356
38f3ce3a
MR		 13357/**
13358 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13359 * @plane: drm plane to clean up for
13360 * @fb: old framebuffer that was on plane
13361 *
13362 * Cleans up a framebuffer that has just been removed from a plane.
13363 */
13364void
13365intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13366 struct drm_framebuffer *fb,
13367 const struct drm_plane_state *old_state)
38f3ce3a
MR		 13368{
13369 struct drm_device *dev = plane->dev;
13370 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13371
13372 if (WARN_ON(!obj))
13373 return;
13374
13375 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13376 !INTEL_INFO(dev)->cursor_needs_physical) {
13377 mutex_lock(&dev->struct_mutex);
82bc3b2d 13378 intel_unpin_fb_obj(fb, old_state);
38f3ce3a
MR		 13379 mutex_unlock(&dev->struct_mutex);
13380 }
465c120c
MR		 13381}
13382
6156a456
CK		 13383int
13384skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13385{
13386 int max_scale;
13387 struct drm_device *dev;
13388 struct drm_i915_private *dev_priv;
13389 int crtc_clock, cdclk;
13390
13391 if (!intel_crtc || !crtc_state)
13392 return DRM_PLANE_HELPER_NO_SCALING;
13393
13394 dev = intel_crtc->base.dev;
13395 dev_priv = dev->dev_private;
13396 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13397 cdclk = dev_priv->display.get_display_clock_speed(dev);
13398
13399 if (!crtc_clock || !cdclk)
13400 return DRM_PLANE_HELPER_NO_SCALING;
13401
13402 /*
13403 * skl max scale is lower of:
13404 * close to 3 but not 3, -1 is for that purpose
13405 * or
13406 * cdclk/crtc_clock
13407 */
13408 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13409
13410 return max_scale;
13411}
13412
465c120c 13413static int
3c692a41
GP		 13414intel_check_primary_plane(struct drm_plane *plane,
13415 struct intel_plane_state *state)
13416{
32b7eeec
MR		 13417 struct drm_device *dev = plane->dev;
13418 struct drm_i915_private *dev_priv = dev->dev_private;
2b875c22 13419 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 13420 struct intel_crtc *intel_crtc;
6156a456 13421 struct intel_crtc_state *crtc_state;
2b875c22 13422 struct drm_framebuffer *fb = state->base.fb;
3c692a41
GP		 13423 struct drm_rect *dest = &state->dst;
13424 struct drm_rect *src = &state->src;
13425 const struct drm_rect *clip = &state->clip;
d8106366 13426 bool can_position = false;
6156a456
CK		 13427 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13428 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
465c120c
MR		 13429 int ret;
13430
ea2c67bb
MR		 13431 crtc = crtc ? crtc : plane->crtc;
13432 intel_crtc = to_intel_crtc(crtc);
6156a456
CK		 13433 crtc_state = state->base.state ?
13434 intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL;
ea2c67bb 13435
6156a456 13436 if (INTEL_INFO(dev)->gen >= 9) {
225c228a
CK		 13437 /* use scaler when colorkey is not required */
13438 if (to_intel_plane(plane)->ckey.flags == I915_SET_COLORKEY_NONE) {
13439 min_scale = 1;
13440 max_scale = skl_max_scale(intel_crtc, crtc_state);
13441 }
d8106366 13442 can_position = true;
6156a456 13443 }
d8106366 13444
c59cb179
MR		 13445 ret = drm_plane_helper_check_update(plane, crtc, fb,
13446 src, dest, clip,
6156a456
CK		 13447 min_scale,
13448 max_scale,
d8106366
SJ		 13449 can_position, true,
13450 &state->visible);
c59cb179
MR		 13451 if (ret)
13452 return ret;
465c120c 13453
32b7eeec 13454 if (intel_crtc->active) {
b70709a6
ML		 13455 struct intel_plane_state *old_state =
13456 to_intel_plane_state(plane->state);
13457
32b7eeec
MR		 13458 intel_crtc->atomic.wait_for_flips = true;
13459
13460 /*
13461 * FBC does not work on some platforms for rotated
13462 * planes, so disable it when rotation is not 0 and
13463 * update it when rotation is set back to 0.
13464 *
13465 * FIXME: This is redundant with the fbc update done in
13466 * the primary plane enable function except that that
13467 * one is done too late. We eventually need to unify
13468 * this.
13469 */
b70709a6 13470 if (state->visible &&
32b7eeec 13471 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
e35fef21 13472 dev_priv->fbc.crtc == intel_crtc &&
8e7d688b 13473 state->base.rotation != BIT(DRM_ROTATE_0)) {
32b7eeec
MR		 13474 intel_crtc->atomic.disable_fbc = true;
13475 }
13476
b70709a6 13477 if (state->visible && !old_state->visible) {
32b7eeec
MR		 13478 /*
13479 * BDW signals flip done immediately if the plane
13480 * is disabled, even if the plane enable is already
13481 * armed to occur at the next vblank :(
13482 */
b70709a6 13483 if (IS_BROADWELL(dev))
32b7eeec
MR		 13484 intel_crtc->atomic.wait_vblank = true;
13485 }
13486
13487 intel_crtc->atomic.fb_bits |=
13488 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
13489
13490 intel_crtc->atomic.update_fbc = true;
0fda6568 13491
1fc0a8f7 13492 if (intel_wm_need_update(plane, &state->base))
0fda6568 13493 intel_crtc->atomic.update_wm = true;
ccc759dc
GP		 13494 }
13495
6156a456
CK		 13496 if (INTEL_INFO(dev)->gen >= 9) {
13497 ret = skl_update_scaler_users(intel_crtc, crtc_state,
13498 to_intel_plane(plane), state, 0);
13499 if (ret)
13500 return ret;
13501 }
13502
14af293f
GP		 13503 return 0;
13504}
13505
13506static void
13507intel_commit_primary_plane(struct drm_plane *plane,
13508 struct intel_plane_state *state)
13509{
2b875c22
MR		 13510 struct drm_crtc *crtc = state->base.crtc;
13511 struct drm_framebuffer *fb = state->base.fb;
13512 struct drm_device *dev = plane->dev;
14af293f 13513 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 13514 struct intel_crtc *intel_crtc;
14af293f
GP		 13515 struct drm_rect *src = &state->src;
13516
ea2c67bb
MR		 13517 crtc = crtc ? crtc : plane->crtc;
13518 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR		 13519
13520 plane->fb = fb;
9dc806fc
MR		 13521 crtc->x = src->x1 >> 16;
13522 crtc->y = src->y1 >> 16;
ccc759dc 13523
ccc759dc 13524 if (intel_crtc->active) {
27321ae8 13525 if (state->visible)
ccc759dc
GP		 13526 /* FIXME: kill this fastboot hack */
13527 intel_update_pipe_size(intel_crtc);
465c120c 13528
27321ae8
ML		 13529 dev_priv->display.update_primary_plane(crtc, plane->fb,
13530 crtc->x, crtc->y);
ccc759dc 13531 }
465c120c
MR		 13532}
13533
a8ad0d8e
ML		 13534static void
13535intel_disable_primary_plane(struct drm_plane *plane,
13536 struct drm_crtc *crtc,
13537 bool force)
13538{
13539 struct drm_device *dev = plane->dev;
13540 struct drm_i915_private *dev_priv = dev->dev_private;
13541
a8ad0d8e
ML		 13542 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13543}
13544
32b7eeec 13545static void intel_begin_crtc_commit(struct drm_crtc *crtc)
3c692a41 13546{
32b7eeec 13547 struct drm_device *dev = crtc->dev;
140fd38d 13548 struct drm_i915_private *dev_priv = dev->dev_private;
3c692a41 13549 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ea2c67bb
MR		 13550 struct intel_plane *intel_plane;
13551 struct drm_plane *p;
13552 unsigned fb_bits = 0;
13553
13554 /* Track fb's for any planes being disabled */
13555 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
13556 intel_plane = to_intel_plane(p);
13557
13558 if (intel_crtc->atomic.disabled_planes &
13559 (1 << drm_plane_index(p))) {
13560 switch (p->type) {
13561 case DRM_PLANE_TYPE_PRIMARY:
13562 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
13563 break;
13564 case DRM_PLANE_TYPE_CURSOR:
13565 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
13566 break;
13567 case DRM_PLANE_TYPE_OVERLAY:
13568 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
13569 break;
13570 }
3c692a41 13571
ea2c67bb
MR		 13572 mutex_lock(&dev->struct_mutex);
13573 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
13574 mutex_unlock(&dev->struct_mutex);
13575 }
13576 }
3c692a41 13577
32b7eeec
MR		 13578 if (intel_crtc->atomic.wait_for_flips)
13579 intel_crtc_wait_for_pending_flips(crtc);
3c692a41 13580
32b7eeec
MR		 13581 if (intel_crtc->atomic.disable_fbc)
13582 intel_fbc_disable(dev);
3c692a41 13583
32b7eeec
MR		 13584 if (intel_crtc->atomic.pre_disable_primary)
13585 intel_pre_disable_primary(crtc);
3c692a41 13586
32b7eeec
MR		 13587 if (intel_crtc->atomic.update_wm)
13588 intel_update_watermarks(crtc);
3c692a41 13589
32b7eeec 13590 intel_runtime_pm_get(dev_priv);
3c692a41 13591
c34c9ee4
MR		 13592 /* Perform vblank evasion around commit operation */
13593 if (intel_crtc->active)
13594 intel_crtc->atomic.evade =
13595 intel_pipe_update_start(intel_crtc,
13596 &intel_crtc->atomic.start_vbl_count);
32b7eeec
MR		 13597}
13598
13599static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13600{
13601 struct drm_device *dev = crtc->dev;
13602 struct drm_i915_private *dev_priv = dev->dev_private;
13603 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13604 struct drm_plane *p;
13605
c34c9ee4
MR		 13606 if (intel_crtc->atomic.evade)
13607 intel_pipe_update_end(intel_crtc,
13608 intel_crtc->atomic.start_vbl_count);
3c692a41 13609
140fd38d 13610 intel_runtime_pm_put(dev_priv);
3c692a41 13611
32b7eeec
MR		 13612 if (intel_crtc->atomic.wait_vblank)
13613 intel_wait_for_vblank(dev, intel_crtc->pipe);
13614
13615 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
13616
13617 if (intel_crtc->atomic.update_fbc) {
ccc759dc 13618 mutex_lock(&dev->struct_mutex);
7ff0ebcc 13619 intel_fbc_update(dev);
ccc759dc 13620 mutex_unlock(&dev->struct_mutex);
38f3ce3a 13621 }
3c692a41 13622
32b7eeec
MR		 13623 if (intel_crtc->atomic.post_enable_primary)
13624 intel_post_enable_primary(crtc);
3c692a41 13625
32b7eeec
MR		 13626 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
13627 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
13628 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
13629 false, false);
13630
13631 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
3c692a41
GP		 13632}
13633
cf4c7c12 13634/**
4a3b8769
MR		 13635 * intel_plane_destroy - destroy a plane
13636 * @plane: plane to destroy
cf4c7c12 13637 *
4a3b8769
MR		 13638 * Common destruction function for all types of planes (primary, cursor,
13639 * sprite).
cf4c7c12 13640 */
4a3b8769 13641void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 13642{
13643 struct intel_plane *intel_plane = to_intel_plane(plane);
13644 drm_plane_cleanup(plane);
13645 kfree(intel_plane);
13646}
13647
65a3fea0 13648const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR		 13649 .update_plane = drm_atomic_helper_update_plane,
13650 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13651 .destroy = intel_plane_destroy,
c196e1d6 13652 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 13653 .atomic_get_property = intel_plane_atomic_get_property,
13654 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 13655 .atomic_duplicate_state = intel_plane_duplicate_state,
13656 .atomic_destroy_state = intel_plane_destroy_state,
13657
465c120c
MR		 13658};
13659
13660static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13661 int pipe)
13662{
13663 struct intel_plane *primary;
8e7d688b 13664 struct intel_plane_state *state;
465c120c
MR		 13665 const uint32_t *intel_primary_formats;
13666 int num_formats;
13667
13668 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13669 if (primary == NULL)
13670 return NULL;
13671
8e7d688b
MR		 13672 state = intel_create_plane_state(&primary->base);
13673 if (!state) {
ea2c67bb
MR		 13674 kfree(primary);
13675 return NULL;
13676 }
8e7d688b 13677 primary->base.state = &state->base;
ea2c67bb 13678
465c120c
MR		 13679 primary->can_scale = false;
13680 primary->max_downscale = 1;
6156a456
CK		 13681 if (INTEL_INFO(dev)->gen >= 9) {
13682 primary->can_scale = true;
af99ceda 13683 state->scaler_id = -1;
6156a456 13684 }
465c120c
MR		 13685 primary->pipe = pipe;
13686 primary->plane = pipe;
c59cb179
MR		 13687 primary->check_plane = intel_check_primary_plane;
13688 primary->commit_plane = intel_commit_primary_plane;
a8ad0d8e 13689 primary->disable_plane = intel_disable_primary_plane;
08e221fb 13690 primary->ckey.flags = I915_SET_COLORKEY_NONE;
465c120c
MR		 13691 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13692 primary->plane = !pipe;
13693
6c0fd451
DL		 13694 if (INTEL_INFO(dev)->gen >= 9) {
13695 intel_primary_formats = skl_primary_formats;
13696 num_formats = ARRAY_SIZE(skl_primary_formats);
13697 } else if (INTEL_INFO(dev)->gen >= 4) {
568db4f2
DL		 13698 intel_primary_formats = i965_primary_formats;
13699 num_formats = ARRAY_SIZE(i965_primary_formats);
6c0fd451
DL		 13700 } else {
13701 intel_primary_formats = i8xx_primary_formats;
13702 num_formats = ARRAY_SIZE(i8xx_primary_formats);
465c120c
MR		 13703 }
13704
13705 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 13706 &intel_plane_funcs,
465c120c
MR		 13707 intel_primary_formats, num_formats,
13708 DRM_PLANE_TYPE_PRIMARY);
48404c1e 13709
3b7a5119
SJ		 13710 if (INTEL_INFO(dev)->gen >= 4)
13711 intel_create_rotation_property(dev, primary);
48404c1e 13712
ea2c67bb
MR		 13713 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13714
465c120c
MR		 13715 return &primary->base;
13716}
13717
3b7a5119
SJ		 13718void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13719{
13720 if (!dev->mode_config.rotation_property) {
13721 unsigned long flags = BIT(DRM_ROTATE_0) |
13722 BIT(DRM_ROTATE_180);
13723
13724 if (INTEL_INFO(dev)->gen >= 9)
13725 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13726
13727 dev->mode_config.rotation_property =
13728 drm_mode_create_rotation_property(dev, flags);
13729 }
13730 if (dev->mode_config.rotation_property)
13731 drm_object_attach_property(&plane->base.base,
13732 dev->mode_config.rotation_property,
13733 plane->base.state->rotation);
13734}
13735
3d7d6510 13736static int
852e787c
GP		 13737intel_check_cursor_plane(struct drm_plane *plane,
13738 struct intel_plane_state *state)
3d7d6510 13739{
2b875c22 13740 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 13741 struct drm_device *dev = plane->dev;
2b875c22 13742 struct drm_framebuffer *fb = state->base.fb;
852e787c
GP		 13743 struct drm_rect *dest = &state->dst;
13744 struct drm_rect *src = &state->src;
13745 const struct drm_rect *clip = &state->clip;
757f9a3e 13746 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
ea2c67bb 13747 struct intel_crtc *intel_crtc;
757f9a3e
GP		 13748 unsigned stride;
13749 int ret;
3d7d6510 13750
ea2c67bb
MR		 13751 crtc = crtc ? crtc : plane->crtc;
13752 intel_crtc = to_intel_crtc(crtc);
13753
757f9a3e 13754 ret = drm_plane_helper_check_update(plane, crtc, fb,
852e787c 13755 src, dest, clip,
3d7d6510
MR		 13756 DRM_PLANE_HELPER_NO_SCALING,
13757 DRM_PLANE_HELPER_NO_SCALING,
852e787c 13758 true, true, &state->visible);
757f9a3e
GP		 13759 if (ret)
13760 return ret;
13761
13762
13763 /* if we want to turn off the cursor ignore width and height */
13764 if (!obj)
32b7eeec 13765 goto finish;
757f9a3e 13766
757f9a3e 13767 /* Check for which cursor types we support */
ea2c67bb
MR		 13768 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
13769 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13770 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 13771 return -EINVAL;
13772 }
13773
ea2c67bb
MR		 13774 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13775 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 13776 DRM_DEBUG_KMS("buffer is too small\n");
13777 return -ENOMEM;
13778 }
13779
3a656b54 13780 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e
GP		 13781 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13782 ret = -EINVAL;
13783 }
757f9a3e 13784
32b7eeec
MR		 13785finish:
13786 if (intel_crtc->active) {
3749f463 13787 if (plane->state->crtc_w != state->base.crtc_w)
32b7eeec
MR		 13788 intel_crtc->atomic.update_wm = true;
13789
13790 intel_crtc->atomic.fb_bits |=
13791 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
13792 }
13793
757f9a3e 13794 return ret;
852e787c 13795}
3d7d6510 13796
a8ad0d8e
ML		 13797static void
13798intel_disable_cursor_plane(struct drm_plane *plane,
13799 struct drm_crtc *crtc,
13800 bool force)
13801{
13802 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13803
13804 if (!force) {
13805 plane->fb = NULL;
13806 intel_crtc->cursor_bo = NULL;
13807 intel_crtc->cursor_addr = 0;
13808 }
13809
13810 intel_crtc_update_cursor(crtc, false);
13811}
13812
f4a2cf29 13813static void
852e787c
GP		 13814intel_commit_cursor_plane(struct drm_plane *plane,
13815 struct intel_plane_state *state)
13816{
2b875c22 13817 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 13818 struct drm_device *dev = plane->dev;
13819 struct intel_crtc *intel_crtc;
2b875c22 13820 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 13821 uint32_t addr;
852e787c 13822
ea2c67bb
MR		 13823 crtc = crtc ? crtc : plane->crtc;
13824 intel_crtc = to_intel_crtc(crtc);
13825
2b875c22 13826 plane->fb = state->base.fb;
ea2c67bb
MR		 13827 crtc->cursor_x = state->base.crtc_x;
13828 crtc->cursor_y = state->base.crtc_y;
13829
a912f12f
GP		 13830 if (intel_crtc->cursor_bo == obj)
13831 goto update;
4ed91096 13832
f4a2cf29 13833 if (!obj)
a912f12f 13834 addr = 0;
f4a2cf29 13835 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 13836 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 13837 else
a912f12f 13838 addr = obj->phys_handle->busaddr;
852e787c 13839
a912f12f
GP		 13840 intel_crtc->cursor_addr = addr;
13841 intel_crtc->cursor_bo = obj;
13842update:
852e787c 13843
32b7eeec 13844 if (intel_crtc->active)
a912f12f 13845 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 13846}
13847
3d7d6510
MR		 13848static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13849 int pipe)
13850{
13851 struct intel_plane *cursor;
8e7d688b 13852 struct intel_plane_state *state;
3d7d6510
MR		 13853
13854 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13855 if (cursor == NULL)
13856 return NULL;
13857
8e7d688b
MR		 13858 state = intel_create_plane_state(&cursor->base);
13859 if (!state) {
ea2c67bb
MR		 13860 kfree(cursor);
13861 return NULL;
13862 }
8e7d688b 13863 cursor->base.state = &state->base;
ea2c67bb 13864
3d7d6510
MR		 13865 cursor->can_scale = false;
13866 cursor->max_downscale = 1;
13867 cursor->pipe = pipe;
13868 cursor->plane = pipe;
c59cb179
MR		 13869 cursor->check_plane = intel_check_cursor_plane;
13870 cursor->commit_plane = intel_commit_cursor_plane;
a8ad0d8e 13871 cursor->disable_plane = intel_disable_cursor_plane;
3d7d6510
MR		 13872
13873 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 13874 &intel_plane_funcs,
3d7d6510
MR		 13875 intel_cursor_formats,
13876 ARRAY_SIZE(intel_cursor_formats),
13877 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 13878
13879 if (INTEL_INFO(dev)->gen >= 4) {
13880 if (!dev->mode_config.rotation_property)
13881 dev->mode_config.rotation_property =
13882 drm_mode_create_rotation_property(dev,
13883 BIT(DRM_ROTATE_0) |
13884 BIT(DRM_ROTATE_180));
13885 if (dev->mode_config.rotation_property)
13886 drm_object_attach_property(&cursor->base.base,
13887 dev->mode_config.rotation_property,
8e7d688b 13888 state->base.rotation);
4398ad45
VS		 13889 }
13890
af99ceda
CK		 13891 if (INTEL_INFO(dev)->gen >=9)
13892 state->scaler_id = -1;
13893
ea2c67bb
MR		 13894 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13895
3d7d6510
MR		 13896 return &cursor->base;
13897}
13898
549e2bfb
CK		 13899static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13900 struct intel_crtc_state *crtc_state)
13901{
13902 int i;
13903 struct intel_scaler *intel_scaler;
13904 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13905
13906 for (i = 0; i < intel_crtc->num_scalers; i++) {
13907 intel_scaler = &scaler_state->scalers[i];
13908 intel_scaler->in_use = 0;
13909 intel_scaler->id = i;
13910
13911 intel_scaler->mode = PS_SCALER_MODE_DYN;
13912 }
13913
13914 scaler_state->scaler_id = -1;
13915}
13916
b358d0a6 13917static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 13918{
fbee40df 13919 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 13920 struct intel_crtc *intel_crtc;
f5de6e07 13921 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 13922 struct drm_plane *primary = NULL;
13923 struct drm_plane *cursor = NULL;
465c120c 13924 int i, ret;
79e53945 13925
955382f3 13926 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 13927 if (intel_crtc == NULL)
13928 return;
13929
f5de6e07
ACO		 13930 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13931 if (!crtc_state)
13932 goto fail;
550acefd
ACO		 13933 intel_crtc->config = crtc_state;
13934 intel_crtc->base.state = &crtc_state->base;
07878248 13935 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 13936
549e2bfb
CK		 13937 /* initialize shared scalers */
13938 if (INTEL_INFO(dev)->gen >= 9) {
13939 if (pipe == PIPE_C)
13940 intel_crtc->num_scalers = 1;
13941 else
13942 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13943
13944 skl_init_scalers(dev, intel_crtc, crtc_state);
13945 }
13946
465c120c 13947 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 13948 if (!primary)
13949 goto fail;
13950
13951 cursor = intel_cursor_plane_create(dev, pipe);
13952 if (!cursor)
13953 goto fail;
13954
465c120c 13955 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 13956 cursor, &intel_crtc_funcs);
13957 if (ret)
13958 goto fail;
79e53945
JB		 13959
13960 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 13961 for (i = 0; i < 256; i++) {
13962 intel_crtc->lut_r[i] = i;
13963 intel_crtc->lut_g[i] = i;
13964 intel_crtc->lut_b[i] = i;
13965 }
13966
1f1c2e24
VS		 13967 /*
13968 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 13969 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 13970 */
80824003
JB		 13971 intel_crtc->pipe = pipe;
13972 intel_crtc->plane = pipe;
3a77c4c4 13973 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 13974 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 13975 intel_crtc->plane = !pipe;
80824003
JB		 13976 }
13977
4b0e333e
CW		 13978 intel_crtc->cursor_base = ~0;
13979 intel_crtc->cursor_cntl = ~0;
dc41c154 13980 intel_crtc->cursor_size = ~0;
8d7849db 13981
22fd0fab
JB		 13982 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13983 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13984 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13985 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13986
79e53945 13987 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 13988
13989 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 13990 return;
13991
13992fail:
13993 if (primary)
13994 drm_plane_cleanup(primary);
13995 if (cursor)
13996 drm_plane_cleanup(cursor);
f5de6e07 13997 kfree(crtc_state);
3d7d6510 13998 kfree(intel_crtc);
79e53945
JB		 13999}
14000
752aa88a
JB		 14001enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14002{
14003 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 14004 struct drm_device *dev = connector->base.dev;
752aa88a 14005
51fd371b 14006 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 14007
d3babd3f 14008 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 14009 return INVALID_PIPE;
14010
14011 return to_intel_crtc(encoder->crtc)->pipe;
14012}
14013
08d7b3d1 14014int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 14015 struct drm_file *file)
08d7b3d1 14016{
08d7b3d1 14017 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 14018 struct drm_crtc *drmmode_crtc;
c05422d5 14019 struct intel_crtc *crtc;
08d7b3d1 14020
7707e653 14021 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 14022
7707e653 14023 if (!drmmode_crtc) {
08d7b3d1 14024 DRM_ERROR("no such CRTC id\n");
3f2c2057 14025 return -ENOENT;
08d7b3d1
CW		 14026 }
14027
7707e653 14028 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 14029 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 14030
c05422d5 14031 return 0;
08d7b3d1
CW		 14032}
14033
66a9278e 14034static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 14035{
66a9278e
DV		 14036 struct drm_device *dev = encoder->base.dev;
14037 struct intel_encoder *source_encoder;
79e53945 14038 int index_mask = 0;
79e53945
JB		 14039 int entry = 0;
14040
b2784e15 14041 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 14042 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 14043 index_mask |= (1 << entry);
14044
79e53945
JB		 14045 entry++;
14046 }
4ef69c7a 14047
79e53945
JB		 14048 return index_mask;
14049}
14050
4d302442
CW		 14051static bool has_edp_a(struct drm_device *dev)
14052{
14053 struct drm_i915_private *dev_priv = dev->dev_private;
14054
14055 if (!IS_MOBILE(dev))
14056 return false;
14057
14058 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14059 return false;
14060
e3589908 14061 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 14062 return false;
14063
14064 return true;
14065}
14066
84b4e042
JB		 14067static bool intel_crt_present(struct drm_device *dev)
14068{
14069 struct drm_i915_private *dev_priv = dev->dev_private;
14070
884497ed
DL		 14071 if (INTEL_INFO(dev)->gen >= 9)
14072 return false;
14073
cf404ce4 14074 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 14075 return false;
14076
14077 if (IS_CHERRYVIEW(dev))
14078 return false;
14079
14080 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14081 return false;
14082
14083 return true;
14084}
14085
79e53945
JB		 14086static void intel_setup_outputs(struct drm_device *dev)
14087{
725e30ad 14088 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 14089 struct intel_encoder *encoder;
cb0953d7 14090 bool dpd_is_edp = false;
79e53945 14091
c9093354 14092 intel_lvds_init(dev);
79e53945 14093
84b4e042 14094 if (intel_crt_present(dev))
79935fca 14095 intel_crt_init(dev);
cb0953d7 14096
c776eb2e
VK		 14097 if (IS_BROXTON(dev)) {
14098 /*
14099 * FIXME: Broxton doesn't support port detection via the
14100 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14101 * detect the ports.
14102 */
14103 intel_ddi_init(dev, PORT_A);
14104 intel_ddi_init(dev, PORT_B);
14105 intel_ddi_init(dev, PORT_C);
14106 } else if (HAS_DDI(dev)) {
0e72a5b5
ED		 14107 int found;
14108
de31facd
JB		 14109 /*
14110 * Haswell uses DDI functions to detect digital outputs.
14111 * On SKL pre-D0 the strap isn't connected, so we assume
14112 * it's there.
14113 */
0e72a5b5 14114 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
de31facd
JB		 14115 /* WaIgnoreDDIAStrap: skl */
14116 if (found ||
14117 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
0e72a5b5
ED		 14118 intel_ddi_init(dev, PORT_A);
14119
14120 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14121 * register */
14122 found = I915_READ(SFUSE_STRAP);
14123
14124 if (found & SFUSE_STRAP_DDIB_DETECTED)
14125 intel_ddi_init(dev, PORT_B);
14126 if (found & SFUSE_STRAP_DDIC_DETECTED)
14127 intel_ddi_init(dev, PORT_C);
14128 if (found & SFUSE_STRAP_DDID_DETECTED)
14129 intel_ddi_init(dev, PORT_D);
14130 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 14131 int found;
5d8a7752 14132 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 14133
14134 if (has_edp_a(dev))
14135 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 14136
dc0fa718 14137 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 14138 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 14139 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 14140 if (!found)
e2debe91 14141 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 14142 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 14143 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 14144 }
14145
dc0fa718 14146 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 14147 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 14148
dc0fa718 14149 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 14150 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 14151
5eb08b69 14152 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 14153 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 14154
270b3042 14155 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 14156 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 14157 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 14158 /*
14159 * The DP_DETECTED bit is the latched state of the DDC
14160 * SDA pin at boot. However since eDP doesn't require DDC
14161 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14162 * eDP ports may have been muxed to an alternate function.
14163 * Thus we can't rely on the DP_DETECTED bit alone to detect
14164 * eDP ports. Consult the VBT as well as DP_DETECTED to
14165 * detect eDP ports.
14166 */
d2182a66
VS		 14167 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14168 !intel_dp_is_edp(dev, PORT_B))
585a94b8
AB		 14169 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14170 PORT_B);
e17ac6db
VS		 14171 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14172 intel_dp_is_edp(dev, PORT_B))
14173 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
585a94b8 14174
d2182a66
VS		 14175 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14176 !intel_dp_is_edp(dev, PORT_C))
6f6005a5
JB		 14177 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14178 PORT_C);
e17ac6db
VS		 14179 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14180 intel_dp_is_edp(dev, PORT_C))
14181 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 14182
9418c1f1 14183 if (IS_CHERRYVIEW(dev)) {
e17ac6db 14184 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
9418c1f1
VS		 14185 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14186 PORT_D);
e17ac6db
VS		 14187 /* eDP not supported on port D, so don't check VBT */
14188 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14189 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
9418c1f1
VS		 14190 }
14191
3cfca973 14192 intel_dsi_init(dev);
103a196f 14193 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 14194 bool found = false;
7d57382e 14195
e2debe91 14196 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14197 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 14198 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 14199 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
14200 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 14201 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 14202 }
27185ae1 14203
e7281eab 14204 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 14205 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 14206 }
13520b05
KH		 14207
14208 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 14209
e2debe91 14210 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14211 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 14212 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 14213 }
27185ae1 14214
e2debe91 14215 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 14216
b01f2c3a
JB		 14217 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
14218 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 14219 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 14220 }
e7281eab 14221 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 14222 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 14223 }
27185ae1 14224
b01f2c3a 14225 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 14226 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 14227 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 14228 } else if (IS_GEN2(dev))
79e53945
JB		 14229 intel_dvo_init(dev);
14230
103a196f 14231 if (SUPPORTS_TV(dev))
79e53945
JB		 14232 intel_tv_init(dev);
14233
0bc12bcb 14234 intel_psr_init(dev);
7c8f8a70 14235
b2784e15 14236 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 14237 encoder->base.possible_crtcs = encoder->crtc_mask;
14238 encoder->base.possible_clones =
66a9278e 14239 intel_encoder_clones(encoder);
79e53945 14240 }
47356eb6 14241
dde86e2d 14242 intel_init_pch_refclk(dev);
270b3042
DV		 14243
14244 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 14245}
14246
14247static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14248{
60a5ca01 14249 struct drm_device *dev = fb->dev;
79e53945 14250 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 14251
ef2d633e 14252 drm_framebuffer_cleanup(fb);
60a5ca01 14253 mutex_lock(&dev->struct_mutex);
ef2d633e 14254 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 14255 drm_gem_object_unreference(&intel_fb->obj->base);
14256 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 14257 kfree(intel_fb);
14258}
14259
14260static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 14261 struct drm_file *file,
79e53945
JB		 14262 unsigned int *handle)
14263{
14264 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 14265 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 14266
05394f39 14267 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 14268}
14269
14270static const struct drm_framebuffer_funcs intel_fb_funcs = {
14271 .destroy = intel_user_framebuffer_destroy,
14272 .create_handle = intel_user_framebuffer_create_handle,
14273};
14274
b321803d
DL		 14275static
14276u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14277 uint32_t pixel_format)
14278{
14279 u32 gen = INTEL_INFO(dev)->gen;
14280
14281 if (gen >= 9) {
14282 /* "The stride in bytes must not exceed the of the size of 8K
14283 * pixels and 32K bytes."
14284 */
14285 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14286 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14287 return 32*1024;
14288 } else if (gen >= 4) {
14289 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14290 return 16*1024;
14291 else
14292 return 32*1024;
14293 } else if (gen >= 3) {
14294 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14295 return 8*1024;
14296 else
14297 return 16*1024;
14298 } else {
14299 /* XXX DSPC is limited to 4k tiled */
14300 return 8*1024;
14301 }
14302}
14303
b5ea642a
DV		 14304static int intel_framebuffer_init(struct drm_device *dev,
14305 struct intel_framebuffer *intel_fb,
14306 struct drm_mode_fb_cmd2 *mode_cmd,
14307 struct drm_i915_gem_object *obj)
79e53945 14308{
6761dd31 14309 unsigned int aligned_height;
79e53945 14310 int ret;
b321803d 14311 u32 pitch_limit, stride_alignment;
79e53945 14312
dd4916c5
DV		 14313 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14314
2a80eada
DV		 14315 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14316 /* Enforce that fb modifier and tiling mode match, but only for
14317 * X-tiled. This is needed for FBC. */
14318 if (!!(obj->tiling_mode == I915_TILING_X) !=
14319 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14320 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14321 return -EINVAL;
14322 }
14323 } else {
14324 if (obj->tiling_mode == I915_TILING_X)
14325 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14326 else if (obj->tiling_mode == I915_TILING_Y) {
14327 DRM_DEBUG("No Y tiling for legacy addfb\n");
14328 return -EINVAL;
14329 }
14330 }
14331
9a8f0a12
TU		 14332 /* Passed in modifier sanity checking. */
14333 switch (mode_cmd->modifier[0]) {
14334 case I915_FORMAT_MOD_Y_TILED:
14335 case I915_FORMAT_MOD_Yf_TILED:
14336 if (INTEL_INFO(dev)->gen < 9) {
14337 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14338 mode_cmd->modifier[0]);
14339 return -EINVAL;
14340 }
14341 case DRM_FORMAT_MOD_NONE:
14342 case I915_FORMAT_MOD_X_TILED:
14343 break;
14344 default:
c0f40428
JB		 14345 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14346 mode_cmd->modifier[0]);
57cd6508 14347 return -EINVAL;
c16ed4be 14348 }
57cd6508 14349
b321803d
DL		 14350 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14351 mode_cmd->pixel_format);
14352 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14353 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14354 mode_cmd->pitches[0], stride_alignment);
57cd6508 14355 return -EINVAL;
c16ed4be 14356 }
57cd6508 14357
b321803d
DL		 14358 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14359 mode_cmd->pixel_format);
a35cdaa0 14360 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 14361 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14362 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 14363 "tiled" : "linear",
a35cdaa0 14364 mode_cmd->pitches[0], pitch_limit);
5d7bd705 14365 return -EINVAL;
c16ed4be 14366 }
5d7bd705 14367
2a80eada 14368 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 14369 mode_cmd->pitches[0] != obj->stride) {
14370 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14371 mode_cmd->pitches[0], obj->stride);
5d7bd705 14372 return -EINVAL;
c16ed4be 14373 }
5d7bd705 14374
57779d06 14375 /* Reject formats not supported by any plane early. */
308e5bcb 14376 switch (mode_cmd->pixel_format) {
57779d06 14377 case DRM_FORMAT_C8:
04b3924d
VS		 14378 case DRM_FORMAT_RGB565:
14379 case DRM_FORMAT_XRGB8888:
14380 case DRM_FORMAT_ARGB8888:
57779d06
VS		 14381 break;
14382 case DRM_FORMAT_XRGB1555:
c16ed4be 14383 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 14384 DRM_DEBUG("unsupported pixel format: %s\n",
14385 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14386 return -EINVAL;
c16ed4be 14387 }
57779d06 14388 break;
57779d06 14389 case DRM_FORMAT_ABGR8888:
6c0fd451
DL		 14390 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14391 DRM_DEBUG("unsupported pixel format: %s\n",
14392 drm_get_format_name(mode_cmd->pixel_format));
14393 return -EINVAL;
14394 }
14395 break;
14396 case DRM_FORMAT_XBGR8888:
04b3924d 14397 case DRM_FORMAT_XRGB2101010:
57779d06 14398 case DRM_FORMAT_XBGR2101010:
c16ed4be 14399 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 14400 DRM_DEBUG("unsupported pixel format: %s\n",
14401 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14402 return -EINVAL;
c16ed4be 14403 }
b5626747 14404 break;
7531208b
DL		 14405 case DRM_FORMAT_ABGR2101010:
14406 if (!IS_VALLEYVIEW(dev)) {
14407 DRM_DEBUG("unsupported pixel format: %s\n",
14408 drm_get_format_name(mode_cmd->pixel_format));
14409 return -EINVAL;
14410 }
14411 break;
04b3924d
VS		 14412 case DRM_FORMAT_YUYV:
14413 case DRM_FORMAT_UYVY:
14414 case DRM_FORMAT_YVYU:
14415 case DRM_FORMAT_VYUY:
c16ed4be 14416 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 14417 DRM_DEBUG("unsupported pixel format: %s\n",
14418 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14419 return -EINVAL;
c16ed4be 14420 }
57cd6508
CW		 14421 break;
14422 default:
4ee62c76
VS		 14423 DRM_DEBUG("unsupported pixel format: %s\n",
14424 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 14425 return -EINVAL;
14426 }
14427
90f9a336
VS		 14428 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14429 if (mode_cmd->offsets[0] != 0)
14430 return -EINVAL;
14431
ec2c981e 14432 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 14433 mode_cmd->pixel_format,
14434 mode_cmd->modifier[0]);
53155c0a
DV		 14435 /* FIXME drm helper for size checks (especially planar formats)? */
14436 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14437 return -EINVAL;
14438
c7d73f6a
DV		 14439 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14440 intel_fb->obj = obj;
80075d49 14441 intel_fb->obj->framebuffer_references++;
c7d73f6a 14442
79e53945
JB		 14443 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14444 if (ret) {
14445 DRM_ERROR("framebuffer init failed %d\n", ret);
14446 return ret;
14447 }
14448
79e53945
JB		 14449 return 0;
14450}
14451
79e53945
JB		 14452static struct drm_framebuffer *
14453intel_user_framebuffer_create(struct drm_device *dev,
14454 struct drm_file *filp,
308e5bcb 14455 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 14456{
05394f39 14457 struct drm_i915_gem_object *obj;
79e53945 14458
308e5bcb
JB		 14459 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14460 mode_cmd->handles[0]));
c8725226 14461 if (&obj->base == NULL)
cce13ff7 14462 return ERR_PTR(-ENOENT);
79e53945 14463
d2dff872 14464 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 14465}
14466
4520f53a 14467#ifndef CONFIG_DRM_I915_FBDEV
0632fef6 14468static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 14469{
14470}
14471#endif
14472
79e53945 14473static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 14474 .fb_create = intel_user_framebuffer_create,
0632fef6 14475 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 14476 .atomic_check = intel_atomic_check,
14477 .atomic_commit = intel_atomic_commit,
79e53945
JB		 14478};
14479
e70236a8
JB		 14480/* Set up chip specific display functions */
14481static void intel_init_display(struct drm_device *dev)
14482{
14483 struct drm_i915_private *dev_priv = dev->dev_private;
14484
ee9300bb
DV		 14485 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14486 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 14487 else if (IS_CHERRYVIEW(dev))
14488 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 14489 else if (IS_VALLEYVIEW(dev))
14490 dev_priv->display.find_dpll = vlv_find_best_dpll;
14491 else if (IS_PINEVIEW(dev))
14492 dev_priv->display.find_dpll = pnv_find_best_dpll;
14493 else
14494 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14495
bc8d7dff
DL		 14496 if (INTEL_INFO(dev)->gen >= 9) {
14497 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14498 dev_priv->display.get_initial_plane_config =
14499 skylake_get_initial_plane_config;
bc8d7dff
DL		 14500 dev_priv->display.crtc_compute_clock =
14501 haswell_crtc_compute_clock;
14502 dev_priv->display.crtc_enable = haswell_crtc_enable;
14503 dev_priv->display.crtc_disable = haswell_crtc_disable;
14504 dev_priv->display.off = ironlake_crtc_off;
14505 dev_priv->display.update_primary_plane =
14506 skylake_update_primary_plane;
14507 } else if (HAS_DDI(dev)) {
0e8ffe1b 14508 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14509 dev_priv->display.get_initial_plane_config =
14510 ironlake_get_initial_plane_config;
797d0259
ACO		 14511 dev_priv->display.crtc_compute_clock =
14512 haswell_crtc_compute_clock;
4f771f10
PZ		 14513 dev_priv->display.crtc_enable = haswell_crtc_enable;
14514 dev_priv->display.crtc_disable = haswell_crtc_disable;
df8ad70c 14515 dev_priv->display.off = ironlake_crtc_off;
bc8d7dff
DL		 14516 dev_priv->display.update_primary_plane =
14517 ironlake_update_primary_plane;
09b4ddf9 14518 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 14519 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 14520 dev_priv->display.get_initial_plane_config =
14521 ironlake_get_initial_plane_config;
3fb37703
ACO		 14522 dev_priv->display.crtc_compute_clock =
14523 ironlake_crtc_compute_clock;
76e5a89c
DV		 14524 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14525 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 14526 dev_priv->display.off = ironlake_crtc_off;
262ca2b0
MR		 14527 dev_priv->display.update_primary_plane =
14528 ironlake_update_primary_plane;
89b667f8
JB		 14529 } else if (IS_VALLEYVIEW(dev)) {
14530 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14531 dev_priv->display.get_initial_plane_config =
14532 i9xx_get_initial_plane_config;
d6dfee7a 14533 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 14534 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14535 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14536 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR		 14537 dev_priv->display.update_primary_plane =
14538 i9xx_update_primary_plane;
f564048e 14539 } else {
0e8ffe1b 14540 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14541 dev_priv->display.get_initial_plane_config =
14542 i9xx_get_initial_plane_config;
d6dfee7a 14543 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 14544 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14545 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 14546 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR		 14547 dev_priv->display.update_primary_plane =
14548 i9xx_update_primary_plane;
f564048e 14549 }
e70236a8 14550
e70236a8 14551 /* Returns the core display clock speed */
1652d19e
VS		 14552 if (IS_SKYLAKE(dev))
14553 dev_priv->display.get_display_clock_speed =
14554 skylake_get_display_clock_speed;
14555 else if (IS_BROADWELL(dev))
14556 dev_priv->display.get_display_clock_speed =
14557 broadwell_get_display_clock_speed;
14558 else if (IS_HASWELL(dev))
14559 dev_priv->display.get_display_clock_speed =
14560 haswell_get_display_clock_speed;
14561 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB		 14562 dev_priv->display.get_display_clock_speed =
14563 valleyview_get_display_clock_speed;
b37a6434
VS		 14564 else if (IS_GEN5(dev))
14565 dev_priv->display.get_display_clock_speed =
14566 ilk_get_display_clock_speed;
a7c66cd8 14567 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
34edce2f 14568 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
e70236a8
JB		 14569 dev_priv->display.get_display_clock_speed =
14570 i945_get_display_clock_speed;
34edce2f
VS		 14571 else if (IS_GM45(dev))
14572 dev_priv->display.get_display_clock_speed =
14573 gm45_get_display_clock_speed;
14574 else if (IS_CRESTLINE(dev))
14575 dev_priv->display.get_display_clock_speed =
14576 i965gm_get_display_clock_speed;
14577 else if (IS_PINEVIEW(dev))
14578 dev_priv->display.get_display_clock_speed =
14579 pnv_get_display_clock_speed;
14580 else if (IS_G33(dev) || IS_G4X(dev))
14581 dev_priv->display.get_display_clock_speed =
14582 g33_get_display_clock_speed;
e70236a8
JB		 14583 else if (IS_I915G(dev))
14584 dev_priv->display.get_display_clock_speed =
14585 i915_get_display_clock_speed;
257a7ffc 14586 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 14587 dev_priv->display.get_display_clock_speed =
14588 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 14589 else if (IS_PINEVIEW(dev))
14590 dev_priv->display.get_display_clock_speed =
14591 pnv_get_display_clock_speed;
e70236a8
JB		 14592 else if (IS_I915GM(dev))
14593 dev_priv->display.get_display_clock_speed =
14594 i915gm_get_display_clock_speed;
14595 else if (IS_I865G(dev))
14596 dev_priv->display.get_display_clock_speed =
14597 i865_get_display_clock_speed;
f0f8a9ce 14598 else if (IS_I85X(dev))
e70236a8 14599 dev_priv->display.get_display_clock_speed =
1b1d2716 14600 i85x_get_display_clock_speed;
623e01e5
VS		 14601 else { /* 830 */
14602 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
e70236a8
JB		 14603 dev_priv->display.get_display_clock_speed =
14604 i830_get_display_clock_speed;
623e01e5 14605 }
e70236a8 14606
7c10a2b5 14607 if (IS_GEN5(dev)) {
3bb11b53 14608 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 14609 } else if (IS_GEN6(dev)) {
14610 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 14611 } else if (IS_IVYBRIDGE(dev)) {
14612 /* FIXME: detect B0+ stepping and use auto training */
14613 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 14614 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 14615 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
30a970c6
JB		 14616 } else if (IS_VALLEYVIEW(dev)) {
14617 dev_priv->display.modeset_global_resources =
14618 valleyview_modeset_global_resources;
f8437dd1
VK		 14619 } else if (IS_BROXTON(dev)) {
14620 dev_priv->display.modeset_global_resources =
14621 broxton_modeset_global_resources;
e70236a8 14622 }
8c9f3aaf 14623
8c9f3aaf
JB		 14624 switch (INTEL_INFO(dev)->gen) {
14625 case 2:
14626 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14627 break;
14628
14629 case 3:
14630 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14631 break;
14632
14633 case 4:
14634 case 5:
14635 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14636 break;
14637
14638 case 6:
14639 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14640 break;
7c9017e5 14641 case 7:
4e0bbc31 14642 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 14643 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14644 break;
830c81db 14645 case 9:
ba343e02
TU		 14646 /* Drop through - unsupported since execlist only. */
14647 default:
14648 /* Default just returns -ENODEV to indicate unsupported */
14649 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 14650 }
7bd688cd
JN		 14651
14652 intel_panel_init_backlight_funcs(dev);
e39b999a
VS		 14653
14654 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 14655}
14656
b690e96c
JB		 14657/*
14658 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14659 * resume, or other times. This quirk makes sure that's the case for
14660 * affected systems.
14661 */
0206e353 14662static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 14663{
14664 struct drm_i915_private *dev_priv = dev->dev_private;
14665
14666 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 14667 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 14668}
14669
b6b5d049
VS		 14670static void quirk_pipeb_force(struct drm_device *dev)
14671{
14672 struct drm_i915_private *dev_priv = dev->dev_private;
14673
14674 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14675 DRM_INFO("applying pipe b force quirk\n");
14676}
14677
435793df
KP		 14678/*
14679 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14680 */
14681static void quirk_ssc_force_disable(struct drm_device *dev)
14682{
14683 struct drm_i915_private *dev_priv = dev->dev_private;
14684 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 14685 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 14686}
14687
4dca20ef 14688/*
5a15ab5b
CE		 14689 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14690 * brightness value
4dca20ef
CE		 14691 */
14692static void quirk_invert_brightness(struct drm_device *dev)
14693{
14694 struct drm_i915_private *dev_priv = dev->dev_private;
14695 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 14696 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 14697}
14698
9c72cc6f
SD		 14699/* Some VBT's incorrectly indicate no backlight is present */
14700static void quirk_backlight_present(struct drm_device *dev)
14701{
14702 struct drm_i915_private *dev_priv = dev->dev_private;
14703 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14704 DRM_INFO("applying backlight present quirk\n");
14705}
14706
b690e96c
JB		 14707struct intel_quirk {
14708 int device;
14709 int subsystem_vendor;
14710 int subsystem_device;
14711 void (*hook)(struct drm_device *dev);
14712};
14713
5f85f176
EE		 14714/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14715struct intel_dmi_quirk {
14716 void (*hook)(struct drm_device *dev);
14717 const struct dmi_system_id (*dmi_id_list)[];
14718};
14719
14720static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14721{
14722 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14723 return 1;
14724}
14725
14726static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14727 {
14728 .dmi_id_list = &(const struct dmi_system_id[]) {
14729 {
14730 .callback = intel_dmi_reverse_brightness,
14731 .ident = "NCR Corporation",
14732 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14733 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14734 },
14735 },
14736 { } /* terminating entry */
14737 },
14738 .hook = quirk_invert_brightness,
14739 },
14740};
14741
c43b5634 14742static struct intel_quirk intel_quirks[] = {
b690e96c
JB		 14743 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14744 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14745
b690e96c
JB		 14746 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14747 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14748
5f080c0f
VS		 14749 /* 830 needs to leave pipe A & dpll A up */
14750 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14751
b6b5d049
VS		 14752 /* 830 needs to leave pipe B & dpll B up */
14753 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14754
435793df
KP		 14755 /* Lenovo U160 cannot use SSC on LVDS */
14756 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 14757
14758 /* Sony Vaio Y cannot use SSC on LVDS */
14759 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 14760
be505f64
AH		 14761 /* Acer Aspire 5734Z must invert backlight brightness */
14762 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14763
14764 /* Acer/eMachines G725 */
14765 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14766
14767 /* Acer/eMachines e725 */
14768 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14769
14770 /* Acer/Packard Bell NCL20 */
14771 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14772
14773 /* Acer Aspire 4736Z */
14774 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 14775
14776 /* Acer Aspire 5336 */
14777 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 14778
14779 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14780 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 14781
dfb3d47b
SD		 14782 /* Acer C720 Chromebook (Core i3 4005U) */
14783 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14784
b2a9601c 14785 /* Apple Macbook 2,1 (Core 2 T7400) */
14786 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14787
d4967d8c
SD		 14788 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14789 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 14790
14791 /* HP Chromebook 14 (Celeron 2955U) */
14792 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 14793
14794 /* Dell Chromebook 11 */
14795 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 14796};
14797
14798static void intel_init_quirks(struct drm_device *dev)
14799{
14800 struct pci_dev *d = dev->pdev;
14801 int i;
14802
14803 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14804 struct intel_quirk *q = &intel_quirks[i];
14805
14806 if (d->device == q->device &&
14807 (d->subsystem_vendor == q->subsystem_vendor ||
14808 q->subsystem_vendor == PCI_ANY_ID) &&
14809 (d->subsystem_device == q->subsystem_device ||
14810 q->subsystem_device == PCI_ANY_ID))
14811 q->hook(dev);
14812 }
5f85f176
EE		 14813 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14814 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14815 intel_dmi_quirks[i].hook(dev);
14816 }
b690e96c
JB		 14817}
14818
9cce37f4
JB		 14819/* Disable the VGA plane that we never use */
14820static void i915_disable_vga(struct drm_device *dev)
14821{
14822 struct drm_i915_private *dev_priv = dev->dev_private;
14823 u8 sr1;
766aa1c4 14824 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 14825
2b37c616 14826 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 14827 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 14828 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 14829 sr1 = inb(VGA_SR_DATA);
14830 outb(sr1 | 1<<5, VGA_SR_DATA);
14831 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14832 udelay(300);
14833
01f5a626 14834 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 14835 POSTING_READ(vga_reg);
14836}
14837
f817586c
DV		 14838void intel_modeset_init_hw(struct drm_device *dev)
14839{
a8f78b58
ED		 14840 intel_prepare_ddi(dev);
14841
f8bf63fd
VS		 14842 if (IS_VALLEYVIEW(dev))
14843 vlv_update_cdclk(dev);
14844
f817586c
DV		 14845 intel_init_clock_gating(dev);
14846
8090c6b9 14847 intel_enable_gt_powersave(dev);
f817586c
DV		 14848}
14849
79e53945
JB		 14850void intel_modeset_init(struct drm_device *dev)
14851{
652c393a 14852 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 14853 int sprite, ret;
8cc87b75 14854 enum pipe pipe;
46f297fb 14855 struct intel_crtc *crtc;
79e53945
JB		 14856
14857 drm_mode_config_init(dev);
14858
14859 dev->mode_config.min_width = 0;
14860 dev->mode_config.min_height = 0;
14861
019d96cb
DA		 14862 dev->mode_config.preferred_depth = 24;
14863 dev->mode_config.prefer_shadow = 1;
14864
25bab385
TU		 14865 dev->mode_config.allow_fb_modifiers = true;
14866
e6ecefaa 14867 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 14868
b690e96c
JB		 14869 intel_init_quirks(dev);
14870
1fa61106
ED		 14871 intel_init_pm(dev);
14872
e3c74757
BW		 14873 if (INTEL_INFO(dev)->num_pipes == 0)
14874 return;
14875
e70236a8 14876 intel_init_display(dev);
7c10a2b5 14877 intel_init_audio(dev);
e70236a8 14878
a6c45cf0
CW		 14879 if (IS_GEN2(dev)) {
14880 dev->mode_config.max_width = 2048;
14881 dev->mode_config.max_height = 2048;
14882 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 14883 dev->mode_config.max_width = 4096;
14884 dev->mode_config.max_height = 4096;
79e53945 14885 } else {
a6c45cf0
CW		 14886 dev->mode_config.max_width = 8192;
14887 dev->mode_config.max_height = 8192;
79e53945 14888 }
068be561 14889
dc41c154
VS		 14890 if (IS_845G(dev) || IS_I865G(dev)) {
14891 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14892 dev->mode_config.cursor_height = 1023;
14893 } else if (IS_GEN2(dev)) {
068be561
DL		 14894 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14895 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14896 } else {
14897 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14898 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14899 }
14900
5d4545ae 14901 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 14902
28c97730 14903 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 14904 INTEL_INFO(dev)->num_pipes,
14905 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 14906
055e393f 14907 for_each_pipe(dev_priv, pipe) {
8cc87b75 14908 intel_crtc_init(dev, pipe);
3bdcfc0c 14909 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 14910 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 14911 if (ret)
06da8da2 14912 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 14913 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 14914 }
79e53945
JB		 14915 }
14916
f42bb70d
JB		 14917 intel_init_dpio(dev);
14918
e72f9fbf 14919 intel_shared_dpll_init(dev);
ee7b9f93 14920
9cce37f4
JB		 14921 /* Just disable it once at startup */
14922 i915_disable_vga(dev);
79e53945 14923 intel_setup_outputs(dev);
11be49eb
CW		 14924
14925 /* Just in case the BIOS is doing something questionable. */
7ff0ebcc 14926 intel_fbc_disable(dev);
fa9fa083 14927
6e9f798d 14928 drm_modeset_lock_all(dev);
fa9fa083 14929 intel_modeset_setup_hw_state(dev, false);
6e9f798d 14930 drm_modeset_unlock_all(dev);
46f297fb 14931
d3fcc808 14932 for_each_intel_crtc(dev, crtc) {
46f297fb
JB		 14933 if (!crtc->active)
14934 continue;
14935
46f297fb 14936 /*
46f297fb
JB		 14937 * Note that reserving the BIOS fb up front prevents us
14938 * from stuffing other stolen allocations like the ring
14939 * on top. This prevents some ugliness at boot time, and
14940 * can even allow for smooth boot transitions if the BIOS
14941 * fb is large enough for the active pipe configuration.
14942 */
5724dbd1
DL		 14943 if (dev_priv->display.get_initial_plane_config) {
14944 dev_priv->display.get_initial_plane_config(crtc,
46f297fb
JB		 14945 &crtc->plane_config);
14946 /*
14947 * If the fb is shared between multiple heads, we'll
14948 * just get the first one.
14949 */
f6936e29 14950 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
46f297fb 14951 }
46f297fb 14952 }
2c7111db
CW		 14953}
14954
7fad798e
DV		 14955static void intel_enable_pipe_a(struct drm_device *dev)
14956{
14957 struct intel_connector *connector;
14958 struct drm_connector *crt = NULL;
14959 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 14960 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 14961
14962 /* We can't just switch on the pipe A, we need to set things up with a
14963 * proper mode and output configuration. As a gross hack, enable pipe A
14964 * by enabling the load detect pipe once. */
3a3371ff 14965 for_each_intel_connector(dev, connector) {
7fad798e
DV		 14966 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14967 crt = &connector->base;
14968 break;
14969 }
14970 }
14971
14972 if (!crt)
14973 return;
14974
208bf9fd 14975 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 14976 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 14977}
14978
fa555837
DV		 14979static bool
14980intel_check_plane_mapping(struct intel_crtc *crtc)
14981{
7eb552ae
BW		 14982 struct drm_device *dev = crtc->base.dev;
14983 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 14984 u32 reg, val;
14985
7eb552ae 14986 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 14987 return true;
14988
14989 reg = DSPCNTR(!crtc->plane);
14990 val = I915_READ(reg);
14991
14992 if ((val & DISPLAY_PLANE_ENABLE) &&
14993 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14994 return false;
14995
14996 return true;
14997}
14998
24929352
DV		 14999static void intel_sanitize_crtc(struct intel_crtc *crtc)
15000{
15001 struct drm_device *dev = crtc->base.dev;
15002 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 15003 u32 reg;
24929352 15004
24929352 15005 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 15006 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 15007 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15008
d3eaf884 15009 /* restore vblank interrupts to correct state */
9625604c 15010 drm_crtc_vblank_reset(&crtc->base);
d297e103
VS		 15011 if (crtc->active) {
15012 update_scanline_offset(crtc);
9625604c
DV		 15013 drm_crtc_vblank_on(&crtc->base);
15014 }
d3eaf884 15015
24929352 15016 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 15017 * disable the crtc (and hence change the state) if it is wrong. Note
15018 * that gen4+ has a fixed plane -> pipe mapping. */
15019 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 15020 struct intel_connector *connector;
15021 bool plane;
15022
24929352
DV		 15023 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15024 crtc->base.base.id);
15025
15026 /* Pipe has the wrong plane attached and the plane is active.
15027 * Temporarily change the plane mapping and disable everything
15028 * ... */
15029 plane = crtc->plane;
b70709a6 15030 to_intel_plane_state(crtc->base.primary->state)->visible = true;
24929352 15031 crtc->plane = !plane;
ce22dba9 15032 intel_crtc_disable_planes(&crtc->base);
24929352
DV		 15033 dev_priv->display.crtc_disable(&crtc->base);
15034 crtc->plane = plane;
15035
15036 /* ... and break all links. */
3a3371ff 15037 for_each_intel_connector(dev, connector) {
24929352
DV		 15038 if (connector->encoder->base.crtc != &crtc->base)
15039 continue;
15040
7f1950fb
EE		 15041 connector->base.dpms = DRM_MODE_DPMS_OFF;
15042 connector->base.encoder = NULL;
24929352 15043 }
7f1950fb
EE		 15044 /* multiple connectors may have the same encoder:
15045 * handle them and break crtc link separately */
3a3371ff 15046 for_each_intel_connector(dev, connector)
7f1950fb
EE		 15047 if (connector->encoder->base.crtc == &crtc->base) {
15048 connector->encoder->base.crtc = NULL;
15049 connector->encoder->connectors_active = false;
15050 }
24929352
DV		 15051
15052 WARN_ON(crtc->active);
83d65738 15053 crtc->base.state->enable = false;
49d6fa21 15054 crtc->base.state->active = false;
24929352
DV		 15055 crtc->base.enabled = false;
15056 }
24929352 15057
7fad798e
DV		 15058 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15059 crtc->pipe == PIPE_A && !crtc->active) {
15060 /* BIOS forgot to enable pipe A, this mostly happens after
15061 * resume. Force-enable the pipe to fix this, the update_dpms
15062 * call below we restore the pipe to the right state, but leave
15063 * the required bits on. */
15064 intel_enable_pipe_a(dev);
15065 }
15066
24929352
DV		 15067 /* Adjust the state of the output pipe according to whether we
15068 * have active connectors/encoders. */
15069 intel_crtc_update_dpms(&crtc->base);
15070
83d65738 15071 if (crtc->active != crtc->base.state->enable) {
24929352
DV		 15072 struct intel_encoder *encoder;
15073
15074 /* This can happen either due to bugs in the get_hw_state
15075 * functions or because the pipe is force-enabled due to the
15076 * pipe A quirk. */
15077 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15078 crtc->base.base.id,
83d65738 15079 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 15080 crtc->active ? "enabled" : "disabled");
15081
83d65738 15082 crtc->base.state->enable = crtc->active;
49d6fa21 15083 crtc->base.state->active = crtc->active;
24929352
DV		 15084 crtc->base.enabled = crtc->active;
15085
15086 /* Because we only establish the connector -> encoder ->
15087 * crtc links if something is active, this means the
15088 * crtc is now deactivated. Break the links. connector
15089 * -> encoder links are only establish when things are
15090 * actually up, hence no need to break them. */
15091 WARN_ON(crtc->active);
15092
15093 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
15094 WARN_ON(encoder->connectors_active);
15095 encoder->base.crtc = NULL;
15096 }
15097 }
c5ab3bc0 15098
a3ed6aad 15099 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 15100 /*
15101 * We start out with underrun reporting disabled to avoid races.
15102 * For correct bookkeeping mark this on active crtcs.
15103 *
c5ab3bc0
DV		 15104 * Also on gmch platforms we dont have any hardware bits to
15105 * disable the underrun reporting. Which means we need to start
15106 * out with underrun reporting disabled also on inactive pipes,
15107 * since otherwise we'll complain about the garbage we read when
15108 * e.g. coming up after runtime pm.
15109 *
4cc31489
DV		 15110 * No protection against concurrent access is required - at
15111 * worst a fifo underrun happens which also sets this to false.
15112 */
15113 crtc->cpu_fifo_underrun_disabled = true;
15114 crtc->pch_fifo_underrun_disabled = true;
15115 }
24929352
DV		 15116}
15117
15118static void intel_sanitize_encoder(struct intel_encoder *encoder)
15119{
15120 struct intel_connector *connector;
15121 struct drm_device *dev = encoder->base.dev;
15122
15123 /* We need to check both for a crtc link (meaning that the
15124 * encoder is active and trying to read from a pipe) and the
15125 * pipe itself being active. */
15126 bool has_active_crtc = encoder->base.crtc &&
15127 to_intel_crtc(encoder->base.crtc)->active;
15128
15129 if (encoder->connectors_active && !has_active_crtc) {
15130 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15131 encoder->base.base.id,
8e329a03 15132 encoder->base.name);
24929352
DV		 15133
15134 /* Connector is active, but has no active pipe. This is
15135 * fallout from our resume register restoring. Disable
15136 * the encoder manually again. */
15137 if (encoder->base.crtc) {
15138 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15139 encoder->base.base.id,
8e329a03 15140 encoder->base.name);
24929352 15141 encoder->disable(encoder);
a62d1497
VS		 15142 if (encoder->post_disable)
15143 encoder->post_disable(encoder);
24929352 15144 }
7f1950fb
EE		 15145 encoder->base.crtc = NULL;
15146 encoder->connectors_active = false;
24929352
DV		 15147
15148 /* Inconsistent output/port/pipe state happens presumably due to
15149 * a bug in one of the get_hw_state functions. Or someplace else
15150 * in our code, like the register restore mess on resume. Clamp
15151 * things to off as a safer default. */
3a3371ff 15152 for_each_intel_connector(dev, connector) {
24929352
DV		 15153 if (connector->encoder != encoder)
15154 continue;
7f1950fb
EE		 15155 connector->base.dpms = DRM_MODE_DPMS_OFF;
15156 connector->base.encoder = NULL;
24929352
DV		 15157 }
15158 }
15159 /* Enabled encoders without active connectors will be fixed in
15160 * the crtc fixup. */
15161}
15162
04098753 15163void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 15164{
15165 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 15166 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 15167
04098753
ID		 15168 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15169 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15170 i915_disable_vga(dev);
15171 }
15172}
15173
15174void i915_redisable_vga(struct drm_device *dev)
15175{
15176 struct drm_i915_private *dev_priv = dev->dev_private;
15177
8dc8a27c
PZ		 15178 /* This function can be called both from intel_modeset_setup_hw_state or
15179 * at a very early point in our resume sequence, where the power well
15180 * structures are not yet restored. Since this function is at a very
15181 * paranoid "someone might have enabled VGA while we were not looking"
15182 * level, just check if the power well is enabled instead of trying to
15183 * follow the "don't touch the power well if we don't need it" policy
15184 * the rest of the driver uses. */
f458ebbc 15185 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 15186 return;
15187
04098753 15188 i915_redisable_vga_power_on(dev);
0fde901f
KM		 15189}
15190
98ec7739
VS		 15191static bool primary_get_hw_state(struct intel_crtc *crtc)
15192{
15193 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15194
15195 if (!crtc->active)
15196 return false;
15197
15198 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
15199}
15200
30e984df 15201static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 15202{
15203 struct drm_i915_private *dev_priv = dev->dev_private;
15204 enum pipe pipe;
24929352
DV		 15205 struct intel_crtc *crtc;
15206 struct intel_encoder *encoder;
15207 struct intel_connector *connector;
5358901f 15208 int i;
24929352 15209
d3fcc808 15210 for_each_intel_crtc(dev, crtc) {
b70709a6
ML		 15211 struct drm_plane *primary = crtc->base.primary;
15212 struct intel_plane_state *plane_state;
15213
6e3c9717 15214 memset(crtc->config, 0, sizeof(*crtc->config));
3b117c8f 15215
6e3c9717 15216 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
9953599b 15217
0e8ffe1b 15218 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 15219 crtc->config);
24929352 15220
83d65738 15221 crtc->base.state->enable = crtc->active;
49d6fa21 15222 crtc->base.state->active = crtc->active;
24929352 15223 crtc->base.enabled = crtc->active;
b70709a6
ML		 15224
15225 plane_state = to_intel_plane_state(primary->state);
15226 plane_state->visible = primary_get_hw_state(crtc);
24929352
DV		 15227
15228 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15229 crtc->base.base.id,
15230 crtc->active ? "enabled" : "disabled");
15231 }
15232
5358901f
DV		 15233 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15234 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15235
3e369b76
ACO		 15236 pll->on = pll->get_hw_state(dev_priv, pll,
15237 &pll->config.hw_state);
5358901f 15238 pll->active = 0;
3e369b76 15239 pll->config.crtc_mask = 0;
d3fcc808 15240 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 15241 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 15242 pll->active++;
3e369b76 15243 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 15244 }
5358901f 15245 }
5358901f 15246
1e6f2ddc 15247 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 15248 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 15249
3e369b76 15250 if (pll->config.crtc_mask)
bd2bb1b9 15251 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 15252 }
15253
b2784e15 15254 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15255 pipe = 0;
15256
15257 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 15258 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15259 encoder->base.crtc = &crtc->base;
6e3c9717 15260 encoder->get_config(encoder, crtc->config);
24929352
DV		 15261 } else {
15262 encoder->base.crtc = NULL;
15263 }
15264
15265 encoder->connectors_active = false;
6f2bcceb 15266 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 15267 encoder->base.base.id,
8e329a03 15268 encoder->base.name,
24929352 15269 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 15270 pipe_name(pipe));
24929352
DV		 15271 }
15272
3a3371ff 15273 for_each_intel_connector(dev, connector) {
24929352
DV		 15274 if (connector->get_hw_state(connector)) {
15275 connector->base.dpms = DRM_MODE_DPMS_ON;
15276 connector->encoder->connectors_active = true;
15277 connector->base.encoder = &connector->encoder->base;
15278 } else {
15279 connector->base.dpms = DRM_MODE_DPMS_OFF;
15280 connector->base.encoder = NULL;
15281 }
15282 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15283 connector->base.base.id,
c23cc417 15284 connector->base.name,
24929352
DV		 15285 connector->base.encoder ? "enabled" : "disabled");
15286 }
30e984df
DV		 15287}
15288
15289/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15290 * and i915 state tracking structures. */
15291void intel_modeset_setup_hw_state(struct drm_device *dev,
15292 bool force_restore)
15293{
15294 struct drm_i915_private *dev_priv = dev->dev_private;
15295 enum pipe pipe;
30e984df
DV		 15296 struct intel_crtc *crtc;
15297 struct intel_encoder *encoder;
35c95375 15298 int i;
30e984df
DV		 15299
15300 intel_modeset_readout_hw_state(dev);
24929352 15301
babea61d
JB		 15302 /*
15303 * Now that we have the config, copy it to each CRTC struct
15304 * Note that this could go away if we move to using crtc_config
15305 * checking everywhere.
15306 */
d3fcc808 15307 for_each_intel_crtc(dev, crtc) {
d330a953 15308 if (crtc->active && i915.fastboot) {
6e3c9717
ACO		 15309 intel_mode_from_pipe_config(&crtc->base.mode,
15310 crtc->config);
babea61d
JB		 15311 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15312 crtc->base.base.id);
15313 drm_mode_debug_printmodeline(&crtc->base.mode);
15314 }
15315 }
15316
24929352 15317 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 15318 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15319 intel_sanitize_encoder(encoder);
15320 }
15321
055e393f 15322 for_each_pipe(dev_priv, pipe) {
24929352
DV		 15323 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15324 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 15325 intel_dump_pipe_config(crtc, crtc->config,
15326 "[setup_hw_state]");
24929352 15327 }
9a935856 15328
d29b2f9d
ACO		 15329 intel_modeset_update_connector_atomic_state(dev);
15330
35c95375
DV		 15331 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15332 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15333
15334 if (!pll->on || pll->active)
15335 continue;
15336
15337 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15338
15339 pll->disable(dev_priv, pll);
15340 pll->on = false;
15341 }
15342
3078999f
PB		 15343 if (IS_GEN9(dev))
15344 skl_wm_get_hw_state(dev);
15345 else if (HAS_PCH_SPLIT(dev))
243e6a44
VS		 15346 ilk_wm_get_hw_state(dev);
15347
45e2b5f6 15348 if (force_restore) {
7d0bc1ea
VS		 15349 i915_redisable_vga(dev);
15350
f30da187
DV		 15351 /*
15352 * We need to use raw interfaces for restoring state to avoid
15353 * checking (bogus) intermediate states.
15354 */
055e393f 15355 for_each_pipe(dev_priv, pipe) {
b5644d05
JB		 15356 struct drm_crtc *crtc =
15357 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187 15358
83a57153 15359 intel_crtc_restore_mode(crtc);
45e2b5f6
DV		 15360 }
15361 } else {
15362 intel_modeset_update_staged_output_state(dev);
15363 }
8af6cf88
DV		 15364
15365 intel_modeset_check_state(dev);
2c7111db
CW		 15366}
15367
15368void intel_modeset_gem_init(struct drm_device *dev)
15369{
92122789 15370 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd 15371 struct drm_crtc *c;
2ff8fde1 15372 struct drm_i915_gem_object *obj;
e0d6149b 15373 int ret;
484b41dd 15374
ae48434c
ID		 15375 mutex_lock(&dev->struct_mutex);
15376 intel_init_gt_powersave(dev);
15377 mutex_unlock(&dev->struct_mutex);
15378
92122789
JB		 15379 /*
15380 * There may be no VBT; and if the BIOS enabled SSC we can
15381 * just keep using it to avoid unnecessary flicker. Whereas if the
15382 * BIOS isn't using it, don't assume it will work even if the VBT
15383 * indicates as much.
15384 */
15385 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15386 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15387 DREF_SSC1_ENABLE);
15388
1833b134 15389 intel_modeset_init_hw(dev);
02e792fb
DV		 15390
15391 intel_setup_overlay(dev);
484b41dd
JB		 15392
15393 /*
15394 * Make sure any fbs we allocated at startup are properly
15395 * pinned & fenced. When we do the allocation it's too early
15396 * for this.
15397 */
70e1e0ec 15398 for_each_crtc(dev, c) {
2ff8fde1
MR		 15399 obj = intel_fb_obj(c->primary->fb);
15400 if (obj == NULL)
484b41dd
JB		 15401 continue;
15402
e0d6149b
TU		 15403 mutex_lock(&dev->struct_mutex);
15404 ret = intel_pin_and_fence_fb_obj(c->primary,
15405 c->primary->fb,
15406 c->primary->state,
15407 NULL);
15408 mutex_unlock(&dev->struct_mutex);
15409 if (ret) {
484b41dd
JB		 15410 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15411 to_intel_crtc(c)->pipe);
66e514c1
DA		 15412 drm_framebuffer_unreference(c->primary->fb);
15413 c->primary->fb = NULL;
afd65eb4 15414 update_state_fb(c->primary);
484b41dd
JB		 15415 }
15416 }
0962c3c9
VS		 15417
15418 intel_backlight_register(dev);
79e53945
JB		 15419}
15420
4932e2c3
ID		 15421void intel_connector_unregister(struct intel_connector *intel_connector)
15422{
15423 struct drm_connector *connector = &intel_connector->base;
15424
15425 intel_panel_destroy_backlight(connector);
34ea3d38 15426 drm_connector_unregister(connector);
4932e2c3
ID		 15427}
15428
79e53945
JB		 15429void intel_modeset_cleanup(struct drm_device *dev)
15430{
652c393a 15431 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 15432 struct drm_connector *connector;
652c393a 15433
2eb5252e
ID		 15434 intel_disable_gt_powersave(dev);
15435
0962c3c9
VS		 15436 intel_backlight_unregister(dev);
15437
fd0c0642
DV		 15438 /*
15439 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 15440 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 15441 * experience fancy races otherwise.
15442 */
2aeb7d3a 15443 intel_irq_uninstall(dev_priv);
eb21b92b 15444
fd0c0642
DV		 15445 /*
15446 * Due to the hpd irq storm handling the hotplug work can re-arm the
15447 * poll handlers. Hence disable polling after hpd handling is shut down.
15448 */
f87ea761 15449 drm_kms_helper_poll_fini(dev);
fd0c0642 15450
652c393a
JB		 15451 mutex_lock(&dev->struct_mutex);
15452
723bfd70
JB		 15453 intel_unregister_dsm_handler();
15454
7ff0ebcc 15455 intel_fbc_disable(dev);
e70236a8 15456
69341a5e
KH		 15457 mutex_unlock(&dev->struct_mutex);
15458
1630fe75
CW		 15459 /* flush any delayed tasks or pending work */
15460 flush_scheduled_work();
15461
db31af1d
JN		 15462 /* destroy the backlight and sysfs files before encoders/connectors */
15463 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 15464 struct intel_connector *intel_connector;
15465
15466 intel_connector = to_intel_connector(connector);
15467 intel_connector->unregister(intel_connector);
db31af1d 15468 }
d9255d57 15469
79e53945 15470 drm_mode_config_cleanup(dev);
4d7bb011
DV		 15471
15472 intel_cleanup_overlay(dev);
ae48434c
ID		 15473
15474 mutex_lock(&dev->struct_mutex);
15475 intel_cleanup_gt_powersave(dev);
15476 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 15477}
15478
f1c79df3
ZW		 15479/*
15480 * Return which encoder is currently attached for connector.
15481 */
df0e9248 15482struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 15483{
df0e9248
CW		 15484 return &intel_attached_encoder(connector)->base;
15485}
f1c79df3 15486
df0e9248
CW		 15487void intel_connector_attach_encoder(struct intel_connector *connector,
15488 struct intel_encoder *encoder)
15489{
15490 connector->encoder = encoder;
15491 drm_mode_connector_attach_encoder(&connector->base,
15492 &encoder->base);
79e53945 15493}
28d52043
DA		 15494
15495/*
15496 * set vga decode state - true == enable VGA decode
15497 */
15498int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15499{
15500 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 15501 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 15502 u16 gmch_ctrl;
15503
75fa041d
CW		 15504 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15505 DRM_ERROR("failed to read control word\n");
15506 return -EIO;
15507 }
15508
c0cc8a55
CW		 15509 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15510 return 0;
15511
28d52043
DA		 15512 if (state)
15513 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15514 else
15515 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 15516
15517 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15518 DRM_ERROR("failed to write control word\n");
15519 return -EIO;
15520 }
15521
28d52043
DA		 15522 return 0;
15523}
c4a1d9e4 15524
c4a1d9e4 15525struct intel_display_error_state {
ff57f1b0
PZ		 15526
15527 u32 power_well_driver;
15528
63b66e5b
CW		 15529 int num_transcoders;
15530
c4a1d9e4
CW		 15531 struct intel_cursor_error_state {
15532 u32 control;
15533 u32 position;
15534 u32 base;
15535 u32 size;
52331309 15536 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 15537
15538 struct intel_pipe_error_state {
ddf9c536 15539 bool power_domain_on;
c4a1d9e4 15540 u32 source;
f301b1e1 15541 u32 stat;
52331309 15542 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 15543
15544 struct intel_plane_error_state {
15545 u32 control;
15546 u32 stride;
15547 u32 size;
15548 u32 pos;
15549 u32 addr;
15550 u32 surface;
15551 u32 tile_offset;
52331309 15552 } plane[I915_MAX_PIPES];
63b66e5b
CW		 15553
15554 struct intel_transcoder_error_state {
ddf9c536 15555 bool power_domain_on;
63b66e5b
CW		 15556 enum transcoder cpu_transcoder;
15557
15558 u32 conf;
15559
15560 u32 htotal;
15561 u32 hblank;
15562 u32 hsync;
15563 u32 vtotal;
15564 u32 vblank;
15565 u32 vsync;
15566 } transcoder[4];
c4a1d9e4
CW		 15567};
15568
15569struct intel_display_error_state *
15570intel_display_capture_error_state(struct drm_device *dev)
15571{
fbee40df 15572 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 15573 struct intel_display_error_state *error;
63b66e5b
CW		 15574 int transcoders[] = {
15575 TRANSCODER_A,
15576 TRANSCODER_B,
15577 TRANSCODER_C,
15578 TRANSCODER_EDP,
15579 };
c4a1d9e4
CW		 15580 int i;
15581
63b66e5b
CW		 15582 if (INTEL_INFO(dev)->num_pipes == 0)
15583 return NULL;
15584
9d1cb914 15585 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 15586 if (error == NULL)
15587 return NULL;
15588
190be112 15589 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 15590 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15591
055e393f 15592 for_each_pipe(dev_priv, i) {
ddf9c536 15593 error->pipe[i].power_domain_on =
f458ebbc
DV		 15594 __intel_display_power_is_enabled(dev_priv,
15595 POWER_DOMAIN_PIPE(i));
ddf9c536 15596 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 15597 continue;
15598
5efb3e28
VS		 15599 error->cursor[i].control = I915_READ(CURCNTR(i));
15600 error->cursor[i].position = I915_READ(CURPOS(i));
15601 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 15602
15603 error->plane[i].control = I915_READ(DSPCNTR(i));
15604 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 15605 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 15606 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 15607 error->plane[i].pos = I915_READ(DSPPOS(i));
15608 }
ca291363
PZ		 15609 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15610 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 15611 if (INTEL_INFO(dev)->gen >= 4) {
15612 error->plane[i].surface = I915_READ(DSPSURF(i));
15613 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15614 }
15615
c4a1d9e4 15616 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 15617
3abfce77 15618 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 15619 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 15620 }
15621
15622 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15623 if (HAS_DDI(dev_priv->dev))
15624 error->num_transcoders++; /* Account for eDP. */
15625
15626 for (i = 0; i < error->num_transcoders; i++) {
15627 enum transcoder cpu_transcoder = transcoders[i];
15628
ddf9c536 15629 error->transcoder[i].power_domain_on =
f458ebbc 15630 __intel_display_power_is_enabled(dev_priv,
38cc1daf 15631 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 15632 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 15633 continue;
15634
63b66e5b
CW		 15635 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15636
15637 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15638 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15639 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15640 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15641 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15642 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15643 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 15644 }
15645
15646 return error;
15647}
15648
edc3d884
MK		 15649#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15650
c4a1d9e4 15651void
edc3d884 15652intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 15653 struct drm_device *dev,
15654 struct intel_display_error_state *error)
15655{
055e393f 15656 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 15657 int i;
15658
63b66e5b
CW		 15659 if (!error)
15660 return;
15661
edc3d884 15662 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 15663 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 15664 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 15665 error->power_well_driver);
055e393f 15666 for_each_pipe(dev_priv, i) {
edc3d884 15667 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 15668 err_printf(m, " Power: %s\n",
15669 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 15670 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 15671 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 15672
15673 err_printf(m, "Plane [%d]:\n", i);
15674 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15675 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 15676 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 15677 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15678 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 15679 }
4b71a570 15680 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 15681 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 15682 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 15683 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15684 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 15685 }
15686
edc3d884
MK		 15687 err_printf(m, "Cursor [%d]:\n", i);
15688 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15689 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15690 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 15691 }
63b66e5b
CW		 15692
15693 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 15694 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 15695 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 15696 err_printf(m, " Power: %s\n",
15697 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 15698 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15699 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15700 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15701 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15702 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15703 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15704 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15705 }
c4a1d9e4 15706}
e2fcdaa9
VS		 15707
15708void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15709{
15710 struct intel_crtc *crtc;
15711
15712 for_each_intel_crtc(dev, crtc) {
15713 struct intel_unpin_work *work;
e2fcdaa9 15714
5e2d7afc 15715 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 15716
15717 work = crtc->unpin_work;
15718
15719 if (work && work->event &&
15720 work->event->base.file_priv == file) {
15721 kfree(work->event);
15722 work->event = NULL;
15723 }
15724
5e2d7afc 15725 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 15726 }
15727}
Linux kernel - Deliverables
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