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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
79e53945 JB |
35 | #include "drmP.h" |
36 | #include "intel_drv.h" | |
37 | #include "i915_drm.h" | |
38 | #include "i915_drv.h" | |
e5510fac | 39 | #include "i915_trace.h" |
ab2c0672 | 40 | #include "drm_dp_helper.h" |
79e53945 | 41 | #include "drm_crtc_helper.h" |
c0f372b3 | 42 | #include <linux/dma_remapping.h> |
79e53945 | 43 | |
32f9d658 ZW |
44 | #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) |
45 | ||
0206e353 | 46 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type); |
3dec0095 | 47 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
6b383a7f | 48 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 JB |
49 | |
50 | typedef struct { | |
0206e353 AJ |
51 | /* given values */ |
52 | int n; | |
53 | int m1, m2; | |
54 | int p1, p2; | |
55 | /* derived values */ | |
56 | int dot; | |
57 | int vco; | |
58 | int m; | |
59 | int p; | |
79e53945 JB |
60 | } intel_clock_t; |
61 | ||
62 | typedef struct { | |
0206e353 | 63 | int min, max; |
79e53945 JB |
64 | } intel_range_t; |
65 | ||
66 | typedef struct { | |
0206e353 AJ |
67 | int dot_limit; |
68 | int p2_slow, p2_fast; | |
79e53945 JB |
69 | } intel_p2_t; |
70 | ||
71 | #define INTEL_P2_NUM 2 | |
d4906093 ML |
72 | typedef struct intel_limit intel_limit_t; |
73 | struct intel_limit { | |
0206e353 AJ |
74 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
75 | intel_p2_t p2; | |
76 | bool (* find_pll)(const intel_limit_t *, struct drm_crtc *, | |
cec2f356 | 77 | int, int, intel_clock_t *, intel_clock_t *); |
d4906093 | 78 | }; |
79e53945 | 79 | |
2377b741 JB |
80 | /* FDI */ |
81 | #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */ | |
82 | ||
d4906093 ML |
83 | static bool |
84 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
85 | int target, int refclk, intel_clock_t *match_clock, |
86 | intel_clock_t *best_clock); | |
d4906093 ML |
87 | static bool |
88 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
89 | int target, int refclk, intel_clock_t *match_clock, |
90 | intel_clock_t *best_clock); | |
79e53945 | 91 | |
a4fc5ed6 KP |
92 | static bool |
93 | intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc, | |
cec2f356 SP |
94 | int target, int refclk, intel_clock_t *match_clock, |
95 | intel_clock_t *best_clock); | |
5eb08b69 | 96 | static bool |
f2b115e6 | 97 | intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc, |
cec2f356 SP |
98 | int target, int refclk, intel_clock_t *match_clock, |
99 | intel_clock_t *best_clock); | |
a4fc5ed6 | 100 | |
a0c4da24 JB |
101 | static bool |
102 | intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc, | |
103 | int target, int refclk, intel_clock_t *match_clock, | |
104 | intel_clock_t *best_clock); | |
105 | ||
021357ac CW |
106 | static inline u32 /* units of 100MHz */ |
107 | intel_fdi_link_freq(struct drm_device *dev) | |
108 | { | |
8b99e68c CW |
109 | if (IS_GEN5(dev)) { |
110 | struct drm_i915_private *dev_priv = dev->dev_private; | |
111 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
112 | } else | |
113 | return 27; | |
021357ac CW |
114 | } |
115 | ||
e4b36699 | 116 | static const intel_limit_t intel_limits_i8xx_dvo = { |
0206e353 AJ |
117 | .dot = { .min = 25000, .max = 350000 }, |
118 | .vco = { .min = 930000, .max = 1400000 }, | |
119 | .n = { .min = 3, .max = 16 }, | |
120 | .m = { .min = 96, .max = 140 }, | |
121 | .m1 = { .min = 18, .max = 26 }, | |
122 | .m2 = { .min = 6, .max = 16 }, | |
123 | .p = { .min = 4, .max = 128 }, | |
124 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
125 | .p2 = { .dot_limit = 165000, |
126 | .p2_slow = 4, .p2_fast = 2 }, | |
d4906093 | 127 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
128 | }; |
129 | ||
130 | static const intel_limit_t intel_limits_i8xx_lvds = { | |
0206e353 AJ |
131 | .dot = { .min = 25000, .max = 350000 }, |
132 | .vco = { .min = 930000, .max = 1400000 }, | |
133 | .n = { .min = 3, .max = 16 }, | |
134 | .m = { .min = 96, .max = 140 }, | |
135 | .m1 = { .min = 18, .max = 26 }, | |
136 | .m2 = { .min = 6, .max = 16 }, | |
137 | .p = { .min = 4, .max = 128 }, | |
138 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
139 | .p2 = { .dot_limit = 165000, |
140 | .p2_slow = 14, .p2_fast = 7 }, | |
d4906093 | 141 | .find_pll = intel_find_best_PLL, |
e4b36699 | 142 | }; |
273e27ca | 143 | |
e4b36699 | 144 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
145 | .dot = { .min = 20000, .max = 400000 }, |
146 | .vco = { .min = 1400000, .max = 2800000 }, | |
147 | .n = { .min = 1, .max = 6 }, | |
148 | .m = { .min = 70, .max = 120 }, | |
149 | .m1 = { .min = 10, .max = 22 }, | |
150 | .m2 = { .min = 5, .max = 9 }, | |
151 | .p = { .min = 5, .max = 80 }, | |
152 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
153 | .p2 = { .dot_limit = 200000, |
154 | .p2_slow = 10, .p2_fast = 5 }, | |
d4906093 | 155 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
156 | }; |
157 | ||
158 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
159 | .dot = { .min = 20000, .max = 400000 }, |
160 | .vco = { .min = 1400000, .max = 2800000 }, | |
161 | .n = { .min = 1, .max = 6 }, | |
162 | .m = { .min = 70, .max = 120 }, | |
163 | .m1 = { .min = 10, .max = 22 }, | |
164 | .m2 = { .min = 5, .max = 9 }, | |
165 | .p = { .min = 7, .max = 98 }, | |
166 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
167 | .p2 = { .dot_limit = 112000, |
168 | .p2_slow = 14, .p2_fast = 7 }, | |
d4906093 | 169 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
170 | }; |
171 | ||
273e27ca | 172 | |
e4b36699 | 173 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
174 | .dot = { .min = 25000, .max = 270000 }, |
175 | .vco = { .min = 1750000, .max = 3500000}, | |
176 | .n = { .min = 1, .max = 4 }, | |
177 | .m = { .min = 104, .max = 138 }, | |
178 | .m1 = { .min = 17, .max = 23 }, | |
179 | .m2 = { .min = 5, .max = 11 }, | |
180 | .p = { .min = 10, .max = 30 }, | |
181 | .p1 = { .min = 1, .max = 3}, | |
182 | .p2 = { .dot_limit = 270000, | |
183 | .p2_slow = 10, | |
184 | .p2_fast = 10 | |
044c7c41 | 185 | }, |
d4906093 | 186 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
187 | }; |
188 | ||
189 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
190 | .dot = { .min = 22000, .max = 400000 }, |
191 | .vco = { .min = 1750000, .max = 3500000}, | |
192 | .n = { .min = 1, .max = 4 }, | |
193 | .m = { .min = 104, .max = 138 }, | |
194 | .m1 = { .min = 16, .max = 23 }, | |
195 | .m2 = { .min = 5, .max = 11 }, | |
196 | .p = { .min = 5, .max = 80 }, | |
197 | .p1 = { .min = 1, .max = 8}, | |
198 | .p2 = { .dot_limit = 165000, | |
199 | .p2_slow = 10, .p2_fast = 5 }, | |
d4906093 | 200 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
201 | }; |
202 | ||
203 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
204 | .dot = { .min = 20000, .max = 115000 }, |
205 | .vco = { .min = 1750000, .max = 3500000 }, | |
206 | .n = { .min = 1, .max = 3 }, | |
207 | .m = { .min = 104, .max = 138 }, | |
208 | .m1 = { .min = 17, .max = 23 }, | |
209 | .m2 = { .min = 5, .max = 11 }, | |
210 | .p = { .min = 28, .max = 112 }, | |
211 | .p1 = { .min = 2, .max = 8 }, | |
212 | .p2 = { .dot_limit = 0, | |
213 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 214 | }, |
d4906093 | 215 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
216 | }; |
217 | ||
218 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
219 | .dot = { .min = 80000, .max = 224000 }, |
220 | .vco = { .min = 1750000, .max = 3500000 }, | |
221 | .n = { .min = 1, .max = 3 }, | |
222 | .m = { .min = 104, .max = 138 }, | |
223 | .m1 = { .min = 17, .max = 23 }, | |
224 | .m2 = { .min = 5, .max = 11 }, | |
225 | .p = { .min = 14, .max = 42 }, | |
226 | .p1 = { .min = 2, .max = 6 }, | |
227 | .p2 = { .dot_limit = 0, | |
228 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 229 | }, |
d4906093 | 230 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
231 | }; |
232 | ||
233 | static const intel_limit_t intel_limits_g4x_display_port = { | |
0206e353 AJ |
234 | .dot = { .min = 161670, .max = 227000 }, |
235 | .vco = { .min = 1750000, .max = 3500000}, | |
236 | .n = { .min = 1, .max = 2 }, | |
237 | .m = { .min = 97, .max = 108 }, | |
238 | .m1 = { .min = 0x10, .max = 0x12 }, | |
239 | .m2 = { .min = 0x05, .max = 0x06 }, | |
240 | .p = { .min = 10, .max = 20 }, | |
241 | .p1 = { .min = 1, .max = 2}, | |
242 | .p2 = { .dot_limit = 0, | |
273e27ca | 243 | .p2_slow = 10, .p2_fast = 10 }, |
0206e353 | 244 | .find_pll = intel_find_pll_g4x_dp, |
e4b36699 KP |
245 | }; |
246 | ||
f2b115e6 | 247 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
248 | .dot = { .min = 20000, .max = 400000}, |
249 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 250 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
251 | .n = { .min = 3, .max = 6 }, |
252 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 253 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
254 | .m1 = { .min = 0, .max = 0 }, |
255 | .m2 = { .min = 0, .max = 254 }, | |
256 | .p = { .min = 5, .max = 80 }, | |
257 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
258 | .p2 = { .dot_limit = 200000, |
259 | .p2_slow = 10, .p2_fast = 5 }, | |
6115707b | 260 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
261 | }; |
262 | ||
f2b115e6 | 263 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
264 | .dot = { .min = 20000, .max = 400000 }, |
265 | .vco = { .min = 1700000, .max = 3500000 }, | |
266 | .n = { .min = 3, .max = 6 }, | |
267 | .m = { .min = 2, .max = 256 }, | |
268 | .m1 = { .min = 0, .max = 0 }, | |
269 | .m2 = { .min = 0, .max = 254 }, | |
270 | .p = { .min = 7, .max = 112 }, | |
271 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
272 | .p2 = { .dot_limit = 112000, |
273 | .p2_slow = 14, .p2_fast = 14 }, | |
6115707b | 274 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
275 | }; |
276 | ||
273e27ca EA |
277 | /* Ironlake / Sandybridge |
278 | * | |
279 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
280 | * the range value for them is (actual_value - 2). | |
281 | */ | |
b91ad0ec | 282 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
283 | .dot = { .min = 25000, .max = 350000 }, |
284 | .vco = { .min = 1760000, .max = 3510000 }, | |
285 | .n = { .min = 1, .max = 5 }, | |
286 | .m = { .min = 79, .max = 127 }, | |
287 | .m1 = { .min = 12, .max = 22 }, | |
288 | .m2 = { .min = 5, .max = 9 }, | |
289 | .p = { .min = 5, .max = 80 }, | |
290 | .p1 = { .min = 1, .max = 8 }, | |
291 | .p2 = { .dot_limit = 225000, | |
292 | .p2_slow = 10, .p2_fast = 5 }, | |
4547668a | 293 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
294 | }; |
295 | ||
b91ad0ec | 296 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
297 | .dot = { .min = 25000, .max = 350000 }, |
298 | .vco = { .min = 1760000, .max = 3510000 }, | |
299 | .n = { .min = 1, .max = 3 }, | |
300 | .m = { .min = 79, .max = 118 }, | |
301 | .m1 = { .min = 12, .max = 22 }, | |
302 | .m2 = { .min = 5, .max = 9 }, | |
303 | .p = { .min = 28, .max = 112 }, | |
304 | .p1 = { .min = 2, .max = 8 }, | |
305 | .p2 = { .dot_limit = 225000, | |
306 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
307 | .find_pll = intel_g4x_find_best_PLL, |
308 | }; | |
309 | ||
310 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
311 | .dot = { .min = 25000, .max = 350000 }, |
312 | .vco = { .min = 1760000, .max = 3510000 }, | |
313 | .n = { .min = 1, .max = 3 }, | |
314 | .m = { .min = 79, .max = 127 }, | |
315 | .m1 = { .min = 12, .max = 22 }, | |
316 | .m2 = { .min = 5, .max = 9 }, | |
317 | .p = { .min = 14, .max = 56 }, | |
318 | .p1 = { .min = 2, .max = 8 }, | |
319 | .p2 = { .dot_limit = 225000, | |
320 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
321 | .find_pll = intel_g4x_find_best_PLL, |
322 | }; | |
323 | ||
273e27ca | 324 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 325 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
326 | .dot = { .min = 25000, .max = 350000 }, |
327 | .vco = { .min = 1760000, .max = 3510000 }, | |
328 | .n = { .min = 1, .max = 2 }, | |
329 | .m = { .min = 79, .max = 126 }, | |
330 | .m1 = { .min = 12, .max = 22 }, | |
331 | .m2 = { .min = 5, .max = 9 }, | |
332 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 333 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
334 | .p2 = { .dot_limit = 225000, |
335 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
336 | .find_pll = intel_g4x_find_best_PLL, |
337 | }; | |
338 | ||
339 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
340 | .dot = { .min = 25000, .max = 350000 }, |
341 | .vco = { .min = 1760000, .max = 3510000 }, | |
342 | .n = { .min = 1, .max = 3 }, | |
343 | .m = { .min = 79, .max = 126 }, | |
344 | .m1 = { .min = 12, .max = 22 }, | |
345 | .m2 = { .min = 5, .max = 9 }, | |
346 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 347 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
348 | .p2 = { .dot_limit = 225000, |
349 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
350 | .find_pll = intel_g4x_find_best_PLL, |
351 | }; | |
352 | ||
353 | static const intel_limit_t intel_limits_ironlake_display_port = { | |
0206e353 AJ |
354 | .dot = { .min = 25000, .max = 350000 }, |
355 | .vco = { .min = 1760000, .max = 3510000}, | |
356 | .n = { .min = 1, .max = 2 }, | |
357 | .m = { .min = 81, .max = 90 }, | |
358 | .m1 = { .min = 12, .max = 22 }, | |
359 | .m2 = { .min = 5, .max = 9 }, | |
360 | .p = { .min = 10, .max = 20 }, | |
361 | .p1 = { .min = 1, .max = 2}, | |
362 | .p2 = { .dot_limit = 0, | |
273e27ca | 363 | .p2_slow = 10, .p2_fast = 10 }, |
0206e353 | 364 | .find_pll = intel_find_pll_ironlake_dp, |
79e53945 JB |
365 | }; |
366 | ||
a0c4da24 JB |
367 | static const intel_limit_t intel_limits_vlv_dac = { |
368 | .dot = { .min = 25000, .max = 270000 }, | |
369 | .vco = { .min = 4000000, .max = 6000000 }, | |
370 | .n = { .min = 1, .max = 7 }, | |
371 | .m = { .min = 22, .max = 450 }, /* guess */ | |
372 | .m1 = { .min = 2, .max = 3 }, | |
373 | .m2 = { .min = 11, .max = 156 }, | |
374 | .p = { .min = 10, .max = 30 }, | |
375 | .p1 = { .min = 2, .max = 3 }, | |
376 | .p2 = { .dot_limit = 270000, | |
377 | .p2_slow = 2, .p2_fast = 20 }, | |
378 | .find_pll = intel_vlv_find_best_pll, | |
379 | }; | |
380 | ||
381 | static const intel_limit_t intel_limits_vlv_hdmi = { | |
382 | .dot = { .min = 20000, .max = 165000 }, | |
383 | .vco = { .min = 5994000, .max = 4000000 }, | |
384 | .n = { .min = 1, .max = 7 }, | |
385 | .m = { .min = 60, .max = 300 }, /* guess */ | |
386 | .m1 = { .min = 2, .max = 3 }, | |
387 | .m2 = { .min = 11, .max = 156 }, | |
388 | .p = { .min = 10, .max = 30 }, | |
389 | .p1 = { .min = 2, .max = 3 }, | |
390 | .p2 = { .dot_limit = 270000, | |
391 | .p2_slow = 2, .p2_fast = 20 }, | |
392 | .find_pll = intel_vlv_find_best_pll, | |
393 | }; | |
394 | ||
395 | static const intel_limit_t intel_limits_vlv_dp = { | |
396 | .dot = { .min = 162000, .max = 270000 }, | |
397 | .vco = { .min = 5994000, .max = 4000000 }, | |
398 | .n = { .min = 1, .max = 7 }, | |
399 | .m = { .min = 60, .max = 300 }, /* guess */ | |
400 | .m1 = { .min = 2, .max = 3 }, | |
401 | .m2 = { .min = 11, .max = 156 }, | |
402 | .p = { .min = 10, .max = 30 }, | |
403 | .p1 = { .min = 2, .max = 3 }, | |
404 | .p2 = { .dot_limit = 270000, | |
405 | .p2_slow = 2, .p2_fast = 20 }, | |
406 | .find_pll = intel_vlv_find_best_pll, | |
407 | }; | |
408 | ||
57f350b6 JB |
409 | u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg) |
410 | { | |
411 | unsigned long flags; | |
412 | u32 val = 0; | |
413 | ||
414 | spin_lock_irqsave(&dev_priv->dpio_lock, flags); | |
415 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { | |
416 | DRM_ERROR("DPIO idle wait timed out\n"); | |
417 | goto out_unlock; | |
418 | } | |
419 | ||
420 | I915_WRITE(DPIO_REG, reg); | |
421 | I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID | | |
422 | DPIO_BYTE); | |
423 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { | |
424 | DRM_ERROR("DPIO read wait timed out\n"); | |
425 | goto out_unlock; | |
426 | } | |
427 | val = I915_READ(DPIO_DATA); | |
428 | ||
429 | out_unlock: | |
430 | spin_unlock_irqrestore(&dev_priv->dpio_lock, flags); | |
431 | return val; | |
432 | } | |
433 | ||
a0c4da24 JB |
434 | static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, |
435 | u32 val) | |
436 | { | |
437 | unsigned long flags; | |
438 | ||
439 | spin_lock_irqsave(&dev_priv->dpio_lock, flags); | |
440 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { | |
441 | DRM_ERROR("DPIO idle wait timed out\n"); | |
442 | goto out_unlock; | |
443 | } | |
444 | ||
445 | I915_WRITE(DPIO_DATA, val); | |
446 | I915_WRITE(DPIO_REG, reg); | |
447 | I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID | | |
448 | DPIO_BYTE); | |
449 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) | |
450 | DRM_ERROR("DPIO write wait timed out\n"); | |
451 | ||
452 | out_unlock: | |
453 | spin_unlock_irqrestore(&dev_priv->dpio_lock, flags); | |
454 | } | |
455 | ||
57f350b6 JB |
456 | static void vlv_init_dpio(struct drm_device *dev) |
457 | { | |
458 | struct drm_i915_private *dev_priv = dev->dev_private; | |
459 | ||
460 | /* Reset the DPIO config */ | |
461 | I915_WRITE(DPIO_CTL, 0); | |
462 | POSTING_READ(DPIO_CTL); | |
463 | I915_WRITE(DPIO_CTL, 1); | |
464 | POSTING_READ(DPIO_CTL); | |
465 | } | |
466 | ||
618563e3 DV |
467 | static int intel_dual_link_lvds_callback(const struct dmi_system_id *id) |
468 | { | |
469 | DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident); | |
470 | return 1; | |
471 | } | |
472 | ||
473 | static const struct dmi_system_id intel_dual_link_lvds[] = { | |
474 | { | |
475 | .callback = intel_dual_link_lvds_callback, | |
476 | .ident = "Apple MacBook Pro (Core i5/i7 Series)", | |
477 | .matches = { | |
478 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), | |
479 | DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"), | |
480 | }, | |
481 | }, | |
482 | { } /* terminating entry */ | |
483 | }; | |
484 | ||
b0354385 TI |
485 | static bool is_dual_link_lvds(struct drm_i915_private *dev_priv, |
486 | unsigned int reg) | |
487 | { | |
488 | unsigned int val; | |
489 | ||
121d527a TI |
490 | /* use the module option value if specified */ |
491 | if (i915_lvds_channel_mode > 0) | |
492 | return i915_lvds_channel_mode == 2; | |
493 | ||
618563e3 DV |
494 | if (dmi_check_system(intel_dual_link_lvds)) |
495 | return true; | |
496 | ||
b0354385 TI |
497 | if (dev_priv->lvds_val) |
498 | val = dev_priv->lvds_val; | |
499 | else { | |
500 | /* BIOS should set the proper LVDS register value at boot, but | |
501 | * in reality, it doesn't set the value when the lid is closed; | |
502 | * we need to check "the value to be set" in VBT when LVDS | |
503 | * register is uninitialized. | |
504 | */ | |
505 | val = I915_READ(reg); | |
14d94a3d | 506 | if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED))) |
b0354385 TI |
507 | val = dev_priv->bios_lvds_val; |
508 | dev_priv->lvds_val = val; | |
509 | } | |
510 | return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP; | |
511 | } | |
512 | ||
1b894b59 CW |
513 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
514 | int refclk) | |
2c07245f | 515 | { |
b91ad0ec ZW |
516 | struct drm_device *dev = crtc->dev; |
517 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2c07245f | 518 | const intel_limit_t *limit; |
b91ad0ec ZW |
519 | |
520 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
b0354385 | 521 | if (is_dual_link_lvds(dev_priv, PCH_LVDS)) { |
b91ad0ec | 522 | /* LVDS dual channel */ |
1b894b59 | 523 | if (refclk == 100000) |
b91ad0ec ZW |
524 | limit = &intel_limits_ironlake_dual_lvds_100m; |
525 | else | |
526 | limit = &intel_limits_ironlake_dual_lvds; | |
527 | } else { | |
1b894b59 | 528 | if (refclk == 100000) |
b91ad0ec ZW |
529 | limit = &intel_limits_ironlake_single_lvds_100m; |
530 | else | |
531 | limit = &intel_limits_ironlake_single_lvds; | |
532 | } | |
533 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || | |
4547668a ZY |
534 | HAS_eDP) |
535 | limit = &intel_limits_ironlake_display_port; | |
2c07245f | 536 | else |
b91ad0ec | 537 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
538 | |
539 | return limit; | |
540 | } | |
541 | ||
044c7c41 ML |
542 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
543 | { | |
544 | struct drm_device *dev = crtc->dev; | |
545 | struct drm_i915_private *dev_priv = dev->dev_private; | |
546 | const intel_limit_t *limit; | |
547 | ||
548 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
b0354385 | 549 | if (is_dual_link_lvds(dev_priv, LVDS)) |
044c7c41 | 550 | /* LVDS with dual channel */ |
e4b36699 | 551 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 ML |
552 | else |
553 | /* LVDS with dual channel */ | |
e4b36699 | 554 | limit = &intel_limits_g4x_single_channel_lvds; |
044c7c41 ML |
555 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
556 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 557 | limit = &intel_limits_g4x_hdmi; |
044c7c41 | 558 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 559 | limit = &intel_limits_g4x_sdvo; |
0206e353 | 560 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
e4b36699 | 561 | limit = &intel_limits_g4x_display_port; |
044c7c41 | 562 | } else /* The option is for other outputs */ |
e4b36699 | 563 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
564 | |
565 | return limit; | |
566 | } | |
567 | ||
1b894b59 | 568 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
79e53945 JB |
569 | { |
570 | struct drm_device *dev = crtc->dev; | |
571 | const intel_limit_t *limit; | |
572 | ||
bad720ff | 573 | if (HAS_PCH_SPLIT(dev)) |
1b894b59 | 574 | limit = intel_ironlake_limit(crtc, refclk); |
2c07245f | 575 | else if (IS_G4X(dev)) { |
044c7c41 | 576 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 577 | } else if (IS_PINEVIEW(dev)) { |
2177832f | 578 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 579 | limit = &intel_limits_pineview_lvds; |
2177832f | 580 | else |
f2b115e6 | 581 | limit = &intel_limits_pineview_sdvo; |
a0c4da24 JB |
582 | } else if (IS_VALLEYVIEW(dev)) { |
583 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) | |
584 | limit = &intel_limits_vlv_dac; | |
585 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
586 | limit = &intel_limits_vlv_hdmi; | |
587 | else | |
588 | limit = &intel_limits_vlv_dp; | |
a6c45cf0 CW |
589 | } else if (!IS_GEN2(dev)) { |
590 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
591 | limit = &intel_limits_i9xx_lvds; | |
592 | else | |
593 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 JB |
594 | } else { |
595 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 596 | limit = &intel_limits_i8xx_lvds; |
79e53945 | 597 | else |
e4b36699 | 598 | limit = &intel_limits_i8xx_dvo; |
79e53945 JB |
599 | } |
600 | return limit; | |
601 | } | |
602 | ||
f2b115e6 AJ |
603 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
604 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 605 | { |
2177832f SL |
606 | clock->m = clock->m2 + 2; |
607 | clock->p = clock->p1 * clock->p2; | |
608 | clock->vco = refclk * clock->m / clock->n; | |
609 | clock->dot = clock->vco / clock->p; | |
610 | } | |
611 | ||
612 | static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock) | |
613 | { | |
f2b115e6 AJ |
614 | if (IS_PINEVIEW(dev)) { |
615 | pineview_clock(refclk, clock); | |
2177832f SL |
616 | return; |
617 | } | |
79e53945 JB |
618 | clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); |
619 | clock->p = clock->p1 * clock->p2; | |
620 | clock->vco = refclk * clock->m / (clock->n + 2); | |
621 | clock->dot = clock->vco / clock->p; | |
622 | } | |
623 | ||
79e53945 JB |
624 | /** |
625 | * Returns whether any output on the specified pipe is of the specified type | |
626 | */ | |
4ef69c7a | 627 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type) |
79e53945 | 628 | { |
4ef69c7a | 629 | struct drm_device *dev = crtc->dev; |
4ef69c7a CW |
630 | struct intel_encoder *encoder; |
631 | ||
6c2b7c12 DV |
632 | for_each_encoder_on_crtc(dev, crtc, encoder) |
633 | if (encoder->type == type) | |
4ef69c7a CW |
634 | return true; |
635 | ||
636 | return false; | |
79e53945 JB |
637 | } |
638 | ||
7c04d1d9 | 639 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
640 | /** |
641 | * Returns whether the given set of divisors are valid for a given refclk with | |
642 | * the given connectors. | |
643 | */ | |
644 | ||
1b894b59 CW |
645 | static bool intel_PLL_is_valid(struct drm_device *dev, |
646 | const intel_limit_t *limit, | |
647 | const intel_clock_t *clock) | |
79e53945 | 648 | { |
79e53945 | 649 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 650 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 651 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
0206e353 | 652 | INTELPllInvalid("p out of range\n"); |
79e53945 | 653 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 654 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 655 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 656 | INTELPllInvalid("m1 out of range\n"); |
f2b115e6 | 657 | if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev)) |
0206e353 | 658 | INTELPllInvalid("m1 <= m2\n"); |
79e53945 | 659 | if (clock->m < limit->m.min || limit->m.max < clock->m) |
0206e353 | 660 | INTELPllInvalid("m out of range\n"); |
79e53945 | 661 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
0206e353 | 662 | INTELPllInvalid("n out of range\n"); |
79e53945 | 663 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 664 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
665 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
666 | * connector, etc., rather than just a single range. | |
667 | */ | |
668 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 669 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
670 | |
671 | return true; | |
672 | } | |
673 | ||
d4906093 ML |
674 | static bool |
675 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
676 | int target, int refclk, intel_clock_t *match_clock, |
677 | intel_clock_t *best_clock) | |
d4906093 | 678 | |
79e53945 JB |
679 | { |
680 | struct drm_device *dev = crtc->dev; | |
681 | struct drm_i915_private *dev_priv = dev->dev_private; | |
682 | intel_clock_t clock; | |
79e53945 JB |
683 | int err = target; |
684 | ||
bc5e5718 | 685 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
832cc28d | 686 | (I915_READ(LVDS)) != 0) { |
79e53945 JB |
687 | /* |
688 | * For LVDS, if the panel is on, just rely on its current | |
689 | * settings for dual-channel. We haven't figured out how to | |
690 | * reliably set up different single/dual channel state, if we | |
691 | * even can. | |
692 | */ | |
b0354385 | 693 | if (is_dual_link_lvds(dev_priv, LVDS)) |
79e53945 JB |
694 | clock.p2 = limit->p2.p2_fast; |
695 | else | |
696 | clock.p2 = limit->p2.p2_slow; | |
697 | } else { | |
698 | if (target < limit->p2.dot_limit) | |
699 | clock.p2 = limit->p2.p2_slow; | |
700 | else | |
701 | clock.p2 = limit->p2.p2_fast; | |
702 | } | |
703 | ||
0206e353 | 704 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 705 | |
42158660 ZY |
706 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
707 | clock.m1++) { | |
708 | for (clock.m2 = limit->m2.min; | |
709 | clock.m2 <= limit->m2.max; clock.m2++) { | |
f2b115e6 AJ |
710 | /* m1 is always 0 in Pineview */ |
711 | if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev)) | |
42158660 ZY |
712 | break; |
713 | for (clock.n = limit->n.min; | |
714 | clock.n <= limit->n.max; clock.n++) { | |
715 | for (clock.p1 = limit->p1.min; | |
716 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
717 | int this_err; |
718 | ||
2177832f | 719 | intel_clock(dev, refclk, &clock); |
1b894b59 CW |
720 | if (!intel_PLL_is_valid(dev, limit, |
721 | &clock)) | |
79e53945 | 722 | continue; |
cec2f356 SP |
723 | if (match_clock && |
724 | clock.p != match_clock->p) | |
725 | continue; | |
79e53945 JB |
726 | |
727 | this_err = abs(clock.dot - target); | |
728 | if (this_err < err) { | |
729 | *best_clock = clock; | |
730 | err = this_err; | |
731 | } | |
732 | } | |
733 | } | |
734 | } | |
735 | } | |
736 | ||
737 | return (err != target); | |
738 | } | |
739 | ||
d4906093 ML |
740 | static bool |
741 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
742 | int target, int refclk, intel_clock_t *match_clock, |
743 | intel_clock_t *best_clock) | |
d4906093 ML |
744 | { |
745 | struct drm_device *dev = crtc->dev; | |
746 | struct drm_i915_private *dev_priv = dev->dev_private; | |
747 | intel_clock_t clock; | |
748 | int max_n; | |
749 | bool found; | |
6ba770dc AJ |
750 | /* approximately equals target * 0.00585 */ |
751 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
752 | found = false; |
753 | ||
754 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
4547668a ZY |
755 | int lvds_reg; |
756 | ||
c619eed4 | 757 | if (HAS_PCH_SPLIT(dev)) |
4547668a ZY |
758 | lvds_reg = PCH_LVDS; |
759 | else | |
760 | lvds_reg = LVDS; | |
761 | if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) == | |
d4906093 ML |
762 | LVDS_CLKB_POWER_UP) |
763 | clock.p2 = limit->p2.p2_fast; | |
764 | else | |
765 | clock.p2 = limit->p2.p2_slow; | |
766 | } else { | |
767 | if (target < limit->p2.dot_limit) | |
768 | clock.p2 = limit->p2.p2_slow; | |
769 | else | |
770 | clock.p2 = limit->p2.p2_fast; | |
771 | } | |
772 | ||
773 | memset(best_clock, 0, sizeof(*best_clock)); | |
774 | max_n = limit->n.max; | |
f77f13e2 | 775 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 776 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 777 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
778 | for (clock.m1 = limit->m1.max; |
779 | clock.m1 >= limit->m1.min; clock.m1--) { | |
780 | for (clock.m2 = limit->m2.max; | |
781 | clock.m2 >= limit->m2.min; clock.m2--) { | |
782 | for (clock.p1 = limit->p1.max; | |
783 | clock.p1 >= limit->p1.min; clock.p1--) { | |
784 | int this_err; | |
785 | ||
2177832f | 786 | intel_clock(dev, refclk, &clock); |
1b894b59 CW |
787 | if (!intel_PLL_is_valid(dev, limit, |
788 | &clock)) | |
d4906093 | 789 | continue; |
cec2f356 SP |
790 | if (match_clock && |
791 | clock.p != match_clock->p) | |
792 | continue; | |
1b894b59 CW |
793 | |
794 | this_err = abs(clock.dot - target); | |
d4906093 ML |
795 | if (this_err < err_most) { |
796 | *best_clock = clock; | |
797 | err_most = this_err; | |
798 | max_n = clock.n; | |
799 | found = true; | |
800 | } | |
801 | } | |
802 | } | |
803 | } | |
804 | } | |
2c07245f ZW |
805 | return found; |
806 | } | |
807 | ||
5eb08b69 | 808 | static bool |
f2b115e6 | 809 | intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc, |
cec2f356 SP |
810 | int target, int refclk, intel_clock_t *match_clock, |
811 | intel_clock_t *best_clock) | |
5eb08b69 ZW |
812 | { |
813 | struct drm_device *dev = crtc->dev; | |
814 | intel_clock_t clock; | |
4547668a | 815 | |
5eb08b69 ZW |
816 | if (target < 200000) { |
817 | clock.n = 1; | |
818 | clock.p1 = 2; | |
819 | clock.p2 = 10; | |
820 | clock.m1 = 12; | |
821 | clock.m2 = 9; | |
822 | } else { | |
823 | clock.n = 2; | |
824 | clock.p1 = 1; | |
825 | clock.p2 = 10; | |
826 | clock.m1 = 14; | |
827 | clock.m2 = 8; | |
828 | } | |
829 | intel_clock(dev, refclk, &clock); | |
830 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); | |
831 | return true; | |
832 | } | |
833 | ||
a4fc5ed6 KP |
834 | /* DisplayPort has only two frequencies, 162MHz and 270MHz */ |
835 | static bool | |
836 | intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
837 | int target, int refclk, intel_clock_t *match_clock, |
838 | intel_clock_t *best_clock) | |
a4fc5ed6 | 839 | { |
5eddb70b CW |
840 | intel_clock_t clock; |
841 | if (target < 200000) { | |
842 | clock.p1 = 2; | |
843 | clock.p2 = 10; | |
844 | clock.n = 2; | |
845 | clock.m1 = 23; | |
846 | clock.m2 = 8; | |
847 | } else { | |
848 | clock.p1 = 1; | |
849 | clock.p2 = 10; | |
850 | clock.n = 1; | |
851 | clock.m1 = 14; | |
852 | clock.m2 = 2; | |
853 | } | |
854 | clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2); | |
855 | clock.p = (clock.p1 * clock.p2); | |
856 | clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p; | |
857 | clock.vco = 0; | |
858 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); | |
859 | return true; | |
a4fc5ed6 | 860 | } |
a0c4da24 JB |
861 | static bool |
862 | intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc, | |
863 | int target, int refclk, intel_clock_t *match_clock, | |
864 | intel_clock_t *best_clock) | |
865 | { | |
866 | u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2; | |
867 | u32 m, n, fastclk; | |
868 | u32 updrate, minupdate, fracbits, p; | |
869 | unsigned long bestppm, ppm, absppm; | |
870 | int dotclk, flag; | |
871 | ||
872 | dotclk = target * 1000; | |
873 | bestppm = 1000000; | |
874 | ppm = absppm = 0; | |
875 | fastclk = dotclk / (2*100); | |
876 | updrate = 0; | |
877 | minupdate = 19200; | |
878 | fracbits = 1; | |
879 | n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0; | |
880 | bestm1 = bestm2 = bestp1 = bestp2 = 0; | |
881 | ||
882 | /* based on hardware requirement, prefer smaller n to precision */ | |
883 | for (n = limit->n.min; n <= ((refclk) / minupdate); n++) { | |
884 | updrate = refclk / n; | |
885 | for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) { | |
886 | for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) { | |
887 | if (p2 > 10) | |
888 | p2 = p2 - 1; | |
889 | p = p1 * p2; | |
890 | /* based on hardware requirement, prefer bigger m1,m2 values */ | |
891 | for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) { | |
892 | m2 = (((2*(fastclk * p * n / m1 )) + | |
893 | refclk) / (2*refclk)); | |
894 | m = m1 * m2; | |
895 | vco = updrate * m; | |
896 | if (vco >= limit->vco.min && vco < limit->vco.max) { | |
897 | ppm = 1000000 * ((vco / p) - fastclk) / fastclk; | |
898 | absppm = (ppm > 0) ? ppm : (-ppm); | |
899 | if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) { | |
900 | bestppm = 0; | |
901 | flag = 1; | |
902 | } | |
903 | if (absppm < bestppm - 10) { | |
904 | bestppm = absppm; | |
905 | flag = 1; | |
906 | } | |
907 | if (flag) { | |
908 | bestn = n; | |
909 | bestm1 = m1; | |
910 | bestm2 = m2; | |
911 | bestp1 = p1; | |
912 | bestp2 = p2; | |
913 | flag = 0; | |
914 | } | |
915 | } | |
916 | } | |
917 | } | |
918 | } | |
919 | } | |
920 | best_clock->n = bestn; | |
921 | best_clock->m1 = bestm1; | |
922 | best_clock->m2 = bestm2; | |
923 | best_clock->p1 = bestp1; | |
924 | best_clock->p2 = bestp2; | |
925 | ||
926 | return true; | |
927 | } | |
a4fc5ed6 | 928 | |
a928d536 PZ |
929 | static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe) |
930 | { | |
931 | struct drm_i915_private *dev_priv = dev->dev_private; | |
932 | u32 frame, frame_reg = PIPEFRAME(pipe); | |
933 | ||
934 | frame = I915_READ(frame_reg); | |
935 | ||
936 | if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) | |
937 | DRM_DEBUG_KMS("vblank wait timed out\n"); | |
938 | } | |
939 | ||
9d0498a2 JB |
940 | /** |
941 | * intel_wait_for_vblank - wait for vblank on a given pipe | |
942 | * @dev: drm device | |
943 | * @pipe: pipe to wait for | |
944 | * | |
945 | * Wait for vblank to occur on a given pipe. Needed for various bits of | |
946 | * mode setting code. | |
947 | */ | |
948 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) | |
79e53945 | 949 | { |
9d0498a2 | 950 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 951 | int pipestat_reg = PIPESTAT(pipe); |
9d0498a2 | 952 | |
a928d536 PZ |
953 | if (INTEL_INFO(dev)->gen >= 5) { |
954 | ironlake_wait_for_vblank(dev, pipe); | |
955 | return; | |
956 | } | |
957 | ||
300387c0 CW |
958 | /* Clear existing vblank status. Note this will clear any other |
959 | * sticky status fields as well. | |
960 | * | |
961 | * This races with i915_driver_irq_handler() with the result | |
962 | * that either function could miss a vblank event. Here it is not | |
963 | * fatal, as we will either wait upon the next vblank interrupt or | |
964 | * timeout. Generally speaking intel_wait_for_vblank() is only | |
965 | * called during modeset at which time the GPU should be idle and | |
966 | * should *not* be performing page flips and thus not waiting on | |
967 | * vblanks... | |
968 | * Currently, the result of us stealing a vblank from the irq | |
969 | * handler is that a single frame will be skipped during swapbuffers. | |
970 | */ | |
971 | I915_WRITE(pipestat_reg, | |
972 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); | |
973 | ||
9d0498a2 | 974 | /* Wait for vblank interrupt bit to set */ |
481b6af3 CW |
975 | if (wait_for(I915_READ(pipestat_reg) & |
976 | PIPE_VBLANK_INTERRUPT_STATUS, | |
977 | 50)) | |
9d0498a2 JB |
978 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
979 | } | |
980 | ||
ab7ad7f6 KP |
981 | /* |
982 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
9d0498a2 JB |
983 | * @dev: drm device |
984 | * @pipe: pipe to wait for | |
985 | * | |
986 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
987 | * spinning on the vblank interrupt status bit, since we won't actually | |
988 | * see an interrupt when the pipe is disabled. | |
989 | * | |
ab7ad7f6 KP |
990 | * On Gen4 and above: |
991 | * wait for the pipe register state bit to turn off | |
992 | * | |
993 | * Otherwise: | |
994 | * wait for the display line value to settle (it usually | |
995 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 996 | * |
9d0498a2 | 997 | */ |
58e10eb9 | 998 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
9d0498a2 JB |
999 | { |
1000 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ab7ad7f6 KP |
1001 | |
1002 | if (INTEL_INFO(dev)->gen >= 4) { | |
58e10eb9 | 1003 | int reg = PIPECONF(pipe); |
ab7ad7f6 KP |
1004 | |
1005 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
1006 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1007 | 100)) | |
ab7ad7f6 KP |
1008 | DRM_DEBUG_KMS("pipe_off wait timed out\n"); |
1009 | } else { | |
837ba00f | 1010 | u32 last_line, line_mask; |
58e10eb9 | 1011 | int reg = PIPEDSL(pipe); |
ab7ad7f6 KP |
1012 | unsigned long timeout = jiffies + msecs_to_jiffies(100); |
1013 | ||
837ba00f PZ |
1014 | if (IS_GEN2(dev)) |
1015 | line_mask = DSL_LINEMASK_GEN2; | |
1016 | else | |
1017 | line_mask = DSL_LINEMASK_GEN3; | |
1018 | ||
ab7ad7f6 KP |
1019 | /* Wait for the display line to settle */ |
1020 | do { | |
837ba00f | 1021 | last_line = I915_READ(reg) & line_mask; |
ab7ad7f6 | 1022 | mdelay(5); |
837ba00f | 1023 | } while (((I915_READ(reg) & line_mask) != last_line) && |
ab7ad7f6 KP |
1024 | time_after(timeout, jiffies)); |
1025 | if (time_after(jiffies, timeout)) | |
1026 | DRM_DEBUG_KMS("pipe_off wait timed out\n"); | |
1027 | } | |
79e53945 JB |
1028 | } |
1029 | ||
b24e7179 JB |
1030 | static const char *state_string(bool enabled) |
1031 | { | |
1032 | return enabled ? "on" : "off"; | |
1033 | } | |
1034 | ||
1035 | /* Only for pre-ILK configs */ | |
1036 | static void assert_pll(struct drm_i915_private *dev_priv, | |
1037 | enum pipe pipe, bool state) | |
1038 | { | |
1039 | int reg; | |
1040 | u32 val; | |
1041 | bool cur_state; | |
1042 | ||
1043 | reg = DPLL(pipe); | |
1044 | val = I915_READ(reg); | |
1045 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
1046 | WARN(cur_state != state, | |
1047 | "PLL state assertion failure (expected %s, current %s)\n", | |
1048 | state_string(state), state_string(cur_state)); | |
1049 | } | |
1050 | #define assert_pll_enabled(d, p) assert_pll(d, p, true) | |
1051 | #define assert_pll_disabled(d, p) assert_pll(d, p, false) | |
1052 | ||
040484af JB |
1053 | /* For ILK+ */ |
1054 | static void assert_pch_pll(struct drm_i915_private *dev_priv, | |
92b27b08 CW |
1055 | struct intel_pch_pll *pll, |
1056 | struct intel_crtc *crtc, | |
1057 | bool state) | |
040484af | 1058 | { |
040484af JB |
1059 | u32 val; |
1060 | bool cur_state; | |
1061 | ||
9d82aa17 ED |
1062 | if (HAS_PCH_LPT(dev_priv->dev)) { |
1063 | DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n"); | |
1064 | return; | |
1065 | } | |
1066 | ||
92b27b08 CW |
1067 | if (WARN (!pll, |
1068 | "asserting PCH PLL %s with no PLL\n", state_string(state))) | |
ee7b9f93 | 1069 | return; |
ee7b9f93 | 1070 | |
92b27b08 CW |
1071 | val = I915_READ(pll->pll_reg); |
1072 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
1073 | WARN(cur_state != state, | |
1074 | "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n", | |
1075 | pll->pll_reg, state_string(state), state_string(cur_state), val); | |
1076 | ||
1077 | /* Make sure the selected PLL is correctly attached to the transcoder */ | |
1078 | if (crtc && HAS_PCH_CPT(dev_priv->dev)) { | |
d3ccbe86 JB |
1079 | u32 pch_dpll; |
1080 | ||
1081 | pch_dpll = I915_READ(PCH_DPLL_SEL); | |
92b27b08 CW |
1082 | cur_state = pll->pll_reg == _PCH_DPLL_B; |
1083 | if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state, | |
1084 | "PLL[%d] not attached to this transcoder %d: %08x\n", | |
1085 | cur_state, crtc->pipe, pch_dpll)) { | |
1086 | cur_state = !!(val >> (4*crtc->pipe + 3)); | |
1087 | WARN(cur_state != state, | |
1088 | "PLL[%d] not %s on this transcoder %d: %08x\n", | |
1089 | pll->pll_reg == _PCH_DPLL_B, | |
1090 | state_string(state), | |
1091 | crtc->pipe, | |
1092 | val); | |
1093 | } | |
d3ccbe86 | 1094 | } |
040484af | 1095 | } |
92b27b08 CW |
1096 | #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true) |
1097 | #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false) | |
040484af JB |
1098 | |
1099 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1100 | enum pipe pipe, bool state) | |
1101 | { | |
1102 | int reg; | |
1103 | u32 val; | |
1104 | bool cur_state; | |
1105 | ||
bf507ef7 ED |
1106 | if (IS_HASWELL(dev_priv->dev)) { |
1107 | /* On Haswell, DDI is used instead of FDI_TX_CTL */ | |
1108 | reg = DDI_FUNC_CTL(pipe); | |
1109 | val = I915_READ(reg); | |
1110 | cur_state = !!(val & PIPE_DDI_FUNC_ENABLE); | |
1111 | } else { | |
1112 | reg = FDI_TX_CTL(pipe); | |
1113 | val = I915_READ(reg); | |
1114 | cur_state = !!(val & FDI_TX_ENABLE); | |
1115 | } | |
040484af JB |
1116 | WARN(cur_state != state, |
1117 | "FDI TX state assertion failure (expected %s, current %s)\n", | |
1118 | state_string(state), state_string(cur_state)); | |
1119 | } | |
1120 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1121 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1122 | ||
1123 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1124 | enum pipe pipe, bool state) | |
1125 | { | |
1126 | int reg; | |
1127 | u32 val; | |
1128 | bool cur_state; | |
1129 | ||
59c859d6 ED |
1130 | if (IS_HASWELL(dev_priv->dev) && pipe > 0) { |
1131 | DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n"); | |
1132 | return; | |
1133 | } else { | |
1134 | reg = FDI_RX_CTL(pipe); | |
1135 | val = I915_READ(reg); | |
1136 | cur_state = !!(val & FDI_RX_ENABLE); | |
1137 | } | |
040484af JB |
1138 | WARN(cur_state != state, |
1139 | "FDI RX state assertion failure (expected %s, current %s)\n", | |
1140 | state_string(state), state_string(cur_state)); | |
1141 | } | |
1142 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1143 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1144 | ||
1145 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1146 | enum pipe pipe) | |
1147 | { | |
1148 | int reg; | |
1149 | u32 val; | |
1150 | ||
1151 | /* ILK FDI PLL is always enabled */ | |
1152 | if (dev_priv->info->gen == 5) | |
1153 | return; | |
1154 | ||
bf507ef7 ED |
1155 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
1156 | if (IS_HASWELL(dev_priv->dev)) | |
1157 | return; | |
1158 | ||
040484af JB |
1159 | reg = FDI_TX_CTL(pipe); |
1160 | val = I915_READ(reg); | |
1161 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); | |
1162 | } | |
1163 | ||
1164 | static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv, | |
1165 | enum pipe pipe) | |
1166 | { | |
1167 | int reg; | |
1168 | u32 val; | |
1169 | ||
59c859d6 ED |
1170 | if (IS_HASWELL(dev_priv->dev) && pipe > 0) { |
1171 | DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n"); | |
1172 | return; | |
1173 | } | |
040484af JB |
1174 | reg = FDI_RX_CTL(pipe); |
1175 | val = I915_READ(reg); | |
1176 | WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n"); | |
1177 | } | |
1178 | ||
ea0760cf JB |
1179 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1180 | enum pipe pipe) | |
1181 | { | |
1182 | int pp_reg, lvds_reg; | |
1183 | u32 val; | |
1184 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1185 | bool locked = true; |
ea0760cf JB |
1186 | |
1187 | if (HAS_PCH_SPLIT(dev_priv->dev)) { | |
1188 | pp_reg = PCH_PP_CONTROL; | |
1189 | lvds_reg = PCH_LVDS; | |
1190 | } else { | |
1191 | pp_reg = PP_CONTROL; | |
1192 | lvds_reg = LVDS; | |
1193 | } | |
1194 | ||
1195 | val = I915_READ(pp_reg); | |
1196 | if (!(val & PANEL_POWER_ON) || | |
1197 | ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) | |
1198 | locked = false; | |
1199 | ||
1200 | if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) | |
1201 | panel_pipe = PIPE_B; | |
1202 | ||
1203 | WARN(panel_pipe == pipe && locked, | |
1204 | "panel assertion failure, pipe %c regs locked\n", | |
9db4a9c7 | 1205 | pipe_name(pipe)); |
ea0760cf JB |
1206 | } |
1207 | ||
b840d907 JB |
1208 | void assert_pipe(struct drm_i915_private *dev_priv, |
1209 | enum pipe pipe, bool state) | |
b24e7179 JB |
1210 | { |
1211 | int reg; | |
1212 | u32 val; | |
63d7bbe9 | 1213 | bool cur_state; |
b24e7179 | 1214 | |
8e636784 DV |
1215 | /* if we need the pipe A quirk it must be always on */ |
1216 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
1217 | state = true; | |
1218 | ||
b24e7179 JB |
1219 | reg = PIPECONF(pipe); |
1220 | val = I915_READ(reg); | |
63d7bbe9 JB |
1221 | cur_state = !!(val & PIPECONF_ENABLE); |
1222 | WARN(cur_state != state, | |
1223 | "pipe %c assertion failure (expected %s, current %s)\n", | |
9db4a9c7 | 1224 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1225 | } |
1226 | ||
931872fc CW |
1227 | static void assert_plane(struct drm_i915_private *dev_priv, |
1228 | enum plane plane, bool state) | |
b24e7179 JB |
1229 | { |
1230 | int reg; | |
1231 | u32 val; | |
931872fc | 1232 | bool cur_state; |
b24e7179 JB |
1233 | |
1234 | reg = DSPCNTR(plane); | |
1235 | val = I915_READ(reg); | |
931872fc CW |
1236 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
1237 | WARN(cur_state != state, | |
1238 | "plane %c assertion failure (expected %s, current %s)\n", | |
1239 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1240 | } |
1241 | ||
931872fc CW |
1242 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1243 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1244 | ||
b24e7179 JB |
1245 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1246 | enum pipe pipe) | |
1247 | { | |
1248 | int reg, i; | |
1249 | u32 val; | |
1250 | int cur_pipe; | |
1251 | ||
19ec1358 | 1252 | /* Planes are fixed to pipes on ILK+ */ |
28c05794 AJ |
1253 | if (HAS_PCH_SPLIT(dev_priv->dev)) { |
1254 | reg = DSPCNTR(pipe); | |
1255 | val = I915_READ(reg); | |
1256 | WARN((val & DISPLAY_PLANE_ENABLE), | |
1257 | "plane %c assertion failure, should be disabled but not\n", | |
1258 | plane_name(pipe)); | |
19ec1358 | 1259 | return; |
28c05794 | 1260 | } |
19ec1358 | 1261 | |
b24e7179 JB |
1262 | /* Need to check both planes against the pipe */ |
1263 | for (i = 0; i < 2; i++) { | |
1264 | reg = DSPCNTR(i); | |
1265 | val = I915_READ(reg); | |
1266 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1267 | DISPPLANE_SEL_PIPE_SHIFT; | |
1268 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, | |
9db4a9c7 JB |
1269 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1270 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1271 | } |
1272 | } | |
1273 | ||
92f2584a JB |
1274 | static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
1275 | { | |
1276 | u32 val; | |
1277 | bool enabled; | |
1278 | ||
9d82aa17 ED |
1279 | if (HAS_PCH_LPT(dev_priv->dev)) { |
1280 | DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n"); | |
1281 | return; | |
1282 | } | |
1283 | ||
92f2584a JB |
1284 | val = I915_READ(PCH_DREF_CONTROL); |
1285 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1286 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
1287 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); | |
1288 | } | |
1289 | ||
1290 | static void assert_transcoder_disabled(struct drm_i915_private *dev_priv, | |
1291 | enum pipe pipe) | |
1292 | { | |
1293 | int reg; | |
1294 | u32 val; | |
1295 | bool enabled; | |
1296 | ||
1297 | reg = TRANSCONF(pipe); | |
1298 | val = I915_READ(reg); | |
1299 | enabled = !!(val & TRANS_ENABLE); | |
9db4a9c7 JB |
1300 | WARN(enabled, |
1301 | "transcoder assertion failed, should be off on pipe %c but is still active\n", | |
1302 | pipe_name(pipe)); | |
92f2584a JB |
1303 | } |
1304 | ||
4e634389 KP |
1305 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1306 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1307 | { |
1308 | if ((val & DP_PORT_EN) == 0) | |
1309 | return false; | |
1310 | ||
1311 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1312 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1313 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1314 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1315 | return false; | |
1316 | } else { | |
1317 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1318 | return false; | |
1319 | } | |
1320 | return true; | |
1321 | } | |
1322 | ||
1519b995 KP |
1323 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1324 | enum pipe pipe, u32 val) | |
1325 | { | |
1326 | if ((val & PORT_ENABLE) == 0) | |
1327 | return false; | |
1328 | ||
1329 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1330 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1331 | return false; | |
1332 | } else { | |
1333 | if ((val & TRANSCODER_MASK) != TRANSCODER(pipe)) | |
1334 | return false; | |
1335 | } | |
1336 | return true; | |
1337 | } | |
1338 | ||
1339 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1340 | enum pipe pipe, u32 val) | |
1341 | { | |
1342 | if ((val & LVDS_PORT_EN) == 0) | |
1343 | return false; | |
1344 | ||
1345 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1346 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1347 | return false; | |
1348 | } else { | |
1349 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1350 | return false; | |
1351 | } | |
1352 | return true; | |
1353 | } | |
1354 | ||
1355 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1356 | enum pipe pipe, u32 val) | |
1357 | { | |
1358 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1359 | return false; | |
1360 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1361 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1362 | return false; | |
1363 | } else { | |
1364 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1365 | return false; | |
1366 | } | |
1367 | return true; | |
1368 | } | |
1369 | ||
291906f1 | 1370 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1371 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1372 | { |
47a05eca | 1373 | u32 val = I915_READ(reg); |
4e634389 | 1374 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1375 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1376 | reg, pipe_name(pipe)); |
de9a35ab DV |
1377 | |
1378 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT), | |
1379 | "IBX PCH dp port still using transcoder B\n"); | |
291906f1 JB |
1380 | } |
1381 | ||
1382 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1383 | enum pipe pipe, int reg) | |
1384 | { | |
47a05eca | 1385 | u32 val = I915_READ(reg); |
1519b995 | 1386 | WARN(hdmi_pipe_enabled(dev_priv, val, pipe), |
23c99e77 | 1387 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1388 | reg, pipe_name(pipe)); |
de9a35ab DV |
1389 | |
1390 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT), | |
1391 | "IBX PCH hdmi port still using transcoder B\n"); | |
291906f1 JB |
1392 | } |
1393 | ||
1394 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1395 | enum pipe pipe) | |
1396 | { | |
1397 | int reg; | |
1398 | u32 val; | |
291906f1 | 1399 | |
f0575e92 KP |
1400 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1401 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1402 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1403 | |
1404 | reg = PCH_ADPA; | |
1405 | val = I915_READ(reg); | |
1519b995 | 1406 | WARN(adpa_pipe_enabled(dev_priv, val, pipe), |
291906f1 | 1407 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1408 | pipe_name(pipe)); |
291906f1 JB |
1409 | |
1410 | reg = PCH_LVDS; | |
1411 | val = I915_READ(reg); | |
1519b995 | 1412 | WARN(lvds_pipe_enabled(dev_priv, val, pipe), |
291906f1 | 1413 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1414 | pipe_name(pipe)); |
291906f1 JB |
1415 | |
1416 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB); | |
1417 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC); | |
1418 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMID); | |
1419 | } | |
1420 | ||
63d7bbe9 JB |
1421 | /** |
1422 | * intel_enable_pll - enable a PLL | |
1423 | * @dev_priv: i915 private structure | |
1424 | * @pipe: pipe PLL to enable | |
1425 | * | |
1426 | * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to | |
1427 | * make sure the PLL reg is writable first though, since the panel write | |
1428 | * protect mechanism may be enabled. | |
1429 | * | |
1430 | * Note! This is for pre-ILK only. | |
1431 | */ | |
1432 | static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1433 | { | |
1434 | int reg; | |
1435 | u32 val; | |
1436 | ||
1437 | /* No really, not for ILK+ */ | |
a0c4da24 | 1438 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5); |
63d7bbe9 JB |
1439 | |
1440 | /* PLL is protected by panel, make sure we can write it */ | |
1441 | if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) | |
1442 | assert_panel_unlocked(dev_priv, pipe); | |
1443 | ||
1444 | reg = DPLL(pipe); | |
1445 | val = I915_READ(reg); | |
1446 | val |= DPLL_VCO_ENABLE; | |
1447 | ||
1448 | /* We do this three times for luck */ | |
1449 | I915_WRITE(reg, val); | |
1450 | POSTING_READ(reg); | |
1451 | udelay(150); /* wait for warmup */ | |
1452 | I915_WRITE(reg, val); | |
1453 | POSTING_READ(reg); | |
1454 | udelay(150); /* wait for warmup */ | |
1455 | I915_WRITE(reg, val); | |
1456 | POSTING_READ(reg); | |
1457 | udelay(150); /* wait for warmup */ | |
1458 | } | |
1459 | ||
1460 | /** | |
1461 | * intel_disable_pll - disable a PLL | |
1462 | * @dev_priv: i915 private structure | |
1463 | * @pipe: pipe PLL to disable | |
1464 | * | |
1465 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1466 | * | |
1467 | * Note! This is for pre-ILK only. | |
1468 | */ | |
1469 | static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1470 | { | |
1471 | int reg; | |
1472 | u32 val; | |
1473 | ||
1474 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
1475 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1476 | return; | |
1477 | ||
1478 | /* Make sure the pipe isn't still relying on us */ | |
1479 | assert_pipe_disabled(dev_priv, pipe); | |
1480 | ||
1481 | reg = DPLL(pipe); | |
1482 | val = I915_READ(reg); | |
1483 | val &= ~DPLL_VCO_ENABLE; | |
1484 | I915_WRITE(reg, val); | |
1485 | POSTING_READ(reg); | |
1486 | } | |
1487 | ||
a416edef ED |
1488 | /* SBI access */ |
1489 | static void | |
1490 | intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value) | |
1491 | { | |
1492 | unsigned long flags; | |
1493 | ||
1494 | spin_lock_irqsave(&dev_priv->dpio_lock, flags); | |
39fb50f6 | 1495 | if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, |
a416edef ED |
1496 | 100)) { |
1497 | DRM_ERROR("timeout waiting for SBI to become ready\n"); | |
1498 | goto out_unlock; | |
1499 | } | |
1500 | ||
1501 | I915_WRITE(SBI_ADDR, | |
1502 | (reg << 16)); | |
1503 | I915_WRITE(SBI_DATA, | |
1504 | value); | |
1505 | I915_WRITE(SBI_CTL_STAT, | |
1506 | SBI_BUSY | | |
1507 | SBI_CTL_OP_CRWR); | |
1508 | ||
39fb50f6 | 1509 | if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0, |
a416edef ED |
1510 | 100)) { |
1511 | DRM_ERROR("timeout waiting for SBI to complete write transaction\n"); | |
1512 | goto out_unlock; | |
1513 | } | |
1514 | ||
1515 | out_unlock: | |
1516 | spin_unlock_irqrestore(&dev_priv->dpio_lock, flags); | |
1517 | } | |
1518 | ||
1519 | static u32 | |
1520 | intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg) | |
1521 | { | |
1522 | unsigned long flags; | |
39fb50f6 | 1523 | u32 value = 0; |
a416edef ED |
1524 | |
1525 | spin_lock_irqsave(&dev_priv->dpio_lock, flags); | |
39fb50f6 | 1526 | if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, |
a416edef ED |
1527 | 100)) { |
1528 | DRM_ERROR("timeout waiting for SBI to become ready\n"); | |
1529 | goto out_unlock; | |
1530 | } | |
1531 | ||
1532 | I915_WRITE(SBI_ADDR, | |
1533 | (reg << 16)); | |
1534 | I915_WRITE(SBI_CTL_STAT, | |
1535 | SBI_BUSY | | |
1536 | SBI_CTL_OP_CRRD); | |
1537 | ||
39fb50f6 | 1538 | if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0, |
a416edef ED |
1539 | 100)) { |
1540 | DRM_ERROR("timeout waiting for SBI to complete read transaction\n"); | |
1541 | goto out_unlock; | |
1542 | } | |
1543 | ||
1544 | value = I915_READ(SBI_DATA); | |
1545 | ||
1546 | out_unlock: | |
1547 | spin_unlock_irqrestore(&dev_priv->dpio_lock, flags); | |
1548 | return value; | |
1549 | } | |
1550 | ||
92f2584a JB |
1551 | /** |
1552 | * intel_enable_pch_pll - enable PCH PLL | |
1553 | * @dev_priv: i915 private structure | |
1554 | * @pipe: pipe PLL to enable | |
1555 | * | |
1556 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1557 | * drives the transcoder clock. | |
1558 | */ | |
ee7b9f93 | 1559 | static void intel_enable_pch_pll(struct intel_crtc *intel_crtc) |
92f2584a | 1560 | { |
ee7b9f93 | 1561 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; |
48da64a8 | 1562 | struct intel_pch_pll *pll; |
92f2584a JB |
1563 | int reg; |
1564 | u32 val; | |
1565 | ||
48da64a8 | 1566 | /* PCH PLLs only available on ILK, SNB and IVB */ |
92f2584a | 1567 | BUG_ON(dev_priv->info->gen < 5); |
48da64a8 CW |
1568 | pll = intel_crtc->pch_pll; |
1569 | if (pll == NULL) | |
1570 | return; | |
1571 | ||
1572 | if (WARN_ON(pll->refcount == 0)) | |
1573 | return; | |
ee7b9f93 JB |
1574 | |
1575 | DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n", | |
1576 | pll->pll_reg, pll->active, pll->on, | |
1577 | intel_crtc->base.base.id); | |
92f2584a JB |
1578 | |
1579 | /* PCH refclock must be enabled first */ | |
1580 | assert_pch_refclk_enabled(dev_priv); | |
1581 | ||
ee7b9f93 | 1582 | if (pll->active++ && pll->on) { |
92b27b08 | 1583 | assert_pch_pll_enabled(dev_priv, pll, NULL); |
ee7b9f93 JB |
1584 | return; |
1585 | } | |
1586 | ||
1587 | DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg); | |
1588 | ||
1589 | reg = pll->pll_reg; | |
92f2584a JB |
1590 | val = I915_READ(reg); |
1591 | val |= DPLL_VCO_ENABLE; | |
1592 | I915_WRITE(reg, val); | |
1593 | POSTING_READ(reg); | |
1594 | udelay(200); | |
ee7b9f93 JB |
1595 | |
1596 | pll->on = true; | |
92f2584a JB |
1597 | } |
1598 | ||
ee7b9f93 | 1599 | static void intel_disable_pch_pll(struct intel_crtc *intel_crtc) |
92f2584a | 1600 | { |
ee7b9f93 JB |
1601 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; |
1602 | struct intel_pch_pll *pll = intel_crtc->pch_pll; | |
92f2584a | 1603 | int reg; |
ee7b9f93 | 1604 | u32 val; |
4c609cb8 | 1605 | |
92f2584a JB |
1606 | /* PCH only available on ILK+ */ |
1607 | BUG_ON(dev_priv->info->gen < 5); | |
ee7b9f93 JB |
1608 | if (pll == NULL) |
1609 | return; | |
92f2584a | 1610 | |
48da64a8 CW |
1611 | if (WARN_ON(pll->refcount == 0)) |
1612 | return; | |
7a419866 | 1613 | |
ee7b9f93 JB |
1614 | DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n", |
1615 | pll->pll_reg, pll->active, pll->on, | |
1616 | intel_crtc->base.base.id); | |
7a419866 | 1617 | |
48da64a8 | 1618 | if (WARN_ON(pll->active == 0)) { |
92b27b08 | 1619 | assert_pch_pll_disabled(dev_priv, pll, NULL); |
48da64a8 CW |
1620 | return; |
1621 | } | |
1622 | ||
ee7b9f93 | 1623 | if (--pll->active) { |
92b27b08 | 1624 | assert_pch_pll_enabled(dev_priv, pll, NULL); |
7a419866 | 1625 | return; |
ee7b9f93 JB |
1626 | } |
1627 | ||
1628 | DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg); | |
1629 | ||
1630 | /* Make sure transcoder isn't still depending on us */ | |
1631 | assert_transcoder_disabled(dev_priv, intel_crtc->pipe); | |
7a419866 | 1632 | |
ee7b9f93 | 1633 | reg = pll->pll_reg; |
92f2584a JB |
1634 | val = I915_READ(reg); |
1635 | val &= ~DPLL_VCO_ENABLE; | |
1636 | I915_WRITE(reg, val); | |
1637 | POSTING_READ(reg); | |
1638 | udelay(200); | |
ee7b9f93 JB |
1639 | |
1640 | pll->on = false; | |
92f2584a JB |
1641 | } |
1642 | ||
040484af JB |
1643 | static void intel_enable_transcoder(struct drm_i915_private *dev_priv, |
1644 | enum pipe pipe) | |
1645 | { | |
1646 | int reg; | |
5f7f726d | 1647 | u32 val, pipeconf_val; |
7c26e5c6 | 1648 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
040484af JB |
1649 | |
1650 | /* PCH only available on ILK+ */ | |
1651 | BUG_ON(dev_priv->info->gen < 5); | |
1652 | ||
1653 | /* Make sure PCH DPLL is enabled */ | |
92b27b08 CW |
1654 | assert_pch_pll_enabled(dev_priv, |
1655 | to_intel_crtc(crtc)->pch_pll, | |
1656 | to_intel_crtc(crtc)); | |
040484af JB |
1657 | |
1658 | /* FDI must be feeding us bits for PCH ports */ | |
1659 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1660 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1661 | ||
59c859d6 ED |
1662 | if (IS_HASWELL(dev_priv->dev) && pipe > 0) { |
1663 | DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n"); | |
1664 | return; | |
1665 | } | |
040484af JB |
1666 | reg = TRANSCONF(pipe); |
1667 | val = I915_READ(reg); | |
5f7f726d | 1668 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1669 | |
1670 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1671 | /* | |
1672 | * make the BPC in transcoder be consistent with | |
1673 | * that in pipeconf reg. | |
1674 | */ | |
1675 | val &= ~PIPE_BPC_MASK; | |
5f7f726d | 1676 | val |= pipeconf_val & PIPE_BPC_MASK; |
e9bcff5c | 1677 | } |
5f7f726d PZ |
1678 | |
1679 | val &= ~TRANS_INTERLACE_MASK; | |
1680 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 PZ |
1681 | if (HAS_PCH_IBX(dev_priv->dev) && |
1682 | intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) | |
1683 | val |= TRANS_LEGACY_INTERLACED_ILK; | |
1684 | else | |
1685 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1686 | else |
1687 | val |= TRANS_PROGRESSIVE; | |
1688 | ||
040484af JB |
1689 | I915_WRITE(reg, val | TRANS_ENABLE); |
1690 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
1691 | DRM_ERROR("failed to enable transcoder %d\n", pipe); | |
1692 | } | |
1693 | ||
1694 | static void intel_disable_transcoder(struct drm_i915_private *dev_priv, | |
1695 | enum pipe pipe) | |
1696 | { | |
1697 | int reg; | |
1698 | u32 val; | |
1699 | ||
1700 | /* FDI relies on the transcoder */ | |
1701 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1702 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1703 | ||
291906f1 JB |
1704 | /* Ports must be off as well */ |
1705 | assert_pch_ports_disabled(dev_priv, pipe); | |
1706 | ||
040484af JB |
1707 | reg = TRANSCONF(pipe); |
1708 | val = I915_READ(reg); | |
1709 | val &= ~TRANS_ENABLE; | |
1710 | I915_WRITE(reg, val); | |
1711 | /* wait for PCH transcoder off, transcoder state */ | |
1712 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4c9c18c2 | 1713 | DRM_ERROR("failed to disable transcoder %d\n", pipe); |
040484af JB |
1714 | } |
1715 | ||
b24e7179 | 1716 | /** |
309cfea8 | 1717 | * intel_enable_pipe - enable a pipe, asserting requirements |
b24e7179 JB |
1718 | * @dev_priv: i915 private structure |
1719 | * @pipe: pipe to enable | |
040484af | 1720 | * @pch_port: on ILK+, is this pipe driving a PCH port or not |
b24e7179 JB |
1721 | * |
1722 | * Enable @pipe, making sure that various hardware specific requirements | |
1723 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. | |
1724 | * | |
1725 | * @pipe should be %PIPE_A or %PIPE_B. | |
1726 | * | |
1727 | * Will wait until the pipe is actually running (i.e. first vblank) before | |
1728 | * returning. | |
1729 | */ | |
040484af JB |
1730 | static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
1731 | bool pch_port) | |
b24e7179 JB |
1732 | { |
1733 | int reg; | |
1734 | u32 val; | |
1735 | ||
1736 | /* | |
1737 | * A pipe without a PLL won't actually be able to drive bits from | |
1738 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1739 | * need the check. | |
1740 | */ | |
1741 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
1742 | assert_pll_enabled(dev_priv, pipe); | |
040484af JB |
1743 | else { |
1744 | if (pch_port) { | |
1745 | /* if driving the PCH, we need FDI enabled */ | |
1746 | assert_fdi_rx_pll_enabled(dev_priv, pipe); | |
1747 | assert_fdi_tx_pll_enabled(dev_priv, pipe); | |
1748 | } | |
1749 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1750 | } | |
b24e7179 JB |
1751 | |
1752 | reg = PIPECONF(pipe); | |
1753 | val = I915_READ(reg); | |
00d70b15 CW |
1754 | if (val & PIPECONF_ENABLE) |
1755 | return; | |
1756 | ||
1757 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
b24e7179 JB |
1758 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1759 | } | |
1760 | ||
1761 | /** | |
309cfea8 | 1762 | * intel_disable_pipe - disable a pipe, asserting requirements |
b24e7179 JB |
1763 | * @dev_priv: i915 private structure |
1764 | * @pipe: pipe to disable | |
1765 | * | |
1766 | * Disable @pipe, making sure that various hardware specific requirements | |
1767 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. | |
1768 | * | |
1769 | * @pipe should be %PIPE_A or %PIPE_B. | |
1770 | * | |
1771 | * Will wait until the pipe has shut down before returning. | |
1772 | */ | |
1773 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, | |
1774 | enum pipe pipe) | |
1775 | { | |
1776 | int reg; | |
1777 | u32 val; | |
1778 | ||
1779 | /* | |
1780 | * Make sure planes won't keep trying to pump pixels to us, | |
1781 | * or we might hang the display. | |
1782 | */ | |
1783 | assert_planes_disabled(dev_priv, pipe); | |
1784 | ||
1785 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
1786 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1787 | return; | |
1788 | ||
1789 | reg = PIPECONF(pipe); | |
1790 | val = I915_READ(reg); | |
00d70b15 CW |
1791 | if ((val & PIPECONF_ENABLE) == 0) |
1792 | return; | |
1793 | ||
1794 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); | |
b24e7179 JB |
1795 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
1796 | } | |
1797 | ||
d74362c9 KP |
1798 | /* |
1799 | * Plane regs are double buffered, going from enabled->disabled needs a | |
1800 | * trigger in order to latch. The display address reg provides this. | |
1801 | */ | |
6f1d69b0 | 1802 | void intel_flush_display_plane(struct drm_i915_private *dev_priv, |
d74362c9 KP |
1803 | enum plane plane) |
1804 | { | |
1805 | I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane))); | |
1806 | I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane))); | |
1807 | } | |
1808 | ||
b24e7179 JB |
1809 | /** |
1810 | * intel_enable_plane - enable a display plane on a given pipe | |
1811 | * @dev_priv: i915 private structure | |
1812 | * @plane: plane to enable | |
1813 | * @pipe: pipe being fed | |
1814 | * | |
1815 | * Enable @plane on @pipe, making sure that @pipe is running first. | |
1816 | */ | |
1817 | static void intel_enable_plane(struct drm_i915_private *dev_priv, | |
1818 | enum plane plane, enum pipe pipe) | |
1819 | { | |
1820 | int reg; | |
1821 | u32 val; | |
1822 | ||
1823 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
1824 | assert_pipe_enabled(dev_priv, pipe); | |
1825 | ||
1826 | reg = DSPCNTR(plane); | |
1827 | val = I915_READ(reg); | |
00d70b15 CW |
1828 | if (val & DISPLAY_PLANE_ENABLE) |
1829 | return; | |
1830 | ||
1831 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); | |
d74362c9 | 1832 | intel_flush_display_plane(dev_priv, plane); |
b24e7179 JB |
1833 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1834 | } | |
1835 | ||
b24e7179 JB |
1836 | /** |
1837 | * intel_disable_plane - disable a display plane | |
1838 | * @dev_priv: i915 private structure | |
1839 | * @plane: plane to disable | |
1840 | * @pipe: pipe consuming the data | |
1841 | * | |
1842 | * Disable @plane; should be an independent operation. | |
1843 | */ | |
1844 | static void intel_disable_plane(struct drm_i915_private *dev_priv, | |
1845 | enum plane plane, enum pipe pipe) | |
1846 | { | |
1847 | int reg; | |
1848 | u32 val; | |
1849 | ||
1850 | reg = DSPCNTR(plane); | |
1851 | val = I915_READ(reg); | |
00d70b15 CW |
1852 | if ((val & DISPLAY_PLANE_ENABLE) == 0) |
1853 | return; | |
1854 | ||
1855 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); | |
b24e7179 JB |
1856 | intel_flush_display_plane(dev_priv, plane); |
1857 | intel_wait_for_vblank(dev_priv->dev, pipe); | |
1858 | } | |
1859 | ||
47a05eca | 1860 | static void disable_pch_dp(struct drm_i915_private *dev_priv, |
f0575e92 | 1861 | enum pipe pipe, int reg, u32 port_sel) |
47a05eca JB |
1862 | { |
1863 | u32 val = I915_READ(reg); | |
4e634389 | 1864 | if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) { |
f0575e92 | 1865 | DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe); |
47a05eca | 1866 | I915_WRITE(reg, val & ~DP_PORT_EN); |
f0575e92 | 1867 | } |
47a05eca JB |
1868 | } |
1869 | ||
1870 | static void disable_pch_hdmi(struct drm_i915_private *dev_priv, | |
1871 | enum pipe pipe, int reg) | |
1872 | { | |
1873 | u32 val = I915_READ(reg); | |
1519b995 | 1874 | if (hdmi_pipe_enabled(dev_priv, val, pipe)) { |
f0575e92 KP |
1875 | DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n", |
1876 | reg, pipe); | |
47a05eca | 1877 | I915_WRITE(reg, val & ~PORT_ENABLE); |
f0575e92 | 1878 | } |
47a05eca JB |
1879 | } |
1880 | ||
1881 | /* Disable any ports connected to this transcoder */ | |
1882 | static void intel_disable_pch_ports(struct drm_i915_private *dev_priv, | |
1883 | enum pipe pipe) | |
1884 | { | |
1885 | u32 reg, val; | |
1886 | ||
1887 | val = I915_READ(PCH_PP_CONTROL); | |
1888 | I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS); | |
1889 | ||
f0575e92 KP |
1890 | disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1891 | disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1892 | disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
47a05eca JB |
1893 | |
1894 | reg = PCH_ADPA; | |
1895 | val = I915_READ(reg); | |
1519b995 | 1896 | if (adpa_pipe_enabled(dev_priv, val, pipe)) |
47a05eca JB |
1897 | I915_WRITE(reg, val & ~ADPA_DAC_ENABLE); |
1898 | ||
1899 | reg = PCH_LVDS; | |
1900 | val = I915_READ(reg); | |
1519b995 KP |
1901 | if (lvds_pipe_enabled(dev_priv, val, pipe)) { |
1902 | DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val); | |
47a05eca JB |
1903 | I915_WRITE(reg, val & ~LVDS_PORT_EN); |
1904 | POSTING_READ(reg); | |
1905 | udelay(100); | |
1906 | } | |
1907 | ||
1908 | disable_pch_hdmi(dev_priv, pipe, HDMIB); | |
1909 | disable_pch_hdmi(dev_priv, pipe, HDMIC); | |
1910 | disable_pch_hdmi(dev_priv, pipe, HDMID); | |
1911 | } | |
1912 | ||
127bd2ac | 1913 | int |
48b956c5 | 1914 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
05394f39 | 1915 | struct drm_i915_gem_object *obj, |
919926ae | 1916 | struct intel_ring_buffer *pipelined) |
6b95a207 | 1917 | { |
ce453d81 | 1918 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
1919 | u32 alignment; |
1920 | int ret; | |
1921 | ||
05394f39 | 1922 | switch (obj->tiling_mode) { |
6b95a207 | 1923 | case I915_TILING_NONE: |
534843da CW |
1924 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
1925 | alignment = 128 * 1024; | |
a6c45cf0 | 1926 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
1927 | alignment = 4 * 1024; |
1928 | else | |
1929 | alignment = 64 * 1024; | |
6b95a207 KH |
1930 | break; |
1931 | case I915_TILING_X: | |
1932 | /* pin() will align the object as required by fence */ | |
1933 | alignment = 0; | |
1934 | break; | |
1935 | case I915_TILING_Y: | |
1936 | /* FIXME: Is this true? */ | |
1937 | DRM_ERROR("Y tiled not allowed for scan out buffers\n"); | |
1938 | return -EINVAL; | |
1939 | default: | |
1940 | BUG(); | |
1941 | } | |
1942 | ||
ce453d81 | 1943 | dev_priv->mm.interruptible = false; |
2da3b9b9 | 1944 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
48b956c5 | 1945 | if (ret) |
ce453d81 | 1946 | goto err_interruptible; |
6b95a207 KH |
1947 | |
1948 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
1949 | * fence, whereas 965+ only requires a fence if using | |
1950 | * framebuffer compression. For simplicity, we always install | |
1951 | * a fence as the cost is not that onerous. | |
1952 | */ | |
06d98131 | 1953 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
1954 | if (ret) |
1955 | goto err_unpin; | |
1690e1eb | 1956 | |
9a5a53b3 | 1957 | i915_gem_object_pin_fence(obj); |
6b95a207 | 1958 | |
ce453d81 | 1959 | dev_priv->mm.interruptible = true; |
6b95a207 | 1960 | return 0; |
48b956c5 CW |
1961 | |
1962 | err_unpin: | |
1963 | i915_gem_object_unpin(obj); | |
ce453d81 CW |
1964 | err_interruptible: |
1965 | dev_priv->mm.interruptible = true; | |
48b956c5 | 1966 | return ret; |
6b95a207 KH |
1967 | } |
1968 | ||
1690e1eb CW |
1969 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
1970 | { | |
1971 | i915_gem_object_unpin_fence(obj); | |
1972 | i915_gem_object_unpin(obj); | |
1973 | } | |
1974 | ||
c2c75131 DV |
1975 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
1976 | * is assumed to be a power-of-two. */ | |
1977 | static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y, | |
1978 | unsigned int bpp, | |
1979 | unsigned int pitch) | |
1980 | { | |
1981 | int tile_rows, tiles; | |
1982 | ||
1983 | tile_rows = *y / 8; | |
1984 | *y %= 8; | |
1985 | tiles = *x / (512/bpp); | |
1986 | *x %= 512/bpp; | |
1987 | ||
1988 | return tile_rows * pitch * 8 + tiles * 4096; | |
1989 | } | |
1990 | ||
17638cd6 JB |
1991 | static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
1992 | int x, int y) | |
81255565 JB |
1993 | { |
1994 | struct drm_device *dev = crtc->dev; | |
1995 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1996 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1997 | struct intel_framebuffer *intel_fb; | |
05394f39 | 1998 | struct drm_i915_gem_object *obj; |
81255565 | 1999 | int plane = intel_crtc->plane; |
e506a0c6 | 2000 | unsigned long linear_offset; |
81255565 | 2001 | u32 dspcntr; |
5eddb70b | 2002 | u32 reg; |
81255565 JB |
2003 | |
2004 | switch (plane) { | |
2005 | case 0: | |
2006 | case 1: | |
2007 | break; | |
2008 | default: | |
2009 | DRM_ERROR("Can't update plane %d in SAREA\n", plane); | |
2010 | return -EINVAL; | |
2011 | } | |
2012 | ||
2013 | intel_fb = to_intel_framebuffer(fb); | |
2014 | obj = intel_fb->obj; | |
81255565 | 2015 | |
5eddb70b CW |
2016 | reg = DSPCNTR(plane); |
2017 | dspcntr = I915_READ(reg); | |
81255565 JB |
2018 | /* Mask out pixel format bits in case we change it */ |
2019 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
2020 | switch (fb->bits_per_pixel) { | |
2021 | case 8: | |
2022 | dspcntr |= DISPPLANE_8BPP; | |
2023 | break; | |
2024 | case 16: | |
2025 | if (fb->depth == 15) | |
2026 | dspcntr |= DISPPLANE_15_16BPP; | |
2027 | else | |
2028 | dspcntr |= DISPPLANE_16BPP; | |
2029 | break; | |
2030 | case 24: | |
2031 | case 32: | |
2032 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; | |
2033 | break; | |
2034 | default: | |
17638cd6 | 2035 | DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel); |
81255565 JB |
2036 | return -EINVAL; |
2037 | } | |
a6c45cf0 | 2038 | if (INTEL_INFO(dev)->gen >= 4) { |
05394f39 | 2039 | if (obj->tiling_mode != I915_TILING_NONE) |
81255565 JB |
2040 | dspcntr |= DISPPLANE_TILED; |
2041 | else | |
2042 | dspcntr &= ~DISPPLANE_TILED; | |
2043 | } | |
2044 | ||
5eddb70b | 2045 | I915_WRITE(reg, dspcntr); |
81255565 | 2046 | |
e506a0c6 | 2047 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
81255565 | 2048 | |
c2c75131 DV |
2049 | if (INTEL_INFO(dev)->gen >= 4) { |
2050 | intel_crtc->dspaddr_offset = | |
2051 | gen4_compute_dspaddr_offset_xtiled(&x, &y, | |
2052 | fb->bits_per_pixel / 8, | |
2053 | fb->pitches[0]); | |
2054 | linear_offset -= intel_crtc->dspaddr_offset; | |
2055 | } else { | |
e506a0c6 | 2056 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2057 | } |
e506a0c6 DV |
2058 | |
2059 | DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n", | |
2060 | obj->gtt_offset, linear_offset, x, y, fb->pitches[0]); | |
01f2c773 | 2061 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2062 | if (INTEL_INFO(dev)->gen >= 4) { |
c2c75131 DV |
2063 | I915_MODIFY_DISPBASE(DSPSURF(plane), |
2064 | obj->gtt_offset + intel_crtc->dspaddr_offset); | |
5eddb70b | 2065 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2066 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2067 | } else |
e506a0c6 | 2068 | I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset); |
5eddb70b | 2069 | POSTING_READ(reg); |
81255565 | 2070 | |
17638cd6 JB |
2071 | return 0; |
2072 | } | |
2073 | ||
2074 | static int ironlake_update_plane(struct drm_crtc *crtc, | |
2075 | struct drm_framebuffer *fb, int x, int y) | |
2076 | { | |
2077 | struct drm_device *dev = crtc->dev; | |
2078 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2079 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2080 | struct intel_framebuffer *intel_fb; | |
2081 | struct drm_i915_gem_object *obj; | |
2082 | int plane = intel_crtc->plane; | |
e506a0c6 | 2083 | unsigned long linear_offset; |
17638cd6 JB |
2084 | u32 dspcntr; |
2085 | u32 reg; | |
2086 | ||
2087 | switch (plane) { | |
2088 | case 0: | |
2089 | case 1: | |
27f8227b | 2090 | case 2: |
17638cd6 JB |
2091 | break; |
2092 | default: | |
2093 | DRM_ERROR("Can't update plane %d in SAREA\n", plane); | |
2094 | return -EINVAL; | |
2095 | } | |
2096 | ||
2097 | intel_fb = to_intel_framebuffer(fb); | |
2098 | obj = intel_fb->obj; | |
2099 | ||
2100 | reg = DSPCNTR(plane); | |
2101 | dspcntr = I915_READ(reg); | |
2102 | /* Mask out pixel format bits in case we change it */ | |
2103 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
2104 | switch (fb->bits_per_pixel) { | |
2105 | case 8: | |
2106 | dspcntr |= DISPPLANE_8BPP; | |
2107 | break; | |
2108 | case 16: | |
2109 | if (fb->depth != 16) | |
2110 | return -EINVAL; | |
2111 | ||
2112 | dspcntr |= DISPPLANE_16BPP; | |
2113 | break; | |
2114 | case 24: | |
2115 | case 32: | |
2116 | if (fb->depth == 24) | |
2117 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; | |
2118 | else if (fb->depth == 30) | |
2119 | dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA; | |
2120 | else | |
2121 | return -EINVAL; | |
2122 | break; | |
2123 | default: | |
2124 | DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel); | |
2125 | return -EINVAL; | |
2126 | } | |
2127 | ||
2128 | if (obj->tiling_mode != I915_TILING_NONE) | |
2129 | dspcntr |= DISPPLANE_TILED; | |
2130 | else | |
2131 | dspcntr &= ~DISPPLANE_TILED; | |
2132 | ||
2133 | /* must disable */ | |
2134 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2135 | ||
2136 | I915_WRITE(reg, dspcntr); | |
2137 | ||
e506a0c6 | 2138 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
c2c75131 DV |
2139 | intel_crtc->dspaddr_offset = |
2140 | gen4_compute_dspaddr_offset_xtiled(&x, &y, | |
2141 | fb->bits_per_pixel / 8, | |
2142 | fb->pitches[0]); | |
2143 | linear_offset -= intel_crtc->dspaddr_offset; | |
17638cd6 | 2144 | |
e506a0c6 DV |
2145 | DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n", |
2146 | obj->gtt_offset, linear_offset, x, y, fb->pitches[0]); | |
01f2c773 | 2147 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
c2c75131 DV |
2148 | I915_MODIFY_DISPBASE(DSPSURF(plane), |
2149 | obj->gtt_offset + intel_crtc->dspaddr_offset); | |
17638cd6 | 2150 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2151 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
17638cd6 JB |
2152 | POSTING_READ(reg); |
2153 | ||
2154 | return 0; | |
2155 | } | |
2156 | ||
2157 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ | |
2158 | static int | |
2159 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
2160 | int x, int y, enum mode_set_atomic state) | |
2161 | { | |
2162 | struct drm_device *dev = crtc->dev; | |
2163 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 2164 | |
6b8e6ed0 CW |
2165 | if (dev_priv->display.disable_fbc) |
2166 | dev_priv->display.disable_fbc(dev); | |
3dec0095 | 2167 | intel_increase_pllclock(crtc); |
81255565 | 2168 | |
6b8e6ed0 | 2169 | return dev_priv->display.update_plane(crtc, fb, x, y); |
81255565 JB |
2170 | } |
2171 | ||
14667a4b CW |
2172 | static int |
2173 | intel_finish_fb(struct drm_framebuffer *old_fb) | |
2174 | { | |
2175 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; | |
2176 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2177 | bool was_interruptible = dev_priv->mm.interruptible; | |
2178 | int ret; | |
2179 | ||
2180 | wait_event(dev_priv->pending_flip_queue, | |
2181 | atomic_read(&dev_priv->mm.wedged) || | |
2182 | atomic_read(&obj->pending_flip) == 0); | |
2183 | ||
2184 | /* Big Hammer, we also need to ensure that any pending | |
2185 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
2186 | * current scanout is retired before unpinning the old | |
2187 | * framebuffer. | |
2188 | * | |
2189 | * This should only fail upon a hung GPU, in which case we | |
2190 | * can safely continue. | |
2191 | */ | |
2192 | dev_priv->mm.interruptible = false; | |
2193 | ret = i915_gem_object_finish_gpu(obj); | |
2194 | dev_priv->mm.interruptible = was_interruptible; | |
2195 | ||
2196 | return ret; | |
2197 | } | |
2198 | ||
5c3b82e2 | 2199 | static int |
3c4fdcfb KH |
2200 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
2201 | struct drm_framebuffer *old_fb) | |
79e53945 JB |
2202 | { |
2203 | struct drm_device *dev = crtc->dev; | |
6b8e6ed0 | 2204 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 JB |
2205 | struct drm_i915_master_private *master_priv; |
2206 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5c3b82e2 | 2207 | int ret; |
79e53945 JB |
2208 | |
2209 | /* no fb bound */ | |
2210 | if (!crtc->fb) { | |
a5071c2f | 2211 | DRM_ERROR("No FB bound\n"); |
5c3b82e2 CW |
2212 | return 0; |
2213 | } | |
2214 | ||
5826eca5 ED |
2215 | if(intel_crtc->plane > dev_priv->num_pipe) { |
2216 | DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n", | |
2217 | intel_crtc->plane, | |
2218 | dev_priv->num_pipe); | |
5c3b82e2 | 2219 | return -EINVAL; |
79e53945 JB |
2220 | } |
2221 | ||
5c3b82e2 | 2222 | mutex_lock(&dev->struct_mutex); |
265db958 CW |
2223 | ret = intel_pin_and_fence_fb_obj(dev, |
2224 | to_intel_framebuffer(crtc->fb)->obj, | |
919926ae | 2225 | NULL); |
5c3b82e2 CW |
2226 | if (ret != 0) { |
2227 | mutex_unlock(&dev->struct_mutex); | |
a5071c2f | 2228 | DRM_ERROR("pin & fence failed\n"); |
5c3b82e2 CW |
2229 | return ret; |
2230 | } | |
79e53945 | 2231 | |
14667a4b CW |
2232 | if (old_fb) |
2233 | intel_finish_fb(old_fb); | |
265db958 | 2234 | |
6b8e6ed0 | 2235 | ret = dev_priv->display.update_plane(crtc, crtc->fb, x, y); |
4e6cfefc | 2236 | if (ret) { |
1690e1eb | 2237 | intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); |
5c3b82e2 | 2238 | mutex_unlock(&dev->struct_mutex); |
a5071c2f | 2239 | DRM_ERROR("failed to update base address\n"); |
4e6cfefc | 2240 | return ret; |
79e53945 | 2241 | } |
3c4fdcfb | 2242 | |
b7f1de28 CW |
2243 | if (old_fb) { |
2244 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1690e1eb | 2245 | intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); |
b7f1de28 | 2246 | } |
652c393a | 2247 | |
6b8e6ed0 | 2248 | intel_update_fbc(dev); |
5c3b82e2 | 2249 | mutex_unlock(&dev->struct_mutex); |
79e53945 JB |
2250 | |
2251 | if (!dev->primary->master) | |
5c3b82e2 | 2252 | return 0; |
79e53945 JB |
2253 | |
2254 | master_priv = dev->primary->master->driver_priv; | |
2255 | if (!master_priv->sarea_priv) | |
5c3b82e2 | 2256 | return 0; |
79e53945 | 2257 | |
265db958 | 2258 | if (intel_crtc->pipe) { |
79e53945 JB |
2259 | master_priv->sarea_priv->pipeB_x = x; |
2260 | master_priv->sarea_priv->pipeB_y = y; | |
5c3b82e2 CW |
2261 | } else { |
2262 | master_priv->sarea_priv->pipeA_x = x; | |
2263 | master_priv->sarea_priv->pipeA_y = y; | |
79e53945 | 2264 | } |
5c3b82e2 CW |
2265 | |
2266 | return 0; | |
79e53945 JB |
2267 | } |
2268 | ||
5eddb70b | 2269 | static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock) |
32f9d658 ZW |
2270 | { |
2271 | struct drm_device *dev = crtc->dev; | |
2272 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2273 | u32 dpa_ctl; | |
2274 | ||
28c97730 | 2275 | DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock); |
32f9d658 ZW |
2276 | dpa_ctl = I915_READ(DP_A); |
2277 | dpa_ctl &= ~DP_PLL_FREQ_MASK; | |
2278 | ||
2279 | if (clock < 200000) { | |
2280 | u32 temp; | |
2281 | dpa_ctl |= DP_PLL_FREQ_160MHZ; | |
2282 | /* workaround for 160Mhz: | |
2283 | 1) program 0x4600c bits 15:0 = 0x8124 | |
2284 | 2) program 0x46010 bit 0 = 1 | |
2285 | 3) program 0x46034 bit 24 = 1 | |
2286 | 4) program 0x64000 bit 14 = 1 | |
2287 | */ | |
2288 | temp = I915_READ(0x4600c); | |
2289 | temp &= 0xffff0000; | |
2290 | I915_WRITE(0x4600c, temp | 0x8124); | |
2291 | ||
2292 | temp = I915_READ(0x46010); | |
2293 | I915_WRITE(0x46010, temp | 1); | |
2294 | ||
2295 | temp = I915_READ(0x46034); | |
2296 | I915_WRITE(0x46034, temp | (1 << 24)); | |
2297 | } else { | |
2298 | dpa_ctl |= DP_PLL_FREQ_270MHZ; | |
2299 | } | |
2300 | I915_WRITE(DP_A, dpa_ctl); | |
2301 | ||
5eddb70b | 2302 | POSTING_READ(DP_A); |
32f9d658 ZW |
2303 | udelay(500); |
2304 | } | |
2305 | ||
5e84e1a4 ZW |
2306 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
2307 | { | |
2308 | struct drm_device *dev = crtc->dev; | |
2309 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2310 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2311 | int pipe = intel_crtc->pipe; | |
2312 | u32 reg, temp; | |
2313 | ||
2314 | /* enable normal train */ | |
2315 | reg = FDI_TX_CTL(pipe); | |
2316 | temp = I915_READ(reg); | |
61e499bf | 2317 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
2318 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2319 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
2320 | } else { |
2321 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2322 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 2323 | } |
5e84e1a4 ZW |
2324 | I915_WRITE(reg, temp); |
2325 | ||
2326 | reg = FDI_RX_CTL(pipe); | |
2327 | temp = I915_READ(reg); | |
2328 | if (HAS_PCH_CPT(dev)) { | |
2329 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2330 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
2331 | } else { | |
2332 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2333 | temp |= FDI_LINK_TRAIN_NONE; | |
2334 | } | |
2335 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
2336 | ||
2337 | /* wait one idle pattern time */ | |
2338 | POSTING_READ(reg); | |
2339 | udelay(1000); | |
357555c0 JB |
2340 | |
2341 | /* IVB wants error correction enabled */ | |
2342 | if (IS_IVYBRIDGE(dev)) | |
2343 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
2344 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
2345 | } |
2346 | ||
291427f5 JB |
2347 | static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe) |
2348 | { | |
2349 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2350 | u32 flags = I915_READ(SOUTH_CHICKEN1); | |
2351 | ||
2352 | flags |= FDI_PHASE_SYNC_OVR(pipe); | |
2353 | I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */ | |
2354 | flags |= FDI_PHASE_SYNC_EN(pipe); | |
2355 | I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */ | |
2356 | POSTING_READ(SOUTH_CHICKEN1); | |
2357 | } | |
2358 | ||
8db9d77b ZW |
2359 | /* The FDI link training functions for ILK/Ibexpeak. */ |
2360 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
2361 | { | |
2362 | struct drm_device *dev = crtc->dev; | |
2363 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2364 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2365 | int pipe = intel_crtc->pipe; | |
0fc932b8 | 2366 | int plane = intel_crtc->plane; |
5eddb70b | 2367 | u32 reg, temp, tries; |
8db9d77b | 2368 | |
0fc932b8 JB |
2369 | /* FDI needs bits from pipe & plane first */ |
2370 | assert_pipe_enabled(dev_priv, pipe); | |
2371 | assert_plane_enabled(dev_priv, plane); | |
2372 | ||
e1a44743 AJ |
2373 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2374 | for train result */ | |
5eddb70b CW |
2375 | reg = FDI_RX_IMR(pipe); |
2376 | temp = I915_READ(reg); | |
e1a44743 AJ |
2377 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2378 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2379 | I915_WRITE(reg, temp); |
2380 | I915_READ(reg); | |
e1a44743 AJ |
2381 | udelay(150); |
2382 | ||
8db9d77b | 2383 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2384 | reg = FDI_TX_CTL(pipe); |
2385 | temp = I915_READ(reg); | |
77ffb597 AJ |
2386 | temp &= ~(7 << 19); |
2387 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
8db9d77b ZW |
2388 | temp &= ~FDI_LINK_TRAIN_NONE; |
2389 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 2390 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2391 | |
5eddb70b CW |
2392 | reg = FDI_RX_CTL(pipe); |
2393 | temp = I915_READ(reg); | |
8db9d77b ZW |
2394 | temp &= ~FDI_LINK_TRAIN_NONE; |
2395 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
2396 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2397 | ||
2398 | POSTING_READ(reg); | |
8db9d77b ZW |
2399 | udelay(150); |
2400 | ||
5b2adf89 | 2401 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
6f06ce18 JB |
2402 | if (HAS_PCH_IBX(dev)) { |
2403 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); | |
2404 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
2405 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
2406 | } | |
5b2adf89 | 2407 | |
5eddb70b | 2408 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2409 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2410 | temp = I915_READ(reg); |
8db9d77b ZW |
2411 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2412 | ||
2413 | if ((temp & FDI_RX_BIT_LOCK)) { | |
2414 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 2415 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
2416 | break; |
2417 | } | |
8db9d77b | 2418 | } |
e1a44743 | 2419 | if (tries == 5) |
5eddb70b | 2420 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2421 | |
2422 | /* Train 2 */ | |
5eddb70b CW |
2423 | reg = FDI_TX_CTL(pipe); |
2424 | temp = I915_READ(reg); | |
8db9d77b ZW |
2425 | temp &= ~FDI_LINK_TRAIN_NONE; |
2426 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2427 | I915_WRITE(reg, temp); |
8db9d77b | 2428 | |
5eddb70b CW |
2429 | reg = FDI_RX_CTL(pipe); |
2430 | temp = I915_READ(reg); | |
8db9d77b ZW |
2431 | temp &= ~FDI_LINK_TRAIN_NONE; |
2432 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2433 | I915_WRITE(reg, temp); |
8db9d77b | 2434 | |
5eddb70b CW |
2435 | POSTING_READ(reg); |
2436 | udelay(150); | |
8db9d77b | 2437 | |
5eddb70b | 2438 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2439 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2440 | temp = I915_READ(reg); |
8db9d77b ZW |
2441 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2442 | ||
2443 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 2444 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
2445 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2446 | break; | |
2447 | } | |
8db9d77b | 2448 | } |
e1a44743 | 2449 | if (tries == 5) |
5eddb70b | 2450 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2451 | |
2452 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 2453 | |
8db9d77b ZW |
2454 | } |
2455 | ||
0206e353 | 2456 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
2457 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
2458 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
2459 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
2460 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
2461 | }; | |
2462 | ||
2463 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
2464 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
2465 | { | |
2466 | struct drm_device *dev = crtc->dev; | |
2467 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2468 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2469 | int pipe = intel_crtc->pipe; | |
fa37d39e | 2470 | u32 reg, temp, i, retry; |
8db9d77b | 2471 | |
e1a44743 AJ |
2472 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2473 | for train result */ | |
5eddb70b CW |
2474 | reg = FDI_RX_IMR(pipe); |
2475 | temp = I915_READ(reg); | |
e1a44743 AJ |
2476 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2477 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2478 | I915_WRITE(reg, temp); |
2479 | ||
2480 | POSTING_READ(reg); | |
e1a44743 AJ |
2481 | udelay(150); |
2482 | ||
8db9d77b | 2483 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2484 | reg = FDI_TX_CTL(pipe); |
2485 | temp = I915_READ(reg); | |
77ffb597 AJ |
2486 | temp &= ~(7 << 19); |
2487 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
8db9d77b ZW |
2488 | temp &= ~FDI_LINK_TRAIN_NONE; |
2489 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2490 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2491 | /* SNB-B */ | |
2492 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 2493 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2494 | |
5eddb70b CW |
2495 | reg = FDI_RX_CTL(pipe); |
2496 | temp = I915_READ(reg); | |
8db9d77b ZW |
2497 | if (HAS_PCH_CPT(dev)) { |
2498 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2499 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2500 | } else { | |
2501 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2502 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2503 | } | |
5eddb70b CW |
2504 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2505 | ||
2506 | POSTING_READ(reg); | |
8db9d77b ZW |
2507 | udelay(150); |
2508 | ||
291427f5 JB |
2509 | if (HAS_PCH_CPT(dev)) |
2510 | cpt_phase_pointer_enable(dev, pipe); | |
2511 | ||
0206e353 | 2512 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2513 | reg = FDI_TX_CTL(pipe); |
2514 | temp = I915_READ(reg); | |
8db9d77b ZW |
2515 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2516 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2517 | I915_WRITE(reg, temp); |
2518 | ||
2519 | POSTING_READ(reg); | |
8db9d77b ZW |
2520 | udelay(500); |
2521 | ||
fa37d39e SP |
2522 | for (retry = 0; retry < 5; retry++) { |
2523 | reg = FDI_RX_IIR(pipe); | |
2524 | temp = I915_READ(reg); | |
2525 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2526 | if (temp & FDI_RX_BIT_LOCK) { | |
2527 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
2528 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
2529 | break; | |
2530 | } | |
2531 | udelay(50); | |
8db9d77b | 2532 | } |
fa37d39e SP |
2533 | if (retry < 5) |
2534 | break; | |
8db9d77b ZW |
2535 | } |
2536 | if (i == 4) | |
5eddb70b | 2537 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2538 | |
2539 | /* Train 2 */ | |
5eddb70b CW |
2540 | reg = FDI_TX_CTL(pipe); |
2541 | temp = I915_READ(reg); | |
8db9d77b ZW |
2542 | temp &= ~FDI_LINK_TRAIN_NONE; |
2543 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2544 | if (IS_GEN6(dev)) { | |
2545 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2546 | /* SNB-B */ | |
2547 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
2548 | } | |
5eddb70b | 2549 | I915_WRITE(reg, temp); |
8db9d77b | 2550 | |
5eddb70b CW |
2551 | reg = FDI_RX_CTL(pipe); |
2552 | temp = I915_READ(reg); | |
8db9d77b ZW |
2553 | if (HAS_PCH_CPT(dev)) { |
2554 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2555 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
2556 | } else { | |
2557 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2558 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2559 | } | |
5eddb70b CW |
2560 | I915_WRITE(reg, temp); |
2561 | ||
2562 | POSTING_READ(reg); | |
8db9d77b ZW |
2563 | udelay(150); |
2564 | ||
0206e353 | 2565 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2566 | reg = FDI_TX_CTL(pipe); |
2567 | temp = I915_READ(reg); | |
8db9d77b ZW |
2568 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2569 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2570 | I915_WRITE(reg, temp); |
2571 | ||
2572 | POSTING_READ(reg); | |
8db9d77b ZW |
2573 | udelay(500); |
2574 | ||
fa37d39e SP |
2575 | for (retry = 0; retry < 5; retry++) { |
2576 | reg = FDI_RX_IIR(pipe); | |
2577 | temp = I915_READ(reg); | |
2578 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2579 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
2580 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
2581 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
2582 | break; | |
2583 | } | |
2584 | udelay(50); | |
8db9d77b | 2585 | } |
fa37d39e SP |
2586 | if (retry < 5) |
2587 | break; | |
8db9d77b ZW |
2588 | } |
2589 | if (i == 4) | |
5eddb70b | 2590 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2591 | |
2592 | DRM_DEBUG_KMS("FDI train done.\n"); | |
2593 | } | |
2594 | ||
357555c0 JB |
2595 | /* Manual link training for Ivy Bridge A0 parts */ |
2596 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
2597 | { | |
2598 | struct drm_device *dev = crtc->dev; | |
2599 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2600 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2601 | int pipe = intel_crtc->pipe; | |
2602 | u32 reg, temp, i; | |
2603 | ||
2604 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
2605 | for train result */ | |
2606 | reg = FDI_RX_IMR(pipe); | |
2607 | temp = I915_READ(reg); | |
2608 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
2609 | temp &= ~FDI_RX_BIT_LOCK; | |
2610 | I915_WRITE(reg, temp); | |
2611 | ||
2612 | POSTING_READ(reg); | |
2613 | udelay(150); | |
2614 | ||
2615 | /* enable CPU FDI TX and PCH FDI RX */ | |
2616 | reg = FDI_TX_CTL(pipe); | |
2617 | temp = I915_READ(reg); | |
2618 | temp &= ~(7 << 19); | |
2619 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
2620 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
2621 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; | |
2622 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2623 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
c4f9c4c2 | 2624 | temp |= FDI_COMPOSITE_SYNC; |
357555c0 JB |
2625 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
2626 | ||
2627 | reg = FDI_RX_CTL(pipe); | |
2628 | temp = I915_READ(reg); | |
2629 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
2630 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2631 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
c4f9c4c2 | 2632 | temp |= FDI_COMPOSITE_SYNC; |
357555c0 JB |
2633 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2634 | ||
2635 | POSTING_READ(reg); | |
2636 | udelay(150); | |
2637 | ||
291427f5 JB |
2638 | if (HAS_PCH_CPT(dev)) |
2639 | cpt_phase_pointer_enable(dev, pipe); | |
2640 | ||
0206e353 | 2641 | for (i = 0; i < 4; i++) { |
357555c0 JB |
2642 | reg = FDI_TX_CTL(pipe); |
2643 | temp = I915_READ(reg); | |
2644 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2645 | temp |= snb_b_fdi_train_param[i]; | |
2646 | I915_WRITE(reg, temp); | |
2647 | ||
2648 | POSTING_READ(reg); | |
2649 | udelay(500); | |
2650 | ||
2651 | reg = FDI_RX_IIR(pipe); | |
2652 | temp = I915_READ(reg); | |
2653 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2654 | ||
2655 | if (temp & FDI_RX_BIT_LOCK || | |
2656 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
2657 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
2658 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
2659 | break; | |
2660 | } | |
2661 | } | |
2662 | if (i == 4) | |
2663 | DRM_ERROR("FDI train 1 fail!\n"); | |
2664 | ||
2665 | /* Train 2 */ | |
2666 | reg = FDI_TX_CTL(pipe); | |
2667 | temp = I915_READ(reg); | |
2668 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; | |
2669 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
2670 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2671 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
2672 | I915_WRITE(reg, temp); | |
2673 | ||
2674 | reg = FDI_RX_CTL(pipe); | |
2675 | temp = I915_READ(reg); | |
2676 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2677 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
2678 | I915_WRITE(reg, temp); | |
2679 | ||
2680 | POSTING_READ(reg); | |
2681 | udelay(150); | |
2682 | ||
0206e353 | 2683 | for (i = 0; i < 4; i++) { |
357555c0 JB |
2684 | reg = FDI_TX_CTL(pipe); |
2685 | temp = I915_READ(reg); | |
2686 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2687 | temp |= snb_b_fdi_train_param[i]; | |
2688 | I915_WRITE(reg, temp); | |
2689 | ||
2690 | POSTING_READ(reg); | |
2691 | udelay(500); | |
2692 | ||
2693 | reg = FDI_RX_IIR(pipe); | |
2694 | temp = I915_READ(reg); | |
2695 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2696 | ||
2697 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
2698 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
2699 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
2700 | break; | |
2701 | } | |
2702 | } | |
2703 | if (i == 4) | |
2704 | DRM_ERROR("FDI train 2 fail!\n"); | |
2705 | ||
2706 | DRM_DEBUG_KMS("FDI train done.\n"); | |
2707 | } | |
2708 | ||
2709 | static void ironlake_fdi_pll_enable(struct drm_crtc *crtc) | |
2c07245f ZW |
2710 | { |
2711 | struct drm_device *dev = crtc->dev; | |
2712 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2713 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2714 | int pipe = intel_crtc->pipe; | |
5eddb70b | 2715 | u32 reg, temp; |
79e53945 | 2716 | |
c64e311e | 2717 | /* Write the TU size bits so error detection works */ |
5eddb70b CW |
2718 | I915_WRITE(FDI_RX_TUSIZE1(pipe), |
2719 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
c64e311e | 2720 | |
c98e9dcf | 2721 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
2722 | reg = FDI_RX_CTL(pipe); |
2723 | temp = I915_READ(reg); | |
2724 | temp &= ~((0x7 << 19) | (0x7 << 16)); | |
c98e9dcf | 2725 | temp |= (intel_crtc->fdi_lanes - 1) << 19; |
5eddb70b CW |
2726 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; |
2727 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); | |
2728 | ||
2729 | POSTING_READ(reg); | |
c98e9dcf JB |
2730 | udelay(200); |
2731 | ||
2732 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
2733 | temp = I915_READ(reg); |
2734 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
2735 | ||
2736 | POSTING_READ(reg); | |
c98e9dcf JB |
2737 | udelay(200); |
2738 | ||
bf507ef7 ED |
2739 | /* On Haswell, the PLL configuration for ports and pipes is handled |
2740 | * separately, as part of DDI setup */ | |
2741 | if (!IS_HASWELL(dev)) { | |
2742 | /* Enable CPU FDI TX PLL, always on for Ironlake */ | |
2743 | reg = FDI_TX_CTL(pipe); | |
2744 | temp = I915_READ(reg); | |
2745 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
2746 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 2747 | |
bf507ef7 ED |
2748 | POSTING_READ(reg); |
2749 | udelay(100); | |
2750 | } | |
6be4a607 | 2751 | } |
0e23b99d JB |
2752 | } |
2753 | ||
291427f5 JB |
2754 | static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe) |
2755 | { | |
2756 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2757 | u32 flags = I915_READ(SOUTH_CHICKEN1); | |
2758 | ||
2759 | flags &= ~(FDI_PHASE_SYNC_EN(pipe)); | |
2760 | I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */ | |
2761 | flags &= ~(FDI_PHASE_SYNC_OVR(pipe)); | |
2762 | I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */ | |
2763 | POSTING_READ(SOUTH_CHICKEN1); | |
2764 | } | |
0fc932b8 JB |
2765 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
2766 | { | |
2767 | struct drm_device *dev = crtc->dev; | |
2768 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2769 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2770 | int pipe = intel_crtc->pipe; | |
2771 | u32 reg, temp; | |
2772 | ||
2773 | /* disable CPU FDI tx and PCH FDI rx */ | |
2774 | reg = FDI_TX_CTL(pipe); | |
2775 | temp = I915_READ(reg); | |
2776 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
2777 | POSTING_READ(reg); | |
2778 | ||
2779 | reg = FDI_RX_CTL(pipe); | |
2780 | temp = I915_READ(reg); | |
2781 | temp &= ~(0x7 << 16); | |
2782 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; | |
2783 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); | |
2784 | ||
2785 | POSTING_READ(reg); | |
2786 | udelay(100); | |
2787 | ||
2788 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
6f06ce18 JB |
2789 | if (HAS_PCH_IBX(dev)) { |
2790 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); | |
0fc932b8 JB |
2791 | I915_WRITE(FDI_RX_CHICKEN(pipe), |
2792 | I915_READ(FDI_RX_CHICKEN(pipe) & | |
6f06ce18 | 2793 | ~FDI_RX_PHASE_SYNC_POINTER_EN)); |
291427f5 JB |
2794 | } else if (HAS_PCH_CPT(dev)) { |
2795 | cpt_phase_pointer_disable(dev, pipe); | |
6f06ce18 | 2796 | } |
0fc932b8 JB |
2797 | |
2798 | /* still set train pattern 1 */ | |
2799 | reg = FDI_TX_CTL(pipe); | |
2800 | temp = I915_READ(reg); | |
2801 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2802 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2803 | I915_WRITE(reg, temp); | |
2804 | ||
2805 | reg = FDI_RX_CTL(pipe); | |
2806 | temp = I915_READ(reg); | |
2807 | if (HAS_PCH_CPT(dev)) { | |
2808 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2809 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2810 | } else { | |
2811 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2812 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2813 | } | |
2814 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
2815 | temp &= ~(0x07 << 16); | |
2816 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; | |
2817 | I915_WRITE(reg, temp); | |
2818 | ||
2819 | POSTING_READ(reg); | |
2820 | udelay(100); | |
2821 | } | |
2822 | ||
e6c3a2a6 CW |
2823 | static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
2824 | { | |
0f91128d | 2825 | struct drm_device *dev = crtc->dev; |
e6c3a2a6 CW |
2826 | |
2827 | if (crtc->fb == NULL) | |
2828 | return; | |
2829 | ||
0f91128d CW |
2830 | mutex_lock(&dev->struct_mutex); |
2831 | intel_finish_fb(crtc->fb); | |
2832 | mutex_unlock(&dev->struct_mutex); | |
e6c3a2a6 CW |
2833 | } |
2834 | ||
040484af JB |
2835 | static bool intel_crtc_driving_pch(struct drm_crtc *crtc) |
2836 | { | |
2837 | struct drm_device *dev = crtc->dev; | |
040484af JB |
2838 | struct intel_encoder *encoder; |
2839 | ||
2840 | /* | |
2841 | * If there's a non-PCH eDP on this crtc, it must be DP_A, and that | |
2842 | * must be driven by its own crtc; no sharing is possible. | |
2843 | */ | |
6c2b7c12 | 2844 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
040484af | 2845 | |
6ee8bab0 ED |
2846 | /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell |
2847 | * CPU handles all others */ | |
2848 | if (IS_HASWELL(dev)) { | |
2849 | /* It is still unclear how this will work on PPT, so throw up a warning */ | |
2850 | WARN_ON(!HAS_PCH_LPT(dev)); | |
2851 | ||
2852 | if (encoder->type == DRM_MODE_ENCODER_DAC) { | |
2853 | DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n"); | |
2854 | return true; | |
2855 | } else { | |
2856 | DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n", | |
2857 | encoder->type); | |
2858 | return false; | |
2859 | } | |
2860 | } | |
2861 | ||
040484af JB |
2862 | switch (encoder->type) { |
2863 | case INTEL_OUTPUT_EDP: | |
2864 | if (!intel_encoder_is_pch_edp(&encoder->base)) | |
2865 | return false; | |
2866 | continue; | |
2867 | } | |
2868 | } | |
2869 | ||
2870 | return true; | |
2871 | } | |
2872 | ||
e615efe4 ED |
2873 | /* Program iCLKIP clock to the desired frequency */ |
2874 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
2875 | { | |
2876 | struct drm_device *dev = crtc->dev; | |
2877 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2878 | u32 divsel, phaseinc, auxdiv, phasedir = 0; | |
2879 | u32 temp; | |
2880 | ||
2881 | /* It is necessary to ungate the pixclk gate prior to programming | |
2882 | * the divisors, and gate it back when it is done. | |
2883 | */ | |
2884 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
2885 | ||
2886 | /* Disable SSCCTL */ | |
2887 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
2888 | intel_sbi_read(dev_priv, SBI_SSCCTL6) | | |
2889 | SBI_SSCCTL_DISABLE); | |
2890 | ||
2891 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
2892 | if (crtc->mode.clock == 20000) { | |
2893 | auxdiv = 1; | |
2894 | divsel = 0x41; | |
2895 | phaseinc = 0x20; | |
2896 | } else { | |
2897 | /* The iCLK virtual clock root frequency is in MHz, | |
2898 | * but the crtc->mode.clock in in KHz. To get the divisors, | |
2899 | * it is necessary to divide one by another, so we | |
2900 | * convert the virtual clock precision to KHz here for higher | |
2901 | * precision. | |
2902 | */ | |
2903 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
2904 | u32 iclk_pi_range = 64; | |
2905 | u32 desired_divisor, msb_divisor_value, pi_value; | |
2906 | ||
2907 | desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock); | |
2908 | msb_divisor_value = desired_divisor / iclk_pi_range; | |
2909 | pi_value = desired_divisor % iclk_pi_range; | |
2910 | ||
2911 | auxdiv = 0; | |
2912 | divsel = msb_divisor_value - 2; | |
2913 | phaseinc = pi_value; | |
2914 | } | |
2915 | ||
2916 | /* This should not happen with any sane values */ | |
2917 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
2918 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
2919 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
2920 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
2921 | ||
2922 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
2923 | crtc->mode.clock, | |
2924 | auxdiv, | |
2925 | divsel, | |
2926 | phasedir, | |
2927 | phaseinc); | |
2928 | ||
2929 | /* Program SSCDIVINTPHASE6 */ | |
2930 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6); | |
2931 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; | |
2932 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
2933 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
2934 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
2935 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
2936 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
2937 | ||
2938 | intel_sbi_write(dev_priv, | |
2939 | SBI_SSCDIVINTPHASE6, | |
2940 | temp); | |
2941 | ||
2942 | /* Program SSCAUXDIV */ | |
2943 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6); | |
2944 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); | |
2945 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
2946 | intel_sbi_write(dev_priv, | |
2947 | SBI_SSCAUXDIV6, | |
2948 | temp); | |
2949 | ||
2950 | ||
2951 | /* Enable modulator and associated divider */ | |
2952 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6); | |
2953 | temp &= ~SBI_SSCCTL_DISABLE; | |
2954 | intel_sbi_write(dev_priv, | |
2955 | SBI_SSCCTL6, | |
2956 | temp); | |
2957 | ||
2958 | /* Wait for initialization time */ | |
2959 | udelay(24); | |
2960 | ||
2961 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
2962 | } | |
2963 | ||
f67a559d JB |
2964 | /* |
2965 | * Enable PCH resources required for PCH ports: | |
2966 | * - PCH PLLs | |
2967 | * - FDI training & RX/TX | |
2968 | * - update transcoder timings | |
2969 | * - DP transcoding bits | |
2970 | * - transcoder | |
2971 | */ | |
2972 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
2973 | { |
2974 | struct drm_device *dev = crtc->dev; | |
2975 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2976 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2977 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 2978 | u32 reg, temp; |
2c07245f | 2979 | |
e7e164db CW |
2980 | assert_transcoder_disabled(dev_priv, pipe); |
2981 | ||
c98e9dcf | 2982 | /* For PCH output, training FDI link */ |
674cf967 | 2983 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 2984 | |
6f13b7b5 CW |
2985 | intel_enable_pch_pll(intel_crtc); |
2986 | ||
e615efe4 ED |
2987 | if (HAS_PCH_LPT(dev)) { |
2988 | DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n"); | |
2989 | lpt_program_iclkip(crtc); | |
2990 | } else if (HAS_PCH_CPT(dev)) { | |
ee7b9f93 | 2991 | u32 sel; |
4b645f14 | 2992 | |
c98e9dcf | 2993 | temp = I915_READ(PCH_DPLL_SEL); |
ee7b9f93 JB |
2994 | switch (pipe) { |
2995 | default: | |
2996 | case 0: | |
2997 | temp |= TRANSA_DPLL_ENABLE; | |
2998 | sel = TRANSA_DPLLB_SEL; | |
2999 | break; | |
3000 | case 1: | |
3001 | temp |= TRANSB_DPLL_ENABLE; | |
3002 | sel = TRANSB_DPLLB_SEL; | |
3003 | break; | |
3004 | case 2: | |
3005 | temp |= TRANSC_DPLL_ENABLE; | |
3006 | sel = TRANSC_DPLLB_SEL; | |
3007 | break; | |
d64311ab | 3008 | } |
ee7b9f93 JB |
3009 | if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B) |
3010 | temp |= sel; | |
3011 | else | |
3012 | temp &= ~sel; | |
c98e9dcf | 3013 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 3014 | } |
5eddb70b | 3015 | |
d9b6cb56 JB |
3016 | /* set transcoder timing, panel must allow it */ |
3017 | assert_panel_unlocked(dev_priv, pipe); | |
5eddb70b CW |
3018 | I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe))); |
3019 | I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe))); | |
3020 | I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe))); | |
8db9d77b | 3021 | |
5eddb70b CW |
3022 | I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe))); |
3023 | I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe))); | |
3024 | I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe))); | |
0529a0d9 | 3025 | I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe))); |
8db9d77b | 3026 | |
f57e1e3a ED |
3027 | if (!IS_HASWELL(dev)) |
3028 | intel_fdi_normal_train(crtc); | |
5e84e1a4 | 3029 | |
c98e9dcf JB |
3030 | /* For PCH DP, enable TRANS_DP_CTL */ |
3031 | if (HAS_PCH_CPT(dev) && | |
417e822d KP |
3032 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
3033 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
9325c9f0 | 3034 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5; |
5eddb70b CW |
3035 | reg = TRANS_DP_CTL(pipe); |
3036 | temp = I915_READ(reg); | |
3037 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
3038 | TRANS_DP_SYNC_MASK | |
3039 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
3040 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
3041 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 3042 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
3043 | |
3044 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 3045 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 3046 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 3047 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
3048 | |
3049 | switch (intel_trans_dp_port_sel(crtc)) { | |
3050 | case PCH_DP_B: | |
5eddb70b | 3051 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
3052 | break; |
3053 | case PCH_DP_C: | |
5eddb70b | 3054 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
3055 | break; |
3056 | case PCH_DP_D: | |
5eddb70b | 3057 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
3058 | break; |
3059 | default: | |
3060 | DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n"); | |
5eddb70b | 3061 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 3062 | break; |
32f9d658 | 3063 | } |
2c07245f | 3064 | |
5eddb70b | 3065 | I915_WRITE(reg, temp); |
6be4a607 | 3066 | } |
b52eb4dc | 3067 | |
040484af | 3068 | intel_enable_transcoder(dev_priv, pipe); |
f67a559d JB |
3069 | } |
3070 | ||
ee7b9f93 JB |
3071 | static void intel_put_pch_pll(struct intel_crtc *intel_crtc) |
3072 | { | |
3073 | struct intel_pch_pll *pll = intel_crtc->pch_pll; | |
3074 | ||
3075 | if (pll == NULL) | |
3076 | return; | |
3077 | ||
3078 | if (pll->refcount == 0) { | |
3079 | WARN(1, "bad PCH PLL refcount\n"); | |
3080 | return; | |
3081 | } | |
3082 | ||
3083 | --pll->refcount; | |
3084 | intel_crtc->pch_pll = NULL; | |
3085 | } | |
3086 | ||
3087 | static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp) | |
3088 | { | |
3089 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; | |
3090 | struct intel_pch_pll *pll; | |
3091 | int i; | |
3092 | ||
3093 | pll = intel_crtc->pch_pll; | |
3094 | if (pll) { | |
3095 | DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n", | |
3096 | intel_crtc->base.base.id, pll->pll_reg); | |
3097 | goto prepare; | |
3098 | } | |
3099 | ||
98b6bd99 DV |
3100 | if (HAS_PCH_IBX(dev_priv->dev)) { |
3101 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
3102 | i = intel_crtc->pipe; | |
3103 | pll = &dev_priv->pch_plls[i]; | |
3104 | ||
3105 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n", | |
3106 | intel_crtc->base.base.id, pll->pll_reg); | |
3107 | ||
3108 | goto found; | |
3109 | } | |
3110 | ||
ee7b9f93 JB |
3111 | for (i = 0; i < dev_priv->num_pch_pll; i++) { |
3112 | pll = &dev_priv->pch_plls[i]; | |
3113 | ||
3114 | /* Only want to check enabled timings first */ | |
3115 | if (pll->refcount == 0) | |
3116 | continue; | |
3117 | ||
3118 | if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) && | |
3119 | fp == I915_READ(pll->fp0_reg)) { | |
3120 | DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n", | |
3121 | intel_crtc->base.base.id, | |
3122 | pll->pll_reg, pll->refcount, pll->active); | |
3123 | ||
3124 | goto found; | |
3125 | } | |
3126 | } | |
3127 | ||
3128 | /* Ok no matching timings, maybe there's a free one? */ | |
3129 | for (i = 0; i < dev_priv->num_pch_pll; i++) { | |
3130 | pll = &dev_priv->pch_plls[i]; | |
3131 | if (pll->refcount == 0) { | |
3132 | DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n", | |
3133 | intel_crtc->base.base.id, pll->pll_reg); | |
3134 | goto found; | |
3135 | } | |
3136 | } | |
3137 | ||
3138 | return NULL; | |
3139 | ||
3140 | found: | |
3141 | intel_crtc->pch_pll = pll; | |
3142 | pll->refcount++; | |
3143 | DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe); | |
3144 | prepare: /* separate function? */ | |
3145 | DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg); | |
ee7b9f93 | 3146 | |
e04c7350 CW |
3147 | /* Wait for the clocks to stabilize before rewriting the regs */ |
3148 | I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE); | |
ee7b9f93 JB |
3149 | POSTING_READ(pll->pll_reg); |
3150 | udelay(150); | |
e04c7350 CW |
3151 | |
3152 | I915_WRITE(pll->fp0_reg, fp); | |
3153 | I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE); | |
ee7b9f93 JB |
3154 | pll->on = false; |
3155 | return pll; | |
3156 | } | |
3157 | ||
d4270e57 JB |
3158 | void intel_cpt_verify_modeset(struct drm_device *dev, int pipe) |
3159 | { | |
3160 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3161 | int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe); | |
3162 | u32 temp; | |
3163 | ||
3164 | temp = I915_READ(dslreg); | |
3165 | udelay(500); | |
3166 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
3167 | /* Without this, mode sets may fail silently on FDI */ | |
3168 | I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS); | |
3169 | udelay(250); | |
3170 | I915_WRITE(tc2reg, 0); | |
3171 | if (wait_for(I915_READ(dslreg) != temp, 5)) | |
3172 | DRM_ERROR("mode set failed: pipe %d stuck\n", pipe); | |
3173 | } | |
3174 | } | |
3175 | ||
f67a559d JB |
3176 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
3177 | { | |
3178 | struct drm_device *dev = crtc->dev; | |
3179 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3180 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3181 | int pipe = intel_crtc->pipe; | |
3182 | int plane = intel_crtc->plane; | |
3183 | u32 temp; | |
3184 | bool is_pch_port; | |
3185 | ||
3186 | if (intel_crtc->active) | |
3187 | return; | |
3188 | ||
3189 | intel_crtc->active = true; | |
3190 | intel_update_watermarks(dev); | |
3191 | ||
3192 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
3193 | temp = I915_READ(PCH_LVDS); | |
3194 | if ((temp & LVDS_PORT_EN) == 0) | |
3195 | I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN); | |
3196 | } | |
3197 | ||
3198 | is_pch_port = intel_crtc_driving_pch(crtc); | |
3199 | ||
3200 | if (is_pch_port) | |
357555c0 | 3201 | ironlake_fdi_pll_enable(crtc); |
f67a559d JB |
3202 | else |
3203 | ironlake_fdi_disable(crtc); | |
3204 | ||
3205 | /* Enable panel fitting for LVDS */ | |
3206 | if (dev_priv->pch_pf_size && | |
3207 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) { | |
3208 | /* Force use of hard-coded filter coefficients | |
3209 | * as some pre-programmed values are broken, | |
3210 | * e.g. x201. | |
3211 | */ | |
9db4a9c7 JB |
3212 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); |
3213 | I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos); | |
3214 | I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size); | |
f67a559d JB |
3215 | } |
3216 | ||
9c54c0dd JB |
3217 | /* |
3218 | * On ILK+ LUT must be loaded before the pipe is running but with | |
3219 | * clocks enabled | |
3220 | */ | |
3221 | intel_crtc_load_lut(crtc); | |
3222 | ||
f67a559d JB |
3223 | intel_enable_pipe(dev_priv, pipe, is_pch_port); |
3224 | intel_enable_plane(dev_priv, plane, pipe); | |
3225 | ||
3226 | if (is_pch_port) | |
3227 | ironlake_pch_enable(crtc); | |
c98e9dcf | 3228 | |
d1ebd816 | 3229 | mutex_lock(&dev->struct_mutex); |
bed4a673 | 3230 | intel_update_fbc(dev); |
d1ebd816 BW |
3231 | mutex_unlock(&dev->struct_mutex); |
3232 | ||
6b383a7f | 3233 | intel_crtc_update_cursor(crtc, true); |
6be4a607 JB |
3234 | } |
3235 | ||
3236 | static void ironlake_crtc_disable(struct drm_crtc *crtc) | |
3237 | { | |
3238 | struct drm_device *dev = crtc->dev; | |
3239 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3240 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3241 | int pipe = intel_crtc->pipe; | |
3242 | int plane = intel_crtc->plane; | |
5eddb70b | 3243 | u32 reg, temp; |
b52eb4dc | 3244 | |
f7abfe8b CW |
3245 | if (!intel_crtc->active) |
3246 | return; | |
3247 | ||
e6c3a2a6 | 3248 | intel_crtc_wait_for_pending_flips(crtc); |
6be4a607 | 3249 | drm_vblank_off(dev, pipe); |
6b383a7f | 3250 | intel_crtc_update_cursor(crtc, false); |
5eddb70b | 3251 | |
b24e7179 | 3252 | intel_disable_plane(dev_priv, plane, pipe); |
913d8d11 | 3253 | |
973d04f9 CW |
3254 | if (dev_priv->cfb_plane == plane) |
3255 | intel_disable_fbc(dev); | |
2c07245f | 3256 | |
b24e7179 | 3257 | intel_disable_pipe(dev_priv, pipe); |
32f9d658 | 3258 | |
6be4a607 | 3259 | /* Disable PF */ |
9db4a9c7 JB |
3260 | I915_WRITE(PF_CTL(pipe), 0); |
3261 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
2c07245f | 3262 | |
0fc932b8 | 3263 | ironlake_fdi_disable(crtc); |
2c07245f | 3264 | |
47a05eca JB |
3265 | /* This is a horrible layering violation; we should be doing this in |
3266 | * the connector/encoder ->prepare instead, but we don't always have | |
3267 | * enough information there about the config to know whether it will | |
3268 | * actually be necessary or just cause undesired flicker. | |
3269 | */ | |
3270 | intel_disable_pch_ports(dev_priv, pipe); | |
249c0e64 | 3271 | |
040484af | 3272 | intel_disable_transcoder(dev_priv, pipe); |
913d8d11 | 3273 | |
6be4a607 JB |
3274 | if (HAS_PCH_CPT(dev)) { |
3275 | /* disable TRANS_DP_CTL */ | |
5eddb70b CW |
3276 | reg = TRANS_DP_CTL(pipe); |
3277 | temp = I915_READ(reg); | |
3278 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK); | |
cb3543c6 | 3279 | temp |= TRANS_DP_PORT_SEL_NONE; |
5eddb70b | 3280 | I915_WRITE(reg, temp); |
6be4a607 JB |
3281 | |
3282 | /* disable DPLL_SEL */ | |
3283 | temp = I915_READ(PCH_DPLL_SEL); | |
9db4a9c7 JB |
3284 | switch (pipe) { |
3285 | case 0: | |
d64311ab | 3286 | temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL); |
9db4a9c7 JB |
3287 | break; |
3288 | case 1: | |
6be4a607 | 3289 | temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); |
9db4a9c7 JB |
3290 | break; |
3291 | case 2: | |
4b645f14 | 3292 | /* C shares PLL A or B */ |
d64311ab | 3293 | temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL); |
9db4a9c7 JB |
3294 | break; |
3295 | default: | |
3296 | BUG(); /* wtf */ | |
3297 | } | |
6be4a607 | 3298 | I915_WRITE(PCH_DPLL_SEL, temp); |
6be4a607 | 3299 | } |
e3421a18 | 3300 | |
6be4a607 | 3301 | /* disable PCH DPLL */ |
ee7b9f93 | 3302 | intel_disable_pch_pll(intel_crtc); |
8db9d77b | 3303 | |
6be4a607 | 3304 | /* Switch from PCDclk to Rawclk */ |
5eddb70b CW |
3305 | reg = FDI_RX_CTL(pipe); |
3306 | temp = I915_READ(reg); | |
3307 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
8db9d77b | 3308 | |
6be4a607 | 3309 | /* Disable CPU FDI TX PLL */ |
5eddb70b CW |
3310 | reg = FDI_TX_CTL(pipe); |
3311 | temp = I915_READ(reg); | |
3312 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3313 | ||
3314 | POSTING_READ(reg); | |
6be4a607 | 3315 | udelay(100); |
8db9d77b | 3316 | |
5eddb70b CW |
3317 | reg = FDI_RX_CTL(pipe); |
3318 | temp = I915_READ(reg); | |
3319 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
2c07245f | 3320 | |
6be4a607 | 3321 | /* Wait for the clocks to turn off. */ |
5eddb70b | 3322 | POSTING_READ(reg); |
6be4a607 | 3323 | udelay(100); |
6b383a7f | 3324 | |
f7abfe8b | 3325 | intel_crtc->active = false; |
6b383a7f | 3326 | intel_update_watermarks(dev); |
d1ebd816 BW |
3327 | |
3328 | mutex_lock(&dev->struct_mutex); | |
6b383a7f | 3329 | intel_update_fbc(dev); |
d1ebd816 | 3330 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 3331 | } |
1b3c7a47 | 3332 | |
6be4a607 JB |
3333 | static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode) |
3334 | { | |
3335 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3336 | int pipe = intel_crtc->pipe; | |
3337 | int plane = intel_crtc->plane; | |
8db9d77b | 3338 | |
6be4a607 JB |
3339 | /* XXX: When our outputs are all unaware of DPMS modes other than off |
3340 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. | |
3341 | */ | |
3342 | switch (mode) { | |
3343 | case DRM_MODE_DPMS_ON: | |
3344 | case DRM_MODE_DPMS_STANDBY: | |
3345 | case DRM_MODE_DPMS_SUSPEND: | |
3346 | DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane); | |
3347 | ironlake_crtc_enable(crtc); | |
3348 | break; | |
1b3c7a47 | 3349 | |
6be4a607 JB |
3350 | case DRM_MODE_DPMS_OFF: |
3351 | DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane); | |
3352 | ironlake_crtc_disable(crtc); | |
2c07245f ZW |
3353 | break; |
3354 | } | |
3355 | } | |
3356 | ||
ee7b9f93 JB |
3357 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
3358 | { | |
3359 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3360 | intel_put_pch_pll(intel_crtc); | |
3361 | } | |
3362 | ||
02e792fb DV |
3363 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
3364 | { | |
02e792fb | 3365 | if (!enable && intel_crtc->overlay) { |
23f09ce3 | 3366 | struct drm_device *dev = intel_crtc->base.dev; |
ce453d81 | 3367 | struct drm_i915_private *dev_priv = dev->dev_private; |
03f77ea5 | 3368 | |
23f09ce3 | 3369 | mutex_lock(&dev->struct_mutex); |
ce453d81 CW |
3370 | dev_priv->mm.interruptible = false; |
3371 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
3372 | dev_priv->mm.interruptible = true; | |
23f09ce3 | 3373 | mutex_unlock(&dev->struct_mutex); |
02e792fb | 3374 | } |
02e792fb | 3375 | |
5dcdbcb0 CW |
3376 | /* Let userspace switch the overlay on again. In most cases userspace |
3377 | * has to recompute where to put it anyway. | |
3378 | */ | |
02e792fb DV |
3379 | } |
3380 | ||
0b8765c6 | 3381 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
3382 | { |
3383 | struct drm_device *dev = crtc->dev; | |
79e53945 JB |
3384 | struct drm_i915_private *dev_priv = dev->dev_private; |
3385 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3386 | int pipe = intel_crtc->pipe; | |
80824003 | 3387 | int plane = intel_crtc->plane; |
79e53945 | 3388 | |
f7abfe8b CW |
3389 | if (intel_crtc->active) |
3390 | return; | |
3391 | ||
3392 | intel_crtc->active = true; | |
6b383a7f CW |
3393 | intel_update_watermarks(dev); |
3394 | ||
63d7bbe9 | 3395 | intel_enable_pll(dev_priv, pipe); |
040484af | 3396 | intel_enable_pipe(dev_priv, pipe, false); |
b24e7179 | 3397 | intel_enable_plane(dev_priv, plane, pipe); |
79e53945 | 3398 | |
0b8765c6 | 3399 | intel_crtc_load_lut(crtc); |
bed4a673 | 3400 | intel_update_fbc(dev); |
79e53945 | 3401 | |
0b8765c6 JB |
3402 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
3403 | intel_crtc_dpms_overlay(intel_crtc, true); | |
6b383a7f | 3404 | intel_crtc_update_cursor(crtc, true); |
0b8765c6 | 3405 | } |
79e53945 | 3406 | |
0b8765c6 JB |
3407 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
3408 | { | |
3409 | struct drm_device *dev = crtc->dev; | |
3410 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3411 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3412 | int pipe = intel_crtc->pipe; | |
3413 | int plane = intel_crtc->plane; | |
b690e96c | 3414 | |
f7abfe8b CW |
3415 | if (!intel_crtc->active) |
3416 | return; | |
3417 | ||
0b8765c6 | 3418 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
e6c3a2a6 CW |
3419 | intel_crtc_wait_for_pending_flips(crtc); |
3420 | drm_vblank_off(dev, pipe); | |
0b8765c6 | 3421 | intel_crtc_dpms_overlay(intel_crtc, false); |
6b383a7f | 3422 | intel_crtc_update_cursor(crtc, false); |
0b8765c6 | 3423 | |
973d04f9 CW |
3424 | if (dev_priv->cfb_plane == plane) |
3425 | intel_disable_fbc(dev); | |
79e53945 | 3426 | |
b24e7179 | 3427 | intel_disable_plane(dev_priv, plane, pipe); |
b24e7179 | 3428 | intel_disable_pipe(dev_priv, pipe); |
63d7bbe9 | 3429 | intel_disable_pll(dev_priv, pipe); |
0b8765c6 | 3430 | |
f7abfe8b | 3431 | intel_crtc->active = false; |
6b383a7f CW |
3432 | intel_update_fbc(dev); |
3433 | intel_update_watermarks(dev); | |
0b8765c6 JB |
3434 | } |
3435 | ||
3436 | static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode) | |
3437 | { | |
3438 | /* XXX: When our outputs are all unaware of DPMS modes other than off | |
3439 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. | |
3440 | */ | |
3441 | switch (mode) { | |
3442 | case DRM_MODE_DPMS_ON: | |
3443 | case DRM_MODE_DPMS_STANDBY: | |
3444 | case DRM_MODE_DPMS_SUSPEND: | |
3445 | i9xx_crtc_enable(crtc); | |
3446 | break; | |
3447 | case DRM_MODE_DPMS_OFF: | |
3448 | i9xx_crtc_disable(crtc); | |
79e53945 JB |
3449 | break; |
3450 | } | |
2c07245f ZW |
3451 | } |
3452 | ||
ee7b9f93 JB |
3453 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
3454 | { | |
3455 | } | |
3456 | ||
2c07245f ZW |
3457 | /** |
3458 | * Sets the power management mode of the pipe and plane. | |
2c07245f ZW |
3459 | */ |
3460 | static void intel_crtc_dpms(struct drm_crtc *crtc, int mode) | |
3461 | { | |
3462 | struct drm_device *dev = crtc->dev; | |
e70236a8 | 3463 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f ZW |
3464 | struct drm_i915_master_private *master_priv; |
3465 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3466 | int pipe = intel_crtc->pipe; | |
3467 | bool enabled; | |
3468 | ||
032d2a0d CW |
3469 | if (intel_crtc->dpms_mode == mode) |
3470 | return; | |
3471 | ||
65655d4a | 3472 | intel_crtc->dpms_mode = mode; |
debcaddc | 3473 | |
e70236a8 | 3474 | dev_priv->display.dpms(crtc, mode); |
79e53945 JB |
3475 | |
3476 | if (!dev->primary->master) | |
3477 | return; | |
3478 | ||
3479 | master_priv = dev->primary->master->driver_priv; | |
3480 | if (!master_priv->sarea_priv) | |
3481 | return; | |
3482 | ||
3483 | enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF; | |
3484 | ||
3485 | switch (pipe) { | |
3486 | case 0: | |
3487 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; | |
3488 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; | |
3489 | break; | |
3490 | case 1: | |
3491 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; | |
3492 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; | |
3493 | break; | |
3494 | default: | |
9db4a9c7 | 3495 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
79e53945 JB |
3496 | break; |
3497 | } | |
79e53945 JB |
3498 | } |
3499 | ||
cdd59983 CW |
3500 | static void intel_crtc_disable(struct drm_crtc *crtc) |
3501 | { | |
3502 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
3503 | struct drm_device *dev = crtc->dev; | |
ee7b9f93 | 3504 | struct drm_i915_private *dev_priv = dev->dev_private; |
cdd59983 CW |
3505 | |
3506 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); | |
ee7b9f93 JB |
3507 | dev_priv->display.off(crtc); |
3508 | ||
931872fc CW |
3509 | assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); |
3510 | assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); | |
cdd59983 CW |
3511 | |
3512 | if (crtc->fb) { | |
3513 | mutex_lock(&dev->struct_mutex); | |
1690e1eb | 3514 | intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); |
cdd59983 CW |
3515 | mutex_unlock(&dev->struct_mutex); |
3516 | } | |
3517 | } | |
3518 | ||
7e7d76c3 JB |
3519 | /* Prepare for a mode set. |
3520 | * | |
3521 | * Note we could be a lot smarter here. We need to figure out which outputs | |
3522 | * will be enabled, which disabled (in short, how the config will changes) | |
3523 | * and perform the minimum necessary steps to accomplish that, e.g. updating | |
3524 | * watermarks, FBC configuration, making sure PLLs are programmed correctly, | |
3525 | * panel fitting is in the proper state, etc. | |
3526 | */ | |
3527 | static void i9xx_crtc_prepare(struct drm_crtc *crtc) | |
79e53945 | 3528 | { |
7e7d76c3 | 3529 | i9xx_crtc_disable(crtc); |
79e53945 JB |
3530 | } |
3531 | ||
7e7d76c3 | 3532 | static void i9xx_crtc_commit(struct drm_crtc *crtc) |
79e53945 | 3533 | { |
7e7d76c3 | 3534 | i9xx_crtc_enable(crtc); |
7e7d76c3 JB |
3535 | } |
3536 | ||
3537 | static void ironlake_crtc_prepare(struct drm_crtc *crtc) | |
3538 | { | |
7e7d76c3 | 3539 | ironlake_crtc_disable(crtc); |
7e7d76c3 JB |
3540 | } |
3541 | ||
3542 | static void ironlake_crtc_commit(struct drm_crtc *crtc) | |
3543 | { | |
7e7d76c3 | 3544 | ironlake_crtc_enable(crtc); |
79e53945 JB |
3545 | } |
3546 | ||
0206e353 | 3547 | void intel_encoder_prepare(struct drm_encoder *encoder) |
79e53945 JB |
3548 | { |
3549 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
3550 | /* lvds has its own version of prepare see intel_lvds_prepare */ | |
3551 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); | |
3552 | } | |
3553 | ||
0206e353 | 3554 | void intel_encoder_commit(struct drm_encoder *encoder) |
79e53945 JB |
3555 | { |
3556 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
d4270e57 | 3557 | struct drm_device *dev = encoder->dev; |
d47d7cb8 | 3558 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
d4270e57 | 3559 | |
79e53945 JB |
3560 | /* lvds has its own version of commit see intel_lvds_commit */ |
3561 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); | |
d4270e57 JB |
3562 | |
3563 | if (HAS_PCH_CPT(dev)) | |
3564 | intel_cpt_verify_modeset(dev, intel_crtc->pipe); | |
79e53945 JB |
3565 | } |
3566 | ||
ea5b213a CW |
3567 | void intel_encoder_destroy(struct drm_encoder *encoder) |
3568 | { | |
4ef69c7a | 3569 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 3570 | |
ea5b213a CW |
3571 | drm_encoder_cleanup(encoder); |
3572 | kfree(intel_encoder); | |
3573 | } | |
3574 | ||
79e53945 | 3575 | static bool intel_crtc_mode_fixup(struct drm_crtc *crtc, |
35313cde | 3576 | const struct drm_display_mode *mode, |
79e53945 JB |
3577 | struct drm_display_mode *adjusted_mode) |
3578 | { | |
2c07245f | 3579 | struct drm_device *dev = crtc->dev; |
89749350 | 3580 | |
bad720ff | 3581 | if (HAS_PCH_SPLIT(dev)) { |
2c07245f | 3582 | /* FDI link clock is fixed at 2.7G */ |
2377b741 JB |
3583 | if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4) |
3584 | return false; | |
2c07245f | 3585 | } |
89749350 | 3586 | |
f9bef081 DV |
3587 | /* All interlaced capable intel hw wants timings in frames. Note though |
3588 | * that intel_lvds_mode_fixup does some funny tricks with the crtc | |
3589 | * timings, so we need to be careful not to clobber these.*/ | |
3590 | if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET)) | |
3591 | drm_mode_set_crtcinfo(adjusted_mode, 0); | |
89749350 | 3592 | |
79e53945 JB |
3593 | return true; |
3594 | } | |
3595 | ||
25eb05fc JB |
3596 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
3597 | { | |
3598 | return 400000; /* FIXME */ | |
3599 | } | |
3600 | ||
e70236a8 JB |
3601 | static int i945_get_display_clock_speed(struct drm_device *dev) |
3602 | { | |
3603 | return 400000; | |
3604 | } | |
79e53945 | 3605 | |
e70236a8 | 3606 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 3607 | { |
e70236a8 JB |
3608 | return 333000; |
3609 | } | |
79e53945 | 3610 | |
e70236a8 JB |
3611 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
3612 | { | |
3613 | return 200000; | |
3614 | } | |
79e53945 | 3615 | |
e70236a8 JB |
3616 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
3617 | { | |
3618 | u16 gcfgc = 0; | |
79e53945 | 3619 | |
e70236a8 JB |
3620 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
3621 | ||
3622 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
3623 | return 133000; | |
3624 | else { | |
3625 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
3626 | case GC_DISPLAY_CLOCK_333_MHZ: | |
3627 | return 333000; | |
3628 | default: | |
3629 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
3630 | return 190000; | |
79e53945 | 3631 | } |
e70236a8 JB |
3632 | } |
3633 | } | |
3634 | ||
3635 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
3636 | { | |
3637 | return 266000; | |
3638 | } | |
3639 | ||
3640 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
3641 | { | |
3642 | u16 hpllcc = 0; | |
3643 | /* Assume that the hardware is in the high speed state. This | |
3644 | * should be the default. | |
3645 | */ | |
3646 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
3647 | case GC_CLOCK_133_200: | |
3648 | case GC_CLOCK_100_200: | |
3649 | return 200000; | |
3650 | case GC_CLOCK_166_250: | |
3651 | return 250000; | |
3652 | case GC_CLOCK_100_133: | |
79e53945 | 3653 | return 133000; |
e70236a8 | 3654 | } |
79e53945 | 3655 | |
e70236a8 JB |
3656 | /* Shouldn't happen */ |
3657 | return 0; | |
3658 | } | |
79e53945 | 3659 | |
e70236a8 JB |
3660 | static int i830_get_display_clock_speed(struct drm_device *dev) |
3661 | { | |
3662 | return 133000; | |
79e53945 JB |
3663 | } |
3664 | ||
2c07245f ZW |
3665 | struct fdi_m_n { |
3666 | u32 tu; | |
3667 | u32 gmch_m; | |
3668 | u32 gmch_n; | |
3669 | u32 link_m; | |
3670 | u32 link_n; | |
3671 | }; | |
3672 | ||
3673 | static void | |
3674 | fdi_reduce_ratio(u32 *num, u32 *den) | |
3675 | { | |
3676 | while (*num > 0xffffff || *den > 0xffffff) { | |
3677 | *num >>= 1; | |
3678 | *den >>= 1; | |
3679 | } | |
3680 | } | |
3681 | ||
2c07245f | 3682 | static void |
f2b115e6 AJ |
3683 | ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock, |
3684 | int link_clock, struct fdi_m_n *m_n) | |
2c07245f | 3685 | { |
2c07245f ZW |
3686 | m_n->tu = 64; /* default size */ |
3687 | ||
22ed1113 CW |
3688 | /* BUG_ON(pixel_clock > INT_MAX / 36); */ |
3689 | m_n->gmch_m = bits_per_pixel * pixel_clock; | |
3690 | m_n->gmch_n = link_clock * nlanes * 8; | |
2c07245f ZW |
3691 | fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); |
3692 | ||
22ed1113 CW |
3693 | m_n->link_m = pixel_clock; |
3694 | m_n->link_n = link_clock; | |
2c07245f ZW |
3695 | fdi_reduce_ratio(&m_n->link_m, &m_n->link_n); |
3696 | } | |
3697 | ||
a7615030 CW |
3698 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
3699 | { | |
72bbe58c KP |
3700 | if (i915_panel_use_ssc >= 0) |
3701 | return i915_panel_use_ssc != 0; | |
3702 | return dev_priv->lvds_use_ssc | |
435793df | 3703 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
3704 | } |
3705 | ||
5a354204 JB |
3706 | /** |
3707 | * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send | |
3708 | * @crtc: CRTC structure | |
3b5c78a3 | 3709 | * @mode: requested mode |
5a354204 JB |
3710 | * |
3711 | * A pipe may be connected to one or more outputs. Based on the depth of the | |
3712 | * attached framebuffer, choose a good color depth to use on the pipe. | |
3713 | * | |
3714 | * If possible, match the pipe depth to the fb depth. In some cases, this | |
3715 | * isn't ideal, because the connected output supports a lesser or restricted | |
3716 | * set of depths. Resolve that here: | |
3717 | * LVDS typically supports only 6bpc, so clamp down in that case | |
3718 | * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc | |
3719 | * Displays may support a restricted set as well, check EDID and clamp as | |
3720 | * appropriate. | |
3b5c78a3 | 3721 | * DP may want to dither down to 6bpc to fit larger modes |
5a354204 JB |
3722 | * |
3723 | * RETURNS: | |
3724 | * Dithering requirement (i.e. false if display bpc and pipe bpc match, | |
3725 | * true if they don't match). | |
3726 | */ | |
3727 | static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc, | |
3b5c78a3 AJ |
3728 | unsigned int *pipe_bpp, |
3729 | struct drm_display_mode *mode) | |
5a354204 JB |
3730 | { |
3731 | struct drm_device *dev = crtc->dev; | |
3732 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5a354204 | 3733 | struct drm_connector *connector; |
6c2b7c12 | 3734 | struct intel_encoder *intel_encoder; |
5a354204 JB |
3735 | unsigned int display_bpc = UINT_MAX, bpc; |
3736 | ||
3737 | /* Walk the encoders & connectors on this crtc, get min bpc */ | |
6c2b7c12 | 3738 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
5a354204 JB |
3739 | |
3740 | if (intel_encoder->type == INTEL_OUTPUT_LVDS) { | |
3741 | unsigned int lvds_bpc; | |
3742 | ||
3743 | if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == | |
3744 | LVDS_A3_POWER_UP) | |
3745 | lvds_bpc = 8; | |
3746 | else | |
3747 | lvds_bpc = 6; | |
3748 | ||
3749 | if (lvds_bpc < display_bpc) { | |
82820490 | 3750 | DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc); |
5a354204 JB |
3751 | display_bpc = lvds_bpc; |
3752 | } | |
3753 | continue; | |
3754 | } | |
3755 | ||
3756 | if (intel_encoder->type == INTEL_OUTPUT_EDP) { | |
3757 | /* Use VBT settings if we have an eDP panel */ | |
3758 | unsigned int edp_bpc = dev_priv->edp.bpp / 3; | |
3759 | ||
3760 | if (edp_bpc < display_bpc) { | |
82820490 | 3761 | DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc); |
5a354204 JB |
3762 | display_bpc = edp_bpc; |
3763 | } | |
3764 | continue; | |
3765 | } | |
3766 | ||
3767 | /* Not one of the known troublemakers, check the EDID */ | |
3768 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
3769 | head) { | |
6c2b7c12 | 3770 | if (connector->encoder != &intel_encoder->base) |
5a354204 JB |
3771 | continue; |
3772 | ||
62ac41a6 JB |
3773 | /* Don't use an invalid EDID bpc value */ |
3774 | if (connector->display_info.bpc && | |
3775 | connector->display_info.bpc < display_bpc) { | |
82820490 | 3776 | DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc); |
5a354204 JB |
3777 | display_bpc = connector->display_info.bpc; |
3778 | } | |
3779 | } | |
3780 | ||
3781 | /* | |
3782 | * HDMI is either 12 or 8, so if the display lets 10bpc sneak | |
3783 | * through, clamp it down. (Note: >12bpc will be caught below.) | |
3784 | */ | |
3785 | if (intel_encoder->type == INTEL_OUTPUT_HDMI) { | |
3786 | if (display_bpc > 8 && display_bpc < 12) { | |
82820490 | 3787 | DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n"); |
5a354204 JB |
3788 | display_bpc = 12; |
3789 | } else { | |
82820490 | 3790 | DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n"); |
5a354204 JB |
3791 | display_bpc = 8; |
3792 | } | |
3793 | } | |
3794 | } | |
3795 | ||
3b5c78a3 AJ |
3796 | if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) { |
3797 | DRM_DEBUG_KMS("Dithering DP to 6bpc\n"); | |
3798 | display_bpc = 6; | |
3799 | } | |
3800 | ||
5a354204 JB |
3801 | /* |
3802 | * We could just drive the pipe at the highest bpc all the time and | |
3803 | * enable dithering as needed, but that costs bandwidth. So choose | |
3804 | * the minimum value that expresses the full color range of the fb but | |
3805 | * also stays within the max display bpc discovered above. | |
3806 | */ | |
3807 | ||
3808 | switch (crtc->fb->depth) { | |
3809 | case 8: | |
3810 | bpc = 8; /* since we go through a colormap */ | |
3811 | break; | |
3812 | case 15: | |
3813 | case 16: | |
3814 | bpc = 6; /* min is 18bpp */ | |
3815 | break; | |
3816 | case 24: | |
578393cd | 3817 | bpc = 8; |
5a354204 JB |
3818 | break; |
3819 | case 30: | |
578393cd | 3820 | bpc = 10; |
5a354204 JB |
3821 | break; |
3822 | case 48: | |
578393cd | 3823 | bpc = 12; |
5a354204 JB |
3824 | break; |
3825 | default: | |
3826 | DRM_DEBUG("unsupported depth, assuming 24 bits\n"); | |
3827 | bpc = min((unsigned int)8, display_bpc); | |
3828 | break; | |
3829 | } | |
3830 | ||
578393cd KP |
3831 | display_bpc = min(display_bpc, bpc); |
3832 | ||
82820490 AJ |
3833 | DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n", |
3834 | bpc, display_bpc); | |
5a354204 | 3835 | |
578393cd | 3836 | *pipe_bpp = display_bpc * 3; |
5a354204 JB |
3837 | |
3838 | return display_bpc != bpc; | |
3839 | } | |
3840 | ||
a0c4da24 JB |
3841 | static int vlv_get_refclk(struct drm_crtc *crtc) |
3842 | { | |
3843 | struct drm_device *dev = crtc->dev; | |
3844 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3845 | int refclk = 27000; /* for DP & HDMI */ | |
3846 | ||
3847 | return 100000; /* only one validated so far */ | |
3848 | ||
3849 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
3850 | refclk = 96000; | |
3851 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
3852 | if (intel_panel_use_ssc(dev_priv)) | |
3853 | refclk = 100000; | |
3854 | else | |
3855 | refclk = 96000; | |
3856 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) { | |
3857 | refclk = 100000; | |
3858 | } | |
3859 | ||
3860 | return refclk; | |
3861 | } | |
3862 | ||
c65d77d8 JB |
3863 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
3864 | { | |
3865 | struct drm_device *dev = crtc->dev; | |
3866 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3867 | int refclk; | |
3868 | ||
a0c4da24 JB |
3869 | if (IS_VALLEYVIEW(dev)) { |
3870 | refclk = vlv_get_refclk(crtc); | |
3871 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && | |
c65d77d8 JB |
3872 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
3873 | refclk = dev_priv->lvds_ssc_freq * 1000; | |
3874 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", | |
3875 | refclk / 1000); | |
3876 | } else if (!IS_GEN2(dev)) { | |
3877 | refclk = 96000; | |
3878 | } else { | |
3879 | refclk = 48000; | |
3880 | } | |
3881 | ||
3882 | return refclk; | |
3883 | } | |
3884 | ||
3885 | static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode, | |
3886 | intel_clock_t *clock) | |
3887 | { | |
3888 | /* SDVO TV has fixed PLL values depend on its clock range, | |
3889 | this mirrors vbios setting. */ | |
3890 | if (adjusted_mode->clock >= 100000 | |
3891 | && adjusted_mode->clock < 140500) { | |
3892 | clock->p1 = 2; | |
3893 | clock->p2 = 10; | |
3894 | clock->n = 3; | |
3895 | clock->m1 = 16; | |
3896 | clock->m2 = 8; | |
3897 | } else if (adjusted_mode->clock >= 140500 | |
3898 | && adjusted_mode->clock <= 200000) { | |
3899 | clock->p1 = 1; | |
3900 | clock->p2 = 10; | |
3901 | clock->n = 6; | |
3902 | clock->m1 = 12; | |
3903 | clock->m2 = 8; | |
3904 | } | |
3905 | } | |
3906 | ||
a7516a05 JB |
3907 | static void i9xx_update_pll_dividers(struct drm_crtc *crtc, |
3908 | intel_clock_t *clock, | |
3909 | intel_clock_t *reduced_clock) | |
3910 | { | |
3911 | struct drm_device *dev = crtc->dev; | |
3912 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3913 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3914 | int pipe = intel_crtc->pipe; | |
3915 | u32 fp, fp2 = 0; | |
3916 | ||
3917 | if (IS_PINEVIEW(dev)) { | |
3918 | fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2; | |
3919 | if (reduced_clock) | |
3920 | fp2 = (1 << reduced_clock->n) << 16 | | |
3921 | reduced_clock->m1 << 8 | reduced_clock->m2; | |
3922 | } else { | |
3923 | fp = clock->n << 16 | clock->m1 << 8 | clock->m2; | |
3924 | if (reduced_clock) | |
3925 | fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 | | |
3926 | reduced_clock->m2; | |
3927 | } | |
3928 | ||
3929 | I915_WRITE(FP0(pipe), fp); | |
3930 | ||
3931 | intel_crtc->lowfreq_avail = false; | |
3932 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && | |
3933 | reduced_clock && i915_powersave) { | |
3934 | I915_WRITE(FP1(pipe), fp2); | |
3935 | intel_crtc->lowfreq_avail = true; | |
3936 | } else { | |
3937 | I915_WRITE(FP1(pipe), fp); | |
3938 | } | |
3939 | } | |
3940 | ||
93e537a1 DV |
3941 | static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock, |
3942 | struct drm_display_mode *adjusted_mode) | |
3943 | { | |
3944 | struct drm_device *dev = crtc->dev; | |
3945 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3946 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3947 | int pipe = intel_crtc->pipe; | |
284d5df5 | 3948 | u32 temp; |
93e537a1 DV |
3949 | |
3950 | temp = I915_READ(LVDS); | |
3951 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; | |
3952 | if (pipe == 1) { | |
3953 | temp |= LVDS_PIPEB_SELECT; | |
3954 | } else { | |
3955 | temp &= ~LVDS_PIPEB_SELECT; | |
3956 | } | |
3957 | /* set the corresponsding LVDS_BORDER bit */ | |
3958 | temp |= dev_priv->lvds_border_bits; | |
3959 | /* Set the B0-B3 data pairs corresponding to whether we're going to | |
3960 | * set the DPLLs for dual-channel mode or not. | |
3961 | */ | |
3962 | if (clock->p2 == 7) | |
3963 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; | |
3964 | else | |
3965 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); | |
3966 | ||
3967 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) | |
3968 | * appropriately here, but we need to look more thoroughly into how | |
3969 | * panels behave in the two modes. | |
3970 | */ | |
3971 | /* set the dithering flag on LVDS as needed */ | |
3972 | if (INTEL_INFO(dev)->gen >= 4) { | |
3973 | if (dev_priv->lvds_dither) | |
3974 | temp |= LVDS_ENABLE_DITHER; | |
3975 | else | |
3976 | temp &= ~LVDS_ENABLE_DITHER; | |
3977 | } | |
284d5df5 | 3978 | temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); |
93e537a1 | 3979 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
284d5df5 | 3980 | temp |= LVDS_HSYNC_POLARITY; |
93e537a1 | 3981 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) |
284d5df5 | 3982 | temp |= LVDS_VSYNC_POLARITY; |
93e537a1 DV |
3983 | I915_WRITE(LVDS, temp); |
3984 | } | |
3985 | ||
a0c4da24 JB |
3986 | static void vlv_update_pll(struct drm_crtc *crtc, |
3987 | struct drm_display_mode *mode, | |
3988 | struct drm_display_mode *adjusted_mode, | |
3989 | intel_clock_t *clock, intel_clock_t *reduced_clock, | |
3990 | int refclk, int num_connectors) | |
3991 | { | |
3992 | struct drm_device *dev = crtc->dev; | |
3993 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3994 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3995 | int pipe = intel_crtc->pipe; | |
3996 | u32 dpll, mdiv, pdiv; | |
3997 | u32 bestn, bestm1, bestm2, bestp1, bestp2; | |
3998 | bool is_hdmi; | |
3999 | ||
4000 | is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI); | |
4001 | ||
4002 | bestn = clock->n; | |
4003 | bestm1 = clock->m1; | |
4004 | bestm2 = clock->m2; | |
4005 | bestp1 = clock->p1; | |
4006 | bestp2 = clock->p2; | |
4007 | ||
4008 | /* Enable DPIO clock input */ | |
4009 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | | |
4010 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; | |
4011 | I915_WRITE(DPLL(pipe), dpll); | |
4012 | POSTING_READ(DPLL(pipe)); | |
4013 | ||
4014 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); | |
4015 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
4016 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
4017 | mdiv |= (1 << DPIO_POST_DIV_SHIFT); | |
4018 | mdiv |= (1 << DPIO_K_SHIFT); | |
4019 | mdiv |= DPIO_ENABLE_CALIBRATION; | |
4020 | intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv); | |
4021 | ||
4022 | intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000); | |
4023 | ||
4024 | pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) | | |
4025 | (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) | | |
4026 | (8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT); | |
4027 | intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv); | |
4028 | ||
4029 | intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051); | |
4030 | ||
4031 | dpll |= DPLL_VCO_ENABLE; | |
4032 | I915_WRITE(DPLL(pipe), dpll); | |
4033 | POSTING_READ(DPLL(pipe)); | |
4034 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
4035 | DRM_ERROR("DPLL %d failed to lock\n", pipe); | |
4036 | ||
4037 | if (is_hdmi) { | |
4038 | u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode); | |
4039 | ||
4040 | if (temp > 1) | |
4041 | temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
4042 | else | |
4043 | temp = 0; | |
4044 | ||
4045 | I915_WRITE(DPLL_MD(pipe), temp); | |
4046 | POSTING_READ(DPLL_MD(pipe)); | |
4047 | } | |
4048 | ||
4049 | intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */ | |
4050 | } | |
4051 | ||
eb1cbe48 DV |
4052 | static void i9xx_update_pll(struct drm_crtc *crtc, |
4053 | struct drm_display_mode *mode, | |
4054 | struct drm_display_mode *adjusted_mode, | |
4055 | intel_clock_t *clock, intel_clock_t *reduced_clock, | |
4056 | int num_connectors) | |
4057 | { | |
4058 | struct drm_device *dev = crtc->dev; | |
4059 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4060 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4061 | int pipe = intel_crtc->pipe; | |
4062 | u32 dpll; | |
4063 | bool is_sdvo; | |
4064 | ||
4065 | is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) || | |
4066 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI); | |
4067 | ||
4068 | dpll = DPLL_VGA_MODE_DIS; | |
4069 | ||
4070 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
4071 | dpll |= DPLLB_MODE_LVDS; | |
4072 | else | |
4073 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
4074 | if (is_sdvo) { | |
4075 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); | |
4076 | if (pixel_multiplier > 1) { | |
4077 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
4078 | dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; | |
4079 | } | |
4080 | dpll |= DPLL_DVO_HIGH_SPEED; | |
4081 | } | |
4082 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) | |
4083 | dpll |= DPLL_DVO_HIGH_SPEED; | |
4084 | ||
4085 | /* compute bitmask from p1 value */ | |
4086 | if (IS_PINEVIEW(dev)) | |
4087 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
4088 | else { | |
4089 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
4090 | if (IS_G4X(dev) && reduced_clock) | |
4091 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
4092 | } | |
4093 | switch (clock->p2) { | |
4094 | case 5: | |
4095 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
4096 | break; | |
4097 | case 7: | |
4098 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
4099 | break; | |
4100 | case 10: | |
4101 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
4102 | break; | |
4103 | case 14: | |
4104 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
4105 | break; | |
4106 | } | |
4107 | if (INTEL_INFO(dev)->gen >= 4) | |
4108 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
4109 | ||
4110 | if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT)) | |
4111 | dpll |= PLL_REF_INPUT_TVCLKINBC; | |
4112 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT)) | |
4113 | /* XXX: just matching BIOS for now */ | |
4114 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ | |
4115 | dpll |= 3; | |
4116 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && | |
4117 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) | |
4118 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
4119 | else | |
4120 | dpll |= PLL_REF_INPUT_DREFCLK; | |
4121 | ||
4122 | dpll |= DPLL_VCO_ENABLE; | |
4123 | I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); | |
4124 | POSTING_READ(DPLL(pipe)); | |
4125 | udelay(150); | |
4126 | ||
4127 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. | |
4128 | * This is an exception to the general rule that mode_set doesn't turn | |
4129 | * things on. | |
4130 | */ | |
4131 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
4132 | intel_update_lvds(crtc, clock, adjusted_mode); | |
4133 | ||
4134 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) | |
4135 | intel_dp_set_m_n(crtc, mode, adjusted_mode); | |
4136 | ||
4137 | I915_WRITE(DPLL(pipe), dpll); | |
4138 | ||
4139 | /* Wait for the clocks to stabilize. */ | |
4140 | POSTING_READ(DPLL(pipe)); | |
4141 | udelay(150); | |
4142 | ||
4143 | if (INTEL_INFO(dev)->gen >= 4) { | |
4144 | u32 temp = 0; | |
4145 | if (is_sdvo) { | |
4146 | temp = intel_mode_get_pixel_multiplier(adjusted_mode); | |
4147 | if (temp > 1) | |
4148 | temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
4149 | else | |
4150 | temp = 0; | |
4151 | } | |
4152 | I915_WRITE(DPLL_MD(pipe), temp); | |
4153 | } else { | |
4154 | /* The pixel multiplier can only be updated once the | |
4155 | * DPLL is enabled and the clocks are stable. | |
4156 | * | |
4157 | * So write it again. | |
4158 | */ | |
4159 | I915_WRITE(DPLL(pipe), dpll); | |
4160 | } | |
4161 | } | |
4162 | ||
4163 | static void i8xx_update_pll(struct drm_crtc *crtc, | |
4164 | struct drm_display_mode *adjusted_mode, | |
4165 | intel_clock_t *clock, | |
4166 | int num_connectors) | |
4167 | { | |
4168 | struct drm_device *dev = crtc->dev; | |
4169 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4170 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4171 | int pipe = intel_crtc->pipe; | |
4172 | u32 dpll; | |
4173 | ||
4174 | dpll = DPLL_VGA_MODE_DIS; | |
4175 | ||
4176 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
4177 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
4178 | } else { | |
4179 | if (clock->p1 == 2) | |
4180 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
4181 | else | |
4182 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
4183 | if (clock->p2 == 4) | |
4184 | dpll |= PLL_P2_DIVIDE_BY_4; | |
4185 | } | |
4186 | ||
4187 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT)) | |
4188 | /* XXX: just matching BIOS for now */ | |
4189 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ | |
4190 | dpll |= 3; | |
4191 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && | |
4192 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) | |
4193 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
4194 | else | |
4195 | dpll |= PLL_REF_INPUT_DREFCLK; | |
4196 | ||
4197 | dpll |= DPLL_VCO_ENABLE; | |
4198 | I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); | |
4199 | POSTING_READ(DPLL(pipe)); | |
4200 | udelay(150); | |
4201 | ||
4202 | I915_WRITE(DPLL(pipe), dpll); | |
4203 | ||
4204 | /* Wait for the clocks to stabilize. */ | |
4205 | POSTING_READ(DPLL(pipe)); | |
4206 | udelay(150); | |
4207 | ||
4208 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. | |
4209 | * This is an exception to the general rule that mode_set doesn't turn | |
4210 | * things on. | |
4211 | */ | |
4212 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
4213 | intel_update_lvds(crtc, clock, adjusted_mode); | |
4214 | ||
4215 | /* The pixel multiplier can only be updated once the | |
4216 | * DPLL is enabled and the clocks are stable. | |
4217 | * | |
4218 | * So write it again. | |
4219 | */ | |
4220 | I915_WRITE(DPLL(pipe), dpll); | |
4221 | } | |
4222 | ||
f564048e EA |
4223 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
4224 | struct drm_display_mode *mode, | |
4225 | struct drm_display_mode *adjusted_mode, | |
4226 | int x, int y, | |
4227 | struct drm_framebuffer *old_fb) | |
79e53945 JB |
4228 | { |
4229 | struct drm_device *dev = crtc->dev; | |
4230 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4231 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4232 | int pipe = intel_crtc->pipe; | |
80824003 | 4233 | int plane = intel_crtc->plane; |
c751ce4f | 4234 | int refclk, num_connectors = 0; |
652c393a | 4235 | intel_clock_t clock, reduced_clock; |
eb1cbe48 DV |
4236 | u32 dspcntr, pipeconf, vsyncshift; |
4237 | bool ok, has_reduced_clock = false, is_sdvo = false; | |
4238 | bool is_lvds = false, is_tv = false, is_dp = false; | |
5eddb70b | 4239 | struct intel_encoder *encoder; |
d4906093 | 4240 | const intel_limit_t *limit; |
5c3b82e2 | 4241 | int ret; |
79e53945 | 4242 | |
6c2b7c12 | 4243 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5eddb70b | 4244 | switch (encoder->type) { |
79e53945 JB |
4245 | case INTEL_OUTPUT_LVDS: |
4246 | is_lvds = true; | |
4247 | break; | |
4248 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 4249 | case INTEL_OUTPUT_HDMI: |
79e53945 | 4250 | is_sdvo = true; |
5eddb70b | 4251 | if (encoder->needs_tv_clock) |
e2f0ba97 | 4252 | is_tv = true; |
79e53945 | 4253 | break; |
79e53945 JB |
4254 | case INTEL_OUTPUT_TVOUT: |
4255 | is_tv = true; | |
4256 | break; | |
a4fc5ed6 KP |
4257 | case INTEL_OUTPUT_DISPLAYPORT: |
4258 | is_dp = true; | |
4259 | break; | |
79e53945 | 4260 | } |
43565a06 | 4261 | |
c751ce4f | 4262 | num_connectors++; |
79e53945 JB |
4263 | } |
4264 | ||
c65d77d8 | 4265 | refclk = i9xx_get_refclk(crtc, num_connectors); |
79e53945 | 4266 | |
d4906093 ML |
4267 | /* |
4268 | * Returns a set of divisors for the desired target clock with the given | |
4269 | * refclk, or FALSE. The returned values represent the clock equation: | |
4270 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
4271 | */ | |
1b894b59 | 4272 | limit = intel_limit(crtc, refclk); |
cec2f356 SP |
4273 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL, |
4274 | &clock); | |
79e53945 JB |
4275 | if (!ok) { |
4276 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
5c3b82e2 | 4277 | return -EINVAL; |
79e53945 JB |
4278 | } |
4279 | ||
cda4b7d3 | 4280 | /* Ensure that the cursor is valid for the new mode before changing... */ |
6b383a7f | 4281 | intel_crtc_update_cursor(crtc, true); |
cda4b7d3 | 4282 | |
ddc9003c | 4283 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
4284 | /* |
4285 | * Ensure we match the reduced clock's P to the target clock. | |
4286 | * If the clocks don't match, we can't switch the display clock | |
4287 | * by using the FP0/FP1. In such case we will disable the LVDS | |
4288 | * downclock feature. | |
4289 | */ | |
ddc9003c | 4290 | has_reduced_clock = limit->find_pll(limit, crtc, |
5eddb70b CW |
4291 | dev_priv->lvds_downclock, |
4292 | refclk, | |
cec2f356 | 4293 | &clock, |
5eddb70b | 4294 | &reduced_clock); |
7026d4ac ZW |
4295 | } |
4296 | ||
c65d77d8 JB |
4297 | if (is_sdvo && is_tv) |
4298 | i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock); | |
7026d4ac | 4299 | |
a7516a05 JB |
4300 | i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ? |
4301 | &reduced_clock : NULL); | |
79e53945 | 4302 | |
eb1cbe48 DV |
4303 | if (IS_GEN2(dev)) |
4304 | i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors); | |
a0c4da24 JB |
4305 | else if (IS_VALLEYVIEW(dev)) |
4306 | vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL, | |
4307 | refclk, num_connectors); | |
79e53945 | 4308 | else |
eb1cbe48 DV |
4309 | i9xx_update_pll(crtc, mode, adjusted_mode, &clock, |
4310 | has_reduced_clock ? &reduced_clock : NULL, | |
4311 | num_connectors); | |
79e53945 JB |
4312 | |
4313 | /* setup pipeconf */ | |
5eddb70b | 4314 | pipeconf = I915_READ(PIPECONF(pipe)); |
79e53945 JB |
4315 | |
4316 | /* Set up the display plane register */ | |
4317 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
4318 | ||
929c77fb EA |
4319 | if (pipe == 0) |
4320 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; | |
4321 | else | |
4322 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
79e53945 | 4323 | |
a6c45cf0 | 4324 | if (pipe == 0 && INTEL_INFO(dev)->gen < 4) { |
79e53945 JB |
4325 | /* Enable pixel doubling when the dot clock is > 90% of the (display) |
4326 | * core speed. | |
4327 | * | |
4328 | * XXX: No double-wide on 915GM pipe B. Is that the only reason for the | |
4329 | * pipe == 0 check? | |
4330 | */ | |
e70236a8 JB |
4331 | if (mode->clock > |
4332 | dev_priv->display.get_display_clock_speed(dev) * 9 / 10) | |
5eddb70b | 4333 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
79e53945 | 4334 | else |
5eddb70b | 4335 | pipeconf &= ~PIPECONF_DOUBLE_WIDE; |
79e53945 JB |
4336 | } |
4337 | ||
3b5c78a3 AJ |
4338 | /* default to 8bpc */ |
4339 | pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN); | |
4340 | if (is_dp) { | |
4341 | if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) { | |
4342 | pipeconf |= PIPECONF_BPP_6 | | |
4343 | PIPECONF_DITHER_EN | | |
4344 | PIPECONF_DITHER_TYPE_SP; | |
4345 | } | |
4346 | } | |
4347 | ||
28c97730 | 4348 | DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); |
79e53945 JB |
4349 | drm_mode_debug_printmodeline(mode); |
4350 | ||
a7516a05 JB |
4351 | if (HAS_PIPE_CXSR(dev)) { |
4352 | if (intel_crtc->lowfreq_avail) { | |
28c97730 | 4353 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); |
652c393a | 4354 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; |
a7516a05 | 4355 | } else { |
28c97730 | 4356 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); |
652c393a JB |
4357 | pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; |
4358 | } | |
4359 | } | |
4360 | ||
617cf884 | 4361 | pipeconf &= ~PIPECONF_INTERLACE_MASK; |
dbb02575 DV |
4362 | if (!IS_GEN2(dev) && |
4363 | adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { | |
734b4157 KH |
4364 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
4365 | /* the chip adds 2 halflines automatically */ | |
734b4157 | 4366 | adjusted_mode->crtc_vtotal -= 1; |
734b4157 | 4367 | adjusted_mode->crtc_vblank_end -= 1; |
0529a0d9 DV |
4368 | vsyncshift = adjusted_mode->crtc_hsync_start |
4369 | - adjusted_mode->crtc_htotal/2; | |
4370 | } else { | |
617cf884 | 4371 | pipeconf |= PIPECONF_PROGRESSIVE; |
0529a0d9 DV |
4372 | vsyncshift = 0; |
4373 | } | |
4374 | ||
4375 | if (!IS_GEN3(dev)) | |
4376 | I915_WRITE(VSYNCSHIFT(pipe), vsyncshift); | |
734b4157 | 4377 | |
5eddb70b CW |
4378 | I915_WRITE(HTOTAL(pipe), |
4379 | (adjusted_mode->crtc_hdisplay - 1) | | |
79e53945 | 4380 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
5eddb70b CW |
4381 | I915_WRITE(HBLANK(pipe), |
4382 | (adjusted_mode->crtc_hblank_start - 1) | | |
79e53945 | 4383 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
5eddb70b CW |
4384 | I915_WRITE(HSYNC(pipe), |
4385 | (adjusted_mode->crtc_hsync_start - 1) | | |
79e53945 | 4386 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
5eddb70b CW |
4387 | |
4388 | I915_WRITE(VTOTAL(pipe), | |
4389 | (adjusted_mode->crtc_vdisplay - 1) | | |
79e53945 | 4390 | ((adjusted_mode->crtc_vtotal - 1) << 16)); |
5eddb70b CW |
4391 | I915_WRITE(VBLANK(pipe), |
4392 | (adjusted_mode->crtc_vblank_start - 1) | | |
79e53945 | 4393 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); |
5eddb70b CW |
4394 | I915_WRITE(VSYNC(pipe), |
4395 | (adjusted_mode->crtc_vsync_start - 1) | | |
79e53945 | 4396 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
5eddb70b CW |
4397 | |
4398 | /* pipesrc and dspsize control the size that is scaled from, | |
4399 | * which should always be the user's requested size. | |
79e53945 | 4400 | */ |
929c77fb EA |
4401 | I915_WRITE(DSPSIZE(plane), |
4402 | ((mode->vdisplay - 1) << 16) | | |
4403 | (mode->hdisplay - 1)); | |
4404 | I915_WRITE(DSPPOS(plane), 0); | |
5eddb70b CW |
4405 | I915_WRITE(PIPESRC(pipe), |
4406 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); | |
2c07245f | 4407 | |
f564048e EA |
4408 | I915_WRITE(PIPECONF(pipe), pipeconf); |
4409 | POSTING_READ(PIPECONF(pipe)); | |
929c77fb | 4410 | intel_enable_pipe(dev_priv, pipe, false); |
f564048e EA |
4411 | |
4412 | intel_wait_for_vblank(dev, pipe); | |
4413 | ||
f564048e EA |
4414 | I915_WRITE(DSPCNTR(plane), dspcntr); |
4415 | POSTING_READ(DSPCNTR(plane)); | |
4416 | ||
4417 | ret = intel_pipe_set_base(crtc, x, y, old_fb); | |
4418 | ||
4419 | intel_update_watermarks(dev); | |
4420 | ||
f564048e EA |
4421 | return ret; |
4422 | } | |
4423 | ||
9fb526db KP |
4424 | /* |
4425 | * Initialize reference clocks when the driver loads | |
4426 | */ | |
4427 | void ironlake_init_pch_refclk(struct drm_device *dev) | |
13d83a67 JB |
4428 | { |
4429 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4430 | struct drm_mode_config *mode_config = &dev->mode_config; | |
13d83a67 | 4431 | struct intel_encoder *encoder; |
13d83a67 JB |
4432 | u32 temp; |
4433 | bool has_lvds = false; | |
199e5d79 KP |
4434 | bool has_cpu_edp = false; |
4435 | bool has_pch_edp = false; | |
4436 | bool has_panel = false; | |
99eb6a01 KP |
4437 | bool has_ck505 = false; |
4438 | bool can_ssc = false; | |
13d83a67 JB |
4439 | |
4440 | /* We need to take the global config into account */ | |
199e5d79 KP |
4441 | list_for_each_entry(encoder, &mode_config->encoder_list, |
4442 | base.head) { | |
4443 | switch (encoder->type) { | |
4444 | case INTEL_OUTPUT_LVDS: | |
4445 | has_panel = true; | |
4446 | has_lvds = true; | |
4447 | break; | |
4448 | case INTEL_OUTPUT_EDP: | |
4449 | has_panel = true; | |
4450 | if (intel_encoder_is_pch_edp(&encoder->base)) | |
4451 | has_pch_edp = true; | |
4452 | else | |
4453 | has_cpu_edp = true; | |
4454 | break; | |
13d83a67 JB |
4455 | } |
4456 | } | |
4457 | ||
99eb6a01 KP |
4458 | if (HAS_PCH_IBX(dev)) { |
4459 | has_ck505 = dev_priv->display_clock_mode; | |
4460 | can_ssc = has_ck505; | |
4461 | } else { | |
4462 | has_ck505 = false; | |
4463 | can_ssc = true; | |
4464 | } | |
4465 | ||
4466 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n", | |
4467 | has_panel, has_lvds, has_pch_edp, has_cpu_edp, | |
4468 | has_ck505); | |
13d83a67 JB |
4469 | |
4470 | /* Ironlake: try to setup display ref clock before DPLL | |
4471 | * enabling. This is only under driver's control after | |
4472 | * PCH B stepping, previous chipset stepping should be | |
4473 | * ignoring this setting. | |
4474 | */ | |
4475 | temp = I915_READ(PCH_DREF_CONTROL); | |
4476 | /* Always enable nonspread source */ | |
4477 | temp &= ~DREF_NONSPREAD_SOURCE_MASK; | |
13d83a67 | 4478 | |
99eb6a01 KP |
4479 | if (has_ck505) |
4480 | temp |= DREF_NONSPREAD_CK505_ENABLE; | |
4481 | else | |
4482 | temp |= DREF_NONSPREAD_SOURCE_ENABLE; | |
13d83a67 | 4483 | |
199e5d79 KP |
4484 | if (has_panel) { |
4485 | temp &= ~DREF_SSC_SOURCE_MASK; | |
4486 | temp |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 4487 | |
199e5d79 | 4488 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 4489 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 4490 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
13d83a67 | 4491 | temp |= DREF_SSC1_ENABLE; |
e77166b5 DV |
4492 | } else |
4493 | temp &= ~DREF_SSC1_ENABLE; | |
199e5d79 KP |
4494 | |
4495 | /* Get SSC going before enabling the outputs */ | |
4496 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
4497 | POSTING_READ(PCH_DREF_CONTROL); | |
4498 | udelay(200); | |
4499 | ||
13d83a67 JB |
4500 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
4501 | ||
4502 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 4503 | if (has_cpu_edp) { |
99eb6a01 | 4504 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 4505 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
13d83a67 | 4506 | temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
199e5d79 | 4507 | } |
13d83a67 JB |
4508 | else |
4509 | temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
199e5d79 KP |
4510 | } else |
4511 | temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
4512 | ||
4513 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
4514 | POSTING_READ(PCH_DREF_CONTROL); | |
4515 | udelay(200); | |
4516 | } else { | |
4517 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
4518 | ||
4519 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
4520 | ||
4521 | /* Turn off CPU output */ | |
4522 | temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
4523 | ||
4524 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
4525 | POSTING_READ(PCH_DREF_CONTROL); | |
4526 | udelay(200); | |
4527 | ||
4528 | /* Turn off the SSC source */ | |
4529 | temp &= ~DREF_SSC_SOURCE_MASK; | |
4530 | temp |= DREF_SSC_SOURCE_DISABLE; | |
4531 | ||
4532 | /* Turn off SSC1 */ | |
4533 | temp &= ~ DREF_SSC1_ENABLE; | |
4534 | ||
13d83a67 JB |
4535 | I915_WRITE(PCH_DREF_CONTROL, temp); |
4536 | POSTING_READ(PCH_DREF_CONTROL); | |
4537 | udelay(200); | |
4538 | } | |
4539 | } | |
4540 | ||
d9d444cb JB |
4541 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
4542 | { | |
4543 | struct drm_device *dev = crtc->dev; | |
4544 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4545 | struct intel_encoder *encoder; | |
d9d444cb JB |
4546 | struct intel_encoder *edp_encoder = NULL; |
4547 | int num_connectors = 0; | |
4548 | bool is_lvds = false; | |
4549 | ||
6c2b7c12 | 4550 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
d9d444cb JB |
4551 | switch (encoder->type) { |
4552 | case INTEL_OUTPUT_LVDS: | |
4553 | is_lvds = true; | |
4554 | break; | |
4555 | case INTEL_OUTPUT_EDP: | |
4556 | edp_encoder = encoder; | |
4557 | break; | |
4558 | } | |
4559 | num_connectors++; | |
4560 | } | |
4561 | ||
4562 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
4563 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", | |
4564 | dev_priv->lvds_ssc_freq); | |
4565 | return dev_priv->lvds_ssc_freq * 1000; | |
4566 | } | |
4567 | ||
4568 | return 120000; | |
4569 | } | |
4570 | ||
f564048e EA |
4571 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, |
4572 | struct drm_display_mode *mode, | |
4573 | struct drm_display_mode *adjusted_mode, | |
4574 | int x, int y, | |
4575 | struct drm_framebuffer *old_fb) | |
79e53945 JB |
4576 | { |
4577 | struct drm_device *dev = crtc->dev; | |
4578 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4579 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4580 | int pipe = intel_crtc->pipe; | |
80824003 | 4581 | int plane = intel_crtc->plane; |
c751ce4f | 4582 | int refclk, num_connectors = 0; |
652c393a | 4583 | intel_clock_t clock, reduced_clock; |
5eddb70b | 4584 | u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf; |
a07d6787 | 4585 | bool ok, has_reduced_clock = false, is_sdvo = false; |
a4fc5ed6 | 4586 | bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; |
e3aef172 | 4587 | struct intel_encoder *encoder, *edp_encoder = NULL; |
d4906093 | 4588 | const intel_limit_t *limit; |
5c3b82e2 | 4589 | int ret; |
2c07245f | 4590 | struct fdi_m_n m_n = {0}; |
fae14981 | 4591 | u32 temp; |
5a354204 JB |
4592 | int target_clock, pixel_multiplier, lane, link_bw, factor; |
4593 | unsigned int pipe_bpp; | |
4594 | bool dither; | |
e3aef172 | 4595 | bool is_cpu_edp = false, is_pch_edp = false; |
79e53945 | 4596 | |
6c2b7c12 | 4597 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5eddb70b | 4598 | switch (encoder->type) { |
79e53945 JB |
4599 | case INTEL_OUTPUT_LVDS: |
4600 | is_lvds = true; | |
4601 | break; | |
4602 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 4603 | case INTEL_OUTPUT_HDMI: |
79e53945 | 4604 | is_sdvo = true; |
5eddb70b | 4605 | if (encoder->needs_tv_clock) |
e2f0ba97 | 4606 | is_tv = true; |
79e53945 | 4607 | break; |
79e53945 JB |
4608 | case INTEL_OUTPUT_TVOUT: |
4609 | is_tv = true; | |
4610 | break; | |
4611 | case INTEL_OUTPUT_ANALOG: | |
4612 | is_crt = true; | |
4613 | break; | |
a4fc5ed6 KP |
4614 | case INTEL_OUTPUT_DISPLAYPORT: |
4615 | is_dp = true; | |
4616 | break; | |
32f9d658 | 4617 | case INTEL_OUTPUT_EDP: |
e3aef172 JB |
4618 | is_dp = true; |
4619 | if (intel_encoder_is_pch_edp(&encoder->base)) | |
4620 | is_pch_edp = true; | |
4621 | else | |
4622 | is_cpu_edp = true; | |
4623 | edp_encoder = encoder; | |
32f9d658 | 4624 | break; |
79e53945 | 4625 | } |
43565a06 | 4626 | |
c751ce4f | 4627 | num_connectors++; |
79e53945 JB |
4628 | } |
4629 | ||
d9d444cb | 4630 | refclk = ironlake_get_refclk(crtc); |
79e53945 | 4631 | |
d4906093 ML |
4632 | /* |
4633 | * Returns a set of divisors for the desired target clock with the given | |
4634 | * refclk, or FALSE. The returned values represent the clock equation: | |
4635 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
4636 | */ | |
1b894b59 | 4637 | limit = intel_limit(crtc, refclk); |
cec2f356 SP |
4638 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL, |
4639 | &clock); | |
79e53945 JB |
4640 | if (!ok) { |
4641 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
5c3b82e2 | 4642 | return -EINVAL; |
79e53945 JB |
4643 | } |
4644 | ||
cda4b7d3 | 4645 | /* Ensure that the cursor is valid for the new mode before changing... */ |
6b383a7f | 4646 | intel_crtc_update_cursor(crtc, true); |
cda4b7d3 | 4647 | |
ddc9003c | 4648 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
4649 | /* |
4650 | * Ensure we match the reduced clock's P to the target clock. | |
4651 | * If the clocks don't match, we can't switch the display clock | |
4652 | * by using the FP0/FP1. In such case we will disable the LVDS | |
4653 | * downclock feature. | |
4654 | */ | |
ddc9003c | 4655 | has_reduced_clock = limit->find_pll(limit, crtc, |
5eddb70b CW |
4656 | dev_priv->lvds_downclock, |
4657 | refclk, | |
cec2f356 | 4658 | &clock, |
5eddb70b | 4659 | &reduced_clock); |
652c393a | 4660 | } |
61e9653f DV |
4661 | |
4662 | if (is_sdvo && is_tv) | |
4663 | i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock); | |
4664 | ||
7026d4ac | 4665 | |
2c07245f | 4666 | /* FDI link */ |
8febb297 EA |
4667 | pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
4668 | lane = 0; | |
4669 | /* CPU eDP doesn't require FDI link, so just set DP M/N | |
4670 | according to current link config */ | |
e3aef172 | 4671 | if (is_cpu_edp) { |
e3aef172 | 4672 | intel_edp_link_config(edp_encoder, &lane, &link_bw); |
8febb297 | 4673 | } else { |
8febb297 EA |
4674 | /* FDI is a binary signal running at ~2.7GHz, encoding |
4675 | * each output octet as 10 bits. The actual frequency | |
4676 | * is stored as a divider into a 100MHz clock, and the | |
4677 | * mode pixel clock is stored in units of 1KHz. | |
4678 | * Hence the bw of each lane in terms of the mode signal | |
4679 | * is: | |
4680 | */ | |
4681 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
4682 | } | |
58a27471 | 4683 | |
94bf2ced DV |
4684 | /* [e]DP over FDI requires target mode clock instead of link clock. */ |
4685 | if (edp_encoder) | |
4686 | target_clock = intel_edp_target_clock(edp_encoder, mode); | |
4687 | else if (is_dp) | |
4688 | target_clock = mode->clock; | |
4689 | else | |
4690 | target_clock = adjusted_mode->clock; | |
4691 | ||
8febb297 EA |
4692 | /* determine panel color depth */ |
4693 | temp = I915_READ(PIPECONF(pipe)); | |
4694 | temp &= ~PIPE_BPC_MASK; | |
3b5c78a3 | 4695 | dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode); |
5a354204 JB |
4696 | switch (pipe_bpp) { |
4697 | case 18: | |
4698 | temp |= PIPE_6BPC; | |
8febb297 | 4699 | break; |
5a354204 JB |
4700 | case 24: |
4701 | temp |= PIPE_8BPC; | |
8febb297 | 4702 | break; |
5a354204 JB |
4703 | case 30: |
4704 | temp |= PIPE_10BPC; | |
8febb297 | 4705 | break; |
5a354204 JB |
4706 | case 36: |
4707 | temp |= PIPE_12BPC; | |
8febb297 EA |
4708 | break; |
4709 | default: | |
62ac41a6 JB |
4710 | WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n", |
4711 | pipe_bpp); | |
5a354204 JB |
4712 | temp |= PIPE_8BPC; |
4713 | pipe_bpp = 24; | |
4714 | break; | |
8febb297 | 4715 | } |
77ffb597 | 4716 | |
5a354204 JB |
4717 | intel_crtc->bpp = pipe_bpp; |
4718 | I915_WRITE(PIPECONF(pipe), temp); | |
4719 | ||
8febb297 EA |
4720 | if (!lane) { |
4721 | /* | |
4722 | * Account for spread spectrum to avoid | |
4723 | * oversubscribing the link. Max center spread | |
4724 | * is 2.5%; use 5% for safety's sake. | |
4725 | */ | |
5a354204 | 4726 | u32 bps = target_clock * intel_crtc->bpp * 21 / 20; |
8febb297 | 4727 | lane = bps / (link_bw * 8) + 1; |
5eb08b69 | 4728 | } |
2c07245f | 4729 | |
8febb297 EA |
4730 | intel_crtc->fdi_lanes = lane; |
4731 | ||
4732 | if (pixel_multiplier > 1) | |
4733 | link_bw *= pixel_multiplier; | |
5a354204 JB |
4734 | ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, |
4735 | &m_n); | |
8febb297 | 4736 | |
a07d6787 EA |
4737 | fp = clock.n << 16 | clock.m1 << 8 | clock.m2; |
4738 | if (has_reduced_clock) | |
4739 | fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 | | |
4740 | reduced_clock.m2; | |
79e53945 | 4741 | |
c1858123 | 4742 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
4743 | factor = 21; |
4744 | if (is_lvds) { | |
4745 | if ((intel_panel_use_ssc(dev_priv) && | |
4746 | dev_priv->lvds_ssc_freq == 100) || | |
4747 | (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP) | |
4748 | factor = 25; | |
4749 | } else if (is_sdvo && is_tv) | |
4750 | factor = 20; | |
c1858123 | 4751 | |
cb0e0931 | 4752 | if (clock.m < factor * clock.n) |
8febb297 | 4753 | fp |= FP_CB_TUNE; |
2c07245f | 4754 | |
5eddb70b | 4755 | dpll = 0; |
2c07245f | 4756 | |
a07d6787 EA |
4757 | if (is_lvds) |
4758 | dpll |= DPLLB_MODE_LVDS; | |
4759 | else | |
4760 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
4761 | if (is_sdvo) { | |
4762 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); | |
4763 | if (pixel_multiplier > 1) { | |
4764 | dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | |
79e53945 | 4765 | } |
a07d6787 EA |
4766 | dpll |= DPLL_DVO_HIGH_SPEED; |
4767 | } | |
e3aef172 | 4768 | if (is_dp && !is_cpu_edp) |
a07d6787 | 4769 | dpll |= DPLL_DVO_HIGH_SPEED; |
79e53945 | 4770 | |
a07d6787 EA |
4771 | /* compute bitmask from p1 value */ |
4772 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
4773 | /* also FPA1 */ | |
4774 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
4775 | ||
4776 | switch (clock.p2) { | |
4777 | case 5: | |
4778 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
4779 | break; | |
4780 | case 7: | |
4781 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
4782 | break; | |
4783 | case 10: | |
4784 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
4785 | break; | |
4786 | case 14: | |
4787 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
4788 | break; | |
79e53945 JB |
4789 | } |
4790 | ||
43565a06 KH |
4791 | if (is_sdvo && is_tv) |
4792 | dpll |= PLL_REF_INPUT_TVCLKINBC; | |
4793 | else if (is_tv) | |
79e53945 | 4794 | /* XXX: just matching BIOS for now */ |
43565a06 | 4795 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
79e53945 | 4796 | dpll |= 3; |
a7615030 | 4797 | else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 4798 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
4799 | else |
4800 | dpll |= PLL_REF_INPUT_DREFCLK; | |
4801 | ||
4802 | /* setup pipeconf */ | |
5eddb70b | 4803 | pipeconf = I915_READ(PIPECONF(pipe)); |
79e53945 JB |
4804 | |
4805 | /* Set up the display plane register */ | |
4806 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
4807 | ||
f7cb34d4 | 4808 | DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe); |
79e53945 JB |
4809 | drm_mode_debug_printmodeline(mode); |
4810 | ||
9d82aa17 ED |
4811 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own on |
4812 | * pre-Haswell/LPT generation */ | |
4813 | if (HAS_PCH_LPT(dev)) { | |
4814 | DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n", | |
4815 | pipe); | |
4816 | } else if (!is_cpu_edp) { | |
ee7b9f93 | 4817 | struct intel_pch_pll *pll; |
4b645f14 | 4818 | |
ee7b9f93 JB |
4819 | pll = intel_get_pch_pll(intel_crtc, dpll, fp); |
4820 | if (pll == NULL) { | |
4821 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n", | |
4822 | pipe); | |
4b645f14 JB |
4823 | return -EINVAL; |
4824 | } | |
ee7b9f93 JB |
4825 | } else |
4826 | intel_put_pch_pll(intel_crtc); | |
79e53945 JB |
4827 | |
4828 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. | |
4829 | * This is an exception to the general rule that mode_set doesn't turn | |
4830 | * things on. | |
4831 | */ | |
4832 | if (is_lvds) { | |
fae14981 | 4833 | temp = I915_READ(PCH_LVDS); |
5eddb70b | 4834 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; |
7885d205 JB |
4835 | if (HAS_PCH_CPT(dev)) { |
4836 | temp &= ~PORT_TRANS_SEL_MASK; | |
4b645f14 | 4837 | temp |= PORT_TRANS_SEL_CPT(pipe); |
7885d205 JB |
4838 | } else { |
4839 | if (pipe == 1) | |
4840 | temp |= LVDS_PIPEB_SELECT; | |
4841 | else | |
4842 | temp &= ~LVDS_PIPEB_SELECT; | |
4843 | } | |
4b645f14 | 4844 | |
a3e17eb8 | 4845 | /* set the corresponsding LVDS_BORDER bit */ |
5eddb70b | 4846 | temp |= dev_priv->lvds_border_bits; |
79e53945 JB |
4847 | /* Set the B0-B3 data pairs corresponding to whether we're going to |
4848 | * set the DPLLs for dual-channel mode or not. | |
4849 | */ | |
4850 | if (clock.p2 == 7) | |
5eddb70b | 4851 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; |
79e53945 | 4852 | else |
5eddb70b | 4853 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); |
79e53945 JB |
4854 | |
4855 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) | |
4856 | * appropriately here, but we need to look more thoroughly into how | |
4857 | * panels behave in the two modes. | |
4858 | */ | |
284d5df5 | 4859 | temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); |
aa9b500d | 4860 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
284d5df5 | 4861 | temp |= LVDS_HSYNC_POLARITY; |
aa9b500d | 4862 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) |
284d5df5 | 4863 | temp |= LVDS_VSYNC_POLARITY; |
fae14981 | 4864 | I915_WRITE(PCH_LVDS, temp); |
79e53945 | 4865 | } |
434ed097 | 4866 | |
8febb297 EA |
4867 | pipeconf &= ~PIPECONF_DITHER_EN; |
4868 | pipeconf &= ~PIPECONF_DITHER_TYPE_MASK; | |
5a354204 | 4869 | if ((is_lvds && dev_priv->lvds_dither) || dither) { |
8febb297 | 4870 | pipeconf |= PIPECONF_DITHER_EN; |
f74974c7 | 4871 | pipeconf |= PIPECONF_DITHER_TYPE_SP; |
434ed097 | 4872 | } |
e3aef172 | 4873 | if (is_dp && !is_cpu_edp) { |
a4fc5ed6 | 4874 | intel_dp_set_m_n(crtc, mode, adjusted_mode); |
8febb297 | 4875 | } else { |
8db9d77b | 4876 | /* For non-DP output, clear any trans DP clock recovery setting.*/ |
9db4a9c7 JB |
4877 | I915_WRITE(TRANSDATA_M1(pipe), 0); |
4878 | I915_WRITE(TRANSDATA_N1(pipe), 0); | |
4879 | I915_WRITE(TRANSDPLINK_M1(pipe), 0); | |
4880 | I915_WRITE(TRANSDPLINK_N1(pipe), 0); | |
8db9d77b | 4881 | } |
79e53945 | 4882 | |
ee7b9f93 JB |
4883 | if (intel_crtc->pch_pll) { |
4884 | I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll); | |
5eddb70b | 4885 | |
32f9d658 | 4886 | /* Wait for the clocks to stabilize. */ |
ee7b9f93 | 4887 | POSTING_READ(intel_crtc->pch_pll->pll_reg); |
32f9d658 ZW |
4888 | udelay(150); |
4889 | ||
8febb297 EA |
4890 | /* The pixel multiplier can only be updated once the |
4891 | * DPLL is enabled and the clocks are stable. | |
4892 | * | |
4893 | * So write it again. | |
4894 | */ | |
ee7b9f93 | 4895 | I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll); |
79e53945 | 4896 | } |
79e53945 | 4897 | |
5eddb70b | 4898 | intel_crtc->lowfreq_avail = false; |
ee7b9f93 | 4899 | if (intel_crtc->pch_pll) { |
4b645f14 | 4900 | if (is_lvds && has_reduced_clock && i915_powersave) { |
ee7b9f93 | 4901 | I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2); |
4b645f14 | 4902 | intel_crtc->lowfreq_avail = true; |
4b645f14 | 4903 | } else { |
ee7b9f93 | 4904 | I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp); |
652c393a JB |
4905 | } |
4906 | } | |
4907 | ||
617cf884 | 4908 | pipeconf &= ~PIPECONF_INTERLACE_MASK; |
734b4157 | 4909 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
5def474e | 4910 | pipeconf |= PIPECONF_INTERLACED_ILK; |
734b4157 | 4911 | /* the chip adds 2 halflines automatically */ |
734b4157 | 4912 | adjusted_mode->crtc_vtotal -= 1; |
734b4157 | 4913 | adjusted_mode->crtc_vblank_end -= 1; |
0529a0d9 DV |
4914 | I915_WRITE(VSYNCSHIFT(pipe), |
4915 | adjusted_mode->crtc_hsync_start | |
4916 | - adjusted_mode->crtc_htotal/2); | |
4917 | } else { | |
617cf884 | 4918 | pipeconf |= PIPECONF_PROGRESSIVE; |
0529a0d9 DV |
4919 | I915_WRITE(VSYNCSHIFT(pipe), 0); |
4920 | } | |
734b4157 | 4921 | |
5eddb70b CW |
4922 | I915_WRITE(HTOTAL(pipe), |
4923 | (adjusted_mode->crtc_hdisplay - 1) | | |
79e53945 | 4924 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
5eddb70b CW |
4925 | I915_WRITE(HBLANK(pipe), |
4926 | (adjusted_mode->crtc_hblank_start - 1) | | |
79e53945 | 4927 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
5eddb70b CW |
4928 | I915_WRITE(HSYNC(pipe), |
4929 | (adjusted_mode->crtc_hsync_start - 1) | | |
79e53945 | 4930 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
5eddb70b CW |
4931 | |
4932 | I915_WRITE(VTOTAL(pipe), | |
4933 | (adjusted_mode->crtc_vdisplay - 1) | | |
79e53945 | 4934 | ((adjusted_mode->crtc_vtotal - 1) << 16)); |
5eddb70b CW |
4935 | I915_WRITE(VBLANK(pipe), |
4936 | (adjusted_mode->crtc_vblank_start - 1) | | |
79e53945 | 4937 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); |
5eddb70b CW |
4938 | I915_WRITE(VSYNC(pipe), |
4939 | (adjusted_mode->crtc_vsync_start - 1) | | |
79e53945 | 4940 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
5eddb70b | 4941 | |
8febb297 EA |
4942 | /* pipesrc controls the size that is scaled from, which should |
4943 | * always be the user's requested size. | |
79e53945 | 4944 | */ |
5eddb70b CW |
4945 | I915_WRITE(PIPESRC(pipe), |
4946 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); | |
2c07245f | 4947 | |
8febb297 EA |
4948 | I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); |
4949 | I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n); | |
4950 | I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m); | |
4951 | I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n); | |
2c07245f | 4952 | |
e3aef172 | 4953 | if (is_cpu_edp) |
8febb297 | 4954 | ironlake_set_pll_edp(crtc, adjusted_mode->clock); |
2c07245f | 4955 | |
5eddb70b CW |
4956 | I915_WRITE(PIPECONF(pipe), pipeconf); |
4957 | POSTING_READ(PIPECONF(pipe)); | |
79e53945 | 4958 | |
9d0498a2 | 4959 | intel_wait_for_vblank(dev, pipe); |
79e53945 | 4960 | |
5eddb70b | 4961 | I915_WRITE(DSPCNTR(plane), dspcntr); |
b24e7179 | 4962 | POSTING_READ(DSPCNTR(plane)); |
79e53945 | 4963 | |
5c3b82e2 | 4964 | ret = intel_pipe_set_base(crtc, x, y, old_fb); |
7662c8bd SL |
4965 | |
4966 | intel_update_watermarks(dev); | |
4967 | ||
1f8eeabf ED |
4968 | intel_update_linetime_watermarks(dev, pipe, adjusted_mode); |
4969 | ||
1f803ee5 | 4970 | return ret; |
79e53945 JB |
4971 | } |
4972 | ||
f564048e EA |
4973 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
4974 | struct drm_display_mode *mode, | |
4975 | struct drm_display_mode *adjusted_mode, | |
4976 | int x, int y, | |
4977 | struct drm_framebuffer *old_fb) | |
4978 | { | |
4979 | struct drm_device *dev = crtc->dev; | |
4980 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0b701d27 EA |
4981 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4982 | int pipe = intel_crtc->pipe; | |
f564048e EA |
4983 | int ret; |
4984 | ||
0b701d27 | 4985 | drm_vblank_pre_modeset(dev, pipe); |
7662c8bd | 4986 | |
f564048e EA |
4987 | ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode, |
4988 | x, y, old_fb); | |
79e53945 | 4989 | drm_vblank_post_modeset(dev, pipe); |
5c3b82e2 | 4990 | |
d8e70a25 JB |
4991 | if (ret) |
4992 | intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF; | |
4993 | else | |
4994 | intel_crtc->dpms_mode = DRM_MODE_DPMS_ON; | |
120eced9 | 4995 | |
1f803ee5 | 4996 | return ret; |
79e53945 JB |
4997 | } |
4998 | ||
3a9627f4 WF |
4999 | static bool intel_eld_uptodate(struct drm_connector *connector, |
5000 | int reg_eldv, uint32_t bits_eldv, | |
5001 | int reg_elda, uint32_t bits_elda, | |
5002 | int reg_edid) | |
5003 | { | |
5004 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
5005 | uint8_t *eld = connector->eld; | |
5006 | uint32_t i; | |
5007 | ||
5008 | i = I915_READ(reg_eldv); | |
5009 | i &= bits_eldv; | |
5010 | ||
5011 | if (!eld[0]) | |
5012 | return !i; | |
5013 | ||
5014 | if (!i) | |
5015 | return false; | |
5016 | ||
5017 | i = I915_READ(reg_elda); | |
5018 | i &= ~bits_elda; | |
5019 | I915_WRITE(reg_elda, i); | |
5020 | ||
5021 | for (i = 0; i < eld[2]; i++) | |
5022 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) | |
5023 | return false; | |
5024 | ||
5025 | return true; | |
5026 | } | |
5027 | ||
e0dac65e WF |
5028 | static void g4x_write_eld(struct drm_connector *connector, |
5029 | struct drm_crtc *crtc) | |
5030 | { | |
5031 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
5032 | uint8_t *eld = connector->eld; | |
5033 | uint32_t eldv; | |
5034 | uint32_t len; | |
5035 | uint32_t i; | |
5036 | ||
5037 | i = I915_READ(G4X_AUD_VID_DID); | |
5038 | ||
5039 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) | |
5040 | eldv = G4X_ELDV_DEVCL_DEVBLC; | |
5041 | else | |
5042 | eldv = G4X_ELDV_DEVCTG; | |
5043 | ||
3a9627f4 WF |
5044 | if (intel_eld_uptodate(connector, |
5045 | G4X_AUD_CNTL_ST, eldv, | |
5046 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, | |
5047 | G4X_HDMIW_HDMIEDID)) | |
5048 | return; | |
5049 | ||
e0dac65e WF |
5050 | i = I915_READ(G4X_AUD_CNTL_ST); |
5051 | i &= ~(eldv | G4X_ELD_ADDR); | |
5052 | len = (i >> 9) & 0x1f; /* ELD buffer size */ | |
5053 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
5054 | ||
5055 | if (!eld[0]) | |
5056 | return; | |
5057 | ||
5058 | len = min_t(uint8_t, eld[2], len); | |
5059 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
5060 | for (i = 0; i < len; i++) | |
5061 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); | |
5062 | ||
5063 | i = I915_READ(G4X_AUD_CNTL_ST); | |
5064 | i |= eldv; | |
5065 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
5066 | } | |
5067 | ||
5068 | static void ironlake_write_eld(struct drm_connector *connector, | |
5069 | struct drm_crtc *crtc) | |
5070 | { | |
5071 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
5072 | uint8_t *eld = connector->eld; | |
5073 | uint32_t eldv; | |
5074 | uint32_t i; | |
5075 | int len; | |
5076 | int hdmiw_hdmiedid; | |
b6daa025 | 5077 | int aud_config; |
e0dac65e WF |
5078 | int aud_cntl_st; |
5079 | int aud_cntrl_st2; | |
5080 | ||
b3f33cbf | 5081 | if (HAS_PCH_IBX(connector->dev)) { |
1202b4c6 | 5082 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A; |
b6daa025 | 5083 | aud_config = IBX_AUD_CONFIG_A; |
1202b4c6 WF |
5084 | aud_cntl_st = IBX_AUD_CNTL_ST_A; |
5085 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; | |
e0dac65e | 5086 | } else { |
1202b4c6 | 5087 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A; |
b6daa025 | 5088 | aud_config = CPT_AUD_CONFIG_A; |
1202b4c6 WF |
5089 | aud_cntl_st = CPT_AUD_CNTL_ST_A; |
5090 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; | |
e0dac65e WF |
5091 | } |
5092 | ||
5093 | i = to_intel_crtc(crtc)->pipe; | |
5094 | hdmiw_hdmiedid += i * 0x100; | |
5095 | aud_cntl_st += i * 0x100; | |
b6daa025 | 5096 | aud_config += i * 0x100; |
e0dac65e WF |
5097 | |
5098 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i)); | |
5099 | ||
5100 | i = I915_READ(aud_cntl_st); | |
5101 | i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */ | |
5102 | if (!i) { | |
5103 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); | |
5104 | /* operate blindly on all ports */ | |
1202b4c6 WF |
5105 | eldv = IBX_ELD_VALIDB; |
5106 | eldv |= IBX_ELD_VALIDB << 4; | |
5107 | eldv |= IBX_ELD_VALIDB << 8; | |
e0dac65e WF |
5108 | } else { |
5109 | DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i); | |
1202b4c6 | 5110 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
e0dac65e WF |
5111 | } |
5112 | ||
3a9627f4 WF |
5113 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
5114 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
5115 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
b6daa025 WF |
5116 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
5117 | } else | |
5118 | I915_WRITE(aud_config, 0); | |
e0dac65e | 5119 | |
3a9627f4 WF |
5120 | if (intel_eld_uptodate(connector, |
5121 | aud_cntrl_st2, eldv, | |
5122 | aud_cntl_st, IBX_ELD_ADDRESS, | |
5123 | hdmiw_hdmiedid)) | |
5124 | return; | |
5125 | ||
e0dac65e WF |
5126 | i = I915_READ(aud_cntrl_st2); |
5127 | i &= ~eldv; | |
5128 | I915_WRITE(aud_cntrl_st2, i); | |
5129 | ||
5130 | if (!eld[0]) | |
5131 | return; | |
5132 | ||
e0dac65e | 5133 | i = I915_READ(aud_cntl_st); |
1202b4c6 | 5134 | i &= ~IBX_ELD_ADDRESS; |
e0dac65e WF |
5135 | I915_WRITE(aud_cntl_st, i); |
5136 | ||
5137 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
5138 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
5139 | for (i = 0; i < len; i++) | |
5140 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
5141 | ||
5142 | i = I915_READ(aud_cntrl_st2); | |
5143 | i |= eldv; | |
5144 | I915_WRITE(aud_cntrl_st2, i); | |
5145 | } | |
5146 | ||
5147 | void intel_write_eld(struct drm_encoder *encoder, | |
5148 | struct drm_display_mode *mode) | |
5149 | { | |
5150 | struct drm_crtc *crtc = encoder->crtc; | |
5151 | struct drm_connector *connector; | |
5152 | struct drm_device *dev = encoder->dev; | |
5153 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5154 | ||
5155 | connector = drm_select_eld(encoder, mode); | |
5156 | if (!connector) | |
5157 | return; | |
5158 | ||
5159 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", | |
5160 | connector->base.id, | |
5161 | drm_get_connector_name(connector), | |
5162 | connector->encoder->base.id, | |
5163 | drm_get_encoder_name(connector->encoder)); | |
5164 | ||
5165 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; | |
5166 | ||
5167 | if (dev_priv->display.write_eld) | |
5168 | dev_priv->display.write_eld(connector, crtc); | |
5169 | } | |
5170 | ||
79e53945 JB |
5171 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ |
5172 | void intel_crtc_load_lut(struct drm_crtc *crtc) | |
5173 | { | |
5174 | struct drm_device *dev = crtc->dev; | |
5175 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5176 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9db4a9c7 | 5177 | int palreg = PALETTE(intel_crtc->pipe); |
79e53945 JB |
5178 | int i; |
5179 | ||
5180 | /* The clocks have to be on to load the palette. */ | |
aed3f09d | 5181 | if (!crtc->enabled || !intel_crtc->active) |
79e53945 JB |
5182 | return; |
5183 | ||
f2b115e6 | 5184 | /* use legacy palette for Ironlake */ |
bad720ff | 5185 | if (HAS_PCH_SPLIT(dev)) |
9db4a9c7 | 5186 | palreg = LGC_PALETTE(intel_crtc->pipe); |
2c07245f | 5187 | |
79e53945 JB |
5188 | for (i = 0; i < 256; i++) { |
5189 | I915_WRITE(palreg + 4 * i, | |
5190 | (intel_crtc->lut_r[i] << 16) | | |
5191 | (intel_crtc->lut_g[i] << 8) | | |
5192 | intel_crtc->lut_b[i]); | |
5193 | } | |
5194 | } | |
5195 | ||
560b85bb CW |
5196 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
5197 | { | |
5198 | struct drm_device *dev = crtc->dev; | |
5199 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5200 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5201 | bool visible = base != 0; | |
5202 | u32 cntl; | |
5203 | ||
5204 | if (intel_crtc->cursor_visible == visible) | |
5205 | return; | |
5206 | ||
9db4a9c7 | 5207 | cntl = I915_READ(_CURACNTR); |
560b85bb CW |
5208 | if (visible) { |
5209 | /* On these chipsets we can only modify the base whilst | |
5210 | * the cursor is disabled. | |
5211 | */ | |
9db4a9c7 | 5212 | I915_WRITE(_CURABASE, base); |
560b85bb CW |
5213 | |
5214 | cntl &= ~(CURSOR_FORMAT_MASK); | |
5215 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ | |
5216 | cntl |= CURSOR_ENABLE | | |
5217 | CURSOR_GAMMA_ENABLE | | |
5218 | CURSOR_FORMAT_ARGB; | |
5219 | } else | |
5220 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); | |
9db4a9c7 | 5221 | I915_WRITE(_CURACNTR, cntl); |
560b85bb CW |
5222 | |
5223 | intel_crtc->cursor_visible = visible; | |
5224 | } | |
5225 | ||
5226 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) | |
5227 | { | |
5228 | struct drm_device *dev = crtc->dev; | |
5229 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5230 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5231 | int pipe = intel_crtc->pipe; | |
5232 | bool visible = base != 0; | |
5233 | ||
5234 | if (intel_crtc->cursor_visible != visible) { | |
548f245b | 5235 | uint32_t cntl = I915_READ(CURCNTR(pipe)); |
560b85bb CW |
5236 | if (base) { |
5237 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); | |
5238 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
5239 | cntl |= pipe << 28; /* Connect to correct pipe */ | |
5240 | } else { | |
5241 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
5242 | cntl |= CURSOR_MODE_DISABLE; | |
5243 | } | |
9db4a9c7 | 5244 | I915_WRITE(CURCNTR(pipe), cntl); |
560b85bb CW |
5245 | |
5246 | intel_crtc->cursor_visible = visible; | |
5247 | } | |
5248 | /* and commit changes on next vblank */ | |
9db4a9c7 | 5249 | I915_WRITE(CURBASE(pipe), base); |
560b85bb CW |
5250 | } |
5251 | ||
65a21cd6 JB |
5252 | static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) |
5253 | { | |
5254 | struct drm_device *dev = crtc->dev; | |
5255 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5256 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5257 | int pipe = intel_crtc->pipe; | |
5258 | bool visible = base != 0; | |
5259 | ||
5260 | if (intel_crtc->cursor_visible != visible) { | |
5261 | uint32_t cntl = I915_READ(CURCNTR_IVB(pipe)); | |
5262 | if (base) { | |
5263 | cntl &= ~CURSOR_MODE; | |
5264 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
5265 | } else { | |
5266 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
5267 | cntl |= CURSOR_MODE_DISABLE; | |
5268 | } | |
5269 | I915_WRITE(CURCNTR_IVB(pipe), cntl); | |
5270 | ||
5271 | intel_crtc->cursor_visible = visible; | |
5272 | } | |
5273 | /* and commit changes on next vblank */ | |
5274 | I915_WRITE(CURBASE_IVB(pipe), base); | |
5275 | } | |
5276 | ||
cda4b7d3 | 5277 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
5278 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
5279 | bool on) | |
cda4b7d3 CW |
5280 | { |
5281 | struct drm_device *dev = crtc->dev; | |
5282 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5283 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5284 | int pipe = intel_crtc->pipe; | |
5285 | int x = intel_crtc->cursor_x; | |
5286 | int y = intel_crtc->cursor_y; | |
560b85bb | 5287 | u32 base, pos; |
cda4b7d3 CW |
5288 | bool visible; |
5289 | ||
5290 | pos = 0; | |
5291 | ||
6b383a7f | 5292 | if (on && crtc->enabled && crtc->fb) { |
cda4b7d3 CW |
5293 | base = intel_crtc->cursor_addr; |
5294 | if (x > (int) crtc->fb->width) | |
5295 | base = 0; | |
5296 | ||
5297 | if (y > (int) crtc->fb->height) | |
5298 | base = 0; | |
5299 | } else | |
5300 | base = 0; | |
5301 | ||
5302 | if (x < 0) { | |
5303 | if (x + intel_crtc->cursor_width < 0) | |
5304 | base = 0; | |
5305 | ||
5306 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
5307 | x = -x; | |
5308 | } | |
5309 | pos |= x << CURSOR_X_SHIFT; | |
5310 | ||
5311 | if (y < 0) { | |
5312 | if (y + intel_crtc->cursor_height < 0) | |
5313 | base = 0; | |
5314 | ||
5315 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
5316 | y = -y; | |
5317 | } | |
5318 | pos |= y << CURSOR_Y_SHIFT; | |
5319 | ||
5320 | visible = base != 0; | |
560b85bb | 5321 | if (!visible && !intel_crtc->cursor_visible) |
cda4b7d3 CW |
5322 | return; |
5323 | ||
0cd83aa9 | 5324 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
65a21cd6 JB |
5325 | I915_WRITE(CURPOS_IVB(pipe), pos); |
5326 | ivb_update_cursor(crtc, base); | |
5327 | } else { | |
5328 | I915_WRITE(CURPOS(pipe), pos); | |
5329 | if (IS_845G(dev) || IS_I865G(dev)) | |
5330 | i845_update_cursor(crtc, base); | |
5331 | else | |
5332 | i9xx_update_cursor(crtc, base); | |
5333 | } | |
cda4b7d3 CW |
5334 | } |
5335 | ||
79e53945 | 5336 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
05394f39 | 5337 | struct drm_file *file, |
79e53945 JB |
5338 | uint32_t handle, |
5339 | uint32_t width, uint32_t height) | |
5340 | { | |
5341 | struct drm_device *dev = crtc->dev; | |
5342 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5343 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 5344 | struct drm_i915_gem_object *obj; |
cda4b7d3 | 5345 | uint32_t addr; |
3f8bc370 | 5346 | int ret; |
79e53945 | 5347 | |
28c97730 | 5348 | DRM_DEBUG_KMS("\n"); |
79e53945 JB |
5349 | |
5350 | /* if we want to turn off the cursor ignore width and height */ | |
5351 | if (!handle) { | |
28c97730 | 5352 | DRM_DEBUG_KMS("cursor off\n"); |
3f8bc370 | 5353 | addr = 0; |
05394f39 | 5354 | obj = NULL; |
5004417d | 5355 | mutex_lock(&dev->struct_mutex); |
3f8bc370 | 5356 | goto finish; |
79e53945 JB |
5357 | } |
5358 | ||
5359 | /* Currently we only support 64x64 cursors */ | |
5360 | if (width != 64 || height != 64) { | |
5361 | DRM_ERROR("we currently only support 64x64 cursors\n"); | |
5362 | return -EINVAL; | |
5363 | } | |
5364 | ||
05394f39 | 5365 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 5366 | if (&obj->base == NULL) |
79e53945 JB |
5367 | return -ENOENT; |
5368 | ||
05394f39 | 5369 | if (obj->base.size < width * height * 4) { |
79e53945 | 5370 | DRM_ERROR("buffer is to small\n"); |
34b8686e DA |
5371 | ret = -ENOMEM; |
5372 | goto fail; | |
79e53945 JB |
5373 | } |
5374 | ||
71acb5eb | 5375 | /* we only need to pin inside GTT if cursor is non-phy */ |
7f9872e0 | 5376 | mutex_lock(&dev->struct_mutex); |
b295d1b6 | 5377 | if (!dev_priv->info->cursor_needs_physical) { |
d9e86c0e CW |
5378 | if (obj->tiling_mode) { |
5379 | DRM_ERROR("cursor cannot be tiled\n"); | |
5380 | ret = -EINVAL; | |
5381 | goto fail_locked; | |
5382 | } | |
5383 | ||
2da3b9b9 | 5384 | ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL); |
e7b526bb CW |
5385 | if (ret) { |
5386 | DRM_ERROR("failed to move cursor bo into the GTT\n"); | |
2da3b9b9 | 5387 | goto fail_locked; |
e7b526bb CW |
5388 | } |
5389 | ||
d9e86c0e CW |
5390 | ret = i915_gem_object_put_fence(obj); |
5391 | if (ret) { | |
2da3b9b9 | 5392 | DRM_ERROR("failed to release fence for cursor"); |
d9e86c0e CW |
5393 | goto fail_unpin; |
5394 | } | |
5395 | ||
05394f39 | 5396 | addr = obj->gtt_offset; |
71acb5eb | 5397 | } else { |
6eeefaf3 | 5398 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
05394f39 | 5399 | ret = i915_gem_attach_phys_object(dev, obj, |
6eeefaf3 CW |
5400 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
5401 | align); | |
71acb5eb DA |
5402 | if (ret) { |
5403 | DRM_ERROR("failed to attach phys object\n"); | |
7f9872e0 | 5404 | goto fail_locked; |
71acb5eb | 5405 | } |
05394f39 | 5406 | addr = obj->phys_obj->handle->busaddr; |
3f8bc370 KH |
5407 | } |
5408 | ||
a6c45cf0 | 5409 | if (IS_GEN2(dev)) |
14b60391 JB |
5410 | I915_WRITE(CURSIZE, (height << 12) | width); |
5411 | ||
3f8bc370 | 5412 | finish: |
3f8bc370 | 5413 | if (intel_crtc->cursor_bo) { |
b295d1b6 | 5414 | if (dev_priv->info->cursor_needs_physical) { |
05394f39 | 5415 | if (intel_crtc->cursor_bo != obj) |
71acb5eb DA |
5416 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); |
5417 | } else | |
5418 | i915_gem_object_unpin(intel_crtc->cursor_bo); | |
05394f39 | 5419 | drm_gem_object_unreference(&intel_crtc->cursor_bo->base); |
3f8bc370 | 5420 | } |
80824003 | 5421 | |
7f9872e0 | 5422 | mutex_unlock(&dev->struct_mutex); |
3f8bc370 KH |
5423 | |
5424 | intel_crtc->cursor_addr = addr; | |
05394f39 | 5425 | intel_crtc->cursor_bo = obj; |
cda4b7d3 CW |
5426 | intel_crtc->cursor_width = width; |
5427 | intel_crtc->cursor_height = height; | |
5428 | ||
6b383a7f | 5429 | intel_crtc_update_cursor(crtc, true); |
3f8bc370 | 5430 | |
79e53945 | 5431 | return 0; |
e7b526bb | 5432 | fail_unpin: |
05394f39 | 5433 | i915_gem_object_unpin(obj); |
7f9872e0 | 5434 | fail_locked: |
34b8686e | 5435 | mutex_unlock(&dev->struct_mutex); |
bc9025bd | 5436 | fail: |
05394f39 | 5437 | drm_gem_object_unreference_unlocked(&obj->base); |
34b8686e | 5438 | return ret; |
79e53945 JB |
5439 | } |
5440 | ||
5441 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
5442 | { | |
79e53945 | 5443 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 5444 | |
cda4b7d3 CW |
5445 | intel_crtc->cursor_x = x; |
5446 | intel_crtc->cursor_y = y; | |
652c393a | 5447 | |
6b383a7f | 5448 | intel_crtc_update_cursor(crtc, true); |
79e53945 JB |
5449 | |
5450 | return 0; | |
5451 | } | |
5452 | ||
5453 | /** Sets the color ramps on behalf of RandR */ | |
5454 | void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, | |
5455 | u16 blue, int regno) | |
5456 | { | |
5457 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5458 | ||
5459 | intel_crtc->lut_r[regno] = red >> 8; | |
5460 | intel_crtc->lut_g[regno] = green >> 8; | |
5461 | intel_crtc->lut_b[regno] = blue >> 8; | |
5462 | } | |
5463 | ||
b8c00ac5 DA |
5464 | void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
5465 | u16 *blue, int regno) | |
5466 | { | |
5467 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5468 | ||
5469 | *red = intel_crtc->lut_r[regno] << 8; | |
5470 | *green = intel_crtc->lut_g[regno] << 8; | |
5471 | *blue = intel_crtc->lut_b[regno] << 8; | |
5472 | } | |
5473 | ||
79e53945 | 5474 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 5475 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 5476 | { |
7203425a | 5477 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 5478 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 5479 | |
7203425a | 5480 | for (i = start; i < end; i++) { |
79e53945 JB |
5481 | intel_crtc->lut_r[i] = red[i] >> 8; |
5482 | intel_crtc->lut_g[i] = green[i] >> 8; | |
5483 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
5484 | } | |
5485 | ||
5486 | intel_crtc_load_lut(crtc); | |
5487 | } | |
5488 | ||
5489 | /** | |
5490 | * Get a pipe with a simple mode set on it for doing load-based monitor | |
5491 | * detection. | |
5492 | * | |
5493 | * It will be up to the load-detect code to adjust the pipe as appropriate for | |
c751ce4f | 5494 | * its requirements. The pipe will be connected to no other encoders. |
79e53945 | 5495 | * |
c751ce4f | 5496 | * Currently this code will only succeed if there is a pipe with no encoders |
79e53945 JB |
5497 | * configured for it. In the future, it could choose to temporarily disable |
5498 | * some outputs to free up a pipe for its use. | |
5499 | * | |
5500 | * \return crtc, or NULL if no pipes are available. | |
5501 | */ | |
5502 | ||
5503 | /* VESA 640x480x72Hz mode to set on the pipe */ | |
5504 | static struct drm_display_mode load_detect_mode = { | |
5505 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
5506 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
5507 | }; | |
5508 | ||
d2dff872 CW |
5509 | static struct drm_framebuffer * |
5510 | intel_framebuffer_create(struct drm_device *dev, | |
308e5bcb | 5511 | struct drm_mode_fb_cmd2 *mode_cmd, |
d2dff872 CW |
5512 | struct drm_i915_gem_object *obj) |
5513 | { | |
5514 | struct intel_framebuffer *intel_fb; | |
5515 | int ret; | |
5516 | ||
5517 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
5518 | if (!intel_fb) { | |
5519 | drm_gem_object_unreference_unlocked(&obj->base); | |
5520 | return ERR_PTR(-ENOMEM); | |
5521 | } | |
5522 | ||
5523 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
5524 | if (ret) { | |
5525 | drm_gem_object_unreference_unlocked(&obj->base); | |
5526 | kfree(intel_fb); | |
5527 | return ERR_PTR(ret); | |
5528 | } | |
5529 | ||
5530 | return &intel_fb->base; | |
5531 | } | |
5532 | ||
5533 | static u32 | |
5534 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
5535 | { | |
5536 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
5537 | return ALIGN(pitch, 64); | |
5538 | } | |
5539 | ||
5540 | static u32 | |
5541 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
5542 | { | |
5543 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
5544 | return ALIGN(pitch * mode->vdisplay, PAGE_SIZE); | |
5545 | } | |
5546 | ||
5547 | static struct drm_framebuffer * | |
5548 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
5549 | struct drm_display_mode *mode, | |
5550 | int depth, int bpp) | |
5551 | { | |
5552 | struct drm_i915_gem_object *obj; | |
308e5bcb | 5553 | struct drm_mode_fb_cmd2 mode_cmd; |
d2dff872 CW |
5554 | |
5555 | obj = i915_gem_alloc_object(dev, | |
5556 | intel_framebuffer_size_for_mode(mode, bpp)); | |
5557 | if (obj == NULL) | |
5558 | return ERR_PTR(-ENOMEM); | |
5559 | ||
5560 | mode_cmd.width = mode->hdisplay; | |
5561 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
5562 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
5563 | bpp); | |
5ca0c34a | 5564 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
5565 | |
5566 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
5567 | } | |
5568 | ||
5569 | static struct drm_framebuffer * | |
5570 | mode_fits_in_fbdev(struct drm_device *dev, | |
5571 | struct drm_display_mode *mode) | |
5572 | { | |
5573 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5574 | struct drm_i915_gem_object *obj; | |
5575 | struct drm_framebuffer *fb; | |
5576 | ||
5577 | if (dev_priv->fbdev == NULL) | |
5578 | return NULL; | |
5579 | ||
5580 | obj = dev_priv->fbdev->ifb.obj; | |
5581 | if (obj == NULL) | |
5582 | return NULL; | |
5583 | ||
5584 | fb = &dev_priv->fbdev->ifb.base; | |
01f2c773 VS |
5585 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
5586 | fb->bits_per_pixel)) | |
d2dff872 CW |
5587 | return NULL; |
5588 | ||
01f2c773 | 5589 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
5590 | return NULL; |
5591 | ||
5592 | return fb; | |
5593 | } | |
5594 | ||
7173188d CW |
5595 | bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder, |
5596 | struct drm_connector *connector, | |
5597 | struct drm_display_mode *mode, | |
8261b191 | 5598 | struct intel_load_detect_pipe *old) |
79e53945 JB |
5599 | { |
5600 | struct intel_crtc *intel_crtc; | |
5601 | struct drm_crtc *possible_crtc; | |
4ef69c7a | 5602 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
5603 | struct drm_crtc *crtc = NULL; |
5604 | struct drm_device *dev = encoder->dev; | |
d2dff872 | 5605 | struct drm_framebuffer *old_fb; |
79e53945 JB |
5606 | int i = -1; |
5607 | ||
d2dff872 CW |
5608 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
5609 | connector->base.id, drm_get_connector_name(connector), | |
5610 | encoder->base.id, drm_get_encoder_name(encoder)); | |
5611 | ||
79e53945 JB |
5612 | /* |
5613 | * Algorithm gets a little messy: | |
7a5e4805 | 5614 | * |
79e53945 JB |
5615 | * - if the connector already has an assigned crtc, use it (but make |
5616 | * sure it's on first) | |
7a5e4805 | 5617 | * |
79e53945 JB |
5618 | * - try to find the first unused crtc that can drive this connector, |
5619 | * and use that if we find one | |
79e53945 JB |
5620 | */ |
5621 | ||
5622 | /* See if we already have a CRTC for this connector */ | |
5623 | if (encoder->crtc) { | |
5624 | crtc = encoder->crtc; | |
8261b191 | 5625 | |
79e53945 | 5626 | intel_crtc = to_intel_crtc(crtc); |
8261b191 CW |
5627 | old->dpms_mode = intel_crtc->dpms_mode; |
5628 | old->load_detect_temp = false; | |
5629 | ||
5630 | /* Make sure the crtc and connector are running */ | |
79e53945 | 5631 | if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) { |
6492711d CW |
5632 | struct drm_encoder_helper_funcs *encoder_funcs; |
5633 | struct drm_crtc_helper_funcs *crtc_funcs; | |
5634 | ||
79e53945 JB |
5635 | crtc_funcs = crtc->helper_private; |
5636 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); | |
6492711d CW |
5637 | |
5638 | encoder_funcs = encoder->helper_private; | |
79e53945 JB |
5639 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); |
5640 | } | |
8261b191 | 5641 | |
7173188d | 5642 | return true; |
79e53945 JB |
5643 | } |
5644 | ||
5645 | /* Find an unused one (if possible) */ | |
5646 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { | |
5647 | i++; | |
5648 | if (!(encoder->possible_crtcs & (1 << i))) | |
5649 | continue; | |
5650 | if (!possible_crtc->enabled) { | |
5651 | crtc = possible_crtc; | |
5652 | break; | |
5653 | } | |
79e53945 JB |
5654 | } |
5655 | ||
5656 | /* | |
5657 | * If we didn't find an unused CRTC, don't use any. | |
5658 | */ | |
5659 | if (!crtc) { | |
7173188d CW |
5660 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
5661 | return false; | |
79e53945 JB |
5662 | } |
5663 | ||
5664 | encoder->crtc = crtc; | |
c1c43977 | 5665 | connector->encoder = encoder; |
79e53945 JB |
5666 | |
5667 | intel_crtc = to_intel_crtc(crtc); | |
8261b191 CW |
5668 | old->dpms_mode = intel_crtc->dpms_mode; |
5669 | old->load_detect_temp = true; | |
d2dff872 | 5670 | old->release_fb = NULL; |
79e53945 | 5671 | |
6492711d CW |
5672 | if (!mode) |
5673 | mode = &load_detect_mode; | |
79e53945 | 5674 | |
d2dff872 CW |
5675 | old_fb = crtc->fb; |
5676 | ||
5677 | /* We need a framebuffer large enough to accommodate all accesses | |
5678 | * that the plane may generate whilst we perform load detection. | |
5679 | * We can not rely on the fbcon either being present (we get called | |
5680 | * during its initialisation to detect all boot displays, or it may | |
5681 | * not even exist) or that it is large enough to satisfy the | |
5682 | * requested mode. | |
5683 | */ | |
5684 | crtc->fb = mode_fits_in_fbdev(dev, mode); | |
5685 | if (crtc->fb == NULL) { | |
5686 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); | |
5687 | crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); | |
5688 | old->release_fb = crtc->fb; | |
5689 | } else | |
5690 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
5691 | if (IS_ERR(crtc->fb)) { | |
5692 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); | |
5693 | crtc->fb = old_fb; | |
5694 | return false; | |
79e53945 | 5695 | } |
79e53945 | 5696 | |
d2dff872 | 5697 | if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) { |
6492711d | 5698 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
5699 | if (old->release_fb) |
5700 | old->release_fb->funcs->destroy(old->release_fb); | |
5701 | crtc->fb = old_fb; | |
6492711d | 5702 | return false; |
79e53945 | 5703 | } |
7173188d | 5704 | |
79e53945 | 5705 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 5706 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
79e53945 | 5707 | |
7173188d | 5708 | return true; |
79e53945 JB |
5709 | } |
5710 | ||
c1c43977 | 5711 | void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder, |
8261b191 CW |
5712 | struct drm_connector *connector, |
5713 | struct intel_load_detect_pipe *old) | |
79e53945 | 5714 | { |
4ef69c7a | 5715 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
5716 | struct drm_device *dev = encoder->dev; |
5717 | struct drm_crtc *crtc = encoder->crtc; | |
5718 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
5719 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
5720 | ||
d2dff872 CW |
5721 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
5722 | connector->base.id, drm_get_connector_name(connector), | |
5723 | encoder->base.id, drm_get_encoder_name(encoder)); | |
5724 | ||
8261b191 | 5725 | if (old->load_detect_temp) { |
c1c43977 | 5726 | connector->encoder = NULL; |
79e53945 | 5727 | drm_helper_disable_unused_functions(dev); |
d2dff872 CW |
5728 | |
5729 | if (old->release_fb) | |
5730 | old->release_fb->funcs->destroy(old->release_fb); | |
5731 | ||
0622a53c | 5732 | return; |
79e53945 JB |
5733 | } |
5734 | ||
c751ce4f | 5735 | /* Switch crtc and encoder back off if necessary */ |
0622a53c CW |
5736 | if (old->dpms_mode != DRM_MODE_DPMS_ON) { |
5737 | encoder_funcs->dpms(encoder, old->dpms_mode); | |
8261b191 | 5738 | crtc_funcs->dpms(crtc, old->dpms_mode); |
79e53945 JB |
5739 | } |
5740 | } | |
5741 | ||
5742 | /* Returns the clock of the currently programmed mode of the given pipe. */ | |
5743 | static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc) | |
5744 | { | |
5745 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5746 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5747 | int pipe = intel_crtc->pipe; | |
548f245b | 5748 | u32 dpll = I915_READ(DPLL(pipe)); |
79e53945 JB |
5749 | u32 fp; |
5750 | intel_clock_t clock; | |
5751 | ||
5752 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
39adb7a5 | 5753 | fp = I915_READ(FP0(pipe)); |
79e53945 | 5754 | else |
39adb7a5 | 5755 | fp = I915_READ(FP1(pipe)); |
79e53945 JB |
5756 | |
5757 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
5758 | if (IS_PINEVIEW(dev)) { |
5759 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
5760 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
5761 | } else { |
5762 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
5763 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
5764 | } | |
5765 | ||
a6c45cf0 | 5766 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
5767 | if (IS_PINEVIEW(dev)) |
5768 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
5769 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
5770 | else |
5771 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
5772 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
5773 | ||
5774 | switch (dpll & DPLL_MODE_MASK) { | |
5775 | case DPLLB_MODE_DAC_SERIAL: | |
5776 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
5777 | 5 : 10; | |
5778 | break; | |
5779 | case DPLLB_MODE_LVDS: | |
5780 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
5781 | 7 : 14; | |
5782 | break; | |
5783 | default: | |
28c97730 | 5784 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 JB |
5785 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
5786 | return 0; | |
5787 | } | |
5788 | ||
5789 | /* XXX: Handle the 100Mhz refclk */ | |
2177832f | 5790 | intel_clock(dev, 96000, &clock); |
79e53945 JB |
5791 | } else { |
5792 | bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); | |
5793 | ||
5794 | if (is_lvds) { | |
5795 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
5796 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
5797 | clock.p2 = 14; | |
5798 | ||
5799 | if ((dpll & PLL_REF_INPUT_MASK) == | |
5800 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
5801 | /* XXX: might not be 66MHz */ | |
2177832f | 5802 | intel_clock(dev, 66000, &clock); |
79e53945 | 5803 | } else |
2177832f | 5804 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
5805 | } else { |
5806 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
5807 | clock.p1 = 2; | |
5808 | else { | |
5809 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
5810 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
5811 | } | |
5812 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
5813 | clock.p2 = 4; | |
5814 | else | |
5815 | clock.p2 = 2; | |
5816 | ||
2177832f | 5817 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
5818 | } |
5819 | } | |
5820 | ||
5821 | /* XXX: It would be nice to validate the clocks, but we can't reuse | |
5822 | * i830PllIsValid() because it relies on the xf86_config connector | |
5823 | * configuration being accurate, which it isn't necessarily. | |
5824 | */ | |
5825 | ||
5826 | return clock.dot; | |
5827 | } | |
5828 | ||
5829 | /** Returns the currently programmed mode of the given pipe. */ | |
5830 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
5831 | struct drm_crtc *crtc) | |
5832 | { | |
548f245b | 5833 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 JB |
5834 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5835 | int pipe = intel_crtc->pipe; | |
5836 | struct drm_display_mode *mode; | |
548f245b JB |
5837 | int htot = I915_READ(HTOTAL(pipe)); |
5838 | int hsync = I915_READ(HSYNC(pipe)); | |
5839 | int vtot = I915_READ(VTOTAL(pipe)); | |
5840 | int vsync = I915_READ(VSYNC(pipe)); | |
79e53945 JB |
5841 | |
5842 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
5843 | if (!mode) | |
5844 | return NULL; | |
5845 | ||
5846 | mode->clock = intel_crtc_clock_get(dev, crtc); | |
5847 | mode->hdisplay = (htot & 0xffff) + 1; | |
5848 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
5849 | mode->hsync_start = (hsync & 0xffff) + 1; | |
5850 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
5851 | mode->vdisplay = (vtot & 0xffff) + 1; | |
5852 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
5853 | mode->vsync_start = (vsync & 0xffff) + 1; | |
5854 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
5855 | ||
5856 | drm_mode_set_name(mode); | |
79e53945 JB |
5857 | |
5858 | return mode; | |
5859 | } | |
5860 | ||
652c393a JB |
5861 | #define GPU_IDLE_TIMEOUT 500 /* ms */ |
5862 | ||
5863 | /* When this timer fires, we've been idle for awhile */ | |
5864 | static void intel_gpu_idle_timer(unsigned long arg) | |
5865 | { | |
5866 | struct drm_device *dev = (struct drm_device *)arg; | |
5867 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5868 | ||
ff7ea4c0 CW |
5869 | if (!list_empty(&dev_priv->mm.active_list)) { |
5870 | /* Still processing requests, so just re-arm the timer. */ | |
5871 | mod_timer(&dev_priv->idle_timer, jiffies + | |
5872 | msecs_to_jiffies(GPU_IDLE_TIMEOUT)); | |
5873 | return; | |
5874 | } | |
652c393a | 5875 | |
ff7ea4c0 | 5876 | dev_priv->busy = false; |
01dfba93 | 5877 | queue_work(dev_priv->wq, &dev_priv->idle_work); |
652c393a JB |
5878 | } |
5879 | ||
652c393a JB |
5880 | #define CRTC_IDLE_TIMEOUT 1000 /* ms */ |
5881 | ||
5882 | static void intel_crtc_idle_timer(unsigned long arg) | |
5883 | { | |
5884 | struct intel_crtc *intel_crtc = (struct intel_crtc *)arg; | |
5885 | struct drm_crtc *crtc = &intel_crtc->base; | |
5886 | drm_i915_private_t *dev_priv = crtc->dev->dev_private; | |
ff7ea4c0 | 5887 | struct intel_framebuffer *intel_fb; |
652c393a | 5888 | |
ff7ea4c0 CW |
5889 | intel_fb = to_intel_framebuffer(crtc->fb); |
5890 | if (intel_fb && intel_fb->obj->active) { | |
5891 | /* The framebuffer is still being accessed by the GPU. */ | |
5892 | mod_timer(&intel_crtc->idle_timer, jiffies + | |
5893 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); | |
5894 | return; | |
5895 | } | |
652c393a | 5896 | |
ff7ea4c0 | 5897 | intel_crtc->busy = false; |
01dfba93 | 5898 | queue_work(dev_priv->wq, &dev_priv->idle_work); |
652c393a JB |
5899 | } |
5900 | ||
3dec0095 | 5901 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
652c393a JB |
5902 | { |
5903 | struct drm_device *dev = crtc->dev; | |
5904 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5905 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5906 | int pipe = intel_crtc->pipe; | |
dbdc6479 JB |
5907 | int dpll_reg = DPLL(pipe); |
5908 | int dpll; | |
652c393a | 5909 | |
bad720ff | 5910 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
5911 | return; |
5912 | ||
5913 | if (!dev_priv->lvds_downclock_avail) | |
5914 | return; | |
5915 | ||
dbdc6479 | 5916 | dpll = I915_READ(dpll_reg); |
652c393a | 5917 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
44d98a61 | 5918 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
652c393a | 5919 | |
8ac5a6d5 | 5920 | assert_panel_unlocked(dev_priv, pipe); |
652c393a JB |
5921 | |
5922 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; | |
5923 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 5924 | intel_wait_for_vblank(dev, pipe); |
dbdc6479 | 5925 | |
652c393a JB |
5926 | dpll = I915_READ(dpll_reg); |
5927 | if (dpll & DISPLAY_RATE_SELECT_FPA1) | |
44d98a61 | 5928 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
652c393a JB |
5929 | } |
5930 | ||
5931 | /* Schedule downclock */ | |
3dec0095 DV |
5932 | mod_timer(&intel_crtc->idle_timer, jiffies + |
5933 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); | |
652c393a JB |
5934 | } |
5935 | ||
5936 | static void intel_decrease_pllclock(struct drm_crtc *crtc) | |
5937 | { | |
5938 | struct drm_device *dev = crtc->dev; | |
5939 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5940 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
652c393a | 5941 | |
bad720ff | 5942 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
5943 | return; |
5944 | ||
5945 | if (!dev_priv->lvds_downclock_avail) | |
5946 | return; | |
5947 | ||
5948 | /* | |
5949 | * Since this is called by a timer, we should never get here in | |
5950 | * the manual case. | |
5951 | */ | |
5952 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
dc257cf1 DV |
5953 | int pipe = intel_crtc->pipe; |
5954 | int dpll_reg = DPLL(pipe); | |
5955 | int dpll; | |
f6e5b160 | 5956 | |
44d98a61 | 5957 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 5958 | |
8ac5a6d5 | 5959 | assert_panel_unlocked(dev_priv, pipe); |
652c393a | 5960 | |
dc257cf1 | 5961 | dpll = I915_READ(dpll_reg); |
652c393a JB |
5962 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
5963 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 5964 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
5965 | dpll = I915_READ(dpll_reg); |
5966 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 5967 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
5968 | } |
5969 | ||
5970 | } | |
5971 | ||
5972 | /** | |
5973 | * intel_idle_update - adjust clocks for idleness | |
5974 | * @work: work struct | |
5975 | * | |
5976 | * Either the GPU or display (or both) went idle. Check the busy status | |
5977 | * here and adjust the CRTC and GPU clocks as necessary. | |
5978 | */ | |
5979 | static void intel_idle_update(struct work_struct *work) | |
5980 | { | |
5981 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
5982 | idle_work); | |
5983 | struct drm_device *dev = dev_priv->dev; | |
5984 | struct drm_crtc *crtc; | |
5985 | struct intel_crtc *intel_crtc; | |
5986 | ||
5987 | if (!i915_powersave) | |
5988 | return; | |
5989 | ||
5990 | mutex_lock(&dev->struct_mutex); | |
5991 | ||
7648fa99 JB |
5992 | i915_update_gfx_val(dev_priv); |
5993 | ||
652c393a JB |
5994 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
5995 | /* Skip inactive CRTCs */ | |
5996 | if (!crtc->fb) | |
5997 | continue; | |
5998 | ||
5999 | intel_crtc = to_intel_crtc(crtc); | |
6000 | if (!intel_crtc->busy) | |
6001 | intel_decrease_pllclock(crtc); | |
6002 | } | |
6003 | ||
45ac22c8 | 6004 | |
652c393a JB |
6005 | mutex_unlock(&dev->struct_mutex); |
6006 | } | |
6007 | ||
6008 | /** | |
6009 | * intel_mark_busy - mark the GPU and possibly the display busy | |
6010 | * @dev: drm device | |
6011 | * @obj: object we're operating on | |
6012 | * | |
6013 | * Callers can use this function to indicate that the GPU is busy processing | |
6014 | * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout | |
6015 | * buffer), we'll also mark the display as busy, so we know to increase its | |
6016 | * clock frequency. | |
6017 | */ | |
05394f39 | 6018 | void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj) |
652c393a JB |
6019 | { |
6020 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6021 | struct drm_crtc *crtc = NULL; | |
6022 | struct intel_framebuffer *intel_fb; | |
6023 | struct intel_crtc *intel_crtc; | |
6024 | ||
5e17ee74 ZW |
6025 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
6026 | return; | |
6027 | ||
9104183d CW |
6028 | if (!dev_priv->busy) { |
6029 | intel_sanitize_pm(dev); | |
28cf798f | 6030 | dev_priv->busy = true; |
9104183d | 6031 | } else |
28cf798f CW |
6032 | mod_timer(&dev_priv->idle_timer, jiffies + |
6033 | msecs_to_jiffies(GPU_IDLE_TIMEOUT)); | |
652c393a | 6034 | |
acb87dfb CW |
6035 | if (obj == NULL) |
6036 | return; | |
6037 | ||
652c393a JB |
6038 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
6039 | if (!crtc->fb) | |
6040 | continue; | |
6041 | ||
6042 | intel_crtc = to_intel_crtc(crtc); | |
6043 | intel_fb = to_intel_framebuffer(crtc->fb); | |
6044 | if (intel_fb->obj == obj) { | |
6045 | if (!intel_crtc->busy) { | |
6046 | /* Non-busy -> busy, upclock */ | |
3dec0095 | 6047 | intel_increase_pllclock(crtc); |
652c393a JB |
6048 | intel_crtc->busy = true; |
6049 | } else { | |
6050 | /* Busy -> busy, put off timer */ | |
6051 | mod_timer(&intel_crtc->idle_timer, jiffies + | |
6052 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); | |
6053 | } | |
6054 | } | |
6055 | } | |
6056 | } | |
6057 | ||
79e53945 JB |
6058 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
6059 | { | |
6060 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
6061 | struct drm_device *dev = crtc->dev; |
6062 | struct intel_unpin_work *work; | |
6063 | unsigned long flags; | |
6064 | ||
6065 | spin_lock_irqsave(&dev->event_lock, flags); | |
6066 | work = intel_crtc->unpin_work; | |
6067 | intel_crtc->unpin_work = NULL; | |
6068 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
6069 | ||
6070 | if (work) { | |
6071 | cancel_work_sync(&work->work); | |
6072 | kfree(work); | |
6073 | } | |
79e53945 JB |
6074 | |
6075 | drm_crtc_cleanup(crtc); | |
67e77c5a | 6076 | |
79e53945 JB |
6077 | kfree(intel_crtc); |
6078 | } | |
6079 | ||
6b95a207 KH |
6080 | static void intel_unpin_work_fn(struct work_struct *__work) |
6081 | { | |
6082 | struct intel_unpin_work *work = | |
6083 | container_of(__work, struct intel_unpin_work, work); | |
6084 | ||
6085 | mutex_lock(&work->dev->struct_mutex); | |
1690e1eb | 6086 | intel_unpin_fb_obj(work->old_fb_obj); |
05394f39 CW |
6087 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
6088 | drm_gem_object_unreference(&work->old_fb_obj->base); | |
d9e86c0e | 6089 | |
7782de3b | 6090 | intel_update_fbc(work->dev); |
6b95a207 KH |
6091 | mutex_unlock(&work->dev->struct_mutex); |
6092 | kfree(work); | |
6093 | } | |
6094 | ||
1afe3e9d | 6095 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 6096 | struct drm_crtc *crtc) |
6b95a207 KH |
6097 | { |
6098 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6b95a207 KH |
6099 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6100 | struct intel_unpin_work *work; | |
05394f39 | 6101 | struct drm_i915_gem_object *obj; |
6b95a207 | 6102 | struct drm_pending_vblank_event *e; |
49b14a5c | 6103 | struct timeval tnow, tvbl; |
6b95a207 KH |
6104 | unsigned long flags; |
6105 | ||
6106 | /* Ignore early vblank irqs */ | |
6107 | if (intel_crtc == NULL) | |
6108 | return; | |
6109 | ||
49b14a5c MK |
6110 | do_gettimeofday(&tnow); |
6111 | ||
6b95a207 KH |
6112 | spin_lock_irqsave(&dev->event_lock, flags); |
6113 | work = intel_crtc->unpin_work; | |
6114 | if (work == NULL || !work->pending) { | |
6115 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
6116 | return; | |
6117 | } | |
6118 | ||
6119 | intel_crtc->unpin_work = NULL; | |
6b95a207 KH |
6120 | |
6121 | if (work->event) { | |
6122 | e = work->event; | |
49b14a5c | 6123 | e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl); |
0af7e4df MK |
6124 | |
6125 | /* Called before vblank count and timestamps have | |
6126 | * been updated for the vblank interval of flip | |
6127 | * completion? Need to increment vblank count and | |
6128 | * add one videorefresh duration to returned timestamp | |
49b14a5c MK |
6129 | * to account for this. We assume this happened if we |
6130 | * get called over 0.9 frame durations after the last | |
6131 | * timestamped vblank. | |
6132 | * | |
6133 | * This calculation can not be used with vrefresh rates | |
6134 | * below 5Hz (10Hz to be on the safe side) without | |
6135 | * promoting to 64 integers. | |
0af7e4df | 6136 | */ |
49b14a5c MK |
6137 | if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) > |
6138 | 9 * crtc->framedur_ns) { | |
0af7e4df | 6139 | e->event.sequence++; |
49b14a5c MK |
6140 | tvbl = ns_to_timeval(timeval_to_ns(&tvbl) + |
6141 | crtc->framedur_ns); | |
0af7e4df MK |
6142 | } |
6143 | ||
49b14a5c MK |
6144 | e->event.tv_sec = tvbl.tv_sec; |
6145 | e->event.tv_usec = tvbl.tv_usec; | |
0af7e4df | 6146 | |
6b95a207 KH |
6147 | list_add_tail(&e->base.link, |
6148 | &e->base.file_priv->event_list); | |
6149 | wake_up_interruptible(&e->base.file_priv->event_wait); | |
6150 | } | |
6151 | ||
0af7e4df MK |
6152 | drm_vblank_put(dev, intel_crtc->pipe); |
6153 | ||
6b95a207 KH |
6154 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6155 | ||
05394f39 | 6156 | obj = work->old_fb_obj; |
d9e86c0e | 6157 | |
e59f2bac | 6158 | atomic_clear_mask(1 << intel_crtc->plane, |
05394f39 CW |
6159 | &obj->pending_flip.counter); |
6160 | if (atomic_read(&obj->pending_flip) == 0) | |
f787a5f5 | 6161 | wake_up(&dev_priv->pending_flip_queue); |
d9e86c0e | 6162 | |
6b95a207 | 6163 | schedule_work(&work->work); |
e5510fac JB |
6164 | |
6165 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); | |
6b95a207 KH |
6166 | } |
6167 | ||
1afe3e9d JB |
6168 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
6169 | { | |
6170 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6171 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
6172 | ||
49b14a5c | 6173 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
6174 | } |
6175 | ||
6176 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
6177 | { | |
6178 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6179 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; | |
6180 | ||
49b14a5c | 6181 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
6182 | } |
6183 | ||
6b95a207 KH |
6184 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
6185 | { | |
6186 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6187 | struct intel_crtc *intel_crtc = | |
6188 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
6189 | unsigned long flags; | |
6190 | ||
6191 | spin_lock_irqsave(&dev->event_lock, flags); | |
de3f440f | 6192 | if (intel_crtc->unpin_work) { |
4e5359cd SF |
6193 | if ((++intel_crtc->unpin_work->pending) > 1) |
6194 | DRM_ERROR("Prepared flip multiple times\n"); | |
de3f440f JB |
6195 | } else { |
6196 | DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n"); | |
6197 | } | |
6b95a207 KH |
6198 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6199 | } | |
6200 | ||
8c9f3aaf JB |
6201 | static int intel_gen2_queue_flip(struct drm_device *dev, |
6202 | struct drm_crtc *crtc, | |
6203 | struct drm_framebuffer *fb, | |
6204 | struct drm_i915_gem_object *obj) | |
6205 | { | |
6206 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6207 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8c9f3aaf | 6208 | u32 flip_mask; |
6d90c952 | 6209 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
6210 | int ret; |
6211 | ||
6d90c952 | 6212 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 6213 | if (ret) |
83d4092b | 6214 | goto err; |
8c9f3aaf | 6215 | |
6d90c952 | 6216 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 6217 | if (ret) |
83d4092b | 6218 | goto err_unpin; |
8c9f3aaf JB |
6219 | |
6220 | /* Can't queue multiple flips, so wait for the previous | |
6221 | * one to finish before executing the next. | |
6222 | */ | |
6223 | if (intel_crtc->plane) | |
6224 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
6225 | else | |
6226 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
6227 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
6228 | intel_ring_emit(ring, MI_NOOP); | |
6229 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
6230 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
6231 | intel_ring_emit(ring, fb->pitches[0]); | |
e506a0c6 | 6232 | intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); |
6d90c952 DV |
6233 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
6234 | intel_ring_advance(ring); | |
83d4092b CW |
6235 | return 0; |
6236 | ||
6237 | err_unpin: | |
6238 | intel_unpin_fb_obj(obj); | |
6239 | err: | |
8c9f3aaf JB |
6240 | return ret; |
6241 | } | |
6242 | ||
6243 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
6244 | struct drm_crtc *crtc, | |
6245 | struct drm_framebuffer *fb, | |
6246 | struct drm_i915_gem_object *obj) | |
6247 | { | |
6248 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6249 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8c9f3aaf | 6250 | u32 flip_mask; |
6d90c952 | 6251 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
6252 | int ret; |
6253 | ||
6d90c952 | 6254 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 6255 | if (ret) |
83d4092b | 6256 | goto err; |
8c9f3aaf | 6257 | |
6d90c952 | 6258 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 6259 | if (ret) |
83d4092b | 6260 | goto err_unpin; |
8c9f3aaf JB |
6261 | |
6262 | if (intel_crtc->plane) | |
6263 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
6264 | else | |
6265 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
6266 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
6267 | intel_ring_emit(ring, MI_NOOP); | |
6268 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
6269 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
6270 | intel_ring_emit(ring, fb->pitches[0]); | |
e506a0c6 | 6271 | intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); |
6d90c952 DV |
6272 | intel_ring_emit(ring, MI_NOOP); |
6273 | ||
6274 | intel_ring_advance(ring); | |
83d4092b CW |
6275 | return 0; |
6276 | ||
6277 | err_unpin: | |
6278 | intel_unpin_fb_obj(obj); | |
6279 | err: | |
8c9f3aaf JB |
6280 | return ret; |
6281 | } | |
6282 | ||
6283 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
6284 | struct drm_crtc *crtc, | |
6285 | struct drm_framebuffer *fb, | |
6286 | struct drm_i915_gem_object *obj) | |
6287 | { | |
6288 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6289 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6290 | uint32_t pf, pipesrc; | |
6d90c952 | 6291 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
6292 | int ret; |
6293 | ||
6d90c952 | 6294 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 6295 | if (ret) |
83d4092b | 6296 | goto err; |
8c9f3aaf | 6297 | |
6d90c952 | 6298 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 6299 | if (ret) |
83d4092b | 6300 | goto err_unpin; |
8c9f3aaf JB |
6301 | |
6302 | /* i965+ uses the linear or tiled offsets from the | |
6303 | * Display Registers (which do not change across a page-flip) | |
6304 | * so we need only reprogram the base address. | |
6305 | */ | |
6d90c952 DV |
6306 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
6307 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
6308 | intel_ring_emit(ring, fb->pitches[0]); | |
c2c75131 DV |
6309 | intel_ring_emit(ring, |
6310 | (obj->gtt_offset + intel_crtc->dspaddr_offset) | | |
6311 | obj->tiling_mode); | |
8c9f3aaf JB |
6312 | |
6313 | /* XXX Enabling the panel-fitter across page-flip is so far | |
6314 | * untested on non-native modes, so ignore it for now. | |
6315 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
6316 | */ | |
6317 | pf = 0; | |
6318 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 DV |
6319 | intel_ring_emit(ring, pf | pipesrc); |
6320 | intel_ring_advance(ring); | |
83d4092b CW |
6321 | return 0; |
6322 | ||
6323 | err_unpin: | |
6324 | intel_unpin_fb_obj(obj); | |
6325 | err: | |
8c9f3aaf JB |
6326 | return ret; |
6327 | } | |
6328 | ||
6329 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
6330 | struct drm_crtc *crtc, | |
6331 | struct drm_framebuffer *fb, | |
6332 | struct drm_i915_gem_object *obj) | |
6333 | { | |
6334 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6335 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6d90c952 | 6336 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
6337 | uint32_t pf, pipesrc; |
6338 | int ret; | |
6339 | ||
6d90c952 | 6340 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 6341 | if (ret) |
83d4092b | 6342 | goto err; |
8c9f3aaf | 6343 | |
6d90c952 | 6344 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 6345 | if (ret) |
83d4092b | 6346 | goto err_unpin; |
8c9f3aaf | 6347 | |
6d90c952 DV |
6348 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
6349 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
6350 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
c2c75131 | 6351 | intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); |
8c9f3aaf | 6352 | |
dc257cf1 DV |
6353 | /* Contrary to the suggestions in the documentation, |
6354 | * "Enable Panel Fitter" does not seem to be required when page | |
6355 | * flipping with a non-native mode, and worse causes a normal | |
6356 | * modeset to fail. | |
6357 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
6358 | */ | |
6359 | pf = 0; | |
8c9f3aaf | 6360 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 DV |
6361 | intel_ring_emit(ring, pf | pipesrc); |
6362 | intel_ring_advance(ring); | |
83d4092b CW |
6363 | return 0; |
6364 | ||
6365 | err_unpin: | |
6366 | intel_unpin_fb_obj(obj); | |
6367 | err: | |
8c9f3aaf JB |
6368 | return ret; |
6369 | } | |
6370 | ||
7c9017e5 JB |
6371 | /* |
6372 | * On gen7 we currently use the blit ring because (in early silicon at least) | |
6373 | * the render ring doesn't give us interrpts for page flip completion, which | |
6374 | * means clients will hang after the first flip is queued. Fortunately the | |
6375 | * blit ring generates interrupts properly, so use it instead. | |
6376 | */ | |
6377 | static int intel_gen7_queue_flip(struct drm_device *dev, | |
6378 | struct drm_crtc *crtc, | |
6379 | struct drm_framebuffer *fb, | |
6380 | struct drm_i915_gem_object *obj) | |
6381 | { | |
6382 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6383 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6384 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; | |
cb05d8de | 6385 | uint32_t plane_bit = 0; |
7c9017e5 JB |
6386 | int ret; |
6387 | ||
6388 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); | |
6389 | if (ret) | |
83d4092b | 6390 | goto err; |
7c9017e5 | 6391 | |
cb05d8de DV |
6392 | switch(intel_crtc->plane) { |
6393 | case PLANE_A: | |
6394 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
6395 | break; | |
6396 | case PLANE_B: | |
6397 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
6398 | break; | |
6399 | case PLANE_C: | |
6400 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
6401 | break; | |
6402 | default: | |
6403 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
6404 | ret = -ENODEV; | |
6405 | goto err; | |
6406 | } | |
6407 | ||
7c9017e5 JB |
6408 | ret = intel_ring_begin(ring, 4); |
6409 | if (ret) | |
83d4092b | 6410 | goto err_unpin; |
7c9017e5 | 6411 | |
cb05d8de | 6412 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 6413 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
c2c75131 | 6414 | intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); |
7c9017e5 JB |
6415 | intel_ring_emit(ring, (MI_NOOP)); |
6416 | intel_ring_advance(ring); | |
83d4092b CW |
6417 | return 0; |
6418 | ||
6419 | err_unpin: | |
6420 | intel_unpin_fb_obj(obj); | |
6421 | err: | |
7c9017e5 JB |
6422 | return ret; |
6423 | } | |
6424 | ||
8c9f3aaf JB |
6425 | static int intel_default_queue_flip(struct drm_device *dev, |
6426 | struct drm_crtc *crtc, | |
6427 | struct drm_framebuffer *fb, | |
6428 | struct drm_i915_gem_object *obj) | |
6429 | { | |
6430 | return -ENODEV; | |
6431 | } | |
6432 | ||
6b95a207 KH |
6433 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
6434 | struct drm_framebuffer *fb, | |
6435 | struct drm_pending_vblank_event *event) | |
6436 | { | |
6437 | struct drm_device *dev = crtc->dev; | |
6438 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6439 | struct intel_framebuffer *intel_fb; | |
05394f39 | 6440 | struct drm_i915_gem_object *obj; |
6b95a207 KH |
6441 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6442 | struct intel_unpin_work *work; | |
8c9f3aaf | 6443 | unsigned long flags; |
52e68630 | 6444 | int ret; |
6b95a207 | 6445 | |
e6a595d2 VS |
6446 | /* Can't change pixel format via MI display flips. */ |
6447 | if (fb->pixel_format != crtc->fb->pixel_format) | |
6448 | return -EINVAL; | |
6449 | ||
6450 | /* | |
6451 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
6452 | * Note that pitch changes could also affect these register. | |
6453 | */ | |
6454 | if (INTEL_INFO(dev)->gen > 3 && | |
6455 | (fb->offsets[0] != crtc->fb->offsets[0] || | |
6456 | fb->pitches[0] != crtc->fb->pitches[0])) | |
6457 | return -EINVAL; | |
6458 | ||
6b95a207 KH |
6459 | work = kzalloc(sizeof *work, GFP_KERNEL); |
6460 | if (work == NULL) | |
6461 | return -ENOMEM; | |
6462 | ||
6b95a207 KH |
6463 | work->event = event; |
6464 | work->dev = crtc->dev; | |
6465 | intel_fb = to_intel_framebuffer(crtc->fb); | |
b1b87f6b | 6466 | work->old_fb_obj = intel_fb->obj; |
6b95a207 KH |
6467 | INIT_WORK(&work->work, intel_unpin_work_fn); |
6468 | ||
7317c75e JB |
6469 | ret = drm_vblank_get(dev, intel_crtc->pipe); |
6470 | if (ret) | |
6471 | goto free_work; | |
6472 | ||
6b95a207 KH |
6473 | /* We borrow the event spin lock for protecting unpin_work */ |
6474 | spin_lock_irqsave(&dev->event_lock, flags); | |
6475 | if (intel_crtc->unpin_work) { | |
6476 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
6477 | kfree(work); | |
7317c75e | 6478 | drm_vblank_put(dev, intel_crtc->pipe); |
468f0b44 CW |
6479 | |
6480 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
6b95a207 KH |
6481 | return -EBUSY; |
6482 | } | |
6483 | intel_crtc->unpin_work = work; | |
6484 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
6485 | ||
6486 | intel_fb = to_intel_framebuffer(fb); | |
6487 | obj = intel_fb->obj; | |
6488 | ||
79158103 CW |
6489 | ret = i915_mutex_lock_interruptible(dev); |
6490 | if (ret) | |
6491 | goto cleanup; | |
6b95a207 | 6492 | |
75dfca80 | 6493 | /* Reference the objects for the scheduled work. */ |
05394f39 CW |
6494 | drm_gem_object_reference(&work->old_fb_obj->base); |
6495 | drm_gem_object_reference(&obj->base); | |
6b95a207 KH |
6496 | |
6497 | crtc->fb = fb; | |
96b099fd | 6498 | |
e1f99ce6 | 6499 | work->pending_flip_obj = obj; |
e1f99ce6 | 6500 | |
4e5359cd SF |
6501 | work->enable_stall_check = true; |
6502 | ||
e1f99ce6 CW |
6503 | /* Block clients from rendering to the new back buffer until |
6504 | * the flip occurs and the object is no longer visible. | |
6505 | */ | |
05394f39 | 6506 | atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip); |
e1f99ce6 | 6507 | |
8c9f3aaf JB |
6508 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj); |
6509 | if (ret) | |
6510 | goto cleanup_pending; | |
6b95a207 | 6511 | |
7782de3b | 6512 | intel_disable_fbc(dev); |
acb87dfb | 6513 | intel_mark_busy(dev, obj); |
6b95a207 KH |
6514 | mutex_unlock(&dev->struct_mutex); |
6515 | ||
e5510fac JB |
6516 | trace_i915_flip_request(intel_crtc->plane, obj); |
6517 | ||
6b95a207 | 6518 | return 0; |
96b099fd | 6519 | |
8c9f3aaf JB |
6520 | cleanup_pending: |
6521 | atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip); | |
05394f39 CW |
6522 | drm_gem_object_unreference(&work->old_fb_obj->base); |
6523 | drm_gem_object_unreference(&obj->base); | |
96b099fd CW |
6524 | mutex_unlock(&dev->struct_mutex); |
6525 | ||
79158103 | 6526 | cleanup: |
96b099fd CW |
6527 | spin_lock_irqsave(&dev->event_lock, flags); |
6528 | intel_crtc->unpin_work = NULL; | |
6529 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
6530 | ||
7317c75e JB |
6531 | drm_vblank_put(dev, intel_crtc->pipe); |
6532 | free_work: | |
96b099fd CW |
6533 | kfree(work); |
6534 | ||
6535 | return ret; | |
6b95a207 KH |
6536 | } |
6537 | ||
47f1c6c9 CW |
6538 | static void intel_sanitize_modesetting(struct drm_device *dev, |
6539 | int pipe, int plane) | |
6540 | { | |
6541 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6542 | u32 reg, val; | |
a9dcf84b | 6543 | int i; |
47f1c6c9 | 6544 | |
f47166d2 | 6545 | /* Clear any frame start delays used for debugging left by the BIOS */ |
a9dcf84b DV |
6546 | for_each_pipe(i) { |
6547 | reg = PIPECONF(i); | |
f47166d2 CW |
6548 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
6549 | } | |
6550 | ||
47f1c6c9 CW |
6551 | if (HAS_PCH_SPLIT(dev)) |
6552 | return; | |
6553 | ||
6554 | /* Who knows what state these registers were left in by the BIOS or | |
6555 | * grub? | |
6556 | * | |
6557 | * If we leave the registers in a conflicting state (e.g. with the | |
6558 | * display plane reading from the other pipe than the one we intend | |
6559 | * to use) then when we attempt to teardown the active mode, we will | |
6560 | * not disable the pipes and planes in the correct order -- leaving | |
6561 | * a plane reading from a disabled pipe and possibly leading to | |
6562 | * undefined behaviour. | |
6563 | */ | |
6564 | ||
6565 | reg = DSPCNTR(plane); | |
6566 | val = I915_READ(reg); | |
6567 | ||
6568 | if ((val & DISPLAY_PLANE_ENABLE) == 0) | |
6569 | return; | |
6570 | if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe) | |
6571 | return; | |
6572 | ||
6573 | /* This display plane is active and attached to the other CPU pipe. */ | |
6574 | pipe = !pipe; | |
6575 | ||
6576 | /* Disable the plane and wait for it to stop reading from the pipe. */ | |
b24e7179 JB |
6577 | intel_disable_plane(dev_priv, plane, pipe); |
6578 | intel_disable_pipe(dev_priv, pipe); | |
47f1c6c9 | 6579 | } |
79e53945 | 6580 | |
f6e5b160 CW |
6581 | static void intel_crtc_reset(struct drm_crtc *crtc) |
6582 | { | |
6583 | struct drm_device *dev = crtc->dev; | |
6584 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6585 | ||
6586 | /* Reset flags back to the 'unknown' status so that they | |
6587 | * will be correctly set on the initial modeset. | |
6588 | */ | |
6589 | intel_crtc->dpms_mode = -1; | |
6590 | ||
6591 | /* We need to fix up any BIOS configuration that conflicts with | |
6592 | * our expectations. | |
6593 | */ | |
6594 | intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane); | |
6595 | } | |
6596 | ||
6597 | static struct drm_crtc_helper_funcs intel_helper_funcs = { | |
6598 | .dpms = intel_crtc_dpms, | |
6599 | .mode_fixup = intel_crtc_mode_fixup, | |
6600 | .mode_set = intel_crtc_mode_set, | |
6601 | .mode_set_base = intel_pipe_set_base, | |
6602 | .mode_set_base_atomic = intel_pipe_set_base_atomic, | |
6603 | .load_lut = intel_crtc_load_lut, | |
6604 | .disable = intel_crtc_disable, | |
6605 | }; | |
6606 | ||
6607 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
6608 | .reset = intel_crtc_reset, | |
6609 | .cursor_set = intel_crtc_cursor_set, | |
6610 | .cursor_move = intel_crtc_cursor_move, | |
6611 | .gamma_set = intel_crtc_gamma_set, | |
6612 | .set_config = drm_crtc_helper_set_config, | |
6613 | .destroy = intel_crtc_destroy, | |
6614 | .page_flip = intel_crtc_page_flip, | |
6615 | }; | |
6616 | ||
ee7b9f93 JB |
6617 | static void intel_pch_pll_init(struct drm_device *dev) |
6618 | { | |
6619 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6620 | int i; | |
6621 | ||
6622 | if (dev_priv->num_pch_pll == 0) { | |
6623 | DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n"); | |
6624 | return; | |
6625 | } | |
6626 | ||
6627 | for (i = 0; i < dev_priv->num_pch_pll; i++) { | |
6628 | dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i); | |
6629 | dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i); | |
6630 | dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i); | |
6631 | } | |
6632 | } | |
6633 | ||
b358d0a6 | 6634 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 6635 | { |
22fd0fab | 6636 | drm_i915_private_t *dev_priv = dev->dev_private; |
79e53945 JB |
6637 | struct intel_crtc *intel_crtc; |
6638 | int i; | |
6639 | ||
6640 | intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); | |
6641 | if (intel_crtc == NULL) | |
6642 | return; | |
6643 | ||
6644 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); | |
6645 | ||
6646 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
6647 | for (i = 0; i < 256; i++) { |
6648 | intel_crtc->lut_r[i] = i; | |
6649 | intel_crtc->lut_g[i] = i; | |
6650 | intel_crtc->lut_b[i] = i; | |
6651 | } | |
6652 | ||
80824003 JB |
6653 | /* Swap pipes & planes for FBC on pre-965 */ |
6654 | intel_crtc->pipe = pipe; | |
6655 | intel_crtc->plane = pipe; | |
e2e767ab | 6656 | if (IS_MOBILE(dev) && IS_GEN3(dev)) { |
28c97730 | 6657 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 6658 | intel_crtc->plane = !pipe; |
80824003 JB |
6659 | } |
6660 | ||
22fd0fab JB |
6661 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
6662 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
6663 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
6664 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
6665 | ||
5d1d0cc8 | 6666 | intel_crtc_reset(&intel_crtc->base); |
04dbff52 | 6667 | intel_crtc->active = true; /* force the pipe off on setup_init_config */ |
5a354204 | 6668 | intel_crtc->bpp = 24; /* default for pre-Ironlake */ |
7e7d76c3 JB |
6669 | |
6670 | if (HAS_PCH_SPLIT(dev)) { | |
6671 | intel_helper_funcs.prepare = ironlake_crtc_prepare; | |
6672 | intel_helper_funcs.commit = ironlake_crtc_commit; | |
6673 | } else { | |
6674 | intel_helper_funcs.prepare = i9xx_crtc_prepare; | |
6675 | intel_helper_funcs.commit = i9xx_crtc_commit; | |
6676 | } | |
6677 | ||
79e53945 JB |
6678 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
6679 | ||
652c393a JB |
6680 | intel_crtc->busy = false; |
6681 | ||
6682 | setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer, | |
6683 | (unsigned long)intel_crtc); | |
79e53945 JB |
6684 | } |
6685 | ||
08d7b3d1 | 6686 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 6687 | struct drm_file *file) |
08d7b3d1 | 6688 | { |
08d7b3d1 | 6689 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
c05422d5 DV |
6690 | struct drm_mode_object *drmmode_obj; |
6691 | struct intel_crtc *crtc; | |
08d7b3d1 | 6692 | |
1cff8f6b DV |
6693 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
6694 | return -ENODEV; | |
08d7b3d1 | 6695 | |
c05422d5 DV |
6696 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
6697 | DRM_MODE_OBJECT_CRTC); | |
08d7b3d1 | 6698 | |
c05422d5 | 6699 | if (!drmmode_obj) { |
08d7b3d1 CW |
6700 | DRM_ERROR("no such CRTC id\n"); |
6701 | return -EINVAL; | |
6702 | } | |
6703 | ||
c05422d5 DV |
6704 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
6705 | pipe_from_crtc_id->pipe = crtc->pipe; | |
08d7b3d1 | 6706 | |
c05422d5 | 6707 | return 0; |
08d7b3d1 CW |
6708 | } |
6709 | ||
66a9278e | 6710 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 6711 | { |
66a9278e DV |
6712 | struct drm_device *dev = encoder->base.dev; |
6713 | struct intel_encoder *source_encoder; | |
79e53945 | 6714 | int index_mask = 0; |
79e53945 JB |
6715 | int entry = 0; |
6716 | ||
66a9278e DV |
6717 | list_for_each_entry(source_encoder, |
6718 | &dev->mode_config.encoder_list, base.head) { | |
6719 | ||
6720 | if (encoder == source_encoder) | |
79e53945 | 6721 | index_mask |= (1 << entry); |
66a9278e DV |
6722 | |
6723 | /* Intel hw has only one MUX where enocoders could be cloned. */ | |
6724 | if (encoder->cloneable && source_encoder->cloneable) | |
6725 | index_mask |= (1 << entry); | |
6726 | ||
79e53945 JB |
6727 | entry++; |
6728 | } | |
4ef69c7a | 6729 | |
79e53945 JB |
6730 | return index_mask; |
6731 | } | |
6732 | ||
4d302442 CW |
6733 | static bool has_edp_a(struct drm_device *dev) |
6734 | { | |
6735 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6736 | ||
6737 | if (!IS_MOBILE(dev)) | |
6738 | return false; | |
6739 | ||
6740 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
6741 | return false; | |
6742 | ||
6743 | if (IS_GEN5(dev) && | |
6744 | (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE)) | |
6745 | return false; | |
6746 | ||
6747 | return true; | |
6748 | } | |
6749 | ||
79e53945 JB |
6750 | static void intel_setup_outputs(struct drm_device *dev) |
6751 | { | |
725e30ad | 6752 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 6753 | struct intel_encoder *encoder; |
cb0953d7 | 6754 | bool dpd_is_edp = false; |
f3cfcba6 | 6755 | bool has_lvds; |
79e53945 | 6756 | |
f3cfcba6 | 6757 | has_lvds = intel_lvds_init(dev); |
c5d1b51d CW |
6758 | if (!has_lvds && !HAS_PCH_SPLIT(dev)) { |
6759 | /* disable the panel fitter on everything but LVDS */ | |
6760 | I915_WRITE(PFIT_CONTROL, 0); | |
6761 | } | |
79e53945 | 6762 | |
bad720ff | 6763 | if (HAS_PCH_SPLIT(dev)) { |
cb0953d7 | 6764 | dpd_is_edp = intel_dpd_is_edp(dev); |
30ad48b7 | 6765 | |
4d302442 | 6766 | if (has_edp_a(dev)) |
32f9d658 ZW |
6767 | intel_dp_init(dev, DP_A); |
6768 | ||
cb0953d7 AJ |
6769 | if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) |
6770 | intel_dp_init(dev, PCH_DP_D); | |
6771 | } | |
6772 | ||
6773 | intel_crt_init(dev); | |
6774 | ||
0e72a5b5 ED |
6775 | if (IS_HASWELL(dev)) { |
6776 | int found; | |
6777 | ||
6778 | /* Haswell uses DDI functions to detect digital outputs */ | |
6779 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; | |
6780 | /* DDI A only supports eDP */ | |
6781 | if (found) | |
6782 | intel_ddi_init(dev, PORT_A); | |
6783 | ||
6784 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
6785 | * register */ | |
6786 | found = I915_READ(SFUSE_STRAP); | |
6787 | ||
6788 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
6789 | intel_ddi_init(dev, PORT_B); | |
6790 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
6791 | intel_ddi_init(dev, PORT_C); | |
6792 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
6793 | intel_ddi_init(dev, PORT_D); | |
6794 | } else if (HAS_PCH_SPLIT(dev)) { | |
cb0953d7 AJ |
6795 | int found; |
6796 | ||
30ad48b7 | 6797 | if (I915_READ(HDMIB) & PORT_DETECTED) { |
461ed3ca | 6798 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 6799 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 6800 | if (!found) |
08d644ad | 6801 | intel_hdmi_init(dev, HDMIB, PORT_B); |
5eb08b69 ZW |
6802 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
6803 | intel_dp_init(dev, PCH_DP_B); | |
30ad48b7 ZW |
6804 | } |
6805 | ||
6806 | if (I915_READ(HDMIC) & PORT_DETECTED) | |
08d644ad | 6807 | intel_hdmi_init(dev, HDMIC, PORT_C); |
30ad48b7 | 6808 | |
b708a1d5 | 6809 | if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED) |
08d644ad | 6810 | intel_hdmi_init(dev, HDMID, PORT_D); |
30ad48b7 | 6811 | |
5eb08b69 ZW |
6812 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
6813 | intel_dp_init(dev, PCH_DP_C); | |
6814 | ||
cb0953d7 | 6815 | if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) |
5eb08b69 | 6816 | intel_dp_init(dev, PCH_DP_D); |
4a87d65d JB |
6817 | } else if (IS_VALLEYVIEW(dev)) { |
6818 | int found; | |
6819 | ||
6820 | if (I915_READ(SDVOB) & PORT_DETECTED) { | |
6821 | /* SDVOB multiplex with HDMIB */ | |
6822 | found = intel_sdvo_init(dev, SDVOB, true); | |
6823 | if (!found) | |
08d644ad | 6824 | intel_hdmi_init(dev, SDVOB, PORT_B); |
4a87d65d JB |
6825 | if (!found && (I915_READ(DP_B) & DP_DETECTED)) |
6826 | intel_dp_init(dev, DP_B); | |
6827 | } | |
6828 | ||
6829 | if (I915_READ(SDVOC) & PORT_DETECTED) | |
08d644ad | 6830 | intel_hdmi_init(dev, SDVOC, PORT_C); |
5eb08b69 | 6831 | |
4a87d65d JB |
6832 | /* Shares lanes with HDMI on SDVOC */ |
6833 | if (I915_READ(DP_C) & DP_DETECTED) | |
6834 | intel_dp_init(dev, DP_C); | |
103a196f | 6835 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 6836 | bool found = false; |
7d57382e | 6837 | |
725e30ad | 6838 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 6839 | DRM_DEBUG_KMS("probing SDVOB\n"); |
eef4eacb | 6840 | found = intel_sdvo_init(dev, SDVOB, true); |
b01f2c3a JB |
6841 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
6842 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
08d644ad | 6843 | intel_hdmi_init(dev, SDVOB, PORT_B); |
b01f2c3a | 6844 | } |
27185ae1 | 6845 | |
b01f2c3a JB |
6846 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) { |
6847 | DRM_DEBUG_KMS("probing DP_B\n"); | |
a4fc5ed6 | 6848 | intel_dp_init(dev, DP_B); |
b01f2c3a | 6849 | } |
725e30ad | 6850 | } |
13520b05 KH |
6851 | |
6852 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 6853 | |
b01f2c3a JB |
6854 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
6855 | DRM_DEBUG_KMS("probing SDVOC\n"); | |
eef4eacb | 6856 | found = intel_sdvo_init(dev, SDVOC, false); |
b01f2c3a | 6857 | } |
27185ae1 ML |
6858 | |
6859 | if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) { | |
6860 | ||
b01f2c3a JB |
6861 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
6862 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
08d644ad | 6863 | intel_hdmi_init(dev, SDVOC, PORT_C); |
b01f2c3a JB |
6864 | } |
6865 | if (SUPPORTS_INTEGRATED_DP(dev)) { | |
6866 | DRM_DEBUG_KMS("probing DP_C\n"); | |
a4fc5ed6 | 6867 | intel_dp_init(dev, DP_C); |
b01f2c3a | 6868 | } |
725e30ad | 6869 | } |
27185ae1 | 6870 | |
b01f2c3a JB |
6871 | if (SUPPORTS_INTEGRATED_DP(dev) && |
6872 | (I915_READ(DP_D) & DP_DETECTED)) { | |
6873 | DRM_DEBUG_KMS("probing DP_D\n"); | |
a4fc5ed6 | 6874 | intel_dp_init(dev, DP_D); |
b01f2c3a | 6875 | } |
bad720ff | 6876 | } else if (IS_GEN2(dev)) |
79e53945 JB |
6877 | intel_dvo_init(dev); |
6878 | ||
103a196f | 6879 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
6880 | intel_tv_init(dev); |
6881 | ||
4ef69c7a CW |
6882 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
6883 | encoder->base.possible_crtcs = encoder->crtc_mask; | |
6884 | encoder->base.possible_clones = | |
66a9278e | 6885 | intel_encoder_clones(encoder); |
79e53945 | 6886 | } |
47356eb6 | 6887 | |
2c7111db CW |
6888 | /* disable all the possible outputs/crtcs before entering KMS mode */ |
6889 | drm_helper_disable_unused_functions(dev); | |
9fb526db | 6890 | |
40579abe | 6891 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
9fb526db | 6892 | ironlake_init_pch_refclk(dev); |
79e53945 JB |
6893 | } |
6894 | ||
6895 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
6896 | { | |
6897 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 JB |
6898 | |
6899 | drm_framebuffer_cleanup(fb); | |
05394f39 | 6900 | drm_gem_object_unreference_unlocked(&intel_fb->obj->base); |
79e53945 JB |
6901 | |
6902 | kfree(intel_fb); | |
6903 | } | |
6904 | ||
6905 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 6906 | struct drm_file *file, |
79e53945 JB |
6907 | unsigned int *handle) |
6908 | { | |
6909 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 6910 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 6911 | |
05394f39 | 6912 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
6913 | } |
6914 | ||
6915 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
6916 | .destroy = intel_user_framebuffer_destroy, | |
6917 | .create_handle = intel_user_framebuffer_create_handle, | |
6918 | }; | |
6919 | ||
38651674 DA |
6920 | int intel_framebuffer_init(struct drm_device *dev, |
6921 | struct intel_framebuffer *intel_fb, | |
308e5bcb | 6922 | struct drm_mode_fb_cmd2 *mode_cmd, |
05394f39 | 6923 | struct drm_i915_gem_object *obj) |
79e53945 | 6924 | { |
79e53945 JB |
6925 | int ret; |
6926 | ||
05394f39 | 6927 | if (obj->tiling_mode == I915_TILING_Y) |
57cd6508 CW |
6928 | return -EINVAL; |
6929 | ||
308e5bcb | 6930 | if (mode_cmd->pitches[0] & 63) |
57cd6508 CW |
6931 | return -EINVAL; |
6932 | ||
308e5bcb | 6933 | switch (mode_cmd->pixel_format) { |
04b3924d VS |
6934 | case DRM_FORMAT_RGB332: |
6935 | case DRM_FORMAT_RGB565: | |
6936 | case DRM_FORMAT_XRGB8888: | |
b250da79 | 6937 | case DRM_FORMAT_XBGR8888: |
04b3924d VS |
6938 | case DRM_FORMAT_ARGB8888: |
6939 | case DRM_FORMAT_XRGB2101010: | |
6940 | case DRM_FORMAT_ARGB2101010: | |
308e5bcb | 6941 | /* RGB formats are common across chipsets */ |
b5626747 | 6942 | break; |
04b3924d VS |
6943 | case DRM_FORMAT_YUYV: |
6944 | case DRM_FORMAT_UYVY: | |
6945 | case DRM_FORMAT_YVYU: | |
6946 | case DRM_FORMAT_VYUY: | |
57cd6508 CW |
6947 | break; |
6948 | default: | |
aca25848 ED |
6949 | DRM_DEBUG_KMS("unsupported pixel format %u\n", |
6950 | mode_cmd->pixel_format); | |
57cd6508 CW |
6951 | return -EINVAL; |
6952 | } | |
6953 | ||
79e53945 JB |
6954 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
6955 | if (ret) { | |
6956 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
6957 | return ret; | |
6958 | } | |
6959 | ||
6960 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); | |
79e53945 | 6961 | intel_fb->obj = obj; |
79e53945 JB |
6962 | return 0; |
6963 | } | |
6964 | ||
79e53945 JB |
6965 | static struct drm_framebuffer * |
6966 | intel_user_framebuffer_create(struct drm_device *dev, | |
6967 | struct drm_file *filp, | |
308e5bcb | 6968 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 6969 | { |
05394f39 | 6970 | struct drm_i915_gem_object *obj; |
79e53945 | 6971 | |
308e5bcb JB |
6972 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
6973 | mode_cmd->handles[0])); | |
c8725226 | 6974 | if (&obj->base == NULL) |
cce13ff7 | 6975 | return ERR_PTR(-ENOENT); |
79e53945 | 6976 | |
d2dff872 | 6977 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
6978 | } |
6979 | ||
79e53945 | 6980 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 6981 | .fb_create = intel_user_framebuffer_create, |
eb1f8e4f | 6982 | .output_poll_changed = intel_fb_output_poll_changed, |
79e53945 JB |
6983 | }; |
6984 | ||
e70236a8 JB |
6985 | /* Set up chip specific display functions */ |
6986 | static void intel_init_display(struct drm_device *dev) | |
6987 | { | |
6988 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6989 | ||
6990 | /* We always want a DPMS function */ | |
f564048e | 6991 | if (HAS_PCH_SPLIT(dev)) { |
f2b115e6 | 6992 | dev_priv->display.dpms = ironlake_crtc_dpms; |
f564048e | 6993 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
ee7b9f93 | 6994 | dev_priv->display.off = ironlake_crtc_off; |
17638cd6 | 6995 | dev_priv->display.update_plane = ironlake_update_plane; |
f564048e | 6996 | } else { |
e70236a8 | 6997 | dev_priv->display.dpms = i9xx_crtc_dpms; |
f564048e | 6998 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
ee7b9f93 | 6999 | dev_priv->display.off = i9xx_crtc_off; |
17638cd6 | 7000 | dev_priv->display.update_plane = i9xx_update_plane; |
f564048e | 7001 | } |
e70236a8 | 7002 | |
e70236a8 | 7003 | /* Returns the core display clock speed */ |
25eb05fc JB |
7004 | if (IS_VALLEYVIEW(dev)) |
7005 | dev_priv->display.get_display_clock_speed = | |
7006 | valleyview_get_display_clock_speed; | |
7007 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) | |
e70236a8 JB |
7008 | dev_priv->display.get_display_clock_speed = |
7009 | i945_get_display_clock_speed; | |
7010 | else if (IS_I915G(dev)) | |
7011 | dev_priv->display.get_display_clock_speed = | |
7012 | i915_get_display_clock_speed; | |
f2b115e6 | 7013 | else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev)) |
e70236a8 JB |
7014 | dev_priv->display.get_display_clock_speed = |
7015 | i9xx_misc_get_display_clock_speed; | |
7016 | else if (IS_I915GM(dev)) | |
7017 | dev_priv->display.get_display_clock_speed = | |
7018 | i915gm_get_display_clock_speed; | |
7019 | else if (IS_I865G(dev)) | |
7020 | dev_priv->display.get_display_clock_speed = | |
7021 | i865_get_display_clock_speed; | |
f0f8a9ce | 7022 | else if (IS_I85X(dev)) |
e70236a8 JB |
7023 | dev_priv->display.get_display_clock_speed = |
7024 | i855_get_display_clock_speed; | |
7025 | else /* 852, 830 */ | |
7026 | dev_priv->display.get_display_clock_speed = | |
7027 | i830_get_display_clock_speed; | |
7028 | ||
7f8a8569 | 7029 | if (HAS_PCH_SPLIT(dev)) { |
f00a3ddf | 7030 | if (IS_GEN5(dev)) { |
674cf967 | 7031 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
e0dac65e | 7032 | dev_priv->display.write_eld = ironlake_write_eld; |
1398261a | 7033 | } else if (IS_GEN6(dev)) { |
674cf967 | 7034 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
e0dac65e | 7035 | dev_priv->display.write_eld = ironlake_write_eld; |
357555c0 JB |
7036 | } else if (IS_IVYBRIDGE(dev)) { |
7037 | /* FIXME: detect B0+ stepping and use auto training */ | |
7038 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
e0dac65e | 7039 | dev_priv->display.write_eld = ironlake_write_eld; |
c82e4d26 ED |
7040 | } else if (IS_HASWELL(dev)) { |
7041 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; | |
4abb3c8c | 7042 | dev_priv->display.write_eld = ironlake_write_eld; |
7f8a8569 ZW |
7043 | } else |
7044 | dev_priv->display.update_wm = NULL; | |
6067aaea | 7045 | } else if (IS_G4X(dev)) { |
e0dac65e | 7046 | dev_priv->display.write_eld = g4x_write_eld; |
e70236a8 | 7047 | } |
8c9f3aaf JB |
7048 | |
7049 | /* Default just returns -ENODEV to indicate unsupported */ | |
7050 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
7051 | ||
7052 | switch (INTEL_INFO(dev)->gen) { | |
7053 | case 2: | |
7054 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
7055 | break; | |
7056 | ||
7057 | case 3: | |
7058 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
7059 | break; | |
7060 | ||
7061 | case 4: | |
7062 | case 5: | |
7063 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
7064 | break; | |
7065 | ||
7066 | case 6: | |
7067 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
7068 | break; | |
7c9017e5 JB |
7069 | case 7: |
7070 | dev_priv->display.queue_flip = intel_gen7_queue_flip; | |
7071 | break; | |
8c9f3aaf | 7072 | } |
e70236a8 JB |
7073 | } |
7074 | ||
b690e96c JB |
7075 | /* |
7076 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
7077 | * resume, or other times. This quirk makes sure that's the case for | |
7078 | * affected systems. | |
7079 | */ | |
0206e353 | 7080 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
7081 | { |
7082 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7083 | ||
7084 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 7085 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
7086 | } |
7087 | ||
435793df KP |
7088 | /* |
7089 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
7090 | */ | |
7091 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
7092 | { | |
7093 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7094 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 7095 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
7096 | } |
7097 | ||
4dca20ef | 7098 | /* |
5a15ab5b CE |
7099 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
7100 | * brightness value | |
4dca20ef CE |
7101 | */ |
7102 | static void quirk_invert_brightness(struct drm_device *dev) | |
7103 | { | |
7104 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7105 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 7106 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
7107 | } |
7108 | ||
b690e96c JB |
7109 | struct intel_quirk { |
7110 | int device; | |
7111 | int subsystem_vendor; | |
7112 | int subsystem_device; | |
7113 | void (*hook)(struct drm_device *dev); | |
7114 | }; | |
7115 | ||
c43b5634 | 7116 | static struct intel_quirk intel_quirks[] = { |
b690e96c | 7117 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
0206e353 | 7118 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c JB |
7119 | |
7120 | /* Thinkpad R31 needs pipe A force quirk */ | |
7121 | { 0x3577, 0x1014, 0x0505, quirk_pipea_force }, | |
7122 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ | |
7123 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
7124 | ||
7125 | /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */ | |
7126 | { 0x3577, 0x1014, 0x0513, quirk_pipea_force }, | |
7127 | /* ThinkPad X40 needs pipe A force quirk */ | |
7128 | ||
7129 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ | |
7130 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
7131 | ||
7132 | /* 855 & before need to leave pipe A & dpll A up */ | |
7133 | { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
7134 | { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
435793df KP |
7135 | |
7136 | /* Lenovo U160 cannot use SSC on LVDS */ | |
7137 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
7138 | |
7139 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
7140 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b CE |
7141 | |
7142 | /* Acer Aspire 5734Z must invert backlight brightness */ | |
7143 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
b690e96c JB |
7144 | }; |
7145 | ||
7146 | static void intel_init_quirks(struct drm_device *dev) | |
7147 | { | |
7148 | struct pci_dev *d = dev->pdev; | |
7149 | int i; | |
7150 | ||
7151 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
7152 | struct intel_quirk *q = &intel_quirks[i]; | |
7153 | ||
7154 | if (d->device == q->device && | |
7155 | (d->subsystem_vendor == q->subsystem_vendor || | |
7156 | q->subsystem_vendor == PCI_ANY_ID) && | |
7157 | (d->subsystem_device == q->subsystem_device || | |
7158 | q->subsystem_device == PCI_ANY_ID)) | |
7159 | q->hook(dev); | |
7160 | } | |
7161 | } | |
7162 | ||
9cce37f4 JB |
7163 | /* Disable the VGA plane that we never use */ |
7164 | static void i915_disable_vga(struct drm_device *dev) | |
7165 | { | |
7166 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7167 | u8 sr1; | |
7168 | u32 vga_reg; | |
7169 | ||
7170 | if (HAS_PCH_SPLIT(dev)) | |
7171 | vga_reg = CPU_VGACNTRL; | |
7172 | else | |
7173 | vga_reg = VGACNTRL; | |
7174 | ||
7175 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); | |
3fdcf431 | 7176 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
7177 | sr1 = inb(VGA_SR_DATA); |
7178 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
7179 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
7180 | udelay(300); | |
7181 | ||
7182 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); | |
7183 | POSTING_READ(vga_reg); | |
7184 | } | |
7185 | ||
f82cfb6b JB |
7186 | static void ivb_pch_pwm_override(struct drm_device *dev) |
7187 | { | |
7188 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7189 | ||
7190 | /* | |
7191 | * IVB has CPU eDP backlight regs too, set things up to let the | |
7192 | * PCH regs control the backlight | |
7193 | */ | |
7cf41601 | 7194 | I915_WRITE(BLC_PWM_CPU_CTL2, BLM_PWM_ENABLE); |
f82cfb6b | 7195 | I915_WRITE(BLC_PWM_CPU_CTL, 0); |
7cf41601 | 7196 | I915_WRITE(BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE | BLM_PCH_OVERRIDE_ENABLE); |
f82cfb6b JB |
7197 | } |
7198 | ||
f817586c DV |
7199 | void intel_modeset_init_hw(struct drm_device *dev) |
7200 | { | |
0232e927 ED |
7201 | /* We attempt to init the necessary power wells early in the initialization |
7202 | * time, so the subsystems that expect power to be enabled can work. | |
7203 | */ | |
7204 | intel_init_power_wells(dev); | |
7205 | ||
a8f78b58 ED |
7206 | intel_prepare_ddi(dev); |
7207 | ||
f817586c DV |
7208 | intel_init_clock_gating(dev); |
7209 | ||
79f5b2c7 | 7210 | mutex_lock(&dev->struct_mutex); |
8090c6b9 | 7211 | intel_enable_gt_powersave(dev); |
79f5b2c7 | 7212 | mutex_unlock(&dev->struct_mutex); |
f82cfb6b JB |
7213 | |
7214 | if (IS_IVYBRIDGE(dev)) | |
7215 | ivb_pch_pwm_override(dev); | |
f817586c DV |
7216 | } |
7217 | ||
79e53945 JB |
7218 | void intel_modeset_init(struct drm_device *dev) |
7219 | { | |
652c393a | 7220 | struct drm_i915_private *dev_priv = dev->dev_private; |
b840d907 | 7221 | int i, ret; |
79e53945 JB |
7222 | |
7223 | drm_mode_config_init(dev); | |
7224 | ||
7225 | dev->mode_config.min_width = 0; | |
7226 | dev->mode_config.min_height = 0; | |
7227 | ||
019d96cb DA |
7228 | dev->mode_config.preferred_depth = 24; |
7229 | dev->mode_config.prefer_shadow = 1; | |
7230 | ||
e6ecefaa | 7231 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 7232 | |
b690e96c JB |
7233 | intel_init_quirks(dev); |
7234 | ||
1fa61106 ED |
7235 | intel_init_pm(dev); |
7236 | ||
e70236a8 JB |
7237 | intel_init_display(dev); |
7238 | ||
a6c45cf0 CW |
7239 | if (IS_GEN2(dev)) { |
7240 | dev->mode_config.max_width = 2048; | |
7241 | dev->mode_config.max_height = 2048; | |
7242 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
7243 | dev->mode_config.max_width = 4096; |
7244 | dev->mode_config.max_height = 4096; | |
79e53945 | 7245 | } else { |
a6c45cf0 CW |
7246 | dev->mode_config.max_width = 8192; |
7247 | dev->mode_config.max_height = 8192; | |
79e53945 | 7248 | } |
dd2757f8 | 7249 | dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr; |
79e53945 | 7250 | |
28c97730 | 7251 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
a3524f1b | 7252 | dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : ""); |
79e53945 | 7253 | |
a3524f1b | 7254 | for (i = 0; i < dev_priv->num_pipe; i++) { |
79e53945 | 7255 | intel_crtc_init(dev, i); |
00c2064b JB |
7256 | ret = intel_plane_init(dev, i); |
7257 | if (ret) | |
7258 | DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret); | |
79e53945 JB |
7259 | } |
7260 | ||
ee7b9f93 JB |
7261 | intel_pch_pll_init(dev); |
7262 | ||
9cce37f4 JB |
7263 | /* Just disable it once at startup */ |
7264 | i915_disable_vga(dev); | |
79e53945 | 7265 | intel_setup_outputs(dev); |
652c393a | 7266 | |
652c393a JB |
7267 | INIT_WORK(&dev_priv->idle_work, intel_idle_update); |
7268 | setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer, | |
7269 | (unsigned long)dev); | |
2c7111db CW |
7270 | } |
7271 | ||
7272 | void intel_modeset_gem_init(struct drm_device *dev) | |
7273 | { | |
1833b134 | 7274 | intel_modeset_init_hw(dev); |
02e792fb DV |
7275 | |
7276 | intel_setup_overlay(dev); | |
79e53945 JB |
7277 | } |
7278 | ||
7279 | void intel_modeset_cleanup(struct drm_device *dev) | |
7280 | { | |
652c393a JB |
7281 | struct drm_i915_private *dev_priv = dev->dev_private; |
7282 | struct drm_crtc *crtc; | |
7283 | struct intel_crtc *intel_crtc; | |
7284 | ||
f87ea761 | 7285 | drm_kms_helper_poll_fini(dev); |
652c393a JB |
7286 | mutex_lock(&dev->struct_mutex); |
7287 | ||
723bfd70 JB |
7288 | intel_unregister_dsm_handler(); |
7289 | ||
7290 | ||
652c393a JB |
7291 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
7292 | /* Skip inactive CRTCs */ | |
7293 | if (!crtc->fb) | |
7294 | continue; | |
7295 | ||
7296 | intel_crtc = to_intel_crtc(crtc); | |
3dec0095 | 7297 | intel_increase_pllclock(crtc); |
652c393a JB |
7298 | } |
7299 | ||
973d04f9 | 7300 | intel_disable_fbc(dev); |
e70236a8 | 7301 | |
8090c6b9 | 7302 | intel_disable_gt_powersave(dev); |
0cdab21f | 7303 | |
930ebb46 DV |
7304 | ironlake_teardown_rc6(dev); |
7305 | ||
57f350b6 JB |
7306 | if (IS_VALLEYVIEW(dev)) |
7307 | vlv_init_dpio(dev); | |
7308 | ||
69341a5e KH |
7309 | mutex_unlock(&dev->struct_mutex); |
7310 | ||
6c0d9350 DV |
7311 | /* Disable the irq before mode object teardown, for the irq might |
7312 | * enqueue unpin/hotplug work. */ | |
7313 | drm_irq_uninstall(dev); | |
7314 | cancel_work_sync(&dev_priv->hotplug_work); | |
6fdd4d98 | 7315 | cancel_work_sync(&dev_priv->rps_work); |
6c0d9350 | 7316 | |
1630fe75 CW |
7317 | /* flush any delayed tasks or pending work */ |
7318 | flush_scheduled_work(); | |
7319 | ||
3dec0095 DV |
7320 | /* Shut off idle work before the crtcs get freed. */ |
7321 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
7322 | intel_crtc = to_intel_crtc(crtc); | |
7323 | del_timer_sync(&intel_crtc->idle_timer); | |
7324 | } | |
7325 | del_timer_sync(&dev_priv->idle_timer); | |
7326 | cancel_work_sync(&dev_priv->idle_work); | |
7327 | ||
79e53945 JB |
7328 | drm_mode_config_cleanup(dev); |
7329 | } | |
7330 | ||
f1c79df3 ZW |
7331 | /* |
7332 | * Return which encoder is currently attached for connector. | |
7333 | */ | |
df0e9248 | 7334 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 7335 | { |
df0e9248 CW |
7336 | return &intel_attached_encoder(connector)->base; |
7337 | } | |
f1c79df3 | 7338 | |
df0e9248 CW |
7339 | void intel_connector_attach_encoder(struct intel_connector *connector, |
7340 | struct intel_encoder *encoder) | |
7341 | { | |
7342 | connector->encoder = encoder; | |
7343 | drm_mode_connector_attach_encoder(&connector->base, | |
7344 | &encoder->base); | |
79e53945 | 7345 | } |
28d52043 DA |
7346 | |
7347 | /* | |
7348 | * set vga decode state - true == enable VGA decode | |
7349 | */ | |
7350 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
7351 | { | |
7352 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7353 | u16 gmch_ctrl; | |
7354 | ||
7355 | pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl); | |
7356 | if (state) | |
7357 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
7358 | else | |
7359 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
7360 | pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl); | |
7361 | return 0; | |
7362 | } | |
c4a1d9e4 CW |
7363 | |
7364 | #ifdef CONFIG_DEBUG_FS | |
7365 | #include <linux/seq_file.h> | |
7366 | ||
7367 | struct intel_display_error_state { | |
7368 | struct intel_cursor_error_state { | |
7369 | u32 control; | |
7370 | u32 position; | |
7371 | u32 base; | |
7372 | u32 size; | |
7373 | } cursor[2]; | |
7374 | ||
7375 | struct intel_pipe_error_state { | |
7376 | u32 conf; | |
7377 | u32 source; | |
7378 | ||
7379 | u32 htotal; | |
7380 | u32 hblank; | |
7381 | u32 hsync; | |
7382 | u32 vtotal; | |
7383 | u32 vblank; | |
7384 | u32 vsync; | |
7385 | } pipe[2]; | |
7386 | ||
7387 | struct intel_plane_error_state { | |
7388 | u32 control; | |
7389 | u32 stride; | |
7390 | u32 size; | |
7391 | u32 pos; | |
7392 | u32 addr; | |
7393 | u32 surface; | |
7394 | u32 tile_offset; | |
7395 | } plane[2]; | |
7396 | }; | |
7397 | ||
7398 | struct intel_display_error_state * | |
7399 | intel_display_capture_error_state(struct drm_device *dev) | |
7400 | { | |
0206e353 | 7401 | drm_i915_private_t *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
7402 | struct intel_display_error_state *error; |
7403 | int i; | |
7404 | ||
7405 | error = kmalloc(sizeof(*error), GFP_ATOMIC); | |
7406 | if (error == NULL) | |
7407 | return NULL; | |
7408 | ||
7409 | for (i = 0; i < 2; i++) { | |
7410 | error->cursor[i].control = I915_READ(CURCNTR(i)); | |
7411 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
7412 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
7413 | ||
7414 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
7415 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
7416 | error->plane[i].size = I915_READ(DSPSIZE(i)); | |
0206e353 | 7417 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
c4a1d9e4 CW |
7418 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
7419 | if (INTEL_INFO(dev)->gen >= 4) { | |
7420 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
7421 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
7422 | } | |
7423 | ||
7424 | error->pipe[i].conf = I915_READ(PIPECONF(i)); | |
7425 | error->pipe[i].source = I915_READ(PIPESRC(i)); | |
7426 | error->pipe[i].htotal = I915_READ(HTOTAL(i)); | |
7427 | error->pipe[i].hblank = I915_READ(HBLANK(i)); | |
7428 | error->pipe[i].hsync = I915_READ(HSYNC(i)); | |
7429 | error->pipe[i].vtotal = I915_READ(VTOTAL(i)); | |
7430 | error->pipe[i].vblank = I915_READ(VBLANK(i)); | |
7431 | error->pipe[i].vsync = I915_READ(VSYNC(i)); | |
7432 | } | |
7433 | ||
7434 | return error; | |
7435 | } | |
7436 | ||
7437 | void | |
7438 | intel_display_print_error_state(struct seq_file *m, | |
7439 | struct drm_device *dev, | |
7440 | struct intel_display_error_state *error) | |
7441 | { | |
7442 | int i; | |
7443 | ||
7444 | for (i = 0; i < 2; i++) { | |
7445 | seq_printf(m, "Pipe [%d]:\n", i); | |
7446 | seq_printf(m, " CONF: %08x\n", error->pipe[i].conf); | |
7447 | seq_printf(m, " SRC: %08x\n", error->pipe[i].source); | |
7448 | seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal); | |
7449 | seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank); | |
7450 | seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync); | |
7451 | seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal); | |
7452 | seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank); | |
7453 | seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync); | |
7454 | ||
7455 | seq_printf(m, "Plane [%d]:\n", i); | |
7456 | seq_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
7457 | seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
7458 | seq_printf(m, " SIZE: %08x\n", error->plane[i].size); | |
7459 | seq_printf(m, " POS: %08x\n", error->plane[i].pos); | |
7460 | seq_printf(m, " ADDR: %08x\n", error->plane[i].addr); | |
7461 | if (INTEL_INFO(dev)->gen >= 4) { | |
7462 | seq_printf(m, " SURF: %08x\n", error->plane[i].surface); | |
7463 | seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
7464 | } | |
7465 | ||
7466 | seq_printf(m, "Cursor [%d]:\n", i); | |
7467 | seq_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
7468 | seq_printf(m, " POS: %08x\n", error->cursor[i].position); | |
7469 | seq_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
7470 | } | |
7471 | } | |
7472 | #endif |