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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
760285e7 DH |
40 | #include <drm/drm_dp_helper.h> |
41 | #include <drm/drm_crtc_helper.h> | |
c0f372b3 | 42 | #include <linux/dma_remapping.h> |
79e53945 | 43 | |
3dec0095 | 44 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
6b383a7f | 45 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 46 | |
f1f644dc JB |
47 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
48 | struct intel_crtc_config *pipe_config); | |
18442d08 VS |
49 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
50 | struct intel_crtc_config *pipe_config); | |
f1f644dc | 51 | |
e7457a9a DL |
52 | static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
53 | int x, int y, struct drm_framebuffer *old_fb); | |
54 | ||
55 | ||
79e53945 | 56 | typedef struct { |
0206e353 | 57 | int min, max; |
79e53945 JB |
58 | } intel_range_t; |
59 | ||
60 | typedef struct { | |
0206e353 AJ |
61 | int dot_limit; |
62 | int p2_slow, p2_fast; | |
79e53945 JB |
63 | } intel_p2_t; |
64 | ||
d4906093 ML |
65 | typedef struct intel_limit intel_limit_t; |
66 | struct intel_limit { | |
0206e353 AJ |
67 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
68 | intel_p2_t p2; | |
d4906093 | 69 | }; |
79e53945 | 70 | |
d2acd215 DV |
71 | int |
72 | intel_pch_rawclk(struct drm_device *dev) | |
73 | { | |
74 | struct drm_i915_private *dev_priv = dev->dev_private; | |
75 | ||
76 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
77 | ||
78 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
79 | } | |
80 | ||
021357ac CW |
81 | static inline u32 /* units of 100MHz */ |
82 | intel_fdi_link_freq(struct drm_device *dev) | |
83 | { | |
8b99e68c CW |
84 | if (IS_GEN5(dev)) { |
85 | struct drm_i915_private *dev_priv = dev->dev_private; | |
86 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
87 | } else | |
88 | return 27; | |
021357ac CW |
89 | } |
90 | ||
5d536e28 | 91 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 92 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 93 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 94 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
95 | .m = { .min = 96, .max = 140 }, |
96 | .m1 = { .min = 18, .max = 26 }, | |
97 | .m2 = { .min = 6, .max = 16 }, | |
98 | .p = { .min = 4, .max = 128 }, | |
99 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
100 | .p2 = { .dot_limit = 165000, |
101 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
102 | }; |
103 | ||
5d536e28 DV |
104 | static const intel_limit_t intel_limits_i8xx_dvo = { |
105 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 106 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 107 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
108 | .m = { .min = 96, .max = 140 }, |
109 | .m1 = { .min = 18, .max = 26 }, | |
110 | .m2 = { .min = 6, .max = 16 }, | |
111 | .p = { .min = 4, .max = 128 }, | |
112 | .p1 = { .min = 2, .max = 33 }, | |
113 | .p2 = { .dot_limit = 165000, | |
114 | .p2_slow = 4, .p2_fast = 4 }, | |
115 | }; | |
116 | ||
e4b36699 | 117 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 118 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 119 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 120 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
121 | .m = { .min = 96, .max = 140 }, |
122 | .m1 = { .min = 18, .max = 26 }, | |
123 | .m2 = { .min = 6, .max = 16 }, | |
124 | .p = { .min = 4, .max = 128 }, | |
125 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
126 | .p2 = { .dot_limit = 165000, |
127 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 128 | }; |
273e27ca | 129 | |
e4b36699 | 130 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
131 | .dot = { .min = 20000, .max = 400000 }, |
132 | .vco = { .min = 1400000, .max = 2800000 }, | |
133 | .n = { .min = 1, .max = 6 }, | |
134 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
135 | .m1 = { .min = 8, .max = 18 }, |
136 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
137 | .p = { .min = 5, .max = 80 }, |
138 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
139 | .p2 = { .dot_limit = 200000, |
140 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
141 | }; |
142 | ||
143 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
144 | .dot = { .min = 20000, .max = 400000 }, |
145 | .vco = { .min = 1400000, .max = 2800000 }, | |
146 | .n = { .min = 1, .max = 6 }, | |
147 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
148 | .m1 = { .min = 8, .max = 18 }, |
149 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
150 | .p = { .min = 7, .max = 98 }, |
151 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
152 | .p2 = { .dot_limit = 112000, |
153 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
154 | }; |
155 | ||
273e27ca | 156 | |
e4b36699 | 157 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
158 | .dot = { .min = 25000, .max = 270000 }, |
159 | .vco = { .min = 1750000, .max = 3500000}, | |
160 | .n = { .min = 1, .max = 4 }, | |
161 | .m = { .min = 104, .max = 138 }, | |
162 | .m1 = { .min = 17, .max = 23 }, | |
163 | .m2 = { .min = 5, .max = 11 }, | |
164 | .p = { .min = 10, .max = 30 }, | |
165 | .p1 = { .min = 1, .max = 3}, | |
166 | .p2 = { .dot_limit = 270000, | |
167 | .p2_slow = 10, | |
168 | .p2_fast = 10 | |
044c7c41 | 169 | }, |
e4b36699 KP |
170 | }; |
171 | ||
172 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
173 | .dot = { .min = 22000, .max = 400000 }, |
174 | .vco = { .min = 1750000, .max = 3500000}, | |
175 | .n = { .min = 1, .max = 4 }, | |
176 | .m = { .min = 104, .max = 138 }, | |
177 | .m1 = { .min = 16, .max = 23 }, | |
178 | .m2 = { .min = 5, .max = 11 }, | |
179 | .p = { .min = 5, .max = 80 }, | |
180 | .p1 = { .min = 1, .max = 8}, | |
181 | .p2 = { .dot_limit = 165000, | |
182 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
183 | }; |
184 | ||
185 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
186 | .dot = { .min = 20000, .max = 115000 }, |
187 | .vco = { .min = 1750000, .max = 3500000 }, | |
188 | .n = { .min = 1, .max = 3 }, | |
189 | .m = { .min = 104, .max = 138 }, | |
190 | .m1 = { .min = 17, .max = 23 }, | |
191 | .m2 = { .min = 5, .max = 11 }, | |
192 | .p = { .min = 28, .max = 112 }, | |
193 | .p1 = { .min = 2, .max = 8 }, | |
194 | .p2 = { .dot_limit = 0, | |
195 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 196 | }, |
e4b36699 KP |
197 | }; |
198 | ||
199 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
200 | .dot = { .min = 80000, .max = 224000 }, |
201 | .vco = { .min = 1750000, .max = 3500000 }, | |
202 | .n = { .min = 1, .max = 3 }, | |
203 | .m = { .min = 104, .max = 138 }, | |
204 | .m1 = { .min = 17, .max = 23 }, | |
205 | .m2 = { .min = 5, .max = 11 }, | |
206 | .p = { .min = 14, .max = 42 }, | |
207 | .p1 = { .min = 2, .max = 6 }, | |
208 | .p2 = { .dot_limit = 0, | |
209 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 210 | }, |
e4b36699 KP |
211 | }; |
212 | ||
f2b115e6 | 213 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
214 | .dot = { .min = 20000, .max = 400000}, |
215 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 216 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
217 | .n = { .min = 3, .max = 6 }, |
218 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 219 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
220 | .m1 = { .min = 0, .max = 0 }, |
221 | .m2 = { .min = 0, .max = 254 }, | |
222 | .p = { .min = 5, .max = 80 }, | |
223 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
224 | .p2 = { .dot_limit = 200000, |
225 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
226 | }; |
227 | ||
f2b115e6 | 228 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
229 | .dot = { .min = 20000, .max = 400000 }, |
230 | .vco = { .min = 1700000, .max = 3500000 }, | |
231 | .n = { .min = 3, .max = 6 }, | |
232 | .m = { .min = 2, .max = 256 }, | |
233 | .m1 = { .min = 0, .max = 0 }, | |
234 | .m2 = { .min = 0, .max = 254 }, | |
235 | .p = { .min = 7, .max = 112 }, | |
236 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
237 | .p2 = { .dot_limit = 112000, |
238 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
239 | }; |
240 | ||
273e27ca EA |
241 | /* Ironlake / Sandybridge |
242 | * | |
243 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
244 | * the range value for them is (actual_value - 2). | |
245 | */ | |
b91ad0ec | 246 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
247 | .dot = { .min = 25000, .max = 350000 }, |
248 | .vco = { .min = 1760000, .max = 3510000 }, | |
249 | .n = { .min = 1, .max = 5 }, | |
250 | .m = { .min = 79, .max = 127 }, | |
251 | .m1 = { .min = 12, .max = 22 }, | |
252 | .m2 = { .min = 5, .max = 9 }, | |
253 | .p = { .min = 5, .max = 80 }, | |
254 | .p1 = { .min = 1, .max = 8 }, | |
255 | .p2 = { .dot_limit = 225000, | |
256 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
257 | }; |
258 | ||
b91ad0ec | 259 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
260 | .dot = { .min = 25000, .max = 350000 }, |
261 | .vco = { .min = 1760000, .max = 3510000 }, | |
262 | .n = { .min = 1, .max = 3 }, | |
263 | .m = { .min = 79, .max = 118 }, | |
264 | .m1 = { .min = 12, .max = 22 }, | |
265 | .m2 = { .min = 5, .max = 9 }, | |
266 | .p = { .min = 28, .max = 112 }, | |
267 | .p1 = { .min = 2, .max = 8 }, | |
268 | .p2 = { .dot_limit = 225000, | |
269 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
270 | }; |
271 | ||
272 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
273 | .dot = { .min = 25000, .max = 350000 }, |
274 | .vco = { .min = 1760000, .max = 3510000 }, | |
275 | .n = { .min = 1, .max = 3 }, | |
276 | .m = { .min = 79, .max = 127 }, | |
277 | .m1 = { .min = 12, .max = 22 }, | |
278 | .m2 = { .min = 5, .max = 9 }, | |
279 | .p = { .min = 14, .max = 56 }, | |
280 | .p1 = { .min = 2, .max = 8 }, | |
281 | .p2 = { .dot_limit = 225000, | |
282 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
283 | }; |
284 | ||
273e27ca | 285 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 286 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
287 | .dot = { .min = 25000, .max = 350000 }, |
288 | .vco = { .min = 1760000, .max = 3510000 }, | |
289 | .n = { .min = 1, .max = 2 }, | |
290 | .m = { .min = 79, .max = 126 }, | |
291 | .m1 = { .min = 12, .max = 22 }, | |
292 | .m2 = { .min = 5, .max = 9 }, | |
293 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 294 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
295 | .p2 = { .dot_limit = 225000, |
296 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
297 | }; |
298 | ||
299 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
300 | .dot = { .min = 25000, .max = 350000 }, |
301 | .vco = { .min = 1760000, .max = 3510000 }, | |
302 | .n = { .min = 1, .max = 3 }, | |
303 | .m = { .min = 79, .max = 126 }, | |
304 | .m1 = { .min = 12, .max = 22 }, | |
305 | .m2 = { .min = 5, .max = 9 }, | |
306 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 307 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
308 | .p2 = { .dot_limit = 225000, |
309 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
310 | }; |
311 | ||
dc730512 | 312 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
313 | /* |
314 | * These are the data rate limits (measured in fast clocks) | |
315 | * since those are the strictest limits we have. The fast | |
316 | * clock and actual rate limits are more relaxed, so checking | |
317 | * them would make no difference. | |
318 | */ | |
319 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 320 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 321 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
322 | .m1 = { .min = 2, .max = 3 }, |
323 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 324 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 325 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
326 | }; |
327 | ||
6b4bf1c4 VS |
328 | static void vlv_clock(int refclk, intel_clock_t *clock) |
329 | { | |
330 | clock->m = clock->m1 * clock->m2; | |
331 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
332 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
333 | return; | |
fb03ac01 VS |
334 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
335 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
6b4bf1c4 VS |
336 | } |
337 | ||
e0638cdf PZ |
338 | /** |
339 | * Returns whether any output on the specified pipe is of the specified type | |
340 | */ | |
341 | static bool intel_pipe_has_type(struct drm_crtc *crtc, int type) | |
342 | { | |
343 | struct drm_device *dev = crtc->dev; | |
344 | struct intel_encoder *encoder; | |
345 | ||
346 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
347 | if (encoder->type == type) | |
348 | return true; | |
349 | ||
350 | return false; | |
351 | } | |
352 | ||
1b894b59 CW |
353 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
354 | int refclk) | |
2c07245f | 355 | { |
b91ad0ec | 356 | struct drm_device *dev = crtc->dev; |
2c07245f | 357 | const intel_limit_t *limit; |
b91ad0ec ZW |
358 | |
359 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 360 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 361 | if (refclk == 100000) |
b91ad0ec ZW |
362 | limit = &intel_limits_ironlake_dual_lvds_100m; |
363 | else | |
364 | limit = &intel_limits_ironlake_dual_lvds; | |
365 | } else { | |
1b894b59 | 366 | if (refclk == 100000) |
b91ad0ec ZW |
367 | limit = &intel_limits_ironlake_single_lvds_100m; |
368 | else | |
369 | limit = &intel_limits_ironlake_single_lvds; | |
370 | } | |
c6bb3538 | 371 | } else |
b91ad0ec | 372 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
373 | |
374 | return limit; | |
375 | } | |
376 | ||
044c7c41 ML |
377 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
378 | { | |
379 | struct drm_device *dev = crtc->dev; | |
044c7c41 ML |
380 | const intel_limit_t *limit; |
381 | ||
382 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 383 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 384 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 385 | else |
e4b36699 | 386 | limit = &intel_limits_g4x_single_channel_lvds; |
044c7c41 ML |
387 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
388 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 389 | limit = &intel_limits_g4x_hdmi; |
044c7c41 | 390 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 391 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 392 | } else /* The option is for other outputs */ |
e4b36699 | 393 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
394 | |
395 | return limit; | |
396 | } | |
397 | ||
1b894b59 | 398 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
79e53945 JB |
399 | { |
400 | struct drm_device *dev = crtc->dev; | |
401 | const intel_limit_t *limit; | |
402 | ||
bad720ff | 403 | if (HAS_PCH_SPLIT(dev)) |
1b894b59 | 404 | limit = intel_ironlake_limit(crtc, refclk); |
2c07245f | 405 | else if (IS_G4X(dev)) { |
044c7c41 | 406 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 407 | } else if (IS_PINEVIEW(dev)) { |
2177832f | 408 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 409 | limit = &intel_limits_pineview_lvds; |
2177832f | 410 | else |
f2b115e6 | 411 | limit = &intel_limits_pineview_sdvo; |
a0c4da24 | 412 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 413 | limit = &intel_limits_vlv; |
a6c45cf0 CW |
414 | } else if (!IS_GEN2(dev)) { |
415 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
416 | limit = &intel_limits_i9xx_lvds; | |
417 | else | |
418 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 JB |
419 | } else { |
420 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 421 | limit = &intel_limits_i8xx_lvds; |
5d536e28 | 422 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO)) |
e4b36699 | 423 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
424 | else |
425 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
426 | } |
427 | return limit; | |
428 | } | |
429 | ||
f2b115e6 AJ |
430 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
431 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 432 | { |
2177832f SL |
433 | clock->m = clock->m2 + 2; |
434 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
435 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
436 | return; | |
fb03ac01 VS |
437 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
438 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
2177832f SL |
439 | } |
440 | ||
7429e9d4 DV |
441 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
442 | { | |
443 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
444 | } | |
445 | ||
ac58c3f0 | 446 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
2177832f | 447 | { |
7429e9d4 | 448 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 449 | clock->p = clock->p1 * clock->p2; |
ed5ca77e VS |
450 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
451 | return; | |
fb03ac01 VS |
452 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
453 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
79e53945 JB |
454 | } |
455 | ||
7c04d1d9 | 456 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
457 | /** |
458 | * Returns whether the given set of divisors are valid for a given refclk with | |
459 | * the given connectors. | |
460 | */ | |
461 | ||
1b894b59 CW |
462 | static bool intel_PLL_is_valid(struct drm_device *dev, |
463 | const intel_limit_t *limit, | |
464 | const intel_clock_t *clock) | |
79e53945 | 465 | { |
f01b7962 VS |
466 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
467 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 468 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 469 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 470 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 471 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 472 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 473 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 VS |
474 | |
475 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev)) | |
476 | if (clock->m1 <= clock->m2) | |
477 | INTELPllInvalid("m1 <= m2\n"); | |
478 | ||
479 | if (!IS_VALLEYVIEW(dev)) { | |
480 | if (clock->p < limit->p.min || limit->p.max < clock->p) | |
481 | INTELPllInvalid("p out of range\n"); | |
482 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
483 | INTELPllInvalid("m out of range\n"); | |
484 | } | |
485 | ||
79e53945 | 486 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 487 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
488 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
489 | * connector, etc., rather than just a single range. | |
490 | */ | |
491 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 492 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
493 | |
494 | return true; | |
495 | } | |
496 | ||
d4906093 | 497 | static bool |
ee9300bb | 498 | i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
cec2f356 SP |
499 | int target, int refclk, intel_clock_t *match_clock, |
500 | intel_clock_t *best_clock) | |
79e53945 JB |
501 | { |
502 | struct drm_device *dev = crtc->dev; | |
79e53945 | 503 | intel_clock_t clock; |
79e53945 JB |
504 | int err = target; |
505 | ||
a210b028 | 506 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 507 | /* |
a210b028 DV |
508 | * For LVDS just rely on its current settings for dual-channel. |
509 | * We haven't figured out how to reliably set up different | |
510 | * single/dual channel state, if we even can. | |
79e53945 | 511 | */ |
1974cad0 | 512 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
513 | clock.p2 = limit->p2.p2_fast; |
514 | else | |
515 | clock.p2 = limit->p2.p2_slow; | |
516 | } else { | |
517 | if (target < limit->p2.dot_limit) | |
518 | clock.p2 = limit->p2.p2_slow; | |
519 | else | |
520 | clock.p2 = limit->p2.p2_fast; | |
521 | } | |
522 | ||
0206e353 | 523 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 524 | |
42158660 ZY |
525 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
526 | clock.m1++) { | |
527 | for (clock.m2 = limit->m2.min; | |
528 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 529 | if (clock.m2 >= clock.m1) |
42158660 ZY |
530 | break; |
531 | for (clock.n = limit->n.min; | |
532 | clock.n <= limit->n.max; clock.n++) { | |
533 | for (clock.p1 = limit->p1.min; | |
534 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
535 | int this_err; |
536 | ||
ac58c3f0 DV |
537 | i9xx_clock(refclk, &clock); |
538 | if (!intel_PLL_is_valid(dev, limit, | |
539 | &clock)) | |
540 | continue; | |
541 | if (match_clock && | |
542 | clock.p != match_clock->p) | |
543 | continue; | |
544 | ||
545 | this_err = abs(clock.dot - target); | |
546 | if (this_err < err) { | |
547 | *best_clock = clock; | |
548 | err = this_err; | |
549 | } | |
550 | } | |
551 | } | |
552 | } | |
553 | } | |
554 | ||
555 | return (err != target); | |
556 | } | |
557 | ||
558 | static bool | |
ee9300bb DV |
559 | pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
560 | int target, int refclk, intel_clock_t *match_clock, | |
561 | intel_clock_t *best_clock) | |
79e53945 JB |
562 | { |
563 | struct drm_device *dev = crtc->dev; | |
79e53945 | 564 | intel_clock_t clock; |
79e53945 JB |
565 | int err = target; |
566 | ||
a210b028 | 567 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 568 | /* |
a210b028 DV |
569 | * For LVDS just rely on its current settings for dual-channel. |
570 | * We haven't figured out how to reliably set up different | |
571 | * single/dual channel state, if we even can. | |
79e53945 | 572 | */ |
1974cad0 | 573 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
574 | clock.p2 = limit->p2.p2_fast; |
575 | else | |
576 | clock.p2 = limit->p2.p2_slow; | |
577 | } else { | |
578 | if (target < limit->p2.dot_limit) | |
579 | clock.p2 = limit->p2.p2_slow; | |
580 | else | |
581 | clock.p2 = limit->p2.p2_fast; | |
582 | } | |
583 | ||
0206e353 | 584 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 585 | |
42158660 ZY |
586 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
587 | clock.m1++) { | |
588 | for (clock.m2 = limit->m2.min; | |
589 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
590 | for (clock.n = limit->n.min; |
591 | clock.n <= limit->n.max; clock.n++) { | |
592 | for (clock.p1 = limit->p1.min; | |
593 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
594 | int this_err; |
595 | ||
ac58c3f0 | 596 | pineview_clock(refclk, &clock); |
1b894b59 CW |
597 | if (!intel_PLL_is_valid(dev, limit, |
598 | &clock)) | |
79e53945 | 599 | continue; |
cec2f356 SP |
600 | if (match_clock && |
601 | clock.p != match_clock->p) | |
602 | continue; | |
79e53945 JB |
603 | |
604 | this_err = abs(clock.dot - target); | |
605 | if (this_err < err) { | |
606 | *best_clock = clock; | |
607 | err = this_err; | |
608 | } | |
609 | } | |
610 | } | |
611 | } | |
612 | } | |
613 | ||
614 | return (err != target); | |
615 | } | |
616 | ||
d4906093 | 617 | static bool |
ee9300bb DV |
618 | g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
619 | int target, int refclk, intel_clock_t *match_clock, | |
620 | intel_clock_t *best_clock) | |
d4906093 ML |
621 | { |
622 | struct drm_device *dev = crtc->dev; | |
d4906093 ML |
623 | intel_clock_t clock; |
624 | int max_n; | |
625 | bool found; | |
6ba770dc AJ |
626 | /* approximately equals target * 0.00585 */ |
627 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
628 | found = false; |
629 | ||
630 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 631 | if (intel_is_dual_link_lvds(dev)) |
d4906093 ML |
632 | clock.p2 = limit->p2.p2_fast; |
633 | else | |
634 | clock.p2 = limit->p2.p2_slow; | |
635 | } else { | |
636 | if (target < limit->p2.dot_limit) | |
637 | clock.p2 = limit->p2.p2_slow; | |
638 | else | |
639 | clock.p2 = limit->p2.p2_fast; | |
640 | } | |
641 | ||
642 | memset(best_clock, 0, sizeof(*best_clock)); | |
643 | max_n = limit->n.max; | |
f77f13e2 | 644 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 645 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 646 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
647 | for (clock.m1 = limit->m1.max; |
648 | clock.m1 >= limit->m1.min; clock.m1--) { | |
649 | for (clock.m2 = limit->m2.max; | |
650 | clock.m2 >= limit->m2.min; clock.m2--) { | |
651 | for (clock.p1 = limit->p1.max; | |
652 | clock.p1 >= limit->p1.min; clock.p1--) { | |
653 | int this_err; | |
654 | ||
ac58c3f0 | 655 | i9xx_clock(refclk, &clock); |
1b894b59 CW |
656 | if (!intel_PLL_is_valid(dev, limit, |
657 | &clock)) | |
d4906093 | 658 | continue; |
1b894b59 CW |
659 | |
660 | this_err = abs(clock.dot - target); | |
d4906093 ML |
661 | if (this_err < err_most) { |
662 | *best_clock = clock; | |
663 | err_most = this_err; | |
664 | max_n = clock.n; | |
665 | found = true; | |
666 | } | |
667 | } | |
668 | } | |
669 | } | |
670 | } | |
2c07245f ZW |
671 | return found; |
672 | } | |
673 | ||
a0c4da24 | 674 | static bool |
ee9300bb DV |
675 | vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
676 | int target, int refclk, intel_clock_t *match_clock, | |
677 | intel_clock_t *best_clock) | |
a0c4da24 | 678 | { |
f01b7962 | 679 | struct drm_device *dev = crtc->dev; |
6b4bf1c4 | 680 | intel_clock_t clock; |
69e4f900 | 681 | unsigned int bestppm = 1000000; |
27e639bf VS |
682 | /* min update 19.2 MHz */ |
683 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 684 | bool found = false; |
a0c4da24 | 685 | |
6b4bf1c4 VS |
686 | target *= 5; /* fast clock */ |
687 | ||
688 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
689 | |
690 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 691 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 692 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 693 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 694 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 695 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 696 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 697 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
69e4f900 VS |
698 | unsigned int ppm, diff; |
699 | ||
6b4bf1c4 VS |
700 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
701 | refclk * clock.m1); | |
702 | ||
703 | vlv_clock(refclk, &clock); | |
43b0ac53 | 704 | |
f01b7962 VS |
705 | if (!intel_PLL_is_valid(dev, limit, |
706 | &clock)) | |
43b0ac53 VS |
707 | continue; |
708 | ||
6b4bf1c4 VS |
709 | diff = abs(clock.dot - target); |
710 | ppm = div_u64(1000000ULL * diff, target); | |
711 | ||
712 | if (ppm < 100 && clock.p > best_clock->p) { | |
43b0ac53 | 713 | bestppm = 0; |
6b4bf1c4 | 714 | *best_clock = clock; |
49e497ef | 715 | found = true; |
43b0ac53 | 716 | } |
6b4bf1c4 | 717 | |
c686122c | 718 | if (bestppm >= 10 && ppm < bestppm - 10) { |
69e4f900 | 719 | bestppm = ppm; |
6b4bf1c4 | 720 | *best_clock = clock; |
49e497ef | 721 | found = true; |
a0c4da24 JB |
722 | } |
723 | } | |
724 | } | |
725 | } | |
726 | } | |
a0c4da24 | 727 | |
49e497ef | 728 | return found; |
a0c4da24 | 729 | } |
a4fc5ed6 | 730 | |
20ddf665 VS |
731 | bool intel_crtc_active(struct drm_crtc *crtc) |
732 | { | |
733 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
734 | ||
735 | /* Be paranoid as we can arrive here with only partial | |
736 | * state retrieved from the hardware during setup. | |
737 | * | |
241bfc38 | 738 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
739 | * as Haswell has gained clock readout/fastboot support. |
740 | * | |
741 | * We can ditch the crtc->fb check as soon as we can | |
742 | * properly reconstruct framebuffers. | |
743 | */ | |
744 | return intel_crtc->active && crtc->fb && | |
241bfc38 | 745 | intel_crtc->config.adjusted_mode.crtc_clock; |
20ddf665 VS |
746 | } |
747 | ||
a5c961d1 PZ |
748 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
749 | enum pipe pipe) | |
750 | { | |
751 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
752 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
753 | ||
3b117c8f | 754 | return intel_crtc->config.cpu_transcoder; |
a5c961d1 PZ |
755 | } |
756 | ||
57e22f4a | 757 | static void g4x_wait_for_vblank(struct drm_device *dev, int pipe) |
a928d536 PZ |
758 | { |
759 | struct drm_i915_private *dev_priv = dev->dev_private; | |
57e22f4a | 760 | u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe); |
a928d536 PZ |
761 | |
762 | frame = I915_READ(frame_reg); | |
763 | ||
764 | if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) | |
765 | DRM_DEBUG_KMS("vblank wait timed out\n"); | |
766 | } | |
767 | ||
9d0498a2 JB |
768 | /** |
769 | * intel_wait_for_vblank - wait for vblank on a given pipe | |
770 | * @dev: drm device | |
771 | * @pipe: pipe to wait for | |
772 | * | |
773 | * Wait for vblank to occur on a given pipe. Needed for various bits of | |
774 | * mode setting code. | |
775 | */ | |
776 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) | |
79e53945 | 777 | { |
9d0498a2 | 778 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 779 | int pipestat_reg = PIPESTAT(pipe); |
9d0498a2 | 780 | |
57e22f4a VS |
781 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
782 | g4x_wait_for_vblank(dev, pipe); | |
a928d536 PZ |
783 | return; |
784 | } | |
785 | ||
300387c0 CW |
786 | /* Clear existing vblank status. Note this will clear any other |
787 | * sticky status fields as well. | |
788 | * | |
789 | * This races with i915_driver_irq_handler() with the result | |
790 | * that either function could miss a vblank event. Here it is not | |
791 | * fatal, as we will either wait upon the next vblank interrupt or | |
792 | * timeout. Generally speaking intel_wait_for_vblank() is only | |
793 | * called during modeset at which time the GPU should be idle and | |
794 | * should *not* be performing page flips and thus not waiting on | |
795 | * vblanks... | |
796 | * Currently, the result of us stealing a vblank from the irq | |
797 | * handler is that a single frame will be skipped during swapbuffers. | |
798 | */ | |
799 | I915_WRITE(pipestat_reg, | |
800 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); | |
801 | ||
9d0498a2 | 802 | /* Wait for vblank interrupt bit to set */ |
481b6af3 CW |
803 | if (wait_for(I915_READ(pipestat_reg) & |
804 | PIPE_VBLANK_INTERRUPT_STATUS, | |
805 | 50)) | |
9d0498a2 JB |
806 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
807 | } | |
808 | ||
fbf49ea2 VS |
809 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
810 | { | |
811 | struct drm_i915_private *dev_priv = dev->dev_private; | |
812 | u32 reg = PIPEDSL(pipe); | |
813 | u32 line1, line2; | |
814 | u32 line_mask; | |
815 | ||
816 | if (IS_GEN2(dev)) | |
817 | line_mask = DSL_LINEMASK_GEN2; | |
818 | else | |
819 | line_mask = DSL_LINEMASK_GEN3; | |
820 | ||
821 | line1 = I915_READ(reg) & line_mask; | |
822 | mdelay(5); | |
823 | line2 = I915_READ(reg) & line_mask; | |
824 | ||
825 | return line1 == line2; | |
826 | } | |
827 | ||
ab7ad7f6 KP |
828 | /* |
829 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
9d0498a2 JB |
830 | * @dev: drm device |
831 | * @pipe: pipe to wait for | |
832 | * | |
833 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
834 | * spinning on the vblank interrupt status bit, since we won't actually | |
835 | * see an interrupt when the pipe is disabled. | |
836 | * | |
ab7ad7f6 KP |
837 | * On Gen4 and above: |
838 | * wait for the pipe register state bit to turn off | |
839 | * | |
840 | * Otherwise: | |
841 | * wait for the display line value to settle (it usually | |
842 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 843 | * |
9d0498a2 | 844 | */ |
58e10eb9 | 845 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
9d0498a2 JB |
846 | { |
847 | struct drm_i915_private *dev_priv = dev->dev_private; | |
702e7a56 PZ |
848 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
849 | pipe); | |
ab7ad7f6 KP |
850 | |
851 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 852 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
853 | |
854 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
855 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
856 | 100)) | |
284637d9 | 857 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 858 | } else { |
ab7ad7f6 | 859 | /* Wait for the display line to settle */ |
fbf49ea2 | 860 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 861 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 862 | } |
79e53945 JB |
863 | } |
864 | ||
b0ea7d37 DL |
865 | /* |
866 | * ibx_digital_port_connected - is the specified port connected? | |
867 | * @dev_priv: i915 private structure | |
868 | * @port: the port to test | |
869 | * | |
870 | * Returns true if @port is connected, false otherwise. | |
871 | */ | |
872 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, | |
873 | struct intel_digital_port *port) | |
874 | { | |
875 | u32 bit; | |
876 | ||
c36346e3 DL |
877 | if (HAS_PCH_IBX(dev_priv->dev)) { |
878 | switch(port->port) { | |
879 | case PORT_B: | |
880 | bit = SDE_PORTB_HOTPLUG; | |
881 | break; | |
882 | case PORT_C: | |
883 | bit = SDE_PORTC_HOTPLUG; | |
884 | break; | |
885 | case PORT_D: | |
886 | bit = SDE_PORTD_HOTPLUG; | |
887 | break; | |
888 | default: | |
889 | return true; | |
890 | } | |
891 | } else { | |
892 | switch(port->port) { | |
893 | case PORT_B: | |
894 | bit = SDE_PORTB_HOTPLUG_CPT; | |
895 | break; | |
896 | case PORT_C: | |
897 | bit = SDE_PORTC_HOTPLUG_CPT; | |
898 | break; | |
899 | case PORT_D: | |
900 | bit = SDE_PORTD_HOTPLUG_CPT; | |
901 | break; | |
902 | default: | |
903 | return true; | |
904 | } | |
b0ea7d37 DL |
905 | } |
906 | ||
907 | return I915_READ(SDEISR) & bit; | |
908 | } | |
909 | ||
b24e7179 JB |
910 | static const char *state_string(bool enabled) |
911 | { | |
912 | return enabled ? "on" : "off"; | |
913 | } | |
914 | ||
915 | /* Only for pre-ILK configs */ | |
55607e8a DV |
916 | void assert_pll(struct drm_i915_private *dev_priv, |
917 | enum pipe pipe, bool state) | |
b24e7179 JB |
918 | { |
919 | int reg; | |
920 | u32 val; | |
921 | bool cur_state; | |
922 | ||
923 | reg = DPLL(pipe); | |
924 | val = I915_READ(reg); | |
925 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
926 | WARN(cur_state != state, | |
927 | "PLL state assertion failure (expected %s, current %s)\n", | |
928 | state_string(state), state_string(cur_state)); | |
929 | } | |
b24e7179 | 930 | |
23538ef1 JN |
931 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
932 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
933 | { | |
934 | u32 val; | |
935 | bool cur_state; | |
936 | ||
937 | mutex_lock(&dev_priv->dpio_lock); | |
938 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); | |
939 | mutex_unlock(&dev_priv->dpio_lock); | |
940 | ||
941 | cur_state = val & DSI_PLL_VCO_EN; | |
942 | WARN(cur_state != state, | |
943 | "DSI PLL state assertion failure (expected %s, current %s)\n", | |
944 | state_string(state), state_string(cur_state)); | |
945 | } | |
946 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
947 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
948 | ||
55607e8a | 949 | struct intel_shared_dpll * |
e2b78267 DV |
950 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
951 | { | |
952 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
953 | ||
a43f6e0f | 954 | if (crtc->config.shared_dpll < 0) |
e2b78267 DV |
955 | return NULL; |
956 | ||
a43f6e0f | 957 | return &dev_priv->shared_dplls[crtc->config.shared_dpll]; |
e2b78267 DV |
958 | } |
959 | ||
040484af | 960 | /* For ILK+ */ |
55607e8a DV |
961 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
962 | struct intel_shared_dpll *pll, | |
963 | bool state) | |
040484af | 964 | { |
040484af | 965 | bool cur_state; |
5358901f | 966 | struct intel_dpll_hw_state hw_state; |
040484af | 967 | |
9d82aa17 ED |
968 | if (HAS_PCH_LPT(dev_priv->dev)) { |
969 | DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n"); | |
970 | return; | |
971 | } | |
972 | ||
92b27b08 | 973 | if (WARN (!pll, |
46edb027 | 974 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 975 | return; |
ee7b9f93 | 976 | |
5358901f | 977 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
92b27b08 | 978 | WARN(cur_state != state, |
5358901f DV |
979 | "%s assertion failure (expected %s, current %s)\n", |
980 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 981 | } |
040484af JB |
982 | |
983 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
984 | enum pipe pipe, bool state) | |
985 | { | |
986 | int reg; | |
987 | u32 val; | |
988 | bool cur_state; | |
ad80a810 PZ |
989 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
990 | pipe); | |
040484af | 991 | |
affa9354 PZ |
992 | if (HAS_DDI(dev_priv->dev)) { |
993 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 994 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 995 | val = I915_READ(reg); |
ad80a810 | 996 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
997 | } else { |
998 | reg = FDI_TX_CTL(pipe); | |
999 | val = I915_READ(reg); | |
1000 | cur_state = !!(val & FDI_TX_ENABLE); | |
1001 | } | |
040484af JB |
1002 | WARN(cur_state != state, |
1003 | "FDI TX state assertion failure (expected %s, current %s)\n", | |
1004 | state_string(state), state_string(cur_state)); | |
1005 | } | |
1006 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1007 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1008 | ||
1009 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1010 | enum pipe pipe, bool state) | |
1011 | { | |
1012 | int reg; | |
1013 | u32 val; | |
1014 | bool cur_state; | |
1015 | ||
d63fa0dc PZ |
1016 | reg = FDI_RX_CTL(pipe); |
1017 | val = I915_READ(reg); | |
1018 | cur_state = !!(val & FDI_RX_ENABLE); | |
040484af JB |
1019 | WARN(cur_state != state, |
1020 | "FDI RX state assertion failure (expected %s, current %s)\n", | |
1021 | state_string(state), state_string(cur_state)); | |
1022 | } | |
1023 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1024 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1025 | ||
1026 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1027 | enum pipe pipe) | |
1028 | { | |
1029 | int reg; | |
1030 | u32 val; | |
1031 | ||
1032 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1033 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1034 | return; |
1035 | ||
bf507ef7 | 1036 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1037 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1038 | return; |
1039 | ||
040484af JB |
1040 | reg = FDI_TX_CTL(pipe); |
1041 | val = I915_READ(reg); | |
1042 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); | |
1043 | } | |
1044 | ||
55607e8a DV |
1045 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1046 | enum pipe pipe, bool state) | |
040484af JB |
1047 | { |
1048 | int reg; | |
1049 | u32 val; | |
55607e8a | 1050 | bool cur_state; |
040484af JB |
1051 | |
1052 | reg = FDI_RX_CTL(pipe); | |
1053 | val = I915_READ(reg); | |
55607e8a DV |
1054 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
1055 | WARN(cur_state != state, | |
1056 | "FDI RX PLL assertion failure (expected %s, current %s)\n", | |
1057 | state_string(state), state_string(cur_state)); | |
040484af JB |
1058 | } |
1059 | ||
ea0760cf JB |
1060 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1061 | enum pipe pipe) | |
1062 | { | |
1063 | int pp_reg, lvds_reg; | |
1064 | u32 val; | |
1065 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1066 | bool locked = true; |
ea0760cf JB |
1067 | |
1068 | if (HAS_PCH_SPLIT(dev_priv->dev)) { | |
1069 | pp_reg = PCH_PP_CONTROL; | |
1070 | lvds_reg = PCH_LVDS; | |
1071 | } else { | |
1072 | pp_reg = PP_CONTROL; | |
1073 | lvds_reg = LVDS; | |
1074 | } | |
1075 | ||
1076 | val = I915_READ(pp_reg); | |
1077 | if (!(val & PANEL_POWER_ON) || | |
1078 | ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) | |
1079 | locked = false; | |
1080 | ||
1081 | if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) | |
1082 | panel_pipe = PIPE_B; | |
1083 | ||
1084 | WARN(panel_pipe == pipe && locked, | |
1085 | "panel assertion failure, pipe %c regs locked\n", | |
9db4a9c7 | 1086 | pipe_name(pipe)); |
ea0760cf JB |
1087 | } |
1088 | ||
93ce0ba6 JN |
1089 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1090 | enum pipe pipe, bool state) | |
1091 | { | |
1092 | struct drm_device *dev = dev_priv->dev; | |
1093 | bool cur_state; | |
1094 | ||
1095 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
1096 | cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE; | |
1097 | else if (IS_845G(dev) || IS_I865G(dev)) | |
1098 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; | |
1099 | else | |
1100 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; | |
1101 | ||
1102 | WARN(cur_state != state, | |
1103 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", | |
1104 | pipe_name(pipe), state_string(state), state_string(cur_state)); | |
1105 | } | |
1106 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1107 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1108 | ||
b840d907 JB |
1109 | void assert_pipe(struct drm_i915_private *dev_priv, |
1110 | enum pipe pipe, bool state) | |
b24e7179 JB |
1111 | { |
1112 | int reg; | |
1113 | u32 val; | |
63d7bbe9 | 1114 | bool cur_state; |
702e7a56 PZ |
1115 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1116 | pipe); | |
b24e7179 | 1117 | |
8e636784 DV |
1118 | /* if we need the pipe A quirk it must be always on */ |
1119 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
1120 | state = true; | |
1121 | ||
b97186f0 PZ |
1122 | if (!intel_display_power_enabled(dev_priv->dev, |
1123 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { | |
69310161 PZ |
1124 | cur_state = false; |
1125 | } else { | |
1126 | reg = PIPECONF(cpu_transcoder); | |
1127 | val = I915_READ(reg); | |
1128 | cur_state = !!(val & PIPECONF_ENABLE); | |
1129 | } | |
1130 | ||
63d7bbe9 JB |
1131 | WARN(cur_state != state, |
1132 | "pipe %c assertion failure (expected %s, current %s)\n", | |
9db4a9c7 | 1133 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1134 | } |
1135 | ||
931872fc CW |
1136 | static void assert_plane(struct drm_i915_private *dev_priv, |
1137 | enum plane plane, bool state) | |
b24e7179 JB |
1138 | { |
1139 | int reg; | |
1140 | u32 val; | |
931872fc | 1141 | bool cur_state; |
b24e7179 JB |
1142 | |
1143 | reg = DSPCNTR(plane); | |
1144 | val = I915_READ(reg); | |
931872fc CW |
1145 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
1146 | WARN(cur_state != state, | |
1147 | "plane %c assertion failure (expected %s, current %s)\n", | |
1148 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1149 | } |
1150 | ||
931872fc CW |
1151 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1152 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1153 | ||
b24e7179 JB |
1154 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1155 | enum pipe pipe) | |
1156 | { | |
653e1026 | 1157 | struct drm_device *dev = dev_priv->dev; |
b24e7179 JB |
1158 | int reg, i; |
1159 | u32 val; | |
1160 | int cur_pipe; | |
1161 | ||
653e1026 VS |
1162 | /* Primary planes are fixed to pipes on gen4+ */ |
1163 | if (INTEL_INFO(dev)->gen >= 4) { | |
28c05794 AJ |
1164 | reg = DSPCNTR(pipe); |
1165 | val = I915_READ(reg); | |
1166 | WARN((val & DISPLAY_PLANE_ENABLE), | |
1167 | "plane %c assertion failure, should be disabled but not\n", | |
1168 | plane_name(pipe)); | |
19ec1358 | 1169 | return; |
28c05794 | 1170 | } |
19ec1358 | 1171 | |
b24e7179 | 1172 | /* Need to check both planes against the pipe */ |
08e2a7de | 1173 | for_each_pipe(i) { |
b24e7179 JB |
1174 | reg = DSPCNTR(i); |
1175 | val = I915_READ(reg); | |
1176 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1177 | DISPPLANE_SEL_PIPE_SHIFT; | |
1178 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, | |
9db4a9c7 JB |
1179 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1180 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1181 | } |
1182 | } | |
1183 | ||
19332d7a JB |
1184 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1185 | enum pipe pipe) | |
1186 | { | |
20674eef | 1187 | struct drm_device *dev = dev_priv->dev; |
19332d7a JB |
1188 | int reg, i; |
1189 | u32 val; | |
1190 | ||
20674eef | 1191 | if (IS_VALLEYVIEW(dev)) { |
22d3fd46 | 1192 | for (i = 0; i < INTEL_INFO(dev)->num_sprites; i++) { |
20674eef VS |
1193 | reg = SPCNTR(pipe, i); |
1194 | val = I915_READ(reg); | |
1195 | WARN((val & SP_ENABLE), | |
1196 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", | |
1197 | sprite_name(pipe, i), pipe_name(pipe)); | |
1198 | } | |
1199 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
1200 | reg = SPRCTL(pipe); | |
19332d7a | 1201 | val = I915_READ(reg); |
20674eef | 1202 | WARN((val & SPRITE_ENABLE), |
06da8da2 | 1203 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1204 | plane_name(pipe), pipe_name(pipe)); |
1205 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
1206 | reg = DVSCNTR(pipe); | |
19332d7a | 1207 | val = I915_READ(reg); |
20674eef | 1208 | WARN((val & DVS_ENABLE), |
06da8da2 | 1209 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1210 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1211 | } |
1212 | } | |
1213 | ||
89eff4be | 1214 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1215 | { |
1216 | u32 val; | |
1217 | bool enabled; | |
1218 | ||
89eff4be | 1219 | WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1220 | |
92f2584a JB |
1221 | val = I915_READ(PCH_DREF_CONTROL); |
1222 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1223 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
1224 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); | |
1225 | } | |
1226 | ||
ab9412ba DV |
1227 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1228 | enum pipe pipe) | |
92f2584a JB |
1229 | { |
1230 | int reg; | |
1231 | u32 val; | |
1232 | bool enabled; | |
1233 | ||
ab9412ba | 1234 | reg = PCH_TRANSCONF(pipe); |
92f2584a JB |
1235 | val = I915_READ(reg); |
1236 | enabled = !!(val & TRANS_ENABLE); | |
9db4a9c7 JB |
1237 | WARN(enabled, |
1238 | "transcoder assertion failed, should be off on pipe %c but is still active\n", | |
1239 | pipe_name(pipe)); | |
92f2584a JB |
1240 | } |
1241 | ||
4e634389 KP |
1242 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1243 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1244 | { |
1245 | if ((val & DP_PORT_EN) == 0) | |
1246 | return false; | |
1247 | ||
1248 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1249 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1250 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1251 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1252 | return false; | |
1253 | } else { | |
1254 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1255 | return false; | |
1256 | } | |
1257 | return true; | |
1258 | } | |
1259 | ||
1519b995 KP |
1260 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1261 | enum pipe pipe, u32 val) | |
1262 | { | |
dc0fa718 | 1263 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1264 | return false; |
1265 | ||
1266 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1267 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 KP |
1268 | return false; |
1269 | } else { | |
dc0fa718 | 1270 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1271 | return false; |
1272 | } | |
1273 | return true; | |
1274 | } | |
1275 | ||
1276 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1277 | enum pipe pipe, u32 val) | |
1278 | { | |
1279 | if ((val & LVDS_PORT_EN) == 0) | |
1280 | return false; | |
1281 | ||
1282 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1283 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1284 | return false; | |
1285 | } else { | |
1286 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1287 | return false; | |
1288 | } | |
1289 | return true; | |
1290 | } | |
1291 | ||
1292 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1293 | enum pipe pipe, u32 val) | |
1294 | { | |
1295 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1296 | return false; | |
1297 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1298 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1299 | return false; | |
1300 | } else { | |
1301 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1302 | return false; | |
1303 | } | |
1304 | return true; | |
1305 | } | |
1306 | ||
291906f1 | 1307 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1308 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1309 | { |
47a05eca | 1310 | u32 val = I915_READ(reg); |
4e634389 | 1311 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1312 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1313 | reg, pipe_name(pipe)); |
de9a35ab | 1314 | |
75c5da27 DV |
1315 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
1316 | && (val & DP_PIPEB_SELECT), | |
de9a35ab | 1317 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1318 | } |
1319 | ||
1320 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1321 | enum pipe pipe, int reg) | |
1322 | { | |
47a05eca | 1323 | u32 val = I915_READ(reg); |
b70ad586 | 1324 | WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1325 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1326 | reg, pipe_name(pipe)); |
de9a35ab | 1327 | |
dc0fa718 | 1328 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1329 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1330 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1331 | } |
1332 | ||
1333 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1334 | enum pipe pipe) | |
1335 | { | |
1336 | int reg; | |
1337 | u32 val; | |
291906f1 | 1338 | |
f0575e92 KP |
1339 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1340 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1341 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1342 | |
1343 | reg = PCH_ADPA; | |
1344 | val = I915_READ(reg); | |
b70ad586 | 1345 | WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1346 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1347 | pipe_name(pipe)); |
291906f1 JB |
1348 | |
1349 | reg = PCH_LVDS; | |
1350 | val = I915_READ(reg); | |
b70ad586 | 1351 | WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1352 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1353 | pipe_name(pipe)); |
291906f1 | 1354 | |
e2debe91 PZ |
1355 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1356 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1357 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1358 | } |
1359 | ||
40e9cf64 JB |
1360 | static void intel_init_dpio(struct drm_device *dev) |
1361 | { | |
1362 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1363 | ||
1364 | if (!IS_VALLEYVIEW(dev)) | |
1365 | return; | |
1366 | ||
e4607fcf | 1367 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; |
5382f5f3 JB |
1368 | } |
1369 | ||
1370 | static void intel_reset_dpio(struct drm_device *dev) | |
1371 | { | |
1372 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1373 | ||
1374 | if (!IS_VALLEYVIEW(dev)) | |
1375 | return; | |
1376 | ||
e5cbfbfb ID |
1377 | /* |
1378 | * Enable the CRI clock source so we can get at the display and the | |
1379 | * reference clock for VGA hotplug / manual detection. | |
1380 | */ | |
404faabc | 1381 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | |
e5cbfbfb | 1382 | DPLL_REFA_CLK_ENABLE_VLV | |
404faabc ID |
1383 | DPLL_INTEGRATED_CRI_CLK_VLV); |
1384 | ||
40e9cf64 JB |
1385 | /* |
1386 | * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - | |
1387 | * 6. De-assert cmn_reset/side_reset. Same as VLV X0. | |
1388 | * a. GUnit 0x2110 bit[0] set to 1 (def 0) | |
1389 | * b. The other bits such as sfr settings / modesel may all be set | |
1390 | * to 0. | |
1391 | * | |
1392 | * This should only be done on init and resume from S3 with both | |
1393 | * PLLs disabled, or we risk losing DPIO and PLL synchronization. | |
1394 | */ | |
1395 | I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); | |
1396 | } | |
1397 | ||
426115cf | 1398 | static void vlv_enable_pll(struct intel_crtc *crtc) |
87442f73 | 1399 | { |
426115cf DV |
1400 | struct drm_device *dev = crtc->base.dev; |
1401 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1402 | int reg = DPLL(crtc->pipe); | |
1403 | u32 dpll = crtc->config.dpll_hw_state.dpll; | |
87442f73 | 1404 | |
426115cf | 1405 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 DV |
1406 | |
1407 | /* No really, not for ILK+ */ | |
1408 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); | |
1409 | ||
1410 | /* PLL is protected by panel, make sure we can write it */ | |
1411 | if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) | |
426115cf | 1412 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1413 | |
426115cf DV |
1414 | I915_WRITE(reg, dpll); |
1415 | POSTING_READ(reg); | |
1416 | udelay(150); | |
1417 | ||
1418 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1419 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1420 | ||
1421 | I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md); | |
1422 | POSTING_READ(DPLL_MD(crtc->pipe)); | |
87442f73 DV |
1423 | |
1424 | /* We do this three times for luck */ | |
426115cf | 1425 | I915_WRITE(reg, dpll); |
87442f73 DV |
1426 | POSTING_READ(reg); |
1427 | udelay(150); /* wait for warmup */ | |
426115cf | 1428 | I915_WRITE(reg, dpll); |
87442f73 DV |
1429 | POSTING_READ(reg); |
1430 | udelay(150); /* wait for warmup */ | |
426115cf | 1431 | I915_WRITE(reg, dpll); |
87442f73 DV |
1432 | POSTING_READ(reg); |
1433 | udelay(150); /* wait for warmup */ | |
1434 | } | |
1435 | ||
66e3d5c0 | 1436 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1437 | { |
66e3d5c0 DV |
1438 | struct drm_device *dev = crtc->base.dev; |
1439 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1440 | int reg = DPLL(crtc->pipe); | |
1441 | u32 dpll = crtc->config.dpll_hw_state.dpll; | |
63d7bbe9 | 1442 | |
66e3d5c0 | 1443 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1444 | |
63d7bbe9 | 1445 | /* No really, not for ILK+ */ |
3d13ef2e | 1446 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1447 | |
1448 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1449 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1450 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1451 | |
66e3d5c0 DV |
1452 | I915_WRITE(reg, dpll); |
1453 | ||
1454 | /* Wait for the clocks to stabilize. */ | |
1455 | POSTING_READ(reg); | |
1456 | udelay(150); | |
1457 | ||
1458 | if (INTEL_INFO(dev)->gen >= 4) { | |
1459 | I915_WRITE(DPLL_MD(crtc->pipe), | |
1460 | crtc->config.dpll_hw_state.dpll_md); | |
1461 | } else { | |
1462 | /* The pixel multiplier can only be updated once the | |
1463 | * DPLL is enabled and the clocks are stable. | |
1464 | * | |
1465 | * So write it again. | |
1466 | */ | |
1467 | I915_WRITE(reg, dpll); | |
1468 | } | |
63d7bbe9 JB |
1469 | |
1470 | /* We do this three times for luck */ | |
66e3d5c0 | 1471 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1472 | POSTING_READ(reg); |
1473 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1474 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1475 | POSTING_READ(reg); |
1476 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1477 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1478 | POSTING_READ(reg); |
1479 | udelay(150); /* wait for warmup */ | |
1480 | } | |
1481 | ||
1482 | /** | |
50b44a44 | 1483 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1484 | * @dev_priv: i915 private structure |
1485 | * @pipe: pipe PLL to disable | |
1486 | * | |
1487 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1488 | * | |
1489 | * Note! This is for pre-ILK only. | |
1490 | */ | |
50b44a44 | 1491 | static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
63d7bbe9 | 1492 | { |
63d7bbe9 JB |
1493 | /* Don't disable pipe A or pipe A PLLs if needed */ |
1494 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1495 | return; | |
1496 | ||
1497 | /* Make sure the pipe isn't still relying on us */ | |
1498 | assert_pipe_disabled(dev_priv, pipe); | |
1499 | ||
50b44a44 DV |
1500 | I915_WRITE(DPLL(pipe), 0); |
1501 | POSTING_READ(DPLL(pipe)); | |
63d7bbe9 JB |
1502 | } |
1503 | ||
f6071166 JB |
1504 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1505 | { | |
1506 | u32 val = 0; | |
1507 | ||
1508 | /* Make sure the pipe isn't still relying on us */ | |
1509 | assert_pipe_disabled(dev_priv, pipe); | |
1510 | ||
e5cbfbfb ID |
1511 | /* |
1512 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1513 | * The latter is needed for VGA hotplug / manual detection. | |
1514 | */ | |
f6071166 | 1515 | if (pipe == PIPE_B) |
e5cbfbfb | 1516 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV; |
f6071166 JB |
1517 | I915_WRITE(DPLL(pipe), val); |
1518 | POSTING_READ(DPLL(pipe)); | |
1519 | } | |
1520 | ||
e4607fcf CML |
1521 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
1522 | struct intel_digital_port *dport) | |
89b667f8 JB |
1523 | { |
1524 | u32 port_mask; | |
1525 | ||
e4607fcf CML |
1526 | switch (dport->port) { |
1527 | case PORT_B: | |
89b667f8 | 1528 | port_mask = DPLL_PORTB_READY_MASK; |
e4607fcf CML |
1529 | break; |
1530 | case PORT_C: | |
89b667f8 | 1531 | port_mask = DPLL_PORTC_READY_MASK; |
e4607fcf CML |
1532 | break; |
1533 | default: | |
1534 | BUG(); | |
1535 | } | |
89b667f8 JB |
1536 | |
1537 | if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000)) | |
1538 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", | |
be46ffd4 | 1539 | port_name(dport->port), I915_READ(DPLL(0))); |
89b667f8 JB |
1540 | } |
1541 | ||
92f2584a | 1542 | /** |
e72f9fbf | 1543 | * ironlake_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1544 | * @dev_priv: i915 private structure |
1545 | * @pipe: pipe PLL to enable | |
1546 | * | |
1547 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1548 | * drives the transcoder clock. | |
1549 | */ | |
e2b78267 | 1550 | static void ironlake_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1551 | { |
3d13ef2e DL |
1552 | struct drm_device *dev = crtc->base.dev; |
1553 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1554 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1555 | |
48da64a8 | 1556 | /* PCH PLLs only available on ILK, SNB and IVB */ |
3d13ef2e | 1557 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
87a875bb | 1558 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1559 | return; |
1560 | ||
1561 | if (WARN_ON(pll->refcount == 0)) | |
1562 | return; | |
ee7b9f93 | 1563 | |
46edb027 DV |
1564 | DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n", |
1565 | pll->name, pll->active, pll->on, | |
e2b78267 | 1566 | crtc->base.base.id); |
92f2584a | 1567 | |
cdbd2316 DV |
1568 | if (pll->active++) { |
1569 | WARN_ON(!pll->on); | |
e9d6944e | 1570 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1571 | return; |
1572 | } | |
f4a091c7 | 1573 | WARN_ON(pll->on); |
ee7b9f93 | 1574 | |
46edb027 | 1575 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1576 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1577 | pll->on = true; |
92f2584a JB |
1578 | } |
1579 | ||
e2b78267 | 1580 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1581 | { |
3d13ef2e DL |
1582 | struct drm_device *dev = crtc->base.dev; |
1583 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1584 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1585 | |
92f2584a | 1586 | /* PCH only available on ILK+ */ |
3d13ef2e | 1587 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
87a875bb | 1588 | if (WARN_ON(pll == NULL)) |
ee7b9f93 | 1589 | return; |
92f2584a | 1590 | |
48da64a8 CW |
1591 | if (WARN_ON(pll->refcount == 0)) |
1592 | return; | |
7a419866 | 1593 | |
46edb027 DV |
1594 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1595 | pll->name, pll->active, pll->on, | |
e2b78267 | 1596 | crtc->base.base.id); |
7a419866 | 1597 | |
48da64a8 | 1598 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1599 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1600 | return; |
1601 | } | |
1602 | ||
e9d6944e | 1603 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1604 | WARN_ON(!pll->on); |
cdbd2316 | 1605 | if (--pll->active) |
7a419866 | 1606 | return; |
ee7b9f93 | 1607 | |
46edb027 | 1608 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1609 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1610 | pll->on = false; |
92f2584a JB |
1611 | } |
1612 | ||
b8a4f404 PZ |
1613 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1614 | enum pipe pipe) | |
040484af | 1615 | { |
23670b32 | 1616 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1617 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1618 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
23670b32 | 1619 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1620 | |
1621 | /* PCH only available on ILK+ */ | |
3d13ef2e | 1622 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
040484af JB |
1623 | |
1624 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1625 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1626 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1627 | |
1628 | /* FDI must be feeding us bits for PCH ports */ | |
1629 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1630 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1631 | ||
23670b32 DV |
1632 | if (HAS_PCH_CPT(dev)) { |
1633 | /* Workaround: Set the timing override bit before enabling the | |
1634 | * pch transcoder. */ | |
1635 | reg = TRANS_CHICKEN2(pipe); | |
1636 | val = I915_READ(reg); | |
1637 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1638 | I915_WRITE(reg, val); | |
59c859d6 | 1639 | } |
23670b32 | 1640 | |
ab9412ba | 1641 | reg = PCH_TRANSCONF(pipe); |
040484af | 1642 | val = I915_READ(reg); |
5f7f726d | 1643 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1644 | |
1645 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1646 | /* | |
1647 | * make the BPC in transcoder be consistent with | |
1648 | * that in pipeconf reg. | |
1649 | */ | |
dfd07d72 DV |
1650 | val &= ~PIPECONF_BPC_MASK; |
1651 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1652 | } |
5f7f726d PZ |
1653 | |
1654 | val &= ~TRANS_INTERLACE_MASK; | |
1655 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 PZ |
1656 | if (HAS_PCH_IBX(dev_priv->dev) && |
1657 | intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) | |
1658 | val |= TRANS_LEGACY_INTERLACED_ILK; | |
1659 | else | |
1660 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1661 | else |
1662 | val |= TRANS_PROGRESSIVE; | |
1663 | ||
040484af JB |
1664 | I915_WRITE(reg, val | TRANS_ENABLE); |
1665 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 1666 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1667 | } |
1668 | ||
8fb033d7 | 1669 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1670 | enum transcoder cpu_transcoder) |
040484af | 1671 | { |
8fb033d7 | 1672 | u32 val, pipeconf_val; |
8fb033d7 PZ |
1673 | |
1674 | /* PCH only available on ILK+ */ | |
3d13ef2e | 1675 | BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5); |
8fb033d7 | 1676 | |
8fb033d7 | 1677 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1678 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1679 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1680 | |
223a6fdf PZ |
1681 | /* Workaround: set timing override bit. */ |
1682 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1683 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf PZ |
1684 | I915_WRITE(_TRANSA_CHICKEN2, val); |
1685 | ||
25f3ef11 | 1686 | val = TRANS_ENABLE; |
937bb610 | 1687 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1688 | |
9a76b1c6 PZ |
1689 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1690 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1691 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1692 | else |
1693 | val |= TRANS_PROGRESSIVE; | |
1694 | ||
ab9412ba DV |
1695 | I915_WRITE(LPT_TRANSCONF, val); |
1696 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 1697 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1698 | } |
1699 | ||
b8a4f404 PZ |
1700 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1701 | enum pipe pipe) | |
040484af | 1702 | { |
23670b32 DV |
1703 | struct drm_device *dev = dev_priv->dev; |
1704 | uint32_t reg, val; | |
040484af JB |
1705 | |
1706 | /* FDI relies on the transcoder */ | |
1707 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1708 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1709 | ||
291906f1 JB |
1710 | /* Ports must be off as well */ |
1711 | assert_pch_ports_disabled(dev_priv, pipe); | |
1712 | ||
ab9412ba | 1713 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1714 | val = I915_READ(reg); |
1715 | val &= ~TRANS_ENABLE; | |
1716 | I915_WRITE(reg, val); | |
1717 | /* wait for PCH transcoder off, transcoder state */ | |
1718 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 1719 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 DV |
1720 | |
1721 | if (!HAS_PCH_IBX(dev)) { | |
1722 | /* Workaround: Clear the timing override chicken bit again. */ | |
1723 | reg = TRANS_CHICKEN2(pipe); | |
1724 | val = I915_READ(reg); | |
1725 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1726 | I915_WRITE(reg, val); | |
1727 | } | |
040484af JB |
1728 | } |
1729 | ||
ab4d966c | 1730 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1731 | { |
8fb033d7 PZ |
1732 | u32 val; |
1733 | ||
ab9412ba | 1734 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1735 | val &= ~TRANS_ENABLE; |
ab9412ba | 1736 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1737 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 1738 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 1739 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1740 | |
1741 | /* Workaround: clear timing override bit. */ | |
1742 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1743 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf | 1744 | I915_WRITE(_TRANSA_CHICKEN2, val); |
040484af JB |
1745 | } |
1746 | ||
b24e7179 | 1747 | /** |
309cfea8 | 1748 | * intel_enable_pipe - enable a pipe, asserting requirements |
b24e7179 JB |
1749 | * @dev_priv: i915 private structure |
1750 | * @pipe: pipe to enable | |
040484af | 1751 | * @pch_port: on ILK+, is this pipe driving a PCH port or not |
b24e7179 JB |
1752 | * |
1753 | * Enable @pipe, making sure that various hardware specific requirements | |
1754 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. | |
1755 | * | |
1756 | * @pipe should be %PIPE_A or %PIPE_B. | |
1757 | * | |
1758 | * Will wait until the pipe is actually running (i.e. first vblank) before | |
1759 | * returning. | |
1760 | */ | |
040484af | 1761 | static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
23538ef1 | 1762 | bool pch_port, bool dsi) |
b24e7179 | 1763 | { |
702e7a56 PZ |
1764 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1765 | pipe); | |
1a240d4d | 1766 | enum pipe pch_transcoder; |
b24e7179 JB |
1767 | int reg; |
1768 | u32 val; | |
1769 | ||
58c6eaa2 | 1770 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 1771 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
1772 | assert_sprites_disabled(dev_priv, pipe); |
1773 | ||
681e5811 | 1774 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
1775 | pch_transcoder = TRANSCODER_A; |
1776 | else | |
1777 | pch_transcoder = pipe; | |
1778 | ||
b24e7179 JB |
1779 | /* |
1780 | * A pipe without a PLL won't actually be able to drive bits from | |
1781 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1782 | * need the check. | |
1783 | */ | |
1784 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
23538ef1 JN |
1785 | if (dsi) |
1786 | assert_dsi_pll_enabled(dev_priv); | |
1787 | else | |
1788 | assert_pll_enabled(dev_priv, pipe); | |
040484af JB |
1789 | else { |
1790 | if (pch_port) { | |
1791 | /* if driving the PCH, we need FDI enabled */ | |
cc391bbb | 1792 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
1793 | assert_fdi_tx_pll_enabled(dev_priv, |
1794 | (enum pipe) cpu_transcoder); | |
040484af JB |
1795 | } |
1796 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1797 | } | |
b24e7179 | 1798 | |
702e7a56 | 1799 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1800 | val = I915_READ(reg); |
00d70b15 CW |
1801 | if (val & PIPECONF_ENABLE) |
1802 | return; | |
1803 | ||
1804 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
b24e7179 JB |
1805 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1806 | } | |
1807 | ||
1808 | /** | |
309cfea8 | 1809 | * intel_disable_pipe - disable a pipe, asserting requirements |
b24e7179 JB |
1810 | * @dev_priv: i915 private structure |
1811 | * @pipe: pipe to disable | |
1812 | * | |
1813 | * Disable @pipe, making sure that various hardware specific requirements | |
1814 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. | |
1815 | * | |
1816 | * @pipe should be %PIPE_A or %PIPE_B. | |
1817 | * | |
1818 | * Will wait until the pipe has shut down before returning. | |
1819 | */ | |
1820 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, | |
1821 | enum pipe pipe) | |
1822 | { | |
702e7a56 PZ |
1823 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1824 | pipe); | |
b24e7179 JB |
1825 | int reg; |
1826 | u32 val; | |
1827 | ||
1828 | /* | |
1829 | * Make sure planes won't keep trying to pump pixels to us, | |
1830 | * or we might hang the display. | |
1831 | */ | |
1832 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 1833 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 1834 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 JB |
1835 | |
1836 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
1837 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1838 | return; | |
1839 | ||
702e7a56 | 1840 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1841 | val = I915_READ(reg); |
00d70b15 CW |
1842 | if ((val & PIPECONF_ENABLE) == 0) |
1843 | return; | |
1844 | ||
1845 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); | |
b24e7179 JB |
1846 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
1847 | } | |
1848 | ||
d74362c9 KP |
1849 | /* |
1850 | * Plane regs are double buffered, going from enabled->disabled needs a | |
1851 | * trigger in order to latch. The display address reg provides this. | |
1852 | */ | |
1dba99f4 VS |
1853 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
1854 | enum plane plane) | |
d74362c9 | 1855 | { |
3d13ef2e DL |
1856 | struct drm_device *dev = dev_priv->dev; |
1857 | u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); | |
1dba99f4 VS |
1858 | |
1859 | I915_WRITE(reg, I915_READ(reg)); | |
1860 | POSTING_READ(reg); | |
d74362c9 KP |
1861 | } |
1862 | ||
b24e7179 | 1863 | /** |
d1de00ef | 1864 | * intel_enable_primary_plane - enable the primary plane on a given pipe |
b24e7179 JB |
1865 | * @dev_priv: i915 private structure |
1866 | * @plane: plane to enable | |
1867 | * @pipe: pipe being fed | |
1868 | * | |
1869 | * Enable @plane on @pipe, making sure that @pipe is running first. | |
1870 | */ | |
d1de00ef VS |
1871 | static void intel_enable_primary_plane(struct drm_i915_private *dev_priv, |
1872 | enum plane plane, enum pipe pipe) | |
b24e7179 | 1873 | { |
939c2fe8 VS |
1874 | struct intel_crtc *intel_crtc = |
1875 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
b24e7179 JB |
1876 | int reg; |
1877 | u32 val; | |
1878 | ||
1879 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
1880 | assert_pipe_enabled(dev_priv, pipe); | |
1881 | ||
4c445e0e | 1882 | WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n"); |
0037f71c | 1883 | |
4c445e0e | 1884 | intel_crtc->primary_enabled = true; |
939c2fe8 | 1885 | |
b24e7179 JB |
1886 | reg = DSPCNTR(plane); |
1887 | val = I915_READ(reg); | |
00d70b15 CW |
1888 | if (val & DISPLAY_PLANE_ENABLE) |
1889 | return; | |
1890 | ||
1891 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); | |
1dba99f4 | 1892 | intel_flush_primary_plane(dev_priv, plane); |
b24e7179 JB |
1893 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1894 | } | |
1895 | ||
b24e7179 | 1896 | /** |
d1de00ef | 1897 | * intel_disable_primary_plane - disable the primary plane |
b24e7179 JB |
1898 | * @dev_priv: i915 private structure |
1899 | * @plane: plane to disable | |
1900 | * @pipe: pipe consuming the data | |
1901 | * | |
1902 | * Disable @plane; should be an independent operation. | |
1903 | */ | |
d1de00ef VS |
1904 | static void intel_disable_primary_plane(struct drm_i915_private *dev_priv, |
1905 | enum plane plane, enum pipe pipe) | |
b24e7179 | 1906 | { |
939c2fe8 VS |
1907 | struct intel_crtc *intel_crtc = |
1908 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
b24e7179 JB |
1909 | int reg; |
1910 | u32 val; | |
1911 | ||
4c445e0e | 1912 | WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n"); |
0037f71c | 1913 | |
4c445e0e | 1914 | intel_crtc->primary_enabled = false; |
939c2fe8 | 1915 | |
b24e7179 JB |
1916 | reg = DSPCNTR(plane); |
1917 | val = I915_READ(reg); | |
00d70b15 CW |
1918 | if ((val & DISPLAY_PLANE_ENABLE) == 0) |
1919 | return; | |
1920 | ||
1921 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); | |
1dba99f4 | 1922 | intel_flush_primary_plane(dev_priv, plane); |
b24e7179 JB |
1923 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1924 | } | |
1925 | ||
693db184 CW |
1926 | static bool need_vtd_wa(struct drm_device *dev) |
1927 | { | |
1928 | #ifdef CONFIG_INTEL_IOMMU | |
1929 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
1930 | return true; | |
1931 | #endif | |
1932 | return false; | |
1933 | } | |
1934 | ||
a57ce0b2 JB |
1935 | static int intel_align_height(struct drm_device *dev, int height, bool tiled) |
1936 | { | |
1937 | int tile_height; | |
1938 | ||
1939 | tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1; | |
1940 | return ALIGN(height, tile_height); | |
1941 | } | |
1942 | ||
127bd2ac | 1943 | int |
48b956c5 | 1944 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
05394f39 | 1945 | struct drm_i915_gem_object *obj, |
919926ae | 1946 | struct intel_ring_buffer *pipelined) |
6b95a207 | 1947 | { |
ce453d81 | 1948 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
1949 | u32 alignment; |
1950 | int ret; | |
1951 | ||
05394f39 | 1952 | switch (obj->tiling_mode) { |
6b95a207 | 1953 | case I915_TILING_NONE: |
534843da CW |
1954 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
1955 | alignment = 128 * 1024; | |
a6c45cf0 | 1956 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
1957 | alignment = 4 * 1024; |
1958 | else | |
1959 | alignment = 64 * 1024; | |
6b95a207 KH |
1960 | break; |
1961 | case I915_TILING_X: | |
1962 | /* pin() will align the object as required by fence */ | |
1963 | alignment = 0; | |
1964 | break; | |
1965 | case I915_TILING_Y: | |
80075d49 | 1966 | WARN(1, "Y tiled bo slipped through, driver bug!\n"); |
6b95a207 KH |
1967 | return -EINVAL; |
1968 | default: | |
1969 | BUG(); | |
1970 | } | |
1971 | ||
693db184 CW |
1972 | /* Note that the w/a also requires 64 PTE of padding following the |
1973 | * bo. We currently fill all unused PTE with the shadow page and so | |
1974 | * we should always have valid PTE following the scanout preventing | |
1975 | * the VT-d warning. | |
1976 | */ | |
1977 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
1978 | alignment = 256 * 1024; | |
1979 | ||
ce453d81 | 1980 | dev_priv->mm.interruptible = false; |
2da3b9b9 | 1981 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
48b956c5 | 1982 | if (ret) |
ce453d81 | 1983 | goto err_interruptible; |
6b95a207 KH |
1984 | |
1985 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
1986 | * fence, whereas 965+ only requires a fence if using | |
1987 | * framebuffer compression. For simplicity, we always install | |
1988 | * a fence as the cost is not that onerous. | |
1989 | */ | |
06d98131 | 1990 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
1991 | if (ret) |
1992 | goto err_unpin; | |
1690e1eb | 1993 | |
9a5a53b3 | 1994 | i915_gem_object_pin_fence(obj); |
6b95a207 | 1995 | |
ce453d81 | 1996 | dev_priv->mm.interruptible = true; |
6b95a207 | 1997 | return 0; |
48b956c5 CW |
1998 | |
1999 | err_unpin: | |
cc98b413 | 2000 | i915_gem_object_unpin_from_display_plane(obj); |
ce453d81 CW |
2001 | err_interruptible: |
2002 | dev_priv->mm.interruptible = true; | |
48b956c5 | 2003 | return ret; |
6b95a207 KH |
2004 | } |
2005 | ||
1690e1eb CW |
2006 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
2007 | { | |
2008 | i915_gem_object_unpin_fence(obj); | |
cc98b413 | 2009 | i915_gem_object_unpin_from_display_plane(obj); |
1690e1eb CW |
2010 | } |
2011 | ||
c2c75131 DV |
2012 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2013 | * is assumed to be a power-of-two. */ | |
bc752862 CW |
2014 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
2015 | unsigned int tiling_mode, | |
2016 | unsigned int cpp, | |
2017 | unsigned int pitch) | |
c2c75131 | 2018 | { |
bc752862 CW |
2019 | if (tiling_mode != I915_TILING_NONE) { |
2020 | unsigned int tile_rows, tiles; | |
c2c75131 | 2021 | |
bc752862 CW |
2022 | tile_rows = *y / 8; |
2023 | *y %= 8; | |
c2c75131 | 2024 | |
bc752862 CW |
2025 | tiles = *x / (512/cpp); |
2026 | *x %= 512/cpp; | |
2027 | ||
2028 | return tile_rows * pitch * 8 + tiles * 4096; | |
2029 | } else { | |
2030 | unsigned int offset; | |
2031 | ||
2032 | offset = *y * pitch + *x * cpp; | |
2033 | *y = 0; | |
2034 | *x = (offset & 4095) / cpp; | |
2035 | return offset & -4096; | |
2036 | } | |
c2c75131 DV |
2037 | } |
2038 | ||
17638cd6 JB |
2039 | static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
2040 | int x, int y) | |
81255565 JB |
2041 | { |
2042 | struct drm_device *dev = crtc->dev; | |
2043 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2044 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2045 | struct intel_framebuffer *intel_fb; | |
05394f39 | 2046 | struct drm_i915_gem_object *obj; |
81255565 | 2047 | int plane = intel_crtc->plane; |
e506a0c6 | 2048 | unsigned long linear_offset; |
81255565 | 2049 | u32 dspcntr; |
5eddb70b | 2050 | u32 reg; |
81255565 JB |
2051 | |
2052 | switch (plane) { | |
2053 | case 0: | |
2054 | case 1: | |
2055 | break; | |
2056 | default: | |
84f44ce7 | 2057 | DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane)); |
81255565 JB |
2058 | return -EINVAL; |
2059 | } | |
2060 | ||
2061 | intel_fb = to_intel_framebuffer(fb); | |
2062 | obj = intel_fb->obj; | |
81255565 | 2063 | |
5eddb70b CW |
2064 | reg = DSPCNTR(plane); |
2065 | dspcntr = I915_READ(reg); | |
81255565 JB |
2066 | /* Mask out pixel format bits in case we change it */ |
2067 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
57779d06 VS |
2068 | switch (fb->pixel_format) { |
2069 | case DRM_FORMAT_C8: | |
81255565 JB |
2070 | dspcntr |= DISPPLANE_8BPP; |
2071 | break; | |
57779d06 VS |
2072 | case DRM_FORMAT_XRGB1555: |
2073 | case DRM_FORMAT_ARGB1555: | |
2074 | dspcntr |= DISPPLANE_BGRX555; | |
81255565 | 2075 | break; |
57779d06 VS |
2076 | case DRM_FORMAT_RGB565: |
2077 | dspcntr |= DISPPLANE_BGRX565; | |
2078 | break; | |
2079 | case DRM_FORMAT_XRGB8888: | |
2080 | case DRM_FORMAT_ARGB8888: | |
2081 | dspcntr |= DISPPLANE_BGRX888; | |
2082 | break; | |
2083 | case DRM_FORMAT_XBGR8888: | |
2084 | case DRM_FORMAT_ABGR8888: | |
2085 | dspcntr |= DISPPLANE_RGBX888; | |
2086 | break; | |
2087 | case DRM_FORMAT_XRGB2101010: | |
2088 | case DRM_FORMAT_ARGB2101010: | |
2089 | dspcntr |= DISPPLANE_BGRX101010; | |
2090 | break; | |
2091 | case DRM_FORMAT_XBGR2101010: | |
2092 | case DRM_FORMAT_ABGR2101010: | |
2093 | dspcntr |= DISPPLANE_RGBX101010; | |
81255565 JB |
2094 | break; |
2095 | default: | |
baba133a | 2096 | BUG(); |
81255565 | 2097 | } |
57779d06 | 2098 | |
a6c45cf0 | 2099 | if (INTEL_INFO(dev)->gen >= 4) { |
05394f39 | 2100 | if (obj->tiling_mode != I915_TILING_NONE) |
81255565 JB |
2101 | dspcntr |= DISPPLANE_TILED; |
2102 | else | |
2103 | dspcntr &= ~DISPPLANE_TILED; | |
2104 | } | |
2105 | ||
de1aa629 VS |
2106 | if (IS_G4X(dev)) |
2107 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2108 | ||
5eddb70b | 2109 | I915_WRITE(reg, dspcntr); |
81255565 | 2110 | |
e506a0c6 | 2111 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
81255565 | 2112 | |
c2c75131 DV |
2113 | if (INTEL_INFO(dev)->gen >= 4) { |
2114 | intel_crtc->dspaddr_offset = | |
bc752862 CW |
2115 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2116 | fb->bits_per_pixel / 8, | |
2117 | fb->pitches[0]); | |
c2c75131 DV |
2118 | linear_offset -= intel_crtc->dspaddr_offset; |
2119 | } else { | |
e506a0c6 | 2120 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2121 | } |
e506a0c6 | 2122 | |
f343c5f6 BW |
2123 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2124 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2125 | fb->pitches[0]); | |
01f2c773 | 2126 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2127 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2128 | I915_WRITE(DSPSURF(plane), |
2129 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2130 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2131 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2132 | } else |
f343c5f6 | 2133 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2134 | POSTING_READ(reg); |
81255565 | 2135 | |
17638cd6 JB |
2136 | return 0; |
2137 | } | |
2138 | ||
2139 | static int ironlake_update_plane(struct drm_crtc *crtc, | |
2140 | struct drm_framebuffer *fb, int x, int y) | |
2141 | { | |
2142 | struct drm_device *dev = crtc->dev; | |
2143 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2144 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2145 | struct intel_framebuffer *intel_fb; | |
2146 | struct drm_i915_gem_object *obj; | |
2147 | int plane = intel_crtc->plane; | |
e506a0c6 | 2148 | unsigned long linear_offset; |
17638cd6 JB |
2149 | u32 dspcntr; |
2150 | u32 reg; | |
2151 | ||
2152 | switch (plane) { | |
2153 | case 0: | |
2154 | case 1: | |
27f8227b | 2155 | case 2: |
17638cd6 JB |
2156 | break; |
2157 | default: | |
84f44ce7 | 2158 | DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane)); |
17638cd6 JB |
2159 | return -EINVAL; |
2160 | } | |
2161 | ||
2162 | intel_fb = to_intel_framebuffer(fb); | |
2163 | obj = intel_fb->obj; | |
2164 | ||
2165 | reg = DSPCNTR(plane); | |
2166 | dspcntr = I915_READ(reg); | |
2167 | /* Mask out pixel format bits in case we change it */ | |
2168 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
57779d06 VS |
2169 | switch (fb->pixel_format) { |
2170 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2171 | dspcntr |= DISPPLANE_8BPP; |
2172 | break; | |
57779d06 VS |
2173 | case DRM_FORMAT_RGB565: |
2174 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2175 | break; |
57779d06 VS |
2176 | case DRM_FORMAT_XRGB8888: |
2177 | case DRM_FORMAT_ARGB8888: | |
2178 | dspcntr |= DISPPLANE_BGRX888; | |
2179 | break; | |
2180 | case DRM_FORMAT_XBGR8888: | |
2181 | case DRM_FORMAT_ABGR8888: | |
2182 | dspcntr |= DISPPLANE_RGBX888; | |
2183 | break; | |
2184 | case DRM_FORMAT_XRGB2101010: | |
2185 | case DRM_FORMAT_ARGB2101010: | |
2186 | dspcntr |= DISPPLANE_BGRX101010; | |
2187 | break; | |
2188 | case DRM_FORMAT_XBGR2101010: | |
2189 | case DRM_FORMAT_ABGR2101010: | |
2190 | dspcntr |= DISPPLANE_RGBX101010; | |
17638cd6 JB |
2191 | break; |
2192 | default: | |
baba133a | 2193 | BUG(); |
17638cd6 JB |
2194 | } |
2195 | ||
2196 | if (obj->tiling_mode != I915_TILING_NONE) | |
2197 | dspcntr |= DISPPLANE_TILED; | |
2198 | else | |
2199 | dspcntr &= ~DISPPLANE_TILED; | |
2200 | ||
b42c6009 | 2201 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
1f5d76db PZ |
2202 | dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE; |
2203 | else | |
2204 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
17638cd6 JB |
2205 | |
2206 | I915_WRITE(reg, dspcntr); | |
2207 | ||
e506a0c6 | 2208 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
c2c75131 | 2209 | intel_crtc->dspaddr_offset = |
bc752862 CW |
2210 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2211 | fb->bits_per_pixel / 8, | |
2212 | fb->pitches[0]); | |
c2c75131 | 2213 | linear_offset -= intel_crtc->dspaddr_offset; |
17638cd6 | 2214 | |
f343c5f6 BW |
2215 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2216 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2217 | fb->pitches[0]); | |
01f2c773 | 2218 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2219 | I915_WRITE(DSPSURF(plane), |
2220 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2221 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2222 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2223 | } else { | |
2224 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2225 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2226 | } | |
17638cd6 JB |
2227 | POSTING_READ(reg); |
2228 | ||
2229 | return 0; | |
2230 | } | |
2231 | ||
2232 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ | |
2233 | static int | |
2234 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
2235 | int x, int y, enum mode_set_atomic state) | |
2236 | { | |
2237 | struct drm_device *dev = crtc->dev; | |
2238 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 2239 | |
6b8e6ed0 CW |
2240 | if (dev_priv->display.disable_fbc) |
2241 | dev_priv->display.disable_fbc(dev); | |
3dec0095 | 2242 | intel_increase_pllclock(crtc); |
81255565 | 2243 | |
6b8e6ed0 | 2244 | return dev_priv->display.update_plane(crtc, fb, x, y); |
81255565 JB |
2245 | } |
2246 | ||
96a02917 VS |
2247 | void intel_display_handle_reset(struct drm_device *dev) |
2248 | { | |
2249 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2250 | struct drm_crtc *crtc; | |
2251 | ||
2252 | /* | |
2253 | * Flips in the rings have been nuked by the reset, | |
2254 | * so complete all pending flips so that user space | |
2255 | * will get its events and not get stuck. | |
2256 | * | |
2257 | * Also update the base address of all primary | |
2258 | * planes to the the last fb to make sure we're | |
2259 | * showing the correct fb after a reset. | |
2260 | * | |
2261 | * Need to make two loops over the crtcs so that we | |
2262 | * don't try to grab a crtc mutex before the | |
2263 | * pending_flip_queue really got woken up. | |
2264 | */ | |
2265 | ||
2266 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2267 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2268 | enum plane plane = intel_crtc->plane; | |
2269 | ||
2270 | intel_prepare_page_flip(dev, plane); | |
2271 | intel_finish_page_flip_plane(dev, plane); | |
2272 | } | |
2273 | ||
2274 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2275 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2276 | ||
2277 | mutex_lock(&crtc->mutex); | |
947fdaad CW |
2278 | /* |
2279 | * FIXME: Once we have proper support for primary planes (and | |
2280 | * disabling them without disabling the entire crtc) allow again | |
2281 | * a NULL crtc->fb. | |
2282 | */ | |
2283 | if (intel_crtc->active && crtc->fb) | |
96a02917 VS |
2284 | dev_priv->display.update_plane(crtc, crtc->fb, |
2285 | crtc->x, crtc->y); | |
2286 | mutex_unlock(&crtc->mutex); | |
2287 | } | |
2288 | } | |
2289 | ||
14667a4b CW |
2290 | static int |
2291 | intel_finish_fb(struct drm_framebuffer *old_fb) | |
2292 | { | |
2293 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; | |
2294 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2295 | bool was_interruptible = dev_priv->mm.interruptible; | |
2296 | int ret; | |
2297 | ||
14667a4b CW |
2298 | /* Big Hammer, we also need to ensure that any pending |
2299 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
2300 | * current scanout is retired before unpinning the old | |
2301 | * framebuffer. | |
2302 | * | |
2303 | * This should only fail upon a hung GPU, in which case we | |
2304 | * can safely continue. | |
2305 | */ | |
2306 | dev_priv->mm.interruptible = false; | |
2307 | ret = i915_gem_object_finish_gpu(obj); | |
2308 | dev_priv->mm.interruptible = was_interruptible; | |
2309 | ||
2310 | return ret; | |
2311 | } | |
2312 | ||
198598d0 VS |
2313 | static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y) |
2314 | { | |
2315 | struct drm_device *dev = crtc->dev; | |
2316 | struct drm_i915_master_private *master_priv; | |
2317 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2318 | ||
2319 | if (!dev->primary->master) | |
2320 | return; | |
2321 | ||
2322 | master_priv = dev->primary->master->driver_priv; | |
2323 | if (!master_priv->sarea_priv) | |
2324 | return; | |
2325 | ||
2326 | switch (intel_crtc->pipe) { | |
2327 | case 0: | |
2328 | master_priv->sarea_priv->pipeA_x = x; | |
2329 | master_priv->sarea_priv->pipeA_y = y; | |
2330 | break; | |
2331 | case 1: | |
2332 | master_priv->sarea_priv->pipeB_x = x; | |
2333 | master_priv->sarea_priv->pipeB_y = y; | |
2334 | break; | |
2335 | default: | |
2336 | break; | |
2337 | } | |
2338 | } | |
2339 | ||
5c3b82e2 | 2340 | static int |
3c4fdcfb | 2341 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
94352cf9 | 2342 | struct drm_framebuffer *fb) |
79e53945 JB |
2343 | { |
2344 | struct drm_device *dev = crtc->dev; | |
6b8e6ed0 | 2345 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 2346 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
94352cf9 | 2347 | struct drm_framebuffer *old_fb; |
5c3b82e2 | 2348 | int ret; |
79e53945 JB |
2349 | |
2350 | /* no fb bound */ | |
94352cf9 | 2351 | if (!fb) { |
a5071c2f | 2352 | DRM_ERROR("No FB bound\n"); |
5c3b82e2 CW |
2353 | return 0; |
2354 | } | |
2355 | ||
7eb552ae | 2356 | if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) { |
84f44ce7 VS |
2357 | DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n", |
2358 | plane_name(intel_crtc->plane), | |
2359 | INTEL_INFO(dev)->num_pipes); | |
5c3b82e2 | 2360 | return -EINVAL; |
79e53945 JB |
2361 | } |
2362 | ||
5c3b82e2 | 2363 | mutex_lock(&dev->struct_mutex); |
265db958 | 2364 | ret = intel_pin_and_fence_fb_obj(dev, |
94352cf9 | 2365 | to_intel_framebuffer(fb)->obj, |
919926ae | 2366 | NULL); |
5c3b82e2 CW |
2367 | if (ret != 0) { |
2368 | mutex_unlock(&dev->struct_mutex); | |
a5071c2f | 2369 | DRM_ERROR("pin & fence failed\n"); |
5c3b82e2 CW |
2370 | return ret; |
2371 | } | |
79e53945 | 2372 | |
bb2043de DL |
2373 | /* |
2374 | * Update pipe size and adjust fitter if needed: the reason for this is | |
2375 | * that in compute_mode_changes we check the native mode (not the pfit | |
2376 | * mode) to see if we can flip rather than do a full mode set. In the | |
2377 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
2378 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
2379 | * sized surface. | |
2380 | * | |
2381 | * To fix this properly, we need to hoist the checks up into | |
2382 | * compute_mode_changes (or above), check the actual pfit state and | |
2383 | * whether the platform allows pfit disable with pipe active, and only | |
2384 | * then update the pipesrc and pfit state, even on the flip path. | |
2385 | */ | |
d330a953 | 2386 | if (i915.fastboot) { |
d7bf63f2 DL |
2387 | const struct drm_display_mode *adjusted_mode = |
2388 | &intel_crtc->config.adjusted_mode; | |
2389 | ||
4d6a3e63 | 2390 | I915_WRITE(PIPESRC(intel_crtc->pipe), |
d7bf63f2 DL |
2391 | ((adjusted_mode->crtc_hdisplay - 1) << 16) | |
2392 | (adjusted_mode->crtc_vdisplay - 1)); | |
fd4daa9c | 2393 | if (!intel_crtc->config.pch_pfit.enabled && |
4d6a3e63 JB |
2394 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
2395 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
2396 | I915_WRITE(PF_CTL(intel_crtc->pipe), 0); | |
2397 | I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0); | |
2398 | I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0); | |
2399 | } | |
0637d60d JB |
2400 | intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay; |
2401 | intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay; | |
4d6a3e63 JB |
2402 | } |
2403 | ||
94352cf9 | 2404 | ret = dev_priv->display.update_plane(crtc, fb, x, y); |
4e6cfefc | 2405 | if (ret) { |
94352cf9 | 2406 | intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj); |
5c3b82e2 | 2407 | mutex_unlock(&dev->struct_mutex); |
a5071c2f | 2408 | DRM_ERROR("failed to update base address\n"); |
4e6cfefc | 2409 | return ret; |
79e53945 | 2410 | } |
3c4fdcfb | 2411 | |
94352cf9 DV |
2412 | old_fb = crtc->fb; |
2413 | crtc->fb = fb; | |
6c4c86f5 DV |
2414 | crtc->x = x; |
2415 | crtc->y = y; | |
94352cf9 | 2416 | |
b7f1de28 | 2417 | if (old_fb) { |
d7697eea DV |
2418 | if (intel_crtc->active && old_fb != fb) |
2419 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1690e1eb | 2420 | intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); |
b7f1de28 | 2421 | } |
652c393a | 2422 | |
6b8e6ed0 | 2423 | intel_update_fbc(dev); |
4906557e | 2424 | intel_edp_psr_update(dev); |
5c3b82e2 | 2425 | mutex_unlock(&dev->struct_mutex); |
79e53945 | 2426 | |
198598d0 | 2427 | intel_crtc_update_sarea_pos(crtc, x, y); |
5c3b82e2 CW |
2428 | |
2429 | return 0; | |
79e53945 JB |
2430 | } |
2431 | ||
5e84e1a4 ZW |
2432 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
2433 | { | |
2434 | struct drm_device *dev = crtc->dev; | |
2435 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2436 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2437 | int pipe = intel_crtc->pipe; | |
2438 | u32 reg, temp; | |
2439 | ||
2440 | /* enable normal train */ | |
2441 | reg = FDI_TX_CTL(pipe); | |
2442 | temp = I915_READ(reg); | |
61e499bf | 2443 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
2444 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2445 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
2446 | } else { |
2447 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2448 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 2449 | } |
5e84e1a4 ZW |
2450 | I915_WRITE(reg, temp); |
2451 | ||
2452 | reg = FDI_RX_CTL(pipe); | |
2453 | temp = I915_READ(reg); | |
2454 | if (HAS_PCH_CPT(dev)) { | |
2455 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2456 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
2457 | } else { | |
2458 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2459 | temp |= FDI_LINK_TRAIN_NONE; | |
2460 | } | |
2461 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
2462 | ||
2463 | /* wait one idle pattern time */ | |
2464 | POSTING_READ(reg); | |
2465 | udelay(1000); | |
357555c0 JB |
2466 | |
2467 | /* IVB wants error correction enabled */ | |
2468 | if (IS_IVYBRIDGE(dev)) | |
2469 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
2470 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
2471 | } |
2472 | ||
1fbc0d78 | 2473 | static bool pipe_has_enabled_pch(struct intel_crtc *crtc) |
1e833f40 | 2474 | { |
1fbc0d78 DV |
2475 | return crtc->base.enabled && crtc->active && |
2476 | crtc->config.has_pch_encoder; | |
1e833f40 DV |
2477 | } |
2478 | ||
01a415fd DV |
2479 | static void ivb_modeset_global_resources(struct drm_device *dev) |
2480 | { | |
2481 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2482 | struct intel_crtc *pipe_B_crtc = | |
2483 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
2484 | struct intel_crtc *pipe_C_crtc = | |
2485 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]); | |
2486 | uint32_t temp; | |
2487 | ||
1e833f40 DV |
2488 | /* |
2489 | * When everything is off disable fdi C so that we could enable fdi B | |
2490 | * with all lanes. Note that we don't care about enabled pipes without | |
2491 | * an enabled pch encoder. | |
2492 | */ | |
2493 | if (!pipe_has_enabled_pch(pipe_B_crtc) && | |
2494 | !pipe_has_enabled_pch(pipe_C_crtc)) { | |
01a415fd DV |
2495 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
2496 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
2497 | ||
2498 | temp = I915_READ(SOUTH_CHICKEN1); | |
2499 | temp &= ~FDI_BC_BIFURCATION_SELECT; | |
2500 | DRM_DEBUG_KMS("disabling fdi C rx\n"); | |
2501 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
2502 | } | |
2503 | } | |
2504 | ||
8db9d77b ZW |
2505 | /* The FDI link training functions for ILK/Ibexpeak. */ |
2506 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
2507 | { | |
2508 | struct drm_device *dev = crtc->dev; | |
2509 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2510 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2511 | int pipe = intel_crtc->pipe; | |
0fc932b8 | 2512 | int plane = intel_crtc->plane; |
5eddb70b | 2513 | u32 reg, temp, tries; |
8db9d77b | 2514 | |
0fc932b8 JB |
2515 | /* FDI needs bits from pipe & plane first */ |
2516 | assert_pipe_enabled(dev_priv, pipe); | |
2517 | assert_plane_enabled(dev_priv, plane); | |
2518 | ||
e1a44743 AJ |
2519 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2520 | for train result */ | |
5eddb70b CW |
2521 | reg = FDI_RX_IMR(pipe); |
2522 | temp = I915_READ(reg); | |
e1a44743 AJ |
2523 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2524 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2525 | I915_WRITE(reg, temp); |
2526 | I915_READ(reg); | |
e1a44743 AJ |
2527 | udelay(150); |
2528 | ||
8db9d77b | 2529 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2530 | reg = FDI_TX_CTL(pipe); |
2531 | temp = I915_READ(reg); | |
627eb5a3 DV |
2532 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2533 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
2534 | temp &= ~FDI_LINK_TRAIN_NONE; |
2535 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 2536 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2537 | |
5eddb70b CW |
2538 | reg = FDI_RX_CTL(pipe); |
2539 | temp = I915_READ(reg); | |
8db9d77b ZW |
2540 | temp &= ~FDI_LINK_TRAIN_NONE; |
2541 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
2542 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2543 | ||
2544 | POSTING_READ(reg); | |
8db9d77b ZW |
2545 | udelay(150); |
2546 | ||
5b2adf89 | 2547 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
2548 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
2549 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
2550 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 2551 | |
5eddb70b | 2552 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2553 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2554 | temp = I915_READ(reg); |
8db9d77b ZW |
2555 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2556 | ||
2557 | if ((temp & FDI_RX_BIT_LOCK)) { | |
2558 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 2559 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
2560 | break; |
2561 | } | |
8db9d77b | 2562 | } |
e1a44743 | 2563 | if (tries == 5) |
5eddb70b | 2564 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2565 | |
2566 | /* Train 2 */ | |
5eddb70b CW |
2567 | reg = FDI_TX_CTL(pipe); |
2568 | temp = I915_READ(reg); | |
8db9d77b ZW |
2569 | temp &= ~FDI_LINK_TRAIN_NONE; |
2570 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2571 | I915_WRITE(reg, temp); |
8db9d77b | 2572 | |
5eddb70b CW |
2573 | reg = FDI_RX_CTL(pipe); |
2574 | temp = I915_READ(reg); | |
8db9d77b ZW |
2575 | temp &= ~FDI_LINK_TRAIN_NONE; |
2576 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2577 | I915_WRITE(reg, temp); |
8db9d77b | 2578 | |
5eddb70b CW |
2579 | POSTING_READ(reg); |
2580 | udelay(150); | |
8db9d77b | 2581 | |
5eddb70b | 2582 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2583 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2584 | temp = I915_READ(reg); |
8db9d77b ZW |
2585 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2586 | ||
2587 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 2588 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
2589 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2590 | break; | |
2591 | } | |
8db9d77b | 2592 | } |
e1a44743 | 2593 | if (tries == 5) |
5eddb70b | 2594 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2595 | |
2596 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 2597 | |
8db9d77b ZW |
2598 | } |
2599 | ||
0206e353 | 2600 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
2601 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
2602 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
2603 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
2604 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
2605 | }; | |
2606 | ||
2607 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
2608 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
2609 | { | |
2610 | struct drm_device *dev = crtc->dev; | |
2611 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2612 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2613 | int pipe = intel_crtc->pipe; | |
fa37d39e | 2614 | u32 reg, temp, i, retry; |
8db9d77b | 2615 | |
e1a44743 AJ |
2616 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2617 | for train result */ | |
5eddb70b CW |
2618 | reg = FDI_RX_IMR(pipe); |
2619 | temp = I915_READ(reg); | |
e1a44743 AJ |
2620 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2621 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2622 | I915_WRITE(reg, temp); |
2623 | ||
2624 | POSTING_READ(reg); | |
e1a44743 AJ |
2625 | udelay(150); |
2626 | ||
8db9d77b | 2627 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2628 | reg = FDI_TX_CTL(pipe); |
2629 | temp = I915_READ(reg); | |
627eb5a3 DV |
2630 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2631 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
2632 | temp &= ~FDI_LINK_TRAIN_NONE; |
2633 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2634 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2635 | /* SNB-B */ | |
2636 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 2637 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2638 | |
d74cf324 DV |
2639 | I915_WRITE(FDI_RX_MISC(pipe), |
2640 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
2641 | ||
5eddb70b CW |
2642 | reg = FDI_RX_CTL(pipe); |
2643 | temp = I915_READ(reg); | |
8db9d77b ZW |
2644 | if (HAS_PCH_CPT(dev)) { |
2645 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2646 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2647 | } else { | |
2648 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2649 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2650 | } | |
5eddb70b CW |
2651 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2652 | ||
2653 | POSTING_READ(reg); | |
8db9d77b ZW |
2654 | udelay(150); |
2655 | ||
0206e353 | 2656 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2657 | reg = FDI_TX_CTL(pipe); |
2658 | temp = I915_READ(reg); | |
8db9d77b ZW |
2659 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2660 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2661 | I915_WRITE(reg, temp); |
2662 | ||
2663 | POSTING_READ(reg); | |
8db9d77b ZW |
2664 | udelay(500); |
2665 | ||
fa37d39e SP |
2666 | for (retry = 0; retry < 5; retry++) { |
2667 | reg = FDI_RX_IIR(pipe); | |
2668 | temp = I915_READ(reg); | |
2669 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2670 | if (temp & FDI_RX_BIT_LOCK) { | |
2671 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
2672 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
2673 | break; | |
2674 | } | |
2675 | udelay(50); | |
8db9d77b | 2676 | } |
fa37d39e SP |
2677 | if (retry < 5) |
2678 | break; | |
8db9d77b ZW |
2679 | } |
2680 | if (i == 4) | |
5eddb70b | 2681 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2682 | |
2683 | /* Train 2 */ | |
5eddb70b CW |
2684 | reg = FDI_TX_CTL(pipe); |
2685 | temp = I915_READ(reg); | |
8db9d77b ZW |
2686 | temp &= ~FDI_LINK_TRAIN_NONE; |
2687 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2688 | if (IS_GEN6(dev)) { | |
2689 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2690 | /* SNB-B */ | |
2691 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
2692 | } | |
5eddb70b | 2693 | I915_WRITE(reg, temp); |
8db9d77b | 2694 | |
5eddb70b CW |
2695 | reg = FDI_RX_CTL(pipe); |
2696 | temp = I915_READ(reg); | |
8db9d77b ZW |
2697 | if (HAS_PCH_CPT(dev)) { |
2698 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2699 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
2700 | } else { | |
2701 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2702 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2703 | } | |
5eddb70b CW |
2704 | I915_WRITE(reg, temp); |
2705 | ||
2706 | POSTING_READ(reg); | |
8db9d77b ZW |
2707 | udelay(150); |
2708 | ||
0206e353 | 2709 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2710 | reg = FDI_TX_CTL(pipe); |
2711 | temp = I915_READ(reg); | |
8db9d77b ZW |
2712 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2713 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2714 | I915_WRITE(reg, temp); |
2715 | ||
2716 | POSTING_READ(reg); | |
8db9d77b ZW |
2717 | udelay(500); |
2718 | ||
fa37d39e SP |
2719 | for (retry = 0; retry < 5; retry++) { |
2720 | reg = FDI_RX_IIR(pipe); | |
2721 | temp = I915_READ(reg); | |
2722 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2723 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
2724 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
2725 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
2726 | break; | |
2727 | } | |
2728 | udelay(50); | |
8db9d77b | 2729 | } |
fa37d39e SP |
2730 | if (retry < 5) |
2731 | break; | |
8db9d77b ZW |
2732 | } |
2733 | if (i == 4) | |
5eddb70b | 2734 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2735 | |
2736 | DRM_DEBUG_KMS("FDI train done.\n"); | |
2737 | } | |
2738 | ||
357555c0 JB |
2739 | /* Manual link training for Ivy Bridge A0 parts */ |
2740 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
2741 | { | |
2742 | struct drm_device *dev = crtc->dev; | |
2743 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2744 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2745 | int pipe = intel_crtc->pipe; | |
139ccd3f | 2746 | u32 reg, temp, i, j; |
357555c0 JB |
2747 | |
2748 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
2749 | for train result */ | |
2750 | reg = FDI_RX_IMR(pipe); | |
2751 | temp = I915_READ(reg); | |
2752 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
2753 | temp &= ~FDI_RX_BIT_LOCK; | |
2754 | I915_WRITE(reg, temp); | |
2755 | ||
2756 | POSTING_READ(reg); | |
2757 | udelay(150); | |
2758 | ||
01a415fd DV |
2759 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
2760 | I915_READ(FDI_RX_IIR(pipe))); | |
2761 | ||
139ccd3f JB |
2762 | /* Try each vswing and preemphasis setting twice before moving on */ |
2763 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
2764 | /* disable first in case we need to retry */ | |
2765 | reg = FDI_TX_CTL(pipe); | |
2766 | temp = I915_READ(reg); | |
2767 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
2768 | temp &= ~FDI_TX_ENABLE; | |
2769 | I915_WRITE(reg, temp); | |
357555c0 | 2770 | |
139ccd3f JB |
2771 | reg = FDI_RX_CTL(pipe); |
2772 | temp = I915_READ(reg); | |
2773 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
2774 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2775 | temp &= ~FDI_RX_ENABLE; | |
2776 | I915_WRITE(reg, temp); | |
357555c0 | 2777 | |
139ccd3f | 2778 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
2779 | reg = FDI_TX_CTL(pipe); |
2780 | temp = I915_READ(reg); | |
139ccd3f JB |
2781 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2782 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
2783 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; | |
357555c0 | 2784 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
2785 | temp |= snb_b_fdi_train_param[j/2]; |
2786 | temp |= FDI_COMPOSITE_SYNC; | |
2787 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 2788 | |
139ccd3f JB |
2789 | I915_WRITE(FDI_RX_MISC(pipe), |
2790 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 2791 | |
139ccd3f | 2792 | reg = FDI_RX_CTL(pipe); |
357555c0 | 2793 | temp = I915_READ(reg); |
139ccd3f JB |
2794 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
2795 | temp |= FDI_COMPOSITE_SYNC; | |
2796 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 2797 | |
139ccd3f JB |
2798 | POSTING_READ(reg); |
2799 | udelay(1); /* should be 0.5us */ | |
357555c0 | 2800 | |
139ccd3f JB |
2801 | for (i = 0; i < 4; i++) { |
2802 | reg = FDI_RX_IIR(pipe); | |
2803 | temp = I915_READ(reg); | |
2804 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 2805 | |
139ccd3f JB |
2806 | if (temp & FDI_RX_BIT_LOCK || |
2807 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
2808 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
2809 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
2810 | i); | |
2811 | break; | |
2812 | } | |
2813 | udelay(1); /* should be 0.5us */ | |
2814 | } | |
2815 | if (i == 4) { | |
2816 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
2817 | continue; | |
2818 | } | |
357555c0 | 2819 | |
139ccd3f | 2820 | /* Train 2 */ |
357555c0 JB |
2821 | reg = FDI_TX_CTL(pipe); |
2822 | temp = I915_READ(reg); | |
139ccd3f JB |
2823 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2824 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
2825 | I915_WRITE(reg, temp); | |
2826 | ||
2827 | reg = FDI_RX_CTL(pipe); | |
2828 | temp = I915_READ(reg); | |
2829 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2830 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
2831 | I915_WRITE(reg, temp); |
2832 | ||
2833 | POSTING_READ(reg); | |
139ccd3f | 2834 | udelay(2); /* should be 1.5us */ |
357555c0 | 2835 | |
139ccd3f JB |
2836 | for (i = 0; i < 4; i++) { |
2837 | reg = FDI_RX_IIR(pipe); | |
2838 | temp = I915_READ(reg); | |
2839 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 2840 | |
139ccd3f JB |
2841 | if (temp & FDI_RX_SYMBOL_LOCK || |
2842 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
2843 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
2844 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
2845 | i); | |
2846 | goto train_done; | |
2847 | } | |
2848 | udelay(2); /* should be 1.5us */ | |
357555c0 | 2849 | } |
139ccd3f JB |
2850 | if (i == 4) |
2851 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 2852 | } |
357555c0 | 2853 | |
139ccd3f | 2854 | train_done: |
357555c0 JB |
2855 | DRM_DEBUG_KMS("FDI train done.\n"); |
2856 | } | |
2857 | ||
88cefb6c | 2858 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 2859 | { |
88cefb6c | 2860 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 2861 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 2862 | int pipe = intel_crtc->pipe; |
5eddb70b | 2863 | u32 reg, temp; |
79e53945 | 2864 | |
c64e311e | 2865 | |
c98e9dcf | 2866 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
2867 | reg = FDI_RX_CTL(pipe); |
2868 | temp = I915_READ(reg); | |
627eb5a3 DV |
2869 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
2870 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
dfd07d72 | 2871 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
2872 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
2873 | ||
2874 | POSTING_READ(reg); | |
c98e9dcf JB |
2875 | udelay(200); |
2876 | ||
2877 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
2878 | temp = I915_READ(reg); |
2879 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
2880 | ||
2881 | POSTING_READ(reg); | |
c98e9dcf JB |
2882 | udelay(200); |
2883 | ||
20749730 PZ |
2884 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
2885 | reg = FDI_TX_CTL(pipe); | |
2886 | temp = I915_READ(reg); | |
2887 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
2888 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 2889 | |
20749730 PZ |
2890 | POSTING_READ(reg); |
2891 | udelay(100); | |
6be4a607 | 2892 | } |
0e23b99d JB |
2893 | } |
2894 | ||
88cefb6c DV |
2895 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
2896 | { | |
2897 | struct drm_device *dev = intel_crtc->base.dev; | |
2898 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2899 | int pipe = intel_crtc->pipe; | |
2900 | u32 reg, temp; | |
2901 | ||
2902 | /* Switch from PCDclk to Rawclk */ | |
2903 | reg = FDI_RX_CTL(pipe); | |
2904 | temp = I915_READ(reg); | |
2905 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
2906 | ||
2907 | /* Disable CPU FDI TX PLL */ | |
2908 | reg = FDI_TX_CTL(pipe); | |
2909 | temp = I915_READ(reg); | |
2910 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
2911 | ||
2912 | POSTING_READ(reg); | |
2913 | udelay(100); | |
2914 | ||
2915 | reg = FDI_RX_CTL(pipe); | |
2916 | temp = I915_READ(reg); | |
2917 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
2918 | ||
2919 | /* Wait for the clocks to turn off. */ | |
2920 | POSTING_READ(reg); | |
2921 | udelay(100); | |
2922 | } | |
2923 | ||
0fc932b8 JB |
2924 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
2925 | { | |
2926 | struct drm_device *dev = crtc->dev; | |
2927 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2928 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2929 | int pipe = intel_crtc->pipe; | |
2930 | u32 reg, temp; | |
2931 | ||
2932 | /* disable CPU FDI tx and PCH FDI rx */ | |
2933 | reg = FDI_TX_CTL(pipe); | |
2934 | temp = I915_READ(reg); | |
2935 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
2936 | POSTING_READ(reg); | |
2937 | ||
2938 | reg = FDI_RX_CTL(pipe); | |
2939 | temp = I915_READ(reg); | |
2940 | temp &= ~(0x7 << 16); | |
dfd07d72 | 2941 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
2942 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
2943 | ||
2944 | POSTING_READ(reg); | |
2945 | udelay(100); | |
2946 | ||
2947 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
6f06ce18 JB |
2948 | if (HAS_PCH_IBX(dev)) { |
2949 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); | |
6f06ce18 | 2950 | } |
0fc932b8 JB |
2951 | |
2952 | /* still set train pattern 1 */ | |
2953 | reg = FDI_TX_CTL(pipe); | |
2954 | temp = I915_READ(reg); | |
2955 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2956 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2957 | I915_WRITE(reg, temp); | |
2958 | ||
2959 | reg = FDI_RX_CTL(pipe); | |
2960 | temp = I915_READ(reg); | |
2961 | if (HAS_PCH_CPT(dev)) { | |
2962 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2963 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2964 | } else { | |
2965 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2966 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2967 | } | |
2968 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
2969 | temp &= ~(0x07 << 16); | |
dfd07d72 | 2970 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
2971 | I915_WRITE(reg, temp); |
2972 | ||
2973 | POSTING_READ(reg); | |
2974 | udelay(100); | |
2975 | } | |
2976 | ||
5bb61643 CW |
2977 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
2978 | { | |
2979 | struct drm_device *dev = crtc->dev; | |
2980 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10d83730 | 2981 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5bb61643 CW |
2982 | unsigned long flags; |
2983 | bool pending; | |
2984 | ||
10d83730 VS |
2985 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
2986 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
5bb61643 CW |
2987 | return false; |
2988 | ||
2989 | spin_lock_irqsave(&dev->event_lock, flags); | |
2990 | pending = to_intel_crtc(crtc)->unpin_work != NULL; | |
2991 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
2992 | ||
2993 | return pending; | |
2994 | } | |
2995 | ||
5dce5b93 CW |
2996 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
2997 | { | |
2998 | struct intel_crtc *crtc; | |
2999 | ||
3000 | /* Note that we don't need to be called with mode_config.lock here | |
3001 | * as our list of CRTC objects is static for the lifetime of the | |
3002 | * device and so cannot disappear as we iterate. Similarly, we can | |
3003 | * happily treat the predicates as racy, atomic checks as userspace | |
3004 | * cannot claim and pin a new fb without at least acquring the | |
3005 | * struct_mutex and so serialising with us. | |
3006 | */ | |
3007 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
3008 | if (atomic_read(&crtc->unpin_work_count) == 0) | |
3009 | continue; | |
3010 | ||
3011 | if (crtc->unpin_work) | |
3012 | intel_wait_for_vblank(dev, crtc->pipe); | |
3013 | ||
3014 | return true; | |
3015 | } | |
3016 | ||
3017 | return false; | |
3018 | } | |
3019 | ||
e6c3a2a6 CW |
3020 | static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
3021 | { | |
0f91128d | 3022 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3023 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 CW |
3024 | |
3025 | if (crtc->fb == NULL) | |
3026 | return; | |
3027 | ||
2c10d571 DV |
3028 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
3029 | ||
5bb61643 CW |
3030 | wait_event(dev_priv->pending_flip_queue, |
3031 | !intel_crtc_has_pending_flip(crtc)); | |
3032 | ||
0f91128d CW |
3033 | mutex_lock(&dev->struct_mutex); |
3034 | intel_finish_fb(crtc->fb); | |
3035 | mutex_unlock(&dev->struct_mutex); | |
e6c3a2a6 CW |
3036 | } |
3037 | ||
e615efe4 ED |
3038 | /* Program iCLKIP clock to the desired frequency */ |
3039 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3040 | { | |
3041 | struct drm_device *dev = crtc->dev; | |
3042 | struct drm_i915_private *dev_priv = dev->dev_private; | |
241bfc38 | 3043 | int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock; |
e615efe4 ED |
3044 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3045 | u32 temp; | |
3046 | ||
09153000 DV |
3047 | mutex_lock(&dev_priv->dpio_lock); |
3048 | ||
e615efe4 ED |
3049 | /* It is necessary to ungate the pixclk gate prior to programming |
3050 | * the divisors, and gate it back when it is done. | |
3051 | */ | |
3052 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3053 | ||
3054 | /* Disable SSCCTL */ | |
3055 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
3056 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
3057 | SBI_SSCCTL_DISABLE, | |
3058 | SBI_ICLK); | |
e615efe4 ED |
3059 | |
3060 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3061 | if (clock == 20000) { |
e615efe4 ED |
3062 | auxdiv = 1; |
3063 | divsel = 0x41; | |
3064 | phaseinc = 0x20; | |
3065 | } else { | |
3066 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3067 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3068 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3069 | * convert the virtual clock precision to KHz here for higher |
3070 | * precision. | |
3071 | */ | |
3072 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3073 | u32 iclk_pi_range = 64; | |
3074 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3075 | ||
12d7ceed | 3076 | desired_divisor = (iclk_virtual_root_freq / clock); |
e615efe4 ED |
3077 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3078 | pi_value = desired_divisor % iclk_pi_range; | |
3079 | ||
3080 | auxdiv = 0; | |
3081 | divsel = msb_divisor_value - 2; | |
3082 | phaseinc = pi_value; | |
3083 | } | |
3084 | ||
3085 | /* This should not happen with any sane values */ | |
3086 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3087 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3088 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3089 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3090 | ||
3091 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3092 | clock, |
e615efe4 ED |
3093 | auxdiv, |
3094 | divsel, | |
3095 | phasedir, | |
3096 | phaseinc); | |
3097 | ||
3098 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 3099 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
3100 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3101 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
3102 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
3103 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
3104 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
3105 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 3106 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
3107 | |
3108 | /* Program SSCAUXDIV */ | |
988d6ee8 | 3109 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
3110 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3111 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 3112 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
3113 | |
3114 | /* Enable modulator and associated divider */ | |
988d6ee8 | 3115 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 3116 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 3117 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
3118 | |
3119 | /* Wait for initialization time */ | |
3120 | udelay(24); | |
3121 | ||
3122 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 DV |
3123 | |
3124 | mutex_unlock(&dev_priv->dpio_lock); | |
e615efe4 ED |
3125 | } |
3126 | ||
275f01b2 DV |
3127 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
3128 | enum pipe pch_transcoder) | |
3129 | { | |
3130 | struct drm_device *dev = crtc->base.dev; | |
3131 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3132 | enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; | |
3133 | ||
3134 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
3135 | I915_READ(HTOTAL(cpu_transcoder))); | |
3136 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
3137 | I915_READ(HBLANK(cpu_transcoder))); | |
3138 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
3139 | I915_READ(HSYNC(cpu_transcoder))); | |
3140 | ||
3141 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
3142 | I915_READ(VTOTAL(cpu_transcoder))); | |
3143 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
3144 | I915_READ(VBLANK(cpu_transcoder))); | |
3145 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
3146 | I915_READ(VSYNC(cpu_transcoder))); | |
3147 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
3148 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
3149 | } | |
3150 | ||
1fbc0d78 DV |
3151 | static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev) |
3152 | { | |
3153 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3154 | uint32_t temp; | |
3155 | ||
3156 | temp = I915_READ(SOUTH_CHICKEN1); | |
3157 | if (temp & FDI_BC_BIFURCATION_SELECT) | |
3158 | return; | |
3159 | ||
3160 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
3161 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
3162 | ||
3163 | temp |= FDI_BC_BIFURCATION_SELECT; | |
3164 | DRM_DEBUG_KMS("enabling fdi C rx\n"); | |
3165 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
3166 | POSTING_READ(SOUTH_CHICKEN1); | |
3167 | } | |
3168 | ||
3169 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
3170 | { | |
3171 | struct drm_device *dev = intel_crtc->base.dev; | |
3172 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3173 | ||
3174 | switch (intel_crtc->pipe) { | |
3175 | case PIPE_A: | |
3176 | break; | |
3177 | case PIPE_B: | |
3178 | if (intel_crtc->config.fdi_lanes > 2) | |
3179 | WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); | |
3180 | else | |
3181 | cpt_enable_fdi_bc_bifurcation(dev); | |
3182 | ||
3183 | break; | |
3184 | case PIPE_C: | |
3185 | cpt_enable_fdi_bc_bifurcation(dev); | |
3186 | ||
3187 | break; | |
3188 | default: | |
3189 | BUG(); | |
3190 | } | |
3191 | } | |
3192 | ||
f67a559d JB |
3193 | /* |
3194 | * Enable PCH resources required for PCH ports: | |
3195 | * - PCH PLLs | |
3196 | * - FDI training & RX/TX | |
3197 | * - update transcoder timings | |
3198 | * - DP transcoding bits | |
3199 | * - transcoder | |
3200 | */ | |
3201 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
3202 | { |
3203 | struct drm_device *dev = crtc->dev; | |
3204 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3205 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3206 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 3207 | u32 reg, temp; |
2c07245f | 3208 | |
ab9412ba | 3209 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 3210 | |
1fbc0d78 DV |
3211 | if (IS_IVYBRIDGE(dev)) |
3212 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
3213 | ||
cd986abb DV |
3214 | /* Write the TU size bits before fdi link training, so that error |
3215 | * detection works. */ | |
3216 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
3217 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
3218 | ||
c98e9dcf | 3219 | /* For PCH output, training FDI link */ |
674cf967 | 3220 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 3221 | |
3ad8a208 DV |
3222 | /* We need to program the right clock selection before writing the pixel |
3223 | * mutliplier into the DPLL. */ | |
303b81e0 | 3224 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 3225 | u32 sel; |
4b645f14 | 3226 | |
c98e9dcf | 3227 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
3228 | temp |= TRANS_DPLL_ENABLE(pipe); |
3229 | sel = TRANS_DPLLB_SEL(pipe); | |
a43f6e0f | 3230 | if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
3231 | temp |= sel; |
3232 | else | |
3233 | temp &= ~sel; | |
c98e9dcf | 3234 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 3235 | } |
5eddb70b | 3236 | |
3ad8a208 DV |
3237 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
3238 | * transcoder, and we actually should do this to not upset any PCH | |
3239 | * transcoder that already use the clock when we share it. | |
3240 | * | |
3241 | * Note that enable_shared_dpll tries to do the right thing, but | |
3242 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
3243 | * the right LVDS enable sequence. */ | |
3244 | ironlake_enable_shared_dpll(intel_crtc); | |
3245 | ||
d9b6cb56 JB |
3246 | /* set transcoder timing, panel must allow it */ |
3247 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 3248 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 3249 | |
303b81e0 | 3250 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 3251 | |
c98e9dcf JB |
3252 | /* For PCH DP, enable TRANS_DP_CTL */ |
3253 | if (HAS_PCH_CPT(dev) && | |
417e822d KP |
3254 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
3255 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
dfd07d72 | 3256 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
5eddb70b CW |
3257 | reg = TRANS_DP_CTL(pipe); |
3258 | temp = I915_READ(reg); | |
3259 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
3260 | TRANS_DP_SYNC_MASK | |
3261 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
3262 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
3263 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 3264 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
3265 | |
3266 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 3267 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 3268 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 3269 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
3270 | |
3271 | switch (intel_trans_dp_port_sel(crtc)) { | |
3272 | case PCH_DP_B: | |
5eddb70b | 3273 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
3274 | break; |
3275 | case PCH_DP_C: | |
5eddb70b | 3276 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
3277 | break; |
3278 | case PCH_DP_D: | |
5eddb70b | 3279 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
3280 | break; |
3281 | default: | |
e95d41e1 | 3282 | BUG(); |
32f9d658 | 3283 | } |
2c07245f | 3284 | |
5eddb70b | 3285 | I915_WRITE(reg, temp); |
6be4a607 | 3286 | } |
b52eb4dc | 3287 | |
b8a4f404 | 3288 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
3289 | } |
3290 | ||
1507e5bd PZ |
3291 | static void lpt_pch_enable(struct drm_crtc *crtc) |
3292 | { | |
3293 | struct drm_device *dev = crtc->dev; | |
3294 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3295 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3b117c8f | 3296 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
1507e5bd | 3297 | |
ab9412ba | 3298 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 3299 | |
8c52b5e8 | 3300 | lpt_program_iclkip(crtc); |
1507e5bd | 3301 | |
0540e488 | 3302 | /* Set transcoder timing. */ |
275f01b2 | 3303 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 3304 | |
937bb610 | 3305 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
3306 | } |
3307 | ||
e2b78267 | 3308 | static void intel_put_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3309 | { |
e2b78267 | 3310 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
ee7b9f93 JB |
3311 | |
3312 | if (pll == NULL) | |
3313 | return; | |
3314 | ||
3315 | if (pll->refcount == 0) { | |
46edb027 | 3316 | WARN(1, "bad %s refcount\n", pll->name); |
ee7b9f93 JB |
3317 | return; |
3318 | } | |
3319 | ||
f4a091c7 DV |
3320 | if (--pll->refcount == 0) { |
3321 | WARN_ON(pll->on); | |
3322 | WARN_ON(pll->active); | |
3323 | } | |
3324 | ||
a43f6e0f | 3325 | crtc->config.shared_dpll = DPLL_ID_PRIVATE; |
ee7b9f93 JB |
3326 | } |
3327 | ||
b89a1d39 | 3328 | static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3329 | { |
e2b78267 DV |
3330 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
3331 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
3332 | enum intel_dpll_id i; | |
ee7b9f93 | 3333 | |
ee7b9f93 | 3334 | if (pll) { |
46edb027 DV |
3335 | DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n", |
3336 | crtc->base.base.id, pll->name); | |
e2b78267 | 3337 | intel_put_shared_dpll(crtc); |
ee7b9f93 JB |
3338 | } |
3339 | ||
98b6bd99 DV |
3340 | if (HAS_PCH_IBX(dev_priv->dev)) { |
3341 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 3342 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 3343 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 3344 | |
46edb027 DV |
3345 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
3346 | crtc->base.base.id, pll->name); | |
98b6bd99 DV |
3347 | |
3348 | goto found; | |
3349 | } | |
3350 | ||
e72f9fbf DV |
3351 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3352 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 JB |
3353 | |
3354 | /* Only want to check enabled timings first */ | |
3355 | if (pll->refcount == 0) | |
3356 | continue; | |
3357 | ||
b89a1d39 DV |
3358 | if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state, |
3359 | sizeof(pll->hw_state)) == 0) { | |
46edb027 | 3360 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n", |
e2b78267 | 3361 | crtc->base.base.id, |
46edb027 | 3362 | pll->name, pll->refcount, pll->active); |
ee7b9f93 JB |
3363 | |
3364 | goto found; | |
3365 | } | |
3366 | } | |
3367 | ||
3368 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
3369 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3370 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 | 3371 | if (pll->refcount == 0) { |
46edb027 DV |
3372 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
3373 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
3374 | goto found; |
3375 | } | |
3376 | } | |
3377 | ||
3378 | return NULL; | |
3379 | ||
3380 | found: | |
a43f6e0f | 3381 | crtc->config.shared_dpll = i; |
46edb027 DV |
3382 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
3383 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 3384 | |
cdbd2316 | 3385 | if (pll->active == 0) { |
66e985c0 DV |
3386 | memcpy(&pll->hw_state, &crtc->config.dpll_hw_state, |
3387 | sizeof(pll->hw_state)); | |
3388 | ||
46edb027 | 3389 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); |
cdbd2316 | 3390 | WARN_ON(pll->on); |
e9d6944e | 3391 | assert_shared_dpll_disabled(dev_priv, pll); |
ee7b9f93 | 3392 | |
15bdd4cf | 3393 | pll->mode_set(dev_priv, pll); |
cdbd2316 DV |
3394 | } |
3395 | pll->refcount++; | |
e04c7350 | 3396 | |
ee7b9f93 JB |
3397 | return pll; |
3398 | } | |
3399 | ||
a1520318 | 3400 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
3401 | { |
3402 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 3403 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
3404 | u32 temp; |
3405 | ||
3406 | temp = I915_READ(dslreg); | |
3407 | udelay(500); | |
3408 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 3409 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 3410 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
3411 | } |
3412 | } | |
3413 | ||
b074cec8 JB |
3414 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
3415 | { | |
3416 | struct drm_device *dev = crtc->base.dev; | |
3417 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3418 | int pipe = crtc->pipe; | |
3419 | ||
fd4daa9c | 3420 | if (crtc->config.pch_pfit.enabled) { |
b074cec8 JB |
3421 | /* Force use of hard-coded filter coefficients |
3422 | * as some pre-programmed values are broken, | |
3423 | * e.g. x201. | |
3424 | */ | |
3425 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
3426 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
3427 | PF_PIPE_SEL_IVB(pipe)); | |
3428 | else | |
3429 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
3430 | I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos); | |
3431 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size); | |
d4270e57 JB |
3432 | } |
3433 | } | |
3434 | ||
bb53d4ae VS |
3435 | static void intel_enable_planes(struct drm_crtc *crtc) |
3436 | { | |
3437 | struct drm_device *dev = crtc->dev; | |
3438 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
3439 | struct intel_plane *intel_plane; | |
3440 | ||
3441 | list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head) | |
3442 | if (intel_plane->pipe == pipe) | |
3443 | intel_plane_restore(&intel_plane->base); | |
3444 | } | |
3445 | ||
3446 | static void intel_disable_planes(struct drm_crtc *crtc) | |
3447 | { | |
3448 | struct drm_device *dev = crtc->dev; | |
3449 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
3450 | struct intel_plane *intel_plane; | |
3451 | ||
3452 | list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head) | |
3453 | if (intel_plane->pipe == pipe) | |
3454 | intel_plane_disable(&intel_plane->base); | |
3455 | } | |
3456 | ||
20bc8673 | 3457 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
3458 | { |
3459 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
3460 | ||
3461 | if (!crtc->config.ips_enabled) | |
3462 | return; | |
3463 | ||
3464 | /* We can only enable IPS after we enable a plane and wait for a vblank. | |
3465 | * We guarantee that the plane is enabled by calling intel_enable_ips | |
3466 | * only after intel_enable_plane. And intel_enable_plane already waits | |
3467 | * for a vblank, so all we need to do here is to enable the IPS bit. */ | |
3468 | assert_plane_enabled(dev_priv, crtc->plane); | |
2a114cc1 BW |
3469 | if (IS_BROADWELL(crtc->base.dev)) { |
3470 | mutex_lock(&dev_priv->rps.hw_lock); | |
3471 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
3472 | mutex_unlock(&dev_priv->rps.hw_lock); | |
3473 | /* Quoting Art Runyan: "its not safe to expect any particular | |
3474 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
3475 | * mailbox." Moreover, the mailbox may return a bogus state, |
3476 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
3477 | */ |
3478 | } else { | |
3479 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
3480 | /* The bit only becomes 1 in the next vblank, so this wait here | |
3481 | * is essentially intel_wait_for_vblank. If we don't have this | |
3482 | * and don't wait for vblanks until the end of crtc_enable, then | |
3483 | * the HW state readout code will complain that the expected | |
3484 | * IPS_CTL value is not the one we read. */ | |
3485 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
3486 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
3487 | } | |
d77e4531 PZ |
3488 | } |
3489 | ||
20bc8673 | 3490 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
3491 | { |
3492 | struct drm_device *dev = crtc->base.dev; | |
3493 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3494 | ||
3495 | if (!crtc->config.ips_enabled) | |
3496 | return; | |
3497 | ||
3498 | assert_plane_enabled(dev_priv, crtc->plane); | |
2a114cc1 BW |
3499 | if (IS_BROADWELL(crtc->base.dev)) { |
3500 | mutex_lock(&dev_priv->rps.hw_lock); | |
3501 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
3502 | mutex_unlock(&dev_priv->rps.hw_lock); | |
e59150dc | 3503 | } else { |
2a114cc1 | 3504 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
3505 | POSTING_READ(IPS_CTL); |
3506 | } | |
d77e4531 PZ |
3507 | |
3508 | /* We need to wait for a vblank before we can disable the plane. */ | |
3509 | intel_wait_for_vblank(dev, crtc->pipe); | |
3510 | } | |
3511 | ||
3512 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
3513 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
3514 | { | |
3515 | struct drm_device *dev = crtc->dev; | |
3516 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3517 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3518 | enum pipe pipe = intel_crtc->pipe; | |
3519 | int palreg = PALETTE(pipe); | |
3520 | int i; | |
3521 | bool reenable_ips = false; | |
3522 | ||
3523 | /* The clocks have to be on to load the palette. */ | |
3524 | if (!crtc->enabled || !intel_crtc->active) | |
3525 | return; | |
3526 | ||
3527 | if (!HAS_PCH_SPLIT(dev_priv->dev)) { | |
3528 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) | |
3529 | assert_dsi_pll_enabled(dev_priv); | |
3530 | else | |
3531 | assert_pll_enabled(dev_priv, pipe); | |
3532 | } | |
3533 | ||
3534 | /* use legacy palette for Ironlake */ | |
3535 | if (HAS_PCH_SPLIT(dev)) | |
3536 | palreg = LGC_PALETTE(pipe); | |
3537 | ||
3538 | /* Workaround : Do not read or write the pipe palette/gamma data while | |
3539 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
3540 | */ | |
41e6fc4c | 3541 | if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled && |
d77e4531 PZ |
3542 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
3543 | GAMMA_MODE_MODE_SPLIT)) { | |
3544 | hsw_disable_ips(intel_crtc); | |
3545 | reenable_ips = true; | |
3546 | } | |
3547 | ||
3548 | for (i = 0; i < 256; i++) { | |
3549 | I915_WRITE(palreg + 4 * i, | |
3550 | (intel_crtc->lut_r[i] << 16) | | |
3551 | (intel_crtc->lut_g[i] << 8) | | |
3552 | intel_crtc->lut_b[i]); | |
3553 | } | |
3554 | ||
3555 | if (reenable_ips) | |
3556 | hsw_enable_ips(intel_crtc); | |
3557 | } | |
3558 | ||
f67a559d JB |
3559 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
3560 | { | |
3561 | struct drm_device *dev = crtc->dev; | |
3562 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3563 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3564 | struct intel_encoder *encoder; |
f67a559d JB |
3565 | int pipe = intel_crtc->pipe; |
3566 | int plane = intel_crtc->plane; | |
f67a559d | 3567 | |
08a48469 DV |
3568 | WARN_ON(!crtc->enabled); |
3569 | ||
f67a559d JB |
3570 | if (intel_crtc->active) |
3571 | return; | |
3572 | ||
3573 | intel_crtc->active = true; | |
8664281b PZ |
3574 | |
3575 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
3576 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); | |
3577 | ||
f6736a1a | 3578 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
3579 | if (encoder->pre_enable) |
3580 | encoder->pre_enable(encoder); | |
f67a559d | 3581 | |
5bfe2ac0 | 3582 | if (intel_crtc->config.has_pch_encoder) { |
fff367c7 DV |
3583 | /* Note: FDI PLL enabling _must_ be done before we enable the |
3584 | * cpu pipes, hence this is separate from all the other fdi/pch | |
3585 | * enabling. */ | |
88cefb6c | 3586 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
3587 | } else { |
3588 | assert_fdi_tx_disabled(dev_priv, pipe); | |
3589 | assert_fdi_rx_disabled(dev_priv, pipe); | |
3590 | } | |
f67a559d | 3591 | |
b074cec8 | 3592 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 3593 | |
9c54c0dd JB |
3594 | /* |
3595 | * On ILK+ LUT must be loaded before the pipe is running but with | |
3596 | * clocks enabled | |
3597 | */ | |
3598 | intel_crtc_load_lut(crtc); | |
3599 | ||
f37fcc2a | 3600 | intel_update_watermarks(crtc); |
5bfe2ac0 | 3601 | intel_enable_pipe(dev_priv, pipe, |
23538ef1 | 3602 | intel_crtc->config.has_pch_encoder, false); |
d1de00ef | 3603 | intel_enable_primary_plane(dev_priv, plane, pipe); |
bb53d4ae | 3604 | intel_enable_planes(crtc); |
5c38d48c | 3605 | intel_crtc_update_cursor(crtc, true); |
f67a559d | 3606 | |
5bfe2ac0 | 3607 | if (intel_crtc->config.has_pch_encoder) |
f67a559d | 3608 | ironlake_pch_enable(crtc); |
c98e9dcf | 3609 | |
d1ebd816 | 3610 | mutex_lock(&dev->struct_mutex); |
bed4a673 | 3611 | intel_update_fbc(dev); |
d1ebd816 BW |
3612 | mutex_unlock(&dev->struct_mutex); |
3613 | ||
fa5c73b1 DV |
3614 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3615 | encoder->enable(encoder); | |
61b77ddd DV |
3616 | |
3617 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 3618 | cpt_verify_modeset(dev, intel_crtc->pipe); |
6ce94100 DV |
3619 | |
3620 | /* | |
3621 | * There seems to be a race in PCH platform hw (at least on some | |
3622 | * outputs) where an enabled pipe still completes any pageflip right | |
3623 | * away (as if the pipe is off) instead of waiting for vblank. As soon | |
3624 | * as the first vblank happend, everything works as expected. Hence just | |
3625 | * wait for one vblank before returning to avoid strange things | |
3626 | * happening. | |
3627 | */ | |
3628 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
6be4a607 JB |
3629 | } |
3630 | ||
42db64ef PZ |
3631 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
3632 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
3633 | { | |
f5adf94e | 3634 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
3635 | } |
3636 | ||
dda9a66a VS |
3637 | static void haswell_crtc_enable_planes(struct drm_crtc *crtc) |
3638 | { | |
3639 | struct drm_device *dev = crtc->dev; | |
3640 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3641 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3642 | int pipe = intel_crtc->pipe; | |
3643 | int plane = intel_crtc->plane; | |
3644 | ||
d1de00ef | 3645 | intel_enable_primary_plane(dev_priv, plane, pipe); |
dda9a66a VS |
3646 | intel_enable_planes(crtc); |
3647 | intel_crtc_update_cursor(crtc, true); | |
3648 | ||
3649 | hsw_enable_ips(intel_crtc); | |
3650 | ||
3651 | mutex_lock(&dev->struct_mutex); | |
3652 | intel_update_fbc(dev); | |
3653 | mutex_unlock(&dev->struct_mutex); | |
3654 | } | |
3655 | ||
3656 | static void haswell_crtc_disable_planes(struct drm_crtc *crtc) | |
3657 | { | |
3658 | struct drm_device *dev = crtc->dev; | |
3659 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3660 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3661 | int pipe = intel_crtc->pipe; | |
3662 | int plane = intel_crtc->plane; | |
3663 | ||
3664 | intel_crtc_wait_for_pending_flips(crtc); | |
3665 | drm_vblank_off(dev, pipe); | |
3666 | ||
3667 | /* FBC must be disabled before disabling the plane on HSW. */ | |
3668 | if (dev_priv->fbc.plane == plane) | |
3669 | intel_disable_fbc(dev); | |
3670 | ||
3671 | hsw_disable_ips(intel_crtc); | |
3672 | ||
3673 | intel_crtc_update_cursor(crtc, false); | |
3674 | intel_disable_planes(crtc); | |
d1de00ef | 3675 | intel_disable_primary_plane(dev_priv, plane, pipe); |
dda9a66a VS |
3676 | } |
3677 | ||
e4916946 PZ |
3678 | /* |
3679 | * This implements the workaround described in the "notes" section of the mode | |
3680 | * set sequence documentation. When going from no pipes or single pipe to | |
3681 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
3682 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
3683 | */ | |
3684 | static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) | |
3685 | { | |
3686 | struct drm_device *dev = crtc->base.dev; | |
3687 | struct intel_crtc *crtc_it, *other_active_crtc = NULL; | |
3688 | ||
3689 | /* We want to get the other_active_crtc only if there's only 1 other | |
3690 | * active crtc. */ | |
3691 | list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) { | |
3692 | if (!crtc_it->active || crtc_it == crtc) | |
3693 | continue; | |
3694 | ||
3695 | if (other_active_crtc) | |
3696 | return; | |
3697 | ||
3698 | other_active_crtc = crtc_it; | |
3699 | } | |
3700 | if (!other_active_crtc) | |
3701 | return; | |
3702 | ||
3703 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
3704 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
3705 | } | |
3706 | ||
4f771f10 PZ |
3707 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
3708 | { | |
3709 | struct drm_device *dev = crtc->dev; | |
3710 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3711 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3712 | struct intel_encoder *encoder; | |
3713 | int pipe = intel_crtc->pipe; | |
4f771f10 PZ |
3714 | |
3715 | WARN_ON(!crtc->enabled); | |
3716 | ||
3717 | if (intel_crtc->active) | |
3718 | return; | |
3719 | ||
3720 | intel_crtc->active = true; | |
8664281b PZ |
3721 | |
3722 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
3723 | if (intel_crtc->config.has_pch_encoder) | |
3724 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); | |
3725 | ||
5bfe2ac0 | 3726 | if (intel_crtc->config.has_pch_encoder) |
04945641 | 3727 | dev_priv->display.fdi_link_train(crtc); |
4f771f10 PZ |
3728 | |
3729 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3730 | if (encoder->pre_enable) | |
3731 | encoder->pre_enable(encoder); | |
3732 | ||
1f544388 | 3733 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 3734 | |
b074cec8 | 3735 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
3736 | |
3737 | /* | |
3738 | * On ILK+ LUT must be loaded before the pipe is running but with | |
3739 | * clocks enabled | |
3740 | */ | |
3741 | intel_crtc_load_lut(crtc); | |
3742 | ||
1f544388 | 3743 | intel_ddi_set_pipe_settings(crtc); |
8228c251 | 3744 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 3745 | |
f37fcc2a | 3746 | intel_update_watermarks(crtc); |
5bfe2ac0 | 3747 | intel_enable_pipe(dev_priv, pipe, |
23538ef1 | 3748 | intel_crtc->config.has_pch_encoder, false); |
42db64ef | 3749 | |
5bfe2ac0 | 3750 | if (intel_crtc->config.has_pch_encoder) |
1507e5bd | 3751 | lpt_pch_enable(crtc); |
4f771f10 | 3752 | |
8807e55b | 3753 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 3754 | encoder->enable(encoder); |
8807e55b JN |
3755 | intel_opregion_notify_encoder(encoder, true); |
3756 | } | |
4f771f10 | 3757 | |
e4916946 PZ |
3758 | /* If we change the relative order between pipe/planes enabling, we need |
3759 | * to change the workaround. */ | |
3760 | haswell_mode_set_planes_workaround(intel_crtc); | |
dda9a66a VS |
3761 | haswell_crtc_enable_planes(crtc); |
3762 | ||
4f771f10 PZ |
3763 | /* |
3764 | * There seems to be a race in PCH platform hw (at least on some | |
3765 | * outputs) where an enabled pipe still completes any pageflip right | |
3766 | * away (as if the pipe is off) instead of waiting for vblank. As soon | |
3767 | * as the first vblank happend, everything works as expected. Hence just | |
3768 | * wait for one vblank before returning to avoid strange things | |
3769 | * happening. | |
3770 | */ | |
3771 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
3772 | } | |
3773 | ||
3f8dce3a DV |
3774 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
3775 | { | |
3776 | struct drm_device *dev = crtc->base.dev; | |
3777 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3778 | int pipe = crtc->pipe; | |
3779 | ||
3780 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
3781 | * it's in use. The hw state code will make sure we get this right. */ | |
fd4daa9c | 3782 | if (crtc->config.pch_pfit.enabled) { |
3f8dce3a DV |
3783 | I915_WRITE(PF_CTL(pipe), 0); |
3784 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
3785 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
3786 | } | |
3787 | } | |
3788 | ||
6be4a607 JB |
3789 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
3790 | { | |
3791 | struct drm_device *dev = crtc->dev; | |
3792 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3793 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3794 | struct intel_encoder *encoder; |
6be4a607 JB |
3795 | int pipe = intel_crtc->pipe; |
3796 | int plane = intel_crtc->plane; | |
5eddb70b | 3797 | u32 reg, temp; |
b52eb4dc | 3798 | |
ef9c3aee | 3799 | |
f7abfe8b CW |
3800 | if (!intel_crtc->active) |
3801 | return; | |
3802 | ||
ea9d758d DV |
3803 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3804 | encoder->disable(encoder); | |
3805 | ||
e6c3a2a6 | 3806 | intel_crtc_wait_for_pending_flips(crtc); |
6be4a607 | 3807 | drm_vblank_off(dev, pipe); |
913d8d11 | 3808 | |
5c3fe8b0 | 3809 | if (dev_priv->fbc.plane == plane) |
973d04f9 | 3810 | intel_disable_fbc(dev); |
2c07245f | 3811 | |
0d5b8c61 | 3812 | intel_crtc_update_cursor(crtc, false); |
bb53d4ae | 3813 | intel_disable_planes(crtc); |
d1de00ef | 3814 | intel_disable_primary_plane(dev_priv, plane, pipe); |
0d5b8c61 | 3815 | |
d925c59a DV |
3816 | if (intel_crtc->config.has_pch_encoder) |
3817 | intel_set_pch_fifo_underrun_reporting(dev, pipe, false); | |
3818 | ||
b24e7179 | 3819 | intel_disable_pipe(dev_priv, pipe); |
32f9d658 | 3820 | |
3f8dce3a | 3821 | ironlake_pfit_disable(intel_crtc); |
2c07245f | 3822 | |
bf49ec8c DV |
3823 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3824 | if (encoder->post_disable) | |
3825 | encoder->post_disable(encoder); | |
2c07245f | 3826 | |
d925c59a DV |
3827 | if (intel_crtc->config.has_pch_encoder) { |
3828 | ironlake_fdi_disable(crtc); | |
913d8d11 | 3829 | |
d925c59a DV |
3830 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
3831 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); | |
6be4a607 | 3832 | |
d925c59a DV |
3833 | if (HAS_PCH_CPT(dev)) { |
3834 | /* disable TRANS_DP_CTL */ | |
3835 | reg = TRANS_DP_CTL(pipe); | |
3836 | temp = I915_READ(reg); | |
3837 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
3838 | TRANS_DP_PORT_SEL_MASK); | |
3839 | temp |= TRANS_DP_PORT_SEL_NONE; | |
3840 | I915_WRITE(reg, temp); | |
3841 | ||
3842 | /* disable DPLL_SEL */ | |
3843 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 3844 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 3845 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 3846 | } |
e3421a18 | 3847 | |
d925c59a | 3848 | /* disable PCH DPLL */ |
e72f9fbf | 3849 | intel_disable_shared_dpll(intel_crtc); |
8db9d77b | 3850 | |
d925c59a DV |
3851 | ironlake_fdi_pll_disable(intel_crtc); |
3852 | } | |
6b383a7f | 3853 | |
f7abfe8b | 3854 | intel_crtc->active = false; |
46ba614c | 3855 | intel_update_watermarks(crtc); |
d1ebd816 BW |
3856 | |
3857 | mutex_lock(&dev->struct_mutex); | |
6b383a7f | 3858 | intel_update_fbc(dev); |
d1ebd816 | 3859 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 3860 | } |
1b3c7a47 | 3861 | |
4f771f10 | 3862 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 3863 | { |
4f771f10 PZ |
3864 | struct drm_device *dev = crtc->dev; |
3865 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 3866 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 PZ |
3867 | struct intel_encoder *encoder; |
3868 | int pipe = intel_crtc->pipe; | |
3b117c8f | 3869 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee7b9f93 | 3870 | |
4f771f10 PZ |
3871 | if (!intel_crtc->active) |
3872 | return; | |
3873 | ||
dda9a66a VS |
3874 | haswell_crtc_disable_planes(crtc); |
3875 | ||
8807e55b JN |
3876 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
3877 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 3878 | encoder->disable(encoder); |
8807e55b | 3879 | } |
4f771f10 | 3880 | |
8664281b PZ |
3881 | if (intel_crtc->config.has_pch_encoder) |
3882 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false); | |
4f771f10 PZ |
3883 | intel_disable_pipe(dev_priv, pipe); |
3884 | ||
ad80a810 | 3885 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 3886 | |
3f8dce3a | 3887 | ironlake_pfit_disable(intel_crtc); |
4f771f10 | 3888 | |
1f544388 | 3889 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 PZ |
3890 | |
3891 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3892 | if (encoder->post_disable) | |
3893 | encoder->post_disable(encoder); | |
3894 | ||
88adfff1 | 3895 | if (intel_crtc->config.has_pch_encoder) { |
ab4d966c | 3896 | lpt_disable_pch_transcoder(dev_priv); |
8664281b | 3897 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
1ad960f2 | 3898 | intel_ddi_fdi_disable(crtc); |
83616634 | 3899 | } |
4f771f10 PZ |
3900 | |
3901 | intel_crtc->active = false; | |
46ba614c | 3902 | intel_update_watermarks(crtc); |
4f771f10 PZ |
3903 | |
3904 | mutex_lock(&dev->struct_mutex); | |
3905 | intel_update_fbc(dev); | |
3906 | mutex_unlock(&dev->struct_mutex); | |
3907 | } | |
3908 | ||
ee7b9f93 JB |
3909 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
3910 | { | |
3911 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e72f9fbf | 3912 | intel_put_shared_dpll(intel_crtc); |
ee7b9f93 JB |
3913 | } |
3914 | ||
6441ab5f PZ |
3915 | static void haswell_crtc_off(struct drm_crtc *crtc) |
3916 | { | |
3917 | intel_ddi_put_crtc_pll(crtc); | |
3918 | } | |
3919 | ||
02e792fb DV |
3920 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
3921 | { | |
02e792fb | 3922 | if (!enable && intel_crtc->overlay) { |
23f09ce3 | 3923 | struct drm_device *dev = intel_crtc->base.dev; |
ce453d81 | 3924 | struct drm_i915_private *dev_priv = dev->dev_private; |
03f77ea5 | 3925 | |
23f09ce3 | 3926 | mutex_lock(&dev->struct_mutex); |
ce453d81 CW |
3927 | dev_priv->mm.interruptible = false; |
3928 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
3929 | dev_priv->mm.interruptible = true; | |
23f09ce3 | 3930 | mutex_unlock(&dev->struct_mutex); |
02e792fb | 3931 | } |
02e792fb | 3932 | |
5dcdbcb0 CW |
3933 | /* Let userspace switch the overlay on again. In most cases userspace |
3934 | * has to recompute where to put it anyway. | |
3935 | */ | |
02e792fb DV |
3936 | } |
3937 | ||
61bc95c1 EE |
3938 | /** |
3939 | * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware | |
3940 | * cursor plane briefly if not already running after enabling the display | |
3941 | * plane. | |
3942 | * This workaround avoids occasional blank screens when self refresh is | |
3943 | * enabled. | |
3944 | */ | |
3945 | static void | |
3946 | g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe) | |
3947 | { | |
3948 | u32 cntl = I915_READ(CURCNTR(pipe)); | |
3949 | ||
3950 | if ((cntl & CURSOR_MODE) == 0) { | |
3951 | u32 fw_bcl_self = I915_READ(FW_BLC_SELF); | |
3952 | ||
3953 | I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN); | |
3954 | I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX); | |
3955 | intel_wait_for_vblank(dev_priv->dev, pipe); | |
3956 | I915_WRITE(CURCNTR(pipe), cntl); | |
3957 | I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); | |
3958 | I915_WRITE(FW_BLC_SELF, fw_bcl_self); | |
3959 | } | |
3960 | } | |
3961 | ||
2dd24552 JB |
3962 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
3963 | { | |
3964 | struct drm_device *dev = crtc->base.dev; | |
3965 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3966 | struct intel_crtc_config *pipe_config = &crtc->config; | |
3967 | ||
328d8e82 | 3968 | if (!crtc->config.gmch_pfit.control) |
2dd24552 JB |
3969 | return; |
3970 | ||
2dd24552 | 3971 | /* |
c0b03411 DV |
3972 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
3973 | * according to register description and PRM. | |
2dd24552 | 3974 | */ |
c0b03411 DV |
3975 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
3976 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 3977 | |
b074cec8 JB |
3978 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
3979 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
3980 | |
3981 | /* Border color in case we don't scale up to the full screen. Black by | |
3982 | * default, change to something else for debugging. */ | |
3983 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
3984 | } |
3985 | ||
586f49dc | 3986 | int valleyview_get_vco(struct drm_i915_private *dev_priv) |
30a970c6 | 3987 | { |
586f49dc | 3988 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
30a970c6 | 3989 | |
586f49dc JB |
3990 | /* Obtain SKU information */ |
3991 | mutex_lock(&dev_priv->dpio_lock); | |
3992 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
3993 | CCK_FUSE_HPLL_FREQ_MASK; | |
3994 | mutex_unlock(&dev_priv->dpio_lock); | |
30a970c6 | 3995 | |
586f49dc | 3996 | return vco_freq[hpll_freq]; |
30a970c6 JB |
3997 | } |
3998 | ||
3999 | /* Adjust CDclk dividers to allow high res or save power if possible */ | |
4000 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
4001 | { | |
4002 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4003 | u32 val, cmd; | |
4004 | ||
4005 | if (cdclk >= 320) /* jump to highest voltage for 400MHz too */ | |
4006 | cmd = 2; | |
4007 | else if (cdclk == 266) | |
4008 | cmd = 1; | |
4009 | else | |
4010 | cmd = 0; | |
4011 | ||
4012 | mutex_lock(&dev_priv->rps.hw_lock); | |
4013 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
4014 | val &= ~DSPFREQGUAR_MASK; | |
4015 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
4016 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
4017 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
4018 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
4019 | 50)) { | |
4020 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
4021 | } | |
4022 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4023 | ||
4024 | if (cdclk == 400) { | |
4025 | u32 divider, vco; | |
4026 | ||
4027 | vco = valleyview_get_vco(dev_priv); | |
4028 | divider = ((vco << 1) / cdclk) - 1; | |
4029 | ||
4030 | mutex_lock(&dev_priv->dpio_lock); | |
4031 | /* adjust cdclk divider */ | |
4032 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
4033 | val &= ~0xf; | |
4034 | val |= divider; | |
4035 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
4036 | mutex_unlock(&dev_priv->dpio_lock); | |
4037 | } | |
4038 | ||
4039 | mutex_lock(&dev_priv->dpio_lock); | |
4040 | /* adjust self-refresh exit latency value */ | |
4041 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
4042 | val &= ~0x7f; | |
4043 | ||
4044 | /* | |
4045 | * For high bandwidth configs, we set a higher latency in the bunit | |
4046 | * so that the core display fetch happens in time to avoid underruns. | |
4047 | */ | |
4048 | if (cdclk == 400) | |
4049 | val |= 4500 / 250; /* 4.5 usec */ | |
4050 | else | |
4051 | val |= 3000 / 250; /* 3.0 usec */ | |
4052 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
4053 | mutex_unlock(&dev_priv->dpio_lock); | |
4054 | ||
4055 | /* Since we changed the CDclk, we need to update the GMBUSFREQ too */ | |
4056 | intel_i2c_reset(dev); | |
4057 | } | |
4058 | ||
4059 | static int valleyview_cur_cdclk(struct drm_i915_private *dev_priv) | |
4060 | { | |
4061 | int cur_cdclk, vco; | |
4062 | int divider; | |
4063 | ||
4064 | vco = valleyview_get_vco(dev_priv); | |
4065 | ||
4066 | mutex_lock(&dev_priv->dpio_lock); | |
4067 | divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
4068 | mutex_unlock(&dev_priv->dpio_lock); | |
4069 | ||
4070 | divider &= 0xf; | |
4071 | ||
4072 | cur_cdclk = (vco << 1) / (divider + 1); | |
4073 | ||
4074 | return cur_cdclk; | |
4075 | } | |
4076 | ||
4077 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, | |
4078 | int max_pixclk) | |
4079 | { | |
4080 | int cur_cdclk; | |
4081 | ||
4082 | cur_cdclk = valleyview_cur_cdclk(dev_priv); | |
4083 | ||
4084 | /* | |
4085 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
4086 | * 200MHz | |
4087 | * 267MHz | |
4088 | * 320MHz | |
4089 | * 400MHz | |
4090 | * So we check to see whether we're above 90% of the lower bin and | |
4091 | * adjust if needed. | |
4092 | */ | |
4093 | if (max_pixclk > 288000) { | |
4094 | return 400; | |
4095 | } else if (max_pixclk > 240000) { | |
4096 | return 320; | |
4097 | } else | |
4098 | return 266; | |
4099 | /* Looks like the 200MHz CDclk freq doesn't work on some configs */ | |
4100 | } | |
4101 | ||
2f2d7aa1 VS |
4102 | /* compute the max pixel clock for new configuration */ |
4103 | static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv) | |
30a970c6 JB |
4104 | { |
4105 | struct drm_device *dev = dev_priv->dev; | |
4106 | struct intel_crtc *intel_crtc; | |
4107 | int max_pixclk = 0; | |
4108 | ||
4109 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, | |
4110 | base.head) { | |
2f2d7aa1 | 4111 | if (intel_crtc->new_enabled) |
30a970c6 | 4112 | max_pixclk = max(max_pixclk, |
2f2d7aa1 | 4113 | intel_crtc->new_config->adjusted_mode.crtc_clock); |
30a970c6 JB |
4114 | } |
4115 | ||
4116 | return max_pixclk; | |
4117 | } | |
4118 | ||
4119 | static void valleyview_modeset_global_pipes(struct drm_device *dev, | |
2f2d7aa1 | 4120 | unsigned *prepare_pipes) |
30a970c6 JB |
4121 | { |
4122 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4123 | struct intel_crtc *intel_crtc; | |
2f2d7aa1 | 4124 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
30a970c6 JB |
4125 | int cur_cdclk = valleyview_cur_cdclk(dev_priv); |
4126 | ||
4127 | if (valleyview_calc_cdclk(dev_priv, max_pixclk) == cur_cdclk) | |
4128 | return; | |
4129 | ||
2f2d7aa1 | 4130 | /* disable/enable all currently active pipes while we change cdclk */ |
30a970c6 JB |
4131 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
4132 | base.head) | |
4133 | if (intel_crtc->base.enabled) | |
4134 | *prepare_pipes |= (1 << intel_crtc->pipe); | |
4135 | } | |
4136 | ||
4137 | static void valleyview_modeset_global_resources(struct drm_device *dev) | |
4138 | { | |
4139 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2f2d7aa1 | 4140 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
30a970c6 JB |
4141 | int cur_cdclk = valleyview_cur_cdclk(dev_priv); |
4142 | int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); | |
4143 | ||
4144 | if (req_cdclk != cur_cdclk) | |
4145 | valleyview_set_cdclk(dev, req_cdclk); | |
4146 | } | |
4147 | ||
89b667f8 JB |
4148 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
4149 | { | |
4150 | struct drm_device *dev = crtc->dev; | |
4151 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4152 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4153 | struct intel_encoder *encoder; | |
4154 | int pipe = intel_crtc->pipe; | |
4155 | int plane = intel_crtc->plane; | |
23538ef1 | 4156 | bool is_dsi; |
89b667f8 JB |
4157 | |
4158 | WARN_ON(!crtc->enabled); | |
4159 | ||
4160 | if (intel_crtc->active) | |
4161 | return; | |
4162 | ||
4163 | intel_crtc->active = true; | |
89b667f8 | 4164 | |
89b667f8 JB |
4165 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4166 | if (encoder->pre_pll_enable) | |
4167 | encoder->pre_pll_enable(encoder); | |
4168 | ||
23538ef1 JN |
4169 | is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI); |
4170 | ||
e9fd1c02 JN |
4171 | if (!is_dsi) |
4172 | vlv_enable_pll(intel_crtc); | |
89b667f8 JB |
4173 | |
4174 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
4175 | if (encoder->pre_enable) | |
4176 | encoder->pre_enable(encoder); | |
4177 | ||
2dd24552 JB |
4178 | i9xx_pfit_enable(intel_crtc); |
4179 | ||
63cbb074 VS |
4180 | intel_crtc_load_lut(crtc); |
4181 | ||
f37fcc2a | 4182 | intel_update_watermarks(crtc); |
23538ef1 | 4183 | intel_enable_pipe(dev_priv, pipe, false, is_dsi); |
2d9d2b0b | 4184 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
d1de00ef | 4185 | intel_enable_primary_plane(dev_priv, plane, pipe); |
bb53d4ae | 4186 | intel_enable_planes(crtc); |
5c38d48c | 4187 | intel_crtc_update_cursor(crtc, true); |
89b667f8 | 4188 | |
89b667f8 | 4189 | intel_update_fbc(dev); |
5004945f JN |
4190 | |
4191 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
4192 | encoder->enable(encoder); | |
89b667f8 JB |
4193 | } |
4194 | ||
0b8765c6 | 4195 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
4196 | { |
4197 | struct drm_device *dev = crtc->dev; | |
79e53945 JB |
4198 | struct drm_i915_private *dev_priv = dev->dev_private; |
4199 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4200 | struct intel_encoder *encoder; |
79e53945 | 4201 | int pipe = intel_crtc->pipe; |
80824003 | 4202 | int plane = intel_crtc->plane; |
79e53945 | 4203 | |
08a48469 DV |
4204 | WARN_ON(!crtc->enabled); |
4205 | ||
f7abfe8b CW |
4206 | if (intel_crtc->active) |
4207 | return; | |
4208 | ||
4209 | intel_crtc->active = true; | |
6b383a7f | 4210 | |
9d6d9f19 MK |
4211 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4212 | if (encoder->pre_enable) | |
4213 | encoder->pre_enable(encoder); | |
4214 | ||
f6736a1a DV |
4215 | i9xx_enable_pll(intel_crtc); |
4216 | ||
2dd24552 JB |
4217 | i9xx_pfit_enable(intel_crtc); |
4218 | ||
63cbb074 VS |
4219 | intel_crtc_load_lut(crtc); |
4220 | ||
f37fcc2a | 4221 | intel_update_watermarks(crtc); |
23538ef1 | 4222 | intel_enable_pipe(dev_priv, pipe, false, false); |
2d9d2b0b | 4223 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
d1de00ef | 4224 | intel_enable_primary_plane(dev_priv, plane, pipe); |
bb53d4ae | 4225 | intel_enable_planes(crtc); |
22e407d7 | 4226 | /* The fixup needs to happen before cursor is enabled */ |
61bc95c1 EE |
4227 | if (IS_G4X(dev)) |
4228 | g4x_fixup_plane(dev_priv, pipe); | |
22e407d7 | 4229 | intel_crtc_update_cursor(crtc, true); |
79e53945 | 4230 | |
0b8765c6 JB |
4231 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
4232 | intel_crtc_dpms_overlay(intel_crtc, true); | |
ef9c3aee | 4233 | |
f440eb13 | 4234 | intel_update_fbc(dev); |
ef9c3aee | 4235 | |
fa5c73b1 DV |
4236 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4237 | encoder->enable(encoder); | |
0b8765c6 | 4238 | } |
79e53945 | 4239 | |
87476d63 DV |
4240 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
4241 | { | |
4242 | struct drm_device *dev = crtc->base.dev; | |
4243 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 4244 | |
328d8e82 DV |
4245 | if (!crtc->config.gmch_pfit.control) |
4246 | return; | |
87476d63 | 4247 | |
328d8e82 | 4248 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 4249 | |
328d8e82 DV |
4250 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
4251 | I915_READ(PFIT_CONTROL)); | |
4252 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
4253 | } |
4254 | ||
0b8765c6 JB |
4255 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
4256 | { | |
4257 | struct drm_device *dev = crtc->dev; | |
4258 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4259 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4260 | struct intel_encoder *encoder; |
0b8765c6 JB |
4261 | int pipe = intel_crtc->pipe; |
4262 | int plane = intel_crtc->plane; | |
ef9c3aee | 4263 | |
f7abfe8b CW |
4264 | if (!intel_crtc->active) |
4265 | return; | |
4266 | ||
ea9d758d DV |
4267 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4268 | encoder->disable(encoder); | |
4269 | ||
0b8765c6 | 4270 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
e6c3a2a6 CW |
4271 | intel_crtc_wait_for_pending_flips(crtc); |
4272 | drm_vblank_off(dev, pipe); | |
0b8765c6 | 4273 | |
5c3fe8b0 | 4274 | if (dev_priv->fbc.plane == plane) |
973d04f9 | 4275 | intel_disable_fbc(dev); |
79e53945 | 4276 | |
0d5b8c61 VS |
4277 | intel_crtc_dpms_overlay(intel_crtc, false); |
4278 | intel_crtc_update_cursor(crtc, false); | |
bb53d4ae | 4279 | intel_disable_planes(crtc); |
d1de00ef | 4280 | intel_disable_primary_plane(dev_priv, plane, pipe); |
0d5b8c61 | 4281 | |
2d9d2b0b | 4282 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false); |
b24e7179 | 4283 | intel_disable_pipe(dev_priv, pipe); |
24a1f16d | 4284 | |
87476d63 | 4285 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 4286 | |
89b667f8 JB |
4287 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4288 | if (encoder->post_disable) | |
4289 | encoder->post_disable(encoder); | |
4290 | ||
f6071166 JB |
4291 | if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) |
4292 | vlv_disable_pll(dev_priv, pipe); | |
4293 | else if (!IS_VALLEYVIEW(dev)) | |
e9fd1c02 | 4294 | i9xx_disable_pll(dev_priv, pipe); |
0b8765c6 | 4295 | |
f7abfe8b | 4296 | intel_crtc->active = false; |
46ba614c | 4297 | intel_update_watermarks(crtc); |
f37fcc2a | 4298 | |
6b383a7f | 4299 | intel_update_fbc(dev); |
0b8765c6 JB |
4300 | } |
4301 | ||
ee7b9f93 JB |
4302 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
4303 | { | |
4304 | } | |
4305 | ||
976f8a20 DV |
4306 | static void intel_crtc_update_sarea(struct drm_crtc *crtc, |
4307 | bool enabled) | |
2c07245f ZW |
4308 | { |
4309 | struct drm_device *dev = crtc->dev; | |
4310 | struct drm_i915_master_private *master_priv; | |
4311 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4312 | int pipe = intel_crtc->pipe; | |
79e53945 JB |
4313 | |
4314 | if (!dev->primary->master) | |
4315 | return; | |
4316 | ||
4317 | master_priv = dev->primary->master->driver_priv; | |
4318 | if (!master_priv->sarea_priv) | |
4319 | return; | |
4320 | ||
79e53945 JB |
4321 | switch (pipe) { |
4322 | case 0: | |
4323 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; | |
4324 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; | |
4325 | break; | |
4326 | case 1: | |
4327 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; | |
4328 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; | |
4329 | break; | |
4330 | default: | |
9db4a9c7 | 4331 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
79e53945 JB |
4332 | break; |
4333 | } | |
79e53945 JB |
4334 | } |
4335 | ||
976f8a20 DV |
4336 | /** |
4337 | * Sets the power management mode of the pipe and plane. | |
4338 | */ | |
4339 | void intel_crtc_update_dpms(struct drm_crtc *crtc) | |
4340 | { | |
4341 | struct drm_device *dev = crtc->dev; | |
4342 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4343 | struct intel_encoder *intel_encoder; | |
4344 | bool enable = false; | |
4345 | ||
4346 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) | |
4347 | enable |= intel_encoder->connectors_active; | |
4348 | ||
4349 | if (enable) | |
4350 | dev_priv->display.crtc_enable(crtc); | |
4351 | else | |
4352 | dev_priv->display.crtc_disable(crtc); | |
4353 | ||
4354 | intel_crtc_update_sarea(crtc, enable); | |
4355 | } | |
4356 | ||
cdd59983 CW |
4357 | static void intel_crtc_disable(struct drm_crtc *crtc) |
4358 | { | |
cdd59983 | 4359 | struct drm_device *dev = crtc->dev; |
976f8a20 | 4360 | struct drm_connector *connector; |
ee7b9f93 | 4361 | struct drm_i915_private *dev_priv = dev->dev_private; |
7b9f35a6 | 4362 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cdd59983 | 4363 | |
976f8a20 DV |
4364 | /* crtc should still be enabled when we disable it. */ |
4365 | WARN_ON(!crtc->enabled); | |
4366 | ||
4367 | dev_priv->display.crtc_disable(crtc); | |
c77bf565 | 4368 | intel_crtc->eld_vld = false; |
976f8a20 | 4369 | intel_crtc_update_sarea(crtc, false); |
ee7b9f93 JB |
4370 | dev_priv->display.off(crtc); |
4371 | ||
931872fc | 4372 | assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); |
93ce0ba6 | 4373 | assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe); |
931872fc | 4374 | assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); |
cdd59983 CW |
4375 | |
4376 | if (crtc->fb) { | |
4377 | mutex_lock(&dev->struct_mutex); | |
1690e1eb | 4378 | intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); |
cdd59983 | 4379 | mutex_unlock(&dev->struct_mutex); |
976f8a20 DV |
4380 | crtc->fb = NULL; |
4381 | } | |
4382 | ||
4383 | /* Update computed state. */ | |
4384 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4385 | if (!connector->encoder || !connector->encoder->crtc) | |
4386 | continue; | |
4387 | ||
4388 | if (connector->encoder->crtc != crtc) | |
4389 | continue; | |
4390 | ||
4391 | connector->dpms = DRM_MODE_DPMS_OFF; | |
4392 | to_intel_encoder(connector->encoder)->connectors_active = false; | |
cdd59983 CW |
4393 | } |
4394 | } | |
4395 | ||
ea5b213a | 4396 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 4397 | { |
4ef69c7a | 4398 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 4399 | |
ea5b213a CW |
4400 | drm_encoder_cleanup(encoder); |
4401 | kfree(intel_encoder); | |
7e7d76c3 JB |
4402 | } |
4403 | ||
9237329d | 4404 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
5ab432ef DV |
4405 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
4406 | * state of the entire output pipe. */ | |
9237329d | 4407 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
7e7d76c3 | 4408 | { |
5ab432ef DV |
4409 | if (mode == DRM_MODE_DPMS_ON) { |
4410 | encoder->connectors_active = true; | |
4411 | ||
b2cabb0e | 4412 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef DV |
4413 | } else { |
4414 | encoder->connectors_active = false; | |
4415 | ||
b2cabb0e | 4416 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef | 4417 | } |
79e53945 JB |
4418 | } |
4419 | ||
0a91ca29 DV |
4420 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
4421 | * internal consistency). */ | |
b980514c | 4422 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 4423 | { |
0a91ca29 DV |
4424 | if (connector->get_hw_state(connector)) { |
4425 | struct intel_encoder *encoder = connector->encoder; | |
4426 | struct drm_crtc *crtc; | |
4427 | bool encoder_enabled; | |
4428 | enum pipe pipe; | |
4429 | ||
4430 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
4431 | connector->base.base.id, | |
4432 | drm_get_connector_name(&connector->base)); | |
4433 | ||
4434 | WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, | |
4435 | "wrong connector dpms state\n"); | |
4436 | WARN(connector->base.encoder != &encoder->base, | |
4437 | "active connector not linked to encoder\n"); | |
4438 | WARN(!encoder->connectors_active, | |
4439 | "encoder->connectors_active not set\n"); | |
4440 | ||
4441 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); | |
4442 | WARN(!encoder_enabled, "encoder not enabled\n"); | |
4443 | if (WARN_ON(!encoder->base.crtc)) | |
4444 | return; | |
4445 | ||
4446 | crtc = encoder->base.crtc; | |
4447 | ||
4448 | WARN(!crtc->enabled, "crtc not enabled\n"); | |
4449 | WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); | |
4450 | WARN(pipe != to_intel_crtc(crtc)->pipe, | |
4451 | "encoder active on the wrong pipe\n"); | |
4452 | } | |
79e53945 JB |
4453 | } |
4454 | ||
5ab432ef DV |
4455 | /* Even simpler default implementation, if there's really no special case to |
4456 | * consider. */ | |
4457 | void intel_connector_dpms(struct drm_connector *connector, int mode) | |
79e53945 | 4458 | { |
5ab432ef DV |
4459 | /* All the simple cases only support two dpms states. */ |
4460 | if (mode != DRM_MODE_DPMS_ON) | |
4461 | mode = DRM_MODE_DPMS_OFF; | |
d4270e57 | 4462 | |
5ab432ef DV |
4463 | if (mode == connector->dpms) |
4464 | return; | |
4465 | ||
4466 | connector->dpms = mode; | |
4467 | ||
4468 | /* Only need to change hw state when actually enabled */ | |
c9976dcf CW |
4469 | if (connector->encoder) |
4470 | intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); | |
0a91ca29 | 4471 | |
b980514c | 4472 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
4473 | } |
4474 | ||
f0947c37 DV |
4475 | /* Simple connector->get_hw_state implementation for encoders that support only |
4476 | * one connector and no cloning and hence the encoder state determines the state | |
4477 | * of the connector. */ | |
4478 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 4479 | { |
24929352 | 4480 | enum pipe pipe = 0; |
f0947c37 | 4481 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 4482 | |
f0947c37 | 4483 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
4484 | } |
4485 | ||
1857e1da DV |
4486 | static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
4487 | struct intel_crtc_config *pipe_config) | |
4488 | { | |
4489 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4490 | struct intel_crtc *pipe_B_crtc = | |
4491 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
4492 | ||
4493 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", | |
4494 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4495 | if (pipe_config->fdi_lanes > 4) { | |
4496 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
4497 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4498 | return false; | |
4499 | } | |
4500 | ||
bafb6553 | 4501 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
4502 | if (pipe_config->fdi_lanes > 2) { |
4503 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
4504 | pipe_config->fdi_lanes); | |
4505 | return false; | |
4506 | } else { | |
4507 | return true; | |
4508 | } | |
4509 | } | |
4510 | ||
4511 | if (INTEL_INFO(dev)->num_pipes == 2) | |
4512 | return true; | |
4513 | ||
4514 | /* Ivybridge 3 pipe is really complicated */ | |
4515 | switch (pipe) { | |
4516 | case PIPE_A: | |
4517 | return true; | |
4518 | case PIPE_B: | |
4519 | if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled && | |
4520 | pipe_config->fdi_lanes > 2) { | |
4521 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
4522 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4523 | return false; | |
4524 | } | |
4525 | return true; | |
4526 | case PIPE_C: | |
1e833f40 | 4527 | if (!pipe_has_enabled_pch(pipe_B_crtc) || |
1857e1da DV |
4528 | pipe_B_crtc->config.fdi_lanes <= 2) { |
4529 | if (pipe_config->fdi_lanes > 2) { | |
4530 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
4531 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4532 | return false; | |
4533 | } | |
4534 | } else { | |
4535 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); | |
4536 | return false; | |
4537 | } | |
4538 | return true; | |
4539 | default: | |
4540 | BUG(); | |
4541 | } | |
4542 | } | |
4543 | ||
e29c22c0 DV |
4544 | #define RETRY 1 |
4545 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
4546 | struct intel_crtc_config *pipe_config) | |
877d48d5 | 4547 | { |
1857e1da | 4548 | struct drm_device *dev = intel_crtc->base.dev; |
877d48d5 | 4549 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
ff9a6750 | 4550 | int lane, link_bw, fdi_dotclock; |
e29c22c0 | 4551 | bool setup_ok, needs_recompute = false; |
877d48d5 | 4552 | |
e29c22c0 | 4553 | retry: |
877d48d5 DV |
4554 | /* FDI is a binary signal running at ~2.7GHz, encoding |
4555 | * each output octet as 10 bits. The actual frequency | |
4556 | * is stored as a divider into a 100MHz clock, and the | |
4557 | * mode pixel clock is stored in units of 1KHz. | |
4558 | * Hence the bw of each lane in terms of the mode signal | |
4559 | * is: | |
4560 | */ | |
4561 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
4562 | ||
241bfc38 | 4563 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 4564 | |
2bd89a07 | 4565 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
4566 | pipe_config->pipe_bpp); |
4567 | ||
4568 | pipe_config->fdi_lanes = lane; | |
4569 | ||
2bd89a07 | 4570 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 4571 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 4572 | |
e29c22c0 DV |
4573 | setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
4574 | intel_crtc->pipe, pipe_config); | |
4575 | if (!setup_ok && pipe_config->pipe_bpp > 6*3) { | |
4576 | pipe_config->pipe_bpp -= 2*3; | |
4577 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
4578 | pipe_config->pipe_bpp); | |
4579 | needs_recompute = true; | |
4580 | pipe_config->bw_constrained = true; | |
4581 | ||
4582 | goto retry; | |
4583 | } | |
4584 | ||
4585 | if (needs_recompute) | |
4586 | return RETRY; | |
4587 | ||
4588 | return setup_ok ? 0 : -EINVAL; | |
877d48d5 DV |
4589 | } |
4590 | ||
42db64ef PZ |
4591 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
4592 | struct intel_crtc_config *pipe_config) | |
4593 | { | |
d330a953 | 4594 | pipe_config->ips_enabled = i915.enable_ips && |
3c4ca58c | 4595 | hsw_crtc_supports_ips(crtc) && |
b6dfdc9b | 4596 | pipe_config->pipe_bpp <= 24; |
42db64ef PZ |
4597 | } |
4598 | ||
a43f6e0f | 4599 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
e29c22c0 | 4600 | struct intel_crtc_config *pipe_config) |
79e53945 | 4601 | { |
a43f6e0f | 4602 | struct drm_device *dev = crtc->base.dev; |
b8cecdf5 | 4603 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
89749350 | 4604 | |
ad3a4479 | 4605 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 VS |
4606 | if (INTEL_INFO(dev)->gen < 4) { |
4607 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4608 | int clock_limit = | |
4609 | dev_priv->display.get_display_clock_speed(dev); | |
4610 | ||
4611 | /* | |
4612 | * Enable pixel doubling when the dot clock | |
4613 | * is > 90% of the (display) core speed. | |
4614 | * | |
b397c96b VS |
4615 | * GDG double wide on either pipe, |
4616 | * otherwise pipe A only. | |
cf532bb2 | 4617 | */ |
b397c96b | 4618 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
241bfc38 | 4619 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
ad3a4479 | 4620 | clock_limit *= 2; |
cf532bb2 | 4621 | pipe_config->double_wide = true; |
ad3a4479 VS |
4622 | } |
4623 | ||
241bfc38 | 4624 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
e29c22c0 | 4625 | return -EINVAL; |
2c07245f | 4626 | } |
89749350 | 4627 | |
1d1d0e27 VS |
4628 | /* |
4629 | * Pipe horizontal size must be even in: | |
4630 | * - DVO ganged mode | |
4631 | * - LVDS dual channel mode | |
4632 | * - Double wide pipe | |
4633 | */ | |
4634 | if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && | |
4635 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) | |
4636 | pipe_config->pipe_src_w &= ~1; | |
4637 | ||
8693a824 DL |
4638 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
4639 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
4640 | */ |
4641 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
4642 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | |
e29c22c0 | 4643 | return -EINVAL; |
44f46b42 | 4644 | |
bd080ee5 | 4645 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { |
5d2d38dd | 4646 | pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ |
bd080ee5 | 4647 | } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { |
5d2d38dd DV |
4648 | /* only a 8bpc pipe, with 6bpc dither through the panel fitter |
4649 | * for lvds. */ | |
4650 | pipe_config->pipe_bpp = 8*3; | |
4651 | } | |
4652 | ||
f5adf94e | 4653 | if (HAS_IPS(dev)) |
a43f6e0f DV |
4654 | hsw_compute_ips_config(crtc, pipe_config); |
4655 | ||
4656 | /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old | |
4657 | * clock survives for now. */ | |
4658 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
4659 | pipe_config->shared_dpll = crtc->config.shared_dpll; | |
42db64ef | 4660 | |
877d48d5 | 4661 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 4662 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 4663 | |
e29c22c0 | 4664 | return 0; |
79e53945 JB |
4665 | } |
4666 | ||
25eb05fc JB |
4667 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
4668 | { | |
4669 | return 400000; /* FIXME */ | |
4670 | } | |
4671 | ||
e70236a8 JB |
4672 | static int i945_get_display_clock_speed(struct drm_device *dev) |
4673 | { | |
4674 | return 400000; | |
4675 | } | |
79e53945 | 4676 | |
e70236a8 | 4677 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 4678 | { |
e70236a8 JB |
4679 | return 333000; |
4680 | } | |
79e53945 | 4681 | |
e70236a8 JB |
4682 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
4683 | { | |
4684 | return 200000; | |
4685 | } | |
79e53945 | 4686 | |
257a7ffc DV |
4687 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
4688 | { | |
4689 | u16 gcfgc = 0; | |
4690 | ||
4691 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
4692 | ||
4693 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
4694 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
4695 | return 267000; | |
4696 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: | |
4697 | return 333000; | |
4698 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: | |
4699 | return 444000; | |
4700 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: | |
4701 | return 200000; | |
4702 | default: | |
4703 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
4704 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
4705 | return 133000; | |
4706 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: | |
4707 | return 167000; | |
4708 | } | |
4709 | } | |
4710 | ||
e70236a8 JB |
4711 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
4712 | { | |
4713 | u16 gcfgc = 0; | |
79e53945 | 4714 | |
e70236a8 JB |
4715 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
4716 | ||
4717 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
4718 | return 133000; | |
4719 | else { | |
4720 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
4721 | case GC_DISPLAY_CLOCK_333_MHZ: | |
4722 | return 333000; | |
4723 | default: | |
4724 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
4725 | return 190000; | |
79e53945 | 4726 | } |
e70236a8 JB |
4727 | } |
4728 | } | |
4729 | ||
4730 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
4731 | { | |
4732 | return 266000; | |
4733 | } | |
4734 | ||
4735 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
4736 | { | |
4737 | u16 hpllcc = 0; | |
4738 | /* Assume that the hardware is in the high speed state. This | |
4739 | * should be the default. | |
4740 | */ | |
4741 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
4742 | case GC_CLOCK_133_200: | |
4743 | case GC_CLOCK_100_200: | |
4744 | return 200000; | |
4745 | case GC_CLOCK_166_250: | |
4746 | return 250000; | |
4747 | case GC_CLOCK_100_133: | |
79e53945 | 4748 | return 133000; |
e70236a8 | 4749 | } |
79e53945 | 4750 | |
e70236a8 JB |
4751 | /* Shouldn't happen */ |
4752 | return 0; | |
4753 | } | |
79e53945 | 4754 | |
e70236a8 JB |
4755 | static int i830_get_display_clock_speed(struct drm_device *dev) |
4756 | { | |
4757 | return 133000; | |
79e53945 JB |
4758 | } |
4759 | ||
2c07245f | 4760 | static void |
a65851af | 4761 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 4762 | { |
a65851af VS |
4763 | while (*num > DATA_LINK_M_N_MASK || |
4764 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
4765 | *num >>= 1; |
4766 | *den >>= 1; | |
4767 | } | |
4768 | } | |
4769 | ||
a65851af VS |
4770 | static void compute_m_n(unsigned int m, unsigned int n, |
4771 | uint32_t *ret_m, uint32_t *ret_n) | |
4772 | { | |
4773 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
4774 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
4775 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
4776 | } | |
4777 | ||
e69d0bc1 DV |
4778 | void |
4779 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
4780 | int pixel_clock, int link_clock, | |
4781 | struct intel_link_m_n *m_n) | |
2c07245f | 4782 | { |
e69d0bc1 | 4783 | m_n->tu = 64; |
a65851af VS |
4784 | |
4785 | compute_m_n(bits_per_pixel * pixel_clock, | |
4786 | link_clock * nlanes * 8, | |
4787 | &m_n->gmch_m, &m_n->gmch_n); | |
4788 | ||
4789 | compute_m_n(pixel_clock, link_clock, | |
4790 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
4791 | } |
4792 | ||
a7615030 CW |
4793 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
4794 | { | |
d330a953 JN |
4795 | if (i915.panel_use_ssc >= 0) |
4796 | return i915.panel_use_ssc != 0; | |
41aa3448 | 4797 | return dev_priv->vbt.lvds_use_ssc |
435793df | 4798 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
4799 | } |
4800 | ||
c65d77d8 JB |
4801 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
4802 | { | |
4803 | struct drm_device *dev = crtc->dev; | |
4804 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4805 | int refclk; | |
4806 | ||
a0c4da24 | 4807 | if (IS_VALLEYVIEW(dev)) { |
9a0ea498 | 4808 | refclk = 100000; |
a0c4da24 | 4809 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 4810 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
4811 | refclk = dev_priv->vbt.lvds_ssc_freq; |
4812 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
4813 | } else if (!IS_GEN2(dev)) { |
4814 | refclk = 96000; | |
4815 | } else { | |
4816 | refclk = 48000; | |
4817 | } | |
4818 | ||
4819 | return refclk; | |
4820 | } | |
4821 | ||
7429e9d4 | 4822 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 4823 | { |
7df00d7a | 4824 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 4825 | } |
f47709a9 | 4826 | |
7429e9d4 DV |
4827 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
4828 | { | |
4829 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
4830 | } |
4831 | ||
f47709a9 | 4832 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
a7516a05 JB |
4833 | intel_clock_t *reduced_clock) |
4834 | { | |
f47709a9 | 4835 | struct drm_device *dev = crtc->base.dev; |
a7516a05 | 4836 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 4837 | int pipe = crtc->pipe; |
a7516a05 JB |
4838 | u32 fp, fp2 = 0; |
4839 | ||
4840 | if (IS_PINEVIEW(dev)) { | |
7429e9d4 | 4841 | fp = pnv_dpll_compute_fp(&crtc->config.dpll); |
a7516a05 | 4842 | if (reduced_clock) |
7429e9d4 | 4843 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 4844 | } else { |
7429e9d4 | 4845 | fp = i9xx_dpll_compute_fp(&crtc->config.dpll); |
a7516a05 | 4846 | if (reduced_clock) |
7429e9d4 | 4847 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
4848 | } |
4849 | ||
4850 | I915_WRITE(FP0(pipe), fp); | |
8bcc2795 | 4851 | crtc->config.dpll_hw_state.fp0 = fp; |
a7516a05 | 4852 | |
f47709a9 DV |
4853 | crtc->lowfreq_avail = false; |
4854 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && | |
d330a953 | 4855 | reduced_clock && i915.powersave) { |
a7516a05 | 4856 | I915_WRITE(FP1(pipe), fp2); |
8bcc2795 | 4857 | crtc->config.dpll_hw_state.fp1 = fp2; |
f47709a9 | 4858 | crtc->lowfreq_avail = true; |
a7516a05 JB |
4859 | } else { |
4860 | I915_WRITE(FP1(pipe), fp); | |
8bcc2795 | 4861 | crtc->config.dpll_hw_state.fp1 = fp; |
a7516a05 JB |
4862 | } |
4863 | } | |
4864 | ||
5e69f97f CML |
4865 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
4866 | pipe) | |
89b667f8 JB |
4867 | { |
4868 | u32 reg_val; | |
4869 | ||
4870 | /* | |
4871 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
4872 | * and set it to a reasonable value instead. | |
4873 | */ | |
ab3c759a | 4874 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
4875 | reg_val &= 0xffffff00; |
4876 | reg_val |= 0x00000030; | |
ab3c759a | 4877 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 4878 | |
ab3c759a | 4879 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
4880 | reg_val &= 0x8cffffff; |
4881 | reg_val = 0x8c000000; | |
ab3c759a | 4882 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 4883 | |
ab3c759a | 4884 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 4885 | reg_val &= 0xffffff00; |
ab3c759a | 4886 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 4887 | |
ab3c759a | 4888 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
4889 | reg_val &= 0x00ffffff; |
4890 | reg_val |= 0xb0000000; | |
ab3c759a | 4891 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
4892 | } |
4893 | ||
b551842d DV |
4894 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
4895 | struct intel_link_m_n *m_n) | |
4896 | { | |
4897 | struct drm_device *dev = crtc->base.dev; | |
4898 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4899 | int pipe = crtc->pipe; | |
4900 | ||
e3b95f1e DV |
4901 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
4902 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
4903 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
4904 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
4905 | } |
4906 | ||
4907 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
4908 | struct intel_link_m_n *m_n) | |
4909 | { | |
4910 | struct drm_device *dev = crtc->base.dev; | |
4911 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4912 | int pipe = crtc->pipe; | |
4913 | enum transcoder transcoder = crtc->config.cpu_transcoder; | |
4914 | ||
4915 | if (INTEL_INFO(dev)->gen >= 5) { | |
4916 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
4917 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
4918 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
4919 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
4920 | } else { | |
e3b95f1e DV |
4921 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
4922 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
4923 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
4924 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
4925 | } |
4926 | } | |
4927 | ||
03afc4a2 DV |
4928 | static void intel_dp_set_m_n(struct intel_crtc *crtc) |
4929 | { | |
4930 | if (crtc->config.has_pch_encoder) | |
4931 | intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); | |
4932 | else | |
4933 | intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); | |
4934 | } | |
4935 | ||
f47709a9 | 4936 | static void vlv_update_pll(struct intel_crtc *crtc) |
a0c4da24 | 4937 | { |
f47709a9 | 4938 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 4939 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 4940 | int pipe = crtc->pipe; |
89b667f8 | 4941 | u32 dpll, mdiv; |
a0c4da24 | 4942 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
198a037f | 4943 | u32 coreclk, reg_val, dpll_md; |
a0c4da24 | 4944 | |
09153000 DV |
4945 | mutex_lock(&dev_priv->dpio_lock); |
4946 | ||
f47709a9 DV |
4947 | bestn = crtc->config.dpll.n; |
4948 | bestm1 = crtc->config.dpll.m1; | |
4949 | bestm2 = crtc->config.dpll.m2; | |
4950 | bestp1 = crtc->config.dpll.p1; | |
4951 | bestp2 = crtc->config.dpll.p2; | |
a0c4da24 | 4952 | |
89b667f8 JB |
4953 | /* See eDP HDMI DPIO driver vbios notes doc */ |
4954 | ||
4955 | /* PLL B needs special handling */ | |
4956 | if (pipe) | |
5e69f97f | 4957 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
4958 | |
4959 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 4960 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
4961 | |
4962 | /* Disable target IRef on PLL */ | |
ab3c759a | 4963 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 4964 | reg_val &= 0x00ffffff; |
ab3c759a | 4965 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
4966 | |
4967 | /* Disable fast lock */ | |
ab3c759a | 4968 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
4969 | |
4970 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
4971 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
4972 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
4973 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 4974 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
4975 | |
4976 | /* | |
4977 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
4978 | * but we don't support that). | |
4979 | * Note: don't use the DAC post divider as it seems unstable. | |
4980 | */ | |
4981 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 4982 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 4983 | |
a0c4da24 | 4984 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 4985 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 4986 | |
89b667f8 | 4987 | /* Set HBR and RBR LPF coefficients */ |
ff9a6750 | 4988 | if (crtc->config.port_clock == 162000 || |
99750bd4 | 4989 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) || |
89b667f8 | 4990 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) |
ab3c759a | 4991 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 4992 | 0x009f0003); |
89b667f8 | 4993 | else |
ab3c759a | 4994 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
4995 | 0x00d0000f); |
4996 | ||
4997 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) || | |
4998 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) { | |
4999 | /* Use SSC source */ | |
5000 | if (!pipe) | |
ab3c759a | 5001 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5002 | 0x0df40000); |
5003 | else | |
ab3c759a | 5004 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5005 | 0x0df70000); |
5006 | } else { /* HDMI or VGA */ | |
5007 | /* Use bend source */ | |
5008 | if (!pipe) | |
ab3c759a | 5009 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5010 | 0x0df70000); |
5011 | else | |
ab3c759a | 5012 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5013 | 0x0df40000); |
5014 | } | |
a0c4da24 | 5015 | |
ab3c759a | 5016 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 JB |
5017 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
5018 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) || | |
5019 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) | |
5020 | coreclk |= 0x01000000; | |
ab3c759a | 5021 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 5022 | |
ab3c759a | 5023 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a0c4da24 | 5024 | |
e5cbfbfb ID |
5025 | /* |
5026 | * Enable DPIO clock input. We should never disable the reference | |
5027 | * clock for pipe B, since VGA hotplug / manual detection depends | |
5028 | * on it. | |
5029 | */ | |
89b667f8 JB |
5030 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | |
5031 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; | |
f6071166 JB |
5032 | /* We should never disable this, set it here for state tracking */ |
5033 | if (pipe == PIPE_B) | |
89b667f8 | 5034 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
a0c4da24 | 5035 | dpll |= DPLL_VCO_ENABLE; |
8bcc2795 DV |
5036 | crtc->config.dpll_hw_state.dpll = dpll; |
5037 | ||
ef1b460d DV |
5038 | dpll_md = (crtc->config.pixel_multiplier - 1) |
5039 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
8bcc2795 DV |
5040 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
5041 | ||
89b667f8 JB |
5042 | if (crtc->config.has_dp_encoder) |
5043 | intel_dp_set_m_n(crtc); | |
09153000 DV |
5044 | |
5045 | mutex_unlock(&dev_priv->dpio_lock); | |
a0c4da24 JB |
5046 | } |
5047 | ||
f47709a9 DV |
5048 | static void i9xx_update_pll(struct intel_crtc *crtc, |
5049 | intel_clock_t *reduced_clock, | |
eb1cbe48 DV |
5050 | int num_connectors) |
5051 | { | |
f47709a9 | 5052 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 5053 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
5054 | u32 dpll; |
5055 | bool is_sdvo; | |
f47709a9 | 5056 | struct dpll *clock = &crtc->config.dpll; |
eb1cbe48 | 5057 | |
f47709a9 | 5058 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 5059 | |
f47709a9 DV |
5060 | is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) || |
5061 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
5062 | |
5063 | dpll = DPLL_VGA_MODE_DIS; | |
5064 | ||
f47709a9 | 5065 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
5066 | dpll |= DPLLB_MODE_LVDS; |
5067 | else | |
5068 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 5069 | |
ef1b460d | 5070 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
198a037f DV |
5071 | dpll |= (crtc->config.pixel_multiplier - 1) |
5072 | << SDVO_MULTIPLIER_SHIFT_HIRES; | |
eb1cbe48 | 5073 | } |
198a037f DV |
5074 | |
5075 | if (is_sdvo) | |
4a33e48d | 5076 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 5077 | |
f47709a9 | 5078 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) |
4a33e48d | 5079 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
5080 | |
5081 | /* compute bitmask from p1 value */ | |
5082 | if (IS_PINEVIEW(dev)) | |
5083 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
5084 | else { | |
5085 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5086 | if (IS_G4X(dev) && reduced_clock) | |
5087 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
5088 | } | |
5089 | switch (clock->p2) { | |
5090 | case 5: | |
5091 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
5092 | break; | |
5093 | case 7: | |
5094 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
5095 | break; | |
5096 | case 10: | |
5097 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
5098 | break; | |
5099 | case 14: | |
5100 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
5101 | break; | |
5102 | } | |
5103 | if (INTEL_INFO(dev)->gen >= 4) | |
5104 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
5105 | ||
09ede541 | 5106 | if (crtc->config.sdvo_tv_clock) |
eb1cbe48 | 5107 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
f47709a9 | 5108 | else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
5109 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
5110 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
5111 | else | |
5112 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5113 | ||
5114 | dpll |= DPLL_VCO_ENABLE; | |
8bcc2795 DV |
5115 | crtc->config.dpll_hw_state.dpll = dpll; |
5116 | ||
eb1cbe48 | 5117 | if (INTEL_INFO(dev)->gen >= 4) { |
ef1b460d DV |
5118 | u32 dpll_md = (crtc->config.pixel_multiplier - 1) |
5119 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
8bcc2795 | 5120 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 | 5121 | } |
66e3d5c0 DV |
5122 | |
5123 | if (crtc->config.has_dp_encoder) | |
5124 | intel_dp_set_m_n(crtc); | |
eb1cbe48 DV |
5125 | } |
5126 | ||
f47709a9 | 5127 | static void i8xx_update_pll(struct intel_crtc *crtc, |
f47709a9 | 5128 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
5129 | int num_connectors) |
5130 | { | |
f47709a9 | 5131 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 5132 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 5133 | u32 dpll; |
f47709a9 | 5134 | struct dpll *clock = &crtc->config.dpll; |
eb1cbe48 | 5135 | |
f47709a9 | 5136 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 5137 | |
eb1cbe48 DV |
5138 | dpll = DPLL_VGA_MODE_DIS; |
5139 | ||
f47709a9 | 5140 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
5141 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
5142 | } else { | |
5143 | if (clock->p1 == 2) | |
5144 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
5145 | else | |
5146 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5147 | if (clock->p2 == 4) | |
5148 | dpll |= PLL_P2_DIVIDE_BY_4; | |
5149 | } | |
5150 | ||
4a33e48d DV |
5151 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO)) |
5152 | dpll |= DPLL_DVO_2X_MODE; | |
5153 | ||
f47709a9 | 5154 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
5155 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
5156 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
5157 | else | |
5158 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5159 | ||
5160 | dpll |= DPLL_VCO_ENABLE; | |
8bcc2795 | 5161 | crtc->config.dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
5162 | } |
5163 | ||
8a654f3b | 5164 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
5165 | { |
5166 | struct drm_device *dev = intel_crtc->base.dev; | |
5167 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5168 | enum pipe pipe = intel_crtc->pipe; | |
3b117c8f | 5169 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
8a654f3b DV |
5170 | struct drm_display_mode *adjusted_mode = |
5171 | &intel_crtc->config.adjusted_mode; | |
4d8a62ea DV |
5172 | uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end; |
5173 | ||
5174 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
5175 | * the hw state checker will get angry at the mismatch. */ | |
5176 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
5177 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c PZ |
5178 | |
5179 | if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { | |
5180 | /* the chip adds 2 halflines automatically */ | |
4d8a62ea DV |
5181 | crtc_vtotal -= 1; |
5182 | crtc_vblank_end -= 1; | |
b0e77b9c PZ |
5183 | vsyncshift = adjusted_mode->crtc_hsync_start |
5184 | - adjusted_mode->crtc_htotal / 2; | |
5185 | } else { | |
5186 | vsyncshift = 0; | |
5187 | } | |
5188 | ||
5189 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 5190 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 5191 | |
fe2b8f9d | 5192 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
5193 | (adjusted_mode->crtc_hdisplay - 1) | |
5194 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 5195 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
5196 | (adjusted_mode->crtc_hblank_start - 1) | |
5197 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 5198 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
5199 | (adjusted_mode->crtc_hsync_start - 1) | |
5200 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
5201 | ||
fe2b8f9d | 5202 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 5203 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 5204 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 5205 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 5206 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 5207 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 5208 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
5209 | (adjusted_mode->crtc_vsync_start - 1) | |
5210 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
5211 | ||
b5e508d4 PZ |
5212 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
5213 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
5214 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
5215 | * bits. */ | |
5216 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
5217 | (pipe == PIPE_B || pipe == PIPE_C)) | |
5218 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
5219 | ||
b0e77b9c PZ |
5220 | /* pipesrc controls the size that is scaled from, which should |
5221 | * always be the user's requested size. | |
5222 | */ | |
5223 | I915_WRITE(PIPESRC(pipe), | |
37327abd VS |
5224 | ((intel_crtc->config.pipe_src_w - 1) << 16) | |
5225 | (intel_crtc->config.pipe_src_h - 1)); | |
b0e77b9c PZ |
5226 | } |
5227 | ||
1bd1bd80 DV |
5228 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5229 | struct intel_crtc_config *pipe_config) | |
5230 | { | |
5231 | struct drm_device *dev = crtc->base.dev; | |
5232 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5233 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
5234 | uint32_t tmp; | |
5235 | ||
5236 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
5237 | pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; | |
5238 | pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
5239 | tmp = I915_READ(HBLANK(cpu_transcoder)); | |
5240 | pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; | |
5241 | pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
5242 | tmp = I915_READ(HSYNC(cpu_transcoder)); | |
5243 | pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; | |
5244 | pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
5245 | ||
5246 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
5247 | pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; | |
5248 | pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
5249 | tmp = I915_READ(VBLANK(cpu_transcoder)); | |
5250 | pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; | |
5251 | pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
5252 | tmp = I915_READ(VSYNC(cpu_transcoder)); | |
5253 | pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; | |
5254 | pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
5255 | ||
5256 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
5257 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; | |
5258 | pipe_config->adjusted_mode.crtc_vtotal += 1; | |
5259 | pipe_config->adjusted_mode.crtc_vblank_end += 1; | |
5260 | } | |
5261 | ||
5262 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
5263 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
5264 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
5265 | ||
5266 | pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h; | |
5267 | pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
5268 | } |
5269 | ||
babea61d JB |
5270 | static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc, |
5271 | struct intel_crtc_config *pipe_config) | |
5272 | { | |
5273 | struct drm_crtc *crtc = &intel_crtc->base; | |
5274 | ||
5275 | crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay; | |
5276 | crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal; | |
5277 | crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start; | |
5278 | crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end; | |
5279 | ||
5280 | crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay; | |
5281 | crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal; | |
5282 | crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start; | |
5283 | crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end; | |
5284 | ||
5285 | crtc->mode.flags = pipe_config->adjusted_mode.flags; | |
5286 | ||
241bfc38 | 5287 | crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock; |
babea61d JB |
5288 | crtc->mode.flags |= pipe_config->adjusted_mode.flags; |
5289 | } | |
5290 | ||
84b046f3 DV |
5291 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
5292 | { | |
5293 | struct drm_device *dev = intel_crtc->base.dev; | |
5294 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5295 | uint32_t pipeconf; | |
5296 | ||
9f11a9e4 | 5297 | pipeconf = 0; |
84b046f3 | 5298 | |
67c72a12 DV |
5299 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
5300 | I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE) | |
5301 | pipeconf |= PIPECONF_ENABLE; | |
5302 | ||
cf532bb2 VS |
5303 | if (intel_crtc->config.double_wide) |
5304 | pipeconf |= PIPECONF_DOUBLE_WIDE; | |
84b046f3 | 5305 | |
ff9ce46e DV |
5306 | /* only g4x and later have fancy bpc/dither controls */ |
5307 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { | |
ff9ce46e DV |
5308 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
5309 | if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30) | |
5310 | pipeconf |= PIPECONF_DITHER_EN | | |
84b046f3 | 5311 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 5312 | |
ff9ce46e DV |
5313 | switch (intel_crtc->config.pipe_bpp) { |
5314 | case 18: | |
5315 | pipeconf |= PIPECONF_6BPC; | |
5316 | break; | |
5317 | case 24: | |
5318 | pipeconf |= PIPECONF_8BPC; | |
5319 | break; | |
5320 | case 30: | |
5321 | pipeconf |= PIPECONF_10BPC; | |
5322 | break; | |
5323 | default: | |
5324 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
5325 | BUG(); | |
84b046f3 DV |
5326 | } |
5327 | } | |
5328 | ||
5329 | if (HAS_PIPE_CXSR(dev)) { | |
5330 | if (intel_crtc->lowfreq_avail) { | |
5331 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
5332 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
5333 | } else { | |
5334 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
5335 | } |
5336 | } | |
5337 | ||
84b046f3 DV |
5338 | if (!IS_GEN2(dev) && |
5339 | intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) | |
5340 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; | |
5341 | else | |
5342 | pipeconf |= PIPECONF_PROGRESSIVE; | |
5343 | ||
9f11a9e4 DV |
5344 | if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range) |
5345 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; | |
9c8e09b7 | 5346 | |
84b046f3 DV |
5347 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
5348 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
5349 | } | |
5350 | ||
f564048e | 5351 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
f564048e | 5352 | int x, int y, |
94352cf9 | 5353 | struct drm_framebuffer *fb) |
79e53945 JB |
5354 | { |
5355 | struct drm_device *dev = crtc->dev; | |
5356 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5357 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5358 | int pipe = intel_crtc->pipe; | |
80824003 | 5359 | int plane = intel_crtc->plane; |
c751ce4f | 5360 | int refclk, num_connectors = 0; |
652c393a | 5361 | intel_clock_t clock, reduced_clock; |
84b046f3 | 5362 | u32 dspcntr; |
a16af721 | 5363 | bool ok, has_reduced_clock = false; |
e9fd1c02 | 5364 | bool is_lvds = false, is_dsi = false; |
5eddb70b | 5365 | struct intel_encoder *encoder; |
d4906093 | 5366 | const intel_limit_t *limit; |
5c3b82e2 | 5367 | int ret; |
79e53945 | 5368 | |
6c2b7c12 | 5369 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5eddb70b | 5370 | switch (encoder->type) { |
79e53945 JB |
5371 | case INTEL_OUTPUT_LVDS: |
5372 | is_lvds = true; | |
5373 | break; | |
e9fd1c02 JN |
5374 | case INTEL_OUTPUT_DSI: |
5375 | is_dsi = true; | |
5376 | break; | |
79e53945 | 5377 | } |
43565a06 | 5378 | |
c751ce4f | 5379 | num_connectors++; |
79e53945 JB |
5380 | } |
5381 | ||
f2335330 JN |
5382 | if (is_dsi) |
5383 | goto skip_dpll; | |
5384 | ||
5385 | if (!intel_crtc->config.clock_set) { | |
5386 | refclk = i9xx_get_refclk(crtc, num_connectors); | |
79e53945 | 5387 | |
e9fd1c02 JN |
5388 | /* |
5389 | * Returns a set of divisors for the desired target clock with | |
5390 | * the given refclk, or FALSE. The returned values represent | |
5391 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
5392 | * 2) / p1 / p2. | |
5393 | */ | |
5394 | limit = intel_limit(crtc, refclk); | |
5395 | ok = dev_priv->display.find_dpll(limit, crtc, | |
5396 | intel_crtc->config.port_clock, | |
5397 | refclk, NULL, &clock); | |
f2335330 | 5398 | if (!ok) { |
e9fd1c02 JN |
5399 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
5400 | return -EINVAL; | |
5401 | } | |
79e53945 | 5402 | |
f2335330 JN |
5403 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
5404 | /* | |
5405 | * Ensure we match the reduced clock's P to the target | |
5406 | * clock. If the clocks don't match, we can't switch | |
5407 | * the display clock by using the FP0/FP1. In such case | |
5408 | * we will disable the LVDS downclock feature. | |
5409 | */ | |
5410 | has_reduced_clock = | |
5411 | dev_priv->display.find_dpll(limit, crtc, | |
5412 | dev_priv->lvds_downclock, | |
5413 | refclk, &clock, | |
5414 | &reduced_clock); | |
5415 | } | |
5416 | /* Compat-code for transition, will disappear. */ | |
f47709a9 DV |
5417 | intel_crtc->config.dpll.n = clock.n; |
5418 | intel_crtc->config.dpll.m1 = clock.m1; | |
5419 | intel_crtc->config.dpll.m2 = clock.m2; | |
5420 | intel_crtc->config.dpll.p1 = clock.p1; | |
5421 | intel_crtc->config.dpll.p2 = clock.p2; | |
5422 | } | |
7026d4ac | 5423 | |
e9fd1c02 | 5424 | if (IS_GEN2(dev)) { |
8a654f3b | 5425 | i8xx_update_pll(intel_crtc, |
2a8f64ca VP |
5426 | has_reduced_clock ? &reduced_clock : NULL, |
5427 | num_connectors); | |
e9fd1c02 | 5428 | } else if (IS_VALLEYVIEW(dev)) { |
f2335330 | 5429 | vlv_update_pll(intel_crtc); |
e9fd1c02 | 5430 | } else { |
f47709a9 | 5431 | i9xx_update_pll(intel_crtc, |
eb1cbe48 | 5432 | has_reduced_clock ? &reduced_clock : NULL, |
89b667f8 | 5433 | num_connectors); |
e9fd1c02 | 5434 | } |
79e53945 | 5435 | |
f2335330 | 5436 | skip_dpll: |
79e53945 JB |
5437 | /* Set up the display plane register */ |
5438 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
5439 | ||
da6ecc5d JB |
5440 | if (!IS_VALLEYVIEW(dev)) { |
5441 | if (pipe == 0) | |
5442 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; | |
5443 | else | |
5444 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
5445 | } | |
79e53945 | 5446 | |
8a654f3b | 5447 | intel_set_pipe_timings(intel_crtc); |
5eddb70b CW |
5448 | |
5449 | /* pipesrc and dspsize control the size that is scaled from, | |
5450 | * which should always be the user's requested size. | |
79e53945 | 5451 | */ |
929c77fb | 5452 | I915_WRITE(DSPSIZE(plane), |
37327abd VS |
5453 | ((intel_crtc->config.pipe_src_h - 1) << 16) | |
5454 | (intel_crtc->config.pipe_src_w - 1)); | |
929c77fb | 5455 | I915_WRITE(DSPPOS(plane), 0); |
2c07245f | 5456 | |
84b046f3 DV |
5457 | i9xx_set_pipeconf(intel_crtc); |
5458 | ||
f564048e EA |
5459 | I915_WRITE(DSPCNTR(plane), dspcntr); |
5460 | POSTING_READ(DSPCNTR(plane)); | |
5461 | ||
94352cf9 | 5462 | ret = intel_pipe_set_base(crtc, x, y, fb); |
f564048e | 5463 | |
f564048e EA |
5464 | return ret; |
5465 | } | |
5466 | ||
2fa2fe9a DV |
5467 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5468 | struct intel_crtc_config *pipe_config) | |
5469 | { | |
5470 | struct drm_device *dev = crtc->base.dev; | |
5471 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5472 | uint32_t tmp; | |
5473 | ||
dc9e7dec VS |
5474 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
5475 | return; | |
5476 | ||
2fa2fe9a | 5477 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
5478 | if (!(tmp & PFIT_ENABLE)) |
5479 | return; | |
2fa2fe9a | 5480 | |
06922821 | 5481 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
5482 | if (INTEL_INFO(dev)->gen < 4) { |
5483 | if (crtc->pipe != PIPE_B) | |
5484 | return; | |
2fa2fe9a DV |
5485 | } else { |
5486 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
5487 | return; | |
5488 | } | |
5489 | ||
06922821 | 5490 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
5491 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
5492 | if (INTEL_INFO(dev)->gen < 5) | |
5493 | pipe_config->gmch_pfit.lvds_border_bits = | |
5494 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
5495 | } | |
5496 | ||
acbec814 JB |
5497 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5498 | struct intel_crtc_config *pipe_config) | |
5499 | { | |
5500 | struct drm_device *dev = crtc->base.dev; | |
5501 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5502 | int pipe = pipe_config->cpu_transcoder; | |
5503 | intel_clock_t clock; | |
5504 | u32 mdiv; | |
662c6ecb | 5505 | int refclk = 100000; |
acbec814 JB |
5506 | |
5507 | mutex_lock(&dev_priv->dpio_lock); | |
ab3c759a | 5508 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
acbec814 JB |
5509 | mutex_unlock(&dev_priv->dpio_lock); |
5510 | ||
5511 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
5512 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
5513 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
5514 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
5515 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
5516 | ||
f646628b | 5517 | vlv_clock(refclk, &clock); |
acbec814 | 5518 | |
f646628b VS |
5519 | /* clock.dot is the fast clock */ |
5520 | pipe_config->port_clock = clock.dot / 5; | |
acbec814 JB |
5521 | } |
5522 | ||
0e8ffe1b DV |
5523 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5524 | struct intel_crtc_config *pipe_config) | |
5525 | { | |
5526 | struct drm_device *dev = crtc->base.dev; | |
5527 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5528 | uint32_t tmp; | |
5529 | ||
e143a21c | 5530 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 5531 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 5532 | |
0e8ffe1b DV |
5533 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
5534 | if (!(tmp & PIPECONF_ENABLE)) | |
5535 | return false; | |
5536 | ||
42571aef VS |
5537 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
5538 | switch (tmp & PIPECONF_BPC_MASK) { | |
5539 | case PIPECONF_6BPC: | |
5540 | pipe_config->pipe_bpp = 18; | |
5541 | break; | |
5542 | case PIPECONF_8BPC: | |
5543 | pipe_config->pipe_bpp = 24; | |
5544 | break; | |
5545 | case PIPECONF_10BPC: | |
5546 | pipe_config->pipe_bpp = 30; | |
5547 | break; | |
5548 | default: | |
5549 | break; | |
5550 | } | |
5551 | } | |
5552 | ||
282740f7 VS |
5553 | if (INTEL_INFO(dev)->gen < 4) |
5554 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
5555 | ||
1bd1bd80 DV |
5556 | intel_get_pipe_timings(crtc, pipe_config); |
5557 | ||
2fa2fe9a DV |
5558 | i9xx_get_pfit_config(crtc, pipe_config); |
5559 | ||
6c49f241 DV |
5560 | if (INTEL_INFO(dev)->gen >= 4) { |
5561 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
5562 | pipe_config->pixel_multiplier = | |
5563 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
5564 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 5565 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
5566 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
5567 | tmp = I915_READ(DPLL(crtc->pipe)); | |
5568 | pipe_config->pixel_multiplier = | |
5569 | ((tmp & SDVO_MULTIPLIER_MASK) | |
5570 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
5571 | } else { | |
5572 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
5573 | * port and will be fixed up in the encoder->get_config | |
5574 | * function. */ | |
5575 | pipe_config->pixel_multiplier = 1; | |
5576 | } | |
8bcc2795 DV |
5577 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
5578 | if (!IS_VALLEYVIEW(dev)) { | |
5579 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); | |
5580 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
5581 | } else { |
5582 | /* Mask out read-only status bits. */ | |
5583 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
5584 | DPLL_PORTC_READY_MASK | | |
5585 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 5586 | } |
6c49f241 | 5587 | |
acbec814 JB |
5588 | if (IS_VALLEYVIEW(dev)) |
5589 | vlv_crtc_clock_get(crtc, pipe_config); | |
5590 | else | |
5591 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 5592 | |
0e8ffe1b DV |
5593 | return true; |
5594 | } | |
5595 | ||
dde86e2d | 5596 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
5597 | { |
5598 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5599 | struct drm_mode_config *mode_config = &dev->mode_config; | |
13d83a67 | 5600 | struct intel_encoder *encoder; |
74cfd7ac | 5601 | u32 val, final; |
13d83a67 | 5602 | bool has_lvds = false; |
199e5d79 | 5603 | bool has_cpu_edp = false; |
199e5d79 | 5604 | bool has_panel = false; |
99eb6a01 KP |
5605 | bool has_ck505 = false; |
5606 | bool can_ssc = false; | |
13d83a67 JB |
5607 | |
5608 | /* We need to take the global config into account */ | |
199e5d79 KP |
5609 | list_for_each_entry(encoder, &mode_config->encoder_list, |
5610 | base.head) { | |
5611 | switch (encoder->type) { | |
5612 | case INTEL_OUTPUT_LVDS: | |
5613 | has_panel = true; | |
5614 | has_lvds = true; | |
5615 | break; | |
5616 | case INTEL_OUTPUT_EDP: | |
5617 | has_panel = true; | |
2de6905f | 5618 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
5619 | has_cpu_edp = true; |
5620 | break; | |
13d83a67 JB |
5621 | } |
5622 | } | |
5623 | ||
99eb6a01 | 5624 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 5625 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
5626 | can_ssc = has_ck505; |
5627 | } else { | |
5628 | has_ck505 = false; | |
5629 | can_ssc = true; | |
5630 | } | |
5631 | ||
2de6905f ID |
5632 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
5633 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
5634 | |
5635 | /* Ironlake: try to setup display ref clock before DPLL | |
5636 | * enabling. This is only under driver's control after | |
5637 | * PCH B stepping, previous chipset stepping should be | |
5638 | * ignoring this setting. | |
5639 | */ | |
74cfd7ac CW |
5640 | val = I915_READ(PCH_DREF_CONTROL); |
5641 | ||
5642 | /* As we must carefully and slowly disable/enable each source in turn, | |
5643 | * compute the final state we want first and check if we need to | |
5644 | * make any changes at all. | |
5645 | */ | |
5646 | final = val; | |
5647 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
5648 | if (has_ck505) | |
5649 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
5650 | else | |
5651 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
5652 | ||
5653 | final &= ~DREF_SSC_SOURCE_MASK; | |
5654 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
5655 | final &= ~DREF_SSC1_ENABLE; | |
5656 | ||
5657 | if (has_panel) { | |
5658 | final |= DREF_SSC_SOURCE_ENABLE; | |
5659 | ||
5660 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
5661 | final |= DREF_SSC1_ENABLE; | |
5662 | ||
5663 | if (has_cpu_edp) { | |
5664 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
5665 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
5666 | else | |
5667 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
5668 | } else | |
5669 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
5670 | } else { | |
5671 | final |= DREF_SSC_SOURCE_DISABLE; | |
5672 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
5673 | } | |
5674 | ||
5675 | if (final == val) | |
5676 | return; | |
5677 | ||
13d83a67 | 5678 | /* Always enable nonspread source */ |
74cfd7ac | 5679 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 5680 | |
99eb6a01 | 5681 | if (has_ck505) |
74cfd7ac | 5682 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 5683 | else |
74cfd7ac | 5684 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 5685 | |
199e5d79 | 5686 | if (has_panel) { |
74cfd7ac CW |
5687 | val &= ~DREF_SSC_SOURCE_MASK; |
5688 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 5689 | |
199e5d79 | 5690 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 5691 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 5692 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 5693 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 5694 | } else |
74cfd7ac | 5695 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
5696 | |
5697 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 5698 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
5699 | POSTING_READ(PCH_DREF_CONTROL); |
5700 | udelay(200); | |
5701 | ||
74cfd7ac | 5702 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
5703 | |
5704 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 5705 | if (has_cpu_edp) { |
99eb6a01 | 5706 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 5707 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 5708 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
199e5d79 | 5709 | } |
13d83a67 | 5710 | else |
74cfd7ac | 5711 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 5712 | } else |
74cfd7ac | 5713 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 5714 | |
74cfd7ac | 5715 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
5716 | POSTING_READ(PCH_DREF_CONTROL); |
5717 | udelay(200); | |
5718 | } else { | |
5719 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
5720 | ||
74cfd7ac | 5721 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
5722 | |
5723 | /* Turn off CPU output */ | |
74cfd7ac | 5724 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 5725 | |
74cfd7ac | 5726 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
5727 | POSTING_READ(PCH_DREF_CONTROL); |
5728 | udelay(200); | |
5729 | ||
5730 | /* Turn off the SSC source */ | |
74cfd7ac CW |
5731 | val &= ~DREF_SSC_SOURCE_MASK; |
5732 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
5733 | |
5734 | /* Turn off SSC1 */ | |
74cfd7ac | 5735 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 5736 | |
74cfd7ac | 5737 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
5738 | POSTING_READ(PCH_DREF_CONTROL); |
5739 | udelay(200); | |
5740 | } | |
74cfd7ac CW |
5741 | |
5742 | BUG_ON(val != final); | |
13d83a67 JB |
5743 | } |
5744 | ||
f31f2d55 | 5745 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 5746 | { |
f31f2d55 | 5747 | uint32_t tmp; |
dde86e2d | 5748 | |
0ff066a9 PZ |
5749 | tmp = I915_READ(SOUTH_CHICKEN2); |
5750 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
5751 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 5752 | |
0ff066a9 PZ |
5753 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
5754 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
5755 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 5756 | |
0ff066a9 PZ |
5757 | tmp = I915_READ(SOUTH_CHICKEN2); |
5758 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
5759 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 5760 | |
0ff066a9 PZ |
5761 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
5762 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
5763 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
5764 | } |
5765 | ||
5766 | /* WaMPhyProgramming:hsw */ | |
5767 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
5768 | { | |
5769 | uint32_t tmp; | |
dde86e2d PZ |
5770 | |
5771 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
5772 | tmp &= ~(0xFF << 24); | |
5773 | tmp |= (0x12 << 24); | |
5774 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
5775 | ||
dde86e2d PZ |
5776 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
5777 | tmp |= (1 << 11); | |
5778 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
5779 | ||
5780 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
5781 | tmp |= (1 << 11); | |
5782 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
5783 | ||
dde86e2d PZ |
5784 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
5785 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
5786 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
5787 | ||
5788 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
5789 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
5790 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
5791 | ||
0ff066a9 PZ |
5792 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
5793 | tmp &= ~(7 << 13); | |
5794 | tmp |= (5 << 13); | |
5795 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 5796 | |
0ff066a9 PZ |
5797 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
5798 | tmp &= ~(7 << 13); | |
5799 | tmp |= (5 << 13); | |
5800 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
5801 | |
5802 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
5803 | tmp &= ~0xFF; | |
5804 | tmp |= 0x1C; | |
5805 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
5806 | ||
5807 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
5808 | tmp &= ~0xFF; | |
5809 | tmp |= 0x1C; | |
5810 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
5811 | ||
5812 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
5813 | tmp &= ~(0xFF << 16); | |
5814 | tmp |= (0x1C << 16); | |
5815 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
5816 | ||
5817 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
5818 | tmp &= ~(0xFF << 16); | |
5819 | tmp |= (0x1C << 16); | |
5820 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
5821 | ||
0ff066a9 PZ |
5822 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
5823 | tmp |= (1 << 27); | |
5824 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 5825 | |
0ff066a9 PZ |
5826 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
5827 | tmp |= (1 << 27); | |
5828 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 5829 | |
0ff066a9 PZ |
5830 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
5831 | tmp &= ~(0xF << 28); | |
5832 | tmp |= (4 << 28); | |
5833 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 5834 | |
0ff066a9 PZ |
5835 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
5836 | tmp &= ~(0xF << 28); | |
5837 | tmp |= (4 << 28); | |
5838 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
5839 | } |
5840 | ||
2fa86a1f PZ |
5841 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
5842 | * Programming" based on the parameters passed: | |
5843 | * - Sequence to enable CLKOUT_DP | |
5844 | * - Sequence to enable CLKOUT_DP without spread | |
5845 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
5846 | */ | |
5847 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
5848 | bool with_fdi) | |
f31f2d55 PZ |
5849 | { |
5850 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
5851 | uint32_t reg, tmp; |
5852 | ||
5853 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
5854 | with_spread = true; | |
5855 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && | |
5856 | with_fdi, "LP PCH doesn't have FDI\n")) | |
5857 | with_fdi = false; | |
f31f2d55 PZ |
5858 | |
5859 | mutex_lock(&dev_priv->dpio_lock); | |
5860 | ||
5861 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
5862 | tmp &= ~SBI_SSCCTL_DISABLE; | |
5863 | tmp |= SBI_SSCCTL_PATHALT; | |
5864 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
5865 | ||
5866 | udelay(24); | |
5867 | ||
2fa86a1f PZ |
5868 | if (with_spread) { |
5869 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
5870 | tmp &= ~SBI_SSCCTL_PATHALT; | |
5871 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 5872 | |
2fa86a1f PZ |
5873 | if (with_fdi) { |
5874 | lpt_reset_fdi_mphy(dev_priv); | |
5875 | lpt_program_fdi_mphy(dev_priv); | |
5876 | } | |
5877 | } | |
dde86e2d | 5878 | |
2fa86a1f PZ |
5879 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
5880 | SBI_GEN0 : SBI_DBUFF0; | |
5881 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
5882 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
5883 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 DV |
5884 | |
5885 | mutex_unlock(&dev_priv->dpio_lock); | |
dde86e2d PZ |
5886 | } |
5887 | ||
47701c3b PZ |
5888 | /* Sequence to disable CLKOUT_DP */ |
5889 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
5890 | { | |
5891 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5892 | uint32_t reg, tmp; | |
5893 | ||
5894 | mutex_lock(&dev_priv->dpio_lock); | |
5895 | ||
5896 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? | |
5897 | SBI_GEN0 : SBI_DBUFF0; | |
5898 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
5899 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
5900 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
5901 | ||
5902 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
5903 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
5904 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
5905 | tmp |= SBI_SSCCTL_PATHALT; | |
5906 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
5907 | udelay(32); | |
5908 | } | |
5909 | tmp |= SBI_SSCCTL_DISABLE; | |
5910 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
5911 | } | |
5912 | ||
5913 | mutex_unlock(&dev_priv->dpio_lock); | |
5914 | } | |
5915 | ||
bf8fa3d3 PZ |
5916 | static void lpt_init_pch_refclk(struct drm_device *dev) |
5917 | { | |
5918 | struct drm_mode_config *mode_config = &dev->mode_config; | |
5919 | struct intel_encoder *encoder; | |
5920 | bool has_vga = false; | |
5921 | ||
5922 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { | |
5923 | switch (encoder->type) { | |
5924 | case INTEL_OUTPUT_ANALOG: | |
5925 | has_vga = true; | |
5926 | break; | |
5927 | } | |
5928 | } | |
5929 | ||
47701c3b PZ |
5930 | if (has_vga) |
5931 | lpt_enable_clkout_dp(dev, true, true); | |
5932 | else | |
5933 | lpt_disable_clkout_dp(dev); | |
bf8fa3d3 PZ |
5934 | } |
5935 | ||
dde86e2d PZ |
5936 | /* |
5937 | * Initialize reference clocks when the driver loads | |
5938 | */ | |
5939 | void intel_init_pch_refclk(struct drm_device *dev) | |
5940 | { | |
5941 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
5942 | ironlake_init_pch_refclk(dev); | |
5943 | else if (HAS_PCH_LPT(dev)) | |
5944 | lpt_init_pch_refclk(dev); | |
5945 | } | |
5946 | ||
d9d444cb JB |
5947 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
5948 | { | |
5949 | struct drm_device *dev = crtc->dev; | |
5950 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5951 | struct intel_encoder *encoder; | |
d9d444cb JB |
5952 | int num_connectors = 0; |
5953 | bool is_lvds = false; | |
5954 | ||
6c2b7c12 | 5955 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
d9d444cb JB |
5956 | switch (encoder->type) { |
5957 | case INTEL_OUTPUT_LVDS: | |
5958 | is_lvds = true; | |
5959 | break; | |
d9d444cb JB |
5960 | } |
5961 | num_connectors++; | |
5962 | } | |
5963 | ||
5964 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 5965 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 5966 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 5967 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
5968 | } |
5969 | ||
5970 | return 120000; | |
5971 | } | |
5972 | ||
6ff93609 | 5973 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 5974 | { |
c8203565 | 5975 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
5976 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5977 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
5978 | uint32_t val; |
5979 | ||
78114071 | 5980 | val = 0; |
c8203565 | 5981 | |
965e0c48 | 5982 | switch (intel_crtc->config.pipe_bpp) { |
c8203565 | 5983 | case 18: |
dfd07d72 | 5984 | val |= PIPECONF_6BPC; |
c8203565 PZ |
5985 | break; |
5986 | case 24: | |
dfd07d72 | 5987 | val |= PIPECONF_8BPC; |
c8203565 PZ |
5988 | break; |
5989 | case 30: | |
dfd07d72 | 5990 | val |= PIPECONF_10BPC; |
c8203565 PZ |
5991 | break; |
5992 | case 36: | |
dfd07d72 | 5993 | val |= PIPECONF_12BPC; |
c8203565 PZ |
5994 | break; |
5995 | default: | |
cc769b62 PZ |
5996 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
5997 | BUG(); | |
c8203565 PZ |
5998 | } |
5999 | ||
d8b32247 | 6000 | if (intel_crtc->config.dither) |
c8203565 PZ |
6001 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
6002 | ||
6ff93609 | 6003 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
6004 | val |= PIPECONF_INTERLACED_ILK; |
6005 | else | |
6006 | val |= PIPECONF_PROGRESSIVE; | |
6007 | ||
50f3b016 | 6008 | if (intel_crtc->config.limited_color_range) |
3685a8f3 | 6009 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 6010 | |
c8203565 PZ |
6011 | I915_WRITE(PIPECONF(pipe), val); |
6012 | POSTING_READ(PIPECONF(pipe)); | |
6013 | } | |
6014 | ||
86d3efce VS |
6015 | /* |
6016 | * Set up the pipe CSC unit. | |
6017 | * | |
6018 | * Currently only full range RGB to limited range RGB conversion | |
6019 | * is supported, but eventually this should handle various | |
6020 | * RGB<->YCbCr scenarios as well. | |
6021 | */ | |
50f3b016 | 6022 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
6023 | { |
6024 | struct drm_device *dev = crtc->dev; | |
6025 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6026 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6027 | int pipe = intel_crtc->pipe; | |
6028 | uint16_t coeff = 0x7800; /* 1.0 */ | |
6029 | ||
6030 | /* | |
6031 | * TODO: Check what kind of values actually come out of the pipe | |
6032 | * with these coeff/postoff values and adjust to get the best | |
6033 | * accuracy. Perhaps we even need to take the bpc value into | |
6034 | * consideration. | |
6035 | */ | |
6036 | ||
50f3b016 | 6037 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
6038 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
6039 | ||
6040 | /* | |
6041 | * GY/GU and RY/RU should be the other way around according | |
6042 | * to BSpec, but reality doesn't agree. Just set them up in | |
6043 | * a way that results in the correct picture. | |
6044 | */ | |
6045 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
6046 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
6047 | ||
6048 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
6049 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
6050 | ||
6051 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
6052 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
6053 | ||
6054 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
6055 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
6056 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
6057 | ||
6058 | if (INTEL_INFO(dev)->gen > 6) { | |
6059 | uint16_t postoff = 0; | |
6060 | ||
50f3b016 | 6061 | if (intel_crtc->config.limited_color_range) |
32cf0cb0 | 6062 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
6063 | |
6064 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
6065 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
6066 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
6067 | ||
6068 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
6069 | } else { | |
6070 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
6071 | ||
50f3b016 | 6072 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
6073 | mode |= CSC_BLACK_SCREEN_OFFSET; |
6074 | ||
6075 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
6076 | } | |
6077 | } | |
6078 | ||
6ff93609 | 6079 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 6080 | { |
756f85cf PZ |
6081 | struct drm_device *dev = crtc->dev; |
6082 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 6083 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 6084 | enum pipe pipe = intel_crtc->pipe; |
3b117c8f | 6085 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee2b0b38 PZ |
6086 | uint32_t val; |
6087 | ||
3eff4faa | 6088 | val = 0; |
ee2b0b38 | 6089 | |
756f85cf | 6090 | if (IS_HASWELL(dev) && intel_crtc->config.dither) |
ee2b0b38 PZ |
6091 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
6092 | ||
6ff93609 | 6093 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
6094 | val |= PIPECONF_INTERLACED_ILK; |
6095 | else | |
6096 | val |= PIPECONF_PROGRESSIVE; | |
6097 | ||
702e7a56 PZ |
6098 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
6099 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
6100 | |
6101 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
6102 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf PZ |
6103 | |
6104 | if (IS_BROADWELL(dev)) { | |
6105 | val = 0; | |
6106 | ||
6107 | switch (intel_crtc->config.pipe_bpp) { | |
6108 | case 18: | |
6109 | val |= PIPEMISC_DITHER_6_BPC; | |
6110 | break; | |
6111 | case 24: | |
6112 | val |= PIPEMISC_DITHER_8_BPC; | |
6113 | break; | |
6114 | case 30: | |
6115 | val |= PIPEMISC_DITHER_10_BPC; | |
6116 | break; | |
6117 | case 36: | |
6118 | val |= PIPEMISC_DITHER_12_BPC; | |
6119 | break; | |
6120 | default: | |
6121 | /* Case prevented by pipe_config_set_bpp. */ | |
6122 | BUG(); | |
6123 | } | |
6124 | ||
6125 | if (intel_crtc->config.dither) | |
6126 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; | |
6127 | ||
6128 | I915_WRITE(PIPEMISC(pipe), val); | |
6129 | } | |
ee2b0b38 PZ |
6130 | } |
6131 | ||
6591c6e4 | 6132 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
6591c6e4 PZ |
6133 | intel_clock_t *clock, |
6134 | bool *has_reduced_clock, | |
6135 | intel_clock_t *reduced_clock) | |
6136 | { | |
6137 | struct drm_device *dev = crtc->dev; | |
6138 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6139 | struct intel_encoder *intel_encoder; | |
6140 | int refclk; | |
d4906093 | 6141 | const intel_limit_t *limit; |
a16af721 | 6142 | bool ret, is_lvds = false; |
79e53945 | 6143 | |
6591c6e4 PZ |
6144 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
6145 | switch (intel_encoder->type) { | |
79e53945 JB |
6146 | case INTEL_OUTPUT_LVDS: |
6147 | is_lvds = true; | |
6148 | break; | |
79e53945 JB |
6149 | } |
6150 | } | |
6151 | ||
d9d444cb | 6152 | refclk = ironlake_get_refclk(crtc); |
79e53945 | 6153 | |
d4906093 ML |
6154 | /* |
6155 | * Returns a set of divisors for the desired target clock with the given | |
6156 | * refclk, or FALSE. The returned values represent the clock equation: | |
6157 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
6158 | */ | |
1b894b59 | 6159 | limit = intel_limit(crtc, refclk); |
ff9a6750 DV |
6160 | ret = dev_priv->display.find_dpll(limit, crtc, |
6161 | to_intel_crtc(crtc)->config.port_clock, | |
ee9300bb | 6162 | refclk, NULL, clock); |
6591c6e4 PZ |
6163 | if (!ret) |
6164 | return false; | |
cda4b7d3 | 6165 | |
ddc9003c | 6166 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
6167 | /* |
6168 | * Ensure we match the reduced clock's P to the target clock. | |
6169 | * If the clocks don't match, we can't switch the display clock | |
6170 | * by using the FP0/FP1. In such case we will disable the LVDS | |
6171 | * downclock feature. | |
6172 | */ | |
ee9300bb DV |
6173 | *has_reduced_clock = |
6174 | dev_priv->display.find_dpll(limit, crtc, | |
6175 | dev_priv->lvds_downclock, | |
6176 | refclk, clock, | |
6177 | reduced_clock); | |
652c393a | 6178 | } |
61e9653f | 6179 | |
6591c6e4 PZ |
6180 | return true; |
6181 | } | |
6182 | ||
d4b1931c PZ |
6183 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
6184 | { | |
6185 | /* | |
6186 | * Account for spread spectrum to avoid | |
6187 | * oversubscribing the link. Max center spread | |
6188 | * is 2.5%; use 5% for safety's sake. | |
6189 | */ | |
6190 | u32 bps = target_clock * bpp * 21 / 20; | |
6191 | return bps / (link_bw * 8) + 1; | |
6192 | } | |
6193 | ||
7429e9d4 | 6194 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 6195 | { |
7429e9d4 | 6196 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
6197 | } |
6198 | ||
de13a2e3 | 6199 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
7429e9d4 | 6200 | u32 *fp, |
9a7c7890 | 6201 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 6202 | { |
de13a2e3 | 6203 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
6204 | struct drm_device *dev = crtc->dev; |
6205 | struct drm_i915_private *dev_priv = dev->dev_private; | |
de13a2e3 PZ |
6206 | struct intel_encoder *intel_encoder; |
6207 | uint32_t dpll; | |
6cc5f341 | 6208 | int factor, num_connectors = 0; |
09ede541 | 6209 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 6210 | |
de13a2e3 PZ |
6211 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
6212 | switch (intel_encoder->type) { | |
79e53945 JB |
6213 | case INTEL_OUTPUT_LVDS: |
6214 | is_lvds = true; | |
6215 | break; | |
6216 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 6217 | case INTEL_OUTPUT_HDMI: |
79e53945 | 6218 | is_sdvo = true; |
79e53945 | 6219 | break; |
79e53945 | 6220 | } |
43565a06 | 6221 | |
c751ce4f | 6222 | num_connectors++; |
79e53945 | 6223 | } |
79e53945 | 6224 | |
c1858123 | 6225 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
6226 | factor = 21; |
6227 | if (is_lvds) { | |
6228 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 6229 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 6230 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 6231 | factor = 25; |
09ede541 | 6232 | } else if (intel_crtc->config.sdvo_tv_clock) |
8febb297 | 6233 | factor = 20; |
c1858123 | 6234 | |
7429e9d4 | 6235 | if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor)) |
7d0ac5b7 | 6236 | *fp |= FP_CB_TUNE; |
2c07245f | 6237 | |
9a7c7890 DV |
6238 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
6239 | *fp2 |= FP_CB_TUNE; | |
6240 | ||
5eddb70b | 6241 | dpll = 0; |
2c07245f | 6242 | |
a07d6787 EA |
6243 | if (is_lvds) |
6244 | dpll |= DPLLB_MODE_LVDS; | |
6245 | else | |
6246 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 6247 | |
ef1b460d DV |
6248 | dpll |= (intel_crtc->config.pixel_multiplier - 1) |
6249 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | |
198a037f DV |
6250 | |
6251 | if (is_sdvo) | |
4a33e48d | 6252 | dpll |= DPLL_SDVO_HIGH_SPEED; |
9566e9af | 6253 | if (intel_crtc->config.has_dp_encoder) |
4a33e48d | 6254 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 6255 | |
a07d6787 | 6256 | /* compute bitmask from p1 value */ |
7429e9d4 | 6257 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 6258 | /* also FPA1 */ |
7429e9d4 | 6259 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 6260 | |
7429e9d4 | 6261 | switch (intel_crtc->config.dpll.p2) { |
a07d6787 EA |
6262 | case 5: |
6263 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
6264 | break; | |
6265 | case 7: | |
6266 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
6267 | break; | |
6268 | case 10: | |
6269 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
6270 | break; | |
6271 | case 14: | |
6272 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
6273 | break; | |
79e53945 JB |
6274 | } |
6275 | ||
b4c09f3b | 6276 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 6277 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
6278 | else |
6279 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6280 | ||
959e16d6 | 6281 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
6282 | } |
6283 | ||
6284 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, | |
de13a2e3 PZ |
6285 | int x, int y, |
6286 | struct drm_framebuffer *fb) | |
6287 | { | |
6288 | struct drm_device *dev = crtc->dev; | |
6289 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6290 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6291 | int pipe = intel_crtc->pipe; | |
6292 | int plane = intel_crtc->plane; | |
6293 | int num_connectors = 0; | |
6294 | intel_clock_t clock, reduced_clock; | |
cbbab5bd | 6295 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 6296 | bool ok, has_reduced_clock = false; |
8b47047b | 6297 | bool is_lvds = false; |
de13a2e3 | 6298 | struct intel_encoder *encoder; |
e2b78267 | 6299 | struct intel_shared_dpll *pll; |
de13a2e3 | 6300 | int ret; |
de13a2e3 PZ |
6301 | |
6302 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
6303 | switch (encoder->type) { | |
6304 | case INTEL_OUTPUT_LVDS: | |
6305 | is_lvds = true; | |
6306 | break; | |
de13a2e3 PZ |
6307 | } |
6308 | ||
6309 | num_connectors++; | |
a07d6787 | 6310 | } |
79e53945 | 6311 | |
5dc5298b PZ |
6312 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
6313 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 6314 | |
ff9a6750 | 6315 | ok = ironlake_compute_clocks(crtc, &clock, |
de13a2e3 | 6316 | &has_reduced_clock, &reduced_clock); |
ee9300bb | 6317 | if (!ok && !intel_crtc->config.clock_set) { |
de13a2e3 PZ |
6318 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
6319 | return -EINVAL; | |
79e53945 | 6320 | } |
f47709a9 DV |
6321 | /* Compat-code for transition, will disappear. */ |
6322 | if (!intel_crtc->config.clock_set) { | |
6323 | intel_crtc->config.dpll.n = clock.n; | |
6324 | intel_crtc->config.dpll.m1 = clock.m1; | |
6325 | intel_crtc->config.dpll.m2 = clock.m2; | |
6326 | intel_crtc->config.dpll.p1 = clock.p1; | |
6327 | intel_crtc->config.dpll.p2 = clock.p2; | |
6328 | } | |
79e53945 | 6329 | |
5dc5298b | 6330 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
8b47047b | 6331 | if (intel_crtc->config.has_pch_encoder) { |
7429e9d4 | 6332 | fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll); |
cbbab5bd | 6333 | if (has_reduced_clock) |
7429e9d4 | 6334 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 6335 | |
7429e9d4 | 6336 | dpll = ironlake_compute_dpll(intel_crtc, |
cbbab5bd DV |
6337 | &fp, &reduced_clock, |
6338 | has_reduced_clock ? &fp2 : NULL); | |
6339 | ||
959e16d6 | 6340 | intel_crtc->config.dpll_hw_state.dpll = dpll; |
66e985c0 DV |
6341 | intel_crtc->config.dpll_hw_state.fp0 = fp; |
6342 | if (has_reduced_clock) | |
6343 | intel_crtc->config.dpll_hw_state.fp1 = fp2; | |
6344 | else | |
6345 | intel_crtc->config.dpll_hw_state.fp1 = fp; | |
6346 | ||
b89a1d39 | 6347 | pll = intel_get_shared_dpll(intel_crtc); |
ee7b9f93 | 6348 | if (pll == NULL) { |
84f44ce7 VS |
6349 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
6350 | pipe_name(pipe)); | |
4b645f14 JB |
6351 | return -EINVAL; |
6352 | } | |
ee7b9f93 | 6353 | } else |
e72f9fbf | 6354 | intel_put_shared_dpll(intel_crtc); |
79e53945 | 6355 | |
03afc4a2 DV |
6356 | if (intel_crtc->config.has_dp_encoder) |
6357 | intel_dp_set_m_n(intel_crtc); | |
79e53945 | 6358 | |
d330a953 | 6359 | if (is_lvds && has_reduced_clock && i915.powersave) |
bcd644e0 DV |
6360 | intel_crtc->lowfreq_avail = true; |
6361 | else | |
6362 | intel_crtc->lowfreq_avail = false; | |
e2b78267 | 6363 | |
8a654f3b | 6364 | intel_set_pipe_timings(intel_crtc); |
5eddb70b | 6365 | |
ca3a0ff8 | 6366 | if (intel_crtc->config.has_pch_encoder) { |
ca3a0ff8 DV |
6367 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6368 | &intel_crtc->config.fdi_m_n); | |
6369 | } | |
2c07245f | 6370 | |
6ff93609 | 6371 | ironlake_set_pipeconf(crtc); |
79e53945 | 6372 | |
a1f9e77e PZ |
6373 | /* Set up the display plane register */ |
6374 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); | |
b24e7179 | 6375 | POSTING_READ(DSPCNTR(plane)); |
79e53945 | 6376 | |
94352cf9 | 6377 | ret = intel_pipe_set_base(crtc, x, y, fb); |
7662c8bd | 6378 | |
1857e1da | 6379 | return ret; |
79e53945 JB |
6380 | } |
6381 | ||
eb14cb74 VS |
6382 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
6383 | struct intel_link_m_n *m_n) | |
6384 | { | |
6385 | struct drm_device *dev = crtc->base.dev; | |
6386 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6387 | enum pipe pipe = crtc->pipe; | |
6388 | ||
6389 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
6390 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
6391 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
6392 | & ~TU_SIZE_MASK; | |
6393 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
6394 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
6395 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
6396 | } | |
6397 | ||
6398 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
6399 | enum transcoder transcoder, | |
6400 | struct intel_link_m_n *m_n) | |
72419203 DV |
6401 | { |
6402 | struct drm_device *dev = crtc->base.dev; | |
6403 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 6404 | enum pipe pipe = crtc->pipe; |
72419203 | 6405 | |
eb14cb74 VS |
6406 | if (INTEL_INFO(dev)->gen >= 5) { |
6407 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
6408 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
6409 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
6410 | & ~TU_SIZE_MASK; | |
6411 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
6412 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
6413 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
6414 | } else { | |
6415 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
6416 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
6417 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
6418 | & ~TU_SIZE_MASK; | |
6419 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
6420 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
6421 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
6422 | } | |
6423 | } | |
6424 | ||
6425 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
6426 | struct intel_crtc_config *pipe_config) | |
6427 | { | |
6428 | if (crtc->config.has_pch_encoder) | |
6429 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); | |
6430 | else | |
6431 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
6432 | &pipe_config->dp_m_n); | |
6433 | } | |
72419203 | 6434 | |
eb14cb74 VS |
6435 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
6436 | struct intel_crtc_config *pipe_config) | |
6437 | { | |
6438 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
6439 | &pipe_config->fdi_m_n); | |
72419203 DV |
6440 | } |
6441 | ||
2fa2fe9a DV |
6442 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
6443 | struct intel_crtc_config *pipe_config) | |
6444 | { | |
6445 | struct drm_device *dev = crtc->base.dev; | |
6446 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6447 | uint32_t tmp; | |
6448 | ||
6449 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
6450 | ||
6451 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 6452 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
6453 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
6454 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
6455 | |
6456 | /* We currently do not free assignements of panel fitters on | |
6457 | * ivb/hsw (since we don't use the higher upscaling modes which | |
6458 | * differentiates them) so just WARN about this case for now. */ | |
6459 | if (IS_GEN7(dev)) { | |
6460 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
6461 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
6462 | } | |
2fa2fe9a | 6463 | } |
79e53945 JB |
6464 | } |
6465 | ||
0e8ffe1b DV |
6466 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
6467 | struct intel_crtc_config *pipe_config) | |
6468 | { | |
6469 | struct drm_device *dev = crtc->base.dev; | |
6470 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6471 | uint32_t tmp; | |
6472 | ||
e143a21c | 6473 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 6474 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 6475 | |
0e8ffe1b DV |
6476 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
6477 | if (!(tmp & PIPECONF_ENABLE)) | |
6478 | return false; | |
6479 | ||
42571aef VS |
6480 | switch (tmp & PIPECONF_BPC_MASK) { |
6481 | case PIPECONF_6BPC: | |
6482 | pipe_config->pipe_bpp = 18; | |
6483 | break; | |
6484 | case PIPECONF_8BPC: | |
6485 | pipe_config->pipe_bpp = 24; | |
6486 | break; | |
6487 | case PIPECONF_10BPC: | |
6488 | pipe_config->pipe_bpp = 30; | |
6489 | break; | |
6490 | case PIPECONF_12BPC: | |
6491 | pipe_config->pipe_bpp = 36; | |
6492 | break; | |
6493 | default: | |
6494 | break; | |
6495 | } | |
6496 | ||
ab9412ba | 6497 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
6498 | struct intel_shared_dpll *pll; |
6499 | ||
88adfff1 DV |
6500 | pipe_config->has_pch_encoder = true; |
6501 | ||
627eb5a3 DV |
6502 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
6503 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
6504 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
6505 | |
6506 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 6507 | |
c0d43d62 | 6508 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
6509 | pipe_config->shared_dpll = |
6510 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
6511 | } else { |
6512 | tmp = I915_READ(PCH_DPLL_SEL); | |
6513 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
6514 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
6515 | else | |
6516 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
6517 | } | |
66e985c0 DV |
6518 | |
6519 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
6520 | ||
6521 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
6522 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
6523 | |
6524 | tmp = pipe_config->dpll_hw_state.dpll; | |
6525 | pipe_config->pixel_multiplier = | |
6526 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
6527 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
6528 | |
6529 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
6530 | } else { |
6531 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
6532 | } |
6533 | ||
1bd1bd80 DV |
6534 | intel_get_pipe_timings(crtc, pipe_config); |
6535 | ||
2fa2fe9a DV |
6536 | ironlake_get_pfit_config(crtc, pipe_config); |
6537 | ||
0e8ffe1b DV |
6538 | return true; |
6539 | } | |
6540 | ||
be256dc7 PZ |
6541 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
6542 | { | |
6543 | struct drm_device *dev = dev_priv->dev; | |
6544 | struct intel_ddi_plls *plls = &dev_priv->ddi_plls; | |
6545 | struct intel_crtc *crtc; | |
6546 | unsigned long irqflags; | |
bd633a7c | 6547 | uint32_t val; |
be256dc7 PZ |
6548 | |
6549 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) | |
798183c5 | 6550 | WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
6551 | pipe_name(crtc->pipe)); |
6552 | ||
6553 | WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); | |
6554 | WARN(plls->spll_refcount, "SPLL enabled\n"); | |
6555 | WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n"); | |
6556 | WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n"); | |
6557 | WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); | |
6558 | WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
6559 | "CPU PWM1 enabled\n"); | |
6560 | WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, | |
6561 | "CPU PWM2 enabled\n"); | |
6562 | WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, | |
6563 | "PCH PWM1 enabled\n"); | |
6564 | WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, | |
6565 | "Utility pin enabled\n"); | |
6566 | WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); | |
6567 | ||
6568 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
6569 | val = I915_READ(DEIMR); | |
6806e63f | 6570 | WARN((val | DE_PCH_EVENT_IVB) != 0xffffffff, |
be256dc7 PZ |
6571 | "Unexpected DEIMR bits enabled: 0x%x\n", val); |
6572 | val = I915_READ(SDEIMR); | |
bd633a7c | 6573 | WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff, |
be256dc7 PZ |
6574 | "Unexpected SDEIMR bits enabled: 0x%x\n", val); |
6575 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
6576 | } | |
6577 | ||
6578 | /* | |
6579 | * This function implements pieces of two sequences from BSpec: | |
6580 | * - Sequence for display software to disable LCPLL | |
6581 | * - Sequence for display software to allow package C8+ | |
6582 | * The steps implemented here are just the steps that actually touch the LCPLL | |
6583 | * register. Callers should take care of disabling all the display engine | |
6584 | * functions, doing the mode unset, fixing interrupts, etc. | |
6585 | */ | |
6ff58d53 PZ |
6586 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
6587 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
6588 | { |
6589 | uint32_t val; | |
6590 | ||
6591 | assert_can_disable_lcpll(dev_priv); | |
6592 | ||
6593 | val = I915_READ(LCPLL_CTL); | |
6594 | ||
6595 | if (switch_to_fclk) { | |
6596 | val |= LCPLL_CD_SOURCE_FCLK; | |
6597 | I915_WRITE(LCPLL_CTL, val); | |
6598 | ||
6599 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
6600 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
6601 | DRM_ERROR("Switching to FCLK failed\n"); | |
6602 | ||
6603 | val = I915_READ(LCPLL_CTL); | |
6604 | } | |
6605 | ||
6606 | val |= LCPLL_PLL_DISABLE; | |
6607 | I915_WRITE(LCPLL_CTL, val); | |
6608 | POSTING_READ(LCPLL_CTL); | |
6609 | ||
6610 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
6611 | DRM_ERROR("LCPLL still locked\n"); | |
6612 | ||
6613 | val = I915_READ(D_COMP); | |
6614 | val |= D_COMP_COMP_DISABLE; | |
515b2392 PZ |
6615 | mutex_lock(&dev_priv->rps.hw_lock); |
6616 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val)) | |
6617 | DRM_ERROR("Failed to disable D_COMP\n"); | |
6618 | mutex_unlock(&dev_priv->rps.hw_lock); | |
be256dc7 PZ |
6619 | POSTING_READ(D_COMP); |
6620 | ndelay(100); | |
6621 | ||
6622 | if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1)) | |
6623 | DRM_ERROR("D_COMP RCOMP still in progress\n"); | |
6624 | ||
6625 | if (allow_power_down) { | |
6626 | val = I915_READ(LCPLL_CTL); | |
6627 | val |= LCPLL_POWER_DOWN_ALLOW; | |
6628 | I915_WRITE(LCPLL_CTL, val); | |
6629 | POSTING_READ(LCPLL_CTL); | |
6630 | } | |
6631 | } | |
6632 | ||
6633 | /* | |
6634 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
6635 | * source. | |
6636 | */ | |
6ff58d53 | 6637 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
6638 | { |
6639 | uint32_t val; | |
6640 | ||
6641 | val = I915_READ(LCPLL_CTL); | |
6642 | ||
6643 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
6644 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
6645 | return; | |
6646 | ||
215733fa PZ |
6647 | /* Make sure we're not on PC8 state before disabling PC8, otherwise |
6648 | * we'll hang the machine! */ | |
0d9d349d | 6649 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 6650 | |
be256dc7 PZ |
6651 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
6652 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
6653 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 6654 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
6655 | } |
6656 | ||
6657 | val = I915_READ(D_COMP); | |
6658 | val |= D_COMP_COMP_FORCE; | |
6659 | val &= ~D_COMP_COMP_DISABLE; | |
515b2392 PZ |
6660 | mutex_lock(&dev_priv->rps.hw_lock); |
6661 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val)) | |
6662 | DRM_ERROR("Failed to enable D_COMP\n"); | |
6663 | mutex_unlock(&dev_priv->rps.hw_lock); | |
35d8f2eb | 6664 | POSTING_READ(D_COMP); |
be256dc7 PZ |
6665 | |
6666 | val = I915_READ(LCPLL_CTL); | |
6667 | val &= ~LCPLL_PLL_DISABLE; | |
6668 | I915_WRITE(LCPLL_CTL, val); | |
6669 | ||
6670 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
6671 | DRM_ERROR("LCPLL not locked yet\n"); | |
6672 | ||
6673 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
6674 | val = I915_READ(LCPLL_CTL); | |
6675 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
6676 | I915_WRITE(LCPLL_CTL, val); | |
6677 | ||
6678 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
6679 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
6680 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
6681 | } | |
215733fa | 6682 | |
0d9d349d | 6683 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
be256dc7 PZ |
6684 | } |
6685 | ||
c67a470b PZ |
6686 | void hsw_enable_pc8_work(struct work_struct *__work) |
6687 | { | |
6688 | struct drm_i915_private *dev_priv = | |
6689 | container_of(to_delayed_work(__work), struct drm_i915_private, | |
6690 | pc8.enable_work); | |
6691 | struct drm_device *dev = dev_priv->dev; | |
6692 | uint32_t val; | |
6693 | ||
7125ecb8 PZ |
6694 | WARN_ON(!HAS_PC8(dev)); |
6695 | ||
c67a470b PZ |
6696 | if (dev_priv->pc8.enabled) |
6697 | return; | |
6698 | ||
6699 | DRM_DEBUG_KMS("Enabling package C8+\n"); | |
6700 | ||
6701 | dev_priv->pc8.enabled = true; | |
6702 | ||
6703 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
6704 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
6705 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
6706 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
6707 | } | |
6708 | ||
6709 | lpt_disable_clkout_dp(dev); | |
6710 | hsw_pc8_disable_interrupts(dev); | |
6711 | hsw_disable_lcpll(dev_priv, true, true); | |
8771a7f8 PZ |
6712 | |
6713 | intel_runtime_pm_put(dev_priv); | |
c67a470b PZ |
6714 | } |
6715 | ||
6716 | static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv) | |
6717 | { | |
6718 | WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock)); | |
6719 | WARN(dev_priv->pc8.disable_count < 1, | |
6720 | "pc8.disable_count: %d\n", dev_priv->pc8.disable_count); | |
6721 | ||
6722 | dev_priv->pc8.disable_count--; | |
6723 | if (dev_priv->pc8.disable_count != 0) | |
6724 | return; | |
6725 | ||
6726 | schedule_delayed_work(&dev_priv->pc8.enable_work, | |
d330a953 | 6727 | msecs_to_jiffies(i915.pc8_timeout)); |
c67a470b PZ |
6728 | } |
6729 | ||
6730 | static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv) | |
6731 | { | |
6732 | struct drm_device *dev = dev_priv->dev; | |
6733 | uint32_t val; | |
6734 | ||
6735 | WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock)); | |
6736 | WARN(dev_priv->pc8.disable_count < 0, | |
6737 | "pc8.disable_count: %d\n", dev_priv->pc8.disable_count); | |
6738 | ||
6739 | dev_priv->pc8.disable_count++; | |
6740 | if (dev_priv->pc8.disable_count != 1) | |
6741 | return; | |
6742 | ||
7125ecb8 PZ |
6743 | WARN_ON(!HAS_PC8(dev)); |
6744 | ||
c67a470b PZ |
6745 | cancel_delayed_work_sync(&dev_priv->pc8.enable_work); |
6746 | if (!dev_priv->pc8.enabled) | |
6747 | return; | |
6748 | ||
6749 | DRM_DEBUG_KMS("Disabling package C8+\n"); | |
6750 | ||
8771a7f8 PZ |
6751 | intel_runtime_pm_get(dev_priv); |
6752 | ||
c67a470b PZ |
6753 | hsw_restore_lcpll(dev_priv); |
6754 | hsw_pc8_restore_interrupts(dev); | |
6755 | lpt_init_pch_refclk(dev); | |
6756 | ||
6757 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
6758 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
6759 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
6760 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
6761 | } | |
6762 | ||
6763 | intel_prepare_ddi(dev); | |
6764 | i915_gem_init_swizzling(dev); | |
6765 | mutex_lock(&dev_priv->rps.hw_lock); | |
6766 | gen6_update_ring_freq(dev); | |
6767 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6768 | dev_priv->pc8.enabled = false; | |
6769 | } | |
6770 | ||
6771 | void hsw_enable_package_c8(struct drm_i915_private *dev_priv) | |
6772 | { | |
7c6c2652 CW |
6773 | if (!HAS_PC8(dev_priv->dev)) |
6774 | return; | |
6775 | ||
c67a470b PZ |
6776 | mutex_lock(&dev_priv->pc8.lock); |
6777 | __hsw_enable_package_c8(dev_priv); | |
6778 | mutex_unlock(&dev_priv->pc8.lock); | |
6779 | } | |
6780 | ||
6781 | void hsw_disable_package_c8(struct drm_i915_private *dev_priv) | |
6782 | { | |
7c6c2652 CW |
6783 | if (!HAS_PC8(dev_priv->dev)) |
6784 | return; | |
6785 | ||
c67a470b PZ |
6786 | mutex_lock(&dev_priv->pc8.lock); |
6787 | __hsw_disable_package_c8(dev_priv); | |
6788 | mutex_unlock(&dev_priv->pc8.lock); | |
6789 | } | |
6790 | ||
6791 | static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv) | |
6792 | { | |
6793 | struct drm_device *dev = dev_priv->dev; | |
6794 | struct intel_crtc *crtc; | |
6795 | uint32_t val; | |
6796 | ||
6797 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) | |
6798 | if (crtc->base.enabled) | |
6799 | return false; | |
6800 | ||
6801 | /* This case is still possible since we have the i915.disable_power_well | |
6802 | * parameter and also the KVMr or something else might be requesting the | |
6803 | * power well. */ | |
6804 | val = I915_READ(HSW_PWR_WELL_DRIVER); | |
6805 | if (val != 0) { | |
6806 | DRM_DEBUG_KMS("Not enabling PC8: power well on\n"); | |
6807 | return false; | |
6808 | } | |
6809 | ||
6810 | return true; | |
6811 | } | |
6812 | ||
6813 | /* Since we're called from modeset_global_resources there's no way to | |
6814 | * symmetrically increase and decrease the refcount, so we use | |
6815 | * dev_priv->pc8.requirements_met to track whether we already have the refcount | |
6816 | * or not. | |
6817 | */ | |
6818 | static void hsw_update_package_c8(struct drm_device *dev) | |
6819 | { | |
6820 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6821 | bool allow; | |
6822 | ||
7c6c2652 CW |
6823 | if (!HAS_PC8(dev_priv->dev)) |
6824 | return; | |
6825 | ||
d330a953 | 6826 | if (!i915.enable_pc8) |
c67a470b PZ |
6827 | return; |
6828 | ||
6829 | mutex_lock(&dev_priv->pc8.lock); | |
6830 | ||
6831 | allow = hsw_can_enable_package_c8(dev_priv); | |
6832 | ||
6833 | if (allow == dev_priv->pc8.requirements_met) | |
6834 | goto done; | |
6835 | ||
6836 | dev_priv->pc8.requirements_met = allow; | |
6837 | ||
6838 | if (allow) | |
6839 | __hsw_enable_package_c8(dev_priv); | |
6840 | else | |
6841 | __hsw_disable_package_c8(dev_priv); | |
6842 | ||
6843 | done: | |
6844 | mutex_unlock(&dev_priv->pc8.lock); | |
6845 | } | |
6846 | ||
6847 | static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv) | |
6848 | { | |
7c6c2652 CW |
6849 | if (!HAS_PC8(dev_priv->dev)) |
6850 | return; | |
6851 | ||
3458122e | 6852 | mutex_lock(&dev_priv->pc8.lock); |
c67a470b PZ |
6853 | if (!dev_priv->pc8.gpu_idle) { |
6854 | dev_priv->pc8.gpu_idle = true; | |
3458122e | 6855 | __hsw_enable_package_c8(dev_priv); |
c67a470b | 6856 | } |
3458122e | 6857 | mutex_unlock(&dev_priv->pc8.lock); |
c67a470b PZ |
6858 | } |
6859 | ||
6860 | static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv) | |
6861 | { | |
7c6c2652 CW |
6862 | if (!HAS_PC8(dev_priv->dev)) |
6863 | return; | |
6864 | ||
3458122e | 6865 | mutex_lock(&dev_priv->pc8.lock); |
c67a470b PZ |
6866 | if (dev_priv->pc8.gpu_idle) { |
6867 | dev_priv->pc8.gpu_idle = false; | |
3458122e | 6868 | __hsw_disable_package_c8(dev_priv); |
c67a470b | 6869 | } |
3458122e | 6870 | mutex_unlock(&dev_priv->pc8.lock); |
be256dc7 PZ |
6871 | } |
6872 | ||
6efdf354 ID |
6873 | #define for_each_power_domain(domain, mask) \ |
6874 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
6875 | if ((1 << (domain)) & (mask)) | |
6876 | ||
6877 | static unsigned long get_pipe_power_domains(struct drm_device *dev, | |
6878 | enum pipe pipe, bool pfit_enabled) | |
6879 | { | |
6880 | unsigned long mask; | |
6881 | enum transcoder transcoder; | |
6882 | ||
6883 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); | |
6884 | ||
6885 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); | |
6886 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
6887 | if (pfit_enabled) | |
6888 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); | |
6889 | ||
6890 | return mask; | |
6891 | } | |
6892 | ||
baa70707 ID |
6893 | void intel_display_set_init_power(struct drm_device *dev, bool enable) |
6894 | { | |
6895 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6896 | ||
6897 | if (dev_priv->power_domains.init_power_on == enable) | |
6898 | return; | |
6899 | ||
6900 | if (enable) | |
6901 | intel_display_power_get(dev, POWER_DOMAIN_INIT); | |
6902 | else | |
6903 | intel_display_power_put(dev, POWER_DOMAIN_INIT); | |
6904 | ||
6905 | dev_priv->power_domains.init_power_on = enable; | |
6906 | } | |
6907 | ||
4f074129 | 6908 | static void modeset_update_power_wells(struct drm_device *dev) |
d6dd9eb1 | 6909 | { |
6efdf354 | 6910 | unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; |
d6dd9eb1 | 6911 | struct intel_crtc *crtc; |
d6dd9eb1 | 6912 | |
6efdf354 ID |
6913 | /* |
6914 | * First get all needed power domains, then put all unneeded, to avoid | |
6915 | * any unnecessary toggling of the power wells. | |
6916 | */ | |
d6dd9eb1 | 6917 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
6efdf354 ID |
6918 | enum intel_display_power_domain domain; |
6919 | ||
e7a639c4 DV |
6920 | if (!crtc->base.enabled) |
6921 | continue; | |
d6dd9eb1 | 6922 | |
6efdf354 ID |
6923 | pipe_domains[crtc->pipe] = get_pipe_power_domains(dev, |
6924 | crtc->pipe, | |
6925 | crtc->config.pch_pfit.enabled); | |
6926 | ||
6927 | for_each_power_domain(domain, pipe_domains[crtc->pipe]) | |
6928 | intel_display_power_get(dev, domain); | |
d6dd9eb1 DV |
6929 | } |
6930 | ||
6efdf354 ID |
6931 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
6932 | enum intel_display_power_domain domain; | |
6933 | ||
6934 | for_each_power_domain(domain, crtc->enabled_power_domains) | |
6935 | intel_display_power_put(dev, domain); | |
6936 | ||
6937 | crtc->enabled_power_domains = pipe_domains[crtc->pipe]; | |
6938 | } | |
baa70707 ID |
6939 | |
6940 | intel_display_set_init_power(dev, false); | |
4f074129 | 6941 | } |
c67a470b | 6942 | |
4f074129 ID |
6943 | static void haswell_modeset_global_resources(struct drm_device *dev) |
6944 | { | |
6945 | modeset_update_power_wells(dev); | |
c67a470b | 6946 | hsw_update_package_c8(dev); |
d6dd9eb1 DV |
6947 | } |
6948 | ||
09b4ddf9 | 6949 | static int haswell_crtc_mode_set(struct drm_crtc *crtc, |
09b4ddf9 PZ |
6950 | int x, int y, |
6951 | struct drm_framebuffer *fb) | |
6952 | { | |
6953 | struct drm_device *dev = crtc->dev; | |
6954 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6955 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
09b4ddf9 | 6956 | int plane = intel_crtc->plane; |
09b4ddf9 | 6957 | int ret; |
09b4ddf9 | 6958 | |
566b734a | 6959 | if (!intel_ddi_pll_select(intel_crtc)) |
6441ab5f | 6960 | return -EINVAL; |
566b734a | 6961 | intel_ddi_pll_enable(intel_crtc); |
6441ab5f | 6962 | |
03afc4a2 DV |
6963 | if (intel_crtc->config.has_dp_encoder) |
6964 | intel_dp_set_m_n(intel_crtc); | |
09b4ddf9 PZ |
6965 | |
6966 | intel_crtc->lowfreq_avail = false; | |
09b4ddf9 | 6967 | |
8a654f3b | 6968 | intel_set_pipe_timings(intel_crtc); |
09b4ddf9 | 6969 | |
ca3a0ff8 | 6970 | if (intel_crtc->config.has_pch_encoder) { |
ca3a0ff8 DV |
6971 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6972 | &intel_crtc->config.fdi_m_n); | |
6973 | } | |
09b4ddf9 | 6974 | |
6ff93609 | 6975 | haswell_set_pipeconf(crtc); |
09b4ddf9 | 6976 | |
50f3b016 | 6977 | intel_set_pipe_csc(crtc); |
86d3efce | 6978 | |
09b4ddf9 | 6979 | /* Set up the display plane register */ |
86d3efce | 6980 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE); |
09b4ddf9 PZ |
6981 | POSTING_READ(DSPCNTR(plane)); |
6982 | ||
6983 | ret = intel_pipe_set_base(crtc, x, y, fb); | |
6984 | ||
1f803ee5 | 6985 | return ret; |
79e53945 JB |
6986 | } |
6987 | ||
0e8ffe1b DV |
6988 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
6989 | struct intel_crtc_config *pipe_config) | |
6990 | { | |
6991 | struct drm_device *dev = crtc->base.dev; | |
6992 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 6993 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
6994 | uint32_t tmp; |
6995 | ||
e143a21c | 6996 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
6997 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
6998 | ||
eccb140b DV |
6999 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
7000 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
7001 | enum pipe trans_edp_pipe; | |
7002 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
7003 | default: | |
7004 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
7005 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
7006 | case TRANS_DDI_EDP_INPUT_A_ON: | |
7007 | trans_edp_pipe = PIPE_A; | |
7008 | break; | |
7009 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
7010 | trans_edp_pipe = PIPE_B; | |
7011 | break; | |
7012 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
7013 | trans_edp_pipe = PIPE_C; | |
7014 | break; | |
7015 | } | |
7016 | ||
7017 | if (trans_edp_pipe == crtc->pipe) | |
7018 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
7019 | } | |
7020 | ||
b97186f0 | 7021 | if (!intel_display_power_enabled(dev, |
eccb140b | 7022 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
7023 | return false; |
7024 | ||
eccb140b | 7025 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
7026 | if (!(tmp & PIPECONF_ENABLE)) |
7027 | return false; | |
7028 | ||
88adfff1 | 7029 | /* |
f196e6be | 7030 | * Haswell has only FDI/PCH transcoder A. It is which is connected to |
88adfff1 DV |
7031 | * DDI E. So just check whether this pipe is wired to DDI E and whether |
7032 | * the PCH transcoder is on. | |
7033 | */ | |
eccb140b | 7034 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); |
88adfff1 | 7035 | if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) && |
ab9412ba | 7036 | I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { |
88adfff1 DV |
7037 | pipe_config->has_pch_encoder = true; |
7038 | ||
627eb5a3 DV |
7039 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); |
7040 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
7041 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
7042 | |
7043 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
627eb5a3 DV |
7044 | } |
7045 | ||
1bd1bd80 DV |
7046 | intel_get_pipe_timings(crtc, pipe_config); |
7047 | ||
2fa2fe9a DV |
7048 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
7049 | if (intel_display_power_enabled(dev, pfit_domain)) | |
7050 | ironlake_get_pfit_config(crtc, pipe_config); | |
88adfff1 | 7051 | |
e59150dc JB |
7052 | if (IS_HASWELL(dev)) |
7053 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
7054 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 7055 | |
6c49f241 DV |
7056 | pipe_config->pixel_multiplier = 1; |
7057 | ||
0e8ffe1b DV |
7058 | return true; |
7059 | } | |
7060 | ||
f564048e | 7061 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
f564048e | 7062 | int x, int y, |
94352cf9 | 7063 | struct drm_framebuffer *fb) |
f564048e EA |
7064 | { |
7065 | struct drm_device *dev = crtc->dev; | |
7066 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9256aa19 | 7067 | struct intel_encoder *encoder; |
0b701d27 | 7068 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
b8cecdf5 | 7069 | struct drm_display_mode *mode = &intel_crtc->config.requested_mode; |
0b701d27 | 7070 | int pipe = intel_crtc->pipe; |
f564048e EA |
7071 | int ret; |
7072 | ||
0b701d27 | 7073 | drm_vblank_pre_modeset(dev, pipe); |
7662c8bd | 7074 | |
b8cecdf5 DV |
7075 | ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb); |
7076 | ||
79e53945 | 7077 | drm_vblank_post_modeset(dev, pipe); |
5c3b82e2 | 7078 | |
9256aa19 DV |
7079 | if (ret != 0) |
7080 | return ret; | |
7081 | ||
7082 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
7083 | DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n", | |
7084 | encoder->base.base.id, | |
7085 | drm_get_encoder_name(&encoder->base), | |
7086 | mode->base.id, mode->name); | |
36f2d1f1 | 7087 | encoder->mode_set(encoder); |
9256aa19 DV |
7088 | } |
7089 | ||
7090 | return 0; | |
79e53945 JB |
7091 | } |
7092 | ||
1a91510d JN |
7093 | static struct { |
7094 | int clock; | |
7095 | u32 config; | |
7096 | } hdmi_audio_clock[] = { | |
7097 | { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, | |
7098 | { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ | |
7099 | { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, | |
7100 | { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, | |
7101 | { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, | |
7102 | { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, | |
7103 | { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, | |
7104 | { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, | |
7105 | { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, | |
7106 | { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, | |
7107 | }; | |
7108 | ||
7109 | /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ | |
7110 | static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode) | |
7111 | { | |
7112 | int i; | |
7113 | ||
7114 | for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { | |
7115 | if (mode->clock == hdmi_audio_clock[i].clock) | |
7116 | break; | |
7117 | } | |
7118 | ||
7119 | if (i == ARRAY_SIZE(hdmi_audio_clock)) { | |
7120 | DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock); | |
7121 | i = 1; | |
7122 | } | |
7123 | ||
7124 | DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n", | |
7125 | hdmi_audio_clock[i].clock, | |
7126 | hdmi_audio_clock[i].config); | |
7127 | ||
7128 | return hdmi_audio_clock[i].config; | |
7129 | } | |
7130 | ||
3a9627f4 WF |
7131 | static bool intel_eld_uptodate(struct drm_connector *connector, |
7132 | int reg_eldv, uint32_t bits_eldv, | |
7133 | int reg_elda, uint32_t bits_elda, | |
7134 | int reg_edid) | |
7135 | { | |
7136 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7137 | uint8_t *eld = connector->eld; | |
7138 | uint32_t i; | |
7139 | ||
7140 | i = I915_READ(reg_eldv); | |
7141 | i &= bits_eldv; | |
7142 | ||
7143 | if (!eld[0]) | |
7144 | return !i; | |
7145 | ||
7146 | if (!i) | |
7147 | return false; | |
7148 | ||
7149 | i = I915_READ(reg_elda); | |
7150 | i &= ~bits_elda; | |
7151 | I915_WRITE(reg_elda, i); | |
7152 | ||
7153 | for (i = 0; i < eld[2]; i++) | |
7154 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) | |
7155 | return false; | |
7156 | ||
7157 | return true; | |
7158 | } | |
7159 | ||
e0dac65e | 7160 | static void g4x_write_eld(struct drm_connector *connector, |
34427052 JN |
7161 | struct drm_crtc *crtc, |
7162 | struct drm_display_mode *mode) | |
e0dac65e WF |
7163 | { |
7164 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7165 | uint8_t *eld = connector->eld; | |
7166 | uint32_t eldv; | |
7167 | uint32_t len; | |
7168 | uint32_t i; | |
7169 | ||
7170 | i = I915_READ(G4X_AUD_VID_DID); | |
7171 | ||
7172 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) | |
7173 | eldv = G4X_ELDV_DEVCL_DEVBLC; | |
7174 | else | |
7175 | eldv = G4X_ELDV_DEVCTG; | |
7176 | ||
3a9627f4 WF |
7177 | if (intel_eld_uptodate(connector, |
7178 | G4X_AUD_CNTL_ST, eldv, | |
7179 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, | |
7180 | G4X_HDMIW_HDMIEDID)) | |
7181 | return; | |
7182 | ||
e0dac65e WF |
7183 | i = I915_READ(G4X_AUD_CNTL_ST); |
7184 | i &= ~(eldv | G4X_ELD_ADDR); | |
7185 | len = (i >> 9) & 0x1f; /* ELD buffer size */ | |
7186 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
7187 | ||
7188 | if (!eld[0]) | |
7189 | return; | |
7190 | ||
7191 | len = min_t(uint8_t, eld[2], len); | |
7192 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7193 | for (i = 0; i < len; i++) | |
7194 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); | |
7195 | ||
7196 | i = I915_READ(G4X_AUD_CNTL_ST); | |
7197 | i |= eldv; | |
7198 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
7199 | } | |
7200 | ||
83358c85 | 7201 | static void haswell_write_eld(struct drm_connector *connector, |
34427052 JN |
7202 | struct drm_crtc *crtc, |
7203 | struct drm_display_mode *mode) | |
83358c85 WX |
7204 | { |
7205 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7206 | uint8_t *eld = connector->eld; | |
7207 | struct drm_device *dev = crtc->dev; | |
7b9f35a6 | 7208 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
83358c85 WX |
7209 | uint32_t eldv; |
7210 | uint32_t i; | |
7211 | int len; | |
7212 | int pipe = to_intel_crtc(crtc)->pipe; | |
7213 | int tmp; | |
7214 | ||
7215 | int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe); | |
7216 | int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe); | |
7217 | int aud_config = HSW_AUD_CFG(pipe); | |
7218 | int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD; | |
7219 | ||
7220 | ||
7221 | DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n"); | |
7222 | ||
7223 | /* Audio output enable */ | |
7224 | DRM_DEBUG_DRIVER("HDMI audio: enable codec\n"); | |
7225 | tmp = I915_READ(aud_cntrl_st2); | |
7226 | tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4)); | |
7227 | I915_WRITE(aud_cntrl_st2, tmp); | |
7228 | ||
7229 | /* Wait for 1 vertical blank */ | |
7230 | intel_wait_for_vblank(dev, pipe); | |
7231 | ||
7232 | /* Set ELD valid state */ | |
7233 | tmp = I915_READ(aud_cntrl_st2); | |
7e7cb34f | 7234 | DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp); |
83358c85 WX |
7235 | tmp |= (AUDIO_ELD_VALID_A << (pipe * 4)); |
7236 | I915_WRITE(aud_cntrl_st2, tmp); | |
7237 | tmp = I915_READ(aud_cntrl_st2); | |
7e7cb34f | 7238 | DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp); |
83358c85 WX |
7239 | |
7240 | /* Enable HDMI mode */ | |
7241 | tmp = I915_READ(aud_config); | |
7e7cb34f | 7242 | DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp); |
83358c85 WX |
7243 | /* clear N_programing_enable and N_value_index */ |
7244 | tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE); | |
7245 | I915_WRITE(aud_config, tmp); | |
7246 | ||
7247 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); | |
7248 | ||
7249 | eldv = AUDIO_ELD_VALID_A << (pipe * 4); | |
7b9f35a6 | 7250 | intel_crtc->eld_vld = true; |
83358c85 WX |
7251 | |
7252 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { | |
7253 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
7254 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
7255 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ | |
1a91510d JN |
7256 | } else { |
7257 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); | |
7258 | } | |
83358c85 WX |
7259 | |
7260 | if (intel_eld_uptodate(connector, | |
7261 | aud_cntrl_st2, eldv, | |
7262 | aud_cntl_st, IBX_ELD_ADDRESS, | |
7263 | hdmiw_hdmiedid)) | |
7264 | return; | |
7265 | ||
7266 | i = I915_READ(aud_cntrl_st2); | |
7267 | i &= ~eldv; | |
7268 | I915_WRITE(aud_cntrl_st2, i); | |
7269 | ||
7270 | if (!eld[0]) | |
7271 | return; | |
7272 | ||
7273 | i = I915_READ(aud_cntl_st); | |
7274 | i &= ~IBX_ELD_ADDRESS; | |
7275 | I915_WRITE(aud_cntl_st, i); | |
7276 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ | |
7277 | DRM_DEBUG_DRIVER("port num:%d\n", i); | |
7278 | ||
7279 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
7280 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7281 | for (i = 0; i < len; i++) | |
7282 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
7283 | ||
7284 | i = I915_READ(aud_cntrl_st2); | |
7285 | i |= eldv; | |
7286 | I915_WRITE(aud_cntrl_st2, i); | |
7287 | ||
7288 | } | |
7289 | ||
e0dac65e | 7290 | static void ironlake_write_eld(struct drm_connector *connector, |
34427052 JN |
7291 | struct drm_crtc *crtc, |
7292 | struct drm_display_mode *mode) | |
e0dac65e WF |
7293 | { |
7294 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7295 | uint8_t *eld = connector->eld; | |
7296 | uint32_t eldv; | |
7297 | uint32_t i; | |
7298 | int len; | |
7299 | int hdmiw_hdmiedid; | |
b6daa025 | 7300 | int aud_config; |
e0dac65e WF |
7301 | int aud_cntl_st; |
7302 | int aud_cntrl_st2; | |
9b138a83 | 7303 | int pipe = to_intel_crtc(crtc)->pipe; |
e0dac65e | 7304 | |
b3f33cbf | 7305 | if (HAS_PCH_IBX(connector->dev)) { |
9b138a83 WX |
7306 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); |
7307 | aud_config = IBX_AUD_CFG(pipe); | |
7308 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); | |
1202b4c6 | 7309 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
9ca2fe73 ML |
7310 | } else if (IS_VALLEYVIEW(connector->dev)) { |
7311 | hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); | |
7312 | aud_config = VLV_AUD_CFG(pipe); | |
7313 | aud_cntl_st = VLV_AUD_CNTL_ST(pipe); | |
7314 | aud_cntrl_st2 = VLV_AUD_CNTL_ST2; | |
e0dac65e | 7315 | } else { |
9b138a83 WX |
7316 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); |
7317 | aud_config = CPT_AUD_CFG(pipe); | |
7318 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); | |
1202b4c6 | 7319 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
e0dac65e WF |
7320 | } |
7321 | ||
9b138a83 | 7322 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
e0dac65e | 7323 | |
9ca2fe73 ML |
7324 | if (IS_VALLEYVIEW(connector->dev)) { |
7325 | struct intel_encoder *intel_encoder; | |
7326 | struct intel_digital_port *intel_dig_port; | |
7327 | ||
7328 | intel_encoder = intel_attached_encoder(connector); | |
7329 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
7330 | i = intel_dig_port->port; | |
7331 | } else { | |
7332 | i = I915_READ(aud_cntl_st); | |
7333 | i = (i >> 29) & DIP_PORT_SEL_MASK; | |
7334 | /* DIP_Port_Select, 0x1 = PortB */ | |
7335 | } | |
7336 | ||
e0dac65e WF |
7337 | if (!i) { |
7338 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); | |
7339 | /* operate blindly on all ports */ | |
1202b4c6 WF |
7340 | eldv = IBX_ELD_VALIDB; |
7341 | eldv |= IBX_ELD_VALIDB << 4; | |
7342 | eldv |= IBX_ELD_VALIDB << 8; | |
e0dac65e | 7343 | } else { |
2582a850 | 7344 | DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i)); |
1202b4c6 | 7345 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
e0dac65e WF |
7346 | } |
7347 | ||
3a9627f4 WF |
7348 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
7349 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
7350 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
b6daa025 | 7351 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
1a91510d JN |
7352 | } else { |
7353 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); | |
7354 | } | |
e0dac65e | 7355 | |
3a9627f4 WF |
7356 | if (intel_eld_uptodate(connector, |
7357 | aud_cntrl_st2, eldv, | |
7358 | aud_cntl_st, IBX_ELD_ADDRESS, | |
7359 | hdmiw_hdmiedid)) | |
7360 | return; | |
7361 | ||
e0dac65e WF |
7362 | i = I915_READ(aud_cntrl_st2); |
7363 | i &= ~eldv; | |
7364 | I915_WRITE(aud_cntrl_st2, i); | |
7365 | ||
7366 | if (!eld[0]) | |
7367 | return; | |
7368 | ||
e0dac65e | 7369 | i = I915_READ(aud_cntl_st); |
1202b4c6 | 7370 | i &= ~IBX_ELD_ADDRESS; |
e0dac65e WF |
7371 | I915_WRITE(aud_cntl_st, i); |
7372 | ||
7373 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
7374 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7375 | for (i = 0; i < len; i++) | |
7376 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
7377 | ||
7378 | i = I915_READ(aud_cntrl_st2); | |
7379 | i |= eldv; | |
7380 | I915_WRITE(aud_cntrl_st2, i); | |
7381 | } | |
7382 | ||
7383 | void intel_write_eld(struct drm_encoder *encoder, | |
7384 | struct drm_display_mode *mode) | |
7385 | { | |
7386 | struct drm_crtc *crtc = encoder->crtc; | |
7387 | struct drm_connector *connector; | |
7388 | struct drm_device *dev = encoder->dev; | |
7389 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7390 | ||
7391 | connector = drm_select_eld(encoder, mode); | |
7392 | if (!connector) | |
7393 | return; | |
7394 | ||
7395 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", | |
7396 | connector->base.id, | |
7397 | drm_get_connector_name(connector), | |
7398 | connector->encoder->base.id, | |
7399 | drm_get_encoder_name(connector->encoder)); | |
7400 | ||
7401 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; | |
7402 | ||
7403 | if (dev_priv->display.write_eld) | |
34427052 | 7404 | dev_priv->display.write_eld(connector, crtc, mode); |
e0dac65e WF |
7405 | } |
7406 | ||
560b85bb CW |
7407 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
7408 | { | |
7409 | struct drm_device *dev = crtc->dev; | |
7410 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7411 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7412 | bool visible = base != 0; | |
7413 | u32 cntl; | |
7414 | ||
7415 | if (intel_crtc->cursor_visible == visible) | |
7416 | return; | |
7417 | ||
9db4a9c7 | 7418 | cntl = I915_READ(_CURACNTR); |
560b85bb CW |
7419 | if (visible) { |
7420 | /* On these chipsets we can only modify the base whilst | |
7421 | * the cursor is disabled. | |
7422 | */ | |
9db4a9c7 | 7423 | I915_WRITE(_CURABASE, base); |
560b85bb CW |
7424 | |
7425 | cntl &= ~(CURSOR_FORMAT_MASK); | |
7426 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ | |
7427 | cntl |= CURSOR_ENABLE | | |
7428 | CURSOR_GAMMA_ENABLE | | |
7429 | CURSOR_FORMAT_ARGB; | |
7430 | } else | |
7431 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); | |
9db4a9c7 | 7432 | I915_WRITE(_CURACNTR, cntl); |
560b85bb CW |
7433 | |
7434 | intel_crtc->cursor_visible = visible; | |
7435 | } | |
7436 | ||
7437 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) | |
7438 | { | |
7439 | struct drm_device *dev = crtc->dev; | |
7440 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7441 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7442 | int pipe = intel_crtc->pipe; | |
7443 | bool visible = base != 0; | |
7444 | ||
7445 | if (intel_crtc->cursor_visible != visible) { | |
548f245b | 7446 | uint32_t cntl = I915_READ(CURCNTR(pipe)); |
560b85bb CW |
7447 | if (base) { |
7448 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); | |
7449 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
7450 | cntl |= pipe << 28; /* Connect to correct pipe */ | |
7451 | } else { | |
7452 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
7453 | cntl |= CURSOR_MODE_DISABLE; | |
7454 | } | |
9db4a9c7 | 7455 | I915_WRITE(CURCNTR(pipe), cntl); |
560b85bb CW |
7456 | |
7457 | intel_crtc->cursor_visible = visible; | |
7458 | } | |
7459 | /* and commit changes on next vblank */ | |
b2ea8ef5 | 7460 | POSTING_READ(CURCNTR(pipe)); |
9db4a9c7 | 7461 | I915_WRITE(CURBASE(pipe), base); |
b2ea8ef5 | 7462 | POSTING_READ(CURBASE(pipe)); |
560b85bb CW |
7463 | } |
7464 | ||
65a21cd6 JB |
7465 | static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) |
7466 | { | |
7467 | struct drm_device *dev = crtc->dev; | |
7468 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7469 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7470 | int pipe = intel_crtc->pipe; | |
7471 | bool visible = base != 0; | |
7472 | ||
7473 | if (intel_crtc->cursor_visible != visible) { | |
7474 | uint32_t cntl = I915_READ(CURCNTR_IVB(pipe)); | |
7475 | if (base) { | |
7476 | cntl &= ~CURSOR_MODE; | |
7477 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
7478 | } else { | |
7479 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
7480 | cntl |= CURSOR_MODE_DISABLE; | |
7481 | } | |
6bbfa1c5 | 7482 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
86d3efce | 7483 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
1f5d76db PZ |
7484 | cntl &= ~CURSOR_TRICKLE_FEED_DISABLE; |
7485 | } | |
65a21cd6 JB |
7486 | I915_WRITE(CURCNTR_IVB(pipe), cntl); |
7487 | ||
7488 | intel_crtc->cursor_visible = visible; | |
7489 | } | |
7490 | /* and commit changes on next vblank */ | |
b2ea8ef5 | 7491 | POSTING_READ(CURCNTR_IVB(pipe)); |
65a21cd6 | 7492 | I915_WRITE(CURBASE_IVB(pipe), base); |
b2ea8ef5 | 7493 | POSTING_READ(CURBASE_IVB(pipe)); |
65a21cd6 JB |
7494 | } |
7495 | ||
cda4b7d3 | 7496 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
7497 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
7498 | bool on) | |
cda4b7d3 CW |
7499 | { |
7500 | struct drm_device *dev = crtc->dev; | |
7501 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7502 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7503 | int pipe = intel_crtc->pipe; | |
7504 | int x = intel_crtc->cursor_x; | |
7505 | int y = intel_crtc->cursor_y; | |
d6e4db15 | 7506 | u32 base = 0, pos = 0; |
cda4b7d3 CW |
7507 | bool visible; |
7508 | ||
d6e4db15 | 7509 | if (on) |
cda4b7d3 | 7510 | base = intel_crtc->cursor_addr; |
cda4b7d3 | 7511 | |
d6e4db15 VS |
7512 | if (x >= intel_crtc->config.pipe_src_w) |
7513 | base = 0; | |
7514 | ||
7515 | if (y >= intel_crtc->config.pipe_src_h) | |
cda4b7d3 CW |
7516 | base = 0; |
7517 | ||
7518 | if (x < 0) { | |
efc9064e | 7519 | if (x + intel_crtc->cursor_width <= 0) |
cda4b7d3 CW |
7520 | base = 0; |
7521 | ||
7522 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
7523 | x = -x; | |
7524 | } | |
7525 | pos |= x << CURSOR_X_SHIFT; | |
7526 | ||
7527 | if (y < 0) { | |
efc9064e | 7528 | if (y + intel_crtc->cursor_height <= 0) |
cda4b7d3 CW |
7529 | base = 0; |
7530 | ||
7531 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
7532 | y = -y; | |
7533 | } | |
7534 | pos |= y << CURSOR_Y_SHIFT; | |
7535 | ||
7536 | visible = base != 0; | |
560b85bb | 7537 | if (!visible && !intel_crtc->cursor_visible) |
cda4b7d3 CW |
7538 | return; |
7539 | ||
b3dc685e | 7540 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
65a21cd6 JB |
7541 | I915_WRITE(CURPOS_IVB(pipe), pos); |
7542 | ivb_update_cursor(crtc, base); | |
7543 | } else { | |
7544 | I915_WRITE(CURPOS(pipe), pos); | |
7545 | if (IS_845G(dev) || IS_I865G(dev)) | |
7546 | i845_update_cursor(crtc, base); | |
7547 | else | |
7548 | i9xx_update_cursor(crtc, base); | |
7549 | } | |
cda4b7d3 CW |
7550 | } |
7551 | ||
79e53945 | 7552 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
05394f39 | 7553 | struct drm_file *file, |
79e53945 JB |
7554 | uint32_t handle, |
7555 | uint32_t width, uint32_t height) | |
7556 | { | |
7557 | struct drm_device *dev = crtc->dev; | |
7558 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7559 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 7560 | struct drm_i915_gem_object *obj; |
cda4b7d3 | 7561 | uint32_t addr; |
3f8bc370 | 7562 | int ret; |
79e53945 | 7563 | |
79e53945 JB |
7564 | /* if we want to turn off the cursor ignore width and height */ |
7565 | if (!handle) { | |
28c97730 | 7566 | DRM_DEBUG_KMS("cursor off\n"); |
3f8bc370 | 7567 | addr = 0; |
05394f39 | 7568 | obj = NULL; |
5004417d | 7569 | mutex_lock(&dev->struct_mutex); |
3f8bc370 | 7570 | goto finish; |
79e53945 JB |
7571 | } |
7572 | ||
7573 | /* Currently we only support 64x64 cursors */ | |
7574 | if (width != 64 || height != 64) { | |
7575 | DRM_ERROR("we currently only support 64x64 cursors\n"); | |
7576 | return -EINVAL; | |
7577 | } | |
7578 | ||
05394f39 | 7579 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 7580 | if (&obj->base == NULL) |
79e53945 JB |
7581 | return -ENOENT; |
7582 | ||
05394f39 | 7583 | if (obj->base.size < width * height * 4) { |
79e53945 | 7584 | DRM_ERROR("buffer is to small\n"); |
34b8686e DA |
7585 | ret = -ENOMEM; |
7586 | goto fail; | |
79e53945 JB |
7587 | } |
7588 | ||
71acb5eb | 7589 | /* we only need to pin inside GTT if cursor is non-phy */ |
7f9872e0 | 7590 | mutex_lock(&dev->struct_mutex); |
3d13ef2e | 7591 | if (!INTEL_INFO(dev)->cursor_needs_physical) { |
693db184 CW |
7592 | unsigned alignment; |
7593 | ||
d9e86c0e CW |
7594 | if (obj->tiling_mode) { |
7595 | DRM_ERROR("cursor cannot be tiled\n"); | |
7596 | ret = -EINVAL; | |
7597 | goto fail_locked; | |
7598 | } | |
7599 | ||
693db184 CW |
7600 | /* Note that the w/a also requires 2 PTE of padding following |
7601 | * the bo. We currently fill all unused PTE with the shadow | |
7602 | * page and so we should always have valid PTE following the | |
7603 | * cursor preventing the VT-d warning. | |
7604 | */ | |
7605 | alignment = 0; | |
7606 | if (need_vtd_wa(dev)) | |
7607 | alignment = 64*1024; | |
7608 | ||
7609 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL); | |
e7b526bb CW |
7610 | if (ret) { |
7611 | DRM_ERROR("failed to move cursor bo into the GTT\n"); | |
2da3b9b9 | 7612 | goto fail_locked; |
e7b526bb CW |
7613 | } |
7614 | ||
d9e86c0e CW |
7615 | ret = i915_gem_object_put_fence(obj); |
7616 | if (ret) { | |
2da3b9b9 | 7617 | DRM_ERROR("failed to release fence for cursor"); |
d9e86c0e CW |
7618 | goto fail_unpin; |
7619 | } | |
7620 | ||
f343c5f6 | 7621 | addr = i915_gem_obj_ggtt_offset(obj); |
71acb5eb | 7622 | } else { |
6eeefaf3 | 7623 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
05394f39 | 7624 | ret = i915_gem_attach_phys_object(dev, obj, |
6eeefaf3 CW |
7625 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
7626 | align); | |
71acb5eb DA |
7627 | if (ret) { |
7628 | DRM_ERROR("failed to attach phys object\n"); | |
7f9872e0 | 7629 | goto fail_locked; |
71acb5eb | 7630 | } |
05394f39 | 7631 | addr = obj->phys_obj->handle->busaddr; |
3f8bc370 KH |
7632 | } |
7633 | ||
a6c45cf0 | 7634 | if (IS_GEN2(dev)) |
14b60391 JB |
7635 | I915_WRITE(CURSIZE, (height << 12) | width); |
7636 | ||
3f8bc370 | 7637 | finish: |
3f8bc370 | 7638 | if (intel_crtc->cursor_bo) { |
3d13ef2e | 7639 | if (INTEL_INFO(dev)->cursor_needs_physical) { |
05394f39 | 7640 | if (intel_crtc->cursor_bo != obj) |
71acb5eb DA |
7641 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); |
7642 | } else | |
cc98b413 | 7643 | i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo); |
05394f39 | 7644 | drm_gem_object_unreference(&intel_crtc->cursor_bo->base); |
3f8bc370 | 7645 | } |
80824003 | 7646 | |
7f9872e0 | 7647 | mutex_unlock(&dev->struct_mutex); |
3f8bc370 KH |
7648 | |
7649 | intel_crtc->cursor_addr = addr; | |
05394f39 | 7650 | intel_crtc->cursor_bo = obj; |
cda4b7d3 CW |
7651 | intel_crtc->cursor_width = width; |
7652 | intel_crtc->cursor_height = height; | |
7653 | ||
f2f5f771 VS |
7654 | if (intel_crtc->active) |
7655 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); | |
3f8bc370 | 7656 | |
79e53945 | 7657 | return 0; |
e7b526bb | 7658 | fail_unpin: |
cc98b413 | 7659 | i915_gem_object_unpin_from_display_plane(obj); |
7f9872e0 | 7660 | fail_locked: |
34b8686e | 7661 | mutex_unlock(&dev->struct_mutex); |
bc9025bd | 7662 | fail: |
05394f39 | 7663 | drm_gem_object_unreference_unlocked(&obj->base); |
34b8686e | 7664 | return ret; |
79e53945 JB |
7665 | } |
7666 | ||
7667 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
7668 | { | |
79e53945 | 7669 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 7670 | |
92e76c8c VS |
7671 | intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX); |
7672 | intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX); | |
652c393a | 7673 | |
f2f5f771 VS |
7674 | if (intel_crtc->active) |
7675 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); | |
79e53945 JB |
7676 | |
7677 | return 0; | |
b8c00ac5 DA |
7678 | } |
7679 | ||
79e53945 | 7680 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 7681 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 7682 | { |
7203425a | 7683 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 7684 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 7685 | |
7203425a | 7686 | for (i = start; i < end; i++) { |
79e53945 JB |
7687 | intel_crtc->lut_r[i] = red[i] >> 8; |
7688 | intel_crtc->lut_g[i] = green[i] >> 8; | |
7689 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
7690 | } | |
7691 | ||
7692 | intel_crtc_load_lut(crtc); | |
7693 | } | |
7694 | ||
79e53945 JB |
7695 | /* VESA 640x480x72Hz mode to set on the pipe */ |
7696 | static struct drm_display_mode load_detect_mode = { | |
7697 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
7698 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
7699 | }; | |
7700 | ||
a8bb6818 DV |
7701 | static int intel_framebuffer_init(struct drm_device *dev, |
7702 | struct intel_framebuffer *ifb, | |
7703 | struct drm_mode_fb_cmd2 *mode_cmd, | |
7704 | struct drm_i915_gem_object *obj); | |
7705 | ||
7706 | struct drm_framebuffer * | |
7707 | __intel_framebuffer_create(struct drm_device *dev, | |
7708 | struct drm_mode_fb_cmd2 *mode_cmd, | |
7709 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
7710 | { |
7711 | struct intel_framebuffer *intel_fb; | |
7712 | int ret; | |
7713 | ||
7714 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
7715 | if (!intel_fb) { | |
7716 | drm_gem_object_unreference_unlocked(&obj->base); | |
7717 | return ERR_PTR(-ENOMEM); | |
7718 | } | |
7719 | ||
7720 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
7721 | if (ret) |
7722 | goto err; | |
d2dff872 CW |
7723 | |
7724 | return &intel_fb->base; | |
dd4916c5 DV |
7725 | err: |
7726 | drm_gem_object_unreference_unlocked(&obj->base); | |
7727 | kfree(intel_fb); | |
7728 | ||
7729 | return ERR_PTR(ret); | |
d2dff872 CW |
7730 | } |
7731 | ||
a8bb6818 DV |
7732 | struct drm_framebuffer * |
7733 | intel_framebuffer_create(struct drm_device *dev, | |
7734 | struct drm_mode_fb_cmd2 *mode_cmd, | |
7735 | struct drm_i915_gem_object *obj) | |
7736 | { | |
7737 | struct drm_framebuffer *fb; | |
7738 | int ret; | |
7739 | ||
7740 | ret = i915_mutex_lock_interruptible(dev); | |
7741 | if (ret) | |
7742 | return ERR_PTR(ret); | |
7743 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
7744 | mutex_unlock(&dev->struct_mutex); | |
7745 | ||
7746 | return fb; | |
7747 | } | |
7748 | ||
d2dff872 CW |
7749 | static u32 |
7750 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
7751 | { | |
7752 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
7753 | return ALIGN(pitch, 64); | |
7754 | } | |
7755 | ||
7756 | static u32 | |
7757 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
7758 | { | |
7759 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
7760 | return ALIGN(pitch * mode->vdisplay, PAGE_SIZE); | |
7761 | } | |
7762 | ||
7763 | static struct drm_framebuffer * | |
7764 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
7765 | struct drm_display_mode *mode, | |
7766 | int depth, int bpp) | |
7767 | { | |
7768 | struct drm_i915_gem_object *obj; | |
0fed39bd | 7769 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
7770 | |
7771 | obj = i915_gem_alloc_object(dev, | |
7772 | intel_framebuffer_size_for_mode(mode, bpp)); | |
7773 | if (obj == NULL) | |
7774 | return ERR_PTR(-ENOMEM); | |
7775 | ||
7776 | mode_cmd.width = mode->hdisplay; | |
7777 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
7778 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
7779 | bpp); | |
5ca0c34a | 7780 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
7781 | |
7782 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
7783 | } | |
7784 | ||
7785 | static struct drm_framebuffer * | |
7786 | mode_fits_in_fbdev(struct drm_device *dev, | |
7787 | struct drm_display_mode *mode) | |
7788 | { | |
4520f53a | 7789 | #ifdef CONFIG_DRM_I915_FBDEV |
d2dff872 CW |
7790 | struct drm_i915_private *dev_priv = dev->dev_private; |
7791 | struct drm_i915_gem_object *obj; | |
7792 | struct drm_framebuffer *fb; | |
7793 | ||
7794 | if (dev_priv->fbdev == NULL) | |
7795 | return NULL; | |
7796 | ||
8bcd4553 | 7797 | obj = dev_priv->fbdev->fb->obj; |
d2dff872 CW |
7798 | if (obj == NULL) |
7799 | return NULL; | |
7800 | ||
8bcd4553 | 7801 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
7802 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
7803 | fb->bits_per_pixel)) | |
d2dff872 CW |
7804 | return NULL; |
7805 | ||
01f2c773 | 7806 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
7807 | return NULL; |
7808 | ||
7809 | return fb; | |
4520f53a DV |
7810 | #else |
7811 | return NULL; | |
7812 | #endif | |
d2dff872 CW |
7813 | } |
7814 | ||
d2434ab7 | 7815 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 7816 | struct drm_display_mode *mode, |
8261b191 | 7817 | struct intel_load_detect_pipe *old) |
79e53945 JB |
7818 | { |
7819 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
7820 | struct intel_encoder *intel_encoder = |
7821 | intel_attached_encoder(connector); | |
79e53945 | 7822 | struct drm_crtc *possible_crtc; |
4ef69c7a | 7823 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
7824 | struct drm_crtc *crtc = NULL; |
7825 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 7826 | struct drm_framebuffer *fb; |
79e53945 JB |
7827 | int i = -1; |
7828 | ||
d2dff872 CW |
7829 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
7830 | connector->base.id, drm_get_connector_name(connector), | |
7831 | encoder->base.id, drm_get_encoder_name(encoder)); | |
7832 | ||
79e53945 JB |
7833 | /* |
7834 | * Algorithm gets a little messy: | |
7a5e4805 | 7835 | * |
79e53945 JB |
7836 | * - if the connector already has an assigned crtc, use it (but make |
7837 | * sure it's on first) | |
7a5e4805 | 7838 | * |
79e53945 JB |
7839 | * - try to find the first unused crtc that can drive this connector, |
7840 | * and use that if we find one | |
79e53945 JB |
7841 | */ |
7842 | ||
7843 | /* See if we already have a CRTC for this connector */ | |
7844 | if (encoder->crtc) { | |
7845 | crtc = encoder->crtc; | |
8261b191 | 7846 | |
7b24056b DV |
7847 | mutex_lock(&crtc->mutex); |
7848 | ||
24218aac | 7849 | old->dpms_mode = connector->dpms; |
8261b191 CW |
7850 | old->load_detect_temp = false; |
7851 | ||
7852 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
7853 | if (connector->dpms != DRM_MODE_DPMS_ON) |
7854 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 7855 | |
7173188d | 7856 | return true; |
79e53945 JB |
7857 | } |
7858 | ||
7859 | /* Find an unused one (if possible) */ | |
7860 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { | |
7861 | i++; | |
7862 | if (!(encoder->possible_crtcs & (1 << i))) | |
7863 | continue; | |
7864 | if (!possible_crtc->enabled) { | |
7865 | crtc = possible_crtc; | |
7866 | break; | |
7867 | } | |
79e53945 JB |
7868 | } |
7869 | ||
7870 | /* | |
7871 | * If we didn't find an unused CRTC, don't use any. | |
7872 | */ | |
7873 | if (!crtc) { | |
7173188d CW |
7874 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
7875 | return false; | |
79e53945 JB |
7876 | } |
7877 | ||
7b24056b | 7878 | mutex_lock(&crtc->mutex); |
fc303101 DV |
7879 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
7880 | to_intel_connector(connector)->new_encoder = intel_encoder; | |
79e53945 JB |
7881 | |
7882 | intel_crtc = to_intel_crtc(crtc); | |
412b61d8 VS |
7883 | intel_crtc->new_enabled = true; |
7884 | intel_crtc->new_config = &intel_crtc->config; | |
24218aac | 7885 | old->dpms_mode = connector->dpms; |
8261b191 | 7886 | old->load_detect_temp = true; |
d2dff872 | 7887 | old->release_fb = NULL; |
79e53945 | 7888 | |
6492711d CW |
7889 | if (!mode) |
7890 | mode = &load_detect_mode; | |
79e53945 | 7891 | |
d2dff872 CW |
7892 | /* We need a framebuffer large enough to accommodate all accesses |
7893 | * that the plane may generate whilst we perform load detection. | |
7894 | * We can not rely on the fbcon either being present (we get called | |
7895 | * during its initialisation to detect all boot displays, or it may | |
7896 | * not even exist) or that it is large enough to satisfy the | |
7897 | * requested mode. | |
7898 | */ | |
94352cf9 DV |
7899 | fb = mode_fits_in_fbdev(dev, mode); |
7900 | if (fb == NULL) { | |
d2dff872 | 7901 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
7902 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
7903 | old->release_fb = fb; | |
d2dff872 CW |
7904 | } else |
7905 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 7906 | if (IS_ERR(fb)) { |
d2dff872 | 7907 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 7908 | goto fail; |
79e53945 | 7909 | } |
79e53945 | 7910 | |
c0c36b94 | 7911 | if (intel_set_mode(crtc, mode, 0, 0, fb)) { |
6492711d | 7912 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
7913 | if (old->release_fb) |
7914 | old->release_fb->funcs->destroy(old->release_fb); | |
412b61d8 | 7915 | goto fail; |
79e53945 | 7916 | } |
7173188d | 7917 | |
79e53945 | 7918 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 7919 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 7920 | return true; |
412b61d8 VS |
7921 | |
7922 | fail: | |
7923 | intel_crtc->new_enabled = crtc->enabled; | |
7924 | if (intel_crtc->new_enabled) | |
7925 | intel_crtc->new_config = &intel_crtc->config; | |
7926 | else | |
7927 | intel_crtc->new_config = NULL; | |
7928 | mutex_unlock(&crtc->mutex); | |
7929 | return false; | |
79e53945 JB |
7930 | } |
7931 | ||
d2434ab7 | 7932 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
8261b191 | 7933 | struct intel_load_detect_pipe *old) |
79e53945 | 7934 | { |
d2434ab7 DV |
7935 | struct intel_encoder *intel_encoder = |
7936 | intel_attached_encoder(connector); | |
4ef69c7a | 7937 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 7938 | struct drm_crtc *crtc = encoder->crtc; |
412b61d8 | 7939 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 7940 | |
d2dff872 CW |
7941 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
7942 | connector->base.id, drm_get_connector_name(connector), | |
7943 | encoder->base.id, drm_get_encoder_name(encoder)); | |
7944 | ||
8261b191 | 7945 | if (old->load_detect_temp) { |
fc303101 DV |
7946 | to_intel_connector(connector)->new_encoder = NULL; |
7947 | intel_encoder->new_crtc = NULL; | |
412b61d8 VS |
7948 | intel_crtc->new_enabled = false; |
7949 | intel_crtc->new_config = NULL; | |
fc303101 | 7950 | intel_set_mode(crtc, NULL, 0, 0, NULL); |
d2dff872 | 7951 | |
36206361 DV |
7952 | if (old->release_fb) { |
7953 | drm_framebuffer_unregister_private(old->release_fb); | |
7954 | drm_framebuffer_unreference(old->release_fb); | |
7955 | } | |
d2dff872 | 7956 | |
67c96400 | 7957 | mutex_unlock(&crtc->mutex); |
0622a53c | 7958 | return; |
79e53945 JB |
7959 | } |
7960 | ||
c751ce4f | 7961 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
7962 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
7963 | connector->funcs->dpms(connector, old->dpms_mode); | |
7b24056b DV |
7964 | |
7965 | mutex_unlock(&crtc->mutex); | |
79e53945 JB |
7966 | } |
7967 | ||
da4a1efa VS |
7968 | static int i9xx_pll_refclk(struct drm_device *dev, |
7969 | const struct intel_crtc_config *pipe_config) | |
7970 | { | |
7971 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7972 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
7973 | ||
7974 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 7975 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
7976 | else if (HAS_PCH_SPLIT(dev)) |
7977 | return 120000; | |
7978 | else if (!IS_GEN2(dev)) | |
7979 | return 96000; | |
7980 | else | |
7981 | return 48000; | |
7982 | } | |
7983 | ||
79e53945 | 7984 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc JB |
7985 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
7986 | struct intel_crtc_config *pipe_config) | |
79e53945 | 7987 | { |
f1f644dc | 7988 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 7989 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 7990 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 7991 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
7992 | u32 fp; |
7993 | intel_clock_t clock; | |
da4a1efa | 7994 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
7995 | |
7996 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 7997 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 7998 | else |
293623f7 | 7999 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
8000 | |
8001 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
8002 | if (IS_PINEVIEW(dev)) { |
8003 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
8004 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
8005 | } else { |
8006 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
8007 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
8008 | } | |
8009 | ||
a6c45cf0 | 8010 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
8011 | if (IS_PINEVIEW(dev)) |
8012 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
8013 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
8014 | else |
8015 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
8016 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
8017 | ||
8018 | switch (dpll & DPLL_MODE_MASK) { | |
8019 | case DPLLB_MODE_DAC_SERIAL: | |
8020 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
8021 | 5 : 10; | |
8022 | break; | |
8023 | case DPLLB_MODE_LVDS: | |
8024 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
8025 | 7 : 14; | |
8026 | break; | |
8027 | default: | |
28c97730 | 8028 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 8029 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 8030 | return; |
79e53945 JB |
8031 | } |
8032 | ||
ac58c3f0 | 8033 | if (IS_PINEVIEW(dev)) |
da4a1efa | 8034 | pineview_clock(refclk, &clock); |
ac58c3f0 | 8035 | else |
da4a1efa | 8036 | i9xx_clock(refclk, &clock); |
79e53945 | 8037 | } else { |
0fb58223 | 8038 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 8039 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
8040 | |
8041 | if (is_lvds) { | |
8042 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
8043 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
8044 | |
8045 | if (lvds & LVDS_CLKB_POWER_UP) | |
8046 | clock.p2 = 7; | |
8047 | else | |
8048 | clock.p2 = 14; | |
79e53945 JB |
8049 | } else { |
8050 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
8051 | clock.p1 = 2; | |
8052 | else { | |
8053 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
8054 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
8055 | } | |
8056 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
8057 | clock.p2 = 4; | |
8058 | else | |
8059 | clock.p2 = 2; | |
79e53945 | 8060 | } |
da4a1efa VS |
8061 | |
8062 | i9xx_clock(refclk, &clock); | |
79e53945 JB |
8063 | } |
8064 | ||
18442d08 VS |
8065 | /* |
8066 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 8067 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
8068 | * encoder's get_config() function. |
8069 | */ | |
8070 | pipe_config->port_clock = clock.dot; | |
f1f644dc JB |
8071 | } |
8072 | ||
6878da05 VS |
8073 | int intel_dotclock_calculate(int link_freq, |
8074 | const struct intel_link_m_n *m_n) | |
f1f644dc | 8075 | { |
f1f644dc JB |
8076 | /* |
8077 | * The calculation for the data clock is: | |
1041a02f | 8078 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 8079 | * But we want to avoid losing precison if possible, so: |
1041a02f | 8080 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
8081 | * |
8082 | * and the link clock is simpler: | |
1041a02f | 8083 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
8084 | */ |
8085 | ||
6878da05 VS |
8086 | if (!m_n->link_n) |
8087 | return 0; | |
f1f644dc | 8088 | |
6878da05 VS |
8089 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
8090 | } | |
f1f644dc | 8091 | |
18442d08 VS |
8092 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
8093 | struct intel_crtc_config *pipe_config) | |
6878da05 VS |
8094 | { |
8095 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 8096 | |
18442d08 VS |
8097 | /* read out port_clock from the DPLL */ |
8098 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 8099 | |
f1f644dc | 8100 | /* |
18442d08 | 8101 | * This value does not include pixel_multiplier. |
241bfc38 | 8102 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
8103 | * agree once we know their relationship in the encoder's |
8104 | * get_config() function. | |
79e53945 | 8105 | */ |
241bfc38 | 8106 | pipe_config->adjusted_mode.crtc_clock = |
18442d08 VS |
8107 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
8108 | &pipe_config->fdi_m_n); | |
79e53945 JB |
8109 | } |
8110 | ||
8111 | /** Returns the currently programmed mode of the given pipe. */ | |
8112 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
8113 | struct drm_crtc *crtc) | |
8114 | { | |
548f245b | 8115 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 8116 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3b117c8f | 8117 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
79e53945 | 8118 | struct drm_display_mode *mode; |
f1f644dc | 8119 | struct intel_crtc_config pipe_config; |
fe2b8f9d PZ |
8120 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
8121 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
8122 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
8123 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 8124 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
8125 | |
8126 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
8127 | if (!mode) | |
8128 | return NULL; | |
8129 | ||
f1f644dc JB |
8130 | /* |
8131 | * Construct a pipe_config sufficient for getting the clock info | |
8132 | * back out of crtc_clock_get. | |
8133 | * | |
8134 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
8135 | * to use a real value here instead. | |
8136 | */ | |
293623f7 | 8137 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 8138 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
8139 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
8140 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
8141 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
8142 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
8143 | ||
773ae034 | 8144 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
79e53945 JB |
8145 | mode->hdisplay = (htot & 0xffff) + 1; |
8146 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
8147 | mode->hsync_start = (hsync & 0xffff) + 1; | |
8148 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
8149 | mode->vdisplay = (vtot & 0xffff) + 1; | |
8150 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
8151 | mode->vsync_start = (vsync & 0xffff) + 1; | |
8152 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
8153 | ||
8154 | drm_mode_set_name(mode); | |
79e53945 JB |
8155 | |
8156 | return mode; | |
8157 | } | |
8158 | ||
3dec0095 | 8159 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
652c393a JB |
8160 | { |
8161 | struct drm_device *dev = crtc->dev; | |
8162 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8163 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8164 | int pipe = intel_crtc->pipe; | |
dbdc6479 JB |
8165 | int dpll_reg = DPLL(pipe); |
8166 | int dpll; | |
652c393a | 8167 | |
bad720ff | 8168 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
8169 | return; |
8170 | ||
8171 | if (!dev_priv->lvds_downclock_avail) | |
8172 | return; | |
8173 | ||
dbdc6479 | 8174 | dpll = I915_READ(dpll_reg); |
652c393a | 8175 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
44d98a61 | 8176 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
652c393a | 8177 | |
8ac5a6d5 | 8178 | assert_panel_unlocked(dev_priv, pipe); |
652c393a JB |
8179 | |
8180 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; | |
8181 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 8182 | intel_wait_for_vblank(dev, pipe); |
dbdc6479 | 8183 | |
652c393a JB |
8184 | dpll = I915_READ(dpll_reg); |
8185 | if (dpll & DISPLAY_RATE_SELECT_FPA1) | |
44d98a61 | 8186 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
652c393a | 8187 | } |
652c393a JB |
8188 | } |
8189 | ||
8190 | static void intel_decrease_pllclock(struct drm_crtc *crtc) | |
8191 | { | |
8192 | struct drm_device *dev = crtc->dev; | |
8193 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8194 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
652c393a | 8195 | |
bad720ff | 8196 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
8197 | return; |
8198 | ||
8199 | if (!dev_priv->lvds_downclock_avail) | |
8200 | return; | |
8201 | ||
8202 | /* | |
8203 | * Since this is called by a timer, we should never get here in | |
8204 | * the manual case. | |
8205 | */ | |
8206 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
dc257cf1 DV |
8207 | int pipe = intel_crtc->pipe; |
8208 | int dpll_reg = DPLL(pipe); | |
8209 | int dpll; | |
f6e5b160 | 8210 | |
44d98a61 | 8211 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 8212 | |
8ac5a6d5 | 8213 | assert_panel_unlocked(dev_priv, pipe); |
652c393a | 8214 | |
dc257cf1 | 8215 | dpll = I915_READ(dpll_reg); |
652c393a JB |
8216 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
8217 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 8218 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
8219 | dpll = I915_READ(dpll_reg); |
8220 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 8221 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
8222 | } |
8223 | ||
8224 | } | |
8225 | ||
f047e395 CW |
8226 | void intel_mark_busy(struct drm_device *dev) |
8227 | { | |
c67a470b PZ |
8228 | struct drm_i915_private *dev_priv = dev->dev_private; |
8229 | ||
8230 | hsw_package_c8_gpu_busy(dev_priv); | |
8231 | i915_update_gfx_val(dev_priv); | |
f047e395 CW |
8232 | } |
8233 | ||
8234 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 8235 | { |
c67a470b | 8236 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 8237 | struct drm_crtc *crtc; |
652c393a | 8238 | |
c67a470b PZ |
8239 | hsw_package_c8_gpu_idle(dev_priv); |
8240 | ||
d330a953 | 8241 | if (!i915.powersave) |
652c393a JB |
8242 | return; |
8243 | ||
652c393a | 8244 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
652c393a JB |
8245 | if (!crtc->fb) |
8246 | continue; | |
8247 | ||
725a5b54 | 8248 | intel_decrease_pllclock(crtc); |
652c393a | 8249 | } |
b29c19b6 | 8250 | |
3d13ef2e | 8251 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 8252 | gen6_rps_idle(dev->dev_private); |
652c393a JB |
8253 | } |
8254 | ||
c65355bb CW |
8255 | void intel_mark_fb_busy(struct drm_i915_gem_object *obj, |
8256 | struct intel_ring_buffer *ring) | |
652c393a | 8257 | { |
f047e395 CW |
8258 | struct drm_device *dev = obj->base.dev; |
8259 | struct drm_crtc *crtc; | |
652c393a | 8260 | |
d330a953 | 8261 | if (!i915.powersave) |
acb87dfb CW |
8262 | return; |
8263 | ||
652c393a JB |
8264 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
8265 | if (!crtc->fb) | |
8266 | continue; | |
8267 | ||
c65355bb CW |
8268 | if (to_intel_framebuffer(crtc->fb)->obj != obj) |
8269 | continue; | |
8270 | ||
8271 | intel_increase_pllclock(crtc); | |
8272 | if (ring && intel_fbc_enabled(dev)) | |
8273 | ring->fbc_dirty = true; | |
652c393a JB |
8274 | } |
8275 | } | |
8276 | ||
79e53945 JB |
8277 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
8278 | { | |
8279 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
8280 | struct drm_device *dev = crtc->dev; |
8281 | struct intel_unpin_work *work; | |
8282 | unsigned long flags; | |
8283 | ||
8284 | spin_lock_irqsave(&dev->event_lock, flags); | |
8285 | work = intel_crtc->unpin_work; | |
8286 | intel_crtc->unpin_work = NULL; | |
8287 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
8288 | ||
8289 | if (work) { | |
8290 | cancel_work_sync(&work->work); | |
8291 | kfree(work); | |
8292 | } | |
79e53945 | 8293 | |
40ccc72b MK |
8294 | intel_crtc_cursor_set(crtc, NULL, 0, 0, 0); |
8295 | ||
79e53945 | 8296 | drm_crtc_cleanup(crtc); |
67e77c5a | 8297 | |
79e53945 JB |
8298 | kfree(intel_crtc); |
8299 | } | |
8300 | ||
6b95a207 KH |
8301 | static void intel_unpin_work_fn(struct work_struct *__work) |
8302 | { | |
8303 | struct intel_unpin_work *work = | |
8304 | container_of(__work, struct intel_unpin_work, work); | |
b4a98e57 | 8305 | struct drm_device *dev = work->crtc->dev; |
6b95a207 | 8306 | |
b4a98e57 | 8307 | mutex_lock(&dev->struct_mutex); |
1690e1eb | 8308 | intel_unpin_fb_obj(work->old_fb_obj); |
05394f39 CW |
8309 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
8310 | drm_gem_object_unreference(&work->old_fb_obj->base); | |
d9e86c0e | 8311 | |
b4a98e57 CW |
8312 | intel_update_fbc(dev); |
8313 | mutex_unlock(&dev->struct_mutex); | |
8314 | ||
8315 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); | |
8316 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); | |
8317 | ||
6b95a207 KH |
8318 | kfree(work); |
8319 | } | |
8320 | ||
1afe3e9d | 8321 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 8322 | struct drm_crtc *crtc) |
6b95a207 KH |
8323 | { |
8324 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6b95a207 KH |
8325 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8326 | struct intel_unpin_work *work; | |
6b95a207 KH |
8327 | unsigned long flags; |
8328 | ||
8329 | /* Ignore early vblank irqs */ | |
8330 | if (intel_crtc == NULL) | |
8331 | return; | |
8332 | ||
8333 | spin_lock_irqsave(&dev->event_lock, flags); | |
8334 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
8335 | |
8336 | /* Ensure we don't miss a work->pending update ... */ | |
8337 | smp_rmb(); | |
8338 | ||
8339 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
8340 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8341 | return; | |
8342 | } | |
8343 | ||
e7d841ca CW |
8344 | /* and that the unpin work is consistent wrt ->pending. */ |
8345 | smp_rmb(); | |
8346 | ||
6b95a207 | 8347 | intel_crtc->unpin_work = NULL; |
6b95a207 | 8348 | |
45a066eb RC |
8349 | if (work->event) |
8350 | drm_send_vblank_event(dev, intel_crtc->pipe, work->event); | |
6b95a207 | 8351 | |
0af7e4df MK |
8352 | drm_vblank_put(dev, intel_crtc->pipe); |
8353 | ||
6b95a207 KH |
8354 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8355 | ||
2c10d571 | 8356 | wake_up_all(&dev_priv->pending_flip_queue); |
b4a98e57 CW |
8357 | |
8358 | queue_work(dev_priv->wq, &work->work); | |
e5510fac JB |
8359 | |
8360 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); | |
6b95a207 KH |
8361 | } |
8362 | ||
1afe3e9d JB |
8363 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
8364 | { | |
8365 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8366 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
8367 | ||
49b14a5c | 8368 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
8369 | } |
8370 | ||
8371 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
8372 | { | |
8373 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8374 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; | |
8375 | ||
49b14a5c | 8376 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
8377 | } |
8378 | ||
6b95a207 KH |
8379 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
8380 | { | |
8381 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8382 | struct intel_crtc *intel_crtc = | |
8383 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
8384 | unsigned long flags; | |
8385 | ||
e7d841ca CW |
8386 | /* NB: An MMIO update of the plane base pointer will also |
8387 | * generate a page-flip completion irq, i.e. every modeset | |
8388 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
8389 | */ | |
6b95a207 | 8390 | spin_lock_irqsave(&dev->event_lock, flags); |
e7d841ca CW |
8391 | if (intel_crtc->unpin_work) |
8392 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); | |
6b95a207 KH |
8393 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8394 | } | |
8395 | ||
e7d841ca CW |
8396 | inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
8397 | { | |
8398 | /* Ensure that the work item is consistent when activating it ... */ | |
8399 | smp_wmb(); | |
8400 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); | |
8401 | /* and that it is marked active as soon as the irq could fire. */ | |
8402 | smp_wmb(); | |
8403 | } | |
8404 | ||
8c9f3aaf JB |
8405 | static int intel_gen2_queue_flip(struct drm_device *dev, |
8406 | struct drm_crtc *crtc, | |
8407 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8408 | struct drm_i915_gem_object *obj, |
8409 | uint32_t flags) | |
8c9f3aaf JB |
8410 | { |
8411 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8412 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8c9f3aaf | 8413 | u32 flip_mask; |
6d90c952 | 8414 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
8415 | int ret; |
8416 | ||
6d90c952 | 8417 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 8418 | if (ret) |
83d4092b | 8419 | goto err; |
8c9f3aaf | 8420 | |
6d90c952 | 8421 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 8422 | if (ret) |
83d4092b | 8423 | goto err_unpin; |
8c9f3aaf JB |
8424 | |
8425 | /* Can't queue multiple flips, so wait for the previous | |
8426 | * one to finish before executing the next. | |
8427 | */ | |
8428 | if (intel_crtc->plane) | |
8429 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
8430 | else | |
8431 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
8432 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
8433 | intel_ring_emit(ring, MI_NOOP); | |
8434 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
8435 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
8436 | intel_ring_emit(ring, fb->pitches[0]); | |
f343c5f6 | 8437 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
6d90c952 | 8438 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca CW |
8439 | |
8440 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 8441 | __intel_ring_advance(ring); |
83d4092b CW |
8442 | return 0; |
8443 | ||
8444 | err_unpin: | |
8445 | intel_unpin_fb_obj(obj); | |
8446 | err: | |
8c9f3aaf JB |
8447 | return ret; |
8448 | } | |
8449 | ||
8450 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
8451 | struct drm_crtc *crtc, | |
8452 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8453 | struct drm_i915_gem_object *obj, |
8454 | uint32_t flags) | |
8c9f3aaf JB |
8455 | { |
8456 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8457 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8c9f3aaf | 8458 | u32 flip_mask; |
6d90c952 | 8459 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
8460 | int ret; |
8461 | ||
6d90c952 | 8462 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 8463 | if (ret) |
83d4092b | 8464 | goto err; |
8c9f3aaf | 8465 | |
6d90c952 | 8466 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 8467 | if (ret) |
83d4092b | 8468 | goto err_unpin; |
8c9f3aaf JB |
8469 | |
8470 | if (intel_crtc->plane) | |
8471 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
8472 | else | |
8473 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
8474 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
8475 | intel_ring_emit(ring, MI_NOOP); | |
8476 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
8477 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
8478 | intel_ring_emit(ring, fb->pitches[0]); | |
f343c5f6 | 8479 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
6d90c952 DV |
8480 | intel_ring_emit(ring, MI_NOOP); |
8481 | ||
e7d841ca | 8482 | intel_mark_page_flip_active(intel_crtc); |
09246732 | 8483 | __intel_ring_advance(ring); |
83d4092b CW |
8484 | return 0; |
8485 | ||
8486 | err_unpin: | |
8487 | intel_unpin_fb_obj(obj); | |
8488 | err: | |
8c9f3aaf JB |
8489 | return ret; |
8490 | } | |
8491 | ||
8492 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
8493 | struct drm_crtc *crtc, | |
8494 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8495 | struct drm_i915_gem_object *obj, |
8496 | uint32_t flags) | |
8c9f3aaf JB |
8497 | { |
8498 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8499 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8500 | uint32_t pf, pipesrc; | |
6d90c952 | 8501 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
8502 | int ret; |
8503 | ||
6d90c952 | 8504 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 8505 | if (ret) |
83d4092b | 8506 | goto err; |
8c9f3aaf | 8507 | |
6d90c952 | 8508 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 8509 | if (ret) |
83d4092b | 8510 | goto err_unpin; |
8c9f3aaf JB |
8511 | |
8512 | /* i965+ uses the linear or tiled offsets from the | |
8513 | * Display Registers (which do not change across a page-flip) | |
8514 | * so we need only reprogram the base address. | |
8515 | */ | |
6d90c952 DV |
8516 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
8517 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
8518 | intel_ring_emit(ring, fb->pitches[0]); | |
c2c75131 | 8519 | intel_ring_emit(ring, |
f343c5f6 | 8520 | (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) | |
c2c75131 | 8521 | obj->tiling_mode); |
8c9f3aaf JB |
8522 | |
8523 | /* XXX Enabling the panel-fitter across page-flip is so far | |
8524 | * untested on non-native modes, so ignore it for now. | |
8525 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
8526 | */ | |
8527 | pf = 0; | |
8528 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 8529 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
8530 | |
8531 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 8532 | __intel_ring_advance(ring); |
83d4092b CW |
8533 | return 0; |
8534 | ||
8535 | err_unpin: | |
8536 | intel_unpin_fb_obj(obj); | |
8537 | err: | |
8c9f3aaf JB |
8538 | return ret; |
8539 | } | |
8540 | ||
8541 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
8542 | struct drm_crtc *crtc, | |
8543 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8544 | struct drm_i915_gem_object *obj, |
8545 | uint32_t flags) | |
8c9f3aaf JB |
8546 | { |
8547 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8548 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6d90c952 | 8549 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
8550 | uint32_t pf, pipesrc; |
8551 | int ret; | |
8552 | ||
6d90c952 | 8553 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 8554 | if (ret) |
83d4092b | 8555 | goto err; |
8c9f3aaf | 8556 | |
6d90c952 | 8557 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 8558 | if (ret) |
83d4092b | 8559 | goto err_unpin; |
8c9f3aaf | 8560 | |
6d90c952 DV |
8561 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
8562 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
8563 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
f343c5f6 | 8564 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
8c9f3aaf | 8565 | |
dc257cf1 DV |
8566 | /* Contrary to the suggestions in the documentation, |
8567 | * "Enable Panel Fitter" does not seem to be required when page | |
8568 | * flipping with a non-native mode, and worse causes a normal | |
8569 | * modeset to fail. | |
8570 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
8571 | */ | |
8572 | pf = 0; | |
8c9f3aaf | 8573 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 8574 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
8575 | |
8576 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 8577 | __intel_ring_advance(ring); |
83d4092b CW |
8578 | return 0; |
8579 | ||
8580 | err_unpin: | |
8581 | intel_unpin_fb_obj(obj); | |
8582 | err: | |
8c9f3aaf JB |
8583 | return ret; |
8584 | } | |
8585 | ||
7c9017e5 JB |
8586 | static int intel_gen7_queue_flip(struct drm_device *dev, |
8587 | struct drm_crtc *crtc, | |
8588 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8589 | struct drm_i915_gem_object *obj, |
8590 | uint32_t flags) | |
7c9017e5 JB |
8591 | { |
8592 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8593 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ffe74d75 | 8594 | struct intel_ring_buffer *ring; |
cb05d8de | 8595 | uint32_t plane_bit = 0; |
ffe74d75 CW |
8596 | int len, ret; |
8597 | ||
8598 | ring = obj->ring; | |
1c5fd085 | 8599 | if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS) |
ffe74d75 | 8600 | ring = &dev_priv->ring[BCS]; |
7c9017e5 JB |
8601 | |
8602 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); | |
8603 | if (ret) | |
83d4092b | 8604 | goto err; |
7c9017e5 | 8605 | |
cb05d8de DV |
8606 | switch(intel_crtc->plane) { |
8607 | case PLANE_A: | |
8608 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
8609 | break; | |
8610 | case PLANE_B: | |
8611 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
8612 | break; | |
8613 | case PLANE_C: | |
8614 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
8615 | break; | |
8616 | default: | |
8617 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
8618 | ret = -ENODEV; | |
ab3951eb | 8619 | goto err_unpin; |
cb05d8de DV |
8620 | } |
8621 | ||
ffe74d75 CW |
8622 | len = 4; |
8623 | if (ring->id == RCS) | |
8624 | len += 6; | |
8625 | ||
8626 | ret = intel_ring_begin(ring, len); | |
7c9017e5 | 8627 | if (ret) |
83d4092b | 8628 | goto err_unpin; |
7c9017e5 | 8629 | |
ffe74d75 CW |
8630 | /* Unmask the flip-done completion message. Note that the bspec says that |
8631 | * we should do this for both the BCS and RCS, and that we must not unmask | |
8632 | * more than one flip event at any time (or ensure that one flip message | |
8633 | * can be sent by waiting for flip-done prior to queueing new flips). | |
8634 | * Experimentation says that BCS works despite DERRMR masking all | |
8635 | * flip-done completion events and that unmasking all planes at once | |
8636 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
8637 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
8638 | */ | |
8639 | if (ring->id == RCS) { | |
8640 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
8641 | intel_ring_emit(ring, DERRMR); | |
8642 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
8643 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
8644 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
22613c96 VS |
8645 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | |
8646 | MI_SRM_LRM_GLOBAL_GTT); | |
ffe74d75 CW |
8647 | intel_ring_emit(ring, DERRMR); |
8648 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
8649 | } | |
8650 | ||
cb05d8de | 8651 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 8652 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
f343c5f6 | 8653 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
7c9017e5 | 8654 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca CW |
8655 | |
8656 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 8657 | __intel_ring_advance(ring); |
83d4092b CW |
8658 | return 0; |
8659 | ||
8660 | err_unpin: | |
8661 | intel_unpin_fb_obj(obj); | |
8662 | err: | |
7c9017e5 JB |
8663 | return ret; |
8664 | } | |
8665 | ||
8c9f3aaf JB |
8666 | static int intel_default_queue_flip(struct drm_device *dev, |
8667 | struct drm_crtc *crtc, | |
8668 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8669 | struct drm_i915_gem_object *obj, |
8670 | uint32_t flags) | |
8c9f3aaf JB |
8671 | { |
8672 | return -ENODEV; | |
8673 | } | |
8674 | ||
6b95a207 KH |
8675 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
8676 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8677 | struct drm_pending_vblank_event *event, |
8678 | uint32_t page_flip_flags) | |
6b95a207 KH |
8679 | { |
8680 | struct drm_device *dev = crtc->dev; | |
8681 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4a35f83b VS |
8682 | struct drm_framebuffer *old_fb = crtc->fb; |
8683 | struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj; | |
6b95a207 KH |
8684 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8685 | struct intel_unpin_work *work; | |
8c9f3aaf | 8686 | unsigned long flags; |
52e68630 | 8687 | int ret; |
6b95a207 | 8688 | |
e6a595d2 VS |
8689 | /* Can't change pixel format via MI display flips. */ |
8690 | if (fb->pixel_format != crtc->fb->pixel_format) | |
8691 | return -EINVAL; | |
8692 | ||
8693 | /* | |
8694 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
8695 | * Note that pitch changes could also affect these register. | |
8696 | */ | |
8697 | if (INTEL_INFO(dev)->gen > 3 && | |
8698 | (fb->offsets[0] != crtc->fb->offsets[0] || | |
8699 | fb->pitches[0] != crtc->fb->pitches[0])) | |
8700 | return -EINVAL; | |
8701 | ||
b14c5679 | 8702 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
8703 | if (work == NULL) |
8704 | return -ENOMEM; | |
8705 | ||
6b95a207 | 8706 | work->event = event; |
b4a98e57 | 8707 | work->crtc = crtc; |
4a35f83b | 8708 | work->old_fb_obj = to_intel_framebuffer(old_fb)->obj; |
6b95a207 KH |
8709 | INIT_WORK(&work->work, intel_unpin_work_fn); |
8710 | ||
7317c75e JB |
8711 | ret = drm_vblank_get(dev, intel_crtc->pipe); |
8712 | if (ret) | |
8713 | goto free_work; | |
8714 | ||
6b95a207 KH |
8715 | /* We borrow the event spin lock for protecting unpin_work */ |
8716 | spin_lock_irqsave(&dev->event_lock, flags); | |
8717 | if (intel_crtc->unpin_work) { | |
8718 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
8719 | kfree(work); | |
7317c75e | 8720 | drm_vblank_put(dev, intel_crtc->pipe); |
468f0b44 CW |
8721 | |
8722 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
6b95a207 KH |
8723 | return -EBUSY; |
8724 | } | |
8725 | intel_crtc->unpin_work = work; | |
8726 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
8727 | ||
b4a98e57 CW |
8728 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
8729 | flush_workqueue(dev_priv->wq); | |
8730 | ||
79158103 CW |
8731 | ret = i915_mutex_lock_interruptible(dev); |
8732 | if (ret) | |
8733 | goto cleanup; | |
6b95a207 | 8734 | |
75dfca80 | 8735 | /* Reference the objects for the scheduled work. */ |
05394f39 CW |
8736 | drm_gem_object_reference(&work->old_fb_obj->base); |
8737 | drm_gem_object_reference(&obj->base); | |
6b95a207 KH |
8738 | |
8739 | crtc->fb = fb; | |
96b099fd | 8740 | |
e1f99ce6 | 8741 | work->pending_flip_obj = obj; |
e1f99ce6 | 8742 | |
4e5359cd SF |
8743 | work->enable_stall_check = true; |
8744 | ||
b4a98e57 | 8745 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 8746 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 8747 | |
ed8d1975 | 8748 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags); |
8c9f3aaf JB |
8749 | if (ret) |
8750 | goto cleanup_pending; | |
6b95a207 | 8751 | |
7782de3b | 8752 | intel_disable_fbc(dev); |
c65355bb | 8753 | intel_mark_fb_busy(obj, NULL); |
6b95a207 KH |
8754 | mutex_unlock(&dev->struct_mutex); |
8755 | ||
e5510fac JB |
8756 | trace_i915_flip_request(intel_crtc->plane, obj); |
8757 | ||
6b95a207 | 8758 | return 0; |
96b099fd | 8759 | |
8c9f3aaf | 8760 | cleanup_pending: |
b4a98e57 | 8761 | atomic_dec(&intel_crtc->unpin_work_count); |
4a35f83b | 8762 | crtc->fb = old_fb; |
05394f39 CW |
8763 | drm_gem_object_unreference(&work->old_fb_obj->base); |
8764 | drm_gem_object_unreference(&obj->base); | |
96b099fd CW |
8765 | mutex_unlock(&dev->struct_mutex); |
8766 | ||
79158103 | 8767 | cleanup: |
96b099fd CW |
8768 | spin_lock_irqsave(&dev->event_lock, flags); |
8769 | intel_crtc->unpin_work = NULL; | |
8770 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
8771 | ||
7317c75e JB |
8772 | drm_vblank_put(dev, intel_crtc->pipe); |
8773 | free_work: | |
96b099fd CW |
8774 | kfree(work); |
8775 | ||
8776 | return ret; | |
6b95a207 KH |
8777 | } |
8778 | ||
f6e5b160 | 8779 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
8780 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
8781 | .load_lut = intel_crtc_load_lut, | |
f6e5b160 CW |
8782 | }; |
8783 | ||
9a935856 DV |
8784 | /** |
8785 | * intel_modeset_update_staged_output_state | |
8786 | * | |
8787 | * Updates the staged output configuration state, e.g. after we've read out the | |
8788 | * current hw state. | |
8789 | */ | |
8790 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) | |
f6e5b160 | 8791 | { |
7668851f | 8792 | struct intel_crtc *crtc; |
9a935856 DV |
8793 | struct intel_encoder *encoder; |
8794 | struct intel_connector *connector; | |
f6e5b160 | 8795 | |
9a935856 DV |
8796 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8797 | base.head) { | |
8798 | connector->new_encoder = | |
8799 | to_intel_encoder(connector->base.encoder); | |
8800 | } | |
f6e5b160 | 8801 | |
9a935856 DV |
8802 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8803 | base.head) { | |
8804 | encoder->new_crtc = | |
8805 | to_intel_crtc(encoder->base.crtc); | |
8806 | } | |
7668851f VS |
8807 | |
8808 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
8809 | base.head) { | |
8810 | crtc->new_enabled = crtc->base.enabled; | |
7bd0a8e7 VS |
8811 | |
8812 | if (crtc->new_enabled) | |
8813 | crtc->new_config = &crtc->config; | |
8814 | else | |
8815 | crtc->new_config = NULL; | |
7668851f | 8816 | } |
f6e5b160 CW |
8817 | } |
8818 | ||
9a935856 DV |
8819 | /** |
8820 | * intel_modeset_commit_output_state | |
8821 | * | |
8822 | * This function copies the stage display pipe configuration to the real one. | |
8823 | */ | |
8824 | static void intel_modeset_commit_output_state(struct drm_device *dev) | |
8825 | { | |
7668851f | 8826 | struct intel_crtc *crtc; |
9a935856 DV |
8827 | struct intel_encoder *encoder; |
8828 | struct intel_connector *connector; | |
f6e5b160 | 8829 | |
9a935856 DV |
8830 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8831 | base.head) { | |
8832 | connector->base.encoder = &connector->new_encoder->base; | |
8833 | } | |
f6e5b160 | 8834 | |
9a935856 DV |
8835 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8836 | base.head) { | |
8837 | encoder->base.crtc = &encoder->new_crtc->base; | |
8838 | } | |
7668851f VS |
8839 | |
8840 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
8841 | base.head) { | |
8842 | crtc->base.enabled = crtc->new_enabled; | |
8843 | } | |
9a935856 DV |
8844 | } |
8845 | ||
050f7aeb DV |
8846 | static void |
8847 | connected_sink_compute_bpp(struct intel_connector * connector, | |
8848 | struct intel_crtc_config *pipe_config) | |
8849 | { | |
8850 | int bpp = pipe_config->pipe_bpp; | |
8851 | ||
8852 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
8853 | connector->base.base.id, | |
8854 | drm_get_connector_name(&connector->base)); | |
8855 | ||
8856 | /* Don't use an invalid EDID bpc value */ | |
8857 | if (connector->base.display_info.bpc && | |
8858 | connector->base.display_info.bpc * 3 < bpp) { | |
8859 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
8860 | bpp, connector->base.display_info.bpc*3); | |
8861 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
8862 | } | |
8863 | ||
8864 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
8865 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
8866 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
8867 | bpp); | |
8868 | pipe_config->pipe_bpp = 24; | |
8869 | } | |
8870 | } | |
8871 | ||
4e53c2e0 | 8872 | static int |
050f7aeb DV |
8873 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
8874 | struct drm_framebuffer *fb, | |
8875 | struct intel_crtc_config *pipe_config) | |
4e53c2e0 | 8876 | { |
050f7aeb DV |
8877 | struct drm_device *dev = crtc->base.dev; |
8878 | struct intel_connector *connector; | |
4e53c2e0 DV |
8879 | int bpp; |
8880 | ||
d42264b1 DV |
8881 | switch (fb->pixel_format) { |
8882 | case DRM_FORMAT_C8: | |
4e53c2e0 DV |
8883 | bpp = 8*3; /* since we go through a colormap */ |
8884 | break; | |
d42264b1 DV |
8885 | case DRM_FORMAT_XRGB1555: |
8886 | case DRM_FORMAT_ARGB1555: | |
8887 | /* checked in intel_framebuffer_init already */ | |
8888 | if (WARN_ON(INTEL_INFO(dev)->gen > 3)) | |
8889 | return -EINVAL; | |
8890 | case DRM_FORMAT_RGB565: | |
4e53c2e0 DV |
8891 | bpp = 6*3; /* min is 18bpp */ |
8892 | break; | |
d42264b1 DV |
8893 | case DRM_FORMAT_XBGR8888: |
8894 | case DRM_FORMAT_ABGR8888: | |
8895 | /* checked in intel_framebuffer_init already */ | |
8896 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
8897 | return -EINVAL; | |
8898 | case DRM_FORMAT_XRGB8888: | |
8899 | case DRM_FORMAT_ARGB8888: | |
4e53c2e0 DV |
8900 | bpp = 8*3; |
8901 | break; | |
d42264b1 DV |
8902 | case DRM_FORMAT_XRGB2101010: |
8903 | case DRM_FORMAT_ARGB2101010: | |
8904 | case DRM_FORMAT_XBGR2101010: | |
8905 | case DRM_FORMAT_ABGR2101010: | |
8906 | /* checked in intel_framebuffer_init already */ | |
8907 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
baba133a | 8908 | return -EINVAL; |
4e53c2e0 DV |
8909 | bpp = 10*3; |
8910 | break; | |
baba133a | 8911 | /* TODO: gen4+ supports 16 bpc floating point, too. */ |
4e53c2e0 DV |
8912 | default: |
8913 | DRM_DEBUG_KMS("unsupported depth\n"); | |
8914 | return -EINVAL; | |
8915 | } | |
8916 | ||
4e53c2e0 DV |
8917 | pipe_config->pipe_bpp = bpp; |
8918 | ||
8919 | /* Clamp display bpp to EDID value */ | |
8920 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
050f7aeb | 8921 | base.head) { |
1b829e05 DV |
8922 | if (!connector->new_encoder || |
8923 | connector->new_encoder->new_crtc != crtc) | |
4e53c2e0 DV |
8924 | continue; |
8925 | ||
050f7aeb | 8926 | connected_sink_compute_bpp(connector, pipe_config); |
4e53c2e0 DV |
8927 | } |
8928 | ||
8929 | return bpp; | |
8930 | } | |
8931 | ||
644db711 DV |
8932 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
8933 | { | |
8934 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
8935 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 8936 | mode->crtc_clock, |
644db711 DV |
8937 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
8938 | mode->crtc_hsync_end, mode->crtc_htotal, | |
8939 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
8940 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
8941 | } | |
8942 | ||
c0b03411 DV |
8943 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
8944 | struct intel_crtc_config *pipe_config, | |
8945 | const char *context) | |
8946 | { | |
8947 | DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id, | |
8948 | context, pipe_name(crtc->pipe)); | |
8949 | ||
8950 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
8951 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
8952 | pipe_config->pipe_bpp, pipe_config->dither); | |
8953 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
8954 | pipe_config->has_pch_encoder, | |
8955 | pipe_config->fdi_lanes, | |
8956 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
8957 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
8958 | pipe_config->fdi_m_n.tu); | |
eb14cb74 VS |
8959 | DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
8960 | pipe_config->has_dp_encoder, | |
8961 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, | |
8962 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
8963 | pipe_config->dp_m_n.tu); | |
c0b03411 DV |
8964 | DRM_DEBUG_KMS("requested mode:\n"); |
8965 | drm_mode_debug_printmodeline(&pipe_config->requested_mode); | |
8966 | DRM_DEBUG_KMS("adjusted mode:\n"); | |
8967 | drm_mode_debug_printmodeline(&pipe_config->adjusted_mode); | |
644db711 | 8968 | intel_dump_crtc_timings(&pipe_config->adjusted_mode); |
d71b8d4a | 8969 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
8970 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
8971 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
c0b03411 DV |
8972 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
8973 | pipe_config->gmch_pfit.control, | |
8974 | pipe_config->gmch_pfit.pgm_ratios, | |
8975 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 8976 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 8977 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
8978 | pipe_config->pch_pfit.size, |
8979 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 8980 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 8981 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
c0b03411 DV |
8982 | } |
8983 | ||
accfc0c5 DV |
8984 | static bool check_encoder_cloning(struct drm_crtc *crtc) |
8985 | { | |
8986 | int num_encoders = 0; | |
8987 | bool uncloneable_encoders = false; | |
8988 | struct intel_encoder *encoder; | |
8989 | ||
8990 | list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list, | |
8991 | base.head) { | |
8992 | if (&encoder->new_crtc->base != crtc) | |
8993 | continue; | |
8994 | ||
8995 | num_encoders++; | |
8996 | if (!encoder->cloneable) | |
8997 | uncloneable_encoders = true; | |
8998 | } | |
8999 | ||
9000 | return !(num_encoders > 1 && uncloneable_encoders); | |
9001 | } | |
9002 | ||
b8cecdf5 DV |
9003 | static struct intel_crtc_config * |
9004 | intel_modeset_pipe_config(struct drm_crtc *crtc, | |
4e53c2e0 | 9005 | struct drm_framebuffer *fb, |
b8cecdf5 | 9006 | struct drm_display_mode *mode) |
ee7b9f93 | 9007 | { |
7758a113 | 9008 | struct drm_device *dev = crtc->dev; |
7758a113 | 9009 | struct intel_encoder *encoder; |
b8cecdf5 | 9010 | struct intel_crtc_config *pipe_config; |
e29c22c0 DV |
9011 | int plane_bpp, ret = -EINVAL; |
9012 | bool retry = true; | |
ee7b9f93 | 9013 | |
accfc0c5 DV |
9014 | if (!check_encoder_cloning(crtc)) { |
9015 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
9016 | return ERR_PTR(-EINVAL); | |
9017 | } | |
9018 | ||
b8cecdf5 DV |
9019 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
9020 | if (!pipe_config) | |
7758a113 DV |
9021 | return ERR_PTR(-ENOMEM); |
9022 | ||
b8cecdf5 DV |
9023 | drm_mode_copy(&pipe_config->adjusted_mode, mode); |
9024 | drm_mode_copy(&pipe_config->requested_mode, mode); | |
37327abd | 9025 | |
e143a21c DV |
9026 | pipe_config->cpu_transcoder = |
9027 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
c0d43d62 | 9028 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
b8cecdf5 | 9029 | |
2960bc9c ID |
9030 | /* |
9031 | * Sanitize sync polarity flags based on requested ones. If neither | |
9032 | * positive or negative polarity is requested, treat this as meaning | |
9033 | * negative polarity. | |
9034 | */ | |
9035 | if (!(pipe_config->adjusted_mode.flags & | |
9036 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) | |
9037 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; | |
9038 | ||
9039 | if (!(pipe_config->adjusted_mode.flags & | |
9040 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) | |
9041 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; | |
9042 | ||
050f7aeb DV |
9043 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
9044 | * plane pixel format and any sink constraints into account. Returns the | |
9045 | * source plane bpp so that dithering can be selected on mismatches | |
9046 | * after encoders and crtc also have had their say. */ | |
9047 | plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), | |
9048 | fb, pipe_config); | |
4e53c2e0 DV |
9049 | if (plane_bpp < 0) |
9050 | goto fail; | |
9051 | ||
e41a56be VS |
9052 | /* |
9053 | * Determine the real pipe dimensions. Note that stereo modes can | |
9054 | * increase the actual pipe size due to the frame doubling and | |
9055 | * insertion of additional space for blanks between the frame. This | |
9056 | * is stored in the crtc timings. We use the requested mode to do this | |
9057 | * computation to clearly distinguish it from the adjusted mode, which | |
9058 | * can be changed by the connectors in the below retry loop. | |
9059 | */ | |
9060 | drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE); | |
9061 | pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay; | |
9062 | pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay; | |
9063 | ||
e29c22c0 | 9064 | encoder_retry: |
ef1b460d | 9065 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 9066 | pipe_config->port_clock = 0; |
ef1b460d | 9067 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 9068 | |
135c81b8 | 9069 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
6ce70f5e | 9070 | drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE); |
135c81b8 | 9071 | |
7758a113 DV |
9072 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
9073 | * adjust it according to limitations or connector properties, and also | |
9074 | * a chance to reject the mode entirely. | |
47f1c6c9 | 9075 | */ |
7758a113 DV |
9076 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9077 | base.head) { | |
47f1c6c9 | 9078 | |
7758a113 DV |
9079 | if (&encoder->new_crtc->base != crtc) |
9080 | continue; | |
7ae89233 | 9081 | |
efea6e8e DV |
9082 | if (!(encoder->compute_config(encoder, pipe_config))) { |
9083 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
9084 | goto fail; |
9085 | } | |
ee7b9f93 | 9086 | } |
47f1c6c9 | 9087 | |
ff9a6750 DV |
9088 | /* Set default port clock if not overwritten by the encoder. Needs to be |
9089 | * done afterwards in case the encoder adjusts the mode. */ | |
9090 | if (!pipe_config->port_clock) | |
241bfc38 DL |
9091 | pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock |
9092 | * pipe_config->pixel_multiplier; | |
ff9a6750 | 9093 | |
a43f6e0f | 9094 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 9095 | if (ret < 0) { |
7758a113 DV |
9096 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
9097 | goto fail; | |
ee7b9f93 | 9098 | } |
e29c22c0 DV |
9099 | |
9100 | if (ret == RETRY) { | |
9101 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
9102 | ret = -EINVAL; | |
9103 | goto fail; | |
9104 | } | |
9105 | ||
9106 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
9107 | retry = false; | |
9108 | goto encoder_retry; | |
9109 | } | |
9110 | ||
4e53c2e0 DV |
9111 | pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; |
9112 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", | |
9113 | plane_bpp, pipe_config->pipe_bpp, pipe_config->dither); | |
9114 | ||
b8cecdf5 | 9115 | return pipe_config; |
7758a113 | 9116 | fail: |
b8cecdf5 | 9117 | kfree(pipe_config); |
e29c22c0 | 9118 | return ERR_PTR(ret); |
ee7b9f93 | 9119 | } |
47f1c6c9 | 9120 | |
e2e1ed41 DV |
9121 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
9122 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ | |
9123 | static void | |
9124 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, | |
9125 | unsigned *prepare_pipes, unsigned *disable_pipes) | |
79e53945 JB |
9126 | { |
9127 | struct intel_crtc *intel_crtc; | |
e2e1ed41 DV |
9128 | struct drm_device *dev = crtc->dev; |
9129 | struct intel_encoder *encoder; | |
9130 | struct intel_connector *connector; | |
9131 | struct drm_crtc *tmp_crtc; | |
79e53945 | 9132 | |
e2e1ed41 | 9133 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
79e53945 | 9134 | |
e2e1ed41 DV |
9135 | /* Check which crtcs have changed outputs connected to them, these need |
9136 | * to be part of the prepare_pipes mask. We don't (yet) support global | |
9137 | * modeset across multiple crtcs, so modeset_pipes will only have one | |
9138 | * bit set at most. */ | |
9139 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
9140 | base.head) { | |
9141 | if (connector->base.encoder == &connector->new_encoder->base) | |
9142 | continue; | |
79e53945 | 9143 | |
e2e1ed41 DV |
9144 | if (connector->base.encoder) { |
9145 | tmp_crtc = connector->base.encoder->crtc; | |
9146 | ||
9147 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
9148 | } | |
9149 | ||
9150 | if (connector->new_encoder) | |
9151 | *prepare_pipes |= | |
9152 | 1 << connector->new_encoder->new_crtc->pipe; | |
79e53945 JB |
9153 | } |
9154 | ||
e2e1ed41 DV |
9155 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9156 | base.head) { | |
9157 | if (encoder->base.crtc == &encoder->new_crtc->base) | |
9158 | continue; | |
9159 | ||
9160 | if (encoder->base.crtc) { | |
9161 | tmp_crtc = encoder->base.crtc; | |
9162 | ||
9163 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
9164 | } | |
9165 | ||
9166 | if (encoder->new_crtc) | |
9167 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; | |
80824003 JB |
9168 | } |
9169 | ||
7668851f | 9170 | /* Check for pipes that will be enabled/disabled ... */ |
e2e1ed41 DV |
9171 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
9172 | base.head) { | |
7668851f | 9173 | if (intel_crtc->base.enabled == intel_crtc->new_enabled) |
e2e1ed41 | 9174 | continue; |
7e7d76c3 | 9175 | |
7668851f | 9176 | if (!intel_crtc->new_enabled) |
e2e1ed41 | 9177 | *disable_pipes |= 1 << intel_crtc->pipe; |
7668851f VS |
9178 | else |
9179 | *prepare_pipes |= 1 << intel_crtc->pipe; | |
7e7d76c3 JB |
9180 | } |
9181 | ||
e2e1ed41 DV |
9182 | |
9183 | /* set_mode is also used to update properties on life display pipes. */ | |
9184 | intel_crtc = to_intel_crtc(crtc); | |
7668851f | 9185 | if (intel_crtc->new_enabled) |
e2e1ed41 DV |
9186 | *prepare_pipes |= 1 << intel_crtc->pipe; |
9187 | ||
b6c5164d DV |
9188 | /* |
9189 | * For simplicity do a full modeset on any pipe where the output routing | |
9190 | * changed. We could be more clever, but that would require us to be | |
9191 | * more careful with calling the relevant encoder->mode_set functions. | |
9192 | */ | |
e2e1ed41 DV |
9193 | if (*prepare_pipes) |
9194 | *modeset_pipes = *prepare_pipes; | |
9195 | ||
9196 | /* ... and mask these out. */ | |
9197 | *modeset_pipes &= ~(*disable_pipes); | |
9198 | *prepare_pipes &= ~(*disable_pipes); | |
b6c5164d DV |
9199 | |
9200 | /* | |
9201 | * HACK: We don't (yet) fully support global modesets. intel_set_config | |
9202 | * obies this rule, but the modeset restore mode of | |
9203 | * intel_modeset_setup_hw_state does not. | |
9204 | */ | |
9205 | *modeset_pipes &= 1 << intel_crtc->pipe; | |
9206 | *prepare_pipes &= 1 << intel_crtc->pipe; | |
e3641d3f DV |
9207 | |
9208 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", | |
9209 | *modeset_pipes, *prepare_pipes, *disable_pipes); | |
47f1c6c9 | 9210 | } |
79e53945 | 9211 | |
ea9d758d | 9212 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
f6e5b160 | 9213 | { |
ea9d758d | 9214 | struct drm_encoder *encoder; |
f6e5b160 | 9215 | struct drm_device *dev = crtc->dev; |
f6e5b160 | 9216 | |
ea9d758d DV |
9217 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
9218 | if (encoder->crtc == crtc) | |
9219 | return true; | |
9220 | ||
9221 | return false; | |
9222 | } | |
9223 | ||
9224 | static void | |
9225 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) | |
9226 | { | |
9227 | struct intel_encoder *intel_encoder; | |
9228 | struct intel_crtc *intel_crtc; | |
9229 | struct drm_connector *connector; | |
9230 | ||
9231 | list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list, | |
9232 | base.head) { | |
9233 | if (!intel_encoder->base.crtc) | |
9234 | continue; | |
9235 | ||
9236 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
9237 | ||
9238 | if (prepare_pipes & (1 << intel_crtc->pipe)) | |
9239 | intel_encoder->connectors_active = false; | |
9240 | } | |
9241 | ||
9242 | intel_modeset_commit_output_state(dev); | |
9243 | ||
7668851f | 9244 | /* Double check state. */ |
ea9d758d DV |
9245 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
9246 | base.head) { | |
7668851f | 9247 | WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base)); |
7bd0a8e7 VS |
9248 | WARN_ON(intel_crtc->new_config && |
9249 | intel_crtc->new_config != &intel_crtc->config); | |
9250 | WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config); | |
ea9d758d DV |
9251 | } |
9252 | ||
9253 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
9254 | if (!connector->encoder || !connector->encoder->crtc) | |
9255 | continue; | |
9256 | ||
9257 | intel_crtc = to_intel_crtc(connector->encoder->crtc); | |
9258 | ||
9259 | if (prepare_pipes & (1 << intel_crtc->pipe)) { | |
68d34720 DV |
9260 | struct drm_property *dpms_property = |
9261 | dev->mode_config.dpms_property; | |
9262 | ||
ea9d758d | 9263 | connector->dpms = DRM_MODE_DPMS_ON; |
662595df | 9264 | drm_object_property_set_value(&connector->base, |
68d34720 DV |
9265 | dpms_property, |
9266 | DRM_MODE_DPMS_ON); | |
ea9d758d DV |
9267 | |
9268 | intel_encoder = to_intel_encoder(connector->encoder); | |
9269 | intel_encoder->connectors_active = true; | |
9270 | } | |
9271 | } | |
9272 | ||
9273 | } | |
9274 | ||
3bd26263 | 9275 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 9276 | { |
3bd26263 | 9277 | int diff; |
f1f644dc JB |
9278 | |
9279 | if (clock1 == clock2) | |
9280 | return true; | |
9281 | ||
9282 | if (!clock1 || !clock2) | |
9283 | return false; | |
9284 | ||
9285 | diff = abs(clock1 - clock2); | |
9286 | ||
9287 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
9288 | return true; | |
9289 | ||
9290 | return false; | |
9291 | } | |
9292 | ||
25c5b266 DV |
9293 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
9294 | list_for_each_entry((intel_crtc), \ | |
9295 | &(dev)->mode_config.crtc_list, \ | |
9296 | base.head) \ | |
0973f18f | 9297 | if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 9298 | |
0e8ffe1b | 9299 | static bool |
2fa2fe9a DV |
9300 | intel_pipe_config_compare(struct drm_device *dev, |
9301 | struct intel_crtc_config *current_config, | |
0e8ffe1b DV |
9302 | struct intel_crtc_config *pipe_config) |
9303 | { | |
66e985c0 DV |
9304 | #define PIPE_CONF_CHECK_X(name) \ |
9305 | if (current_config->name != pipe_config->name) { \ | |
9306 | DRM_ERROR("mismatch in " #name " " \ | |
9307 | "(expected 0x%08x, found 0x%08x)\n", \ | |
9308 | current_config->name, \ | |
9309 | pipe_config->name); \ | |
9310 | return false; \ | |
9311 | } | |
9312 | ||
08a24034 DV |
9313 | #define PIPE_CONF_CHECK_I(name) \ |
9314 | if (current_config->name != pipe_config->name) { \ | |
9315 | DRM_ERROR("mismatch in " #name " " \ | |
9316 | "(expected %i, found %i)\n", \ | |
9317 | current_config->name, \ | |
9318 | pipe_config->name); \ | |
9319 | return false; \ | |
88adfff1 DV |
9320 | } |
9321 | ||
1bd1bd80 DV |
9322 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
9323 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
6f02488e | 9324 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
9325 | "(expected %i, found %i)\n", \ |
9326 | current_config->name & (mask), \ | |
9327 | pipe_config->name & (mask)); \ | |
9328 | return false; \ | |
9329 | } | |
9330 | ||
5e550656 VS |
9331 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
9332 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
9333 | DRM_ERROR("mismatch in " #name " " \ | |
9334 | "(expected %i, found %i)\n", \ | |
9335 | current_config->name, \ | |
9336 | pipe_config->name); \ | |
9337 | return false; \ | |
9338 | } | |
9339 | ||
bb760063 DV |
9340 | #define PIPE_CONF_QUIRK(quirk) \ |
9341 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
9342 | ||
eccb140b DV |
9343 | PIPE_CONF_CHECK_I(cpu_transcoder); |
9344 | ||
08a24034 DV |
9345 | PIPE_CONF_CHECK_I(has_pch_encoder); |
9346 | PIPE_CONF_CHECK_I(fdi_lanes); | |
72419203 DV |
9347 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
9348 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); | |
9349 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); | |
9350 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); | |
9351 | PIPE_CONF_CHECK_I(fdi_m_n.tu); | |
08a24034 | 9352 | |
eb14cb74 VS |
9353 | PIPE_CONF_CHECK_I(has_dp_encoder); |
9354 | PIPE_CONF_CHECK_I(dp_m_n.gmch_m); | |
9355 | PIPE_CONF_CHECK_I(dp_m_n.gmch_n); | |
9356 | PIPE_CONF_CHECK_I(dp_m_n.link_m); | |
9357 | PIPE_CONF_CHECK_I(dp_m_n.link_n); | |
9358 | PIPE_CONF_CHECK_I(dp_m_n.tu); | |
9359 | ||
1bd1bd80 DV |
9360 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay); |
9361 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal); | |
9362 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start); | |
9363 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end); | |
9364 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start); | |
9365 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end); | |
9366 | ||
9367 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay); | |
9368 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal); | |
9369 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start); | |
9370 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end); | |
9371 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start); | |
9372 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end); | |
9373 | ||
c93f54cf | 9374 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6c49f241 | 9375 | |
1bd1bd80 DV |
9376 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
9377 | DRM_MODE_FLAG_INTERLACE); | |
9378 | ||
bb760063 DV |
9379 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
9380 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
9381 | DRM_MODE_FLAG_PHSYNC); | |
9382 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
9383 | DRM_MODE_FLAG_NHSYNC); | |
9384 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
9385 | DRM_MODE_FLAG_PVSYNC); | |
9386 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
9387 | DRM_MODE_FLAG_NVSYNC); | |
9388 | } | |
045ac3b5 | 9389 | |
37327abd VS |
9390 | PIPE_CONF_CHECK_I(pipe_src_w); |
9391 | PIPE_CONF_CHECK_I(pipe_src_h); | |
1bd1bd80 | 9392 | |
2fa2fe9a DV |
9393 | PIPE_CONF_CHECK_I(gmch_pfit.control); |
9394 | /* pfit ratios are autocomputed by the hw on gen4+ */ | |
9395 | if (INTEL_INFO(dev)->gen < 4) | |
9396 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
9397 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); | |
fd4daa9c CW |
9398 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
9399 | if (current_config->pch_pfit.enabled) { | |
9400 | PIPE_CONF_CHECK_I(pch_pfit.pos); | |
9401 | PIPE_CONF_CHECK_I(pch_pfit.size); | |
9402 | } | |
2fa2fe9a | 9403 | |
e59150dc JB |
9404 | /* BDW+ don't expose a synchronous way to read the state */ |
9405 | if (IS_HASWELL(dev)) | |
9406 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 9407 | |
282740f7 VS |
9408 | PIPE_CONF_CHECK_I(double_wide); |
9409 | ||
c0d43d62 | 9410 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 9411 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 9412 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
9413 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
9414 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
c0d43d62 | 9415 | |
42571aef VS |
9416 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
9417 | PIPE_CONF_CHECK_I(pipe_bpp); | |
9418 | ||
a9a7e98a JB |
9419 | PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock); |
9420 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); | |
5e550656 | 9421 | |
66e985c0 | 9422 | #undef PIPE_CONF_CHECK_X |
08a24034 | 9423 | #undef PIPE_CONF_CHECK_I |
1bd1bd80 | 9424 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 9425 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 9426 | #undef PIPE_CONF_QUIRK |
88adfff1 | 9427 | |
0e8ffe1b DV |
9428 | return true; |
9429 | } | |
9430 | ||
91d1b4bd DV |
9431 | static void |
9432 | check_connector_state(struct drm_device *dev) | |
8af6cf88 | 9433 | { |
8af6cf88 DV |
9434 | struct intel_connector *connector; |
9435 | ||
9436 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
9437 | base.head) { | |
9438 | /* This also checks the encoder/connector hw state with the | |
9439 | * ->get_hw_state callbacks. */ | |
9440 | intel_connector_check_state(connector); | |
9441 | ||
9442 | WARN(&connector->new_encoder->base != connector->base.encoder, | |
9443 | "connector's staged encoder doesn't match current encoder\n"); | |
9444 | } | |
91d1b4bd DV |
9445 | } |
9446 | ||
9447 | static void | |
9448 | check_encoder_state(struct drm_device *dev) | |
9449 | { | |
9450 | struct intel_encoder *encoder; | |
9451 | struct intel_connector *connector; | |
8af6cf88 DV |
9452 | |
9453 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
9454 | base.head) { | |
9455 | bool enabled = false; | |
9456 | bool active = false; | |
9457 | enum pipe pipe, tracked_pipe; | |
9458 | ||
9459 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
9460 | encoder->base.base.id, | |
9461 | drm_get_encoder_name(&encoder->base)); | |
9462 | ||
9463 | WARN(&encoder->new_crtc->base != encoder->base.crtc, | |
9464 | "encoder's stage crtc doesn't match current crtc\n"); | |
9465 | WARN(encoder->connectors_active && !encoder->base.crtc, | |
9466 | "encoder's active_connectors set, but no crtc\n"); | |
9467 | ||
9468 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
9469 | base.head) { | |
9470 | if (connector->base.encoder != &encoder->base) | |
9471 | continue; | |
9472 | enabled = true; | |
9473 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) | |
9474 | active = true; | |
9475 | } | |
9476 | WARN(!!encoder->base.crtc != enabled, | |
9477 | "encoder's enabled state mismatch " | |
9478 | "(expected %i, found %i)\n", | |
9479 | !!encoder->base.crtc, enabled); | |
9480 | WARN(active && !encoder->base.crtc, | |
9481 | "active encoder with no crtc\n"); | |
9482 | ||
9483 | WARN(encoder->connectors_active != active, | |
9484 | "encoder's computed active state doesn't match tracked active state " | |
9485 | "(expected %i, found %i)\n", active, encoder->connectors_active); | |
9486 | ||
9487 | active = encoder->get_hw_state(encoder, &pipe); | |
9488 | WARN(active != encoder->connectors_active, | |
9489 | "encoder's hw state doesn't match sw tracking " | |
9490 | "(expected %i, found %i)\n", | |
9491 | encoder->connectors_active, active); | |
9492 | ||
9493 | if (!encoder->base.crtc) | |
9494 | continue; | |
9495 | ||
9496 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
9497 | WARN(active && pipe != tracked_pipe, | |
9498 | "active encoder's pipe doesn't match" | |
9499 | "(expected %i, found %i)\n", | |
9500 | tracked_pipe, pipe); | |
9501 | ||
9502 | } | |
91d1b4bd DV |
9503 | } |
9504 | ||
9505 | static void | |
9506 | check_crtc_state(struct drm_device *dev) | |
9507 | { | |
9508 | drm_i915_private_t *dev_priv = dev->dev_private; | |
9509 | struct intel_crtc *crtc; | |
9510 | struct intel_encoder *encoder; | |
9511 | struct intel_crtc_config pipe_config; | |
8af6cf88 DV |
9512 | |
9513 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
9514 | base.head) { | |
9515 | bool enabled = false; | |
9516 | bool active = false; | |
9517 | ||
045ac3b5 JB |
9518 | memset(&pipe_config, 0, sizeof(pipe_config)); |
9519 | ||
8af6cf88 DV |
9520 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
9521 | crtc->base.base.id); | |
9522 | ||
9523 | WARN(crtc->active && !crtc->base.enabled, | |
9524 | "active crtc, but not enabled in sw tracking\n"); | |
9525 | ||
9526 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
9527 | base.head) { | |
9528 | if (encoder->base.crtc != &crtc->base) | |
9529 | continue; | |
9530 | enabled = true; | |
9531 | if (encoder->connectors_active) | |
9532 | active = true; | |
9533 | } | |
6c49f241 | 9534 | |
8af6cf88 DV |
9535 | WARN(active != crtc->active, |
9536 | "crtc's computed active state doesn't match tracked active state " | |
9537 | "(expected %i, found %i)\n", active, crtc->active); | |
9538 | WARN(enabled != crtc->base.enabled, | |
9539 | "crtc's computed enabled state doesn't match tracked enabled state " | |
9540 | "(expected %i, found %i)\n", enabled, crtc->base.enabled); | |
9541 | ||
0e8ffe1b DV |
9542 | active = dev_priv->display.get_pipe_config(crtc, |
9543 | &pipe_config); | |
d62cf62a DV |
9544 | |
9545 | /* hw state is inconsistent with the pipe A quirk */ | |
9546 | if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
9547 | active = crtc->active; | |
9548 | ||
6c49f241 DV |
9549 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9550 | base.head) { | |
3eaba51c | 9551 | enum pipe pipe; |
6c49f241 DV |
9552 | if (encoder->base.crtc != &crtc->base) |
9553 | continue; | |
1d37b689 | 9554 | if (encoder->get_hw_state(encoder, &pipe)) |
6c49f241 DV |
9555 | encoder->get_config(encoder, &pipe_config); |
9556 | } | |
9557 | ||
0e8ffe1b DV |
9558 | WARN(crtc->active != active, |
9559 | "crtc active state doesn't match with hw state " | |
9560 | "(expected %i, found %i)\n", crtc->active, active); | |
9561 | ||
c0b03411 DV |
9562 | if (active && |
9563 | !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) { | |
9564 | WARN(1, "pipe state doesn't match!\n"); | |
9565 | intel_dump_pipe_config(crtc, &pipe_config, | |
9566 | "[hw state]"); | |
9567 | intel_dump_pipe_config(crtc, &crtc->config, | |
9568 | "[sw state]"); | |
9569 | } | |
8af6cf88 DV |
9570 | } |
9571 | } | |
9572 | ||
91d1b4bd DV |
9573 | static void |
9574 | check_shared_dpll_state(struct drm_device *dev) | |
9575 | { | |
9576 | drm_i915_private_t *dev_priv = dev->dev_private; | |
9577 | struct intel_crtc *crtc; | |
9578 | struct intel_dpll_hw_state dpll_hw_state; | |
9579 | int i; | |
5358901f DV |
9580 | |
9581 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
9582 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
9583 | int enabled_crtcs = 0, active_crtcs = 0; | |
9584 | bool active; | |
9585 | ||
9586 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
9587 | ||
9588 | DRM_DEBUG_KMS("%s\n", pll->name); | |
9589 | ||
9590 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
9591 | ||
9592 | WARN(pll->active > pll->refcount, | |
9593 | "more active pll users than references: %i vs %i\n", | |
9594 | pll->active, pll->refcount); | |
9595 | WARN(pll->active && !pll->on, | |
9596 | "pll in active use but not on in sw tracking\n"); | |
35c95375 DV |
9597 | WARN(pll->on && !pll->active, |
9598 | "pll in on but not on in use in sw tracking\n"); | |
5358901f DV |
9599 | WARN(pll->on != active, |
9600 | "pll on state mismatch (expected %i, found %i)\n", | |
9601 | pll->on, active); | |
9602 | ||
9603 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
9604 | base.head) { | |
9605 | if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll) | |
9606 | enabled_crtcs++; | |
9607 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
9608 | active_crtcs++; | |
9609 | } | |
9610 | WARN(pll->active != active_crtcs, | |
9611 | "pll active crtcs mismatch (expected %i, found %i)\n", | |
9612 | pll->active, active_crtcs); | |
9613 | WARN(pll->refcount != enabled_crtcs, | |
9614 | "pll enabled crtcs mismatch (expected %i, found %i)\n", | |
9615 | pll->refcount, enabled_crtcs); | |
66e985c0 DV |
9616 | |
9617 | WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state, | |
9618 | sizeof(dpll_hw_state)), | |
9619 | "pll hw state mismatch\n"); | |
5358901f | 9620 | } |
8af6cf88 DV |
9621 | } |
9622 | ||
91d1b4bd DV |
9623 | void |
9624 | intel_modeset_check_state(struct drm_device *dev) | |
9625 | { | |
9626 | check_connector_state(dev); | |
9627 | check_encoder_state(dev); | |
9628 | check_crtc_state(dev); | |
9629 | check_shared_dpll_state(dev); | |
9630 | } | |
9631 | ||
18442d08 VS |
9632 | void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, |
9633 | int dotclock) | |
9634 | { | |
9635 | /* | |
9636 | * FDI already provided one idea for the dotclock. | |
9637 | * Yell if the encoder disagrees. | |
9638 | */ | |
241bfc38 | 9639 | WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock), |
18442d08 | 9640 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
241bfc38 | 9641 | pipe_config->adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
9642 | } |
9643 | ||
f30da187 DV |
9644 | static int __intel_set_mode(struct drm_crtc *crtc, |
9645 | struct drm_display_mode *mode, | |
9646 | int x, int y, struct drm_framebuffer *fb) | |
a6778b3c DV |
9647 | { |
9648 | struct drm_device *dev = crtc->dev; | |
dbf2b54e | 9649 | drm_i915_private_t *dev_priv = dev->dev_private; |
4b4b9238 | 9650 | struct drm_display_mode *saved_mode; |
b8cecdf5 | 9651 | struct intel_crtc_config *pipe_config = NULL; |
25c5b266 DV |
9652 | struct intel_crtc *intel_crtc; |
9653 | unsigned disable_pipes, prepare_pipes, modeset_pipes; | |
c0c36b94 | 9654 | int ret = 0; |
a6778b3c | 9655 | |
4b4b9238 | 9656 | saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL); |
c0c36b94 CW |
9657 | if (!saved_mode) |
9658 | return -ENOMEM; | |
a6778b3c | 9659 | |
e2e1ed41 | 9660 | intel_modeset_affected_pipes(crtc, &modeset_pipes, |
25c5b266 DV |
9661 | &prepare_pipes, &disable_pipes); |
9662 | ||
3ac18232 | 9663 | *saved_mode = crtc->mode; |
a6778b3c | 9664 | |
25c5b266 DV |
9665 | /* Hack: Because we don't (yet) support global modeset on multiple |
9666 | * crtcs, we don't keep track of the new mode for more than one crtc. | |
9667 | * Hence simply check whether any bit is set in modeset_pipes in all the | |
9668 | * pieces of code that are not yet converted to deal with mutliple crtcs | |
9669 | * changing their mode at the same time. */ | |
25c5b266 | 9670 | if (modeset_pipes) { |
4e53c2e0 | 9671 | pipe_config = intel_modeset_pipe_config(crtc, fb, mode); |
b8cecdf5 DV |
9672 | if (IS_ERR(pipe_config)) { |
9673 | ret = PTR_ERR(pipe_config); | |
9674 | pipe_config = NULL; | |
9675 | ||
3ac18232 | 9676 | goto out; |
25c5b266 | 9677 | } |
c0b03411 DV |
9678 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
9679 | "[modeset]"); | |
50741abc | 9680 | to_intel_crtc(crtc)->new_config = pipe_config; |
25c5b266 | 9681 | } |
a6778b3c | 9682 | |
30a970c6 JB |
9683 | /* |
9684 | * See if the config requires any additional preparation, e.g. | |
9685 | * to adjust global state with pipes off. We need to do this | |
9686 | * here so we can get the modeset_pipe updated config for the new | |
9687 | * mode set on this crtc. For other crtcs we need to use the | |
9688 | * adjusted_mode bits in the crtc directly. | |
9689 | */ | |
c164f833 | 9690 | if (IS_VALLEYVIEW(dev)) { |
2f2d7aa1 | 9691 | valleyview_modeset_global_pipes(dev, &prepare_pipes); |
30a970c6 | 9692 | |
c164f833 VS |
9693 | /* may have added more to prepare_pipes than we should */ |
9694 | prepare_pipes &= ~disable_pipes; | |
9695 | } | |
9696 | ||
460da916 DV |
9697 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
9698 | intel_crtc_disable(&intel_crtc->base); | |
9699 | ||
ea9d758d DV |
9700 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
9701 | if (intel_crtc->base.enabled) | |
9702 | dev_priv->display.crtc_disable(&intel_crtc->base); | |
9703 | } | |
a6778b3c | 9704 | |
6c4c86f5 DV |
9705 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
9706 | * to set it here already despite that we pass it down the callchain. | |
f6e5b160 | 9707 | */ |
b8cecdf5 | 9708 | if (modeset_pipes) { |
25c5b266 | 9709 | crtc->mode = *mode; |
b8cecdf5 DV |
9710 | /* mode_set/enable/disable functions rely on a correct pipe |
9711 | * config. */ | |
9712 | to_intel_crtc(crtc)->config = *pipe_config; | |
50741abc | 9713 | to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config; |
c326c0a9 VS |
9714 | |
9715 | /* | |
9716 | * Calculate and store various constants which | |
9717 | * are later needed by vblank and swap-completion | |
9718 | * timestamping. They are derived from true hwmode. | |
9719 | */ | |
9720 | drm_calc_timestamping_constants(crtc, | |
9721 | &pipe_config->adjusted_mode); | |
b8cecdf5 | 9722 | } |
7758a113 | 9723 | |
ea9d758d DV |
9724 | /* Only after disabling all output pipelines that will be changed can we |
9725 | * update the the output configuration. */ | |
9726 | intel_modeset_update_state(dev, prepare_pipes); | |
f6e5b160 | 9727 | |
47fab737 DV |
9728 | if (dev_priv->display.modeset_global_resources) |
9729 | dev_priv->display.modeset_global_resources(dev); | |
9730 | ||
a6778b3c DV |
9731 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
9732 | * on the DPLL. | |
f6e5b160 | 9733 | */ |
25c5b266 | 9734 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
c0c36b94 | 9735 | ret = intel_crtc_mode_set(&intel_crtc->base, |
c0c36b94 CW |
9736 | x, y, fb); |
9737 | if (ret) | |
9738 | goto done; | |
a6778b3c DV |
9739 | } |
9740 | ||
9741 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ | |
25c5b266 DV |
9742 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) |
9743 | dev_priv->display.crtc_enable(&intel_crtc->base); | |
a6778b3c | 9744 | |
a6778b3c DV |
9745 | /* FIXME: add subpixel order */ |
9746 | done: | |
4b4b9238 | 9747 | if (ret && crtc->enabled) |
3ac18232 | 9748 | crtc->mode = *saved_mode; |
a6778b3c | 9749 | |
3ac18232 | 9750 | out: |
b8cecdf5 | 9751 | kfree(pipe_config); |
3ac18232 | 9752 | kfree(saved_mode); |
a6778b3c | 9753 | return ret; |
f6e5b160 CW |
9754 | } |
9755 | ||
e7457a9a DL |
9756 | static int intel_set_mode(struct drm_crtc *crtc, |
9757 | struct drm_display_mode *mode, | |
9758 | int x, int y, struct drm_framebuffer *fb) | |
f30da187 DV |
9759 | { |
9760 | int ret; | |
9761 | ||
9762 | ret = __intel_set_mode(crtc, mode, x, y, fb); | |
9763 | ||
9764 | if (ret == 0) | |
9765 | intel_modeset_check_state(crtc->dev); | |
9766 | ||
9767 | return ret; | |
9768 | } | |
9769 | ||
c0c36b94 CW |
9770 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
9771 | { | |
9772 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb); | |
9773 | } | |
9774 | ||
25c5b266 DV |
9775 | #undef for_each_intel_crtc_masked |
9776 | ||
d9e55608 DV |
9777 | static void intel_set_config_free(struct intel_set_config *config) |
9778 | { | |
9779 | if (!config) | |
9780 | return; | |
9781 | ||
1aa4b628 DV |
9782 | kfree(config->save_connector_encoders); |
9783 | kfree(config->save_encoder_crtcs); | |
7668851f | 9784 | kfree(config->save_crtc_enabled); |
d9e55608 DV |
9785 | kfree(config); |
9786 | } | |
9787 | ||
85f9eb71 DV |
9788 | static int intel_set_config_save_state(struct drm_device *dev, |
9789 | struct intel_set_config *config) | |
9790 | { | |
7668851f | 9791 | struct drm_crtc *crtc; |
85f9eb71 DV |
9792 | struct drm_encoder *encoder; |
9793 | struct drm_connector *connector; | |
9794 | int count; | |
9795 | ||
7668851f VS |
9796 | config->save_crtc_enabled = |
9797 | kcalloc(dev->mode_config.num_crtc, | |
9798 | sizeof(bool), GFP_KERNEL); | |
9799 | if (!config->save_crtc_enabled) | |
9800 | return -ENOMEM; | |
9801 | ||
1aa4b628 DV |
9802 | config->save_encoder_crtcs = |
9803 | kcalloc(dev->mode_config.num_encoder, | |
9804 | sizeof(struct drm_crtc *), GFP_KERNEL); | |
9805 | if (!config->save_encoder_crtcs) | |
85f9eb71 DV |
9806 | return -ENOMEM; |
9807 | ||
1aa4b628 DV |
9808 | config->save_connector_encoders = |
9809 | kcalloc(dev->mode_config.num_connector, | |
9810 | sizeof(struct drm_encoder *), GFP_KERNEL); | |
9811 | if (!config->save_connector_encoders) | |
85f9eb71 DV |
9812 | return -ENOMEM; |
9813 | ||
9814 | /* Copy data. Note that driver private data is not affected. | |
9815 | * Should anything bad happen only the expected state is | |
9816 | * restored, not the drivers personal bookkeeping. | |
9817 | */ | |
7668851f VS |
9818 | count = 0; |
9819 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
9820 | config->save_crtc_enabled[count++] = crtc->enabled; | |
9821 | } | |
9822 | ||
85f9eb71 DV |
9823 | count = 0; |
9824 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1aa4b628 | 9825 | config->save_encoder_crtcs[count++] = encoder->crtc; |
85f9eb71 DV |
9826 | } |
9827 | ||
9828 | count = 0; | |
9829 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1aa4b628 | 9830 | config->save_connector_encoders[count++] = connector->encoder; |
85f9eb71 DV |
9831 | } |
9832 | ||
9833 | return 0; | |
9834 | } | |
9835 | ||
9836 | static void intel_set_config_restore_state(struct drm_device *dev, | |
9837 | struct intel_set_config *config) | |
9838 | { | |
7668851f | 9839 | struct intel_crtc *crtc; |
9a935856 DV |
9840 | struct intel_encoder *encoder; |
9841 | struct intel_connector *connector; | |
85f9eb71 DV |
9842 | int count; |
9843 | ||
7668851f VS |
9844 | count = 0; |
9845 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
9846 | crtc->new_enabled = config->save_crtc_enabled[count++]; | |
7bd0a8e7 VS |
9847 | |
9848 | if (crtc->new_enabled) | |
9849 | crtc->new_config = &crtc->config; | |
9850 | else | |
9851 | crtc->new_config = NULL; | |
7668851f VS |
9852 | } |
9853 | ||
85f9eb71 | 9854 | count = 0; |
9a935856 DV |
9855 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
9856 | encoder->new_crtc = | |
9857 | to_intel_crtc(config->save_encoder_crtcs[count++]); | |
85f9eb71 DV |
9858 | } |
9859 | ||
9860 | count = 0; | |
9a935856 DV |
9861 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
9862 | connector->new_encoder = | |
9863 | to_intel_encoder(config->save_connector_encoders[count++]); | |
85f9eb71 DV |
9864 | } |
9865 | } | |
9866 | ||
e3de42b6 | 9867 | static bool |
2e57f47d | 9868 | is_crtc_connector_off(struct drm_mode_set *set) |
e3de42b6 ID |
9869 | { |
9870 | int i; | |
9871 | ||
2e57f47d CW |
9872 | if (set->num_connectors == 0) |
9873 | return false; | |
9874 | ||
9875 | if (WARN_ON(set->connectors == NULL)) | |
9876 | return false; | |
9877 | ||
9878 | for (i = 0; i < set->num_connectors; i++) | |
9879 | if (set->connectors[i]->encoder && | |
9880 | set->connectors[i]->encoder->crtc == set->crtc && | |
9881 | set->connectors[i]->dpms != DRM_MODE_DPMS_ON) | |
e3de42b6 ID |
9882 | return true; |
9883 | ||
9884 | return false; | |
9885 | } | |
9886 | ||
5e2b584e DV |
9887 | static void |
9888 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, | |
9889 | struct intel_set_config *config) | |
9890 | { | |
9891 | ||
9892 | /* We should be able to check here if the fb has the same properties | |
9893 | * and then just flip_or_move it */ | |
2e57f47d CW |
9894 | if (is_crtc_connector_off(set)) { |
9895 | config->mode_changed = true; | |
e3de42b6 | 9896 | } else if (set->crtc->fb != set->fb) { |
5e2b584e DV |
9897 | /* If we have no fb then treat it as a full mode set */ |
9898 | if (set->crtc->fb == NULL) { | |
319d9827 JB |
9899 | struct intel_crtc *intel_crtc = |
9900 | to_intel_crtc(set->crtc); | |
9901 | ||
d330a953 | 9902 | if (intel_crtc->active && i915.fastboot) { |
319d9827 JB |
9903 | DRM_DEBUG_KMS("crtc has no fb, will flip\n"); |
9904 | config->fb_changed = true; | |
9905 | } else { | |
9906 | DRM_DEBUG_KMS("inactive crtc, full mode set\n"); | |
9907 | config->mode_changed = true; | |
9908 | } | |
5e2b584e DV |
9909 | } else if (set->fb == NULL) { |
9910 | config->mode_changed = true; | |
72f4901e DV |
9911 | } else if (set->fb->pixel_format != |
9912 | set->crtc->fb->pixel_format) { | |
5e2b584e | 9913 | config->mode_changed = true; |
e3de42b6 | 9914 | } else { |
5e2b584e | 9915 | config->fb_changed = true; |
e3de42b6 | 9916 | } |
5e2b584e DV |
9917 | } |
9918 | ||
835c5873 | 9919 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
5e2b584e DV |
9920 | config->fb_changed = true; |
9921 | ||
9922 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { | |
9923 | DRM_DEBUG_KMS("modes are different, full mode set\n"); | |
9924 | drm_mode_debug_printmodeline(&set->crtc->mode); | |
9925 | drm_mode_debug_printmodeline(set->mode); | |
9926 | config->mode_changed = true; | |
9927 | } | |
a1d95703 CW |
9928 | |
9929 | DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n", | |
9930 | set->crtc->base.id, config->mode_changed, config->fb_changed); | |
5e2b584e DV |
9931 | } |
9932 | ||
2e431051 | 9933 | static int |
9a935856 DV |
9934 | intel_modeset_stage_output_state(struct drm_device *dev, |
9935 | struct drm_mode_set *set, | |
9936 | struct intel_set_config *config) | |
50f56119 | 9937 | { |
9a935856 DV |
9938 | struct intel_connector *connector; |
9939 | struct intel_encoder *encoder; | |
7668851f | 9940 | struct intel_crtc *crtc; |
f3f08572 | 9941 | int ro; |
50f56119 | 9942 | |
9abdda74 | 9943 | /* The upper layers ensure that we either disable a crtc or have a list |
9a935856 DV |
9944 | * of connectors. For paranoia, double-check this. */ |
9945 | WARN_ON(!set->fb && (set->num_connectors != 0)); | |
9946 | WARN_ON(set->fb && (set->num_connectors == 0)); | |
9947 | ||
9a935856 DV |
9948 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9949 | base.head) { | |
9950 | /* Otherwise traverse passed in connector list and get encoders | |
9951 | * for them. */ | |
50f56119 | 9952 | for (ro = 0; ro < set->num_connectors; ro++) { |
9a935856 DV |
9953 | if (set->connectors[ro] == &connector->base) { |
9954 | connector->new_encoder = connector->encoder; | |
50f56119 DV |
9955 | break; |
9956 | } | |
9957 | } | |
9958 | ||
9a935856 DV |
9959 | /* If we disable the crtc, disable all its connectors. Also, if |
9960 | * the connector is on the changing crtc but not on the new | |
9961 | * connector list, disable it. */ | |
9962 | if ((!set->fb || ro == set->num_connectors) && | |
9963 | connector->base.encoder && | |
9964 | connector->base.encoder->crtc == set->crtc) { | |
9965 | connector->new_encoder = NULL; | |
9966 | ||
9967 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", | |
9968 | connector->base.base.id, | |
9969 | drm_get_connector_name(&connector->base)); | |
9970 | } | |
9971 | ||
9972 | ||
9973 | if (&connector->new_encoder->base != connector->base.encoder) { | |
50f56119 | 9974 | DRM_DEBUG_KMS("encoder changed, full mode switch\n"); |
5e2b584e | 9975 | config->mode_changed = true; |
50f56119 DV |
9976 | } |
9977 | } | |
9a935856 | 9978 | /* connector->new_encoder is now updated for all connectors. */ |
50f56119 | 9979 | |
9a935856 | 9980 | /* Update crtc of enabled connectors. */ |
9a935856 DV |
9981 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9982 | base.head) { | |
7668851f VS |
9983 | struct drm_crtc *new_crtc; |
9984 | ||
9a935856 | 9985 | if (!connector->new_encoder) |
50f56119 DV |
9986 | continue; |
9987 | ||
9a935856 | 9988 | new_crtc = connector->new_encoder->base.crtc; |
50f56119 DV |
9989 | |
9990 | for (ro = 0; ro < set->num_connectors; ro++) { | |
9a935856 | 9991 | if (set->connectors[ro] == &connector->base) |
50f56119 DV |
9992 | new_crtc = set->crtc; |
9993 | } | |
9994 | ||
9995 | /* Make sure the new CRTC will work with the encoder */ | |
14509916 TR |
9996 | if (!drm_encoder_crtc_ok(&connector->new_encoder->base, |
9997 | new_crtc)) { | |
5e2b584e | 9998 | return -EINVAL; |
50f56119 | 9999 | } |
9a935856 DV |
10000 | connector->encoder->new_crtc = to_intel_crtc(new_crtc); |
10001 | ||
10002 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", | |
10003 | connector->base.base.id, | |
10004 | drm_get_connector_name(&connector->base), | |
10005 | new_crtc->base.id); | |
10006 | } | |
10007 | ||
10008 | /* Check for any encoders that needs to be disabled. */ | |
10009 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
10010 | base.head) { | |
5a65f358 | 10011 | int num_connectors = 0; |
9a935856 DV |
10012 | list_for_each_entry(connector, |
10013 | &dev->mode_config.connector_list, | |
10014 | base.head) { | |
10015 | if (connector->new_encoder == encoder) { | |
10016 | WARN_ON(!connector->new_encoder->new_crtc); | |
5a65f358 | 10017 | num_connectors++; |
9a935856 DV |
10018 | } |
10019 | } | |
5a65f358 PZ |
10020 | |
10021 | if (num_connectors == 0) | |
10022 | encoder->new_crtc = NULL; | |
10023 | else if (num_connectors > 1) | |
10024 | return -EINVAL; | |
10025 | ||
9a935856 DV |
10026 | /* Only now check for crtc changes so we don't miss encoders |
10027 | * that will be disabled. */ | |
10028 | if (&encoder->new_crtc->base != encoder->base.crtc) { | |
50f56119 | 10029 | DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
5e2b584e | 10030 | config->mode_changed = true; |
50f56119 DV |
10031 | } |
10032 | } | |
9a935856 | 10033 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
50f56119 | 10034 | |
7668851f VS |
10035 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
10036 | base.head) { | |
10037 | crtc->new_enabled = false; | |
10038 | ||
10039 | list_for_each_entry(encoder, | |
10040 | &dev->mode_config.encoder_list, | |
10041 | base.head) { | |
10042 | if (encoder->new_crtc == crtc) { | |
10043 | crtc->new_enabled = true; | |
10044 | break; | |
10045 | } | |
10046 | } | |
10047 | ||
10048 | if (crtc->new_enabled != crtc->base.enabled) { | |
10049 | DRM_DEBUG_KMS("crtc %sabled, full mode switch\n", | |
10050 | crtc->new_enabled ? "en" : "dis"); | |
10051 | config->mode_changed = true; | |
10052 | } | |
7bd0a8e7 VS |
10053 | |
10054 | if (crtc->new_enabled) | |
10055 | crtc->new_config = &crtc->config; | |
10056 | else | |
10057 | crtc->new_config = NULL; | |
7668851f VS |
10058 | } |
10059 | ||
2e431051 DV |
10060 | return 0; |
10061 | } | |
10062 | ||
7d00a1f5 VS |
10063 | static void disable_crtc_nofb(struct intel_crtc *crtc) |
10064 | { | |
10065 | struct drm_device *dev = crtc->base.dev; | |
10066 | struct intel_encoder *encoder; | |
10067 | struct intel_connector *connector; | |
10068 | ||
10069 | DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n", | |
10070 | pipe_name(crtc->pipe)); | |
10071 | ||
10072 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { | |
10073 | if (connector->new_encoder && | |
10074 | connector->new_encoder->new_crtc == crtc) | |
10075 | connector->new_encoder = NULL; | |
10076 | } | |
10077 | ||
10078 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { | |
10079 | if (encoder->new_crtc == crtc) | |
10080 | encoder->new_crtc = NULL; | |
10081 | } | |
10082 | ||
10083 | crtc->new_enabled = false; | |
7bd0a8e7 | 10084 | crtc->new_config = NULL; |
7d00a1f5 VS |
10085 | } |
10086 | ||
2e431051 DV |
10087 | static int intel_crtc_set_config(struct drm_mode_set *set) |
10088 | { | |
10089 | struct drm_device *dev; | |
2e431051 DV |
10090 | struct drm_mode_set save_set; |
10091 | struct intel_set_config *config; | |
10092 | int ret; | |
2e431051 | 10093 | |
8d3e375e DV |
10094 | BUG_ON(!set); |
10095 | BUG_ON(!set->crtc); | |
10096 | BUG_ON(!set->crtc->helper_private); | |
2e431051 | 10097 | |
7e53f3a4 DV |
10098 | /* Enforce sane interface api - has been abused by the fb helper. */ |
10099 | BUG_ON(!set->mode && set->fb); | |
10100 | BUG_ON(set->fb && set->num_connectors == 0); | |
431e50f7 | 10101 | |
2e431051 DV |
10102 | if (set->fb) { |
10103 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", | |
10104 | set->crtc->base.id, set->fb->base.id, | |
10105 | (int)set->num_connectors, set->x, set->y); | |
10106 | } else { | |
10107 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); | |
2e431051 DV |
10108 | } |
10109 | ||
10110 | dev = set->crtc->dev; | |
10111 | ||
10112 | ret = -ENOMEM; | |
10113 | config = kzalloc(sizeof(*config), GFP_KERNEL); | |
10114 | if (!config) | |
10115 | goto out_config; | |
10116 | ||
10117 | ret = intel_set_config_save_state(dev, config); | |
10118 | if (ret) | |
10119 | goto out_config; | |
10120 | ||
10121 | save_set.crtc = set->crtc; | |
10122 | save_set.mode = &set->crtc->mode; | |
10123 | save_set.x = set->crtc->x; | |
10124 | save_set.y = set->crtc->y; | |
10125 | save_set.fb = set->crtc->fb; | |
10126 | ||
10127 | /* Compute whether we need a full modeset, only an fb base update or no | |
10128 | * change at all. In the future we might also check whether only the | |
10129 | * mode changed, e.g. for LVDS where we only change the panel fitter in | |
10130 | * such cases. */ | |
10131 | intel_set_config_compute_mode_changes(set, config); | |
10132 | ||
9a935856 | 10133 | ret = intel_modeset_stage_output_state(dev, set, config); |
2e431051 DV |
10134 | if (ret) |
10135 | goto fail; | |
10136 | ||
5e2b584e | 10137 | if (config->mode_changed) { |
c0c36b94 CW |
10138 | ret = intel_set_mode(set->crtc, set->mode, |
10139 | set->x, set->y, set->fb); | |
5e2b584e | 10140 | } else if (config->fb_changed) { |
4878cae2 VS |
10141 | intel_crtc_wait_for_pending_flips(set->crtc); |
10142 | ||
4f660f49 | 10143 | ret = intel_pipe_set_base(set->crtc, |
94352cf9 | 10144 | set->x, set->y, set->fb); |
7ca51a3a JB |
10145 | /* |
10146 | * In the fastboot case this may be our only check of the | |
10147 | * state after boot. It would be better to only do it on | |
10148 | * the first update, but we don't have a nice way of doing that | |
10149 | * (and really, set_config isn't used much for high freq page | |
10150 | * flipping, so increasing its cost here shouldn't be a big | |
10151 | * deal). | |
10152 | */ | |
d330a953 | 10153 | if (i915.fastboot && ret == 0) |
7ca51a3a | 10154 | intel_modeset_check_state(set->crtc->dev); |
50f56119 DV |
10155 | } |
10156 | ||
2d05eae1 | 10157 | if (ret) { |
bf67dfeb DV |
10158 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
10159 | set->crtc->base.id, ret); | |
50f56119 | 10160 | fail: |
2d05eae1 | 10161 | intel_set_config_restore_state(dev, config); |
50f56119 | 10162 | |
7d00a1f5 VS |
10163 | /* |
10164 | * HACK: if the pipe was on, but we didn't have a framebuffer, | |
10165 | * force the pipe off to avoid oopsing in the modeset code | |
10166 | * due to fb==NULL. This should only happen during boot since | |
10167 | * we don't yet reconstruct the FB from the hardware state. | |
10168 | */ | |
10169 | if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb) | |
10170 | disable_crtc_nofb(to_intel_crtc(save_set.crtc)); | |
10171 | ||
2d05eae1 CW |
10172 | /* Try to restore the config */ |
10173 | if (config->mode_changed && | |
10174 | intel_set_mode(save_set.crtc, save_set.mode, | |
10175 | save_set.x, save_set.y, save_set.fb)) | |
10176 | DRM_ERROR("failed to restore config after modeset failure\n"); | |
10177 | } | |
50f56119 | 10178 | |
d9e55608 DV |
10179 | out_config: |
10180 | intel_set_config_free(config); | |
50f56119 DV |
10181 | return ret; |
10182 | } | |
f6e5b160 CW |
10183 | |
10184 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
f6e5b160 CW |
10185 | .cursor_set = intel_crtc_cursor_set, |
10186 | .cursor_move = intel_crtc_cursor_move, | |
10187 | .gamma_set = intel_crtc_gamma_set, | |
50f56119 | 10188 | .set_config = intel_crtc_set_config, |
f6e5b160 CW |
10189 | .destroy = intel_crtc_destroy, |
10190 | .page_flip = intel_crtc_page_flip, | |
10191 | }; | |
10192 | ||
79f689aa PZ |
10193 | static void intel_cpu_pll_init(struct drm_device *dev) |
10194 | { | |
affa9354 | 10195 | if (HAS_DDI(dev)) |
79f689aa PZ |
10196 | intel_ddi_pll_init(dev); |
10197 | } | |
10198 | ||
5358901f DV |
10199 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
10200 | struct intel_shared_dpll *pll, | |
10201 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 10202 | { |
5358901f | 10203 | uint32_t val; |
ee7b9f93 | 10204 | |
5358901f | 10205 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
10206 | hw_state->dpll = val; |
10207 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
10208 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
10209 | |
10210 | return val & DPLL_VCO_ENABLE; | |
10211 | } | |
10212 | ||
15bdd4cf DV |
10213 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
10214 | struct intel_shared_dpll *pll) | |
10215 | { | |
10216 | I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0); | |
10217 | I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1); | |
10218 | } | |
10219 | ||
e7b903d2 DV |
10220 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
10221 | struct intel_shared_dpll *pll) | |
10222 | { | |
e7b903d2 | 10223 | /* PCH refclock must be enabled first */ |
89eff4be | 10224 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 10225 | |
15bdd4cf DV |
10226 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); |
10227 | ||
10228 | /* Wait for the clocks to stabilize. */ | |
10229 | POSTING_READ(PCH_DPLL(pll->id)); | |
10230 | udelay(150); | |
10231 | ||
10232 | /* The pixel multiplier can only be updated once the | |
10233 | * DPLL is enabled and the clocks are stable. | |
10234 | * | |
10235 | * So write it again. | |
10236 | */ | |
10237 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); | |
10238 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
10239 | udelay(200); |
10240 | } | |
10241 | ||
10242 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
10243 | struct intel_shared_dpll *pll) | |
10244 | { | |
10245 | struct drm_device *dev = dev_priv->dev; | |
10246 | struct intel_crtc *crtc; | |
e7b903d2 DV |
10247 | |
10248 | /* Make sure no transcoder isn't still depending on us. */ | |
10249 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
10250 | if (intel_crtc_to_shared_dpll(crtc) == pll) | |
10251 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
10252 | } |
10253 | ||
15bdd4cf DV |
10254 | I915_WRITE(PCH_DPLL(pll->id), 0); |
10255 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
10256 | udelay(200); |
10257 | } | |
10258 | ||
46edb027 DV |
10259 | static char *ibx_pch_dpll_names[] = { |
10260 | "PCH DPLL A", | |
10261 | "PCH DPLL B", | |
10262 | }; | |
10263 | ||
7c74ade1 | 10264 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 10265 | { |
e7b903d2 | 10266 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
10267 | int i; |
10268 | ||
7c74ade1 | 10269 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 10270 | |
e72f9fbf | 10271 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
10272 | dev_priv->shared_dplls[i].id = i; |
10273 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 10274 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
10275 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
10276 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
10277 | dev_priv->shared_dplls[i].get_hw_state = |
10278 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
10279 | } |
10280 | } | |
10281 | ||
7c74ade1 DV |
10282 | static void intel_shared_dpll_init(struct drm_device *dev) |
10283 | { | |
e7b903d2 | 10284 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 DV |
10285 | |
10286 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
10287 | ibx_pch_dpll_init(dev); | |
10288 | else | |
10289 | dev_priv->num_shared_dpll = 0; | |
10290 | ||
10291 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
10292 | } |
10293 | ||
b358d0a6 | 10294 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 10295 | { |
22fd0fab | 10296 | drm_i915_private_t *dev_priv = dev->dev_private; |
79e53945 JB |
10297 | struct intel_crtc *intel_crtc; |
10298 | int i; | |
10299 | ||
955382f3 | 10300 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
10301 | if (intel_crtc == NULL) |
10302 | return; | |
10303 | ||
10304 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); | |
10305 | ||
10306 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
10307 | for (i = 0; i < 256; i++) { |
10308 | intel_crtc->lut_r[i] = i; | |
10309 | intel_crtc->lut_g[i] = i; | |
10310 | intel_crtc->lut_b[i] = i; | |
10311 | } | |
10312 | ||
1f1c2e24 VS |
10313 | /* |
10314 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
10315 | * is hooked to plane B. Hence we want plane A feeding pipe B. | |
10316 | */ | |
80824003 JB |
10317 | intel_crtc->pipe = pipe; |
10318 | intel_crtc->plane = pipe; | |
3a77c4c4 | 10319 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 10320 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 10321 | intel_crtc->plane = !pipe; |
80824003 JB |
10322 | } |
10323 | ||
22fd0fab JB |
10324 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
10325 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
10326 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
10327 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
10328 | ||
79e53945 | 10329 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
79e53945 JB |
10330 | } |
10331 | ||
752aa88a JB |
10332 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
10333 | { | |
10334 | struct drm_encoder *encoder = connector->base.encoder; | |
10335 | ||
10336 | WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex)); | |
10337 | ||
10338 | if (!encoder) | |
10339 | return INVALID_PIPE; | |
10340 | ||
10341 | return to_intel_crtc(encoder->crtc)->pipe; | |
10342 | } | |
10343 | ||
08d7b3d1 | 10344 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 10345 | struct drm_file *file) |
08d7b3d1 | 10346 | { |
08d7b3d1 | 10347 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
c05422d5 DV |
10348 | struct drm_mode_object *drmmode_obj; |
10349 | struct intel_crtc *crtc; | |
08d7b3d1 | 10350 | |
1cff8f6b DV |
10351 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
10352 | return -ENODEV; | |
08d7b3d1 | 10353 | |
c05422d5 DV |
10354 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
10355 | DRM_MODE_OBJECT_CRTC); | |
08d7b3d1 | 10356 | |
c05422d5 | 10357 | if (!drmmode_obj) { |
08d7b3d1 | 10358 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 10359 | return -ENOENT; |
08d7b3d1 CW |
10360 | } |
10361 | ||
c05422d5 DV |
10362 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
10363 | pipe_from_crtc_id->pipe = crtc->pipe; | |
08d7b3d1 | 10364 | |
c05422d5 | 10365 | return 0; |
08d7b3d1 CW |
10366 | } |
10367 | ||
66a9278e | 10368 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 10369 | { |
66a9278e DV |
10370 | struct drm_device *dev = encoder->base.dev; |
10371 | struct intel_encoder *source_encoder; | |
79e53945 | 10372 | int index_mask = 0; |
79e53945 JB |
10373 | int entry = 0; |
10374 | ||
66a9278e DV |
10375 | list_for_each_entry(source_encoder, |
10376 | &dev->mode_config.encoder_list, base.head) { | |
10377 | ||
10378 | if (encoder == source_encoder) | |
79e53945 | 10379 | index_mask |= (1 << entry); |
66a9278e DV |
10380 | |
10381 | /* Intel hw has only one MUX where enocoders could be cloned. */ | |
10382 | if (encoder->cloneable && source_encoder->cloneable) | |
10383 | index_mask |= (1 << entry); | |
10384 | ||
79e53945 JB |
10385 | entry++; |
10386 | } | |
4ef69c7a | 10387 | |
79e53945 JB |
10388 | return index_mask; |
10389 | } | |
10390 | ||
4d302442 CW |
10391 | static bool has_edp_a(struct drm_device *dev) |
10392 | { | |
10393 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10394 | ||
10395 | if (!IS_MOBILE(dev)) | |
10396 | return false; | |
10397 | ||
10398 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
10399 | return false; | |
10400 | ||
e3589908 | 10401 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
10402 | return false; |
10403 | ||
10404 | return true; | |
10405 | } | |
10406 | ||
ba0fbca4 DL |
10407 | const char *intel_output_name(int output) |
10408 | { | |
10409 | static const char *names[] = { | |
10410 | [INTEL_OUTPUT_UNUSED] = "Unused", | |
10411 | [INTEL_OUTPUT_ANALOG] = "Analog", | |
10412 | [INTEL_OUTPUT_DVO] = "DVO", | |
10413 | [INTEL_OUTPUT_SDVO] = "SDVO", | |
10414 | [INTEL_OUTPUT_LVDS] = "LVDS", | |
10415 | [INTEL_OUTPUT_TVOUT] = "TV", | |
10416 | [INTEL_OUTPUT_HDMI] = "HDMI", | |
10417 | [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort", | |
10418 | [INTEL_OUTPUT_EDP] = "eDP", | |
10419 | [INTEL_OUTPUT_DSI] = "DSI", | |
10420 | [INTEL_OUTPUT_UNKNOWN] = "Unknown", | |
10421 | }; | |
10422 | ||
10423 | if (output < 0 || output >= ARRAY_SIZE(names) || !names[output]) | |
10424 | return "Invalid"; | |
10425 | ||
10426 | return names[output]; | |
10427 | } | |
10428 | ||
79e53945 JB |
10429 | static void intel_setup_outputs(struct drm_device *dev) |
10430 | { | |
725e30ad | 10431 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 10432 | struct intel_encoder *encoder; |
cb0953d7 | 10433 | bool dpd_is_edp = false; |
79e53945 | 10434 | |
c9093354 | 10435 | intel_lvds_init(dev); |
79e53945 | 10436 | |
c40c0f5b | 10437 | if (!IS_ULT(dev)) |
79935fca | 10438 | intel_crt_init(dev); |
cb0953d7 | 10439 | |
affa9354 | 10440 | if (HAS_DDI(dev)) { |
0e72a5b5 ED |
10441 | int found; |
10442 | ||
10443 | /* Haswell uses DDI functions to detect digital outputs */ | |
10444 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; | |
10445 | /* DDI A only supports eDP */ | |
10446 | if (found) | |
10447 | intel_ddi_init(dev, PORT_A); | |
10448 | ||
10449 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
10450 | * register */ | |
10451 | found = I915_READ(SFUSE_STRAP); | |
10452 | ||
10453 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
10454 | intel_ddi_init(dev, PORT_B); | |
10455 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
10456 | intel_ddi_init(dev, PORT_C); | |
10457 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
10458 | intel_ddi_init(dev, PORT_D); | |
10459 | } else if (HAS_PCH_SPLIT(dev)) { | |
cb0953d7 | 10460 | int found; |
5d8a7752 | 10461 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
10462 | |
10463 | if (has_edp_a(dev)) | |
10464 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 10465 | |
dc0fa718 | 10466 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 10467 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 10468 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 10469 | if (!found) |
e2debe91 | 10470 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 10471 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 10472 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
10473 | } |
10474 | ||
dc0fa718 | 10475 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 10476 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 10477 | |
dc0fa718 | 10478 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 10479 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 10480 | |
5eb08b69 | 10481 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 10482 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 10483 | |
270b3042 | 10484 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 10485 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d | 10486 | } else if (IS_VALLEYVIEW(dev)) { |
585a94b8 AB |
10487 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) { |
10488 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, | |
10489 | PORT_B); | |
10490 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED) | |
10491 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); | |
10492 | } | |
10493 | ||
6f6005a5 JB |
10494 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) { |
10495 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, | |
10496 | PORT_C); | |
10497 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) | |
5d8a7752 | 10498 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); |
6f6005a5 | 10499 | } |
19c03924 | 10500 | |
3cfca973 | 10501 | intel_dsi_init(dev); |
103a196f | 10502 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 10503 | bool found = false; |
7d57382e | 10504 | |
e2debe91 | 10505 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 10506 | DRM_DEBUG_KMS("probing SDVOB\n"); |
e2debe91 | 10507 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
b01f2c3a JB |
10508 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
10509 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
e2debe91 | 10510 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 10511 | } |
27185ae1 | 10512 | |
e7281eab | 10513 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 10514 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 10515 | } |
13520b05 KH |
10516 | |
10517 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 10518 | |
e2debe91 | 10519 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 10520 | DRM_DEBUG_KMS("probing SDVOC\n"); |
e2debe91 | 10521 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
b01f2c3a | 10522 | } |
27185ae1 | 10523 | |
e2debe91 | 10524 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 10525 | |
b01f2c3a JB |
10526 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
10527 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
e2debe91 | 10528 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 10529 | } |
e7281eab | 10530 | if (SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 10531 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 10532 | } |
27185ae1 | 10533 | |
b01f2c3a | 10534 | if (SUPPORTS_INTEGRATED_DP(dev) && |
e7281eab | 10535 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 10536 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 10537 | } else if (IS_GEN2(dev)) |
79e53945 JB |
10538 | intel_dvo_init(dev); |
10539 | ||
103a196f | 10540 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
10541 | intel_tv_init(dev); |
10542 | ||
4ef69c7a CW |
10543 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
10544 | encoder->base.possible_crtcs = encoder->crtc_mask; | |
10545 | encoder->base.possible_clones = | |
66a9278e | 10546 | intel_encoder_clones(encoder); |
79e53945 | 10547 | } |
47356eb6 | 10548 | |
dde86e2d | 10549 | intel_init_pch_refclk(dev); |
270b3042 DV |
10550 | |
10551 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
10552 | } |
10553 | ||
10554 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
10555 | { | |
10556 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 | 10557 | |
ef2d633e DV |
10558 | drm_framebuffer_cleanup(fb); |
10559 | WARN_ON(!intel_fb->obj->framebuffer_references--); | |
10560 | drm_gem_object_unreference_unlocked(&intel_fb->obj->base); | |
79e53945 JB |
10561 | kfree(intel_fb); |
10562 | } | |
10563 | ||
10564 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 10565 | struct drm_file *file, |
79e53945 JB |
10566 | unsigned int *handle) |
10567 | { | |
10568 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 10569 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 10570 | |
05394f39 | 10571 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
10572 | } |
10573 | ||
10574 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
10575 | .destroy = intel_user_framebuffer_destroy, | |
10576 | .create_handle = intel_user_framebuffer_create_handle, | |
10577 | }; | |
10578 | ||
38651674 DA |
10579 | int intel_framebuffer_init(struct drm_device *dev, |
10580 | struct intel_framebuffer *intel_fb, | |
308e5bcb | 10581 | struct drm_mode_fb_cmd2 *mode_cmd, |
05394f39 | 10582 | struct drm_i915_gem_object *obj) |
79e53945 | 10583 | { |
a57ce0b2 | 10584 | int aligned_height; |
a35cdaa0 | 10585 | int pitch_limit; |
79e53945 JB |
10586 | int ret; |
10587 | ||
dd4916c5 DV |
10588 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
10589 | ||
c16ed4be CW |
10590 | if (obj->tiling_mode == I915_TILING_Y) { |
10591 | DRM_DEBUG("hardware does not support tiling Y\n"); | |
57cd6508 | 10592 | return -EINVAL; |
c16ed4be | 10593 | } |
57cd6508 | 10594 | |
c16ed4be CW |
10595 | if (mode_cmd->pitches[0] & 63) { |
10596 | DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n", | |
10597 | mode_cmd->pitches[0]); | |
57cd6508 | 10598 | return -EINVAL; |
c16ed4be | 10599 | } |
57cd6508 | 10600 | |
a35cdaa0 CW |
10601 | if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) { |
10602 | pitch_limit = 32*1024; | |
10603 | } else if (INTEL_INFO(dev)->gen >= 4) { | |
10604 | if (obj->tiling_mode) | |
10605 | pitch_limit = 16*1024; | |
10606 | else | |
10607 | pitch_limit = 32*1024; | |
10608 | } else if (INTEL_INFO(dev)->gen >= 3) { | |
10609 | if (obj->tiling_mode) | |
10610 | pitch_limit = 8*1024; | |
10611 | else | |
10612 | pitch_limit = 16*1024; | |
10613 | } else | |
10614 | /* XXX DSPC is limited to 4k tiled */ | |
10615 | pitch_limit = 8*1024; | |
10616 | ||
10617 | if (mode_cmd->pitches[0] > pitch_limit) { | |
10618 | DRM_DEBUG("%s pitch (%d) must be at less than %d\n", | |
10619 | obj->tiling_mode ? "tiled" : "linear", | |
10620 | mode_cmd->pitches[0], pitch_limit); | |
5d7bd705 | 10621 | return -EINVAL; |
c16ed4be | 10622 | } |
5d7bd705 VS |
10623 | |
10624 | if (obj->tiling_mode != I915_TILING_NONE && | |
c16ed4be CW |
10625 | mode_cmd->pitches[0] != obj->stride) { |
10626 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
10627 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 10628 | return -EINVAL; |
c16ed4be | 10629 | } |
5d7bd705 | 10630 | |
57779d06 | 10631 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 10632 | switch (mode_cmd->pixel_format) { |
57779d06 | 10633 | case DRM_FORMAT_C8: |
04b3924d VS |
10634 | case DRM_FORMAT_RGB565: |
10635 | case DRM_FORMAT_XRGB8888: | |
10636 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
10637 | break; |
10638 | case DRM_FORMAT_XRGB1555: | |
10639 | case DRM_FORMAT_ARGB1555: | |
c16ed4be | 10640 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
10641 | DRM_DEBUG("unsupported pixel format: %s\n", |
10642 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 10643 | return -EINVAL; |
c16ed4be | 10644 | } |
57779d06 VS |
10645 | break; |
10646 | case DRM_FORMAT_XBGR8888: | |
10647 | case DRM_FORMAT_ABGR8888: | |
04b3924d VS |
10648 | case DRM_FORMAT_XRGB2101010: |
10649 | case DRM_FORMAT_ARGB2101010: | |
57779d06 VS |
10650 | case DRM_FORMAT_XBGR2101010: |
10651 | case DRM_FORMAT_ABGR2101010: | |
c16ed4be | 10652 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
10653 | DRM_DEBUG("unsupported pixel format: %s\n", |
10654 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 10655 | return -EINVAL; |
c16ed4be | 10656 | } |
b5626747 | 10657 | break; |
04b3924d VS |
10658 | case DRM_FORMAT_YUYV: |
10659 | case DRM_FORMAT_UYVY: | |
10660 | case DRM_FORMAT_YVYU: | |
10661 | case DRM_FORMAT_VYUY: | |
c16ed4be | 10662 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
10663 | DRM_DEBUG("unsupported pixel format: %s\n", |
10664 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 10665 | return -EINVAL; |
c16ed4be | 10666 | } |
57cd6508 CW |
10667 | break; |
10668 | default: | |
4ee62c76 VS |
10669 | DRM_DEBUG("unsupported pixel format: %s\n", |
10670 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
10671 | return -EINVAL; |
10672 | } | |
10673 | ||
90f9a336 VS |
10674 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
10675 | if (mode_cmd->offsets[0] != 0) | |
10676 | return -EINVAL; | |
10677 | ||
a57ce0b2 JB |
10678 | aligned_height = intel_align_height(dev, mode_cmd->height, |
10679 | obj->tiling_mode); | |
53155c0a DV |
10680 | /* FIXME drm helper for size checks (especially planar formats)? */ |
10681 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
10682 | return -EINVAL; | |
10683 | ||
c7d73f6a DV |
10684 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
10685 | intel_fb->obj = obj; | |
80075d49 | 10686 | intel_fb->obj->framebuffer_references++; |
c7d73f6a | 10687 | |
79e53945 JB |
10688 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
10689 | if (ret) { | |
10690 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
10691 | return ret; | |
10692 | } | |
10693 | ||
79e53945 JB |
10694 | return 0; |
10695 | } | |
10696 | ||
79e53945 JB |
10697 | static struct drm_framebuffer * |
10698 | intel_user_framebuffer_create(struct drm_device *dev, | |
10699 | struct drm_file *filp, | |
308e5bcb | 10700 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 10701 | { |
05394f39 | 10702 | struct drm_i915_gem_object *obj; |
79e53945 | 10703 | |
308e5bcb JB |
10704 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
10705 | mode_cmd->handles[0])); | |
c8725226 | 10706 | if (&obj->base == NULL) |
cce13ff7 | 10707 | return ERR_PTR(-ENOENT); |
79e53945 | 10708 | |
d2dff872 | 10709 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
10710 | } |
10711 | ||
4520f53a | 10712 | #ifndef CONFIG_DRM_I915_FBDEV |
0632fef6 | 10713 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
10714 | { |
10715 | } | |
10716 | #endif | |
10717 | ||
79e53945 | 10718 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 10719 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 10720 | .output_poll_changed = intel_fbdev_output_poll_changed, |
79e53945 JB |
10721 | }; |
10722 | ||
e70236a8 JB |
10723 | /* Set up chip specific display functions */ |
10724 | static void intel_init_display(struct drm_device *dev) | |
10725 | { | |
10726 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10727 | ||
ee9300bb DV |
10728 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
10729 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
10730 | else if (IS_VALLEYVIEW(dev)) | |
10731 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
10732 | else if (IS_PINEVIEW(dev)) | |
10733 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
10734 | else | |
10735 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
10736 | ||
affa9354 | 10737 | if (HAS_DDI(dev)) { |
0e8ffe1b | 10738 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
09b4ddf9 | 10739 | dev_priv->display.crtc_mode_set = haswell_crtc_mode_set; |
4f771f10 PZ |
10740 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
10741 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
6441ab5f | 10742 | dev_priv->display.off = haswell_crtc_off; |
09b4ddf9 PZ |
10743 | dev_priv->display.update_plane = ironlake_update_plane; |
10744 | } else if (HAS_PCH_SPLIT(dev)) { | |
0e8ffe1b | 10745 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
f564048e | 10746 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
76e5a89c DV |
10747 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
10748 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
ee7b9f93 | 10749 | dev_priv->display.off = ironlake_crtc_off; |
17638cd6 | 10750 | dev_priv->display.update_plane = ironlake_update_plane; |
89b667f8 JB |
10751 | } else if (IS_VALLEYVIEW(dev)) { |
10752 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
10753 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; | |
10754 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
10755 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
10756 | dev_priv->display.off = i9xx_crtc_off; | |
10757 | dev_priv->display.update_plane = i9xx_update_plane; | |
f564048e | 10758 | } else { |
0e8ffe1b | 10759 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
f564048e | 10760 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
76e5a89c DV |
10761 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
10762 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
ee7b9f93 | 10763 | dev_priv->display.off = i9xx_crtc_off; |
17638cd6 | 10764 | dev_priv->display.update_plane = i9xx_update_plane; |
f564048e | 10765 | } |
e70236a8 | 10766 | |
e70236a8 | 10767 | /* Returns the core display clock speed */ |
25eb05fc JB |
10768 | if (IS_VALLEYVIEW(dev)) |
10769 | dev_priv->display.get_display_clock_speed = | |
10770 | valleyview_get_display_clock_speed; | |
10771 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) | |
e70236a8 JB |
10772 | dev_priv->display.get_display_clock_speed = |
10773 | i945_get_display_clock_speed; | |
10774 | else if (IS_I915G(dev)) | |
10775 | dev_priv->display.get_display_clock_speed = | |
10776 | i915_get_display_clock_speed; | |
257a7ffc | 10777 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
10778 | dev_priv->display.get_display_clock_speed = |
10779 | i9xx_misc_get_display_clock_speed; | |
257a7ffc DV |
10780 | else if (IS_PINEVIEW(dev)) |
10781 | dev_priv->display.get_display_clock_speed = | |
10782 | pnv_get_display_clock_speed; | |
e70236a8 JB |
10783 | else if (IS_I915GM(dev)) |
10784 | dev_priv->display.get_display_clock_speed = | |
10785 | i915gm_get_display_clock_speed; | |
10786 | else if (IS_I865G(dev)) | |
10787 | dev_priv->display.get_display_clock_speed = | |
10788 | i865_get_display_clock_speed; | |
f0f8a9ce | 10789 | else if (IS_I85X(dev)) |
e70236a8 JB |
10790 | dev_priv->display.get_display_clock_speed = |
10791 | i855_get_display_clock_speed; | |
10792 | else /* 852, 830 */ | |
10793 | dev_priv->display.get_display_clock_speed = | |
10794 | i830_get_display_clock_speed; | |
10795 | ||
7f8a8569 | 10796 | if (HAS_PCH_SPLIT(dev)) { |
f00a3ddf | 10797 | if (IS_GEN5(dev)) { |
674cf967 | 10798 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
e0dac65e | 10799 | dev_priv->display.write_eld = ironlake_write_eld; |
1398261a | 10800 | } else if (IS_GEN6(dev)) { |
674cf967 | 10801 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
e0dac65e | 10802 | dev_priv->display.write_eld = ironlake_write_eld; |
357555c0 JB |
10803 | } else if (IS_IVYBRIDGE(dev)) { |
10804 | /* FIXME: detect B0+ stepping and use auto training */ | |
10805 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
e0dac65e | 10806 | dev_priv->display.write_eld = ironlake_write_eld; |
01a415fd DV |
10807 | dev_priv->display.modeset_global_resources = |
10808 | ivb_modeset_global_resources; | |
4e0bbc31 | 10809 | } else if (IS_HASWELL(dev) || IS_GEN8(dev)) { |
c82e4d26 | 10810 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
83358c85 | 10811 | dev_priv->display.write_eld = haswell_write_eld; |
d6dd9eb1 DV |
10812 | dev_priv->display.modeset_global_resources = |
10813 | haswell_modeset_global_resources; | |
a0e63c22 | 10814 | } |
6067aaea | 10815 | } else if (IS_G4X(dev)) { |
e0dac65e | 10816 | dev_priv->display.write_eld = g4x_write_eld; |
30a970c6 JB |
10817 | } else if (IS_VALLEYVIEW(dev)) { |
10818 | dev_priv->display.modeset_global_resources = | |
10819 | valleyview_modeset_global_resources; | |
9ca2fe73 | 10820 | dev_priv->display.write_eld = ironlake_write_eld; |
e70236a8 | 10821 | } |
8c9f3aaf JB |
10822 | |
10823 | /* Default just returns -ENODEV to indicate unsupported */ | |
10824 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
10825 | ||
10826 | switch (INTEL_INFO(dev)->gen) { | |
10827 | case 2: | |
10828 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
10829 | break; | |
10830 | ||
10831 | case 3: | |
10832 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
10833 | break; | |
10834 | ||
10835 | case 4: | |
10836 | case 5: | |
10837 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
10838 | break; | |
10839 | ||
10840 | case 6: | |
10841 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
10842 | break; | |
7c9017e5 | 10843 | case 7: |
4e0bbc31 | 10844 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
10845 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
10846 | break; | |
8c9f3aaf | 10847 | } |
7bd688cd JN |
10848 | |
10849 | intel_panel_init_backlight_funcs(dev); | |
e70236a8 JB |
10850 | } |
10851 | ||
b690e96c JB |
10852 | /* |
10853 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
10854 | * resume, or other times. This quirk makes sure that's the case for | |
10855 | * affected systems. | |
10856 | */ | |
0206e353 | 10857 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
10858 | { |
10859 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10860 | ||
10861 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 10862 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
10863 | } |
10864 | ||
435793df KP |
10865 | /* |
10866 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
10867 | */ | |
10868 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
10869 | { | |
10870 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10871 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 10872 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
10873 | } |
10874 | ||
4dca20ef | 10875 | /* |
5a15ab5b CE |
10876 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
10877 | * brightness value | |
4dca20ef CE |
10878 | */ |
10879 | static void quirk_invert_brightness(struct drm_device *dev) | |
10880 | { | |
10881 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10882 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 10883 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
10884 | } |
10885 | ||
b690e96c JB |
10886 | struct intel_quirk { |
10887 | int device; | |
10888 | int subsystem_vendor; | |
10889 | int subsystem_device; | |
10890 | void (*hook)(struct drm_device *dev); | |
10891 | }; | |
10892 | ||
5f85f176 EE |
10893 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
10894 | struct intel_dmi_quirk { | |
10895 | void (*hook)(struct drm_device *dev); | |
10896 | const struct dmi_system_id (*dmi_id_list)[]; | |
10897 | }; | |
10898 | ||
10899 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
10900 | { | |
10901 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
10902 | return 1; | |
10903 | } | |
10904 | ||
10905 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
10906 | { | |
10907 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
10908 | { | |
10909 | .callback = intel_dmi_reverse_brightness, | |
10910 | .ident = "NCR Corporation", | |
10911 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
10912 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
10913 | }, | |
10914 | }, | |
10915 | { } /* terminating entry */ | |
10916 | }, | |
10917 | .hook = quirk_invert_brightness, | |
10918 | }, | |
10919 | }; | |
10920 | ||
c43b5634 | 10921 | static struct intel_quirk intel_quirks[] = { |
b690e96c | 10922 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
0206e353 | 10923 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c | 10924 | |
b690e96c JB |
10925 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
10926 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
10927 | ||
b690e96c JB |
10928 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
10929 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
10930 | ||
a4945f95 | 10931 | /* 830 needs to leave pipe A & dpll A up */ |
dcdaed6e | 10932 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
435793df KP |
10933 | |
10934 | /* Lenovo U160 cannot use SSC on LVDS */ | |
10935 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
10936 | |
10937 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
10938 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 10939 | |
be505f64 AH |
10940 | /* Acer Aspire 5734Z must invert backlight brightness */ |
10941 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
10942 | ||
10943 | /* Acer/eMachines G725 */ | |
10944 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
10945 | ||
10946 | /* Acer/eMachines e725 */ | |
10947 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
10948 | ||
10949 | /* Acer/Packard Bell NCL20 */ | |
10950 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
10951 | ||
10952 | /* Acer Aspire 4736Z */ | |
10953 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
10954 | |
10955 | /* Acer Aspire 5336 */ | |
10956 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
b690e96c JB |
10957 | }; |
10958 | ||
10959 | static void intel_init_quirks(struct drm_device *dev) | |
10960 | { | |
10961 | struct pci_dev *d = dev->pdev; | |
10962 | int i; | |
10963 | ||
10964 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
10965 | struct intel_quirk *q = &intel_quirks[i]; | |
10966 | ||
10967 | if (d->device == q->device && | |
10968 | (d->subsystem_vendor == q->subsystem_vendor || | |
10969 | q->subsystem_vendor == PCI_ANY_ID) && | |
10970 | (d->subsystem_device == q->subsystem_device || | |
10971 | q->subsystem_device == PCI_ANY_ID)) | |
10972 | q->hook(dev); | |
10973 | } | |
5f85f176 EE |
10974 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
10975 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
10976 | intel_dmi_quirks[i].hook(dev); | |
10977 | } | |
b690e96c JB |
10978 | } |
10979 | ||
9cce37f4 JB |
10980 | /* Disable the VGA plane that we never use */ |
10981 | static void i915_disable_vga(struct drm_device *dev) | |
10982 | { | |
10983 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10984 | u8 sr1; | |
766aa1c4 | 10985 | u32 vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 10986 | |
2b37c616 | 10987 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 10988 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 10989 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
10990 | sr1 = inb(VGA_SR_DATA); |
10991 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
10992 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
10993 | udelay(300); | |
10994 | ||
10995 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); | |
10996 | POSTING_READ(vga_reg); | |
10997 | } | |
10998 | ||
f817586c DV |
10999 | void intel_modeset_init_hw(struct drm_device *dev) |
11000 | { | |
a8f78b58 ED |
11001 | intel_prepare_ddi(dev); |
11002 | ||
f817586c DV |
11003 | intel_init_clock_gating(dev); |
11004 | ||
5382f5f3 | 11005 | intel_reset_dpio(dev); |
40e9cf64 | 11006 | |
79f5b2c7 | 11007 | mutex_lock(&dev->struct_mutex); |
8090c6b9 | 11008 | intel_enable_gt_powersave(dev); |
79f5b2c7 | 11009 | mutex_unlock(&dev->struct_mutex); |
f817586c DV |
11010 | } |
11011 | ||
7d708ee4 ID |
11012 | void intel_modeset_suspend_hw(struct drm_device *dev) |
11013 | { | |
11014 | intel_suspend_hw(dev); | |
11015 | } | |
11016 | ||
79e53945 JB |
11017 | void intel_modeset_init(struct drm_device *dev) |
11018 | { | |
652c393a | 11019 | struct drm_i915_private *dev_priv = dev->dev_private; |
7f1f3851 | 11020 | int i, j, ret; |
79e53945 JB |
11021 | |
11022 | drm_mode_config_init(dev); | |
11023 | ||
11024 | dev->mode_config.min_width = 0; | |
11025 | dev->mode_config.min_height = 0; | |
11026 | ||
019d96cb DA |
11027 | dev->mode_config.preferred_depth = 24; |
11028 | dev->mode_config.prefer_shadow = 1; | |
11029 | ||
e6ecefaa | 11030 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 11031 | |
b690e96c JB |
11032 | intel_init_quirks(dev); |
11033 | ||
1fa61106 ED |
11034 | intel_init_pm(dev); |
11035 | ||
e3c74757 BW |
11036 | if (INTEL_INFO(dev)->num_pipes == 0) |
11037 | return; | |
11038 | ||
e70236a8 JB |
11039 | intel_init_display(dev); |
11040 | ||
a6c45cf0 CW |
11041 | if (IS_GEN2(dev)) { |
11042 | dev->mode_config.max_width = 2048; | |
11043 | dev->mode_config.max_height = 2048; | |
11044 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
11045 | dev->mode_config.max_width = 4096; |
11046 | dev->mode_config.max_height = 4096; | |
79e53945 | 11047 | } else { |
a6c45cf0 CW |
11048 | dev->mode_config.max_width = 8192; |
11049 | dev->mode_config.max_height = 8192; | |
79e53945 | 11050 | } |
5d4545ae | 11051 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 11052 | |
28c97730 | 11053 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
11054 | INTEL_INFO(dev)->num_pipes, |
11055 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 11056 | |
08e2a7de | 11057 | for_each_pipe(i) { |
79e53945 | 11058 | intel_crtc_init(dev, i); |
22d3fd46 | 11059 | for (j = 0; j < INTEL_INFO(dev)->num_sprites; j++) { |
7f1f3851 JB |
11060 | ret = intel_plane_init(dev, i, j); |
11061 | if (ret) | |
06da8da2 VS |
11062 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
11063 | pipe_name(i), sprite_name(i, j), ret); | |
7f1f3851 | 11064 | } |
79e53945 JB |
11065 | } |
11066 | ||
f42bb70d | 11067 | intel_init_dpio(dev); |
5382f5f3 | 11068 | intel_reset_dpio(dev); |
f42bb70d | 11069 | |
79f689aa | 11070 | intel_cpu_pll_init(dev); |
e72f9fbf | 11071 | intel_shared_dpll_init(dev); |
ee7b9f93 | 11072 | |
9cce37f4 JB |
11073 | /* Just disable it once at startup */ |
11074 | i915_disable_vga(dev); | |
79e53945 | 11075 | intel_setup_outputs(dev); |
11be49eb CW |
11076 | |
11077 | /* Just in case the BIOS is doing something questionable. */ | |
11078 | intel_disable_fbc(dev); | |
2c7111db CW |
11079 | } |
11080 | ||
24929352 DV |
11081 | static void |
11082 | intel_connector_break_all_links(struct intel_connector *connector) | |
11083 | { | |
11084 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
11085 | connector->base.encoder = NULL; | |
11086 | connector->encoder->connectors_active = false; | |
11087 | connector->encoder->base.crtc = NULL; | |
11088 | } | |
11089 | ||
7fad798e DV |
11090 | static void intel_enable_pipe_a(struct drm_device *dev) |
11091 | { | |
11092 | struct intel_connector *connector; | |
11093 | struct drm_connector *crt = NULL; | |
11094 | struct intel_load_detect_pipe load_detect_temp; | |
11095 | ||
11096 | /* We can't just switch on the pipe A, we need to set things up with a | |
11097 | * proper mode and output configuration. As a gross hack, enable pipe A | |
11098 | * by enabling the load detect pipe once. */ | |
11099 | list_for_each_entry(connector, | |
11100 | &dev->mode_config.connector_list, | |
11101 | base.head) { | |
11102 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { | |
11103 | crt = &connector->base; | |
11104 | break; | |
11105 | } | |
11106 | } | |
11107 | ||
11108 | if (!crt) | |
11109 | return; | |
11110 | ||
11111 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp)) | |
11112 | intel_release_load_detect_pipe(crt, &load_detect_temp); | |
11113 | ||
652c393a | 11114 | |
7fad798e DV |
11115 | } |
11116 | ||
fa555837 DV |
11117 | static bool |
11118 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
11119 | { | |
7eb552ae BW |
11120 | struct drm_device *dev = crtc->base.dev; |
11121 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 DV |
11122 | u32 reg, val; |
11123 | ||
7eb552ae | 11124 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
11125 | return true; |
11126 | ||
11127 | reg = DSPCNTR(!crtc->plane); | |
11128 | val = I915_READ(reg); | |
11129 | ||
11130 | if ((val & DISPLAY_PLANE_ENABLE) && | |
11131 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
11132 | return false; | |
11133 | ||
11134 | return true; | |
11135 | } | |
11136 | ||
24929352 DV |
11137 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
11138 | { | |
11139 | struct drm_device *dev = crtc->base.dev; | |
11140 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 | 11141 | u32 reg; |
24929352 | 11142 | |
24929352 | 11143 | /* Clear any frame start delays used for debugging left by the BIOS */ |
3b117c8f | 11144 | reg = PIPECONF(crtc->config.cpu_transcoder); |
24929352 DV |
11145 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
11146 | ||
11147 | /* We need to sanitize the plane -> pipe mapping first because this will | |
fa555837 DV |
11148 | * disable the crtc (and hence change the state) if it is wrong. Note |
11149 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
11150 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
11151 | struct intel_connector *connector; |
11152 | bool plane; | |
11153 | ||
24929352 DV |
11154 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
11155 | crtc->base.base.id); | |
11156 | ||
11157 | /* Pipe has the wrong plane attached and the plane is active. | |
11158 | * Temporarily change the plane mapping and disable everything | |
11159 | * ... */ | |
11160 | plane = crtc->plane; | |
11161 | crtc->plane = !plane; | |
11162 | dev_priv->display.crtc_disable(&crtc->base); | |
11163 | crtc->plane = plane; | |
11164 | ||
11165 | /* ... and break all links. */ | |
11166 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
11167 | base.head) { | |
11168 | if (connector->encoder->base.crtc != &crtc->base) | |
11169 | continue; | |
11170 | ||
11171 | intel_connector_break_all_links(connector); | |
11172 | } | |
11173 | ||
11174 | WARN_ON(crtc->active); | |
11175 | crtc->base.enabled = false; | |
11176 | } | |
24929352 | 11177 | |
7fad798e DV |
11178 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
11179 | crtc->pipe == PIPE_A && !crtc->active) { | |
11180 | /* BIOS forgot to enable pipe A, this mostly happens after | |
11181 | * resume. Force-enable the pipe to fix this, the update_dpms | |
11182 | * call below we restore the pipe to the right state, but leave | |
11183 | * the required bits on. */ | |
11184 | intel_enable_pipe_a(dev); | |
11185 | } | |
11186 | ||
24929352 DV |
11187 | /* Adjust the state of the output pipe according to whether we |
11188 | * have active connectors/encoders. */ | |
11189 | intel_crtc_update_dpms(&crtc->base); | |
11190 | ||
11191 | if (crtc->active != crtc->base.enabled) { | |
11192 | struct intel_encoder *encoder; | |
11193 | ||
11194 | /* This can happen either due to bugs in the get_hw_state | |
11195 | * functions or because the pipe is force-enabled due to the | |
11196 | * pipe A quirk. */ | |
11197 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
11198 | crtc->base.base.id, | |
11199 | crtc->base.enabled ? "enabled" : "disabled", | |
11200 | crtc->active ? "enabled" : "disabled"); | |
11201 | ||
11202 | crtc->base.enabled = crtc->active; | |
11203 | ||
11204 | /* Because we only establish the connector -> encoder -> | |
11205 | * crtc links if something is active, this means the | |
11206 | * crtc is now deactivated. Break the links. connector | |
11207 | * -> encoder links are only establish when things are | |
11208 | * actually up, hence no need to break them. */ | |
11209 | WARN_ON(crtc->active); | |
11210 | ||
11211 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { | |
11212 | WARN_ON(encoder->connectors_active); | |
11213 | encoder->base.crtc = NULL; | |
11214 | } | |
11215 | } | |
11216 | } | |
11217 | ||
11218 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
11219 | { | |
11220 | struct intel_connector *connector; | |
11221 | struct drm_device *dev = encoder->base.dev; | |
11222 | ||
11223 | /* We need to check both for a crtc link (meaning that the | |
11224 | * encoder is active and trying to read from a pipe) and the | |
11225 | * pipe itself being active. */ | |
11226 | bool has_active_crtc = encoder->base.crtc && | |
11227 | to_intel_crtc(encoder->base.crtc)->active; | |
11228 | ||
11229 | if (encoder->connectors_active && !has_active_crtc) { | |
11230 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
11231 | encoder->base.base.id, | |
11232 | drm_get_encoder_name(&encoder->base)); | |
11233 | ||
11234 | /* Connector is active, but has no active pipe. This is | |
11235 | * fallout from our resume register restoring. Disable | |
11236 | * the encoder manually again. */ | |
11237 | if (encoder->base.crtc) { | |
11238 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
11239 | encoder->base.base.id, | |
11240 | drm_get_encoder_name(&encoder->base)); | |
11241 | encoder->disable(encoder); | |
11242 | } | |
11243 | ||
11244 | /* Inconsistent output/port/pipe state happens presumably due to | |
11245 | * a bug in one of the get_hw_state functions. Or someplace else | |
11246 | * in our code, like the register restore mess on resume. Clamp | |
11247 | * things to off as a safer default. */ | |
11248 | list_for_each_entry(connector, | |
11249 | &dev->mode_config.connector_list, | |
11250 | base.head) { | |
11251 | if (connector->encoder != encoder) | |
11252 | continue; | |
11253 | ||
11254 | intel_connector_break_all_links(connector); | |
11255 | } | |
11256 | } | |
11257 | /* Enabled encoders without active connectors will be fixed in | |
11258 | * the crtc fixup. */ | |
11259 | } | |
11260 | ||
44cec740 | 11261 | void i915_redisable_vga(struct drm_device *dev) |
0fde901f KM |
11262 | { |
11263 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766aa1c4 | 11264 | u32 vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 11265 | |
8dc8a27c PZ |
11266 | /* This function can be called both from intel_modeset_setup_hw_state or |
11267 | * at a very early point in our resume sequence, where the power well | |
11268 | * structures are not yet restored. Since this function is at a very | |
11269 | * paranoid "someone might have enabled VGA while we were not looking" | |
11270 | * level, just check if the power well is enabled instead of trying to | |
11271 | * follow the "don't touch the power well if we don't need it" policy | |
11272 | * the rest of the driver uses. */ | |
f9e711e9 | 11273 | if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && |
6aedd1f5 | 11274 | (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0) |
8dc8a27c PZ |
11275 | return; |
11276 | ||
e1553faa | 11277 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
0fde901f | 11278 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); |
209d5211 | 11279 | i915_disable_vga(dev); |
0fde901f KM |
11280 | } |
11281 | } | |
11282 | ||
30e984df | 11283 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
11284 | { |
11285 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11286 | enum pipe pipe; | |
24929352 DV |
11287 | struct intel_crtc *crtc; |
11288 | struct intel_encoder *encoder; | |
11289 | struct intel_connector *connector; | |
5358901f | 11290 | int i; |
24929352 | 11291 | |
0e8ffe1b DV |
11292 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
11293 | base.head) { | |
88adfff1 | 11294 | memset(&crtc->config, 0, sizeof(crtc->config)); |
3b117c8f | 11295 | |
0e8ffe1b DV |
11296 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
11297 | &crtc->config); | |
24929352 DV |
11298 | |
11299 | crtc->base.enabled = crtc->active; | |
4c445e0e | 11300 | crtc->primary_enabled = crtc->active; |
24929352 DV |
11301 | |
11302 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
11303 | crtc->base.base.id, | |
11304 | crtc->active ? "enabled" : "disabled"); | |
11305 | } | |
11306 | ||
5358901f | 11307 | /* FIXME: Smash this into the new shared dpll infrastructure. */ |
affa9354 | 11308 | if (HAS_DDI(dev)) |
6441ab5f PZ |
11309 | intel_ddi_setup_hw_pll_state(dev); |
11310 | ||
5358901f DV |
11311 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
11312 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
11313 | ||
11314 | pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state); | |
11315 | pll->active = 0; | |
11316 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
11317 | base.head) { | |
11318 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
11319 | pll->active++; | |
11320 | } | |
11321 | pll->refcount = pll->active; | |
11322 | ||
35c95375 DV |
11323 | DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n", |
11324 | pll->name, pll->refcount, pll->on); | |
5358901f DV |
11325 | } |
11326 | ||
24929352 DV |
11327 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
11328 | base.head) { | |
11329 | pipe = 0; | |
11330 | ||
11331 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
11332 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
11333 | encoder->base.crtc = &crtc->base; | |
1d37b689 | 11334 | encoder->get_config(encoder, &crtc->config); |
24929352 DV |
11335 | } else { |
11336 | encoder->base.crtc = NULL; | |
11337 | } | |
11338 | ||
11339 | encoder->connectors_active = false; | |
6f2bcceb | 11340 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 DV |
11341 | encoder->base.base.id, |
11342 | drm_get_encoder_name(&encoder->base), | |
11343 | encoder->base.crtc ? "enabled" : "disabled", | |
6f2bcceb | 11344 | pipe_name(pipe)); |
24929352 DV |
11345 | } |
11346 | ||
11347 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
11348 | base.head) { | |
11349 | if (connector->get_hw_state(connector)) { | |
11350 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
11351 | connector->encoder->connectors_active = true; | |
11352 | connector->base.encoder = &connector->encoder->base; | |
11353 | } else { | |
11354 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
11355 | connector->base.encoder = NULL; | |
11356 | } | |
11357 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
11358 | connector->base.base.id, | |
11359 | drm_get_connector_name(&connector->base), | |
11360 | connector->base.encoder ? "enabled" : "disabled"); | |
11361 | } | |
30e984df DV |
11362 | } |
11363 | ||
11364 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm | |
11365 | * and i915 state tracking structures. */ | |
11366 | void intel_modeset_setup_hw_state(struct drm_device *dev, | |
11367 | bool force_restore) | |
11368 | { | |
11369 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11370 | enum pipe pipe; | |
30e984df DV |
11371 | struct intel_crtc *crtc; |
11372 | struct intel_encoder *encoder; | |
35c95375 | 11373 | int i; |
30e984df DV |
11374 | |
11375 | intel_modeset_readout_hw_state(dev); | |
24929352 | 11376 | |
babea61d JB |
11377 | /* |
11378 | * Now that we have the config, copy it to each CRTC struct | |
11379 | * Note that this could go away if we move to using crtc_config | |
11380 | * checking everywhere. | |
11381 | */ | |
11382 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
11383 | base.head) { | |
d330a953 | 11384 | if (crtc->active && i915.fastboot) { |
babea61d JB |
11385 | intel_crtc_mode_from_pipe_config(crtc, &crtc->config); |
11386 | ||
11387 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", | |
11388 | crtc->base.base.id); | |
11389 | drm_mode_debug_printmodeline(&crtc->base.mode); | |
11390 | } | |
11391 | } | |
11392 | ||
24929352 DV |
11393 | /* HW state is read out, now we need to sanitize this mess. */ |
11394 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
11395 | base.head) { | |
11396 | intel_sanitize_encoder(encoder); | |
11397 | } | |
11398 | ||
11399 | for_each_pipe(pipe) { | |
11400 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
11401 | intel_sanitize_crtc(crtc); | |
c0b03411 | 11402 | intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]"); |
24929352 | 11403 | } |
9a935856 | 11404 | |
35c95375 DV |
11405 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
11406 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
11407 | ||
11408 | if (!pll->on || pll->active) | |
11409 | continue; | |
11410 | ||
11411 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
11412 | ||
11413 | pll->disable(dev_priv, pll); | |
11414 | pll->on = false; | |
11415 | } | |
11416 | ||
96f90c54 | 11417 | if (HAS_PCH_SPLIT(dev)) |
243e6a44 VS |
11418 | ilk_wm_get_hw_state(dev); |
11419 | ||
45e2b5f6 | 11420 | if (force_restore) { |
7d0bc1ea VS |
11421 | i915_redisable_vga(dev); |
11422 | ||
f30da187 DV |
11423 | /* |
11424 | * We need to use raw interfaces for restoring state to avoid | |
11425 | * checking (bogus) intermediate states. | |
11426 | */ | |
45e2b5f6 | 11427 | for_each_pipe(pipe) { |
b5644d05 JB |
11428 | struct drm_crtc *crtc = |
11429 | dev_priv->pipe_to_crtc_mapping[pipe]; | |
f30da187 DV |
11430 | |
11431 | __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, | |
11432 | crtc->fb); | |
45e2b5f6 DV |
11433 | } |
11434 | } else { | |
11435 | intel_modeset_update_staged_output_state(dev); | |
11436 | } | |
8af6cf88 DV |
11437 | |
11438 | intel_modeset_check_state(dev); | |
2c7111db CW |
11439 | } |
11440 | ||
11441 | void intel_modeset_gem_init(struct drm_device *dev) | |
11442 | { | |
1833b134 | 11443 | intel_modeset_init_hw(dev); |
02e792fb DV |
11444 | |
11445 | intel_setup_overlay(dev); | |
24929352 | 11446 | |
7ad228b1 | 11447 | mutex_lock(&dev->mode_config.mutex); |
45e2b5f6 | 11448 | intel_modeset_setup_hw_state(dev, false); |
7ad228b1 | 11449 | mutex_unlock(&dev->mode_config.mutex); |
79e53945 JB |
11450 | } |
11451 | ||
11452 | void intel_modeset_cleanup(struct drm_device *dev) | |
11453 | { | |
652c393a JB |
11454 | struct drm_i915_private *dev_priv = dev->dev_private; |
11455 | struct drm_crtc *crtc; | |
d9255d57 | 11456 | struct drm_connector *connector; |
652c393a | 11457 | |
fd0c0642 DV |
11458 | /* |
11459 | * Interrupts and polling as the first thing to avoid creating havoc. | |
11460 | * Too much stuff here (turning of rps, connectors, ...) would | |
11461 | * experience fancy races otherwise. | |
11462 | */ | |
11463 | drm_irq_uninstall(dev); | |
11464 | cancel_work_sync(&dev_priv->hotplug_work); | |
11465 | /* | |
11466 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
11467 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
11468 | */ | |
f87ea761 | 11469 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 11470 | |
652c393a JB |
11471 | mutex_lock(&dev->struct_mutex); |
11472 | ||
723bfd70 JB |
11473 | intel_unregister_dsm_handler(); |
11474 | ||
652c393a JB |
11475 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
11476 | /* Skip inactive CRTCs */ | |
11477 | if (!crtc->fb) | |
11478 | continue; | |
11479 | ||
3dec0095 | 11480 | intel_increase_pllclock(crtc); |
652c393a JB |
11481 | } |
11482 | ||
973d04f9 | 11483 | intel_disable_fbc(dev); |
e70236a8 | 11484 | |
8090c6b9 | 11485 | intel_disable_gt_powersave(dev); |
0cdab21f | 11486 | |
930ebb46 DV |
11487 | ironlake_teardown_rc6(dev); |
11488 | ||
69341a5e KH |
11489 | mutex_unlock(&dev->struct_mutex); |
11490 | ||
1630fe75 CW |
11491 | /* flush any delayed tasks or pending work */ |
11492 | flush_scheduled_work(); | |
11493 | ||
db31af1d JN |
11494 | /* destroy the backlight and sysfs files before encoders/connectors */ |
11495 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
11496 | intel_panel_destroy_backlight(connector); | |
d9255d57 | 11497 | drm_sysfs_connector_remove(connector); |
db31af1d | 11498 | } |
d9255d57 | 11499 | |
79e53945 | 11500 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
11501 | |
11502 | intel_cleanup_overlay(dev); | |
79e53945 JB |
11503 | } |
11504 | ||
f1c79df3 ZW |
11505 | /* |
11506 | * Return which encoder is currently attached for connector. | |
11507 | */ | |
df0e9248 | 11508 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 11509 | { |
df0e9248 CW |
11510 | return &intel_attached_encoder(connector)->base; |
11511 | } | |
f1c79df3 | 11512 | |
df0e9248 CW |
11513 | void intel_connector_attach_encoder(struct intel_connector *connector, |
11514 | struct intel_encoder *encoder) | |
11515 | { | |
11516 | connector->encoder = encoder; | |
11517 | drm_mode_connector_attach_encoder(&connector->base, | |
11518 | &encoder->base); | |
79e53945 | 11519 | } |
28d52043 DA |
11520 | |
11521 | /* | |
11522 | * set vga decode state - true == enable VGA decode | |
11523 | */ | |
11524 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
11525 | { | |
11526 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 11527 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
11528 | u16 gmch_ctrl; |
11529 | ||
75fa041d CW |
11530 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
11531 | DRM_ERROR("failed to read control word\n"); | |
11532 | return -EIO; | |
11533 | } | |
11534 | ||
c0cc8a55 CW |
11535 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
11536 | return 0; | |
11537 | ||
28d52043 DA |
11538 | if (state) |
11539 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
11540 | else | |
11541 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
11542 | |
11543 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
11544 | DRM_ERROR("failed to write control word\n"); | |
11545 | return -EIO; | |
11546 | } | |
11547 | ||
28d52043 DA |
11548 | return 0; |
11549 | } | |
c4a1d9e4 | 11550 | |
c4a1d9e4 | 11551 | struct intel_display_error_state { |
ff57f1b0 PZ |
11552 | |
11553 | u32 power_well_driver; | |
11554 | ||
63b66e5b CW |
11555 | int num_transcoders; |
11556 | ||
c4a1d9e4 CW |
11557 | struct intel_cursor_error_state { |
11558 | u32 control; | |
11559 | u32 position; | |
11560 | u32 base; | |
11561 | u32 size; | |
52331309 | 11562 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
11563 | |
11564 | struct intel_pipe_error_state { | |
ddf9c536 | 11565 | bool power_domain_on; |
c4a1d9e4 | 11566 | u32 source; |
52331309 | 11567 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
11568 | |
11569 | struct intel_plane_error_state { | |
11570 | u32 control; | |
11571 | u32 stride; | |
11572 | u32 size; | |
11573 | u32 pos; | |
11574 | u32 addr; | |
11575 | u32 surface; | |
11576 | u32 tile_offset; | |
52331309 | 11577 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
11578 | |
11579 | struct intel_transcoder_error_state { | |
ddf9c536 | 11580 | bool power_domain_on; |
63b66e5b CW |
11581 | enum transcoder cpu_transcoder; |
11582 | ||
11583 | u32 conf; | |
11584 | ||
11585 | u32 htotal; | |
11586 | u32 hblank; | |
11587 | u32 hsync; | |
11588 | u32 vtotal; | |
11589 | u32 vblank; | |
11590 | u32 vsync; | |
11591 | } transcoder[4]; | |
c4a1d9e4 CW |
11592 | }; |
11593 | ||
11594 | struct intel_display_error_state * | |
11595 | intel_display_capture_error_state(struct drm_device *dev) | |
11596 | { | |
0206e353 | 11597 | drm_i915_private_t *dev_priv = dev->dev_private; |
c4a1d9e4 | 11598 | struct intel_display_error_state *error; |
63b66e5b CW |
11599 | int transcoders[] = { |
11600 | TRANSCODER_A, | |
11601 | TRANSCODER_B, | |
11602 | TRANSCODER_C, | |
11603 | TRANSCODER_EDP, | |
11604 | }; | |
c4a1d9e4 CW |
11605 | int i; |
11606 | ||
63b66e5b CW |
11607 | if (INTEL_INFO(dev)->num_pipes == 0) |
11608 | return NULL; | |
11609 | ||
9d1cb914 | 11610 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
11611 | if (error == NULL) |
11612 | return NULL; | |
11613 | ||
190be112 | 11614 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
11615 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
11616 | ||
52331309 | 11617 | for_each_pipe(i) { |
ddf9c536 ID |
11618 | error->pipe[i].power_domain_on = |
11619 | intel_display_power_enabled_sw(dev, POWER_DOMAIN_PIPE(i)); | |
11620 | if (!error->pipe[i].power_domain_on) | |
9d1cb914 PZ |
11621 | continue; |
11622 | ||
a18c4c3d PZ |
11623 | if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) { |
11624 | error->cursor[i].control = I915_READ(CURCNTR(i)); | |
11625 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
11626 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
11627 | } else { | |
11628 | error->cursor[i].control = I915_READ(CURCNTR_IVB(i)); | |
11629 | error->cursor[i].position = I915_READ(CURPOS_IVB(i)); | |
11630 | error->cursor[i].base = I915_READ(CURBASE_IVB(i)); | |
11631 | } | |
c4a1d9e4 CW |
11632 | |
11633 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
11634 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 11635 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 11636 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
11637 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
11638 | } | |
ca291363 PZ |
11639 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
11640 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
11641 | if (INTEL_INFO(dev)->gen >= 4) { |
11642 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
11643 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
11644 | } | |
11645 | ||
c4a1d9e4 | 11646 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
63b66e5b CW |
11647 | } |
11648 | ||
11649 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
11650 | if (HAS_DDI(dev_priv->dev)) | |
11651 | error->num_transcoders++; /* Account for eDP. */ | |
11652 | ||
11653 | for (i = 0; i < error->num_transcoders; i++) { | |
11654 | enum transcoder cpu_transcoder = transcoders[i]; | |
11655 | ||
ddf9c536 | 11656 | error->transcoder[i].power_domain_on = |
38cc1daf PZ |
11657 | intel_display_power_enabled_sw(dev, |
11658 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); | |
ddf9c536 | 11659 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
11660 | continue; |
11661 | ||
63b66e5b CW |
11662 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
11663 | ||
11664 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
11665 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
11666 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
11667 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
11668 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
11669 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
11670 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
11671 | } |
11672 | ||
11673 | return error; | |
11674 | } | |
11675 | ||
edc3d884 MK |
11676 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
11677 | ||
c4a1d9e4 | 11678 | void |
edc3d884 | 11679 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
11680 | struct drm_device *dev, |
11681 | struct intel_display_error_state *error) | |
11682 | { | |
11683 | int i; | |
11684 | ||
63b66e5b CW |
11685 | if (!error) |
11686 | return; | |
11687 | ||
edc3d884 | 11688 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 11689 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 11690 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 11691 | error->power_well_driver); |
52331309 | 11692 | for_each_pipe(i) { |
edc3d884 | 11693 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 ID |
11694 | err_printf(m, " Power: %s\n", |
11695 | error->pipe[i].power_domain_on ? "on" : "off"); | |
edc3d884 | 11696 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
edc3d884 MK |
11697 | |
11698 | err_printf(m, "Plane [%d]:\n", i); | |
11699 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
11700 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 11701 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
11702 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
11703 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 11704 | } |
4b71a570 | 11705 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 11706 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 11707 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
11708 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
11709 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
11710 | } |
11711 | ||
edc3d884 MK |
11712 | err_printf(m, "Cursor [%d]:\n", i); |
11713 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
11714 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
11715 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 11716 | } |
63b66e5b CW |
11717 | |
11718 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 11719 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 11720 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 ID |
11721 | err_printf(m, " Power: %s\n", |
11722 | error->transcoder[i].power_domain_on ? "on" : "off"); | |
63b66e5b CW |
11723 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
11724 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
11725 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
11726 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
11727 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
11728 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
11729 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
11730 | } | |
c4a1d9e4 | 11731 | } |