Commit | Line | Data |
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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
760285e7 DH |
40 | #include <drm/drm_dp_helper.h> |
41 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
42 | #include <drm/drm_plane_helper.h> |
43 | #include <drm/drm_rect.h> | |
c0f372b3 | 44 | #include <linux/dma_remapping.h> |
79e53945 | 45 | |
465c120c MR |
46 | /* Primary plane formats supported by all gen */ |
47 | #define COMMON_PRIMARY_FORMATS \ | |
48 | DRM_FORMAT_C8, \ | |
49 | DRM_FORMAT_RGB565, \ | |
50 | DRM_FORMAT_XRGB8888, \ | |
51 | DRM_FORMAT_ARGB8888 | |
52 | ||
53 | /* Primary plane formats for gen <= 3 */ | |
54 | static const uint32_t intel_primary_formats_gen2[] = { | |
55 | COMMON_PRIMARY_FORMATS, | |
56 | DRM_FORMAT_XRGB1555, | |
57 | DRM_FORMAT_ARGB1555, | |
58 | }; | |
59 | ||
60 | /* Primary plane formats for gen >= 4 */ | |
61 | static const uint32_t intel_primary_formats_gen4[] = { | |
62 | COMMON_PRIMARY_FORMATS, \ | |
63 | DRM_FORMAT_XBGR8888, | |
64 | DRM_FORMAT_ABGR8888, | |
65 | DRM_FORMAT_XRGB2101010, | |
66 | DRM_FORMAT_ARGB2101010, | |
67 | DRM_FORMAT_XBGR2101010, | |
68 | DRM_FORMAT_ABGR2101010, | |
69 | }; | |
70 | ||
3d7d6510 MR |
71 | /* Cursor formats */ |
72 | static const uint32_t intel_cursor_formats[] = { | |
73 | DRM_FORMAT_ARGB8888, | |
74 | }; | |
75 | ||
6b383a7f | 76 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 77 | |
f1f644dc JB |
78 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
79 | struct intel_crtc_config *pipe_config); | |
18442d08 VS |
80 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
81 | struct intel_crtc_config *pipe_config); | |
f1f644dc | 82 | |
e7457a9a DL |
83 | static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
84 | int x, int y, struct drm_framebuffer *old_fb); | |
eb1bfe80 JB |
85 | static int intel_framebuffer_init(struct drm_device *dev, |
86 | struct intel_framebuffer *ifb, | |
87 | struct drm_mode_fb_cmd2 *mode_cmd, | |
88 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
89 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
90 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
29407aab | 91 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
92 | struct intel_link_m_n *m_n, |
93 | struct intel_link_m_n *m2_n2); | |
29407aab | 94 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 DV |
95 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
96 | static void intel_set_pipe_csc(struct drm_crtc *crtc); | |
d288f65f VS |
97 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
98 | const struct intel_crtc_config *pipe_config); | |
99 | static void chv_prepare_pll(struct intel_crtc *crtc, | |
100 | const struct intel_crtc_config *pipe_config); | |
e7457a9a | 101 | |
0e32b39c DA |
102 | static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe) |
103 | { | |
104 | if (!connector->mst_port) | |
105 | return connector->encoder; | |
106 | else | |
107 | return &connector->mst_port->mst_encoders[pipe]->base; | |
108 | } | |
109 | ||
79e53945 | 110 | typedef struct { |
0206e353 | 111 | int min, max; |
79e53945 JB |
112 | } intel_range_t; |
113 | ||
114 | typedef struct { | |
0206e353 AJ |
115 | int dot_limit; |
116 | int p2_slow, p2_fast; | |
79e53945 JB |
117 | } intel_p2_t; |
118 | ||
d4906093 ML |
119 | typedef struct intel_limit intel_limit_t; |
120 | struct intel_limit { | |
0206e353 AJ |
121 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
122 | intel_p2_t p2; | |
d4906093 | 123 | }; |
79e53945 | 124 | |
d2acd215 DV |
125 | int |
126 | intel_pch_rawclk(struct drm_device *dev) | |
127 | { | |
128 | struct drm_i915_private *dev_priv = dev->dev_private; | |
129 | ||
130 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
131 | ||
132 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
133 | } | |
134 | ||
021357ac CW |
135 | static inline u32 /* units of 100MHz */ |
136 | intel_fdi_link_freq(struct drm_device *dev) | |
137 | { | |
8b99e68c CW |
138 | if (IS_GEN5(dev)) { |
139 | struct drm_i915_private *dev_priv = dev->dev_private; | |
140 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
141 | } else | |
142 | return 27; | |
021357ac CW |
143 | } |
144 | ||
5d536e28 | 145 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 146 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 147 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 148 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
149 | .m = { .min = 96, .max = 140 }, |
150 | .m1 = { .min = 18, .max = 26 }, | |
151 | .m2 = { .min = 6, .max = 16 }, | |
152 | .p = { .min = 4, .max = 128 }, | |
153 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
154 | .p2 = { .dot_limit = 165000, |
155 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
156 | }; |
157 | ||
5d536e28 DV |
158 | static const intel_limit_t intel_limits_i8xx_dvo = { |
159 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 160 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 161 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
162 | .m = { .min = 96, .max = 140 }, |
163 | .m1 = { .min = 18, .max = 26 }, | |
164 | .m2 = { .min = 6, .max = 16 }, | |
165 | .p = { .min = 4, .max = 128 }, | |
166 | .p1 = { .min = 2, .max = 33 }, | |
167 | .p2 = { .dot_limit = 165000, | |
168 | .p2_slow = 4, .p2_fast = 4 }, | |
169 | }; | |
170 | ||
e4b36699 | 171 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 172 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 173 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 174 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
175 | .m = { .min = 96, .max = 140 }, |
176 | .m1 = { .min = 18, .max = 26 }, | |
177 | .m2 = { .min = 6, .max = 16 }, | |
178 | .p = { .min = 4, .max = 128 }, | |
179 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
180 | .p2 = { .dot_limit = 165000, |
181 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 182 | }; |
273e27ca | 183 | |
e4b36699 | 184 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
185 | .dot = { .min = 20000, .max = 400000 }, |
186 | .vco = { .min = 1400000, .max = 2800000 }, | |
187 | .n = { .min = 1, .max = 6 }, | |
188 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
189 | .m1 = { .min = 8, .max = 18 }, |
190 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
191 | .p = { .min = 5, .max = 80 }, |
192 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
193 | .p2 = { .dot_limit = 200000, |
194 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
195 | }; |
196 | ||
197 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
198 | .dot = { .min = 20000, .max = 400000 }, |
199 | .vco = { .min = 1400000, .max = 2800000 }, | |
200 | .n = { .min = 1, .max = 6 }, | |
201 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
202 | .m1 = { .min = 8, .max = 18 }, |
203 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
204 | .p = { .min = 7, .max = 98 }, |
205 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
206 | .p2 = { .dot_limit = 112000, |
207 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
208 | }; |
209 | ||
273e27ca | 210 | |
e4b36699 | 211 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
212 | .dot = { .min = 25000, .max = 270000 }, |
213 | .vco = { .min = 1750000, .max = 3500000}, | |
214 | .n = { .min = 1, .max = 4 }, | |
215 | .m = { .min = 104, .max = 138 }, | |
216 | .m1 = { .min = 17, .max = 23 }, | |
217 | .m2 = { .min = 5, .max = 11 }, | |
218 | .p = { .min = 10, .max = 30 }, | |
219 | .p1 = { .min = 1, .max = 3}, | |
220 | .p2 = { .dot_limit = 270000, | |
221 | .p2_slow = 10, | |
222 | .p2_fast = 10 | |
044c7c41 | 223 | }, |
e4b36699 KP |
224 | }; |
225 | ||
226 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
227 | .dot = { .min = 22000, .max = 400000 }, |
228 | .vco = { .min = 1750000, .max = 3500000}, | |
229 | .n = { .min = 1, .max = 4 }, | |
230 | .m = { .min = 104, .max = 138 }, | |
231 | .m1 = { .min = 16, .max = 23 }, | |
232 | .m2 = { .min = 5, .max = 11 }, | |
233 | .p = { .min = 5, .max = 80 }, | |
234 | .p1 = { .min = 1, .max = 8}, | |
235 | .p2 = { .dot_limit = 165000, | |
236 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
237 | }; |
238 | ||
239 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
240 | .dot = { .min = 20000, .max = 115000 }, |
241 | .vco = { .min = 1750000, .max = 3500000 }, | |
242 | .n = { .min = 1, .max = 3 }, | |
243 | .m = { .min = 104, .max = 138 }, | |
244 | .m1 = { .min = 17, .max = 23 }, | |
245 | .m2 = { .min = 5, .max = 11 }, | |
246 | .p = { .min = 28, .max = 112 }, | |
247 | .p1 = { .min = 2, .max = 8 }, | |
248 | .p2 = { .dot_limit = 0, | |
249 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 250 | }, |
e4b36699 KP |
251 | }; |
252 | ||
253 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
254 | .dot = { .min = 80000, .max = 224000 }, |
255 | .vco = { .min = 1750000, .max = 3500000 }, | |
256 | .n = { .min = 1, .max = 3 }, | |
257 | .m = { .min = 104, .max = 138 }, | |
258 | .m1 = { .min = 17, .max = 23 }, | |
259 | .m2 = { .min = 5, .max = 11 }, | |
260 | .p = { .min = 14, .max = 42 }, | |
261 | .p1 = { .min = 2, .max = 6 }, | |
262 | .p2 = { .dot_limit = 0, | |
263 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 264 | }, |
e4b36699 KP |
265 | }; |
266 | ||
f2b115e6 | 267 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
268 | .dot = { .min = 20000, .max = 400000}, |
269 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 270 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
271 | .n = { .min = 3, .max = 6 }, |
272 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 273 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
274 | .m1 = { .min = 0, .max = 0 }, |
275 | .m2 = { .min = 0, .max = 254 }, | |
276 | .p = { .min = 5, .max = 80 }, | |
277 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
278 | .p2 = { .dot_limit = 200000, |
279 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
280 | }; |
281 | ||
f2b115e6 | 282 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
283 | .dot = { .min = 20000, .max = 400000 }, |
284 | .vco = { .min = 1700000, .max = 3500000 }, | |
285 | .n = { .min = 3, .max = 6 }, | |
286 | .m = { .min = 2, .max = 256 }, | |
287 | .m1 = { .min = 0, .max = 0 }, | |
288 | .m2 = { .min = 0, .max = 254 }, | |
289 | .p = { .min = 7, .max = 112 }, | |
290 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
291 | .p2 = { .dot_limit = 112000, |
292 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
293 | }; |
294 | ||
273e27ca EA |
295 | /* Ironlake / Sandybridge |
296 | * | |
297 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
298 | * the range value for them is (actual_value - 2). | |
299 | */ | |
b91ad0ec | 300 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
301 | .dot = { .min = 25000, .max = 350000 }, |
302 | .vco = { .min = 1760000, .max = 3510000 }, | |
303 | .n = { .min = 1, .max = 5 }, | |
304 | .m = { .min = 79, .max = 127 }, | |
305 | .m1 = { .min = 12, .max = 22 }, | |
306 | .m2 = { .min = 5, .max = 9 }, | |
307 | .p = { .min = 5, .max = 80 }, | |
308 | .p1 = { .min = 1, .max = 8 }, | |
309 | .p2 = { .dot_limit = 225000, | |
310 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
311 | }; |
312 | ||
b91ad0ec | 313 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
314 | .dot = { .min = 25000, .max = 350000 }, |
315 | .vco = { .min = 1760000, .max = 3510000 }, | |
316 | .n = { .min = 1, .max = 3 }, | |
317 | .m = { .min = 79, .max = 118 }, | |
318 | .m1 = { .min = 12, .max = 22 }, | |
319 | .m2 = { .min = 5, .max = 9 }, | |
320 | .p = { .min = 28, .max = 112 }, | |
321 | .p1 = { .min = 2, .max = 8 }, | |
322 | .p2 = { .dot_limit = 225000, | |
323 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
324 | }; |
325 | ||
326 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
327 | .dot = { .min = 25000, .max = 350000 }, |
328 | .vco = { .min = 1760000, .max = 3510000 }, | |
329 | .n = { .min = 1, .max = 3 }, | |
330 | .m = { .min = 79, .max = 127 }, | |
331 | .m1 = { .min = 12, .max = 22 }, | |
332 | .m2 = { .min = 5, .max = 9 }, | |
333 | .p = { .min = 14, .max = 56 }, | |
334 | .p1 = { .min = 2, .max = 8 }, | |
335 | .p2 = { .dot_limit = 225000, | |
336 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
337 | }; |
338 | ||
273e27ca | 339 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 340 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
341 | .dot = { .min = 25000, .max = 350000 }, |
342 | .vco = { .min = 1760000, .max = 3510000 }, | |
343 | .n = { .min = 1, .max = 2 }, | |
344 | .m = { .min = 79, .max = 126 }, | |
345 | .m1 = { .min = 12, .max = 22 }, | |
346 | .m2 = { .min = 5, .max = 9 }, | |
347 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 348 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
349 | .p2 = { .dot_limit = 225000, |
350 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
351 | }; |
352 | ||
353 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
354 | .dot = { .min = 25000, .max = 350000 }, |
355 | .vco = { .min = 1760000, .max = 3510000 }, | |
356 | .n = { .min = 1, .max = 3 }, | |
357 | .m = { .min = 79, .max = 126 }, | |
358 | .m1 = { .min = 12, .max = 22 }, | |
359 | .m2 = { .min = 5, .max = 9 }, | |
360 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 361 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
362 | .p2 = { .dot_limit = 225000, |
363 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
364 | }; |
365 | ||
dc730512 | 366 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
367 | /* |
368 | * These are the data rate limits (measured in fast clocks) | |
369 | * since those are the strictest limits we have. The fast | |
370 | * clock and actual rate limits are more relaxed, so checking | |
371 | * them would make no difference. | |
372 | */ | |
373 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 374 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 375 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
376 | .m1 = { .min = 2, .max = 3 }, |
377 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 378 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 379 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
380 | }; |
381 | ||
ef9348c8 CML |
382 | static const intel_limit_t intel_limits_chv = { |
383 | /* | |
384 | * These are the data rate limits (measured in fast clocks) | |
385 | * since those are the strictest limits we have. The fast | |
386 | * clock and actual rate limits are more relaxed, so checking | |
387 | * them would make no difference. | |
388 | */ | |
389 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
390 | .vco = { .min = 4860000, .max = 6700000 }, | |
391 | .n = { .min = 1, .max = 1 }, | |
392 | .m1 = { .min = 2, .max = 2 }, | |
393 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
394 | .p1 = { .min = 2, .max = 4 }, | |
395 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
396 | }; | |
397 | ||
6b4bf1c4 VS |
398 | static void vlv_clock(int refclk, intel_clock_t *clock) |
399 | { | |
400 | clock->m = clock->m1 * clock->m2; | |
401 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
402 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
403 | return; | |
fb03ac01 VS |
404 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
405 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
6b4bf1c4 VS |
406 | } |
407 | ||
e0638cdf PZ |
408 | /** |
409 | * Returns whether any output on the specified pipe is of the specified type | |
410 | */ | |
4093561b | 411 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) |
e0638cdf | 412 | { |
409ee761 | 413 | struct drm_device *dev = crtc->base.dev; |
e0638cdf PZ |
414 | struct intel_encoder *encoder; |
415 | ||
409ee761 | 416 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
e0638cdf PZ |
417 | if (encoder->type == type) |
418 | return true; | |
419 | ||
420 | return false; | |
421 | } | |
422 | ||
d0737e1d ACO |
423 | /** |
424 | * Returns whether any output on the specified pipe will have the specified | |
425 | * type after a staged modeset is complete, i.e., the same as | |
426 | * intel_pipe_has_type() but looking at encoder->new_crtc instead of | |
427 | * encoder->crtc. | |
428 | */ | |
429 | static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type) | |
430 | { | |
431 | struct drm_device *dev = crtc->base.dev; | |
432 | struct intel_encoder *encoder; | |
433 | ||
434 | for_each_intel_encoder(dev, encoder) | |
435 | if (encoder->new_crtc == crtc && encoder->type == type) | |
436 | return true; | |
437 | ||
438 | return false; | |
439 | } | |
440 | ||
409ee761 | 441 | static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc, |
1b894b59 | 442 | int refclk) |
2c07245f | 443 | { |
409ee761 | 444 | struct drm_device *dev = crtc->base.dev; |
2c07245f | 445 | const intel_limit_t *limit; |
b91ad0ec | 446 | |
d0737e1d | 447 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 448 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 449 | if (refclk == 100000) |
b91ad0ec ZW |
450 | limit = &intel_limits_ironlake_dual_lvds_100m; |
451 | else | |
452 | limit = &intel_limits_ironlake_dual_lvds; | |
453 | } else { | |
1b894b59 | 454 | if (refclk == 100000) |
b91ad0ec ZW |
455 | limit = &intel_limits_ironlake_single_lvds_100m; |
456 | else | |
457 | limit = &intel_limits_ironlake_single_lvds; | |
458 | } | |
c6bb3538 | 459 | } else |
b91ad0ec | 460 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
461 | |
462 | return limit; | |
463 | } | |
464 | ||
409ee761 | 465 | static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc) |
044c7c41 | 466 | { |
409ee761 | 467 | struct drm_device *dev = crtc->base.dev; |
044c7c41 ML |
468 | const intel_limit_t *limit; |
469 | ||
d0737e1d | 470 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 471 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 472 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 473 | else |
e4b36699 | 474 | limit = &intel_limits_g4x_single_channel_lvds; |
d0737e1d ACO |
475 | } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) || |
476 | intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 477 | limit = &intel_limits_g4x_hdmi; |
d0737e1d | 478 | } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 479 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 480 | } else /* The option is for other outputs */ |
e4b36699 | 481 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
482 | |
483 | return limit; | |
484 | } | |
485 | ||
409ee761 | 486 | static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk) |
79e53945 | 487 | { |
409ee761 | 488 | struct drm_device *dev = crtc->base.dev; |
79e53945 JB |
489 | const intel_limit_t *limit; |
490 | ||
bad720ff | 491 | if (HAS_PCH_SPLIT(dev)) |
1b894b59 | 492 | limit = intel_ironlake_limit(crtc, refclk); |
2c07245f | 493 | else if (IS_G4X(dev)) { |
044c7c41 | 494 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 495 | } else if (IS_PINEVIEW(dev)) { |
d0737e1d | 496 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 497 | limit = &intel_limits_pineview_lvds; |
2177832f | 498 | else |
f2b115e6 | 499 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
500 | } else if (IS_CHERRYVIEW(dev)) { |
501 | limit = &intel_limits_chv; | |
a0c4da24 | 502 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 503 | limit = &intel_limits_vlv; |
a6c45cf0 | 504 | } else if (!IS_GEN2(dev)) { |
d0737e1d | 505 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) |
a6c45cf0 CW |
506 | limit = &intel_limits_i9xx_lvds; |
507 | else | |
508 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 | 509 | } else { |
d0737e1d | 510 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) |
e4b36699 | 511 | limit = &intel_limits_i8xx_lvds; |
d0737e1d | 512 | else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO)) |
e4b36699 | 513 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
514 | else |
515 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
516 | } |
517 | return limit; | |
518 | } | |
519 | ||
f2b115e6 AJ |
520 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
521 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 522 | { |
2177832f SL |
523 | clock->m = clock->m2 + 2; |
524 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
525 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
526 | return; | |
fb03ac01 VS |
527 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
528 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
2177832f SL |
529 | } |
530 | ||
7429e9d4 DV |
531 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
532 | { | |
533 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
534 | } | |
535 | ||
ac58c3f0 | 536 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
2177832f | 537 | { |
7429e9d4 | 538 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 539 | clock->p = clock->p1 * clock->p2; |
ed5ca77e VS |
540 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
541 | return; | |
fb03ac01 VS |
542 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
543 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
79e53945 JB |
544 | } |
545 | ||
ef9348c8 CML |
546 | static void chv_clock(int refclk, intel_clock_t *clock) |
547 | { | |
548 | clock->m = clock->m1 * clock->m2; | |
549 | clock->p = clock->p1 * clock->p2; | |
550 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
551 | return; | |
552 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, | |
553 | clock->n << 22); | |
554 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
555 | } | |
556 | ||
7c04d1d9 | 557 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
558 | /** |
559 | * Returns whether the given set of divisors are valid for a given refclk with | |
560 | * the given connectors. | |
561 | */ | |
562 | ||
1b894b59 CW |
563 | static bool intel_PLL_is_valid(struct drm_device *dev, |
564 | const intel_limit_t *limit, | |
565 | const intel_clock_t *clock) | |
79e53945 | 566 | { |
f01b7962 VS |
567 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
568 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 569 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 570 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 571 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 572 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 573 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 574 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 VS |
575 | |
576 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev)) | |
577 | if (clock->m1 <= clock->m2) | |
578 | INTELPllInvalid("m1 <= m2\n"); | |
579 | ||
580 | if (!IS_VALLEYVIEW(dev)) { | |
581 | if (clock->p < limit->p.min || limit->p.max < clock->p) | |
582 | INTELPllInvalid("p out of range\n"); | |
583 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
584 | INTELPllInvalid("m out of range\n"); | |
585 | } | |
586 | ||
79e53945 | 587 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 588 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
589 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
590 | * connector, etc., rather than just a single range. | |
591 | */ | |
592 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 593 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
594 | |
595 | return true; | |
596 | } | |
597 | ||
d4906093 | 598 | static bool |
a919ff14 | 599 | i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc, |
cec2f356 SP |
600 | int target, int refclk, intel_clock_t *match_clock, |
601 | intel_clock_t *best_clock) | |
79e53945 | 602 | { |
a919ff14 | 603 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 604 | intel_clock_t clock; |
79e53945 JB |
605 | int err = target; |
606 | ||
d0737e1d | 607 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 608 | /* |
a210b028 DV |
609 | * For LVDS just rely on its current settings for dual-channel. |
610 | * We haven't figured out how to reliably set up different | |
611 | * single/dual channel state, if we even can. | |
79e53945 | 612 | */ |
1974cad0 | 613 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
614 | clock.p2 = limit->p2.p2_fast; |
615 | else | |
616 | clock.p2 = limit->p2.p2_slow; | |
617 | } else { | |
618 | if (target < limit->p2.dot_limit) | |
619 | clock.p2 = limit->p2.p2_slow; | |
620 | else | |
621 | clock.p2 = limit->p2.p2_fast; | |
622 | } | |
623 | ||
0206e353 | 624 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 625 | |
42158660 ZY |
626 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
627 | clock.m1++) { | |
628 | for (clock.m2 = limit->m2.min; | |
629 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 630 | if (clock.m2 >= clock.m1) |
42158660 ZY |
631 | break; |
632 | for (clock.n = limit->n.min; | |
633 | clock.n <= limit->n.max; clock.n++) { | |
634 | for (clock.p1 = limit->p1.min; | |
635 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
636 | int this_err; |
637 | ||
ac58c3f0 DV |
638 | i9xx_clock(refclk, &clock); |
639 | if (!intel_PLL_is_valid(dev, limit, | |
640 | &clock)) | |
641 | continue; | |
642 | if (match_clock && | |
643 | clock.p != match_clock->p) | |
644 | continue; | |
645 | ||
646 | this_err = abs(clock.dot - target); | |
647 | if (this_err < err) { | |
648 | *best_clock = clock; | |
649 | err = this_err; | |
650 | } | |
651 | } | |
652 | } | |
653 | } | |
654 | } | |
655 | ||
656 | return (err != target); | |
657 | } | |
658 | ||
659 | static bool | |
a919ff14 | 660 | pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc, |
ee9300bb DV |
661 | int target, int refclk, intel_clock_t *match_clock, |
662 | intel_clock_t *best_clock) | |
79e53945 | 663 | { |
a919ff14 | 664 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 665 | intel_clock_t clock; |
79e53945 JB |
666 | int err = target; |
667 | ||
d0737e1d | 668 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 669 | /* |
a210b028 DV |
670 | * For LVDS just rely on its current settings for dual-channel. |
671 | * We haven't figured out how to reliably set up different | |
672 | * single/dual channel state, if we even can. | |
79e53945 | 673 | */ |
1974cad0 | 674 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
675 | clock.p2 = limit->p2.p2_fast; |
676 | else | |
677 | clock.p2 = limit->p2.p2_slow; | |
678 | } else { | |
679 | if (target < limit->p2.dot_limit) | |
680 | clock.p2 = limit->p2.p2_slow; | |
681 | else | |
682 | clock.p2 = limit->p2.p2_fast; | |
683 | } | |
684 | ||
0206e353 | 685 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 686 | |
42158660 ZY |
687 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
688 | clock.m1++) { | |
689 | for (clock.m2 = limit->m2.min; | |
690 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
691 | for (clock.n = limit->n.min; |
692 | clock.n <= limit->n.max; clock.n++) { | |
693 | for (clock.p1 = limit->p1.min; | |
694 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
695 | int this_err; |
696 | ||
ac58c3f0 | 697 | pineview_clock(refclk, &clock); |
1b894b59 CW |
698 | if (!intel_PLL_is_valid(dev, limit, |
699 | &clock)) | |
79e53945 | 700 | continue; |
cec2f356 SP |
701 | if (match_clock && |
702 | clock.p != match_clock->p) | |
703 | continue; | |
79e53945 JB |
704 | |
705 | this_err = abs(clock.dot - target); | |
706 | if (this_err < err) { | |
707 | *best_clock = clock; | |
708 | err = this_err; | |
709 | } | |
710 | } | |
711 | } | |
712 | } | |
713 | } | |
714 | ||
715 | return (err != target); | |
716 | } | |
717 | ||
d4906093 | 718 | static bool |
a919ff14 | 719 | g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc, |
ee9300bb DV |
720 | int target, int refclk, intel_clock_t *match_clock, |
721 | intel_clock_t *best_clock) | |
d4906093 | 722 | { |
a919ff14 | 723 | struct drm_device *dev = crtc->base.dev; |
d4906093 ML |
724 | intel_clock_t clock; |
725 | int max_n; | |
726 | bool found; | |
6ba770dc AJ |
727 | /* approximately equals target * 0.00585 */ |
728 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
729 | found = false; |
730 | ||
d0737e1d | 731 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 732 | if (intel_is_dual_link_lvds(dev)) |
d4906093 ML |
733 | clock.p2 = limit->p2.p2_fast; |
734 | else | |
735 | clock.p2 = limit->p2.p2_slow; | |
736 | } else { | |
737 | if (target < limit->p2.dot_limit) | |
738 | clock.p2 = limit->p2.p2_slow; | |
739 | else | |
740 | clock.p2 = limit->p2.p2_fast; | |
741 | } | |
742 | ||
743 | memset(best_clock, 0, sizeof(*best_clock)); | |
744 | max_n = limit->n.max; | |
f77f13e2 | 745 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 746 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 747 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
748 | for (clock.m1 = limit->m1.max; |
749 | clock.m1 >= limit->m1.min; clock.m1--) { | |
750 | for (clock.m2 = limit->m2.max; | |
751 | clock.m2 >= limit->m2.min; clock.m2--) { | |
752 | for (clock.p1 = limit->p1.max; | |
753 | clock.p1 >= limit->p1.min; clock.p1--) { | |
754 | int this_err; | |
755 | ||
ac58c3f0 | 756 | i9xx_clock(refclk, &clock); |
1b894b59 CW |
757 | if (!intel_PLL_is_valid(dev, limit, |
758 | &clock)) | |
d4906093 | 759 | continue; |
1b894b59 CW |
760 | |
761 | this_err = abs(clock.dot - target); | |
d4906093 ML |
762 | if (this_err < err_most) { |
763 | *best_clock = clock; | |
764 | err_most = this_err; | |
765 | max_n = clock.n; | |
766 | found = true; | |
767 | } | |
768 | } | |
769 | } | |
770 | } | |
771 | } | |
2c07245f ZW |
772 | return found; |
773 | } | |
774 | ||
a0c4da24 | 775 | static bool |
a919ff14 | 776 | vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc, |
ee9300bb DV |
777 | int target, int refclk, intel_clock_t *match_clock, |
778 | intel_clock_t *best_clock) | |
a0c4da24 | 779 | { |
a919ff14 | 780 | struct drm_device *dev = crtc->base.dev; |
6b4bf1c4 | 781 | intel_clock_t clock; |
69e4f900 | 782 | unsigned int bestppm = 1000000; |
27e639bf VS |
783 | /* min update 19.2 MHz */ |
784 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 785 | bool found = false; |
a0c4da24 | 786 | |
6b4bf1c4 VS |
787 | target *= 5; /* fast clock */ |
788 | ||
789 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
790 | |
791 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 792 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 793 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 794 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 795 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 796 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 797 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 798 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
69e4f900 VS |
799 | unsigned int ppm, diff; |
800 | ||
6b4bf1c4 VS |
801 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
802 | refclk * clock.m1); | |
803 | ||
804 | vlv_clock(refclk, &clock); | |
43b0ac53 | 805 | |
f01b7962 VS |
806 | if (!intel_PLL_is_valid(dev, limit, |
807 | &clock)) | |
43b0ac53 VS |
808 | continue; |
809 | ||
6b4bf1c4 VS |
810 | diff = abs(clock.dot - target); |
811 | ppm = div_u64(1000000ULL * diff, target); | |
812 | ||
813 | if (ppm < 100 && clock.p > best_clock->p) { | |
43b0ac53 | 814 | bestppm = 0; |
6b4bf1c4 | 815 | *best_clock = clock; |
49e497ef | 816 | found = true; |
43b0ac53 | 817 | } |
6b4bf1c4 | 818 | |
c686122c | 819 | if (bestppm >= 10 && ppm < bestppm - 10) { |
69e4f900 | 820 | bestppm = ppm; |
6b4bf1c4 | 821 | *best_clock = clock; |
49e497ef | 822 | found = true; |
a0c4da24 JB |
823 | } |
824 | } | |
825 | } | |
826 | } | |
827 | } | |
a0c4da24 | 828 | |
49e497ef | 829 | return found; |
a0c4da24 | 830 | } |
a4fc5ed6 | 831 | |
ef9348c8 | 832 | static bool |
a919ff14 | 833 | chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc, |
ef9348c8 CML |
834 | int target, int refclk, intel_clock_t *match_clock, |
835 | intel_clock_t *best_clock) | |
836 | { | |
a919ff14 | 837 | struct drm_device *dev = crtc->base.dev; |
ef9348c8 CML |
838 | intel_clock_t clock; |
839 | uint64_t m2; | |
840 | int found = false; | |
841 | ||
842 | memset(best_clock, 0, sizeof(*best_clock)); | |
843 | ||
844 | /* | |
845 | * Based on hardware doc, the n always set to 1, and m1 always | |
846 | * set to 2. If requires to support 200Mhz refclk, we need to | |
847 | * revisit this because n may not 1 anymore. | |
848 | */ | |
849 | clock.n = 1, clock.m1 = 2; | |
850 | target *= 5; /* fast clock */ | |
851 | ||
852 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
853 | for (clock.p2 = limit->p2.p2_fast; | |
854 | clock.p2 >= limit->p2.p2_slow; | |
855 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
856 | ||
857 | clock.p = clock.p1 * clock.p2; | |
858 | ||
859 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
860 | clock.n) << 22, refclk * clock.m1); | |
861 | ||
862 | if (m2 > INT_MAX/clock.m1) | |
863 | continue; | |
864 | ||
865 | clock.m2 = m2; | |
866 | ||
867 | chv_clock(refclk, &clock); | |
868 | ||
869 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
870 | continue; | |
871 | ||
872 | /* based on hardware requirement, prefer bigger p | |
873 | */ | |
874 | if (clock.p > best_clock->p) { | |
875 | *best_clock = clock; | |
876 | found = true; | |
877 | } | |
878 | } | |
879 | } | |
880 | ||
881 | return found; | |
882 | } | |
883 | ||
20ddf665 VS |
884 | bool intel_crtc_active(struct drm_crtc *crtc) |
885 | { | |
886 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
887 | ||
888 | /* Be paranoid as we can arrive here with only partial | |
889 | * state retrieved from the hardware during setup. | |
890 | * | |
241bfc38 | 891 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
892 | * as Haswell has gained clock readout/fastboot support. |
893 | * | |
66e514c1 | 894 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 VS |
895 | * properly reconstruct framebuffers. |
896 | */ | |
f4510a27 | 897 | return intel_crtc->active && crtc->primary->fb && |
241bfc38 | 898 | intel_crtc->config.adjusted_mode.crtc_clock; |
20ddf665 VS |
899 | } |
900 | ||
a5c961d1 PZ |
901 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
902 | enum pipe pipe) | |
903 | { | |
904 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
905 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
906 | ||
3b117c8f | 907 | return intel_crtc->config.cpu_transcoder; |
a5c961d1 PZ |
908 | } |
909 | ||
fbf49ea2 VS |
910 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
911 | { | |
912 | struct drm_i915_private *dev_priv = dev->dev_private; | |
913 | u32 reg = PIPEDSL(pipe); | |
914 | u32 line1, line2; | |
915 | u32 line_mask; | |
916 | ||
917 | if (IS_GEN2(dev)) | |
918 | line_mask = DSL_LINEMASK_GEN2; | |
919 | else | |
920 | line_mask = DSL_LINEMASK_GEN3; | |
921 | ||
922 | line1 = I915_READ(reg) & line_mask; | |
923 | mdelay(5); | |
924 | line2 = I915_READ(reg) & line_mask; | |
925 | ||
926 | return line1 == line2; | |
927 | } | |
928 | ||
ab7ad7f6 KP |
929 | /* |
930 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 931 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
932 | * |
933 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
934 | * spinning on the vblank interrupt status bit, since we won't actually | |
935 | * see an interrupt when the pipe is disabled. | |
936 | * | |
ab7ad7f6 KP |
937 | * On Gen4 and above: |
938 | * wait for the pipe register state bit to turn off | |
939 | * | |
940 | * Otherwise: | |
941 | * wait for the display line value to settle (it usually | |
942 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 943 | * |
9d0498a2 | 944 | */ |
575f7ab7 | 945 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 946 | { |
575f7ab7 | 947 | struct drm_device *dev = crtc->base.dev; |
9d0498a2 | 948 | struct drm_i915_private *dev_priv = dev->dev_private; |
575f7ab7 VS |
949 | enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; |
950 | enum pipe pipe = crtc->pipe; | |
ab7ad7f6 KP |
951 | |
952 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 953 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
954 | |
955 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
956 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
957 | 100)) | |
284637d9 | 958 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 959 | } else { |
ab7ad7f6 | 960 | /* Wait for the display line to settle */ |
fbf49ea2 | 961 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 962 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 963 | } |
79e53945 JB |
964 | } |
965 | ||
b0ea7d37 DL |
966 | /* |
967 | * ibx_digital_port_connected - is the specified port connected? | |
968 | * @dev_priv: i915 private structure | |
969 | * @port: the port to test | |
970 | * | |
971 | * Returns true if @port is connected, false otherwise. | |
972 | */ | |
973 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, | |
974 | struct intel_digital_port *port) | |
975 | { | |
976 | u32 bit; | |
977 | ||
c36346e3 | 978 | if (HAS_PCH_IBX(dev_priv->dev)) { |
eba905b2 | 979 | switch (port->port) { |
c36346e3 DL |
980 | case PORT_B: |
981 | bit = SDE_PORTB_HOTPLUG; | |
982 | break; | |
983 | case PORT_C: | |
984 | bit = SDE_PORTC_HOTPLUG; | |
985 | break; | |
986 | case PORT_D: | |
987 | bit = SDE_PORTD_HOTPLUG; | |
988 | break; | |
989 | default: | |
990 | return true; | |
991 | } | |
992 | } else { | |
eba905b2 | 993 | switch (port->port) { |
c36346e3 DL |
994 | case PORT_B: |
995 | bit = SDE_PORTB_HOTPLUG_CPT; | |
996 | break; | |
997 | case PORT_C: | |
998 | bit = SDE_PORTC_HOTPLUG_CPT; | |
999 | break; | |
1000 | case PORT_D: | |
1001 | bit = SDE_PORTD_HOTPLUG_CPT; | |
1002 | break; | |
1003 | default: | |
1004 | return true; | |
1005 | } | |
b0ea7d37 DL |
1006 | } |
1007 | ||
1008 | return I915_READ(SDEISR) & bit; | |
1009 | } | |
1010 | ||
b24e7179 JB |
1011 | static const char *state_string(bool enabled) |
1012 | { | |
1013 | return enabled ? "on" : "off"; | |
1014 | } | |
1015 | ||
1016 | /* Only for pre-ILK configs */ | |
55607e8a DV |
1017 | void assert_pll(struct drm_i915_private *dev_priv, |
1018 | enum pipe pipe, bool state) | |
b24e7179 JB |
1019 | { |
1020 | int reg; | |
1021 | u32 val; | |
1022 | bool cur_state; | |
1023 | ||
1024 | reg = DPLL(pipe); | |
1025 | val = I915_READ(reg); | |
1026 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
1027 | WARN(cur_state != state, | |
1028 | "PLL state assertion failure (expected %s, current %s)\n", | |
1029 | state_string(state), state_string(cur_state)); | |
1030 | } | |
b24e7179 | 1031 | |
23538ef1 JN |
1032 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
1033 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
1034 | { | |
1035 | u32 val; | |
1036 | bool cur_state; | |
1037 | ||
1038 | mutex_lock(&dev_priv->dpio_lock); | |
1039 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); | |
1040 | mutex_unlock(&dev_priv->dpio_lock); | |
1041 | ||
1042 | cur_state = val & DSI_PLL_VCO_EN; | |
1043 | WARN(cur_state != state, | |
1044 | "DSI PLL state assertion failure (expected %s, current %s)\n", | |
1045 | state_string(state), state_string(cur_state)); | |
1046 | } | |
1047 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1048 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
1049 | ||
55607e8a | 1050 | struct intel_shared_dpll * |
e2b78267 DV |
1051 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
1052 | { | |
1053 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1054 | ||
a43f6e0f | 1055 | if (crtc->config.shared_dpll < 0) |
e2b78267 DV |
1056 | return NULL; |
1057 | ||
a43f6e0f | 1058 | return &dev_priv->shared_dplls[crtc->config.shared_dpll]; |
e2b78267 DV |
1059 | } |
1060 | ||
040484af | 1061 | /* For ILK+ */ |
55607e8a DV |
1062 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1063 | struct intel_shared_dpll *pll, | |
1064 | bool state) | |
040484af | 1065 | { |
040484af | 1066 | bool cur_state; |
5358901f | 1067 | struct intel_dpll_hw_state hw_state; |
040484af | 1068 | |
92b27b08 | 1069 | if (WARN (!pll, |
46edb027 | 1070 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 1071 | return; |
ee7b9f93 | 1072 | |
5358901f | 1073 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
92b27b08 | 1074 | WARN(cur_state != state, |
5358901f DV |
1075 | "%s assertion failure (expected %s, current %s)\n", |
1076 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 1077 | } |
040484af JB |
1078 | |
1079 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1080 | enum pipe pipe, bool state) | |
1081 | { | |
1082 | int reg; | |
1083 | u32 val; | |
1084 | bool cur_state; | |
ad80a810 PZ |
1085 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1086 | pipe); | |
040484af | 1087 | |
affa9354 PZ |
1088 | if (HAS_DDI(dev_priv->dev)) { |
1089 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 1090 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 1091 | val = I915_READ(reg); |
ad80a810 | 1092 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
1093 | } else { |
1094 | reg = FDI_TX_CTL(pipe); | |
1095 | val = I915_READ(reg); | |
1096 | cur_state = !!(val & FDI_TX_ENABLE); | |
1097 | } | |
040484af JB |
1098 | WARN(cur_state != state, |
1099 | "FDI TX state assertion failure (expected %s, current %s)\n", | |
1100 | state_string(state), state_string(cur_state)); | |
1101 | } | |
1102 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1103 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1104 | ||
1105 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1106 | enum pipe pipe, bool state) | |
1107 | { | |
1108 | int reg; | |
1109 | u32 val; | |
1110 | bool cur_state; | |
1111 | ||
d63fa0dc PZ |
1112 | reg = FDI_RX_CTL(pipe); |
1113 | val = I915_READ(reg); | |
1114 | cur_state = !!(val & FDI_RX_ENABLE); | |
040484af JB |
1115 | WARN(cur_state != state, |
1116 | "FDI RX state assertion failure (expected %s, current %s)\n", | |
1117 | state_string(state), state_string(cur_state)); | |
1118 | } | |
1119 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1120 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1121 | ||
1122 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1123 | enum pipe pipe) | |
1124 | { | |
1125 | int reg; | |
1126 | u32 val; | |
1127 | ||
1128 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1129 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1130 | return; |
1131 | ||
bf507ef7 | 1132 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1133 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1134 | return; |
1135 | ||
040484af JB |
1136 | reg = FDI_TX_CTL(pipe); |
1137 | val = I915_READ(reg); | |
1138 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); | |
1139 | } | |
1140 | ||
55607e8a DV |
1141 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1142 | enum pipe pipe, bool state) | |
040484af JB |
1143 | { |
1144 | int reg; | |
1145 | u32 val; | |
55607e8a | 1146 | bool cur_state; |
040484af JB |
1147 | |
1148 | reg = FDI_RX_CTL(pipe); | |
1149 | val = I915_READ(reg); | |
55607e8a DV |
1150 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
1151 | WARN(cur_state != state, | |
1152 | "FDI RX PLL assertion failure (expected %s, current %s)\n", | |
1153 | state_string(state), state_string(cur_state)); | |
040484af JB |
1154 | } |
1155 | ||
b680c37a DV |
1156 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1157 | enum pipe pipe) | |
ea0760cf | 1158 | { |
bedd4dba JN |
1159 | struct drm_device *dev = dev_priv->dev; |
1160 | int pp_reg; | |
ea0760cf JB |
1161 | u32 val; |
1162 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1163 | bool locked = true; |
ea0760cf | 1164 | |
bedd4dba JN |
1165 | if (WARN_ON(HAS_DDI(dev))) |
1166 | return; | |
1167 | ||
1168 | if (HAS_PCH_SPLIT(dev)) { | |
1169 | u32 port_sel; | |
1170 | ||
ea0760cf | 1171 | pp_reg = PCH_PP_CONTROL; |
bedd4dba JN |
1172 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
1173 | ||
1174 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1175 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1176 | panel_pipe = PIPE_B; | |
1177 | /* XXX: else fix for eDP */ | |
1178 | } else if (IS_VALLEYVIEW(dev)) { | |
1179 | /* presumably write lock depends on pipe, not port select */ | |
1180 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1181 | panel_pipe = pipe; | |
ea0760cf JB |
1182 | } else { |
1183 | pp_reg = PP_CONTROL; | |
bedd4dba JN |
1184 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1185 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1186 | } |
1187 | ||
1188 | val = I915_READ(pp_reg); | |
1189 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1190 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1191 | locked = false; |
1192 | ||
ea0760cf JB |
1193 | WARN(panel_pipe == pipe && locked, |
1194 | "panel assertion failure, pipe %c regs locked\n", | |
9db4a9c7 | 1195 | pipe_name(pipe)); |
ea0760cf JB |
1196 | } |
1197 | ||
93ce0ba6 JN |
1198 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1199 | enum pipe pipe, bool state) | |
1200 | { | |
1201 | struct drm_device *dev = dev_priv->dev; | |
1202 | bool cur_state; | |
1203 | ||
d9d82081 | 1204 | if (IS_845G(dev) || IS_I865G(dev)) |
93ce0ba6 | 1205 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; |
d9d82081 | 1206 | else |
5efb3e28 | 1207 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 JN |
1208 | |
1209 | WARN(cur_state != state, | |
1210 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", | |
1211 | pipe_name(pipe), state_string(state), state_string(cur_state)); | |
1212 | } | |
1213 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1214 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1215 | ||
b840d907 JB |
1216 | void assert_pipe(struct drm_i915_private *dev_priv, |
1217 | enum pipe pipe, bool state) | |
b24e7179 JB |
1218 | { |
1219 | int reg; | |
1220 | u32 val; | |
63d7bbe9 | 1221 | bool cur_state; |
702e7a56 PZ |
1222 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1223 | pipe); | |
b24e7179 | 1224 | |
b6b5d049 VS |
1225 | /* if we need the pipe quirk it must be always on */ |
1226 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1227 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1228 | state = true; |
1229 | ||
f458ebbc | 1230 | if (!intel_display_power_is_enabled(dev_priv, |
b97186f0 | 1231 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
69310161 PZ |
1232 | cur_state = false; |
1233 | } else { | |
1234 | reg = PIPECONF(cpu_transcoder); | |
1235 | val = I915_READ(reg); | |
1236 | cur_state = !!(val & PIPECONF_ENABLE); | |
1237 | } | |
1238 | ||
63d7bbe9 JB |
1239 | WARN(cur_state != state, |
1240 | "pipe %c assertion failure (expected %s, current %s)\n", | |
9db4a9c7 | 1241 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1242 | } |
1243 | ||
931872fc CW |
1244 | static void assert_plane(struct drm_i915_private *dev_priv, |
1245 | enum plane plane, bool state) | |
b24e7179 JB |
1246 | { |
1247 | int reg; | |
1248 | u32 val; | |
931872fc | 1249 | bool cur_state; |
b24e7179 JB |
1250 | |
1251 | reg = DSPCNTR(plane); | |
1252 | val = I915_READ(reg); | |
931872fc CW |
1253 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
1254 | WARN(cur_state != state, | |
1255 | "plane %c assertion failure (expected %s, current %s)\n", | |
1256 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1257 | } |
1258 | ||
931872fc CW |
1259 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1260 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1261 | ||
b24e7179 JB |
1262 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1263 | enum pipe pipe) | |
1264 | { | |
653e1026 | 1265 | struct drm_device *dev = dev_priv->dev; |
b24e7179 JB |
1266 | int reg, i; |
1267 | u32 val; | |
1268 | int cur_pipe; | |
1269 | ||
653e1026 VS |
1270 | /* Primary planes are fixed to pipes on gen4+ */ |
1271 | if (INTEL_INFO(dev)->gen >= 4) { | |
28c05794 AJ |
1272 | reg = DSPCNTR(pipe); |
1273 | val = I915_READ(reg); | |
83f26f16 | 1274 | WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1275 | "plane %c assertion failure, should be disabled but not\n", |
1276 | plane_name(pipe)); | |
19ec1358 | 1277 | return; |
28c05794 | 1278 | } |
19ec1358 | 1279 | |
b24e7179 | 1280 | /* Need to check both planes against the pipe */ |
055e393f | 1281 | for_each_pipe(dev_priv, i) { |
b24e7179 JB |
1282 | reg = DSPCNTR(i); |
1283 | val = I915_READ(reg); | |
1284 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1285 | DISPPLANE_SEL_PIPE_SHIFT; | |
1286 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, | |
9db4a9c7 JB |
1287 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1288 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1289 | } |
1290 | } | |
1291 | ||
19332d7a JB |
1292 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1293 | enum pipe pipe) | |
1294 | { | |
20674eef | 1295 | struct drm_device *dev = dev_priv->dev; |
1fe47785 | 1296 | int reg, sprite; |
19332d7a JB |
1297 | u32 val; |
1298 | ||
7feb8b88 DL |
1299 | if (INTEL_INFO(dev)->gen >= 9) { |
1300 | for_each_sprite(pipe, sprite) { | |
1301 | val = I915_READ(PLANE_CTL(pipe, sprite)); | |
1302 | WARN(val & PLANE_CTL_ENABLE, | |
1303 | "plane %d assertion failure, should be off on pipe %c but is still active\n", | |
1304 | sprite, pipe_name(pipe)); | |
1305 | } | |
1306 | } else if (IS_VALLEYVIEW(dev)) { | |
1fe47785 DL |
1307 | for_each_sprite(pipe, sprite) { |
1308 | reg = SPCNTR(pipe, sprite); | |
20674eef | 1309 | val = I915_READ(reg); |
83f26f16 | 1310 | WARN(val & SP_ENABLE, |
20674eef | 1311 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1312 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1313 | } |
1314 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
1315 | reg = SPRCTL(pipe); | |
19332d7a | 1316 | val = I915_READ(reg); |
83f26f16 | 1317 | WARN(val & SPRITE_ENABLE, |
06da8da2 | 1318 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1319 | plane_name(pipe), pipe_name(pipe)); |
1320 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
1321 | reg = DVSCNTR(pipe); | |
19332d7a | 1322 | val = I915_READ(reg); |
83f26f16 | 1323 | WARN(val & DVS_ENABLE, |
06da8da2 | 1324 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1325 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1326 | } |
1327 | } | |
1328 | ||
08c71e5e VS |
1329 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1330 | { | |
1331 | if (WARN_ON(drm_crtc_vblank_get(crtc) == 0)) | |
1332 | drm_crtc_vblank_put(crtc); | |
1333 | } | |
1334 | ||
89eff4be | 1335 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1336 | { |
1337 | u32 val; | |
1338 | bool enabled; | |
1339 | ||
89eff4be | 1340 | WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1341 | |
92f2584a JB |
1342 | val = I915_READ(PCH_DREF_CONTROL); |
1343 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1344 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
1345 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); | |
1346 | } | |
1347 | ||
ab9412ba DV |
1348 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1349 | enum pipe pipe) | |
92f2584a JB |
1350 | { |
1351 | int reg; | |
1352 | u32 val; | |
1353 | bool enabled; | |
1354 | ||
ab9412ba | 1355 | reg = PCH_TRANSCONF(pipe); |
92f2584a JB |
1356 | val = I915_READ(reg); |
1357 | enabled = !!(val & TRANS_ENABLE); | |
9db4a9c7 JB |
1358 | WARN(enabled, |
1359 | "transcoder assertion failed, should be off on pipe %c but is still active\n", | |
1360 | pipe_name(pipe)); | |
92f2584a JB |
1361 | } |
1362 | ||
4e634389 KP |
1363 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1364 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1365 | { |
1366 | if ((val & DP_PORT_EN) == 0) | |
1367 | return false; | |
1368 | ||
1369 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1370 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1371 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1372 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1373 | return false; | |
44f37d1f CML |
1374 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1375 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1376 | return false; | |
f0575e92 KP |
1377 | } else { |
1378 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1379 | return false; | |
1380 | } | |
1381 | return true; | |
1382 | } | |
1383 | ||
1519b995 KP |
1384 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1385 | enum pipe pipe, u32 val) | |
1386 | { | |
dc0fa718 | 1387 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1388 | return false; |
1389 | ||
1390 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1391 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1392 | return false; |
44f37d1f CML |
1393 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1394 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1395 | return false; | |
1519b995 | 1396 | } else { |
dc0fa718 | 1397 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1398 | return false; |
1399 | } | |
1400 | return true; | |
1401 | } | |
1402 | ||
1403 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1404 | enum pipe pipe, u32 val) | |
1405 | { | |
1406 | if ((val & LVDS_PORT_EN) == 0) | |
1407 | return false; | |
1408 | ||
1409 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1410 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1411 | return false; | |
1412 | } else { | |
1413 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1414 | return false; | |
1415 | } | |
1416 | return true; | |
1417 | } | |
1418 | ||
1419 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1420 | enum pipe pipe, u32 val) | |
1421 | { | |
1422 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1423 | return false; | |
1424 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1425 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1426 | return false; | |
1427 | } else { | |
1428 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1429 | return false; | |
1430 | } | |
1431 | return true; | |
1432 | } | |
1433 | ||
291906f1 | 1434 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1435 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1436 | { |
47a05eca | 1437 | u32 val = I915_READ(reg); |
4e634389 | 1438 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1439 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1440 | reg, pipe_name(pipe)); |
de9a35ab | 1441 | |
75c5da27 DV |
1442 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
1443 | && (val & DP_PIPEB_SELECT), | |
de9a35ab | 1444 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1445 | } |
1446 | ||
1447 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1448 | enum pipe pipe, int reg) | |
1449 | { | |
47a05eca | 1450 | u32 val = I915_READ(reg); |
b70ad586 | 1451 | WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1452 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1453 | reg, pipe_name(pipe)); |
de9a35ab | 1454 | |
dc0fa718 | 1455 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1456 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1457 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1458 | } |
1459 | ||
1460 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1461 | enum pipe pipe) | |
1462 | { | |
1463 | int reg; | |
1464 | u32 val; | |
291906f1 | 1465 | |
f0575e92 KP |
1466 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1467 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1468 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1469 | |
1470 | reg = PCH_ADPA; | |
1471 | val = I915_READ(reg); | |
b70ad586 | 1472 | WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1473 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1474 | pipe_name(pipe)); |
291906f1 JB |
1475 | |
1476 | reg = PCH_LVDS; | |
1477 | val = I915_READ(reg); | |
b70ad586 | 1478 | WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1479 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1480 | pipe_name(pipe)); |
291906f1 | 1481 | |
e2debe91 PZ |
1482 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1483 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1484 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1485 | } |
1486 | ||
40e9cf64 JB |
1487 | static void intel_init_dpio(struct drm_device *dev) |
1488 | { | |
1489 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1490 | ||
1491 | if (!IS_VALLEYVIEW(dev)) | |
1492 | return; | |
1493 | ||
a09caddd CML |
1494 | /* |
1495 | * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C), | |
1496 | * CHV x1 PHY (DP/HDMI D) | |
1497 | * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C) | |
1498 | */ | |
1499 | if (IS_CHERRYVIEW(dev)) { | |
1500 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2; | |
1501 | DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO; | |
1502 | } else { | |
1503 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; | |
1504 | } | |
5382f5f3 JB |
1505 | } |
1506 | ||
d288f65f VS |
1507 | static void vlv_enable_pll(struct intel_crtc *crtc, |
1508 | const struct intel_crtc_config *pipe_config) | |
87442f73 | 1509 | { |
426115cf DV |
1510 | struct drm_device *dev = crtc->base.dev; |
1511 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1512 | int reg = DPLL(crtc->pipe); | |
d288f65f | 1513 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
87442f73 | 1514 | |
426115cf | 1515 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 DV |
1516 | |
1517 | /* No really, not for ILK+ */ | |
1518 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); | |
1519 | ||
1520 | /* PLL is protected by panel, make sure we can write it */ | |
6a9e7363 | 1521 | if (IS_MOBILE(dev_priv->dev)) |
426115cf | 1522 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1523 | |
426115cf DV |
1524 | I915_WRITE(reg, dpll); |
1525 | POSTING_READ(reg); | |
1526 | udelay(150); | |
1527 | ||
1528 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1529 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1530 | ||
d288f65f | 1531 | I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); |
426115cf | 1532 | POSTING_READ(DPLL_MD(crtc->pipe)); |
87442f73 DV |
1533 | |
1534 | /* We do this three times for luck */ | |
426115cf | 1535 | I915_WRITE(reg, dpll); |
87442f73 DV |
1536 | POSTING_READ(reg); |
1537 | udelay(150); /* wait for warmup */ | |
426115cf | 1538 | I915_WRITE(reg, dpll); |
87442f73 DV |
1539 | POSTING_READ(reg); |
1540 | udelay(150); /* wait for warmup */ | |
426115cf | 1541 | I915_WRITE(reg, dpll); |
87442f73 DV |
1542 | POSTING_READ(reg); |
1543 | udelay(150); /* wait for warmup */ | |
1544 | } | |
1545 | ||
d288f65f VS |
1546 | static void chv_enable_pll(struct intel_crtc *crtc, |
1547 | const struct intel_crtc_config *pipe_config) | |
9d556c99 CML |
1548 | { |
1549 | struct drm_device *dev = crtc->base.dev; | |
1550 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1551 | int pipe = crtc->pipe; | |
1552 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9d556c99 CML |
1553 | u32 tmp; |
1554 | ||
1555 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1556 | ||
1557 | BUG_ON(!IS_CHERRYVIEW(dev_priv->dev)); | |
1558 | ||
1559 | mutex_lock(&dev_priv->dpio_lock); | |
1560 | ||
1561 | /* Enable back the 10bit clock to display controller */ | |
1562 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1563 | tmp |= DPIO_DCLKP_EN; | |
1564 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1565 | ||
1566 | /* | |
1567 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1568 | */ | |
1569 | udelay(1); | |
1570 | ||
1571 | /* Enable PLL */ | |
d288f65f | 1572 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1573 | |
1574 | /* Check PLL is locked */ | |
a11b0703 | 1575 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1576 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1577 | ||
a11b0703 | 1578 | /* not sure when this should be written */ |
d288f65f | 1579 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
a11b0703 VS |
1580 | POSTING_READ(DPLL_MD(pipe)); |
1581 | ||
9d556c99 CML |
1582 | mutex_unlock(&dev_priv->dpio_lock); |
1583 | } | |
1584 | ||
1c4e0274 VS |
1585 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1586 | { | |
1587 | struct intel_crtc *crtc; | |
1588 | int count = 0; | |
1589 | ||
1590 | for_each_intel_crtc(dev, crtc) | |
1591 | count += crtc->active && | |
409ee761 | 1592 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); |
1c4e0274 VS |
1593 | |
1594 | return count; | |
1595 | } | |
1596 | ||
66e3d5c0 | 1597 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1598 | { |
66e3d5c0 DV |
1599 | struct drm_device *dev = crtc->base.dev; |
1600 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1601 | int reg = DPLL(crtc->pipe); | |
1602 | u32 dpll = crtc->config.dpll_hw_state.dpll; | |
63d7bbe9 | 1603 | |
66e3d5c0 | 1604 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1605 | |
63d7bbe9 | 1606 | /* No really, not for ILK+ */ |
3d13ef2e | 1607 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1608 | |
1609 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1610 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1611 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1612 | |
1c4e0274 VS |
1613 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1614 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1615 | /* | |
1616 | * It appears to be important that we don't enable this | |
1617 | * for the current pipe before otherwise configuring the | |
1618 | * PLL. No idea how this should be handled if multiple | |
1619 | * DVO outputs are enabled simultaneosly. | |
1620 | */ | |
1621 | dpll |= DPLL_DVO_2X_MODE; | |
1622 | I915_WRITE(DPLL(!crtc->pipe), | |
1623 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1624 | } | |
66e3d5c0 DV |
1625 | |
1626 | /* Wait for the clocks to stabilize. */ | |
1627 | POSTING_READ(reg); | |
1628 | udelay(150); | |
1629 | ||
1630 | if (INTEL_INFO(dev)->gen >= 4) { | |
1631 | I915_WRITE(DPLL_MD(crtc->pipe), | |
1632 | crtc->config.dpll_hw_state.dpll_md); | |
1633 | } else { | |
1634 | /* The pixel multiplier can only be updated once the | |
1635 | * DPLL is enabled and the clocks are stable. | |
1636 | * | |
1637 | * So write it again. | |
1638 | */ | |
1639 | I915_WRITE(reg, dpll); | |
1640 | } | |
63d7bbe9 JB |
1641 | |
1642 | /* We do this three times for luck */ | |
66e3d5c0 | 1643 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1644 | POSTING_READ(reg); |
1645 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1646 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1647 | POSTING_READ(reg); |
1648 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1649 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1650 | POSTING_READ(reg); |
1651 | udelay(150); /* wait for warmup */ | |
1652 | } | |
1653 | ||
1654 | /** | |
50b44a44 | 1655 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1656 | * @dev_priv: i915 private structure |
1657 | * @pipe: pipe PLL to disable | |
1658 | * | |
1659 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1660 | * | |
1661 | * Note! This is for pre-ILK only. | |
1662 | */ | |
1c4e0274 | 1663 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1664 | { |
1c4e0274 VS |
1665 | struct drm_device *dev = crtc->base.dev; |
1666 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1667 | enum pipe pipe = crtc->pipe; | |
1668 | ||
1669 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1670 | if (IS_I830(dev) && | |
409ee761 | 1671 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && |
1c4e0274 VS |
1672 | intel_num_dvo_pipes(dev) == 1) { |
1673 | I915_WRITE(DPLL(PIPE_B), | |
1674 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1675 | I915_WRITE(DPLL(PIPE_A), | |
1676 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1677 | } | |
1678 | ||
b6b5d049 VS |
1679 | /* Don't disable pipe or pipe PLLs if needed */ |
1680 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1681 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1682 | return; |
1683 | ||
1684 | /* Make sure the pipe isn't still relying on us */ | |
1685 | assert_pipe_disabled(dev_priv, pipe); | |
1686 | ||
50b44a44 DV |
1687 | I915_WRITE(DPLL(pipe), 0); |
1688 | POSTING_READ(DPLL(pipe)); | |
63d7bbe9 JB |
1689 | } |
1690 | ||
f6071166 JB |
1691 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1692 | { | |
1693 | u32 val = 0; | |
1694 | ||
1695 | /* Make sure the pipe isn't still relying on us */ | |
1696 | assert_pipe_disabled(dev_priv, pipe); | |
1697 | ||
e5cbfbfb ID |
1698 | /* |
1699 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1700 | * The latter is needed for VGA hotplug / manual detection. | |
1701 | */ | |
f6071166 | 1702 | if (pipe == PIPE_B) |
e5cbfbfb | 1703 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV; |
f6071166 JB |
1704 | I915_WRITE(DPLL(pipe), val); |
1705 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1706 | |
1707 | } | |
1708 | ||
1709 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1710 | { | |
d752048d | 1711 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1712 | u32 val; |
1713 | ||
a11b0703 VS |
1714 | /* Make sure the pipe isn't still relying on us */ |
1715 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1716 | |
a11b0703 | 1717 | /* Set PLL en = 0 */ |
d17ec4ce | 1718 | val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV; |
a11b0703 VS |
1719 | if (pipe != PIPE_A) |
1720 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1721 | I915_WRITE(DPLL(pipe), val); | |
1722 | POSTING_READ(DPLL(pipe)); | |
d752048d VS |
1723 | |
1724 | mutex_lock(&dev_priv->dpio_lock); | |
1725 | ||
1726 | /* Disable 10bit clock to display controller */ | |
1727 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1728 | val &= ~DPIO_DCLKP_EN; | |
1729 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1730 | ||
61407f6d VS |
1731 | /* disable left/right clock distribution */ |
1732 | if (pipe != PIPE_B) { | |
1733 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); | |
1734 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); | |
1735 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); | |
1736 | } else { | |
1737 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); | |
1738 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); | |
1739 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); | |
1740 | } | |
1741 | ||
d752048d | 1742 | mutex_unlock(&dev_priv->dpio_lock); |
f6071166 JB |
1743 | } |
1744 | ||
e4607fcf CML |
1745 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
1746 | struct intel_digital_port *dport) | |
89b667f8 JB |
1747 | { |
1748 | u32 port_mask; | |
00fc31b7 | 1749 | int dpll_reg; |
89b667f8 | 1750 | |
e4607fcf CML |
1751 | switch (dport->port) { |
1752 | case PORT_B: | |
89b667f8 | 1753 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1754 | dpll_reg = DPLL(0); |
e4607fcf CML |
1755 | break; |
1756 | case PORT_C: | |
89b667f8 | 1757 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 CML |
1758 | dpll_reg = DPLL(0); |
1759 | break; | |
1760 | case PORT_D: | |
1761 | port_mask = DPLL_PORTD_READY_MASK; | |
1762 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1763 | break; |
1764 | default: | |
1765 | BUG(); | |
1766 | } | |
89b667f8 | 1767 | |
00fc31b7 | 1768 | if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000)) |
89b667f8 | 1769 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", |
00fc31b7 | 1770 | port_name(dport->port), I915_READ(dpll_reg)); |
89b667f8 JB |
1771 | } |
1772 | ||
b14b1055 DV |
1773 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
1774 | { | |
1775 | struct drm_device *dev = crtc->base.dev; | |
1776 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1777 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
1778 | ||
be19f0ff CW |
1779 | if (WARN_ON(pll == NULL)) |
1780 | return; | |
1781 | ||
3e369b76 | 1782 | WARN_ON(!pll->config.crtc_mask); |
b14b1055 DV |
1783 | if (pll->active == 0) { |
1784 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); | |
1785 | WARN_ON(pll->on); | |
1786 | assert_shared_dpll_disabled(dev_priv, pll); | |
1787 | ||
1788 | pll->mode_set(dev_priv, pll); | |
1789 | } | |
1790 | } | |
1791 | ||
92f2584a | 1792 | /** |
85b3894f | 1793 | * intel_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1794 | * @dev_priv: i915 private structure |
1795 | * @pipe: pipe PLL to enable | |
1796 | * | |
1797 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1798 | * drives the transcoder clock. | |
1799 | */ | |
85b3894f | 1800 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1801 | { |
3d13ef2e DL |
1802 | struct drm_device *dev = crtc->base.dev; |
1803 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1804 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1805 | |
87a875bb | 1806 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1807 | return; |
1808 | ||
3e369b76 | 1809 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1810 | return; |
ee7b9f93 | 1811 | |
74dd6928 | 1812 | DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n", |
46edb027 | 1813 | pll->name, pll->active, pll->on, |
e2b78267 | 1814 | crtc->base.base.id); |
92f2584a | 1815 | |
cdbd2316 DV |
1816 | if (pll->active++) { |
1817 | WARN_ON(!pll->on); | |
e9d6944e | 1818 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1819 | return; |
1820 | } | |
f4a091c7 | 1821 | WARN_ON(pll->on); |
ee7b9f93 | 1822 | |
bd2bb1b9 PZ |
1823 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
1824 | ||
46edb027 | 1825 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1826 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1827 | pll->on = true; |
92f2584a JB |
1828 | } |
1829 | ||
f6daaec2 | 1830 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1831 | { |
3d13ef2e DL |
1832 | struct drm_device *dev = crtc->base.dev; |
1833 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1834 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1835 | |
92f2584a | 1836 | /* PCH only available on ILK+ */ |
3d13ef2e | 1837 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
87a875bb | 1838 | if (WARN_ON(pll == NULL)) |
ee7b9f93 | 1839 | return; |
92f2584a | 1840 | |
3e369b76 | 1841 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1842 | return; |
7a419866 | 1843 | |
46edb027 DV |
1844 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1845 | pll->name, pll->active, pll->on, | |
e2b78267 | 1846 | crtc->base.base.id); |
7a419866 | 1847 | |
48da64a8 | 1848 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1849 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1850 | return; |
1851 | } | |
1852 | ||
e9d6944e | 1853 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1854 | WARN_ON(!pll->on); |
cdbd2316 | 1855 | if (--pll->active) |
7a419866 | 1856 | return; |
ee7b9f93 | 1857 | |
46edb027 | 1858 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1859 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1860 | pll->on = false; |
bd2bb1b9 PZ |
1861 | |
1862 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
92f2584a JB |
1863 | } |
1864 | ||
b8a4f404 PZ |
1865 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1866 | enum pipe pipe) | |
040484af | 1867 | { |
23670b32 | 1868 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1869 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1870 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
23670b32 | 1871 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1872 | |
1873 | /* PCH only available on ILK+ */ | |
55522f37 | 1874 | BUG_ON(!HAS_PCH_SPLIT(dev)); |
040484af JB |
1875 | |
1876 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1877 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1878 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1879 | |
1880 | /* FDI must be feeding us bits for PCH ports */ | |
1881 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1882 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1883 | ||
23670b32 DV |
1884 | if (HAS_PCH_CPT(dev)) { |
1885 | /* Workaround: Set the timing override bit before enabling the | |
1886 | * pch transcoder. */ | |
1887 | reg = TRANS_CHICKEN2(pipe); | |
1888 | val = I915_READ(reg); | |
1889 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1890 | I915_WRITE(reg, val); | |
59c859d6 | 1891 | } |
23670b32 | 1892 | |
ab9412ba | 1893 | reg = PCH_TRANSCONF(pipe); |
040484af | 1894 | val = I915_READ(reg); |
5f7f726d | 1895 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1896 | |
1897 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1898 | /* | |
1899 | * make the BPC in transcoder be consistent with | |
1900 | * that in pipeconf reg. | |
1901 | */ | |
dfd07d72 DV |
1902 | val &= ~PIPECONF_BPC_MASK; |
1903 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1904 | } |
5f7f726d PZ |
1905 | |
1906 | val &= ~TRANS_INTERLACE_MASK; | |
1907 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 | 1908 | if (HAS_PCH_IBX(dev_priv->dev) && |
409ee761 | 1909 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
1910 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1911 | else | |
1912 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1913 | else |
1914 | val |= TRANS_PROGRESSIVE; | |
1915 | ||
040484af JB |
1916 | I915_WRITE(reg, val | TRANS_ENABLE); |
1917 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 1918 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1919 | } |
1920 | ||
8fb033d7 | 1921 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1922 | enum transcoder cpu_transcoder) |
040484af | 1923 | { |
8fb033d7 | 1924 | u32 val, pipeconf_val; |
8fb033d7 PZ |
1925 | |
1926 | /* PCH only available on ILK+ */ | |
55522f37 | 1927 | BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev)); |
8fb033d7 | 1928 | |
8fb033d7 | 1929 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1930 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1931 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1932 | |
223a6fdf PZ |
1933 | /* Workaround: set timing override bit. */ |
1934 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1935 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf PZ |
1936 | I915_WRITE(_TRANSA_CHICKEN2, val); |
1937 | ||
25f3ef11 | 1938 | val = TRANS_ENABLE; |
937bb610 | 1939 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1940 | |
9a76b1c6 PZ |
1941 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1942 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1943 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1944 | else |
1945 | val |= TRANS_PROGRESSIVE; | |
1946 | ||
ab9412ba DV |
1947 | I915_WRITE(LPT_TRANSCONF, val); |
1948 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 1949 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1950 | } |
1951 | ||
b8a4f404 PZ |
1952 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1953 | enum pipe pipe) | |
040484af | 1954 | { |
23670b32 DV |
1955 | struct drm_device *dev = dev_priv->dev; |
1956 | uint32_t reg, val; | |
040484af JB |
1957 | |
1958 | /* FDI relies on the transcoder */ | |
1959 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1960 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1961 | ||
291906f1 JB |
1962 | /* Ports must be off as well */ |
1963 | assert_pch_ports_disabled(dev_priv, pipe); | |
1964 | ||
ab9412ba | 1965 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1966 | val = I915_READ(reg); |
1967 | val &= ~TRANS_ENABLE; | |
1968 | I915_WRITE(reg, val); | |
1969 | /* wait for PCH transcoder off, transcoder state */ | |
1970 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 1971 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 DV |
1972 | |
1973 | if (!HAS_PCH_IBX(dev)) { | |
1974 | /* Workaround: Clear the timing override chicken bit again. */ | |
1975 | reg = TRANS_CHICKEN2(pipe); | |
1976 | val = I915_READ(reg); | |
1977 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1978 | I915_WRITE(reg, val); | |
1979 | } | |
040484af JB |
1980 | } |
1981 | ||
ab4d966c | 1982 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1983 | { |
8fb033d7 PZ |
1984 | u32 val; |
1985 | ||
ab9412ba | 1986 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1987 | val &= ~TRANS_ENABLE; |
ab9412ba | 1988 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1989 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 1990 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 1991 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1992 | |
1993 | /* Workaround: clear timing override bit. */ | |
1994 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1995 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf | 1996 | I915_WRITE(_TRANSA_CHICKEN2, val); |
040484af JB |
1997 | } |
1998 | ||
b24e7179 | 1999 | /** |
309cfea8 | 2000 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 2001 | * @crtc: crtc responsible for the pipe |
b24e7179 | 2002 | * |
0372264a | 2003 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 2004 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 2005 | */ |
e1fdc473 | 2006 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2007 | { |
0372264a PZ |
2008 | struct drm_device *dev = crtc->base.dev; |
2009 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2010 | enum pipe pipe = crtc->pipe; | |
702e7a56 PZ |
2011 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
2012 | pipe); | |
1a240d4d | 2013 | enum pipe pch_transcoder; |
b24e7179 JB |
2014 | int reg; |
2015 | u32 val; | |
2016 | ||
58c6eaa2 | 2017 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 2018 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
2019 | assert_sprites_disabled(dev_priv, pipe); |
2020 | ||
681e5811 | 2021 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
2022 | pch_transcoder = TRANSCODER_A; |
2023 | else | |
2024 | pch_transcoder = pipe; | |
2025 | ||
b24e7179 JB |
2026 | /* |
2027 | * A pipe without a PLL won't actually be able to drive bits from | |
2028 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
2029 | * need the check. | |
2030 | */ | |
2031 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
409ee761 | 2032 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
2033 | assert_dsi_pll_enabled(dev_priv); |
2034 | else | |
2035 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 2036 | else { |
30421c4f | 2037 | if (crtc->config.has_pch_encoder) { |
040484af | 2038 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 2039 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
2040 | assert_fdi_tx_pll_enabled(dev_priv, |
2041 | (enum pipe) cpu_transcoder); | |
040484af JB |
2042 | } |
2043 | /* FIXME: assert CPU port conditions for SNB+ */ | |
2044 | } | |
b24e7179 | 2045 | |
702e7a56 | 2046 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2047 | val = I915_READ(reg); |
7ad25d48 | 2048 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
2049 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
2050 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 2051 | return; |
7ad25d48 | 2052 | } |
00d70b15 CW |
2053 | |
2054 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2055 | POSTING_READ(reg); |
b24e7179 JB |
2056 | } |
2057 | ||
2058 | /** | |
309cfea8 | 2059 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2060 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2061 | * |
575f7ab7 VS |
2062 | * Disable the pipe of @crtc, making sure that various hardware |
2063 | * specific requirements are met, if applicable, e.g. plane | |
2064 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2065 | * |
2066 | * Will wait until the pipe has shut down before returning. | |
2067 | */ | |
575f7ab7 | 2068 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2069 | { |
575f7ab7 VS |
2070 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
2071 | enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; | |
2072 | enum pipe pipe = crtc->pipe; | |
b24e7179 JB |
2073 | int reg; |
2074 | u32 val; | |
2075 | ||
2076 | /* | |
2077 | * Make sure planes won't keep trying to pump pixels to us, | |
2078 | * or we might hang the display. | |
2079 | */ | |
2080 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2081 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2082 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2083 | |
702e7a56 | 2084 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2085 | val = I915_READ(reg); |
00d70b15 CW |
2086 | if ((val & PIPECONF_ENABLE) == 0) |
2087 | return; | |
2088 | ||
67adc644 VS |
2089 | /* |
2090 | * Double wide has implications for planes | |
2091 | * so best keep it disabled when not needed. | |
2092 | */ | |
2093 | if (crtc->config.double_wide) | |
2094 | val &= ~PIPECONF_DOUBLE_WIDE; | |
2095 | ||
2096 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2097 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2098 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2099 | val &= ~PIPECONF_ENABLE; |
2100 | ||
2101 | I915_WRITE(reg, val); | |
2102 | if ((val & PIPECONF_ENABLE) == 0) | |
2103 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2104 | } |
2105 | ||
d74362c9 KP |
2106 | /* |
2107 | * Plane regs are double buffered, going from enabled->disabled needs a | |
2108 | * trigger in order to latch. The display address reg provides this. | |
2109 | */ | |
1dba99f4 VS |
2110 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
2111 | enum plane plane) | |
d74362c9 | 2112 | { |
3d13ef2e DL |
2113 | struct drm_device *dev = dev_priv->dev; |
2114 | u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); | |
1dba99f4 VS |
2115 | |
2116 | I915_WRITE(reg, I915_READ(reg)); | |
2117 | POSTING_READ(reg); | |
d74362c9 KP |
2118 | } |
2119 | ||
b24e7179 | 2120 | /** |
262ca2b0 | 2121 | * intel_enable_primary_hw_plane - enable the primary plane on a given pipe |
fdd508a6 VS |
2122 | * @plane: plane to be enabled |
2123 | * @crtc: crtc for the plane | |
b24e7179 | 2124 | * |
fdd508a6 | 2125 | * Enable @plane on @crtc, making sure that the pipe is running first. |
b24e7179 | 2126 | */ |
fdd508a6 VS |
2127 | static void intel_enable_primary_hw_plane(struct drm_plane *plane, |
2128 | struct drm_crtc *crtc) | |
b24e7179 | 2129 | { |
fdd508a6 VS |
2130 | struct drm_device *dev = plane->dev; |
2131 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2132 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b24e7179 JB |
2133 | |
2134 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
fdd508a6 | 2135 | assert_pipe_enabled(dev_priv, intel_crtc->pipe); |
b24e7179 | 2136 | |
98ec7739 VS |
2137 | if (intel_crtc->primary_enabled) |
2138 | return; | |
0037f71c | 2139 | |
4c445e0e | 2140 | intel_crtc->primary_enabled = true; |
939c2fe8 | 2141 | |
fdd508a6 VS |
2142 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
2143 | crtc->x, crtc->y); | |
33c3b0d1 VS |
2144 | |
2145 | /* | |
2146 | * BDW signals flip done immediately if the plane | |
2147 | * is disabled, even if the plane enable is already | |
2148 | * armed to occur at the next vblank :( | |
2149 | */ | |
2150 | if (IS_BROADWELL(dev)) | |
2151 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
b24e7179 JB |
2152 | } |
2153 | ||
b24e7179 | 2154 | /** |
262ca2b0 | 2155 | * intel_disable_primary_hw_plane - disable the primary hardware plane |
fdd508a6 VS |
2156 | * @plane: plane to be disabled |
2157 | * @crtc: crtc for the plane | |
b24e7179 | 2158 | * |
fdd508a6 | 2159 | * Disable @plane on @crtc, making sure that the pipe is running first. |
b24e7179 | 2160 | */ |
fdd508a6 VS |
2161 | static void intel_disable_primary_hw_plane(struct drm_plane *plane, |
2162 | struct drm_crtc *crtc) | |
b24e7179 | 2163 | { |
fdd508a6 VS |
2164 | struct drm_device *dev = plane->dev; |
2165 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2166 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2167 | ||
2168 | assert_pipe_enabled(dev_priv, intel_crtc->pipe); | |
b24e7179 | 2169 | |
98ec7739 VS |
2170 | if (!intel_crtc->primary_enabled) |
2171 | return; | |
0037f71c | 2172 | |
4c445e0e | 2173 | intel_crtc->primary_enabled = false; |
939c2fe8 | 2174 | |
fdd508a6 VS |
2175 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
2176 | crtc->x, crtc->y); | |
b24e7179 JB |
2177 | } |
2178 | ||
693db184 CW |
2179 | static bool need_vtd_wa(struct drm_device *dev) |
2180 | { | |
2181 | #ifdef CONFIG_INTEL_IOMMU | |
2182 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2183 | return true; | |
2184 | #endif | |
2185 | return false; | |
2186 | } | |
2187 | ||
a57ce0b2 JB |
2188 | static int intel_align_height(struct drm_device *dev, int height, bool tiled) |
2189 | { | |
2190 | int tile_height; | |
2191 | ||
2192 | tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1; | |
2193 | return ALIGN(height, tile_height); | |
2194 | } | |
2195 | ||
127bd2ac | 2196 | int |
850c4cdc TU |
2197 | intel_pin_and_fence_fb_obj(struct drm_plane *plane, |
2198 | struct drm_framebuffer *fb, | |
a4872ba6 | 2199 | struct intel_engine_cs *pipelined) |
6b95a207 | 2200 | { |
850c4cdc | 2201 | struct drm_device *dev = fb->dev; |
ce453d81 | 2202 | struct drm_i915_private *dev_priv = dev->dev_private; |
850c4cdc | 2203 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 KH |
2204 | u32 alignment; |
2205 | int ret; | |
2206 | ||
ebcdd39e MR |
2207 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2208 | ||
05394f39 | 2209 | switch (obj->tiling_mode) { |
6b95a207 | 2210 | case I915_TILING_NONE: |
1fada4cc DL |
2211 | if (INTEL_INFO(dev)->gen >= 9) |
2212 | alignment = 256 * 1024; | |
2213 | else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) | |
534843da | 2214 | alignment = 128 * 1024; |
a6c45cf0 | 2215 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
2216 | alignment = 4 * 1024; |
2217 | else | |
2218 | alignment = 64 * 1024; | |
6b95a207 KH |
2219 | break; |
2220 | case I915_TILING_X: | |
1fada4cc DL |
2221 | if (INTEL_INFO(dev)->gen >= 9) |
2222 | alignment = 256 * 1024; | |
2223 | else { | |
2224 | /* pin() will align the object as required by fence */ | |
2225 | alignment = 0; | |
2226 | } | |
6b95a207 KH |
2227 | break; |
2228 | case I915_TILING_Y: | |
80075d49 | 2229 | WARN(1, "Y tiled bo slipped through, driver bug!\n"); |
6b95a207 KH |
2230 | return -EINVAL; |
2231 | default: | |
2232 | BUG(); | |
2233 | } | |
2234 | ||
693db184 CW |
2235 | /* Note that the w/a also requires 64 PTE of padding following the |
2236 | * bo. We currently fill all unused PTE with the shadow page and so | |
2237 | * we should always have valid PTE following the scanout preventing | |
2238 | * the VT-d warning. | |
2239 | */ | |
2240 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2241 | alignment = 256 * 1024; | |
2242 | ||
d6dd6843 PZ |
2243 | /* |
2244 | * Global gtt pte registers are special registers which actually forward | |
2245 | * writes to a chunk of system memory. Which means that there is no risk | |
2246 | * that the register values disappear as soon as we call | |
2247 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2248 | * pin/unpin/fence and not more. | |
2249 | */ | |
2250 | intel_runtime_pm_get(dev_priv); | |
2251 | ||
ce453d81 | 2252 | dev_priv->mm.interruptible = false; |
2da3b9b9 | 2253 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
48b956c5 | 2254 | if (ret) |
ce453d81 | 2255 | goto err_interruptible; |
6b95a207 KH |
2256 | |
2257 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2258 | * fence, whereas 965+ only requires a fence if using | |
2259 | * framebuffer compression. For simplicity, we always install | |
2260 | * a fence as the cost is not that onerous. | |
2261 | */ | |
06d98131 | 2262 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
2263 | if (ret) |
2264 | goto err_unpin; | |
1690e1eb | 2265 | |
9a5a53b3 | 2266 | i915_gem_object_pin_fence(obj); |
6b95a207 | 2267 | |
ce453d81 | 2268 | dev_priv->mm.interruptible = true; |
d6dd6843 | 2269 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2270 | return 0; |
48b956c5 CW |
2271 | |
2272 | err_unpin: | |
cc98b413 | 2273 | i915_gem_object_unpin_from_display_plane(obj); |
ce453d81 CW |
2274 | err_interruptible: |
2275 | dev_priv->mm.interruptible = true; | |
d6dd6843 | 2276 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2277 | return ret; |
6b95a207 KH |
2278 | } |
2279 | ||
1690e1eb CW |
2280 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
2281 | { | |
ebcdd39e MR |
2282 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2283 | ||
1690e1eb | 2284 | i915_gem_object_unpin_fence(obj); |
cc98b413 | 2285 | i915_gem_object_unpin_from_display_plane(obj); |
1690e1eb CW |
2286 | } |
2287 | ||
c2c75131 DV |
2288 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2289 | * is assumed to be a power-of-two. */ | |
bc752862 CW |
2290 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
2291 | unsigned int tiling_mode, | |
2292 | unsigned int cpp, | |
2293 | unsigned int pitch) | |
c2c75131 | 2294 | { |
bc752862 CW |
2295 | if (tiling_mode != I915_TILING_NONE) { |
2296 | unsigned int tile_rows, tiles; | |
c2c75131 | 2297 | |
bc752862 CW |
2298 | tile_rows = *y / 8; |
2299 | *y %= 8; | |
c2c75131 | 2300 | |
bc752862 CW |
2301 | tiles = *x / (512/cpp); |
2302 | *x %= 512/cpp; | |
2303 | ||
2304 | return tile_rows * pitch * 8 + tiles * 4096; | |
2305 | } else { | |
2306 | unsigned int offset; | |
2307 | ||
2308 | offset = *y * pitch + *x * cpp; | |
2309 | *y = 0; | |
2310 | *x = (offset & 4095) / cpp; | |
2311 | return offset & -4096; | |
2312 | } | |
c2c75131 DV |
2313 | } |
2314 | ||
46f297fb JB |
2315 | int intel_format_to_fourcc(int format) |
2316 | { | |
2317 | switch (format) { | |
2318 | case DISPPLANE_8BPP: | |
2319 | return DRM_FORMAT_C8; | |
2320 | case DISPPLANE_BGRX555: | |
2321 | return DRM_FORMAT_XRGB1555; | |
2322 | case DISPPLANE_BGRX565: | |
2323 | return DRM_FORMAT_RGB565; | |
2324 | default: | |
2325 | case DISPPLANE_BGRX888: | |
2326 | return DRM_FORMAT_XRGB8888; | |
2327 | case DISPPLANE_RGBX888: | |
2328 | return DRM_FORMAT_XBGR8888; | |
2329 | case DISPPLANE_BGRX101010: | |
2330 | return DRM_FORMAT_XRGB2101010; | |
2331 | case DISPPLANE_RGBX101010: | |
2332 | return DRM_FORMAT_XBGR2101010; | |
2333 | } | |
2334 | } | |
2335 | ||
484b41dd | 2336 | static bool intel_alloc_plane_obj(struct intel_crtc *crtc, |
46f297fb JB |
2337 | struct intel_plane_config *plane_config) |
2338 | { | |
2339 | struct drm_device *dev = crtc->base.dev; | |
2340 | struct drm_i915_gem_object *obj = NULL; | |
2341 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2342 | u32 base = plane_config->base; | |
2343 | ||
ff2652ea CW |
2344 | if (plane_config->size == 0) |
2345 | return false; | |
2346 | ||
46f297fb JB |
2347 | obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base, |
2348 | plane_config->size); | |
2349 | if (!obj) | |
484b41dd | 2350 | return false; |
46f297fb JB |
2351 | |
2352 | if (plane_config->tiled) { | |
2353 | obj->tiling_mode = I915_TILING_X; | |
66e514c1 | 2354 | obj->stride = crtc->base.primary->fb->pitches[0]; |
46f297fb JB |
2355 | } |
2356 | ||
66e514c1 DA |
2357 | mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format; |
2358 | mode_cmd.width = crtc->base.primary->fb->width; | |
2359 | mode_cmd.height = crtc->base.primary->fb->height; | |
2360 | mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0]; | |
46f297fb JB |
2361 | |
2362 | mutex_lock(&dev->struct_mutex); | |
2363 | ||
66e514c1 | 2364 | if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb), |
484b41dd | 2365 | &mode_cmd, obj)) { |
46f297fb JB |
2366 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2367 | goto out_unref_obj; | |
2368 | } | |
2369 | ||
a071fa00 | 2370 | obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe); |
46f297fb | 2371 | mutex_unlock(&dev->struct_mutex); |
484b41dd JB |
2372 | |
2373 | DRM_DEBUG_KMS("plane fb obj %p\n", obj); | |
2374 | return true; | |
46f297fb JB |
2375 | |
2376 | out_unref_obj: | |
2377 | drm_gem_object_unreference(&obj->base); | |
2378 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2379 | return false; |
2380 | } | |
2381 | ||
2382 | static void intel_find_plane_obj(struct intel_crtc *intel_crtc, | |
2383 | struct intel_plane_config *plane_config) | |
2384 | { | |
2385 | struct drm_device *dev = intel_crtc->base.dev; | |
d9ceb816 | 2386 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd JB |
2387 | struct drm_crtc *c; |
2388 | struct intel_crtc *i; | |
2ff8fde1 | 2389 | struct drm_i915_gem_object *obj; |
484b41dd | 2390 | |
66e514c1 | 2391 | if (!intel_crtc->base.primary->fb) |
484b41dd JB |
2392 | return; |
2393 | ||
2394 | if (intel_alloc_plane_obj(intel_crtc, plane_config)) | |
2395 | return; | |
2396 | ||
66e514c1 DA |
2397 | kfree(intel_crtc->base.primary->fb); |
2398 | intel_crtc->base.primary->fb = NULL; | |
484b41dd JB |
2399 | |
2400 | /* | |
2401 | * Failed to alloc the obj, check to see if we should share | |
2402 | * an fb with another CRTC instead | |
2403 | */ | |
70e1e0ec | 2404 | for_each_crtc(dev, c) { |
484b41dd JB |
2405 | i = to_intel_crtc(c); |
2406 | ||
2407 | if (c == &intel_crtc->base) | |
2408 | continue; | |
2409 | ||
2ff8fde1 MR |
2410 | if (!i->active) |
2411 | continue; | |
2412 | ||
2413 | obj = intel_fb_obj(c->primary->fb); | |
2414 | if (obj == NULL) | |
484b41dd JB |
2415 | continue; |
2416 | ||
2ff8fde1 | 2417 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
d9ceb816 JB |
2418 | if (obj->tiling_mode != I915_TILING_NONE) |
2419 | dev_priv->preserve_bios_swizzle = true; | |
2420 | ||
66e514c1 DA |
2421 | drm_framebuffer_reference(c->primary->fb); |
2422 | intel_crtc->base.primary->fb = c->primary->fb; | |
2ff8fde1 | 2423 | obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); |
484b41dd JB |
2424 | break; |
2425 | } | |
2426 | } | |
46f297fb JB |
2427 | } |
2428 | ||
29b9bde6 DV |
2429 | static void i9xx_update_primary_plane(struct drm_crtc *crtc, |
2430 | struct drm_framebuffer *fb, | |
2431 | int x, int y) | |
81255565 JB |
2432 | { |
2433 | struct drm_device *dev = crtc->dev; | |
2434 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2435 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
c9ba6fad | 2436 | struct drm_i915_gem_object *obj; |
81255565 | 2437 | int plane = intel_crtc->plane; |
e506a0c6 | 2438 | unsigned long linear_offset; |
81255565 | 2439 | u32 dspcntr; |
f45651ba | 2440 | u32 reg = DSPCNTR(plane); |
48404c1e | 2441 | int pixel_size; |
f45651ba | 2442 | |
fdd508a6 VS |
2443 | if (!intel_crtc->primary_enabled) { |
2444 | I915_WRITE(reg, 0); | |
2445 | if (INTEL_INFO(dev)->gen >= 4) | |
2446 | I915_WRITE(DSPSURF(plane), 0); | |
2447 | else | |
2448 | I915_WRITE(DSPADDR(plane), 0); | |
2449 | POSTING_READ(reg); | |
2450 | return; | |
2451 | } | |
2452 | ||
c9ba6fad VS |
2453 | obj = intel_fb_obj(fb); |
2454 | if (WARN_ON(obj == NULL)) | |
2455 | return; | |
2456 | ||
2457 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2458 | ||
f45651ba VS |
2459 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2460 | ||
fdd508a6 | 2461 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2462 | |
2463 | if (INTEL_INFO(dev)->gen < 4) { | |
2464 | if (intel_crtc->pipe == PIPE_B) | |
2465 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2466 | ||
2467 | /* pipesrc and dspsize control the size that is scaled from, | |
2468 | * which should always be the user's requested size. | |
2469 | */ | |
2470 | I915_WRITE(DSPSIZE(plane), | |
2471 | ((intel_crtc->config.pipe_src_h - 1) << 16) | | |
2472 | (intel_crtc->config.pipe_src_w - 1)); | |
2473 | I915_WRITE(DSPPOS(plane), 0); | |
c14b0485 VS |
2474 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2475 | I915_WRITE(PRIMSIZE(plane), | |
2476 | ((intel_crtc->config.pipe_src_h - 1) << 16) | | |
2477 | (intel_crtc->config.pipe_src_w - 1)); | |
2478 | I915_WRITE(PRIMPOS(plane), 0); | |
2479 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2480 | } |
81255565 | 2481 | |
57779d06 VS |
2482 | switch (fb->pixel_format) { |
2483 | case DRM_FORMAT_C8: | |
81255565 JB |
2484 | dspcntr |= DISPPLANE_8BPP; |
2485 | break; | |
57779d06 VS |
2486 | case DRM_FORMAT_XRGB1555: |
2487 | case DRM_FORMAT_ARGB1555: | |
2488 | dspcntr |= DISPPLANE_BGRX555; | |
81255565 | 2489 | break; |
57779d06 VS |
2490 | case DRM_FORMAT_RGB565: |
2491 | dspcntr |= DISPPLANE_BGRX565; | |
2492 | break; | |
2493 | case DRM_FORMAT_XRGB8888: | |
2494 | case DRM_FORMAT_ARGB8888: | |
2495 | dspcntr |= DISPPLANE_BGRX888; | |
2496 | break; | |
2497 | case DRM_FORMAT_XBGR8888: | |
2498 | case DRM_FORMAT_ABGR8888: | |
2499 | dspcntr |= DISPPLANE_RGBX888; | |
2500 | break; | |
2501 | case DRM_FORMAT_XRGB2101010: | |
2502 | case DRM_FORMAT_ARGB2101010: | |
2503 | dspcntr |= DISPPLANE_BGRX101010; | |
2504 | break; | |
2505 | case DRM_FORMAT_XBGR2101010: | |
2506 | case DRM_FORMAT_ABGR2101010: | |
2507 | dspcntr |= DISPPLANE_RGBX101010; | |
81255565 JB |
2508 | break; |
2509 | default: | |
baba133a | 2510 | BUG(); |
81255565 | 2511 | } |
57779d06 | 2512 | |
f45651ba VS |
2513 | if (INTEL_INFO(dev)->gen >= 4 && |
2514 | obj->tiling_mode != I915_TILING_NONE) | |
2515 | dspcntr |= DISPPLANE_TILED; | |
81255565 | 2516 | |
de1aa629 VS |
2517 | if (IS_G4X(dev)) |
2518 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2519 | ||
b9897127 | 2520 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
81255565 | 2521 | |
c2c75131 DV |
2522 | if (INTEL_INFO(dev)->gen >= 4) { |
2523 | intel_crtc->dspaddr_offset = | |
bc752862 | 2524 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
b9897127 | 2525 | pixel_size, |
bc752862 | 2526 | fb->pitches[0]); |
c2c75131 DV |
2527 | linear_offset -= intel_crtc->dspaddr_offset; |
2528 | } else { | |
e506a0c6 | 2529 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2530 | } |
e506a0c6 | 2531 | |
48404c1e SJ |
2532 | if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) { |
2533 | dspcntr |= DISPPLANE_ROTATE_180; | |
2534 | ||
2535 | x += (intel_crtc->config.pipe_src_w - 1); | |
2536 | y += (intel_crtc->config.pipe_src_h - 1); | |
2537 | ||
2538 | /* Finding the last pixel of the last line of the display | |
2539 | data and adding to linear_offset*/ | |
2540 | linear_offset += | |
2541 | (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] + | |
2542 | (intel_crtc->config.pipe_src_w - 1) * pixel_size; | |
2543 | } | |
2544 | ||
2545 | I915_WRITE(reg, dspcntr); | |
2546 | ||
f343c5f6 BW |
2547 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2548 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2549 | fb->pitches[0]); | |
01f2c773 | 2550 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2551 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2552 | I915_WRITE(DSPSURF(plane), |
2553 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2554 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2555 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2556 | } else |
f343c5f6 | 2557 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2558 | POSTING_READ(reg); |
17638cd6 JB |
2559 | } |
2560 | ||
29b9bde6 DV |
2561 | static void ironlake_update_primary_plane(struct drm_crtc *crtc, |
2562 | struct drm_framebuffer *fb, | |
2563 | int x, int y) | |
17638cd6 JB |
2564 | { |
2565 | struct drm_device *dev = crtc->dev; | |
2566 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2567 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
c9ba6fad | 2568 | struct drm_i915_gem_object *obj; |
17638cd6 | 2569 | int plane = intel_crtc->plane; |
e506a0c6 | 2570 | unsigned long linear_offset; |
17638cd6 | 2571 | u32 dspcntr; |
f45651ba | 2572 | u32 reg = DSPCNTR(plane); |
48404c1e | 2573 | int pixel_size; |
f45651ba | 2574 | |
fdd508a6 VS |
2575 | if (!intel_crtc->primary_enabled) { |
2576 | I915_WRITE(reg, 0); | |
2577 | I915_WRITE(DSPSURF(plane), 0); | |
2578 | POSTING_READ(reg); | |
2579 | return; | |
2580 | } | |
2581 | ||
c9ba6fad VS |
2582 | obj = intel_fb_obj(fb); |
2583 | if (WARN_ON(obj == NULL)) | |
2584 | return; | |
2585 | ||
2586 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2587 | ||
f45651ba VS |
2588 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2589 | ||
fdd508a6 | 2590 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2591 | |
2592 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2593 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2594 | |
57779d06 VS |
2595 | switch (fb->pixel_format) { |
2596 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2597 | dspcntr |= DISPPLANE_8BPP; |
2598 | break; | |
57779d06 VS |
2599 | case DRM_FORMAT_RGB565: |
2600 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2601 | break; |
57779d06 VS |
2602 | case DRM_FORMAT_XRGB8888: |
2603 | case DRM_FORMAT_ARGB8888: | |
2604 | dspcntr |= DISPPLANE_BGRX888; | |
2605 | break; | |
2606 | case DRM_FORMAT_XBGR8888: | |
2607 | case DRM_FORMAT_ABGR8888: | |
2608 | dspcntr |= DISPPLANE_RGBX888; | |
2609 | break; | |
2610 | case DRM_FORMAT_XRGB2101010: | |
2611 | case DRM_FORMAT_ARGB2101010: | |
2612 | dspcntr |= DISPPLANE_BGRX101010; | |
2613 | break; | |
2614 | case DRM_FORMAT_XBGR2101010: | |
2615 | case DRM_FORMAT_ABGR2101010: | |
2616 | dspcntr |= DISPPLANE_RGBX101010; | |
17638cd6 JB |
2617 | break; |
2618 | default: | |
baba133a | 2619 | BUG(); |
17638cd6 JB |
2620 | } |
2621 | ||
2622 | if (obj->tiling_mode != I915_TILING_NONE) | |
2623 | dspcntr |= DISPPLANE_TILED; | |
17638cd6 | 2624 | |
f45651ba | 2625 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2626 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2627 | |
b9897127 | 2628 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
c2c75131 | 2629 | intel_crtc->dspaddr_offset = |
bc752862 | 2630 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
b9897127 | 2631 | pixel_size, |
bc752862 | 2632 | fb->pitches[0]); |
c2c75131 | 2633 | linear_offset -= intel_crtc->dspaddr_offset; |
48404c1e SJ |
2634 | if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) { |
2635 | dspcntr |= DISPPLANE_ROTATE_180; | |
2636 | ||
2637 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
2638 | x += (intel_crtc->config.pipe_src_w - 1); | |
2639 | y += (intel_crtc->config.pipe_src_h - 1); | |
2640 | ||
2641 | /* Finding the last pixel of the last line of the display | |
2642 | data and adding to linear_offset*/ | |
2643 | linear_offset += | |
2644 | (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] + | |
2645 | (intel_crtc->config.pipe_src_w - 1) * pixel_size; | |
2646 | } | |
2647 | } | |
2648 | ||
2649 | I915_WRITE(reg, dspcntr); | |
17638cd6 | 2650 | |
f343c5f6 BW |
2651 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2652 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2653 | fb->pitches[0]); | |
01f2c773 | 2654 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2655 | I915_WRITE(DSPSURF(plane), |
2656 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2657 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2658 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2659 | } else { | |
2660 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2661 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2662 | } | |
17638cd6 | 2663 | POSTING_READ(reg); |
17638cd6 JB |
2664 | } |
2665 | ||
70d21f0e DL |
2666 | static void skylake_update_primary_plane(struct drm_crtc *crtc, |
2667 | struct drm_framebuffer *fb, | |
2668 | int x, int y) | |
2669 | { | |
2670 | struct drm_device *dev = crtc->dev; | |
2671 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2672 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2673 | struct intel_framebuffer *intel_fb; | |
2674 | struct drm_i915_gem_object *obj; | |
2675 | int pipe = intel_crtc->pipe; | |
2676 | u32 plane_ctl, stride; | |
2677 | ||
2678 | if (!intel_crtc->primary_enabled) { | |
2679 | I915_WRITE(PLANE_CTL(pipe, 0), 0); | |
2680 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
2681 | POSTING_READ(PLANE_CTL(pipe, 0)); | |
2682 | return; | |
2683 | } | |
2684 | ||
2685 | plane_ctl = PLANE_CTL_ENABLE | | |
2686 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
2687 | PLANE_CTL_PIPE_CSC_ENABLE; | |
2688 | ||
2689 | switch (fb->pixel_format) { | |
2690 | case DRM_FORMAT_RGB565: | |
2691 | plane_ctl |= PLANE_CTL_FORMAT_RGB_565; | |
2692 | break; | |
2693 | case DRM_FORMAT_XRGB8888: | |
2694 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; | |
2695 | break; | |
2696 | case DRM_FORMAT_XBGR8888: | |
2697 | plane_ctl |= PLANE_CTL_ORDER_RGBX; | |
2698 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; | |
2699 | break; | |
2700 | case DRM_FORMAT_XRGB2101010: | |
2701 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010; | |
2702 | break; | |
2703 | case DRM_FORMAT_XBGR2101010: | |
2704 | plane_ctl |= PLANE_CTL_ORDER_RGBX; | |
2705 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010; | |
2706 | break; | |
2707 | default: | |
2708 | BUG(); | |
2709 | } | |
2710 | ||
2711 | intel_fb = to_intel_framebuffer(fb); | |
2712 | obj = intel_fb->obj; | |
2713 | ||
2714 | /* | |
2715 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
2716 | * linear buffers or in number of tiles for tiled buffers. | |
2717 | */ | |
2718 | switch (obj->tiling_mode) { | |
2719 | case I915_TILING_NONE: | |
2720 | stride = fb->pitches[0] >> 6; | |
2721 | break; | |
2722 | case I915_TILING_X: | |
2723 | plane_ctl |= PLANE_CTL_TILED_X; | |
2724 | stride = fb->pitches[0] >> 9; | |
2725 | break; | |
2726 | default: | |
2727 | BUG(); | |
2728 | } | |
2729 | ||
2730 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
1447dde0 SJ |
2731 | if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) |
2732 | plane_ctl |= PLANE_CTL_ROTATE_180; | |
70d21f0e DL |
2733 | |
2734 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); | |
2735 | ||
2736 | DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n", | |
2737 | i915_gem_obj_ggtt_offset(obj), | |
2738 | x, y, fb->width, fb->height, | |
2739 | fb->pitches[0]); | |
2740 | ||
2741 | I915_WRITE(PLANE_POS(pipe, 0), 0); | |
2742 | I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x); | |
2743 | I915_WRITE(PLANE_SIZE(pipe, 0), | |
2744 | (intel_crtc->config.pipe_src_h - 1) << 16 | | |
2745 | (intel_crtc->config.pipe_src_w - 1)); | |
2746 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
2747 | I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj)); | |
2748 | ||
2749 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
2750 | } | |
2751 | ||
17638cd6 JB |
2752 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
2753 | static int | |
2754 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
2755 | int x, int y, enum mode_set_atomic state) | |
2756 | { | |
2757 | struct drm_device *dev = crtc->dev; | |
2758 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 2759 | |
6b8e6ed0 CW |
2760 | if (dev_priv->display.disable_fbc) |
2761 | dev_priv->display.disable_fbc(dev); | |
81255565 | 2762 | |
29b9bde6 DV |
2763 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
2764 | ||
2765 | return 0; | |
81255565 JB |
2766 | } |
2767 | ||
96a02917 VS |
2768 | void intel_display_handle_reset(struct drm_device *dev) |
2769 | { | |
2770 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2771 | struct drm_crtc *crtc; | |
2772 | ||
2773 | /* | |
2774 | * Flips in the rings have been nuked by the reset, | |
2775 | * so complete all pending flips so that user space | |
2776 | * will get its events and not get stuck. | |
2777 | * | |
2778 | * Also update the base address of all primary | |
2779 | * planes to the the last fb to make sure we're | |
2780 | * showing the correct fb after a reset. | |
2781 | * | |
2782 | * Need to make two loops over the crtcs so that we | |
2783 | * don't try to grab a crtc mutex before the | |
2784 | * pending_flip_queue really got woken up. | |
2785 | */ | |
2786 | ||
70e1e0ec | 2787 | for_each_crtc(dev, crtc) { |
96a02917 VS |
2788 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2789 | enum plane plane = intel_crtc->plane; | |
2790 | ||
2791 | intel_prepare_page_flip(dev, plane); | |
2792 | intel_finish_page_flip_plane(dev, plane); | |
2793 | } | |
2794 | ||
70e1e0ec | 2795 | for_each_crtc(dev, crtc) { |
96a02917 VS |
2796 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2797 | ||
51fd371b | 2798 | drm_modeset_lock(&crtc->mutex, NULL); |
947fdaad CW |
2799 | /* |
2800 | * FIXME: Once we have proper support for primary planes (and | |
2801 | * disabling them without disabling the entire crtc) allow again | |
66e514c1 | 2802 | * a NULL crtc->primary->fb. |
947fdaad | 2803 | */ |
f4510a27 | 2804 | if (intel_crtc->active && crtc->primary->fb) |
262ca2b0 | 2805 | dev_priv->display.update_primary_plane(crtc, |
66e514c1 | 2806 | crtc->primary->fb, |
262ca2b0 MR |
2807 | crtc->x, |
2808 | crtc->y); | |
51fd371b | 2809 | drm_modeset_unlock(&crtc->mutex); |
96a02917 VS |
2810 | } |
2811 | } | |
2812 | ||
14667a4b CW |
2813 | static int |
2814 | intel_finish_fb(struct drm_framebuffer *old_fb) | |
2815 | { | |
2ff8fde1 | 2816 | struct drm_i915_gem_object *obj = intel_fb_obj(old_fb); |
14667a4b CW |
2817 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
2818 | bool was_interruptible = dev_priv->mm.interruptible; | |
2819 | int ret; | |
2820 | ||
14667a4b CW |
2821 | /* Big Hammer, we also need to ensure that any pending |
2822 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
2823 | * current scanout is retired before unpinning the old | |
2824 | * framebuffer. | |
2825 | * | |
2826 | * This should only fail upon a hung GPU, in which case we | |
2827 | * can safely continue. | |
2828 | */ | |
2829 | dev_priv->mm.interruptible = false; | |
2830 | ret = i915_gem_object_finish_gpu(obj); | |
2831 | dev_priv->mm.interruptible = was_interruptible; | |
2832 | ||
2833 | return ret; | |
2834 | } | |
2835 | ||
7d5e3799 CW |
2836 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
2837 | { | |
2838 | struct drm_device *dev = crtc->dev; | |
2839 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2840 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7d5e3799 CW |
2841 | bool pending; |
2842 | ||
2843 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
2844 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
2845 | return false; | |
2846 | ||
5e2d7afc | 2847 | spin_lock_irq(&dev->event_lock); |
7d5e3799 | 2848 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
5e2d7afc | 2849 | spin_unlock_irq(&dev->event_lock); |
7d5e3799 CW |
2850 | |
2851 | return pending; | |
2852 | } | |
2853 | ||
e30e8f75 GP |
2854 | static void intel_update_pipe_size(struct intel_crtc *crtc) |
2855 | { | |
2856 | struct drm_device *dev = crtc->base.dev; | |
2857 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2858 | const struct drm_display_mode *adjusted_mode; | |
2859 | ||
2860 | if (!i915.fastboot) | |
2861 | return; | |
2862 | ||
2863 | /* | |
2864 | * Update pipe size and adjust fitter if needed: the reason for this is | |
2865 | * that in compute_mode_changes we check the native mode (not the pfit | |
2866 | * mode) to see if we can flip rather than do a full mode set. In the | |
2867 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
2868 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
2869 | * sized surface. | |
2870 | * | |
2871 | * To fix this properly, we need to hoist the checks up into | |
2872 | * compute_mode_changes (or above), check the actual pfit state and | |
2873 | * whether the platform allows pfit disable with pipe active, and only | |
2874 | * then update the pipesrc and pfit state, even on the flip path. | |
2875 | */ | |
2876 | ||
2877 | adjusted_mode = &crtc->config.adjusted_mode; | |
2878 | ||
2879 | I915_WRITE(PIPESRC(crtc->pipe), | |
2880 | ((adjusted_mode->crtc_hdisplay - 1) << 16) | | |
2881 | (adjusted_mode->crtc_vdisplay - 1)); | |
2882 | if (!crtc->config.pch_pfit.enabled && | |
409ee761 ACO |
2883 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
2884 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
e30e8f75 GP |
2885 | I915_WRITE(PF_CTL(crtc->pipe), 0); |
2886 | I915_WRITE(PF_WIN_POS(crtc->pipe), 0); | |
2887 | I915_WRITE(PF_WIN_SZ(crtc->pipe), 0); | |
2888 | } | |
2889 | crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay; | |
2890 | crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay; | |
2891 | } | |
2892 | ||
5c3b82e2 | 2893 | static int |
3c4fdcfb | 2894 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
94352cf9 | 2895 | struct drm_framebuffer *fb) |
79e53945 JB |
2896 | { |
2897 | struct drm_device *dev = crtc->dev; | |
6b8e6ed0 | 2898 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 2899 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
a071fa00 | 2900 | enum pipe pipe = intel_crtc->pipe; |
2ff8fde1 | 2901 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2ff8fde1 | 2902 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb); |
5c3b82e2 | 2903 | int ret; |
79e53945 | 2904 | |
7d5e3799 CW |
2905 | if (intel_crtc_has_pending_flip(crtc)) { |
2906 | DRM_ERROR("pipe is still busy with an old pageflip\n"); | |
2907 | return -EBUSY; | |
2908 | } | |
2909 | ||
79e53945 | 2910 | /* no fb bound */ |
94352cf9 | 2911 | if (!fb) { |
a5071c2f | 2912 | DRM_ERROR("No FB bound\n"); |
5c3b82e2 CW |
2913 | return 0; |
2914 | } | |
2915 | ||
7eb552ae | 2916 | if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) { |
84f44ce7 VS |
2917 | DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n", |
2918 | plane_name(intel_crtc->plane), | |
2919 | INTEL_INFO(dev)->num_pipes); | |
5c3b82e2 | 2920 | return -EINVAL; |
79e53945 JB |
2921 | } |
2922 | ||
5c3b82e2 | 2923 | mutex_lock(&dev->struct_mutex); |
850c4cdc | 2924 | ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, NULL); |
a071fa00 | 2925 | if (ret == 0) |
850c4cdc | 2926 | i915_gem_track_fb(old_obj, intel_fb_obj(fb), |
a071fa00 | 2927 | INTEL_FRONTBUFFER_PRIMARY(pipe)); |
8ac36ec1 | 2928 | mutex_unlock(&dev->struct_mutex); |
5c3b82e2 | 2929 | if (ret != 0) { |
a5071c2f | 2930 | DRM_ERROR("pin & fence failed\n"); |
5c3b82e2 CW |
2931 | return ret; |
2932 | } | |
79e53945 | 2933 | |
29b9bde6 | 2934 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
3c4fdcfb | 2935 | |
f99d7069 DV |
2936 | if (intel_crtc->active) |
2937 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); | |
2938 | ||
f4510a27 | 2939 | crtc->primary->fb = fb; |
6c4c86f5 DV |
2940 | crtc->x = x; |
2941 | crtc->y = y; | |
94352cf9 | 2942 | |
b7f1de28 | 2943 | if (old_fb) { |
d7697eea DV |
2944 | if (intel_crtc->active && old_fb != fb) |
2945 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
8ac36ec1 | 2946 | mutex_lock(&dev->struct_mutex); |
2ff8fde1 | 2947 | intel_unpin_fb_obj(old_obj); |
8ac36ec1 | 2948 | mutex_unlock(&dev->struct_mutex); |
b7f1de28 | 2949 | } |
652c393a | 2950 | |
8ac36ec1 | 2951 | mutex_lock(&dev->struct_mutex); |
6b8e6ed0 | 2952 | intel_update_fbc(dev); |
5c3b82e2 | 2953 | mutex_unlock(&dev->struct_mutex); |
79e53945 | 2954 | |
5c3b82e2 | 2955 | return 0; |
79e53945 JB |
2956 | } |
2957 | ||
5e84e1a4 ZW |
2958 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
2959 | { | |
2960 | struct drm_device *dev = crtc->dev; | |
2961 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2962 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2963 | int pipe = intel_crtc->pipe; | |
2964 | u32 reg, temp; | |
2965 | ||
2966 | /* enable normal train */ | |
2967 | reg = FDI_TX_CTL(pipe); | |
2968 | temp = I915_READ(reg); | |
61e499bf | 2969 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
2970 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2971 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
2972 | } else { |
2973 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2974 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 2975 | } |
5e84e1a4 ZW |
2976 | I915_WRITE(reg, temp); |
2977 | ||
2978 | reg = FDI_RX_CTL(pipe); | |
2979 | temp = I915_READ(reg); | |
2980 | if (HAS_PCH_CPT(dev)) { | |
2981 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2982 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
2983 | } else { | |
2984 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2985 | temp |= FDI_LINK_TRAIN_NONE; | |
2986 | } | |
2987 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
2988 | ||
2989 | /* wait one idle pattern time */ | |
2990 | POSTING_READ(reg); | |
2991 | udelay(1000); | |
357555c0 JB |
2992 | |
2993 | /* IVB wants error correction enabled */ | |
2994 | if (IS_IVYBRIDGE(dev)) | |
2995 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
2996 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
2997 | } |
2998 | ||
1fbc0d78 | 2999 | static bool pipe_has_enabled_pch(struct intel_crtc *crtc) |
1e833f40 | 3000 | { |
1fbc0d78 DV |
3001 | return crtc->base.enabled && crtc->active && |
3002 | crtc->config.has_pch_encoder; | |
1e833f40 DV |
3003 | } |
3004 | ||
01a415fd DV |
3005 | static void ivb_modeset_global_resources(struct drm_device *dev) |
3006 | { | |
3007 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3008 | struct intel_crtc *pipe_B_crtc = | |
3009 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
3010 | struct intel_crtc *pipe_C_crtc = | |
3011 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]); | |
3012 | uint32_t temp; | |
3013 | ||
1e833f40 DV |
3014 | /* |
3015 | * When everything is off disable fdi C so that we could enable fdi B | |
3016 | * with all lanes. Note that we don't care about enabled pipes without | |
3017 | * an enabled pch encoder. | |
3018 | */ | |
3019 | if (!pipe_has_enabled_pch(pipe_B_crtc) && | |
3020 | !pipe_has_enabled_pch(pipe_C_crtc)) { | |
01a415fd DV |
3021 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
3022 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
3023 | ||
3024 | temp = I915_READ(SOUTH_CHICKEN1); | |
3025 | temp &= ~FDI_BC_BIFURCATION_SELECT; | |
3026 | DRM_DEBUG_KMS("disabling fdi C rx\n"); | |
3027 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
3028 | } | |
3029 | } | |
3030 | ||
8db9d77b ZW |
3031 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3032 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3033 | { | |
3034 | struct drm_device *dev = crtc->dev; | |
3035 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3036 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3037 | int pipe = intel_crtc->pipe; | |
5eddb70b | 3038 | u32 reg, temp, tries; |
8db9d77b | 3039 | |
1c8562f6 | 3040 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3041 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3042 | |
e1a44743 AJ |
3043 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3044 | for train result */ | |
5eddb70b CW |
3045 | reg = FDI_RX_IMR(pipe); |
3046 | temp = I915_READ(reg); | |
e1a44743 AJ |
3047 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3048 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3049 | I915_WRITE(reg, temp); |
3050 | I915_READ(reg); | |
e1a44743 AJ |
3051 | udelay(150); |
3052 | ||
8db9d77b | 3053 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3054 | reg = FDI_TX_CTL(pipe); |
3055 | temp = I915_READ(reg); | |
627eb5a3 DV |
3056 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
3057 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
3058 | temp &= ~FDI_LINK_TRAIN_NONE; |
3059 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3060 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3061 | |
5eddb70b CW |
3062 | reg = FDI_RX_CTL(pipe); |
3063 | temp = I915_READ(reg); | |
8db9d77b ZW |
3064 | temp &= ~FDI_LINK_TRAIN_NONE; |
3065 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3066 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3067 | ||
3068 | POSTING_READ(reg); | |
8db9d77b ZW |
3069 | udelay(150); |
3070 | ||
5b2adf89 | 3071 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3072 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3073 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3074 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3075 | |
5eddb70b | 3076 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3077 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3078 | temp = I915_READ(reg); |
8db9d77b ZW |
3079 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3080 | ||
3081 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3082 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3083 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3084 | break; |
3085 | } | |
8db9d77b | 3086 | } |
e1a44743 | 3087 | if (tries == 5) |
5eddb70b | 3088 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3089 | |
3090 | /* Train 2 */ | |
5eddb70b CW |
3091 | reg = FDI_TX_CTL(pipe); |
3092 | temp = I915_READ(reg); | |
8db9d77b ZW |
3093 | temp &= ~FDI_LINK_TRAIN_NONE; |
3094 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3095 | I915_WRITE(reg, temp); |
8db9d77b | 3096 | |
5eddb70b CW |
3097 | reg = FDI_RX_CTL(pipe); |
3098 | temp = I915_READ(reg); | |
8db9d77b ZW |
3099 | temp &= ~FDI_LINK_TRAIN_NONE; |
3100 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3101 | I915_WRITE(reg, temp); |
8db9d77b | 3102 | |
5eddb70b CW |
3103 | POSTING_READ(reg); |
3104 | udelay(150); | |
8db9d77b | 3105 | |
5eddb70b | 3106 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3107 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3108 | temp = I915_READ(reg); |
8db9d77b ZW |
3109 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3110 | ||
3111 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3112 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3113 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3114 | break; | |
3115 | } | |
8db9d77b | 3116 | } |
e1a44743 | 3117 | if (tries == 5) |
5eddb70b | 3118 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3119 | |
3120 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3121 | |
8db9d77b ZW |
3122 | } |
3123 | ||
0206e353 | 3124 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3125 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3126 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3127 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3128 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3129 | }; | |
3130 | ||
3131 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3132 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3133 | { | |
3134 | struct drm_device *dev = crtc->dev; | |
3135 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3136 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3137 | int pipe = intel_crtc->pipe; | |
fa37d39e | 3138 | u32 reg, temp, i, retry; |
8db9d77b | 3139 | |
e1a44743 AJ |
3140 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3141 | for train result */ | |
5eddb70b CW |
3142 | reg = FDI_RX_IMR(pipe); |
3143 | temp = I915_READ(reg); | |
e1a44743 AJ |
3144 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3145 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3146 | I915_WRITE(reg, temp); |
3147 | ||
3148 | POSTING_READ(reg); | |
e1a44743 AJ |
3149 | udelay(150); |
3150 | ||
8db9d77b | 3151 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3152 | reg = FDI_TX_CTL(pipe); |
3153 | temp = I915_READ(reg); | |
627eb5a3 DV |
3154 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
3155 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
3156 | temp &= ~FDI_LINK_TRAIN_NONE; |
3157 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3158 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3159 | /* SNB-B */ | |
3160 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3161 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3162 | |
d74cf324 DV |
3163 | I915_WRITE(FDI_RX_MISC(pipe), |
3164 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3165 | ||
5eddb70b CW |
3166 | reg = FDI_RX_CTL(pipe); |
3167 | temp = I915_READ(reg); | |
8db9d77b ZW |
3168 | if (HAS_PCH_CPT(dev)) { |
3169 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3170 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3171 | } else { | |
3172 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3173 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3174 | } | |
5eddb70b CW |
3175 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3176 | ||
3177 | POSTING_READ(reg); | |
8db9d77b ZW |
3178 | udelay(150); |
3179 | ||
0206e353 | 3180 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3181 | reg = FDI_TX_CTL(pipe); |
3182 | temp = I915_READ(reg); | |
8db9d77b ZW |
3183 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3184 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3185 | I915_WRITE(reg, temp); |
3186 | ||
3187 | POSTING_READ(reg); | |
8db9d77b ZW |
3188 | udelay(500); |
3189 | ||
fa37d39e SP |
3190 | for (retry = 0; retry < 5; retry++) { |
3191 | reg = FDI_RX_IIR(pipe); | |
3192 | temp = I915_READ(reg); | |
3193 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3194 | if (temp & FDI_RX_BIT_LOCK) { | |
3195 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3196 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3197 | break; | |
3198 | } | |
3199 | udelay(50); | |
8db9d77b | 3200 | } |
fa37d39e SP |
3201 | if (retry < 5) |
3202 | break; | |
8db9d77b ZW |
3203 | } |
3204 | if (i == 4) | |
5eddb70b | 3205 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3206 | |
3207 | /* Train 2 */ | |
5eddb70b CW |
3208 | reg = FDI_TX_CTL(pipe); |
3209 | temp = I915_READ(reg); | |
8db9d77b ZW |
3210 | temp &= ~FDI_LINK_TRAIN_NONE; |
3211 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3212 | if (IS_GEN6(dev)) { | |
3213 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3214 | /* SNB-B */ | |
3215 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3216 | } | |
5eddb70b | 3217 | I915_WRITE(reg, temp); |
8db9d77b | 3218 | |
5eddb70b CW |
3219 | reg = FDI_RX_CTL(pipe); |
3220 | temp = I915_READ(reg); | |
8db9d77b ZW |
3221 | if (HAS_PCH_CPT(dev)) { |
3222 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3223 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3224 | } else { | |
3225 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3226 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3227 | } | |
5eddb70b CW |
3228 | I915_WRITE(reg, temp); |
3229 | ||
3230 | POSTING_READ(reg); | |
8db9d77b ZW |
3231 | udelay(150); |
3232 | ||
0206e353 | 3233 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3234 | reg = FDI_TX_CTL(pipe); |
3235 | temp = I915_READ(reg); | |
8db9d77b ZW |
3236 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3237 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3238 | I915_WRITE(reg, temp); |
3239 | ||
3240 | POSTING_READ(reg); | |
8db9d77b ZW |
3241 | udelay(500); |
3242 | ||
fa37d39e SP |
3243 | for (retry = 0; retry < 5; retry++) { |
3244 | reg = FDI_RX_IIR(pipe); | |
3245 | temp = I915_READ(reg); | |
3246 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3247 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3248 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3249 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3250 | break; | |
3251 | } | |
3252 | udelay(50); | |
8db9d77b | 3253 | } |
fa37d39e SP |
3254 | if (retry < 5) |
3255 | break; | |
8db9d77b ZW |
3256 | } |
3257 | if (i == 4) | |
5eddb70b | 3258 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3259 | |
3260 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3261 | } | |
3262 | ||
357555c0 JB |
3263 | /* Manual link training for Ivy Bridge A0 parts */ |
3264 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3265 | { | |
3266 | struct drm_device *dev = crtc->dev; | |
3267 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3268 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3269 | int pipe = intel_crtc->pipe; | |
139ccd3f | 3270 | u32 reg, temp, i, j; |
357555c0 JB |
3271 | |
3272 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3273 | for train result */ | |
3274 | reg = FDI_RX_IMR(pipe); | |
3275 | temp = I915_READ(reg); | |
3276 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3277 | temp &= ~FDI_RX_BIT_LOCK; | |
3278 | I915_WRITE(reg, temp); | |
3279 | ||
3280 | POSTING_READ(reg); | |
3281 | udelay(150); | |
3282 | ||
01a415fd DV |
3283 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3284 | I915_READ(FDI_RX_IIR(pipe))); | |
3285 | ||
139ccd3f JB |
3286 | /* Try each vswing and preemphasis setting twice before moving on */ |
3287 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3288 | /* disable first in case we need to retry */ | |
3289 | reg = FDI_TX_CTL(pipe); | |
3290 | temp = I915_READ(reg); | |
3291 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3292 | temp &= ~FDI_TX_ENABLE; | |
3293 | I915_WRITE(reg, temp); | |
357555c0 | 3294 | |
139ccd3f JB |
3295 | reg = FDI_RX_CTL(pipe); |
3296 | temp = I915_READ(reg); | |
3297 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3298 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3299 | temp &= ~FDI_RX_ENABLE; | |
3300 | I915_WRITE(reg, temp); | |
357555c0 | 3301 | |
139ccd3f | 3302 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3303 | reg = FDI_TX_CTL(pipe); |
3304 | temp = I915_READ(reg); | |
139ccd3f JB |
3305 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
3306 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
3307 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; | |
357555c0 | 3308 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3309 | temp |= snb_b_fdi_train_param[j/2]; |
3310 | temp |= FDI_COMPOSITE_SYNC; | |
3311 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3312 | |
139ccd3f JB |
3313 | I915_WRITE(FDI_RX_MISC(pipe), |
3314 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3315 | |
139ccd3f | 3316 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3317 | temp = I915_READ(reg); |
139ccd3f JB |
3318 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3319 | temp |= FDI_COMPOSITE_SYNC; | |
3320 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3321 | |
139ccd3f JB |
3322 | POSTING_READ(reg); |
3323 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3324 | |
139ccd3f JB |
3325 | for (i = 0; i < 4; i++) { |
3326 | reg = FDI_RX_IIR(pipe); | |
3327 | temp = I915_READ(reg); | |
3328 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3329 | |
139ccd3f JB |
3330 | if (temp & FDI_RX_BIT_LOCK || |
3331 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3332 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3333 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3334 | i); | |
3335 | break; | |
3336 | } | |
3337 | udelay(1); /* should be 0.5us */ | |
3338 | } | |
3339 | if (i == 4) { | |
3340 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3341 | continue; | |
3342 | } | |
357555c0 | 3343 | |
139ccd3f | 3344 | /* Train 2 */ |
357555c0 JB |
3345 | reg = FDI_TX_CTL(pipe); |
3346 | temp = I915_READ(reg); | |
139ccd3f JB |
3347 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3348 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3349 | I915_WRITE(reg, temp); | |
3350 | ||
3351 | reg = FDI_RX_CTL(pipe); | |
3352 | temp = I915_READ(reg); | |
3353 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3354 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3355 | I915_WRITE(reg, temp); |
3356 | ||
3357 | POSTING_READ(reg); | |
139ccd3f | 3358 | udelay(2); /* should be 1.5us */ |
357555c0 | 3359 | |
139ccd3f JB |
3360 | for (i = 0; i < 4; i++) { |
3361 | reg = FDI_RX_IIR(pipe); | |
3362 | temp = I915_READ(reg); | |
3363 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3364 | |
139ccd3f JB |
3365 | if (temp & FDI_RX_SYMBOL_LOCK || |
3366 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3367 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3368 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3369 | i); | |
3370 | goto train_done; | |
3371 | } | |
3372 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3373 | } |
139ccd3f JB |
3374 | if (i == 4) |
3375 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3376 | } |
357555c0 | 3377 | |
139ccd3f | 3378 | train_done: |
357555c0 JB |
3379 | DRM_DEBUG_KMS("FDI train done.\n"); |
3380 | } | |
3381 | ||
88cefb6c | 3382 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3383 | { |
88cefb6c | 3384 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3385 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3386 | int pipe = intel_crtc->pipe; |
5eddb70b | 3387 | u32 reg, temp; |
79e53945 | 3388 | |
c64e311e | 3389 | |
c98e9dcf | 3390 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3391 | reg = FDI_RX_CTL(pipe); |
3392 | temp = I915_READ(reg); | |
627eb5a3 DV |
3393 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
3394 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
dfd07d72 | 3395 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3396 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3397 | ||
3398 | POSTING_READ(reg); | |
c98e9dcf JB |
3399 | udelay(200); |
3400 | ||
3401 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3402 | temp = I915_READ(reg); |
3403 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3404 | ||
3405 | POSTING_READ(reg); | |
c98e9dcf JB |
3406 | udelay(200); |
3407 | ||
20749730 PZ |
3408 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3409 | reg = FDI_TX_CTL(pipe); | |
3410 | temp = I915_READ(reg); | |
3411 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3412 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3413 | |
20749730 PZ |
3414 | POSTING_READ(reg); |
3415 | udelay(100); | |
6be4a607 | 3416 | } |
0e23b99d JB |
3417 | } |
3418 | ||
88cefb6c DV |
3419 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3420 | { | |
3421 | struct drm_device *dev = intel_crtc->base.dev; | |
3422 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3423 | int pipe = intel_crtc->pipe; | |
3424 | u32 reg, temp; | |
3425 | ||
3426 | /* Switch from PCDclk to Rawclk */ | |
3427 | reg = FDI_RX_CTL(pipe); | |
3428 | temp = I915_READ(reg); | |
3429 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3430 | ||
3431 | /* Disable CPU FDI TX PLL */ | |
3432 | reg = FDI_TX_CTL(pipe); | |
3433 | temp = I915_READ(reg); | |
3434 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3435 | ||
3436 | POSTING_READ(reg); | |
3437 | udelay(100); | |
3438 | ||
3439 | reg = FDI_RX_CTL(pipe); | |
3440 | temp = I915_READ(reg); | |
3441 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3442 | ||
3443 | /* Wait for the clocks to turn off. */ | |
3444 | POSTING_READ(reg); | |
3445 | udelay(100); | |
3446 | } | |
3447 | ||
0fc932b8 JB |
3448 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3449 | { | |
3450 | struct drm_device *dev = crtc->dev; | |
3451 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3452 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3453 | int pipe = intel_crtc->pipe; | |
3454 | u32 reg, temp; | |
3455 | ||
3456 | /* disable CPU FDI tx and PCH FDI rx */ | |
3457 | reg = FDI_TX_CTL(pipe); | |
3458 | temp = I915_READ(reg); | |
3459 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3460 | POSTING_READ(reg); | |
3461 | ||
3462 | reg = FDI_RX_CTL(pipe); | |
3463 | temp = I915_READ(reg); | |
3464 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3465 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3466 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3467 | ||
3468 | POSTING_READ(reg); | |
3469 | udelay(100); | |
3470 | ||
3471 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3472 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3473 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3474 | |
3475 | /* still set train pattern 1 */ | |
3476 | reg = FDI_TX_CTL(pipe); | |
3477 | temp = I915_READ(reg); | |
3478 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3479 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3480 | I915_WRITE(reg, temp); | |
3481 | ||
3482 | reg = FDI_RX_CTL(pipe); | |
3483 | temp = I915_READ(reg); | |
3484 | if (HAS_PCH_CPT(dev)) { | |
3485 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3486 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3487 | } else { | |
3488 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3489 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3490 | } | |
3491 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3492 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3493 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3494 | I915_WRITE(reg, temp); |
3495 | ||
3496 | POSTING_READ(reg); | |
3497 | udelay(100); | |
3498 | } | |
3499 | ||
5dce5b93 CW |
3500 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3501 | { | |
3502 | struct intel_crtc *crtc; | |
3503 | ||
3504 | /* Note that we don't need to be called with mode_config.lock here | |
3505 | * as our list of CRTC objects is static for the lifetime of the | |
3506 | * device and so cannot disappear as we iterate. Similarly, we can | |
3507 | * happily treat the predicates as racy, atomic checks as userspace | |
3508 | * cannot claim and pin a new fb without at least acquring the | |
3509 | * struct_mutex and so serialising with us. | |
3510 | */ | |
d3fcc808 | 3511 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3512 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3513 | continue; | |
3514 | ||
3515 | if (crtc->unpin_work) | |
3516 | intel_wait_for_vblank(dev, crtc->pipe); | |
3517 | ||
3518 | return true; | |
3519 | } | |
3520 | ||
3521 | return false; | |
3522 | } | |
3523 | ||
d6bbafa1 CW |
3524 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
3525 | { | |
3526 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
3527 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
3528 | ||
3529 | /* ensure that the unpin work is consistent wrt ->pending. */ | |
3530 | smp_rmb(); | |
3531 | intel_crtc->unpin_work = NULL; | |
3532 | ||
3533 | if (work->event) | |
3534 | drm_send_vblank_event(intel_crtc->base.dev, | |
3535 | intel_crtc->pipe, | |
3536 | work->event); | |
3537 | ||
3538 | drm_crtc_vblank_put(&intel_crtc->base); | |
3539 | ||
3540 | wake_up_all(&dev_priv->pending_flip_queue); | |
3541 | queue_work(dev_priv->wq, &work->work); | |
3542 | ||
3543 | trace_i915_flip_complete(intel_crtc->plane, | |
3544 | work->pending_flip_obj); | |
3545 | } | |
3546 | ||
46a55d30 | 3547 | void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3548 | { |
0f91128d | 3549 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3550 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 | 3551 | |
2c10d571 | 3552 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
9c787942 CW |
3553 | if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue, |
3554 | !intel_crtc_has_pending_flip(crtc), | |
3555 | 60*HZ) == 0)) { | |
3556 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2c10d571 | 3557 | |
5e2d7afc | 3558 | spin_lock_irq(&dev->event_lock); |
9c787942 CW |
3559 | if (intel_crtc->unpin_work) { |
3560 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
3561 | page_flip_completed(intel_crtc); | |
3562 | } | |
5e2d7afc | 3563 | spin_unlock_irq(&dev->event_lock); |
9c787942 | 3564 | } |
5bb61643 | 3565 | |
975d568a CW |
3566 | if (crtc->primary->fb) { |
3567 | mutex_lock(&dev->struct_mutex); | |
3568 | intel_finish_fb(crtc->primary->fb); | |
3569 | mutex_unlock(&dev->struct_mutex); | |
3570 | } | |
e6c3a2a6 CW |
3571 | } |
3572 | ||
e615efe4 ED |
3573 | /* Program iCLKIP clock to the desired frequency */ |
3574 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3575 | { | |
3576 | struct drm_device *dev = crtc->dev; | |
3577 | struct drm_i915_private *dev_priv = dev->dev_private; | |
241bfc38 | 3578 | int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock; |
e615efe4 ED |
3579 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3580 | u32 temp; | |
3581 | ||
09153000 DV |
3582 | mutex_lock(&dev_priv->dpio_lock); |
3583 | ||
e615efe4 ED |
3584 | /* It is necessary to ungate the pixclk gate prior to programming |
3585 | * the divisors, and gate it back when it is done. | |
3586 | */ | |
3587 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3588 | ||
3589 | /* Disable SSCCTL */ | |
3590 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
3591 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
3592 | SBI_SSCCTL_DISABLE, | |
3593 | SBI_ICLK); | |
e615efe4 ED |
3594 | |
3595 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3596 | if (clock == 20000) { |
e615efe4 ED |
3597 | auxdiv = 1; |
3598 | divsel = 0x41; | |
3599 | phaseinc = 0x20; | |
3600 | } else { | |
3601 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3602 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3603 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3604 | * convert the virtual clock precision to KHz here for higher |
3605 | * precision. | |
3606 | */ | |
3607 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3608 | u32 iclk_pi_range = 64; | |
3609 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3610 | ||
12d7ceed | 3611 | desired_divisor = (iclk_virtual_root_freq / clock); |
e615efe4 ED |
3612 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3613 | pi_value = desired_divisor % iclk_pi_range; | |
3614 | ||
3615 | auxdiv = 0; | |
3616 | divsel = msb_divisor_value - 2; | |
3617 | phaseinc = pi_value; | |
3618 | } | |
3619 | ||
3620 | /* This should not happen with any sane values */ | |
3621 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3622 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3623 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3624 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3625 | ||
3626 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3627 | clock, |
e615efe4 ED |
3628 | auxdiv, |
3629 | divsel, | |
3630 | phasedir, | |
3631 | phaseinc); | |
3632 | ||
3633 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 3634 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
3635 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3636 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
3637 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
3638 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
3639 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
3640 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 3641 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
3642 | |
3643 | /* Program SSCAUXDIV */ | |
988d6ee8 | 3644 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
3645 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3646 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 3647 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
3648 | |
3649 | /* Enable modulator and associated divider */ | |
988d6ee8 | 3650 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 3651 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 3652 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
3653 | |
3654 | /* Wait for initialization time */ | |
3655 | udelay(24); | |
3656 | ||
3657 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 DV |
3658 | |
3659 | mutex_unlock(&dev_priv->dpio_lock); | |
e615efe4 ED |
3660 | } |
3661 | ||
275f01b2 DV |
3662 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
3663 | enum pipe pch_transcoder) | |
3664 | { | |
3665 | struct drm_device *dev = crtc->base.dev; | |
3666 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3667 | enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; | |
3668 | ||
3669 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
3670 | I915_READ(HTOTAL(cpu_transcoder))); | |
3671 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
3672 | I915_READ(HBLANK(cpu_transcoder))); | |
3673 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
3674 | I915_READ(HSYNC(cpu_transcoder))); | |
3675 | ||
3676 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
3677 | I915_READ(VTOTAL(cpu_transcoder))); | |
3678 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
3679 | I915_READ(VBLANK(cpu_transcoder))); | |
3680 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
3681 | I915_READ(VSYNC(cpu_transcoder))); | |
3682 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
3683 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
3684 | } | |
3685 | ||
1fbc0d78 DV |
3686 | static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev) |
3687 | { | |
3688 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3689 | uint32_t temp; | |
3690 | ||
3691 | temp = I915_READ(SOUTH_CHICKEN1); | |
3692 | if (temp & FDI_BC_BIFURCATION_SELECT) | |
3693 | return; | |
3694 | ||
3695 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
3696 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
3697 | ||
3698 | temp |= FDI_BC_BIFURCATION_SELECT; | |
3699 | DRM_DEBUG_KMS("enabling fdi C rx\n"); | |
3700 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
3701 | POSTING_READ(SOUTH_CHICKEN1); | |
3702 | } | |
3703 | ||
3704 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
3705 | { | |
3706 | struct drm_device *dev = intel_crtc->base.dev; | |
3707 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3708 | ||
3709 | switch (intel_crtc->pipe) { | |
3710 | case PIPE_A: | |
3711 | break; | |
3712 | case PIPE_B: | |
3713 | if (intel_crtc->config.fdi_lanes > 2) | |
3714 | WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); | |
3715 | else | |
3716 | cpt_enable_fdi_bc_bifurcation(dev); | |
3717 | ||
3718 | break; | |
3719 | case PIPE_C: | |
3720 | cpt_enable_fdi_bc_bifurcation(dev); | |
3721 | ||
3722 | break; | |
3723 | default: | |
3724 | BUG(); | |
3725 | } | |
3726 | } | |
3727 | ||
f67a559d JB |
3728 | /* |
3729 | * Enable PCH resources required for PCH ports: | |
3730 | * - PCH PLLs | |
3731 | * - FDI training & RX/TX | |
3732 | * - update transcoder timings | |
3733 | * - DP transcoding bits | |
3734 | * - transcoder | |
3735 | */ | |
3736 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
3737 | { |
3738 | struct drm_device *dev = crtc->dev; | |
3739 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3740 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3741 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 3742 | u32 reg, temp; |
2c07245f | 3743 | |
ab9412ba | 3744 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 3745 | |
1fbc0d78 DV |
3746 | if (IS_IVYBRIDGE(dev)) |
3747 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
3748 | ||
cd986abb DV |
3749 | /* Write the TU size bits before fdi link training, so that error |
3750 | * detection works. */ | |
3751 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
3752 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
3753 | ||
c98e9dcf | 3754 | /* For PCH output, training FDI link */ |
674cf967 | 3755 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 3756 | |
3ad8a208 DV |
3757 | /* We need to program the right clock selection before writing the pixel |
3758 | * mutliplier into the DPLL. */ | |
303b81e0 | 3759 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 3760 | u32 sel; |
4b645f14 | 3761 | |
c98e9dcf | 3762 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
3763 | temp |= TRANS_DPLL_ENABLE(pipe); |
3764 | sel = TRANS_DPLLB_SEL(pipe); | |
a43f6e0f | 3765 | if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
3766 | temp |= sel; |
3767 | else | |
3768 | temp &= ~sel; | |
c98e9dcf | 3769 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 3770 | } |
5eddb70b | 3771 | |
3ad8a208 DV |
3772 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
3773 | * transcoder, and we actually should do this to not upset any PCH | |
3774 | * transcoder that already use the clock when we share it. | |
3775 | * | |
3776 | * Note that enable_shared_dpll tries to do the right thing, but | |
3777 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
3778 | * the right LVDS enable sequence. */ | |
85b3894f | 3779 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 3780 | |
d9b6cb56 JB |
3781 | /* set transcoder timing, panel must allow it */ |
3782 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 3783 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 3784 | |
303b81e0 | 3785 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 3786 | |
c98e9dcf | 3787 | /* For PCH DP, enable TRANS_DP_CTL */ |
0a88818d | 3788 | if (HAS_PCH_CPT(dev) && intel_crtc->config.has_dp_encoder) { |
dfd07d72 | 3789 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
5eddb70b CW |
3790 | reg = TRANS_DP_CTL(pipe); |
3791 | temp = I915_READ(reg); | |
3792 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
3793 | TRANS_DP_SYNC_MASK | |
3794 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
3795 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
3796 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 3797 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
3798 | |
3799 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 3800 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 3801 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 3802 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
3803 | |
3804 | switch (intel_trans_dp_port_sel(crtc)) { | |
3805 | case PCH_DP_B: | |
5eddb70b | 3806 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
3807 | break; |
3808 | case PCH_DP_C: | |
5eddb70b | 3809 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
3810 | break; |
3811 | case PCH_DP_D: | |
5eddb70b | 3812 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
3813 | break; |
3814 | default: | |
e95d41e1 | 3815 | BUG(); |
32f9d658 | 3816 | } |
2c07245f | 3817 | |
5eddb70b | 3818 | I915_WRITE(reg, temp); |
6be4a607 | 3819 | } |
b52eb4dc | 3820 | |
b8a4f404 | 3821 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
3822 | } |
3823 | ||
1507e5bd PZ |
3824 | static void lpt_pch_enable(struct drm_crtc *crtc) |
3825 | { | |
3826 | struct drm_device *dev = crtc->dev; | |
3827 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3828 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3b117c8f | 3829 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
1507e5bd | 3830 | |
ab9412ba | 3831 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 3832 | |
8c52b5e8 | 3833 | lpt_program_iclkip(crtc); |
1507e5bd | 3834 | |
0540e488 | 3835 | /* Set transcoder timing. */ |
275f01b2 | 3836 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 3837 | |
937bb610 | 3838 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
3839 | } |
3840 | ||
716c2e55 | 3841 | void intel_put_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3842 | { |
e2b78267 | 3843 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
ee7b9f93 JB |
3844 | |
3845 | if (pll == NULL) | |
3846 | return; | |
3847 | ||
3e369b76 | 3848 | if (!(pll->config.crtc_mask & (1 << crtc->pipe))) { |
1e6f2ddc | 3849 | WARN(1, "bad %s crtc mask\n", pll->name); |
ee7b9f93 JB |
3850 | return; |
3851 | } | |
3852 | ||
3e369b76 ACO |
3853 | pll->config.crtc_mask &= ~(1 << crtc->pipe); |
3854 | if (pll->config.crtc_mask == 0) { | |
f4a091c7 DV |
3855 | WARN_ON(pll->on); |
3856 | WARN_ON(pll->active); | |
3857 | } | |
3858 | ||
a43f6e0f | 3859 | crtc->config.shared_dpll = DPLL_ID_PRIVATE; |
ee7b9f93 JB |
3860 | } |
3861 | ||
716c2e55 | 3862 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3863 | { |
e2b78267 | 3864 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
8bd31e67 | 3865 | struct intel_shared_dpll *pll; |
e2b78267 | 3866 | enum intel_dpll_id i; |
ee7b9f93 | 3867 | |
98b6bd99 DV |
3868 | if (HAS_PCH_IBX(dev_priv->dev)) { |
3869 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 3870 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 3871 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 3872 | |
46edb027 DV |
3873 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
3874 | crtc->base.base.id, pll->name); | |
98b6bd99 | 3875 | |
8bd31e67 | 3876 | WARN_ON(pll->new_config->crtc_mask); |
f2a69f44 | 3877 | |
98b6bd99 DV |
3878 | goto found; |
3879 | } | |
3880 | ||
e72f9fbf DV |
3881 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3882 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 JB |
3883 | |
3884 | /* Only want to check enabled timings first */ | |
8bd31e67 | 3885 | if (pll->new_config->crtc_mask == 0) |
ee7b9f93 JB |
3886 | continue; |
3887 | ||
8bd31e67 ACO |
3888 | if (memcmp(&crtc->new_config->dpll_hw_state, |
3889 | &pll->new_config->hw_state, | |
3890 | sizeof(pll->new_config->hw_state)) == 0) { | |
3891 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n", | |
1e6f2ddc | 3892 | crtc->base.base.id, pll->name, |
8bd31e67 ACO |
3893 | pll->new_config->crtc_mask, |
3894 | pll->active); | |
ee7b9f93 JB |
3895 | goto found; |
3896 | } | |
3897 | } | |
3898 | ||
3899 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
3900 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3901 | pll = &dev_priv->shared_dplls[i]; | |
8bd31e67 | 3902 | if (pll->new_config->crtc_mask == 0) { |
46edb027 DV |
3903 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
3904 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
3905 | goto found; |
3906 | } | |
3907 | } | |
3908 | ||
3909 | return NULL; | |
3910 | ||
3911 | found: | |
8bd31e67 ACO |
3912 | if (pll->new_config->crtc_mask == 0) |
3913 | pll->new_config->hw_state = crtc->new_config->dpll_hw_state; | |
f2a69f44 | 3914 | |
8bd31e67 | 3915 | crtc->new_config->shared_dpll = i; |
46edb027 DV |
3916 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
3917 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 3918 | |
8bd31e67 | 3919 | pll->new_config->crtc_mask |= 1 << crtc->pipe; |
e04c7350 | 3920 | |
ee7b9f93 JB |
3921 | return pll; |
3922 | } | |
3923 | ||
8bd31e67 ACO |
3924 | /** |
3925 | * intel_shared_dpll_start_config - start a new PLL staged config | |
3926 | * @dev_priv: DRM device | |
3927 | * @clear_pipes: mask of pipes that will have their PLLs freed | |
3928 | * | |
3929 | * Starts a new PLL staged config, copying the current config but | |
3930 | * releasing the references of pipes specified in clear_pipes. | |
3931 | */ | |
3932 | static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv, | |
3933 | unsigned clear_pipes) | |
3934 | { | |
3935 | struct intel_shared_dpll *pll; | |
3936 | enum intel_dpll_id i; | |
3937 | ||
3938 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
3939 | pll = &dev_priv->shared_dplls[i]; | |
3940 | ||
3941 | pll->new_config = kmemdup(&pll->config, sizeof pll->config, | |
3942 | GFP_KERNEL); | |
3943 | if (!pll->new_config) | |
3944 | goto cleanup; | |
3945 | ||
3946 | pll->new_config->crtc_mask &= ~clear_pipes; | |
3947 | } | |
3948 | ||
3949 | return 0; | |
3950 | ||
3951 | cleanup: | |
3952 | while (--i >= 0) { | |
3953 | pll = &dev_priv->shared_dplls[i]; | |
f354d733 | 3954 | kfree(pll->new_config); |
8bd31e67 ACO |
3955 | pll->new_config = NULL; |
3956 | } | |
3957 | ||
3958 | return -ENOMEM; | |
3959 | } | |
3960 | ||
3961 | static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv) | |
3962 | { | |
3963 | struct intel_shared_dpll *pll; | |
3964 | enum intel_dpll_id i; | |
3965 | ||
3966 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
3967 | pll = &dev_priv->shared_dplls[i]; | |
3968 | ||
3969 | WARN_ON(pll->new_config == &pll->config); | |
3970 | ||
3971 | pll->config = *pll->new_config; | |
3972 | kfree(pll->new_config); | |
3973 | pll->new_config = NULL; | |
3974 | } | |
3975 | } | |
3976 | ||
3977 | static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv) | |
3978 | { | |
3979 | struct intel_shared_dpll *pll; | |
3980 | enum intel_dpll_id i; | |
3981 | ||
3982 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
3983 | pll = &dev_priv->shared_dplls[i]; | |
3984 | ||
3985 | WARN_ON(pll->new_config == &pll->config); | |
3986 | ||
3987 | kfree(pll->new_config); | |
3988 | pll->new_config = NULL; | |
3989 | } | |
3990 | } | |
3991 | ||
a1520318 | 3992 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
3993 | { |
3994 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 3995 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
3996 | u32 temp; |
3997 | ||
3998 | temp = I915_READ(dslreg); | |
3999 | udelay(500); | |
4000 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4001 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4002 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4003 | } |
4004 | } | |
4005 | ||
bd2e244f JB |
4006 | static void skylake_pfit_enable(struct intel_crtc *crtc) |
4007 | { | |
4008 | struct drm_device *dev = crtc->base.dev; | |
4009 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4010 | int pipe = crtc->pipe; | |
4011 | ||
4012 | if (crtc->config.pch_pfit.enabled) { | |
4013 | I915_WRITE(PS_CTL(pipe), PS_ENABLE); | |
4014 | I915_WRITE(PS_WIN_POS(pipe), crtc->config.pch_pfit.pos); | |
4015 | I915_WRITE(PS_WIN_SZ(pipe), crtc->config.pch_pfit.size); | |
4016 | } | |
4017 | } | |
4018 | ||
b074cec8 JB |
4019 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4020 | { | |
4021 | struct drm_device *dev = crtc->base.dev; | |
4022 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4023 | int pipe = crtc->pipe; | |
4024 | ||
fd4daa9c | 4025 | if (crtc->config.pch_pfit.enabled) { |
b074cec8 JB |
4026 | /* Force use of hard-coded filter coefficients |
4027 | * as some pre-programmed values are broken, | |
4028 | * e.g. x201. | |
4029 | */ | |
4030 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4031 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4032 | PF_PIPE_SEL_IVB(pipe)); | |
4033 | else | |
4034 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
4035 | I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos); | |
4036 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size); | |
d4270e57 JB |
4037 | } |
4038 | } | |
4039 | ||
bb53d4ae VS |
4040 | static void intel_enable_planes(struct drm_crtc *crtc) |
4041 | { | |
4042 | struct drm_device *dev = crtc->dev; | |
4043 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 4044 | struct drm_plane *plane; |
bb53d4ae VS |
4045 | struct intel_plane *intel_plane; |
4046 | ||
af2b653b MR |
4047 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
4048 | intel_plane = to_intel_plane(plane); | |
bb53d4ae VS |
4049 | if (intel_plane->pipe == pipe) |
4050 | intel_plane_restore(&intel_plane->base); | |
af2b653b | 4051 | } |
bb53d4ae VS |
4052 | } |
4053 | ||
4054 | static void intel_disable_planes(struct drm_crtc *crtc) | |
4055 | { | |
4056 | struct drm_device *dev = crtc->dev; | |
4057 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 4058 | struct drm_plane *plane; |
bb53d4ae VS |
4059 | struct intel_plane *intel_plane; |
4060 | ||
af2b653b MR |
4061 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
4062 | intel_plane = to_intel_plane(plane); | |
bb53d4ae VS |
4063 | if (intel_plane->pipe == pipe) |
4064 | intel_plane_disable(&intel_plane->base); | |
af2b653b | 4065 | } |
bb53d4ae VS |
4066 | } |
4067 | ||
20bc8673 | 4068 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4069 | { |
cea165c3 VS |
4070 | struct drm_device *dev = crtc->base.dev; |
4071 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 PZ |
4072 | |
4073 | if (!crtc->config.ips_enabled) | |
4074 | return; | |
4075 | ||
cea165c3 VS |
4076 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
4077 | intel_wait_for_vblank(dev, crtc->pipe); | |
4078 | ||
d77e4531 | 4079 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4080 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4081 | mutex_lock(&dev_priv->rps.hw_lock); |
4082 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4083 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4084 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4085 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4086 | * mailbox." Moreover, the mailbox may return a bogus state, |
4087 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4088 | */ |
4089 | } else { | |
4090 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4091 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4092 | * is essentially intel_wait_for_vblank. If we don't have this | |
4093 | * and don't wait for vblanks until the end of crtc_enable, then | |
4094 | * the HW state readout code will complain that the expected | |
4095 | * IPS_CTL value is not the one we read. */ | |
4096 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
4097 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
4098 | } | |
d77e4531 PZ |
4099 | } |
4100 | ||
20bc8673 | 4101 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4102 | { |
4103 | struct drm_device *dev = crtc->base.dev; | |
4104 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4105 | ||
4106 | if (!crtc->config.ips_enabled) | |
4107 | return; | |
4108 | ||
4109 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4110 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4111 | mutex_lock(&dev_priv->rps.hw_lock); |
4112 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4113 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
4114 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
4115 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
4116 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 4117 | } else { |
2a114cc1 | 4118 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4119 | POSTING_READ(IPS_CTL); |
4120 | } | |
d77e4531 PZ |
4121 | |
4122 | /* We need to wait for a vblank before we can disable the plane. */ | |
4123 | intel_wait_for_vblank(dev, crtc->pipe); | |
4124 | } | |
4125 | ||
4126 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
4127 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
4128 | { | |
4129 | struct drm_device *dev = crtc->dev; | |
4130 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4131 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4132 | enum pipe pipe = intel_crtc->pipe; | |
4133 | int palreg = PALETTE(pipe); | |
4134 | int i; | |
4135 | bool reenable_ips = false; | |
4136 | ||
4137 | /* The clocks have to be on to load the palette. */ | |
4138 | if (!crtc->enabled || !intel_crtc->active) | |
4139 | return; | |
4140 | ||
4141 | if (!HAS_PCH_SPLIT(dev_priv->dev)) { | |
409ee761 | 4142 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) |
d77e4531 PZ |
4143 | assert_dsi_pll_enabled(dev_priv); |
4144 | else | |
4145 | assert_pll_enabled(dev_priv, pipe); | |
4146 | } | |
4147 | ||
4148 | /* use legacy palette for Ironlake */ | |
7a1db49a | 4149 | if (!HAS_GMCH_DISPLAY(dev)) |
d77e4531 PZ |
4150 | palreg = LGC_PALETTE(pipe); |
4151 | ||
4152 | /* Workaround : Do not read or write the pipe palette/gamma data while | |
4153 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
4154 | */ | |
41e6fc4c | 4155 | if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled && |
d77e4531 PZ |
4156 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
4157 | GAMMA_MODE_MODE_SPLIT)) { | |
4158 | hsw_disable_ips(intel_crtc); | |
4159 | reenable_ips = true; | |
4160 | } | |
4161 | ||
4162 | for (i = 0; i < 256; i++) { | |
4163 | I915_WRITE(palreg + 4 * i, | |
4164 | (intel_crtc->lut_r[i] << 16) | | |
4165 | (intel_crtc->lut_g[i] << 8) | | |
4166 | intel_crtc->lut_b[i]); | |
4167 | } | |
4168 | ||
4169 | if (reenable_ips) | |
4170 | hsw_enable_ips(intel_crtc); | |
4171 | } | |
4172 | ||
d3eedb1a VS |
4173 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
4174 | { | |
4175 | if (!enable && intel_crtc->overlay) { | |
4176 | struct drm_device *dev = intel_crtc->base.dev; | |
4177 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4178 | ||
4179 | mutex_lock(&dev->struct_mutex); | |
4180 | dev_priv->mm.interruptible = false; | |
4181 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4182 | dev_priv->mm.interruptible = true; | |
4183 | mutex_unlock(&dev->struct_mutex); | |
4184 | } | |
4185 | ||
4186 | /* Let userspace switch the overlay on again. In most cases userspace | |
4187 | * has to recompute where to put it anyway. | |
4188 | */ | |
4189 | } | |
4190 | ||
d3eedb1a | 4191 | static void intel_crtc_enable_planes(struct drm_crtc *crtc) |
a5c4d7bc VS |
4192 | { |
4193 | struct drm_device *dev = crtc->dev; | |
a5c4d7bc VS |
4194 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4195 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4196 | |
fdd508a6 | 4197 | intel_enable_primary_hw_plane(crtc->primary, crtc); |
a5c4d7bc VS |
4198 | intel_enable_planes(crtc); |
4199 | intel_crtc_update_cursor(crtc, true); | |
d3eedb1a | 4200 | intel_crtc_dpms_overlay(intel_crtc, true); |
a5c4d7bc VS |
4201 | |
4202 | hsw_enable_ips(intel_crtc); | |
4203 | ||
4204 | mutex_lock(&dev->struct_mutex); | |
4205 | intel_update_fbc(dev); | |
4206 | mutex_unlock(&dev->struct_mutex); | |
f99d7069 DV |
4207 | |
4208 | /* | |
4209 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4210 | * to compute the mask of flip planes precisely. For the time being | |
4211 | * consider this a flip from a NULL plane. | |
4212 | */ | |
4213 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4214 | } |
4215 | ||
d3eedb1a | 4216 | static void intel_crtc_disable_planes(struct drm_crtc *crtc) |
a5c4d7bc VS |
4217 | { |
4218 | struct drm_device *dev = crtc->dev; | |
4219 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4220 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4221 | int pipe = intel_crtc->pipe; | |
4222 | int plane = intel_crtc->plane; | |
4223 | ||
4224 | intel_crtc_wait_for_pending_flips(crtc); | |
a5c4d7bc VS |
4225 | |
4226 | if (dev_priv->fbc.plane == plane) | |
4227 | intel_disable_fbc(dev); | |
4228 | ||
4229 | hsw_disable_ips(intel_crtc); | |
4230 | ||
d3eedb1a | 4231 | intel_crtc_dpms_overlay(intel_crtc, false); |
a5c4d7bc VS |
4232 | intel_crtc_update_cursor(crtc, false); |
4233 | intel_disable_planes(crtc); | |
fdd508a6 | 4234 | intel_disable_primary_hw_plane(crtc->primary, crtc); |
f98551ae | 4235 | |
f99d7069 DV |
4236 | /* |
4237 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4238 | * to compute the mask of flip planes precisely. For the time being | |
4239 | * consider this a flip to a NULL plane. | |
4240 | */ | |
4241 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4242 | } |
4243 | ||
f67a559d JB |
4244 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4245 | { | |
4246 | struct drm_device *dev = crtc->dev; | |
4247 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4248 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4249 | struct intel_encoder *encoder; |
f67a559d | 4250 | int pipe = intel_crtc->pipe; |
f67a559d | 4251 | |
08a48469 DV |
4252 | WARN_ON(!crtc->enabled); |
4253 | ||
f67a559d JB |
4254 | if (intel_crtc->active) |
4255 | return; | |
4256 | ||
b14b1055 DV |
4257 | if (intel_crtc->config.has_pch_encoder) |
4258 | intel_prepare_shared_dpll(intel_crtc); | |
4259 | ||
29407aab DV |
4260 | if (intel_crtc->config.has_dp_encoder) |
4261 | intel_dp_set_m_n(intel_crtc); | |
4262 | ||
4263 | intel_set_pipe_timings(intel_crtc); | |
4264 | ||
4265 | if (intel_crtc->config.has_pch_encoder) { | |
4266 | intel_cpu_transcoder_set_m_n(intel_crtc, | |
f769cd24 | 4267 | &intel_crtc->config.fdi_m_n, NULL); |
29407aab DV |
4268 | } |
4269 | ||
4270 | ironlake_set_pipeconf(crtc); | |
4271 | ||
f67a559d | 4272 | intel_crtc->active = true; |
8664281b | 4273 | |
a72e4c9f DV |
4274 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4275 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
8664281b | 4276 | |
f6736a1a | 4277 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4278 | if (encoder->pre_enable) |
4279 | encoder->pre_enable(encoder); | |
f67a559d | 4280 | |
5bfe2ac0 | 4281 | if (intel_crtc->config.has_pch_encoder) { |
fff367c7 DV |
4282 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4283 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4284 | * enabling. */ | |
88cefb6c | 4285 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4286 | } else { |
4287 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4288 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4289 | } | |
f67a559d | 4290 | |
b074cec8 | 4291 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4292 | |
9c54c0dd JB |
4293 | /* |
4294 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4295 | * clocks enabled | |
4296 | */ | |
4297 | intel_crtc_load_lut(crtc); | |
4298 | ||
f37fcc2a | 4299 | intel_update_watermarks(crtc); |
e1fdc473 | 4300 | intel_enable_pipe(intel_crtc); |
f67a559d | 4301 | |
5bfe2ac0 | 4302 | if (intel_crtc->config.has_pch_encoder) |
f67a559d | 4303 | ironlake_pch_enable(crtc); |
c98e9dcf | 4304 | |
fa5c73b1 DV |
4305 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4306 | encoder->enable(encoder); | |
61b77ddd DV |
4307 | |
4308 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4309 | cpt_verify_modeset(dev, intel_crtc->pipe); |
6ce94100 | 4310 | |
4b3a9526 VS |
4311 | assert_vblank_disabled(crtc); |
4312 | drm_crtc_vblank_on(crtc); | |
4313 | ||
d3eedb1a | 4314 | intel_crtc_enable_planes(crtc); |
6be4a607 JB |
4315 | } |
4316 | ||
42db64ef PZ |
4317 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4318 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4319 | { | |
f5adf94e | 4320 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4321 | } |
4322 | ||
e4916946 PZ |
4323 | /* |
4324 | * This implements the workaround described in the "notes" section of the mode | |
4325 | * set sequence documentation. When going from no pipes or single pipe to | |
4326 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
4327 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
4328 | */ | |
4329 | static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) | |
4330 | { | |
4331 | struct drm_device *dev = crtc->base.dev; | |
4332 | struct intel_crtc *crtc_it, *other_active_crtc = NULL; | |
4333 | ||
4334 | /* We want to get the other_active_crtc only if there's only 1 other | |
4335 | * active crtc. */ | |
d3fcc808 | 4336 | for_each_intel_crtc(dev, crtc_it) { |
e4916946 PZ |
4337 | if (!crtc_it->active || crtc_it == crtc) |
4338 | continue; | |
4339 | ||
4340 | if (other_active_crtc) | |
4341 | return; | |
4342 | ||
4343 | other_active_crtc = crtc_it; | |
4344 | } | |
4345 | if (!other_active_crtc) | |
4346 | return; | |
4347 | ||
4348 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4349 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4350 | } | |
4351 | ||
4f771f10 PZ |
4352 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4353 | { | |
4354 | struct drm_device *dev = crtc->dev; | |
4355 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4356 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4357 | struct intel_encoder *encoder; | |
4358 | int pipe = intel_crtc->pipe; | |
4f771f10 PZ |
4359 | |
4360 | WARN_ON(!crtc->enabled); | |
4361 | ||
4362 | if (intel_crtc->active) | |
4363 | return; | |
4364 | ||
df8ad70c DV |
4365 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
4366 | intel_enable_shared_dpll(intel_crtc); | |
4367 | ||
229fca97 DV |
4368 | if (intel_crtc->config.has_dp_encoder) |
4369 | intel_dp_set_m_n(intel_crtc); | |
4370 | ||
4371 | intel_set_pipe_timings(intel_crtc); | |
4372 | ||
ebb69c95 CT |
4373 | if (intel_crtc->config.cpu_transcoder != TRANSCODER_EDP) { |
4374 | I915_WRITE(PIPE_MULT(intel_crtc->config.cpu_transcoder), | |
4375 | intel_crtc->config.pixel_multiplier - 1); | |
4376 | } | |
4377 | ||
229fca97 DV |
4378 | if (intel_crtc->config.has_pch_encoder) { |
4379 | intel_cpu_transcoder_set_m_n(intel_crtc, | |
f769cd24 | 4380 | &intel_crtc->config.fdi_m_n, NULL); |
229fca97 DV |
4381 | } |
4382 | ||
4383 | haswell_set_pipeconf(crtc); | |
4384 | ||
4385 | intel_set_pipe_csc(crtc); | |
4386 | ||
4f771f10 | 4387 | intel_crtc->active = true; |
8664281b | 4388 | |
a72e4c9f | 4389 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4f771f10 PZ |
4390 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4391 | if (encoder->pre_enable) | |
4392 | encoder->pre_enable(encoder); | |
4393 | ||
4fe9467d | 4394 | if (intel_crtc->config.has_pch_encoder) { |
a72e4c9f DV |
4395 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
4396 | true); | |
4fe9467d ID |
4397 | dev_priv->display.fdi_link_train(crtc); |
4398 | } | |
4399 | ||
1f544388 | 4400 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 4401 | |
bd2e244f JB |
4402 | if (IS_SKYLAKE(dev)) |
4403 | skylake_pfit_enable(intel_crtc); | |
4404 | else | |
4405 | ironlake_pfit_enable(intel_crtc); | |
4f771f10 PZ |
4406 | |
4407 | /* | |
4408 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4409 | * clocks enabled | |
4410 | */ | |
4411 | intel_crtc_load_lut(crtc); | |
4412 | ||
1f544388 | 4413 | intel_ddi_set_pipe_settings(crtc); |
8228c251 | 4414 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 4415 | |
f37fcc2a | 4416 | intel_update_watermarks(crtc); |
e1fdc473 | 4417 | intel_enable_pipe(intel_crtc); |
42db64ef | 4418 | |
5bfe2ac0 | 4419 | if (intel_crtc->config.has_pch_encoder) |
1507e5bd | 4420 | lpt_pch_enable(crtc); |
4f771f10 | 4421 | |
0e32b39c DA |
4422 | if (intel_crtc->config.dp_encoder_is_mst) |
4423 | intel_ddi_set_vc_payload_alloc(crtc, true); | |
4424 | ||
8807e55b | 4425 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 4426 | encoder->enable(encoder); |
8807e55b JN |
4427 | intel_opregion_notify_encoder(encoder, true); |
4428 | } | |
4f771f10 | 4429 | |
4b3a9526 VS |
4430 | assert_vblank_disabled(crtc); |
4431 | drm_crtc_vblank_on(crtc); | |
4432 | ||
e4916946 PZ |
4433 | /* If we change the relative order between pipe/planes enabling, we need |
4434 | * to change the workaround. */ | |
4435 | haswell_mode_set_planes_workaround(intel_crtc); | |
d3eedb1a | 4436 | intel_crtc_enable_planes(crtc); |
4f771f10 PZ |
4437 | } |
4438 | ||
bd2e244f JB |
4439 | static void skylake_pfit_disable(struct intel_crtc *crtc) |
4440 | { | |
4441 | struct drm_device *dev = crtc->base.dev; | |
4442 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4443 | int pipe = crtc->pipe; | |
4444 | ||
4445 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
4446 | * it's in use. The hw state code will make sure we get this right. */ | |
4447 | if (crtc->config.pch_pfit.enabled) { | |
4448 | I915_WRITE(PS_CTL(pipe), 0); | |
4449 | I915_WRITE(PS_WIN_POS(pipe), 0); | |
4450 | I915_WRITE(PS_WIN_SZ(pipe), 0); | |
4451 | } | |
4452 | } | |
4453 | ||
3f8dce3a DV |
4454 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
4455 | { | |
4456 | struct drm_device *dev = crtc->base.dev; | |
4457 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4458 | int pipe = crtc->pipe; | |
4459 | ||
4460 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
4461 | * it's in use. The hw state code will make sure we get this right. */ | |
fd4daa9c | 4462 | if (crtc->config.pch_pfit.enabled) { |
3f8dce3a DV |
4463 | I915_WRITE(PF_CTL(pipe), 0); |
4464 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
4465 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
4466 | } | |
4467 | } | |
4468 | ||
6be4a607 JB |
4469 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
4470 | { | |
4471 | struct drm_device *dev = crtc->dev; | |
4472 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4473 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4474 | struct intel_encoder *encoder; |
6be4a607 | 4475 | int pipe = intel_crtc->pipe; |
5eddb70b | 4476 | u32 reg, temp; |
b52eb4dc | 4477 | |
f7abfe8b CW |
4478 | if (!intel_crtc->active) |
4479 | return; | |
4480 | ||
d3eedb1a | 4481 | intel_crtc_disable_planes(crtc); |
a5c4d7bc | 4482 | |
4b3a9526 VS |
4483 | drm_crtc_vblank_off(crtc); |
4484 | assert_vblank_disabled(crtc); | |
4485 | ||
ea9d758d DV |
4486 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4487 | encoder->disable(encoder); | |
4488 | ||
d925c59a | 4489 | if (intel_crtc->config.has_pch_encoder) |
a72e4c9f | 4490 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
d925c59a | 4491 | |
575f7ab7 | 4492 | intel_disable_pipe(intel_crtc); |
32f9d658 | 4493 | |
3f8dce3a | 4494 | ironlake_pfit_disable(intel_crtc); |
2c07245f | 4495 | |
bf49ec8c DV |
4496 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4497 | if (encoder->post_disable) | |
4498 | encoder->post_disable(encoder); | |
2c07245f | 4499 | |
d925c59a DV |
4500 | if (intel_crtc->config.has_pch_encoder) { |
4501 | ironlake_fdi_disable(crtc); | |
913d8d11 | 4502 | |
d925c59a | 4503 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
a72e4c9f | 4504 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 | 4505 | |
d925c59a DV |
4506 | if (HAS_PCH_CPT(dev)) { |
4507 | /* disable TRANS_DP_CTL */ | |
4508 | reg = TRANS_DP_CTL(pipe); | |
4509 | temp = I915_READ(reg); | |
4510 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
4511 | TRANS_DP_PORT_SEL_MASK); | |
4512 | temp |= TRANS_DP_PORT_SEL_NONE; | |
4513 | I915_WRITE(reg, temp); | |
4514 | ||
4515 | /* disable DPLL_SEL */ | |
4516 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 4517 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 4518 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 4519 | } |
e3421a18 | 4520 | |
d925c59a | 4521 | /* disable PCH DPLL */ |
e72f9fbf | 4522 | intel_disable_shared_dpll(intel_crtc); |
8db9d77b | 4523 | |
d925c59a DV |
4524 | ironlake_fdi_pll_disable(intel_crtc); |
4525 | } | |
6b383a7f | 4526 | |
f7abfe8b | 4527 | intel_crtc->active = false; |
46ba614c | 4528 | intel_update_watermarks(crtc); |
d1ebd816 BW |
4529 | |
4530 | mutex_lock(&dev->struct_mutex); | |
6b383a7f | 4531 | intel_update_fbc(dev); |
d1ebd816 | 4532 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 4533 | } |
1b3c7a47 | 4534 | |
4f771f10 | 4535 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 4536 | { |
4f771f10 PZ |
4537 | struct drm_device *dev = crtc->dev; |
4538 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 4539 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 4540 | struct intel_encoder *encoder; |
3b117c8f | 4541 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee7b9f93 | 4542 | |
4f771f10 PZ |
4543 | if (!intel_crtc->active) |
4544 | return; | |
4545 | ||
d3eedb1a | 4546 | intel_crtc_disable_planes(crtc); |
dda9a66a | 4547 | |
4b3a9526 VS |
4548 | drm_crtc_vblank_off(crtc); |
4549 | assert_vblank_disabled(crtc); | |
4550 | ||
8807e55b JN |
4551 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4552 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 4553 | encoder->disable(encoder); |
8807e55b | 4554 | } |
4f771f10 | 4555 | |
8664281b | 4556 | if (intel_crtc->config.has_pch_encoder) |
a72e4c9f DV |
4557 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
4558 | false); | |
575f7ab7 | 4559 | intel_disable_pipe(intel_crtc); |
4f771f10 | 4560 | |
a4bf214f VS |
4561 | if (intel_crtc->config.dp_encoder_is_mst) |
4562 | intel_ddi_set_vc_payload_alloc(crtc, false); | |
4563 | ||
ad80a810 | 4564 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 4565 | |
bd2e244f JB |
4566 | if (IS_SKYLAKE(dev)) |
4567 | skylake_pfit_disable(intel_crtc); | |
4568 | else | |
4569 | ironlake_pfit_disable(intel_crtc); | |
4f771f10 | 4570 | |
1f544388 | 4571 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 4572 | |
88adfff1 | 4573 | if (intel_crtc->config.has_pch_encoder) { |
ab4d966c | 4574 | lpt_disable_pch_transcoder(dev_priv); |
a72e4c9f DV |
4575 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
4576 | true); | |
1ad960f2 | 4577 | intel_ddi_fdi_disable(crtc); |
83616634 | 4578 | } |
4f771f10 | 4579 | |
97b040aa ID |
4580 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4581 | if (encoder->post_disable) | |
4582 | encoder->post_disable(encoder); | |
4583 | ||
4f771f10 | 4584 | intel_crtc->active = false; |
46ba614c | 4585 | intel_update_watermarks(crtc); |
4f771f10 PZ |
4586 | |
4587 | mutex_lock(&dev->struct_mutex); | |
4588 | intel_update_fbc(dev); | |
4589 | mutex_unlock(&dev->struct_mutex); | |
df8ad70c DV |
4590 | |
4591 | if (intel_crtc_to_shared_dpll(intel_crtc)) | |
4592 | intel_disable_shared_dpll(intel_crtc); | |
4f771f10 PZ |
4593 | } |
4594 | ||
ee7b9f93 JB |
4595 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
4596 | { | |
4597 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e72f9fbf | 4598 | intel_put_shared_dpll(intel_crtc); |
ee7b9f93 JB |
4599 | } |
4600 | ||
6441ab5f | 4601 | |
2dd24552 JB |
4602 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
4603 | { | |
4604 | struct drm_device *dev = crtc->base.dev; | |
4605 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4606 | struct intel_crtc_config *pipe_config = &crtc->config; | |
4607 | ||
328d8e82 | 4608 | if (!crtc->config.gmch_pfit.control) |
2dd24552 JB |
4609 | return; |
4610 | ||
2dd24552 | 4611 | /* |
c0b03411 DV |
4612 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
4613 | * according to register description and PRM. | |
2dd24552 | 4614 | */ |
c0b03411 DV |
4615 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
4616 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 4617 | |
b074cec8 JB |
4618 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
4619 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
4620 | |
4621 | /* Border color in case we don't scale up to the full screen. Black by | |
4622 | * default, change to something else for debugging. */ | |
4623 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
4624 | } |
4625 | ||
d05410f9 DA |
4626 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
4627 | { | |
4628 | switch (port) { | |
4629 | case PORT_A: | |
4630 | return POWER_DOMAIN_PORT_DDI_A_4_LANES; | |
4631 | case PORT_B: | |
4632 | return POWER_DOMAIN_PORT_DDI_B_4_LANES; | |
4633 | case PORT_C: | |
4634 | return POWER_DOMAIN_PORT_DDI_C_4_LANES; | |
4635 | case PORT_D: | |
4636 | return POWER_DOMAIN_PORT_DDI_D_4_LANES; | |
4637 | default: | |
4638 | WARN_ON_ONCE(1); | |
4639 | return POWER_DOMAIN_PORT_OTHER; | |
4640 | } | |
4641 | } | |
4642 | ||
77d22dca ID |
4643 | #define for_each_power_domain(domain, mask) \ |
4644 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
4645 | if ((1 << (domain)) & (mask)) | |
4646 | ||
319be8ae ID |
4647 | enum intel_display_power_domain |
4648 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
4649 | { | |
4650 | struct drm_device *dev = intel_encoder->base.dev; | |
4651 | struct intel_digital_port *intel_dig_port; | |
4652 | ||
4653 | switch (intel_encoder->type) { | |
4654 | case INTEL_OUTPUT_UNKNOWN: | |
4655 | /* Only DDI platforms should ever use this output type */ | |
4656 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
4657 | case INTEL_OUTPUT_DISPLAYPORT: | |
4658 | case INTEL_OUTPUT_HDMI: | |
4659 | case INTEL_OUTPUT_EDP: | |
4660 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 4661 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
4662 | case INTEL_OUTPUT_DP_MST: |
4663 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
4664 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
4665 | case INTEL_OUTPUT_ANALOG: |
4666 | return POWER_DOMAIN_PORT_CRT; | |
4667 | case INTEL_OUTPUT_DSI: | |
4668 | return POWER_DOMAIN_PORT_DSI; | |
4669 | default: | |
4670 | return POWER_DOMAIN_PORT_OTHER; | |
4671 | } | |
4672 | } | |
4673 | ||
4674 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) | |
77d22dca | 4675 | { |
319be8ae ID |
4676 | struct drm_device *dev = crtc->dev; |
4677 | struct intel_encoder *intel_encoder; | |
4678 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4679 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca ID |
4680 | unsigned long mask; |
4681 | enum transcoder transcoder; | |
4682 | ||
4683 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); | |
4684 | ||
4685 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); | |
4686 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
fabf6e51 DV |
4687 | if (intel_crtc->config.pch_pfit.enabled || |
4688 | intel_crtc->config.pch_pfit.force_thru) | |
77d22dca ID |
4689 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
4690 | ||
319be8ae ID |
4691 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
4692 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); | |
4693 | ||
77d22dca ID |
4694 | return mask; |
4695 | } | |
4696 | ||
77d22dca ID |
4697 | static void modeset_update_crtc_power_domains(struct drm_device *dev) |
4698 | { | |
4699 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4700 | unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; | |
4701 | struct intel_crtc *crtc; | |
4702 | ||
4703 | /* | |
4704 | * First get all needed power domains, then put all unneeded, to avoid | |
4705 | * any unnecessary toggling of the power wells. | |
4706 | */ | |
d3fcc808 | 4707 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
4708 | enum intel_display_power_domain domain; |
4709 | ||
4710 | if (!crtc->base.enabled) | |
4711 | continue; | |
4712 | ||
319be8ae | 4713 | pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base); |
77d22dca ID |
4714 | |
4715 | for_each_power_domain(domain, pipe_domains[crtc->pipe]) | |
4716 | intel_display_power_get(dev_priv, domain); | |
4717 | } | |
4718 | ||
50f6e502 VS |
4719 | if (dev_priv->display.modeset_global_resources) |
4720 | dev_priv->display.modeset_global_resources(dev); | |
4721 | ||
d3fcc808 | 4722 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
4723 | enum intel_display_power_domain domain; |
4724 | ||
4725 | for_each_power_domain(domain, crtc->enabled_power_domains) | |
4726 | intel_display_power_put(dev_priv, domain); | |
4727 | ||
4728 | crtc->enabled_power_domains = pipe_domains[crtc->pipe]; | |
4729 | } | |
4730 | ||
4731 | intel_display_set_init_power(dev_priv, false); | |
4732 | } | |
4733 | ||
dfcab17e | 4734 | /* returns HPLL frequency in kHz */ |
f8bf63fd | 4735 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) |
30a970c6 | 4736 | { |
586f49dc | 4737 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
30a970c6 | 4738 | |
586f49dc JB |
4739 | /* Obtain SKU information */ |
4740 | mutex_lock(&dev_priv->dpio_lock); | |
4741 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
4742 | CCK_FUSE_HPLL_FREQ_MASK; | |
4743 | mutex_unlock(&dev_priv->dpio_lock); | |
30a970c6 | 4744 | |
dfcab17e | 4745 | return vco_freq[hpll_freq] * 1000; |
30a970c6 JB |
4746 | } |
4747 | ||
f8bf63fd VS |
4748 | static void vlv_update_cdclk(struct drm_device *dev) |
4749 | { | |
4750 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4751 | ||
4752 | dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
43dc52c3 | 4753 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", |
f8bf63fd VS |
4754 | dev_priv->vlv_cdclk_freq); |
4755 | ||
4756 | /* | |
4757 | * Program the gmbus_freq based on the cdclk frequency. | |
4758 | * BSpec erroneously claims we should aim for 4MHz, but | |
4759 | * in fact 1MHz is the correct frequency. | |
4760 | */ | |
6be1e3d3 | 4761 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000)); |
f8bf63fd VS |
4762 | } |
4763 | ||
30a970c6 JB |
4764 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
4765 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
4766 | { | |
4767 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4768 | u32 val, cmd; | |
4769 | ||
d197b7d3 | 4770 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq); |
d60c4473 | 4771 | |
dfcab17e | 4772 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 4773 | cmd = 2; |
dfcab17e | 4774 | else if (cdclk == 266667) |
30a970c6 JB |
4775 | cmd = 1; |
4776 | else | |
4777 | cmd = 0; | |
4778 | ||
4779 | mutex_lock(&dev_priv->rps.hw_lock); | |
4780 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
4781 | val &= ~DSPFREQGUAR_MASK; | |
4782 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
4783 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
4784 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
4785 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
4786 | 50)) { | |
4787 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
4788 | } | |
4789 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4790 | ||
dfcab17e | 4791 | if (cdclk == 400000) { |
6bcda4f0 | 4792 | u32 divider; |
30a970c6 | 4793 | |
6bcda4f0 | 4794 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 JB |
4795 | |
4796 | mutex_lock(&dev_priv->dpio_lock); | |
4797 | /* adjust cdclk divider */ | |
4798 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
9cf33db5 | 4799 | val &= ~DISPLAY_FREQUENCY_VALUES; |
30a970c6 JB |
4800 | val |= divider; |
4801 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
4802 | |
4803 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
4804 | DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
4805 | 50)) | |
4806 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
4807 | mutex_unlock(&dev_priv->dpio_lock); |
4808 | } | |
4809 | ||
4810 | mutex_lock(&dev_priv->dpio_lock); | |
4811 | /* adjust self-refresh exit latency value */ | |
4812 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
4813 | val &= ~0x7f; | |
4814 | ||
4815 | /* | |
4816 | * For high bandwidth configs, we set a higher latency in the bunit | |
4817 | * so that the core display fetch happens in time to avoid underruns. | |
4818 | */ | |
dfcab17e | 4819 | if (cdclk == 400000) |
30a970c6 JB |
4820 | val |= 4500 / 250; /* 4.5 usec */ |
4821 | else | |
4822 | val |= 3000 / 250; /* 3.0 usec */ | |
4823 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
4824 | mutex_unlock(&dev_priv->dpio_lock); | |
4825 | ||
f8bf63fd | 4826 | vlv_update_cdclk(dev); |
30a970c6 JB |
4827 | } |
4828 | ||
383c5a6a VS |
4829 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
4830 | { | |
4831 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4832 | u32 val, cmd; | |
4833 | ||
4834 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq); | |
4835 | ||
4836 | switch (cdclk) { | |
4837 | case 400000: | |
4838 | cmd = 3; | |
4839 | break; | |
4840 | case 333333: | |
4841 | case 320000: | |
4842 | cmd = 2; | |
4843 | break; | |
4844 | case 266667: | |
4845 | cmd = 1; | |
4846 | break; | |
4847 | case 200000: | |
4848 | cmd = 0; | |
4849 | break; | |
4850 | default: | |
4851 | WARN_ON(1); | |
4852 | return; | |
4853 | } | |
4854 | ||
4855 | mutex_lock(&dev_priv->rps.hw_lock); | |
4856 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
4857 | val &= ~DSPFREQGUAR_MASK_CHV; | |
4858 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
4859 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
4860 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
4861 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
4862 | 50)) { | |
4863 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
4864 | } | |
4865 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4866 | ||
4867 | vlv_update_cdclk(dev); | |
4868 | } | |
4869 | ||
30a970c6 JB |
4870 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
4871 | int max_pixclk) | |
4872 | { | |
6bcda4f0 | 4873 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
29dc7ef3 | 4874 | |
d49a340d VS |
4875 | /* FIXME: Punit isn't quite ready yet */ |
4876 | if (IS_CHERRYVIEW(dev_priv->dev)) | |
4877 | return 400000; | |
4878 | ||
30a970c6 JB |
4879 | /* |
4880 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
4881 | * 200MHz | |
4882 | * 267MHz | |
29dc7ef3 | 4883 | * 320/333MHz (depends on HPLL freq) |
30a970c6 JB |
4884 | * 400MHz |
4885 | * So we check to see whether we're above 90% of the lower bin and | |
4886 | * adjust if needed. | |
e37c67a1 VS |
4887 | * |
4888 | * We seem to get an unstable or solid color picture at 200MHz. | |
4889 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
4890 | * are off. | |
30a970c6 | 4891 | */ |
29dc7ef3 | 4892 | if (max_pixclk > freq_320*9/10) |
dfcab17e VS |
4893 | return 400000; |
4894 | else if (max_pixclk > 266667*9/10) | |
29dc7ef3 | 4895 | return freq_320; |
e37c67a1 | 4896 | else if (max_pixclk > 0) |
dfcab17e | 4897 | return 266667; |
e37c67a1 VS |
4898 | else |
4899 | return 200000; | |
30a970c6 JB |
4900 | } |
4901 | ||
2f2d7aa1 VS |
4902 | /* compute the max pixel clock for new configuration */ |
4903 | static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv) | |
30a970c6 JB |
4904 | { |
4905 | struct drm_device *dev = dev_priv->dev; | |
4906 | struct intel_crtc *intel_crtc; | |
4907 | int max_pixclk = 0; | |
4908 | ||
d3fcc808 | 4909 | for_each_intel_crtc(dev, intel_crtc) { |
2f2d7aa1 | 4910 | if (intel_crtc->new_enabled) |
30a970c6 | 4911 | max_pixclk = max(max_pixclk, |
2f2d7aa1 | 4912 | intel_crtc->new_config->adjusted_mode.crtc_clock); |
30a970c6 JB |
4913 | } |
4914 | ||
4915 | return max_pixclk; | |
4916 | } | |
4917 | ||
4918 | static void valleyview_modeset_global_pipes(struct drm_device *dev, | |
2f2d7aa1 | 4919 | unsigned *prepare_pipes) |
30a970c6 JB |
4920 | { |
4921 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4922 | struct intel_crtc *intel_crtc; | |
2f2d7aa1 | 4923 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
30a970c6 | 4924 | |
d60c4473 ID |
4925 | if (valleyview_calc_cdclk(dev_priv, max_pixclk) == |
4926 | dev_priv->vlv_cdclk_freq) | |
30a970c6 JB |
4927 | return; |
4928 | ||
2f2d7aa1 | 4929 | /* disable/enable all currently active pipes while we change cdclk */ |
d3fcc808 | 4930 | for_each_intel_crtc(dev, intel_crtc) |
30a970c6 JB |
4931 | if (intel_crtc->base.enabled) |
4932 | *prepare_pipes |= (1 << intel_crtc->pipe); | |
4933 | } | |
4934 | ||
4935 | static void valleyview_modeset_global_resources(struct drm_device *dev) | |
4936 | { | |
4937 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2f2d7aa1 | 4938 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
30a970c6 JB |
4939 | int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); |
4940 | ||
383c5a6a | 4941 | if (req_cdclk != dev_priv->vlv_cdclk_freq) { |
738c05c0 ID |
4942 | /* |
4943 | * FIXME: We can end up here with all power domains off, yet | |
4944 | * with a CDCLK frequency other than the minimum. To account | |
4945 | * for this take the PIPE-A power domain, which covers the HW | |
4946 | * blocks needed for the following programming. This can be | |
4947 | * removed once it's guaranteed that we get here either with | |
4948 | * the minimum CDCLK set, or the required power domains | |
4949 | * enabled. | |
4950 | */ | |
4951 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
4952 | ||
383c5a6a VS |
4953 | if (IS_CHERRYVIEW(dev)) |
4954 | cherryview_set_cdclk(dev, req_cdclk); | |
4955 | else | |
4956 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 ID |
4957 | |
4958 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); | |
383c5a6a | 4959 | } |
30a970c6 JB |
4960 | } |
4961 | ||
89b667f8 JB |
4962 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
4963 | { | |
4964 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 4965 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
4966 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4967 | struct intel_encoder *encoder; | |
4968 | int pipe = intel_crtc->pipe; | |
23538ef1 | 4969 | bool is_dsi; |
89b667f8 JB |
4970 | |
4971 | WARN_ON(!crtc->enabled); | |
4972 | ||
4973 | if (intel_crtc->active) | |
4974 | return; | |
4975 | ||
409ee761 | 4976 | is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI); |
8525a235 | 4977 | |
1ae0d137 VS |
4978 | if (!is_dsi) { |
4979 | if (IS_CHERRYVIEW(dev)) | |
d288f65f | 4980 | chv_prepare_pll(intel_crtc, &intel_crtc->config); |
1ae0d137 | 4981 | else |
d288f65f | 4982 | vlv_prepare_pll(intel_crtc, &intel_crtc->config); |
1ae0d137 | 4983 | } |
5b18e57c DV |
4984 | |
4985 | if (intel_crtc->config.has_dp_encoder) | |
4986 | intel_dp_set_m_n(intel_crtc); | |
4987 | ||
4988 | intel_set_pipe_timings(intel_crtc); | |
4989 | ||
c14b0485 VS |
4990 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
4991 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4992 | ||
4993 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
4994 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
4995 | } | |
4996 | ||
5b18e57c DV |
4997 | i9xx_set_pipeconf(intel_crtc); |
4998 | ||
89b667f8 | 4999 | intel_crtc->active = true; |
89b667f8 | 5000 | |
a72e4c9f | 5001 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 5002 | |
89b667f8 JB |
5003 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5004 | if (encoder->pre_pll_enable) | |
5005 | encoder->pre_pll_enable(encoder); | |
5006 | ||
9d556c99 CML |
5007 | if (!is_dsi) { |
5008 | if (IS_CHERRYVIEW(dev)) | |
d288f65f | 5009 | chv_enable_pll(intel_crtc, &intel_crtc->config); |
9d556c99 | 5010 | else |
d288f65f | 5011 | vlv_enable_pll(intel_crtc, &intel_crtc->config); |
9d556c99 | 5012 | } |
89b667f8 JB |
5013 | |
5014 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
5015 | if (encoder->pre_enable) | |
5016 | encoder->pre_enable(encoder); | |
5017 | ||
2dd24552 JB |
5018 | i9xx_pfit_enable(intel_crtc); |
5019 | ||
63cbb074 VS |
5020 | intel_crtc_load_lut(crtc); |
5021 | ||
f37fcc2a | 5022 | intel_update_watermarks(crtc); |
e1fdc473 | 5023 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 5024 | |
5004945f JN |
5025 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5026 | encoder->enable(encoder); | |
9ab0460b | 5027 | |
4b3a9526 VS |
5028 | assert_vblank_disabled(crtc); |
5029 | drm_crtc_vblank_on(crtc); | |
5030 | ||
9ab0460b | 5031 | intel_crtc_enable_planes(crtc); |
d40d9187 | 5032 | |
56b80e1f | 5033 | /* Underruns don't raise interrupts, so check manually. */ |
a72e4c9f | 5034 | i9xx_check_fifo_underruns(dev_priv); |
89b667f8 JB |
5035 | } |
5036 | ||
f13c2ef3 DV |
5037 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
5038 | { | |
5039 | struct drm_device *dev = crtc->base.dev; | |
5040 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5041 | ||
5042 | I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0); | |
5043 | I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1); | |
5044 | } | |
5045 | ||
0b8765c6 | 5046 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
5047 | { |
5048 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 5049 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 5050 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 5051 | struct intel_encoder *encoder; |
79e53945 | 5052 | int pipe = intel_crtc->pipe; |
79e53945 | 5053 | |
08a48469 DV |
5054 | WARN_ON(!crtc->enabled); |
5055 | ||
f7abfe8b CW |
5056 | if (intel_crtc->active) |
5057 | return; | |
5058 | ||
f13c2ef3 DV |
5059 | i9xx_set_pll_dividers(intel_crtc); |
5060 | ||
5b18e57c DV |
5061 | if (intel_crtc->config.has_dp_encoder) |
5062 | intel_dp_set_m_n(intel_crtc); | |
5063 | ||
5064 | intel_set_pipe_timings(intel_crtc); | |
5065 | ||
5b18e57c DV |
5066 | i9xx_set_pipeconf(intel_crtc); |
5067 | ||
f7abfe8b | 5068 | intel_crtc->active = true; |
6b383a7f | 5069 | |
4a3436e8 | 5070 | if (!IS_GEN2(dev)) |
a72e4c9f | 5071 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 5072 | |
9d6d9f19 MK |
5073 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5074 | if (encoder->pre_enable) | |
5075 | encoder->pre_enable(encoder); | |
5076 | ||
f6736a1a DV |
5077 | i9xx_enable_pll(intel_crtc); |
5078 | ||
2dd24552 JB |
5079 | i9xx_pfit_enable(intel_crtc); |
5080 | ||
63cbb074 VS |
5081 | intel_crtc_load_lut(crtc); |
5082 | ||
f37fcc2a | 5083 | intel_update_watermarks(crtc); |
e1fdc473 | 5084 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 5085 | |
fa5c73b1 DV |
5086 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5087 | encoder->enable(encoder); | |
9ab0460b | 5088 | |
4b3a9526 VS |
5089 | assert_vblank_disabled(crtc); |
5090 | drm_crtc_vblank_on(crtc); | |
5091 | ||
9ab0460b | 5092 | intel_crtc_enable_planes(crtc); |
d40d9187 | 5093 | |
4a3436e8 VS |
5094 | /* |
5095 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
5096 | * So don't enable underrun reporting before at least some planes | |
5097 | * are enabled. | |
5098 | * FIXME: Need to fix the logic to work when we turn off all planes | |
5099 | * but leave the pipe running. | |
5100 | */ | |
5101 | if (IS_GEN2(dev)) | |
a72e4c9f | 5102 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 5103 | |
56b80e1f | 5104 | /* Underruns don't raise interrupts, so check manually. */ |
a72e4c9f | 5105 | i9xx_check_fifo_underruns(dev_priv); |
0b8765c6 | 5106 | } |
79e53945 | 5107 | |
87476d63 DV |
5108 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
5109 | { | |
5110 | struct drm_device *dev = crtc->base.dev; | |
5111 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 5112 | |
328d8e82 DV |
5113 | if (!crtc->config.gmch_pfit.control) |
5114 | return; | |
87476d63 | 5115 | |
328d8e82 | 5116 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 5117 | |
328d8e82 DV |
5118 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
5119 | I915_READ(PFIT_CONTROL)); | |
5120 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
5121 | } |
5122 | ||
0b8765c6 JB |
5123 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
5124 | { | |
5125 | struct drm_device *dev = crtc->dev; | |
5126 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5127 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 5128 | struct intel_encoder *encoder; |
0b8765c6 | 5129 | int pipe = intel_crtc->pipe; |
ef9c3aee | 5130 | |
f7abfe8b CW |
5131 | if (!intel_crtc->active) |
5132 | return; | |
5133 | ||
4a3436e8 VS |
5134 | /* |
5135 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
5136 | * So diasble underrun reporting before all the planes get disabled. | |
5137 | * FIXME: Need to fix the logic to work when we turn off all planes | |
5138 | * but leave the pipe running. | |
5139 | */ | |
5140 | if (IS_GEN2(dev)) | |
a72e4c9f | 5141 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
4a3436e8 | 5142 | |
564ed191 ID |
5143 | /* |
5144 | * Vblank time updates from the shadow to live plane control register | |
5145 | * are blocked if the memory self-refresh mode is active at that | |
5146 | * moment. So to make sure the plane gets truly disabled, disable | |
5147 | * first the self-refresh mode. The self-refresh enable bit in turn | |
5148 | * will be checked/applied by the HW only at the next frame start | |
5149 | * event which is after the vblank start event, so we need to have a | |
5150 | * wait-for-vblank between disabling the plane and the pipe. | |
5151 | */ | |
5152 | intel_set_memory_cxsr(dev_priv, false); | |
9ab0460b VS |
5153 | intel_crtc_disable_planes(crtc); |
5154 | ||
6304cd91 VS |
5155 | /* |
5156 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
5157 | * wait for planes to fully turn off before disabling the pipe. | |
564ed191 ID |
5158 | * We also need to wait on all gmch platforms because of the |
5159 | * self-refresh mode constraint explained above. | |
6304cd91 | 5160 | */ |
564ed191 | 5161 | intel_wait_for_vblank(dev, pipe); |
6304cd91 | 5162 | |
4b3a9526 VS |
5163 | drm_crtc_vblank_off(crtc); |
5164 | assert_vblank_disabled(crtc); | |
5165 | ||
5166 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
5167 | encoder->disable(encoder); | |
5168 | ||
575f7ab7 | 5169 | intel_disable_pipe(intel_crtc); |
24a1f16d | 5170 | |
87476d63 | 5171 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 5172 | |
89b667f8 JB |
5173 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5174 | if (encoder->post_disable) | |
5175 | encoder->post_disable(encoder); | |
5176 | ||
409ee761 | 5177 | if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) { |
076ed3b2 CML |
5178 | if (IS_CHERRYVIEW(dev)) |
5179 | chv_disable_pll(dev_priv, pipe); | |
5180 | else if (IS_VALLEYVIEW(dev)) | |
5181 | vlv_disable_pll(dev_priv, pipe); | |
5182 | else | |
1c4e0274 | 5183 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 5184 | } |
0b8765c6 | 5185 | |
4a3436e8 | 5186 | if (!IS_GEN2(dev)) |
a72e4c9f | 5187 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
4a3436e8 | 5188 | |
f7abfe8b | 5189 | intel_crtc->active = false; |
46ba614c | 5190 | intel_update_watermarks(crtc); |
f37fcc2a | 5191 | |
efa9624e | 5192 | mutex_lock(&dev->struct_mutex); |
6b383a7f | 5193 | intel_update_fbc(dev); |
efa9624e | 5194 | mutex_unlock(&dev->struct_mutex); |
0b8765c6 JB |
5195 | } |
5196 | ||
ee7b9f93 JB |
5197 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
5198 | { | |
5199 | } | |
5200 | ||
b04c5bd6 BF |
5201 | /* Master function to enable/disable CRTC and corresponding power wells */ |
5202 | void intel_crtc_control(struct drm_crtc *crtc, bool enable) | |
976f8a20 DV |
5203 | { |
5204 | struct drm_device *dev = crtc->dev; | |
5205 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0e572fe7 | 5206 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
0e572fe7 DV |
5207 | enum intel_display_power_domain domain; |
5208 | unsigned long domains; | |
976f8a20 | 5209 | |
0e572fe7 DV |
5210 | if (enable) { |
5211 | if (!intel_crtc->active) { | |
e1e9fb84 DV |
5212 | domains = get_crtc_power_domains(crtc); |
5213 | for_each_power_domain(domain, domains) | |
5214 | intel_display_power_get(dev_priv, domain); | |
5215 | intel_crtc->enabled_power_domains = domains; | |
0e572fe7 DV |
5216 | |
5217 | dev_priv->display.crtc_enable(crtc); | |
5218 | } | |
5219 | } else { | |
5220 | if (intel_crtc->active) { | |
5221 | dev_priv->display.crtc_disable(crtc); | |
5222 | ||
e1e9fb84 DV |
5223 | domains = intel_crtc->enabled_power_domains; |
5224 | for_each_power_domain(domain, domains) | |
5225 | intel_display_power_put(dev_priv, domain); | |
5226 | intel_crtc->enabled_power_domains = 0; | |
0e572fe7 DV |
5227 | } |
5228 | } | |
b04c5bd6 BF |
5229 | } |
5230 | ||
5231 | /** | |
5232 | * Sets the power management mode of the pipe and plane. | |
5233 | */ | |
5234 | void intel_crtc_update_dpms(struct drm_crtc *crtc) | |
5235 | { | |
5236 | struct drm_device *dev = crtc->dev; | |
5237 | struct intel_encoder *intel_encoder; | |
5238 | bool enable = false; | |
5239 | ||
5240 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) | |
5241 | enable |= intel_encoder->connectors_active; | |
5242 | ||
5243 | intel_crtc_control(crtc, enable); | |
976f8a20 DV |
5244 | } |
5245 | ||
cdd59983 CW |
5246 | static void intel_crtc_disable(struct drm_crtc *crtc) |
5247 | { | |
cdd59983 | 5248 | struct drm_device *dev = crtc->dev; |
976f8a20 | 5249 | struct drm_connector *connector; |
ee7b9f93 | 5250 | struct drm_i915_private *dev_priv = dev->dev_private; |
2ff8fde1 | 5251 | struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb); |
a071fa00 | 5252 | enum pipe pipe = to_intel_crtc(crtc)->pipe; |
cdd59983 | 5253 | |
976f8a20 DV |
5254 | /* crtc should still be enabled when we disable it. */ |
5255 | WARN_ON(!crtc->enabled); | |
5256 | ||
5257 | dev_priv->display.crtc_disable(crtc); | |
ee7b9f93 JB |
5258 | dev_priv->display.off(crtc); |
5259 | ||
f4510a27 | 5260 | if (crtc->primary->fb) { |
cdd59983 | 5261 | mutex_lock(&dev->struct_mutex); |
a071fa00 DV |
5262 | intel_unpin_fb_obj(old_obj); |
5263 | i915_gem_track_fb(old_obj, NULL, | |
5264 | INTEL_FRONTBUFFER_PRIMARY(pipe)); | |
cdd59983 | 5265 | mutex_unlock(&dev->struct_mutex); |
f4510a27 | 5266 | crtc->primary->fb = NULL; |
976f8a20 DV |
5267 | } |
5268 | ||
5269 | /* Update computed state. */ | |
5270 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
5271 | if (!connector->encoder || !connector->encoder->crtc) | |
5272 | continue; | |
5273 | ||
5274 | if (connector->encoder->crtc != crtc) | |
5275 | continue; | |
5276 | ||
5277 | connector->dpms = DRM_MODE_DPMS_OFF; | |
5278 | to_intel_encoder(connector->encoder)->connectors_active = false; | |
cdd59983 CW |
5279 | } |
5280 | } | |
5281 | ||
ea5b213a | 5282 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 5283 | { |
4ef69c7a | 5284 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 5285 | |
ea5b213a CW |
5286 | drm_encoder_cleanup(encoder); |
5287 | kfree(intel_encoder); | |
7e7d76c3 JB |
5288 | } |
5289 | ||
9237329d | 5290 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
5ab432ef DV |
5291 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
5292 | * state of the entire output pipe. */ | |
9237329d | 5293 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
7e7d76c3 | 5294 | { |
5ab432ef DV |
5295 | if (mode == DRM_MODE_DPMS_ON) { |
5296 | encoder->connectors_active = true; | |
5297 | ||
b2cabb0e | 5298 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef DV |
5299 | } else { |
5300 | encoder->connectors_active = false; | |
5301 | ||
b2cabb0e | 5302 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef | 5303 | } |
79e53945 JB |
5304 | } |
5305 | ||
0a91ca29 DV |
5306 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
5307 | * internal consistency). */ | |
b980514c | 5308 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 5309 | { |
0a91ca29 DV |
5310 | if (connector->get_hw_state(connector)) { |
5311 | struct intel_encoder *encoder = connector->encoder; | |
5312 | struct drm_crtc *crtc; | |
5313 | bool encoder_enabled; | |
5314 | enum pipe pipe; | |
5315 | ||
5316 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
5317 | connector->base.base.id, | |
c23cc417 | 5318 | connector->base.name); |
0a91ca29 | 5319 | |
0e32b39c DA |
5320 | /* there is no real hw state for MST connectors */ |
5321 | if (connector->mst_port) | |
5322 | return; | |
5323 | ||
0a91ca29 DV |
5324 | WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, |
5325 | "wrong connector dpms state\n"); | |
5326 | WARN(connector->base.encoder != &encoder->base, | |
5327 | "active connector not linked to encoder\n"); | |
0a91ca29 | 5328 | |
36cd7444 DA |
5329 | if (encoder) { |
5330 | WARN(!encoder->connectors_active, | |
5331 | "encoder->connectors_active not set\n"); | |
5332 | ||
5333 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); | |
5334 | WARN(!encoder_enabled, "encoder not enabled\n"); | |
5335 | if (WARN_ON(!encoder->base.crtc)) | |
5336 | return; | |
0a91ca29 | 5337 | |
36cd7444 | 5338 | crtc = encoder->base.crtc; |
0a91ca29 | 5339 | |
36cd7444 DA |
5340 | WARN(!crtc->enabled, "crtc not enabled\n"); |
5341 | WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); | |
5342 | WARN(pipe != to_intel_crtc(crtc)->pipe, | |
5343 | "encoder active on the wrong pipe\n"); | |
5344 | } | |
0a91ca29 | 5345 | } |
79e53945 JB |
5346 | } |
5347 | ||
5ab432ef DV |
5348 | /* Even simpler default implementation, if there's really no special case to |
5349 | * consider. */ | |
5350 | void intel_connector_dpms(struct drm_connector *connector, int mode) | |
79e53945 | 5351 | { |
5ab432ef DV |
5352 | /* All the simple cases only support two dpms states. */ |
5353 | if (mode != DRM_MODE_DPMS_ON) | |
5354 | mode = DRM_MODE_DPMS_OFF; | |
d4270e57 | 5355 | |
5ab432ef DV |
5356 | if (mode == connector->dpms) |
5357 | return; | |
5358 | ||
5359 | connector->dpms = mode; | |
5360 | ||
5361 | /* Only need to change hw state when actually enabled */ | |
c9976dcf CW |
5362 | if (connector->encoder) |
5363 | intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); | |
0a91ca29 | 5364 | |
b980514c | 5365 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
5366 | } |
5367 | ||
f0947c37 DV |
5368 | /* Simple connector->get_hw_state implementation for encoders that support only |
5369 | * one connector and no cloning and hence the encoder state determines the state | |
5370 | * of the connector. */ | |
5371 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 5372 | { |
24929352 | 5373 | enum pipe pipe = 0; |
f0947c37 | 5374 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 5375 | |
f0947c37 | 5376 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
5377 | } |
5378 | ||
1857e1da DV |
5379 | static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5380 | struct intel_crtc_config *pipe_config) | |
5381 | { | |
5382 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5383 | struct intel_crtc *pipe_B_crtc = | |
5384 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
5385 | ||
5386 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", | |
5387 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5388 | if (pipe_config->fdi_lanes > 4) { | |
5389 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
5390 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5391 | return false; | |
5392 | } | |
5393 | ||
bafb6553 | 5394 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
5395 | if (pipe_config->fdi_lanes > 2) { |
5396 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
5397 | pipe_config->fdi_lanes); | |
5398 | return false; | |
5399 | } else { | |
5400 | return true; | |
5401 | } | |
5402 | } | |
5403 | ||
5404 | if (INTEL_INFO(dev)->num_pipes == 2) | |
5405 | return true; | |
5406 | ||
5407 | /* Ivybridge 3 pipe is really complicated */ | |
5408 | switch (pipe) { | |
5409 | case PIPE_A: | |
5410 | return true; | |
5411 | case PIPE_B: | |
5412 | if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled && | |
5413 | pipe_config->fdi_lanes > 2) { | |
5414 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
5415 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5416 | return false; | |
5417 | } | |
5418 | return true; | |
5419 | case PIPE_C: | |
1e833f40 | 5420 | if (!pipe_has_enabled_pch(pipe_B_crtc) || |
1857e1da DV |
5421 | pipe_B_crtc->config.fdi_lanes <= 2) { |
5422 | if (pipe_config->fdi_lanes > 2) { | |
5423 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
5424 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5425 | return false; | |
5426 | } | |
5427 | } else { | |
5428 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); | |
5429 | return false; | |
5430 | } | |
5431 | return true; | |
5432 | default: | |
5433 | BUG(); | |
5434 | } | |
5435 | } | |
5436 | ||
e29c22c0 DV |
5437 | #define RETRY 1 |
5438 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5439 | struct intel_crtc_config *pipe_config) | |
877d48d5 | 5440 | { |
1857e1da | 5441 | struct drm_device *dev = intel_crtc->base.dev; |
877d48d5 | 5442 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
ff9a6750 | 5443 | int lane, link_bw, fdi_dotclock; |
e29c22c0 | 5444 | bool setup_ok, needs_recompute = false; |
877d48d5 | 5445 | |
e29c22c0 | 5446 | retry: |
877d48d5 DV |
5447 | /* FDI is a binary signal running at ~2.7GHz, encoding |
5448 | * each output octet as 10 bits. The actual frequency | |
5449 | * is stored as a divider into a 100MHz clock, and the | |
5450 | * mode pixel clock is stored in units of 1KHz. | |
5451 | * Hence the bw of each lane in terms of the mode signal | |
5452 | * is: | |
5453 | */ | |
5454 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
5455 | ||
241bfc38 | 5456 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 5457 | |
2bd89a07 | 5458 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
5459 | pipe_config->pipe_bpp); |
5460 | ||
5461 | pipe_config->fdi_lanes = lane; | |
5462 | ||
2bd89a07 | 5463 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 5464 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 5465 | |
e29c22c0 DV |
5466 | setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
5467 | intel_crtc->pipe, pipe_config); | |
5468 | if (!setup_ok && pipe_config->pipe_bpp > 6*3) { | |
5469 | pipe_config->pipe_bpp -= 2*3; | |
5470 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
5471 | pipe_config->pipe_bpp); | |
5472 | needs_recompute = true; | |
5473 | pipe_config->bw_constrained = true; | |
5474 | ||
5475 | goto retry; | |
5476 | } | |
5477 | ||
5478 | if (needs_recompute) | |
5479 | return RETRY; | |
5480 | ||
5481 | return setup_ok ? 0 : -EINVAL; | |
877d48d5 DV |
5482 | } |
5483 | ||
42db64ef PZ |
5484 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5485 | struct intel_crtc_config *pipe_config) | |
5486 | { | |
d330a953 | 5487 | pipe_config->ips_enabled = i915.enable_ips && |
3c4ca58c | 5488 | hsw_crtc_supports_ips(crtc) && |
b6dfdc9b | 5489 | pipe_config->pipe_bpp <= 24; |
42db64ef PZ |
5490 | } |
5491 | ||
a43f6e0f | 5492 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
e29c22c0 | 5493 | struct intel_crtc_config *pipe_config) |
79e53945 | 5494 | { |
a43f6e0f | 5495 | struct drm_device *dev = crtc->base.dev; |
8bd31e67 | 5496 | struct drm_i915_private *dev_priv = dev->dev_private; |
b8cecdf5 | 5497 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
89749350 | 5498 | |
ad3a4479 | 5499 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 | 5500 | if (INTEL_INFO(dev)->gen < 4) { |
cf532bb2 VS |
5501 | int clock_limit = |
5502 | dev_priv->display.get_display_clock_speed(dev); | |
5503 | ||
5504 | /* | |
5505 | * Enable pixel doubling when the dot clock | |
5506 | * is > 90% of the (display) core speed. | |
5507 | * | |
b397c96b VS |
5508 | * GDG double wide on either pipe, |
5509 | * otherwise pipe A only. | |
cf532bb2 | 5510 | */ |
b397c96b | 5511 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
241bfc38 | 5512 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
ad3a4479 | 5513 | clock_limit *= 2; |
cf532bb2 | 5514 | pipe_config->double_wide = true; |
ad3a4479 VS |
5515 | } |
5516 | ||
241bfc38 | 5517 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
e29c22c0 | 5518 | return -EINVAL; |
2c07245f | 5519 | } |
89749350 | 5520 | |
1d1d0e27 VS |
5521 | /* |
5522 | * Pipe horizontal size must be even in: | |
5523 | * - DVO ganged mode | |
5524 | * - LVDS dual channel mode | |
5525 | * - Double wide pipe | |
5526 | */ | |
409ee761 | 5527 | if ((intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
5528 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
5529 | pipe_config->pipe_src_w &= ~1; | |
5530 | ||
8693a824 DL |
5531 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
5532 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
5533 | */ |
5534 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
5535 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | |
e29c22c0 | 5536 | return -EINVAL; |
44f46b42 | 5537 | |
bd080ee5 | 5538 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { |
5d2d38dd | 5539 | pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ |
bd080ee5 | 5540 | } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { |
5d2d38dd DV |
5541 | /* only a 8bpc pipe, with 6bpc dither through the panel fitter |
5542 | * for lvds. */ | |
5543 | pipe_config->pipe_bpp = 8*3; | |
5544 | } | |
5545 | ||
f5adf94e | 5546 | if (HAS_IPS(dev)) |
a43f6e0f DV |
5547 | hsw_compute_ips_config(crtc, pipe_config); |
5548 | ||
877d48d5 | 5549 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 5550 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 5551 | |
e29c22c0 | 5552 | return 0; |
79e53945 JB |
5553 | } |
5554 | ||
25eb05fc JB |
5555 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
5556 | { | |
d197b7d3 | 5557 | struct drm_i915_private *dev_priv = dev->dev_private; |
d197b7d3 VS |
5558 | u32 val; |
5559 | int divider; | |
5560 | ||
d49a340d VS |
5561 | /* FIXME: Punit isn't quite ready yet */ |
5562 | if (IS_CHERRYVIEW(dev)) | |
5563 | return 400000; | |
5564 | ||
6bcda4f0 VS |
5565 | if (dev_priv->hpll_freq == 0) |
5566 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
5567 | ||
d197b7d3 VS |
5568 | mutex_lock(&dev_priv->dpio_lock); |
5569 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
5570 | mutex_unlock(&dev_priv->dpio_lock); | |
5571 | ||
5572 | divider = val & DISPLAY_FREQUENCY_VALUES; | |
5573 | ||
7d007f40 VS |
5574 | WARN((val & DISPLAY_FREQUENCY_STATUS) != |
5575 | (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
5576 | "cdclk change in progress\n"); | |
5577 | ||
6bcda4f0 | 5578 | return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1); |
25eb05fc JB |
5579 | } |
5580 | ||
e70236a8 JB |
5581 | static int i945_get_display_clock_speed(struct drm_device *dev) |
5582 | { | |
5583 | return 400000; | |
5584 | } | |
79e53945 | 5585 | |
e70236a8 | 5586 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 5587 | { |
e70236a8 JB |
5588 | return 333000; |
5589 | } | |
79e53945 | 5590 | |
e70236a8 JB |
5591 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
5592 | { | |
5593 | return 200000; | |
5594 | } | |
79e53945 | 5595 | |
257a7ffc DV |
5596 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
5597 | { | |
5598 | u16 gcfgc = 0; | |
5599 | ||
5600 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
5601 | ||
5602 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
5603 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
5604 | return 267000; | |
5605 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: | |
5606 | return 333000; | |
5607 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: | |
5608 | return 444000; | |
5609 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: | |
5610 | return 200000; | |
5611 | default: | |
5612 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
5613 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
5614 | return 133000; | |
5615 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: | |
5616 | return 167000; | |
5617 | } | |
5618 | } | |
5619 | ||
e70236a8 JB |
5620 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
5621 | { | |
5622 | u16 gcfgc = 0; | |
79e53945 | 5623 | |
e70236a8 JB |
5624 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
5625 | ||
5626 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
5627 | return 133000; | |
5628 | else { | |
5629 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
5630 | case GC_DISPLAY_CLOCK_333_MHZ: | |
5631 | return 333000; | |
5632 | default: | |
5633 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
5634 | return 190000; | |
79e53945 | 5635 | } |
e70236a8 JB |
5636 | } |
5637 | } | |
5638 | ||
5639 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
5640 | { | |
5641 | return 266000; | |
5642 | } | |
5643 | ||
5644 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
5645 | { | |
5646 | u16 hpllcc = 0; | |
5647 | /* Assume that the hardware is in the high speed state. This | |
5648 | * should be the default. | |
5649 | */ | |
5650 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
5651 | case GC_CLOCK_133_200: | |
5652 | case GC_CLOCK_100_200: | |
5653 | return 200000; | |
5654 | case GC_CLOCK_166_250: | |
5655 | return 250000; | |
5656 | case GC_CLOCK_100_133: | |
79e53945 | 5657 | return 133000; |
e70236a8 | 5658 | } |
79e53945 | 5659 | |
e70236a8 JB |
5660 | /* Shouldn't happen */ |
5661 | return 0; | |
5662 | } | |
79e53945 | 5663 | |
e70236a8 JB |
5664 | static int i830_get_display_clock_speed(struct drm_device *dev) |
5665 | { | |
5666 | return 133000; | |
79e53945 JB |
5667 | } |
5668 | ||
2c07245f | 5669 | static void |
a65851af | 5670 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 5671 | { |
a65851af VS |
5672 | while (*num > DATA_LINK_M_N_MASK || |
5673 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
5674 | *num >>= 1; |
5675 | *den >>= 1; | |
5676 | } | |
5677 | } | |
5678 | ||
a65851af VS |
5679 | static void compute_m_n(unsigned int m, unsigned int n, |
5680 | uint32_t *ret_m, uint32_t *ret_n) | |
5681 | { | |
5682 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
5683 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
5684 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
5685 | } | |
5686 | ||
e69d0bc1 DV |
5687 | void |
5688 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
5689 | int pixel_clock, int link_clock, | |
5690 | struct intel_link_m_n *m_n) | |
2c07245f | 5691 | { |
e69d0bc1 | 5692 | m_n->tu = 64; |
a65851af VS |
5693 | |
5694 | compute_m_n(bits_per_pixel * pixel_clock, | |
5695 | link_clock * nlanes * 8, | |
5696 | &m_n->gmch_m, &m_n->gmch_n); | |
5697 | ||
5698 | compute_m_n(pixel_clock, link_clock, | |
5699 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
5700 | } |
5701 | ||
a7615030 CW |
5702 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
5703 | { | |
d330a953 JN |
5704 | if (i915.panel_use_ssc >= 0) |
5705 | return i915.panel_use_ssc != 0; | |
41aa3448 | 5706 | return dev_priv->vbt.lvds_use_ssc |
435793df | 5707 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
5708 | } |
5709 | ||
409ee761 | 5710 | static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors) |
c65d77d8 | 5711 | { |
409ee761 | 5712 | struct drm_device *dev = crtc->base.dev; |
c65d77d8 JB |
5713 | struct drm_i915_private *dev_priv = dev->dev_private; |
5714 | int refclk; | |
5715 | ||
a0c4da24 | 5716 | if (IS_VALLEYVIEW(dev)) { |
9a0ea498 | 5717 | refclk = 100000; |
d0737e1d | 5718 | } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 5719 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
5720 | refclk = dev_priv->vbt.lvds_ssc_freq; |
5721 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
5722 | } else if (!IS_GEN2(dev)) { |
5723 | refclk = 96000; | |
5724 | } else { | |
5725 | refclk = 48000; | |
5726 | } | |
5727 | ||
5728 | return refclk; | |
5729 | } | |
5730 | ||
7429e9d4 | 5731 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 5732 | { |
7df00d7a | 5733 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 5734 | } |
f47709a9 | 5735 | |
7429e9d4 DV |
5736 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
5737 | { | |
5738 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
5739 | } |
5740 | ||
f47709a9 | 5741 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
a7516a05 JB |
5742 | intel_clock_t *reduced_clock) |
5743 | { | |
f47709a9 | 5744 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
5745 | u32 fp, fp2 = 0; |
5746 | ||
5747 | if (IS_PINEVIEW(dev)) { | |
e1f234bd | 5748 | fp = pnv_dpll_compute_fp(&crtc->new_config->dpll); |
a7516a05 | 5749 | if (reduced_clock) |
7429e9d4 | 5750 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 5751 | } else { |
e1f234bd | 5752 | fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll); |
a7516a05 | 5753 | if (reduced_clock) |
7429e9d4 | 5754 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
5755 | } |
5756 | ||
e1f234bd | 5757 | crtc->new_config->dpll_hw_state.fp0 = fp; |
a7516a05 | 5758 | |
f47709a9 | 5759 | crtc->lowfreq_avail = false; |
e1f234bd | 5760 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) && |
d330a953 | 5761 | reduced_clock && i915.powersave) { |
e1f234bd | 5762 | crtc->new_config->dpll_hw_state.fp1 = fp2; |
f47709a9 | 5763 | crtc->lowfreq_avail = true; |
a7516a05 | 5764 | } else { |
e1f234bd | 5765 | crtc->new_config->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
5766 | } |
5767 | } | |
5768 | ||
5e69f97f CML |
5769 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
5770 | pipe) | |
89b667f8 JB |
5771 | { |
5772 | u32 reg_val; | |
5773 | ||
5774 | /* | |
5775 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
5776 | * and set it to a reasonable value instead. | |
5777 | */ | |
ab3c759a | 5778 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
5779 | reg_val &= 0xffffff00; |
5780 | reg_val |= 0x00000030; | |
ab3c759a | 5781 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 5782 | |
ab3c759a | 5783 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
5784 | reg_val &= 0x8cffffff; |
5785 | reg_val = 0x8c000000; | |
ab3c759a | 5786 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 5787 | |
ab3c759a | 5788 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 5789 | reg_val &= 0xffffff00; |
ab3c759a | 5790 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 5791 | |
ab3c759a | 5792 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
5793 | reg_val &= 0x00ffffff; |
5794 | reg_val |= 0xb0000000; | |
ab3c759a | 5795 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
5796 | } |
5797 | ||
b551842d DV |
5798 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
5799 | struct intel_link_m_n *m_n) | |
5800 | { | |
5801 | struct drm_device *dev = crtc->base.dev; | |
5802 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5803 | int pipe = crtc->pipe; | |
5804 | ||
e3b95f1e DV |
5805 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
5806 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
5807 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
5808 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
5809 | } |
5810 | ||
5811 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
5812 | struct intel_link_m_n *m_n, |
5813 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
5814 | { |
5815 | struct drm_device *dev = crtc->base.dev; | |
5816 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5817 | int pipe = crtc->pipe; | |
5818 | enum transcoder transcoder = crtc->config.cpu_transcoder; | |
5819 | ||
5820 | if (INTEL_INFO(dev)->gen >= 5) { | |
5821 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
5822 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
5823 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
5824 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
5825 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
5826 | * for gen < 8) and if DRRS is supported (to make sure the | |
5827 | * registers are not unnecessarily accessed). | |
5828 | */ | |
5829 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
5830 | crtc->config.has_drrs) { | |
5831 | I915_WRITE(PIPE_DATA_M2(transcoder), | |
5832 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
5833 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
5834 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
5835 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
5836 | } | |
b551842d | 5837 | } else { |
e3b95f1e DV |
5838 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
5839 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
5840 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
5841 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
5842 | } |
5843 | } | |
5844 | ||
f769cd24 | 5845 | void intel_dp_set_m_n(struct intel_crtc *crtc) |
03afc4a2 DV |
5846 | { |
5847 | if (crtc->config.has_pch_encoder) | |
5848 | intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); | |
5849 | else | |
f769cd24 VK |
5850 | intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n, |
5851 | &crtc->config.dp_m2_n2); | |
03afc4a2 DV |
5852 | } |
5853 | ||
d288f65f VS |
5854 | static void vlv_update_pll(struct intel_crtc *crtc, |
5855 | struct intel_crtc_config *pipe_config) | |
bdd4b6a6 DV |
5856 | { |
5857 | u32 dpll, dpll_md; | |
5858 | ||
5859 | /* | |
5860 | * Enable DPIO clock input. We should never disable the reference | |
5861 | * clock for pipe B, since VGA hotplug / manual detection depends | |
5862 | * on it. | |
5863 | */ | |
5864 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | | |
5865 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; | |
5866 | /* We should never disable this, set it here for state tracking */ | |
5867 | if (crtc->pipe == PIPE_B) | |
5868 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
5869 | dpll |= DPLL_VCO_ENABLE; | |
d288f65f | 5870 | pipe_config->dpll_hw_state.dpll = dpll; |
bdd4b6a6 | 5871 | |
d288f65f | 5872 | dpll_md = (pipe_config->pixel_multiplier - 1) |
bdd4b6a6 | 5873 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
d288f65f | 5874 | pipe_config->dpll_hw_state.dpll_md = dpll_md; |
bdd4b6a6 DV |
5875 | } |
5876 | ||
d288f65f VS |
5877 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5878 | const struct intel_crtc_config *pipe_config) | |
a0c4da24 | 5879 | { |
f47709a9 | 5880 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 5881 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 5882 | int pipe = crtc->pipe; |
bdd4b6a6 | 5883 | u32 mdiv; |
a0c4da24 | 5884 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 5885 | u32 coreclk, reg_val; |
a0c4da24 | 5886 | |
09153000 DV |
5887 | mutex_lock(&dev_priv->dpio_lock); |
5888 | ||
d288f65f VS |
5889 | bestn = pipe_config->dpll.n; |
5890 | bestm1 = pipe_config->dpll.m1; | |
5891 | bestm2 = pipe_config->dpll.m2; | |
5892 | bestp1 = pipe_config->dpll.p1; | |
5893 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 5894 | |
89b667f8 JB |
5895 | /* See eDP HDMI DPIO driver vbios notes doc */ |
5896 | ||
5897 | /* PLL B needs special handling */ | |
bdd4b6a6 | 5898 | if (pipe == PIPE_B) |
5e69f97f | 5899 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
5900 | |
5901 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 5902 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
5903 | |
5904 | /* Disable target IRef on PLL */ | |
ab3c759a | 5905 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 5906 | reg_val &= 0x00ffffff; |
ab3c759a | 5907 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
5908 | |
5909 | /* Disable fast lock */ | |
ab3c759a | 5910 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
5911 | |
5912 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
5913 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
5914 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
5915 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 5916 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
5917 | |
5918 | /* | |
5919 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
5920 | * but we don't support that). | |
5921 | * Note: don't use the DAC post divider as it seems unstable. | |
5922 | */ | |
5923 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 5924 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 5925 | |
a0c4da24 | 5926 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 5927 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 5928 | |
89b667f8 | 5929 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 5930 | if (pipe_config->port_clock == 162000 || |
409ee761 ACO |
5931 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || |
5932 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 5933 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 5934 | 0x009f0003); |
89b667f8 | 5935 | else |
ab3c759a | 5936 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
5937 | 0x00d0000f); |
5938 | ||
0a88818d | 5939 | if (crtc->config.has_dp_encoder) { |
89b667f8 | 5940 | /* Use SSC source */ |
bdd4b6a6 | 5941 | if (pipe == PIPE_A) |
ab3c759a | 5942 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5943 | 0x0df40000); |
5944 | else | |
ab3c759a | 5945 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5946 | 0x0df70000); |
5947 | } else { /* HDMI or VGA */ | |
5948 | /* Use bend source */ | |
bdd4b6a6 | 5949 | if (pipe == PIPE_A) |
ab3c759a | 5950 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5951 | 0x0df70000); |
5952 | else | |
ab3c759a | 5953 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5954 | 0x0df40000); |
5955 | } | |
a0c4da24 | 5956 | |
ab3c759a | 5957 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 5958 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
409ee761 ACO |
5959 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
5960 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) | |
89b667f8 | 5961 | coreclk |= 0x01000000; |
ab3c759a | 5962 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 5963 | |
ab3c759a | 5964 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
09153000 | 5965 | mutex_unlock(&dev_priv->dpio_lock); |
a0c4da24 JB |
5966 | } |
5967 | ||
d288f65f VS |
5968 | static void chv_update_pll(struct intel_crtc *crtc, |
5969 | struct intel_crtc_config *pipe_config) | |
1ae0d137 | 5970 | { |
d288f65f | 5971 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV | |
1ae0d137 VS |
5972 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | |
5973 | DPLL_VCO_ENABLE; | |
5974 | if (crtc->pipe != PIPE_A) | |
d288f65f | 5975 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
1ae0d137 | 5976 | |
d288f65f VS |
5977 | pipe_config->dpll_hw_state.dpll_md = |
5978 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
1ae0d137 VS |
5979 | } |
5980 | ||
d288f65f VS |
5981 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5982 | const struct intel_crtc_config *pipe_config) | |
9d556c99 CML |
5983 | { |
5984 | struct drm_device *dev = crtc->base.dev; | |
5985 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5986 | int pipe = crtc->pipe; | |
5987 | int dpll_reg = DPLL(crtc->pipe); | |
5988 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
580d3811 | 5989 | u32 loopfilter, intcoeff; |
9d556c99 CML |
5990 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
5991 | int refclk; | |
5992 | ||
d288f65f VS |
5993 | bestn = pipe_config->dpll.n; |
5994 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
5995 | bestm1 = pipe_config->dpll.m1; | |
5996 | bestm2 = pipe_config->dpll.m2 >> 22; | |
5997 | bestp1 = pipe_config->dpll.p1; | |
5998 | bestp2 = pipe_config->dpll.p2; | |
9d556c99 CML |
5999 | |
6000 | /* | |
6001 | * Enable Refclk and SSC | |
6002 | */ | |
a11b0703 | 6003 | I915_WRITE(dpll_reg, |
d288f65f | 6004 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); |
a11b0703 VS |
6005 | |
6006 | mutex_lock(&dev_priv->dpio_lock); | |
9d556c99 | 6007 | |
9d556c99 CML |
6008 | /* p1 and p2 divider */ |
6009 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
6010 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
6011 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
6012 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
6013 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
6014 | ||
6015 | /* Feedback post-divider - m2 */ | |
6016 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
6017 | ||
6018 | /* Feedback refclk divider - n and m1 */ | |
6019 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
6020 | DPIO_CHV_M1_DIV_BY_2 | | |
6021 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
6022 | ||
6023 | /* M2 fraction division */ | |
6024 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); | |
6025 | ||
6026 | /* M2 fraction division enable */ | |
6027 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), | |
6028 | DPIO_CHV_FRAC_DIV_EN | | |
6029 | (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT)); | |
6030 | ||
6031 | /* Loop filter */ | |
409ee761 | 6032 | refclk = i9xx_get_refclk(crtc, 0); |
9d556c99 CML |
6033 | loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT | |
6034 | 2 << DPIO_CHV_GAIN_CTRL_SHIFT; | |
6035 | if (refclk == 100000) | |
6036 | intcoeff = 11; | |
6037 | else if (refclk == 38400) | |
6038 | intcoeff = 10; | |
6039 | else | |
6040 | intcoeff = 9; | |
6041 | loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT; | |
6042 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); | |
6043 | ||
6044 | /* AFC Recal */ | |
6045 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
6046 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
6047 | DPIO_AFC_RECAL); | |
6048 | ||
6049 | mutex_unlock(&dev_priv->dpio_lock); | |
6050 | } | |
6051 | ||
d288f65f VS |
6052 | /** |
6053 | * vlv_force_pll_on - forcibly enable just the PLL | |
6054 | * @dev_priv: i915 private structure | |
6055 | * @pipe: pipe PLL to enable | |
6056 | * @dpll: PLL configuration | |
6057 | * | |
6058 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
6059 | * in cases where we need the PLL enabled even when @pipe is not going to | |
6060 | * be enabled. | |
6061 | */ | |
6062 | void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, | |
6063 | const struct dpll *dpll) | |
6064 | { | |
6065 | struct intel_crtc *crtc = | |
6066 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
6067 | struct intel_crtc_config pipe_config = { | |
6068 | .pixel_multiplier = 1, | |
6069 | .dpll = *dpll, | |
6070 | }; | |
6071 | ||
6072 | if (IS_CHERRYVIEW(dev)) { | |
6073 | chv_update_pll(crtc, &pipe_config); | |
6074 | chv_prepare_pll(crtc, &pipe_config); | |
6075 | chv_enable_pll(crtc, &pipe_config); | |
6076 | } else { | |
6077 | vlv_update_pll(crtc, &pipe_config); | |
6078 | vlv_prepare_pll(crtc, &pipe_config); | |
6079 | vlv_enable_pll(crtc, &pipe_config); | |
6080 | } | |
6081 | } | |
6082 | ||
6083 | /** | |
6084 | * vlv_force_pll_off - forcibly disable just the PLL | |
6085 | * @dev_priv: i915 private structure | |
6086 | * @pipe: pipe PLL to disable | |
6087 | * | |
6088 | * Disable the PLL for @pipe. To be used in cases where we need | |
6089 | * the PLL enabled even when @pipe is not going to be enabled. | |
6090 | */ | |
6091 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
6092 | { | |
6093 | if (IS_CHERRYVIEW(dev)) | |
6094 | chv_disable_pll(to_i915(dev), pipe); | |
6095 | else | |
6096 | vlv_disable_pll(to_i915(dev), pipe); | |
6097 | } | |
6098 | ||
f47709a9 DV |
6099 | static void i9xx_update_pll(struct intel_crtc *crtc, |
6100 | intel_clock_t *reduced_clock, | |
eb1cbe48 DV |
6101 | int num_connectors) |
6102 | { | |
f47709a9 | 6103 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 6104 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
6105 | u32 dpll; |
6106 | bool is_sdvo; | |
d0737e1d | 6107 | struct dpll *clock = &crtc->new_config->dpll; |
eb1cbe48 | 6108 | |
f47709a9 | 6109 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 6110 | |
d0737e1d ACO |
6111 | is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) || |
6112 | intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
6113 | |
6114 | dpll = DPLL_VGA_MODE_DIS; | |
6115 | ||
d0737e1d | 6116 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
6117 | dpll |= DPLLB_MODE_LVDS; |
6118 | else | |
6119 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 6120 | |
ef1b460d | 6121 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
d0737e1d | 6122 | dpll |= (crtc->new_config->pixel_multiplier - 1) |
198a037f | 6123 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 6124 | } |
198a037f DV |
6125 | |
6126 | if (is_sdvo) | |
4a33e48d | 6127 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 6128 | |
0a88818d | 6129 | if (crtc->new_config->has_dp_encoder) |
4a33e48d | 6130 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
6131 | |
6132 | /* compute bitmask from p1 value */ | |
6133 | if (IS_PINEVIEW(dev)) | |
6134 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
6135 | else { | |
6136 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
6137 | if (IS_G4X(dev) && reduced_clock) | |
6138 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
6139 | } | |
6140 | switch (clock->p2) { | |
6141 | case 5: | |
6142 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
6143 | break; | |
6144 | case 7: | |
6145 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
6146 | break; | |
6147 | case 10: | |
6148 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
6149 | break; | |
6150 | case 14: | |
6151 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
6152 | break; | |
6153 | } | |
6154 | if (INTEL_INFO(dev)->gen >= 4) | |
6155 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
6156 | ||
d0737e1d | 6157 | if (crtc->new_config->sdvo_tv_clock) |
eb1cbe48 | 6158 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
d0737e1d | 6159 | else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
6160 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
6161 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
6162 | else | |
6163 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6164 | ||
6165 | dpll |= DPLL_VCO_ENABLE; | |
d0737e1d | 6166 | crtc->new_config->dpll_hw_state.dpll = dpll; |
8bcc2795 | 6167 | |
eb1cbe48 | 6168 | if (INTEL_INFO(dev)->gen >= 4) { |
d0737e1d | 6169 | u32 dpll_md = (crtc->new_config->pixel_multiplier - 1) |
ef1b460d | 6170 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
d0737e1d | 6171 | crtc->new_config->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
6172 | } |
6173 | } | |
6174 | ||
f47709a9 | 6175 | static void i8xx_update_pll(struct intel_crtc *crtc, |
f47709a9 | 6176 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
6177 | int num_connectors) |
6178 | { | |
f47709a9 | 6179 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 6180 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 6181 | u32 dpll; |
d0737e1d | 6182 | struct dpll *clock = &crtc->new_config->dpll; |
eb1cbe48 | 6183 | |
f47709a9 | 6184 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 6185 | |
eb1cbe48 DV |
6186 | dpll = DPLL_VGA_MODE_DIS; |
6187 | ||
d0737e1d | 6188 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
6189 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
6190 | } else { | |
6191 | if (clock->p1 == 2) | |
6192 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
6193 | else | |
6194 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
6195 | if (clock->p2 == 4) | |
6196 | dpll |= PLL_P2_DIVIDE_BY_4; | |
6197 | } | |
6198 | ||
d0737e1d | 6199 | if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
6200 | dpll |= DPLL_DVO_2X_MODE; |
6201 | ||
d0737e1d | 6202 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
6203 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
6204 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
6205 | else | |
6206 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6207 | ||
6208 | dpll |= DPLL_VCO_ENABLE; | |
d0737e1d | 6209 | crtc->new_config->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
6210 | } |
6211 | ||
8a654f3b | 6212 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
6213 | { |
6214 | struct drm_device *dev = intel_crtc->base.dev; | |
6215 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6216 | enum pipe pipe = intel_crtc->pipe; | |
3b117c8f | 6217 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
8a654f3b DV |
6218 | struct drm_display_mode *adjusted_mode = |
6219 | &intel_crtc->config.adjusted_mode; | |
1caea6e9 VS |
6220 | uint32_t crtc_vtotal, crtc_vblank_end; |
6221 | int vsyncshift = 0; | |
4d8a62ea DV |
6222 | |
6223 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
6224 | * the hw state checker will get angry at the mismatch. */ | |
6225 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
6226 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 6227 | |
609aeaca | 6228 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 6229 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
6230 | crtc_vtotal -= 1; |
6231 | crtc_vblank_end -= 1; | |
609aeaca | 6232 | |
409ee761 | 6233 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
6234 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
6235 | else | |
6236 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
6237 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
6238 | if (vsyncshift < 0) |
6239 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
6240 | } |
6241 | ||
6242 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 6243 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 6244 | |
fe2b8f9d | 6245 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
6246 | (adjusted_mode->crtc_hdisplay - 1) | |
6247 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 6248 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
6249 | (adjusted_mode->crtc_hblank_start - 1) | |
6250 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 6251 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
6252 | (adjusted_mode->crtc_hsync_start - 1) | |
6253 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
6254 | ||
fe2b8f9d | 6255 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 6256 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 6257 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 6258 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 6259 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 6260 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 6261 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
6262 | (adjusted_mode->crtc_vsync_start - 1) | |
6263 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
6264 | ||
b5e508d4 PZ |
6265 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
6266 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
6267 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
6268 | * bits. */ | |
6269 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
6270 | (pipe == PIPE_B || pipe == PIPE_C)) | |
6271 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
6272 | ||
b0e77b9c PZ |
6273 | /* pipesrc controls the size that is scaled from, which should |
6274 | * always be the user's requested size. | |
6275 | */ | |
6276 | I915_WRITE(PIPESRC(pipe), | |
37327abd VS |
6277 | ((intel_crtc->config.pipe_src_w - 1) << 16) | |
6278 | (intel_crtc->config.pipe_src_h - 1)); | |
b0e77b9c PZ |
6279 | } |
6280 | ||
1bd1bd80 DV |
6281 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
6282 | struct intel_crtc_config *pipe_config) | |
6283 | { | |
6284 | struct drm_device *dev = crtc->base.dev; | |
6285 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6286 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
6287 | uint32_t tmp; | |
6288 | ||
6289 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
6290 | pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; | |
6291 | pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
6292 | tmp = I915_READ(HBLANK(cpu_transcoder)); | |
6293 | pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; | |
6294 | pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
6295 | tmp = I915_READ(HSYNC(cpu_transcoder)); | |
6296 | pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; | |
6297 | pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
6298 | ||
6299 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
6300 | pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; | |
6301 | pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
6302 | tmp = I915_READ(VBLANK(cpu_transcoder)); | |
6303 | pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; | |
6304 | pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
6305 | tmp = I915_READ(VSYNC(cpu_transcoder)); | |
6306 | pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; | |
6307 | pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
6308 | ||
6309 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
6310 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; | |
6311 | pipe_config->adjusted_mode.crtc_vtotal += 1; | |
6312 | pipe_config->adjusted_mode.crtc_vblank_end += 1; | |
6313 | } | |
6314 | ||
6315 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
6316 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
6317 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
6318 | ||
6319 | pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h; | |
6320 | pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
6321 | } |
6322 | ||
f6a83288 DV |
6323 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
6324 | struct intel_crtc_config *pipe_config) | |
babea61d | 6325 | { |
f6a83288 DV |
6326 | mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay; |
6327 | mode->htotal = pipe_config->adjusted_mode.crtc_htotal; | |
6328 | mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start; | |
6329 | mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end; | |
babea61d | 6330 | |
f6a83288 DV |
6331 | mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay; |
6332 | mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal; | |
6333 | mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start; | |
6334 | mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end; | |
babea61d | 6335 | |
f6a83288 | 6336 | mode->flags = pipe_config->adjusted_mode.flags; |
babea61d | 6337 | |
f6a83288 DV |
6338 | mode->clock = pipe_config->adjusted_mode.crtc_clock; |
6339 | mode->flags |= pipe_config->adjusted_mode.flags; | |
babea61d JB |
6340 | } |
6341 | ||
84b046f3 DV |
6342 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
6343 | { | |
6344 | struct drm_device *dev = intel_crtc->base.dev; | |
6345 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6346 | uint32_t pipeconf; | |
6347 | ||
9f11a9e4 | 6348 | pipeconf = 0; |
84b046f3 | 6349 | |
b6b5d049 VS |
6350 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
6351 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
6352 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 6353 | |
cf532bb2 VS |
6354 | if (intel_crtc->config.double_wide) |
6355 | pipeconf |= PIPECONF_DOUBLE_WIDE; | |
84b046f3 | 6356 | |
ff9ce46e DV |
6357 | /* only g4x and later have fancy bpc/dither controls */ |
6358 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { | |
ff9ce46e DV |
6359 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6360 | if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30) | |
6361 | pipeconf |= PIPECONF_DITHER_EN | | |
84b046f3 | 6362 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 6363 | |
ff9ce46e DV |
6364 | switch (intel_crtc->config.pipe_bpp) { |
6365 | case 18: | |
6366 | pipeconf |= PIPECONF_6BPC; | |
6367 | break; | |
6368 | case 24: | |
6369 | pipeconf |= PIPECONF_8BPC; | |
6370 | break; | |
6371 | case 30: | |
6372 | pipeconf |= PIPECONF_10BPC; | |
6373 | break; | |
6374 | default: | |
6375 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
6376 | BUG(); | |
84b046f3 DV |
6377 | } |
6378 | } | |
6379 | ||
6380 | if (HAS_PIPE_CXSR(dev)) { | |
6381 | if (intel_crtc->lowfreq_avail) { | |
6382 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
6383 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
6384 | } else { | |
6385 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
6386 | } |
6387 | } | |
6388 | ||
efc2cfff VS |
6389 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
6390 | if (INTEL_INFO(dev)->gen < 4 || | |
409ee761 | 6391 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
6392 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
6393 | else | |
6394 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
6395 | } else | |
84b046f3 DV |
6396 | pipeconf |= PIPECONF_PROGRESSIVE; |
6397 | ||
9f11a9e4 DV |
6398 | if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range) |
6399 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; | |
9c8e09b7 | 6400 | |
84b046f3 DV |
6401 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
6402 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
6403 | } | |
6404 | ||
d6dfee7a | 6405 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc) |
79e53945 | 6406 | { |
c7653199 | 6407 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 6408 | struct drm_i915_private *dev_priv = dev->dev_private; |
c751ce4f | 6409 | int refclk, num_connectors = 0; |
652c393a | 6410 | intel_clock_t clock, reduced_clock; |
a16af721 | 6411 | bool ok, has_reduced_clock = false; |
e9fd1c02 | 6412 | bool is_lvds = false, is_dsi = false; |
5eddb70b | 6413 | struct intel_encoder *encoder; |
d4906093 | 6414 | const intel_limit_t *limit; |
79e53945 | 6415 | |
d0737e1d ACO |
6416 | for_each_intel_encoder(dev, encoder) { |
6417 | if (encoder->new_crtc != crtc) | |
6418 | continue; | |
6419 | ||
5eddb70b | 6420 | switch (encoder->type) { |
79e53945 JB |
6421 | case INTEL_OUTPUT_LVDS: |
6422 | is_lvds = true; | |
6423 | break; | |
e9fd1c02 JN |
6424 | case INTEL_OUTPUT_DSI: |
6425 | is_dsi = true; | |
6426 | break; | |
6847d71b PZ |
6427 | default: |
6428 | break; | |
79e53945 | 6429 | } |
43565a06 | 6430 | |
c751ce4f | 6431 | num_connectors++; |
79e53945 JB |
6432 | } |
6433 | ||
f2335330 | 6434 | if (is_dsi) |
5b18e57c | 6435 | return 0; |
f2335330 | 6436 | |
d0737e1d | 6437 | if (!crtc->new_config->clock_set) { |
409ee761 | 6438 | refclk = i9xx_get_refclk(crtc, num_connectors); |
79e53945 | 6439 | |
e9fd1c02 JN |
6440 | /* |
6441 | * Returns a set of divisors for the desired target clock with | |
6442 | * the given refclk, or FALSE. The returned values represent | |
6443 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
6444 | * 2) / p1 / p2. | |
6445 | */ | |
409ee761 | 6446 | limit = intel_limit(crtc, refclk); |
c7653199 | 6447 | ok = dev_priv->display.find_dpll(limit, crtc, |
d0737e1d | 6448 | crtc->new_config->port_clock, |
e9fd1c02 | 6449 | refclk, NULL, &clock); |
f2335330 | 6450 | if (!ok) { |
e9fd1c02 JN |
6451 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
6452 | return -EINVAL; | |
6453 | } | |
79e53945 | 6454 | |
f2335330 JN |
6455 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
6456 | /* | |
6457 | * Ensure we match the reduced clock's P to the target | |
6458 | * clock. If the clocks don't match, we can't switch | |
6459 | * the display clock by using the FP0/FP1. In such case | |
6460 | * we will disable the LVDS downclock feature. | |
6461 | */ | |
6462 | has_reduced_clock = | |
c7653199 | 6463 | dev_priv->display.find_dpll(limit, crtc, |
f2335330 JN |
6464 | dev_priv->lvds_downclock, |
6465 | refclk, &clock, | |
6466 | &reduced_clock); | |
6467 | } | |
6468 | /* Compat-code for transition, will disappear. */ | |
d0737e1d ACO |
6469 | crtc->new_config->dpll.n = clock.n; |
6470 | crtc->new_config->dpll.m1 = clock.m1; | |
6471 | crtc->new_config->dpll.m2 = clock.m2; | |
6472 | crtc->new_config->dpll.p1 = clock.p1; | |
6473 | crtc->new_config->dpll.p2 = clock.p2; | |
f47709a9 | 6474 | } |
7026d4ac | 6475 | |
e9fd1c02 | 6476 | if (IS_GEN2(dev)) { |
c7653199 | 6477 | i8xx_update_pll(crtc, |
2a8f64ca VP |
6478 | has_reduced_clock ? &reduced_clock : NULL, |
6479 | num_connectors); | |
9d556c99 | 6480 | } else if (IS_CHERRYVIEW(dev)) { |
d0737e1d | 6481 | chv_update_pll(crtc, crtc->new_config); |
e9fd1c02 | 6482 | } else if (IS_VALLEYVIEW(dev)) { |
d0737e1d | 6483 | vlv_update_pll(crtc, crtc->new_config); |
e9fd1c02 | 6484 | } else { |
c7653199 | 6485 | i9xx_update_pll(crtc, |
eb1cbe48 | 6486 | has_reduced_clock ? &reduced_clock : NULL, |
eba905b2 | 6487 | num_connectors); |
e9fd1c02 | 6488 | } |
79e53945 | 6489 | |
c8f7a0db | 6490 | return 0; |
f564048e EA |
6491 | } |
6492 | ||
2fa2fe9a DV |
6493 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
6494 | struct intel_crtc_config *pipe_config) | |
6495 | { | |
6496 | struct drm_device *dev = crtc->base.dev; | |
6497 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6498 | uint32_t tmp; | |
6499 | ||
dc9e7dec VS |
6500 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
6501 | return; | |
6502 | ||
2fa2fe9a | 6503 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
6504 | if (!(tmp & PFIT_ENABLE)) |
6505 | return; | |
2fa2fe9a | 6506 | |
06922821 | 6507 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
6508 | if (INTEL_INFO(dev)->gen < 4) { |
6509 | if (crtc->pipe != PIPE_B) | |
6510 | return; | |
2fa2fe9a DV |
6511 | } else { |
6512 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
6513 | return; | |
6514 | } | |
6515 | ||
06922821 | 6516 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
6517 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
6518 | if (INTEL_INFO(dev)->gen < 5) | |
6519 | pipe_config->gmch_pfit.lvds_border_bits = | |
6520 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
6521 | } | |
6522 | ||
acbec814 JB |
6523 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
6524 | struct intel_crtc_config *pipe_config) | |
6525 | { | |
6526 | struct drm_device *dev = crtc->base.dev; | |
6527 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6528 | int pipe = pipe_config->cpu_transcoder; | |
6529 | intel_clock_t clock; | |
6530 | u32 mdiv; | |
662c6ecb | 6531 | int refclk = 100000; |
acbec814 | 6532 | |
f573de5a SK |
6533 | /* In case of MIPI DPLL will not even be used */ |
6534 | if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) | |
6535 | return; | |
6536 | ||
acbec814 | 6537 | mutex_lock(&dev_priv->dpio_lock); |
ab3c759a | 6538 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
acbec814 JB |
6539 | mutex_unlock(&dev_priv->dpio_lock); |
6540 | ||
6541 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
6542 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
6543 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
6544 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
6545 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
6546 | ||
f646628b | 6547 | vlv_clock(refclk, &clock); |
acbec814 | 6548 | |
f646628b VS |
6549 | /* clock.dot is the fast clock */ |
6550 | pipe_config->port_clock = clock.dot / 5; | |
acbec814 JB |
6551 | } |
6552 | ||
1ad292b5 JB |
6553 | static void i9xx_get_plane_config(struct intel_crtc *crtc, |
6554 | struct intel_plane_config *plane_config) | |
6555 | { | |
6556 | struct drm_device *dev = crtc->base.dev; | |
6557 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6558 | u32 val, base, offset; | |
6559 | int pipe = crtc->pipe, plane = crtc->plane; | |
6560 | int fourcc, pixel_format; | |
6561 | int aligned_height; | |
6562 | ||
66e514c1 DA |
6563 | crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL); |
6564 | if (!crtc->base.primary->fb) { | |
1ad292b5 JB |
6565 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
6566 | return; | |
6567 | } | |
6568 | ||
6569 | val = I915_READ(DSPCNTR(plane)); | |
6570 | ||
6571 | if (INTEL_INFO(dev)->gen >= 4) | |
6572 | if (val & DISPPLANE_TILED) | |
6573 | plane_config->tiled = true; | |
6574 | ||
6575 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
6576 | fourcc = intel_format_to_fourcc(pixel_format); | |
66e514c1 DA |
6577 | crtc->base.primary->fb->pixel_format = fourcc; |
6578 | crtc->base.primary->fb->bits_per_pixel = | |
1ad292b5 JB |
6579 | drm_format_plane_cpp(fourcc, 0) * 8; |
6580 | ||
6581 | if (INTEL_INFO(dev)->gen >= 4) { | |
6582 | if (plane_config->tiled) | |
6583 | offset = I915_READ(DSPTILEOFF(plane)); | |
6584 | else | |
6585 | offset = I915_READ(DSPLINOFF(plane)); | |
6586 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
6587 | } else { | |
6588 | base = I915_READ(DSPADDR(plane)); | |
6589 | } | |
6590 | plane_config->base = base; | |
6591 | ||
6592 | val = I915_READ(PIPESRC(pipe)); | |
66e514c1 DA |
6593 | crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1; |
6594 | crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
6595 | |
6596 | val = I915_READ(DSPSTRIDE(pipe)); | |
026b96e2 | 6597 | crtc->base.primary->fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 6598 | |
66e514c1 | 6599 | aligned_height = intel_align_height(dev, crtc->base.primary->fb->height, |
1ad292b5 JB |
6600 | plane_config->tiled); |
6601 | ||
1267a26b FF |
6602 | plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] * |
6603 | aligned_height); | |
1ad292b5 JB |
6604 | |
6605 | DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
66e514c1 DA |
6606 | pipe, plane, crtc->base.primary->fb->width, |
6607 | crtc->base.primary->fb->height, | |
6608 | crtc->base.primary->fb->bits_per_pixel, base, | |
6609 | crtc->base.primary->fb->pitches[0], | |
1ad292b5 JB |
6610 | plane_config->size); |
6611 | ||
6612 | } | |
6613 | ||
70b23a98 VS |
6614 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
6615 | struct intel_crtc_config *pipe_config) | |
6616 | { | |
6617 | struct drm_device *dev = crtc->base.dev; | |
6618 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6619 | int pipe = pipe_config->cpu_transcoder; | |
6620 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
6621 | intel_clock_t clock; | |
6622 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2; | |
6623 | int refclk = 100000; | |
6624 | ||
6625 | mutex_lock(&dev_priv->dpio_lock); | |
6626 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); | |
6627 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
6628 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
6629 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
6630 | mutex_unlock(&dev_priv->dpio_lock); | |
6631 | ||
6632 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
6633 | clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff); | |
6634 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; | |
6635 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
6636 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
6637 | ||
6638 | chv_clock(refclk, &clock); | |
6639 | ||
6640 | /* clock.dot is the fast clock */ | |
6641 | pipe_config->port_clock = clock.dot / 5; | |
6642 | } | |
6643 | ||
0e8ffe1b DV |
6644 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
6645 | struct intel_crtc_config *pipe_config) | |
6646 | { | |
6647 | struct drm_device *dev = crtc->base.dev; | |
6648 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6649 | uint32_t tmp; | |
6650 | ||
f458ebbc DV |
6651 | if (!intel_display_power_is_enabled(dev_priv, |
6652 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
b5482bd0 ID |
6653 | return false; |
6654 | ||
e143a21c | 6655 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 6656 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 6657 | |
0e8ffe1b DV |
6658 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
6659 | if (!(tmp & PIPECONF_ENABLE)) | |
6660 | return false; | |
6661 | ||
42571aef VS |
6662 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
6663 | switch (tmp & PIPECONF_BPC_MASK) { | |
6664 | case PIPECONF_6BPC: | |
6665 | pipe_config->pipe_bpp = 18; | |
6666 | break; | |
6667 | case PIPECONF_8BPC: | |
6668 | pipe_config->pipe_bpp = 24; | |
6669 | break; | |
6670 | case PIPECONF_10BPC: | |
6671 | pipe_config->pipe_bpp = 30; | |
6672 | break; | |
6673 | default: | |
6674 | break; | |
6675 | } | |
6676 | } | |
6677 | ||
b5a9fa09 DV |
6678 | if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
6679 | pipe_config->limited_color_range = true; | |
6680 | ||
282740f7 VS |
6681 | if (INTEL_INFO(dev)->gen < 4) |
6682 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
6683 | ||
1bd1bd80 DV |
6684 | intel_get_pipe_timings(crtc, pipe_config); |
6685 | ||
2fa2fe9a DV |
6686 | i9xx_get_pfit_config(crtc, pipe_config); |
6687 | ||
6c49f241 DV |
6688 | if (INTEL_INFO(dev)->gen >= 4) { |
6689 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
6690 | pipe_config->pixel_multiplier = | |
6691 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
6692 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 6693 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
6694 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
6695 | tmp = I915_READ(DPLL(crtc->pipe)); | |
6696 | pipe_config->pixel_multiplier = | |
6697 | ((tmp & SDVO_MULTIPLIER_MASK) | |
6698 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
6699 | } else { | |
6700 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
6701 | * port and will be fixed up in the encoder->get_config | |
6702 | * function. */ | |
6703 | pipe_config->pixel_multiplier = 1; | |
6704 | } | |
8bcc2795 DV |
6705 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
6706 | if (!IS_VALLEYVIEW(dev)) { | |
1c4e0274 VS |
6707 | /* |
6708 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
6709 | * on 830. Filter it out here so that we don't | |
6710 | * report errors due to that. | |
6711 | */ | |
6712 | if (IS_I830(dev)) | |
6713 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
6714 | ||
8bcc2795 DV |
6715 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
6716 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
6717 | } else { |
6718 | /* Mask out read-only status bits. */ | |
6719 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
6720 | DPLL_PORTC_READY_MASK | | |
6721 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 6722 | } |
6c49f241 | 6723 | |
70b23a98 VS |
6724 | if (IS_CHERRYVIEW(dev)) |
6725 | chv_crtc_clock_get(crtc, pipe_config); | |
6726 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
6727 | vlv_crtc_clock_get(crtc, pipe_config); |
6728 | else | |
6729 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 6730 | |
0e8ffe1b DV |
6731 | return true; |
6732 | } | |
6733 | ||
dde86e2d | 6734 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
6735 | { |
6736 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13d83a67 | 6737 | struct intel_encoder *encoder; |
74cfd7ac | 6738 | u32 val, final; |
13d83a67 | 6739 | bool has_lvds = false; |
199e5d79 | 6740 | bool has_cpu_edp = false; |
199e5d79 | 6741 | bool has_panel = false; |
99eb6a01 KP |
6742 | bool has_ck505 = false; |
6743 | bool can_ssc = false; | |
13d83a67 JB |
6744 | |
6745 | /* We need to take the global config into account */ | |
b2784e15 | 6746 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
6747 | switch (encoder->type) { |
6748 | case INTEL_OUTPUT_LVDS: | |
6749 | has_panel = true; | |
6750 | has_lvds = true; | |
6751 | break; | |
6752 | case INTEL_OUTPUT_EDP: | |
6753 | has_panel = true; | |
2de6905f | 6754 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
6755 | has_cpu_edp = true; |
6756 | break; | |
6847d71b PZ |
6757 | default: |
6758 | break; | |
13d83a67 JB |
6759 | } |
6760 | } | |
6761 | ||
99eb6a01 | 6762 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 6763 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
6764 | can_ssc = has_ck505; |
6765 | } else { | |
6766 | has_ck505 = false; | |
6767 | can_ssc = true; | |
6768 | } | |
6769 | ||
2de6905f ID |
6770 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
6771 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
6772 | |
6773 | /* Ironlake: try to setup display ref clock before DPLL | |
6774 | * enabling. This is only under driver's control after | |
6775 | * PCH B stepping, previous chipset stepping should be | |
6776 | * ignoring this setting. | |
6777 | */ | |
74cfd7ac CW |
6778 | val = I915_READ(PCH_DREF_CONTROL); |
6779 | ||
6780 | /* As we must carefully and slowly disable/enable each source in turn, | |
6781 | * compute the final state we want first and check if we need to | |
6782 | * make any changes at all. | |
6783 | */ | |
6784 | final = val; | |
6785 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
6786 | if (has_ck505) | |
6787 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
6788 | else | |
6789 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
6790 | ||
6791 | final &= ~DREF_SSC_SOURCE_MASK; | |
6792 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
6793 | final &= ~DREF_SSC1_ENABLE; | |
6794 | ||
6795 | if (has_panel) { | |
6796 | final |= DREF_SSC_SOURCE_ENABLE; | |
6797 | ||
6798 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
6799 | final |= DREF_SSC1_ENABLE; | |
6800 | ||
6801 | if (has_cpu_edp) { | |
6802 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
6803 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
6804 | else | |
6805 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
6806 | } else | |
6807 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
6808 | } else { | |
6809 | final |= DREF_SSC_SOURCE_DISABLE; | |
6810 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
6811 | } | |
6812 | ||
6813 | if (final == val) | |
6814 | return; | |
6815 | ||
13d83a67 | 6816 | /* Always enable nonspread source */ |
74cfd7ac | 6817 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 6818 | |
99eb6a01 | 6819 | if (has_ck505) |
74cfd7ac | 6820 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 6821 | else |
74cfd7ac | 6822 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 6823 | |
199e5d79 | 6824 | if (has_panel) { |
74cfd7ac CW |
6825 | val &= ~DREF_SSC_SOURCE_MASK; |
6826 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 6827 | |
199e5d79 | 6828 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 6829 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 6830 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 6831 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 6832 | } else |
74cfd7ac | 6833 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
6834 | |
6835 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 6836 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
6837 | POSTING_READ(PCH_DREF_CONTROL); |
6838 | udelay(200); | |
6839 | ||
74cfd7ac | 6840 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
6841 | |
6842 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 6843 | if (has_cpu_edp) { |
99eb6a01 | 6844 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 6845 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 6846 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 6847 | } else |
74cfd7ac | 6848 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 6849 | } else |
74cfd7ac | 6850 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 6851 | |
74cfd7ac | 6852 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
6853 | POSTING_READ(PCH_DREF_CONTROL); |
6854 | udelay(200); | |
6855 | } else { | |
6856 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
6857 | ||
74cfd7ac | 6858 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
6859 | |
6860 | /* Turn off CPU output */ | |
74cfd7ac | 6861 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 6862 | |
74cfd7ac | 6863 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
6864 | POSTING_READ(PCH_DREF_CONTROL); |
6865 | udelay(200); | |
6866 | ||
6867 | /* Turn off the SSC source */ | |
74cfd7ac CW |
6868 | val &= ~DREF_SSC_SOURCE_MASK; |
6869 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
6870 | |
6871 | /* Turn off SSC1 */ | |
74cfd7ac | 6872 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 6873 | |
74cfd7ac | 6874 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
6875 | POSTING_READ(PCH_DREF_CONTROL); |
6876 | udelay(200); | |
6877 | } | |
74cfd7ac CW |
6878 | |
6879 | BUG_ON(val != final); | |
13d83a67 JB |
6880 | } |
6881 | ||
f31f2d55 | 6882 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 6883 | { |
f31f2d55 | 6884 | uint32_t tmp; |
dde86e2d | 6885 | |
0ff066a9 PZ |
6886 | tmp = I915_READ(SOUTH_CHICKEN2); |
6887 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
6888 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 6889 | |
0ff066a9 PZ |
6890 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
6891 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
6892 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 6893 | |
0ff066a9 PZ |
6894 | tmp = I915_READ(SOUTH_CHICKEN2); |
6895 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
6896 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 6897 | |
0ff066a9 PZ |
6898 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
6899 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
6900 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
6901 | } |
6902 | ||
6903 | /* WaMPhyProgramming:hsw */ | |
6904 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
6905 | { | |
6906 | uint32_t tmp; | |
dde86e2d PZ |
6907 | |
6908 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
6909 | tmp &= ~(0xFF << 24); | |
6910 | tmp |= (0x12 << 24); | |
6911 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
6912 | ||
dde86e2d PZ |
6913 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
6914 | tmp |= (1 << 11); | |
6915 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
6916 | ||
6917 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
6918 | tmp |= (1 << 11); | |
6919 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
6920 | ||
dde86e2d PZ |
6921 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
6922 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
6923 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
6924 | ||
6925 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
6926 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
6927 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
6928 | ||
0ff066a9 PZ |
6929 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
6930 | tmp &= ~(7 << 13); | |
6931 | tmp |= (5 << 13); | |
6932 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 6933 | |
0ff066a9 PZ |
6934 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
6935 | tmp &= ~(7 << 13); | |
6936 | tmp |= (5 << 13); | |
6937 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
6938 | |
6939 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
6940 | tmp &= ~0xFF; | |
6941 | tmp |= 0x1C; | |
6942 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
6943 | ||
6944 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
6945 | tmp &= ~0xFF; | |
6946 | tmp |= 0x1C; | |
6947 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
6948 | ||
6949 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
6950 | tmp &= ~(0xFF << 16); | |
6951 | tmp |= (0x1C << 16); | |
6952 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
6953 | ||
6954 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
6955 | tmp &= ~(0xFF << 16); | |
6956 | tmp |= (0x1C << 16); | |
6957 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
6958 | ||
0ff066a9 PZ |
6959 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
6960 | tmp |= (1 << 27); | |
6961 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 6962 | |
0ff066a9 PZ |
6963 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
6964 | tmp |= (1 << 27); | |
6965 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 6966 | |
0ff066a9 PZ |
6967 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
6968 | tmp &= ~(0xF << 28); | |
6969 | tmp |= (4 << 28); | |
6970 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 6971 | |
0ff066a9 PZ |
6972 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
6973 | tmp &= ~(0xF << 28); | |
6974 | tmp |= (4 << 28); | |
6975 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
6976 | } |
6977 | ||
2fa86a1f PZ |
6978 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
6979 | * Programming" based on the parameters passed: | |
6980 | * - Sequence to enable CLKOUT_DP | |
6981 | * - Sequence to enable CLKOUT_DP without spread | |
6982 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
6983 | */ | |
6984 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
6985 | bool with_fdi) | |
f31f2d55 PZ |
6986 | { |
6987 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
6988 | uint32_t reg, tmp; |
6989 | ||
6990 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
6991 | with_spread = true; | |
6992 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && | |
6993 | with_fdi, "LP PCH doesn't have FDI\n")) | |
6994 | with_fdi = false; | |
f31f2d55 PZ |
6995 | |
6996 | mutex_lock(&dev_priv->dpio_lock); | |
6997 | ||
6998 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
6999 | tmp &= ~SBI_SSCCTL_DISABLE; | |
7000 | tmp |= SBI_SSCCTL_PATHALT; | |
7001 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7002 | ||
7003 | udelay(24); | |
7004 | ||
2fa86a1f PZ |
7005 | if (with_spread) { |
7006 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7007 | tmp &= ~SBI_SSCCTL_PATHALT; | |
7008 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 7009 | |
2fa86a1f PZ |
7010 | if (with_fdi) { |
7011 | lpt_reset_fdi_mphy(dev_priv); | |
7012 | lpt_program_fdi_mphy(dev_priv); | |
7013 | } | |
7014 | } | |
dde86e2d | 7015 | |
2fa86a1f PZ |
7016 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
7017 | SBI_GEN0 : SBI_DBUFF0; | |
7018 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
7019 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
7020 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 DV |
7021 | |
7022 | mutex_unlock(&dev_priv->dpio_lock); | |
dde86e2d PZ |
7023 | } |
7024 | ||
47701c3b PZ |
7025 | /* Sequence to disable CLKOUT_DP */ |
7026 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
7027 | { | |
7028 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7029 | uint32_t reg, tmp; | |
7030 | ||
7031 | mutex_lock(&dev_priv->dpio_lock); | |
7032 | ||
7033 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? | |
7034 | SBI_GEN0 : SBI_DBUFF0; | |
7035 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
7036 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
7037 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
7038 | ||
7039 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7040 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
7041 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
7042 | tmp |= SBI_SSCCTL_PATHALT; | |
7043 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7044 | udelay(32); | |
7045 | } | |
7046 | tmp |= SBI_SSCCTL_DISABLE; | |
7047 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7048 | } | |
7049 | ||
7050 | mutex_unlock(&dev_priv->dpio_lock); | |
7051 | } | |
7052 | ||
bf8fa3d3 PZ |
7053 | static void lpt_init_pch_refclk(struct drm_device *dev) |
7054 | { | |
bf8fa3d3 PZ |
7055 | struct intel_encoder *encoder; |
7056 | bool has_vga = false; | |
7057 | ||
b2784e15 | 7058 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
7059 | switch (encoder->type) { |
7060 | case INTEL_OUTPUT_ANALOG: | |
7061 | has_vga = true; | |
7062 | break; | |
6847d71b PZ |
7063 | default: |
7064 | break; | |
bf8fa3d3 PZ |
7065 | } |
7066 | } | |
7067 | ||
47701c3b PZ |
7068 | if (has_vga) |
7069 | lpt_enable_clkout_dp(dev, true, true); | |
7070 | else | |
7071 | lpt_disable_clkout_dp(dev); | |
bf8fa3d3 PZ |
7072 | } |
7073 | ||
dde86e2d PZ |
7074 | /* |
7075 | * Initialize reference clocks when the driver loads | |
7076 | */ | |
7077 | void intel_init_pch_refclk(struct drm_device *dev) | |
7078 | { | |
7079 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
7080 | ironlake_init_pch_refclk(dev); | |
7081 | else if (HAS_PCH_LPT(dev)) | |
7082 | lpt_init_pch_refclk(dev); | |
7083 | } | |
7084 | ||
d9d444cb JB |
7085 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
7086 | { | |
7087 | struct drm_device *dev = crtc->dev; | |
7088 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7089 | struct intel_encoder *encoder; | |
d9d444cb JB |
7090 | int num_connectors = 0; |
7091 | bool is_lvds = false; | |
7092 | ||
d0737e1d ACO |
7093 | for_each_intel_encoder(dev, encoder) { |
7094 | if (encoder->new_crtc != to_intel_crtc(crtc)) | |
7095 | continue; | |
7096 | ||
d9d444cb JB |
7097 | switch (encoder->type) { |
7098 | case INTEL_OUTPUT_LVDS: | |
7099 | is_lvds = true; | |
7100 | break; | |
6847d71b PZ |
7101 | default: |
7102 | break; | |
d9d444cb JB |
7103 | } |
7104 | num_connectors++; | |
7105 | } | |
7106 | ||
7107 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 7108 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 7109 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 7110 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
7111 | } |
7112 | ||
7113 | return 120000; | |
7114 | } | |
7115 | ||
6ff93609 | 7116 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 7117 | { |
c8203565 | 7118 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
7119 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7120 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
7121 | uint32_t val; |
7122 | ||
78114071 | 7123 | val = 0; |
c8203565 | 7124 | |
965e0c48 | 7125 | switch (intel_crtc->config.pipe_bpp) { |
c8203565 | 7126 | case 18: |
dfd07d72 | 7127 | val |= PIPECONF_6BPC; |
c8203565 PZ |
7128 | break; |
7129 | case 24: | |
dfd07d72 | 7130 | val |= PIPECONF_8BPC; |
c8203565 PZ |
7131 | break; |
7132 | case 30: | |
dfd07d72 | 7133 | val |= PIPECONF_10BPC; |
c8203565 PZ |
7134 | break; |
7135 | case 36: | |
dfd07d72 | 7136 | val |= PIPECONF_12BPC; |
c8203565 PZ |
7137 | break; |
7138 | default: | |
cc769b62 PZ |
7139 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
7140 | BUG(); | |
c8203565 PZ |
7141 | } |
7142 | ||
d8b32247 | 7143 | if (intel_crtc->config.dither) |
c8203565 PZ |
7144 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
7145 | ||
6ff93609 | 7146 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
7147 | val |= PIPECONF_INTERLACED_ILK; |
7148 | else | |
7149 | val |= PIPECONF_PROGRESSIVE; | |
7150 | ||
50f3b016 | 7151 | if (intel_crtc->config.limited_color_range) |
3685a8f3 | 7152 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 7153 | |
c8203565 PZ |
7154 | I915_WRITE(PIPECONF(pipe), val); |
7155 | POSTING_READ(PIPECONF(pipe)); | |
7156 | } | |
7157 | ||
86d3efce VS |
7158 | /* |
7159 | * Set up the pipe CSC unit. | |
7160 | * | |
7161 | * Currently only full range RGB to limited range RGB conversion | |
7162 | * is supported, but eventually this should handle various | |
7163 | * RGB<->YCbCr scenarios as well. | |
7164 | */ | |
50f3b016 | 7165 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
7166 | { |
7167 | struct drm_device *dev = crtc->dev; | |
7168 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7169 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7170 | int pipe = intel_crtc->pipe; | |
7171 | uint16_t coeff = 0x7800; /* 1.0 */ | |
7172 | ||
7173 | /* | |
7174 | * TODO: Check what kind of values actually come out of the pipe | |
7175 | * with these coeff/postoff values and adjust to get the best | |
7176 | * accuracy. Perhaps we even need to take the bpc value into | |
7177 | * consideration. | |
7178 | */ | |
7179 | ||
50f3b016 | 7180 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
7181 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
7182 | ||
7183 | /* | |
7184 | * GY/GU and RY/RU should be the other way around according | |
7185 | * to BSpec, but reality doesn't agree. Just set them up in | |
7186 | * a way that results in the correct picture. | |
7187 | */ | |
7188 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
7189 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
7190 | ||
7191 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
7192 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
7193 | ||
7194 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
7195 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
7196 | ||
7197 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
7198 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
7199 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
7200 | ||
7201 | if (INTEL_INFO(dev)->gen > 6) { | |
7202 | uint16_t postoff = 0; | |
7203 | ||
50f3b016 | 7204 | if (intel_crtc->config.limited_color_range) |
32cf0cb0 | 7205 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
7206 | |
7207 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
7208 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
7209 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
7210 | ||
7211 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
7212 | } else { | |
7213 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
7214 | ||
50f3b016 | 7215 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
7216 | mode |= CSC_BLACK_SCREEN_OFFSET; |
7217 | ||
7218 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
7219 | } | |
7220 | } | |
7221 | ||
6ff93609 | 7222 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 7223 | { |
756f85cf PZ |
7224 | struct drm_device *dev = crtc->dev; |
7225 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 7226 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 7227 | enum pipe pipe = intel_crtc->pipe; |
3b117c8f | 7228 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee2b0b38 PZ |
7229 | uint32_t val; |
7230 | ||
3eff4faa | 7231 | val = 0; |
ee2b0b38 | 7232 | |
756f85cf | 7233 | if (IS_HASWELL(dev) && intel_crtc->config.dither) |
ee2b0b38 PZ |
7234 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
7235 | ||
6ff93609 | 7236 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
7237 | val |= PIPECONF_INTERLACED_ILK; |
7238 | else | |
7239 | val |= PIPECONF_PROGRESSIVE; | |
7240 | ||
702e7a56 PZ |
7241 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
7242 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
7243 | |
7244 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
7245 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf | 7246 | |
3cdf122c | 7247 | if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { |
756f85cf PZ |
7248 | val = 0; |
7249 | ||
7250 | switch (intel_crtc->config.pipe_bpp) { | |
7251 | case 18: | |
7252 | val |= PIPEMISC_DITHER_6_BPC; | |
7253 | break; | |
7254 | case 24: | |
7255 | val |= PIPEMISC_DITHER_8_BPC; | |
7256 | break; | |
7257 | case 30: | |
7258 | val |= PIPEMISC_DITHER_10_BPC; | |
7259 | break; | |
7260 | case 36: | |
7261 | val |= PIPEMISC_DITHER_12_BPC; | |
7262 | break; | |
7263 | default: | |
7264 | /* Case prevented by pipe_config_set_bpp. */ | |
7265 | BUG(); | |
7266 | } | |
7267 | ||
7268 | if (intel_crtc->config.dither) | |
7269 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; | |
7270 | ||
7271 | I915_WRITE(PIPEMISC(pipe), val); | |
7272 | } | |
ee2b0b38 PZ |
7273 | } |
7274 | ||
6591c6e4 | 7275 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
6591c6e4 PZ |
7276 | intel_clock_t *clock, |
7277 | bool *has_reduced_clock, | |
7278 | intel_clock_t *reduced_clock) | |
7279 | { | |
7280 | struct drm_device *dev = crtc->dev; | |
7281 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a919ff14 | 7282 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6591c6e4 | 7283 | int refclk; |
d4906093 | 7284 | const intel_limit_t *limit; |
a16af721 | 7285 | bool ret, is_lvds = false; |
79e53945 | 7286 | |
d0737e1d | 7287 | is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS); |
79e53945 | 7288 | |
d9d444cb | 7289 | refclk = ironlake_get_refclk(crtc); |
79e53945 | 7290 | |
d4906093 ML |
7291 | /* |
7292 | * Returns a set of divisors for the desired target clock with the given | |
7293 | * refclk, or FALSE. The returned values represent the clock equation: | |
7294 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
7295 | */ | |
409ee761 | 7296 | limit = intel_limit(intel_crtc, refclk); |
a919ff14 | 7297 | ret = dev_priv->display.find_dpll(limit, intel_crtc, |
d0737e1d | 7298 | intel_crtc->new_config->port_clock, |
ee9300bb | 7299 | refclk, NULL, clock); |
6591c6e4 PZ |
7300 | if (!ret) |
7301 | return false; | |
cda4b7d3 | 7302 | |
ddc9003c | 7303 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
7304 | /* |
7305 | * Ensure we match the reduced clock's P to the target clock. | |
7306 | * If the clocks don't match, we can't switch the display clock | |
7307 | * by using the FP0/FP1. In such case we will disable the LVDS | |
7308 | * downclock feature. | |
7309 | */ | |
ee9300bb | 7310 | *has_reduced_clock = |
a919ff14 | 7311 | dev_priv->display.find_dpll(limit, intel_crtc, |
ee9300bb DV |
7312 | dev_priv->lvds_downclock, |
7313 | refclk, clock, | |
7314 | reduced_clock); | |
652c393a | 7315 | } |
61e9653f | 7316 | |
6591c6e4 PZ |
7317 | return true; |
7318 | } | |
7319 | ||
d4b1931c PZ |
7320 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
7321 | { | |
7322 | /* | |
7323 | * Account for spread spectrum to avoid | |
7324 | * oversubscribing the link. Max center spread | |
7325 | * is 2.5%; use 5% for safety's sake. | |
7326 | */ | |
7327 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 7328 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
7329 | } |
7330 | ||
7429e9d4 | 7331 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 7332 | { |
7429e9d4 | 7333 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
7334 | } |
7335 | ||
de13a2e3 | 7336 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
7429e9d4 | 7337 | u32 *fp, |
9a7c7890 | 7338 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 7339 | { |
de13a2e3 | 7340 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
7341 | struct drm_device *dev = crtc->dev; |
7342 | struct drm_i915_private *dev_priv = dev->dev_private; | |
de13a2e3 PZ |
7343 | struct intel_encoder *intel_encoder; |
7344 | uint32_t dpll; | |
6cc5f341 | 7345 | int factor, num_connectors = 0; |
09ede541 | 7346 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 7347 | |
d0737e1d ACO |
7348 | for_each_intel_encoder(dev, intel_encoder) { |
7349 | if (intel_encoder->new_crtc != to_intel_crtc(crtc)) | |
7350 | continue; | |
7351 | ||
de13a2e3 | 7352 | switch (intel_encoder->type) { |
79e53945 JB |
7353 | case INTEL_OUTPUT_LVDS: |
7354 | is_lvds = true; | |
7355 | break; | |
7356 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 7357 | case INTEL_OUTPUT_HDMI: |
79e53945 | 7358 | is_sdvo = true; |
79e53945 | 7359 | break; |
6847d71b PZ |
7360 | default: |
7361 | break; | |
79e53945 | 7362 | } |
43565a06 | 7363 | |
c751ce4f | 7364 | num_connectors++; |
79e53945 | 7365 | } |
79e53945 | 7366 | |
c1858123 | 7367 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
7368 | factor = 21; |
7369 | if (is_lvds) { | |
7370 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 7371 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 7372 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 7373 | factor = 25; |
d0737e1d | 7374 | } else if (intel_crtc->new_config->sdvo_tv_clock) |
8febb297 | 7375 | factor = 20; |
c1858123 | 7376 | |
d0737e1d | 7377 | if (ironlake_needs_fb_cb_tune(&intel_crtc->new_config->dpll, factor)) |
7d0ac5b7 | 7378 | *fp |= FP_CB_TUNE; |
2c07245f | 7379 | |
9a7c7890 DV |
7380 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
7381 | *fp2 |= FP_CB_TUNE; | |
7382 | ||
5eddb70b | 7383 | dpll = 0; |
2c07245f | 7384 | |
a07d6787 EA |
7385 | if (is_lvds) |
7386 | dpll |= DPLLB_MODE_LVDS; | |
7387 | else | |
7388 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 7389 | |
d0737e1d | 7390 | dpll |= (intel_crtc->new_config->pixel_multiplier - 1) |
ef1b460d | 7391 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f DV |
7392 | |
7393 | if (is_sdvo) | |
4a33e48d | 7394 | dpll |= DPLL_SDVO_HIGH_SPEED; |
d0737e1d | 7395 | if (intel_crtc->new_config->has_dp_encoder) |
4a33e48d | 7396 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 7397 | |
a07d6787 | 7398 | /* compute bitmask from p1 value */ |
d0737e1d | 7399 | dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 7400 | /* also FPA1 */ |
d0737e1d | 7401 | dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 7402 | |
d0737e1d | 7403 | switch (intel_crtc->new_config->dpll.p2) { |
a07d6787 EA |
7404 | case 5: |
7405 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7406 | break; | |
7407 | case 7: | |
7408 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7409 | break; | |
7410 | case 10: | |
7411 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7412 | break; | |
7413 | case 14: | |
7414 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7415 | break; | |
79e53945 JB |
7416 | } |
7417 | ||
b4c09f3b | 7418 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 7419 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
7420 | else |
7421 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7422 | ||
959e16d6 | 7423 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
7424 | } |
7425 | ||
3fb37703 | 7426 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc) |
de13a2e3 | 7427 | { |
c7653199 | 7428 | struct drm_device *dev = crtc->base.dev; |
de13a2e3 | 7429 | intel_clock_t clock, reduced_clock; |
cbbab5bd | 7430 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 7431 | bool ok, has_reduced_clock = false; |
8b47047b | 7432 | bool is_lvds = false; |
e2b78267 | 7433 | struct intel_shared_dpll *pll; |
de13a2e3 | 7434 | |
409ee761 | 7435 | is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS); |
79e53945 | 7436 | |
5dc5298b PZ |
7437 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
7438 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 7439 | |
c7653199 | 7440 | ok = ironlake_compute_clocks(&crtc->base, &clock, |
de13a2e3 | 7441 | &has_reduced_clock, &reduced_clock); |
d0737e1d | 7442 | if (!ok && !crtc->new_config->clock_set) { |
de13a2e3 PZ |
7443 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
7444 | return -EINVAL; | |
79e53945 | 7445 | } |
f47709a9 | 7446 | /* Compat-code for transition, will disappear. */ |
d0737e1d ACO |
7447 | if (!crtc->new_config->clock_set) { |
7448 | crtc->new_config->dpll.n = clock.n; | |
7449 | crtc->new_config->dpll.m1 = clock.m1; | |
7450 | crtc->new_config->dpll.m2 = clock.m2; | |
7451 | crtc->new_config->dpll.p1 = clock.p1; | |
7452 | crtc->new_config->dpll.p2 = clock.p2; | |
f47709a9 | 7453 | } |
79e53945 | 7454 | |
5dc5298b | 7455 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
d0737e1d ACO |
7456 | if (crtc->new_config->has_pch_encoder) { |
7457 | fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll); | |
cbbab5bd | 7458 | if (has_reduced_clock) |
7429e9d4 | 7459 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 7460 | |
c7653199 | 7461 | dpll = ironlake_compute_dpll(crtc, |
cbbab5bd DV |
7462 | &fp, &reduced_clock, |
7463 | has_reduced_clock ? &fp2 : NULL); | |
7464 | ||
d0737e1d ACO |
7465 | crtc->new_config->dpll_hw_state.dpll = dpll; |
7466 | crtc->new_config->dpll_hw_state.fp0 = fp; | |
66e985c0 | 7467 | if (has_reduced_clock) |
d0737e1d | 7468 | crtc->new_config->dpll_hw_state.fp1 = fp2; |
66e985c0 | 7469 | else |
d0737e1d | 7470 | crtc->new_config->dpll_hw_state.fp1 = fp; |
66e985c0 | 7471 | |
c7653199 | 7472 | pll = intel_get_shared_dpll(crtc); |
ee7b9f93 | 7473 | if (pll == NULL) { |
84f44ce7 | 7474 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
c7653199 | 7475 | pipe_name(crtc->pipe)); |
4b645f14 JB |
7476 | return -EINVAL; |
7477 | } | |
3fb37703 | 7478 | } |
79e53945 | 7479 | |
d330a953 | 7480 | if (is_lvds && has_reduced_clock && i915.powersave) |
c7653199 | 7481 | crtc->lowfreq_avail = true; |
bcd644e0 | 7482 | else |
c7653199 | 7483 | crtc->lowfreq_avail = false; |
e2b78267 | 7484 | |
c8f7a0db | 7485 | return 0; |
79e53945 JB |
7486 | } |
7487 | ||
eb14cb74 VS |
7488 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
7489 | struct intel_link_m_n *m_n) | |
7490 | { | |
7491 | struct drm_device *dev = crtc->base.dev; | |
7492 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7493 | enum pipe pipe = crtc->pipe; | |
7494 | ||
7495 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
7496 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
7497 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
7498 | & ~TU_SIZE_MASK; | |
7499 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
7500 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
7501 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7502 | } | |
7503 | ||
7504 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
7505 | enum transcoder transcoder, | |
b95af8be VK |
7506 | struct intel_link_m_n *m_n, |
7507 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
7508 | { |
7509 | struct drm_device *dev = crtc->base.dev; | |
7510 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 7511 | enum pipe pipe = crtc->pipe; |
72419203 | 7512 | |
eb14cb74 VS |
7513 | if (INTEL_INFO(dev)->gen >= 5) { |
7514 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
7515 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
7516 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
7517 | & ~TU_SIZE_MASK; | |
7518 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
7519 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
7520 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
7521 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
7522 | * gen < 8) and if DRRS is supported (to make sure the | |
7523 | * registers are not unnecessarily read). | |
7524 | */ | |
7525 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
7526 | crtc->config.has_drrs) { | |
7527 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); | |
7528 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
7529 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
7530 | & ~TU_SIZE_MASK; | |
7531 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
7532 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
7533 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7534 | } | |
eb14cb74 VS |
7535 | } else { |
7536 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
7537 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
7538 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
7539 | & ~TU_SIZE_MASK; | |
7540 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
7541 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
7542 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7543 | } | |
7544 | } | |
7545 | ||
7546 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
7547 | struct intel_crtc_config *pipe_config) | |
7548 | { | |
7549 | if (crtc->config.has_pch_encoder) | |
7550 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); | |
7551 | else | |
7552 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
7553 | &pipe_config->dp_m_n, |
7554 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 7555 | } |
72419203 | 7556 | |
eb14cb74 VS |
7557 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
7558 | struct intel_crtc_config *pipe_config) | |
7559 | { | |
7560 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 7561 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
7562 | } |
7563 | ||
bd2e244f JB |
7564 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
7565 | struct intel_crtc_config *pipe_config) | |
7566 | { | |
7567 | struct drm_device *dev = crtc->base.dev; | |
7568 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7569 | uint32_t tmp; | |
7570 | ||
7571 | tmp = I915_READ(PS_CTL(crtc->pipe)); | |
7572 | ||
7573 | if (tmp & PS_ENABLE) { | |
7574 | pipe_config->pch_pfit.enabled = true; | |
7575 | pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe)); | |
7576 | pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe)); | |
7577 | } | |
7578 | } | |
7579 | ||
2fa2fe9a DV |
7580 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
7581 | struct intel_crtc_config *pipe_config) | |
7582 | { | |
7583 | struct drm_device *dev = crtc->base.dev; | |
7584 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7585 | uint32_t tmp; | |
7586 | ||
7587 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
7588 | ||
7589 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 7590 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
7591 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
7592 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
7593 | |
7594 | /* We currently do not free assignements of panel fitters on | |
7595 | * ivb/hsw (since we don't use the higher upscaling modes which | |
7596 | * differentiates them) so just WARN about this case for now. */ | |
7597 | if (IS_GEN7(dev)) { | |
7598 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
7599 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
7600 | } | |
2fa2fe9a | 7601 | } |
79e53945 JB |
7602 | } |
7603 | ||
4c6baa59 JB |
7604 | static void ironlake_get_plane_config(struct intel_crtc *crtc, |
7605 | struct intel_plane_config *plane_config) | |
7606 | { | |
7607 | struct drm_device *dev = crtc->base.dev; | |
7608 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7609 | u32 val, base, offset; | |
7610 | int pipe = crtc->pipe, plane = crtc->plane; | |
7611 | int fourcc, pixel_format; | |
7612 | int aligned_height; | |
7613 | ||
66e514c1 DA |
7614 | crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL); |
7615 | if (!crtc->base.primary->fb) { | |
4c6baa59 JB |
7616 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
7617 | return; | |
7618 | } | |
7619 | ||
7620 | val = I915_READ(DSPCNTR(plane)); | |
7621 | ||
7622 | if (INTEL_INFO(dev)->gen >= 4) | |
7623 | if (val & DISPPLANE_TILED) | |
7624 | plane_config->tiled = true; | |
7625 | ||
7626 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
7627 | fourcc = intel_format_to_fourcc(pixel_format); | |
66e514c1 DA |
7628 | crtc->base.primary->fb->pixel_format = fourcc; |
7629 | crtc->base.primary->fb->bits_per_pixel = | |
4c6baa59 JB |
7630 | drm_format_plane_cpp(fourcc, 0) * 8; |
7631 | ||
7632 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
7633 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
7634 | offset = I915_READ(DSPOFFSET(plane)); | |
7635 | } else { | |
7636 | if (plane_config->tiled) | |
7637 | offset = I915_READ(DSPTILEOFF(plane)); | |
7638 | else | |
7639 | offset = I915_READ(DSPLINOFF(plane)); | |
7640 | } | |
7641 | plane_config->base = base; | |
7642 | ||
7643 | val = I915_READ(PIPESRC(pipe)); | |
66e514c1 DA |
7644 | crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1; |
7645 | crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
7646 | |
7647 | val = I915_READ(DSPSTRIDE(pipe)); | |
026b96e2 | 7648 | crtc->base.primary->fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 7649 | |
66e514c1 | 7650 | aligned_height = intel_align_height(dev, crtc->base.primary->fb->height, |
4c6baa59 JB |
7651 | plane_config->tiled); |
7652 | ||
1267a26b FF |
7653 | plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] * |
7654 | aligned_height); | |
4c6baa59 JB |
7655 | |
7656 | DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
66e514c1 DA |
7657 | pipe, plane, crtc->base.primary->fb->width, |
7658 | crtc->base.primary->fb->height, | |
7659 | crtc->base.primary->fb->bits_per_pixel, base, | |
7660 | crtc->base.primary->fb->pitches[0], | |
4c6baa59 JB |
7661 | plane_config->size); |
7662 | } | |
7663 | ||
0e8ffe1b DV |
7664 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
7665 | struct intel_crtc_config *pipe_config) | |
7666 | { | |
7667 | struct drm_device *dev = crtc->base.dev; | |
7668 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7669 | uint32_t tmp; | |
7670 | ||
f458ebbc DV |
7671 | if (!intel_display_power_is_enabled(dev_priv, |
7672 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
930e8c9e PZ |
7673 | return false; |
7674 | ||
e143a21c | 7675 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 7676 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 7677 | |
0e8ffe1b DV |
7678 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
7679 | if (!(tmp & PIPECONF_ENABLE)) | |
7680 | return false; | |
7681 | ||
42571aef VS |
7682 | switch (tmp & PIPECONF_BPC_MASK) { |
7683 | case PIPECONF_6BPC: | |
7684 | pipe_config->pipe_bpp = 18; | |
7685 | break; | |
7686 | case PIPECONF_8BPC: | |
7687 | pipe_config->pipe_bpp = 24; | |
7688 | break; | |
7689 | case PIPECONF_10BPC: | |
7690 | pipe_config->pipe_bpp = 30; | |
7691 | break; | |
7692 | case PIPECONF_12BPC: | |
7693 | pipe_config->pipe_bpp = 36; | |
7694 | break; | |
7695 | default: | |
7696 | break; | |
7697 | } | |
7698 | ||
b5a9fa09 DV |
7699 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
7700 | pipe_config->limited_color_range = true; | |
7701 | ||
ab9412ba | 7702 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
7703 | struct intel_shared_dpll *pll; |
7704 | ||
88adfff1 DV |
7705 | pipe_config->has_pch_encoder = true; |
7706 | ||
627eb5a3 DV |
7707 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
7708 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
7709 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
7710 | |
7711 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 7712 | |
c0d43d62 | 7713 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
7714 | pipe_config->shared_dpll = |
7715 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
7716 | } else { |
7717 | tmp = I915_READ(PCH_DPLL_SEL); | |
7718 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
7719 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
7720 | else | |
7721 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
7722 | } | |
66e985c0 DV |
7723 | |
7724 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
7725 | ||
7726 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
7727 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
7728 | |
7729 | tmp = pipe_config->dpll_hw_state.dpll; | |
7730 | pipe_config->pixel_multiplier = | |
7731 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
7732 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
7733 | |
7734 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
7735 | } else { |
7736 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
7737 | } |
7738 | ||
1bd1bd80 DV |
7739 | intel_get_pipe_timings(crtc, pipe_config); |
7740 | ||
2fa2fe9a DV |
7741 | ironlake_get_pfit_config(crtc, pipe_config); |
7742 | ||
0e8ffe1b DV |
7743 | return true; |
7744 | } | |
7745 | ||
be256dc7 PZ |
7746 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
7747 | { | |
7748 | struct drm_device *dev = dev_priv->dev; | |
be256dc7 | 7749 | struct intel_crtc *crtc; |
be256dc7 | 7750 | |
d3fcc808 | 7751 | for_each_intel_crtc(dev, crtc) |
798183c5 | 7752 | WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
7753 | pipe_name(crtc->pipe)); |
7754 | ||
7755 | WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); | |
8cc3e169 DV |
7756 | WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); |
7757 | WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); | |
7758 | WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
be256dc7 PZ |
7759 | WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); |
7760 | WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
7761 | "CPU PWM1 enabled\n"); | |
c5107b87 PZ |
7762 | if (IS_HASWELL(dev)) |
7763 | WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, | |
7764 | "CPU PWM2 enabled\n"); | |
be256dc7 PZ |
7765 | WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
7766 | "PCH PWM1 enabled\n"); | |
7767 | WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, | |
7768 | "Utility pin enabled\n"); | |
7769 | WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); | |
7770 | ||
9926ada1 PZ |
7771 | /* |
7772 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
7773 | * interrupts remain enabled. We used to check for that, but since it's | |
7774 | * gen-specific and since we only disable LCPLL after we fully disable | |
7775 | * the interrupts, the check below should be enough. | |
7776 | */ | |
9df7575f | 7777 | WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
7778 | } |
7779 | ||
9ccd5aeb PZ |
7780 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
7781 | { | |
7782 | struct drm_device *dev = dev_priv->dev; | |
7783 | ||
7784 | if (IS_HASWELL(dev)) | |
7785 | return I915_READ(D_COMP_HSW); | |
7786 | else | |
7787 | return I915_READ(D_COMP_BDW); | |
7788 | } | |
7789 | ||
3c4c9b81 PZ |
7790 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
7791 | { | |
7792 | struct drm_device *dev = dev_priv->dev; | |
7793 | ||
7794 | if (IS_HASWELL(dev)) { | |
7795 | mutex_lock(&dev_priv->rps.hw_lock); | |
7796 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
7797 | val)) | |
f475dadf | 7798 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
7799 | mutex_unlock(&dev_priv->rps.hw_lock); |
7800 | } else { | |
9ccd5aeb PZ |
7801 | I915_WRITE(D_COMP_BDW, val); |
7802 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 7803 | } |
be256dc7 PZ |
7804 | } |
7805 | ||
7806 | /* | |
7807 | * This function implements pieces of two sequences from BSpec: | |
7808 | * - Sequence for display software to disable LCPLL | |
7809 | * - Sequence for display software to allow package C8+ | |
7810 | * The steps implemented here are just the steps that actually touch the LCPLL | |
7811 | * register. Callers should take care of disabling all the display engine | |
7812 | * functions, doing the mode unset, fixing interrupts, etc. | |
7813 | */ | |
6ff58d53 PZ |
7814 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
7815 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
7816 | { |
7817 | uint32_t val; | |
7818 | ||
7819 | assert_can_disable_lcpll(dev_priv); | |
7820 | ||
7821 | val = I915_READ(LCPLL_CTL); | |
7822 | ||
7823 | if (switch_to_fclk) { | |
7824 | val |= LCPLL_CD_SOURCE_FCLK; | |
7825 | I915_WRITE(LCPLL_CTL, val); | |
7826 | ||
7827 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
7828 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
7829 | DRM_ERROR("Switching to FCLK failed\n"); | |
7830 | ||
7831 | val = I915_READ(LCPLL_CTL); | |
7832 | } | |
7833 | ||
7834 | val |= LCPLL_PLL_DISABLE; | |
7835 | I915_WRITE(LCPLL_CTL, val); | |
7836 | POSTING_READ(LCPLL_CTL); | |
7837 | ||
7838 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
7839 | DRM_ERROR("LCPLL still locked\n"); | |
7840 | ||
9ccd5aeb | 7841 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 7842 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 7843 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
7844 | ndelay(100); |
7845 | ||
9ccd5aeb PZ |
7846 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
7847 | 1)) | |
be256dc7 PZ |
7848 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
7849 | ||
7850 | if (allow_power_down) { | |
7851 | val = I915_READ(LCPLL_CTL); | |
7852 | val |= LCPLL_POWER_DOWN_ALLOW; | |
7853 | I915_WRITE(LCPLL_CTL, val); | |
7854 | POSTING_READ(LCPLL_CTL); | |
7855 | } | |
7856 | } | |
7857 | ||
7858 | /* | |
7859 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
7860 | * source. | |
7861 | */ | |
6ff58d53 | 7862 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
7863 | { |
7864 | uint32_t val; | |
7865 | ||
7866 | val = I915_READ(LCPLL_CTL); | |
7867 | ||
7868 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
7869 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
7870 | return; | |
7871 | ||
a8a8bd54 PZ |
7872 | /* |
7873 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
7874 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
7875 | * | |
7876 | * The other problem is that hsw_restore_lcpll() is called as part of | |
7877 | * the runtime PM resume sequence, so we can't just call | |
7878 | * gen6_gt_force_wake_get() because that function calls | |
7879 | * intel_runtime_pm_get(), and we can't change the runtime PM refcount | |
7880 | * while we are on the resume sequence. So to solve this problem we have | |
7881 | * to call special forcewake code that doesn't touch runtime PM and | |
7882 | * doesn't enable the forcewake delayed work. | |
7883 | */ | |
d2e40e27 | 7884 | spin_lock_irq(&dev_priv->uncore.lock); |
a8a8bd54 PZ |
7885 | if (dev_priv->uncore.forcewake_count++ == 0) |
7886 | dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL); | |
d2e40e27 | 7887 | spin_unlock_irq(&dev_priv->uncore.lock); |
215733fa | 7888 | |
be256dc7 PZ |
7889 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
7890 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
7891 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 7892 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
7893 | } |
7894 | ||
9ccd5aeb | 7895 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
7896 | val |= D_COMP_COMP_FORCE; |
7897 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 7898 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
7899 | |
7900 | val = I915_READ(LCPLL_CTL); | |
7901 | val &= ~LCPLL_PLL_DISABLE; | |
7902 | I915_WRITE(LCPLL_CTL, val); | |
7903 | ||
7904 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
7905 | DRM_ERROR("LCPLL not locked yet\n"); | |
7906 | ||
7907 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
7908 | val = I915_READ(LCPLL_CTL); | |
7909 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
7910 | I915_WRITE(LCPLL_CTL, val); | |
7911 | ||
7912 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
7913 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
7914 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
7915 | } | |
215733fa | 7916 | |
a8a8bd54 | 7917 | /* See the big comment above. */ |
d2e40e27 | 7918 | spin_lock_irq(&dev_priv->uncore.lock); |
a8a8bd54 PZ |
7919 | if (--dev_priv->uncore.forcewake_count == 0) |
7920 | dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL); | |
d2e40e27 | 7921 | spin_unlock_irq(&dev_priv->uncore.lock); |
be256dc7 PZ |
7922 | } |
7923 | ||
765dab67 PZ |
7924 | /* |
7925 | * Package states C8 and deeper are really deep PC states that can only be | |
7926 | * reached when all the devices on the system allow it, so even if the graphics | |
7927 | * device allows PC8+, it doesn't mean the system will actually get to these | |
7928 | * states. Our driver only allows PC8+ when going into runtime PM. | |
7929 | * | |
7930 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
7931 | * well is disabled and most interrupts are disabled, and these are also | |
7932 | * requirements for runtime PM. When these conditions are met, we manually do | |
7933 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
7934 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
7935 | * hang the machine. | |
7936 | * | |
7937 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
7938 | * the state of some registers, so when we come back from PC8+ we need to | |
7939 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
7940 | * need to take care of the registers kept by RC6. Notice that this happens even | |
7941 | * if we don't put the device in PCI D3 state (which is what currently happens | |
7942 | * because of the runtime PM support). | |
7943 | * | |
7944 | * For more, read "Display Sequences for Package C8" on the hardware | |
7945 | * documentation. | |
7946 | */ | |
a14cb6fc | 7947 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 7948 | { |
c67a470b PZ |
7949 | struct drm_device *dev = dev_priv->dev; |
7950 | uint32_t val; | |
7951 | ||
c67a470b PZ |
7952 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
7953 | ||
c67a470b PZ |
7954 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
7955 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
7956 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
7957 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
7958 | } | |
7959 | ||
7960 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
7961 | hsw_disable_lcpll(dev_priv, true, true); |
7962 | } | |
7963 | ||
a14cb6fc | 7964 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
7965 | { |
7966 | struct drm_device *dev = dev_priv->dev; | |
7967 | uint32_t val; | |
7968 | ||
c67a470b PZ |
7969 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
7970 | ||
7971 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
7972 | lpt_init_pch_refclk(dev); |
7973 | ||
7974 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
7975 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
7976 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
7977 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
7978 | } | |
7979 | ||
7980 | intel_prepare_ddi(dev); | |
c67a470b PZ |
7981 | } |
7982 | ||
797d0259 | 7983 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc) |
09b4ddf9 | 7984 | { |
c7653199 | 7985 | if (!intel_ddi_pll_select(crtc)) |
6441ab5f | 7986 | return -EINVAL; |
716c2e55 | 7987 | |
c7653199 | 7988 | crtc->lowfreq_avail = false; |
644cef34 | 7989 | |
c8f7a0db | 7990 | return 0; |
79e53945 JB |
7991 | } |
7992 | ||
96b7dfb7 S |
7993 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
7994 | enum port port, | |
7995 | struct intel_crtc_config *pipe_config) | |
7996 | { | |
7997 | u32 temp; | |
7998 | ||
7999 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
8000 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
8001 | ||
8002 | switch (pipe_config->ddi_pll_sel) { | |
8003 | case SKL_DPLL1: | |
8004 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
8005 | break; | |
8006 | case SKL_DPLL2: | |
8007 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
8008 | break; | |
8009 | case SKL_DPLL3: | |
8010 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
8011 | break; | |
96b7dfb7 S |
8012 | } |
8013 | } | |
8014 | ||
7d2c8175 DL |
8015 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
8016 | enum port port, | |
8017 | struct intel_crtc_config *pipe_config) | |
8018 | { | |
8019 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); | |
8020 | ||
8021 | switch (pipe_config->ddi_pll_sel) { | |
8022 | case PORT_CLK_SEL_WRPLL1: | |
8023 | pipe_config->shared_dpll = DPLL_ID_WRPLL1; | |
8024 | break; | |
8025 | case PORT_CLK_SEL_WRPLL2: | |
8026 | pipe_config->shared_dpll = DPLL_ID_WRPLL2; | |
8027 | break; | |
8028 | } | |
8029 | } | |
8030 | ||
26804afd DV |
8031 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
8032 | struct intel_crtc_config *pipe_config) | |
8033 | { | |
8034 | struct drm_device *dev = crtc->base.dev; | |
8035 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d452c5b6 | 8036 | struct intel_shared_dpll *pll; |
26804afd DV |
8037 | enum port port; |
8038 | uint32_t tmp; | |
8039 | ||
8040 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
8041 | ||
8042 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
8043 | ||
96b7dfb7 S |
8044 | if (IS_SKYLAKE(dev)) |
8045 | skylake_get_ddi_pll(dev_priv, port, pipe_config); | |
8046 | else | |
8047 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 8048 | |
d452c5b6 DV |
8049 | if (pipe_config->shared_dpll >= 0) { |
8050 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
8051 | ||
8052 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
8053 | &pipe_config->dpll_hw_state)); | |
8054 | } | |
8055 | ||
26804afd DV |
8056 | /* |
8057 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
8058 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
8059 | * the PCH transcoder is on. | |
8060 | */ | |
ca370455 DL |
8061 | if (INTEL_INFO(dev)->gen < 9 && |
8062 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
8063 | pipe_config->has_pch_encoder = true; |
8064 | ||
8065 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
8066 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
8067 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
8068 | ||
8069 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
8070 | } | |
8071 | } | |
8072 | ||
0e8ffe1b DV |
8073 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
8074 | struct intel_crtc_config *pipe_config) | |
8075 | { | |
8076 | struct drm_device *dev = crtc->base.dev; | |
8077 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 8078 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
8079 | uint32_t tmp; |
8080 | ||
f458ebbc | 8081 | if (!intel_display_power_is_enabled(dev_priv, |
b5482bd0 ID |
8082 | POWER_DOMAIN_PIPE(crtc->pipe))) |
8083 | return false; | |
8084 | ||
e143a21c | 8085 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
8086 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
8087 | ||
eccb140b DV |
8088 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
8089 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
8090 | enum pipe trans_edp_pipe; | |
8091 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
8092 | default: | |
8093 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
8094 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
8095 | case TRANS_DDI_EDP_INPUT_A_ON: | |
8096 | trans_edp_pipe = PIPE_A; | |
8097 | break; | |
8098 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
8099 | trans_edp_pipe = PIPE_B; | |
8100 | break; | |
8101 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
8102 | trans_edp_pipe = PIPE_C; | |
8103 | break; | |
8104 | } | |
8105 | ||
8106 | if (trans_edp_pipe == crtc->pipe) | |
8107 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
8108 | } | |
8109 | ||
f458ebbc | 8110 | if (!intel_display_power_is_enabled(dev_priv, |
eccb140b | 8111 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
8112 | return false; |
8113 | ||
eccb140b | 8114 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
8115 | if (!(tmp & PIPECONF_ENABLE)) |
8116 | return false; | |
8117 | ||
26804afd | 8118 | haswell_get_ddi_port_state(crtc, pipe_config); |
627eb5a3 | 8119 | |
1bd1bd80 DV |
8120 | intel_get_pipe_timings(crtc, pipe_config); |
8121 | ||
2fa2fe9a | 8122 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
bd2e244f JB |
8123 | if (intel_display_power_is_enabled(dev_priv, pfit_domain)) { |
8124 | if (IS_SKYLAKE(dev)) | |
8125 | skylake_get_pfit_config(crtc, pipe_config); | |
8126 | else | |
8127 | ironlake_get_pfit_config(crtc, pipe_config); | |
8128 | } | |
88adfff1 | 8129 | |
e59150dc JB |
8130 | if (IS_HASWELL(dev)) |
8131 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
8132 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 8133 | |
ebb69c95 CT |
8134 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP) { |
8135 | pipe_config->pixel_multiplier = | |
8136 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
8137 | } else { | |
8138 | pipe_config->pixel_multiplier = 1; | |
8139 | } | |
6c49f241 | 8140 | |
0e8ffe1b DV |
8141 | return true; |
8142 | } | |
8143 | ||
560b85bb CW |
8144 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
8145 | { | |
8146 | struct drm_device *dev = crtc->dev; | |
8147 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8148 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dc41c154 | 8149 | uint32_t cntl = 0, size = 0; |
560b85bb | 8150 | |
dc41c154 VS |
8151 | if (base) { |
8152 | unsigned int width = intel_crtc->cursor_width; | |
8153 | unsigned int height = intel_crtc->cursor_height; | |
8154 | unsigned int stride = roundup_pow_of_two(width) * 4; | |
8155 | ||
8156 | switch (stride) { | |
8157 | default: | |
8158 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
8159 | width, stride); | |
8160 | stride = 256; | |
8161 | /* fallthrough */ | |
8162 | case 256: | |
8163 | case 512: | |
8164 | case 1024: | |
8165 | case 2048: | |
8166 | break; | |
4b0e333e CW |
8167 | } |
8168 | ||
dc41c154 VS |
8169 | cntl |= CURSOR_ENABLE | |
8170 | CURSOR_GAMMA_ENABLE | | |
8171 | CURSOR_FORMAT_ARGB | | |
8172 | CURSOR_STRIDE(stride); | |
8173 | ||
8174 | size = (height << 12) | width; | |
4b0e333e | 8175 | } |
560b85bb | 8176 | |
dc41c154 VS |
8177 | if (intel_crtc->cursor_cntl != 0 && |
8178 | (intel_crtc->cursor_base != base || | |
8179 | intel_crtc->cursor_size != size || | |
8180 | intel_crtc->cursor_cntl != cntl)) { | |
8181 | /* On these chipsets we can only modify the base/size/stride | |
8182 | * whilst the cursor is disabled. | |
8183 | */ | |
8184 | I915_WRITE(_CURACNTR, 0); | |
4b0e333e | 8185 | POSTING_READ(_CURACNTR); |
dc41c154 | 8186 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 8187 | } |
560b85bb | 8188 | |
99d1f387 | 8189 | if (intel_crtc->cursor_base != base) { |
9db4a9c7 | 8190 | I915_WRITE(_CURABASE, base); |
99d1f387 VS |
8191 | intel_crtc->cursor_base = base; |
8192 | } | |
4726e0b0 | 8193 | |
dc41c154 VS |
8194 | if (intel_crtc->cursor_size != size) { |
8195 | I915_WRITE(CURSIZE, size); | |
8196 | intel_crtc->cursor_size = size; | |
4b0e333e | 8197 | } |
560b85bb | 8198 | |
4b0e333e | 8199 | if (intel_crtc->cursor_cntl != cntl) { |
4b0e333e CW |
8200 | I915_WRITE(_CURACNTR, cntl); |
8201 | POSTING_READ(_CURACNTR); | |
4b0e333e | 8202 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 8203 | } |
560b85bb CW |
8204 | } |
8205 | ||
560b85bb | 8206 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) |
65a21cd6 JB |
8207 | { |
8208 | struct drm_device *dev = crtc->dev; | |
8209 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8210 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8211 | int pipe = intel_crtc->pipe; | |
4b0e333e CW |
8212 | uint32_t cntl; |
8213 | ||
8214 | cntl = 0; | |
8215 | if (base) { | |
8216 | cntl = MCURSOR_GAMMA_ENABLE; | |
8217 | switch (intel_crtc->cursor_width) { | |
4726e0b0 SK |
8218 | case 64: |
8219 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
8220 | break; | |
8221 | case 128: | |
8222 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
8223 | break; | |
8224 | case 256: | |
8225 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
8226 | break; | |
8227 | default: | |
8228 | WARN_ON(1); | |
8229 | return; | |
65a21cd6 | 8230 | } |
4b0e333e | 8231 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 VS |
8232 | |
8233 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
8234 | cntl |= CURSOR_PIPE_CSC_ENABLE; | |
4b0e333e | 8235 | } |
65a21cd6 | 8236 | |
4398ad45 VS |
8237 | if (to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180)) |
8238 | cntl |= CURSOR_ROTATE_180; | |
8239 | ||
4b0e333e CW |
8240 | if (intel_crtc->cursor_cntl != cntl) { |
8241 | I915_WRITE(CURCNTR(pipe), cntl); | |
8242 | POSTING_READ(CURCNTR(pipe)); | |
8243 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 8244 | } |
4b0e333e | 8245 | |
65a21cd6 | 8246 | /* and commit changes on next vblank */ |
5efb3e28 VS |
8247 | I915_WRITE(CURBASE(pipe), base); |
8248 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
8249 | |
8250 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
8251 | } |
8252 | ||
cda4b7d3 | 8253 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
8254 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
8255 | bool on) | |
cda4b7d3 CW |
8256 | { |
8257 | struct drm_device *dev = crtc->dev; | |
8258 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8259 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8260 | int pipe = intel_crtc->pipe; | |
3d7d6510 MR |
8261 | int x = crtc->cursor_x; |
8262 | int y = crtc->cursor_y; | |
d6e4db15 | 8263 | u32 base = 0, pos = 0; |
cda4b7d3 | 8264 | |
d6e4db15 | 8265 | if (on) |
cda4b7d3 | 8266 | base = intel_crtc->cursor_addr; |
cda4b7d3 | 8267 | |
d6e4db15 VS |
8268 | if (x >= intel_crtc->config.pipe_src_w) |
8269 | base = 0; | |
8270 | ||
8271 | if (y >= intel_crtc->config.pipe_src_h) | |
cda4b7d3 CW |
8272 | base = 0; |
8273 | ||
8274 | if (x < 0) { | |
efc9064e | 8275 | if (x + intel_crtc->cursor_width <= 0) |
cda4b7d3 CW |
8276 | base = 0; |
8277 | ||
8278 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
8279 | x = -x; | |
8280 | } | |
8281 | pos |= x << CURSOR_X_SHIFT; | |
8282 | ||
8283 | if (y < 0) { | |
efc9064e | 8284 | if (y + intel_crtc->cursor_height <= 0) |
cda4b7d3 CW |
8285 | base = 0; |
8286 | ||
8287 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
8288 | y = -y; | |
8289 | } | |
8290 | pos |= y << CURSOR_Y_SHIFT; | |
8291 | ||
4b0e333e | 8292 | if (base == 0 && intel_crtc->cursor_base == 0) |
cda4b7d3 CW |
8293 | return; |
8294 | ||
5efb3e28 VS |
8295 | I915_WRITE(CURPOS(pipe), pos); |
8296 | ||
4398ad45 VS |
8297 | /* ILK+ do this automagically */ |
8298 | if (HAS_GMCH_DISPLAY(dev) && | |
8299 | to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180)) { | |
8300 | base += (intel_crtc->cursor_height * | |
8301 | intel_crtc->cursor_width - 1) * 4; | |
8302 | } | |
8303 | ||
8ac54669 | 8304 | if (IS_845G(dev) || IS_I865G(dev)) |
5efb3e28 VS |
8305 | i845_update_cursor(crtc, base); |
8306 | else | |
8307 | i9xx_update_cursor(crtc, base); | |
cda4b7d3 CW |
8308 | } |
8309 | ||
dc41c154 VS |
8310 | static bool cursor_size_ok(struct drm_device *dev, |
8311 | uint32_t width, uint32_t height) | |
8312 | { | |
8313 | if (width == 0 || height == 0) | |
8314 | return false; | |
8315 | ||
8316 | /* | |
8317 | * 845g/865g are special in that they are only limited by | |
8318 | * the width of their cursors, the height is arbitrary up to | |
8319 | * the precision of the register. Everything else requires | |
8320 | * square cursors, limited to a few power-of-two sizes. | |
8321 | */ | |
8322 | if (IS_845G(dev) || IS_I865G(dev)) { | |
8323 | if ((width & 63) != 0) | |
8324 | return false; | |
8325 | ||
8326 | if (width > (IS_845G(dev) ? 64 : 512)) | |
8327 | return false; | |
8328 | ||
8329 | if (height > 1023) | |
8330 | return false; | |
8331 | } else { | |
8332 | switch (width | height) { | |
8333 | case 256: | |
8334 | case 128: | |
8335 | if (IS_GEN2(dev)) | |
8336 | return false; | |
8337 | case 64: | |
8338 | break; | |
8339 | default: | |
8340 | return false; | |
8341 | } | |
8342 | } | |
8343 | ||
8344 | return true; | |
8345 | } | |
8346 | ||
e3287951 MR |
8347 | static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc, |
8348 | struct drm_i915_gem_object *obj, | |
8349 | uint32_t width, uint32_t height) | |
79e53945 JB |
8350 | { |
8351 | struct drm_device *dev = crtc->dev; | |
5c6c6003 | 8352 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 8353 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
a071fa00 | 8354 | enum pipe pipe = intel_crtc->pipe; |
757f9a3e | 8355 | unsigned old_width; |
cda4b7d3 | 8356 | uint32_t addr; |
3f8bc370 | 8357 | int ret; |
79e53945 | 8358 | |
79e53945 | 8359 | /* if we want to turn off the cursor ignore width and height */ |
e3287951 | 8360 | if (!obj) { |
28c97730 | 8361 | DRM_DEBUG_KMS("cursor off\n"); |
3f8bc370 | 8362 | addr = 0; |
5004417d | 8363 | mutex_lock(&dev->struct_mutex); |
3f8bc370 | 8364 | goto finish; |
79e53945 JB |
8365 | } |
8366 | ||
71acb5eb | 8367 | /* we only need to pin inside GTT if cursor is non-phy */ |
7f9872e0 | 8368 | mutex_lock(&dev->struct_mutex); |
3d13ef2e | 8369 | if (!INTEL_INFO(dev)->cursor_needs_physical) { |
693db184 CW |
8370 | unsigned alignment; |
8371 | ||
d6dd6843 PZ |
8372 | /* |
8373 | * Global gtt pte registers are special registers which actually | |
8374 | * forward writes to a chunk of system memory. Which means that | |
8375 | * there is no risk that the register values disappear as soon | |
8376 | * as we call intel_runtime_pm_put(), so it is correct to wrap | |
8377 | * only the pin/unpin/fence and not more. | |
8378 | */ | |
8379 | intel_runtime_pm_get(dev_priv); | |
8380 | ||
693db184 CW |
8381 | /* Note that the w/a also requires 2 PTE of padding following |
8382 | * the bo. We currently fill all unused PTE with the shadow | |
8383 | * page and so we should always have valid PTE following the | |
8384 | * cursor preventing the VT-d warning. | |
8385 | */ | |
8386 | alignment = 0; | |
8387 | if (need_vtd_wa(dev)) | |
8388 | alignment = 64*1024; | |
8389 | ||
8390 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL); | |
e7b526bb | 8391 | if (ret) { |
3b25b31f | 8392 | DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n"); |
d6dd6843 | 8393 | intel_runtime_pm_put(dev_priv); |
2da3b9b9 | 8394 | goto fail_locked; |
e7b526bb CW |
8395 | } |
8396 | ||
d9e86c0e CW |
8397 | ret = i915_gem_object_put_fence(obj); |
8398 | if (ret) { | |
3b25b31f | 8399 | DRM_DEBUG_KMS("failed to release fence for cursor"); |
d6dd6843 | 8400 | intel_runtime_pm_put(dev_priv); |
d9e86c0e CW |
8401 | goto fail_unpin; |
8402 | } | |
8403 | ||
f343c5f6 | 8404 | addr = i915_gem_obj_ggtt_offset(obj); |
d6dd6843 PZ |
8405 | |
8406 | intel_runtime_pm_put(dev_priv); | |
71acb5eb | 8407 | } else { |
6eeefaf3 | 8408 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
00731155 | 8409 | ret = i915_gem_object_attach_phys(obj, align); |
71acb5eb | 8410 | if (ret) { |
3b25b31f | 8411 | DRM_DEBUG_KMS("failed to attach phys object\n"); |
7f9872e0 | 8412 | goto fail_locked; |
71acb5eb | 8413 | } |
00731155 | 8414 | addr = obj->phys_handle->busaddr; |
3f8bc370 KH |
8415 | } |
8416 | ||
3f8bc370 | 8417 | finish: |
3f8bc370 | 8418 | if (intel_crtc->cursor_bo) { |
00731155 | 8419 | if (!INTEL_INFO(dev)->cursor_needs_physical) |
cc98b413 | 8420 | i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo); |
3f8bc370 | 8421 | } |
80824003 | 8422 | |
a071fa00 DV |
8423 | i915_gem_track_fb(intel_crtc->cursor_bo, obj, |
8424 | INTEL_FRONTBUFFER_CURSOR(pipe)); | |
7f9872e0 | 8425 | mutex_unlock(&dev->struct_mutex); |
3f8bc370 | 8426 | |
64f962e3 CW |
8427 | old_width = intel_crtc->cursor_width; |
8428 | ||
3f8bc370 | 8429 | intel_crtc->cursor_addr = addr; |
05394f39 | 8430 | intel_crtc->cursor_bo = obj; |
cda4b7d3 CW |
8431 | intel_crtc->cursor_width = width; |
8432 | intel_crtc->cursor_height = height; | |
8433 | ||
64f962e3 CW |
8434 | if (intel_crtc->active) { |
8435 | if (old_width != width) | |
8436 | intel_update_watermarks(crtc); | |
f2f5f771 | 8437 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); |
3f8bc370 | 8438 | |
3f20df98 GP |
8439 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe)); |
8440 | } | |
f99d7069 | 8441 | |
79e53945 | 8442 | return 0; |
e7b526bb | 8443 | fail_unpin: |
cc98b413 | 8444 | i915_gem_object_unpin_from_display_plane(obj); |
7f9872e0 | 8445 | fail_locked: |
34b8686e DA |
8446 | mutex_unlock(&dev->struct_mutex); |
8447 | return ret; | |
79e53945 JB |
8448 | } |
8449 | ||
79e53945 | 8450 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 8451 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 8452 | { |
7203425a | 8453 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 8454 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 8455 | |
7203425a | 8456 | for (i = start; i < end; i++) { |
79e53945 JB |
8457 | intel_crtc->lut_r[i] = red[i] >> 8; |
8458 | intel_crtc->lut_g[i] = green[i] >> 8; | |
8459 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
8460 | } | |
8461 | ||
8462 | intel_crtc_load_lut(crtc); | |
8463 | } | |
8464 | ||
79e53945 JB |
8465 | /* VESA 640x480x72Hz mode to set on the pipe */ |
8466 | static struct drm_display_mode load_detect_mode = { | |
8467 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
8468 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
8469 | }; | |
8470 | ||
a8bb6818 DV |
8471 | struct drm_framebuffer * |
8472 | __intel_framebuffer_create(struct drm_device *dev, | |
8473 | struct drm_mode_fb_cmd2 *mode_cmd, | |
8474 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
8475 | { |
8476 | struct intel_framebuffer *intel_fb; | |
8477 | int ret; | |
8478 | ||
8479 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
8480 | if (!intel_fb) { | |
6ccb81f2 | 8481 | drm_gem_object_unreference(&obj->base); |
d2dff872 CW |
8482 | return ERR_PTR(-ENOMEM); |
8483 | } | |
8484 | ||
8485 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
8486 | if (ret) |
8487 | goto err; | |
d2dff872 CW |
8488 | |
8489 | return &intel_fb->base; | |
dd4916c5 | 8490 | err: |
6ccb81f2 | 8491 | drm_gem_object_unreference(&obj->base); |
dd4916c5 DV |
8492 | kfree(intel_fb); |
8493 | ||
8494 | return ERR_PTR(ret); | |
d2dff872 CW |
8495 | } |
8496 | ||
b5ea642a | 8497 | static struct drm_framebuffer * |
a8bb6818 DV |
8498 | intel_framebuffer_create(struct drm_device *dev, |
8499 | struct drm_mode_fb_cmd2 *mode_cmd, | |
8500 | struct drm_i915_gem_object *obj) | |
8501 | { | |
8502 | struct drm_framebuffer *fb; | |
8503 | int ret; | |
8504 | ||
8505 | ret = i915_mutex_lock_interruptible(dev); | |
8506 | if (ret) | |
8507 | return ERR_PTR(ret); | |
8508 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
8509 | mutex_unlock(&dev->struct_mutex); | |
8510 | ||
8511 | return fb; | |
8512 | } | |
8513 | ||
d2dff872 CW |
8514 | static u32 |
8515 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
8516 | { | |
8517 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
8518 | return ALIGN(pitch, 64); | |
8519 | } | |
8520 | ||
8521 | static u32 | |
8522 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
8523 | { | |
8524 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 8525 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
8526 | } |
8527 | ||
8528 | static struct drm_framebuffer * | |
8529 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
8530 | struct drm_display_mode *mode, | |
8531 | int depth, int bpp) | |
8532 | { | |
8533 | struct drm_i915_gem_object *obj; | |
0fed39bd | 8534 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
8535 | |
8536 | obj = i915_gem_alloc_object(dev, | |
8537 | intel_framebuffer_size_for_mode(mode, bpp)); | |
8538 | if (obj == NULL) | |
8539 | return ERR_PTR(-ENOMEM); | |
8540 | ||
8541 | mode_cmd.width = mode->hdisplay; | |
8542 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
8543 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
8544 | bpp); | |
5ca0c34a | 8545 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
8546 | |
8547 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
8548 | } | |
8549 | ||
8550 | static struct drm_framebuffer * | |
8551 | mode_fits_in_fbdev(struct drm_device *dev, | |
8552 | struct drm_display_mode *mode) | |
8553 | { | |
4520f53a | 8554 | #ifdef CONFIG_DRM_I915_FBDEV |
d2dff872 CW |
8555 | struct drm_i915_private *dev_priv = dev->dev_private; |
8556 | struct drm_i915_gem_object *obj; | |
8557 | struct drm_framebuffer *fb; | |
8558 | ||
4c0e5528 | 8559 | if (!dev_priv->fbdev) |
d2dff872 CW |
8560 | return NULL; |
8561 | ||
4c0e5528 | 8562 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
8563 | return NULL; |
8564 | ||
4c0e5528 DV |
8565 | obj = dev_priv->fbdev->fb->obj; |
8566 | BUG_ON(!obj); | |
8567 | ||
8bcd4553 | 8568 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
8569 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
8570 | fb->bits_per_pixel)) | |
d2dff872 CW |
8571 | return NULL; |
8572 | ||
01f2c773 | 8573 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
8574 | return NULL; |
8575 | ||
8576 | return fb; | |
4520f53a DV |
8577 | #else |
8578 | return NULL; | |
8579 | #endif | |
d2dff872 CW |
8580 | } |
8581 | ||
d2434ab7 | 8582 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 8583 | struct drm_display_mode *mode, |
51fd371b RC |
8584 | struct intel_load_detect_pipe *old, |
8585 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
8586 | { |
8587 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
8588 | struct intel_encoder *intel_encoder = |
8589 | intel_attached_encoder(connector); | |
79e53945 | 8590 | struct drm_crtc *possible_crtc; |
4ef69c7a | 8591 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
8592 | struct drm_crtc *crtc = NULL; |
8593 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 8594 | struct drm_framebuffer *fb; |
51fd371b RC |
8595 | struct drm_mode_config *config = &dev->mode_config; |
8596 | int ret, i = -1; | |
79e53945 | 8597 | |
d2dff872 | 8598 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 8599 | connector->base.id, connector->name, |
8e329a03 | 8600 | encoder->base.id, encoder->name); |
d2dff872 | 8601 | |
51fd371b RC |
8602 | retry: |
8603 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
8604 | if (ret) | |
8605 | goto fail_unlock; | |
6e9f798d | 8606 | |
79e53945 JB |
8607 | /* |
8608 | * Algorithm gets a little messy: | |
7a5e4805 | 8609 | * |
79e53945 JB |
8610 | * - if the connector already has an assigned crtc, use it (but make |
8611 | * sure it's on first) | |
7a5e4805 | 8612 | * |
79e53945 JB |
8613 | * - try to find the first unused crtc that can drive this connector, |
8614 | * and use that if we find one | |
79e53945 JB |
8615 | */ |
8616 | ||
8617 | /* See if we already have a CRTC for this connector */ | |
8618 | if (encoder->crtc) { | |
8619 | crtc = encoder->crtc; | |
8261b191 | 8620 | |
51fd371b | 8621 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de DV |
8622 | if (ret) |
8623 | goto fail_unlock; | |
8624 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); | |
51fd371b RC |
8625 | if (ret) |
8626 | goto fail_unlock; | |
7b24056b | 8627 | |
24218aac | 8628 | old->dpms_mode = connector->dpms; |
8261b191 CW |
8629 | old->load_detect_temp = false; |
8630 | ||
8631 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
8632 | if (connector->dpms != DRM_MODE_DPMS_ON) |
8633 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 8634 | |
7173188d | 8635 | return true; |
79e53945 JB |
8636 | } |
8637 | ||
8638 | /* Find an unused one (if possible) */ | |
70e1e0ec | 8639 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
8640 | i++; |
8641 | if (!(encoder->possible_crtcs & (1 << i))) | |
8642 | continue; | |
a459249c VS |
8643 | if (possible_crtc->enabled) |
8644 | continue; | |
8645 | /* This can occur when applying the pipe A quirk on resume. */ | |
8646 | if (to_intel_crtc(possible_crtc)->new_enabled) | |
8647 | continue; | |
8648 | ||
8649 | crtc = possible_crtc; | |
8650 | break; | |
79e53945 JB |
8651 | } |
8652 | ||
8653 | /* | |
8654 | * If we didn't find an unused CRTC, don't use any. | |
8655 | */ | |
8656 | if (!crtc) { | |
7173188d | 8657 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
51fd371b | 8658 | goto fail_unlock; |
79e53945 JB |
8659 | } |
8660 | ||
51fd371b RC |
8661 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
8662 | if (ret) | |
4d02e2de DV |
8663 | goto fail_unlock; |
8664 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); | |
8665 | if (ret) | |
51fd371b | 8666 | goto fail_unlock; |
fc303101 DV |
8667 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
8668 | to_intel_connector(connector)->new_encoder = intel_encoder; | |
79e53945 JB |
8669 | |
8670 | intel_crtc = to_intel_crtc(crtc); | |
412b61d8 VS |
8671 | intel_crtc->new_enabled = true; |
8672 | intel_crtc->new_config = &intel_crtc->config; | |
24218aac | 8673 | old->dpms_mode = connector->dpms; |
8261b191 | 8674 | old->load_detect_temp = true; |
d2dff872 | 8675 | old->release_fb = NULL; |
79e53945 | 8676 | |
6492711d CW |
8677 | if (!mode) |
8678 | mode = &load_detect_mode; | |
79e53945 | 8679 | |
d2dff872 CW |
8680 | /* We need a framebuffer large enough to accommodate all accesses |
8681 | * that the plane may generate whilst we perform load detection. | |
8682 | * We can not rely on the fbcon either being present (we get called | |
8683 | * during its initialisation to detect all boot displays, or it may | |
8684 | * not even exist) or that it is large enough to satisfy the | |
8685 | * requested mode. | |
8686 | */ | |
94352cf9 DV |
8687 | fb = mode_fits_in_fbdev(dev, mode); |
8688 | if (fb == NULL) { | |
d2dff872 | 8689 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
8690 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
8691 | old->release_fb = fb; | |
d2dff872 CW |
8692 | } else |
8693 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 8694 | if (IS_ERR(fb)) { |
d2dff872 | 8695 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 8696 | goto fail; |
79e53945 | 8697 | } |
79e53945 | 8698 | |
c0c36b94 | 8699 | if (intel_set_mode(crtc, mode, 0, 0, fb)) { |
6492711d | 8700 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
8701 | if (old->release_fb) |
8702 | old->release_fb->funcs->destroy(old->release_fb); | |
412b61d8 | 8703 | goto fail; |
79e53945 | 8704 | } |
7173188d | 8705 | |
79e53945 | 8706 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 8707 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 8708 | return true; |
412b61d8 VS |
8709 | |
8710 | fail: | |
8711 | intel_crtc->new_enabled = crtc->enabled; | |
8712 | if (intel_crtc->new_enabled) | |
8713 | intel_crtc->new_config = &intel_crtc->config; | |
8714 | else | |
8715 | intel_crtc->new_config = NULL; | |
51fd371b RC |
8716 | fail_unlock: |
8717 | if (ret == -EDEADLK) { | |
8718 | drm_modeset_backoff(ctx); | |
8719 | goto retry; | |
8720 | } | |
8721 | ||
412b61d8 | 8722 | return false; |
79e53945 JB |
8723 | } |
8724 | ||
d2434ab7 | 8725 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
208bf9fd | 8726 | struct intel_load_detect_pipe *old) |
79e53945 | 8727 | { |
d2434ab7 DV |
8728 | struct intel_encoder *intel_encoder = |
8729 | intel_attached_encoder(connector); | |
4ef69c7a | 8730 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 8731 | struct drm_crtc *crtc = encoder->crtc; |
412b61d8 | 8732 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 8733 | |
d2dff872 | 8734 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 8735 | connector->base.id, connector->name, |
8e329a03 | 8736 | encoder->base.id, encoder->name); |
d2dff872 | 8737 | |
8261b191 | 8738 | if (old->load_detect_temp) { |
fc303101 DV |
8739 | to_intel_connector(connector)->new_encoder = NULL; |
8740 | intel_encoder->new_crtc = NULL; | |
412b61d8 VS |
8741 | intel_crtc->new_enabled = false; |
8742 | intel_crtc->new_config = NULL; | |
fc303101 | 8743 | intel_set_mode(crtc, NULL, 0, 0, NULL); |
d2dff872 | 8744 | |
36206361 DV |
8745 | if (old->release_fb) { |
8746 | drm_framebuffer_unregister_private(old->release_fb); | |
8747 | drm_framebuffer_unreference(old->release_fb); | |
8748 | } | |
d2dff872 | 8749 | |
0622a53c | 8750 | return; |
79e53945 JB |
8751 | } |
8752 | ||
c751ce4f | 8753 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
8754 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
8755 | connector->funcs->dpms(connector, old->dpms_mode); | |
79e53945 JB |
8756 | } |
8757 | ||
da4a1efa VS |
8758 | static int i9xx_pll_refclk(struct drm_device *dev, |
8759 | const struct intel_crtc_config *pipe_config) | |
8760 | { | |
8761 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8762 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
8763 | ||
8764 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 8765 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
8766 | else if (HAS_PCH_SPLIT(dev)) |
8767 | return 120000; | |
8768 | else if (!IS_GEN2(dev)) | |
8769 | return 96000; | |
8770 | else | |
8771 | return 48000; | |
8772 | } | |
8773 | ||
79e53945 | 8774 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc JB |
8775 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
8776 | struct intel_crtc_config *pipe_config) | |
79e53945 | 8777 | { |
f1f644dc | 8778 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 8779 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 8780 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 8781 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
8782 | u32 fp; |
8783 | intel_clock_t clock; | |
da4a1efa | 8784 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
8785 | |
8786 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 8787 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 8788 | else |
293623f7 | 8789 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
8790 | |
8791 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
8792 | if (IS_PINEVIEW(dev)) { |
8793 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
8794 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
8795 | } else { |
8796 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
8797 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
8798 | } | |
8799 | ||
a6c45cf0 | 8800 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
8801 | if (IS_PINEVIEW(dev)) |
8802 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
8803 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
8804 | else |
8805 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
8806 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
8807 | ||
8808 | switch (dpll & DPLL_MODE_MASK) { | |
8809 | case DPLLB_MODE_DAC_SERIAL: | |
8810 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
8811 | 5 : 10; | |
8812 | break; | |
8813 | case DPLLB_MODE_LVDS: | |
8814 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
8815 | 7 : 14; | |
8816 | break; | |
8817 | default: | |
28c97730 | 8818 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 8819 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 8820 | return; |
79e53945 JB |
8821 | } |
8822 | ||
ac58c3f0 | 8823 | if (IS_PINEVIEW(dev)) |
da4a1efa | 8824 | pineview_clock(refclk, &clock); |
ac58c3f0 | 8825 | else |
da4a1efa | 8826 | i9xx_clock(refclk, &clock); |
79e53945 | 8827 | } else { |
0fb58223 | 8828 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 8829 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
8830 | |
8831 | if (is_lvds) { | |
8832 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
8833 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
8834 | |
8835 | if (lvds & LVDS_CLKB_POWER_UP) | |
8836 | clock.p2 = 7; | |
8837 | else | |
8838 | clock.p2 = 14; | |
79e53945 JB |
8839 | } else { |
8840 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
8841 | clock.p1 = 2; | |
8842 | else { | |
8843 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
8844 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
8845 | } | |
8846 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
8847 | clock.p2 = 4; | |
8848 | else | |
8849 | clock.p2 = 2; | |
79e53945 | 8850 | } |
da4a1efa VS |
8851 | |
8852 | i9xx_clock(refclk, &clock); | |
79e53945 JB |
8853 | } |
8854 | ||
18442d08 VS |
8855 | /* |
8856 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 8857 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
8858 | * encoder's get_config() function. |
8859 | */ | |
8860 | pipe_config->port_clock = clock.dot; | |
f1f644dc JB |
8861 | } |
8862 | ||
6878da05 VS |
8863 | int intel_dotclock_calculate(int link_freq, |
8864 | const struct intel_link_m_n *m_n) | |
f1f644dc | 8865 | { |
f1f644dc JB |
8866 | /* |
8867 | * The calculation for the data clock is: | |
1041a02f | 8868 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 8869 | * But we want to avoid losing precison if possible, so: |
1041a02f | 8870 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
8871 | * |
8872 | * and the link clock is simpler: | |
1041a02f | 8873 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
8874 | */ |
8875 | ||
6878da05 VS |
8876 | if (!m_n->link_n) |
8877 | return 0; | |
f1f644dc | 8878 | |
6878da05 VS |
8879 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
8880 | } | |
f1f644dc | 8881 | |
18442d08 VS |
8882 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
8883 | struct intel_crtc_config *pipe_config) | |
6878da05 VS |
8884 | { |
8885 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 8886 | |
18442d08 VS |
8887 | /* read out port_clock from the DPLL */ |
8888 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 8889 | |
f1f644dc | 8890 | /* |
18442d08 | 8891 | * This value does not include pixel_multiplier. |
241bfc38 | 8892 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
8893 | * agree once we know their relationship in the encoder's |
8894 | * get_config() function. | |
79e53945 | 8895 | */ |
241bfc38 | 8896 | pipe_config->adjusted_mode.crtc_clock = |
18442d08 VS |
8897 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
8898 | &pipe_config->fdi_m_n); | |
79e53945 JB |
8899 | } |
8900 | ||
8901 | /** Returns the currently programmed mode of the given pipe. */ | |
8902 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
8903 | struct drm_crtc *crtc) | |
8904 | { | |
548f245b | 8905 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 8906 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3b117c8f | 8907 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
79e53945 | 8908 | struct drm_display_mode *mode; |
f1f644dc | 8909 | struct intel_crtc_config pipe_config; |
fe2b8f9d PZ |
8910 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
8911 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
8912 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
8913 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 8914 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
8915 | |
8916 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
8917 | if (!mode) | |
8918 | return NULL; | |
8919 | ||
f1f644dc JB |
8920 | /* |
8921 | * Construct a pipe_config sufficient for getting the clock info | |
8922 | * back out of crtc_clock_get. | |
8923 | * | |
8924 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
8925 | * to use a real value here instead. | |
8926 | */ | |
293623f7 | 8927 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 8928 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
8929 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
8930 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
8931 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
8932 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
8933 | ||
773ae034 | 8934 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
79e53945 JB |
8935 | mode->hdisplay = (htot & 0xffff) + 1; |
8936 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
8937 | mode->hsync_start = (hsync & 0xffff) + 1; | |
8938 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
8939 | mode->vdisplay = (vtot & 0xffff) + 1; | |
8940 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
8941 | mode->vsync_start = (vsync & 0xffff) + 1; | |
8942 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
8943 | ||
8944 | drm_mode_set_name(mode); | |
79e53945 JB |
8945 | |
8946 | return mode; | |
8947 | } | |
8948 | ||
652c393a JB |
8949 | static void intel_decrease_pllclock(struct drm_crtc *crtc) |
8950 | { | |
8951 | struct drm_device *dev = crtc->dev; | |
fbee40df | 8952 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 8953 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
652c393a | 8954 | |
baff296c | 8955 | if (!HAS_GMCH_DISPLAY(dev)) |
652c393a JB |
8956 | return; |
8957 | ||
8958 | if (!dev_priv->lvds_downclock_avail) | |
8959 | return; | |
8960 | ||
8961 | /* | |
8962 | * Since this is called by a timer, we should never get here in | |
8963 | * the manual case. | |
8964 | */ | |
8965 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
dc257cf1 DV |
8966 | int pipe = intel_crtc->pipe; |
8967 | int dpll_reg = DPLL(pipe); | |
8968 | int dpll; | |
f6e5b160 | 8969 | |
44d98a61 | 8970 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 8971 | |
8ac5a6d5 | 8972 | assert_panel_unlocked(dev_priv, pipe); |
652c393a | 8973 | |
dc257cf1 | 8974 | dpll = I915_READ(dpll_reg); |
652c393a JB |
8975 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
8976 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 8977 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
8978 | dpll = I915_READ(dpll_reg); |
8979 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 8980 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
8981 | } |
8982 | ||
8983 | } | |
8984 | ||
f047e395 CW |
8985 | void intel_mark_busy(struct drm_device *dev) |
8986 | { | |
c67a470b PZ |
8987 | struct drm_i915_private *dev_priv = dev->dev_private; |
8988 | ||
f62a0076 CW |
8989 | if (dev_priv->mm.busy) |
8990 | return; | |
8991 | ||
43694d69 | 8992 | intel_runtime_pm_get(dev_priv); |
c67a470b | 8993 | i915_update_gfx_val(dev_priv); |
f62a0076 | 8994 | dev_priv->mm.busy = true; |
f047e395 CW |
8995 | } |
8996 | ||
8997 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 8998 | { |
c67a470b | 8999 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 9000 | struct drm_crtc *crtc; |
652c393a | 9001 | |
f62a0076 CW |
9002 | if (!dev_priv->mm.busy) |
9003 | return; | |
9004 | ||
9005 | dev_priv->mm.busy = false; | |
9006 | ||
d330a953 | 9007 | if (!i915.powersave) |
bb4cdd53 | 9008 | goto out; |
652c393a | 9009 | |
70e1e0ec | 9010 | for_each_crtc(dev, crtc) { |
f4510a27 | 9011 | if (!crtc->primary->fb) |
652c393a JB |
9012 | continue; |
9013 | ||
725a5b54 | 9014 | intel_decrease_pllclock(crtc); |
652c393a | 9015 | } |
b29c19b6 | 9016 | |
3d13ef2e | 9017 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 9018 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 PZ |
9019 | |
9020 | out: | |
43694d69 | 9021 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
9022 | } |
9023 | ||
79e53945 JB |
9024 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
9025 | { | |
9026 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
9027 | struct drm_device *dev = crtc->dev; |
9028 | struct intel_unpin_work *work; | |
67e77c5a | 9029 | |
5e2d7afc | 9030 | spin_lock_irq(&dev->event_lock); |
67e77c5a DV |
9031 | work = intel_crtc->unpin_work; |
9032 | intel_crtc->unpin_work = NULL; | |
5e2d7afc | 9033 | spin_unlock_irq(&dev->event_lock); |
67e77c5a DV |
9034 | |
9035 | if (work) { | |
9036 | cancel_work_sync(&work->work); | |
9037 | kfree(work); | |
9038 | } | |
79e53945 JB |
9039 | |
9040 | drm_crtc_cleanup(crtc); | |
67e77c5a | 9041 | |
79e53945 JB |
9042 | kfree(intel_crtc); |
9043 | } | |
9044 | ||
6b95a207 KH |
9045 | static void intel_unpin_work_fn(struct work_struct *__work) |
9046 | { | |
9047 | struct intel_unpin_work *work = | |
9048 | container_of(__work, struct intel_unpin_work, work); | |
b4a98e57 | 9049 | struct drm_device *dev = work->crtc->dev; |
f99d7069 | 9050 | enum pipe pipe = to_intel_crtc(work->crtc)->pipe; |
6b95a207 | 9051 | |
b4a98e57 | 9052 | mutex_lock(&dev->struct_mutex); |
1690e1eb | 9053 | intel_unpin_fb_obj(work->old_fb_obj); |
05394f39 CW |
9054 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
9055 | drm_gem_object_unreference(&work->old_fb_obj->base); | |
d9e86c0e | 9056 | |
b4a98e57 CW |
9057 | intel_update_fbc(dev); |
9058 | mutex_unlock(&dev->struct_mutex); | |
9059 | ||
f99d7069 DV |
9060 | intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
9061 | ||
b4a98e57 CW |
9062 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); |
9063 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); | |
9064 | ||
6b95a207 KH |
9065 | kfree(work); |
9066 | } | |
9067 | ||
1afe3e9d | 9068 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 9069 | struct drm_crtc *crtc) |
6b95a207 | 9070 | { |
6b95a207 KH |
9071 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
9072 | struct intel_unpin_work *work; | |
6b95a207 KH |
9073 | unsigned long flags; |
9074 | ||
9075 | /* Ignore early vblank irqs */ | |
9076 | if (intel_crtc == NULL) | |
9077 | return; | |
9078 | ||
f326038a DV |
9079 | /* |
9080 | * This is called both by irq handlers and the reset code (to complete | |
9081 | * lost pageflips) so needs the full irqsave spinlocks. | |
9082 | */ | |
6b95a207 KH |
9083 | spin_lock_irqsave(&dev->event_lock, flags); |
9084 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
9085 | |
9086 | /* Ensure we don't miss a work->pending update ... */ | |
9087 | smp_rmb(); | |
9088 | ||
9089 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
9090 | spin_unlock_irqrestore(&dev->event_lock, flags); |
9091 | return; | |
9092 | } | |
9093 | ||
d6bbafa1 | 9094 | page_flip_completed(intel_crtc); |
0af7e4df | 9095 | |
6b95a207 | 9096 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6b95a207 KH |
9097 | } |
9098 | ||
1afe3e9d JB |
9099 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
9100 | { | |
fbee40df | 9101 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
9102 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
9103 | ||
49b14a5c | 9104 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
9105 | } |
9106 | ||
9107 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
9108 | { | |
fbee40df | 9109 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
9110 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
9111 | ||
49b14a5c | 9112 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
9113 | } |
9114 | ||
75f7f3ec VS |
9115 | /* Is 'a' after or equal to 'b'? */ |
9116 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
9117 | { | |
9118 | return !((a - b) & 0x80000000); | |
9119 | } | |
9120 | ||
9121 | static bool page_flip_finished(struct intel_crtc *crtc) | |
9122 | { | |
9123 | struct drm_device *dev = crtc->base.dev; | |
9124 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9125 | ||
bdfa7542 VS |
9126 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
9127 | crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
9128 | return true; | |
9129 | ||
75f7f3ec VS |
9130 | /* |
9131 | * The relevant registers doen't exist on pre-ctg. | |
9132 | * As the flip done interrupt doesn't trigger for mmio | |
9133 | * flips on gmch platforms, a flip count check isn't | |
9134 | * really needed there. But since ctg has the registers, | |
9135 | * include it in the check anyway. | |
9136 | */ | |
9137 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
9138 | return true; | |
9139 | ||
9140 | /* | |
9141 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
9142 | * used the same base address. In that case the mmio flip might | |
9143 | * have completed, but the CS hasn't even executed the flip yet. | |
9144 | * | |
9145 | * A flip count check isn't enough as the CS might have updated | |
9146 | * the base address just after start of vblank, but before we | |
9147 | * managed to process the interrupt. This means we'd complete the | |
9148 | * CS flip too soon. | |
9149 | * | |
9150 | * Combining both checks should get us a good enough result. It may | |
9151 | * still happen that the CS flip has been executed, but has not | |
9152 | * yet actually completed. But in case the base address is the same | |
9153 | * anyway, we don't really care. | |
9154 | */ | |
9155 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
9156 | crtc->unpin_work->gtt_offset && | |
9157 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)), | |
9158 | crtc->unpin_work->flip_count); | |
9159 | } | |
9160 | ||
6b95a207 KH |
9161 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
9162 | { | |
fbee40df | 9163 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
9164 | struct intel_crtc *intel_crtc = |
9165 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
9166 | unsigned long flags; | |
9167 | ||
f326038a DV |
9168 | |
9169 | /* | |
9170 | * This is called both by irq handlers and the reset code (to complete | |
9171 | * lost pageflips) so needs the full irqsave spinlocks. | |
9172 | * | |
9173 | * NB: An MMIO update of the plane base pointer will also | |
e7d841ca CW |
9174 | * generate a page-flip completion irq, i.e. every modeset |
9175 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
9176 | */ | |
6b95a207 | 9177 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 9178 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 9179 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
9180 | spin_unlock_irqrestore(&dev->event_lock, flags); |
9181 | } | |
9182 | ||
eba905b2 | 9183 | static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
e7d841ca CW |
9184 | { |
9185 | /* Ensure that the work item is consistent when activating it ... */ | |
9186 | smp_wmb(); | |
9187 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); | |
9188 | /* and that it is marked active as soon as the irq could fire. */ | |
9189 | smp_wmb(); | |
9190 | } | |
9191 | ||
8c9f3aaf JB |
9192 | static int intel_gen2_queue_flip(struct drm_device *dev, |
9193 | struct drm_crtc *crtc, | |
9194 | struct drm_framebuffer *fb, | |
ed8d1975 | 9195 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9196 | struct intel_engine_cs *ring, |
ed8d1975 | 9197 | uint32_t flags) |
8c9f3aaf | 9198 | { |
8c9f3aaf | 9199 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
9200 | u32 flip_mask; |
9201 | int ret; | |
9202 | ||
6d90c952 | 9203 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 9204 | if (ret) |
4fa62c89 | 9205 | return ret; |
8c9f3aaf JB |
9206 | |
9207 | /* Can't queue multiple flips, so wait for the previous | |
9208 | * one to finish before executing the next. | |
9209 | */ | |
9210 | if (intel_crtc->plane) | |
9211 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
9212 | else | |
9213 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
9214 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
9215 | intel_ring_emit(ring, MI_NOOP); | |
9216 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
9217 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9218 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9219 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 | 9220 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca CW |
9221 | |
9222 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9223 | __intel_ring_advance(ring); |
83d4092b | 9224 | return 0; |
8c9f3aaf JB |
9225 | } |
9226 | ||
9227 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
9228 | struct drm_crtc *crtc, | |
9229 | struct drm_framebuffer *fb, | |
ed8d1975 | 9230 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9231 | struct intel_engine_cs *ring, |
ed8d1975 | 9232 | uint32_t flags) |
8c9f3aaf | 9233 | { |
8c9f3aaf | 9234 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
9235 | u32 flip_mask; |
9236 | int ret; | |
9237 | ||
6d90c952 | 9238 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 9239 | if (ret) |
4fa62c89 | 9240 | return ret; |
8c9f3aaf JB |
9241 | |
9242 | if (intel_crtc->plane) | |
9243 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
9244 | else | |
9245 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
9246 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
9247 | intel_ring_emit(ring, MI_NOOP); | |
9248 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
9249 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9250 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9251 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 DV |
9252 | intel_ring_emit(ring, MI_NOOP); |
9253 | ||
e7d841ca | 9254 | intel_mark_page_flip_active(intel_crtc); |
09246732 | 9255 | __intel_ring_advance(ring); |
83d4092b | 9256 | return 0; |
8c9f3aaf JB |
9257 | } |
9258 | ||
9259 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
9260 | struct drm_crtc *crtc, | |
9261 | struct drm_framebuffer *fb, | |
ed8d1975 | 9262 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9263 | struct intel_engine_cs *ring, |
ed8d1975 | 9264 | uint32_t flags) |
8c9f3aaf JB |
9265 | { |
9266 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9267 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9268 | uint32_t pf, pipesrc; | |
9269 | int ret; | |
9270 | ||
6d90c952 | 9271 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 9272 | if (ret) |
4fa62c89 | 9273 | return ret; |
8c9f3aaf JB |
9274 | |
9275 | /* i965+ uses the linear or tiled offsets from the | |
9276 | * Display Registers (which do not change across a page-flip) | |
9277 | * so we need only reprogram the base address. | |
9278 | */ | |
6d90c952 DV |
9279 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
9280 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9281 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9282 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | |
c2c75131 | 9283 | obj->tiling_mode); |
8c9f3aaf JB |
9284 | |
9285 | /* XXX Enabling the panel-fitter across page-flip is so far | |
9286 | * untested on non-native modes, so ignore it for now. | |
9287 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
9288 | */ | |
9289 | pf = 0; | |
9290 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 9291 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
9292 | |
9293 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9294 | __intel_ring_advance(ring); |
83d4092b | 9295 | return 0; |
8c9f3aaf JB |
9296 | } |
9297 | ||
9298 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
9299 | struct drm_crtc *crtc, | |
9300 | struct drm_framebuffer *fb, | |
ed8d1975 | 9301 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9302 | struct intel_engine_cs *ring, |
ed8d1975 | 9303 | uint32_t flags) |
8c9f3aaf JB |
9304 | { |
9305 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9306 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9307 | uint32_t pf, pipesrc; | |
9308 | int ret; | |
9309 | ||
6d90c952 | 9310 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 9311 | if (ret) |
4fa62c89 | 9312 | return ret; |
8c9f3aaf | 9313 | |
6d90c952 DV |
9314 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
9315 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9316 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
75f7f3ec | 9317 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8c9f3aaf | 9318 | |
dc257cf1 DV |
9319 | /* Contrary to the suggestions in the documentation, |
9320 | * "Enable Panel Fitter" does not seem to be required when page | |
9321 | * flipping with a non-native mode, and worse causes a normal | |
9322 | * modeset to fail. | |
9323 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
9324 | */ | |
9325 | pf = 0; | |
8c9f3aaf | 9326 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 9327 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
9328 | |
9329 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9330 | __intel_ring_advance(ring); |
83d4092b | 9331 | return 0; |
8c9f3aaf JB |
9332 | } |
9333 | ||
7c9017e5 JB |
9334 | static int intel_gen7_queue_flip(struct drm_device *dev, |
9335 | struct drm_crtc *crtc, | |
9336 | struct drm_framebuffer *fb, | |
ed8d1975 | 9337 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9338 | struct intel_engine_cs *ring, |
ed8d1975 | 9339 | uint32_t flags) |
7c9017e5 | 9340 | { |
7c9017e5 | 9341 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 9342 | uint32_t plane_bit = 0; |
ffe74d75 CW |
9343 | int len, ret; |
9344 | ||
eba905b2 | 9345 | switch (intel_crtc->plane) { |
cb05d8de DV |
9346 | case PLANE_A: |
9347 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
9348 | break; | |
9349 | case PLANE_B: | |
9350 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
9351 | break; | |
9352 | case PLANE_C: | |
9353 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
9354 | break; | |
9355 | default: | |
9356 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 9357 | return -ENODEV; |
cb05d8de DV |
9358 | } |
9359 | ||
ffe74d75 | 9360 | len = 4; |
f476828a | 9361 | if (ring->id == RCS) { |
ffe74d75 | 9362 | len += 6; |
f476828a DL |
9363 | /* |
9364 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
9365 | * 48bits addresses, and we need a NOOP for the batch size to | |
9366 | * stay even. | |
9367 | */ | |
9368 | if (IS_GEN8(dev)) | |
9369 | len += 2; | |
9370 | } | |
ffe74d75 | 9371 | |
f66fab8e VS |
9372 | /* |
9373 | * BSpec MI_DISPLAY_FLIP for IVB: | |
9374 | * "The full packet must be contained within the same cache line." | |
9375 | * | |
9376 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
9377 | * cacheline, if we ever start emitting more commands before | |
9378 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
9379 | * then do the cacheline alignment, and finally emit the | |
9380 | * MI_DISPLAY_FLIP. | |
9381 | */ | |
9382 | ret = intel_ring_cacheline_align(ring); | |
9383 | if (ret) | |
4fa62c89 | 9384 | return ret; |
f66fab8e | 9385 | |
ffe74d75 | 9386 | ret = intel_ring_begin(ring, len); |
7c9017e5 | 9387 | if (ret) |
4fa62c89 | 9388 | return ret; |
7c9017e5 | 9389 | |
ffe74d75 CW |
9390 | /* Unmask the flip-done completion message. Note that the bspec says that |
9391 | * we should do this for both the BCS and RCS, and that we must not unmask | |
9392 | * more than one flip event at any time (or ensure that one flip message | |
9393 | * can be sent by waiting for flip-done prior to queueing new flips). | |
9394 | * Experimentation says that BCS works despite DERRMR masking all | |
9395 | * flip-done completion events and that unmasking all planes at once | |
9396 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
9397 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
9398 | */ | |
9399 | if (ring->id == RCS) { | |
9400 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
9401 | intel_ring_emit(ring, DERRMR); | |
9402 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
9403 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
9404 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a DL |
9405 | if (IS_GEN8(dev)) |
9406 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) | | |
9407 | MI_SRM_LRM_GLOBAL_GTT); | |
9408 | else | |
9409 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | | |
9410 | MI_SRM_LRM_GLOBAL_GTT); | |
ffe74d75 CW |
9411 | intel_ring_emit(ring, DERRMR); |
9412 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
f476828a DL |
9413 | if (IS_GEN8(dev)) { |
9414 | intel_ring_emit(ring, 0); | |
9415 | intel_ring_emit(ring, MI_NOOP); | |
9416 | } | |
ffe74d75 CW |
9417 | } |
9418 | ||
cb05d8de | 9419 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 9420 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
75f7f3ec | 9421 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
7c9017e5 | 9422 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca CW |
9423 | |
9424 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9425 | __intel_ring_advance(ring); |
83d4092b | 9426 | return 0; |
7c9017e5 JB |
9427 | } |
9428 | ||
84c33a64 SG |
9429 | static bool use_mmio_flip(struct intel_engine_cs *ring, |
9430 | struct drm_i915_gem_object *obj) | |
9431 | { | |
9432 | /* | |
9433 | * This is not being used for older platforms, because | |
9434 | * non-availability of flip done interrupt forces us to use | |
9435 | * CS flips. Older platforms derive flip done using some clever | |
9436 | * tricks involving the flip_pending status bits and vblank irqs. | |
9437 | * So using MMIO flips there would disrupt this mechanism. | |
9438 | */ | |
9439 | ||
8e09bf83 CW |
9440 | if (ring == NULL) |
9441 | return true; | |
9442 | ||
84c33a64 SG |
9443 | if (INTEL_INFO(ring->dev)->gen < 5) |
9444 | return false; | |
9445 | ||
9446 | if (i915.use_mmio_flip < 0) | |
9447 | return false; | |
9448 | else if (i915.use_mmio_flip > 0) | |
9449 | return true; | |
14bf993e OM |
9450 | else if (i915.enable_execlists) |
9451 | return true; | |
84c33a64 SG |
9452 | else |
9453 | return ring != obj->ring; | |
9454 | } | |
9455 | ||
9456 | static void intel_do_mmio_flip(struct intel_crtc *intel_crtc) | |
9457 | { | |
9458 | struct drm_device *dev = intel_crtc->base.dev; | |
9459 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9460 | struct intel_framebuffer *intel_fb = | |
9461 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
9462 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
9362c7c5 ACO |
9463 | bool atomic_update; |
9464 | u32 start_vbl_count; | |
84c33a64 SG |
9465 | u32 dspcntr; |
9466 | u32 reg; | |
9467 | ||
9468 | intel_mark_page_flip_active(intel_crtc); | |
9469 | ||
9362c7c5 ACO |
9470 | atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count); |
9471 | ||
84c33a64 SG |
9472 | reg = DSPCNTR(intel_crtc->plane); |
9473 | dspcntr = I915_READ(reg); | |
9474 | ||
c5d97472 DL |
9475 | if (obj->tiling_mode != I915_TILING_NONE) |
9476 | dspcntr |= DISPPLANE_TILED; | |
9477 | else | |
9478 | dspcntr &= ~DISPPLANE_TILED; | |
9479 | ||
84c33a64 SG |
9480 | I915_WRITE(reg, dspcntr); |
9481 | ||
9482 | I915_WRITE(DSPSURF(intel_crtc->plane), | |
9483 | intel_crtc->unpin_work->gtt_offset); | |
9484 | POSTING_READ(DSPSURF(intel_crtc->plane)); | |
84c33a64 | 9485 | |
9362c7c5 ACO |
9486 | if (atomic_update) |
9487 | intel_pipe_update_end(intel_crtc, start_vbl_count); | |
84c33a64 SG |
9488 | } |
9489 | ||
9362c7c5 | 9490 | static void intel_mmio_flip_work_func(struct work_struct *work) |
84c33a64 | 9491 | { |
9362c7c5 ACO |
9492 | struct intel_crtc *intel_crtc = |
9493 | container_of(work, struct intel_crtc, mmio_flip.work); | |
84c33a64 | 9494 | struct intel_engine_cs *ring; |
536f5b5e | 9495 | uint32_t seqno; |
84c33a64 | 9496 | |
536f5b5e ACO |
9497 | seqno = intel_crtc->mmio_flip.seqno; |
9498 | ring = intel_crtc->mmio_flip.ring; | |
84c33a64 | 9499 | |
536f5b5e ACO |
9500 | if (seqno) |
9501 | WARN_ON(__i915_wait_seqno(ring, seqno, | |
9502 | intel_crtc->reset_counter, | |
9503 | false, NULL, NULL) != 0); | |
84c33a64 | 9504 | |
536f5b5e | 9505 | intel_do_mmio_flip(intel_crtc); |
84c33a64 SG |
9506 | } |
9507 | ||
9508 | static int intel_queue_mmio_flip(struct drm_device *dev, | |
9509 | struct drm_crtc *crtc, | |
9510 | struct drm_framebuffer *fb, | |
9511 | struct drm_i915_gem_object *obj, | |
9512 | struct intel_engine_cs *ring, | |
9513 | uint32_t flags) | |
9514 | { | |
84c33a64 | 9515 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
84c33a64 | 9516 | |
84c33a64 | 9517 | intel_crtc->mmio_flip.seqno = obj->last_write_seqno; |
536f5b5e ACO |
9518 | intel_crtc->mmio_flip.ring = obj->ring; |
9519 | ||
9520 | schedule_work(&intel_crtc->mmio_flip.work); | |
84c33a64 | 9521 | |
84c33a64 SG |
9522 | return 0; |
9523 | } | |
9524 | ||
830c81db DL |
9525 | static int intel_gen9_queue_flip(struct drm_device *dev, |
9526 | struct drm_crtc *crtc, | |
9527 | struct drm_framebuffer *fb, | |
9528 | struct drm_i915_gem_object *obj, | |
9529 | struct intel_engine_cs *ring, | |
9530 | uint32_t flags) | |
9531 | { | |
9532 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9533 | uint32_t plane = 0, stride; | |
9534 | int ret; | |
9535 | ||
9536 | switch(intel_crtc->pipe) { | |
9537 | case PIPE_A: | |
9538 | plane = MI_DISPLAY_FLIP_SKL_PLANE_1_A; | |
9539 | break; | |
9540 | case PIPE_B: | |
9541 | plane = MI_DISPLAY_FLIP_SKL_PLANE_1_B; | |
9542 | break; | |
9543 | case PIPE_C: | |
9544 | plane = MI_DISPLAY_FLIP_SKL_PLANE_1_C; | |
9545 | break; | |
9546 | default: | |
9547 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
9548 | return -ENODEV; | |
9549 | } | |
9550 | ||
9551 | switch (obj->tiling_mode) { | |
9552 | case I915_TILING_NONE: | |
9553 | stride = fb->pitches[0] >> 6; | |
9554 | break; | |
9555 | case I915_TILING_X: | |
9556 | stride = fb->pitches[0] >> 9; | |
9557 | break; | |
9558 | default: | |
9559 | WARN_ONCE(1, "unknown tiling in flip command\n"); | |
9560 | return -ENODEV; | |
9561 | } | |
9562 | ||
9563 | ret = intel_ring_begin(ring, 10); | |
9564 | if (ret) | |
9565 | return ret; | |
9566 | ||
9567 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
9568 | intel_ring_emit(ring, DERRMR); | |
9569 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
9570 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
9571 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
9572 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) | | |
9573 | MI_SRM_LRM_GLOBAL_GTT); | |
9574 | intel_ring_emit(ring, DERRMR); | |
9575 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
9576 | intel_ring_emit(ring, 0); | |
9577 | ||
9578 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane); | |
9579 | intel_ring_emit(ring, stride << 6 | obj->tiling_mode); | |
9580 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); | |
9581 | ||
9582 | intel_mark_page_flip_active(intel_crtc); | |
9583 | __intel_ring_advance(ring); | |
9584 | ||
9585 | return 0; | |
9586 | } | |
9587 | ||
8c9f3aaf JB |
9588 | static int intel_default_queue_flip(struct drm_device *dev, |
9589 | struct drm_crtc *crtc, | |
9590 | struct drm_framebuffer *fb, | |
ed8d1975 | 9591 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9592 | struct intel_engine_cs *ring, |
ed8d1975 | 9593 | uint32_t flags) |
8c9f3aaf JB |
9594 | { |
9595 | return -ENODEV; | |
9596 | } | |
9597 | ||
d6bbafa1 CW |
9598 | static bool __intel_pageflip_stall_check(struct drm_device *dev, |
9599 | struct drm_crtc *crtc) | |
9600 | { | |
9601 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9602 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9603 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
9604 | u32 addr; | |
9605 | ||
9606 | if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) | |
9607 | return true; | |
9608 | ||
9609 | if (!work->enable_stall_check) | |
9610 | return false; | |
9611 | ||
9612 | if (work->flip_ready_vblank == 0) { | |
9613 | if (work->flip_queued_ring && | |
9614 | !i915_seqno_passed(work->flip_queued_ring->get_seqno(work->flip_queued_ring, true), | |
9615 | work->flip_queued_seqno)) | |
9616 | return false; | |
9617 | ||
9618 | work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe); | |
9619 | } | |
9620 | ||
9621 | if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3) | |
9622 | return false; | |
9623 | ||
9624 | /* Potential stall - if we see that the flip has happened, | |
9625 | * assume a missed interrupt. */ | |
9626 | if (INTEL_INFO(dev)->gen >= 4) | |
9627 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
9628 | else | |
9629 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
9630 | ||
9631 | /* There is a potential issue here with a false positive after a flip | |
9632 | * to the same address. We could address this by checking for a | |
9633 | * non-incrementing frame counter. | |
9634 | */ | |
9635 | return addr == work->gtt_offset; | |
9636 | } | |
9637 | ||
9638 | void intel_check_page_flip(struct drm_device *dev, int pipe) | |
9639 | { | |
9640 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9641 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
9642 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
f326038a DV |
9643 | |
9644 | WARN_ON(!in_irq()); | |
d6bbafa1 CW |
9645 | |
9646 | if (crtc == NULL) | |
9647 | return; | |
9648 | ||
f326038a | 9649 | spin_lock(&dev->event_lock); |
d6bbafa1 CW |
9650 | if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) { |
9651 | WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", | |
9652 | intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe)); | |
9653 | page_flip_completed(intel_crtc); | |
9654 | } | |
f326038a | 9655 | spin_unlock(&dev->event_lock); |
d6bbafa1 CW |
9656 | } |
9657 | ||
6b95a207 KH |
9658 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
9659 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
9660 | struct drm_pending_vblank_event *event, |
9661 | uint32_t page_flip_flags) | |
6b95a207 KH |
9662 | { |
9663 | struct drm_device *dev = crtc->dev; | |
9664 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 9665 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2ff8fde1 | 9666 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 | 9667 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
a071fa00 | 9668 | enum pipe pipe = intel_crtc->pipe; |
6b95a207 | 9669 | struct intel_unpin_work *work; |
a4872ba6 | 9670 | struct intel_engine_cs *ring; |
52e68630 | 9671 | int ret; |
6b95a207 | 9672 | |
2ff8fde1 MR |
9673 | /* |
9674 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
9675 | * check to be safe. In the future we may enable pageflipping from | |
9676 | * a disabled primary plane. | |
9677 | */ | |
9678 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
9679 | return -EBUSY; | |
9680 | ||
e6a595d2 | 9681 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 9682 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
9683 | return -EINVAL; |
9684 | ||
9685 | /* | |
9686 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
9687 | * Note that pitch changes could also affect these register. | |
9688 | */ | |
9689 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
9690 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
9691 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
9692 | return -EINVAL; |
9693 | ||
f900db47 CW |
9694 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
9695 | goto out_hang; | |
9696 | ||
b14c5679 | 9697 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
9698 | if (work == NULL) |
9699 | return -ENOMEM; | |
9700 | ||
6b95a207 | 9701 | work->event = event; |
b4a98e57 | 9702 | work->crtc = crtc; |
2ff8fde1 | 9703 | work->old_fb_obj = intel_fb_obj(old_fb); |
6b95a207 KH |
9704 | INIT_WORK(&work->work, intel_unpin_work_fn); |
9705 | ||
87b6b101 | 9706 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
9707 | if (ret) |
9708 | goto free_work; | |
9709 | ||
6b95a207 | 9710 | /* We borrow the event spin lock for protecting unpin_work */ |
5e2d7afc | 9711 | spin_lock_irq(&dev->event_lock); |
6b95a207 | 9712 | if (intel_crtc->unpin_work) { |
d6bbafa1 CW |
9713 | /* Before declaring the flip queue wedged, check if |
9714 | * the hardware completed the operation behind our backs. | |
9715 | */ | |
9716 | if (__intel_pageflip_stall_check(dev, crtc)) { | |
9717 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
9718 | page_flip_completed(intel_crtc); | |
9719 | } else { | |
9720 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
5e2d7afc | 9721 | spin_unlock_irq(&dev->event_lock); |
468f0b44 | 9722 | |
d6bbafa1 CW |
9723 | drm_crtc_vblank_put(crtc); |
9724 | kfree(work); | |
9725 | return -EBUSY; | |
9726 | } | |
6b95a207 KH |
9727 | } |
9728 | intel_crtc->unpin_work = work; | |
5e2d7afc | 9729 | spin_unlock_irq(&dev->event_lock); |
6b95a207 | 9730 | |
b4a98e57 CW |
9731 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
9732 | flush_workqueue(dev_priv->wq); | |
9733 | ||
79158103 CW |
9734 | ret = i915_mutex_lock_interruptible(dev); |
9735 | if (ret) | |
9736 | goto cleanup; | |
6b95a207 | 9737 | |
75dfca80 | 9738 | /* Reference the objects for the scheduled work. */ |
05394f39 CW |
9739 | drm_gem_object_reference(&work->old_fb_obj->base); |
9740 | drm_gem_object_reference(&obj->base); | |
6b95a207 | 9741 | |
f4510a27 | 9742 | crtc->primary->fb = fb; |
96b099fd | 9743 | |
e1f99ce6 | 9744 | work->pending_flip_obj = obj; |
e1f99ce6 | 9745 | |
b4a98e57 | 9746 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 9747 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 9748 | |
75f7f3ec | 9749 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
a071fa00 | 9750 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1; |
75f7f3ec | 9751 | |
4fa62c89 VS |
9752 | if (IS_VALLEYVIEW(dev)) { |
9753 | ring = &dev_priv->ring[BCS]; | |
8e09bf83 CW |
9754 | if (obj->tiling_mode != work->old_fb_obj->tiling_mode) |
9755 | /* vlv: DISPLAY_FLIP fails to change tiling */ | |
9756 | ring = NULL; | |
2a92d5bc CW |
9757 | } else if (IS_IVYBRIDGE(dev)) { |
9758 | ring = &dev_priv->ring[BCS]; | |
4fa62c89 VS |
9759 | } else if (INTEL_INFO(dev)->gen >= 7) { |
9760 | ring = obj->ring; | |
9761 | if (ring == NULL || ring->id != RCS) | |
9762 | ring = &dev_priv->ring[BCS]; | |
9763 | } else { | |
9764 | ring = &dev_priv->ring[RCS]; | |
9765 | } | |
9766 | ||
850c4cdc | 9767 | ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, ring); |
8c9f3aaf JB |
9768 | if (ret) |
9769 | goto cleanup_pending; | |
6b95a207 | 9770 | |
4fa62c89 VS |
9771 | work->gtt_offset = |
9772 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset; | |
9773 | ||
d6bbafa1 | 9774 | if (use_mmio_flip(ring, obj)) { |
84c33a64 SG |
9775 | ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring, |
9776 | page_flip_flags); | |
d6bbafa1 CW |
9777 | if (ret) |
9778 | goto cleanup_unpin; | |
9779 | ||
9780 | work->flip_queued_seqno = obj->last_write_seqno; | |
9781 | work->flip_queued_ring = obj->ring; | |
9782 | } else { | |
84c33a64 | 9783 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring, |
d6bbafa1 CW |
9784 | page_flip_flags); |
9785 | if (ret) | |
9786 | goto cleanup_unpin; | |
9787 | ||
9788 | work->flip_queued_seqno = intel_ring_get_seqno(ring); | |
9789 | work->flip_queued_ring = ring; | |
9790 | } | |
9791 | ||
9792 | work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe); | |
9793 | work->enable_stall_check = true; | |
4fa62c89 | 9794 | |
a071fa00 DV |
9795 | i915_gem_track_fb(work->old_fb_obj, obj, |
9796 | INTEL_FRONTBUFFER_PRIMARY(pipe)); | |
9797 | ||
7782de3b | 9798 | intel_disable_fbc(dev); |
f99d7069 | 9799 | intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
6b95a207 KH |
9800 | mutex_unlock(&dev->struct_mutex); |
9801 | ||
e5510fac JB |
9802 | trace_i915_flip_request(intel_crtc->plane, obj); |
9803 | ||
6b95a207 | 9804 | return 0; |
96b099fd | 9805 | |
4fa62c89 VS |
9806 | cleanup_unpin: |
9807 | intel_unpin_fb_obj(obj); | |
8c9f3aaf | 9808 | cleanup_pending: |
b4a98e57 | 9809 | atomic_dec(&intel_crtc->unpin_work_count); |
f4510a27 | 9810 | crtc->primary->fb = old_fb; |
05394f39 CW |
9811 | drm_gem_object_unreference(&work->old_fb_obj->base); |
9812 | drm_gem_object_unreference(&obj->base); | |
96b099fd CW |
9813 | mutex_unlock(&dev->struct_mutex); |
9814 | ||
79158103 | 9815 | cleanup: |
5e2d7afc | 9816 | spin_lock_irq(&dev->event_lock); |
96b099fd | 9817 | intel_crtc->unpin_work = NULL; |
5e2d7afc | 9818 | spin_unlock_irq(&dev->event_lock); |
96b099fd | 9819 | |
87b6b101 | 9820 | drm_crtc_vblank_put(crtc); |
7317c75e | 9821 | free_work: |
96b099fd CW |
9822 | kfree(work); |
9823 | ||
f900db47 CW |
9824 | if (ret == -EIO) { |
9825 | out_hang: | |
9826 | intel_crtc_wait_for_pending_flips(crtc); | |
9827 | ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb); | |
f0d3dad3 | 9828 | if (ret == 0 && event) { |
5e2d7afc | 9829 | spin_lock_irq(&dev->event_lock); |
a071fa00 | 9830 | drm_send_vblank_event(dev, pipe, event); |
5e2d7afc | 9831 | spin_unlock_irq(&dev->event_lock); |
f0d3dad3 | 9832 | } |
f900db47 | 9833 | } |
96b099fd | 9834 | return ret; |
6b95a207 KH |
9835 | } |
9836 | ||
f6e5b160 | 9837 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
9838 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
9839 | .load_lut = intel_crtc_load_lut, | |
f6e5b160 CW |
9840 | }; |
9841 | ||
9a935856 DV |
9842 | /** |
9843 | * intel_modeset_update_staged_output_state | |
9844 | * | |
9845 | * Updates the staged output configuration state, e.g. after we've read out the | |
9846 | * current hw state. | |
9847 | */ | |
9848 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) | |
f6e5b160 | 9849 | { |
7668851f | 9850 | struct intel_crtc *crtc; |
9a935856 DV |
9851 | struct intel_encoder *encoder; |
9852 | struct intel_connector *connector; | |
f6e5b160 | 9853 | |
9a935856 DV |
9854 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9855 | base.head) { | |
9856 | connector->new_encoder = | |
9857 | to_intel_encoder(connector->base.encoder); | |
9858 | } | |
f6e5b160 | 9859 | |
b2784e15 | 9860 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
9861 | encoder->new_crtc = |
9862 | to_intel_crtc(encoder->base.crtc); | |
9863 | } | |
7668851f | 9864 | |
d3fcc808 | 9865 | for_each_intel_crtc(dev, crtc) { |
7668851f | 9866 | crtc->new_enabled = crtc->base.enabled; |
7bd0a8e7 VS |
9867 | |
9868 | if (crtc->new_enabled) | |
9869 | crtc->new_config = &crtc->config; | |
9870 | else | |
9871 | crtc->new_config = NULL; | |
7668851f | 9872 | } |
f6e5b160 CW |
9873 | } |
9874 | ||
9a935856 DV |
9875 | /** |
9876 | * intel_modeset_commit_output_state | |
9877 | * | |
9878 | * This function copies the stage display pipe configuration to the real one. | |
9879 | */ | |
9880 | static void intel_modeset_commit_output_state(struct drm_device *dev) | |
9881 | { | |
7668851f | 9882 | struct intel_crtc *crtc; |
9a935856 DV |
9883 | struct intel_encoder *encoder; |
9884 | struct intel_connector *connector; | |
f6e5b160 | 9885 | |
9a935856 DV |
9886 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9887 | base.head) { | |
9888 | connector->base.encoder = &connector->new_encoder->base; | |
9889 | } | |
f6e5b160 | 9890 | |
b2784e15 | 9891 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
9892 | encoder->base.crtc = &encoder->new_crtc->base; |
9893 | } | |
7668851f | 9894 | |
d3fcc808 | 9895 | for_each_intel_crtc(dev, crtc) { |
7668851f VS |
9896 | crtc->base.enabled = crtc->new_enabled; |
9897 | } | |
9a935856 DV |
9898 | } |
9899 | ||
050f7aeb | 9900 | static void |
eba905b2 | 9901 | connected_sink_compute_bpp(struct intel_connector *connector, |
050f7aeb DV |
9902 | struct intel_crtc_config *pipe_config) |
9903 | { | |
9904 | int bpp = pipe_config->pipe_bpp; | |
9905 | ||
9906 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
9907 | connector->base.base.id, | |
c23cc417 | 9908 | connector->base.name); |
050f7aeb DV |
9909 | |
9910 | /* Don't use an invalid EDID bpc value */ | |
9911 | if (connector->base.display_info.bpc && | |
9912 | connector->base.display_info.bpc * 3 < bpp) { | |
9913 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
9914 | bpp, connector->base.display_info.bpc*3); | |
9915 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
9916 | } | |
9917 | ||
9918 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
9919 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
9920 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
9921 | bpp); | |
9922 | pipe_config->pipe_bpp = 24; | |
9923 | } | |
9924 | } | |
9925 | ||
4e53c2e0 | 9926 | static int |
050f7aeb DV |
9927 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
9928 | struct drm_framebuffer *fb, | |
9929 | struct intel_crtc_config *pipe_config) | |
4e53c2e0 | 9930 | { |
050f7aeb DV |
9931 | struct drm_device *dev = crtc->base.dev; |
9932 | struct intel_connector *connector; | |
4e53c2e0 DV |
9933 | int bpp; |
9934 | ||
d42264b1 DV |
9935 | switch (fb->pixel_format) { |
9936 | case DRM_FORMAT_C8: | |
4e53c2e0 DV |
9937 | bpp = 8*3; /* since we go through a colormap */ |
9938 | break; | |
d42264b1 DV |
9939 | case DRM_FORMAT_XRGB1555: |
9940 | case DRM_FORMAT_ARGB1555: | |
9941 | /* checked in intel_framebuffer_init already */ | |
9942 | if (WARN_ON(INTEL_INFO(dev)->gen > 3)) | |
9943 | return -EINVAL; | |
9944 | case DRM_FORMAT_RGB565: | |
4e53c2e0 DV |
9945 | bpp = 6*3; /* min is 18bpp */ |
9946 | break; | |
d42264b1 DV |
9947 | case DRM_FORMAT_XBGR8888: |
9948 | case DRM_FORMAT_ABGR8888: | |
9949 | /* checked in intel_framebuffer_init already */ | |
9950 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
9951 | return -EINVAL; | |
9952 | case DRM_FORMAT_XRGB8888: | |
9953 | case DRM_FORMAT_ARGB8888: | |
4e53c2e0 DV |
9954 | bpp = 8*3; |
9955 | break; | |
d42264b1 DV |
9956 | case DRM_FORMAT_XRGB2101010: |
9957 | case DRM_FORMAT_ARGB2101010: | |
9958 | case DRM_FORMAT_XBGR2101010: | |
9959 | case DRM_FORMAT_ABGR2101010: | |
9960 | /* checked in intel_framebuffer_init already */ | |
9961 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
baba133a | 9962 | return -EINVAL; |
4e53c2e0 DV |
9963 | bpp = 10*3; |
9964 | break; | |
baba133a | 9965 | /* TODO: gen4+ supports 16 bpc floating point, too. */ |
4e53c2e0 DV |
9966 | default: |
9967 | DRM_DEBUG_KMS("unsupported depth\n"); | |
9968 | return -EINVAL; | |
9969 | } | |
9970 | ||
4e53c2e0 DV |
9971 | pipe_config->pipe_bpp = bpp; |
9972 | ||
9973 | /* Clamp display bpp to EDID value */ | |
9974 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
050f7aeb | 9975 | base.head) { |
1b829e05 DV |
9976 | if (!connector->new_encoder || |
9977 | connector->new_encoder->new_crtc != crtc) | |
4e53c2e0 DV |
9978 | continue; |
9979 | ||
050f7aeb | 9980 | connected_sink_compute_bpp(connector, pipe_config); |
4e53c2e0 DV |
9981 | } |
9982 | ||
9983 | return bpp; | |
9984 | } | |
9985 | ||
644db711 DV |
9986 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
9987 | { | |
9988 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
9989 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 9990 | mode->crtc_clock, |
644db711 DV |
9991 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
9992 | mode->crtc_hsync_end, mode->crtc_htotal, | |
9993 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
9994 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
9995 | } | |
9996 | ||
c0b03411 DV |
9997 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
9998 | struct intel_crtc_config *pipe_config, | |
9999 | const char *context) | |
10000 | { | |
10001 | DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id, | |
10002 | context, pipe_name(crtc->pipe)); | |
10003 | ||
10004 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
10005 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
10006 | pipe_config->pipe_bpp, pipe_config->dither); | |
10007 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
10008 | pipe_config->has_pch_encoder, | |
10009 | pipe_config->fdi_lanes, | |
10010 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
10011 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
10012 | pipe_config->fdi_m_n.tu); | |
eb14cb74 VS |
10013 | DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
10014 | pipe_config->has_dp_encoder, | |
10015 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, | |
10016 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
10017 | pipe_config->dp_m_n.tu); | |
b95af8be VK |
10018 | |
10019 | DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", | |
10020 | pipe_config->has_dp_encoder, | |
10021 | pipe_config->dp_m2_n2.gmch_m, | |
10022 | pipe_config->dp_m2_n2.gmch_n, | |
10023 | pipe_config->dp_m2_n2.link_m, | |
10024 | pipe_config->dp_m2_n2.link_n, | |
10025 | pipe_config->dp_m2_n2.tu); | |
10026 | ||
55072d19 DV |
10027 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
10028 | pipe_config->has_audio, | |
10029 | pipe_config->has_infoframe); | |
10030 | ||
c0b03411 DV |
10031 | DRM_DEBUG_KMS("requested mode:\n"); |
10032 | drm_mode_debug_printmodeline(&pipe_config->requested_mode); | |
10033 | DRM_DEBUG_KMS("adjusted mode:\n"); | |
10034 | drm_mode_debug_printmodeline(&pipe_config->adjusted_mode); | |
644db711 | 10035 | intel_dump_crtc_timings(&pipe_config->adjusted_mode); |
d71b8d4a | 10036 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
10037 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
10038 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
c0b03411 DV |
10039 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
10040 | pipe_config->gmch_pfit.control, | |
10041 | pipe_config->gmch_pfit.pgm_ratios, | |
10042 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 10043 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 10044 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
10045 | pipe_config->pch_pfit.size, |
10046 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 10047 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 10048 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
c0b03411 DV |
10049 | } |
10050 | ||
bc079e8b VS |
10051 | static bool encoders_cloneable(const struct intel_encoder *a, |
10052 | const struct intel_encoder *b) | |
accfc0c5 | 10053 | { |
bc079e8b VS |
10054 | /* masks could be asymmetric, so check both ways */ |
10055 | return a == b || (a->cloneable & (1 << b->type) && | |
10056 | b->cloneable & (1 << a->type)); | |
10057 | } | |
10058 | ||
10059 | static bool check_single_encoder_cloning(struct intel_crtc *crtc, | |
10060 | struct intel_encoder *encoder) | |
10061 | { | |
10062 | struct drm_device *dev = crtc->base.dev; | |
10063 | struct intel_encoder *source_encoder; | |
10064 | ||
b2784e15 | 10065 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b VS |
10066 | if (source_encoder->new_crtc != crtc) |
10067 | continue; | |
10068 | ||
10069 | if (!encoders_cloneable(encoder, source_encoder)) | |
10070 | return false; | |
10071 | } | |
10072 | ||
10073 | return true; | |
10074 | } | |
10075 | ||
10076 | static bool check_encoder_cloning(struct intel_crtc *crtc) | |
10077 | { | |
10078 | struct drm_device *dev = crtc->base.dev; | |
accfc0c5 DV |
10079 | struct intel_encoder *encoder; |
10080 | ||
b2784e15 | 10081 | for_each_intel_encoder(dev, encoder) { |
bc079e8b | 10082 | if (encoder->new_crtc != crtc) |
accfc0c5 DV |
10083 | continue; |
10084 | ||
bc079e8b VS |
10085 | if (!check_single_encoder_cloning(crtc, encoder)) |
10086 | return false; | |
accfc0c5 DV |
10087 | } |
10088 | ||
bc079e8b | 10089 | return true; |
accfc0c5 DV |
10090 | } |
10091 | ||
b8cecdf5 DV |
10092 | static struct intel_crtc_config * |
10093 | intel_modeset_pipe_config(struct drm_crtc *crtc, | |
4e53c2e0 | 10094 | struct drm_framebuffer *fb, |
b8cecdf5 | 10095 | struct drm_display_mode *mode) |
ee7b9f93 | 10096 | { |
7758a113 | 10097 | struct drm_device *dev = crtc->dev; |
7758a113 | 10098 | struct intel_encoder *encoder; |
b8cecdf5 | 10099 | struct intel_crtc_config *pipe_config; |
e29c22c0 DV |
10100 | int plane_bpp, ret = -EINVAL; |
10101 | bool retry = true; | |
ee7b9f93 | 10102 | |
bc079e8b | 10103 | if (!check_encoder_cloning(to_intel_crtc(crtc))) { |
accfc0c5 DV |
10104 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); |
10105 | return ERR_PTR(-EINVAL); | |
10106 | } | |
10107 | ||
b8cecdf5 DV |
10108 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
10109 | if (!pipe_config) | |
7758a113 DV |
10110 | return ERR_PTR(-ENOMEM); |
10111 | ||
b8cecdf5 DV |
10112 | drm_mode_copy(&pipe_config->adjusted_mode, mode); |
10113 | drm_mode_copy(&pipe_config->requested_mode, mode); | |
37327abd | 10114 | |
e143a21c DV |
10115 | pipe_config->cpu_transcoder = |
10116 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
c0d43d62 | 10117 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
b8cecdf5 | 10118 | |
2960bc9c ID |
10119 | /* |
10120 | * Sanitize sync polarity flags based on requested ones. If neither | |
10121 | * positive or negative polarity is requested, treat this as meaning | |
10122 | * negative polarity. | |
10123 | */ | |
10124 | if (!(pipe_config->adjusted_mode.flags & | |
10125 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) | |
10126 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; | |
10127 | ||
10128 | if (!(pipe_config->adjusted_mode.flags & | |
10129 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) | |
10130 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; | |
10131 | ||
050f7aeb DV |
10132 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
10133 | * plane pixel format and any sink constraints into account. Returns the | |
10134 | * source plane bpp so that dithering can be selected on mismatches | |
10135 | * after encoders and crtc also have had their say. */ | |
10136 | plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), | |
10137 | fb, pipe_config); | |
4e53c2e0 DV |
10138 | if (plane_bpp < 0) |
10139 | goto fail; | |
10140 | ||
e41a56be VS |
10141 | /* |
10142 | * Determine the real pipe dimensions. Note that stereo modes can | |
10143 | * increase the actual pipe size due to the frame doubling and | |
10144 | * insertion of additional space for blanks between the frame. This | |
10145 | * is stored in the crtc timings. We use the requested mode to do this | |
10146 | * computation to clearly distinguish it from the adjusted mode, which | |
10147 | * can be changed by the connectors in the below retry loop. | |
10148 | */ | |
10149 | drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE); | |
10150 | pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay; | |
10151 | pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay; | |
10152 | ||
e29c22c0 | 10153 | encoder_retry: |
ef1b460d | 10154 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 10155 | pipe_config->port_clock = 0; |
ef1b460d | 10156 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 10157 | |
135c81b8 | 10158 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
6ce70f5e | 10159 | drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE); |
135c81b8 | 10160 | |
7758a113 DV |
10161 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
10162 | * adjust it according to limitations or connector properties, and also | |
10163 | * a chance to reject the mode entirely. | |
47f1c6c9 | 10164 | */ |
b2784e15 | 10165 | for_each_intel_encoder(dev, encoder) { |
47f1c6c9 | 10166 | |
7758a113 DV |
10167 | if (&encoder->new_crtc->base != crtc) |
10168 | continue; | |
7ae89233 | 10169 | |
efea6e8e DV |
10170 | if (!(encoder->compute_config(encoder, pipe_config))) { |
10171 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
10172 | goto fail; |
10173 | } | |
ee7b9f93 | 10174 | } |
47f1c6c9 | 10175 | |
ff9a6750 DV |
10176 | /* Set default port clock if not overwritten by the encoder. Needs to be |
10177 | * done afterwards in case the encoder adjusts the mode. */ | |
10178 | if (!pipe_config->port_clock) | |
241bfc38 DL |
10179 | pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock |
10180 | * pipe_config->pixel_multiplier; | |
ff9a6750 | 10181 | |
a43f6e0f | 10182 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 10183 | if (ret < 0) { |
7758a113 DV |
10184 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
10185 | goto fail; | |
ee7b9f93 | 10186 | } |
e29c22c0 DV |
10187 | |
10188 | if (ret == RETRY) { | |
10189 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
10190 | ret = -EINVAL; | |
10191 | goto fail; | |
10192 | } | |
10193 | ||
10194 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
10195 | retry = false; | |
10196 | goto encoder_retry; | |
10197 | } | |
10198 | ||
4e53c2e0 DV |
10199 | pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; |
10200 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", | |
10201 | plane_bpp, pipe_config->pipe_bpp, pipe_config->dither); | |
10202 | ||
b8cecdf5 | 10203 | return pipe_config; |
7758a113 | 10204 | fail: |
b8cecdf5 | 10205 | kfree(pipe_config); |
e29c22c0 | 10206 | return ERR_PTR(ret); |
ee7b9f93 | 10207 | } |
47f1c6c9 | 10208 | |
e2e1ed41 DV |
10209 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
10210 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ | |
10211 | static void | |
10212 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, | |
10213 | unsigned *prepare_pipes, unsigned *disable_pipes) | |
79e53945 JB |
10214 | { |
10215 | struct intel_crtc *intel_crtc; | |
e2e1ed41 DV |
10216 | struct drm_device *dev = crtc->dev; |
10217 | struct intel_encoder *encoder; | |
10218 | struct intel_connector *connector; | |
10219 | struct drm_crtc *tmp_crtc; | |
79e53945 | 10220 | |
e2e1ed41 | 10221 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
79e53945 | 10222 | |
e2e1ed41 DV |
10223 | /* Check which crtcs have changed outputs connected to them, these need |
10224 | * to be part of the prepare_pipes mask. We don't (yet) support global | |
10225 | * modeset across multiple crtcs, so modeset_pipes will only have one | |
10226 | * bit set at most. */ | |
10227 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
10228 | base.head) { | |
10229 | if (connector->base.encoder == &connector->new_encoder->base) | |
10230 | continue; | |
79e53945 | 10231 | |
e2e1ed41 DV |
10232 | if (connector->base.encoder) { |
10233 | tmp_crtc = connector->base.encoder->crtc; | |
10234 | ||
10235 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
10236 | } | |
10237 | ||
10238 | if (connector->new_encoder) | |
10239 | *prepare_pipes |= | |
10240 | 1 << connector->new_encoder->new_crtc->pipe; | |
79e53945 JB |
10241 | } |
10242 | ||
b2784e15 | 10243 | for_each_intel_encoder(dev, encoder) { |
e2e1ed41 DV |
10244 | if (encoder->base.crtc == &encoder->new_crtc->base) |
10245 | continue; | |
10246 | ||
10247 | if (encoder->base.crtc) { | |
10248 | tmp_crtc = encoder->base.crtc; | |
10249 | ||
10250 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
10251 | } | |
10252 | ||
10253 | if (encoder->new_crtc) | |
10254 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; | |
80824003 JB |
10255 | } |
10256 | ||
7668851f | 10257 | /* Check for pipes that will be enabled/disabled ... */ |
d3fcc808 | 10258 | for_each_intel_crtc(dev, intel_crtc) { |
7668851f | 10259 | if (intel_crtc->base.enabled == intel_crtc->new_enabled) |
e2e1ed41 | 10260 | continue; |
7e7d76c3 | 10261 | |
7668851f | 10262 | if (!intel_crtc->new_enabled) |
e2e1ed41 | 10263 | *disable_pipes |= 1 << intel_crtc->pipe; |
7668851f VS |
10264 | else |
10265 | *prepare_pipes |= 1 << intel_crtc->pipe; | |
7e7d76c3 JB |
10266 | } |
10267 | ||
e2e1ed41 DV |
10268 | |
10269 | /* set_mode is also used to update properties on life display pipes. */ | |
10270 | intel_crtc = to_intel_crtc(crtc); | |
7668851f | 10271 | if (intel_crtc->new_enabled) |
e2e1ed41 DV |
10272 | *prepare_pipes |= 1 << intel_crtc->pipe; |
10273 | ||
b6c5164d DV |
10274 | /* |
10275 | * For simplicity do a full modeset on any pipe where the output routing | |
10276 | * changed. We could be more clever, but that would require us to be | |
10277 | * more careful with calling the relevant encoder->mode_set functions. | |
10278 | */ | |
e2e1ed41 DV |
10279 | if (*prepare_pipes) |
10280 | *modeset_pipes = *prepare_pipes; | |
10281 | ||
10282 | /* ... and mask these out. */ | |
10283 | *modeset_pipes &= ~(*disable_pipes); | |
10284 | *prepare_pipes &= ~(*disable_pipes); | |
b6c5164d DV |
10285 | |
10286 | /* | |
10287 | * HACK: We don't (yet) fully support global modesets. intel_set_config | |
10288 | * obies this rule, but the modeset restore mode of | |
10289 | * intel_modeset_setup_hw_state does not. | |
10290 | */ | |
10291 | *modeset_pipes &= 1 << intel_crtc->pipe; | |
10292 | *prepare_pipes &= 1 << intel_crtc->pipe; | |
e3641d3f DV |
10293 | |
10294 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", | |
10295 | *modeset_pipes, *prepare_pipes, *disable_pipes); | |
47f1c6c9 | 10296 | } |
79e53945 | 10297 | |
ea9d758d | 10298 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
f6e5b160 | 10299 | { |
ea9d758d | 10300 | struct drm_encoder *encoder; |
f6e5b160 | 10301 | struct drm_device *dev = crtc->dev; |
f6e5b160 | 10302 | |
ea9d758d DV |
10303 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
10304 | if (encoder->crtc == crtc) | |
10305 | return true; | |
10306 | ||
10307 | return false; | |
10308 | } | |
10309 | ||
10310 | static void | |
10311 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) | |
10312 | { | |
ba41c0de | 10313 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea9d758d DV |
10314 | struct intel_encoder *intel_encoder; |
10315 | struct intel_crtc *intel_crtc; | |
10316 | struct drm_connector *connector; | |
10317 | ||
ba41c0de DV |
10318 | intel_shared_dpll_commit(dev_priv); |
10319 | ||
b2784e15 | 10320 | for_each_intel_encoder(dev, intel_encoder) { |
ea9d758d DV |
10321 | if (!intel_encoder->base.crtc) |
10322 | continue; | |
10323 | ||
10324 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
10325 | ||
10326 | if (prepare_pipes & (1 << intel_crtc->pipe)) | |
10327 | intel_encoder->connectors_active = false; | |
10328 | } | |
10329 | ||
10330 | intel_modeset_commit_output_state(dev); | |
10331 | ||
7668851f | 10332 | /* Double check state. */ |
d3fcc808 | 10333 | for_each_intel_crtc(dev, intel_crtc) { |
7668851f | 10334 | WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base)); |
7bd0a8e7 VS |
10335 | WARN_ON(intel_crtc->new_config && |
10336 | intel_crtc->new_config != &intel_crtc->config); | |
10337 | WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config); | |
ea9d758d DV |
10338 | } |
10339 | ||
10340 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
10341 | if (!connector->encoder || !connector->encoder->crtc) | |
10342 | continue; | |
10343 | ||
10344 | intel_crtc = to_intel_crtc(connector->encoder->crtc); | |
10345 | ||
10346 | if (prepare_pipes & (1 << intel_crtc->pipe)) { | |
68d34720 DV |
10347 | struct drm_property *dpms_property = |
10348 | dev->mode_config.dpms_property; | |
10349 | ||
ea9d758d | 10350 | connector->dpms = DRM_MODE_DPMS_ON; |
662595df | 10351 | drm_object_property_set_value(&connector->base, |
68d34720 DV |
10352 | dpms_property, |
10353 | DRM_MODE_DPMS_ON); | |
ea9d758d DV |
10354 | |
10355 | intel_encoder = to_intel_encoder(connector->encoder); | |
10356 | intel_encoder->connectors_active = true; | |
10357 | } | |
10358 | } | |
10359 | ||
10360 | } | |
10361 | ||
3bd26263 | 10362 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 10363 | { |
3bd26263 | 10364 | int diff; |
f1f644dc JB |
10365 | |
10366 | if (clock1 == clock2) | |
10367 | return true; | |
10368 | ||
10369 | if (!clock1 || !clock2) | |
10370 | return false; | |
10371 | ||
10372 | diff = abs(clock1 - clock2); | |
10373 | ||
10374 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
10375 | return true; | |
10376 | ||
10377 | return false; | |
10378 | } | |
10379 | ||
25c5b266 DV |
10380 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
10381 | list_for_each_entry((intel_crtc), \ | |
10382 | &(dev)->mode_config.crtc_list, \ | |
10383 | base.head) \ | |
0973f18f | 10384 | if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 10385 | |
0e8ffe1b | 10386 | static bool |
2fa2fe9a DV |
10387 | intel_pipe_config_compare(struct drm_device *dev, |
10388 | struct intel_crtc_config *current_config, | |
0e8ffe1b DV |
10389 | struct intel_crtc_config *pipe_config) |
10390 | { | |
66e985c0 DV |
10391 | #define PIPE_CONF_CHECK_X(name) \ |
10392 | if (current_config->name != pipe_config->name) { \ | |
10393 | DRM_ERROR("mismatch in " #name " " \ | |
10394 | "(expected 0x%08x, found 0x%08x)\n", \ | |
10395 | current_config->name, \ | |
10396 | pipe_config->name); \ | |
10397 | return false; \ | |
10398 | } | |
10399 | ||
08a24034 DV |
10400 | #define PIPE_CONF_CHECK_I(name) \ |
10401 | if (current_config->name != pipe_config->name) { \ | |
10402 | DRM_ERROR("mismatch in " #name " " \ | |
10403 | "(expected %i, found %i)\n", \ | |
10404 | current_config->name, \ | |
10405 | pipe_config->name); \ | |
10406 | return false; \ | |
88adfff1 DV |
10407 | } |
10408 | ||
b95af8be VK |
10409 | /* This is required for BDW+ where there is only one set of registers for |
10410 | * switching between high and low RR. | |
10411 | * This macro can be used whenever a comparison has to be made between one | |
10412 | * hw state and multiple sw state variables. | |
10413 | */ | |
10414 | #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \ | |
10415 | if ((current_config->name != pipe_config->name) && \ | |
10416 | (current_config->alt_name != pipe_config->name)) { \ | |
10417 | DRM_ERROR("mismatch in " #name " " \ | |
10418 | "(expected %i or %i, found %i)\n", \ | |
10419 | current_config->name, \ | |
10420 | current_config->alt_name, \ | |
10421 | pipe_config->name); \ | |
10422 | return false; \ | |
10423 | } | |
10424 | ||
1bd1bd80 DV |
10425 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
10426 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
6f02488e | 10427 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
10428 | "(expected %i, found %i)\n", \ |
10429 | current_config->name & (mask), \ | |
10430 | pipe_config->name & (mask)); \ | |
10431 | return false; \ | |
10432 | } | |
10433 | ||
5e550656 VS |
10434 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
10435 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
10436 | DRM_ERROR("mismatch in " #name " " \ | |
10437 | "(expected %i, found %i)\n", \ | |
10438 | current_config->name, \ | |
10439 | pipe_config->name); \ | |
10440 | return false; \ | |
10441 | } | |
10442 | ||
bb760063 DV |
10443 | #define PIPE_CONF_QUIRK(quirk) \ |
10444 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
10445 | ||
eccb140b DV |
10446 | PIPE_CONF_CHECK_I(cpu_transcoder); |
10447 | ||
08a24034 DV |
10448 | PIPE_CONF_CHECK_I(has_pch_encoder); |
10449 | PIPE_CONF_CHECK_I(fdi_lanes); | |
72419203 DV |
10450 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
10451 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); | |
10452 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); | |
10453 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); | |
10454 | PIPE_CONF_CHECK_I(fdi_m_n.tu); | |
08a24034 | 10455 | |
eb14cb74 | 10456 | PIPE_CONF_CHECK_I(has_dp_encoder); |
b95af8be VK |
10457 | |
10458 | if (INTEL_INFO(dev)->gen < 8) { | |
10459 | PIPE_CONF_CHECK_I(dp_m_n.gmch_m); | |
10460 | PIPE_CONF_CHECK_I(dp_m_n.gmch_n); | |
10461 | PIPE_CONF_CHECK_I(dp_m_n.link_m); | |
10462 | PIPE_CONF_CHECK_I(dp_m_n.link_n); | |
10463 | PIPE_CONF_CHECK_I(dp_m_n.tu); | |
10464 | ||
10465 | if (current_config->has_drrs) { | |
10466 | PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m); | |
10467 | PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n); | |
10468 | PIPE_CONF_CHECK_I(dp_m2_n2.link_m); | |
10469 | PIPE_CONF_CHECK_I(dp_m2_n2.link_n); | |
10470 | PIPE_CONF_CHECK_I(dp_m2_n2.tu); | |
10471 | } | |
10472 | } else { | |
10473 | PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m); | |
10474 | PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n); | |
10475 | PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m); | |
10476 | PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n); | |
10477 | PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu); | |
10478 | } | |
eb14cb74 | 10479 | |
1bd1bd80 DV |
10480 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay); |
10481 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal); | |
10482 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start); | |
10483 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end); | |
10484 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start); | |
10485 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end); | |
10486 | ||
10487 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay); | |
10488 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal); | |
10489 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start); | |
10490 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end); | |
10491 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start); | |
10492 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end); | |
10493 | ||
c93f54cf | 10494 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 10495 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 DV |
10496 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
10497 | IS_VALLEYVIEW(dev)) | |
10498 | PIPE_CONF_CHECK_I(limited_color_range); | |
e43823ec | 10499 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 10500 | |
9ed109a7 DV |
10501 | PIPE_CONF_CHECK_I(has_audio); |
10502 | ||
1bd1bd80 DV |
10503 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
10504 | DRM_MODE_FLAG_INTERLACE); | |
10505 | ||
bb760063 DV |
10506 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
10507 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
10508 | DRM_MODE_FLAG_PHSYNC); | |
10509 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
10510 | DRM_MODE_FLAG_NHSYNC); | |
10511 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
10512 | DRM_MODE_FLAG_PVSYNC); | |
10513 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
10514 | DRM_MODE_FLAG_NVSYNC); | |
10515 | } | |
045ac3b5 | 10516 | |
37327abd VS |
10517 | PIPE_CONF_CHECK_I(pipe_src_w); |
10518 | PIPE_CONF_CHECK_I(pipe_src_h); | |
1bd1bd80 | 10519 | |
9953599b DV |
10520 | /* |
10521 | * FIXME: BIOS likes to set up a cloned config with lvds+external | |
10522 | * screen. Since we don't yet re-compute the pipe config when moving | |
10523 | * just the lvds port away to another pipe the sw tracking won't match. | |
10524 | * | |
10525 | * Proper atomic modesets with recomputed global state will fix this. | |
10526 | * Until then just don't check gmch state for inherited modes. | |
10527 | */ | |
10528 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) { | |
10529 | PIPE_CONF_CHECK_I(gmch_pfit.control); | |
10530 | /* pfit ratios are autocomputed by the hw on gen4+ */ | |
10531 | if (INTEL_INFO(dev)->gen < 4) | |
10532 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
10533 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); | |
10534 | } | |
10535 | ||
fd4daa9c CW |
10536 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
10537 | if (current_config->pch_pfit.enabled) { | |
10538 | PIPE_CONF_CHECK_I(pch_pfit.pos); | |
10539 | PIPE_CONF_CHECK_I(pch_pfit.size); | |
10540 | } | |
2fa2fe9a | 10541 | |
e59150dc JB |
10542 | /* BDW+ don't expose a synchronous way to read the state */ |
10543 | if (IS_HASWELL(dev)) | |
10544 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 10545 | |
282740f7 VS |
10546 | PIPE_CONF_CHECK_I(double_wide); |
10547 | ||
26804afd DV |
10548 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
10549 | ||
c0d43d62 | 10550 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 10551 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 10552 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
10553 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
10554 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 10555 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
3f4cd19f DL |
10556 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
10557 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
10558 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 10559 | |
42571aef VS |
10560 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
10561 | PIPE_CONF_CHECK_I(pipe_bpp); | |
10562 | ||
a9a7e98a JB |
10563 | PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock); |
10564 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); | |
5e550656 | 10565 | |
66e985c0 | 10566 | #undef PIPE_CONF_CHECK_X |
08a24034 | 10567 | #undef PIPE_CONF_CHECK_I |
b95af8be | 10568 | #undef PIPE_CONF_CHECK_I_ALT |
1bd1bd80 | 10569 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 10570 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 10571 | #undef PIPE_CONF_QUIRK |
88adfff1 | 10572 | |
0e8ffe1b DV |
10573 | return true; |
10574 | } | |
10575 | ||
08db6652 DL |
10576 | static void check_wm_state(struct drm_device *dev) |
10577 | { | |
10578 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10579 | struct skl_ddb_allocation hw_ddb, *sw_ddb; | |
10580 | struct intel_crtc *intel_crtc; | |
10581 | int plane; | |
10582 | ||
10583 | if (INTEL_INFO(dev)->gen < 9) | |
10584 | return; | |
10585 | ||
10586 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
10587 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
10588 | ||
10589 | for_each_intel_crtc(dev, intel_crtc) { | |
10590 | struct skl_ddb_entry *hw_entry, *sw_entry; | |
10591 | const enum pipe pipe = intel_crtc->pipe; | |
10592 | ||
10593 | if (!intel_crtc->active) | |
10594 | continue; | |
10595 | ||
10596 | /* planes */ | |
10597 | for_each_plane(pipe, plane) { | |
10598 | hw_entry = &hw_ddb.plane[pipe][plane]; | |
10599 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
10600 | ||
10601 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
10602 | continue; | |
10603 | ||
10604 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " | |
10605 | "(expected (%u,%u), found (%u,%u))\n", | |
10606 | pipe_name(pipe), plane + 1, | |
10607 | sw_entry->start, sw_entry->end, | |
10608 | hw_entry->start, hw_entry->end); | |
10609 | } | |
10610 | ||
10611 | /* cursor */ | |
10612 | hw_entry = &hw_ddb.cursor[pipe]; | |
10613 | sw_entry = &sw_ddb->cursor[pipe]; | |
10614 | ||
10615 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
10616 | continue; | |
10617 | ||
10618 | DRM_ERROR("mismatch in DDB state pipe %c cursor " | |
10619 | "(expected (%u,%u), found (%u,%u))\n", | |
10620 | pipe_name(pipe), | |
10621 | sw_entry->start, sw_entry->end, | |
10622 | hw_entry->start, hw_entry->end); | |
10623 | } | |
10624 | } | |
10625 | ||
91d1b4bd DV |
10626 | static void |
10627 | check_connector_state(struct drm_device *dev) | |
8af6cf88 | 10628 | { |
8af6cf88 DV |
10629 | struct intel_connector *connector; |
10630 | ||
10631 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
10632 | base.head) { | |
10633 | /* This also checks the encoder/connector hw state with the | |
10634 | * ->get_hw_state callbacks. */ | |
10635 | intel_connector_check_state(connector); | |
10636 | ||
10637 | WARN(&connector->new_encoder->base != connector->base.encoder, | |
10638 | "connector's staged encoder doesn't match current encoder\n"); | |
10639 | } | |
91d1b4bd DV |
10640 | } |
10641 | ||
10642 | static void | |
10643 | check_encoder_state(struct drm_device *dev) | |
10644 | { | |
10645 | struct intel_encoder *encoder; | |
10646 | struct intel_connector *connector; | |
8af6cf88 | 10647 | |
b2784e15 | 10648 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 DV |
10649 | bool enabled = false; |
10650 | bool active = false; | |
10651 | enum pipe pipe, tracked_pipe; | |
10652 | ||
10653 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
10654 | encoder->base.base.id, | |
8e329a03 | 10655 | encoder->base.name); |
8af6cf88 DV |
10656 | |
10657 | WARN(&encoder->new_crtc->base != encoder->base.crtc, | |
10658 | "encoder's stage crtc doesn't match current crtc\n"); | |
10659 | WARN(encoder->connectors_active && !encoder->base.crtc, | |
10660 | "encoder's active_connectors set, but no crtc\n"); | |
10661 | ||
10662 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
10663 | base.head) { | |
10664 | if (connector->base.encoder != &encoder->base) | |
10665 | continue; | |
10666 | enabled = true; | |
10667 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) | |
10668 | active = true; | |
10669 | } | |
0e32b39c DA |
10670 | /* |
10671 | * for MST connectors if we unplug the connector is gone | |
10672 | * away but the encoder is still connected to a crtc | |
10673 | * until a modeset happens in response to the hotplug. | |
10674 | */ | |
10675 | if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST) | |
10676 | continue; | |
10677 | ||
8af6cf88 DV |
10678 | WARN(!!encoder->base.crtc != enabled, |
10679 | "encoder's enabled state mismatch " | |
10680 | "(expected %i, found %i)\n", | |
10681 | !!encoder->base.crtc, enabled); | |
10682 | WARN(active && !encoder->base.crtc, | |
10683 | "active encoder with no crtc\n"); | |
10684 | ||
10685 | WARN(encoder->connectors_active != active, | |
10686 | "encoder's computed active state doesn't match tracked active state " | |
10687 | "(expected %i, found %i)\n", active, encoder->connectors_active); | |
10688 | ||
10689 | active = encoder->get_hw_state(encoder, &pipe); | |
10690 | WARN(active != encoder->connectors_active, | |
10691 | "encoder's hw state doesn't match sw tracking " | |
10692 | "(expected %i, found %i)\n", | |
10693 | encoder->connectors_active, active); | |
10694 | ||
10695 | if (!encoder->base.crtc) | |
10696 | continue; | |
10697 | ||
10698 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
10699 | WARN(active && pipe != tracked_pipe, | |
10700 | "active encoder's pipe doesn't match" | |
10701 | "(expected %i, found %i)\n", | |
10702 | tracked_pipe, pipe); | |
10703 | ||
10704 | } | |
91d1b4bd DV |
10705 | } |
10706 | ||
10707 | static void | |
10708 | check_crtc_state(struct drm_device *dev) | |
10709 | { | |
fbee40df | 10710 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
10711 | struct intel_crtc *crtc; |
10712 | struct intel_encoder *encoder; | |
10713 | struct intel_crtc_config pipe_config; | |
8af6cf88 | 10714 | |
d3fcc808 | 10715 | for_each_intel_crtc(dev, crtc) { |
8af6cf88 DV |
10716 | bool enabled = false; |
10717 | bool active = false; | |
10718 | ||
045ac3b5 JB |
10719 | memset(&pipe_config, 0, sizeof(pipe_config)); |
10720 | ||
8af6cf88 DV |
10721 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
10722 | crtc->base.base.id); | |
10723 | ||
10724 | WARN(crtc->active && !crtc->base.enabled, | |
10725 | "active crtc, but not enabled in sw tracking\n"); | |
10726 | ||
b2784e15 | 10727 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 DV |
10728 | if (encoder->base.crtc != &crtc->base) |
10729 | continue; | |
10730 | enabled = true; | |
10731 | if (encoder->connectors_active) | |
10732 | active = true; | |
10733 | } | |
6c49f241 | 10734 | |
8af6cf88 DV |
10735 | WARN(active != crtc->active, |
10736 | "crtc's computed active state doesn't match tracked active state " | |
10737 | "(expected %i, found %i)\n", active, crtc->active); | |
10738 | WARN(enabled != crtc->base.enabled, | |
10739 | "crtc's computed enabled state doesn't match tracked enabled state " | |
10740 | "(expected %i, found %i)\n", enabled, crtc->base.enabled); | |
10741 | ||
0e8ffe1b DV |
10742 | active = dev_priv->display.get_pipe_config(crtc, |
10743 | &pipe_config); | |
d62cf62a | 10744 | |
b6b5d049 VS |
10745 | /* hw state is inconsistent with the pipe quirk */ |
10746 | if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
10747 | (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
d62cf62a DV |
10748 | active = crtc->active; |
10749 | ||
b2784e15 | 10750 | for_each_intel_encoder(dev, encoder) { |
3eaba51c | 10751 | enum pipe pipe; |
6c49f241 DV |
10752 | if (encoder->base.crtc != &crtc->base) |
10753 | continue; | |
1d37b689 | 10754 | if (encoder->get_hw_state(encoder, &pipe)) |
6c49f241 DV |
10755 | encoder->get_config(encoder, &pipe_config); |
10756 | } | |
10757 | ||
0e8ffe1b DV |
10758 | WARN(crtc->active != active, |
10759 | "crtc active state doesn't match with hw state " | |
10760 | "(expected %i, found %i)\n", crtc->active, active); | |
10761 | ||
c0b03411 DV |
10762 | if (active && |
10763 | !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) { | |
10764 | WARN(1, "pipe state doesn't match!\n"); | |
10765 | intel_dump_pipe_config(crtc, &pipe_config, | |
10766 | "[hw state]"); | |
10767 | intel_dump_pipe_config(crtc, &crtc->config, | |
10768 | "[sw state]"); | |
10769 | } | |
8af6cf88 DV |
10770 | } |
10771 | } | |
10772 | ||
91d1b4bd DV |
10773 | static void |
10774 | check_shared_dpll_state(struct drm_device *dev) | |
10775 | { | |
fbee40df | 10776 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
10777 | struct intel_crtc *crtc; |
10778 | struct intel_dpll_hw_state dpll_hw_state; | |
10779 | int i; | |
5358901f DV |
10780 | |
10781 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
10782 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
10783 | int enabled_crtcs = 0, active_crtcs = 0; | |
10784 | bool active; | |
10785 | ||
10786 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
10787 | ||
10788 | DRM_DEBUG_KMS("%s\n", pll->name); | |
10789 | ||
10790 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
10791 | ||
3e369b76 | 10792 | WARN(pll->active > hweight32(pll->config.crtc_mask), |
5358901f | 10793 | "more active pll users than references: %i vs %i\n", |
3e369b76 | 10794 | pll->active, hweight32(pll->config.crtc_mask)); |
5358901f DV |
10795 | WARN(pll->active && !pll->on, |
10796 | "pll in active use but not on in sw tracking\n"); | |
35c95375 DV |
10797 | WARN(pll->on && !pll->active, |
10798 | "pll in on but not on in use in sw tracking\n"); | |
5358901f DV |
10799 | WARN(pll->on != active, |
10800 | "pll on state mismatch (expected %i, found %i)\n", | |
10801 | pll->on, active); | |
10802 | ||
d3fcc808 | 10803 | for_each_intel_crtc(dev, crtc) { |
5358901f DV |
10804 | if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll) |
10805 | enabled_crtcs++; | |
10806 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
10807 | active_crtcs++; | |
10808 | } | |
10809 | WARN(pll->active != active_crtcs, | |
10810 | "pll active crtcs mismatch (expected %i, found %i)\n", | |
10811 | pll->active, active_crtcs); | |
3e369b76 | 10812 | WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs, |
5358901f | 10813 | "pll enabled crtcs mismatch (expected %i, found %i)\n", |
3e369b76 | 10814 | hweight32(pll->config.crtc_mask), enabled_crtcs); |
66e985c0 | 10815 | |
3e369b76 | 10816 | WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state, |
66e985c0 DV |
10817 | sizeof(dpll_hw_state)), |
10818 | "pll hw state mismatch\n"); | |
5358901f | 10819 | } |
8af6cf88 DV |
10820 | } |
10821 | ||
91d1b4bd DV |
10822 | void |
10823 | intel_modeset_check_state(struct drm_device *dev) | |
10824 | { | |
08db6652 | 10825 | check_wm_state(dev); |
91d1b4bd DV |
10826 | check_connector_state(dev); |
10827 | check_encoder_state(dev); | |
10828 | check_crtc_state(dev); | |
10829 | check_shared_dpll_state(dev); | |
10830 | } | |
10831 | ||
18442d08 VS |
10832 | void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, |
10833 | int dotclock) | |
10834 | { | |
10835 | /* | |
10836 | * FDI already provided one idea for the dotclock. | |
10837 | * Yell if the encoder disagrees. | |
10838 | */ | |
241bfc38 | 10839 | WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock), |
18442d08 | 10840 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
241bfc38 | 10841 | pipe_config->adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
10842 | } |
10843 | ||
80715b2f VS |
10844 | static void update_scanline_offset(struct intel_crtc *crtc) |
10845 | { | |
10846 | struct drm_device *dev = crtc->base.dev; | |
10847 | ||
10848 | /* | |
10849 | * The scanline counter increments at the leading edge of hsync. | |
10850 | * | |
10851 | * On most platforms it starts counting from vtotal-1 on the | |
10852 | * first active line. That means the scanline counter value is | |
10853 | * always one less than what we would expect. Ie. just after | |
10854 | * start of vblank, which also occurs at start of hsync (on the | |
10855 | * last active line), the scanline counter will read vblank_start-1. | |
10856 | * | |
10857 | * On gen2 the scanline counter starts counting from 1 instead | |
10858 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
10859 | * to keep the value positive), instead of adding one. | |
10860 | * | |
10861 | * On HSW+ the behaviour of the scanline counter depends on the output | |
10862 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
10863 | * there's an extra 1 line difference. So we need to add two instead of | |
10864 | * one to the value. | |
10865 | */ | |
10866 | if (IS_GEN2(dev)) { | |
10867 | const struct drm_display_mode *mode = &crtc->config.adjusted_mode; | |
10868 | int vtotal; | |
10869 | ||
10870 | vtotal = mode->crtc_vtotal; | |
10871 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
10872 | vtotal /= 2; | |
10873 | ||
10874 | crtc->scanline_offset = vtotal - 1; | |
10875 | } else if (HAS_DDI(dev) && | |
409ee761 | 10876 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
10877 | crtc->scanline_offset = 2; |
10878 | } else | |
10879 | crtc->scanline_offset = 1; | |
10880 | } | |
10881 | ||
7f27126e JB |
10882 | static struct intel_crtc_config * |
10883 | intel_modeset_compute_config(struct drm_crtc *crtc, | |
10884 | struct drm_display_mode *mode, | |
10885 | struct drm_framebuffer *fb, | |
10886 | unsigned *modeset_pipes, | |
10887 | unsigned *prepare_pipes, | |
10888 | unsigned *disable_pipes) | |
10889 | { | |
10890 | struct intel_crtc_config *pipe_config = NULL; | |
10891 | ||
10892 | intel_modeset_affected_pipes(crtc, modeset_pipes, | |
10893 | prepare_pipes, disable_pipes); | |
10894 | ||
10895 | if ((*modeset_pipes) == 0) | |
10896 | goto out; | |
10897 | ||
10898 | /* | |
10899 | * Note this needs changes when we start tracking multiple modes | |
10900 | * and crtcs. At that point we'll need to compute the whole config | |
10901 | * (i.e. one pipe_config for each crtc) rather than just the one | |
10902 | * for this crtc. | |
10903 | */ | |
10904 | pipe_config = intel_modeset_pipe_config(crtc, fb, mode); | |
10905 | if (IS_ERR(pipe_config)) { | |
10906 | goto out; | |
10907 | } | |
10908 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, | |
10909 | "[modeset]"); | |
10910 | to_intel_crtc(crtc)->new_config = pipe_config; | |
10911 | ||
10912 | out: | |
10913 | return pipe_config; | |
10914 | } | |
10915 | ||
f30da187 DV |
10916 | static int __intel_set_mode(struct drm_crtc *crtc, |
10917 | struct drm_display_mode *mode, | |
7f27126e JB |
10918 | int x, int y, struct drm_framebuffer *fb, |
10919 | struct intel_crtc_config *pipe_config, | |
10920 | unsigned modeset_pipes, | |
10921 | unsigned prepare_pipes, | |
10922 | unsigned disable_pipes) | |
a6778b3c DV |
10923 | { |
10924 | struct drm_device *dev = crtc->dev; | |
fbee40df | 10925 | struct drm_i915_private *dev_priv = dev->dev_private; |
4b4b9238 | 10926 | struct drm_display_mode *saved_mode; |
25c5b266 | 10927 | struct intel_crtc *intel_crtc; |
c0c36b94 | 10928 | int ret = 0; |
a6778b3c | 10929 | |
4b4b9238 | 10930 | saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL); |
c0c36b94 CW |
10931 | if (!saved_mode) |
10932 | return -ENOMEM; | |
a6778b3c | 10933 | |
3ac18232 | 10934 | *saved_mode = crtc->mode; |
a6778b3c | 10935 | |
30a970c6 JB |
10936 | /* |
10937 | * See if the config requires any additional preparation, e.g. | |
10938 | * to adjust global state with pipes off. We need to do this | |
10939 | * here so we can get the modeset_pipe updated config for the new | |
10940 | * mode set on this crtc. For other crtcs we need to use the | |
10941 | * adjusted_mode bits in the crtc directly. | |
10942 | */ | |
c164f833 | 10943 | if (IS_VALLEYVIEW(dev)) { |
2f2d7aa1 | 10944 | valleyview_modeset_global_pipes(dev, &prepare_pipes); |
30a970c6 | 10945 | |
c164f833 VS |
10946 | /* may have added more to prepare_pipes than we should */ |
10947 | prepare_pipes &= ~disable_pipes; | |
10948 | } | |
10949 | ||
8bd31e67 ACO |
10950 | if (dev_priv->display.crtc_compute_clock) { |
10951 | unsigned clear_pipes = modeset_pipes | disable_pipes; | |
10952 | ||
10953 | ret = intel_shared_dpll_start_config(dev_priv, clear_pipes); | |
10954 | if (ret) | |
10955 | goto done; | |
10956 | ||
10957 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { | |
10958 | ret = dev_priv->display.crtc_compute_clock(intel_crtc); | |
10959 | if (ret) { | |
10960 | intel_shared_dpll_abort_config(dev_priv); | |
10961 | goto done; | |
10962 | } | |
10963 | } | |
10964 | } | |
10965 | ||
460da916 DV |
10966 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
10967 | intel_crtc_disable(&intel_crtc->base); | |
10968 | ||
ea9d758d DV |
10969 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
10970 | if (intel_crtc->base.enabled) | |
10971 | dev_priv->display.crtc_disable(&intel_crtc->base); | |
10972 | } | |
a6778b3c | 10973 | |
6c4c86f5 DV |
10974 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
10975 | * to set it here already despite that we pass it down the callchain. | |
7f27126e JB |
10976 | * |
10977 | * Note we'll need to fix this up when we start tracking multiple | |
10978 | * pipes; here we assume a single modeset_pipe and only track the | |
10979 | * single crtc and mode. | |
f6e5b160 | 10980 | */ |
b8cecdf5 | 10981 | if (modeset_pipes) { |
25c5b266 | 10982 | crtc->mode = *mode; |
b8cecdf5 DV |
10983 | /* mode_set/enable/disable functions rely on a correct pipe |
10984 | * config. */ | |
10985 | to_intel_crtc(crtc)->config = *pipe_config; | |
50741abc | 10986 | to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config; |
c326c0a9 VS |
10987 | |
10988 | /* | |
10989 | * Calculate and store various constants which | |
10990 | * are later needed by vblank and swap-completion | |
10991 | * timestamping. They are derived from true hwmode. | |
10992 | */ | |
10993 | drm_calc_timestamping_constants(crtc, | |
10994 | &pipe_config->adjusted_mode); | |
b8cecdf5 | 10995 | } |
7758a113 | 10996 | |
ea9d758d DV |
10997 | /* Only after disabling all output pipelines that will be changed can we |
10998 | * update the the output configuration. */ | |
10999 | intel_modeset_update_state(dev, prepare_pipes); | |
f6e5b160 | 11000 | |
50f6e502 | 11001 | modeset_update_crtc_power_domains(dev); |
47fab737 | 11002 | |
a6778b3c DV |
11003 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
11004 | * on the DPLL. | |
f6e5b160 | 11005 | */ |
25c5b266 | 11006 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
2ff8fde1 MR |
11007 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
11008 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb); | |
11009 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
4c10794f DV |
11010 | |
11011 | mutex_lock(&dev->struct_mutex); | |
850c4cdc | 11012 | ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, NULL); |
4c10794f DV |
11013 | if (ret != 0) { |
11014 | DRM_ERROR("pin & fence failed\n"); | |
11015 | mutex_unlock(&dev->struct_mutex); | |
11016 | goto done; | |
11017 | } | |
2ff8fde1 | 11018 | if (old_fb) |
a071fa00 | 11019 | intel_unpin_fb_obj(old_obj); |
a071fa00 DV |
11020 | i915_gem_track_fb(old_obj, obj, |
11021 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe)); | |
4c10794f DV |
11022 | mutex_unlock(&dev->struct_mutex); |
11023 | ||
11024 | crtc->primary->fb = fb; | |
11025 | crtc->x = x; | |
11026 | crtc->y = y; | |
a6778b3c DV |
11027 | } |
11028 | ||
11029 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ | |
80715b2f VS |
11030 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
11031 | update_scanline_offset(intel_crtc); | |
11032 | ||
25c5b266 | 11033 | dev_priv->display.crtc_enable(&intel_crtc->base); |
80715b2f | 11034 | } |
a6778b3c | 11035 | |
a6778b3c DV |
11036 | /* FIXME: add subpixel order */ |
11037 | done: | |
4b4b9238 | 11038 | if (ret && crtc->enabled) |
3ac18232 | 11039 | crtc->mode = *saved_mode; |
a6778b3c | 11040 | |
b8cecdf5 | 11041 | kfree(pipe_config); |
3ac18232 | 11042 | kfree(saved_mode); |
a6778b3c | 11043 | return ret; |
f6e5b160 CW |
11044 | } |
11045 | ||
7f27126e JB |
11046 | static int intel_set_mode_pipes(struct drm_crtc *crtc, |
11047 | struct drm_display_mode *mode, | |
11048 | int x, int y, struct drm_framebuffer *fb, | |
11049 | struct intel_crtc_config *pipe_config, | |
11050 | unsigned modeset_pipes, | |
11051 | unsigned prepare_pipes, | |
11052 | unsigned disable_pipes) | |
f30da187 DV |
11053 | { |
11054 | int ret; | |
11055 | ||
7f27126e JB |
11056 | ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes, |
11057 | prepare_pipes, disable_pipes); | |
f30da187 DV |
11058 | |
11059 | if (ret == 0) | |
11060 | intel_modeset_check_state(crtc->dev); | |
11061 | ||
11062 | return ret; | |
11063 | } | |
11064 | ||
7f27126e JB |
11065 | static int intel_set_mode(struct drm_crtc *crtc, |
11066 | struct drm_display_mode *mode, | |
11067 | int x, int y, struct drm_framebuffer *fb) | |
11068 | { | |
11069 | struct intel_crtc_config *pipe_config; | |
11070 | unsigned modeset_pipes, prepare_pipes, disable_pipes; | |
11071 | ||
11072 | pipe_config = intel_modeset_compute_config(crtc, mode, fb, | |
11073 | &modeset_pipes, | |
11074 | &prepare_pipes, | |
11075 | &disable_pipes); | |
11076 | ||
11077 | if (IS_ERR(pipe_config)) | |
11078 | return PTR_ERR(pipe_config); | |
11079 | ||
11080 | return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config, | |
11081 | modeset_pipes, prepare_pipes, | |
11082 | disable_pipes); | |
11083 | } | |
11084 | ||
c0c36b94 CW |
11085 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
11086 | { | |
f4510a27 | 11087 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb); |
c0c36b94 CW |
11088 | } |
11089 | ||
25c5b266 DV |
11090 | #undef for_each_intel_crtc_masked |
11091 | ||
d9e55608 DV |
11092 | static void intel_set_config_free(struct intel_set_config *config) |
11093 | { | |
11094 | if (!config) | |
11095 | return; | |
11096 | ||
1aa4b628 DV |
11097 | kfree(config->save_connector_encoders); |
11098 | kfree(config->save_encoder_crtcs); | |
7668851f | 11099 | kfree(config->save_crtc_enabled); |
d9e55608 DV |
11100 | kfree(config); |
11101 | } | |
11102 | ||
85f9eb71 DV |
11103 | static int intel_set_config_save_state(struct drm_device *dev, |
11104 | struct intel_set_config *config) | |
11105 | { | |
7668851f | 11106 | struct drm_crtc *crtc; |
85f9eb71 DV |
11107 | struct drm_encoder *encoder; |
11108 | struct drm_connector *connector; | |
11109 | int count; | |
11110 | ||
7668851f VS |
11111 | config->save_crtc_enabled = |
11112 | kcalloc(dev->mode_config.num_crtc, | |
11113 | sizeof(bool), GFP_KERNEL); | |
11114 | if (!config->save_crtc_enabled) | |
11115 | return -ENOMEM; | |
11116 | ||
1aa4b628 DV |
11117 | config->save_encoder_crtcs = |
11118 | kcalloc(dev->mode_config.num_encoder, | |
11119 | sizeof(struct drm_crtc *), GFP_KERNEL); | |
11120 | if (!config->save_encoder_crtcs) | |
85f9eb71 DV |
11121 | return -ENOMEM; |
11122 | ||
1aa4b628 DV |
11123 | config->save_connector_encoders = |
11124 | kcalloc(dev->mode_config.num_connector, | |
11125 | sizeof(struct drm_encoder *), GFP_KERNEL); | |
11126 | if (!config->save_connector_encoders) | |
85f9eb71 DV |
11127 | return -ENOMEM; |
11128 | ||
11129 | /* Copy data. Note that driver private data is not affected. | |
11130 | * Should anything bad happen only the expected state is | |
11131 | * restored, not the drivers personal bookkeeping. | |
11132 | */ | |
7668851f | 11133 | count = 0; |
70e1e0ec | 11134 | for_each_crtc(dev, crtc) { |
7668851f VS |
11135 | config->save_crtc_enabled[count++] = crtc->enabled; |
11136 | } | |
11137 | ||
85f9eb71 DV |
11138 | count = 0; |
11139 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1aa4b628 | 11140 | config->save_encoder_crtcs[count++] = encoder->crtc; |
85f9eb71 DV |
11141 | } |
11142 | ||
11143 | count = 0; | |
11144 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1aa4b628 | 11145 | config->save_connector_encoders[count++] = connector->encoder; |
85f9eb71 DV |
11146 | } |
11147 | ||
11148 | return 0; | |
11149 | } | |
11150 | ||
11151 | static void intel_set_config_restore_state(struct drm_device *dev, | |
11152 | struct intel_set_config *config) | |
11153 | { | |
7668851f | 11154 | struct intel_crtc *crtc; |
9a935856 DV |
11155 | struct intel_encoder *encoder; |
11156 | struct intel_connector *connector; | |
85f9eb71 DV |
11157 | int count; |
11158 | ||
7668851f | 11159 | count = 0; |
d3fcc808 | 11160 | for_each_intel_crtc(dev, crtc) { |
7668851f | 11161 | crtc->new_enabled = config->save_crtc_enabled[count++]; |
7bd0a8e7 VS |
11162 | |
11163 | if (crtc->new_enabled) | |
11164 | crtc->new_config = &crtc->config; | |
11165 | else | |
11166 | crtc->new_config = NULL; | |
7668851f VS |
11167 | } |
11168 | ||
85f9eb71 | 11169 | count = 0; |
b2784e15 | 11170 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
11171 | encoder->new_crtc = |
11172 | to_intel_crtc(config->save_encoder_crtcs[count++]); | |
85f9eb71 DV |
11173 | } |
11174 | ||
11175 | count = 0; | |
9a935856 DV |
11176 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
11177 | connector->new_encoder = | |
11178 | to_intel_encoder(config->save_connector_encoders[count++]); | |
85f9eb71 DV |
11179 | } |
11180 | } | |
11181 | ||
e3de42b6 | 11182 | static bool |
2e57f47d | 11183 | is_crtc_connector_off(struct drm_mode_set *set) |
e3de42b6 ID |
11184 | { |
11185 | int i; | |
11186 | ||
2e57f47d CW |
11187 | if (set->num_connectors == 0) |
11188 | return false; | |
11189 | ||
11190 | if (WARN_ON(set->connectors == NULL)) | |
11191 | return false; | |
11192 | ||
11193 | for (i = 0; i < set->num_connectors; i++) | |
11194 | if (set->connectors[i]->encoder && | |
11195 | set->connectors[i]->encoder->crtc == set->crtc && | |
11196 | set->connectors[i]->dpms != DRM_MODE_DPMS_ON) | |
e3de42b6 ID |
11197 | return true; |
11198 | ||
11199 | return false; | |
11200 | } | |
11201 | ||
5e2b584e DV |
11202 | static void |
11203 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, | |
11204 | struct intel_set_config *config) | |
11205 | { | |
11206 | ||
11207 | /* We should be able to check here if the fb has the same properties | |
11208 | * and then just flip_or_move it */ | |
2e57f47d CW |
11209 | if (is_crtc_connector_off(set)) { |
11210 | config->mode_changed = true; | |
f4510a27 | 11211 | } else if (set->crtc->primary->fb != set->fb) { |
3b150f08 MR |
11212 | /* |
11213 | * If we have no fb, we can only flip as long as the crtc is | |
11214 | * active, otherwise we need a full mode set. The crtc may | |
11215 | * be active if we've only disabled the primary plane, or | |
11216 | * in fastboot situations. | |
11217 | */ | |
f4510a27 | 11218 | if (set->crtc->primary->fb == NULL) { |
319d9827 JB |
11219 | struct intel_crtc *intel_crtc = |
11220 | to_intel_crtc(set->crtc); | |
11221 | ||
3b150f08 | 11222 | if (intel_crtc->active) { |
319d9827 JB |
11223 | DRM_DEBUG_KMS("crtc has no fb, will flip\n"); |
11224 | config->fb_changed = true; | |
11225 | } else { | |
11226 | DRM_DEBUG_KMS("inactive crtc, full mode set\n"); | |
11227 | config->mode_changed = true; | |
11228 | } | |
5e2b584e DV |
11229 | } else if (set->fb == NULL) { |
11230 | config->mode_changed = true; | |
72f4901e | 11231 | } else if (set->fb->pixel_format != |
f4510a27 | 11232 | set->crtc->primary->fb->pixel_format) { |
5e2b584e | 11233 | config->mode_changed = true; |
e3de42b6 | 11234 | } else { |
5e2b584e | 11235 | config->fb_changed = true; |
e3de42b6 | 11236 | } |
5e2b584e DV |
11237 | } |
11238 | ||
835c5873 | 11239 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
5e2b584e DV |
11240 | config->fb_changed = true; |
11241 | ||
11242 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { | |
11243 | DRM_DEBUG_KMS("modes are different, full mode set\n"); | |
11244 | drm_mode_debug_printmodeline(&set->crtc->mode); | |
11245 | drm_mode_debug_printmodeline(set->mode); | |
11246 | config->mode_changed = true; | |
11247 | } | |
a1d95703 CW |
11248 | |
11249 | DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n", | |
11250 | set->crtc->base.id, config->mode_changed, config->fb_changed); | |
5e2b584e DV |
11251 | } |
11252 | ||
2e431051 | 11253 | static int |
9a935856 DV |
11254 | intel_modeset_stage_output_state(struct drm_device *dev, |
11255 | struct drm_mode_set *set, | |
11256 | struct intel_set_config *config) | |
50f56119 | 11257 | { |
9a935856 DV |
11258 | struct intel_connector *connector; |
11259 | struct intel_encoder *encoder; | |
7668851f | 11260 | struct intel_crtc *crtc; |
f3f08572 | 11261 | int ro; |
50f56119 | 11262 | |
9abdda74 | 11263 | /* The upper layers ensure that we either disable a crtc or have a list |
9a935856 DV |
11264 | * of connectors. For paranoia, double-check this. */ |
11265 | WARN_ON(!set->fb && (set->num_connectors != 0)); | |
11266 | WARN_ON(set->fb && (set->num_connectors == 0)); | |
11267 | ||
9a935856 DV |
11268 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
11269 | base.head) { | |
11270 | /* Otherwise traverse passed in connector list and get encoders | |
11271 | * for them. */ | |
50f56119 | 11272 | for (ro = 0; ro < set->num_connectors; ro++) { |
9a935856 | 11273 | if (set->connectors[ro] == &connector->base) { |
0e32b39c | 11274 | connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe); |
50f56119 DV |
11275 | break; |
11276 | } | |
11277 | } | |
11278 | ||
9a935856 DV |
11279 | /* If we disable the crtc, disable all its connectors. Also, if |
11280 | * the connector is on the changing crtc but not on the new | |
11281 | * connector list, disable it. */ | |
11282 | if ((!set->fb || ro == set->num_connectors) && | |
11283 | connector->base.encoder && | |
11284 | connector->base.encoder->crtc == set->crtc) { | |
11285 | connector->new_encoder = NULL; | |
11286 | ||
11287 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", | |
11288 | connector->base.base.id, | |
c23cc417 | 11289 | connector->base.name); |
9a935856 DV |
11290 | } |
11291 | ||
11292 | ||
11293 | if (&connector->new_encoder->base != connector->base.encoder) { | |
50f56119 | 11294 | DRM_DEBUG_KMS("encoder changed, full mode switch\n"); |
5e2b584e | 11295 | config->mode_changed = true; |
50f56119 DV |
11296 | } |
11297 | } | |
9a935856 | 11298 | /* connector->new_encoder is now updated for all connectors. */ |
50f56119 | 11299 | |
9a935856 | 11300 | /* Update crtc of enabled connectors. */ |
9a935856 DV |
11301 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
11302 | base.head) { | |
7668851f VS |
11303 | struct drm_crtc *new_crtc; |
11304 | ||
9a935856 | 11305 | if (!connector->new_encoder) |
50f56119 DV |
11306 | continue; |
11307 | ||
9a935856 | 11308 | new_crtc = connector->new_encoder->base.crtc; |
50f56119 DV |
11309 | |
11310 | for (ro = 0; ro < set->num_connectors; ro++) { | |
9a935856 | 11311 | if (set->connectors[ro] == &connector->base) |
50f56119 DV |
11312 | new_crtc = set->crtc; |
11313 | } | |
11314 | ||
11315 | /* Make sure the new CRTC will work with the encoder */ | |
14509916 TR |
11316 | if (!drm_encoder_crtc_ok(&connector->new_encoder->base, |
11317 | new_crtc)) { | |
5e2b584e | 11318 | return -EINVAL; |
50f56119 | 11319 | } |
0e32b39c | 11320 | connector->new_encoder->new_crtc = to_intel_crtc(new_crtc); |
9a935856 DV |
11321 | |
11322 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", | |
11323 | connector->base.base.id, | |
c23cc417 | 11324 | connector->base.name, |
9a935856 DV |
11325 | new_crtc->base.id); |
11326 | } | |
11327 | ||
11328 | /* Check for any encoders that needs to be disabled. */ | |
b2784e15 | 11329 | for_each_intel_encoder(dev, encoder) { |
5a65f358 | 11330 | int num_connectors = 0; |
9a935856 DV |
11331 | list_for_each_entry(connector, |
11332 | &dev->mode_config.connector_list, | |
11333 | base.head) { | |
11334 | if (connector->new_encoder == encoder) { | |
11335 | WARN_ON(!connector->new_encoder->new_crtc); | |
5a65f358 | 11336 | num_connectors++; |
9a935856 DV |
11337 | } |
11338 | } | |
5a65f358 PZ |
11339 | |
11340 | if (num_connectors == 0) | |
11341 | encoder->new_crtc = NULL; | |
11342 | else if (num_connectors > 1) | |
11343 | return -EINVAL; | |
11344 | ||
9a935856 DV |
11345 | /* Only now check for crtc changes so we don't miss encoders |
11346 | * that will be disabled. */ | |
11347 | if (&encoder->new_crtc->base != encoder->base.crtc) { | |
50f56119 | 11348 | DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
5e2b584e | 11349 | config->mode_changed = true; |
50f56119 DV |
11350 | } |
11351 | } | |
9a935856 | 11352 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
0e32b39c DA |
11353 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
11354 | base.head) { | |
11355 | if (connector->new_encoder) | |
11356 | if (connector->new_encoder != connector->encoder) | |
11357 | connector->encoder = connector->new_encoder; | |
11358 | } | |
d3fcc808 | 11359 | for_each_intel_crtc(dev, crtc) { |
7668851f VS |
11360 | crtc->new_enabled = false; |
11361 | ||
b2784e15 | 11362 | for_each_intel_encoder(dev, encoder) { |
7668851f VS |
11363 | if (encoder->new_crtc == crtc) { |
11364 | crtc->new_enabled = true; | |
11365 | break; | |
11366 | } | |
11367 | } | |
11368 | ||
11369 | if (crtc->new_enabled != crtc->base.enabled) { | |
11370 | DRM_DEBUG_KMS("crtc %sabled, full mode switch\n", | |
11371 | crtc->new_enabled ? "en" : "dis"); | |
11372 | config->mode_changed = true; | |
11373 | } | |
7bd0a8e7 VS |
11374 | |
11375 | if (crtc->new_enabled) | |
11376 | crtc->new_config = &crtc->config; | |
11377 | else | |
11378 | crtc->new_config = NULL; | |
7668851f VS |
11379 | } |
11380 | ||
2e431051 DV |
11381 | return 0; |
11382 | } | |
11383 | ||
7d00a1f5 VS |
11384 | static void disable_crtc_nofb(struct intel_crtc *crtc) |
11385 | { | |
11386 | struct drm_device *dev = crtc->base.dev; | |
11387 | struct intel_encoder *encoder; | |
11388 | struct intel_connector *connector; | |
11389 | ||
11390 | DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n", | |
11391 | pipe_name(crtc->pipe)); | |
11392 | ||
11393 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { | |
11394 | if (connector->new_encoder && | |
11395 | connector->new_encoder->new_crtc == crtc) | |
11396 | connector->new_encoder = NULL; | |
11397 | } | |
11398 | ||
b2784e15 | 11399 | for_each_intel_encoder(dev, encoder) { |
7d00a1f5 VS |
11400 | if (encoder->new_crtc == crtc) |
11401 | encoder->new_crtc = NULL; | |
11402 | } | |
11403 | ||
11404 | crtc->new_enabled = false; | |
7bd0a8e7 | 11405 | crtc->new_config = NULL; |
7d00a1f5 VS |
11406 | } |
11407 | ||
2e431051 DV |
11408 | static int intel_crtc_set_config(struct drm_mode_set *set) |
11409 | { | |
11410 | struct drm_device *dev; | |
2e431051 DV |
11411 | struct drm_mode_set save_set; |
11412 | struct intel_set_config *config; | |
50f52756 JB |
11413 | struct intel_crtc_config *pipe_config; |
11414 | unsigned modeset_pipes, prepare_pipes, disable_pipes; | |
2e431051 | 11415 | int ret; |
2e431051 | 11416 | |
8d3e375e DV |
11417 | BUG_ON(!set); |
11418 | BUG_ON(!set->crtc); | |
11419 | BUG_ON(!set->crtc->helper_private); | |
2e431051 | 11420 | |
7e53f3a4 DV |
11421 | /* Enforce sane interface api - has been abused by the fb helper. */ |
11422 | BUG_ON(!set->mode && set->fb); | |
11423 | BUG_ON(set->fb && set->num_connectors == 0); | |
431e50f7 | 11424 | |
2e431051 DV |
11425 | if (set->fb) { |
11426 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", | |
11427 | set->crtc->base.id, set->fb->base.id, | |
11428 | (int)set->num_connectors, set->x, set->y); | |
11429 | } else { | |
11430 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); | |
2e431051 DV |
11431 | } |
11432 | ||
11433 | dev = set->crtc->dev; | |
11434 | ||
11435 | ret = -ENOMEM; | |
11436 | config = kzalloc(sizeof(*config), GFP_KERNEL); | |
11437 | if (!config) | |
11438 | goto out_config; | |
11439 | ||
11440 | ret = intel_set_config_save_state(dev, config); | |
11441 | if (ret) | |
11442 | goto out_config; | |
11443 | ||
11444 | save_set.crtc = set->crtc; | |
11445 | save_set.mode = &set->crtc->mode; | |
11446 | save_set.x = set->crtc->x; | |
11447 | save_set.y = set->crtc->y; | |
f4510a27 | 11448 | save_set.fb = set->crtc->primary->fb; |
2e431051 DV |
11449 | |
11450 | /* Compute whether we need a full modeset, only an fb base update or no | |
11451 | * change at all. In the future we might also check whether only the | |
11452 | * mode changed, e.g. for LVDS where we only change the panel fitter in | |
11453 | * such cases. */ | |
11454 | intel_set_config_compute_mode_changes(set, config); | |
11455 | ||
9a935856 | 11456 | ret = intel_modeset_stage_output_state(dev, set, config); |
2e431051 DV |
11457 | if (ret) |
11458 | goto fail; | |
11459 | ||
50f52756 JB |
11460 | pipe_config = intel_modeset_compute_config(set->crtc, set->mode, |
11461 | set->fb, | |
11462 | &modeset_pipes, | |
11463 | &prepare_pipes, | |
11464 | &disable_pipes); | |
20664591 | 11465 | if (IS_ERR(pipe_config)) { |
6ac0483b | 11466 | ret = PTR_ERR(pipe_config); |
50f52756 | 11467 | goto fail; |
20664591 JB |
11468 | } else if (pipe_config) { |
11469 | if (to_intel_crtc(set->crtc)->new_config->has_audio != | |
11470 | to_intel_crtc(set->crtc)->config.has_audio) | |
11471 | config->mode_changed = true; | |
11472 | ||
11473 | /* Force mode sets for any infoframe stuff */ | |
11474 | if (to_intel_crtc(set->crtc)->new_config->has_infoframe || | |
11475 | to_intel_crtc(set->crtc)->config.has_infoframe) | |
11476 | config->mode_changed = true; | |
11477 | } | |
50f52756 JB |
11478 | |
11479 | /* set_mode will free it in the mode_changed case */ | |
11480 | if (!config->mode_changed) | |
11481 | kfree(pipe_config); | |
11482 | ||
1f9954d0 JB |
11483 | intel_update_pipe_size(to_intel_crtc(set->crtc)); |
11484 | ||
5e2b584e | 11485 | if (config->mode_changed) { |
50f52756 JB |
11486 | ret = intel_set_mode_pipes(set->crtc, set->mode, |
11487 | set->x, set->y, set->fb, pipe_config, | |
11488 | modeset_pipes, prepare_pipes, | |
11489 | disable_pipes); | |
5e2b584e | 11490 | } else if (config->fb_changed) { |
3b150f08 MR |
11491 | struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc); |
11492 | ||
4878cae2 VS |
11493 | intel_crtc_wait_for_pending_flips(set->crtc); |
11494 | ||
4f660f49 | 11495 | ret = intel_pipe_set_base(set->crtc, |
94352cf9 | 11496 | set->x, set->y, set->fb); |
3b150f08 MR |
11497 | |
11498 | /* | |
11499 | * We need to make sure the primary plane is re-enabled if it | |
11500 | * has previously been turned off. | |
11501 | */ | |
11502 | if (!intel_crtc->primary_enabled && ret == 0) { | |
11503 | WARN_ON(!intel_crtc->active); | |
fdd508a6 | 11504 | intel_enable_primary_hw_plane(set->crtc->primary, set->crtc); |
3b150f08 MR |
11505 | } |
11506 | ||
7ca51a3a JB |
11507 | /* |
11508 | * In the fastboot case this may be our only check of the | |
11509 | * state after boot. It would be better to only do it on | |
11510 | * the first update, but we don't have a nice way of doing that | |
11511 | * (and really, set_config isn't used much for high freq page | |
11512 | * flipping, so increasing its cost here shouldn't be a big | |
11513 | * deal). | |
11514 | */ | |
d330a953 | 11515 | if (i915.fastboot && ret == 0) |
7ca51a3a | 11516 | intel_modeset_check_state(set->crtc->dev); |
50f56119 DV |
11517 | } |
11518 | ||
2d05eae1 | 11519 | if (ret) { |
bf67dfeb DV |
11520 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
11521 | set->crtc->base.id, ret); | |
50f56119 | 11522 | fail: |
2d05eae1 | 11523 | intel_set_config_restore_state(dev, config); |
50f56119 | 11524 | |
7d00a1f5 VS |
11525 | /* |
11526 | * HACK: if the pipe was on, but we didn't have a framebuffer, | |
11527 | * force the pipe off to avoid oopsing in the modeset code | |
11528 | * due to fb==NULL. This should only happen during boot since | |
11529 | * we don't yet reconstruct the FB from the hardware state. | |
11530 | */ | |
11531 | if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb) | |
11532 | disable_crtc_nofb(to_intel_crtc(save_set.crtc)); | |
11533 | ||
2d05eae1 CW |
11534 | /* Try to restore the config */ |
11535 | if (config->mode_changed && | |
11536 | intel_set_mode(save_set.crtc, save_set.mode, | |
11537 | save_set.x, save_set.y, save_set.fb)) | |
11538 | DRM_ERROR("failed to restore config after modeset failure\n"); | |
11539 | } | |
50f56119 | 11540 | |
d9e55608 DV |
11541 | out_config: |
11542 | intel_set_config_free(config); | |
50f56119 DV |
11543 | return ret; |
11544 | } | |
f6e5b160 CW |
11545 | |
11546 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
f6e5b160 | 11547 | .gamma_set = intel_crtc_gamma_set, |
50f56119 | 11548 | .set_config = intel_crtc_set_config, |
f6e5b160 CW |
11549 | .destroy = intel_crtc_destroy, |
11550 | .page_flip = intel_crtc_page_flip, | |
11551 | }; | |
11552 | ||
5358901f DV |
11553 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
11554 | struct intel_shared_dpll *pll, | |
11555 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 11556 | { |
5358901f | 11557 | uint32_t val; |
ee7b9f93 | 11558 | |
f458ebbc | 11559 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
bd2bb1b9 PZ |
11560 | return false; |
11561 | ||
5358901f | 11562 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
11563 | hw_state->dpll = val; |
11564 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
11565 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
11566 | |
11567 | return val & DPLL_VCO_ENABLE; | |
11568 | } | |
11569 | ||
15bdd4cf DV |
11570 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
11571 | struct intel_shared_dpll *pll) | |
11572 | { | |
3e369b76 ACO |
11573 | I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0); |
11574 | I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1); | |
15bdd4cf DV |
11575 | } |
11576 | ||
e7b903d2 DV |
11577 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
11578 | struct intel_shared_dpll *pll) | |
11579 | { | |
e7b903d2 | 11580 | /* PCH refclock must be enabled first */ |
89eff4be | 11581 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 11582 | |
3e369b76 | 11583 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf DV |
11584 | |
11585 | /* Wait for the clocks to stabilize. */ | |
11586 | POSTING_READ(PCH_DPLL(pll->id)); | |
11587 | udelay(150); | |
11588 | ||
11589 | /* The pixel multiplier can only be updated once the | |
11590 | * DPLL is enabled and the clocks are stable. | |
11591 | * | |
11592 | * So write it again. | |
11593 | */ | |
3e369b76 | 11594 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf | 11595 | POSTING_READ(PCH_DPLL(pll->id)); |
e7b903d2 DV |
11596 | udelay(200); |
11597 | } | |
11598 | ||
11599 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
11600 | struct intel_shared_dpll *pll) | |
11601 | { | |
11602 | struct drm_device *dev = dev_priv->dev; | |
11603 | struct intel_crtc *crtc; | |
e7b903d2 DV |
11604 | |
11605 | /* Make sure no transcoder isn't still depending on us. */ | |
d3fcc808 | 11606 | for_each_intel_crtc(dev, crtc) { |
e7b903d2 DV |
11607 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
11608 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
11609 | } |
11610 | ||
15bdd4cf DV |
11611 | I915_WRITE(PCH_DPLL(pll->id), 0); |
11612 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
11613 | udelay(200); |
11614 | } | |
11615 | ||
46edb027 DV |
11616 | static char *ibx_pch_dpll_names[] = { |
11617 | "PCH DPLL A", | |
11618 | "PCH DPLL B", | |
11619 | }; | |
11620 | ||
7c74ade1 | 11621 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 11622 | { |
e7b903d2 | 11623 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
11624 | int i; |
11625 | ||
7c74ade1 | 11626 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 11627 | |
e72f9fbf | 11628 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
11629 | dev_priv->shared_dplls[i].id = i; |
11630 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 11631 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
11632 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
11633 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
11634 | dev_priv->shared_dplls[i].get_hw_state = |
11635 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
11636 | } |
11637 | } | |
11638 | ||
7c74ade1 DV |
11639 | static void intel_shared_dpll_init(struct drm_device *dev) |
11640 | { | |
e7b903d2 | 11641 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 | 11642 | |
9cd86933 DV |
11643 | if (HAS_DDI(dev)) |
11644 | intel_ddi_pll_init(dev); | |
11645 | else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
7c74ade1 DV |
11646 | ibx_pch_dpll_init(dev); |
11647 | else | |
11648 | dev_priv->num_shared_dpll = 0; | |
11649 | ||
11650 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
11651 | } |
11652 | ||
465c120c MR |
11653 | static int |
11654 | intel_primary_plane_disable(struct drm_plane *plane) | |
11655 | { | |
11656 | struct drm_device *dev = plane->dev; | |
465c120c MR |
11657 | struct intel_crtc *intel_crtc; |
11658 | ||
11659 | if (!plane->fb) | |
11660 | return 0; | |
11661 | ||
11662 | BUG_ON(!plane->crtc); | |
11663 | ||
11664 | intel_crtc = to_intel_crtc(plane->crtc); | |
11665 | ||
11666 | /* | |
11667 | * Even though we checked plane->fb above, it's still possible that | |
11668 | * the primary plane has been implicitly disabled because the crtc | |
11669 | * coordinates given weren't visible, or because we detected | |
11670 | * that it was 100% covered by a sprite plane. Or, the CRTC may be | |
11671 | * off and we've set a fb, but haven't actually turned on the CRTC yet. | |
11672 | * In either case, we need to unpin the FB and let the fb pointer get | |
11673 | * updated, but otherwise we don't need to touch the hardware. | |
11674 | */ | |
11675 | if (!intel_crtc->primary_enabled) | |
11676 | goto disable_unpin; | |
11677 | ||
11678 | intel_crtc_wait_for_pending_flips(plane->crtc); | |
fdd508a6 VS |
11679 | intel_disable_primary_hw_plane(plane, plane->crtc); |
11680 | ||
465c120c | 11681 | disable_unpin: |
4c34574f | 11682 | mutex_lock(&dev->struct_mutex); |
2ff8fde1 | 11683 | i915_gem_track_fb(intel_fb_obj(plane->fb), NULL, |
a071fa00 | 11684 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe)); |
2ff8fde1 | 11685 | intel_unpin_fb_obj(intel_fb_obj(plane->fb)); |
4c34574f | 11686 | mutex_unlock(&dev->struct_mutex); |
465c120c MR |
11687 | plane->fb = NULL; |
11688 | ||
11689 | return 0; | |
11690 | } | |
11691 | ||
11692 | static int | |
3c692a41 GP |
11693 | intel_check_primary_plane(struct drm_plane *plane, |
11694 | struct intel_plane_state *state) | |
11695 | { | |
11696 | struct drm_crtc *crtc = state->crtc; | |
11697 | struct drm_framebuffer *fb = state->fb; | |
11698 | struct drm_rect *dest = &state->dst; | |
11699 | struct drm_rect *src = &state->src; | |
11700 | const struct drm_rect *clip = &state->clip; | |
ccc759dc | 11701 | |
3ead8bb2 GP |
11702 | return drm_plane_helper_check_update(plane, crtc, fb, |
11703 | src, dest, clip, | |
11704 | DRM_PLANE_HELPER_NO_SCALING, | |
11705 | DRM_PLANE_HELPER_NO_SCALING, | |
11706 | false, true, &state->visible); | |
3c692a41 GP |
11707 | } |
11708 | ||
11709 | static int | |
14af293f GP |
11710 | intel_prepare_primary_plane(struct drm_plane *plane, |
11711 | struct intel_plane_state *state) | |
465c120c | 11712 | { |
3c692a41 GP |
11713 | struct drm_crtc *crtc = state->crtc; |
11714 | struct drm_framebuffer *fb = state->fb; | |
465c120c | 11715 | struct drm_device *dev = crtc->dev; |
465c120c | 11716 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ccc759dc | 11717 | enum pipe pipe = intel_crtc->pipe; |
2ff8fde1 MR |
11718 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
11719 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb); | |
465c120c MR |
11720 | int ret; |
11721 | ||
465c120c MR |
11722 | intel_crtc_wait_for_pending_flips(crtc); |
11723 | ||
ccc759dc GP |
11724 | if (intel_crtc_has_pending_flip(crtc)) { |
11725 | DRM_ERROR("pipe is still busy with an old pageflip\n"); | |
11726 | return -EBUSY; | |
11727 | } | |
11728 | ||
14af293f | 11729 | if (old_obj != obj) { |
4c34574f | 11730 | mutex_lock(&dev->struct_mutex); |
850c4cdc | 11731 | ret = intel_pin_and_fence_fb_obj(plane, fb, NULL); |
ccc759dc GP |
11732 | if (ret == 0) |
11733 | i915_gem_track_fb(old_obj, obj, | |
11734 | INTEL_FRONTBUFFER_PRIMARY(pipe)); | |
11735 | mutex_unlock(&dev->struct_mutex); | |
11736 | if (ret != 0) { | |
11737 | DRM_DEBUG_KMS("pin & fence failed\n"); | |
11738 | return ret; | |
11739 | } | |
11740 | } | |
11741 | ||
14af293f GP |
11742 | return 0; |
11743 | } | |
11744 | ||
11745 | static void | |
11746 | intel_commit_primary_plane(struct drm_plane *plane, | |
11747 | struct intel_plane_state *state) | |
11748 | { | |
11749 | struct drm_crtc *crtc = state->crtc; | |
11750 | struct drm_framebuffer *fb = state->fb; | |
11751 | struct drm_device *dev = crtc->dev; | |
11752 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11753 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11754 | enum pipe pipe = intel_crtc->pipe; | |
11755 | struct drm_framebuffer *old_fb = plane->fb; | |
11756 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
11757 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb); | |
11758 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
11759 | struct drm_rect *src = &state->src; | |
11760 | ||
ccc759dc | 11761 | crtc->primary->fb = fb; |
9dc806fc MR |
11762 | crtc->x = src->x1 >> 16; |
11763 | crtc->y = src->y1 >> 16; | |
ccc759dc GP |
11764 | |
11765 | intel_plane->crtc_x = state->orig_dst.x1; | |
11766 | intel_plane->crtc_y = state->orig_dst.y1; | |
11767 | intel_plane->crtc_w = drm_rect_width(&state->orig_dst); | |
11768 | intel_plane->crtc_h = drm_rect_height(&state->orig_dst); | |
11769 | intel_plane->src_x = state->orig_src.x1; | |
11770 | intel_plane->src_y = state->orig_src.y1; | |
11771 | intel_plane->src_w = drm_rect_width(&state->orig_src); | |
11772 | intel_plane->src_h = drm_rect_height(&state->orig_src); | |
11773 | intel_plane->obj = obj; | |
4c34574f | 11774 | |
ccc759dc | 11775 | if (intel_crtc->active) { |
465c120c | 11776 | /* |
ccc759dc GP |
11777 | * FBC does not work on some platforms for rotated |
11778 | * planes, so disable it when rotation is not 0 and | |
11779 | * update it when rotation is set back to 0. | |
11780 | * | |
11781 | * FIXME: This is redundant with the fbc update done in | |
11782 | * the primary plane enable function except that that | |
11783 | * one is done too late. We eventually need to unify | |
11784 | * this. | |
465c120c | 11785 | */ |
ccc759dc GP |
11786 | if (intel_crtc->primary_enabled && |
11787 | INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && | |
11788 | dev_priv->fbc.plane == intel_crtc->plane && | |
11789 | intel_plane->rotation != BIT(DRM_ROTATE_0)) { | |
11790 | intel_disable_fbc(dev); | |
465c120c MR |
11791 | } |
11792 | ||
ccc759dc GP |
11793 | if (state->visible) { |
11794 | bool was_enabled = intel_crtc->primary_enabled; | |
465c120c | 11795 | |
ccc759dc GP |
11796 | /* FIXME: kill this fastboot hack */ |
11797 | intel_update_pipe_size(intel_crtc); | |
465c120c | 11798 | |
ccc759dc | 11799 | intel_crtc->primary_enabled = true; |
465c120c | 11800 | |
ccc759dc GP |
11801 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
11802 | crtc->x, crtc->y); | |
4c34574f | 11803 | |
48404c1e | 11804 | /* |
ccc759dc GP |
11805 | * BDW signals flip done immediately if the plane |
11806 | * is disabled, even if the plane enable is already | |
11807 | * armed to occur at the next vblank :( | |
48404c1e | 11808 | */ |
ccc759dc GP |
11809 | if (IS_BROADWELL(dev) && !was_enabled) |
11810 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
11811 | } else { | |
11812 | /* | |
11813 | * If clipping results in a non-visible primary plane, | |
11814 | * we'll disable the primary plane. Note that this is | |
11815 | * a bit different than what happens if userspace | |
11816 | * explicitly disables the plane by passing fb=0 | |
11817 | * because plane->fb still gets set and pinned. | |
11818 | */ | |
11819 | intel_disable_primary_hw_plane(plane, crtc); | |
48404c1e | 11820 | } |
465c120c | 11821 | |
ccc759dc GP |
11822 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
11823 | ||
11824 | mutex_lock(&dev->struct_mutex); | |
11825 | intel_update_fbc(dev); | |
11826 | mutex_unlock(&dev->struct_mutex); | |
ce54d85a | 11827 | } |
465c120c | 11828 | |
ccc759dc GP |
11829 | if (old_fb && old_fb != fb) { |
11830 | if (intel_crtc->active) | |
11831 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
11832 | ||
11833 | mutex_lock(&dev->struct_mutex); | |
11834 | intel_unpin_fb_obj(old_obj); | |
11835 | mutex_unlock(&dev->struct_mutex); | |
11836 | } | |
465c120c MR |
11837 | } |
11838 | ||
3c692a41 GP |
11839 | static int |
11840 | intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc, | |
11841 | struct drm_framebuffer *fb, int crtc_x, int crtc_y, | |
11842 | unsigned int crtc_w, unsigned int crtc_h, | |
11843 | uint32_t src_x, uint32_t src_y, | |
11844 | uint32_t src_w, uint32_t src_h) | |
11845 | { | |
11846 | struct intel_plane_state state; | |
11847 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11848 | int ret; | |
11849 | ||
11850 | state.crtc = crtc; | |
11851 | state.fb = fb; | |
11852 | ||
11853 | /* sample coordinates in 16.16 fixed point */ | |
11854 | state.src.x1 = src_x; | |
11855 | state.src.x2 = src_x + src_w; | |
11856 | state.src.y1 = src_y; | |
11857 | state.src.y2 = src_y + src_h; | |
11858 | ||
11859 | /* integer pixels */ | |
11860 | state.dst.x1 = crtc_x; | |
11861 | state.dst.x2 = crtc_x + crtc_w; | |
11862 | state.dst.y1 = crtc_y; | |
11863 | state.dst.y2 = crtc_y + crtc_h; | |
11864 | ||
11865 | state.clip.x1 = 0; | |
11866 | state.clip.y1 = 0; | |
11867 | state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0; | |
11868 | state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0; | |
11869 | ||
11870 | state.orig_src = state.src; | |
11871 | state.orig_dst = state.dst; | |
11872 | ||
11873 | ret = intel_check_primary_plane(plane, &state); | |
11874 | if (ret) | |
11875 | return ret; | |
11876 | ||
14af293f GP |
11877 | ret = intel_prepare_primary_plane(plane, &state); |
11878 | if (ret) | |
3c692a41 GP |
11879 | return ret; |
11880 | ||
11881 | intel_commit_primary_plane(plane, &state); | |
11882 | ||
11883 | return 0; | |
11884 | } | |
11885 | ||
3d7d6510 MR |
11886 | /* Common destruction function for both primary and cursor planes */ |
11887 | static void intel_plane_destroy(struct drm_plane *plane) | |
465c120c MR |
11888 | { |
11889 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
11890 | drm_plane_cleanup(plane); | |
11891 | kfree(intel_plane); | |
11892 | } | |
11893 | ||
11894 | static const struct drm_plane_funcs intel_primary_plane_funcs = { | |
11895 | .update_plane = intel_primary_plane_setplane, | |
11896 | .disable_plane = intel_primary_plane_disable, | |
3d7d6510 | 11897 | .destroy = intel_plane_destroy, |
48404c1e | 11898 | .set_property = intel_plane_set_property |
465c120c MR |
11899 | }; |
11900 | ||
11901 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
11902 | int pipe) | |
11903 | { | |
11904 | struct intel_plane *primary; | |
11905 | const uint32_t *intel_primary_formats; | |
11906 | int num_formats; | |
11907 | ||
11908 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
11909 | if (primary == NULL) | |
11910 | return NULL; | |
11911 | ||
11912 | primary->can_scale = false; | |
11913 | primary->max_downscale = 1; | |
11914 | primary->pipe = pipe; | |
11915 | primary->plane = pipe; | |
48404c1e | 11916 | primary->rotation = BIT(DRM_ROTATE_0); |
465c120c MR |
11917 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
11918 | primary->plane = !pipe; | |
11919 | ||
11920 | if (INTEL_INFO(dev)->gen <= 3) { | |
11921 | intel_primary_formats = intel_primary_formats_gen2; | |
11922 | num_formats = ARRAY_SIZE(intel_primary_formats_gen2); | |
11923 | } else { | |
11924 | intel_primary_formats = intel_primary_formats_gen4; | |
11925 | num_formats = ARRAY_SIZE(intel_primary_formats_gen4); | |
11926 | } | |
11927 | ||
11928 | drm_universal_plane_init(dev, &primary->base, 0, | |
11929 | &intel_primary_plane_funcs, | |
11930 | intel_primary_formats, num_formats, | |
11931 | DRM_PLANE_TYPE_PRIMARY); | |
48404c1e SJ |
11932 | |
11933 | if (INTEL_INFO(dev)->gen >= 4) { | |
11934 | if (!dev->mode_config.rotation_property) | |
11935 | dev->mode_config.rotation_property = | |
11936 | drm_mode_create_rotation_property(dev, | |
11937 | BIT(DRM_ROTATE_0) | | |
11938 | BIT(DRM_ROTATE_180)); | |
11939 | if (dev->mode_config.rotation_property) | |
11940 | drm_object_attach_property(&primary->base.base, | |
11941 | dev->mode_config.rotation_property, | |
11942 | primary->rotation); | |
11943 | } | |
11944 | ||
465c120c MR |
11945 | return &primary->base; |
11946 | } | |
11947 | ||
3d7d6510 MR |
11948 | static int |
11949 | intel_cursor_plane_disable(struct drm_plane *plane) | |
11950 | { | |
11951 | if (!plane->fb) | |
11952 | return 0; | |
11953 | ||
11954 | BUG_ON(!plane->crtc); | |
11955 | ||
11956 | return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0); | |
11957 | } | |
11958 | ||
11959 | static int | |
852e787c GP |
11960 | intel_check_cursor_plane(struct drm_plane *plane, |
11961 | struct intel_plane_state *state) | |
3d7d6510 | 11962 | { |
852e787c | 11963 | struct drm_crtc *crtc = state->crtc; |
757f9a3e | 11964 | struct drm_device *dev = crtc->dev; |
852e787c GP |
11965 | struct drm_framebuffer *fb = state->fb; |
11966 | struct drm_rect *dest = &state->dst; | |
11967 | struct drm_rect *src = &state->src; | |
11968 | const struct drm_rect *clip = &state->clip; | |
757f9a3e GP |
11969 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
11970 | int crtc_w, crtc_h; | |
11971 | unsigned stride; | |
11972 | int ret; | |
3d7d6510 | 11973 | |
757f9a3e | 11974 | ret = drm_plane_helper_check_update(plane, crtc, fb, |
852e787c | 11975 | src, dest, clip, |
3d7d6510 MR |
11976 | DRM_PLANE_HELPER_NO_SCALING, |
11977 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c | 11978 | true, true, &state->visible); |
757f9a3e GP |
11979 | if (ret) |
11980 | return ret; | |
11981 | ||
11982 | ||
11983 | /* if we want to turn off the cursor ignore width and height */ | |
11984 | if (!obj) | |
11985 | return 0; | |
11986 | ||
757f9a3e GP |
11987 | /* Check for which cursor types we support */ |
11988 | crtc_w = drm_rect_width(&state->orig_dst); | |
11989 | crtc_h = drm_rect_height(&state->orig_dst); | |
11990 | if (!cursor_size_ok(dev, crtc_w, crtc_h)) { | |
11991 | DRM_DEBUG("Cursor dimension not supported\n"); | |
11992 | return -EINVAL; | |
11993 | } | |
11994 | ||
11995 | stride = roundup_pow_of_two(crtc_w) * 4; | |
11996 | if (obj->base.size < stride * crtc_h) { | |
11997 | DRM_DEBUG_KMS("buffer is too small\n"); | |
11998 | return -ENOMEM; | |
11999 | } | |
12000 | ||
e391ea88 GP |
12001 | if (fb == crtc->cursor->fb) |
12002 | return 0; | |
12003 | ||
757f9a3e GP |
12004 | /* we only need to pin inside GTT if cursor is non-phy */ |
12005 | mutex_lock(&dev->struct_mutex); | |
12006 | if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) { | |
12007 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); | |
12008 | ret = -EINVAL; | |
12009 | } | |
12010 | mutex_unlock(&dev->struct_mutex); | |
12011 | ||
12012 | return ret; | |
852e787c | 12013 | } |
3d7d6510 | 12014 | |
852e787c GP |
12015 | static int |
12016 | intel_commit_cursor_plane(struct drm_plane *plane, | |
12017 | struct intel_plane_state *state) | |
12018 | { | |
12019 | struct drm_crtc *crtc = state->crtc; | |
12020 | struct drm_framebuffer *fb = state->fb; | |
12021 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
a919db90 | 12022 | struct intel_plane *intel_plane = to_intel_plane(plane); |
852e787c GP |
12023 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
12024 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
12025 | int crtc_w, crtc_h; | |
12026 | ||
12027 | crtc->cursor_x = state->orig_dst.x1; | |
12028 | crtc->cursor_y = state->orig_dst.y1; | |
a919db90 SJ |
12029 | |
12030 | intel_plane->crtc_x = state->orig_dst.x1; | |
12031 | intel_plane->crtc_y = state->orig_dst.y1; | |
12032 | intel_plane->crtc_w = drm_rect_width(&state->orig_dst); | |
12033 | intel_plane->crtc_h = drm_rect_height(&state->orig_dst); | |
12034 | intel_plane->src_x = state->orig_src.x1; | |
12035 | intel_plane->src_y = state->orig_src.y1; | |
12036 | intel_plane->src_w = drm_rect_width(&state->orig_src); | |
12037 | intel_plane->src_h = drm_rect_height(&state->orig_src); | |
12038 | intel_plane->obj = obj; | |
12039 | ||
3d7d6510 | 12040 | if (fb != crtc->cursor->fb) { |
852e787c GP |
12041 | crtc_w = drm_rect_width(&state->orig_dst); |
12042 | crtc_h = drm_rect_height(&state->orig_dst); | |
3d7d6510 MR |
12043 | return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h); |
12044 | } else { | |
852e787c | 12045 | intel_crtc_update_cursor(crtc, state->visible); |
4ed91096 DV |
12046 | |
12047 | intel_frontbuffer_flip(crtc->dev, | |
12048 | INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe)); | |
12049 | ||
3d7d6510 MR |
12050 | return 0; |
12051 | } | |
12052 | } | |
852e787c GP |
12053 | |
12054 | static int | |
12055 | intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, | |
12056 | struct drm_framebuffer *fb, int crtc_x, int crtc_y, | |
12057 | unsigned int crtc_w, unsigned int crtc_h, | |
12058 | uint32_t src_x, uint32_t src_y, | |
12059 | uint32_t src_w, uint32_t src_h) | |
12060 | { | |
12061 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12062 | struct intel_plane_state state; | |
12063 | int ret; | |
12064 | ||
12065 | state.crtc = crtc; | |
12066 | state.fb = fb; | |
12067 | ||
12068 | /* sample coordinates in 16.16 fixed point */ | |
12069 | state.src.x1 = src_x; | |
12070 | state.src.x2 = src_x + src_w; | |
12071 | state.src.y1 = src_y; | |
12072 | state.src.y2 = src_y + src_h; | |
12073 | ||
12074 | /* integer pixels */ | |
12075 | state.dst.x1 = crtc_x; | |
12076 | state.dst.x2 = crtc_x + crtc_w; | |
12077 | state.dst.y1 = crtc_y; | |
12078 | state.dst.y2 = crtc_y + crtc_h; | |
12079 | ||
12080 | state.clip.x1 = 0; | |
12081 | state.clip.y1 = 0; | |
12082 | state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0; | |
12083 | state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0; | |
12084 | ||
12085 | state.orig_src = state.src; | |
12086 | state.orig_dst = state.dst; | |
12087 | ||
12088 | ret = intel_check_cursor_plane(plane, &state); | |
12089 | if (ret) | |
12090 | return ret; | |
12091 | ||
12092 | return intel_commit_cursor_plane(plane, &state); | |
12093 | } | |
12094 | ||
3d7d6510 MR |
12095 | static const struct drm_plane_funcs intel_cursor_plane_funcs = { |
12096 | .update_plane = intel_cursor_plane_update, | |
12097 | .disable_plane = intel_cursor_plane_disable, | |
12098 | .destroy = intel_plane_destroy, | |
4398ad45 | 12099 | .set_property = intel_plane_set_property, |
3d7d6510 MR |
12100 | }; |
12101 | ||
12102 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, | |
12103 | int pipe) | |
12104 | { | |
12105 | struct intel_plane *cursor; | |
12106 | ||
12107 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
12108 | if (cursor == NULL) | |
12109 | return NULL; | |
12110 | ||
12111 | cursor->can_scale = false; | |
12112 | cursor->max_downscale = 1; | |
12113 | cursor->pipe = pipe; | |
12114 | cursor->plane = pipe; | |
4398ad45 | 12115 | cursor->rotation = BIT(DRM_ROTATE_0); |
3d7d6510 MR |
12116 | |
12117 | drm_universal_plane_init(dev, &cursor->base, 0, | |
12118 | &intel_cursor_plane_funcs, | |
12119 | intel_cursor_formats, | |
12120 | ARRAY_SIZE(intel_cursor_formats), | |
12121 | DRM_PLANE_TYPE_CURSOR); | |
4398ad45 VS |
12122 | |
12123 | if (INTEL_INFO(dev)->gen >= 4) { | |
12124 | if (!dev->mode_config.rotation_property) | |
12125 | dev->mode_config.rotation_property = | |
12126 | drm_mode_create_rotation_property(dev, | |
12127 | BIT(DRM_ROTATE_0) | | |
12128 | BIT(DRM_ROTATE_180)); | |
12129 | if (dev->mode_config.rotation_property) | |
12130 | drm_object_attach_property(&cursor->base.base, | |
12131 | dev->mode_config.rotation_property, | |
12132 | cursor->rotation); | |
12133 | } | |
12134 | ||
3d7d6510 MR |
12135 | return &cursor->base; |
12136 | } | |
12137 | ||
b358d0a6 | 12138 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 12139 | { |
fbee40df | 12140 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 12141 | struct intel_crtc *intel_crtc; |
3d7d6510 MR |
12142 | struct drm_plane *primary = NULL; |
12143 | struct drm_plane *cursor = NULL; | |
465c120c | 12144 | int i, ret; |
79e53945 | 12145 | |
955382f3 | 12146 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
12147 | if (intel_crtc == NULL) |
12148 | return; | |
12149 | ||
465c120c | 12150 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
12151 | if (!primary) |
12152 | goto fail; | |
12153 | ||
12154 | cursor = intel_cursor_plane_create(dev, pipe); | |
12155 | if (!cursor) | |
12156 | goto fail; | |
12157 | ||
465c120c | 12158 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
3d7d6510 MR |
12159 | cursor, &intel_crtc_funcs); |
12160 | if (ret) | |
12161 | goto fail; | |
79e53945 JB |
12162 | |
12163 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
12164 | for (i = 0; i < 256; i++) { |
12165 | intel_crtc->lut_r[i] = i; | |
12166 | intel_crtc->lut_g[i] = i; | |
12167 | intel_crtc->lut_b[i] = i; | |
12168 | } | |
12169 | ||
1f1c2e24 VS |
12170 | /* |
12171 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 12172 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 12173 | */ |
80824003 JB |
12174 | intel_crtc->pipe = pipe; |
12175 | intel_crtc->plane = pipe; | |
3a77c4c4 | 12176 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 12177 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 12178 | intel_crtc->plane = !pipe; |
80824003 JB |
12179 | } |
12180 | ||
4b0e333e CW |
12181 | intel_crtc->cursor_base = ~0; |
12182 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 12183 | intel_crtc->cursor_size = ~0; |
8d7849db | 12184 | |
22fd0fab JB |
12185 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
12186 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
12187 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
12188 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
12189 | ||
9362c7c5 ACO |
12190 | INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func); |
12191 | ||
79e53945 | 12192 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 DV |
12193 | |
12194 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); | |
3d7d6510 MR |
12195 | return; |
12196 | ||
12197 | fail: | |
12198 | if (primary) | |
12199 | drm_plane_cleanup(primary); | |
12200 | if (cursor) | |
12201 | drm_plane_cleanup(cursor); | |
12202 | kfree(intel_crtc); | |
79e53945 JB |
12203 | } |
12204 | ||
752aa88a JB |
12205 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
12206 | { | |
12207 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 12208 | struct drm_device *dev = connector->base.dev; |
752aa88a | 12209 | |
51fd371b | 12210 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 12211 | |
d3babd3f | 12212 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
12213 | return INVALID_PIPE; |
12214 | ||
12215 | return to_intel_crtc(encoder->crtc)->pipe; | |
12216 | } | |
12217 | ||
08d7b3d1 | 12218 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 12219 | struct drm_file *file) |
08d7b3d1 | 12220 | { |
08d7b3d1 | 12221 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 12222 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 12223 | struct intel_crtc *crtc; |
08d7b3d1 | 12224 | |
1cff8f6b DV |
12225 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
12226 | return -ENODEV; | |
08d7b3d1 | 12227 | |
7707e653 | 12228 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
08d7b3d1 | 12229 | |
7707e653 | 12230 | if (!drmmode_crtc) { |
08d7b3d1 | 12231 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 12232 | return -ENOENT; |
08d7b3d1 CW |
12233 | } |
12234 | ||
7707e653 | 12235 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 12236 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 12237 | |
c05422d5 | 12238 | return 0; |
08d7b3d1 CW |
12239 | } |
12240 | ||
66a9278e | 12241 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 12242 | { |
66a9278e DV |
12243 | struct drm_device *dev = encoder->base.dev; |
12244 | struct intel_encoder *source_encoder; | |
79e53945 | 12245 | int index_mask = 0; |
79e53945 JB |
12246 | int entry = 0; |
12247 | ||
b2784e15 | 12248 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 12249 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
12250 | index_mask |= (1 << entry); |
12251 | ||
79e53945 JB |
12252 | entry++; |
12253 | } | |
4ef69c7a | 12254 | |
79e53945 JB |
12255 | return index_mask; |
12256 | } | |
12257 | ||
4d302442 CW |
12258 | static bool has_edp_a(struct drm_device *dev) |
12259 | { | |
12260 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12261 | ||
12262 | if (!IS_MOBILE(dev)) | |
12263 | return false; | |
12264 | ||
12265 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
12266 | return false; | |
12267 | ||
e3589908 | 12268 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
12269 | return false; |
12270 | ||
12271 | return true; | |
12272 | } | |
12273 | ||
ba0fbca4 DL |
12274 | const char *intel_output_name(int output) |
12275 | { | |
12276 | static const char *names[] = { | |
12277 | [INTEL_OUTPUT_UNUSED] = "Unused", | |
12278 | [INTEL_OUTPUT_ANALOG] = "Analog", | |
12279 | [INTEL_OUTPUT_DVO] = "DVO", | |
12280 | [INTEL_OUTPUT_SDVO] = "SDVO", | |
12281 | [INTEL_OUTPUT_LVDS] = "LVDS", | |
12282 | [INTEL_OUTPUT_TVOUT] = "TV", | |
12283 | [INTEL_OUTPUT_HDMI] = "HDMI", | |
12284 | [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort", | |
12285 | [INTEL_OUTPUT_EDP] = "eDP", | |
12286 | [INTEL_OUTPUT_DSI] = "DSI", | |
12287 | [INTEL_OUTPUT_UNKNOWN] = "Unknown", | |
12288 | }; | |
12289 | ||
12290 | if (output < 0 || output >= ARRAY_SIZE(names) || !names[output]) | |
12291 | return "Invalid"; | |
12292 | ||
12293 | return names[output]; | |
12294 | } | |
12295 | ||
84b4e042 JB |
12296 | static bool intel_crt_present(struct drm_device *dev) |
12297 | { | |
12298 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12299 | ||
884497ed DL |
12300 | if (INTEL_INFO(dev)->gen >= 9) |
12301 | return false; | |
12302 | ||
cf404ce4 | 12303 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
12304 | return false; |
12305 | ||
12306 | if (IS_CHERRYVIEW(dev)) | |
12307 | return false; | |
12308 | ||
12309 | if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support) | |
12310 | return false; | |
12311 | ||
12312 | return true; | |
12313 | } | |
12314 | ||
79e53945 JB |
12315 | static void intel_setup_outputs(struct drm_device *dev) |
12316 | { | |
725e30ad | 12317 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 12318 | struct intel_encoder *encoder; |
cb0953d7 | 12319 | bool dpd_is_edp = false; |
79e53945 | 12320 | |
c9093354 | 12321 | intel_lvds_init(dev); |
79e53945 | 12322 | |
84b4e042 | 12323 | if (intel_crt_present(dev)) |
79935fca | 12324 | intel_crt_init(dev); |
cb0953d7 | 12325 | |
affa9354 | 12326 | if (HAS_DDI(dev)) { |
0e72a5b5 ED |
12327 | int found; |
12328 | ||
12329 | /* Haswell uses DDI functions to detect digital outputs */ | |
12330 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; | |
12331 | /* DDI A only supports eDP */ | |
12332 | if (found) | |
12333 | intel_ddi_init(dev, PORT_A); | |
12334 | ||
12335 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
12336 | * register */ | |
12337 | found = I915_READ(SFUSE_STRAP); | |
12338 | ||
12339 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
12340 | intel_ddi_init(dev, PORT_B); | |
12341 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
12342 | intel_ddi_init(dev, PORT_C); | |
12343 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
12344 | intel_ddi_init(dev, PORT_D); | |
12345 | } else if (HAS_PCH_SPLIT(dev)) { | |
cb0953d7 | 12346 | int found; |
5d8a7752 | 12347 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
12348 | |
12349 | if (has_edp_a(dev)) | |
12350 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 12351 | |
dc0fa718 | 12352 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 12353 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 12354 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 12355 | if (!found) |
e2debe91 | 12356 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 12357 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 12358 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
12359 | } |
12360 | ||
dc0fa718 | 12361 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 12362 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 12363 | |
dc0fa718 | 12364 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 12365 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 12366 | |
5eb08b69 | 12367 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 12368 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 12369 | |
270b3042 | 12370 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 12371 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d | 12372 | } else if (IS_VALLEYVIEW(dev)) { |
e17ac6db VS |
12373 | /* |
12374 | * The DP_DETECTED bit is the latched state of the DDC | |
12375 | * SDA pin at boot. However since eDP doesn't require DDC | |
12376 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
12377 | * eDP ports may have been muxed to an alternate function. | |
12378 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
12379 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
12380 | * detect eDP ports. | |
12381 | */ | |
12382 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) | |
585a94b8 AB |
12383 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, |
12384 | PORT_B); | |
e17ac6db VS |
12385 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED || |
12386 | intel_dp_is_edp(dev, PORT_B)) | |
12387 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); | |
585a94b8 | 12388 | |
e17ac6db | 12389 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) |
6f6005a5 JB |
12390 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, |
12391 | PORT_C); | |
e17ac6db VS |
12392 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED || |
12393 | intel_dp_is_edp(dev, PORT_C)) | |
12394 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); | |
19c03924 | 12395 | |
9418c1f1 | 12396 | if (IS_CHERRYVIEW(dev)) { |
e17ac6db | 12397 | if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) |
9418c1f1 VS |
12398 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID, |
12399 | PORT_D); | |
e17ac6db VS |
12400 | /* eDP not supported on port D, so don't check VBT */ |
12401 | if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED) | |
12402 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D); | |
9418c1f1 VS |
12403 | } |
12404 | ||
3cfca973 | 12405 | intel_dsi_init(dev); |
103a196f | 12406 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 12407 | bool found = false; |
7d57382e | 12408 | |
e2debe91 | 12409 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 12410 | DRM_DEBUG_KMS("probing SDVOB\n"); |
e2debe91 | 12411 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
b01f2c3a JB |
12412 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
12413 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
e2debe91 | 12414 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 12415 | } |
27185ae1 | 12416 | |
e7281eab | 12417 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 12418 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 12419 | } |
13520b05 KH |
12420 | |
12421 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 12422 | |
e2debe91 | 12423 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 12424 | DRM_DEBUG_KMS("probing SDVOC\n"); |
e2debe91 | 12425 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
b01f2c3a | 12426 | } |
27185ae1 | 12427 | |
e2debe91 | 12428 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 12429 | |
b01f2c3a JB |
12430 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
12431 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
e2debe91 | 12432 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 12433 | } |
e7281eab | 12434 | if (SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 12435 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 12436 | } |
27185ae1 | 12437 | |
b01f2c3a | 12438 | if (SUPPORTS_INTEGRATED_DP(dev) && |
e7281eab | 12439 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 12440 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 12441 | } else if (IS_GEN2(dev)) |
79e53945 JB |
12442 | intel_dvo_init(dev); |
12443 | ||
103a196f | 12444 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
12445 | intel_tv_init(dev); |
12446 | ||
0bc12bcb | 12447 | intel_psr_init(dev); |
7c8f8a70 | 12448 | |
b2784e15 | 12449 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
12450 | encoder->base.possible_crtcs = encoder->crtc_mask; |
12451 | encoder->base.possible_clones = | |
66a9278e | 12452 | intel_encoder_clones(encoder); |
79e53945 | 12453 | } |
47356eb6 | 12454 | |
dde86e2d | 12455 | intel_init_pch_refclk(dev); |
270b3042 DV |
12456 | |
12457 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
12458 | } |
12459 | ||
12460 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
12461 | { | |
60a5ca01 | 12462 | struct drm_device *dev = fb->dev; |
79e53945 | 12463 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 12464 | |
ef2d633e | 12465 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 12466 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 12467 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
12468 | drm_gem_object_unreference(&intel_fb->obj->base); |
12469 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
12470 | kfree(intel_fb); |
12471 | } | |
12472 | ||
12473 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 12474 | struct drm_file *file, |
79e53945 JB |
12475 | unsigned int *handle) |
12476 | { | |
12477 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 12478 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 12479 | |
05394f39 | 12480 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
12481 | } |
12482 | ||
12483 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
12484 | .destroy = intel_user_framebuffer_destroy, | |
12485 | .create_handle = intel_user_framebuffer_create_handle, | |
12486 | }; | |
12487 | ||
b5ea642a DV |
12488 | static int intel_framebuffer_init(struct drm_device *dev, |
12489 | struct intel_framebuffer *intel_fb, | |
12490 | struct drm_mode_fb_cmd2 *mode_cmd, | |
12491 | struct drm_i915_gem_object *obj) | |
79e53945 | 12492 | { |
a57ce0b2 | 12493 | int aligned_height; |
a35cdaa0 | 12494 | int pitch_limit; |
79e53945 JB |
12495 | int ret; |
12496 | ||
dd4916c5 DV |
12497 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
12498 | ||
c16ed4be CW |
12499 | if (obj->tiling_mode == I915_TILING_Y) { |
12500 | DRM_DEBUG("hardware does not support tiling Y\n"); | |
57cd6508 | 12501 | return -EINVAL; |
c16ed4be | 12502 | } |
57cd6508 | 12503 | |
c16ed4be CW |
12504 | if (mode_cmd->pitches[0] & 63) { |
12505 | DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n", | |
12506 | mode_cmd->pitches[0]); | |
57cd6508 | 12507 | return -EINVAL; |
c16ed4be | 12508 | } |
57cd6508 | 12509 | |
a35cdaa0 CW |
12510 | if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) { |
12511 | pitch_limit = 32*1024; | |
12512 | } else if (INTEL_INFO(dev)->gen >= 4) { | |
12513 | if (obj->tiling_mode) | |
12514 | pitch_limit = 16*1024; | |
12515 | else | |
12516 | pitch_limit = 32*1024; | |
12517 | } else if (INTEL_INFO(dev)->gen >= 3) { | |
12518 | if (obj->tiling_mode) | |
12519 | pitch_limit = 8*1024; | |
12520 | else | |
12521 | pitch_limit = 16*1024; | |
12522 | } else | |
12523 | /* XXX DSPC is limited to 4k tiled */ | |
12524 | pitch_limit = 8*1024; | |
12525 | ||
12526 | if (mode_cmd->pitches[0] > pitch_limit) { | |
12527 | DRM_DEBUG("%s pitch (%d) must be at less than %d\n", | |
12528 | obj->tiling_mode ? "tiled" : "linear", | |
12529 | mode_cmd->pitches[0], pitch_limit); | |
5d7bd705 | 12530 | return -EINVAL; |
c16ed4be | 12531 | } |
5d7bd705 VS |
12532 | |
12533 | if (obj->tiling_mode != I915_TILING_NONE && | |
c16ed4be CW |
12534 | mode_cmd->pitches[0] != obj->stride) { |
12535 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
12536 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 12537 | return -EINVAL; |
c16ed4be | 12538 | } |
5d7bd705 | 12539 | |
57779d06 | 12540 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 12541 | switch (mode_cmd->pixel_format) { |
57779d06 | 12542 | case DRM_FORMAT_C8: |
04b3924d VS |
12543 | case DRM_FORMAT_RGB565: |
12544 | case DRM_FORMAT_XRGB8888: | |
12545 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
12546 | break; |
12547 | case DRM_FORMAT_XRGB1555: | |
12548 | case DRM_FORMAT_ARGB1555: | |
c16ed4be | 12549 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
12550 | DRM_DEBUG("unsupported pixel format: %s\n", |
12551 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 12552 | return -EINVAL; |
c16ed4be | 12553 | } |
57779d06 VS |
12554 | break; |
12555 | case DRM_FORMAT_XBGR8888: | |
12556 | case DRM_FORMAT_ABGR8888: | |
04b3924d VS |
12557 | case DRM_FORMAT_XRGB2101010: |
12558 | case DRM_FORMAT_ARGB2101010: | |
57779d06 VS |
12559 | case DRM_FORMAT_XBGR2101010: |
12560 | case DRM_FORMAT_ABGR2101010: | |
c16ed4be | 12561 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
12562 | DRM_DEBUG("unsupported pixel format: %s\n", |
12563 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 12564 | return -EINVAL; |
c16ed4be | 12565 | } |
b5626747 | 12566 | break; |
04b3924d VS |
12567 | case DRM_FORMAT_YUYV: |
12568 | case DRM_FORMAT_UYVY: | |
12569 | case DRM_FORMAT_YVYU: | |
12570 | case DRM_FORMAT_VYUY: | |
c16ed4be | 12571 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
12572 | DRM_DEBUG("unsupported pixel format: %s\n", |
12573 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 12574 | return -EINVAL; |
c16ed4be | 12575 | } |
57cd6508 CW |
12576 | break; |
12577 | default: | |
4ee62c76 VS |
12578 | DRM_DEBUG("unsupported pixel format: %s\n", |
12579 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
12580 | return -EINVAL; |
12581 | } | |
12582 | ||
90f9a336 VS |
12583 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
12584 | if (mode_cmd->offsets[0] != 0) | |
12585 | return -EINVAL; | |
12586 | ||
a57ce0b2 JB |
12587 | aligned_height = intel_align_height(dev, mode_cmd->height, |
12588 | obj->tiling_mode); | |
53155c0a DV |
12589 | /* FIXME drm helper for size checks (especially planar formats)? */ |
12590 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
12591 | return -EINVAL; | |
12592 | ||
c7d73f6a DV |
12593 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
12594 | intel_fb->obj = obj; | |
80075d49 | 12595 | intel_fb->obj->framebuffer_references++; |
c7d73f6a | 12596 | |
79e53945 JB |
12597 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
12598 | if (ret) { | |
12599 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
12600 | return ret; | |
12601 | } | |
12602 | ||
79e53945 JB |
12603 | return 0; |
12604 | } | |
12605 | ||
79e53945 JB |
12606 | static struct drm_framebuffer * |
12607 | intel_user_framebuffer_create(struct drm_device *dev, | |
12608 | struct drm_file *filp, | |
308e5bcb | 12609 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 12610 | { |
05394f39 | 12611 | struct drm_i915_gem_object *obj; |
79e53945 | 12612 | |
308e5bcb JB |
12613 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
12614 | mode_cmd->handles[0])); | |
c8725226 | 12615 | if (&obj->base == NULL) |
cce13ff7 | 12616 | return ERR_PTR(-ENOENT); |
79e53945 | 12617 | |
d2dff872 | 12618 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
12619 | } |
12620 | ||
4520f53a | 12621 | #ifndef CONFIG_DRM_I915_FBDEV |
0632fef6 | 12622 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
12623 | { |
12624 | } | |
12625 | #endif | |
12626 | ||
79e53945 | 12627 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 12628 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 12629 | .output_poll_changed = intel_fbdev_output_poll_changed, |
79e53945 JB |
12630 | }; |
12631 | ||
e70236a8 JB |
12632 | /* Set up chip specific display functions */ |
12633 | static void intel_init_display(struct drm_device *dev) | |
12634 | { | |
12635 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12636 | ||
ee9300bb DV |
12637 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
12638 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
ef9348c8 CML |
12639 | else if (IS_CHERRYVIEW(dev)) |
12640 | dev_priv->display.find_dpll = chv_find_best_dpll; | |
ee9300bb DV |
12641 | else if (IS_VALLEYVIEW(dev)) |
12642 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
12643 | else if (IS_PINEVIEW(dev)) | |
12644 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
12645 | else | |
12646 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
12647 | ||
affa9354 | 12648 | if (HAS_DDI(dev)) { |
0e8ffe1b | 12649 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
4c6baa59 | 12650 | dev_priv->display.get_plane_config = ironlake_get_plane_config; |
797d0259 ACO |
12651 | dev_priv->display.crtc_compute_clock = |
12652 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
12653 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
12654 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
df8ad70c | 12655 | dev_priv->display.off = ironlake_crtc_off; |
70d21f0e DL |
12656 | if (INTEL_INFO(dev)->gen >= 9) |
12657 | dev_priv->display.update_primary_plane = | |
12658 | skylake_update_primary_plane; | |
12659 | else | |
12660 | dev_priv->display.update_primary_plane = | |
12661 | ironlake_update_primary_plane; | |
09b4ddf9 | 12662 | } else if (HAS_PCH_SPLIT(dev)) { |
0e8ffe1b | 12663 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
4c6baa59 | 12664 | dev_priv->display.get_plane_config = ironlake_get_plane_config; |
3fb37703 ACO |
12665 | dev_priv->display.crtc_compute_clock = |
12666 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
12667 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
12668 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
ee7b9f93 | 12669 | dev_priv->display.off = ironlake_crtc_off; |
262ca2b0 MR |
12670 | dev_priv->display.update_primary_plane = |
12671 | ironlake_update_primary_plane; | |
89b667f8 JB |
12672 | } else if (IS_VALLEYVIEW(dev)) { |
12673 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
1ad292b5 | 12674 | dev_priv->display.get_plane_config = i9xx_get_plane_config; |
d6dfee7a | 12675 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
89b667f8 JB |
12676 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
12677 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
12678 | dev_priv->display.off = i9xx_crtc_off; | |
262ca2b0 MR |
12679 | dev_priv->display.update_primary_plane = |
12680 | i9xx_update_primary_plane; | |
f564048e | 12681 | } else { |
0e8ffe1b | 12682 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
1ad292b5 | 12683 | dev_priv->display.get_plane_config = i9xx_get_plane_config; |
d6dfee7a | 12684 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
12685 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
12686 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
ee7b9f93 | 12687 | dev_priv->display.off = i9xx_crtc_off; |
262ca2b0 MR |
12688 | dev_priv->display.update_primary_plane = |
12689 | i9xx_update_primary_plane; | |
f564048e | 12690 | } |
e70236a8 | 12691 | |
e70236a8 | 12692 | /* Returns the core display clock speed */ |
25eb05fc JB |
12693 | if (IS_VALLEYVIEW(dev)) |
12694 | dev_priv->display.get_display_clock_speed = | |
12695 | valleyview_get_display_clock_speed; | |
12696 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) | |
e70236a8 JB |
12697 | dev_priv->display.get_display_clock_speed = |
12698 | i945_get_display_clock_speed; | |
12699 | else if (IS_I915G(dev)) | |
12700 | dev_priv->display.get_display_clock_speed = | |
12701 | i915_get_display_clock_speed; | |
257a7ffc | 12702 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
12703 | dev_priv->display.get_display_clock_speed = |
12704 | i9xx_misc_get_display_clock_speed; | |
257a7ffc DV |
12705 | else if (IS_PINEVIEW(dev)) |
12706 | dev_priv->display.get_display_clock_speed = | |
12707 | pnv_get_display_clock_speed; | |
e70236a8 JB |
12708 | else if (IS_I915GM(dev)) |
12709 | dev_priv->display.get_display_clock_speed = | |
12710 | i915gm_get_display_clock_speed; | |
12711 | else if (IS_I865G(dev)) | |
12712 | dev_priv->display.get_display_clock_speed = | |
12713 | i865_get_display_clock_speed; | |
f0f8a9ce | 12714 | else if (IS_I85X(dev)) |
e70236a8 JB |
12715 | dev_priv->display.get_display_clock_speed = |
12716 | i855_get_display_clock_speed; | |
12717 | else /* 852, 830 */ | |
12718 | dev_priv->display.get_display_clock_speed = | |
12719 | i830_get_display_clock_speed; | |
12720 | ||
7c10a2b5 | 12721 | if (IS_GEN5(dev)) { |
3bb11b53 | 12722 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
3bb11b53 SJ |
12723 | } else if (IS_GEN6(dev)) { |
12724 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; | |
3bb11b53 SJ |
12725 | } else if (IS_IVYBRIDGE(dev)) { |
12726 | /* FIXME: detect B0+ stepping and use auto training */ | |
12727 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
3bb11b53 SJ |
12728 | dev_priv->display.modeset_global_resources = |
12729 | ivb_modeset_global_resources; | |
059b2fe9 | 12730 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
3bb11b53 | 12731 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
30a970c6 JB |
12732 | } else if (IS_VALLEYVIEW(dev)) { |
12733 | dev_priv->display.modeset_global_resources = | |
12734 | valleyview_modeset_global_resources; | |
e70236a8 | 12735 | } |
8c9f3aaf JB |
12736 | |
12737 | /* Default just returns -ENODEV to indicate unsupported */ | |
12738 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
12739 | ||
12740 | switch (INTEL_INFO(dev)->gen) { | |
12741 | case 2: | |
12742 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
12743 | break; | |
12744 | ||
12745 | case 3: | |
12746 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
12747 | break; | |
12748 | ||
12749 | case 4: | |
12750 | case 5: | |
12751 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
12752 | break; | |
12753 | ||
12754 | case 6: | |
12755 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
12756 | break; | |
7c9017e5 | 12757 | case 7: |
4e0bbc31 | 12758 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
12759 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
12760 | break; | |
830c81db DL |
12761 | case 9: |
12762 | dev_priv->display.queue_flip = intel_gen9_queue_flip; | |
12763 | break; | |
8c9f3aaf | 12764 | } |
7bd688cd JN |
12765 | |
12766 | intel_panel_init_backlight_funcs(dev); | |
e39b999a VS |
12767 | |
12768 | mutex_init(&dev_priv->pps_mutex); | |
e70236a8 JB |
12769 | } |
12770 | ||
b690e96c JB |
12771 | /* |
12772 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
12773 | * resume, or other times. This quirk makes sure that's the case for | |
12774 | * affected systems. | |
12775 | */ | |
0206e353 | 12776 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
12777 | { |
12778 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12779 | ||
12780 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 12781 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
12782 | } |
12783 | ||
b6b5d049 VS |
12784 | static void quirk_pipeb_force(struct drm_device *dev) |
12785 | { | |
12786 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12787 | ||
12788 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
12789 | DRM_INFO("applying pipe b force quirk\n"); | |
12790 | } | |
12791 | ||
435793df KP |
12792 | /* |
12793 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
12794 | */ | |
12795 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
12796 | { | |
12797 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12798 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 12799 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
12800 | } |
12801 | ||
4dca20ef | 12802 | /* |
5a15ab5b CE |
12803 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
12804 | * brightness value | |
4dca20ef CE |
12805 | */ |
12806 | static void quirk_invert_brightness(struct drm_device *dev) | |
12807 | { | |
12808 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12809 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 12810 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
12811 | } |
12812 | ||
9c72cc6f SD |
12813 | /* Some VBT's incorrectly indicate no backlight is present */ |
12814 | static void quirk_backlight_present(struct drm_device *dev) | |
12815 | { | |
12816 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12817 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; | |
12818 | DRM_INFO("applying backlight present quirk\n"); | |
12819 | } | |
12820 | ||
b690e96c JB |
12821 | struct intel_quirk { |
12822 | int device; | |
12823 | int subsystem_vendor; | |
12824 | int subsystem_device; | |
12825 | void (*hook)(struct drm_device *dev); | |
12826 | }; | |
12827 | ||
5f85f176 EE |
12828 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
12829 | struct intel_dmi_quirk { | |
12830 | void (*hook)(struct drm_device *dev); | |
12831 | const struct dmi_system_id (*dmi_id_list)[]; | |
12832 | }; | |
12833 | ||
12834 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
12835 | { | |
12836 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
12837 | return 1; | |
12838 | } | |
12839 | ||
12840 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
12841 | { | |
12842 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
12843 | { | |
12844 | .callback = intel_dmi_reverse_brightness, | |
12845 | .ident = "NCR Corporation", | |
12846 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
12847 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
12848 | }, | |
12849 | }, | |
12850 | { } /* terminating entry */ | |
12851 | }, | |
12852 | .hook = quirk_invert_brightness, | |
12853 | }, | |
12854 | }; | |
12855 | ||
c43b5634 | 12856 | static struct intel_quirk intel_quirks[] = { |
b690e96c | 12857 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
0206e353 | 12858 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c | 12859 | |
b690e96c JB |
12860 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
12861 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
12862 | ||
b690e96c JB |
12863 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
12864 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
12865 | ||
5f080c0f VS |
12866 | /* 830 needs to leave pipe A & dpll A up */ |
12867 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
12868 | ||
b6b5d049 VS |
12869 | /* 830 needs to leave pipe B & dpll B up */ |
12870 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
12871 | ||
435793df KP |
12872 | /* Lenovo U160 cannot use SSC on LVDS */ |
12873 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
12874 | |
12875 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
12876 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 12877 | |
be505f64 AH |
12878 | /* Acer Aspire 5734Z must invert backlight brightness */ |
12879 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
12880 | ||
12881 | /* Acer/eMachines G725 */ | |
12882 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
12883 | ||
12884 | /* Acer/eMachines e725 */ | |
12885 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
12886 | ||
12887 | /* Acer/Packard Bell NCL20 */ | |
12888 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
12889 | ||
12890 | /* Acer Aspire 4736Z */ | |
12891 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
12892 | |
12893 | /* Acer Aspire 5336 */ | |
12894 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
12895 | |
12896 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
12897 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 12898 | |
dfb3d47b SD |
12899 | /* Acer C720 Chromebook (Core i3 4005U) */ |
12900 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
12901 | ||
b2a9601c | 12902 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
12903 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
12904 | ||
d4967d8c SD |
12905 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
12906 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
12907 | |
12908 | /* HP Chromebook 14 (Celeron 2955U) */ | |
12909 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
b690e96c JB |
12910 | }; |
12911 | ||
12912 | static void intel_init_quirks(struct drm_device *dev) | |
12913 | { | |
12914 | struct pci_dev *d = dev->pdev; | |
12915 | int i; | |
12916 | ||
12917 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
12918 | struct intel_quirk *q = &intel_quirks[i]; | |
12919 | ||
12920 | if (d->device == q->device && | |
12921 | (d->subsystem_vendor == q->subsystem_vendor || | |
12922 | q->subsystem_vendor == PCI_ANY_ID) && | |
12923 | (d->subsystem_device == q->subsystem_device || | |
12924 | q->subsystem_device == PCI_ANY_ID)) | |
12925 | q->hook(dev); | |
12926 | } | |
5f85f176 EE |
12927 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
12928 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
12929 | intel_dmi_quirks[i].hook(dev); | |
12930 | } | |
b690e96c JB |
12931 | } |
12932 | ||
9cce37f4 JB |
12933 | /* Disable the VGA plane that we never use */ |
12934 | static void i915_disable_vga(struct drm_device *dev) | |
12935 | { | |
12936 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12937 | u8 sr1; | |
766aa1c4 | 12938 | u32 vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 12939 | |
2b37c616 | 12940 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 12941 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 12942 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
12943 | sr1 = inb(VGA_SR_DATA); |
12944 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
12945 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
12946 | udelay(300); | |
12947 | ||
69769f9a VS |
12948 | /* |
12949 | * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming | |
12950 | * from S3 without preserving (some of?) the other bits. | |
12951 | */ | |
12952 | I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE); | |
9cce37f4 JB |
12953 | POSTING_READ(vga_reg); |
12954 | } | |
12955 | ||
f817586c DV |
12956 | void intel_modeset_init_hw(struct drm_device *dev) |
12957 | { | |
a8f78b58 ED |
12958 | intel_prepare_ddi(dev); |
12959 | ||
f8bf63fd VS |
12960 | if (IS_VALLEYVIEW(dev)) |
12961 | vlv_update_cdclk(dev); | |
12962 | ||
f817586c DV |
12963 | intel_init_clock_gating(dev); |
12964 | ||
8090c6b9 | 12965 | intel_enable_gt_powersave(dev); |
f817586c DV |
12966 | } |
12967 | ||
79e53945 JB |
12968 | void intel_modeset_init(struct drm_device *dev) |
12969 | { | |
652c393a | 12970 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 12971 | int sprite, ret; |
8cc87b75 | 12972 | enum pipe pipe; |
46f297fb | 12973 | struct intel_crtc *crtc; |
79e53945 JB |
12974 | |
12975 | drm_mode_config_init(dev); | |
12976 | ||
12977 | dev->mode_config.min_width = 0; | |
12978 | dev->mode_config.min_height = 0; | |
12979 | ||
019d96cb DA |
12980 | dev->mode_config.preferred_depth = 24; |
12981 | dev->mode_config.prefer_shadow = 1; | |
12982 | ||
e6ecefaa | 12983 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 12984 | |
b690e96c JB |
12985 | intel_init_quirks(dev); |
12986 | ||
1fa61106 ED |
12987 | intel_init_pm(dev); |
12988 | ||
e3c74757 BW |
12989 | if (INTEL_INFO(dev)->num_pipes == 0) |
12990 | return; | |
12991 | ||
e70236a8 | 12992 | intel_init_display(dev); |
7c10a2b5 | 12993 | intel_init_audio(dev); |
e70236a8 | 12994 | |
a6c45cf0 CW |
12995 | if (IS_GEN2(dev)) { |
12996 | dev->mode_config.max_width = 2048; | |
12997 | dev->mode_config.max_height = 2048; | |
12998 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
12999 | dev->mode_config.max_width = 4096; |
13000 | dev->mode_config.max_height = 4096; | |
79e53945 | 13001 | } else { |
a6c45cf0 CW |
13002 | dev->mode_config.max_width = 8192; |
13003 | dev->mode_config.max_height = 8192; | |
79e53945 | 13004 | } |
068be561 | 13005 | |
dc41c154 VS |
13006 | if (IS_845G(dev) || IS_I865G(dev)) { |
13007 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
13008 | dev->mode_config.cursor_height = 1023; | |
13009 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
13010 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
13011 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
13012 | } else { | |
13013 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
13014 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
13015 | } | |
13016 | ||
5d4545ae | 13017 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 13018 | |
28c97730 | 13019 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
13020 | INTEL_INFO(dev)->num_pipes, |
13021 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 13022 | |
055e393f | 13023 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 13024 | intel_crtc_init(dev, pipe); |
1fe47785 DL |
13025 | for_each_sprite(pipe, sprite) { |
13026 | ret = intel_plane_init(dev, pipe, sprite); | |
7f1f3851 | 13027 | if (ret) |
06da8da2 | 13028 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 13029 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 13030 | } |
79e53945 JB |
13031 | } |
13032 | ||
f42bb70d JB |
13033 | intel_init_dpio(dev); |
13034 | ||
e72f9fbf | 13035 | intel_shared_dpll_init(dev); |
ee7b9f93 | 13036 | |
69769f9a VS |
13037 | /* save the BIOS value before clobbering it */ |
13038 | dev_priv->bios_vgacntr = I915_READ(i915_vgacntrl_reg(dev)); | |
9cce37f4 JB |
13039 | /* Just disable it once at startup */ |
13040 | i915_disable_vga(dev); | |
79e53945 | 13041 | intel_setup_outputs(dev); |
11be49eb CW |
13042 | |
13043 | /* Just in case the BIOS is doing something questionable. */ | |
13044 | intel_disable_fbc(dev); | |
fa9fa083 | 13045 | |
6e9f798d | 13046 | drm_modeset_lock_all(dev); |
fa9fa083 | 13047 | intel_modeset_setup_hw_state(dev, false); |
6e9f798d | 13048 | drm_modeset_unlock_all(dev); |
46f297fb | 13049 | |
d3fcc808 | 13050 | for_each_intel_crtc(dev, crtc) { |
46f297fb JB |
13051 | if (!crtc->active) |
13052 | continue; | |
13053 | ||
46f297fb | 13054 | /* |
46f297fb JB |
13055 | * Note that reserving the BIOS fb up front prevents us |
13056 | * from stuffing other stolen allocations like the ring | |
13057 | * on top. This prevents some ugliness at boot time, and | |
13058 | * can even allow for smooth boot transitions if the BIOS | |
13059 | * fb is large enough for the active pipe configuration. | |
13060 | */ | |
13061 | if (dev_priv->display.get_plane_config) { | |
13062 | dev_priv->display.get_plane_config(crtc, | |
13063 | &crtc->plane_config); | |
13064 | /* | |
13065 | * If the fb is shared between multiple heads, we'll | |
13066 | * just get the first one. | |
13067 | */ | |
484b41dd | 13068 | intel_find_plane_obj(crtc, &crtc->plane_config); |
46f297fb | 13069 | } |
46f297fb | 13070 | } |
2c7111db CW |
13071 | } |
13072 | ||
7fad798e DV |
13073 | static void intel_enable_pipe_a(struct drm_device *dev) |
13074 | { | |
13075 | struct intel_connector *connector; | |
13076 | struct drm_connector *crt = NULL; | |
13077 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 13078 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
13079 | |
13080 | /* We can't just switch on the pipe A, we need to set things up with a | |
13081 | * proper mode and output configuration. As a gross hack, enable pipe A | |
13082 | * by enabling the load detect pipe once. */ | |
13083 | list_for_each_entry(connector, | |
13084 | &dev->mode_config.connector_list, | |
13085 | base.head) { | |
13086 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { | |
13087 | crt = &connector->base; | |
13088 | break; | |
13089 | } | |
13090 | } | |
13091 | ||
13092 | if (!crt) | |
13093 | return; | |
13094 | ||
208bf9fd VS |
13095 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
13096 | intel_release_load_detect_pipe(crt, &load_detect_temp); | |
7fad798e DV |
13097 | } |
13098 | ||
fa555837 DV |
13099 | static bool |
13100 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
13101 | { | |
7eb552ae BW |
13102 | struct drm_device *dev = crtc->base.dev; |
13103 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 DV |
13104 | u32 reg, val; |
13105 | ||
7eb552ae | 13106 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
13107 | return true; |
13108 | ||
13109 | reg = DSPCNTR(!crtc->plane); | |
13110 | val = I915_READ(reg); | |
13111 | ||
13112 | if ((val & DISPLAY_PLANE_ENABLE) && | |
13113 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
13114 | return false; | |
13115 | ||
13116 | return true; | |
13117 | } | |
13118 | ||
24929352 DV |
13119 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
13120 | { | |
13121 | struct drm_device *dev = crtc->base.dev; | |
13122 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 | 13123 | u32 reg; |
24929352 | 13124 | |
24929352 | 13125 | /* Clear any frame start delays used for debugging left by the BIOS */ |
3b117c8f | 13126 | reg = PIPECONF(crtc->config.cpu_transcoder); |
24929352 DV |
13127 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
13128 | ||
d3eaf884 | 13129 | /* restore vblank interrupts to correct state */ |
d297e103 VS |
13130 | if (crtc->active) { |
13131 | update_scanline_offset(crtc); | |
d3eaf884 | 13132 | drm_vblank_on(dev, crtc->pipe); |
d297e103 | 13133 | } else |
d3eaf884 VS |
13134 | drm_vblank_off(dev, crtc->pipe); |
13135 | ||
24929352 | 13136 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
13137 | * disable the crtc (and hence change the state) if it is wrong. Note |
13138 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
13139 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
13140 | struct intel_connector *connector; |
13141 | bool plane; | |
13142 | ||
24929352 DV |
13143 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
13144 | crtc->base.base.id); | |
13145 | ||
13146 | /* Pipe has the wrong plane attached and the plane is active. | |
13147 | * Temporarily change the plane mapping and disable everything | |
13148 | * ... */ | |
13149 | plane = crtc->plane; | |
13150 | crtc->plane = !plane; | |
9c8958bc | 13151 | crtc->primary_enabled = true; |
24929352 DV |
13152 | dev_priv->display.crtc_disable(&crtc->base); |
13153 | crtc->plane = plane; | |
13154 | ||
13155 | /* ... and break all links. */ | |
13156 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
13157 | base.head) { | |
13158 | if (connector->encoder->base.crtc != &crtc->base) | |
13159 | continue; | |
13160 | ||
7f1950fb EE |
13161 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
13162 | connector->base.encoder = NULL; | |
24929352 | 13163 | } |
7f1950fb EE |
13164 | /* multiple connectors may have the same encoder: |
13165 | * handle them and break crtc link separately */ | |
13166 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
13167 | base.head) | |
13168 | if (connector->encoder->base.crtc == &crtc->base) { | |
13169 | connector->encoder->base.crtc = NULL; | |
13170 | connector->encoder->connectors_active = false; | |
13171 | } | |
24929352 DV |
13172 | |
13173 | WARN_ON(crtc->active); | |
13174 | crtc->base.enabled = false; | |
13175 | } | |
24929352 | 13176 | |
7fad798e DV |
13177 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
13178 | crtc->pipe == PIPE_A && !crtc->active) { | |
13179 | /* BIOS forgot to enable pipe A, this mostly happens after | |
13180 | * resume. Force-enable the pipe to fix this, the update_dpms | |
13181 | * call below we restore the pipe to the right state, but leave | |
13182 | * the required bits on. */ | |
13183 | intel_enable_pipe_a(dev); | |
13184 | } | |
13185 | ||
24929352 DV |
13186 | /* Adjust the state of the output pipe according to whether we |
13187 | * have active connectors/encoders. */ | |
13188 | intel_crtc_update_dpms(&crtc->base); | |
13189 | ||
13190 | if (crtc->active != crtc->base.enabled) { | |
13191 | struct intel_encoder *encoder; | |
13192 | ||
13193 | /* This can happen either due to bugs in the get_hw_state | |
13194 | * functions or because the pipe is force-enabled due to the | |
13195 | * pipe A quirk. */ | |
13196 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
13197 | crtc->base.base.id, | |
13198 | crtc->base.enabled ? "enabled" : "disabled", | |
13199 | crtc->active ? "enabled" : "disabled"); | |
13200 | ||
13201 | crtc->base.enabled = crtc->active; | |
13202 | ||
13203 | /* Because we only establish the connector -> encoder -> | |
13204 | * crtc links if something is active, this means the | |
13205 | * crtc is now deactivated. Break the links. connector | |
13206 | * -> encoder links are only establish when things are | |
13207 | * actually up, hence no need to break them. */ | |
13208 | WARN_ON(crtc->active); | |
13209 | ||
13210 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { | |
13211 | WARN_ON(encoder->connectors_active); | |
13212 | encoder->base.crtc = NULL; | |
13213 | } | |
13214 | } | |
c5ab3bc0 | 13215 | |
a3ed6aad | 13216 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
13217 | /* |
13218 | * We start out with underrun reporting disabled to avoid races. | |
13219 | * For correct bookkeeping mark this on active crtcs. | |
13220 | * | |
c5ab3bc0 DV |
13221 | * Also on gmch platforms we dont have any hardware bits to |
13222 | * disable the underrun reporting. Which means we need to start | |
13223 | * out with underrun reporting disabled also on inactive pipes, | |
13224 | * since otherwise we'll complain about the garbage we read when | |
13225 | * e.g. coming up after runtime pm. | |
13226 | * | |
4cc31489 DV |
13227 | * No protection against concurrent access is required - at |
13228 | * worst a fifo underrun happens which also sets this to false. | |
13229 | */ | |
13230 | crtc->cpu_fifo_underrun_disabled = true; | |
13231 | crtc->pch_fifo_underrun_disabled = true; | |
13232 | } | |
24929352 DV |
13233 | } |
13234 | ||
13235 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
13236 | { | |
13237 | struct intel_connector *connector; | |
13238 | struct drm_device *dev = encoder->base.dev; | |
13239 | ||
13240 | /* We need to check both for a crtc link (meaning that the | |
13241 | * encoder is active and trying to read from a pipe) and the | |
13242 | * pipe itself being active. */ | |
13243 | bool has_active_crtc = encoder->base.crtc && | |
13244 | to_intel_crtc(encoder->base.crtc)->active; | |
13245 | ||
13246 | if (encoder->connectors_active && !has_active_crtc) { | |
13247 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
13248 | encoder->base.base.id, | |
8e329a03 | 13249 | encoder->base.name); |
24929352 DV |
13250 | |
13251 | /* Connector is active, but has no active pipe. This is | |
13252 | * fallout from our resume register restoring. Disable | |
13253 | * the encoder manually again. */ | |
13254 | if (encoder->base.crtc) { | |
13255 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
13256 | encoder->base.base.id, | |
8e329a03 | 13257 | encoder->base.name); |
24929352 | 13258 | encoder->disable(encoder); |
a62d1497 VS |
13259 | if (encoder->post_disable) |
13260 | encoder->post_disable(encoder); | |
24929352 | 13261 | } |
7f1950fb EE |
13262 | encoder->base.crtc = NULL; |
13263 | encoder->connectors_active = false; | |
24929352 DV |
13264 | |
13265 | /* Inconsistent output/port/pipe state happens presumably due to | |
13266 | * a bug in one of the get_hw_state functions. Or someplace else | |
13267 | * in our code, like the register restore mess on resume. Clamp | |
13268 | * things to off as a safer default. */ | |
13269 | list_for_each_entry(connector, | |
13270 | &dev->mode_config.connector_list, | |
13271 | base.head) { | |
13272 | if (connector->encoder != encoder) | |
13273 | continue; | |
7f1950fb EE |
13274 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
13275 | connector->base.encoder = NULL; | |
24929352 DV |
13276 | } |
13277 | } | |
13278 | /* Enabled encoders without active connectors will be fixed in | |
13279 | * the crtc fixup. */ | |
13280 | } | |
13281 | ||
04098753 | 13282 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
13283 | { |
13284 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766aa1c4 | 13285 | u32 vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 13286 | |
04098753 ID |
13287 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
13288 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
13289 | i915_disable_vga(dev); | |
13290 | } | |
13291 | } | |
13292 | ||
13293 | void i915_redisable_vga(struct drm_device *dev) | |
13294 | { | |
13295 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13296 | ||
8dc8a27c PZ |
13297 | /* This function can be called both from intel_modeset_setup_hw_state or |
13298 | * at a very early point in our resume sequence, where the power well | |
13299 | * structures are not yet restored. Since this function is at a very | |
13300 | * paranoid "someone might have enabled VGA while we were not looking" | |
13301 | * level, just check if the power well is enabled instead of trying to | |
13302 | * follow the "don't touch the power well if we don't need it" policy | |
13303 | * the rest of the driver uses. */ | |
f458ebbc | 13304 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
13305 | return; |
13306 | ||
04098753 | 13307 | i915_redisable_vga_power_on(dev); |
0fde901f KM |
13308 | } |
13309 | ||
98ec7739 VS |
13310 | static bool primary_get_hw_state(struct intel_crtc *crtc) |
13311 | { | |
13312 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
13313 | ||
13314 | if (!crtc->active) | |
13315 | return false; | |
13316 | ||
13317 | return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE; | |
13318 | } | |
13319 | ||
30e984df | 13320 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
13321 | { |
13322 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13323 | enum pipe pipe; | |
24929352 DV |
13324 | struct intel_crtc *crtc; |
13325 | struct intel_encoder *encoder; | |
13326 | struct intel_connector *connector; | |
5358901f | 13327 | int i; |
24929352 | 13328 | |
d3fcc808 | 13329 | for_each_intel_crtc(dev, crtc) { |
88adfff1 | 13330 | memset(&crtc->config, 0, sizeof(crtc->config)); |
3b117c8f | 13331 | |
9953599b DV |
13332 | crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE; |
13333 | ||
0e8ffe1b DV |
13334 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
13335 | &crtc->config); | |
24929352 DV |
13336 | |
13337 | crtc->base.enabled = crtc->active; | |
98ec7739 | 13338 | crtc->primary_enabled = primary_get_hw_state(crtc); |
24929352 DV |
13339 | |
13340 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
13341 | crtc->base.base.id, | |
13342 | crtc->active ? "enabled" : "disabled"); | |
13343 | } | |
13344 | ||
5358901f DV |
13345 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
13346 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
13347 | ||
3e369b76 ACO |
13348 | pll->on = pll->get_hw_state(dev_priv, pll, |
13349 | &pll->config.hw_state); | |
5358901f | 13350 | pll->active = 0; |
3e369b76 | 13351 | pll->config.crtc_mask = 0; |
d3fcc808 | 13352 | for_each_intel_crtc(dev, crtc) { |
1e6f2ddc | 13353 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) { |
5358901f | 13354 | pll->active++; |
3e369b76 | 13355 | pll->config.crtc_mask |= 1 << crtc->pipe; |
1e6f2ddc | 13356 | } |
5358901f | 13357 | } |
5358901f | 13358 | |
1e6f2ddc | 13359 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 13360 | pll->name, pll->config.crtc_mask, pll->on); |
bd2bb1b9 | 13361 | |
3e369b76 | 13362 | if (pll->config.crtc_mask) |
bd2bb1b9 | 13363 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
5358901f DV |
13364 | } |
13365 | ||
b2784e15 | 13366 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
13367 | pipe = 0; |
13368 | ||
13369 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
13370 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
13371 | encoder->base.crtc = &crtc->base; | |
1d37b689 | 13372 | encoder->get_config(encoder, &crtc->config); |
24929352 DV |
13373 | } else { |
13374 | encoder->base.crtc = NULL; | |
13375 | } | |
13376 | ||
13377 | encoder->connectors_active = false; | |
6f2bcceb | 13378 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 13379 | encoder->base.base.id, |
8e329a03 | 13380 | encoder->base.name, |
24929352 | 13381 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 13382 | pipe_name(pipe)); |
24929352 DV |
13383 | } |
13384 | ||
13385 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
13386 | base.head) { | |
13387 | if (connector->get_hw_state(connector)) { | |
13388 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
13389 | connector->encoder->connectors_active = true; | |
13390 | connector->base.encoder = &connector->encoder->base; | |
13391 | } else { | |
13392 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
13393 | connector->base.encoder = NULL; | |
13394 | } | |
13395 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
13396 | connector->base.base.id, | |
c23cc417 | 13397 | connector->base.name, |
24929352 DV |
13398 | connector->base.encoder ? "enabled" : "disabled"); |
13399 | } | |
30e984df DV |
13400 | } |
13401 | ||
13402 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm | |
13403 | * and i915 state tracking structures. */ | |
13404 | void intel_modeset_setup_hw_state(struct drm_device *dev, | |
13405 | bool force_restore) | |
13406 | { | |
13407 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13408 | enum pipe pipe; | |
30e984df DV |
13409 | struct intel_crtc *crtc; |
13410 | struct intel_encoder *encoder; | |
35c95375 | 13411 | int i; |
30e984df DV |
13412 | |
13413 | intel_modeset_readout_hw_state(dev); | |
24929352 | 13414 | |
babea61d JB |
13415 | /* |
13416 | * Now that we have the config, copy it to each CRTC struct | |
13417 | * Note that this could go away if we move to using crtc_config | |
13418 | * checking everywhere. | |
13419 | */ | |
d3fcc808 | 13420 | for_each_intel_crtc(dev, crtc) { |
d330a953 | 13421 | if (crtc->active && i915.fastboot) { |
f6a83288 | 13422 | intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config); |
babea61d JB |
13423 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", |
13424 | crtc->base.base.id); | |
13425 | drm_mode_debug_printmodeline(&crtc->base.mode); | |
13426 | } | |
13427 | } | |
13428 | ||
24929352 | 13429 | /* HW state is read out, now we need to sanitize this mess. */ |
b2784e15 | 13430 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
13431 | intel_sanitize_encoder(encoder); |
13432 | } | |
13433 | ||
055e393f | 13434 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
13435 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
13436 | intel_sanitize_crtc(crtc); | |
c0b03411 | 13437 | intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]"); |
24929352 | 13438 | } |
9a935856 | 13439 | |
35c95375 DV |
13440 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
13441 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
13442 | ||
13443 | if (!pll->on || pll->active) | |
13444 | continue; | |
13445 | ||
13446 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
13447 | ||
13448 | pll->disable(dev_priv, pll); | |
13449 | pll->on = false; | |
13450 | } | |
13451 | ||
3078999f PB |
13452 | if (IS_GEN9(dev)) |
13453 | skl_wm_get_hw_state(dev); | |
13454 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 VS |
13455 | ilk_wm_get_hw_state(dev); |
13456 | ||
45e2b5f6 | 13457 | if (force_restore) { |
7d0bc1ea VS |
13458 | i915_redisable_vga(dev); |
13459 | ||
f30da187 DV |
13460 | /* |
13461 | * We need to use raw interfaces for restoring state to avoid | |
13462 | * checking (bogus) intermediate states. | |
13463 | */ | |
055e393f | 13464 | for_each_pipe(dev_priv, pipe) { |
b5644d05 JB |
13465 | struct drm_crtc *crtc = |
13466 | dev_priv->pipe_to_crtc_mapping[pipe]; | |
f30da187 | 13467 | |
7f27126e JB |
13468 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, |
13469 | crtc->primary->fb); | |
45e2b5f6 DV |
13470 | } |
13471 | } else { | |
13472 | intel_modeset_update_staged_output_state(dev); | |
13473 | } | |
8af6cf88 DV |
13474 | |
13475 | intel_modeset_check_state(dev); | |
2c7111db CW |
13476 | } |
13477 | ||
13478 | void intel_modeset_gem_init(struct drm_device *dev) | |
13479 | { | |
92122789 | 13480 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd | 13481 | struct drm_crtc *c; |
2ff8fde1 | 13482 | struct drm_i915_gem_object *obj; |
484b41dd | 13483 | |
ae48434c ID |
13484 | mutex_lock(&dev->struct_mutex); |
13485 | intel_init_gt_powersave(dev); | |
13486 | mutex_unlock(&dev->struct_mutex); | |
13487 | ||
92122789 JB |
13488 | /* |
13489 | * There may be no VBT; and if the BIOS enabled SSC we can | |
13490 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
13491 | * BIOS isn't using it, don't assume it will work even if the VBT | |
13492 | * indicates as much. | |
13493 | */ | |
13494 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
13495 | dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
13496 | DREF_SSC1_ENABLE); | |
13497 | ||
1833b134 | 13498 | intel_modeset_init_hw(dev); |
02e792fb DV |
13499 | |
13500 | intel_setup_overlay(dev); | |
484b41dd JB |
13501 | |
13502 | /* | |
13503 | * Make sure any fbs we allocated at startup are properly | |
13504 | * pinned & fenced. When we do the allocation it's too early | |
13505 | * for this. | |
13506 | */ | |
13507 | mutex_lock(&dev->struct_mutex); | |
70e1e0ec | 13508 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
13509 | obj = intel_fb_obj(c->primary->fb); |
13510 | if (obj == NULL) | |
484b41dd JB |
13511 | continue; |
13512 | ||
850c4cdc TU |
13513 | if (intel_pin_and_fence_fb_obj(c->primary, |
13514 | c->primary->fb, | |
13515 | NULL)) { | |
484b41dd JB |
13516 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
13517 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
13518 | drm_framebuffer_unreference(c->primary->fb); |
13519 | c->primary->fb = NULL; | |
484b41dd JB |
13520 | } |
13521 | } | |
13522 | mutex_unlock(&dev->struct_mutex); | |
0962c3c9 VS |
13523 | |
13524 | intel_backlight_register(dev); | |
79e53945 JB |
13525 | } |
13526 | ||
4932e2c3 ID |
13527 | void intel_connector_unregister(struct intel_connector *intel_connector) |
13528 | { | |
13529 | struct drm_connector *connector = &intel_connector->base; | |
13530 | ||
13531 | intel_panel_destroy_backlight(connector); | |
34ea3d38 | 13532 | drm_connector_unregister(connector); |
4932e2c3 ID |
13533 | } |
13534 | ||
79e53945 JB |
13535 | void intel_modeset_cleanup(struct drm_device *dev) |
13536 | { | |
652c393a | 13537 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9255d57 | 13538 | struct drm_connector *connector; |
652c393a | 13539 | |
2eb5252e ID |
13540 | intel_disable_gt_powersave(dev); |
13541 | ||
0962c3c9 VS |
13542 | intel_backlight_unregister(dev); |
13543 | ||
fd0c0642 DV |
13544 | /* |
13545 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 13546 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
13547 | * experience fancy races otherwise. |
13548 | */ | |
2aeb7d3a | 13549 | intel_irq_uninstall(dev_priv); |
eb21b92b | 13550 | |
fd0c0642 DV |
13551 | /* |
13552 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
13553 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
13554 | */ | |
f87ea761 | 13555 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 13556 | |
652c393a JB |
13557 | mutex_lock(&dev->struct_mutex); |
13558 | ||
723bfd70 JB |
13559 | intel_unregister_dsm_handler(); |
13560 | ||
973d04f9 | 13561 | intel_disable_fbc(dev); |
e70236a8 | 13562 | |
930ebb46 DV |
13563 | ironlake_teardown_rc6(dev); |
13564 | ||
69341a5e KH |
13565 | mutex_unlock(&dev->struct_mutex); |
13566 | ||
1630fe75 CW |
13567 | /* flush any delayed tasks or pending work */ |
13568 | flush_scheduled_work(); | |
13569 | ||
db31af1d JN |
13570 | /* destroy the backlight and sysfs files before encoders/connectors */ |
13571 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4932e2c3 ID |
13572 | struct intel_connector *intel_connector; |
13573 | ||
13574 | intel_connector = to_intel_connector(connector); | |
13575 | intel_connector->unregister(intel_connector); | |
db31af1d | 13576 | } |
d9255d57 | 13577 | |
79e53945 | 13578 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
13579 | |
13580 | intel_cleanup_overlay(dev); | |
ae48434c ID |
13581 | |
13582 | mutex_lock(&dev->struct_mutex); | |
13583 | intel_cleanup_gt_powersave(dev); | |
13584 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
13585 | } |
13586 | ||
f1c79df3 ZW |
13587 | /* |
13588 | * Return which encoder is currently attached for connector. | |
13589 | */ | |
df0e9248 | 13590 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 13591 | { |
df0e9248 CW |
13592 | return &intel_attached_encoder(connector)->base; |
13593 | } | |
f1c79df3 | 13594 | |
df0e9248 CW |
13595 | void intel_connector_attach_encoder(struct intel_connector *connector, |
13596 | struct intel_encoder *encoder) | |
13597 | { | |
13598 | connector->encoder = encoder; | |
13599 | drm_mode_connector_attach_encoder(&connector->base, | |
13600 | &encoder->base); | |
79e53945 | 13601 | } |
28d52043 DA |
13602 | |
13603 | /* | |
13604 | * set vga decode state - true == enable VGA decode | |
13605 | */ | |
13606 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
13607 | { | |
13608 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 13609 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
13610 | u16 gmch_ctrl; |
13611 | ||
75fa041d CW |
13612 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
13613 | DRM_ERROR("failed to read control word\n"); | |
13614 | return -EIO; | |
13615 | } | |
13616 | ||
c0cc8a55 CW |
13617 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
13618 | return 0; | |
13619 | ||
28d52043 DA |
13620 | if (state) |
13621 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
13622 | else | |
13623 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
13624 | |
13625 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
13626 | DRM_ERROR("failed to write control word\n"); | |
13627 | return -EIO; | |
13628 | } | |
13629 | ||
28d52043 DA |
13630 | return 0; |
13631 | } | |
c4a1d9e4 | 13632 | |
c4a1d9e4 | 13633 | struct intel_display_error_state { |
ff57f1b0 PZ |
13634 | |
13635 | u32 power_well_driver; | |
13636 | ||
63b66e5b CW |
13637 | int num_transcoders; |
13638 | ||
c4a1d9e4 CW |
13639 | struct intel_cursor_error_state { |
13640 | u32 control; | |
13641 | u32 position; | |
13642 | u32 base; | |
13643 | u32 size; | |
52331309 | 13644 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
13645 | |
13646 | struct intel_pipe_error_state { | |
ddf9c536 | 13647 | bool power_domain_on; |
c4a1d9e4 | 13648 | u32 source; |
f301b1e1 | 13649 | u32 stat; |
52331309 | 13650 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
13651 | |
13652 | struct intel_plane_error_state { | |
13653 | u32 control; | |
13654 | u32 stride; | |
13655 | u32 size; | |
13656 | u32 pos; | |
13657 | u32 addr; | |
13658 | u32 surface; | |
13659 | u32 tile_offset; | |
52331309 | 13660 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
13661 | |
13662 | struct intel_transcoder_error_state { | |
ddf9c536 | 13663 | bool power_domain_on; |
63b66e5b CW |
13664 | enum transcoder cpu_transcoder; |
13665 | ||
13666 | u32 conf; | |
13667 | ||
13668 | u32 htotal; | |
13669 | u32 hblank; | |
13670 | u32 hsync; | |
13671 | u32 vtotal; | |
13672 | u32 vblank; | |
13673 | u32 vsync; | |
13674 | } transcoder[4]; | |
c4a1d9e4 CW |
13675 | }; |
13676 | ||
13677 | struct intel_display_error_state * | |
13678 | intel_display_capture_error_state(struct drm_device *dev) | |
13679 | { | |
fbee40df | 13680 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 13681 | struct intel_display_error_state *error; |
63b66e5b CW |
13682 | int transcoders[] = { |
13683 | TRANSCODER_A, | |
13684 | TRANSCODER_B, | |
13685 | TRANSCODER_C, | |
13686 | TRANSCODER_EDP, | |
13687 | }; | |
c4a1d9e4 CW |
13688 | int i; |
13689 | ||
63b66e5b CW |
13690 | if (INTEL_INFO(dev)->num_pipes == 0) |
13691 | return NULL; | |
13692 | ||
9d1cb914 | 13693 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
13694 | if (error == NULL) |
13695 | return NULL; | |
13696 | ||
190be112 | 13697 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
13698 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
13699 | ||
055e393f | 13700 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 13701 | error->pipe[i].power_domain_on = |
f458ebbc DV |
13702 | __intel_display_power_is_enabled(dev_priv, |
13703 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 13704 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
13705 | continue; |
13706 | ||
5efb3e28 VS |
13707 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
13708 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
13709 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
13710 | |
13711 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
13712 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 13713 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 13714 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
13715 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
13716 | } | |
ca291363 PZ |
13717 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
13718 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
13719 | if (INTEL_INFO(dev)->gen >= 4) { |
13720 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
13721 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
13722 | } | |
13723 | ||
c4a1d9e4 | 13724 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 13725 | |
3abfce77 | 13726 | if (HAS_GMCH_DISPLAY(dev)) |
f301b1e1 | 13727 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
13728 | } |
13729 | ||
13730 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
13731 | if (HAS_DDI(dev_priv->dev)) | |
13732 | error->num_transcoders++; /* Account for eDP. */ | |
13733 | ||
13734 | for (i = 0; i < error->num_transcoders; i++) { | |
13735 | enum transcoder cpu_transcoder = transcoders[i]; | |
13736 | ||
ddf9c536 | 13737 | error->transcoder[i].power_domain_on = |
f458ebbc | 13738 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 13739 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 13740 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
13741 | continue; |
13742 | ||
63b66e5b CW |
13743 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
13744 | ||
13745 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
13746 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
13747 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
13748 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
13749 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
13750 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
13751 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
13752 | } |
13753 | ||
13754 | return error; | |
13755 | } | |
13756 | ||
edc3d884 MK |
13757 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
13758 | ||
c4a1d9e4 | 13759 | void |
edc3d884 | 13760 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
13761 | struct drm_device *dev, |
13762 | struct intel_display_error_state *error) | |
13763 | { | |
055e393f | 13764 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
13765 | int i; |
13766 | ||
63b66e5b CW |
13767 | if (!error) |
13768 | return; | |
13769 | ||
edc3d884 | 13770 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 13771 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 13772 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 13773 | error->power_well_driver); |
055e393f | 13774 | for_each_pipe(dev_priv, i) { |
edc3d884 | 13775 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 ID |
13776 | err_printf(m, " Power: %s\n", |
13777 | error->pipe[i].power_domain_on ? "on" : "off"); | |
edc3d884 | 13778 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 13779 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
13780 | |
13781 | err_printf(m, "Plane [%d]:\n", i); | |
13782 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
13783 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 13784 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
13785 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
13786 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 13787 | } |
4b71a570 | 13788 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 13789 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 13790 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
13791 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
13792 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
13793 | } |
13794 | ||
edc3d884 MK |
13795 | err_printf(m, "Cursor [%d]:\n", i); |
13796 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
13797 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
13798 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 13799 | } |
63b66e5b CW |
13800 | |
13801 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 13802 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 13803 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 ID |
13804 | err_printf(m, " Power: %s\n", |
13805 | error->transcoder[i].power_domain_on ? "on" : "off"); | |
63b66e5b CW |
13806 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
13807 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
13808 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
13809 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
13810 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
13811 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
13812 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
13813 | } | |
c4a1d9e4 | 13814 | } |
e2fcdaa9 VS |
13815 | |
13816 | void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file) | |
13817 | { | |
13818 | struct intel_crtc *crtc; | |
13819 | ||
13820 | for_each_intel_crtc(dev, crtc) { | |
13821 | struct intel_unpin_work *work; | |
e2fcdaa9 | 13822 | |
5e2d7afc | 13823 | spin_lock_irq(&dev->event_lock); |
e2fcdaa9 VS |
13824 | |
13825 | work = crtc->unpin_work; | |
13826 | ||
13827 | if (work && work->event && | |
13828 | work->event->base.file_priv == file) { | |
13829 | kfree(work->event); | |
13830 | work->event = NULL; | |
13831 | } | |
13832 | ||
5e2d7afc | 13833 | spin_unlock_irq(&dev->event_lock); |
e2fcdaa9 VS |
13834 | } |
13835 | } |