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drm/i915/skl: Support secondary (rotated) frame buffer mapping
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c
MR		 48/* Primary plane formats supported by all gen */
49#define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_C8, \
51 DRM_FORMAT_RGB565, \
52 DRM_FORMAT_XRGB8888, \
53 DRM_FORMAT_ARGB8888
54
55/* Primary plane formats for gen <= 3 */
56static const uint32_t intel_primary_formats_gen2[] = {
57 COMMON_PRIMARY_FORMATS,
58 DRM_FORMAT_XRGB1555,
59 DRM_FORMAT_ARGB1555,
60};
61
62/* Primary plane formats for gen >= 4 */
63static const uint32_t intel_primary_formats_gen4[] = {
64 COMMON_PRIMARY_FORMATS, \
65 DRM_FORMAT_XBGR8888,
66 DRM_FORMAT_ABGR8888,
67 DRM_FORMAT_XRGB2101010,
68 DRM_FORMAT_ARGB2101010,
69 DRM_FORMAT_XBGR2101010,
70 DRM_FORMAT_ABGR2101010,
71};
72
3d7d6510
MR		 73/* Cursor formats */
74static const uint32_t intel_cursor_formats[] = {
75 DRM_FORMAT_ARGB8888,
76};
77
6b383a7f 78static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 79
f1f644dc 80static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 81 struct intel_crtc_state *pipe_config);
18442d08 82static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 83 struct intel_crtc_state *pipe_config);
f1f644dc 84
e7457a9a
DL		 85static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
86 int x, int y, struct drm_framebuffer *old_fb);
eb1bfe80
JB		 87static int intel_framebuffer_init(struct drm_device *dev,
88 struct intel_framebuffer *ifb,
89 struct drm_mode_fb_cmd2 *mode_cmd,
90 struct drm_i915_gem_object *obj);
5b18e57c
DV		 91static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
92static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 93static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 94 struct intel_link_m_n *m_n,
95 struct intel_link_m_n *m2_n2);
29407aab 96static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 97static void haswell_set_pipeconf(struct drm_crtc *crtc);
98static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 99static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 100 const struct intel_crtc_state *pipe_config);
d288f65f 101static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 102 const struct intel_crtc_state *pipe_config);
ea2c67bb
MR		 103static void intel_begin_crtc_commit(struct drm_crtc *crtc);
104static void intel_finish_crtc_commit(struct drm_crtc *crtc);
e7457a9a 105
0e32b39c
DA		 106static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
107{
108 if (!connector->mst_port)
109 return connector->encoder;
110 else
111 return &connector->mst_port->mst_encoders[pipe]->base;
112}
113
79e53945 114typedef struct {
0206e353 115 int min, max;
79e53945
JB		 116} intel_range_t;
117
118typedef struct {
0206e353
AJ		 119 int dot_limit;
120 int p2_slow, p2_fast;
79e53945
JB		 121} intel_p2_t;
122
d4906093
ML		 123typedef struct intel_limit intel_limit_t;
124struct intel_limit {
0206e353
AJ		 125 intel_range_t dot, vco, n, m, m1, m2, p, p1;
126 intel_p2_t p2;
d4906093 127};
79e53945 128
d2acd215
DV		 129int
130intel_pch_rawclk(struct drm_device *dev)
131{
132 struct drm_i915_private *dev_priv = dev->dev_private;
133
134 WARN_ON(!HAS_PCH_SPLIT(dev));
135
136 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
137}
138
021357ac
CW		 139static inline u32 /* units of 100MHz */
140intel_fdi_link_freq(struct drm_device *dev)
141{
8b99e68c
CW		 142 if (IS_GEN5(dev)) {
143 struct drm_i915_private *dev_priv = dev->dev_private;
144 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
145 } else
146 return 27;
021357ac
CW		 147}
148
5d536e28 149static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 150 .dot = { .min = 25000, .max = 350000 },
9c333719 151 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 152 .n = { .min = 2, .max = 16 },
0206e353
AJ		 153 .m = { .min = 96, .max = 140 },
154 .m1 = { .min = 18, .max = 26 },
155 .m2 = { .min = 6, .max = 16 },
156 .p = { .min = 4, .max = 128 },
157 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 158 .p2 = { .dot_limit = 165000,
159 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 160};
161
5d536e28
DV		 162static const intel_limit_t intel_limits_i8xx_dvo = {
163 .dot = { .min = 25000, .max = 350000 },
9c333719 164 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 165 .n = { .min = 2, .max = 16 },
5d536e28
DV		 166 .m = { .min = 96, .max = 140 },
167 .m1 = { .min = 18, .max = 26 },
168 .m2 = { .min = 6, .max = 16 },
169 .p = { .min = 4, .max = 128 },
170 .p1 = { .min = 2, .max = 33 },
171 .p2 = { .dot_limit = 165000,
172 .p2_slow = 4, .p2_fast = 4 },
173};
174
e4b36699 175static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 176 .dot = { .min = 25000, .max = 350000 },
9c333719 177 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 178 .n = { .min = 2, .max = 16 },
0206e353
AJ		 179 .m = { .min = 96, .max = 140 },
180 .m1 = { .min = 18, .max = 26 },
181 .m2 = { .min = 6, .max = 16 },
182 .p = { .min = 4, .max = 128 },
183 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 184 .p2 = { .dot_limit = 165000,
185 .p2_slow = 14, .p2_fast = 7 },
e4b36699 186};
273e27ca 187
e4b36699 188static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 189 .dot = { .min = 20000, .max = 400000 },
190 .vco = { .min = 1400000, .max = 2800000 },
191 .n = { .min = 1, .max = 6 },
192 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 193 .m1 = { .min = 8, .max = 18 },
194 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 195 .p = { .min = 5, .max = 80 },
196 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 197 .p2 = { .dot_limit = 200000,
198 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 199};
200
201static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 202 .dot = { .min = 20000, .max = 400000 },
203 .vco = { .min = 1400000, .max = 2800000 },
204 .n = { .min = 1, .max = 6 },
205 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 206 .m1 = { .min = 8, .max = 18 },
207 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 208 .p = { .min = 7, .max = 98 },
209 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 210 .p2 = { .dot_limit = 112000,
211 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 212};
213
273e27ca 214
e4b36699 215static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 216 .dot = { .min = 25000, .max = 270000 },
217 .vco = { .min = 1750000, .max = 3500000},
218 .n = { .min = 1, .max = 4 },
219 .m = { .min = 104, .max = 138 },
220 .m1 = { .min = 17, .max = 23 },
221 .m2 = { .min = 5, .max = 11 },
222 .p = { .min = 10, .max = 30 },
223 .p1 = { .min = 1, .max = 3},
224 .p2 = { .dot_limit = 270000,
225 .p2_slow = 10,
226 .p2_fast = 10
044c7c41 227 },
e4b36699
KP		 228};
229
230static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 231 .dot = { .min = 22000, .max = 400000 },
232 .vco = { .min = 1750000, .max = 3500000},
233 .n = { .min = 1, .max = 4 },
234 .m = { .min = 104, .max = 138 },
235 .m1 = { .min = 16, .max = 23 },
236 .m2 = { .min = 5, .max = 11 },
237 .p = { .min = 5, .max = 80 },
238 .p1 = { .min = 1, .max = 8},
239 .p2 = { .dot_limit = 165000,
240 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 241};
242
243static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 244 .dot = { .min = 20000, .max = 115000 },
245 .vco = { .min = 1750000, .max = 3500000 },
246 .n = { .min = 1, .max = 3 },
247 .m = { .min = 104, .max = 138 },
248 .m1 = { .min = 17, .max = 23 },
249 .m2 = { .min = 5, .max = 11 },
250 .p = { .min = 28, .max = 112 },
251 .p1 = { .min = 2, .max = 8 },
252 .p2 = { .dot_limit = 0,
253 .p2_slow = 14, .p2_fast = 14
044c7c41 254 },
e4b36699
KP		 255};
256
257static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 258 .dot = { .min = 80000, .max = 224000 },
259 .vco = { .min = 1750000, .max = 3500000 },
260 .n = { .min = 1, .max = 3 },
261 .m = { .min = 104, .max = 138 },
262 .m1 = { .min = 17, .max = 23 },
263 .m2 = { .min = 5, .max = 11 },
264 .p = { .min = 14, .max = 42 },
265 .p1 = { .min = 2, .max = 6 },
266 .p2 = { .dot_limit = 0,
267 .p2_slow = 7, .p2_fast = 7
044c7c41 268 },
e4b36699
KP		 269};
270
f2b115e6 271static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 272 .dot = { .min = 20000, .max = 400000},
273 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 274 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 275 .n = { .min = 3, .max = 6 },
276 .m = { .min = 2, .max = 256 },
273e27ca 277 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 5, .max = 80 },
281 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 282 .p2 = { .dot_limit = 200000,
283 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 284};
285
f2b115e6 286static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 287 .dot = { .min = 20000, .max = 400000 },
288 .vco = { .min = 1700000, .max = 3500000 },
289 .n = { .min = 3, .max = 6 },
290 .m = { .min = 2, .max = 256 },
291 .m1 = { .min = 0, .max = 0 },
292 .m2 = { .min = 0, .max = 254 },
293 .p = { .min = 7, .max = 112 },
294 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 295 .p2 = { .dot_limit = 112000,
296 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 297};
298
273e27ca
EA		 299/* Ironlake / Sandybridge
300 *
301 * We calculate clock using (register_value + 2) for N/M1/M2, so here
302 * the range value for them is (actual_value - 2).
303 */
b91ad0ec 304static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 305 .dot = { .min = 25000, .max = 350000 },
306 .vco = { .min = 1760000, .max = 3510000 },
307 .n = { .min = 1, .max = 5 },
308 .m = { .min = 79, .max = 127 },
309 .m1 = { .min = 12, .max = 22 },
310 .m2 = { .min = 5, .max = 9 },
311 .p = { .min = 5, .max = 80 },
312 .p1 = { .min = 1, .max = 8 },
313 .p2 = { .dot_limit = 225000,
314 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 315};
316
b91ad0ec 317static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 318 .dot = { .min = 25000, .max = 350000 },
319 .vco = { .min = 1760000, .max = 3510000 },
320 .n = { .min = 1, .max = 3 },
321 .m = { .min = 79, .max = 118 },
322 .m1 = { .min = 12, .max = 22 },
323 .m2 = { .min = 5, .max = 9 },
324 .p = { .min = 28, .max = 112 },
325 .p1 = { .min = 2, .max = 8 },
326 .p2 = { .dot_limit = 225000,
327 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 328};
329
330static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 331 .dot = { .min = 25000, .max = 350000 },
332 .vco = { .min = 1760000, .max = 3510000 },
333 .n = { .min = 1, .max = 3 },
334 .m = { .min = 79, .max = 127 },
335 .m1 = { .min = 12, .max = 22 },
336 .m2 = { .min = 5, .max = 9 },
337 .p = { .min = 14, .max = 56 },
338 .p1 = { .min = 2, .max = 8 },
339 .p2 = { .dot_limit = 225000,
340 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 341};
342
273e27ca 343/* LVDS 100mhz refclk limits. */
b91ad0ec 344static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 345 .dot = { .min = 25000, .max = 350000 },
346 .vco = { .min = 1760000, .max = 3510000 },
347 .n = { .min = 1, .max = 2 },
348 .m = { .min = 79, .max = 126 },
349 .m1 = { .min = 12, .max = 22 },
350 .m2 = { .min = 5, .max = 9 },
351 .p = { .min = 28, .max = 112 },
0206e353 352 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 353 .p2 = { .dot_limit = 225000,
354 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 355};
356
357static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 358 .dot = { .min = 25000, .max = 350000 },
359 .vco = { .min = 1760000, .max = 3510000 },
360 .n = { .min = 1, .max = 3 },
361 .m = { .min = 79, .max = 126 },
362 .m1 = { .min = 12, .max = 22 },
363 .m2 = { .min = 5, .max = 9 },
364 .p = { .min = 14, .max = 42 },
0206e353 365 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 366 .p2 = { .dot_limit = 225000,
367 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 368};
369
dc730512 370static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 371 /*
372 * These are the data rate limits (measured in fast clocks)
373 * since those are the strictest limits we have. The fast
374 * clock and actual rate limits are more relaxed, so checking
375 * them would make no difference.
376 */
377 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 378 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 379 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 380 .m1 = { .min = 2, .max = 3 },
381 .m2 = { .min = 11, .max = 156 },
b99ab663 382 .p1 = { .min = 2, .max = 3 },
5fdc9c49 383 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 384};
385
ef9348c8
CML		 386static const intel_limit_t intel_limits_chv = {
387 /*
388 * These are the data rate limits (measured in fast clocks)
389 * since those are the strictest limits we have. The fast
390 * clock and actual rate limits are more relaxed, so checking
391 * them would make no difference.
392 */
393 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 394 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 395 .n = { .min = 1, .max = 1 },
396 .m1 = { .min = 2, .max = 2 },
397 .m2 = { .min = 24 << 22, .max = 175 << 22 },
398 .p1 = { .min = 2, .max = 4 },
399 .p2 = { .p2_slow = 1, .p2_fast = 14 },
400};
401
6b4bf1c4
VS		 402static void vlv_clock(int refclk, intel_clock_t *clock)
403{
404 clock->m = clock->m1 * clock->m2;
405 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 406 if (WARN_ON(clock->n == 0 || clock->p == 0))
407 return;
fb03ac01
VS		 408 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
409 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
6b4bf1c4
VS		 410}
411
e0638cdf
PZ		 412/**
413 * Returns whether any output on the specified pipe is of the specified type
414 */
4093561b 415bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 416{
409ee761 417 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 418 struct intel_encoder *encoder;
419
409ee761 420 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 421 if (encoder->type == type)
422 return true;
423
424 return false;
425}
426
d0737e1d
ACO		 427/**
428 * Returns whether any output on the specified pipe will have the specified
429 * type after a staged modeset is complete, i.e., the same as
430 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
431 * encoder->crtc.
432 */
433static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
434{
435 struct drm_device *dev = crtc->base.dev;
436 struct intel_encoder *encoder;
437
438 for_each_intel_encoder(dev, encoder)
439 if (encoder->new_crtc == crtc && encoder->type == type)
440 return true;
441
442 return false;
443}
444
409ee761 445static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
1b894b59 446 int refclk)
2c07245f 447{
409ee761 448 struct drm_device *dev = crtc->base.dev;
2c07245f 449 const intel_limit_t *limit;
b91ad0ec 450
d0737e1d 451 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 452 if (intel_is_dual_link_lvds(dev)) {
1b894b59 453 if (refclk == 100000)
b91ad0ec
ZW		 454 limit = &intel_limits_ironlake_dual_lvds_100m;
455 else
456 limit = &intel_limits_ironlake_dual_lvds;
457 } else {
1b894b59 458 if (refclk == 100000)
b91ad0ec
ZW		 459 limit = &intel_limits_ironlake_single_lvds_100m;
460 else
461 limit = &intel_limits_ironlake_single_lvds;
462 }
c6bb3538 463 } else
b91ad0ec 464 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 465
466 return limit;
467}
468
409ee761 469static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
044c7c41 470{
409ee761 471 struct drm_device *dev = crtc->base.dev;
044c7c41
ML		 472 const intel_limit_t *limit;
473
d0737e1d 474 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 475 if (intel_is_dual_link_lvds(dev))
e4b36699 476 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 477 else
e4b36699 478 limit = &intel_limits_g4x_single_channel_lvds;
d0737e1d
ACO		 479 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
480 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 481 limit = &intel_limits_g4x_hdmi;
d0737e1d 482 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 483 limit = &intel_limits_g4x_sdvo;
044c7c41 484 } else /* The option is for other outputs */
e4b36699 485 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 486
487 return limit;
488}
489
409ee761 490static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
79e53945 491{
409ee761 492 struct drm_device *dev = crtc->base.dev;
79e53945
JB		 493 const intel_limit_t *limit;
494
bad720ff 495 if (HAS_PCH_SPLIT(dev))
1b894b59 496 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 497 else if (IS_G4X(dev)) {
044c7c41 498 limit = intel_g4x_limit(crtc);
f2b115e6 499 } else if (IS_PINEVIEW(dev)) {
d0737e1d 500 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 501 limit = &intel_limits_pineview_lvds;
2177832f 502 else
f2b115e6 503 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 504 } else if (IS_CHERRYVIEW(dev)) {
505 limit = &intel_limits_chv;
a0c4da24 506 } else if (IS_VALLEYVIEW(dev)) {
dc730512 507 limit = &intel_limits_vlv;
a6c45cf0 508 } else if (!IS_GEN2(dev)) {
d0737e1d 509 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 510 limit = &intel_limits_i9xx_lvds;
511 else
512 limit = &intel_limits_i9xx_sdvo;
79e53945 513 } else {
d0737e1d 514 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 515 limit = &intel_limits_i8xx_lvds;
d0737e1d 516 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
e4b36699 517 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 518 else
519 limit = &intel_limits_i8xx_dac;
79e53945
JB		 520 }
521 return limit;
522}
523
f2b115e6
AJ		 524/* m1 is reserved as 0 in Pineview, n is a ring counter */
525static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 526{
2177832f
SL		 527 clock->m = clock->m2 + 2;
528 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 529 if (WARN_ON(clock->n == 0 || clock->p == 0))
530 return;
fb03ac01
VS		 531 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
532 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
2177832f
SL		 533}
534
7429e9d4
DV		 535static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
536{
537 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
538}
539
ac58c3f0 540static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 541{
7429e9d4 542 clock->m = i9xx_dpll_compute_m(clock);
79e53945 543 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 544 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
545 return;
fb03ac01
VS		 546 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
547 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
79e53945
JB		 548}
549
ef9348c8
CML		 550static void chv_clock(int refclk, intel_clock_t *clock)
551{
552 clock->m = clock->m1 * clock->m2;
553 clock->p = clock->p1 * clock->p2;
554 if (WARN_ON(clock->n == 0 || clock->p == 0))
555 return;
556 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
557 clock->n << 22);
558 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
559}
560
7c04d1d9 561#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 562/**
563 * Returns whether the given set of divisors are valid for a given refclk with
564 * the given connectors.
565 */
566
1b894b59
CW		 567static bool intel_PLL_is_valid(struct drm_device *dev,
568 const intel_limit_t *limit,
569 const intel_clock_t *clock)
79e53945 570{
f01b7962
VS		 571 if (clock->n < limit->n.min || limit->n.max < clock->n)
572 INTELPllInvalid("n out of range\n");
79e53945 573 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 574 INTELPllInvalid("p1 out of range\n");
79e53945 575 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 576 INTELPllInvalid("m2 out of range\n");
79e53945 577 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 578 INTELPllInvalid("m1 out of range\n");
f01b7962
VS		 579
580 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
581 if (clock->m1 <= clock->m2)
582 INTELPllInvalid("m1 <= m2\n");
583
584 if (!IS_VALLEYVIEW(dev)) {
585 if (clock->p < limit->p.min || limit->p.max < clock->p)
586 INTELPllInvalid("p out of range\n");
587 if (clock->m < limit->m.min || limit->m.max < clock->m)
588 INTELPllInvalid("m out of range\n");
589 }
590
79e53945 591 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 592 INTELPllInvalid("vco out of range\n");
79e53945
JB		 593 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
594 * connector, etc., rather than just a single range.
595 */
596 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 597 INTELPllInvalid("dot out of range\n");
79e53945
JB		 598
599 return true;
600}
601
d4906093 602static bool
a919ff14 603i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
cec2f356
SP		 604 int target, int refclk, intel_clock_t *match_clock,
605 intel_clock_t *best_clock)
79e53945 606{
a919ff14 607 struct drm_device *dev = crtc->base.dev;
79e53945 608 intel_clock_t clock;
79e53945
JB		 609 int err = target;
610
d0737e1d 611 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 612 /*
a210b028
DV		 613 * For LVDS just rely on its current settings for dual-channel.
614 * We haven't figured out how to reliably set up different
615 * single/dual channel state, if we even can.
79e53945 616 */
1974cad0 617 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 618 clock.p2 = limit->p2.p2_fast;
619 else
620 clock.p2 = limit->p2.p2_slow;
621 } else {
622 if (target < limit->p2.dot_limit)
623 clock.p2 = limit->p2.p2_slow;
624 else
625 clock.p2 = limit->p2.p2_fast;
626 }
627
0206e353 628 memset(best_clock, 0, sizeof(*best_clock));
79e53945 629
42158660
ZY		 630 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
631 clock.m1++) {
632 for (clock.m2 = limit->m2.min;
633 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 634 if (clock.m2 >= clock.m1)
42158660
ZY		 635 break;
636 for (clock.n = limit->n.min;
637 clock.n <= limit->n.max; clock.n++) {
638 for (clock.p1 = limit->p1.min;
639 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 640 int this_err;
641
ac58c3f0
DV		 642 i9xx_clock(refclk, &clock);
643 if (!intel_PLL_is_valid(dev, limit,
644 &clock))
645 continue;
646 if (match_clock &&
647 clock.p != match_clock->p)
648 continue;
649
650 this_err = abs(clock.dot - target);
651 if (this_err < err) {
652 *best_clock = clock;
653 err = this_err;
654 }
655 }
656 }
657 }
658 }
659
660 return (err != target);
661}
662
663static bool
a919ff14 664pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
ee9300bb
DV		 665 int target, int refclk, intel_clock_t *match_clock,
666 intel_clock_t *best_clock)
79e53945 667{
a919ff14 668 struct drm_device *dev = crtc->base.dev;
79e53945 669 intel_clock_t clock;
79e53945
JB		 670 int err = target;
671
d0737e1d 672 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 673 /*
a210b028
DV		 674 * For LVDS just rely on its current settings for dual-channel.
675 * We haven't figured out how to reliably set up different
676 * single/dual channel state, if we even can.
79e53945 677 */
1974cad0 678 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 679 clock.p2 = limit->p2.p2_fast;
680 else
681 clock.p2 = limit->p2.p2_slow;
682 } else {
683 if (target < limit->p2.dot_limit)
684 clock.p2 = limit->p2.p2_slow;
685 else
686 clock.p2 = limit->p2.p2_fast;
687 }
688
0206e353 689 memset(best_clock, 0, sizeof(*best_clock));
79e53945 690
42158660
ZY		 691 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
692 clock.m1++) {
693 for (clock.m2 = limit->m2.min;
694 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 695 for (clock.n = limit->n.min;
696 clock.n <= limit->n.max; clock.n++) {
697 for (clock.p1 = limit->p1.min;
698 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 699 int this_err;
700
ac58c3f0 701 pineview_clock(refclk, &clock);
1b894b59
CW		 702 if (!intel_PLL_is_valid(dev, limit,
703 &clock))
79e53945 704 continue;
cec2f356
SP		 705 if (match_clock &&
706 clock.p != match_clock->p)
707 continue;
79e53945
JB		 708
709 this_err = abs(clock.dot - target);
710 if (this_err < err) {
711 *best_clock = clock;
712 err = this_err;
713 }
714 }
715 }
716 }
717 }
718
719 return (err != target);
720}
721
d4906093 722static bool
a919ff14 723g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
ee9300bb
DV		 724 int target, int refclk, intel_clock_t *match_clock,
725 intel_clock_t *best_clock)
d4906093 726{
a919ff14 727 struct drm_device *dev = crtc->base.dev;
d4906093
ML		 728 intel_clock_t clock;
729 int max_n;
730 bool found;
6ba770dc
AJ		 731 /* approximately equals target * 0.00585 */
732 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 733 found = false;
734
d0737e1d 735 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 736 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 737 clock.p2 = limit->p2.p2_fast;
738 else
739 clock.p2 = limit->p2.p2_slow;
740 } else {
741 if (target < limit->p2.dot_limit)
742 clock.p2 = limit->p2.p2_slow;
743 else
744 clock.p2 = limit->p2.p2_fast;
745 }
746
747 memset(best_clock, 0, sizeof(*best_clock));
748 max_n = limit->n.max;
f77f13e2 749 /* based on hardware requirement, prefer smaller n to precision */
d4906093 750 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 751 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 752 for (clock.m1 = limit->m1.max;
753 clock.m1 >= limit->m1.min; clock.m1--) {
754 for (clock.m2 = limit->m2.max;
755 clock.m2 >= limit->m2.min; clock.m2--) {
756 for (clock.p1 = limit->p1.max;
757 clock.p1 >= limit->p1.min; clock.p1--) {
758 int this_err;
759
ac58c3f0 760 i9xx_clock(refclk, &clock);
1b894b59
CW		 761 if (!intel_PLL_is_valid(dev, limit,
762 &clock))
d4906093 763 continue;
1b894b59
CW		 764
765 this_err = abs(clock.dot - target);
d4906093
ML		 766 if (this_err < err_most) {
767 *best_clock = clock;
768 err_most = this_err;
769 max_n = clock.n;
770 found = true;
771 }
772 }
773 }
774 }
775 }
2c07245f
ZW		 776 return found;
777}
778
d5dd62bd
ID		 779/*
780 * Check if the calculated PLL configuration is more optimal compared to the
781 * best configuration and error found so far. Return the calculated error.
782 */
783static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
784 const intel_clock_t *calculated_clock,
785 const intel_clock_t *best_clock,
786 unsigned int best_error_ppm,
787 unsigned int *error_ppm)
788{
9ca3ba01
ID		 789 /*
790 * For CHV ignore the error and consider only the P value.
791 * Prefer a bigger P value based on HW requirements.
792 */
793 if (IS_CHERRYVIEW(dev)) {
794 *error_ppm = 0;
795
796 return calculated_clock->p > best_clock->p;
797 }
798
24be4e46
ID		 799 if (WARN_ON_ONCE(!target_freq))
800 return false;
801
d5dd62bd
ID		 802 *error_ppm = div_u64(1000000ULL *
803 abs(target_freq - calculated_clock->dot),
804 target_freq);
805 /*
806 * Prefer a better P value over a better (smaller) error if the error
807 * is small. Ensure this preference for future configurations too by
808 * setting the error to 0.
809 */
810 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
811 *error_ppm = 0;
812
813 return true;
814 }
815
816 return *error_ppm + 10 < best_error_ppm;
817}
818
a0c4da24 819static bool
a919ff14 820vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
ee9300bb
DV		 821 int target, int refclk, intel_clock_t *match_clock,
822 intel_clock_t *best_clock)
a0c4da24 823{
a919ff14 824 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 825 intel_clock_t clock;
69e4f900 826 unsigned int bestppm = 1000000;
27e639bf
VS		 827 /* min update 19.2 MHz */
828 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 829 bool found = false;
a0c4da24 830
6b4bf1c4
VS		 831 target *= 5; /* fast clock */
832
833 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 834
835 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 836 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 837 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 838 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 839 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 840 clock.p = clock.p1 * clock.p2;
a0c4da24 841 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 842 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 843 unsigned int ppm;
69e4f900 844
6b4bf1c4
VS		 845 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
846 refclk * clock.m1);
847
848 vlv_clock(refclk, &clock);
43b0ac53 849
f01b7962
VS		 850 if (!intel_PLL_is_valid(dev, limit,
851 &clock))
43b0ac53
VS		 852 continue;
853
d5dd62bd
ID		 854 if (!vlv_PLL_is_optimal(dev, target,
855 &clock,
856 best_clock,
857 bestppm, &ppm))
858 continue;
6b4bf1c4 859
d5dd62bd
ID		 860 *best_clock = clock;
861 bestppm = ppm;
862 found = true;
a0c4da24
JB		 863 }
864 }
865 }
866 }
a0c4da24 867
49e497ef 868 return found;
a0c4da24 869}
a4fc5ed6 870
ef9348c8 871static bool
a919ff14 872chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
ef9348c8
CML		 873 int target, int refclk, intel_clock_t *match_clock,
874 intel_clock_t *best_clock)
875{
a919ff14 876 struct drm_device *dev = crtc->base.dev;
9ca3ba01 877 unsigned int best_error_ppm;
ef9348c8
CML		 878 intel_clock_t clock;
879 uint64_t m2;
880 int found = false;
881
882 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 883 best_error_ppm = 1000000;
ef9348c8
CML		 884
885 /*
886 * Based on hardware doc, the n always set to 1, and m1 always
887 * set to 2. If requires to support 200Mhz refclk, we need to
888 * revisit this because n may not 1 anymore.
889 */
890 clock.n = 1, clock.m1 = 2;
891 target *= 5; /* fast clock */
892
893 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
894 for (clock.p2 = limit->p2.p2_fast;
895 clock.p2 >= limit->p2.p2_slow;
896 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 897 unsigned int error_ppm;
ef9348c8
CML		 898
899 clock.p = clock.p1 * clock.p2;
900
901 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
902 clock.n) << 22, refclk * clock.m1);
903
904 if (m2 > INT_MAX/clock.m1)
905 continue;
906
907 clock.m2 = m2;
908
909 chv_clock(refclk, &clock);
910
911 if (!intel_PLL_is_valid(dev, limit, &clock))
912 continue;
913
9ca3ba01
ID		 914 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
915 best_error_ppm, &error_ppm))
916 continue;
917
918 *best_clock = clock;
919 best_error_ppm = error_ppm;
920 found = true;
ef9348c8
CML		 921 }
922 }
923
924 return found;
925}
926
20ddf665
VS		 927bool intel_crtc_active(struct drm_crtc *crtc)
928{
929 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
930
931 /* Be paranoid as we can arrive here with only partial
932 * state retrieved from the hardware during setup.
933 *
241bfc38 934 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 935 * as Haswell has gained clock readout/fastboot support.
936 *
66e514c1 937 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 938 * properly reconstruct framebuffers.
c3d1f436
MR		 939 *
940 * FIXME: The intel_crtc->active here should be switched to
941 * crtc->state->active once we have proper CRTC states wired up
942 * for atomic.
20ddf665 943 */
c3d1f436 944 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 945 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 946}
947
a5c961d1
PZ		 948enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
949 enum pipe pipe)
950{
951 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
952 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
953
6e3c9717 954 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 955}
956
fbf49ea2
VS		 957static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
958{
959 struct drm_i915_private *dev_priv = dev->dev_private;
960 u32 reg = PIPEDSL(pipe);
961 u32 line1, line2;
962 u32 line_mask;
963
964 if (IS_GEN2(dev))
965 line_mask = DSL_LINEMASK_GEN2;
966 else
967 line_mask = DSL_LINEMASK_GEN3;
968
969 line1 = I915_READ(reg) & line_mask;
970 mdelay(5);
971 line2 = I915_READ(reg) & line_mask;
972
973 return line1 == line2;
974}
975
ab7ad7f6
KP		 976/*
977 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 978 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 979 *
980 * After disabling a pipe, we can't wait for vblank in the usual way,
981 * spinning on the vblank interrupt status bit, since we won't actually
982 * see an interrupt when the pipe is disabled.
983 *
ab7ad7f6
KP		 984 * On Gen4 and above:
985 * wait for the pipe register state bit to turn off
986 *
987 * Otherwise:
988 * wait for the display line value to settle (it usually
989 * ends up stopping at the start of the next frame).
58e10eb9 990 *
9d0498a2 991 */
575f7ab7 992static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 993{
575f7ab7 994 struct drm_device *dev = crtc->base.dev;
9d0498a2 995 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 996 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 997 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 998
999 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1000 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1001
1002 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1003 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1004 100))
284637d9 1005 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1006 } else {
ab7ad7f6 1007 /* Wait for the display line to settle */
fbf49ea2 1008 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1009 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1010 }
79e53945
JB		 1011}
1012
b0ea7d37
DL		 1013/*
1014 * ibx_digital_port_connected - is the specified port connected?
1015 * @dev_priv: i915 private structure
1016 * @port: the port to test
1017 *
1018 * Returns true if @port is connected, false otherwise.
1019 */
1020bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1021 struct intel_digital_port *port)
1022{
1023 u32 bit;
1024
c36346e3 1025 if (HAS_PCH_IBX(dev_priv->dev)) {
eba905b2 1026 switch (port->port) {
c36346e3
DL		 1027 case PORT_B:
1028 bit = SDE_PORTB_HOTPLUG;
1029 break;
1030 case PORT_C:
1031 bit = SDE_PORTC_HOTPLUG;
1032 break;
1033 case PORT_D:
1034 bit = SDE_PORTD_HOTPLUG;
1035 break;
1036 default:
1037 return true;
1038 }
1039 } else {
eba905b2 1040 switch (port->port) {
c36346e3
DL		 1041 case PORT_B:
1042 bit = SDE_PORTB_HOTPLUG_CPT;
1043 break;
1044 case PORT_C:
1045 bit = SDE_PORTC_HOTPLUG_CPT;
1046 break;
1047 case PORT_D:
1048 bit = SDE_PORTD_HOTPLUG_CPT;
1049 break;
1050 default:
1051 return true;
1052 }
b0ea7d37
DL		 1053 }
1054
1055 return I915_READ(SDEISR) & bit;
1056}
1057
b24e7179
JB		 1058static const char *state_string(bool enabled)
1059{
1060 return enabled ? "on" : "off";
1061}
1062
1063/* Only for pre-ILK configs */
55607e8a
DV		 1064void assert_pll(struct drm_i915_private *dev_priv,
1065 enum pipe pipe, bool state)
b24e7179
JB		 1066{
1067 int reg;
1068 u32 val;
1069 bool cur_state;
1070
1071 reg = DPLL(pipe);
1072 val = I915_READ(reg);
1073 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1074 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1075 "PLL state assertion failure (expected %s, current %s)\n",
1076 state_string(state), state_string(cur_state));
1077}
b24e7179 1078
23538ef1
JN		 1079/* XXX: the dsi pll is shared between MIPI DSI ports */
1080static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1081{
1082 u32 val;
1083 bool cur_state;
1084
1085 mutex_lock(&dev_priv->dpio_lock);
1086 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1087 mutex_unlock(&dev_priv->dpio_lock);
1088
1089 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1090 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1091 "DSI PLL state assertion failure (expected %s, current %s)\n",
1092 state_string(state), state_string(cur_state));
1093}
1094#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1095#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1096
55607e8a 1097struct intel_shared_dpll *
e2b78267
DV		 1098intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1099{
1100 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1101
6e3c9717 1102 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1103 return NULL;
1104
6e3c9717 1105 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1106}
1107
040484af 1108/* For ILK+ */
55607e8a
DV		 1109void assert_shared_dpll(struct drm_i915_private *dev_priv,
1110 struct intel_shared_dpll *pll,
1111 bool state)
040484af 1112{
040484af 1113 bool cur_state;
5358901f 1114 struct intel_dpll_hw_state hw_state;
040484af 1115
92b27b08 1116 if (WARN (!pll,
46edb027 1117 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1118 return;
ee7b9f93 1119
5358901f 1120 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1121 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1122 "%s assertion failure (expected %s, current %s)\n",
1123 pll->name, state_string(state), state_string(cur_state));
040484af 1124}
040484af
JB		 1125
1126static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1127 enum pipe pipe, bool state)
1128{
1129 int reg;
1130 u32 val;
1131 bool cur_state;
ad80a810
PZ		 1132 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1133 pipe);
040484af 1134
affa9354
PZ		 1135 if (HAS_DDI(dev_priv->dev)) {
1136 /* DDI does not have a specific FDI_TX register */
ad80a810 1137 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1138 val = I915_READ(reg);
ad80a810 1139 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1140 } else {
1141 reg = FDI_TX_CTL(pipe);
1142 val = I915_READ(reg);
1143 cur_state = !!(val & FDI_TX_ENABLE);
1144 }
e2c719b7 1145 I915_STATE_WARN(cur_state != state,
040484af
JB		 1146 "FDI TX state assertion failure (expected %s, current %s)\n",
1147 state_string(state), state_string(cur_state));
1148}
1149#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1150#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1151
1152static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1153 enum pipe pipe, bool state)
1154{
1155 int reg;
1156 u32 val;
1157 bool cur_state;
1158
d63fa0dc
PZ		 1159 reg = FDI_RX_CTL(pipe);
1160 val = I915_READ(reg);
1161 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1162 I915_STATE_WARN(cur_state != state,
040484af
JB		 1163 "FDI RX state assertion failure (expected %s, current %s)\n",
1164 state_string(state), state_string(cur_state));
1165}
1166#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1167#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1168
1169static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1170 enum pipe pipe)
1171{
1172 int reg;
1173 u32 val;
1174
1175 /* ILK FDI PLL is always enabled */
3d13ef2e 1176 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1177 return;
1178
bf507ef7 1179 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1180 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1181 return;
1182
040484af
JB		 1183 reg = FDI_TX_CTL(pipe);
1184 val = I915_READ(reg);
e2c719b7 1185 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1186}
1187
55607e8a
DV		 1188void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1189 enum pipe pipe, bool state)
040484af
JB		 1190{
1191 int reg;
1192 u32 val;
55607e8a 1193 bool cur_state;
040484af
JB		 1194
1195 reg = FDI_RX_CTL(pipe);
1196 val = I915_READ(reg);
55607e8a 1197 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1198 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1199 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1200 state_string(state), state_string(cur_state));
040484af
JB		 1201}
1202
b680c37a
DV		 1203void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1204 enum pipe pipe)
ea0760cf 1205{
bedd4dba
JN		 1206 struct drm_device *dev = dev_priv->dev;
1207 int pp_reg;
ea0760cf
JB		 1208 u32 val;
1209 enum pipe panel_pipe = PIPE_A;
0de3b485 1210 bool locked = true;
ea0760cf 1211
bedd4dba
JN		 1212 if (WARN_ON(HAS_DDI(dev)))
1213 return;
1214
1215 if (HAS_PCH_SPLIT(dev)) {
1216 u32 port_sel;
1217
ea0760cf 1218 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1219 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1220
1221 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1222 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1223 panel_pipe = PIPE_B;
1224 /* XXX: else fix for eDP */
1225 } else if (IS_VALLEYVIEW(dev)) {
1226 /* presumably write lock depends on pipe, not port select */
1227 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1228 panel_pipe = pipe;
ea0760cf
JB		 1229 } else {
1230 pp_reg = PP_CONTROL;
bedd4dba
JN		 1231 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1232 panel_pipe = PIPE_B;
ea0760cf
JB		 1233 }
1234
1235 val = I915_READ(pp_reg);
1236 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1237 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1238 locked = false;
1239
e2c719b7 1240 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1241 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1242 pipe_name(pipe));
ea0760cf
JB		 1243}
1244
93ce0ba6
JN		 1245static void assert_cursor(struct drm_i915_private *dev_priv,
1246 enum pipe pipe, bool state)
1247{
1248 struct drm_device *dev = dev_priv->dev;
1249 bool cur_state;
1250
d9d82081 1251 if (IS_845G(dev) || IS_I865G(dev))
93ce0ba6 1252 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
d9d82081 1253 else
5efb3e28 1254 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1255
e2c719b7 1256 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1257 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1258 pipe_name(pipe), state_string(state), state_string(cur_state));
1259}
1260#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1261#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1262
b840d907
JB		 1263void assert_pipe(struct drm_i915_private *dev_priv,
1264 enum pipe pipe, bool state)
b24e7179
JB		 1265{
1266 int reg;
1267 u32 val;
63d7bbe9 1268 bool cur_state;
702e7a56
PZ		 1269 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1270 pipe);
b24e7179 1271
b6b5d049
VS		 1272 /* if we need the pipe quirk it must be always on */
1273 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1274 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1275 state = true;
1276
f458ebbc 1277 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1278 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1279 cur_state = false;
1280 } else {
1281 reg = PIPECONF(cpu_transcoder);
1282 val = I915_READ(reg);
1283 cur_state = !!(val & PIPECONF_ENABLE);
1284 }
1285
e2c719b7 1286 I915_STATE_WARN(cur_state != state,
63d7bbe9 1287 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1288 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1289}
1290
931872fc
CW		 1291static void assert_plane(struct drm_i915_private *dev_priv,
1292 enum plane plane, bool state)
b24e7179
JB		 1293{
1294 int reg;
1295 u32 val;
931872fc 1296 bool cur_state;
b24e7179
JB		 1297
1298 reg = DSPCNTR(plane);
1299 val = I915_READ(reg);
931872fc 1300 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1301 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1302 "plane %c assertion failure (expected %s, current %s)\n",
1303 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1304}
1305
931872fc
CW		 1306#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1307#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1308
b24e7179
JB		 1309static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1310 enum pipe pipe)
1311{
653e1026 1312 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1313 int reg, i;
1314 u32 val;
1315 int cur_pipe;
1316
653e1026
VS		 1317 /* Primary planes are fixed to pipes on gen4+ */
1318 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1319 reg = DSPCNTR(pipe);
1320 val = I915_READ(reg);
e2c719b7 1321 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1322 "plane %c assertion failure, should be disabled but not\n",
1323 plane_name(pipe));
19ec1358 1324 return;
28c05794 1325 }
19ec1358 1326
b24e7179 1327 /* Need to check both planes against the pipe */
055e393f 1328 for_each_pipe(dev_priv, i) {
b24e7179
JB		 1329 reg = DSPCNTR(i);
1330 val = I915_READ(reg);
1331 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1332 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1333 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1334 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1335 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1336 }
1337}
1338
19332d7a
JB		 1339static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1340 enum pipe pipe)
1341{
20674eef 1342 struct drm_device *dev = dev_priv->dev;
1fe47785 1343 int reg, sprite;
19332d7a
JB		 1344 u32 val;
1345
7feb8b88 1346 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1347 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1348 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1349 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1350 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1351 sprite, pipe_name(pipe));
1352 }
1353 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1354 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1355 reg = SPCNTR(pipe, sprite);
20674eef 1356 val = I915_READ(reg);
e2c719b7 1357 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1358 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1359 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1360 }
1361 } else if (INTEL_INFO(dev)->gen >= 7) {
1362 reg = SPRCTL(pipe);
19332d7a 1363 val = I915_READ(reg);
e2c719b7 1364 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1365 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1366 plane_name(pipe), pipe_name(pipe));
1367 } else if (INTEL_INFO(dev)->gen >= 5) {
1368 reg = DVSCNTR(pipe);
19332d7a 1369 val = I915_READ(reg);
e2c719b7 1370 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1371 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1372 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1373 }
1374}
1375
08c71e5e
VS		 1376static void assert_vblank_disabled(struct drm_crtc *crtc)
1377{
e2c719b7 1378 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1379 drm_crtc_vblank_put(crtc);
1380}
1381
89eff4be 1382static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1383{
1384 u32 val;
1385 bool enabled;
1386
e2c719b7 1387 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1388
92f2584a
JB		 1389 val = I915_READ(PCH_DREF_CONTROL);
1390 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1391 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1392 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1393}
1394
ab9412ba
DV		 1395static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1396 enum pipe pipe)
92f2584a
JB		 1397{
1398 int reg;
1399 u32 val;
1400 bool enabled;
1401
ab9412ba 1402 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1403 val = I915_READ(reg);
1404 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1405 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1406 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1407 pipe_name(pipe));
92f2584a
JB		 1408}
1409
4e634389
KP		 1410static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1411 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1412{
1413 if ((val & DP_PORT_EN) == 0)
1414 return false;
1415
1416 if (HAS_PCH_CPT(dev_priv->dev)) {
1417 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1418 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1419 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1420 return false;
44f37d1f
CML		 1421 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1422 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1423 return false;
f0575e92
KP		 1424 } else {
1425 if ((val & DP_PIPE_MASK) != (pipe << 30))
1426 return false;
1427 }
1428 return true;
1429}
1430
1519b995
KP		 1431static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1432 enum pipe pipe, u32 val)
1433{
dc0fa718 1434 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1435 return false;
1436
1437 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1438 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1439 return false;
44f37d1f
CML		 1440 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1441 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1442 return false;
1519b995 1443 } else {
dc0fa718 1444 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1445 return false;
1446 }
1447 return true;
1448}
1449
1450static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1451 enum pipe pipe, u32 val)
1452{
1453 if ((val & LVDS_PORT_EN) == 0)
1454 return false;
1455
1456 if (HAS_PCH_CPT(dev_priv->dev)) {
1457 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1458 return false;
1459 } else {
1460 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1461 return false;
1462 }
1463 return true;
1464}
1465
1466static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1467 enum pipe pipe, u32 val)
1468{
1469 if ((val & ADPA_DAC_ENABLE) == 0)
1470 return false;
1471 if (HAS_PCH_CPT(dev_priv->dev)) {
1472 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1473 return false;
1474 } else {
1475 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1476 return false;
1477 }
1478 return true;
1479}
1480
291906f1 1481static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1482 enum pipe pipe, int reg, u32 port_sel)
291906f1 1483{
47a05eca 1484 u32 val = I915_READ(reg);
e2c719b7 1485 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1486 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1487 reg, pipe_name(pipe));
de9a35ab 1488
e2c719b7 1489 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1490 && (val & DP_PIPEB_SELECT),
de9a35ab 1491 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1492}
1493
1494static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1495 enum pipe pipe, int reg)
1496{
47a05eca 1497 u32 val = I915_READ(reg);
e2c719b7 1498 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1499 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1500 reg, pipe_name(pipe));
de9a35ab 1501
e2c719b7 1502 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1503 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1504 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1505}
1506
1507static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1508 enum pipe pipe)
1509{
1510 int reg;
1511 u32 val;
291906f1 1512
f0575e92
KP		 1513 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1514 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1515 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1516
1517 reg = PCH_ADPA;
1518 val = I915_READ(reg);
e2c719b7 1519 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1520 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1521 pipe_name(pipe));
291906f1
JB		 1522
1523 reg = PCH_LVDS;
1524 val = I915_READ(reg);
e2c719b7 1525 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1526 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1527 pipe_name(pipe));
291906f1 1528
e2debe91
PZ		 1529 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1530 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1531 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1532}
1533
40e9cf64
JB		 1534static void intel_init_dpio(struct drm_device *dev)
1535{
1536 struct drm_i915_private *dev_priv = dev->dev_private;
1537
1538 if (!IS_VALLEYVIEW(dev))
1539 return;
1540
a09caddd
CML		 1541 /*
1542 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1543 * CHV x1 PHY (DP/HDMI D)
1544 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1545 */
1546 if (IS_CHERRYVIEW(dev)) {
1547 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1548 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1549 } else {
1550 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1551 }
5382f5f3
JB		 1552}
1553
d288f65f 1554static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1555 const struct intel_crtc_state *pipe_config)
87442f73 1556{
426115cf
DV		 1557 struct drm_device *dev = crtc->base.dev;
1558 struct drm_i915_private *dev_priv = dev->dev_private;
1559 int reg = DPLL(crtc->pipe);
d288f65f 1560 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1561
426115cf 1562 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1563
1564 /* No really, not for ILK+ */
1565 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1566
1567 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1568 if (IS_MOBILE(dev_priv->dev))
426115cf 1569 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1570
426115cf
DV		 1571 I915_WRITE(reg, dpll);
1572 POSTING_READ(reg);
1573 udelay(150);
1574
1575 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1576 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1577
d288f65f 1578 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1579 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1580
1581 /* We do this three times for luck */
426115cf 1582 I915_WRITE(reg, dpll);
87442f73
DV		 1583 POSTING_READ(reg);
1584 udelay(150); /* wait for warmup */
426115cf 1585 I915_WRITE(reg, dpll);
87442f73
DV		 1586 POSTING_READ(reg);
1587 udelay(150); /* wait for warmup */
426115cf 1588 I915_WRITE(reg, dpll);
87442f73
DV		 1589 POSTING_READ(reg);
1590 udelay(150); /* wait for warmup */
1591}
1592
d288f65f 1593static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1594 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1595{
1596 struct drm_device *dev = crtc->base.dev;
1597 struct drm_i915_private *dev_priv = dev->dev_private;
1598 int pipe = crtc->pipe;
1599 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1600 u32 tmp;
1601
1602 assert_pipe_disabled(dev_priv, crtc->pipe);
1603
1604 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1605
1606 mutex_lock(&dev_priv->dpio_lock);
1607
1608 /* Enable back the 10bit clock to display controller */
1609 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1610 tmp |= DPIO_DCLKP_EN;
1611 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1612
1613 /*
1614 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1615 */
1616 udelay(1);
1617
1618 /* Enable PLL */
d288f65f 1619 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1620
1621 /* Check PLL is locked */
a11b0703 1622 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1623 DRM_ERROR("PLL %d failed to lock\n", pipe);
1624
a11b0703 1625 /* not sure when this should be written */
d288f65f 1626 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703
VS		 1627 POSTING_READ(DPLL_MD(pipe));
1628
9d556c99
CML		 1629 mutex_unlock(&dev_priv->dpio_lock);
1630}
1631
1c4e0274
VS		 1632static int intel_num_dvo_pipes(struct drm_device *dev)
1633{
1634 struct intel_crtc *crtc;
1635 int count = 0;
1636
1637 for_each_intel_crtc(dev, crtc)
1638 count += crtc->active &&
409ee761 1639 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1640
1641 return count;
1642}
1643
66e3d5c0 1644static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1645{
66e3d5c0
DV		 1646 struct drm_device *dev = crtc->base.dev;
1647 struct drm_i915_private *dev_priv = dev->dev_private;
1648 int reg = DPLL(crtc->pipe);
6e3c9717 1649 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1650
66e3d5c0 1651 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1652
63d7bbe9 1653 /* No really, not for ILK+ */
3d13ef2e 1654 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1655
1656 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1657 if (IS_MOBILE(dev) && !IS_I830(dev))
1658 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1659
1c4e0274
VS		 1660 /* Enable DVO 2x clock on both PLLs if necessary */
1661 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1662 /*
1663 * It appears to be important that we don't enable this
1664 * for the current pipe before otherwise configuring the
1665 * PLL. No idea how this should be handled if multiple
1666 * DVO outputs are enabled simultaneosly.
1667 */
1668 dpll |= DPLL_DVO_2X_MODE;
1669 I915_WRITE(DPLL(!crtc->pipe),
1670 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1671 }
66e3d5c0
DV		 1672
1673 /* Wait for the clocks to stabilize. */
1674 POSTING_READ(reg);
1675 udelay(150);
1676
1677 if (INTEL_INFO(dev)->gen >= 4) {
1678 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1679 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1680 } else {
1681 /* The pixel multiplier can only be updated once the
1682 * DPLL is enabled and the clocks are stable.
1683 *
1684 * So write it again.
1685 */
1686 I915_WRITE(reg, dpll);
1687 }
63d7bbe9
JB		 1688
1689 /* We do this three times for luck */
66e3d5c0 1690 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1691 POSTING_READ(reg);
1692 udelay(150); /* wait for warmup */
66e3d5c0 1693 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1694 POSTING_READ(reg);
1695 udelay(150); /* wait for warmup */
66e3d5c0 1696 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1697 POSTING_READ(reg);
1698 udelay(150); /* wait for warmup */
1699}
1700
1701/**
50b44a44 1702 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1703 * @dev_priv: i915 private structure
1704 * @pipe: pipe PLL to disable
1705 *
1706 * Disable the PLL for @pipe, making sure the pipe is off first.
1707 *
1708 * Note! This is for pre-ILK only.
1709 */
1c4e0274 1710static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1711{
1c4e0274
VS		 1712 struct drm_device *dev = crtc->base.dev;
1713 struct drm_i915_private *dev_priv = dev->dev_private;
1714 enum pipe pipe = crtc->pipe;
1715
1716 /* Disable DVO 2x clock on both PLLs if necessary */
1717 if (IS_I830(dev) &&
409ee761 1718 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1c4e0274
VS		 1719 intel_num_dvo_pipes(dev) == 1) {
1720 I915_WRITE(DPLL(PIPE_B),
1721 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1722 I915_WRITE(DPLL(PIPE_A),
1723 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1724 }
1725
b6b5d049
VS		 1726 /* Don't disable pipe or pipe PLLs if needed */
1727 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1728 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1729 return;
1730
1731 /* Make sure the pipe isn't still relying on us */
1732 assert_pipe_disabled(dev_priv, pipe);
1733
50b44a44
DV		 1734 I915_WRITE(DPLL(pipe), 0);
1735 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1736}
1737
f6071166
JB		 1738static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1739{
1740 u32 val = 0;
1741
1742 /* Make sure the pipe isn't still relying on us */
1743 assert_pipe_disabled(dev_priv, pipe);
1744
e5cbfbfb
ID		 1745 /*
1746 * Leave integrated clock source and reference clock enabled for pipe B.
1747 * The latter is needed for VGA hotplug / manual detection.
1748 */
f6071166 1749 if (pipe == PIPE_B)
e5cbfbfb 1750 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
f6071166
JB		 1751 I915_WRITE(DPLL(pipe), val);
1752 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1753
1754}
1755
1756static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1757{
d752048d 1758 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1759 u32 val;
1760
a11b0703
VS		 1761 /* Make sure the pipe isn't still relying on us */
1762 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1763
a11b0703 1764 /* Set PLL en = 0 */
d17ec4ce 1765 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
a11b0703
VS		 1766 if (pipe != PIPE_A)
1767 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1768 I915_WRITE(DPLL(pipe), val);
1769 POSTING_READ(DPLL(pipe));
d752048d
VS		 1770
1771 mutex_lock(&dev_priv->dpio_lock);
1772
1773 /* Disable 10bit clock to display controller */
1774 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1775 val &= ~DPIO_DCLKP_EN;
1776 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1777
61407f6d
VS		 1778 /* disable left/right clock distribution */
1779 if (pipe != PIPE_B) {
1780 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1781 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1782 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1783 } else {
1784 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1785 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1786 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1787 }
1788
d752048d 1789 mutex_unlock(&dev_priv->dpio_lock);
f6071166
JB		 1790}
1791
e4607fcf
CML		 1792void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1793 struct intel_digital_port *dport)
89b667f8
JB		 1794{
1795 u32 port_mask;
00fc31b7 1796 int dpll_reg;
89b667f8 1797
e4607fcf
CML		 1798 switch (dport->port) {
1799 case PORT_B:
89b667f8 1800 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1801 dpll_reg = DPLL(0);
e4607fcf
CML		 1802 break;
1803 case PORT_C:
89b667f8 1804 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7
CML		 1805 dpll_reg = DPLL(0);
1806 break;
1807 case PORT_D:
1808 port_mask = DPLL_PORTD_READY_MASK;
1809 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1810 break;
1811 default:
1812 BUG();
1813 }
89b667f8 1814
00fc31b7 1815 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
89b667f8 1816 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
00fc31b7 1817 port_name(dport->port), I915_READ(dpll_reg));
89b667f8
JB		 1818}
1819
b14b1055
DV		 1820static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1821{
1822 struct drm_device *dev = crtc->base.dev;
1823 struct drm_i915_private *dev_priv = dev->dev_private;
1824 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1825
be19f0ff
CW		 1826 if (WARN_ON(pll == NULL))
1827 return;
1828
3e369b76 1829 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1830 if (pll->active == 0) {
1831 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1832 WARN_ON(pll->on);
1833 assert_shared_dpll_disabled(dev_priv, pll);
1834
1835 pll->mode_set(dev_priv, pll);
1836 }
1837}
1838
92f2584a 1839/**
85b3894f 1840 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1841 * @dev_priv: i915 private structure
1842 * @pipe: pipe PLL to enable
1843 *
1844 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1845 * drives the transcoder clock.
1846 */
85b3894f 1847static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1848{
3d13ef2e
DL		 1849 struct drm_device *dev = crtc->base.dev;
1850 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1851 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1852
87a875bb 1853 if (WARN_ON(pll == NULL))
48da64a8
CW		 1854 return;
1855
3e369b76 1856 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1857 return;
ee7b9f93 1858
74dd6928 1859 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1860 pll->name, pll->active, pll->on,
e2b78267 1861 crtc->base.base.id);
92f2584a 1862
cdbd2316
DV		 1863 if (pll->active++) {
1864 WARN_ON(!pll->on);
e9d6944e 1865 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1866 return;
1867 }
f4a091c7 1868 WARN_ON(pll->on);
ee7b9f93 1869
bd2bb1b9
PZ		 1870 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1871
46edb027 1872 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1873 pll->enable(dev_priv, pll);
ee7b9f93 1874 pll->on = true;
92f2584a
JB		 1875}
1876
f6daaec2 1877static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1878{
3d13ef2e
DL		 1879 struct drm_device *dev = crtc->base.dev;
1880 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1881 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1882
92f2584a 1883 /* PCH only available on ILK+ */
3d13ef2e 1884 BUG_ON(INTEL_INFO(dev)->gen < 5);
87a875bb 1885 if (WARN_ON(pll == NULL))
ee7b9f93 1886 return;
92f2584a 1887
3e369b76 1888 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1889 return;
7a419866 1890
46edb027
DV		 1891 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1892 pll->name, pll->active, pll->on,
e2b78267 1893 crtc->base.base.id);
7a419866 1894
48da64a8 1895 if (WARN_ON(pll->active == 0)) {
e9d6944e 1896 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1897 return;
1898 }
1899
e9d6944e 1900 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1901 WARN_ON(!pll->on);
cdbd2316 1902 if (--pll->active)
7a419866 1903 return;
ee7b9f93 1904
46edb027 1905 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1906 pll->disable(dev_priv, pll);
ee7b9f93 1907 pll->on = false;
bd2bb1b9
PZ		 1908
1909 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1910}
1911
b8a4f404
PZ		 1912static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1913 enum pipe pipe)
040484af 1914{
23670b32 1915 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1916 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1917 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1918 uint32_t reg, val, pipeconf_val;
040484af
JB		 1919
1920 /* PCH only available on ILK+ */
55522f37 1921 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1922
1923 /* Make sure PCH DPLL is enabled */
e72f9fbf 1924 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1925 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1926
1927 /* FDI must be feeding us bits for PCH ports */
1928 assert_fdi_tx_enabled(dev_priv, pipe);
1929 assert_fdi_rx_enabled(dev_priv, pipe);
1930
23670b32
DV		 1931 if (HAS_PCH_CPT(dev)) {
1932 /* Workaround: Set the timing override bit before enabling the
1933 * pch transcoder. */
1934 reg = TRANS_CHICKEN2(pipe);
1935 val = I915_READ(reg);
1936 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1937 I915_WRITE(reg, val);
59c859d6 1938 }
23670b32 1939
ab9412ba 1940 reg = PCH_TRANSCONF(pipe);
040484af 1941 val = I915_READ(reg);
5f7f726d 1942 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1943
1944 if (HAS_PCH_IBX(dev_priv->dev)) {
1945 /*
1946 * make the BPC in transcoder be consistent with
1947 * that in pipeconf reg.
1948 */
dfd07d72
DV		 1949 val &= ~PIPECONF_BPC_MASK;
1950 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1951 }
5f7f726d
PZ		 1952
1953 val &= ~TRANS_INTERLACE_MASK;
1954 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 1955 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 1956 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 1957 val |= TRANS_LEGACY_INTERLACED_ILK;
1958 else
1959 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1960 else
1961 val |= TRANS_PROGRESSIVE;
1962
040484af
JB		 1963 I915_WRITE(reg, val | TRANS_ENABLE);
1964 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1965 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1966}
1967
8fb033d7 1968static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1969 enum transcoder cpu_transcoder)
040484af 1970{
8fb033d7 1971 u32 val, pipeconf_val;
8fb033d7
PZ		 1972
1973 /* PCH only available on ILK+ */
55522f37 1974 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 1975
8fb033d7 1976 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1977 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1978 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1979
223a6fdf
PZ		 1980 /* Workaround: set timing override bit. */
1981 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1982 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1983 I915_WRITE(_TRANSA_CHICKEN2, val);
1984
25f3ef11 1985 val = TRANS_ENABLE;
937bb610 1986 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1987
9a76b1c6
PZ		 1988 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1989 PIPECONF_INTERLACED_ILK)
a35f2679 1990 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1991 else
1992 val |= TRANS_PROGRESSIVE;
1993
ab9412ba
DV		 1994 I915_WRITE(LPT_TRANSCONF, val);
1995 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1996 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1997}
1998
b8a4f404
PZ		 1999static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2000 enum pipe pipe)
040484af 2001{
23670b32
DV		 2002 struct drm_device *dev = dev_priv->dev;
2003 uint32_t reg, val;
040484af
JB		 2004
2005 /* FDI relies on the transcoder */
2006 assert_fdi_tx_disabled(dev_priv, pipe);
2007 assert_fdi_rx_disabled(dev_priv, pipe);
2008
291906f1
JB		 2009 /* Ports must be off as well */
2010 assert_pch_ports_disabled(dev_priv, pipe);
2011
ab9412ba 2012 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2013 val = I915_READ(reg);
2014 val &= ~TRANS_ENABLE;
2015 I915_WRITE(reg, val);
2016 /* wait for PCH transcoder off, transcoder state */
2017 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2018 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2019
2020 if (!HAS_PCH_IBX(dev)) {
2021 /* Workaround: Clear the timing override chicken bit again. */
2022 reg = TRANS_CHICKEN2(pipe);
2023 val = I915_READ(reg);
2024 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2025 I915_WRITE(reg, val);
2026 }
040484af
JB		 2027}
2028
ab4d966c 2029static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2030{
8fb033d7
PZ		 2031 u32 val;
2032
ab9412ba 2033 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2034 val &= ~TRANS_ENABLE;
ab9412ba 2035 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2036 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2037 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2038 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2039
2040 /* Workaround: clear timing override bit. */
2041 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2042 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 2043 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 2044}
2045
b24e7179 2046/**
309cfea8 2047 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2048 * @crtc: crtc responsible for the pipe
b24e7179 2049 *
0372264a 2050 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2051 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2052 */
e1fdc473 2053static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2054{
0372264a
PZ		 2055 struct drm_device *dev = crtc->base.dev;
2056 struct drm_i915_private *dev_priv = dev->dev_private;
2057 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2058 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2059 pipe);
1a240d4d 2060 enum pipe pch_transcoder;
b24e7179
JB		 2061 int reg;
2062 u32 val;
2063
58c6eaa2 2064 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2065 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2066 assert_sprites_disabled(dev_priv, pipe);
2067
681e5811 2068 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2069 pch_transcoder = TRANSCODER_A;
2070 else
2071 pch_transcoder = pipe;
2072
b24e7179
JB		 2073 /*
2074 * A pipe without a PLL won't actually be able to drive bits from
2075 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2076 * need the check.
2077 */
2078 if (!HAS_PCH_SPLIT(dev_priv->dev))
409ee761 2079 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2080 assert_dsi_pll_enabled(dev_priv);
2081 else
2082 assert_pll_enabled(dev_priv, pipe);
040484af 2083 else {
6e3c9717 2084 if (crtc->config->has_pch_encoder) {
040484af 2085 /* if driving the PCH, we need FDI enabled */
cc391bbb 2086 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2087 assert_fdi_tx_pll_enabled(dev_priv,
2088 (enum pipe) cpu_transcoder);
040484af
JB		 2089 }
2090 /* FIXME: assert CPU port conditions for SNB+ */
2091 }
b24e7179 2092
702e7a56 2093 reg = PIPECONF(cpu_transcoder);
b24e7179 2094 val = I915_READ(reg);
7ad25d48 2095 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2096 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2097 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2098 return;
7ad25d48 2099 }
00d70b15
CW		 2100
2101 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2102 POSTING_READ(reg);
b24e7179
JB		 2103}
2104
2105/**
309cfea8 2106 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2107 * @crtc: crtc whose pipes is to be disabled
b24e7179 2108 *
575f7ab7
VS		 2109 * Disable the pipe of @crtc, making sure that various hardware
2110 * specific requirements are met, if applicable, e.g. plane
2111 * disabled, panel fitter off, etc.
b24e7179
JB		 2112 *
2113 * Will wait until the pipe has shut down before returning.
2114 */
575f7ab7 2115static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2116{
575f7ab7 2117 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2118 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2119 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2120 int reg;
2121 u32 val;
2122
2123 /*
2124 * Make sure planes won't keep trying to pump pixels to us,
2125 * or we might hang the display.
2126 */
2127 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2128 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2129 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2130
702e7a56 2131 reg = PIPECONF(cpu_transcoder);
b24e7179 2132 val = I915_READ(reg);
00d70b15
CW		 2133 if ((val & PIPECONF_ENABLE) == 0)
2134 return;
2135
67adc644
VS		 2136 /*
2137 * Double wide has implications for planes
2138 * so best keep it disabled when not needed.
2139 */
6e3c9717 2140 if (crtc->config->double_wide)
67adc644
VS		 2141 val &= ~PIPECONF_DOUBLE_WIDE;
2142
2143 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2144 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2145 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2146 val &= ~PIPECONF_ENABLE;
2147
2148 I915_WRITE(reg, val);
2149 if ((val & PIPECONF_ENABLE) == 0)
2150 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2151}
2152
d74362c9
KP		 2153/*
2154 * Plane regs are double buffered, going from enabled->disabled needs a
2155 * trigger in order to latch. The display address reg provides this.
2156 */
1dba99f4
VS		 2157void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2158 enum plane plane)
d74362c9 2159{
3d13ef2e
DL		 2160 struct drm_device *dev = dev_priv->dev;
2161 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1dba99f4
VS		 2162
2163 I915_WRITE(reg, I915_READ(reg));
2164 POSTING_READ(reg);
d74362c9
KP		 2165}
2166
b24e7179 2167/**
262ca2b0 2168 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
fdd508a6
VS		 2169 * @plane: plane to be enabled
2170 * @crtc: crtc for the plane
b24e7179 2171 *
fdd508a6 2172 * Enable @plane on @crtc, making sure that the pipe is running first.
b24e7179 2173 */
fdd508a6
VS		 2174static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2175 struct drm_crtc *crtc)
b24e7179 2176{
fdd508a6
VS		 2177 struct drm_device *dev = plane->dev;
2178 struct drm_i915_private *dev_priv = dev->dev_private;
2179 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b24e7179
JB		 2180
2181 /* If the pipe isn't enabled, we can't pump pixels and may hang */
fdd508a6 2182 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
b24e7179 2183
98ec7739
VS		 2184 if (intel_crtc->primary_enabled)
2185 return;
0037f71c 2186
4c445e0e 2187 intel_crtc->primary_enabled = true;
939c2fe8 2188
fdd508a6
VS		 2189 dev_priv->display.update_primary_plane(crtc, plane->fb,
2190 crtc->x, crtc->y);
33c3b0d1
VS		 2191
2192 /*
2193 * BDW signals flip done immediately if the plane
2194 * is disabled, even if the plane enable is already
2195 * armed to occur at the next vblank :(
2196 */
2197 if (IS_BROADWELL(dev))
2198 intel_wait_for_vblank(dev, intel_crtc->pipe);
b24e7179
JB		 2199}
2200
b24e7179 2201/**
262ca2b0 2202 * intel_disable_primary_hw_plane - disable the primary hardware plane
fdd508a6
VS		 2203 * @plane: plane to be disabled
2204 * @crtc: crtc for the plane
b24e7179 2205 *
fdd508a6 2206 * Disable @plane on @crtc, making sure that the pipe is running first.
b24e7179 2207 */
fdd508a6
VS		 2208static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2209 struct drm_crtc *crtc)
b24e7179 2210{
fdd508a6
VS		 2211 struct drm_device *dev = plane->dev;
2212 struct drm_i915_private *dev_priv = dev->dev_private;
2213 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2214
32b7eeec
MR		 2215 if (WARN_ON(!intel_crtc->active))
2216 return;
b24e7179 2217
98ec7739
VS		 2218 if (!intel_crtc->primary_enabled)
2219 return;
0037f71c 2220
4c445e0e 2221 intel_crtc->primary_enabled = false;
939c2fe8 2222
fdd508a6
VS		 2223 dev_priv->display.update_primary_plane(crtc, plane->fb,
2224 crtc->x, crtc->y);
b24e7179
JB		 2225}
2226
693db184
CW		 2227static bool need_vtd_wa(struct drm_device *dev)
2228{
2229#ifdef CONFIG_INTEL_IOMMU
2230 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2231 return true;
2232#endif
2233 return false;
2234}
2235
50470bb0 2236unsigned int
6761dd31
TU		 2237intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2238 uint64_t fb_format_modifier)
a57ce0b2 2239{
6761dd31
TU		 2240 unsigned int tile_height;
2241 uint32_t pixel_bytes;
a57ce0b2 2242
b5d0e9bf
DL		 2243 switch (fb_format_modifier) {
2244 case DRM_FORMAT_MOD_NONE:
2245 tile_height = 1;
2246 break;
2247 case I915_FORMAT_MOD_X_TILED:
2248 tile_height = IS_GEN2(dev) ? 16 : 8;
2249 break;
2250 case I915_FORMAT_MOD_Y_TILED:
2251 tile_height = 32;
2252 break;
2253 case I915_FORMAT_MOD_Yf_TILED:
6761dd31
TU		 2254 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2255 switch (pixel_bytes) {
b5d0e9bf 2256 default:
6761dd31 2257 case 1:
b5d0e9bf
DL		 2258 tile_height = 64;
2259 break;
6761dd31
TU		 2260 case 2:
2261 case 4:
b5d0e9bf
DL		 2262 tile_height = 32;
2263 break;
6761dd31 2264 case 8:
b5d0e9bf
DL		 2265 tile_height = 16;
2266 break;
6761dd31 2267 case 16:
b5d0e9bf
DL		 2268 WARN_ONCE(1,
2269 "128-bit pixels are not supported for display!");
2270 tile_height = 16;
2271 break;
2272 }
2273 break;
2274 default:
2275 MISSING_CASE(fb_format_modifier);
2276 tile_height = 1;
2277 break;
2278 }
091df6cb 2279
6761dd31
TU		 2280 return tile_height;
2281}
2282
2283unsigned int
2284intel_fb_align_height(struct drm_device *dev, unsigned int height,
2285 uint32_t pixel_format, uint64_t fb_format_modifier)
2286{
2287 return ALIGN(height, intel_tile_height(dev, pixel_format,
2288 fb_format_modifier));
a57ce0b2
JB		 2289}
2290
f64b98cd
TU		 2291static int
2292intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2293 const struct drm_plane_state *plane_state)
2294{
50470bb0
TU		 2295 struct intel_rotation_info *info = &view->rotation_info;
2296 static const struct i915_ggtt_view rotated_view =
2297 { .type = I915_GGTT_VIEW_ROTATED };
2298
f64b98cd
TU		 2299 *view = i915_ggtt_view_normal;
2300
50470bb0
TU		 2301 if (!plane_state)
2302 return 0;
2303
2304 if (!(plane_state->rotation &
2305 (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270))))
2306 return 0;
2307
2308 *view = rotated_view;
2309
2310 info->height = fb->height;
2311 info->pixel_format = fb->pixel_format;
2312 info->pitch = fb->pitches[0];
2313 info->fb_modifier = fb->modifier[0];
2314
2315 if (!(info->fb_modifier == I915_FORMAT_MOD_Y_TILED ||
2316 info->fb_modifier == I915_FORMAT_MOD_Yf_TILED)) {
2317 DRM_DEBUG_KMS(
2318 "Y or Yf tiling is needed for 90/270 rotation!\n");
2319 return -EINVAL;
2320 }
2321
f64b98cd
TU		 2322 return 0;
2323}
2324
127bd2ac 2325int
850c4cdc
TU		 2326intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2327 struct drm_framebuffer *fb,
82bc3b2d 2328 const struct drm_plane_state *plane_state,
a4872ba6 2329 struct intel_engine_cs *pipelined)
6b95a207 2330{
850c4cdc 2331 struct drm_device *dev = fb->dev;
ce453d81 2332 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2333 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2334 struct i915_ggtt_view view;
6b95a207
KH		 2335 u32 alignment;
2336 int ret;
2337
ebcdd39e
MR		 2338 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2339
7b911adc
TU		 2340 switch (fb->modifier[0]) {
2341 case DRM_FORMAT_MOD_NONE:
1fada4cc
DL		 2342 if (INTEL_INFO(dev)->gen >= 9)
2343 alignment = 256 * 1024;
2344 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
534843da 2345 alignment = 128 * 1024;
a6c45cf0 2346 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 2347 alignment = 4 * 1024;
2348 else
2349 alignment = 64 * 1024;
6b95a207 2350 break;
7b911adc 2351 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2352 if (INTEL_INFO(dev)->gen >= 9)
2353 alignment = 256 * 1024;
2354 else {
2355 /* pin() will align the object as required by fence */
2356 alignment = 0;
2357 }
6b95a207 2358 break;
7b911adc 2359 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2360 case I915_FORMAT_MOD_Yf_TILED:
2361 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2362 "Y tiling bo slipped through, driver bug!\n"))
2363 return -EINVAL;
2364 alignment = 1 * 1024 * 1024;
2365 break;
6b95a207 2366 default:
7b911adc
TU		 2367 MISSING_CASE(fb->modifier[0]);
2368 return -EINVAL;
6b95a207
KH		 2369 }
2370
f64b98cd
TU		 2371 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2372 if (ret)
2373 return ret;
2374
693db184
CW		 2375 /* Note that the w/a also requires 64 PTE of padding following the
2376 * bo. We currently fill all unused PTE with the shadow page and so
2377 * we should always have valid PTE following the scanout preventing
2378 * the VT-d warning.
2379 */
2380 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2381 alignment = 256 * 1024;
2382
d6dd6843
PZ		 2383 /*
2384 * Global gtt pte registers are special registers which actually forward
2385 * writes to a chunk of system memory. Which means that there is no risk
2386 * that the register values disappear as soon as we call
2387 * intel_runtime_pm_put(), so it is correct to wrap only the
2388 * pin/unpin/fence and not more.
2389 */
2390 intel_runtime_pm_get(dev_priv);
2391
ce453d81 2392 dev_priv->mm.interruptible = false;
e6617330 2393 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
f64b98cd 2394 &view);
48b956c5 2395 if (ret)
ce453d81 2396 goto err_interruptible;
6b95a207
KH		 2397
2398 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2399 * fence, whereas 965+ only requires a fence if using
2400 * framebuffer compression. For simplicity, we always install
2401 * a fence as the cost is not that onerous.
2402 */
06d98131 2403 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2404 if (ret)
2405 goto err_unpin;
1690e1eb 2406
9a5a53b3 2407 i915_gem_object_pin_fence(obj);
6b95a207 2408
ce453d81 2409 dev_priv->mm.interruptible = true;
d6dd6843 2410 intel_runtime_pm_put(dev_priv);
6b95a207 2411 return 0;
48b956c5
CW		 2412
2413err_unpin:
f64b98cd 2414 i915_gem_object_unpin_from_display_plane(obj, &view);
ce453d81
CW		 2415err_interruptible:
2416 dev_priv->mm.interruptible = true;
d6dd6843 2417 intel_runtime_pm_put(dev_priv);
48b956c5 2418 return ret;
6b95a207
KH		 2419}
2420
82bc3b2d
TU		 2421static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2422 const struct drm_plane_state *plane_state)
1690e1eb 2423{
82bc3b2d 2424 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2425 struct i915_ggtt_view view;
2426 int ret;
82bc3b2d 2427
ebcdd39e
MR		 2428 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2429
f64b98cd
TU		 2430 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2431 WARN_ONCE(ret, "Couldn't get view from plane state!");
2432
1690e1eb 2433 i915_gem_object_unpin_fence(obj);
f64b98cd 2434 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2435}
2436
c2c75131
DV		 2437/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2438 * is assumed to be a power-of-two. */
bc752862
CW		 2439unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2440 unsigned int tiling_mode,
2441 unsigned int cpp,
2442 unsigned int pitch)
c2c75131 2443{
bc752862
CW		 2444 if (tiling_mode != I915_TILING_NONE) {
2445 unsigned int tile_rows, tiles;
c2c75131 2446
bc752862
CW		 2447 tile_rows = *y / 8;
2448 *y %= 8;
c2c75131 2449
bc752862
CW		 2450 tiles = *x / (512/cpp);
2451 *x %= 512/cpp;
2452
2453 return tile_rows * pitch * 8 + tiles * 4096;
2454 } else {
2455 unsigned int offset;
2456
2457 offset = *y * pitch + *x * cpp;
2458 *y = 0;
2459 *x = (offset & 4095) / cpp;
2460 return offset & -4096;
2461 }
c2c75131
DV		 2462}
2463
b35d63fa 2464static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2465{
2466 switch (format) {
2467 case DISPPLANE_8BPP:
2468 return DRM_FORMAT_C8;
2469 case DISPPLANE_BGRX555:
2470 return DRM_FORMAT_XRGB1555;
2471 case DISPPLANE_BGRX565:
2472 return DRM_FORMAT_RGB565;
2473 default:
2474 case DISPPLANE_BGRX888:
2475 return DRM_FORMAT_XRGB8888;
2476 case DISPPLANE_RGBX888:
2477 return DRM_FORMAT_XBGR8888;
2478 case DISPPLANE_BGRX101010:
2479 return DRM_FORMAT_XRGB2101010;
2480 case DISPPLANE_RGBX101010:
2481 return DRM_FORMAT_XBGR2101010;
2482 }
2483}
2484
bc8d7dff
DL		 2485static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2486{
2487 switch (format) {
2488 case PLANE_CTL_FORMAT_RGB_565:
2489 return DRM_FORMAT_RGB565;
2490 default:
2491 case PLANE_CTL_FORMAT_XRGB_8888:
2492 if (rgb_order) {
2493 if (alpha)
2494 return DRM_FORMAT_ABGR8888;
2495 else
2496 return DRM_FORMAT_XBGR8888;
2497 } else {
2498 if (alpha)
2499 return DRM_FORMAT_ARGB8888;
2500 else
2501 return DRM_FORMAT_XRGB8888;
2502 }
2503 case PLANE_CTL_FORMAT_XRGB_2101010:
2504 if (rgb_order)
2505 return DRM_FORMAT_XBGR2101010;
2506 else
2507 return DRM_FORMAT_XRGB2101010;
2508 }
2509}
2510
5724dbd1
DL		 2511static bool
2512intel_alloc_plane_obj(struct intel_crtc *crtc,
2513 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2514{
2515 struct drm_device *dev = crtc->base.dev;
2516 struct drm_i915_gem_object *obj = NULL;
2517 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2518 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2519 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2520 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2521 PAGE_SIZE);
2522
2523 size_aligned -= base_aligned;
46f297fb 2524
ff2652ea
CW		 2525 if (plane_config->size == 0)
2526 return false;
2527
f37b5c2b
DV		 2528 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2529 base_aligned,
2530 base_aligned,
2531 size_aligned);
46f297fb 2532 if (!obj)
484b41dd 2533 return false;
46f297fb 2534
49af449b
DL		 2535 obj->tiling_mode = plane_config->tiling;
2536 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2537 obj->stride = fb->pitches[0];
46f297fb 2538
6bf129df
DL		 2539 mode_cmd.pixel_format = fb->pixel_format;
2540 mode_cmd.width = fb->width;
2541 mode_cmd.height = fb->height;
2542 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2543 mode_cmd.modifier[0] = fb->modifier[0];
2544 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2545
2546 mutex_lock(&dev->struct_mutex);
2547
6bf129df 2548 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2549 &mode_cmd, obj)) {
46f297fb
JB		 2550 DRM_DEBUG_KMS("intel fb init failed\n");
2551 goto out_unref_obj;
2552 }
2553
a071fa00 2554 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
46f297fb 2555 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2556
2557 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2558 return true;
46f297fb
JB		 2559
2560out_unref_obj:
2561 drm_gem_object_unreference(&obj->base);
2562 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2563 return false;
2564}
2565
afd65eb4
MR		 2566/* Update plane->state->fb to match plane->fb after driver-internal updates */
2567static void
2568update_state_fb(struct drm_plane *plane)
2569{
2570 if (plane->fb == plane->state->fb)
2571 return;
2572
2573 if (plane->state->fb)
2574 drm_framebuffer_unreference(plane->state->fb);
2575 plane->state->fb = plane->fb;
2576 if (plane->state->fb)
2577 drm_framebuffer_reference(plane->state->fb);
2578}
2579
5724dbd1
DL		 2580static void
2581intel_find_plane_obj(struct intel_crtc *intel_crtc,
2582 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2583{
2584 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2585 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2586 struct drm_crtc *c;
2587 struct intel_crtc *i;
2ff8fde1 2588 struct drm_i915_gem_object *obj;
484b41dd 2589
2d14030b 2590 if (!plane_config->fb)
484b41dd
JB		 2591 return;
2592
f55548b5 2593 if (intel_alloc_plane_obj(intel_crtc, plane_config)) {
fb9981aa
DL		 2594 struct drm_plane *primary = intel_crtc->base.primary;
2595
2596 primary->fb = &plane_config->fb->base;
2597 primary->state->crtc = &intel_crtc->base;
2598 update_state_fb(primary);
2599
484b41dd 2600 return;
f55548b5 2601 }
484b41dd 2602
2d14030b 2603 kfree(plane_config->fb);
484b41dd
JB		 2604
2605 /*
2606 * Failed to alloc the obj, check to see if we should share
2607 * an fb with another CRTC instead
2608 */
70e1e0ec 2609 for_each_crtc(dev, c) {
484b41dd
JB		 2610 i = to_intel_crtc(c);
2611
2612 if (c == &intel_crtc->base)
2613 continue;
2614
2ff8fde1
MR		 2615 if (!i->active)
2616 continue;
2617
2618 obj = intel_fb_obj(c->primary->fb);
2619 if (obj == NULL)
484b41dd
JB		 2620 continue;
2621
2ff8fde1 2622 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
fb9981aa
DL		 2623 struct drm_plane *primary = intel_crtc->base.primary;
2624
d9ceb816
JB		 2625 if (obj->tiling_mode != I915_TILING_NONE)
2626 dev_priv->preserve_bios_swizzle = true;
2627
66e514c1 2628 drm_framebuffer_reference(c->primary->fb);
fb9981aa
DL		 2629 primary->fb = c->primary->fb;
2630 primary->state->crtc = &intel_crtc->base;
5ba76c41 2631 update_state_fb(intel_crtc->base.primary);
2ff8fde1 2632 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
484b41dd
JB		 2633 break;
2634 }
2635 }
46f297fb
JB		 2636}
2637
29b9bde6
DV		 2638static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2639 struct drm_framebuffer *fb,
2640 int x, int y)
81255565
JB		 2641{
2642 struct drm_device *dev = crtc->dev;
2643 struct drm_i915_private *dev_priv = dev->dev_private;
2644 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
c9ba6fad 2645 struct drm_i915_gem_object *obj;
81255565 2646 int plane = intel_crtc->plane;
e506a0c6 2647 unsigned long linear_offset;
81255565 2648 u32 dspcntr;
f45651ba 2649 u32 reg = DSPCNTR(plane);
48404c1e 2650 int pixel_size;
f45651ba 2651
fdd508a6
VS		 2652 if (!intel_crtc->primary_enabled) {
2653 I915_WRITE(reg, 0);
2654 if (INTEL_INFO(dev)->gen >= 4)
2655 I915_WRITE(DSPSURF(plane), 0);
2656 else
2657 I915_WRITE(DSPADDR(plane), 0);
2658 POSTING_READ(reg);
2659 return;
2660 }
2661
c9ba6fad
VS		 2662 obj = intel_fb_obj(fb);
2663 if (WARN_ON(obj == NULL))
2664 return;
2665
2666 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2667
f45651ba
VS		 2668 dspcntr = DISPPLANE_GAMMA_ENABLE;
2669
fdd508a6 2670 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2671
2672 if (INTEL_INFO(dev)->gen < 4) {
2673 if (intel_crtc->pipe == PIPE_B)
2674 dspcntr |= DISPPLANE_SEL_PIPE_B;
2675
2676 /* pipesrc and dspsize control the size that is scaled from,
2677 * which should always be the user's requested size.
2678 */
2679 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2680 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2681 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2682 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2683 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2684 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2685 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2686 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2687 I915_WRITE(PRIMPOS(plane), 0);
2688 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2689 }
81255565 2690
57779d06
VS		 2691 switch (fb->pixel_format) {
2692 case DRM_FORMAT_C8:
81255565
JB		 2693 dspcntr |= DISPPLANE_8BPP;
2694 break;
57779d06
VS		 2695 case DRM_FORMAT_XRGB1555:
2696 case DRM_FORMAT_ARGB1555:
2697 dspcntr |= DISPPLANE_BGRX555;
81255565 2698 break;
57779d06
VS		 2699 case DRM_FORMAT_RGB565:
2700 dspcntr |= DISPPLANE_BGRX565;
2701 break;
2702 case DRM_FORMAT_XRGB8888:
2703 case DRM_FORMAT_ARGB8888:
2704 dspcntr |= DISPPLANE_BGRX888;
2705 break;
2706 case DRM_FORMAT_XBGR8888:
2707 case DRM_FORMAT_ABGR8888:
2708 dspcntr |= DISPPLANE_RGBX888;
2709 break;
2710 case DRM_FORMAT_XRGB2101010:
2711 case DRM_FORMAT_ARGB2101010:
2712 dspcntr |= DISPPLANE_BGRX101010;
2713 break;
2714 case DRM_FORMAT_XBGR2101010:
2715 case DRM_FORMAT_ABGR2101010:
2716 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2717 break;
2718 default:
baba133a 2719 BUG();
81255565 2720 }
57779d06 2721
f45651ba
VS		 2722 if (INTEL_INFO(dev)->gen >= 4 &&
2723 obj->tiling_mode != I915_TILING_NONE)
2724 dspcntr |= DISPPLANE_TILED;
81255565 2725
de1aa629
VS		 2726 if (IS_G4X(dev))
2727 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2728
b9897127 2729 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2730
c2c75131
DV		 2731 if (INTEL_INFO(dev)->gen >= 4) {
2732 intel_crtc->dspaddr_offset =
bc752862 2733 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2734 pixel_size,
bc752862 2735 fb->pitches[0]);
c2c75131
DV		 2736 linear_offset -= intel_crtc->dspaddr_offset;
2737 } else {
e506a0c6 2738 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2739 }
e506a0c6 2740
8e7d688b 2741 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2742 dspcntr |= DISPPLANE_ROTATE_180;
2743
6e3c9717
ACO		 2744 x += (intel_crtc->config->pipe_src_w - 1);
2745 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2746
2747 /* Finding the last pixel of the last line of the display
2748 data and adding to linear_offset*/
2749 linear_offset +=
6e3c9717
ACO		 2750 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2751 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2752 }
2753
2754 I915_WRITE(reg, dspcntr);
2755
01f2c773 2756 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2757 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2758 I915_WRITE(DSPSURF(plane),
2759 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2760 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2761 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2762 } else
f343c5f6 2763 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2764 POSTING_READ(reg);
17638cd6
JB		 2765}
2766
29b9bde6
DV		 2767static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2768 struct drm_framebuffer *fb,
2769 int x, int y)
17638cd6
JB		 2770{
2771 struct drm_device *dev = crtc->dev;
2772 struct drm_i915_private *dev_priv = dev->dev_private;
2773 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
c9ba6fad 2774 struct drm_i915_gem_object *obj;
17638cd6 2775 int plane = intel_crtc->plane;
e506a0c6 2776 unsigned long linear_offset;
17638cd6 2777 u32 dspcntr;
f45651ba 2778 u32 reg = DSPCNTR(plane);
48404c1e 2779 int pixel_size;
f45651ba 2780
fdd508a6
VS		 2781 if (!intel_crtc->primary_enabled) {
2782 I915_WRITE(reg, 0);
2783 I915_WRITE(DSPSURF(plane), 0);
2784 POSTING_READ(reg);
2785 return;
2786 }
2787
c9ba6fad
VS		 2788 obj = intel_fb_obj(fb);
2789 if (WARN_ON(obj == NULL))
2790 return;
2791
2792 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2793
f45651ba
VS		 2794 dspcntr = DISPPLANE_GAMMA_ENABLE;
2795
fdd508a6 2796 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2797
2798 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2799 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2800
57779d06
VS		 2801 switch (fb->pixel_format) {
2802 case DRM_FORMAT_C8:
17638cd6
JB		 2803 dspcntr |= DISPPLANE_8BPP;
2804 break;
57779d06
VS		 2805 case DRM_FORMAT_RGB565:
2806 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2807 break;
57779d06
VS		 2808 case DRM_FORMAT_XRGB8888:
2809 case DRM_FORMAT_ARGB8888:
2810 dspcntr |= DISPPLANE_BGRX888;
2811 break;
2812 case DRM_FORMAT_XBGR8888:
2813 case DRM_FORMAT_ABGR8888:
2814 dspcntr |= DISPPLANE_RGBX888;
2815 break;
2816 case DRM_FORMAT_XRGB2101010:
2817 case DRM_FORMAT_ARGB2101010:
2818 dspcntr |= DISPPLANE_BGRX101010;
2819 break;
2820 case DRM_FORMAT_XBGR2101010:
2821 case DRM_FORMAT_ABGR2101010:
2822 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2823 break;
2824 default:
baba133a 2825 BUG();
17638cd6
JB		 2826 }
2827
2828 if (obj->tiling_mode != I915_TILING_NONE)
2829 dspcntr |= DISPPLANE_TILED;
17638cd6 2830
f45651ba 2831 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2832 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2833
b9897127 2834 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2835 intel_crtc->dspaddr_offset =
bc752862 2836 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2837 pixel_size,
bc752862 2838 fb->pitches[0]);
c2c75131 2839 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2840 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2841 dspcntr |= DISPPLANE_ROTATE_180;
2842
2843 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2844 x += (intel_crtc->config->pipe_src_w - 1);
2845 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2846
2847 /* Finding the last pixel of the last line of the display
2848 data and adding to linear_offset*/
2849 linear_offset +=
6e3c9717
ACO		 2850 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2851 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2852 }
2853 }
2854
2855 I915_WRITE(reg, dspcntr);
17638cd6 2856
01f2c773 2857 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2858 I915_WRITE(DSPSURF(plane),
2859 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2860 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2861 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2862 } else {
2863 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2864 I915_WRITE(DSPLINOFF(plane), linear_offset);
2865 }
17638cd6 2866 POSTING_READ(reg);
17638cd6
JB		 2867}
2868
b321803d
DL		 2869u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2870 uint32_t pixel_format)
2871{
2872 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2873
2874 /*
2875 * The stride is either expressed as a multiple of 64 bytes
2876 * chunks for linear buffers or in number of tiles for tiled
2877 * buffers.
2878 */
2879 switch (fb_modifier) {
2880 case DRM_FORMAT_MOD_NONE:
2881 return 64;
2882 case I915_FORMAT_MOD_X_TILED:
2883 if (INTEL_INFO(dev)->gen == 2)
2884 return 128;
2885 return 512;
2886 case I915_FORMAT_MOD_Y_TILED:
2887 /* No need to check for old gens and Y tiling since this is
2888 * about the display engine and those will be blocked before
2889 * we get here.
2890 */
2891 return 128;
2892 case I915_FORMAT_MOD_Yf_TILED:
2893 if (bits_per_pixel == 8)
2894 return 64;
2895 else
2896 return 128;
2897 default:
2898 MISSING_CASE(fb_modifier);
2899 return 64;
2900 }
2901}
2902
70d21f0e
DL		 2903static void skylake_update_primary_plane(struct drm_crtc *crtc,
2904 struct drm_framebuffer *fb,
2905 int x, int y)
2906{
2907 struct drm_device *dev = crtc->dev;
2908 struct drm_i915_private *dev_priv = dev->dev_private;
2909 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
70d21f0e
DL		 2910 struct drm_i915_gem_object *obj;
2911 int pipe = intel_crtc->pipe;
b321803d 2912 u32 plane_ctl, stride_div;
70d21f0e
DL		 2913
2914 if (!intel_crtc->primary_enabled) {
2915 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2916 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2917 POSTING_READ(PLANE_CTL(pipe, 0));
2918 return;
2919 }
2920
2921 plane_ctl = PLANE_CTL_ENABLE |
2922 PLANE_CTL_PIPE_GAMMA_ENABLE |
2923 PLANE_CTL_PIPE_CSC_ENABLE;
2924
2925 switch (fb->pixel_format) {
2926 case DRM_FORMAT_RGB565:
2927 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2928 break;
2929 case DRM_FORMAT_XRGB8888:
2930 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2931 break;
f75fb42a
JN		 2932 case DRM_FORMAT_ARGB8888:
2933 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2934 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2935 break;
70d21f0e
DL		 2936 case DRM_FORMAT_XBGR8888:
2937 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2938 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2939 break;
f75fb42a
JN		 2940 case DRM_FORMAT_ABGR8888:
2941 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2942 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2943 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2944 break;
70d21f0e
DL		 2945 case DRM_FORMAT_XRGB2101010:
2946 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2947 break;
2948 case DRM_FORMAT_XBGR2101010:
2949 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2950 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2951 break;
2952 default:
2953 BUG();
2954 }
2955
30af77c4
DV		 2956 switch (fb->modifier[0]) {
2957 case DRM_FORMAT_MOD_NONE:
70d21f0e 2958 break;
30af77c4 2959 case I915_FORMAT_MOD_X_TILED:
70d21f0e 2960 plane_ctl |= PLANE_CTL_TILED_X;
b321803d
DL		 2961 break;
2962 case I915_FORMAT_MOD_Y_TILED:
2963 plane_ctl |= PLANE_CTL_TILED_Y;
2964 break;
2965 case I915_FORMAT_MOD_Yf_TILED:
2966 plane_ctl |= PLANE_CTL_TILED_YF;
70d21f0e
DL		 2967 break;
2968 default:
b321803d 2969 MISSING_CASE(fb->modifier[0]);
70d21f0e
DL		 2970 }
2971
2972 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
8e7d688b 2973 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180))
1447dde0 2974 plane_ctl |= PLANE_CTL_ROTATE_180;
70d21f0e 2975
b321803d
DL		 2976 obj = intel_fb_obj(fb);
2977 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
2978 fb->pixel_format);
2979
70d21f0e
DL		 2980 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2981
70d21f0e
DL		 2982 I915_WRITE(PLANE_POS(pipe, 0), 0);
2983 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2984 I915_WRITE(PLANE_SIZE(pipe, 0),
6e3c9717
ACO		 2985 (intel_crtc->config->pipe_src_h - 1) << 16 |
2986 (intel_crtc->config->pipe_src_w - 1));
b321803d 2987 I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
70d21f0e
DL		 2988 I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2989
2990 POSTING_READ(PLANE_SURF(pipe, 0));
2991}
2992
17638cd6
JB		 2993/* Assume fb object is pinned & idle & fenced and just update base pointers */
2994static int
2995intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2996 int x, int y, enum mode_set_atomic state)
2997{
2998 struct drm_device *dev = crtc->dev;
2999 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3000
6b8e6ed0
CW		 3001 if (dev_priv->display.disable_fbc)
3002 dev_priv->display.disable_fbc(dev);
81255565 3003
29b9bde6
DV		 3004 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3005
3006 return 0;
81255565
JB		 3007}
3008
7514747d 3009static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3010{
96a02917
VS		 3011 struct drm_crtc *crtc;
3012
70e1e0ec 3013 for_each_crtc(dev, crtc) {
96a02917
VS		 3014 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3015 enum plane plane = intel_crtc->plane;
3016
3017 intel_prepare_page_flip(dev, plane);
3018 intel_finish_page_flip_plane(dev, plane);
3019 }
7514747d
VS		 3020}
3021
3022static void intel_update_primary_planes(struct drm_device *dev)
3023{
3024 struct drm_i915_private *dev_priv = dev->dev_private;
3025 struct drm_crtc *crtc;
96a02917 3026
70e1e0ec 3027 for_each_crtc(dev, crtc) {
96a02917
VS		 3028 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3029
51fd371b 3030 drm_modeset_lock(&crtc->mutex, NULL);
947fdaad
CW		 3031 /*
3032 * FIXME: Once we have proper support for primary planes (and
3033 * disabling them without disabling the entire crtc) allow again
66e514c1 3034 * a NULL crtc->primary->fb.
947fdaad 3035 */
f4510a27 3036 if (intel_crtc->active && crtc->primary->fb)
262ca2b0 3037 dev_priv->display.update_primary_plane(crtc,
66e514c1 3038 crtc->primary->fb,
262ca2b0
MR		 3039 crtc->x,
3040 crtc->y);
51fd371b 3041 drm_modeset_unlock(&crtc->mutex);
96a02917
VS		 3042 }
3043}
3044
7514747d
VS		 3045void intel_prepare_reset(struct drm_device *dev)
3046{
f98ce92f
VS		 3047 struct drm_i915_private *dev_priv = to_i915(dev);
3048 struct intel_crtc *crtc;
3049
7514747d
VS		 3050 /* no reset support for gen2 */
3051 if (IS_GEN2(dev))
3052 return;
3053
3054 /* reset doesn't touch the display */
3055 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3056 return;
3057
3058 drm_modeset_lock_all(dev);
f98ce92f
VS		 3059
3060 /*
3061 * Disabling the crtcs gracefully seems nicer. Also the
3062 * g33 docs say we should at least disable all the planes.
3063 */
3064 for_each_intel_crtc(dev, crtc) {
3065 if (crtc->active)
3066 dev_priv->display.crtc_disable(&crtc->base);
3067 }
7514747d
VS		 3068}
3069
3070void intel_finish_reset(struct drm_device *dev)
3071{
3072 struct drm_i915_private *dev_priv = to_i915(dev);
3073
3074 /*
3075 * Flips in the rings will be nuked by the reset,
3076 * so complete all pending flips so that user space
3077 * will get its events and not get stuck.
3078 */
3079 intel_complete_page_flips(dev);
3080
3081 /* no reset support for gen2 */
3082 if (IS_GEN2(dev))
3083 return;
3084
3085 /* reset doesn't touch the display */
3086 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3087 /*
3088 * Flips in the rings have been nuked by the reset,
3089 * so update the base address of all primary
3090 * planes to the the last fb to make sure we're
3091 * showing the correct fb after a reset.
3092 */
3093 intel_update_primary_planes(dev);
3094 return;
3095 }
3096
3097 /*
3098 * The display has been reset as well,
3099 * so need a full re-initialization.
3100 */
3101 intel_runtime_pm_disable_interrupts(dev_priv);
3102 intel_runtime_pm_enable_interrupts(dev_priv);
3103
3104 intel_modeset_init_hw(dev);
3105
3106 spin_lock_irq(&dev_priv->irq_lock);
3107 if (dev_priv->display.hpd_irq_setup)
3108 dev_priv->display.hpd_irq_setup(dev);
3109 spin_unlock_irq(&dev_priv->irq_lock);
3110
3111 intel_modeset_setup_hw_state(dev, true);
3112
3113 intel_hpd_init(dev_priv);
3114
3115 drm_modeset_unlock_all(dev);
3116}
3117
14667a4b
CW		 3118static int
3119intel_finish_fb(struct drm_framebuffer *old_fb)
3120{
2ff8fde1 3121 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
14667a4b
CW		 3122 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3123 bool was_interruptible = dev_priv->mm.interruptible;
3124 int ret;
3125
14667a4b
CW		 3126 /* Big Hammer, we also need to ensure that any pending
3127 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3128 * current scanout is retired before unpinning the old
3129 * framebuffer.
3130 *
3131 * This should only fail upon a hung GPU, in which case we
3132 * can safely continue.
3133 */
3134 dev_priv->mm.interruptible = false;
3135 ret = i915_gem_object_finish_gpu(obj);
3136 dev_priv->mm.interruptible = was_interruptible;
3137
3138 return ret;
3139}
3140
7d5e3799
CW		 3141static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3142{
3143 struct drm_device *dev = crtc->dev;
3144 struct drm_i915_private *dev_priv = dev->dev_private;
3145 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3146 bool pending;
3147
3148 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3149 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3150 return false;
3151
5e2d7afc 3152 spin_lock_irq(&dev->event_lock);
7d5e3799 3153 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3154 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3155
3156 return pending;
3157}
3158
e30e8f75
GP		 3159static void intel_update_pipe_size(struct intel_crtc *crtc)
3160{
3161 struct drm_device *dev = crtc->base.dev;
3162 struct drm_i915_private *dev_priv = dev->dev_private;
3163 const struct drm_display_mode *adjusted_mode;
3164
3165 if (!i915.fastboot)
3166 return;
3167
3168 /*
3169 * Update pipe size and adjust fitter if needed: the reason for this is
3170 * that in compute_mode_changes we check the native mode (not the pfit
3171 * mode) to see if we can flip rather than do a full mode set. In the
3172 * fastboot case, we'll flip, but if we don't update the pipesrc and
3173 * pfit state, we'll end up with a big fb scanned out into the wrong
3174 * sized surface.
3175 *
3176 * To fix this properly, we need to hoist the checks up into
3177 * compute_mode_changes (or above), check the actual pfit state and
3178 * whether the platform allows pfit disable with pipe active, and only
3179 * then update the pipesrc and pfit state, even on the flip path.
3180 */
3181
6e3c9717 3182 adjusted_mode = &crtc->config->base.adjusted_mode;
e30e8f75
GP		 3183
3184 I915_WRITE(PIPESRC(crtc->pipe),
3185 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3186 (adjusted_mode->crtc_vdisplay - 1));
6e3c9717 3187 if (!crtc->config->pch_pfit.enabled &&
409ee761
ACO		 3188 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3189 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
e30e8f75
GP		 3190 I915_WRITE(PF_CTL(crtc->pipe), 0);
3191 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3192 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3193 }
6e3c9717
ACO		 3194 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3195 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
e30e8f75
GP		 3196}
3197
5e84e1a4
ZW		 3198static void intel_fdi_normal_train(struct drm_crtc *crtc)
3199{
3200 struct drm_device *dev = crtc->dev;
3201 struct drm_i915_private *dev_priv = dev->dev_private;
3202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3203 int pipe = intel_crtc->pipe;
3204 u32 reg, temp;
3205
3206 /* enable normal train */
3207 reg = FDI_TX_CTL(pipe);
3208 temp = I915_READ(reg);
61e499bf 3209 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3210 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3211 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3212 } else {
3213 temp &= ~FDI_LINK_TRAIN_NONE;
3214 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3215 }
5e84e1a4
ZW		 3216 I915_WRITE(reg, temp);
3217
3218 reg = FDI_RX_CTL(pipe);
3219 temp = I915_READ(reg);
3220 if (HAS_PCH_CPT(dev)) {
3221 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3222 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3223 } else {
3224 temp &= ~FDI_LINK_TRAIN_NONE;
3225 temp |= FDI_LINK_TRAIN_NONE;
3226 }
3227 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3228
3229 /* wait one idle pattern time */
3230 POSTING_READ(reg);
3231 udelay(1000);
357555c0
JB		 3232
3233 /* IVB wants error correction enabled */
3234 if (IS_IVYBRIDGE(dev))
3235 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3236 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3237}
3238
8db9d77b
ZW		 3239/* The FDI link training functions for ILK/Ibexpeak. */
3240static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3241{
3242 struct drm_device *dev = crtc->dev;
3243 struct drm_i915_private *dev_priv = dev->dev_private;
3244 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3245 int pipe = intel_crtc->pipe;
5eddb70b 3246 u32 reg, temp, tries;
8db9d77b 3247
1c8562f6 3248 /* FDI needs bits from pipe first */
0fc932b8 3249 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3250
e1a44743
AJ		 3251 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3252 for train result */
5eddb70b
CW		 3253 reg = FDI_RX_IMR(pipe);
3254 temp = I915_READ(reg);
e1a44743
AJ		 3255 temp &= ~FDI_RX_SYMBOL_LOCK;
3256 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3257 I915_WRITE(reg, temp);
3258 I915_READ(reg);
e1a44743
AJ		 3259 udelay(150);
3260
8db9d77b 3261 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3262 reg = FDI_TX_CTL(pipe);
3263 temp = I915_READ(reg);
627eb5a3 3264 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3265 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3266 temp &= ~FDI_LINK_TRAIN_NONE;
3267 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3268 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3269
5eddb70b
CW		 3270 reg = FDI_RX_CTL(pipe);
3271 temp = I915_READ(reg);
8db9d77b
ZW		 3272 temp &= ~FDI_LINK_TRAIN_NONE;
3273 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3274 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3275
3276 POSTING_READ(reg);
8db9d77b
ZW		 3277 udelay(150);
3278
5b2adf89 3279 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3280 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3281 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3282 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3283
5eddb70b 3284 reg = FDI_RX_IIR(pipe);
e1a44743 3285 for (tries = 0; tries < 5; tries++) {
5eddb70b 3286 temp = I915_READ(reg);
8db9d77b
ZW		 3287 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3288
3289 if ((temp & FDI_RX_BIT_LOCK)) {
3290 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3291 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3292 break;
3293 }
8db9d77b 3294 }
e1a44743 3295 if (tries == 5)
5eddb70b 3296 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3297
3298 /* Train 2 */
5eddb70b
CW		 3299 reg = FDI_TX_CTL(pipe);
3300 temp = I915_READ(reg);
8db9d77b
ZW		 3301 temp &= ~FDI_LINK_TRAIN_NONE;
3302 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3303 I915_WRITE(reg, temp);
8db9d77b 3304
5eddb70b
CW		 3305 reg = FDI_RX_CTL(pipe);
3306 temp = I915_READ(reg);
8db9d77b
ZW		 3307 temp &= ~FDI_LINK_TRAIN_NONE;
3308 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3309 I915_WRITE(reg, temp);
8db9d77b 3310
5eddb70b
CW		 3311 POSTING_READ(reg);
3312 udelay(150);
8db9d77b 3313
5eddb70b 3314 reg = FDI_RX_IIR(pipe);
e1a44743 3315 for (tries = 0; tries < 5; tries++) {
5eddb70b 3316 temp = I915_READ(reg);
8db9d77b
ZW		 3317 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3318
3319 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3320 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3321 DRM_DEBUG_KMS("FDI train 2 done.\n");
3322 break;
3323 }
8db9d77b 3324 }
e1a44743 3325 if (tries == 5)
5eddb70b 3326 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3327
3328 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3329
8db9d77b
ZW		 3330}
3331
0206e353 3332static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3333 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3334 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3335 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3336 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3337};
3338
3339/* The FDI link training functions for SNB/Cougarpoint. */
3340static void gen6_fdi_link_train(struct drm_crtc *crtc)
3341{
3342 struct drm_device *dev = crtc->dev;
3343 struct drm_i915_private *dev_priv = dev->dev_private;
3344 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3345 int pipe = intel_crtc->pipe;
fa37d39e 3346 u32 reg, temp, i, retry;
8db9d77b 3347
e1a44743
AJ		 3348 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3349 for train result */
5eddb70b
CW		 3350 reg = FDI_RX_IMR(pipe);
3351 temp = I915_READ(reg);
e1a44743
AJ		 3352 temp &= ~FDI_RX_SYMBOL_LOCK;
3353 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3354 I915_WRITE(reg, temp);
3355
3356 POSTING_READ(reg);
e1a44743
AJ		 3357 udelay(150);
3358
8db9d77b 3359 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3360 reg = FDI_TX_CTL(pipe);
3361 temp = I915_READ(reg);
627eb5a3 3362 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3363 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3364 temp &= ~FDI_LINK_TRAIN_NONE;
3365 temp |= FDI_LINK_TRAIN_PATTERN_1;
3366 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3367 /* SNB-B */
3368 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3369 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3370
d74cf324
DV		 3371 I915_WRITE(FDI_RX_MISC(pipe),
3372 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3373
5eddb70b
CW		 3374 reg = FDI_RX_CTL(pipe);
3375 temp = I915_READ(reg);
8db9d77b
ZW		 3376 if (HAS_PCH_CPT(dev)) {
3377 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3378 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3379 } else {
3380 temp &= ~FDI_LINK_TRAIN_NONE;
3381 temp |= FDI_LINK_TRAIN_PATTERN_1;
3382 }
5eddb70b
CW		 3383 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3384
3385 POSTING_READ(reg);
8db9d77b
ZW		 3386 udelay(150);
3387
0206e353 3388 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3389 reg = FDI_TX_CTL(pipe);
3390 temp = I915_READ(reg);
8db9d77b
ZW		 3391 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3392 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3393 I915_WRITE(reg, temp);
3394
3395 POSTING_READ(reg);
8db9d77b
ZW		 3396 udelay(500);
3397
fa37d39e
SP		 3398 for (retry = 0; retry < 5; retry++) {
3399 reg = FDI_RX_IIR(pipe);
3400 temp = I915_READ(reg);
3401 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3402 if (temp & FDI_RX_BIT_LOCK) {
3403 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3404 DRM_DEBUG_KMS("FDI train 1 done.\n");
3405 break;
3406 }
3407 udelay(50);
8db9d77b 3408 }
fa37d39e
SP		 3409 if (retry < 5)
3410 break;
8db9d77b
ZW		 3411 }
3412 if (i == 4)
5eddb70b 3413 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3414
3415 /* Train 2 */
5eddb70b
CW		 3416 reg = FDI_TX_CTL(pipe);
3417 temp = I915_READ(reg);
8db9d77b
ZW		 3418 temp &= ~FDI_LINK_TRAIN_NONE;
3419 temp |= FDI_LINK_TRAIN_PATTERN_2;
3420 if (IS_GEN6(dev)) {
3421 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3422 /* SNB-B */
3423 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3424 }
5eddb70b 3425 I915_WRITE(reg, temp);
8db9d77b 3426
5eddb70b
CW		 3427 reg = FDI_RX_CTL(pipe);
3428 temp = I915_READ(reg);
8db9d77b
ZW		 3429 if (HAS_PCH_CPT(dev)) {
3430 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3431 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3432 } else {
3433 temp &= ~FDI_LINK_TRAIN_NONE;
3434 temp |= FDI_LINK_TRAIN_PATTERN_2;
3435 }
5eddb70b
CW		 3436 I915_WRITE(reg, temp);
3437
3438 POSTING_READ(reg);
8db9d77b
ZW		 3439 udelay(150);
3440
0206e353 3441 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3442 reg = FDI_TX_CTL(pipe);
3443 temp = I915_READ(reg);
8db9d77b
ZW		 3444 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3445 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3446 I915_WRITE(reg, temp);
3447
3448 POSTING_READ(reg);
8db9d77b
ZW		 3449 udelay(500);
3450
fa37d39e
SP		 3451 for (retry = 0; retry < 5; retry++) {
3452 reg = FDI_RX_IIR(pipe);
3453 temp = I915_READ(reg);
3454 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3455 if (temp & FDI_RX_SYMBOL_LOCK) {
3456 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3457 DRM_DEBUG_KMS("FDI train 2 done.\n");
3458 break;
3459 }
3460 udelay(50);
8db9d77b 3461 }
fa37d39e
SP		 3462 if (retry < 5)
3463 break;
8db9d77b
ZW		 3464 }
3465 if (i == 4)
5eddb70b 3466 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3467
3468 DRM_DEBUG_KMS("FDI train done.\n");
3469}
3470
357555c0
JB		 3471/* Manual link training for Ivy Bridge A0 parts */
3472static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3473{
3474 struct drm_device *dev = crtc->dev;
3475 struct drm_i915_private *dev_priv = dev->dev_private;
3476 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3477 int pipe = intel_crtc->pipe;
139ccd3f 3478 u32 reg, temp, i, j;
357555c0
JB		 3479
3480 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3481 for train result */
3482 reg = FDI_RX_IMR(pipe);
3483 temp = I915_READ(reg);
3484 temp &= ~FDI_RX_SYMBOL_LOCK;
3485 temp &= ~FDI_RX_BIT_LOCK;
3486 I915_WRITE(reg, temp);
3487
3488 POSTING_READ(reg);
3489 udelay(150);
3490
01a415fd
DV		 3491 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3492 I915_READ(FDI_RX_IIR(pipe)));
3493
139ccd3f
JB		 3494 /* Try each vswing and preemphasis setting twice before moving on */
3495 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3496 /* disable first in case we need to retry */
3497 reg = FDI_TX_CTL(pipe);
3498 temp = I915_READ(reg);
3499 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3500 temp &= ~FDI_TX_ENABLE;
3501 I915_WRITE(reg, temp);
357555c0 3502
139ccd3f
JB		 3503 reg = FDI_RX_CTL(pipe);
3504 temp = I915_READ(reg);
3505 temp &= ~FDI_LINK_TRAIN_AUTO;
3506 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3507 temp &= ~FDI_RX_ENABLE;
3508 I915_WRITE(reg, temp);
357555c0 3509
139ccd3f 3510 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3511 reg = FDI_TX_CTL(pipe);
3512 temp = I915_READ(reg);
139ccd3f 3513 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3514 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3515 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3516 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3517 temp |= snb_b_fdi_train_param[j/2];
3518 temp |= FDI_COMPOSITE_SYNC;
3519 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3520
139ccd3f
JB		 3521 I915_WRITE(FDI_RX_MISC(pipe),
3522 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3523
139ccd3f 3524 reg = FDI_RX_CTL(pipe);
357555c0 3525 temp = I915_READ(reg);
139ccd3f
JB		 3526 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3527 temp |= FDI_COMPOSITE_SYNC;
3528 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3529
139ccd3f
JB		 3530 POSTING_READ(reg);
3531 udelay(1); /* should be 0.5us */
357555c0 3532
139ccd3f
JB		 3533 for (i = 0; i < 4; i++) {
3534 reg = FDI_RX_IIR(pipe);
3535 temp = I915_READ(reg);
3536 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3537
139ccd3f
JB		 3538 if (temp & FDI_RX_BIT_LOCK ||
3539 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3540 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3541 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3542 i);
3543 break;
3544 }
3545 udelay(1); /* should be 0.5us */
3546 }
3547 if (i == 4) {
3548 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3549 continue;
3550 }
357555c0 3551
139ccd3f 3552 /* Train 2 */
357555c0
JB		 3553 reg = FDI_TX_CTL(pipe);
3554 temp = I915_READ(reg);
139ccd3f
JB		 3555 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3556 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3557 I915_WRITE(reg, temp);
3558
3559 reg = FDI_RX_CTL(pipe);
3560 temp = I915_READ(reg);
3561 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3562 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3563 I915_WRITE(reg, temp);
3564
3565 POSTING_READ(reg);
139ccd3f 3566 udelay(2); /* should be 1.5us */
357555c0 3567
139ccd3f
JB		 3568 for (i = 0; i < 4; i++) {
3569 reg = FDI_RX_IIR(pipe);
3570 temp = I915_READ(reg);
3571 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3572
139ccd3f
JB		 3573 if (temp & FDI_RX_SYMBOL_LOCK ||
3574 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3575 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3576 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3577 i);
3578 goto train_done;
3579 }
3580 udelay(2); /* should be 1.5us */
357555c0 3581 }
139ccd3f
JB		 3582 if (i == 4)
3583 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3584 }
357555c0 3585
139ccd3f 3586train_done:
357555c0
JB		 3587 DRM_DEBUG_KMS("FDI train done.\n");
3588}
3589
88cefb6c 3590static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3591{
88cefb6c 3592 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3593 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3594 int pipe = intel_crtc->pipe;
5eddb70b 3595 u32 reg, temp;
79e53945 3596
c64e311e 3597
c98e9dcf 3598 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3599 reg = FDI_RX_CTL(pipe);
3600 temp = I915_READ(reg);
627eb5a3 3601 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3602 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3603 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3604 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3605
3606 POSTING_READ(reg);
c98e9dcf
JB		 3607 udelay(200);
3608
3609 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3610 temp = I915_READ(reg);
3611 I915_WRITE(reg, temp | FDI_PCDCLK);
3612
3613 POSTING_READ(reg);
c98e9dcf
JB		 3614 udelay(200);
3615
20749730
PZ		 3616 /* Enable CPU FDI TX PLL, always on for Ironlake */
3617 reg = FDI_TX_CTL(pipe);
3618 temp = I915_READ(reg);
3619 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3620 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3621
20749730
PZ		 3622 POSTING_READ(reg);
3623 udelay(100);
6be4a607 3624 }
0e23b99d
JB		 3625}
3626
88cefb6c
DV		 3627static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3628{
3629 struct drm_device *dev = intel_crtc->base.dev;
3630 struct drm_i915_private *dev_priv = dev->dev_private;
3631 int pipe = intel_crtc->pipe;
3632 u32 reg, temp;
3633
3634 /* Switch from PCDclk to Rawclk */
3635 reg = FDI_RX_CTL(pipe);
3636 temp = I915_READ(reg);
3637 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3638
3639 /* Disable CPU FDI TX PLL */
3640 reg = FDI_TX_CTL(pipe);
3641 temp = I915_READ(reg);
3642 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3643
3644 POSTING_READ(reg);
3645 udelay(100);
3646
3647 reg = FDI_RX_CTL(pipe);
3648 temp = I915_READ(reg);
3649 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3650
3651 /* Wait for the clocks to turn off. */
3652 POSTING_READ(reg);
3653 udelay(100);
3654}
3655
0fc932b8
JB		 3656static void ironlake_fdi_disable(struct drm_crtc *crtc)
3657{
3658 struct drm_device *dev = crtc->dev;
3659 struct drm_i915_private *dev_priv = dev->dev_private;
3660 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3661 int pipe = intel_crtc->pipe;
3662 u32 reg, temp;
3663
3664 /* disable CPU FDI tx and PCH FDI rx */
3665 reg = FDI_TX_CTL(pipe);
3666 temp = I915_READ(reg);
3667 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3668 POSTING_READ(reg);
3669
3670 reg = FDI_RX_CTL(pipe);
3671 temp = I915_READ(reg);
3672 temp &= ~(0x7 << 16);
dfd07d72 3673 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3674 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3675
3676 POSTING_READ(reg);
3677 udelay(100);
3678
3679 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3680 if (HAS_PCH_IBX(dev))
6f06ce18 3681 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3682
3683 /* still set train pattern 1 */
3684 reg = FDI_TX_CTL(pipe);
3685 temp = I915_READ(reg);
3686 temp &= ~FDI_LINK_TRAIN_NONE;
3687 temp |= FDI_LINK_TRAIN_PATTERN_1;
3688 I915_WRITE(reg, temp);
3689
3690 reg = FDI_RX_CTL(pipe);
3691 temp = I915_READ(reg);
3692 if (HAS_PCH_CPT(dev)) {
3693 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3694 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3695 } else {
3696 temp &= ~FDI_LINK_TRAIN_NONE;
3697 temp |= FDI_LINK_TRAIN_PATTERN_1;
3698 }
3699 /* BPC in FDI rx is consistent with that in PIPECONF */
3700 temp &= ~(0x07 << 16);
dfd07d72 3701 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3702 I915_WRITE(reg, temp);
3703
3704 POSTING_READ(reg);
3705 udelay(100);
3706}
3707
5dce5b93
CW		 3708bool intel_has_pending_fb_unpin(struct drm_device *dev)
3709{
3710 struct intel_crtc *crtc;
3711
3712 /* Note that we don't need to be called with mode_config.lock here
3713 * as our list of CRTC objects is static for the lifetime of the
3714 * device and so cannot disappear as we iterate. Similarly, we can
3715 * happily treat the predicates as racy, atomic checks as userspace
3716 * cannot claim and pin a new fb without at least acquring the
3717 * struct_mutex and so serialising with us.
3718 */
d3fcc808 3719 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3720 if (atomic_read(&crtc->unpin_work_count) == 0)
3721 continue;
3722
3723 if (crtc->unpin_work)
3724 intel_wait_for_vblank(dev, crtc->pipe);
3725
3726 return true;
3727 }
3728
3729 return false;
3730}
3731
d6bbafa1
CW		 3732static void page_flip_completed(struct intel_crtc *intel_crtc)
3733{
3734 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3735 struct intel_unpin_work *work = intel_crtc->unpin_work;
3736
3737 /* ensure that the unpin work is consistent wrt ->pending. */
3738 smp_rmb();
3739 intel_crtc->unpin_work = NULL;
3740
3741 if (work->event)
3742 drm_send_vblank_event(intel_crtc->base.dev,
3743 intel_crtc->pipe,
3744 work->event);
3745
3746 drm_crtc_vblank_put(&intel_crtc->base);
3747
3748 wake_up_all(&dev_priv->pending_flip_queue);
3749 queue_work(dev_priv->wq, &work->work);
3750
3751 trace_i915_flip_complete(intel_crtc->plane,
3752 work->pending_flip_obj);
3753}
3754
46a55d30 3755void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3756{
0f91128d 3757 struct drm_device *dev = crtc->dev;
5bb61643 3758 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3759
2c10d571 3760 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW		 3761 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3762 !intel_crtc_has_pending_flip(crtc),
3763 60*HZ) == 0)) {
3764 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3765
5e2d7afc 3766 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3767 if (intel_crtc->unpin_work) {
3768 WARN_ONCE(1, "Removing stuck page flip\n");
3769 page_flip_completed(intel_crtc);
3770 }
5e2d7afc 3771 spin_unlock_irq(&dev->event_lock);
9c787942 3772 }
5bb61643 3773
975d568a
CW		 3774 if (crtc->primary->fb) {
3775 mutex_lock(&dev->struct_mutex);
3776 intel_finish_fb(crtc->primary->fb);
3777 mutex_unlock(&dev->struct_mutex);
3778 }
e6c3a2a6
CW		 3779}
3780
e615efe4
ED		 3781/* Program iCLKIP clock to the desired frequency */
3782static void lpt_program_iclkip(struct drm_crtc *crtc)
3783{
3784 struct drm_device *dev = crtc->dev;
3785 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3786 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3787 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3788 u32 temp;
3789
09153000
DV		 3790 mutex_lock(&dev_priv->dpio_lock);
3791
e615efe4
ED		 3792 /* It is necessary to ungate the pixclk gate prior to programming
3793 * the divisors, and gate it back when it is done.
3794 */
3795 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3796
3797 /* Disable SSCCTL */
3798 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3799 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3800 SBI_SSCCTL_DISABLE,
3801 SBI_ICLK);
e615efe4
ED		 3802
3803 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3804 if (clock == 20000) {
e615efe4
ED		 3805 auxdiv = 1;
3806 divsel = 0x41;
3807 phaseinc = 0x20;
3808 } else {
3809 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3810 * but the adjusted_mode->crtc_clock in in KHz. To get the
3811 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3812 * convert the virtual clock precision to KHz here for higher
3813 * precision.
3814 */
3815 u32 iclk_virtual_root_freq = 172800 * 1000;
3816 u32 iclk_pi_range = 64;
3817 u32 desired_divisor, msb_divisor_value, pi_value;
3818
12d7ceed 3819 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3820 msb_divisor_value = desired_divisor / iclk_pi_range;
3821 pi_value = desired_divisor % iclk_pi_range;
3822
3823 auxdiv = 0;
3824 divsel = msb_divisor_value - 2;
3825 phaseinc = pi_value;
3826 }
3827
3828 /* This should not happen with any sane values */
3829 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3830 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3831 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3832 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3833
3834 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3835 clock,
e615efe4
ED		 3836 auxdiv,
3837 divsel,
3838 phasedir,
3839 phaseinc);
3840
3841 /* Program SSCDIVINTPHASE6 */
988d6ee8 3842 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3843 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3844 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3845 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3846 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3847 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3848 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3849 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3850
3851 /* Program SSCAUXDIV */
988d6ee8 3852 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3853 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3854 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3855 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3856
3857 /* Enable modulator and associated divider */
988d6ee8 3858 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3859 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3860 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3861
3862 /* Wait for initialization time */
3863 udelay(24);
3864
3865 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3866
3867 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3868}
3869
275f01b2
DV		 3870static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3871 enum pipe pch_transcoder)
3872{
3873 struct drm_device *dev = crtc->base.dev;
3874 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3875 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 3876
3877 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3878 I915_READ(HTOTAL(cpu_transcoder)));
3879 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3880 I915_READ(HBLANK(cpu_transcoder)));
3881 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3882 I915_READ(HSYNC(cpu_transcoder)));
3883
3884 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3885 I915_READ(VTOTAL(cpu_transcoder)));
3886 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3887 I915_READ(VBLANK(cpu_transcoder)));
3888 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3889 I915_READ(VSYNC(cpu_transcoder)));
3890 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3891 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3892}
3893
003632d9 3894static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 3895{
3896 struct drm_i915_private *dev_priv = dev->dev_private;
3897 uint32_t temp;
3898
3899 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 3900 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 3901 return;
3902
3903 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3904 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3905
003632d9
ACO		 3906 temp &= ~FDI_BC_BIFURCATION_SELECT;
3907 if (enable)
3908 temp |= FDI_BC_BIFURCATION_SELECT;
3909
3910 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 3911 I915_WRITE(SOUTH_CHICKEN1, temp);
3912 POSTING_READ(SOUTH_CHICKEN1);
3913}
3914
3915static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3916{
3917 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 3918
3919 switch (intel_crtc->pipe) {
3920 case PIPE_A:
3921 break;
3922 case PIPE_B:
6e3c9717 3923 if (intel_crtc->config->fdi_lanes > 2)
003632d9 3924 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 3925 else
003632d9 3926 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 3927
3928 break;
3929 case PIPE_C:
003632d9 3930 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 3931
3932 break;
3933 default:
3934 BUG();
3935 }
3936}
3937
f67a559d
JB		 3938/*
3939 * Enable PCH resources required for PCH ports:
3940 * - PCH PLLs
3941 * - FDI training & RX/TX
3942 * - update transcoder timings
3943 * - DP transcoding bits
3944 * - transcoder
3945 */
3946static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3947{
3948 struct drm_device *dev = crtc->dev;
3949 struct drm_i915_private *dev_priv = dev->dev_private;
3950 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3951 int pipe = intel_crtc->pipe;
ee7b9f93 3952 u32 reg, temp;
2c07245f 3953
ab9412ba 3954 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 3955
1fbc0d78
DV		 3956 if (IS_IVYBRIDGE(dev))
3957 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3958
cd986abb
DV		 3959 /* Write the TU size bits before fdi link training, so that error
3960 * detection works. */
3961 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3962 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3963
c98e9dcf 3964 /* For PCH output, training FDI link */
674cf967 3965 dev_priv->display.fdi_link_train(crtc);
2c07245f 3966
3ad8a208
DV		 3967 /* We need to program the right clock selection before writing the pixel
3968 * mutliplier into the DPLL. */
303b81e0 3969 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3970 u32 sel;
4b645f14 3971
c98e9dcf 3972 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 3973 temp |= TRANS_DPLL_ENABLE(pipe);
3974 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 3975 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 3976 temp |= sel;
3977 else
3978 temp &= ~sel;
c98e9dcf 3979 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3980 }
5eddb70b 3981
3ad8a208
DV		 3982 /* XXX: pch pll's can be enabled any time before we enable the PCH
3983 * transcoder, and we actually should do this to not upset any PCH
3984 * transcoder that already use the clock when we share it.
3985 *
3986 * Note that enable_shared_dpll tries to do the right thing, but
3987 * get_shared_dpll unconditionally resets the pll - we need that to have
3988 * the right LVDS enable sequence. */
85b3894f 3989 intel_enable_shared_dpll(intel_crtc);
3ad8a208 3990
d9b6cb56
JB		 3991 /* set transcoder timing, panel must allow it */
3992 assert_panel_unlocked(dev_priv, pipe);
275f01b2 3993 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 3994
303b81e0 3995 intel_fdi_normal_train(crtc);
5e84e1a4 3996
c98e9dcf 3997 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 3998 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 3999 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4000 reg = TRANS_DP_CTL(pipe);
4001 temp = I915_READ(reg);
4002 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4003 TRANS_DP_SYNC_MASK |
4004 TRANS_DP_BPC_MASK);
5eddb70b
CW		 4005 temp |= (TRANS_DP_OUTPUT_ENABLE |
4006 TRANS_DP_ENH_FRAMING);
9325c9f0 4007 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4008
4009 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4010 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4011 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4012 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4013
4014 switch (intel_trans_dp_port_sel(crtc)) {
4015 case PCH_DP_B:
5eddb70b 4016 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4017 break;
4018 case PCH_DP_C:
5eddb70b 4019 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4020 break;
4021 case PCH_DP_D:
5eddb70b 4022 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4023 break;
4024 default:
e95d41e1 4025 BUG();
32f9d658 4026 }
2c07245f 4027
5eddb70b 4028 I915_WRITE(reg, temp);
6be4a607 4029 }
b52eb4dc 4030
b8a4f404 4031 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4032}
4033
1507e5bd
PZ		 4034static void lpt_pch_enable(struct drm_crtc *crtc)
4035{
4036 struct drm_device *dev = crtc->dev;
4037 struct drm_i915_private *dev_priv = dev->dev_private;
4038 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4039 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4040
ab9412ba 4041 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4042
8c52b5e8 4043 lpt_program_iclkip(crtc);
1507e5bd 4044
0540e488 4045 /* Set transcoder timing. */
275f01b2 4046 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4047
937bb610 4048 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4049}
4050
716c2e55 4051void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 4052{
e2b78267 4053 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 4054
4055 if (pll == NULL)
4056 return;
4057
3e369b76 4058 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
1e6f2ddc 4059 WARN(1, "bad %s crtc mask\n", pll->name);
ee7b9f93
JB		 4060 return;
4061 }
4062
3e369b76
ACO		 4063 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4064 if (pll->config.crtc_mask == 0) {
f4a091c7
DV		 4065 WARN_ON(pll->on);
4066 WARN_ON(pll->active);
4067 }
4068
6e3c9717 4069 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 4070}
4071
190f68c5
ACO		 4072struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4073 struct intel_crtc_state *crtc_state)
ee7b9f93 4074{
e2b78267 4075 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4076 struct intel_shared_dpll *pll;
e2b78267 4077 enum intel_dpll_id i;
ee7b9f93 4078
98b6bd99
DV		 4079 if (HAS_PCH_IBX(dev_priv->dev)) {
4080 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4081 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4082 pll = &dev_priv->shared_dplls[i];
98b6bd99 4083
46edb027
DV		 4084 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4085 crtc->base.base.id, pll->name);
98b6bd99 4086
8bd31e67 4087 WARN_ON(pll->new_config->crtc_mask);
f2a69f44 4088
98b6bd99
DV		 4089 goto found;
4090 }
4091
e72f9fbf
DV		 4092 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4093 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4094
4095 /* Only want to check enabled timings first */
8bd31e67 4096 if (pll->new_config->crtc_mask == 0)
ee7b9f93
JB		 4097 continue;
4098
190f68c5 4099 if (memcmp(&crtc_state->dpll_hw_state,
8bd31e67
ACO		 4100 &pll->new_config->hw_state,
4101 sizeof(pll->new_config->hw_state)) == 0) {
4102 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4103 crtc->base.base.id, pll->name,
8bd31e67
ACO		 4104 pll->new_config->crtc_mask,
4105 pll->active);
ee7b9f93
JB		 4106 goto found;
4107 }
4108 }
4109
4110 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4111 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4112 pll = &dev_priv->shared_dplls[i];
8bd31e67 4113 if (pll->new_config->crtc_mask == 0) {
46edb027
DV		 4114 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4115 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4116 goto found;
4117 }
4118 }
4119
4120 return NULL;
4121
4122found:
8bd31e67 4123 if (pll->new_config->crtc_mask == 0)
190f68c5 4124 pll->new_config->hw_state = crtc_state->dpll_hw_state;
f2a69f44 4125
190f68c5 4126 crtc_state->shared_dpll = i;
46edb027
DV		 4127 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4128 pipe_name(crtc->pipe));
ee7b9f93 4129
8bd31e67 4130 pll->new_config->crtc_mask |= 1 << crtc->pipe;
e04c7350 4131
ee7b9f93
JB		 4132 return pll;
4133}
4134
8bd31e67
ACO		 4135/**
4136 * intel_shared_dpll_start_config - start a new PLL staged config
4137 * @dev_priv: DRM device
4138 * @clear_pipes: mask of pipes that will have their PLLs freed
4139 *
4140 * Starts a new PLL staged config, copying the current config but
4141 * releasing the references of pipes specified in clear_pipes.
4142 */
4143static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4144 unsigned clear_pipes)
4145{
4146 struct intel_shared_dpll *pll;
4147 enum intel_dpll_id i;
4148
4149 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4150 pll = &dev_priv->shared_dplls[i];
4151
4152 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4153 GFP_KERNEL);
4154 if (!pll->new_config)
4155 goto cleanup;
4156
4157 pll->new_config->crtc_mask &= ~clear_pipes;
4158 }
4159
4160 return 0;
4161
4162cleanup:
4163 while (--i >= 0) {
4164 pll = &dev_priv->shared_dplls[i];
f354d733 4165 kfree(pll->new_config);
8bd31e67
ACO		 4166 pll->new_config = NULL;
4167 }
4168
4169 return -ENOMEM;
4170}
4171
4172static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4173{
4174 struct intel_shared_dpll *pll;
4175 enum intel_dpll_id i;
4176
4177 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4178 pll = &dev_priv->shared_dplls[i];
4179
4180 WARN_ON(pll->new_config == &pll->config);
4181
4182 pll->config = *pll->new_config;
4183 kfree(pll->new_config);
4184 pll->new_config = NULL;
4185 }
4186}
4187
4188static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4189{
4190 struct intel_shared_dpll *pll;
4191 enum intel_dpll_id i;
4192
4193 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4194 pll = &dev_priv->shared_dplls[i];
4195
4196 WARN_ON(pll->new_config == &pll->config);
4197
4198 kfree(pll->new_config);
4199 pll->new_config = NULL;
4200 }
4201}
4202
a1520318 4203static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4204{
4205 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4206 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4207 u32 temp;
4208
4209 temp = I915_READ(dslreg);
4210 udelay(500);
4211 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4212 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4213 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4214 }
4215}
4216
bd2e244f
JB		 4217static void skylake_pfit_enable(struct intel_crtc *crtc)
4218{
4219 struct drm_device *dev = crtc->base.dev;
4220 struct drm_i915_private *dev_priv = dev->dev_private;
4221 int pipe = crtc->pipe;
4222
6e3c9717 4223 if (crtc->config->pch_pfit.enabled) {
bd2e244f 4224 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
6e3c9717
ACO		 4225 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4226 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
bd2e244f
JB		 4227 }
4228}
4229
b074cec8
JB		 4230static void ironlake_pfit_enable(struct intel_crtc *crtc)
4231{
4232 struct drm_device *dev = crtc->base.dev;
4233 struct drm_i915_private *dev_priv = dev->dev_private;
4234 int pipe = crtc->pipe;
4235
6e3c9717 4236 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4237 /* Force use of hard-coded filter coefficients
4238 * as some pre-programmed values are broken,
4239 * e.g. x201.
4240 */
4241 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4242 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4243 PF_PIPE_SEL_IVB(pipe));
4244 else
4245 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4246 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4247 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4248 }
4249}
4250
4a3b8769 4251static void intel_enable_sprite_planes(struct drm_crtc *crtc)
bb53d4ae
VS		 4252{
4253 struct drm_device *dev = crtc->dev;
4254 enum pipe pipe = to_intel_crtc(crtc)->pipe;
af2b653b 4255 struct drm_plane *plane;
bb53d4ae
VS		 4256 struct intel_plane *intel_plane;
4257
af2b653b
MR		 4258 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4259 intel_plane = to_intel_plane(plane);
bb53d4ae
VS		 4260 if (intel_plane->pipe == pipe)
4261 intel_plane_restore(&intel_plane->base);
af2b653b 4262 }
bb53d4ae
VS		 4263}
4264
0d703d4e
MR		 4265/*
4266 * Disable a plane internally without actually modifying the plane's state.
4267 * This will allow us to easily restore the plane later by just reprogramming
4268 * its state.
4269 */
4270static void disable_plane_internal(struct drm_plane *plane)
4271{
4272 struct intel_plane *intel_plane = to_intel_plane(plane);
4273 struct drm_plane_state *state =
4274 plane->funcs->atomic_duplicate_state(plane);
4275 struct intel_plane_state *intel_state = to_intel_plane_state(state);
4276
4277 intel_state->visible = false;
4278 intel_plane->commit_plane(plane, intel_state);
4279
4280 intel_plane_destroy_state(plane, state);
4281}
4282
4a3b8769 4283static void intel_disable_sprite_planes(struct drm_crtc *crtc)
bb53d4ae
VS		 4284{
4285 struct drm_device *dev = crtc->dev;
4286 enum pipe pipe = to_intel_crtc(crtc)->pipe;
af2b653b 4287 struct drm_plane *plane;
bb53d4ae
VS		 4288 struct intel_plane *intel_plane;
4289
af2b653b
MR		 4290 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4291 intel_plane = to_intel_plane(plane);
0d703d4e
MR		 4292 if (plane->fb && intel_plane->pipe == pipe)
4293 disable_plane_internal(plane);
af2b653b 4294 }
bb53d4ae
VS		 4295}
4296
20bc8673 4297void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4298{
cea165c3
VS		 4299 struct drm_device *dev = crtc->base.dev;
4300 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4301
6e3c9717 4302 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4303 return;
4304
cea165c3
VS		 4305 /* We can only enable IPS after we enable a plane and wait for a vblank */
4306 intel_wait_for_vblank(dev, crtc->pipe);
4307
d77e4531 4308 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4309 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4310 mutex_lock(&dev_priv->rps.hw_lock);
4311 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4312 mutex_unlock(&dev_priv->rps.hw_lock);
4313 /* Quoting Art Runyan: "its not safe to expect any particular
4314 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4315 * mailbox." Moreover, the mailbox may return a bogus state,
4316 * so we need to just enable it and continue on.
2a114cc1
BW		 4317 */
4318 } else {
4319 I915_WRITE(IPS_CTL, IPS_ENABLE);
4320 /* The bit only becomes 1 in the next vblank, so this wait here
4321 * is essentially intel_wait_for_vblank. If we don't have this
4322 * and don't wait for vblanks until the end of crtc_enable, then
4323 * the HW state readout code will complain that the expected
4324 * IPS_CTL value is not the one we read. */
4325 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4326 DRM_ERROR("Timed out waiting for IPS enable\n");
4327 }
d77e4531
PZ		 4328}
4329
20bc8673 4330void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4331{
4332 struct drm_device *dev = crtc->base.dev;
4333 struct drm_i915_private *dev_priv = dev->dev_private;
4334
6e3c9717 4335 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4336 return;
4337
4338 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4339 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4340 mutex_lock(&dev_priv->rps.hw_lock);
4341 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4342 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4343 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4344 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4345 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4346 } else {
2a114cc1 4347 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4348 POSTING_READ(IPS_CTL);
4349 }
d77e4531
PZ		 4350
4351 /* We need to wait for a vblank before we can disable the plane. */
4352 intel_wait_for_vblank(dev, crtc->pipe);
4353}
4354
4355/** Loads the palette/gamma unit for the CRTC with the prepared values */
4356static void intel_crtc_load_lut(struct drm_crtc *crtc)
4357{
4358 struct drm_device *dev = crtc->dev;
4359 struct drm_i915_private *dev_priv = dev->dev_private;
4360 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4361 enum pipe pipe = intel_crtc->pipe;
4362 int palreg = PALETTE(pipe);
4363 int i;
4364 bool reenable_ips = false;
4365
4366 /* The clocks have to be on to load the palette. */
83d65738 4367 if (!crtc->state->enable || !intel_crtc->active)
d77e4531
PZ		 4368 return;
4369
4370 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
409ee761 4371 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4372 assert_dsi_pll_enabled(dev_priv);
4373 else
4374 assert_pll_enabled(dev_priv, pipe);
4375 }
4376
4377 /* use legacy palette for Ironlake */
7a1db49a 4378 if (!HAS_GMCH_DISPLAY(dev))
d77e4531
PZ		 4379 palreg = LGC_PALETTE(pipe);
4380
4381 /* Workaround : Do not read or write the pipe palette/gamma data while
4382 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4383 */
6e3c9717 4384 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4385 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4386 GAMMA_MODE_MODE_SPLIT)) {
4387 hsw_disable_ips(intel_crtc);
4388 reenable_ips = true;
4389 }
4390
4391 for (i = 0; i < 256; i++) {
4392 I915_WRITE(palreg + 4 * i,
4393 (intel_crtc->lut_r[i] << 16) |
4394 (intel_crtc->lut_g[i] << 8) |
4395 intel_crtc->lut_b[i]);
4396 }
4397
4398 if (reenable_ips)
4399 hsw_enable_ips(intel_crtc);
4400}
4401
d3eedb1a
VS		 4402static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4403{
4404 if (!enable && intel_crtc->overlay) {
4405 struct drm_device *dev = intel_crtc->base.dev;
4406 struct drm_i915_private *dev_priv = dev->dev_private;
4407
4408 mutex_lock(&dev->struct_mutex);
4409 dev_priv->mm.interruptible = false;
4410 (void) intel_overlay_switch_off(intel_crtc->overlay);
4411 dev_priv->mm.interruptible = true;
4412 mutex_unlock(&dev->struct_mutex);
4413 }
4414
4415 /* Let userspace switch the overlay on again. In most cases userspace
4416 * has to recompute where to put it anyway.
4417 */
4418}
4419
d3eedb1a 4420static void intel_crtc_enable_planes(struct drm_crtc *crtc)
a5c4d7bc
VS		 4421{
4422 struct drm_device *dev = crtc->dev;
a5c4d7bc
VS		 4423 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4424 int pipe = intel_crtc->pipe;
a5c4d7bc 4425
fdd508a6 4426 intel_enable_primary_hw_plane(crtc->primary, crtc);
4a3b8769 4427 intel_enable_sprite_planes(crtc);
a5c4d7bc 4428 intel_crtc_update_cursor(crtc, true);
d3eedb1a 4429 intel_crtc_dpms_overlay(intel_crtc, true);
a5c4d7bc
VS		 4430
4431 hsw_enable_ips(intel_crtc);
4432
4433 mutex_lock(&dev->struct_mutex);
7ff0ebcc 4434 intel_fbc_update(dev);
a5c4d7bc 4435 mutex_unlock(&dev->struct_mutex);
f99d7069
DV		 4436
4437 /*
4438 * FIXME: Once we grow proper nuclear flip support out of this we need
4439 * to compute the mask of flip planes precisely. For the time being
4440 * consider this a flip from a NULL plane.
4441 */
4442 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4443}
4444
d3eedb1a 4445static void intel_crtc_disable_planes(struct drm_crtc *crtc)
a5c4d7bc
VS		 4446{
4447 struct drm_device *dev = crtc->dev;
4448 struct drm_i915_private *dev_priv = dev->dev_private;
4449 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4450 int pipe = intel_crtc->pipe;
a5c4d7bc
VS		 4451
4452 intel_crtc_wait_for_pending_flips(crtc);
a5c4d7bc 4453
e35fef21 4454 if (dev_priv->fbc.crtc == intel_crtc)
7ff0ebcc 4455 intel_fbc_disable(dev);
a5c4d7bc
VS		 4456
4457 hsw_disable_ips(intel_crtc);
4458
d3eedb1a 4459 intel_crtc_dpms_overlay(intel_crtc, false);
a5c4d7bc 4460 intel_crtc_update_cursor(crtc, false);
4a3b8769 4461 intel_disable_sprite_planes(crtc);
fdd508a6 4462 intel_disable_primary_hw_plane(crtc->primary, crtc);
f98551ae 4463
f99d7069
DV		 4464 /*
4465 * FIXME: Once we grow proper nuclear flip support out of this we need
4466 * to compute the mask of flip planes precisely. For the time being
4467 * consider this a flip to a NULL plane.
4468 */
4469 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4470}
4471
f67a559d
JB		 4472static void ironlake_crtc_enable(struct drm_crtc *crtc)
4473{
4474 struct drm_device *dev = crtc->dev;
4475 struct drm_i915_private *dev_priv = dev->dev_private;
4476 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4477 struct intel_encoder *encoder;
f67a559d 4478 int pipe = intel_crtc->pipe;
f67a559d 4479
83d65738 4480 WARN_ON(!crtc->state->enable);
08a48469 4481
f67a559d
JB		 4482 if (intel_crtc->active)
4483 return;
4484
6e3c9717 4485 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4486 intel_prepare_shared_dpll(intel_crtc);
4487
6e3c9717 4488 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4489 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4490
4491 intel_set_pipe_timings(intel_crtc);
4492
6e3c9717 4493 if (intel_crtc->config->has_pch_encoder) {
29407aab 4494 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4495 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4496 }
4497
4498 ironlake_set_pipeconf(crtc);
4499
f67a559d 4500 intel_crtc->active = true;
8664281b 4501
a72e4c9f
DV		 4502 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4503 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4504
f6736a1a 4505 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4506 if (encoder->pre_enable)
4507 encoder->pre_enable(encoder);
f67a559d 4508
6e3c9717 4509 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4510 /* Note: FDI PLL enabling _must_ be done before we enable the
4511 * cpu pipes, hence this is separate from all the other fdi/pch
4512 * enabling. */
88cefb6c 4513 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4514 } else {
4515 assert_fdi_tx_disabled(dev_priv, pipe);
4516 assert_fdi_rx_disabled(dev_priv, pipe);
4517 }
f67a559d 4518
b074cec8 4519 ironlake_pfit_enable(intel_crtc);
f67a559d 4520
9c54c0dd
JB		 4521 /*
4522 * On ILK+ LUT must be loaded before the pipe is running but with
4523 * clocks enabled
4524 */
4525 intel_crtc_load_lut(crtc);
4526
f37fcc2a 4527 intel_update_watermarks(crtc);
e1fdc473 4528 intel_enable_pipe(intel_crtc);
f67a559d 4529
6e3c9717 4530 if (intel_crtc->config->has_pch_encoder)
f67a559d 4531 ironlake_pch_enable(crtc);
c98e9dcf 4532
f9b61ff6
DV		 4533 assert_vblank_disabled(crtc);
4534 drm_crtc_vblank_on(crtc);
4535
fa5c73b1
DV		 4536 for_each_encoder_on_crtc(dev, crtc, encoder)
4537 encoder->enable(encoder);
61b77ddd
DV		 4538
4539 if (HAS_PCH_CPT(dev))
a1520318 4540 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100 4541
d3eedb1a 4542 intel_crtc_enable_planes(crtc);
6be4a607
JB		 4543}
4544
42db64ef
PZ		 4545/* IPS only exists on ULT machines and is tied to pipe A. */
4546static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4547{
f5adf94e 4548 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4549}
4550
e4916946
PZ		 4551/*
4552 * This implements the workaround described in the "notes" section of the mode
4553 * set sequence documentation. When going from no pipes or single pipe to
4554 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4555 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4556 */
4557static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4558{
4559 struct drm_device *dev = crtc->base.dev;
4560 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4561
4562 /* We want to get the other_active_crtc only if there's only 1 other
4563 * active crtc. */
d3fcc808 4564 for_each_intel_crtc(dev, crtc_it) {
e4916946
PZ		 4565 if (!crtc_it->active || crtc_it == crtc)
4566 continue;
4567
4568 if (other_active_crtc)
4569 return;
4570
4571 other_active_crtc = crtc_it;
4572 }
4573 if (!other_active_crtc)
4574 return;
4575
4576 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4577 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4578}
4579
4f771f10
PZ		 4580static void haswell_crtc_enable(struct drm_crtc *crtc)
4581{
4582 struct drm_device *dev = crtc->dev;
4583 struct drm_i915_private *dev_priv = dev->dev_private;
4584 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4585 struct intel_encoder *encoder;
4586 int pipe = intel_crtc->pipe;
4f771f10 4587
83d65738 4588 WARN_ON(!crtc->state->enable);
4f771f10
PZ		 4589
4590 if (intel_crtc->active)
4591 return;
4592
df8ad70c
DV		 4593 if (intel_crtc_to_shared_dpll(intel_crtc))
4594 intel_enable_shared_dpll(intel_crtc);
4595
6e3c9717 4596 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4597 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 4598
4599 intel_set_pipe_timings(intel_crtc);
4600
6e3c9717
ACO		 4601 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4602 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4603 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 4604 }
4605
6e3c9717 4606 if (intel_crtc->config->has_pch_encoder) {
229fca97 4607 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4608 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 4609 }
4610
4611 haswell_set_pipeconf(crtc);
4612
4613 intel_set_pipe_csc(crtc);
4614
4f771f10 4615 intel_crtc->active = true;
8664281b 4616
a72e4c9f 4617 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ		 4618 for_each_encoder_on_crtc(dev, crtc, encoder)
4619 if (encoder->pre_enable)
4620 encoder->pre_enable(encoder);
4621
6e3c9717 4622 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 4623 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4624 true);
4fe9467d
ID		 4625 dev_priv->display.fdi_link_train(crtc);
4626 }
4627
1f544388 4628 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 4629
bd2e244f
JB		 4630 if (IS_SKYLAKE(dev))
4631 skylake_pfit_enable(intel_crtc);
4632 else
4633 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 4634
4635 /*
4636 * On ILK+ LUT must be loaded before the pipe is running but with
4637 * clocks enabled
4638 */
4639 intel_crtc_load_lut(crtc);
4640
1f544388 4641 intel_ddi_set_pipe_settings(crtc);
8228c251 4642 intel_ddi_enable_transcoder_func(crtc);
4f771f10 4643
f37fcc2a 4644 intel_update_watermarks(crtc);
e1fdc473 4645 intel_enable_pipe(intel_crtc);
42db64ef 4646
6e3c9717 4647 if (intel_crtc->config->has_pch_encoder)
1507e5bd 4648 lpt_pch_enable(crtc);
4f771f10 4649
6e3c9717 4650 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA		 4651 intel_ddi_set_vc_payload_alloc(crtc, true);
4652
f9b61ff6
DV		 4653 assert_vblank_disabled(crtc);
4654 drm_crtc_vblank_on(crtc);
4655
8807e55b 4656 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 4657 encoder->enable(encoder);
8807e55b
JN		 4658 intel_opregion_notify_encoder(encoder, true);
4659 }
4f771f10 4660
e4916946
PZ		 4661 /* If we change the relative order between pipe/planes enabling, we need
4662 * to change the workaround. */
4663 haswell_mode_set_planes_workaround(intel_crtc);
d3eedb1a 4664 intel_crtc_enable_planes(crtc);
4f771f10
PZ		 4665}
4666
bd2e244f
JB		 4667static void skylake_pfit_disable(struct intel_crtc *crtc)
4668{
4669 struct drm_device *dev = crtc->base.dev;
4670 struct drm_i915_private *dev_priv = dev->dev_private;
4671 int pipe = crtc->pipe;
4672
4673 /* To avoid upsetting the power well on haswell only disable the pfit if
4674 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 4675 if (crtc->config->pch_pfit.enabled) {
bd2e244f
JB		 4676 I915_WRITE(PS_CTL(pipe), 0);
4677 I915_WRITE(PS_WIN_POS(pipe), 0);
4678 I915_WRITE(PS_WIN_SZ(pipe), 0);
4679 }
4680}
4681
3f8dce3a
DV		 4682static void ironlake_pfit_disable(struct intel_crtc *crtc)
4683{
4684 struct drm_device *dev = crtc->base.dev;
4685 struct drm_i915_private *dev_priv = dev->dev_private;
4686 int pipe = crtc->pipe;
4687
4688 /* To avoid upsetting the power well on haswell only disable the pfit if
4689 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 4690 if (crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 4691 I915_WRITE(PF_CTL(pipe), 0);
4692 I915_WRITE(PF_WIN_POS(pipe), 0);
4693 I915_WRITE(PF_WIN_SZ(pipe), 0);
4694 }
4695}
4696
6be4a607
JB		 4697static void ironlake_crtc_disable(struct drm_crtc *crtc)
4698{
4699 struct drm_device *dev = crtc->dev;
4700 struct drm_i915_private *dev_priv = dev->dev_private;
4701 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4702 struct intel_encoder *encoder;
6be4a607 4703 int pipe = intel_crtc->pipe;
5eddb70b 4704 u32 reg, temp;
b52eb4dc 4705
f7abfe8b
CW		 4706 if (!intel_crtc->active)
4707 return;
4708
d3eedb1a 4709 intel_crtc_disable_planes(crtc);
a5c4d7bc 4710
ea9d758d
DV		 4711 for_each_encoder_on_crtc(dev, crtc, encoder)
4712 encoder->disable(encoder);
4713
f9b61ff6
DV		 4714 drm_crtc_vblank_off(crtc);
4715 assert_vblank_disabled(crtc);
4716
6e3c9717 4717 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 4718 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 4719
575f7ab7 4720 intel_disable_pipe(intel_crtc);
32f9d658 4721
3f8dce3a 4722 ironlake_pfit_disable(intel_crtc);
2c07245f 4723
bf49ec8c
DV		 4724 for_each_encoder_on_crtc(dev, crtc, encoder)
4725 if (encoder->post_disable)
4726 encoder->post_disable(encoder);
2c07245f 4727
6e3c9717 4728 if (intel_crtc->config->has_pch_encoder) {
d925c59a 4729 ironlake_fdi_disable(crtc);
913d8d11 4730
d925c59a 4731 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 4732
d925c59a
DV		 4733 if (HAS_PCH_CPT(dev)) {
4734 /* disable TRANS_DP_CTL */
4735 reg = TRANS_DP_CTL(pipe);
4736 temp = I915_READ(reg);
4737 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4738 TRANS_DP_PORT_SEL_MASK);
4739 temp |= TRANS_DP_PORT_SEL_NONE;
4740 I915_WRITE(reg, temp);
4741
4742 /* disable DPLL_SEL */
4743 temp = I915_READ(PCH_DPLL_SEL);
11887397 4744 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 4745 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 4746 }
e3421a18 4747
d925c59a 4748 /* disable PCH DPLL */
e72f9fbf 4749 intel_disable_shared_dpll(intel_crtc);
8db9d77b 4750
d925c59a
DV		 4751 ironlake_fdi_pll_disable(intel_crtc);
4752 }
6b383a7f 4753
f7abfe8b 4754 intel_crtc->active = false;
46ba614c 4755 intel_update_watermarks(crtc);
d1ebd816
BW		 4756
4757 mutex_lock(&dev->struct_mutex);
7ff0ebcc 4758 intel_fbc_update(dev);
d1ebd816 4759 mutex_unlock(&dev->struct_mutex);
6be4a607 4760}
1b3c7a47 4761
4f771f10 4762static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 4763{
4f771f10
PZ		 4764 struct drm_device *dev = crtc->dev;
4765 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 4766 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 4767 struct intel_encoder *encoder;
6e3c9717 4768 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 4769
4f771f10
PZ		 4770 if (!intel_crtc->active)
4771 return;
4772
d3eedb1a 4773 intel_crtc_disable_planes(crtc);
dda9a66a 4774
8807e55b
JN		 4775 for_each_encoder_on_crtc(dev, crtc, encoder) {
4776 intel_opregion_notify_encoder(encoder, false);
4f771f10 4777 encoder->disable(encoder);
8807e55b 4778 }
4f771f10 4779
f9b61ff6
DV		 4780 drm_crtc_vblank_off(crtc);
4781 assert_vblank_disabled(crtc);
4782
6e3c9717 4783 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 4784 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4785 false);
575f7ab7 4786 intel_disable_pipe(intel_crtc);
4f771f10 4787
6e3c9717 4788 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 4789 intel_ddi_set_vc_payload_alloc(crtc, false);
4790
ad80a810 4791 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 4792
bd2e244f
JB		 4793 if (IS_SKYLAKE(dev))
4794 skylake_pfit_disable(intel_crtc);
4795 else
4796 ironlake_pfit_disable(intel_crtc);
4f771f10 4797
1f544388 4798 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 4799
6e3c9717 4800 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 4801 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 4802 intel_ddi_fdi_disable(crtc);
83616634 4803 }
4f771f10 4804
97b040aa
ID		 4805 for_each_encoder_on_crtc(dev, crtc, encoder)
4806 if (encoder->post_disable)
4807 encoder->post_disable(encoder);
4808
4f771f10 4809 intel_crtc->active = false;
46ba614c 4810 intel_update_watermarks(crtc);
4f771f10
PZ		 4811
4812 mutex_lock(&dev->struct_mutex);
7ff0ebcc 4813 intel_fbc_update(dev);
4f771f10 4814 mutex_unlock(&dev->struct_mutex);
df8ad70c
DV		 4815
4816 if (intel_crtc_to_shared_dpll(intel_crtc))
4817 intel_disable_shared_dpll(intel_crtc);
4f771f10
PZ		 4818}
4819
ee7b9f93
JB		 4820static void ironlake_crtc_off(struct drm_crtc *crtc)
4821{
4822 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 4823 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 4824}
4825
6441ab5f 4826
2dd24552
JB		 4827static void i9xx_pfit_enable(struct intel_crtc *crtc)
4828{
4829 struct drm_device *dev = crtc->base.dev;
4830 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 4831 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 4832
681a8504 4833 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 4834 return;
4835
2dd24552 4836 /*
c0b03411
DV		 4837 * The panel fitter should only be adjusted whilst the pipe is disabled,
4838 * according to register description and PRM.
2dd24552 4839 */
c0b03411
DV		 4840 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4841 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 4842
b074cec8
JB		 4843 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4844 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 4845
4846 /* Border color in case we don't scale up to the full screen. Black by
4847 * default, change to something else for debugging. */
4848 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 4849}
4850
d05410f9
DA		 4851static enum intel_display_power_domain port_to_power_domain(enum port port)
4852{
4853 switch (port) {
4854 case PORT_A:
4855 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4856 case PORT_B:
4857 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4858 case PORT_C:
4859 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4860 case PORT_D:
4861 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4862 default:
4863 WARN_ON_ONCE(1);
4864 return POWER_DOMAIN_PORT_OTHER;
4865 }
4866}
4867
77d22dca
ID		 4868#define for_each_power_domain(domain, mask) \
4869 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4870 if ((1 << (domain)) & (mask))
4871
319be8ae
ID		 4872enum intel_display_power_domain
4873intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4874{
4875 struct drm_device *dev = intel_encoder->base.dev;
4876 struct intel_digital_port *intel_dig_port;
4877
4878 switch (intel_encoder->type) {
4879 case INTEL_OUTPUT_UNKNOWN:
4880 /* Only DDI platforms should ever use this output type */
4881 WARN_ON_ONCE(!HAS_DDI(dev));
4882 case INTEL_OUTPUT_DISPLAYPORT:
4883 case INTEL_OUTPUT_HDMI:
4884 case INTEL_OUTPUT_EDP:
4885 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 4886 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 4887 case INTEL_OUTPUT_DP_MST:
4888 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4889 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 4890 case INTEL_OUTPUT_ANALOG:
4891 return POWER_DOMAIN_PORT_CRT;
4892 case INTEL_OUTPUT_DSI:
4893 return POWER_DOMAIN_PORT_DSI;
4894 default:
4895 return POWER_DOMAIN_PORT_OTHER;
4896 }
4897}
4898
4899static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 4900{
319be8ae
ID		 4901 struct drm_device *dev = crtc->dev;
4902 struct intel_encoder *intel_encoder;
4903 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4904 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 4905 unsigned long mask;
4906 enum transcoder transcoder;
4907
4908 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4909
4910 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4911 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 4912 if (intel_crtc->config->pch_pfit.enabled ||
4913 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 4914 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4915
319be8ae
ID		 4916 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4917 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4918
77d22dca
ID		 4919 return mask;
4920}
4921
77d22dca
ID		 4922static void modeset_update_crtc_power_domains(struct drm_device *dev)
4923{
4924 struct drm_i915_private *dev_priv = dev->dev_private;
4925 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4926 struct intel_crtc *crtc;
4927
4928 /*
4929 * First get all needed power domains, then put all unneeded, to avoid
4930 * any unnecessary toggling of the power wells.
4931 */
d3fcc808 4932 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 4933 enum intel_display_power_domain domain;
4934
83d65738 4935 if (!crtc->base.state->enable)
77d22dca
ID		 4936 continue;
4937
319be8ae 4938 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
77d22dca
ID		 4939
4940 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4941 intel_display_power_get(dev_priv, domain);
4942 }
4943
50f6e502
VS		 4944 if (dev_priv->display.modeset_global_resources)
4945 dev_priv->display.modeset_global_resources(dev);
4946
d3fcc808 4947 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 4948 enum intel_display_power_domain domain;
4949
4950 for_each_power_domain(domain, crtc->enabled_power_domains)
4951 intel_display_power_put(dev_priv, domain);
4952
4953 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4954 }
4955
4956 intel_display_set_init_power(dev_priv, false);
4957}
4958
dfcab17e 4959/* returns HPLL frequency in kHz */
f8bf63fd 4960static int valleyview_get_vco(struct drm_i915_private *dev_priv)
30a970c6 4961{
586f49dc 4962 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
30a970c6 4963
586f49dc
JB		 4964 /* Obtain SKU information */
4965 mutex_lock(&dev_priv->dpio_lock);
4966 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4967 CCK_FUSE_HPLL_FREQ_MASK;
4968 mutex_unlock(&dev_priv->dpio_lock);
30a970c6 4969
dfcab17e 4970 return vco_freq[hpll_freq] * 1000;
30a970c6
JB		 4971}
4972
f8bf63fd
VS		 4973static void vlv_update_cdclk(struct drm_device *dev)
4974{
4975 struct drm_i915_private *dev_priv = dev->dev_private;
4976
4977 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
43dc52c3 4978 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
f8bf63fd
VS		 4979 dev_priv->vlv_cdclk_freq);
4980
4981 /*
4982 * Program the gmbus_freq based on the cdclk frequency.
4983 * BSpec erroneously claims we should aim for 4MHz, but
4984 * in fact 1MHz is the correct frequency.
4985 */
6be1e3d3 4986 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
f8bf63fd
VS		 4987}
4988
30a970c6
JB		 4989/* Adjust CDclk dividers to allow high res or save power if possible */
4990static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4991{
4992 struct drm_i915_private *dev_priv = dev->dev_private;
4993 u32 val, cmd;
4994
d197b7d3 4995 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
d60c4473 4996
dfcab17e 4997 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 4998 cmd = 2;
dfcab17e 4999 else if (cdclk == 266667)
30a970c6
JB		 5000 cmd = 1;
5001 else
5002 cmd = 0;
5003
5004 mutex_lock(&dev_priv->rps.hw_lock);
5005 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5006 val &= ~DSPFREQGUAR_MASK;
5007 val |= (cmd << DSPFREQGUAR_SHIFT);
5008 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5009 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5010 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5011 50)) {
5012 DRM_ERROR("timed out waiting for CDclk change\n");
5013 }
5014 mutex_unlock(&dev_priv->rps.hw_lock);
5015
dfcab17e 5016 if (cdclk == 400000) {
6bcda4f0 5017 u32 divider;
30a970c6 5018
6bcda4f0 5019 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6
JB		 5020
5021 mutex_lock(&dev_priv->dpio_lock);
5022 /* adjust cdclk divider */
5023 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
9cf33db5 5024 val &= ~DISPLAY_FREQUENCY_VALUES;
30a970c6
JB		 5025 val |= divider;
5026 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5027
5028 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5029 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5030 50))
5031 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5032 mutex_unlock(&dev_priv->dpio_lock);
5033 }
5034
5035 mutex_lock(&dev_priv->dpio_lock);
5036 /* adjust self-refresh exit latency value */
5037 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5038 val &= ~0x7f;
5039
5040 /*
5041 * For high bandwidth configs, we set a higher latency in the bunit
5042 * so that the core display fetch happens in time to avoid underruns.
5043 */
dfcab17e 5044 if (cdclk == 400000)
30a970c6
JB		 5045 val |= 4500 / 250; /* 4.5 usec */
5046 else
5047 val |= 3000 / 250; /* 3.0 usec */
5048 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5049 mutex_unlock(&dev_priv->dpio_lock);
5050
f8bf63fd 5051 vlv_update_cdclk(dev);
30a970c6
JB		 5052}
5053
383c5a6a
VS		 5054static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5055{
5056 struct drm_i915_private *dev_priv = dev->dev_private;
5057 u32 val, cmd;
5058
5059 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
5060
5061 switch (cdclk) {
383c5a6a
VS		 5062 case 333333:
5063 case 320000:
383c5a6a 5064 case 266667:
383c5a6a 5065 case 200000:
383c5a6a
VS		 5066 break;
5067 default:
5f77eeb0 5068 MISSING_CASE(cdclk);
383c5a6a
VS		 5069 return;
5070 }
5071
9d0d3fda
VS		 5072 /*
5073 * Specs are full of misinformation, but testing on actual
5074 * hardware has shown that we just need to write the desired
5075 * CCK divider into the Punit register.
5076 */
5077 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5078
383c5a6a
VS		 5079 mutex_lock(&dev_priv->rps.hw_lock);
5080 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5081 val &= ~DSPFREQGUAR_MASK_CHV;
5082 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5083 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5084 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5085 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5086 50)) {
5087 DRM_ERROR("timed out waiting for CDclk change\n");
5088 }
5089 mutex_unlock(&dev_priv->rps.hw_lock);
5090
5091 vlv_update_cdclk(dev);
5092}
5093
30a970c6
JB		 5094static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5095 int max_pixclk)
5096{
6bcda4f0 5097 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5098 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5099
30a970c6
JB		 5100 /*
5101 * Really only a few cases to deal with, as only 4 CDclks are supported:
5102 * 200MHz
5103 * 267MHz
29dc7ef3 5104 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5105 * 400MHz (VLV only)
5106 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5107 * of the lower bin and adjust if needed.
e37c67a1
VS		 5108 *
5109 * We seem to get an unstable or solid color picture at 200MHz.
5110 * Not sure what's wrong. For now use 200MHz only when all pipes
5111 * are off.
30a970c6 5112 */
6cca3195
VS		 5113 if (!IS_CHERRYVIEW(dev_priv) &&
5114 max_pixclk > freq_320*limit/100)
dfcab17e 5115 return 400000;
6cca3195 5116 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5117 return freq_320;
e37c67a1 5118 else if (max_pixclk > 0)
dfcab17e 5119 return 266667;
e37c67a1
VS		 5120 else
5121 return 200000;
30a970c6
JB		 5122}
5123
2f2d7aa1
VS		 5124/* compute the max pixel clock for new configuration */
5125static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
30a970c6
JB		 5126{
5127 struct drm_device *dev = dev_priv->dev;
5128 struct intel_crtc *intel_crtc;
5129 int max_pixclk = 0;
5130
d3fcc808 5131 for_each_intel_crtc(dev, intel_crtc) {
2f2d7aa1 5132 if (intel_crtc->new_enabled)
30a970c6 5133 max_pixclk = max(max_pixclk,
2d112de7 5134 intel_crtc->new_config->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5135 }
5136
5137 return max_pixclk;
5138}
5139
5140static void valleyview_modeset_global_pipes(struct drm_device *dev,
2f2d7aa1 5141 unsigned *prepare_pipes)
30a970c6
JB		 5142{
5143 struct drm_i915_private *dev_priv = dev->dev_private;
5144 struct intel_crtc *intel_crtc;
2f2d7aa1 5145 int max_pixclk = intel_mode_max_pixclk(dev_priv);
30a970c6 5146
d60c4473
ID		 5147 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
5148 dev_priv->vlv_cdclk_freq)
30a970c6
JB		 5149 return;
5150
2f2d7aa1 5151 /* disable/enable all currently active pipes while we change cdclk */
d3fcc808 5152 for_each_intel_crtc(dev, intel_crtc)
83d65738 5153 if (intel_crtc->base.state->enable)
30a970c6
JB		 5154 *prepare_pipes |= (1 << intel_crtc->pipe);
5155}
5156
1e69cd74
VS		 5157static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5158{
5159 unsigned int credits, default_credits;
5160
5161 if (IS_CHERRYVIEW(dev_priv))
5162 default_credits = PFI_CREDIT(12);
5163 else
5164 default_credits = PFI_CREDIT(8);
5165
5166 if (DIV_ROUND_CLOSEST(dev_priv->vlv_cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5167 /* CHV suggested value is 31 or 63 */
5168 if (IS_CHERRYVIEW(dev_priv))
5169 credits = PFI_CREDIT_31;
5170 else
5171 credits = PFI_CREDIT(15);
5172 } else {
5173 credits = default_credits;
5174 }
5175
5176 /*
5177 * WA - write default credits before re-programming
5178 * FIXME: should we also set the resend bit here?
5179 */
5180 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5181 default_credits);
5182
5183 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5184 credits | PFI_CREDIT_RESEND);
5185
5186 /*
5187 * FIXME is this guaranteed to clear
5188 * immediately or should we poll for it?
5189 */
5190 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5191}
5192
30a970c6
JB		 5193static void valleyview_modeset_global_resources(struct drm_device *dev)
5194{
5195 struct drm_i915_private *dev_priv = dev->dev_private;
2f2d7aa1 5196 int max_pixclk = intel_mode_max_pixclk(dev_priv);
30a970c6
JB		 5197 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5198
383c5a6a 5199 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
738c05c0
ID		 5200 /*
5201 * FIXME: We can end up here with all power domains off, yet
5202 * with a CDCLK frequency other than the minimum. To account
5203 * for this take the PIPE-A power domain, which covers the HW
5204 * blocks needed for the following programming. This can be
5205 * removed once it's guaranteed that we get here either with
5206 * the minimum CDCLK set, or the required power domains
5207 * enabled.
5208 */
5209 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5210
383c5a6a
VS		 5211 if (IS_CHERRYVIEW(dev))
5212 cherryview_set_cdclk(dev, req_cdclk);
5213 else
5214 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 5215
1e69cd74
VS		 5216 vlv_program_pfi_credits(dev_priv);
5217
738c05c0 5218 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
383c5a6a 5219 }
30a970c6
JB		 5220}
5221
89b667f8
JB		 5222static void valleyview_crtc_enable(struct drm_crtc *crtc)
5223{
5224 struct drm_device *dev = crtc->dev;
a72e4c9f 5225 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 5226 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5227 struct intel_encoder *encoder;
5228 int pipe = intel_crtc->pipe;
23538ef1 5229 bool is_dsi;
89b667f8 5230
83d65738 5231 WARN_ON(!crtc->state->enable);
89b667f8
JB		 5232
5233 if (intel_crtc->active)
5234 return;
5235
409ee761 5236 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 5237
1ae0d137
VS		 5238 if (!is_dsi) {
5239 if (IS_CHERRYVIEW(dev))
6e3c9717 5240 chv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 5241 else
6e3c9717 5242 vlv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 5243 }
5b18e57c 5244
6e3c9717 5245 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5246 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 5247
5248 intel_set_pipe_timings(intel_crtc);
5249
c14b0485
VS		 5250 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5251 struct drm_i915_private *dev_priv = dev->dev_private;
5252
5253 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5254 I915_WRITE(CHV_CANVAS(pipe), 0);
5255 }
5256
5b18e57c
DV		 5257 i9xx_set_pipeconf(intel_crtc);
5258
89b667f8 5259 intel_crtc->active = true;
89b667f8 5260
a72e4c9f 5261 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5262
89b667f8
JB		 5263 for_each_encoder_on_crtc(dev, crtc, encoder)
5264 if (encoder->pre_pll_enable)
5265 encoder->pre_pll_enable(encoder);
5266
9d556c99
CML		 5267 if (!is_dsi) {
5268 if (IS_CHERRYVIEW(dev))
6e3c9717 5269 chv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 5270 else
6e3c9717 5271 vlv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 5272 }
89b667f8
JB		 5273
5274 for_each_encoder_on_crtc(dev, crtc, encoder)
5275 if (encoder->pre_enable)
5276 encoder->pre_enable(encoder);
5277
2dd24552
JB		 5278 i9xx_pfit_enable(intel_crtc);
5279
63cbb074
VS		 5280 intel_crtc_load_lut(crtc);
5281
f37fcc2a 5282 intel_update_watermarks(crtc);
e1fdc473 5283 intel_enable_pipe(intel_crtc);
be6a6f8e 5284
4b3a9526
VS		 5285 assert_vblank_disabled(crtc);
5286 drm_crtc_vblank_on(crtc);
5287
f9b61ff6
DV		 5288 for_each_encoder_on_crtc(dev, crtc, encoder)
5289 encoder->enable(encoder);
5290
9ab0460b 5291 intel_crtc_enable_planes(crtc);
d40d9187 5292
56b80e1f 5293 /* Underruns don't raise interrupts, so check manually. */
a72e4c9f 5294 i9xx_check_fifo_underruns(dev_priv);
89b667f8
JB		 5295}
5296
f13c2ef3
DV		 5297static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5298{
5299 struct drm_device *dev = crtc->base.dev;
5300 struct drm_i915_private *dev_priv = dev->dev_private;
5301
6e3c9717
ACO		 5302 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5303 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 5304}
5305
0b8765c6 5306static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 5307{
5308 struct drm_device *dev = crtc->dev;
a72e4c9f 5309 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 5310 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5311 struct intel_encoder *encoder;
79e53945 5312 int pipe = intel_crtc->pipe;
79e53945 5313
83d65738 5314 WARN_ON(!crtc->state->enable);
08a48469 5315
f7abfe8b
CW		 5316 if (intel_crtc->active)
5317 return;
5318
f13c2ef3
DV		 5319 i9xx_set_pll_dividers(intel_crtc);
5320
6e3c9717 5321 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5322 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 5323
5324 intel_set_pipe_timings(intel_crtc);
5325
5b18e57c
DV		 5326 i9xx_set_pipeconf(intel_crtc);
5327
f7abfe8b 5328 intel_crtc->active = true;
6b383a7f 5329
4a3436e8 5330 if (!IS_GEN2(dev))
a72e4c9f 5331 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5332
9d6d9f19
MK		 5333 for_each_encoder_on_crtc(dev, crtc, encoder)
5334 if (encoder->pre_enable)
5335 encoder->pre_enable(encoder);
5336
f6736a1a
DV		 5337 i9xx_enable_pll(intel_crtc);
5338
2dd24552
JB		 5339 i9xx_pfit_enable(intel_crtc);
5340
63cbb074
VS		 5341 intel_crtc_load_lut(crtc);
5342
f37fcc2a 5343 intel_update_watermarks(crtc);
e1fdc473 5344 intel_enable_pipe(intel_crtc);
be6a6f8e 5345
4b3a9526
VS		 5346 assert_vblank_disabled(crtc);
5347 drm_crtc_vblank_on(crtc);
5348
f9b61ff6
DV		 5349 for_each_encoder_on_crtc(dev, crtc, encoder)
5350 encoder->enable(encoder);
5351
9ab0460b 5352 intel_crtc_enable_planes(crtc);
d40d9187 5353
4a3436e8
VS		 5354 /*
5355 * Gen2 reports pipe underruns whenever all planes are disabled.
5356 * So don't enable underrun reporting before at least some planes
5357 * are enabled.
5358 * FIXME: Need to fix the logic to work when we turn off all planes
5359 * but leave the pipe running.
5360 */
5361 if (IS_GEN2(dev))
a72e4c9f 5362 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5363
56b80e1f 5364 /* Underruns don't raise interrupts, so check manually. */
a72e4c9f 5365 i9xx_check_fifo_underruns(dev_priv);
0b8765c6 5366}
79e53945 5367
87476d63
DV		 5368static void i9xx_pfit_disable(struct intel_crtc *crtc)
5369{
5370 struct drm_device *dev = crtc->base.dev;
5371 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 5372
6e3c9717 5373 if (!crtc->config->gmch_pfit.control)
328d8e82 5374 return;
87476d63 5375
328d8e82 5376 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 5377
328d8e82
DV		 5378 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5379 I915_READ(PFIT_CONTROL));
5380 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 5381}
5382
0b8765c6
JB		 5383static void i9xx_crtc_disable(struct drm_crtc *crtc)
5384{
5385 struct drm_device *dev = crtc->dev;
5386 struct drm_i915_private *dev_priv = dev->dev_private;
5387 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5388 struct intel_encoder *encoder;
0b8765c6 5389 int pipe = intel_crtc->pipe;
ef9c3aee 5390
f7abfe8b
CW		 5391 if (!intel_crtc->active)
5392 return;
5393
4a3436e8
VS		 5394 /*
5395 * Gen2 reports pipe underruns whenever all planes are disabled.
5396 * So diasble underrun reporting before all the planes get disabled.
5397 * FIXME: Need to fix the logic to work when we turn off all planes
5398 * but leave the pipe running.
5399 */
5400 if (IS_GEN2(dev))
a72e4c9f 5401 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4a3436e8 5402
564ed191
ID		 5403 /*
5404 * Vblank time updates from the shadow to live plane control register
5405 * are blocked if the memory self-refresh mode is active at that
5406 * moment. So to make sure the plane gets truly disabled, disable
5407 * first the self-refresh mode. The self-refresh enable bit in turn
5408 * will be checked/applied by the HW only at the next frame start
5409 * event which is after the vblank start event, so we need to have a
5410 * wait-for-vblank between disabling the plane and the pipe.
5411 */
5412 intel_set_memory_cxsr(dev_priv, false);
9ab0460b
VS		 5413 intel_crtc_disable_planes(crtc);
5414
6304cd91
VS		 5415 /*
5416 * On gen2 planes are double buffered but the pipe isn't, so we must
5417 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 5418 * We also need to wait on all gmch platforms because of the
5419 * self-refresh mode constraint explained above.
6304cd91 5420 */
564ed191 5421 intel_wait_for_vblank(dev, pipe);
6304cd91 5422
4b3a9526
VS		 5423 for_each_encoder_on_crtc(dev, crtc, encoder)
5424 encoder->disable(encoder);
5425
f9b61ff6
DV		 5426 drm_crtc_vblank_off(crtc);
5427 assert_vblank_disabled(crtc);
5428
575f7ab7 5429 intel_disable_pipe(intel_crtc);
24a1f16d 5430
87476d63 5431 i9xx_pfit_disable(intel_crtc);
24a1f16d 5432
89b667f8
JB		 5433 for_each_encoder_on_crtc(dev, crtc, encoder)
5434 if (encoder->post_disable)
5435 encoder->post_disable(encoder);
5436
409ee761 5437 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 5438 if (IS_CHERRYVIEW(dev))
5439 chv_disable_pll(dev_priv, pipe);
5440 else if (IS_VALLEYVIEW(dev))
5441 vlv_disable_pll(dev_priv, pipe);
5442 else
1c4e0274 5443 i9xx_disable_pll(intel_crtc);
076ed3b2 5444 }
0b8765c6 5445
4a3436e8 5446 if (!IS_GEN2(dev))
a72e4c9f 5447 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4a3436e8 5448
f7abfe8b 5449 intel_crtc->active = false;
46ba614c 5450 intel_update_watermarks(crtc);
f37fcc2a 5451
efa9624e 5452 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5453 intel_fbc_update(dev);
efa9624e 5454 mutex_unlock(&dev->struct_mutex);
0b8765c6
JB		 5455}
5456
ee7b9f93
JB		 5457static void i9xx_crtc_off(struct drm_crtc *crtc)
5458{
5459}
5460
b04c5bd6
BF		 5461/* Master function to enable/disable CRTC and corresponding power wells */
5462void intel_crtc_control(struct drm_crtc *crtc, bool enable)
976f8a20
DV		 5463{
5464 struct drm_device *dev = crtc->dev;
5465 struct drm_i915_private *dev_priv = dev->dev_private;
0e572fe7 5466 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
0e572fe7
DV		 5467 enum intel_display_power_domain domain;
5468 unsigned long domains;
976f8a20 5469
0e572fe7
DV		 5470 if (enable) {
5471 if (!intel_crtc->active) {
e1e9fb84
DV		 5472 domains = get_crtc_power_domains(crtc);
5473 for_each_power_domain(domain, domains)
5474 intel_display_power_get(dev_priv, domain);
5475 intel_crtc->enabled_power_domains = domains;
0e572fe7
DV		 5476
5477 dev_priv->display.crtc_enable(crtc);
5478 }
5479 } else {
5480 if (intel_crtc->active) {
5481 dev_priv->display.crtc_disable(crtc);
5482
e1e9fb84
DV		 5483 domains = intel_crtc->enabled_power_domains;
5484 for_each_power_domain(domain, domains)
5485 intel_display_power_put(dev_priv, domain);
5486 intel_crtc->enabled_power_domains = 0;
0e572fe7
DV		 5487 }
5488 }
b04c5bd6
BF		 5489}
5490
5491/**
5492 * Sets the power management mode of the pipe and plane.
5493 */
5494void intel_crtc_update_dpms(struct drm_crtc *crtc)
5495{
5496 struct drm_device *dev = crtc->dev;
5497 struct intel_encoder *intel_encoder;
5498 bool enable = false;
5499
5500 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5501 enable |= intel_encoder->connectors_active;
5502
5503 intel_crtc_control(crtc, enable);
976f8a20
DV		 5504}
5505
cdd59983
CW		 5506static void intel_crtc_disable(struct drm_crtc *crtc)
5507{
cdd59983 5508 struct drm_device *dev = crtc->dev;
976f8a20 5509 struct drm_connector *connector;
ee7b9f93 5510 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 5511
976f8a20 5512 /* crtc should still be enabled when we disable it. */
83d65738 5513 WARN_ON(!crtc->state->enable);
976f8a20
DV		 5514
5515 dev_priv->display.crtc_disable(crtc);
ee7b9f93
JB		 5516 dev_priv->display.off(crtc);
5517
455a6808 5518 crtc->primary->funcs->disable_plane(crtc->primary);
976f8a20
DV		 5519
5520 /* Update computed state. */
5521 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5522 if (!connector->encoder || !connector->encoder->crtc)
5523 continue;
5524
5525 if (connector->encoder->crtc != crtc)
5526 continue;
5527
5528 connector->dpms = DRM_MODE_DPMS_OFF;
5529 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 5530 }
5531}
5532
ea5b213a 5533void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 5534{
4ef69c7a 5535 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 5536
ea5b213a
CW		 5537 drm_encoder_cleanup(encoder);
5538 kfree(intel_encoder);
7e7d76c3
JB		 5539}
5540
9237329d 5541/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 5542 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5543 * state of the entire output pipe. */
9237329d 5544static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 5545{
5ab432ef
DV		 5546 if (mode == DRM_MODE_DPMS_ON) {
5547 encoder->connectors_active = true;
5548
b2cabb0e 5549 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 5550 } else {
5551 encoder->connectors_active = false;
5552
b2cabb0e 5553 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 5554 }
79e53945
JB		 5555}
5556
0a91ca29
DV		 5557/* Cross check the actual hw state with our own modeset state tracking (and it's
5558 * internal consistency). */
b980514c 5559static void intel_connector_check_state(struct intel_connector *connector)
79e53945 5560{
0a91ca29
DV		 5561 if (connector->get_hw_state(connector)) {
5562 struct intel_encoder *encoder = connector->encoder;
5563 struct drm_crtc *crtc;
5564 bool encoder_enabled;
5565 enum pipe pipe;
5566
5567 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5568 connector->base.base.id,
c23cc417 5569 connector->base.name);
0a91ca29 5570
0e32b39c
DA		 5571 /* there is no real hw state for MST connectors */
5572 if (connector->mst_port)
5573 return;
5574
e2c719b7 5575 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
0a91ca29 5576 "wrong connector dpms state\n");
e2c719b7 5577 I915_STATE_WARN(connector->base.encoder != &encoder->base,
0a91ca29 5578 "active connector not linked to encoder\n");
0a91ca29 5579
36cd7444 5580 if (encoder) {
e2c719b7 5581 I915_STATE_WARN(!encoder->connectors_active,
36cd7444
DA		 5582 "encoder->connectors_active not set\n");
5583
5584 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
e2c719b7
RC		 5585 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
5586 if (I915_STATE_WARN_ON(!encoder->base.crtc))
36cd7444 5587 return;
0a91ca29 5588
36cd7444 5589 crtc = encoder->base.crtc;
0a91ca29 5590
83d65738
MR		 5591 I915_STATE_WARN(!crtc->state->enable,
5592 "crtc not enabled\n");
e2c719b7
RC		 5593 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5594 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
36cd7444
DA		 5595 "encoder active on the wrong pipe\n");
5596 }
0a91ca29 5597 }
79e53945
JB		 5598}
5599
5ab432ef
DV		 5600/* Even simpler default implementation, if there's really no special case to
5601 * consider. */
5602void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 5603{
5ab432ef
DV		 5604 /* All the simple cases only support two dpms states. */
5605 if (mode != DRM_MODE_DPMS_ON)
5606 mode = DRM_MODE_DPMS_OFF;
d4270e57 5607
5ab432ef
DV		 5608 if (mode == connector->dpms)
5609 return;
5610
5611 connector->dpms = mode;
5612
5613 /* Only need to change hw state when actually enabled */
c9976dcf
CW		 5614 if (connector->encoder)
5615 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
0a91ca29 5616
b980514c 5617 intel_modeset_check_state(connector->dev);
79e53945
JB		 5618}
5619
f0947c37
DV		 5620/* Simple connector->get_hw_state implementation for encoders that support only
5621 * one connector and no cloning and hence the encoder state determines the state
5622 * of the connector. */
5623bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 5624{
24929352 5625 enum pipe pipe = 0;
f0947c37 5626 struct intel_encoder *encoder = connector->encoder;
ea5b213a 5627
f0947c37 5628 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 5629}
5630
d272ddfa
VS		 5631static int pipe_required_fdi_lanes(struct drm_device *dev, enum pipe pipe)
5632{
5633 struct intel_crtc *crtc =
5634 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5635
5636 if (crtc->base.state->enable &&
5637 crtc->config->has_pch_encoder)
5638 return crtc->config->fdi_lanes;
5639
5640 return 0;
5641}
5642
1857e1da 5643static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 5644 struct intel_crtc_state *pipe_config)
1857e1da 5645{
1857e1da
DV		 5646 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5647 pipe_name(pipe), pipe_config->fdi_lanes);
5648 if (pipe_config->fdi_lanes > 4) {
5649 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5650 pipe_name(pipe), pipe_config->fdi_lanes);
5651 return false;
5652 }
5653
bafb6553 5654 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 5655 if (pipe_config->fdi_lanes > 2) {
5656 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5657 pipe_config->fdi_lanes);
5658 return false;
5659 } else {
5660 return true;
5661 }
5662 }
5663
5664 if (INTEL_INFO(dev)->num_pipes == 2)
5665 return true;
5666
5667 /* Ivybridge 3 pipe is really complicated */
5668 switch (pipe) {
5669 case PIPE_A:
5670 return true;
5671 case PIPE_B:
d272ddfa
VS		 5672 if (pipe_config->fdi_lanes > 2 &&
5673 pipe_required_fdi_lanes(dev, PIPE_C) > 0) {
1857e1da
DV		 5674 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5675 pipe_name(pipe), pipe_config->fdi_lanes);
5676 return false;
5677 }
5678 return true;
5679 case PIPE_C:
251cc67c
VS		 5680 if (pipe_config->fdi_lanes > 2) {
5681 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
5682 pipe_name(pipe), pipe_config->fdi_lanes);
5683 return false;
5684 }
d272ddfa 5685 if (pipe_required_fdi_lanes(dev, PIPE_B) > 2) {
1857e1da
DV		 5686 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5687 return false;
5688 }
5689 return true;
5690 default:
5691 BUG();
5692 }
5693}
5694
e29c22c0
DV		 5695#define RETRY 1
5696static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 5697 struct intel_crtc_state *pipe_config)
877d48d5 5698{
1857e1da 5699 struct drm_device *dev = intel_crtc->base.dev;
2d112de7 5700 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
ff9a6750 5701 int lane, link_bw, fdi_dotclock;
e29c22c0 5702 bool setup_ok, needs_recompute = false;
877d48d5 5703
e29c22c0 5704retry:
877d48d5
DV		 5705 /* FDI is a binary signal running at ~2.7GHz, encoding
5706 * each output octet as 10 bits. The actual frequency
5707 * is stored as a divider into a 100MHz clock, and the
5708 * mode pixel clock is stored in units of 1KHz.
5709 * Hence the bw of each lane in terms of the mode signal
5710 * is:
5711 */
5712 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5713
241bfc38 5714 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 5715
2bd89a07 5716 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 5717 pipe_config->pipe_bpp);
5718
5719 pipe_config->fdi_lanes = lane;
5720
2bd89a07 5721 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 5722 link_bw, &pipe_config->fdi_m_n);
1857e1da 5723
e29c22c0
DV		 5724 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5725 intel_crtc->pipe, pipe_config);
5726 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5727 pipe_config->pipe_bpp -= 2*3;
5728 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5729 pipe_config->pipe_bpp);
5730 needs_recompute = true;
5731 pipe_config->bw_constrained = true;
5732
5733 goto retry;
5734 }
5735
5736 if (needs_recompute)
5737 return RETRY;
5738
5739 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 5740}
5741
42db64ef 5742static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 5743 struct intel_crtc_state *pipe_config)
42db64ef 5744{
d330a953 5745 pipe_config->ips_enabled = i915.enable_ips &&
3c4ca58c 5746 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 5747 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 5748}
5749
a43f6e0f 5750static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 5751 struct intel_crtc_state *pipe_config)
79e53945 5752{
a43f6e0f 5753 struct drm_device *dev = crtc->base.dev;
8bd31e67 5754 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 5755 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
89749350 5756
ad3a4479 5757 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 5758 if (INTEL_INFO(dev)->gen < 4) {
cf532bb2
VS		 5759 int clock_limit =
5760 dev_priv->display.get_display_clock_speed(dev);
5761
5762 /*
5763 * Enable pixel doubling when the dot clock
5764 * is > 90% of the (display) core speed.
5765 *
b397c96b
VS		 5766 * GDG double wide on either pipe,
5767 * otherwise pipe A only.
cf532bb2 5768 */
b397c96b 5769 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 5770 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 5771 clock_limit *= 2;
cf532bb2 5772 pipe_config->double_wide = true;
ad3a4479
VS		 5773 }
5774
241bfc38 5775 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 5776 return -EINVAL;
2c07245f 5777 }
89749350 5778
1d1d0e27
VS		 5779 /*
5780 * Pipe horizontal size must be even in:
5781 * - DVO ganged mode
5782 * - LVDS dual channel mode
5783 * - Double wide pipe
5784 */
b4f2bf4c 5785 if ((intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 5786 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5787 pipe_config->pipe_src_w &= ~1;
5788
8693a824
DL		 5789 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5790 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 5791 */
5792 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5793 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 5794 return -EINVAL;
44f46b42 5795
bd080ee5 5796 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 5797 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 5798 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 5799 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5800 * for lvds. */
5801 pipe_config->pipe_bpp = 8*3;
5802 }
5803
f5adf94e 5804 if (HAS_IPS(dev))
a43f6e0f
DV		 5805 hsw_compute_ips_config(crtc, pipe_config);
5806
877d48d5 5807 if (pipe_config->has_pch_encoder)
a43f6e0f 5808 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 5809
e29c22c0 5810 return 0;
79e53945
JB		 5811}
5812
25eb05fc
JB		 5813static int valleyview_get_display_clock_speed(struct drm_device *dev)
5814{
d197b7d3 5815 struct drm_i915_private *dev_priv = dev->dev_private;
d197b7d3
VS		 5816 u32 val;
5817 int divider;
5818
6bcda4f0
VS		 5819 if (dev_priv->hpll_freq == 0)
5820 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5821
d197b7d3
VS		 5822 mutex_lock(&dev_priv->dpio_lock);
5823 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5824 mutex_unlock(&dev_priv->dpio_lock);
5825
5826 divider = val & DISPLAY_FREQUENCY_VALUES;
5827
7d007f40
VS		 5828 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5829 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5830 "cdclk change in progress\n");
5831
6bcda4f0 5832 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
25eb05fc
JB		 5833}
5834
e70236a8
JB		 5835static int i945_get_display_clock_speed(struct drm_device *dev)
5836{
5837 return 400000;
5838}
79e53945 5839
e70236a8 5840static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 5841{
e70236a8
JB		 5842 return 333000;
5843}
79e53945 5844
e70236a8
JB		 5845static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5846{
5847 return 200000;
5848}
79e53945 5849
257a7ffc
DV		 5850static int pnv_get_display_clock_speed(struct drm_device *dev)
5851{
5852 u16 gcfgc = 0;
5853
5854 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5855
5856 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5857 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5858 return 267000;
5859 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5860 return 333000;
5861 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5862 return 444000;
5863 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5864 return 200000;
5865 default:
5866 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5867 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5868 return 133000;
5869 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5870 return 167000;
5871 }
5872}
5873
e70236a8
JB		 5874static int i915gm_get_display_clock_speed(struct drm_device *dev)
5875{
5876 u16 gcfgc = 0;
79e53945 5877
e70236a8
JB		 5878 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5879
5880 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5881 return 133000;
5882 else {
5883 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5884 case GC_DISPLAY_CLOCK_333_MHZ:
5885 return 333000;
5886 default:
5887 case GC_DISPLAY_CLOCK_190_200_MHZ:
5888 return 190000;
79e53945 5889 }
e70236a8
JB		 5890 }
5891}
5892
5893static int i865_get_display_clock_speed(struct drm_device *dev)
5894{
5895 return 266000;
5896}
5897
5898static int i855_get_display_clock_speed(struct drm_device *dev)
5899{
5900 u16 hpllcc = 0;
5901 /* Assume that the hardware is in the high speed state. This
5902 * should be the default.
5903 */
5904 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5905 case GC_CLOCK_133_200:
5906 case GC_CLOCK_100_200:
5907 return 200000;
5908 case GC_CLOCK_166_250:
5909 return 250000;
5910 case GC_CLOCK_100_133:
79e53945 5911 return 133000;
e70236a8 5912 }
79e53945 5913
e70236a8
JB		 5914 /* Shouldn't happen */
5915 return 0;
5916}
79e53945 5917
e70236a8
JB		 5918static int i830_get_display_clock_speed(struct drm_device *dev)
5919{
5920 return 133000;
79e53945
JB		 5921}
5922
2c07245f 5923static void
a65851af 5924intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 5925{
a65851af
VS		 5926 while (*num > DATA_LINK_M_N_MASK ||
5927 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 5928 *num >>= 1;
5929 *den >>= 1;
5930 }
5931}
5932
a65851af
VS		 5933static void compute_m_n(unsigned int m, unsigned int n,
5934 uint32_t *ret_m, uint32_t *ret_n)
5935{
5936 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5937 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5938 intel_reduce_m_n_ratio(ret_m, ret_n);
5939}
5940
e69d0bc1
DV		 5941void
5942intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5943 int pixel_clock, int link_clock,
5944 struct intel_link_m_n *m_n)
2c07245f 5945{
e69d0bc1 5946 m_n->tu = 64;
a65851af
VS		 5947
5948 compute_m_n(bits_per_pixel * pixel_clock,
5949 link_clock * nlanes * 8,
5950 &m_n->gmch_m, &m_n->gmch_n);
5951
5952 compute_m_n(pixel_clock, link_clock,
5953 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 5954}
5955
a7615030
CW		 5956static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5957{
d330a953
JN		 5958 if (i915.panel_use_ssc >= 0)
5959 return i915.panel_use_ssc != 0;
41aa3448 5960 return dev_priv->vbt.lvds_use_ssc
435793df 5961 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 5962}
5963
409ee761 5964static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
c65d77d8 5965{
409ee761 5966 struct drm_device *dev = crtc->base.dev;
c65d77d8
JB		 5967 struct drm_i915_private *dev_priv = dev->dev_private;
5968 int refclk;
5969
a0c4da24 5970 if (IS_VALLEYVIEW(dev)) {
9a0ea498 5971 refclk = 100000;
d0737e1d 5972 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 5973 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 5974 refclk = dev_priv->vbt.lvds_ssc_freq;
5975 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 5976 } else if (!IS_GEN2(dev)) {
5977 refclk = 96000;
5978 } else {
5979 refclk = 48000;
5980 }
5981
5982 return refclk;
5983}
5984
7429e9d4 5985static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 5986{
7df00d7a 5987 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 5988}
f47709a9 5989
7429e9d4
DV		 5990static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5991{
5992 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 5993}
5994
f47709a9 5995static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 5996 struct intel_crtc_state *crtc_state,
a7516a05
JB		 5997 intel_clock_t *reduced_clock)
5998{
f47709a9 5999 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 6000 u32 fp, fp2 = 0;
6001
6002 if (IS_PINEVIEW(dev)) {
190f68c5 6003 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 6004 if (reduced_clock)
7429e9d4 6005 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 6006 } else {
190f68c5 6007 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 6008 if (reduced_clock)
7429e9d4 6009 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 6010 }
6011
190f68c5 6012 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 6013
f47709a9 6014 crtc->lowfreq_avail = false;
e1f234bd 6015 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
d330a953 6016 reduced_clock && i915.powersave) {
190f68c5 6017 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 6018 crtc->lowfreq_avail = true;
a7516a05 6019 } else {
190f68c5 6020 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 6021 }
6022}
6023
5e69f97f
CML		 6024static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6025 pipe)
89b667f8
JB		 6026{
6027 u32 reg_val;
6028
6029 /*
6030 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6031 * and set it to a reasonable value instead.
6032 */
ab3c759a 6033 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 6034 reg_val &= 0xffffff00;
6035 reg_val |= 0x00000030;
ab3c759a 6036 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 6037
ab3c759a 6038 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 6039 reg_val &= 0x8cffffff;
6040 reg_val = 0x8c000000;
ab3c759a 6041 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 6042
ab3c759a 6043 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 6044 reg_val &= 0xffffff00;
ab3c759a 6045 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 6046
ab3c759a 6047 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 6048 reg_val &= 0x00ffffff;
6049 reg_val |= 0xb0000000;
ab3c759a 6050 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 6051}
6052
b551842d
DV		 6053static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6054 struct intel_link_m_n *m_n)
6055{
6056 struct drm_device *dev = crtc->base.dev;
6057 struct drm_i915_private *dev_priv = dev->dev_private;
6058 int pipe = crtc->pipe;
6059
e3b95f1e
DV		 6060 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6061 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6062 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6063 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 6064}
6065
6066static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 6067 struct intel_link_m_n *m_n,
6068 struct intel_link_m_n *m2_n2)
b551842d
DV		 6069{
6070 struct drm_device *dev = crtc->base.dev;
6071 struct drm_i915_private *dev_priv = dev->dev_private;
6072 int pipe = crtc->pipe;
6e3c9717 6073 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 6074
6075 if (INTEL_INFO(dev)->gen >= 5) {
6076 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6077 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6078 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6079 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 6080 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6081 * for gen < 8) and if DRRS is supported (to make sure the
6082 * registers are not unnecessarily accessed).
6083 */
44395bfe 6084 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 6085 crtc->config->has_drrs) {
f769cd24
VK		 6086 I915_WRITE(PIPE_DATA_M2(transcoder),
6087 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6088 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6089 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6090 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6091 }
b551842d 6092 } else {
e3b95f1e
DV		 6093 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6094 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6095 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6096 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 6097 }
6098}
6099
fe3cd48d 6100void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 6101{
fe3cd48d
R		 6102 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6103
6104 if (m_n == M1_N1) {
6105 dp_m_n = &crtc->config->dp_m_n;
6106 dp_m2_n2 = &crtc->config->dp_m2_n2;
6107 } else if (m_n == M2_N2) {
6108
6109 /*
6110 * M2_N2 registers are not supported. Hence m2_n2 divider value
6111 * needs to be programmed into M1_N1.
6112 */
6113 dp_m_n = &crtc->config->dp_m2_n2;
6114 } else {
6115 DRM_ERROR("Unsupported divider value\n");
6116 return;
6117 }
6118
6e3c9717
ACO		 6119 if (crtc->config->has_pch_encoder)
6120 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 6121 else
fe3cd48d 6122 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 6123}
6124
d288f65f 6125static void vlv_update_pll(struct intel_crtc *crtc,
5cec258b 6126 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 6127{
6128 u32 dpll, dpll_md;
6129
6130 /*
6131 * Enable DPIO clock input. We should never disable the reference
6132 * clock for pipe B, since VGA hotplug / manual detection depends
6133 * on it.
6134 */
6135 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6136 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6137 /* We should never disable this, set it here for state tracking */
6138 if (crtc->pipe == PIPE_B)
6139 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6140 dpll |= DPLL_VCO_ENABLE;
d288f65f 6141 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 6142
d288f65f 6143 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 6144 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 6145 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 6146}
6147
d288f65f 6148static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 6149 const struct intel_crtc_state *pipe_config)
a0c4da24 6150{
f47709a9 6151 struct drm_device *dev = crtc->base.dev;
a0c4da24 6152 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 6153 int pipe = crtc->pipe;
bdd4b6a6 6154 u32 mdiv;
a0c4da24 6155 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 6156 u32 coreclk, reg_val;
a0c4da24 6157
09153000
DV		 6158 mutex_lock(&dev_priv->dpio_lock);
6159
d288f65f
VS		 6160 bestn = pipe_config->dpll.n;
6161 bestm1 = pipe_config->dpll.m1;
6162 bestm2 = pipe_config->dpll.m2;
6163 bestp1 = pipe_config->dpll.p1;
6164 bestp2 = pipe_config->dpll.p2;
a0c4da24 6165
89b667f8
JB		 6166 /* See eDP HDMI DPIO driver vbios notes doc */
6167
6168 /* PLL B needs special handling */
bdd4b6a6 6169 if (pipe == PIPE_B)
5e69f97f 6170 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 6171
6172 /* Set up Tx target for periodic Rcomp update */
ab3c759a 6173 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 6174
6175 /* Disable target IRef on PLL */
ab3c759a 6176 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 6177 reg_val &= 0x00ffffff;
ab3c759a 6178 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 6179
6180 /* Disable fast lock */
ab3c759a 6181 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 6182
6183 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 6184 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6185 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6186 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 6187 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 6188
6189 /*
6190 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6191 * but we don't support that).
6192 * Note: don't use the DAC post divider as it seems unstable.
6193 */
6194 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 6195 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 6196
a0c4da24 6197 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 6198 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 6199
89b667f8 6200 /* Set HBR and RBR LPF coefficients */
d288f65f 6201 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 6202 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6203 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 6204 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 6205 0x009f0003);
89b667f8 6206 else
ab3c759a 6207 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 6208 0x00d0000f);
6209
681a8504 6210 if (pipe_config->has_dp_encoder) {
89b667f8 6211 /* Use SSC source */
bdd4b6a6 6212 if (pipe == PIPE_A)
ab3c759a 6213 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6214 0x0df40000);
6215 else
ab3c759a 6216 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6217 0x0df70000);
6218 } else { /* HDMI or VGA */
6219 /* Use bend source */
bdd4b6a6 6220 if (pipe == PIPE_A)
ab3c759a 6221 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6222 0x0df70000);
6223 else
ab3c759a 6224 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6225 0x0df40000);
6226 }
a0c4da24 6227
ab3c759a 6228 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 6229 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 6230 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6231 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 6232 coreclk |= 0x01000000;
ab3c759a 6233 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 6234
ab3c759a 6235 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
09153000 6236 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 6237}
6238
d288f65f 6239static void chv_update_pll(struct intel_crtc *crtc,
5cec258b 6240 struct intel_crtc_state *pipe_config)
1ae0d137 6241{
d288f65f 6242 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
1ae0d137
VS		 6243 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6244 DPLL_VCO_ENABLE;
6245 if (crtc->pipe != PIPE_A)
d288f65f 6246 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 6247
d288f65f
VS		 6248 pipe_config->dpll_hw_state.dpll_md =
6249 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 6250}
6251
d288f65f 6252static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 6253 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 6254{
6255 struct drm_device *dev = crtc->base.dev;
6256 struct drm_i915_private *dev_priv = dev->dev_private;
6257 int pipe = crtc->pipe;
6258 int dpll_reg = DPLL(crtc->pipe);
6259 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 6260 u32 loopfilter, tribuf_calcntr;
9d556c99 6261 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 6262 u32 dpio_val;
9cbe40c1 6263 int vco;
9d556c99 6264
d288f65f
VS		 6265 bestn = pipe_config->dpll.n;
6266 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6267 bestm1 = pipe_config->dpll.m1;
6268 bestm2 = pipe_config->dpll.m2 >> 22;
6269 bestp1 = pipe_config->dpll.p1;
6270 bestp2 = pipe_config->dpll.p2;
9cbe40c1 6271 vco = pipe_config->dpll.vco;
a945ce7e 6272 dpio_val = 0;
9cbe40c1 6273 loopfilter = 0;
9d556c99
CML		 6274
6275 /*
6276 * Enable Refclk and SSC
6277 */
a11b0703 6278 I915_WRITE(dpll_reg,
d288f65f 6279 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703
VS		 6280
6281 mutex_lock(&dev_priv->dpio_lock);
9d556c99 6282
9d556c99
CML		 6283 /* p1 and p2 divider */
6284 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6285 5 << DPIO_CHV_S1_DIV_SHIFT |
6286 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6287 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6288 1 << DPIO_CHV_K_DIV_SHIFT);
6289
6290 /* Feedback post-divider - m2 */
6291 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6292
6293 /* Feedback refclk divider - n and m1 */
6294 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6295 DPIO_CHV_M1_DIV_BY_2 |
6296 1 << DPIO_CHV_N_DIV_SHIFT);
6297
6298 /* M2 fraction division */
a945ce7e
VP		 6299 if (bestm2_frac)
6300 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 6301
6302 /* M2 fraction division enable */
a945ce7e
VP		 6303 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6304 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6305 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6306 if (bestm2_frac)
6307 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6308 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 6309
de3a0fde
VP		 6310 /* Program digital lock detect threshold */
6311 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6312 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6313 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6314 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6315 if (!bestm2_frac)
6316 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6317 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6318
9d556c99 6319 /* Loop filter */
9cbe40c1
VP		 6320 if (vco == 5400000) {
6321 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6322 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6323 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6324 tribuf_calcntr = 0x9;
6325 } else if (vco <= 6200000) {
6326 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6327 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6328 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6329 tribuf_calcntr = 0x9;
6330 } else if (vco <= 6480000) {
6331 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6332 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6333 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6334 tribuf_calcntr = 0x8;
6335 } else {
6336 /* Not supported. Apply the same limits as in the max case */
6337 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6338 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6339 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6340 tribuf_calcntr = 0;
6341 }
9d556c99
CML		 6342 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6343
968040b2 6344 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 6345 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6346 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6347 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6348
9d556c99
CML		 6349 /* AFC Recal */
6350 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6351 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6352 DPIO_AFC_RECAL);
6353
6354 mutex_unlock(&dev_priv->dpio_lock);
6355}
6356
d288f65f
VS		 6357/**
6358 * vlv_force_pll_on - forcibly enable just the PLL
6359 * @dev_priv: i915 private structure
6360 * @pipe: pipe PLL to enable
6361 * @dpll: PLL configuration
6362 *
6363 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6364 * in cases where we need the PLL enabled even when @pipe is not going to
6365 * be enabled.
6366 */
6367void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6368 const struct dpll *dpll)
6369{
6370 struct intel_crtc *crtc =
6371 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 6372 struct intel_crtc_state pipe_config = {
d288f65f
VS		 6373 .pixel_multiplier = 1,
6374 .dpll = *dpll,
6375 };
6376
6377 if (IS_CHERRYVIEW(dev)) {
6378 chv_update_pll(crtc, &pipe_config);
6379 chv_prepare_pll(crtc, &pipe_config);
6380 chv_enable_pll(crtc, &pipe_config);
6381 } else {
6382 vlv_update_pll(crtc, &pipe_config);
6383 vlv_prepare_pll(crtc, &pipe_config);
6384 vlv_enable_pll(crtc, &pipe_config);
6385 }
6386}
6387
6388/**
6389 * vlv_force_pll_off - forcibly disable just the PLL
6390 * @dev_priv: i915 private structure
6391 * @pipe: pipe PLL to disable
6392 *
6393 * Disable the PLL for @pipe. To be used in cases where we need
6394 * the PLL enabled even when @pipe is not going to be enabled.
6395 */
6396void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6397{
6398 if (IS_CHERRYVIEW(dev))
6399 chv_disable_pll(to_i915(dev), pipe);
6400 else
6401 vlv_disable_pll(to_i915(dev), pipe);
6402}
6403
f47709a9 6404static void i9xx_update_pll(struct intel_crtc *crtc,
190f68c5 6405 struct intel_crtc_state *crtc_state,
f47709a9 6406 intel_clock_t *reduced_clock,
eb1cbe48
DV		 6407 int num_connectors)
6408{
f47709a9 6409 struct drm_device *dev = crtc->base.dev;
eb1cbe48 6410 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 6411 u32 dpll;
6412 bool is_sdvo;
190f68c5 6413 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 6414
190f68c5 6415 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 6416
d0737e1d
ACO		 6417 is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6418 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 6419
6420 dpll = DPLL_VGA_MODE_DIS;
6421
d0737e1d 6422 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 6423 dpll |= DPLLB_MODE_LVDS;
6424 else
6425 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 6426
ef1b460d 6427 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 6428 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 6429 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 6430 }
198a037f
DV		 6431
6432 if (is_sdvo)
4a33e48d 6433 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 6434
190f68c5 6435 if (crtc_state->has_dp_encoder)
4a33e48d 6436 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 6437
6438 /* compute bitmask from p1 value */
6439 if (IS_PINEVIEW(dev))
6440 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6441 else {
6442 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6443 if (IS_G4X(dev) && reduced_clock)
6444 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6445 }
6446 switch (clock->p2) {
6447 case 5:
6448 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6449 break;
6450 case 7:
6451 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6452 break;
6453 case 10:
6454 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6455 break;
6456 case 14:
6457 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6458 break;
6459 }
6460 if (INTEL_INFO(dev)->gen >= 4)
6461 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6462
190f68c5 6463 if (crtc_state->sdvo_tv_clock)
eb1cbe48 6464 dpll |= PLL_REF_INPUT_TVCLKINBC;
d0737e1d 6465 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 6466 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6467 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6468 else
6469 dpll |= PLL_REF_INPUT_DREFCLK;
6470
6471 dpll |= DPLL_VCO_ENABLE;
190f68c5 6472 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 6473
eb1cbe48 6474 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 6475 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 6476 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 6477 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 6478 }
6479}
6480
f47709a9 6481static void i8xx_update_pll(struct intel_crtc *crtc,
190f68c5 6482 struct intel_crtc_state *crtc_state,
f47709a9 6483 intel_clock_t *reduced_clock,
eb1cbe48
DV		 6484 int num_connectors)
6485{
f47709a9 6486 struct drm_device *dev = crtc->base.dev;
eb1cbe48 6487 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 6488 u32 dpll;
190f68c5 6489 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 6490
190f68c5 6491 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 6492
eb1cbe48
DV		 6493 dpll = DPLL_VGA_MODE_DIS;
6494
d0737e1d 6495 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 6496 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6497 } else {
6498 if (clock->p1 == 2)
6499 dpll |= PLL_P1_DIVIDE_BY_TWO;
6500 else
6501 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6502 if (clock->p2 == 4)
6503 dpll |= PLL_P2_DIVIDE_BY_4;
6504 }
6505
d0737e1d 6506 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
4a33e48d
DV		 6507 dpll |= DPLL_DVO_2X_MODE;
6508
d0737e1d 6509 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 6510 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6511 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6512 else
6513 dpll |= PLL_REF_INPUT_DREFCLK;
6514
6515 dpll |= DPLL_VCO_ENABLE;
190f68c5 6516 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 6517}
6518
8a654f3b 6519static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 6520{
6521 struct drm_device *dev = intel_crtc->base.dev;
6522 struct drm_i915_private *dev_priv = dev->dev_private;
6523 enum pipe pipe = intel_crtc->pipe;
6e3c9717 6524 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8a654f3b 6525 struct drm_display_mode *adjusted_mode =
6e3c9717 6526 &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 6527 uint32_t crtc_vtotal, crtc_vblank_end;
6528 int vsyncshift = 0;
4d8a62ea
DV		 6529
6530 /* We need to be careful not to changed the adjusted mode, for otherwise
6531 * the hw state checker will get angry at the mismatch. */
6532 crtc_vtotal = adjusted_mode->crtc_vtotal;
6533 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 6534
609aeaca 6535 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 6536 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 6537 crtc_vtotal -= 1;
6538 crtc_vblank_end -= 1;
609aeaca 6539
409ee761 6540 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 6541 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6542 else
6543 vsyncshift = adjusted_mode->crtc_hsync_start -
6544 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 6545 if (vsyncshift < 0)
6546 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 6547 }
6548
6549 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 6550 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 6551
fe2b8f9d 6552 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 6553 (adjusted_mode->crtc_hdisplay - 1) |
6554 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 6555 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 6556 (adjusted_mode->crtc_hblank_start - 1) |
6557 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 6558 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 6559 (adjusted_mode->crtc_hsync_start - 1) |
6560 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6561
fe2b8f9d 6562 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 6563 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 6564 ((crtc_vtotal - 1) << 16));
fe2b8f9d 6565 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 6566 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 6567 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 6568 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 6569 (adjusted_mode->crtc_vsync_start - 1) |
6570 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6571
b5e508d4
PZ		 6572 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6573 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6574 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6575 * bits. */
6576 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6577 (pipe == PIPE_B || pipe == PIPE_C))
6578 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6579
b0e77b9c
PZ		 6580 /* pipesrc controls the size that is scaled from, which should
6581 * always be the user's requested size.
6582 */
6583 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 6584 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6585 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 6586}
6587
1bd1bd80 6588static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 6589 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 6590{
6591 struct drm_device *dev = crtc->base.dev;
6592 struct drm_i915_private *dev_priv = dev->dev_private;
6593 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6594 uint32_t tmp;
6595
6596 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 6597 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6598 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 6599 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 6600 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6601 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 6602 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 6603 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6604 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 6605
6606 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 6607 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6608 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 6609 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 6610 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6611 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 6612 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 6613 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6614 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 6615
6616 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 6617 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6618 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6619 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 6620 }
6621
6622 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 6623 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6624 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6625
2d112de7
ACO		 6626 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6627 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 6628}
6629
f6a83288 6630void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 6631 struct intel_crtc_state *pipe_config)
babea61d 6632{
2d112de7
ACO		 6633 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6634 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6635 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6636 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 6637
2d112de7
ACO		 6638 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6639 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6640 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6641 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 6642
2d112de7 6643 mode->flags = pipe_config->base.adjusted_mode.flags;
babea61d 6644
2d112de7
ACO		 6645 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6646 mode->flags |= pipe_config->base.adjusted_mode.flags;
babea61d
JB		 6647}
6648
84b046f3
DV		 6649static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6650{
6651 struct drm_device *dev = intel_crtc->base.dev;
6652 struct drm_i915_private *dev_priv = dev->dev_private;
6653 uint32_t pipeconf;
6654
9f11a9e4 6655 pipeconf = 0;
84b046f3 6656
b6b5d049
VS		 6657 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6658 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6659 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 6660
6e3c9717 6661 if (intel_crtc->config->double_wide)
cf532bb2 6662 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 6663
ff9ce46e
DV		 6664 /* only g4x and later have fancy bpc/dither controls */
6665 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 6666 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 6667 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 6668 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 6669 PIPECONF_DITHER_TYPE_SP;
84b046f3 6670
6e3c9717 6671 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 6672 case 18:
6673 pipeconf |= PIPECONF_6BPC;
6674 break;
6675 case 24:
6676 pipeconf |= PIPECONF_8BPC;
6677 break;
6678 case 30:
6679 pipeconf |= PIPECONF_10BPC;
6680 break;
6681 default:
6682 /* Case prevented by intel_choose_pipe_bpp_dither. */
6683 BUG();
84b046f3
DV		 6684 }
6685 }
6686
6687 if (HAS_PIPE_CXSR(dev)) {
6688 if (intel_crtc->lowfreq_avail) {
6689 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6690 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6691 } else {
6692 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 6693 }
6694 }
6695
6e3c9717 6696 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 6697 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 6698 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 6699 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6700 else
6701 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6702 } else
84b046f3
DV		 6703 pipeconf |= PIPECONF_PROGRESSIVE;
6704
6e3c9717 6705 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 6706 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 6707
84b046f3
DV		 6708 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6709 POSTING_READ(PIPECONF(intel_crtc->pipe));
6710}
6711
190f68c5
ACO		 6712static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
6713 struct intel_crtc_state *crtc_state)
79e53945 6714{
c7653199 6715 struct drm_device *dev = crtc->base.dev;
79e53945 6716 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 6717 int refclk, num_connectors = 0;
652c393a 6718 intel_clock_t clock, reduced_clock;
a16af721 6719 bool ok, has_reduced_clock = false;
e9fd1c02 6720 bool is_lvds = false, is_dsi = false;
5eddb70b 6721 struct intel_encoder *encoder;
d4906093 6722 const intel_limit_t *limit;
79e53945 6723
d0737e1d
ACO		 6724 for_each_intel_encoder(dev, encoder) {
6725 if (encoder->new_crtc != crtc)
6726 continue;
6727
5eddb70b 6728 switch (encoder->type) {
79e53945
JB		 6729 case INTEL_OUTPUT_LVDS:
6730 is_lvds = true;
6731 break;
e9fd1c02
JN		 6732 case INTEL_OUTPUT_DSI:
6733 is_dsi = true;
6734 break;
6847d71b
PZ		 6735 default:
6736 break;
79e53945 6737 }
43565a06 6738
c751ce4f 6739 num_connectors++;
79e53945
JB		 6740 }
6741
f2335330 6742 if (is_dsi)
5b18e57c 6743 return 0;
f2335330 6744
190f68c5 6745 if (!crtc_state->clock_set) {
409ee761 6746 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 6747
e9fd1c02
JN		 6748 /*
6749 * Returns a set of divisors for the desired target clock with
6750 * the given refclk, or FALSE. The returned values represent
6751 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6752 * 2) / p1 / p2.
6753 */
409ee761 6754 limit = intel_limit(crtc, refclk);
c7653199 6755 ok = dev_priv->display.find_dpll(limit, crtc,
190f68c5 6756 crtc_state->port_clock,
e9fd1c02 6757 refclk, NULL, &clock);
f2335330 6758 if (!ok) {
e9fd1c02
JN		 6759 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6760 return -EINVAL;
6761 }
79e53945 6762
f2335330
JN		 6763 if (is_lvds && dev_priv->lvds_downclock_avail) {
6764 /*
6765 * Ensure we match the reduced clock's P to the target
6766 * clock. If the clocks don't match, we can't switch
6767 * the display clock by using the FP0/FP1. In such case
6768 * we will disable the LVDS downclock feature.
6769 */
6770 has_reduced_clock =
c7653199 6771 dev_priv->display.find_dpll(limit, crtc,
f2335330
JN		 6772 dev_priv->lvds_downclock,
6773 refclk, &clock,
6774 &reduced_clock);
6775 }
6776 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 6777 crtc_state->dpll.n = clock.n;
6778 crtc_state->dpll.m1 = clock.m1;
6779 crtc_state->dpll.m2 = clock.m2;
6780 crtc_state->dpll.p1 = clock.p1;
6781 crtc_state->dpll.p2 = clock.p2;
f47709a9 6782 }
7026d4ac 6783
e9fd1c02 6784 if (IS_GEN2(dev)) {
190f68c5 6785 i8xx_update_pll(crtc, crtc_state,
2a8f64ca
VP		 6786 has_reduced_clock ? &reduced_clock : NULL,
6787 num_connectors);
9d556c99 6788 } else if (IS_CHERRYVIEW(dev)) {
190f68c5 6789 chv_update_pll(crtc, crtc_state);
e9fd1c02 6790 } else if (IS_VALLEYVIEW(dev)) {
190f68c5 6791 vlv_update_pll(crtc, crtc_state);
e9fd1c02 6792 } else {
190f68c5 6793 i9xx_update_pll(crtc, crtc_state,
eb1cbe48 6794 has_reduced_clock ? &reduced_clock : NULL,
eba905b2 6795 num_connectors);
e9fd1c02 6796 }
79e53945 6797
c8f7a0db 6798 return 0;
f564048e
EA		 6799}
6800
2fa2fe9a 6801static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 6802 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 6803{
6804 struct drm_device *dev = crtc->base.dev;
6805 struct drm_i915_private *dev_priv = dev->dev_private;
6806 uint32_t tmp;
6807
dc9e7dec
VS		 6808 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6809 return;
6810
2fa2fe9a 6811 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 6812 if (!(tmp & PFIT_ENABLE))
6813 return;
2fa2fe9a 6814
06922821 6815 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 6816 if (INTEL_INFO(dev)->gen < 4) {
6817 if (crtc->pipe != PIPE_B)
6818 return;
2fa2fe9a
DV		 6819 } else {
6820 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6821 return;
6822 }
6823
06922821 6824 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 6825 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6826 if (INTEL_INFO(dev)->gen < 5)
6827 pipe_config->gmch_pfit.lvds_border_bits =
6828 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6829}
6830
acbec814 6831static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 6832 struct intel_crtc_state *pipe_config)
acbec814
JB		 6833{
6834 struct drm_device *dev = crtc->base.dev;
6835 struct drm_i915_private *dev_priv = dev->dev_private;
6836 int pipe = pipe_config->cpu_transcoder;
6837 intel_clock_t clock;
6838 u32 mdiv;
662c6ecb 6839 int refclk = 100000;
acbec814 6840
f573de5a
SK		 6841 /* In case of MIPI DPLL will not even be used */
6842 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6843 return;
6844
acbec814 6845 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 6846 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
acbec814
JB		 6847 mutex_unlock(&dev_priv->dpio_lock);
6848
6849 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6850 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6851 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6852 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6853 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6854
f646628b 6855 vlv_clock(refclk, &clock);
acbec814 6856
f646628b
VS		 6857 /* clock.dot is the fast clock */
6858 pipe_config->port_clock = clock.dot / 5;
acbec814
JB		 6859}
6860
5724dbd1
DL		 6861static void
6862i9xx_get_initial_plane_config(struct intel_crtc *crtc,
6863 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 6864{
6865 struct drm_device *dev = crtc->base.dev;
6866 struct drm_i915_private *dev_priv = dev->dev_private;
6867 u32 val, base, offset;
6868 int pipe = crtc->pipe, plane = crtc->plane;
6869 int fourcc, pixel_format;
6761dd31 6870 unsigned int aligned_height;
b113d5ee 6871 struct drm_framebuffer *fb;
1b842c89 6872 struct intel_framebuffer *intel_fb;
1ad292b5 6873
42a7b088
DL		 6874 val = I915_READ(DSPCNTR(plane));
6875 if (!(val & DISPLAY_PLANE_ENABLE))
6876 return;
6877
d9806c9f 6878 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 6879 if (!intel_fb) {
1ad292b5
JB		 6880 DRM_DEBUG_KMS("failed to alloc fb\n");
6881 return;
6882 }
6883
1b842c89
DL		 6884 fb = &intel_fb->base;
6885
18c5247e
DV		 6886 if (INTEL_INFO(dev)->gen >= 4) {
6887 if (val & DISPPLANE_TILED) {
49af449b 6888 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 6889 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
6890 }
6891 }
1ad292b5
JB		 6892
6893 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 6894 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 6895 fb->pixel_format = fourcc;
6896 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 6897
6898 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 6899 if (plane_config->tiling)
1ad292b5
JB		 6900 offset = I915_READ(DSPTILEOFF(plane));
6901 else
6902 offset = I915_READ(DSPLINOFF(plane));
6903 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6904 } else {
6905 base = I915_READ(DSPADDR(plane));
6906 }
6907 plane_config->base = base;
6908
6909 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 6910 fb->width = ((val >> 16) & 0xfff) + 1;
6911 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 6912
6913 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 6914 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 6915
b113d5ee 6916 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 6917 fb->pixel_format,
6918 fb->modifier[0]);
1ad292b5 6919
f37b5c2b 6920 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 6921
2844a921
DL		 6922 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6923 pipe_name(pipe), plane, fb->width, fb->height,
6924 fb->bits_per_pixel, base, fb->pitches[0],
6925 plane_config->size);
1ad292b5 6926
2d14030b 6927 plane_config->fb = intel_fb;
1ad292b5
JB		 6928}
6929
70b23a98 6930static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 6931 struct intel_crtc_state *pipe_config)
70b23a98
VS		 6932{
6933 struct drm_device *dev = crtc->base.dev;
6934 struct drm_i915_private *dev_priv = dev->dev_private;
6935 int pipe = pipe_config->cpu_transcoder;
6936 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6937 intel_clock_t clock;
6938 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6939 int refclk = 100000;
6940
6941 mutex_lock(&dev_priv->dpio_lock);
6942 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6943 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6944 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6945 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6946 mutex_unlock(&dev_priv->dpio_lock);
6947
6948 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6949 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6950 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6951 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6952 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6953
6954 chv_clock(refclk, &clock);
6955
6956 /* clock.dot is the fast clock */
6957 pipe_config->port_clock = clock.dot / 5;
6958}
6959
0e8ffe1b 6960static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 6961 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 6962{
6963 struct drm_device *dev = crtc->base.dev;
6964 struct drm_i915_private *dev_priv = dev->dev_private;
6965 uint32_t tmp;
6966
f458ebbc
DV		 6967 if (!intel_display_power_is_enabled(dev_priv,
6968 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 6969 return false;
6970
e143a21c 6971 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 6972 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 6973
0e8ffe1b
DV		 6974 tmp = I915_READ(PIPECONF(crtc->pipe));
6975 if (!(tmp & PIPECONF_ENABLE))
6976 return false;
6977
42571aef
VS		 6978 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6979 switch (tmp & PIPECONF_BPC_MASK) {
6980 case PIPECONF_6BPC:
6981 pipe_config->pipe_bpp = 18;
6982 break;
6983 case PIPECONF_8BPC:
6984 pipe_config->pipe_bpp = 24;
6985 break;
6986 case PIPECONF_10BPC:
6987 pipe_config->pipe_bpp = 30;
6988 break;
6989 default:
6990 break;
6991 }
6992 }
6993
b5a9fa09
DV		 6994 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6995 pipe_config->limited_color_range = true;
6996
282740f7
VS		 6997 if (INTEL_INFO(dev)->gen < 4)
6998 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6999
1bd1bd80
DV		 7000 intel_get_pipe_timings(crtc, pipe_config);
7001
2fa2fe9a
DV		 7002 i9xx_get_pfit_config(crtc, pipe_config);
7003
6c49f241
DV		 7004 if (INTEL_INFO(dev)->gen >= 4) {
7005 tmp = I915_READ(DPLL_MD(crtc->pipe));
7006 pipe_config->pixel_multiplier =
7007 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7008 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 7009 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 7010 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7011 tmp = I915_READ(DPLL(crtc->pipe));
7012 pipe_config->pixel_multiplier =
7013 ((tmp & SDVO_MULTIPLIER_MASK)
7014 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7015 } else {
7016 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7017 * port and will be fixed up in the encoder->get_config
7018 * function. */
7019 pipe_config->pixel_multiplier = 1;
7020 }
8bcc2795
DV		 7021 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7022 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 7023 /*
7024 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7025 * on 830. Filter it out here so that we don't
7026 * report errors due to that.
7027 */
7028 if (IS_I830(dev))
7029 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7030
8bcc2795
DV		 7031 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7032 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 7033 } else {
7034 /* Mask out read-only status bits. */
7035 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7036 DPLL_PORTC_READY_MASK |
7037 DPLL_PORTB_READY_MASK);
8bcc2795 7038 }
6c49f241 7039
70b23a98
VS		 7040 if (IS_CHERRYVIEW(dev))
7041 chv_crtc_clock_get(crtc, pipe_config);
7042 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 7043 vlv_crtc_clock_get(crtc, pipe_config);
7044 else
7045 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 7046
0e8ffe1b
DV		 7047 return true;
7048}
7049
dde86e2d 7050static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 7051{
7052 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 7053 struct intel_encoder *encoder;
74cfd7ac 7054 u32 val, final;
13d83a67 7055 bool has_lvds = false;
199e5d79 7056 bool has_cpu_edp = false;
199e5d79 7057 bool has_panel = false;
99eb6a01
KP		 7058 bool has_ck505 = false;
7059 bool can_ssc = false;
13d83a67
JB		 7060
7061 /* We need to take the global config into account */
b2784e15 7062 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 7063 switch (encoder->type) {
7064 case INTEL_OUTPUT_LVDS:
7065 has_panel = true;
7066 has_lvds = true;
7067 break;
7068 case INTEL_OUTPUT_EDP:
7069 has_panel = true;
2de6905f 7070 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 7071 has_cpu_edp = true;
7072 break;
6847d71b
PZ		 7073 default:
7074 break;
13d83a67
JB		 7075 }
7076 }
7077
99eb6a01 7078 if (HAS_PCH_IBX(dev)) {
41aa3448 7079 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 7080 can_ssc = has_ck505;
7081 } else {
7082 has_ck505 = false;
7083 can_ssc = true;
7084 }
7085
2de6905f
ID		 7086 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7087 has_panel, has_lvds, has_ck505);
13d83a67
JB		 7088
7089 /* Ironlake: try to setup display ref clock before DPLL
7090 * enabling. This is only under driver's control after
7091 * PCH B stepping, previous chipset stepping should be
7092 * ignoring this setting.
7093 */
74cfd7ac
CW		 7094 val = I915_READ(PCH_DREF_CONTROL);
7095
7096 /* As we must carefully and slowly disable/enable each source in turn,
7097 * compute the final state we want first and check if we need to
7098 * make any changes at all.
7099 */
7100 final = val;
7101 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7102 if (has_ck505)
7103 final |= DREF_NONSPREAD_CK505_ENABLE;
7104 else
7105 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7106
7107 final &= ~DREF_SSC_SOURCE_MASK;
7108 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7109 final &= ~DREF_SSC1_ENABLE;
7110
7111 if (has_panel) {
7112 final |= DREF_SSC_SOURCE_ENABLE;
7113
7114 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7115 final |= DREF_SSC1_ENABLE;
7116
7117 if (has_cpu_edp) {
7118 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7119 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7120 else
7121 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7122 } else
7123 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7124 } else {
7125 final |= DREF_SSC_SOURCE_DISABLE;
7126 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7127 }
7128
7129 if (final == val)
7130 return;
7131
13d83a67 7132 /* Always enable nonspread source */
74cfd7ac 7133 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 7134
99eb6a01 7135 if (has_ck505)
74cfd7ac 7136 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 7137 else
74cfd7ac 7138 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 7139
199e5d79 7140 if (has_panel) {
74cfd7ac
CW		 7141 val &= ~DREF_SSC_SOURCE_MASK;
7142 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 7143
199e5d79 7144 /* SSC must be turned on before enabling the CPU output */
99eb6a01 7145 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 7146 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 7147 val |= DREF_SSC1_ENABLE;
e77166b5 7148 } else
74cfd7ac 7149 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 7150
7151 /* Get SSC going before enabling the outputs */
74cfd7ac 7152 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7153 POSTING_READ(PCH_DREF_CONTROL);
7154 udelay(200);
7155
74cfd7ac 7156 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 7157
7158 /* Enable CPU source on CPU attached eDP */
199e5d79 7159 if (has_cpu_edp) {
99eb6a01 7160 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 7161 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 7162 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 7163 } else
74cfd7ac 7164 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 7165 } else
74cfd7ac 7166 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 7167
74cfd7ac 7168 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7169 POSTING_READ(PCH_DREF_CONTROL);
7170 udelay(200);
7171 } else {
7172 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7173
74cfd7ac 7174 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 7175
7176 /* Turn off CPU output */
74cfd7ac 7177 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 7178
74cfd7ac 7179 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7180 POSTING_READ(PCH_DREF_CONTROL);
7181 udelay(200);
7182
7183 /* Turn off the SSC source */
74cfd7ac
CW		 7184 val &= ~DREF_SSC_SOURCE_MASK;
7185 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 7186
7187 /* Turn off SSC1 */
74cfd7ac 7188 val &= ~DREF_SSC1_ENABLE;
199e5d79 7189
74cfd7ac 7190 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 7191 POSTING_READ(PCH_DREF_CONTROL);
7192 udelay(200);
7193 }
74cfd7ac
CW		 7194
7195 BUG_ON(val != final);
13d83a67
JB		 7196}
7197
f31f2d55 7198static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 7199{
f31f2d55 7200 uint32_t tmp;
dde86e2d 7201
0ff066a9
PZ		 7202 tmp = I915_READ(SOUTH_CHICKEN2);
7203 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7204 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 7205
0ff066a9
PZ		 7206 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7207 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7208 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 7209
0ff066a9
PZ		 7210 tmp = I915_READ(SOUTH_CHICKEN2);
7211 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7212 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 7213
0ff066a9
PZ		 7214 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7215 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7216 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 7217}
7218
7219/* WaMPhyProgramming:hsw */
7220static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7221{
7222 uint32_t tmp;
dde86e2d
PZ		 7223
7224 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7225 tmp &= ~(0xFF << 24);
7226 tmp |= (0x12 << 24);
7227 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7228
dde86e2d
PZ		 7229 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7230 tmp |= (1 << 11);
7231 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7232
7233 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7234 tmp |= (1 << 11);
7235 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7236
dde86e2d
PZ		 7237 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7238 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7239 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7240
7241 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7242 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7243 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7244
0ff066a9
PZ		 7245 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7246 tmp &= ~(7 << 13);
7247 tmp |= (5 << 13);
7248 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 7249
0ff066a9
PZ		 7250 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7251 tmp &= ~(7 << 13);
7252 tmp |= (5 << 13);
7253 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 7254
7255 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7256 tmp &= ~0xFF;
7257 tmp |= 0x1C;
7258 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7259
7260 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7261 tmp &= ~0xFF;
7262 tmp |= 0x1C;
7263 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7264
7265 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7266 tmp &= ~(0xFF << 16);
7267 tmp |= (0x1C << 16);
7268 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7269
7270 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7271 tmp &= ~(0xFF << 16);
7272 tmp |= (0x1C << 16);
7273 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7274
0ff066a9
PZ		 7275 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7276 tmp |= (1 << 27);
7277 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 7278
0ff066a9
PZ		 7279 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7280 tmp |= (1 << 27);
7281 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 7282
0ff066a9
PZ		 7283 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7284 tmp &= ~(0xF << 28);
7285 tmp |= (4 << 28);
7286 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 7287
0ff066a9
PZ		 7288 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7289 tmp &= ~(0xF << 28);
7290 tmp |= (4 << 28);
7291 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 7292}
7293
2fa86a1f
PZ		 7294/* Implements 3 different sequences from BSpec chapter "Display iCLK
7295 * Programming" based on the parameters passed:
7296 * - Sequence to enable CLKOUT_DP
7297 * - Sequence to enable CLKOUT_DP without spread
7298 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7299 */
7300static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7301 bool with_fdi)
f31f2d55
PZ		 7302{
7303 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 7304 uint32_t reg, tmp;
7305
7306 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7307 with_spread = true;
7308 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7309 with_fdi, "LP PCH doesn't have FDI\n"))
7310 with_fdi = false;
f31f2d55
PZ		 7311
7312 mutex_lock(&dev_priv->dpio_lock);
7313
7314 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7315 tmp &= ~SBI_SSCCTL_DISABLE;
7316 tmp |= SBI_SSCCTL_PATHALT;
7317 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7318
7319 udelay(24);
7320
2fa86a1f
PZ		 7321 if (with_spread) {
7322 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7323 tmp &= ~SBI_SSCCTL_PATHALT;
7324 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 7325
2fa86a1f
PZ		 7326 if (with_fdi) {
7327 lpt_reset_fdi_mphy(dev_priv);
7328 lpt_program_fdi_mphy(dev_priv);
7329 }
7330 }
dde86e2d 7331
2fa86a1f
PZ		 7332 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7333 SBI_GEN0 : SBI_DBUFF0;
7334 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7335 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7336 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 7337
7338 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 7339}
7340
47701c3b
PZ		 7341/* Sequence to disable CLKOUT_DP */
7342static void lpt_disable_clkout_dp(struct drm_device *dev)
7343{
7344 struct drm_i915_private *dev_priv = dev->dev_private;
7345 uint32_t reg, tmp;
7346
7347 mutex_lock(&dev_priv->dpio_lock);
7348
7349 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7350 SBI_GEN0 : SBI_DBUFF0;
7351 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7352 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7353 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7354
7355 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7356 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7357 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7358 tmp |= SBI_SSCCTL_PATHALT;
7359 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7360 udelay(32);
7361 }
7362 tmp |= SBI_SSCCTL_DISABLE;
7363 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7364 }
7365
7366 mutex_unlock(&dev_priv->dpio_lock);
7367}
7368
bf8fa3d3
PZ		 7369static void lpt_init_pch_refclk(struct drm_device *dev)
7370{
bf8fa3d3
PZ		 7371 struct intel_encoder *encoder;
7372 bool has_vga = false;
7373
b2784e15 7374 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 7375 switch (encoder->type) {
7376 case INTEL_OUTPUT_ANALOG:
7377 has_vga = true;
7378 break;
6847d71b
PZ		 7379 default:
7380 break;
bf8fa3d3
PZ		 7381 }
7382 }
7383
47701c3b
PZ		 7384 if (has_vga)
7385 lpt_enable_clkout_dp(dev, true, true);
7386 else
7387 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 7388}
7389
dde86e2d
PZ		 7390/*
7391 * Initialize reference clocks when the driver loads
7392 */
7393void intel_init_pch_refclk(struct drm_device *dev)
7394{
7395 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7396 ironlake_init_pch_refclk(dev);
7397 else if (HAS_PCH_LPT(dev))
7398 lpt_init_pch_refclk(dev);
7399}
7400
d9d444cb
JB		 7401static int ironlake_get_refclk(struct drm_crtc *crtc)
7402{
7403 struct drm_device *dev = crtc->dev;
7404 struct drm_i915_private *dev_priv = dev->dev_private;
7405 struct intel_encoder *encoder;
d9d444cb
JB		 7406 int num_connectors = 0;
7407 bool is_lvds = false;
7408
d0737e1d
ACO		 7409 for_each_intel_encoder(dev, encoder) {
7410 if (encoder->new_crtc != to_intel_crtc(crtc))
7411 continue;
7412
d9d444cb
JB		 7413 switch (encoder->type) {
7414 case INTEL_OUTPUT_LVDS:
7415 is_lvds = true;
7416 break;
6847d71b
PZ		 7417 default:
7418 break;
d9d444cb
JB		 7419 }
7420 num_connectors++;
7421 }
7422
7423 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 7424 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 7425 dev_priv->vbt.lvds_ssc_freq);
e91e941b 7426 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 7427 }
7428
7429 return 120000;
7430}
7431
6ff93609 7432static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 7433{
c8203565 7434 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 7435 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7436 int pipe = intel_crtc->pipe;
c8203565
PZ		 7437 uint32_t val;
7438
78114071 7439 val = 0;
c8203565 7440
6e3c9717 7441 switch (intel_crtc->config->pipe_bpp) {
c8203565 7442 case 18:
dfd07d72 7443 val |= PIPECONF_6BPC;
c8203565
PZ		 7444 break;
7445 case 24:
dfd07d72 7446 val |= PIPECONF_8BPC;
c8203565
PZ		 7447 break;
7448 case 30:
dfd07d72 7449 val |= PIPECONF_10BPC;
c8203565
PZ		 7450 break;
7451 case 36:
dfd07d72 7452 val |= PIPECONF_12BPC;
c8203565
PZ		 7453 break;
7454 default:
cc769b62
PZ		 7455 /* Case prevented by intel_choose_pipe_bpp_dither. */
7456 BUG();
c8203565
PZ		 7457 }
7458
6e3c9717 7459 if (intel_crtc->config->dither)
c8203565
PZ		 7460 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7461
6e3c9717 7462 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 7463 val |= PIPECONF_INTERLACED_ILK;
7464 else
7465 val |= PIPECONF_PROGRESSIVE;
7466
6e3c9717 7467 if (intel_crtc->config->limited_color_range)
3685a8f3 7468 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 7469
c8203565
PZ		 7470 I915_WRITE(PIPECONF(pipe), val);
7471 POSTING_READ(PIPECONF(pipe));
7472}
7473
86d3efce
VS		 7474/*
7475 * Set up the pipe CSC unit.
7476 *
7477 * Currently only full range RGB to limited range RGB conversion
7478 * is supported, but eventually this should handle various
7479 * RGB<->YCbCr scenarios as well.
7480 */
50f3b016 7481static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 7482{
7483 struct drm_device *dev = crtc->dev;
7484 struct drm_i915_private *dev_priv = dev->dev_private;
7485 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7486 int pipe = intel_crtc->pipe;
7487 uint16_t coeff = 0x7800; /* 1.0 */
7488
7489 /*
7490 * TODO: Check what kind of values actually come out of the pipe
7491 * with these coeff/postoff values and adjust to get the best
7492 * accuracy. Perhaps we even need to take the bpc value into
7493 * consideration.
7494 */
7495
6e3c9717 7496 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 7497 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7498
7499 /*
7500 * GY/GU and RY/RU should be the other way around according
7501 * to BSpec, but reality doesn't agree. Just set them up in
7502 * a way that results in the correct picture.
7503 */
7504 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7505 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7506
7507 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7508 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7509
7510 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7511 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7512
7513 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7514 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7515 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7516
7517 if (INTEL_INFO(dev)->gen > 6) {
7518 uint16_t postoff = 0;
7519
6e3c9717 7520 if (intel_crtc->config->limited_color_range)
32cf0cb0 7521 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 7522
7523 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7524 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7525 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7526
7527 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7528 } else {
7529 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7530
6e3c9717 7531 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 7532 mode |= CSC_BLACK_SCREEN_OFFSET;
7533
7534 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7535 }
7536}
7537
6ff93609 7538static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 7539{
756f85cf
PZ		 7540 struct drm_device *dev = crtc->dev;
7541 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 7542 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 7543 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7544 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 7545 uint32_t val;
7546
3eff4faa 7547 val = 0;
ee2b0b38 7548
6e3c9717 7549 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 7550 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7551
6e3c9717 7552 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 7553 val |= PIPECONF_INTERLACED_ILK;
7554 else
7555 val |= PIPECONF_PROGRESSIVE;
7556
702e7a56
PZ		 7557 I915_WRITE(PIPECONF(cpu_transcoder), val);
7558 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 7559
7560 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7561 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 7562
3cdf122c 7563 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 7564 val = 0;
7565
6e3c9717 7566 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 7567 case 18:
7568 val |= PIPEMISC_DITHER_6_BPC;
7569 break;
7570 case 24:
7571 val |= PIPEMISC_DITHER_8_BPC;
7572 break;
7573 case 30:
7574 val |= PIPEMISC_DITHER_10_BPC;
7575 break;
7576 case 36:
7577 val |= PIPEMISC_DITHER_12_BPC;
7578 break;
7579 default:
7580 /* Case prevented by pipe_config_set_bpp. */
7581 BUG();
7582 }
7583
6e3c9717 7584 if (intel_crtc->config->dither)
756f85cf
PZ		 7585 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7586
7587 I915_WRITE(PIPEMISC(pipe), val);
7588 }
ee2b0b38
PZ		 7589}
7590
6591c6e4 7591static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 7592 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 7593 intel_clock_t *clock,
7594 bool *has_reduced_clock,
7595 intel_clock_t *reduced_clock)
7596{
7597 struct drm_device *dev = crtc->dev;
7598 struct drm_i915_private *dev_priv = dev->dev_private;
a919ff14 7599 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6591c6e4 7600 int refclk;
d4906093 7601 const intel_limit_t *limit;
a16af721 7602 bool ret, is_lvds = false;
79e53945 7603
d0737e1d 7604 is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
79e53945 7605
d9d444cb 7606 refclk = ironlake_get_refclk(crtc);
79e53945 7607
d4906093
ML		 7608 /*
7609 * Returns a set of divisors for the desired target clock with the given
7610 * refclk, or FALSE. The returned values represent the clock equation:
7611 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7612 */
409ee761 7613 limit = intel_limit(intel_crtc, refclk);
a919ff14 7614 ret = dev_priv->display.find_dpll(limit, intel_crtc,
190f68c5 7615 crtc_state->port_clock,
ee9300bb 7616 refclk, NULL, clock);
6591c6e4
PZ		 7617 if (!ret)
7618 return false;
cda4b7d3 7619
ddc9003c 7620 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 7621 /*
7622 * Ensure we match the reduced clock's P to the target clock.
7623 * If the clocks don't match, we can't switch the display clock
7624 * by using the FP0/FP1. In such case we will disable the LVDS
7625 * downclock feature.
7626 */
ee9300bb 7627 *has_reduced_clock =
a919ff14 7628 dev_priv->display.find_dpll(limit, intel_crtc,
ee9300bb
DV		 7629 dev_priv->lvds_downclock,
7630 refclk, clock,
7631 reduced_clock);
652c393a 7632 }
61e9653f 7633
6591c6e4
PZ		 7634 return true;
7635}
7636
d4b1931c
PZ		 7637int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7638{
7639 /*
7640 * Account for spread spectrum to avoid
7641 * oversubscribing the link. Max center spread
7642 * is 2.5%; use 5% for safety's sake.
7643 */
7644 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 7645 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 7646}
7647
7429e9d4 7648static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 7649{
7429e9d4 7650 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 7651}
7652
de13a2e3 7653static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 7654 struct intel_crtc_state *crtc_state,
7429e9d4 7655 u32 *fp,
9a7c7890 7656 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 7657{
de13a2e3 7658 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 7659 struct drm_device *dev = crtc->dev;
7660 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 7661 struct intel_encoder *intel_encoder;
7662 uint32_t dpll;
6cc5f341 7663 int factor, num_connectors = 0;
09ede541 7664 bool is_lvds = false, is_sdvo = false;
79e53945 7665
d0737e1d
ACO		 7666 for_each_intel_encoder(dev, intel_encoder) {
7667 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7668 continue;
7669
de13a2e3 7670 switch (intel_encoder->type) {
79e53945
JB		 7671 case INTEL_OUTPUT_LVDS:
7672 is_lvds = true;
7673 break;
7674 case INTEL_OUTPUT_SDVO:
7d57382e 7675 case INTEL_OUTPUT_HDMI:
79e53945 7676 is_sdvo = true;
79e53945 7677 break;
6847d71b
PZ		 7678 default:
7679 break;
79e53945 7680 }
43565a06 7681
c751ce4f 7682 num_connectors++;
79e53945 7683 }
79e53945 7684
c1858123 7685 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 7686 factor = 21;
7687 if (is_lvds) {
7688 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 7689 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 7690 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 7691 factor = 25;
190f68c5 7692 } else if (crtc_state->sdvo_tv_clock)
8febb297 7693 factor = 20;
c1858123 7694
190f68c5 7695 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 7696 *fp |= FP_CB_TUNE;
2c07245f 7697
9a7c7890
DV		 7698 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7699 *fp2 |= FP_CB_TUNE;
7700
5eddb70b 7701 dpll = 0;
2c07245f 7702
a07d6787
EA		 7703 if (is_lvds)
7704 dpll |= DPLLB_MODE_LVDS;
7705 else
7706 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 7707
190f68c5 7708 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 7709 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 7710
7711 if (is_sdvo)
4a33e48d 7712 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 7713 if (crtc_state->has_dp_encoder)
4a33e48d 7714 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 7715
a07d6787 7716 /* compute bitmask from p1 value */
190f68c5 7717 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 7718 /* also FPA1 */
190f68c5 7719 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 7720
190f68c5 7721 switch (crtc_state->dpll.p2) {
a07d6787
EA		 7722 case 5:
7723 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7724 break;
7725 case 7:
7726 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7727 break;
7728 case 10:
7729 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7730 break;
7731 case 14:
7732 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7733 break;
79e53945
JB		 7734 }
7735
b4c09f3b 7736 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 7737 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 7738 else
7739 dpll |= PLL_REF_INPUT_DREFCLK;
7740
959e16d6 7741 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 7742}
7743
190f68c5
ACO		 7744static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
7745 struct intel_crtc_state *crtc_state)
de13a2e3 7746{
c7653199 7747 struct drm_device *dev = crtc->base.dev;
de13a2e3 7748 intel_clock_t clock, reduced_clock;
cbbab5bd 7749 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 7750 bool ok, has_reduced_clock = false;
8b47047b 7751 bool is_lvds = false;
e2b78267 7752 struct intel_shared_dpll *pll;
de13a2e3 7753
409ee761 7754 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 7755
5dc5298b
PZ		 7756 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7757 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 7758
190f68c5 7759 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 7760 &has_reduced_clock, &reduced_clock);
190f68c5 7761 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 7762 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7763 return -EINVAL;
79e53945 7764 }
f47709a9 7765 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7766 if (!crtc_state->clock_set) {
7767 crtc_state->dpll.n = clock.n;
7768 crtc_state->dpll.m1 = clock.m1;
7769 crtc_state->dpll.m2 = clock.m2;
7770 crtc_state->dpll.p1 = clock.p1;
7771 crtc_state->dpll.p2 = clock.p2;
f47709a9 7772 }
79e53945 7773
5dc5298b 7774 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 7775 if (crtc_state->has_pch_encoder) {
7776 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 7777 if (has_reduced_clock)
7429e9d4 7778 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 7779
190f68c5 7780 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 7781 &fp, &reduced_clock,
7782 has_reduced_clock ? &fp2 : NULL);
7783
190f68c5
ACO		 7784 crtc_state->dpll_hw_state.dpll = dpll;
7785 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 7786 if (has_reduced_clock)
190f68c5 7787 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 7788 else
190f68c5 7789 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 7790
190f68c5 7791 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 7792 if (pll == NULL) {
84f44ce7 7793 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 7794 pipe_name(crtc->pipe));
4b645f14
JB		 7795 return -EINVAL;
7796 }
3fb37703 7797 }
79e53945 7798
d330a953 7799 if (is_lvds && has_reduced_clock && i915.powersave)
c7653199 7800 crtc->lowfreq_avail = true;
bcd644e0 7801 else
c7653199 7802 crtc->lowfreq_avail = false;
e2b78267 7803
c8f7a0db 7804 return 0;
79e53945
JB		 7805}
7806
eb14cb74
VS		 7807static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7808 struct intel_link_m_n *m_n)
7809{
7810 struct drm_device *dev = crtc->base.dev;
7811 struct drm_i915_private *dev_priv = dev->dev_private;
7812 enum pipe pipe = crtc->pipe;
7813
7814 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7815 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7816 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7817 & ~TU_SIZE_MASK;
7818 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7819 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7820 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7821}
7822
7823static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7824 enum transcoder transcoder,
b95af8be
VK		 7825 struct intel_link_m_n *m_n,
7826 struct intel_link_m_n *m2_n2)
72419203
DV		 7827{
7828 struct drm_device *dev = crtc->base.dev;
7829 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 7830 enum pipe pipe = crtc->pipe;
72419203 7831
eb14cb74
VS		 7832 if (INTEL_INFO(dev)->gen >= 5) {
7833 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7834 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7835 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7836 & ~TU_SIZE_MASK;
7837 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7838 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7839 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 7840 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7841 * gen < 8) and if DRRS is supported (to make sure the
7842 * registers are not unnecessarily read).
7843 */
7844 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 7845 crtc->config->has_drrs) {
b95af8be
VK		 7846 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7847 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7848 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7849 & ~TU_SIZE_MASK;
7850 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7851 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7852 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7853 }
eb14cb74
VS		 7854 } else {
7855 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7856 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7857 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7858 & ~TU_SIZE_MASK;
7859 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7860 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7861 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7862 }
7863}
7864
7865void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 7866 struct intel_crtc_state *pipe_config)
eb14cb74 7867{
681a8504 7868 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 7869 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7870 else
7871 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 7872 &pipe_config->dp_m_n,
7873 &pipe_config->dp_m2_n2);
eb14cb74 7874}
72419203 7875
eb14cb74 7876static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 7877 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 7878{
7879 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 7880 &pipe_config->fdi_m_n, NULL);
72419203
DV		 7881}
7882
bd2e244f 7883static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7884 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 7885{
7886 struct drm_device *dev = crtc->base.dev;
7887 struct drm_i915_private *dev_priv = dev->dev_private;
7888 uint32_t tmp;
7889
7890 tmp = I915_READ(PS_CTL(crtc->pipe));
7891
7892 if (tmp & PS_ENABLE) {
7893 pipe_config->pch_pfit.enabled = true;
7894 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
7895 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
7896 }
7897}
7898
5724dbd1
DL		 7899static void
7900skylake_get_initial_plane_config(struct intel_crtc *crtc,
7901 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 7902{
7903 struct drm_device *dev = crtc->base.dev;
7904 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 7905 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 7906 int pipe = crtc->pipe;
7907 int fourcc, pixel_format;
6761dd31 7908 unsigned int aligned_height;
bc8d7dff 7909 struct drm_framebuffer *fb;
1b842c89 7910 struct intel_framebuffer *intel_fb;
bc8d7dff 7911
d9806c9f 7912 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 7913 if (!intel_fb) {
bc8d7dff
DL		 7914 DRM_DEBUG_KMS("failed to alloc fb\n");
7915 return;
7916 }
7917
1b842c89
DL		 7918 fb = &intel_fb->base;
7919
bc8d7dff 7920 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 7921 if (!(val & PLANE_CTL_ENABLE))
7922 goto error;
7923
bc8d7dff
DL		 7924 pixel_format = val & PLANE_CTL_FORMAT_MASK;
7925 fourcc = skl_format_to_fourcc(pixel_format,
7926 val & PLANE_CTL_ORDER_RGBX,
7927 val & PLANE_CTL_ALPHA_MASK);
7928 fb->pixel_format = fourcc;
7929 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7930
40f46283
DL		 7931 tiling = val & PLANE_CTL_TILED_MASK;
7932 switch (tiling) {
7933 case PLANE_CTL_TILED_LINEAR:
7934 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
7935 break;
7936 case PLANE_CTL_TILED_X:
7937 plane_config->tiling = I915_TILING_X;
7938 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7939 break;
7940 case PLANE_CTL_TILED_Y:
7941 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
7942 break;
7943 case PLANE_CTL_TILED_YF:
7944 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
7945 break;
7946 default:
7947 MISSING_CASE(tiling);
7948 goto error;
7949 }
7950
bc8d7dff
DL		 7951 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
7952 plane_config->base = base;
7953
7954 offset = I915_READ(PLANE_OFFSET(pipe, 0));
7955
7956 val = I915_READ(PLANE_SIZE(pipe, 0));
7957 fb->height = ((val >> 16) & 0xfff) + 1;
7958 fb->width = ((val >> 0) & 0x1fff) + 1;
7959
7960 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 7961 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
7962 fb->pixel_format);
bc8d7dff
DL		 7963 fb->pitches[0] = (val & 0x3ff) * stride_mult;
7964
7965 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 7966 fb->pixel_format,
7967 fb->modifier[0]);
bc8d7dff 7968
f37b5c2b 7969 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 7970
7971 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7972 pipe_name(pipe), fb->width, fb->height,
7973 fb->bits_per_pixel, base, fb->pitches[0],
7974 plane_config->size);
7975
2d14030b 7976 plane_config->fb = intel_fb;
bc8d7dff
DL		 7977 return;
7978
7979error:
7980 kfree(fb);
7981}
7982
2fa2fe9a 7983static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7984 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 7985{
7986 struct drm_device *dev = crtc->base.dev;
7987 struct drm_i915_private *dev_priv = dev->dev_private;
7988 uint32_t tmp;
7989
7990 tmp = I915_READ(PF_CTL(crtc->pipe));
7991
7992 if (tmp & PF_ENABLE) {
fd4daa9c 7993 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 7994 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7995 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 7996
7997 /* We currently do not free assignements of panel fitters on
7998 * ivb/hsw (since we don't use the higher upscaling modes which
7999 * differentiates them) so just WARN about this case for now. */
8000 if (IS_GEN7(dev)) {
8001 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8002 PF_PIPE_SEL_IVB(crtc->pipe));
8003 }
2fa2fe9a 8004 }
79e53945
JB		 8005}
8006
5724dbd1
DL		 8007static void
8008ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8009 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 8010{
8011 struct drm_device *dev = crtc->base.dev;
8012 struct drm_i915_private *dev_priv = dev->dev_private;
8013 u32 val, base, offset;
aeee5a49 8014 int pipe = crtc->pipe;
4c6baa59 8015 int fourcc, pixel_format;
6761dd31 8016 unsigned int aligned_height;
b113d5ee 8017 struct drm_framebuffer *fb;
1b842c89 8018 struct intel_framebuffer *intel_fb;
4c6baa59 8019
42a7b088
DL		 8020 val = I915_READ(DSPCNTR(pipe));
8021 if (!(val & DISPLAY_PLANE_ENABLE))
8022 return;
8023
d9806c9f 8024 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8025 if (!intel_fb) {
4c6baa59
JB		 8026 DRM_DEBUG_KMS("failed to alloc fb\n");
8027 return;
8028 }
8029
1b842c89
DL		 8030 fb = &intel_fb->base;
8031
18c5247e
DV		 8032 if (INTEL_INFO(dev)->gen >= 4) {
8033 if (val & DISPPLANE_TILED) {
49af449b 8034 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 8035 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8036 }
8037 }
4c6baa59
JB		 8038
8039 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 8040 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 8041 fb->pixel_format = fourcc;
8042 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 8043
aeee5a49 8044 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 8045 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 8046 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 8047 } else {
49af449b 8048 if (plane_config->tiling)
aeee5a49 8049 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 8050 else
aeee5a49 8051 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 8052 }
8053 plane_config->base = base;
8054
8055 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 8056 fb->width = ((val >> 16) & 0xfff) + 1;
8057 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 8058
8059 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 8060 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 8061
b113d5ee 8062 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8063 fb->pixel_format,
8064 fb->modifier[0]);
4c6baa59 8065
f37b5c2b 8066 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 8067
2844a921
DL		 8068 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8069 pipe_name(pipe), fb->width, fb->height,
8070 fb->bits_per_pixel, base, fb->pitches[0],
8071 plane_config->size);
b113d5ee 8072
2d14030b 8073 plane_config->fb = intel_fb;
4c6baa59
JB		 8074}
8075
0e8ffe1b 8076static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8077 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8078{
8079 struct drm_device *dev = crtc->base.dev;
8080 struct drm_i915_private *dev_priv = dev->dev_private;
8081 uint32_t tmp;
8082
f458ebbc
DV		 8083 if (!intel_display_power_is_enabled(dev_priv,
8084 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 8085 return false;
8086
e143a21c 8087 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8088 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8089
0e8ffe1b
DV		 8090 tmp = I915_READ(PIPECONF(crtc->pipe));
8091 if (!(tmp & PIPECONF_ENABLE))
8092 return false;
8093
42571aef
VS		 8094 switch (tmp & PIPECONF_BPC_MASK) {
8095 case PIPECONF_6BPC:
8096 pipe_config->pipe_bpp = 18;
8097 break;
8098 case PIPECONF_8BPC:
8099 pipe_config->pipe_bpp = 24;
8100 break;
8101 case PIPECONF_10BPC:
8102 pipe_config->pipe_bpp = 30;
8103 break;
8104 case PIPECONF_12BPC:
8105 pipe_config->pipe_bpp = 36;
8106 break;
8107 default:
8108 break;
8109 }
8110
b5a9fa09
DV		 8111 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8112 pipe_config->limited_color_range = true;
8113
ab9412ba 8114 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 8115 struct intel_shared_dpll *pll;
8116
88adfff1
DV		 8117 pipe_config->has_pch_encoder = true;
8118
627eb5a3
DV		 8119 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8120 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8121 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 8122
8123 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 8124
c0d43d62 8125 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 8126 pipe_config->shared_dpll =
8127 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 8128 } else {
8129 tmp = I915_READ(PCH_DPLL_SEL);
8130 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8131 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8132 else
8133 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8134 }
66e985c0
DV		 8135
8136 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8137
8138 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8139 &pipe_config->dpll_hw_state));
c93f54cf
DV		 8140
8141 tmp = pipe_config->dpll_hw_state.dpll;
8142 pipe_config->pixel_multiplier =
8143 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8144 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 8145
8146 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 8147 } else {
8148 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 8149 }
8150
1bd1bd80
DV		 8151 intel_get_pipe_timings(crtc, pipe_config);
8152
2fa2fe9a
DV		 8153 ironlake_get_pfit_config(crtc, pipe_config);
8154
0e8ffe1b
DV		 8155 return true;
8156}
8157
be256dc7
PZ		 8158static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8159{
8160 struct drm_device *dev = dev_priv->dev;
be256dc7 8161 struct intel_crtc *crtc;
be256dc7 8162
d3fcc808 8163 for_each_intel_crtc(dev, crtc)
e2c719b7 8164 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 8165 pipe_name(crtc->pipe));
8166
e2c719b7
RC		 8167 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8168 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8169 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8170 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8171 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8172 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 8173 "CPU PWM1 enabled\n");
c5107b87 8174 if (IS_HASWELL(dev))
e2c719b7 8175 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 8176 "CPU PWM2 enabled\n");
e2c719b7 8177 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 8178 "PCH PWM1 enabled\n");
e2c719b7 8179 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 8180 "Utility pin enabled\n");
e2c719b7 8181 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 8182
9926ada1
PZ		 8183 /*
8184 * In theory we can still leave IRQs enabled, as long as only the HPD
8185 * interrupts remain enabled. We used to check for that, but since it's
8186 * gen-specific and since we only disable LCPLL after we fully disable
8187 * the interrupts, the check below should be enough.
8188 */
e2c719b7 8189 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 8190}
8191
9ccd5aeb
PZ		 8192static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8193{
8194 struct drm_device *dev = dev_priv->dev;
8195
8196 if (IS_HASWELL(dev))
8197 return I915_READ(D_COMP_HSW);
8198 else
8199 return I915_READ(D_COMP_BDW);
8200}
8201
3c4c9b81
PZ		 8202static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8203{
8204 struct drm_device *dev = dev_priv->dev;
8205
8206 if (IS_HASWELL(dev)) {
8207 mutex_lock(&dev_priv->rps.hw_lock);
8208 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8209 val))
f475dadf 8210 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 8211 mutex_unlock(&dev_priv->rps.hw_lock);
8212 } else {
9ccd5aeb
PZ		 8213 I915_WRITE(D_COMP_BDW, val);
8214 POSTING_READ(D_COMP_BDW);
3c4c9b81 8215 }
be256dc7
PZ		 8216}
8217
8218/*
8219 * This function implements pieces of two sequences from BSpec:
8220 * - Sequence for display software to disable LCPLL
8221 * - Sequence for display software to allow package C8+
8222 * The steps implemented here are just the steps that actually touch the LCPLL
8223 * register. Callers should take care of disabling all the display engine
8224 * functions, doing the mode unset, fixing interrupts, etc.
8225 */
6ff58d53
PZ		 8226static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8227 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 8228{
8229 uint32_t val;
8230
8231 assert_can_disable_lcpll(dev_priv);
8232
8233 val = I915_READ(LCPLL_CTL);
8234
8235 if (switch_to_fclk) {
8236 val |= LCPLL_CD_SOURCE_FCLK;
8237 I915_WRITE(LCPLL_CTL, val);
8238
8239 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
8240 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8241 DRM_ERROR("Switching to FCLK failed\n");
8242
8243 val = I915_READ(LCPLL_CTL);
8244 }
8245
8246 val |= LCPLL_PLL_DISABLE;
8247 I915_WRITE(LCPLL_CTL, val);
8248 POSTING_READ(LCPLL_CTL);
8249
8250 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
8251 DRM_ERROR("LCPLL still locked\n");
8252
9ccd5aeb 8253 val = hsw_read_dcomp(dev_priv);
be256dc7 8254 val |= D_COMP_COMP_DISABLE;
3c4c9b81 8255 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 8256 ndelay(100);
8257
9ccd5aeb
PZ		 8258 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8259 1))
be256dc7
PZ		 8260 DRM_ERROR("D_COMP RCOMP still in progress\n");
8261
8262 if (allow_power_down) {
8263 val = I915_READ(LCPLL_CTL);
8264 val |= LCPLL_POWER_DOWN_ALLOW;
8265 I915_WRITE(LCPLL_CTL, val);
8266 POSTING_READ(LCPLL_CTL);
8267 }
8268}
8269
8270/*
8271 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8272 * source.
8273 */
6ff58d53 8274static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 8275{
8276 uint32_t val;
8277
8278 val = I915_READ(LCPLL_CTL);
8279
8280 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8281 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8282 return;
8283
a8a8bd54
PZ		 8284 /*
8285 * Make sure we're not on PC8 state before disabling PC8, otherwise
8286 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 8287 */
59bad947 8288 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 8289
be256dc7
PZ		 8290 if (val & LCPLL_POWER_DOWN_ALLOW) {
8291 val &= ~LCPLL_POWER_DOWN_ALLOW;
8292 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 8293 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 8294 }
8295
9ccd5aeb 8296 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 8297 val |= D_COMP_COMP_FORCE;
8298 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 8299 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 8300
8301 val = I915_READ(LCPLL_CTL);
8302 val &= ~LCPLL_PLL_DISABLE;
8303 I915_WRITE(LCPLL_CTL, val);
8304
8305 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
8306 DRM_ERROR("LCPLL not locked yet\n");
8307
8308 if (val & LCPLL_CD_SOURCE_FCLK) {
8309 val = I915_READ(LCPLL_CTL);
8310 val &= ~LCPLL_CD_SOURCE_FCLK;
8311 I915_WRITE(LCPLL_CTL, val);
8312
8313 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
8314 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8315 DRM_ERROR("Switching back to LCPLL failed\n");
8316 }
215733fa 8317
59bad947 8318 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
be256dc7
PZ		 8319}
8320
765dab67
PZ		 8321/*
8322 * Package states C8 and deeper are really deep PC states that can only be
8323 * reached when all the devices on the system allow it, so even if the graphics
8324 * device allows PC8+, it doesn't mean the system will actually get to these
8325 * states. Our driver only allows PC8+ when going into runtime PM.
8326 *
8327 * The requirements for PC8+ are that all the outputs are disabled, the power
8328 * well is disabled and most interrupts are disabled, and these are also
8329 * requirements for runtime PM. When these conditions are met, we manually do
8330 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8331 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8332 * hang the machine.
8333 *
8334 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8335 * the state of some registers, so when we come back from PC8+ we need to
8336 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8337 * need to take care of the registers kept by RC6. Notice that this happens even
8338 * if we don't put the device in PCI D3 state (which is what currently happens
8339 * because of the runtime PM support).
8340 *
8341 * For more, read "Display Sequences for Package C8" on the hardware
8342 * documentation.
8343 */
a14cb6fc 8344void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 8345{
c67a470b
PZ		 8346 struct drm_device *dev = dev_priv->dev;
8347 uint32_t val;
8348
c67a470b
PZ		 8349 DRM_DEBUG_KMS("Enabling package C8+\n");
8350
c67a470b
PZ		 8351 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8352 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8353 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8354 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8355 }
8356
8357 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 8358 hsw_disable_lcpll(dev_priv, true, true);
8359}
8360
a14cb6fc 8361void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 8362{
8363 struct drm_device *dev = dev_priv->dev;
8364 uint32_t val;
8365
c67a470b
PZ		 8366 DRM_DEBUG_KMS("Disabling package C8+\n");
8367
8368 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 8369 lpt_init_pch_refclk(dev);
8370
8371 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8372 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8373 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8374 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8375 }
8376
8377 intel_prepare_ddi(dev);
c67a470b
PZ		 8378}
8379
190f68c5
ACO		 8380static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8381 struct intel_crtc_state *crtc_state)
09b4ddf9 8382{
190f68c5 8383 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 8384 return -EINVAL;
716c2e55 8385
c7653199 8386 crtc->lowfreq_avail = false;
644cef34 8387
c8f7a0db 8388 return 0;
79e53945
JB		 8389}
8390
96b7dfb7
S		 8391static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8392 enum port port,
5cec258b 8393 struct intel_crtc_state *pipe_config)
96b7dfb7 8394{
3148ade7 8395 u32 temp, dpll_ctl1;
96b7dfb7
S		 8396
8397 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8398 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
8399
8400 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 8401 case SKL_DPLL0:
8402 /*
8403 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8404 * of the shared DPLL framework and thus needs to be read out
8405 * separately
8406 */
8407 dpll_ctl1 = I915_READ(DPLL_CTRL1);
8408 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
8409 break;
96b7dfb7
S		 8410 case SKL_DPLL1:
8411 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8412 break;
8413 case SKL_DPLL2:
8414 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8415 break;
8416 case SKL_DPLL3:
8417 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8418 break;
96b7dfb7
S		 8419 }
8420}
8421
7d2c8175
DL		 8422static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8423 enum port port,
5cec258b 8424 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 8425{
8426 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8427
8428 switch (pipe_config->ddi_pll_sel) {
8429 case PORT_CLK_SEL_WRPLL1:
8430 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8431 break;
8432 case PORT_CLK_SEL_WRPLL2:
8433 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8434 break;
8435 }
8436}
8437
26804afd 8438static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 8439 struct intel_crtc_state *pipe_config)
26804afd
DV		 8440{
8441 struct drm_device *dev = crtc->base.dev;
8442 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 8443 struct intel_shared_dpll *pll;
26804afd
DV		 8444 enum port port;
8445 uint32_t tmp;
8446
8447 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8448
8449 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8450
96b7dfb7
S		 8451 if (IS_SKYLAKE(dev))
8452 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8453 else
8454 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 8455
d452c5b6
DV		 8456 if (pipe_config->shared_dpll >= 0) {
8457 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8458
8459 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8460 &pipe_config->dpll_hw_state));
8461 }
8462
26804afd
DV		 8463 /*
8464 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8465 * DDI E. So just check whether this pipe is wired to DDI E and whether
8466 * the PCH transcoder is on.
8467 */
ca370455
DL		 8468 if (INTEL_INFO(dev)->gen < 9 &&
8469 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 8470 pipe_config->has_pch_encoder = true;
8471
8472 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8473 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8474 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8475
8476 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8477 }
8478}
8479
0e8ffe1b 8480static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8481 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8482{
8483 struct drm_device *dev = crtc->base.dev;
8484 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 8485 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 8486 uint32_t tmp;
8487
f458ebbc 8488 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 8489 POWER_DOMAIN_PIPE(crtc->pipe)))
8490 return false;
8491
e143a21c 8492 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 8493 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8494
eccb140b
DV		 8495 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8496 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8497 enum pipe trans_edp_pipe;
8498 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8499 default:
8500 WARN(1, "unknown pipe linked to edp transcoder\n");
8501 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8502 case TRANS_DDI_EDP_INPUT_A_ON:
8503 trans_edp_pipe = PIPE_A;
8504 break;
8505 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8506 trans_edp_pipe = PIPE_B;
8507 break;
8508 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8509 trans_edp_pipe = PIPE_C;
8510 break;
8511 }
8512
8513 if (trans_edp_pipe == crtc->pipe)
8514 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8515 }
8516
f458ebbc 8517 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 8518 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 8519 return false;
8520
eccb140b 8521 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 8522 if (!(tmp & PIPECONF_ENABLE))
8523 return false;
8524
26804afd 8525 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 8526
1bd1bd80
DV		 8527 intel_get_pipe_timings(crtc, pipe_config);
8528
2fa2fe9a 8529 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
bd2e244f
JB		 8530 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8531 if (IS_SKYLAKE(dev))
8532 skylake_get_pfit_config(crtc, pipe_config);
8533 else
8534 ironlake_get_pfit_config(crtc, pipe_config);
8535 }
88adfff1 8536
e59150dc
JB		 8537 if (IS_HASWELL(dev))
8538 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8539 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 8540
ebb69c95
CT		 8541 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8542 pipe_config->pixel_multiplier =
8543 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8544 } else {
8545 pipe_config->pixel_multiplier = 1;
8546 }
6c49f241 8547
0e8ffe1b
DV		 8548 return true;
8549}
8550
560b85bb
CW		 8551static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8552{
8553 struct drm_device *dev = crtc->dev;
8554 struct drm_i915_private *dev_priv = dev->dev_private;
8555 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 8556 uint32_t cntl = 0, size = 0;
560b85bb 8557
dc41c154 8558 if (base) {
3dd512fb
MR		 8559 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
8560 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 8561 unsigned int stride = roundup_pow_of_two(width) * 4;
8562
8563 switch (stride) {
8564 default:
8565 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8566 width, stride);
8567 stride = 256;
8568 /* fallthrough */
8569 case 256:
8570 case 512:
8571 case 1024:
8572 case 2048:
8573 break;
4b0e333e
CW		 8574 }
8575
dc41c154
VS		 8576 cntl |= CURSOR_ENABLE |
8577 CURSOR_GAMMA_ENABLE |
8578 CURSOR_FORMAT_ARGB |
8579 CURSOR_STRIDE(stride);
8580
8581 size = (height << 12) | width;
4b0e333e 8582 }
560b85bb 8583
dc41c154
VS		 8584 if (intel_crtc->cursor_cntl != 0 &&
8585 (intel_crtc->cursor_base != base ||
8586 intel_crtc->cursor_size != size ||
8587 intel_crtc->cursor_cntl != cntl)) {
8588 /* On these chipsets we can only modify the base/size/stride
8589 * whilst the cursor is disabled.
8590 */
8591 I915_WRITE(_CURACNTR, 0);
4b0e333e 8592 POSTING_READ(_CURACNTR);
dc41c154 8593 intel_crtc->cursor_cntl = 0;
4b0e333e 8594 }
560b85bb 8595
99d1f387 8596 if (intel_crtc->cursor_base != base) {
9db4a9c7 8597 I915_WRITE(_CURABASE, base);
99d1f387
VS		 8598 intel_crtc->cursor_base = base;
8599 }
4726e0b0 8600
dc41c154
VS		 8601 if (intel_crtc->cursor_size != size) {
8602 I915_WRITE(CURSIZE, size);
8603 intel_crtc->cursor_size = size;
4b0e333e 8604 }
560b85bb 8605
4b0e333e 8606 if (intel_crtc->cursor_cntl != cntl) {
4b0e333e
CW		 8607 I915_WRITE(_CURACNTR, cntl);
8608 POSTING_READ(_CURACNTR);
4b0e333e 8609 intel_crtc->cursor_cntl = cntl;
560b85bb 8610 }
560b85bb
CW		 8611}
8612
560b85bb 8613static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 8614{
8615 struct drm_device *dev = crtc->dev;
8616 struct drm_i915_private *dev_priv = dev->dev_private;
8617 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8618 int pipe = intel_crtc->pipe;
4b0e333e
CW		 8619 uint32_t cntl;
8620
8621 cntl = 0;
8622 if (base) {
8623 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 8624 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 8625 case 64:
8626 cntl |= CURSOR_MODE_64_ARGB_AX;
8627 break;
8628 case 128:
8629 cntl |= CURSOR_MODE_128_ARGB_AX;
8630 break;
8631 case 256:
8632 cntl |= CURSOR_MODE_256_ARGB_AX;
8633 break;
8634 default:
3dd512fb 8635 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 8636 return;
65a21cd6 8637 }
4b0e333e 8638 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS		 8639
8640 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8641 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 8642 }
65a21cd6 8643
8e7d688b 8644 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 8645 cntl |= CURSOR_ROTATE_180;
8646
4b0e333e
CW		 8647 if (intel_crtc->cursor_cntl != cntl) {
8648 I915_WRITE(CURCNTR(pipe), cntl);
8649 POSTING_READ(CURCNTR(pipe));
8650 intel_crtc->cursor_cntl = cntl;
65a21cd6 8651 }
4b0e333e 8652
65a21cd6 8653 /* and commit changes on next vblank */
5efb3e28
VS		 8654 I915_WRITE(CURBASE(pipe), base);
8655 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 8656
8657 intel_crtc->cursor_base = base;
65a21cd6
JB		 8658}
8659
cda4b7d3 8660/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 8661static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8662 bool on)
cda4b7d3
CW		 8663{
8664 struct drm_device *dev = crtc->dev;
8665 struct drm_i915_private *dev_priv = dev->dev_private;
8666 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8667 int pipe = intel_crtc->pipe;
3d7d6510
MR		 8668 int x = crtc->cursor_x;
8669 int y = crtc->cursor_y;
d6e4db15 8670 u32 base = 0, pos = 0;
cda4b7d3 8671
d6e4db15 8672 if (on)
cda4b7d3 8673 base = intel_crtc->cursor_addr;
cda4b7d3 8674
6e3c9717 8675 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 8676 base = 0;
8677
6e3c9717 8678 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 8679 base = 0;
8680
8681 if (x < 0) {
3dd512fb 8682 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
cda4b7d3
CW		 8683 base = 0;
8684
8685 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8686 x = -x;
8687 }
8688 pos |= x << CURSOR_X_SHIFT;
8689
8690 if (y < 0) {
3dd512fb 8691 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
cda4b7d3
CW		 8692 base = 0;
8693
8694 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8695 y = -y;
8696 }
8697 pos |= y << CURSOR_Y_SHIFT;
8698
4b0e333e 8699 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 8700 return;
8701
5efb3e28
VS		 8702 I915_WRITE(CURPOS(pipe), pos);
8703
4398ad45
VS		 8704 /* ILK+ do this automagically */
8705 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 8706 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
3dd512fb
MR		 8707 base += (intel_crtc->base.cursor->state->crtc_h *
8708 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
4398ad45
VS		 8709 }
8710
8ac54669 8711 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 8712 i845_update_cursor(crtc, base);
8713 else
8714 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 8715}
8716
dc41c154
VS		 8717static bool cursor_size_ok(struct drm_device *dev,
8718 uint32_t width, uint32_t height)
8719{
8720 if (width == 0 || height == 0)
8721 return false;
8722
8723 /*
8724 * 845g/865g are special in that they are only limited by
8725 * the width of their cursors, the height is arbitrary up to
8726 * the precision of the register. Everything else requires
8727 * square cursors, limited to a few power-of-two sizes.
8728 */
8729 if (IS_845G(dev) || IS_I865G(dev)) {
8730 if ((width & 63) != 0)
8731 return false;
8732
8733 if (width > (IS_845G(dev) ? 64 : 512))
8734 return false;
8735
8736 if (height > 1023)
8737 return false;
8738 } else {
8739 switch (width | height) {
8740 case 256:
8741 case 128:
8742 if (IS_GEN2(dev))
8743 return false;
8744 case 64:
8745 break;
8746 default:
8747 return false;
8748 }
8749 }
8750
8751 return true;
8752}
8753
79e53945 8754static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 8755 u16 *blue, uint32_t start, uint32_t size)
79e53945 8756{
7203425a 8757 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 8758 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 8759
7203425a 8760 for (i = start; i < end; i++) {
79e53945
JB		 8761 intel_crtc->lut_r[i] = red[i] >> 8;
8762 intel_crtc->lut_g[i] = green[i] >> 8;
8763 intel_crtc->lut_b[i] = blue[i] >> 8;
8764 }
8765
8766 intel_crtc_load_lut(crtc);
8767}
8768
79e53945
JB		 8769/* VESA 640x480x72Hz mode to set on the pipe */
8770static struct drm_display_mode load_detect_mode = {
8771 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8772 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8773};
8774
a8bb6818
DV		 8775struct drm_framebuffer *
8776__intel_framebuffer_create(struct drm_device *dev,
8777 struct drm_mode_fb_cmd2 *mode_cmd,
8778 struct drm_i915_gem_object *obj)
d2dff872
CW		 8779{
8780 struct intel_framebuffer *intel_fb;
8781 int ret;
8782
8783 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8784 if (!intel_fb) {
6ccb81f2 8785 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 8786 return ERR_PTR(-ENOMEM);
8787 }
8788
8789 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 8790 if (ret)
8791 goto err;
d2dff872
CW		 8792
8793 return &intel_fb->base;
dd4916c5 8794err:
6ccb81f2 8795 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 8796 kfree(intel_fb);
8797
8798 return ERR_PTR(ret);
d2dff872
CW		 8799}
8800
b5ea642a 8801static struct drm_framebuffer *
a8bb6818
DV		 8802intel_framebuffer_create(struct drm_device *dev,
8803 struct drm_mode_fb_cmd2 *mode_cmd,
8804 struct drm_i915_gem_object *obj)
8805{
8806 struct drm_framebuffer *fb;
8807 int ret;
8808
8809 ret = i915_mutex_lock_interruptible(dev);
8810 if (ret)
8811 return ERR_PTR(ret);
8812 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8813 mutex_unlock(&dev->struct_mutex);
8814
8815 return fb;
8816}
8817
d2dff872
CW		 8818static u32
8819intel_framebuffer_pitch_for_width(int width, int bpp)
8820{
8821 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8822 return ALIGN(pitch, 64);
8823}
8824
8825static u32
8826intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8827{
8828 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 8829 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 8830}
8831
8832static struct drm_framebuffer *
8833intel_framebuffer_create_for_mode(struct drm_device *dev,
8834 struct drm_display_mode *mode,
8835 int depth, int bpp)
8836{
8837 struct drm_i915_gem_object *obj;
0fed39bd 8838 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 8839
8840 obj = i915_gem_alloc_object(dev,
8841 intel_framebuffer_size_for_mode(mode, bpp));
8842 if (obj == NULL)
8843 return ERR_PTR(-ENOMEM);
8844
8845 mode_cmd.width = mode->hdisplay;
8846 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 8847 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8848 bpp);
5ca0c34a 8849 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 8850
8851 return intel_framebuffer_create(dev, &mode_cmd, obj);
8852}
8853
8854static struct drm_framebuffer *
8855mode_fits_in_fbdev(struct drm_device *dev,
8856 struct drm_display_mode *mode)
8857{
4520f53a 8858#ifdef CONFIG_DRM_I915_FBDEV
d2dff872
CW		 8859 struct drm_i915_private *dev_priv = dev->dev_private;
8860 struct drm_i915_gem_object *obj;
8861 struct drm_framebuffer *fb;
8862
4c0e5528 8863 if (!dev_priv->fbdev)
d2dff872
CW		 8864 return NULL;
8865
4c0e5528 8866 if (!dev_priv->fbdev->fb)
d2dff872
CW		 8867 return NULL;
8868
4c0e5528
DV		 8869 obj = dev_priv->fbdev->fb->obj;
8870 BUG_ON(!obj);
8871
8bcd4553 8872 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 8873 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8874 fb->bits_per_pixel))
d2dff872
CW		 8875 return NULL;
8876
01f2c773 8877 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 8878 return NULL;
8879
8880 return fb;
4520f53a
DV		 8881#else
8882 return NULL;
8883#endif
d2dff872
CW		 8884}
8885
d2434ab7 8886bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 8887 struct drm_display_mode *mode,
51fd371b
RC		 8888 struct intel_load_detect_pipe *old,
8889 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 8890{
8891 struct intel_crtc *intel_crtc;
d2434ab7
DV		 8892 struct intel_encoder *intel_encoder =
8893 intel_attached_encoder(connector);
79e53945 8894 struct drm_crtc *possible_crtc;
4ef69c7a 8895 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 8896 struct drm_crtc *crtc = NULL;
8897 struct drm_device *dev = encoder->dev;
94352cf9 8898 struct drm_framebuffer *fb;
51fd371b
RC		 8899 struct drm_mode_config *config = &dev->mode_config;
8900 int ret, i = -1;
79e53945 8901
d2dff872 8902 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 8903 connector->base.id, connector->name,
8e329a03 8904 encoder->base.id, encoder->name);
d2dff872 8905
51fd371b
RC		 8906retry:
8907 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8908 if (ret)
8909 goto fail_unlock;
6e9f798d 8910
79e53945
JB		 8911 /*
8912 * Algorithm gets a little messy:
7a5e4805 8913 *
79e53945
JB		 8914 * - if the connector already has an assigned crtc, use it (but make
8915 * sure it's on first)
7a5e4805 8916 *
79e53945
JB		 8917 * - try to find the first unused crtc that can drive this connector,
8918 * and use that if we find one
79e53945
JB		 8919 */
8920
8921 /* See if we already have a CRTC for this connector */
8922 if (encoder->crtc) {
8923 crtc = encoder->crtc;
8261b191 8924
51fd371b 8925 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de
DV		 8926 if (ret)
8927 goto fail_unlock;
8928 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b
RC		 8929 if (ret)
8930 goto fail_unlock;
7b24056b 8931
24218aac 8932 old->dpms_mode = connector->dpms;
8261b191
CW		 8933 old->load_detect_temp = false;
8934
8935 /* Make sure the crtc and connector are running */
24218aac
DV		 8936 if (connector->dpms != DRM_MODE_DPMS_ON)
8937 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 8938
7173188d 8939 return true;
79e53945
JB		 8940 }
8941
8942 /* Find an unused one (if possible) */
70e1e0ec 8943 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 8944 i++;
8945 if (!(encoder->possible_crtcs & (1 << i)))
8946 continue;
83d65738 8947 if (possible_crtc->state->enable)
a459249c
VS		 8948 continue;
8949 /* This can occur when applying the pipe A quirk on resume. */
8950 if (to_intel_crtc(possible_crtc)->new_enabled)
8951 continue;
8952
8953 crtc = possible_crtc;
8954 break;
79e53945
JB		 8955 }
8956
8957 /*
8958 * If we didn't find an unused CRTC, don't use any.
8959 */
8960 if (!crtc) {
7173188d 8961 DRM_DEBUG_KMS("no pipe available for load-detect\n");
51fd371b 8962 goto fail_unlock;
79e53945
JB		 8963 }
8964
51fd371b
RC		 8965 ret = drm_modeset_lock(&crtc->mutex, ctx);
8966 if (ret)
4d02e2de
DV		 8967 goto fail_unlock;
8968 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8969 if (ret)
51fd371b 8970 goto fail_unlock;
fc303101
DV		 8971 intel_encoder->new_crtc = to_intel_crtc(crtc);
8972 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 8973
8974 intel_crtc = to_intel_crtc(crtc);
412b61d8 8975 intel_crtc->new_enabled = true;
6e3c9717 8976 intel_crtc->new_config = intel_crtc->config;
24218aac 8977 old->dpms_mode = connector->dpms;
8261b191 8978 old->load_detect_temp = true;
d2dff872 8979 old->release_fb = NULL;
79e53945 8980
6492711d
CW		 8981 if (!mode)
8982 mode = &load_detect_mode;
79e53945 8983
d2dff872
CW		 8984 /* We need a framebuffer large enough to accommodate all accesses
8985 * that the plane may generate whilst we perform load detection.
8986 * We can not rely on the fbcon either being present (we get called
8987 * during its initialisation to detect all boot displays, or it may
8988 * not even exist) or that it is large enough to satisfy the
8989 * requested mode.
8990 */
94352cf9
DV		 8991 fb = mode_fits_in_fbdev(dev, mode);
8992 if (fb == NULL) {
d2dff872 8993 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 8994 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8995 old->release_fb = fb;
d2dff872
CW		 8996 } else
8997 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 8998 if (IS_ERR(fb)) {
d2dff872 8999 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 9000 goto fail;
79e53945 9001 }
79e53945 9002
c0c36b94 9003 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 9004 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 9005 if (old->release_fb)
9006 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 9007 goto fail;
79e53945 9008 }
9128b040 9009 crtc->primary->crtc = crtc;
7173188d 9010
79e53945 9011 /* let the connector get through one full cycle before testing */
9d0498a2 9012 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 9013 return true;
412b61d8
VS		 9014
9015 fail:
83d65738 9016 intel_crtc->new_enabled = crtc->state->enable;
412b61d8 9017 if (intel_crtc->new_enabled)
6e3c9717 9018 intel_crtc->new_config = intel_crtc->config;
412b61d8
VS		 9019 else
9020 intel_crtc->new_config = NULL;
51fd371b
RC		 9021fail_unlock:
9022 if (ret == -EDEADLK) {
9023 drm_modeset_backoff(ctx);
9024 goto retry;
9025 }
9026
412b61d8 9027 return false;
79e53945
JB		 9028}
9029
d2434ab7 9030void intel_release_load_detect_pipe(struct drm_connector *connector,
208bf9fd 9031 struct intel_load_detect_pipe *old)
79e53945 9032{
d2434ab7
DV		 9033 struct intel_encoder *intel_encoder =
9034 intel_attached_encoder(connector);
4ef69c7a 9035 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 9036 struct drm_crtc *crtc = encoder->crtc;
412b61d8 9037 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 9038
d2dff872 9039 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 9040 connector->base.id, connector->name,
8e329a03 9041 encoder->base.id, encoder->name);
d2dff872 9042
8261b191 9043 if (old->load_detect_temp) {
fc303101
DV		 9044 to_intel_connector(connector)->new_encoder = NULL;
9045 intel_encoder->new_crtc = NULL;
412b61d8
VS		 9046 intel_crtc->new_enabled = false;
9047 intel_crtc->new_config = NULL;
fc303101 9048 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 9049
36206361
DV		 9050 if (old->release_fb) {
9051 drm_framebuffer_unregister_private(old->release_fb);
9052 drm_framebuffer_unreference(old->release_fb);
9053 }
d2dff872 9054
0622a53c 9055 return;
79e53945
JB		 9056 }
9057
c751ce4f 9058 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 9059 if (old->dpms_mode != DRM_MODE_DPMS_ON)
9060 connector->funcs->dpms(connector, old->dpms_mode);
79e53945
JB		 9061}
9062
da4a1efa 9063static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 9064 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 9065{
9066 struct drm_i915_private *dev_priv = dev->dev_private;
9067 u32 dpll = pipe_config->dpll_hw_state.dpll;
9068
9069 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 9070 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 9071 else if (HAS_PCH_SPLIT(dev))
9072 return 120000;
9073 else if (!IS_GEN2(dev))
9074 return 96000;
9075 else
9076 return 48000;
9077}
9078
79e53945 9079/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 9080static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 9081 struct intel_crtc_state *pipe_config)
79e53945 9082{
f1f644dc 9083 struct drm_device *dev = crtc->base.dev;
79e53945 9084 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 9085 int pipe = pipe_config->cpu_transcoder;
293623f7 9086 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 9087 u32 fp;
9088 intel_clock_t clock;
da4a1efa 9089 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 9090
9091 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 9092 fp = pipe_config->dpll_hw_state.fp0;
79e53945 9093 else
293623f7 9094 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 9095
9096 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 9097 if (IS_PINEVIEW(dev)) {
9098 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9099 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 9100 } else {
9101 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9102 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9103 }
9104
a6c45cf0 9105 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 9106 if (IS_PINEVIEW(dev))
9107 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9108 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 9109 else
9110 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 9111 DPLL_FPA01_P1_POST_DIV_SHIFT);
9112
9113 switch (dpll & DPLL_MODE_MASK) {
9114 case DPLLB_MODE_DAC_SERIAL:
9115 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9116 5 : 10;
9117 break;
9118 case DPLLB_MODE_LVDS:
9119 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9120 7 : 14;
9121 break;
9122 default:
28c97730 9123 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 9124 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 9125 return;
79e53945
JB		 9126 }
9127
ac58c3f0 9128 if (IS_PINEVIEW(dev))
da4a1efa 9129 pineview_clock(refclk, &clock);
ac58c3f0 9130 else
da4a1efa 9131 i9xx_clock(refclk, &clock);
79e53945 9132 } else {
0fb58223 9133 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 9134 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 9135
9136 if (is_lvds) {
9137 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9138 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 9139
9140 if (lvds & LVDS_CLKB_POWER_UP)
9141 clock.p2 = 7;
9142 else
9143 clock.p2 = 14;
79e53945
JB		 9144 } else {
9145 if (dpll & PLL_P1_DIVIDE_BY_TWO)
9146 clock.p1 = 2;
9147 else {
9148 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9149 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9150 }
9151 if (dpll & PLL_P2_DIVIDE_BY_4)
9152 clock.p2 = 4;
9153 else
9154 clock.p2 = 2;
79e53945 9155 }
da4a1efa
VS		 9156
9157 i9xx_clock(refclk, &clock);
79e53945
JB		 9158 }
9159
18442d08
VS		 9160 /*
9161 * This value includes pixel_multiplier. We will use
241bfc38 9162 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 9163 * encoder's get_config() function.
9164 */
9165 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 9166}
9167
6878da05
VS		 9168int intel_dotclock_calculate(int link_freq,
9169 const struct intel_link_m_n *m_n)
f1f644dc 9170{
f1f644dc
JB		 9171 /*
9172 * The calculation for the data clock is:
1041a02f 9173 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 9174 * But we want to avoid losing precison if possible, so:
1041a02f 9175 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 9176 *
9177 * and the link clock is simpler:
1041a02f 9178 * link_clock = (m * link_clock) / n
f1f644dc
JB		 9179 */
9180
6878da05
VS		 9181 if (!m_n->link_n)
9182 return 0;
f1f644dc 9183
6878da05
VS		 9184 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9185}
f1f644dc 9186
18442d08 9187static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 9188 struct intel_crtc_state *pipe_config)
6878da05
VS		 9189{
9190 struct drm_device *dev = crtc->base.dev;
79e53945 9191
18442d08
VS		 9192 /* read out port_clock from the DPLL */
9193 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 9194
f1f644dc 9195 /*
18442d08 9196 * This value does not include pixel_multiplier.
241bfc38 9197 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 9198 * agree once we know their relationship in the encoder's
9199 * get_config() function.
79e53945 9200 */
2d112de7 9201 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 9202 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
9203 &pipe_config->fdi_m_n);
79e53945
JB		 9204}
9205
9206/** Returns the currently programmed mode of the given pipe. */
9207struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9208 struct drm_crtc *crtc)
9209{
548f245b 9210 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 9211 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 9212 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 9213 struct drm_display_mode *mode;
5cec258b 9214 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 9215 int htot = I915_READ(HTOTAL(cpu_transcoder));
9216 int hsync = I915_READ(HSYNC(cpu_transcoder));
9217 int vtot = I915_READ(VTOTAL(cpu_transcoder));
9218 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 9219 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 9220
9221 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9222 if (!mode)
9223 return NULL;
9224
f1f644dc
JB		 9225 /*
9226 * Construct a pipe_config sufficient for getting the clock info
9227 * back out of crtc_clock_get.
9228 *
9229 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9230 * to use a real value here instead.
9231 */
293623f7 9232 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 9233 pipe_config.pixel_multiplier = 1;
293623f7
VS		 9234 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9235 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9236 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 9237 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
9238
773ae034 9239 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 9240 mode->hdisplay = (htot & 0xffff) + 1;
9241 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9242 mode->hsync_start = (hsync & 0xffff) + 1;
9243 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9244 mode->vdisplay = (vtot & 0xffff) + 1;
9245 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9246 mode->vsync_start = (vsync & 0xffff) + 1;
9247 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9248
9249 drm_mode_set_name(mode);
79e53945
JB		 9250
9251 return mode;
9252}
9253
652c393a
JB		 9254static void intel_decrease_pllclock(struct drm_crtc *crtc)
9255{
9256 struct drm_device *dev = crtc->dev;
fbee40df 9257 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 9258 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 9259
baff296c 9260 if (!HAS_GMCH_DISPLAY(dev))
652c393a
JB		 9261 return;
9262
9263 if (!dev_priv->lvds_downclock_avail)
9264 return;
9265
9266 /*
9267 * Since this is called by a timer, we should never get here in
9268 * the manual case.
9269 */
9270 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 9271 int pipe = intel_crtc->pipe;
9272 int dpll_reg = DPLL(pipe);
9273 int dpll;
f6e5b160 9274
44d98a61 9275 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 9276
8ac5a6d5 9277 assert_panel_unlocked(dev_priv, pipe);
652c393a 9278
dc257cf1 9279 dpll = I915_READ(dpll_reg);
652c393a
JB		 9280 dpll |= DISPLAY_RATE_SELECT_FPA1;
9281 I915_WRITE(dpll_reg, dpll);
9d0498a2 9282 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 9283 dpll = I915_READ(dpll_reg);
9284 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 9285 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 9286 }
9287
9288}
9289
f047e395
CW		 9290void intel_mark_busy(struct drm_device *dev)
9291{
c67a470b
PZ		 9292 struct drm_i915_private *dev_priv = dev->dev_private;
9293
f62a0076
CW		 9294 if (dev_priv->mm.busy)
9295 return;
9296
43694d69 9297 intel_runtime_pm_get(dev_priv);
c67a470b 9298 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 9299 if (INTEL_INFO(dev)->gen >= 6)
9300 gen6_rps_busy(dev_priv);
f62a0076 9301 dev_priv->mm.busy = true;
f047e395
CW		 9302}
9303
9304void intel_mark_idle(struct drm_device *dev)
652c393a 9305{
c67a470b 9306 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 9307 struct drm_crtc *crtc;
652c393a 9308
f62a0076
CW		 9309 if (!dev_priv->mm.busy)
9310 return;
9311
9312 dev_priv->mm.busy = false;
9313
d330a953 9314 if (!i915.powersave)
bb4cdd53 9315 goto out;
652c393a 9316
70e1e0ec 9317 for_each_crtc(dev, crtc) {
f4510a27 9318 if (!crtc->primary->fb)
652c393a
JB		 9319 continue;
9320
725a5b54 9321 intel_decrease_pllclock(crtc);
652c393a 9322 }
b29c19b6 9323
3d13ef2e 9324 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 9325 gen6_rps_idle(dev->dev_private);
bb4cdd53
PZ		 9326
9327out:
43694d69 9328 intel_runtime_pm_put(dev_priv);
652c393a
JB		 9329}
9330
f5de6e07
ACO		 9331static void intel_crtc_set_state(struct intel_crtc *crtc,
9332 struct intel_crtc_state *crtc_state)
9333{
9334 kfree(crtc->config);
9335 crtc->config = crtc_state;
16f3f658 9336 crtc->base.state = &crtc_state->base;
f5de6e07
ACO		 9337}
9338
79e53945
JB		 9339static void intel_crtc_destroy(struct drm_crtc *crtc)
9340{
9341 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 9342 struct drm_device *dev = crtc->dev;
9343 struct intel_unpin_work *work;
67e77c5a 9344
5e2d7afc 9345 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 9346 work = intel_crtc->unpin_work;
9347 intel_crtc->unpin_work = NULL;
5e2d7afc 9348 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 9349
9350 if (work) {
9351 cancel_work_sync(&work->work);
9352 kfree(work);
9353 }
79e53945 9354
f5de6e07 9355 intel_crtc_set_state(intel_crtc, NULL);
79e53945 9356 drm_crtc_cleanup(crtc);
67e77c5a 9357
79e53945
JB		 9358 kfree(intel_crtc);
9359}
9360
6b95a207
KH		 9361static void intel_unpin_work_fn(struct work_struct *__work)
9362{
9363 struct intel_unpin_work *work =
9364 container_of(__work, struct intel_unpin_work, work);
b4a98e57 9365 struct drm_device *dev = work->crtc->dev;
f99d7069 9366 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
6b95a207 9367
b4a98e57 9368 mutex_lock(&dev->struct_mutex);
82bc3b2d 9369 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
05394f39 9370 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 9371
7ff0ebcc 9372 intel_fbc_update(dev);
f06cc1b9
JH		 9373
9374 if (work->flip_queued_req)
146d84f0 9375 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 9376 mutex_unlock(&dev->struct_mutex);
9377
f99d7069 9378 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
89ed88ba 9379 drm_framebuffer_unreference(work->old_fb);
f99d7069 9380
b4a98e57
CW		 9381 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9382 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9383
6b95a207
KH		 9384 kfree(work);
9385}
9386
1afe3e9d 9387static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 9388 struct drm_crtc *crtc)
6b95a207 9389{
6b95a207
KH		 9390 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9391 struct intel_unpin_work *work;
6b95a207
KH		 9392 unsigned long flags;
9393
9394 /* Ignore early vblank irqs */
9395 if (intel_crtc == NULL)
9396 return;
9397
f326038a
DV		 9398 /*
9399 * This is called both by irq handlers and the reset code (to complete
9400 * lost pageflips) so needs the full irqsave spinlocks.
9401 */
6b95a207
KH		 9402 spin_lock_irqsave(&dev->event_lock, flags);
9403 work = intel_crtc->unpin_work;
e7d841ca
CW		 9404
9405 /* Ensure we don't miss a work->pending update ... */
9406 smp_rmb();
9407
9408 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 9409 spin_unlock_irqrestore(&dev->event_lock, flags);
9410 return;
9411 }
9412
d6bbafa1 9413 page_flip_completed(intel_crtc);
0af7e4df 9414
6b95a207 9415 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 9416}
9417
1afe3e9d
JB		 9418void intel_finish_page_flip(struct drm_device *dev, int pipe)
9419{
fbee40df 9420 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 9421 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9422
49b14a5c 9423 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 9424}
9425
9426void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9427{
fbee40df 9428 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 9429 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9430
49b14a5c 9431 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 9432}
9433
75f7f3ec
VS		 9434/* Is 'a' after or equal to 'b'? */
9435static bool g4x_flip_count_after_eq(u32 a, u32 b)
9436{
9437 return !((a - b) & 0x80000000);
9438}
9439
9440static bool page_flip_finished(struct intel_crtc *crtc)
9441{
9442 struct drm_device *dev = crtc->base.dev;
9443 struct drm_i915_private *dev_priv = dev->dev_private;
9444
bdfa7542
VS		 9445 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9446 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9447 return true;
9448
75f7f3ec
VS		 9449 /*
9450 * The relevant registers doen't exist on pre-ctg.
9451 * As the flip done interrupt doesn't trigger for mmio
9452 * flips on gmch platforms, a flip count check isn't
9453 * really needed there. But since ctg has the registers,
9454 * include it in the check anyway.
9455 */
9456 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9457 return true;
9458
9459 /*
9460 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9461 * used the same base address. In that case the mmio flip might
9462 * have completed, but the CS hasn't even executed the flip yet.
9463 *
9464 * A flip count check isn't enough as the CS might have updated
9465 * the base address just after start of vblank, but before we
9466 * managed to process the interrupt. This means we'd complete the
9467 * CS flip too soon.
9468 *
9469 * Combining both checks should get us a good enough result. It may
9470 * still happen that the CS flip has been executed, but has not
9471 * yet actually completed. But in case the base address is the same
9472 * anyway, we don't really care.
9473 */
9474 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9475 crtc->unpin_work->gtt_offset &&
9476 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9477 crtc->unpin_work->flip_count);
9478}
9479
6b95a207
KH		 9480void intel_prepare_page_flip(struct drm_device *dev, int plane)
9481{
fbee40df 9482 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 9483 struct intel_crtc *intel_crtc =
9484 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9485 unsigned long flags;
9486
f326038a
DV		 9487
9488 /*
9489 * This is called both by irq handlers and the reset code (to complete
9490 * lost pageflips) so needs the full irqsave spinlocks.
9491 *
9492 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 9493 * generate a page-flip completion irq, i.e. every modeset
9494 * is also accompanied by a spurious intel_prepare_page_flip().
9495 */
6b95a207 9496 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 9497 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 9498 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 9499 spin_unlock_irqrestore(&dev->event_lock, flags);
9500}
9501
eba905b2 9502static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW		 9503{
9504 /* Ensure that the work item is consistent when activating it ... */
9505 smp_wmb();
9506 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9507 /* and that it is marked active as soon as the irq could fire. */
9508 smp_wmb();
9509}
9510
8c9f3aaf
JB		 9511static int intel_gen2_queue_flip(struct drm_device *dev,
9512 struct drm_crtc *crtc,
9513 struct drm_framebuffer *fb,
ed8d1975 9514 struct drm_i915_gem_object *obj,
a4872ba6 9515 struct intel_engine_cs *ring,
ed8d1975 9516 uint32_t flags)
8c9f3aaf 9517{
8c9f3aaf 9518 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 9519 u32 flip_mask;
9520 int ret;
9521
6d90c952 9522 ret = intel_ring_begin(ring, 6);
8c9f3aaf 9523 if (ret)
4fa62c89 9524 return ret;
8c9f3aaf
JB		 9525
9526 /* Can't queue multiple flips, so wait for the previous
9527 * one to finish before executing the next.
9528 */
9529 if (intel_crtc->plane)
9530 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9531 else
9532 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 9533 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9534 intel_ring_emit(ring, MI_NOOP);
9535 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9536 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9537 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 9538 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 9539 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 9540
9541 intel_mark_page_flip_active(intel_crtc);
09246732 9542 __intel_ring_advance(ring);
83d4092b 9543 return 0;
8c9f3aaf
JB		 9544}
9545
9546static int intel_gen3_queue_flip(struct drm_device *dev,
9547 struct drm_crtc *crtc,
9548 struct drm_framebuffer *fb,
ed8d1975 9549 struct drm_i915_gem_object *obj,
a4872ba6 9550 struct intel_engine_cs *ring,
ed8d1975 9551 uint32_t flags)
8c9f3aaf 9552{
8c9f3aaf 9553 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 9554 u32 flip_mask;
9555 int ret;
9556
6d90c952 9557 ret = intel_ring_begin(ring, 6);
8c9f3aaf 9558 if (ret)
4fa62c89 9559 return ret;
8c9f3aaf
JB		 9560
9561 if (intel_crtc->plane)
9562 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9563 else
9564 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 9565 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9566 intel_ring_emit(ring, MI_NOOP);
9567 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9568 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9569 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 9570 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 9571 intel_ring_emit(ring, MI_NOOP);
9572
e7d841ca 9573 intel_mark_page_flip_active(intel_crtc);
09246732 9574 __intel_ring_advance(ring);
83d4092b 9575 return 0;
8c9f3aaf
JB		 9576}
9577
9578static int intel_gen4_queue_flip(struct drm_device *dev,
9579 struct drm_crtc *crtc,
9580 struct drm_framebuffer *fb,
ed8d1975 9581 struct drm_i915_gem_object *obj,
a4872ba6 9582 struct intel_engine_cs *ring,
ed8d1975 9583 uint32_t flags)
8c9f3aaf
JB		 9584{
9585 struct drm_i915_private *dev_priv = dev->dev_private;
9586 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9587 uint32_t pf, pipesrc;
9588 int ret;
9589
6d90c952 9590 ret = intel_ring_begin(ring, 4);
8c9f3aaf 9591 if (ret)
4fa62c89 9592 return ret;
8c9f3aaf
JB		 9593
9594 /* i965+ uses the linear or tiled offsets from the
9595 * Display Registers (which do not change across a page-flip)
9596 * so we need only reprogram the base address.
9597 */
6d90c952
DV		 9598 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9599 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9600 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 9601 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 9602 obj->tiling_mode);
8c9f3aaf
JB		 9603
9604 /* XXX Enabling the panel-fitter across page-flip is so far
9605 * untested on non-native modes, so ignore it for now.
9606 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9607 */
9608 pf = 0;
9609 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 9610 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 9611
9612 intel_mark_page_flip_active(intel_crtc);
09246732 9613 __intel_ring_advance(ring);
83d4092b 9614 return 0;
8c9f3aaf
JB		 9615}
9616
9617static int intel_gen6_queue_flip(struct drm_device *dev,
9618 struct drm_crtc *crtc,
9619 struct drm_framebuffer *fb,
ed8d1975 9620 struct drm_i915_gem_object *obj,
a4872ba6 9621 struct intel_engine_cs *ring,
ed8d1975 9622 uint32_t flags)
8c9f3aaf
JB		 9623{
9624 struct drm_i915_private *dev_priv = dev->dev_private;
9625 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9626 uint32_t pf, pipesrc;
9627 int ret;
9628
6d90c952 9629 ret = intel_ring_begin(ring, 4);
8c9f3aaf 9630 if (ret)
4fa62c89 9631 return ret;
8c9f3aaf 9632
6d90c952
DV		 9633 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9634 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9635 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 9636 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 9637
dc257cf1
DV		 9638 /* Contrary to the suggestions in the documentation,
9639 * "Enable Panel Fitter" does not seem to be required when page
9640 * flipping with a non-native mode, and worse causes a normal
9641 * modeset to fail.
9642 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9643 */
9644 pf = 0;
8c9f3aaf 9645 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 9646 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 9647
9648 intel_mark_page_flip_active(intel_crtc);
09246732 9649 __intel_ring_advance(ring);
83d4092b 9650 return 0;
8c9f3aaf
JB		 9651}
9652
7c9017e5
JB		 9653static int intel_gen7_queue_flip(struct drm_device *dev,
9654 struct drm_crtc *crtc,
9655 struct drm_framebuffer *fb,
ed8d1975 9656 struct drm_i915_gem_object *obj,
a4872ba6 9657 struct intel_engine_cs *ring,
ed8d1975 9658 uint32_t flags)
7c9017e5 9659{
7c9017e5 9660 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 9661 uint32_t plane_bit = 0;
ffe74d75
CW		 9662 int len, ret;
9663
eba905b2 9664 switch (intel_crtc->plane) {
cb05d8de
DV		 9665 case PLANE_A:
9666 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9667 break;
9668 case PLANE_B:
9669 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9670 break;
9671 case PLANE_C:
9672 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9673 break;
9674 default:
9675 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 9676 return -ENODEV;
cb05d8de
DV		 9677 }
9678
ffe74d75 9679 len = 4;
f476828a 9680 if (ring->id == RCS) {
ffe74d75 9681 len += 6;
f476828a
DL		 9682 /*
9683 * On Gen 8, SRM is now taking an extra dword to accommodate
9684 * 48bits addresses, and we need a NOOP for the batch size to
9685 * stay even.
9686 */
9687 if (IS_GEN8(dev))
9688 len += 2;
9689 }
ffe74d75 9690
f66fab8e
VS		 9691 /*
9692 * BSpec MI_DISPLAY_FLIP for IVB:
9693 * "The full packet must be contained within the same cache line."
9694 *
9695 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9696 * cacheline, if we ever start emitting more commands before
9697 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9698 * then do the cacheline alignment, and finally emit the
9699 * MI_DISPLAY_FLIP.
9700 */
9701 ret = intel_ring_cacheline_align(ring);
9702 if (ret)
4fa62c89 9703 return ret;
f66fab8e 9704
ffe74d75 9705 ret = intel_ring_begin(ring, len);
7c9017e5 9706 if (ret)
4fa62c89 9707 return ret;
7c9017e5 9708
ffe74d75
CW		 9709 /* Unmask the flip-done completion message. Note that the bspec says that
9710 * we should do this for both the BCS and RCS, and that we must not unmask
9711 * more than one flip event at any time (or ensure that one flip message
9712 * can be sent by waiting for flip-done prior to queueing new flips).
9713 * Experimentation says that BCS works despite DERRMR masking all
9714 * flip-done completion events and that unmasking all planes at once
9715 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9716 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9717 */
9718 if (ring->id == RCS) {
9719 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9720 intel_ring_emit(ring, DERRMR);
9721 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9722 DERRMR_PIPEB_PRI_FLIP_DONE |
9723 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a
DL		 9724 if (IS_GEN8(dev))
9725 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9726 MI_SRM_LRM_GLOBAL_GTT);
9727 else
9728 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9729 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 9730 intel_ring_emit(ring, DERRMR);
9731 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 9732 if (IS_GEN8(dev)) {
9733 intel_ring_emit(ring, 0);
9734 intel_ring_emit(ring, MI_NOOP);
9735 }
ffe74d75
CW		 9736 }
9737
cb05d8de 9738 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 9739 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 9740 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 9741 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 9742
9743 intel_mark_page_flip_active(intel_crtc);
09246732 9744 __intel_ring_advance(ring);
83d4092b 9745 return 0;
7c9017e5
JB		 9746}
9747
84c33a64
SG		 9748static bool use_mmio_flip(struct intel_engine_cs *ring,
9749 struct drm_i915_gem_object *obj)
9750{
9751 /*
9752 * This is not being used for older platforms, because
9753 * non-availability of flip done interrupt forces us to use
9754 * CS flips. Older platforms derive flip done using some clever
9755 * tricks involving the flip_pending status bits and vblank irqs.
9756 * So using MMIO flips there would disrupt this mechanism.
9757 */
9758
8e09bf83
CW		 9759 if (ring == NULL)
9760 return true;
9761
84c33a64
SG		 9762 if (INTEL_INFO(ring->dev)->gen < 5)
9763 return false;
9764
9765 if (i915.use_mmio_flip < 0)
9766 return false;
9767 else if (i915.use_mmio_flip > 0)
9768 return true;
14bf993e
OM		 9769 else if (i915.enable_execlists)
9770 return true;
84c33a64 9771 else
41c52415 9772 return ring != i915_gem_request_get_ring(obj->last_read_req);
84c33a64
SG		 9773}
9774
ff944564
DL		 9775static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
9776{
9777 struct drm_device *dev = intel_crtc->base.dev;
9778 struct drm_i915_private *dev_priv = dev->dev_private;
9779 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
9780 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9781 struct drm_i915_gem_object *obj = intel_fb->obj;
9782 const enum pipe pipe = intel_crtc->pipe;
9783 u32 ctl, stride;
9784
9785 ctl = I915_READ(PLANE_CTL(pipe, 0));
9786 ctl &= ~PLANE_CTL_TILED_MASK;
9787 if (obj->tiling_mode == I915_TILING_X)
9788 ctl |= PLANE_CTL_TILED_X;
9789
9790 /*
9791 * The stride is either expressed as a multiple of 64 bytes chunks for
9792 * linear buffers or in number of tiles for tiled buffers.
9793 */
9794 stride = fb->pitches[0] >> 6;
9795 if (obj->tiling_mode == I915_TILING_X)
9796 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
9797
9798 /*
9799 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9800 * PLANE_SURF updates, the update is then guaranteed to be atomic.
9801 */
9802 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
9803 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
9804
9805 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
9806 POSTING_READ(PLANE_SURF(pipe, 0));
9807}
9808
9809static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG		 9810{
9811 struct drm_device *dev = intel_crtc->base.dev;
9812 struct drm_i915_private *dev_priv = dev->dev_private;
9813 struct intel_framebuffer *intel_fb =
9814 to_intel_framebuffer(intel_crtc->base.primary->fb);
9815 struct drm_i915_gem_object *obj = intel_fb->obj;
9816 u32 dspcntr;
9817 u32 reg;
9818
84c33a64
SG		 9819 reg = DSPCNTR(intel_crtc->plane);
9820 dspcntr = I915_READ(reg);
9821
c5d97472
DL		 9822 if (obj->tiling_mode != I915_TILING_NONE)
9823 dspcntr |= DISPPLANE_TILED;
9824 else
9825 dspcntr &= ~DISPPLANE_TILED;
9826
84c33a64
SG		 9827 I915_WRITE(reg, dspcntr);
9828
9829 I915_WRITE(DSPSURF(intel_crtc->plane),
9830 intel_crtc->unpin_work->gtt_offset);
9831 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 9832
ff944564
DL		 9833}
9834
9835/*
9836 * XXX: This is the temporary way to update the plane registers until we get
9837 * around to using the usual plane update functions for MMIO flips
9838 */
9839static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9840{
9841 struct drm_device *dev = intel_crtc->base.dev;
9842 bool atomic_update;
9843 u32 start_vbl_count;
9844
9845 intel_mark_page_flip_active(intel_crtc);
9846
9847 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9848
9849 if (INTEL_INFO(dev)->gen >= 9)
9850 skl_do_mmio_flip(intel_crtc);
9851 else
9852 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9853 ilk_do_mmio_flip(intel_crtc);
9854
9362c7c5
ACO		 9855 if (atomic_update)
9856 intel_pipe_update_end(intel_crtc, start_vbl_count);
84c33a64
SG		 9857}
9858
9362c7c5 9859static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 9860{
cc8c4cc2 9861 struct intel_crtc *crtc =
9362c7c5 9862 container_of(work, struct intel_crtc, mmio_flip.work);
cc8c4cc2 9863 struct intel_mmio_flip *mmio_flip;
84c33a64 9864
cc8c4cc2
JH		 9865 mmio_flip = &crtc->mmio_flip;
9866 if (mmio_flip->req)
9c654818
JH		 9867 WARN_ON(__i915_wait_request(mmio_flip->req,
9868 crtc->reset_counter,
9869 false, NULL, NULL) != 0);
84c33a64 9870
cc8c4cc2
JH		 9871 intel_do_mmio_flip(crtc);
9872 if (mmio_flip->req) {
9873 mutex_lock(&crtc->base.dev->struct_mutex);
146d84f0 9874 i915_gem_request_assign(&mmio_flip->req, NULL);
cc8c4cc2
JH		 9875 mutex_unlock(&crtc->base.dev->struct_mutex);
9876 }
84c33a64
SG		 9877}
9878
9879static int intel_queue_mmio_flip(struct drm_device *dev,
9880 struct drm_crtc *crtc,
9881 struct drm_framebuffer *fb,
9882 struct drm_i915_gem_object *obj,
9883 struct intel_engine_cs *ring,
9884 uint32_t flags)
9885{
84c33a64 9886 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
84c33a64 9887
cc8c4cc2
JH		 9888 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
9889 obj->last_write_req);
536f5b5e
ACO		 9890
9891 schedule_work(&intel_crtc->mmio_flip.work);
84c33a64 9892
84c33a64
SG		 9893 return 0;
9894}
9895
8c9f3aaf
JB		 9896static int intel_default_queue_flip(struct drm_device *dev,
9897 struct drm_crtc *crtc,
9898 struct drm_framebuffer *fb,
ed8d1975 9899 struct drm_i915_gem_object *obj,
a4872ba6 9900 struct intel_engine_cs *ring,
ed8d1975 9901 uint32_t flags)
8c9f3aaf
JB		 9902{
9903 return -ENODEV;
9904}
9905
d6bbafa1
CW		 9906static bool __intel_pageflip_stall_check(struct drm_device *dev,
9907 struct drm_crtc *crtc)
9908{
9909 struct drm_i915_private *dev_priv = dev->dev_private;
9910 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9911 struct intel_unpin_work *work = intel_crtc->unpin_work;
9912 u32 addr;
9913
9914 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9915 return true;
9916
9917 if (!work->enable_stall_check)
9918 return false;
9919
9920 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 9921 if (work->flip_queued_req &&
9922 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 9923 return false;
9924
1e3feefd 9925 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 9926 }
9927
1e3feefd 9928 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 9929 return false;
9930
9931 /* Potential stall - if we see that the flip has happened,
9932 * assume a missed interrupt. */
9933 if (INTEL_INFO(dev)->gen >= 4)
9934 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9935 else
9936 addr = I915_READ(DSPADDR(intel_crtc->plane));
9937
9938 /* There is a potential issue here with a false positive after a flip
9939 * to the same address. We could address this by checking for a
9940 * non-incrementing frame counter.
9941 */
9942 return addr == work->gtt_offset;
9943}
9944
9945void intel_check_page_flip(struct drm_device *dev, int pipe)
9946{
9947 struct drm_i915_private *dev_priv = dev->dev_private;
9948 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9949 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
f326038a 9950
6c51d46f 9951 WARN_ON(!in_interrupt());
d6bbafa1
CW		 9952
9953 if (crtc == NULL)
9954 return;
9955
f326038a 9956 spin_lock(&dev->event_lock);
d6bbafa1
CW		 9957 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9958 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
1e3feefd
DV		 9959 intel_crtc->unpin_work->flip_queued_vblank,
9960 drm_vblank_count(dev, pipe));
d6bbafa1
CW		 9961 page_flip_completed(intel_crtc);
9962 }
f326038a 9963 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 9964}
9965
6b95a207
KH		 9966static int intel_crtc_page_flip(struct drm_crtc *crtc,
9967 struct drm_framebuffer *fb,
ed8d1975
KP		 9968 struct drm_pending_vblank_event *event,
9969 uint32_t page_flip_flags)
6b95a207
KH		 9970{
9971 struct drm_device *dev = crtc->dev;
9972 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 9973 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 9974 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 9975 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 9976 struct drm_plane *primary = crtc->primary;
a071fa00 9977 enum pipe pipe = intel_crtc->pipe;
6b95a207 9978 struct intel_unpin_work *work;
a4872ba6 9979 struct intel_engine_cs *ring;
52e68630 9980 int ret;
6b95a207 9981
2ff8fde1
MR		 9982 /*
9983 * drm_mode_page_flip_ioctl() should already catch this, but double
9984 * check to be safe. In the future we may enable pageflipping from
9985 * a disabled primary plane.
9986 */
9987 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9988 return -EBUSY;
9989
e6a595d2 9990 /* Can't change pixel format via MI display flips. */
f4510a27 9991 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 9992 return -EINVAL;
9993
9994 /*
9995 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9996 * Note that pitch changes could also affect these register.
9997 */
9998 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 9999 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10000 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 10001 return -EINVAL;
10002
f900db47
CW		 10003 if (i915_terminally_wedged(&dev_priv->gpu_error))
10004 goto out_hang;
10005
b14c5679 10006 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 10007 if (work == NULL)
10008 return -ENOMEM;
10009
6b95a207 10010 work->event = event;
b4a98e57 10011 work->crtc = crtc;
ab8d6675 10012 work->old_fb = old_fb;
6b95a207
KH		 10013 INIT_WORK(&work->work, intel_unpin_work_fn);
10014
87b6b101 10015 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 10016 if (ret)
10017 goto free_work;
10018
6b95a207 10019 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 10020 spin_lock_irq(&dev->event_lock);
6b95a207 10021 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 10022 /* Before declaring the flip queue wedged, check if
10023 * the hardware completed the operation behind our backs.
10024 */
10025 if (__intel_pageflip_stall_check(dev, crtc)) {
10026 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10027 page_flip_completed(intel_crtc);
10028 } else {
10029 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 10030 spin_unlock_irq(&dev->event_lock);
468f0b44 10031
d6bbafa1
CW		 10032 drm_crtc_vblank_put(crtc);
10033 kfree(work);
10034 return -EBUSY;
10035 }
6b95a207
KH		 10036 }
10037 intel_crtc->unpin_work = work;
5e2d7afc 10038 spin_unlock_irq(&dev->event_lock);
6b95a207 10039
b4a98e57
CW		 10040 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10041 flush_workqueue(dev_priv->wq);
10042
75dfca80 10043 /* Reference the objects for the scheduled work. */
ab8d6675 10044 drm_framebuffer_reference(work->old_fb);
05394f39 10045 drm_gem_object_reference(&obj->base);
6b95a207 10046
f4510a27 10047 crtc->primary->fb = fb;
afd65eb4 10048 update_state_fb(crtc->primary);
1ed1f968 10049
e1f99ce6 10050 work->pending_flip_obj = obj;
e1f99ce6 10051
89ed88ba
CW		 10052 ret = i915_mutex_lock_interruptible(dev);
10053 if (ret)
10054 goto cleanup;
10055
b4a98e57 10056 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 10057 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 10058
75f7f3ec 10059 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 10060 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 10061
4fa62c89
VS		 10062 if (IS_VALLEYVIEW(dev)) {
10063 ring = &dev_priv->ring[BCS];
ab8d6675 10064 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 10065 /* vlv: DISPLAY_FLIP fails to change tiling */
10066 ring = NULL;
48bf5b2d 10067 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 10068 ring = &dev_priv->ring[BCS];
4fa62c89 10069 } else if (INTEL_INFO(dev)->gen >= 7) {
41c52415 10070 ring = i915_gem_request_get_ring(obj->last_read_req);
4fa62c89
VS		 10071 if (ring == NULL || ring->id != RCS)
10072 ring = &dev_priv->ring[BCS];
10073 } else {
10074 ring = &dev_priv->ring[RCS];
10075 }
10076
82bc3b2d
TU		 10077 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
10078 crtc->primary->state, ring);
8c9f3aaf
JB		 10079 if (ret)
10080 goto cleanup_pending;
6b95a207 10081
4fa62c89
VS		 10082 work->gtt_offset =
10083 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
10084
d6bbafa1 10085 if (use_mmio_flip(ring, obj)) {
84c33a64
SG		 10086 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
10087 page_flip_flags);
d6bbafa1
CW		 10088 if (ret)
10089 goto cleanup_unpin;
10090
f06cc1b9
JH		 10091 i915_gem_request_assign(&work->flip_queued_req,
10092 obj->last_write_req);
d6bbafa1 10093 } else {
84c33a64 10094 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
d6bbafa1
CW		 10095 page_flip_flags);
10096 if (ret)
10097 goto cleanup_unpin;
10098
f06cc1b9
JH		 10099 i915_gem_request_assign(&work->flip_queued_req,
10100 intel_ring_get_request(ring));
d6bbafa1
CW		 10101 }
10102
1e3feefd 10103 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 10104 work->enable_stall_check = true;
4fa62c89 10105
ab8d6675 10106 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a071fa00
DV		 10107 INTEL_FRONTBUFFER_PRIMARY(pipe));
10108
7ff0ebcc 10109 intel_fbc_disable(dev);
f99d7069 10110 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
6b95a207
KH		 10111 mutex_unlock(&dev->struct_mutex);
10112
e5510fac
JB		 10113 trace_i915_flip_request(intel_crtc->plane, obj);
10114
6b95a207 10115 return 0;
96b099fd 10116
4fa62c89 10117cleanup_unpin:
82bc3b2d 10118 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 10119cleanup_pending:
b4a98e57 10120 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 10121 mutex_unlock(&dev->struct_mutex);
10122cleanup:
f4510a27 10123 crtc->primary->fb = old_fb;
afd65eb4 10124 update_state_fb(crtc->primary);
89ed88ba
CW		 10125
10126 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 10127 drm_framebuffer_unreference(work->old_fb);
96b099fd 10128
5e2d7afc 10129 spin_lock_irq(&dev->event_lock);
96b099fd 10130 intel_crtc->unpin_work = NULL;
5e2d7afc 10131 spin_unlock_irq(&dev->event_lock);
96b099fd 10132
87b6b101 10133 drm_crtc_vblank_put(crtc);
7317c75e 10134free_work:
96b099fd
CW		 10135 kfree(work);
10136
f900db47
CW		 10137 if (ret == -EIO) {
10138out_hang:
53a366b9 10139 ret = intel_plane_restore(primary);
f0d3dad3 10140 if (ret == 0 && event) {
5e2d7afc 10141 spin_lock_irq(&dev->event_lock);
a071fa00 10142 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 10143 spin_unlock_irq(&dev->event_lock);
f0d3dad3 10144 }
f900db47 10145 }
96b099fd 10146 return ret;
6b95a207
KH		 10147}
10148
f6e5b160 10149static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 10150 .mode_set_base_atomic = intel_pipe_set_base_atomic,
10151 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 10152 .atomic_begin = intel_begin_crtc_commit,
10153 .atomic_flush = intel_finish_crtc_commit,
f6e5b160
CW		 10154};
10155
9a935856
DV		 10156/**
10157 * intel_modeset_update_staged_output_state
10158 *
10159 * Updates the staged output configuration state, e.g. after we've read out the
10160 * current hw state.
10161 */
10162static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 10163{
7668851f 10164 struct intel_crtc *crtc;
9a935856
DV		 10165 struct intel_encoder *encoder;
10166 struct intel_connector *connector;
f6e5b160 10167
3a3371ff 10168 for_each_intel_connector(dev, connector) {
9a935856
DV		 10169 connector->new_encoder =
10170 to_intel_encoder(connector->base.encoder);
10171 }
f6e5b160 10172
b2784e15 10173 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 10174 encoder->new_crtc =
10175 to_intel_crtc(encoder->base.crtc);
10176 }
7668851f 10177
d3fcc808 10178 for_each_intel_crtc(dev, crtc) {
83d65738 10179 crtc->new_enabled = crtc->base.state->enable;
7bd0a8e7
VS		 10180
10181 if (crtc->new_enabled)
6e3c9717 10182 crtc->new_config = crtc->config;
7bd0a8e7
VS		 10183 else
10184 crtc->new_config = NULL;
7668851f 10185 }
f6e5b160
CW		 10186}
10187
9a935856
DV		 10188/**
10189 * intel_modeset_commit_output_state
10190 *
10191 * This function copies the stage display pipe configuration to the real one.
10192 */
10193static void intel_modeset_commit_output_state(struct drm_device *dev)
10194{
7668851f 10195 struct intel_crtc *crtc;
9a935856
DV		 10196 struct intel_encoder *encoder;
10197 struct intel_connector *connector;
f6e5b160 10198
3a3371ff 10199 for_each_intel_connector(dev, connector) {
9a935856
DV		 10200 connector->base.encoder = &connector->new_encoder->base;
10201 }
f6e5b160 10202
b2784e15 10203 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 10204 encoder->base.crtc = &encoder->new_crtc->base;
10205 }
7668851f 10206
d3fcc808 10207 for_each_intel_crtc(dev, crtc) {
83d65738 10208 crtc->base.state->enable = crtc->new_enabled;
7668851f
VS		 10209 crtc->base.enabled = crtc->new_enabled;
10210 }
9a935856
DV		 10211}
10212
050f7aeb 10213static void
eba905b2 10214connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 10215 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 10216{
10217 int bpp = pipe_config->pipe_bpp;
10218
10219 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10220 connector->base.base.id,
c23cc417 10221 connector->base.name);
050f7aeb
DV		 10222
10223 /* Don't use an invalid EDID bpc value */
10224 if (connector->base.display_info.bpc &&
10225 connector->base.display_info.bpc * 3 < bpp) {
10226 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10227 bpp, connector->base.display_info.bpc*3);
10228 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10229 }
10230
10231 /* Clamp bpp to 8 on screens without EDID 1.4 */
10232 if (connector->base.display_info.bpc == 0 && bpp > 24) {
10233 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10234 bpp);
10235 pipe_config->pipe_bpp = 24;
10236 }
10237}
10238
4e53c2e0 10239static int
050f7aeb
DV		 10240compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10241 struct drm_framebuffer *fb,
5cec258b 10242 struct intel_crtc_state *pipe_config)
4e53c2e0 10243{
050f7aeb
DV		 10244 struct drm_device *dev = crtc->base.dev;
10245 struct intel_connector *connector;
4e53c2e0
DV		 10246 int bpp;
10247
d42264b1
DV		 10248 switch (fb->pixel_format) {
10249 case DRM_FORMAT_C8:
4e53c2e0
DV		 10250 bpp = 8*3; /* since we go through a colormap */
10251 break;
d42264b1
DV		 10252 case DRM_FORMAT_XRGB1555:
10253 case DRM_FORMAT_ARGB1555:
10254 /* checked in intel_framebuffer_init already */
10255 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10256 return -EINVAL;
10257 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 10258 bpp = 6*3; /* min is 18bpp */
10259 break;
d42264b1
DV		 10260 case DRM_FORMAT_XBGR8888:
10261 case DRM_FORMAT_ABGR8888:
10262 /* checked in intel_framebuffer_init already */
10263 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10264 return -EINVAL;
10265 case DRM_FORMAT_XRGB8888:
10266 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 10267 bpp = 8*3;
10268 break;
d42264b1
DV		 10269 case DRM_FORMAT_XRGB2101010:
10270 case DRM_FORMAT_ARGB2101010:
10271 case DRM_FORMAT_XBGR2101010:
10272 case DRM_FORMAT_ABGR2101010:
10273 /* checked in intel_framebuffer_init already */
10274 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 10275 return -EINVAL;
4e53c2e0
DV		 10276 bpp = 10*3;
10277 break;
baba133a 10278 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 10279 default:
10280 DRM_DEBUG_KMS("unsupported depth\n");
10281 return -EINVAL;
10282 }
10283
4e53c2e0
DV		 10284 pipe_config->pipe_bpp = bpp;
10285
10286 /* Clamp display bpp to EDID value */
3a3371ff 10287 for_each_intel_connector(dev, connector) {
1b829e05
DV		 10288 if (!connector->new_encoder ||
10289 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 10290 continue;
10291
050f7aeb 10292 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 10293 }
10294
10295 return bpp;
10296}
10297
644db711
DV		 10298static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10299{
10300 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10301 "type: 0x%x flags: 0x%x\n",
1342830c 10302 mode->crtc_clock,
644db711
DV		 10303 mode->crtc_hdisplay, mode->crtc_hsync_start,
10304 mode->crtc_hsync_end, mode->crtc_htotal,
10305 mode->crtc_vdisplay, mode->crtc_vsync_start,
10306 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10307}
10308
c0b03411 10309static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 10310 struct intel_crtc_state *pipe_config,
c0b03411
DV		 10311 const char *context)
10312{
10313 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10314 context, pipe_name(crtc->pipe));
10315
10316 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10317 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10318 pipe_config->pipe_bpp, pipe_config->dither);
10319 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10320 pipe_config->has_pch_encoder,
10321 pipe_config->fdi_lanes,
10322 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10323 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10324 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 10325 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10326 pipe_config->has_dp_encoder,
10327 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10328 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10329 pipe_config->dp_m_n.tu);
b95af8be
VK		 10330
10331 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10332 pipe_config->has_dp_encoder,
10333 pipe_config->dp_m2_n2.gmch_m,
10334 pipe_config->dp_m2_n2.gmch_n,
10335 pipe_config->dp_m2_n2.link_m,
10336 pipe_config->dp_m2_n2.link_n,
10337 pipe_config->dp_m2_n2.tu);
10338
55072d19
DV		 10339 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10340 pipe_config->has_audio,
10341 pipe_config->has_infoframe);
10342
c0b03411 10343 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 10344 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 10345 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 10346 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10347 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 10348 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 10349 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10350 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
c0b03411
DV		 10351 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10352 pipe_config->gmch_pfit.control,
10353 pipe_config->gmch_pfit.pgm_ratios,
10354 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 10355 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 10356 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 10357 pipe_config->pch_pfit.size,
10358 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 10359 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 10360 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
c0b03411
DV		 10361}
10362
bc079e8b
VS		 10363static bool encoders_cloneable(const struct intel_encoder *a,
10364 const struct intel_encoder *b)
accfc0c5 10365{
bc079e8b
VS		 10366 /* masks could be asymmetric, so check both ways */
10367 return a == b || (a->cloneable & (1 << b->type) &&
10368 b->cloneable & (1 << a->type));
10369}
10370
10371static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10372 struct intel_encoder *encoder)
10373{
10374 struct drm_device *dev = crtc->base.dev;
10375 struct intel_encoder *source_encoder;
10376
b2784e15 10377 for_each_intel_encoder(dev, source_encoder) {
bc079e8b
VS		 10378 if (source_encoder->new_crtc != crtc)
10379 continue;
10380
10381 if (!encoders_cloneable(encoder, source_encoder))
10382 return false;
10383 }
10384
10385 return true;
10386}
10387
10388static bool check_encoder_cloning(struct intel_crtc *crtc)
10389{
10390 struct drm_device *dev = crtc->base.dev;
accfc0c5
DV		 10391 struct intel_encoder *encoder;
10392
b2784e15 10393 for_each_intel_encoder(dev, encoder) {
bc079e8b 10394 if (encoder->new_crtc != crtc)
accfc0c5
DV		 10395 continue;
10396
bc079e8b
VS		 10397 if (!check_single_encoder_cloning(crtc, encoder))
10398 return false;
accfc0c5
DV		 10399 }
10400
bc079e8b 10401 return true;
accfc0c5
DV		 10402}
10403
00f0b378
VS		 10404static bool check_digital_port_conflicts(struct drm_device *dev)
10405{
10406 struct intel_connector *connector;
10407 unsigned int used_ports = 0;
10408
10409 /*
10410 * Walk the connector list instead of the encoder
10411 * list to detect the problem on ddi platforms
10412 * where there's just one encoder per digital port.
10413 */
3a3371ff 10414 for_each_intel_connector(dev, connector) {
00f0b378
VS		 10415 struct intel_encoder *encoder = connector->new_encoder;
10416
10417 if (!encoder)
10418 continue;
10419
10420 WARN_ON(!encoder->new_crtc);
10421
10422 switch (encoder->type) {
10423 unsigned int port_mask;
10424 case INTEL_OUTPUT_UNKNOWN:
10425 if (WARN_ON(!HAS_DDI(dev)))
10426 break;
10427 case INTEL_OUTPUT_DISPLAYPORT:
10428 case INTEL_OUTPUT_HDMI:
10429 case INTEL_OUTPUT_EDP:
10430 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10431
10432 /* the same port mustn't appear more than once */
10433 if (used_ports & port_mask)
10434 return false;
10435
10436 used_ports |= port_mask;
10437 default:
10438 break;
10439 }
10440 }
10441
10442 return true;
10443}
10444
5cec258b 10445static struct intel_crtc_state *
b8cecdf5 10446intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 10447 struct drm_framebuffer *fb,
b8cecdf5 10448 struct drm_display_mode *mode)
ee7b9f93 10449{
7758a113 10450 struct drm_device *dev = crtc->dev;
7758a113 10451 struct intel_encoder *encoder;
5cec258b 10452 struct intel_crtc_state *pipe_config;
e29c22c0
DV		 10453 int plane_bpp, ret = -EINVAL;
10454 bool retry = true;
ee7b9f93 10455
bc079e8b 10456 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
accfc0c5
DV		 10457 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10458 return ERR_PTR(-EINVAL);
10459 }
10460
00f0b378
VS		 10461 if (!check_digital_port_conflicts(dev)) {
10462 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10463 return ERR_PTR(-EINVAL);
10464 }
10465
b8cecdf5
DV		 10466 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10467 if (!pipe_config)
7758a113
DV		 10468 return ERR_PTR(-ENOMEM);
10469
07878248 10470 pipe_config->base.crtc = crtc;
2d112de7
ACO		 10471 drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
10472 drm_mode_copy(&pipe_config->base.mode, mode);
37327abd 10473
e143a21c
DV		 10474 pipe_config->cpu_transcoder =
10475 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 10476 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 10477
2960bc9c
ID		 10478 /*
10479 * Sanitize sync polarity flags based on requested ones. If neither
10480 * positive or negative polarity is requested, treat this as meaning
10481 * negative polarity.
10482 */
2d112de7 10483 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 10484 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 10485 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 10486
2d112de7 10487 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 10488 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 10489 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 10490
050f7aeb
DV		 10491 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10492 * plane pixel format and any sink constraints into account. Returns the
10493 * source plane bpp so that dithering can be selected on mismatches
10494 * after encoders and crtc also have had their say. */
10495 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10496 fb, pipe_config);
4e53c2e0
DV		 10497 if (plane_bpp < 0)
10498 goto fail;
10499
e41a56be
VS		 10500 /*
10501 * Determine the real pipe dimensions. Note that stereo modes can
10502 * increase the actual pipe size due to the frame doubling and
10503 * insertion of additional space for blanks between the frame. This
10504 * is stored in the crtc timings. We use the requested mode to do this
10505 * computation to clearly distinguish it from the adjusted mode, which
10506 * can be changed by the connectors in the below retry loop.
10507 */
2d112de7 10508 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 10509 &pipe_config->pipe_src_w,
10510 &pipe_config->pipe_src_h);
e41a56be 10511
e29c22c0 10512encoder_retry:
ef1b460d 10513 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 10514 pipe_config->port_clock = 0;
ef1b460d 10515 pipe_config->pixel_multiplier = 1;
ff9a6750 10516
135c81b8 10517 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 10518 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10519 CRTC_STEREO_DOUBLE);
135c81b8 10520
7758a113
DV		 10521 /* Pass our mode to the connectors and the CRTC to give them a chance to
10522 * adjust it according to limitations or connector properties, and also
10523 * a chance to reject the mode entirely.
47f1c6c9 10524 */
b2784e15 10525 for_each_intel_encoder(dev, encoder) {
47f1c6c9 10526
7758a113
DV		 10527 if (&encoder->new_crtc->base != crtc)
10528 continue;
7ae89233 10529
efea6e8e
DV		 10530 if (!(encoder->compute_config(encoder, pipe_config))) {
10531 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 10532 goto fail;
10533 }
ee7b9f93 10534 }
47f1c6c9 10535
ff9a6750
DV		 10536 /* Set default port clock if not overwritten by the encoder. Needs to be
10537 * done afterwards in case the encoder adjusts the mode. */
10538 if (!pipe_config->port_clock)
2d112de7 10539 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 10540 * pipe_config->pixel_multiplier;
ff9a6750 10541
a43f6e0f 10542 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 10543 if (ret < 0) {
7758a113
DV		 10544 DRM_DEBUG_KMS("CRTC fixup failed\n");
10545 goto fail;
ee7b9f93 10546 }
e29c22c0
DV		 10547
10548 if (ret == RETRY) {
10549 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10550 ret = -EINVAL;
10551 goto fail;
10552 }
10553
10554 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10555 retry = false;
10556 goto encoder_retry;
10557 }
10558
4e53c2e0
DV		 10559 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10560 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10561 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10562
b8cecdf5 10563 return pipe_config;
7758a113 10564fail:
b8cecdf5 10565 kfree(pipe_config);
e29c22c0 10566 return ERR_PTR(ret);
ee7b9f93 10567}
47f1c6c9 10568
e2e1ed41
DV		 10569/* Computes which crtcs are affected and sets the relevant bits in the mask. For
10570 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10571static void
10572intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10573 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 10574{
10575 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 10576 struct drm_device *dev = crtc->dev;
10577 struct intel_encoder *encoder;
10578 struct intel_connector *connector;
10579 struct drm_crtc *tmp_crtc;
79e53945 10580
e2e1ed41 10581 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 10582
e2e1ed41
DV		 10583 /* Check which crtcs have changed outputs connected to them, these need
10584 * to be part of the prepare_pipes mask. We don't (yet) support global
10585 * modeset across multiple crtcs, so modeset_pipes will only have one
10586 * bit set at most. */
3a3371ff 10587 for_each_intel_connector(dev, connector) {
e2e1ed41
DV		 10588 if (connector->base.encoder == &connector->new_encoder->base)
10589 continue;
79e53945 10590
e2e1ed41
DV		 10591 if (connector->base.encoder) {
10592 tmp_crtc = connector->base.encoder->crtc;
10593
10594 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10595 }
10596
10597 if (connector->new_encoder)
10598 *prepare_pipes |=
10599 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 10600 }
10601
b2784e15 10602 for_each_intel_encoder(dev, encoder) {
e2e1ed41
DV		 10603 if (encoder->base.crtc == &encoder->new_crtc->base)
10604 continue;
10605
10606 if (encoder->base.crtc) {
10607 tmp_crtc = encoder->base.crtc;
10608
10609 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10610 }
10611
10612 if (encoder->new_crtc)
10613 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 10614 }
10615
7668851f 10616 /* Check for pipes that will be enabled/disabled ... */
d3fcc808 10617 for_each_intel_crtc(dev, intel_crtc) {
83d65738 10618 if (intel_crtc->base.state->enable == intel_crtc->new_enabled)
e2e1ed41 10619 continue;
7e7d76c3 10620
7668851f 10621 if (!intel_crtc->new_enabled)
e2e1ed41 10622 *disable_pipes |= 1 << intel_crtc->pipe;
7668851f
VS		 10623 else
10624 *prepare_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 10625 }
10626
e2e1ed41
DV		 10627
10628 /* set_mode is also used to update properties on life display pipes. */
10629 intel_crtc = to_intel_crtc(crtc);
7668851f 10630 if (intel_crtc->new_enabled)
e2e1ed41
DV		 10631 *prepare_pipes |= 1 << intel_crtc->pipe;
10632
b6c5164d
DV		 10633 /*
10634 * For simplicity do a full modeset on any pipe where the output routing
10635 * changed. We could be more clever, but that would require us to be
10636 * more careful with calling the relevant encoder->mode_set functions.
10637 */
e2e1ed41
DV		 10638 if (*prepare_pipes)
10639 *modeset_pipes = *prepare_pipes;
10640
10641 /* ... and mask these out. */
10642 *modeset_pipes &= ~(*disable_pipes);
10643 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 10644
10645 /*
10646 * HACK: We don't (yet) fully support global modesets. intel_set_config
10647 * obies this rule, but the modeset restore mode of
10648 * intel_modeset_setup_hw_state does not.
10649 */
10650 *modeset_pipes &= 1 << intel_crtc->pipe;
10651 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 10652
10653 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10654 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 10655}
79e53945 10656
ea9d758d 10657static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 10658{
ea9d758d 10659 struct drm_encoder *encoder;
f6e5b160 10660 struct drm_device *dev = crtc->dev;
f6e5b160 10661
ea9d758d
DV		 10662 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10663 if (encoder->crtc == crtc)
10664 return true;
10665
10666 return false;
10667}
10668
10669static void
10670intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10671{
ba41c0de 10672 struct drm_i915_private *dev_priv = dev->dev_private;
ea9d758d
DV		 10673 struct intel_encoder *intel_encoder;
10674 struct intel_crtc *intel_crtc;
10675 struct drm_connector *connector;
10676
ba41c0de
DV		 10677 intel_shared_dpll_commit(dev_priv);
10678
b2784e15 10679 for_each_intel_encoder(dev, intel_encoder) {
ea9d758d
DV		 10680 if (!intel_encoder->base.crtc)
10681 continue;
10682
10683 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10684
10685 if (prepare_pipes & (1 << intel_crtc->pipe))
10686 intel_encoder->connectors_active = false;
10687 }
10688
10689 intel_modeset_commit_output_state(dev);
10690
7668851f 10691 /* Double check state. */
d3fcc808 10692 for_each_intel_crtc(dev, intel_crtc) {
83d65738 10693 WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base));
7bd0a8e7 10694 WARN_ON(intel_crtc->new_config &&
6e3c9717 10695 intel_crtc->new_config != intel_crtc->config);
83d65738 10696 WARN_ON(intel_crtc->base.state->enable != !!intel_crtc->new_config);
ea9d758d
DV		 10697 }
10698
10699 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10700 if (!connector->encoder || !connector->encoder->crtc)
10701 continue;
10702
10703 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10704
10705 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 10706 struct drm_property *dpms_property =
10707 dev->mode_config.dpms_property;
10708
ea9d758d 10709 connector->dpms = DRM_MODE_DPMS_ON;
662595df 10710 drm_object_property_set_value(&connector->base,
68d34720
DV		 10711 dpms_property,
10712 DRM_MODE_DPMS_ON);
ea9d758d
DV		 10713
10714 intel_encoder = to_intel_encoder(connector->encoder);
10715 intel_encoder->connectors_active = true;
10716 }
10717 }
10718
10719}
10720
3bd26263 10721static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 10722{
3bd26263 10723 int diff;
f1f644dc
JB		 10724
10725 if (clock1 == clock2)
10726 return true;
10727
10728 if (!clock1 || !clock2)
10729 return false;
10730
10731 diff = abs(clock1 - clock2);
10732
10733 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10734 return true;
10735
10736 return false;
10737}
10738
25c5b266
DV		 10739#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10740 list_for_each_entry((intel_crtc), \
10741 &(dev)->mode_config.crtc_list, \
10742 base.head) \
0973f18f 10743 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 10744
0e8ffe1b 10745static bool
2fa2fe9a 10746intel_pipe_config_compare(struct drm_device *dev,
5cec258b
ACO		 10747 struct intel_crtc_state *current_config,
10748 struct intel_crtc_state *pipe_config)
0e8ffe1b 10749{
66e985c0
DV		 10750#define PIPE_CONF_CHECK_X(name) \
10751 if (current_config->name != pipe_config->name) { \
10752 DRM_ERROR("mismatch in " #name " " \
10753 "(expected 0x%08x, found 0x%08x)\n", \
10754 current_config->name, \
10755 pipe_config->name); \
10756 return false; \
10757 }
10758
08a24034
DV		 10759#define PIPE_CONF_CHECK_I(name) \
10760 if (current_config->name != pipe_config->name) { \
10761 DRM_ERROR("mismatch in " #name " " \
10762 "(expected %i, found %i)\n", \
10763 current_config->name, \
10764 pipe_config->name); \
10765 return false; \
88adfff1
DV		 10766 }
10767
b95af8be
VK		 10768/* This is required for BDW+ where there is only one set of registers for
10769 * switching between high and low RR.
10770 * This macro can be used whenever a comparison has to be made between one
10771 * hw state and multiple sw state variables.
10772 */
10773#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10774 if ((current_config->name != pipe_config->name) && \
10775 (current_config->alt_name != pipe_config->name)) { \
10776 DRM_ERROR("mismatch in " #name " " \
10777 "(expected %i or %i, found %i)\n", \
10778 current_config->name, \
10779 current_config->alt_name, \
10780 pipe_config->name); \
10781 return false; \
10782 }
10783
1bd1bd80
DV		 10784#define PIPE_CONF_CHECK_FLAGS(name, mask) \
10785 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 10786 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 10787 "(expected %i, found %i)\n", \
10788 current_config->name & (mask), \
10789 pipe_config->name & (mask)); \
10790 return false; \
10791 }
10792
5e550656
VS		 10793#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10794 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10795 DRM_ERROR("mismatch in " #name " " \
10796 "(expected %i, found %i)\n", \
10797 current_config->name, \
10798 pipe_config->name); \
10799 return false; \
10800 }
10801
bb760063
DV		 10802#define PIPE_CONF_QUIRK(quirk) \
10803 ((current_config->quirks | pipe_config->quirks) & (quirk))
10804
eccb140b
DV		 10805 PIPE_CONF_CHECK_I(cpu_transcoder);
10806
08a24034
DV		 10807 PIPE_CONF_CHECK_I(has_pch_encoder);
10808 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 10809 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10810 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10811 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10812 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10813 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 10814
eb14cb74 10815 PIPE_CONF_CHECK_I(has_dp_encoder);
b95af8be
VK		 10816
10817 if (INTEL_INFO(dev)->gen < 8) {
10818 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10819 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10820 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10821 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10822 PIPE_CONF_CHECK_I(dp_m_n.tu);
10823
10824 if (current_config->has_drrs) {
10825 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10826 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10827 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10828 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10829 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10830 }
10831 } else {
10832 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10833 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10834 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10835 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10836 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10837 }
eb14cb74 10838
2d112de7
ACO		 10839 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
10840 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
10841 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
10842 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
10843 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
10844 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 10845
2d112de7
ACO		 10846 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
10847 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
10848 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
10849 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
10850 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
10851 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 10852
c93f54cf 10853 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 10854 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 10855 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10856 IS_VALLEYVIEW(dev))
10857 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 10858 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 10859
9ed109a7
DV		 10860 PIPE_CONF_CHECK_I(has_audio);
10861
2d112de7 10862 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 10863 DRM_MODE_FLAG_INTERLACE);
10864
bb760063 10865 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 10866 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 10867 DRM_MODE_FLAG_PHSYNC);
2d112de7 10868 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 10869 DRM_MODE_FLAG_NHSYNC);
2d112de7 10870 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 10871 DRM_MODE_FLAG_PVSYNC);
2d112de7 10872 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 10873 DRM_MODE_FLAG_NVSYNC);
10874 }
045ac3b5 10875
37327abd
VS		 10876 PIPE_CONF_CHECK_I(pipe_src_w);
10877 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 10878
9953599b
DV		 10879 /*
10880 * FIXME: BIOS likes to set up a cloned config with lvds+external
10881 * screen. Since we don't yet re-compute the pipe config when moving
10882 * just the lvds port away to another pipe the sw tracking won't match.
10883 *
10884 * Proper atomic modesets with recomputed global state will fix this.
10885 * Until then just don't check gmch state for inherited modes.
10886 */
10887 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10888 PIPE_CONF_CHECK_I(gmch_pfit.control);
10889 /* pfit ratios are autocomputed by the hw on gen4+ */
10890 if (INTEL_INFO(dev)->gen < 4)
10891 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10892 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10893 }
10894
fd4daa9c
CW		 10895 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10896 if (current_config->pch_pfit.enabled) {
10897 PIPE_CONF_CHECK_I(pch_pfit.pos);
10898 PIPE_CONF_CHECK_I(pch_pfit.size);
10899 }
2fa2fe9a 10900
e59150dc
JB		 10901 /* BDW+ don't expose a synchronous way to read the state */
10902 if (IS_HASWELL(dev))
10903 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 10904
282740f7
VS		 10905 PIPE_CONF_CHECK_I(double_wide);
10906
26804afd
DV		 10907 PIPE_CONF_CHECK_X(ddi_pll_sel);
10908
c0d43d62 10909 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 10910 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 10911 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 10912 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10913 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 10914 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 10915 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
10916 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
10917 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 10918
42571aef
VS		 10919 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10920 PIPE_CONF_CHECK_I(pipe_bpp);
10921
2d112de7 10922 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 10923 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 10924
66e985c0 10925#undef PIPE_CONF_CHECK_X
08a24034 10926#undef PIPE_CONF_CHECK_I
b95af8be 10927#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 10928#undef PIPE_CONF_CHECK_FLAGS
5e550656 10929#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 10930#undef PIPE_CONF_QUIRK
88adfff1 10931
0e8ffe1b
DV		 10932 return true;
10933}
10934
08db6652
DL		 10935static void check_wm_state(struct drm_device *dev)
10936{
10937 struct drm_i915_private *dev_priv = dev->dev_private;
10938 struct skl_ddb_allocation hw_ddb, *sw_ddb;
10939 struct intel_crtc *intel_crtc;
10940 int plane;
10941
10942 if (INTEL_INFO(dev)->gen < 9)
10943 return;
10944
10945 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
10946 sw_ddb = &dev_priv->wm.skl_hw.ddb;
10947
10948 for_each_intel_crtc(dev, intel_crtc) {
10949 struct skl_ddb_entry *hw_entry, *sw_entry;
10950 const enum pipe pipe = intel_crtc->pipe;
10951
10952 if (!intel_crtc->active)
10953 continue;
10954
10955 /* planes */
dd740780 10956 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 10957 hw_entry = &hw_ddb.plane[pipe][plane];
10958 sw_entry = &sw_ddb->plane[pipe][plane];
10959
10960 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10961 continue;
10962
10963 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10964 "(expected (%u,%u), found (%u,%u))\n",
10965 pipe_name(pipe), plane + 1,
10966 sw_entry->start, sw_entry->end,
10967 hw_entry->start, hw_entry->end);
10968 }
10969
10970 /* cursor */
10971 hw_entry = &hw_ddb.cursor[pipe];
10972 sw_entry = &sw_ddb->cursor[pipe];
10973
10974 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10975 continue;
10976
10977 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10978 "(expected (%u,%u), found (%u,%u))\n",
10979 pipe_name(pipe),
10980 sw_entry->start, sw_entry->end,
10981 hw_entry->start, hw_entry->end);
10982 }
10983}
10984
91d1b4bd
DV		 10985static void
10986check_connector_state(struct drm_device *dev)
8af6cf88 10987{
8af6cf88
DV		 10988 struct intel_connector *connector;
10989
3a3371ff 10990 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 10991 /* This also checks the encoder/connector hw state with the
10992 * ->get_hw_state callbacks. */
10993 intel_connector_check_state(connector);
10994
e2c719b7 10995 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
8af6cf88
DV		 10996 "connector's staged encoder doesn't match current encoder\n");
10997 }
91d1b4bd
DV		 10998}
10999
11000static void
11001check_encoder_state(struct drm_device *dev)
11002{
11003 struct intel_encoder *encoder;
11004 struct intel_connector *connector;
8af6cf88 11005
b2784e15 11006 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 11007 bool enabled = false;
11008 bool active = false;
11009 enum pipe pipe, tracked_pipe;
11010
11011 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11012 encoder->base.base.id,
8e329a03 11013 encoder->base.name);
8af6cf88 11014
e2c719b7 11015 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
8af6cf88 11016 "encoder's stage crtc doesn't match current crtc\n");
e2c719b7 11017 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
8af6cf88
DV		 11018 "encoder's active_connectors set, but no crtc\n");
11019
3a3371ff 11020 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 11021 if (connector->base.encoder != &encoder->base)
11022 continue;
11023 enabled = true;
11024 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
11025 active = true;
11026 }
0e32b39c
DA		 11027 /*
11028 * for MST connectors if we unplug the connector is gone
11029 * away but the encoder is still connected to a crtc
11030 * until a modeset happens in response to the hotplug.
11031 */
11032 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
11033 continue;
11034
e2c719b7 11035 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 11036 "encoder's enabled state mismatch "
11037 "(expected %i, found %i)\n",
11038 !!encoder->base.crtc, enabled);
e2c719b7 11039 I915_STATE_WARN(active && !encoder->base.crtc,
8af6cf88
DV		 11040 "active encoder with no crtc\n");
11041
e2c719b7 11042 I915_STATE_WARN(encoder->connectors_active != active,
8af6cf88
DV		 11043 "encoder's computed active state doesn't match tracked active state "
11044 "(expected %i, found %i)\n", active, encoder->connectors_active);
11045
11046 active = encoder->get_hw_state(encoder, &pipe);
e2c719b7 11047 I915_STATE_WARN(active != encoder->connectors_active,
8af6cf88
DV		 11048 "encoder's hw state doesn't match sw tracking "
11049 "(expected %i, found %i)\n",
11050 encoder->connectors_active, active);
11051
11052 if (!encoder->base.crtc)
11053 continue;
11054
11055 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
e2c719b7 11056 I915_STATE_WARN(active && pipe != tracked_pipe,
8af6cf88
DV		 11057 "active encoder's pipe doesn't match"
11058 "(expected %i, found %i)\n",
11059 tracked_pipe, pipe);
11060
11061 }
91d1b4bd
DV		 11062}
11063
11064static void
11065check_crtc_state(struct drm_device *dev)
11066{
fbee40df 11067 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 11068 struct intel_crtc *crtc;
11069 struct intel_encoder *encoder;
5cec258b 11070 struct intel_crtc_state pipe_config;
8af6cf88 11071
d3fcc808 11072 for_each_intel_crtc(dev, crtc) {
8af6cf88
DV		 11073 bool enabled = false;
11074 bool active = false;
11075
045ac3b5
JB		 11076 memset(&pipe_config, 0, sizeof(pipe_config));
11077
8af6cf88
DV		 11078 DRM_DEBUG_KMS("[CRTC:%d]\n",
11079 crtc->base.base.id);
11080
83d65738 11081 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
8af6cf88
DV		 11082 "active crtc, but not enabled in sw tracking\n");
11083
b2784e15 11084 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 11085 if (encoder->base.crtc != &crtc->base)
11086 continue;
11087 enabled = true;
11088 if (encoder->connectors_active)
11089 active = true;
11090 }
6c49f241 11091
e2c719b7 11092 I915_STATE_WARN(active != crtc->active,
8af6cf88
DV		 11093 "crtc's computed active state doesn't match tracked active state "
11094 "(expected %i, found %i)\n", active, crtc->active);
83d65738 11095 I915_STATE_WARN(enabled != crtc->base.state->enable,
8af6cf88 11096 "crtc's computed enabled state doesn't match tracked enabled state "
83d65738
MR		 11097 "(expected %i, found %i)\n", enabled,
11098 crtc->base.state->enable);
8af6cf88 11099
0e8ffe1b
DV		 11100 active = dev_priv->display.get_pipe_config(crtc,
11101 &pipe_config);
d62cf62a 11102
b6b5d049
VS		 11103 /* hw state is inconsistent with the pipe quirk */
11104 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
11105 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
d62cf62a
DV		 11106 active = crtc->active;
11107
b2784e15 11108 for_each_intel_encoder(dev, encoder) {
3eaba51c 11109 enum pipe pipe;
6c49f241
DV		 11110 if (encoder->base.crtc != &crtc->base)
11111 continue;
1d37b689 11112 if (encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 11113 encoder->get_config(encoder, &pipe_config);
11114 }
11115
e2c719b7 11116 I915_STATE_WARN(crtc->active != active,
0e8ffe1b
DV		 11117 "crtc active state doesn't match with hw state "
11118 "(expected %i, found %i)\n", crtc->active, active);
11119
c0b03411 11120 if (active &&
6e3c9717 11121 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
e2c719b7 11122 I915_STATE_WARN(1, "pipe state doesn't match!\n");
c0b03411
DV		 11123 intel_dump_pipe_config(crtc, &pipe_config,
11124 "[hw state]");
6e3c9717 11125 intel_dump_pipe_config(crtc, crtc->config,
c0b03411
DV		 11126 "[sw state]");
11127 }
8af6cf88
DV		 11128 }
11129}
11130
91d1b4bd
DV		 11131static void
11132check_shared_dpll_state(struct drm_device *dev)
11133{
fbee40df 11134 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 11135 struct intel_crtc *crtc;
11136 struct intel_dpll_hw_state dpll_hw_state;
11137 int i;
5358901f
DV		 11138
11139 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11140 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11141 int enabled_crtcs = 0, active_crtcs = 0;
11142 bool active;
11143
11144 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11145
11146 DRM_DEBUG_KMS("%s\n", pll->name);
11147
11148 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
11149
e2c719b7 11150 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 11151 "more active pll users than references: %i vs %i\n",
3e369b76 11152 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 11153 I915_STATE_WARN(pll->active && !pll->on,
5358901f 11154 "pll in active use but not on in sw tracking\n");
e2c719b7 11155 I915_STATE_WARN(pll->on && !pll->active,
35c95375 11156 "pll in on but not on in use in sw tracking\n");
e2c719b7 11157 I915_STATE_WARN(pll->on != active,
5358901f
DV		 11158 "pll on state mismatch (expected %i, found %i)\n",
11159 pll->on, active);
11160
d3fcc808 11161 for_each_intel_crtc(dev, crtc) {
83d65738 11162 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 11163 enabled_crtcs++;
11164 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11165 active_crtcs++;
11166 }
e2c719b7 11167 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 11168 "pll active crtcs mismatch (expected %i, found %i)\n",
11169 pll->active, active_crtcs);
e2c719b7 11170 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 11171 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 11172 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 11173
e2c719b7 11174 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 11175 sizeof(dpll_hw_state)),
11176 "pll hw state mismatch\n");
5358901f 11177 }
8af6cf88
DV		 11178}
11179
91d1b4bd
DV		 11180void
11181intel_modeset_check_state(struct drm_device *dev)
11182{
08db6652 11183 check_wm_state(dev);
91d1b4bd
DV		 11184 check_connector_state(dev);
11185 check_encoder_state(dev);
11186 check_crtc_state(dev);
11187 check_shared_dpll_state(dev);
11188}
11189
5cec258b 11190void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 11191 int dotclock)
11192{
11193 /*
11194 * FDI already provided one idea for the dotclock.
11195 * Yell if the encoder disagrees.
11196 */
2d112de7 11197 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 11198 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 11199 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 11200}
11201
80715b2f
VS		 11202static void update_scanline_offset(struct intel_crtc *crtc)
11203{
11204 struct drm_device *dev = crtc->base.dev;
11205
11206 /*
11207 * The scanline counter increments at the leading edge of hsync.
11208 *
11209 * On most platforms it starts counting from vtotal-1 on the
11210 * first active line. That means the scanline counter value is
11211 * always one less than what we would expect. Ie. just after
11212 * start of vblank, which also occurs at start of hsync (on the
11213 * last active line), the scanline counter will read vblank_start-1.
11214 *
11215 * On gen2 the scanline counter starts counting from 1 instead
11216 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11217 * to keep the value positive), instead of adding one.
11218 *
11219 * On HSW+ the behaviour of the scanline counter depends on the output
11220 * type. For DP ports it behaves like most other platforms, but on HDMI
11221 * there's an extra 1 line difference. So we need to add two instead of
11222 * one to the value.
11223 */
11224 if (IS_GEN2(dev)) {
6e3c9717 11225 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 11226 int vtotal;
11227
11228 vtotal = mode->crtc_vtotal;
11229 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
11230 vtotal /= 2;
11231
11232 crtc->scanline_offset = vtotal - 1;
11233 } else if (HAS_DDI(dev) &&
409ee761 11234 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 11235 crtc->scanline_offset = 2;
11236 } else
11237 crtc->scanline_offset = 1;
11238}
11239
5cec258b 11240static struct intel_crtc_state *
7f27126e
JB		 11241intel_modeset_compute_config(struct drm_crtc *crtc,
11242 struct drm_display_mode *mode,
11243 struct drm_framebuffer *fb,
11244 unsigned *modeset_pipes,
11245 unsigned *prepare_pipes,
11246 unsigned *disable_pipes)
11247{
5cec258b 11248 struct intel_crtc_state *pipe_config = NULL;
7f27126e
JB		 11249
11250 intel_modeset_affected_pipes(crtc, modeset_pipes,
11251 prepare_pipes, disable_pipes);
11252
11253 if ((*modeset_pipes) == 0)
11254 goto out;
11255
11256 /*
11257 * Note this needs changes when we start tracking multiple modes
11258 * and crtcs. At that point we'll need to compute the whole config
11259 * (i.e. one pipe_config for each crtc) rather than just the one
11260 * for this crtc.
11261 */
11262 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
11263 if (IS_ERR(pipe_config)) {
11264 goto out;
11265 }
11266 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11267 "[modeset]");
7f27126e
JB		 11268
11269out:
11270 return pipe_config;
11271}
11272
ed6739ef
ACO		 11273static int __intel_set_mode_setup_plls(struct drm_device *dev,
11274 unsigned modeset_pipes,
11275 unsigned disable_pipes)
11276{
11277 struct drm_i915_private *dev_priv = to_i915(dev);
11278 unsigned clear_pipes = modeset_pipes | disable_pipes;
11279 struct intel_crtc *intel_crtc;
11280 int ret = 0;
11281
11282 if (!dev_priv->display.crtc_compute_clock)
11283 return 0;
11284
11285 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
11286 if (ret)
11287 goto done;
11288
11289 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11290 struct intel_crtc_state *state = intel_crtc->new_config;
11291 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11292 state);
11293 if (ret) {
11294 intel_shared_dpll_abort_config(dev_priv);
11295 goto done;
11296 }
11297 }
11298
11299done:
11300 return ret;
11301}
11302
f30da187
DV		 11303static int __intel_set_mode(struct drm_crtc *crtc,
11304 struct drm_display_mode *mode,
7f27126e 11305 int x, int y, struct drm_framebuffer *fb,
5cec258b 11306 struct intel_crtc_state *pipe_config,
7f27126e
JB		 11307 unsigned modeset_pipes,
11308 unsigned prepare_pipes,
11309 unsigned disable_pipes)
a6778b3c
DV		 11310{
11311 struct drm_device *dev = crtc->dev;
fbee40df 11312 struct drm_i915_private *dev_priv = dev->dev_private;
4b4b9238 11313 struct drm_display_mode *saved_mode;
25c5b266 11314 struct intel_crtc *intel_crtc;
c0c36b94 11315 int ret = 0;
a6778b3c 11316
4b4b9238 11317 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 11318 if (!saved_mode)
11319 return -ENOMEM;
a6778b3c 11320
3ac18232 11321 *saved_mode = crtc->mode;
a6778b3c 11322
b9950a13
VS		 11323 if (modeset_pipes)
11324 to_intel_crtc(crtc)->new_config = pipe_config;
11325
30a970c6
JB		 11326 /*
11327 * See if the config requires any additional preparation, e.g.
11328 * to adjust global state with pipes off. We need to do this
11329 * here so we can get the modeset_pipe updated config for the new
11330 * mode set on this crtc. For other crtcs we need to use the
11331 * adjusted_mode bits in the crtc directly.
11332 */
c164f833 11333 if (IS_VALLEYVIEW(dev)) {
2f2d7aa1 11334 valleyview_modeset_global_pipes(dev, &prepare_pipes);
30a970c6 11335
c164f833
VS		 11336 /* may have added more to prepare_pipes than we should */
11337 prepare_pipes &= ~disable_pipes;
11338 }
11339
ed6739ef
ACO		 11340 ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
11341 if (ret)
11342 goto done;
8bd31e67 11343
460da916
DV		 11344 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11345 intel_crtc_disable(&intel_crtc->base);
11346
ea9d758d 11347 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
83d65738 11348 if (intel_crtc->base.state->enable)
ea9d758d
DV		 11349 dev_priv->display.crtc_disable(&intel_crtc->base);
11350 }
a6778b3c 11351
6c4c86f5
DV		 11352 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11353 * to set it here already despite that we pass it down the callchain.
7f27126e
JB		 11354 *
11355 * Note we'll need to fix this up when we start tracking multiple
11356 * pipes; here we assume a single modeset_pipe and only track the
11357 * single crtc and mode.
f6e5b160 11358 */
b8cecdf5 11359 if (modeset_pipes) {
25c5b266 11360 crtc->mode = *mode;
b8cecdf5
DV		 11361 /* mode_set/enable/disable functions rely on a correct pipe
11362 * config. */
f5de6e07 11363 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
c326c0a9
VS		 11364
11365 /*
11366 * Calculate and store various constants which
11367 * are later needed by vblank and swap-completion
11368 * timestamping. They are derived from true hwmode.
11369 */
11370 drm_calc_timestamping_constants(crtc,
2d112de7 11371 &pipe_config->base.adjusted_mode);
b8cecdf5 11372 }
7758a113 11373
ea9d758d
DV		 11374 /* Only after disabling all output pipelines that will be changed can we
11375 * update the the output configuration. */
11376 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 11377
50f6e502 11378 modeset_update_crtc_power_domains(dev);
47fab737 11379
a6778b3c
DV		 11380 /* Set up the DPLL and any encoders state that needs to adjust or depend
11381 * on the DPLL.
f6e5b160 11382 */
25c5b266 11383 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
455a6808
GP		 11384 struct drm_plane *primary = intel_crtc->base.primary;
11385 int vdisplay, hdisplay;
4c10794f 11386
455a6808
GP		 11387 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11388 ret = primary->funcs->update_plane(primary, &intel_crtc->base,
11389 fb, 0, 0,
11390 hdisplay, vdisplay,
11391 x << 16, y << 16,
11392 hdisplay << 16, vdisplay << 16);
a6778b3c
DV		 11393 }
11394
11395 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
80715b2f
VS		 11396 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11397 update_scanline_offset(intel_crtc);
11398
25c5b266 11399 dev_priv->display.crtc_enable(&intel_crtc->base);
80715b2f 11400 }
a6778b3c 11401
a6778b3c
DV		 11402 /* FIXME: add subpixel order */
11403done:
83d65738 11404 if (ret && crtc->state->enable)
3ac18232 11405 crtc->mode = *saved_mode;
a6778b3c 11406
3ac18232 11407 kfree(saved_mode);
a6778b3c 11408 return ret;
f6e5b160
CW		 11409}
11410
7f27126e
JB		 11411static int intel_set_mode_pipes(struct drm_crtc *crtc,
11412 struct drm_display_mode *mode,
11413 int x, int y, struct drm_framebuffer *fb,
5cec258b 11414 struct intel_crtc_state *pipe_config,
7f27126e
JB		 11415 unsigned modeset_pipes,
11416 unsigned prepare_pipes,
11417 unsigned disable_pipes)
f30da187
DV		 11418{
11419 int ret;
11420
7f27126e
JB		 11421 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11422 prepare_pipes, disable_pipes);
f30da187
DV		 11423
11424 if (ret == 0)
11425 intel_modeset_check_state(crtc->dev);
11426
11427 return ret;
11428}
11429
7f27126e
JB		 11430static int intel_set_mode(struct drm_crtc *crtc,
11431 struct drm_display_mode *mode,
11432 int x, int y, struct drm_framebuffer *fb)
11433{
5cec258b 11434 struct intel_crtc_state *pipe_config;
7f27126e
JB		 11435 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11436
11437 pipe_config = intel_modeset_compute_config(crtc, mode, fb,
11438 &modeset_pipes,
11439 &prepare_pipes,
11440 &disable_pipes);
11441
11442 if (IS_ERR(pipe_config))
11443 return PTR_ERR(pipe_config);
11444
11445 return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11446 modeset_pipes, prepare_pipes,
11447 disable_pipes);
11448}
11449
c0c36b94
CW		 11450void intel_crtc_restore_mode(struct drm_crtc *crtc)
11451{
f4510a27 11452 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
c0c36b94
CW		 11453}
11454
25c5b266
DV		 11455#undef for_each_intel_crtc_masked
11456
d9e55608
DV		 11457static void intel_set_config_free(struct intel_set_config *config)
11458{
11459 if (!config)
11460 return;
11461
1aa4b628
DV		 11462 kfree(config->save_connector_encoders);
11463 kfree(config->save_encoder_crtcs);
7668851f 11464 kfree(config->save_crtc_enabled);
d9e55608
DV		 11465 kfree(config);
11466}
11467
85f9eb71
DV		 11468static int intel_set_config_save_state(struct drm_device *dev,
11469 struct intel_set_config *config)
11470{
7668851f 11471 struct drm_crtc *crtc;
85f9eb71
DV		 11472 struct drm_encoder *encoder;
11473 struct drm_connector *connector;
11474 int count;
11475
7668851f
VS		 11476 config->save_crtc_enabled =
11477 kcalloc(dev->mode_config.num_crtc,
11478 sizeof(bool), GFP_KERNEL);
11479 if (!config->save_crtc_enabled)
11480 return -ENOMEM;
11481
1aa4b628
DV		 11482 config->save_encoder_crtcs =
11483 kcalloc(dev->mode_config.num_encoder,
11484 sizeof(struct drm_crtc *), GFP_KERNEL);
11485 if (!config->save_encoder_crtcs)
85f9eb71
DV		 11486 return -ENOMEM;
11487
1aa4b628
DV		 11488 config->save_connector_encoders =
11489 kcalloc(dev->mode_config.num_connector,
11490 sizeof(struct drm_encoder *), GFP_KERNEL);
11491 if (!config->save_connector_encoders)
85f9eb71
DV		 11492 return -ENOMEM;
11493
11494 /* Copy data. Note that driver private data is not affected.
11495 * Should anything bad happen only the expected state is
11496 * restored, not the drivers personal bookkeeping.
11497 */
7668851f 11498 count = 0;
70e1e0ec 11499 for_each_crtc(dev, crtc) {
83d65738 11500 config->save_crtc_enabled[count++] = crtc->state->enable;
7668851f
VS		 11501 }
11502
85f9eb71
DV		 11503 count = 0;
11504 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 11505 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 11506 }
11507
11508 count = 0;
11509 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 11510 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 11511 }
11512
11513 return 0;
11514}
11515
11516static void intel_set_config_restore_state(struct drm_device *dev,
11517 struct intel_set_config *config)
11518{
7668851f 11519 struct intel_crtc *crtc;
9a935856
DV		 11520 struct intel_encoder *encoder;
11521 struct intel_connector *connector;
85f9eb71
DV		 11522 int count;
11523
7668851f 11524 count = 0;
d3fcc808 11525 for_each_intel_crtc(dev, crtc) {
7668851f 11526 crtc->new_enabled = config->save_crtc_enabled[count++];
7bd0a8e7
VS		 11527
11528 if (crtc->new_enabled)
6e3c9717 11529 crtc->new_config = crtc->config;
7bd0a8e7
VS		 11530 else
11531 crtc->new_config = NULL;
7668851f
VS		 11532 }
11533
85f9eb71 11534 count = 0;
b2784e15 11535 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 11536 encoder->new_crtc =
11537 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 11538 }
11539
11540 count = 0;
3a3371ff 11541 for_each_intel_connector(dev, connector) {
9a935856
DV		 11542 connector->new_encoder =
11543 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 11544 }
11545}
11546
e3de42b6 11547static bool
2e57f47d 11548is_crtc_connector_off(struct drm_mode_set *set)
e3de42b6
ID		 11549{
11550 int i;
11551
2e57f47d
CW		 11552 if (set->num_connectors == 0)
11553 return false;
11554
11555 if (WARN_ON(set->connectors == NULL))
11556 return false;
11557
11558 for (i = 0; i < set->num_connectors; i++)
11559 if (set->connectors[i]->encoder &&
11560 set->connectors[i]->encoder->crtc == set->crtc &&
11561 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
e3de42b6
ID		 11562 return true;
11563
11564 return false;
11565}
11566
5e2b584e
DV		 11567static void
11568intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11569 struct intel_set_config *config)
11570{
11571
11572 /* We should be able to check here if the fb has the same properties
11573 * and then just flip_or_move it */
2e57f47d
CW		 11574 if (is_crtc_connector_off(set)) {
11575 config->mode_changed = true;
f4510a27 11576 } else if (set->crtc->primary->fb != set->fb) {
3b150f08
MR		 11577 /*
11578 * If we have no fb, we can only flip as long as the crtc is
11579 * active, otherwise we need a full mode set. The crtc may
11580 * be active if we've only disabled the primary plane, or
11581 * in fastboot situations.
11582 */
f4510a27 11583 if (set->crtc->primary->fb == NULL) {
319d9827
JB		 11584 struct intel_crtc *intel_crtc =
11585 to_intel_crtc(set->crtc);
11586
3b150f08 11587 if (intel_crtc->active) {
319d9827
JB		 11588 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11589 config->fb_changed = true;
11590 } else {
11591 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11592 config->mode_changed = true;
11593 }
5e2b584e
DV		 11594 } else if (set->fb == NULL) {
11595 config->mode_changed = true;
72f4901e 11596 } else if (set->fb->pixel_format !=
f4510a27 11597 set->crtc->primary->fb->pixel_format) {
5e2b584e 11598 config->mode_changed = true;
e3de42b6 11599 } else {
5e2b584e 11600 config->fb_changed = true;
e3de42b6 11601 }
5e2b584e
DV		 11602 }
11603
835c5873 11604 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 11605 config->fb_changed = true;
11606
11607 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11608 DRM_DEBUG_KMS("modes are different, full mode set\n");
11609 drm_mode_debug_printmodeline(&set->crtc->mode);
11610 drm_mode_debug_printmodeline(set->mode);
11611 config->mode_changed = true;
11612 }
a1d95703
CW		 11613
11614 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11615 set->crtc->base.id, config->mode_changed, config->fb_changed);
5e2b584e
DV		 11616}
11617
2e431051 11618static int
9a935856
DV		 11619intel_modeset_stage_output_state(struct drm_device *dev,
11620 struct drm_mode_set *set,
11621 struct intel_set_config *config)
50f56119 11622{
9a935856
DV		 11623 struct intel_connector *connector;
11624 struct intel_encoder *encoder;
7668851f 11625 struct intel_crtc *crtc;
f3f08572 11626 int ro;
50f56119 11627
9abdda74 11628 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 11629 * of connectors. For paranoia, double-check this. */
11630 WARN_ON(!set->fb && (set->num_connectors != 0));
11631 WARN_ON(set->fb && (set->num_connectors == 0));
11632
3a3371ff 11633 for_each_intel_connector(dev, connector) {
9a935856
DV		 11634 /* Otherwise traverse passed in connector list and get encoders
11635 * for them. */
50f56119 11636 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 11637 if (set->connectors[ro] == &connector->base) {
0e32b39c 11638 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
50f56119
DV		 11639 break;
11640 }
11641 }
11642
9a935856
DV		 11643 /* If we disable the crtc, disable all its connectors. Also, if
11644 * the connector is on the changing crtc but not on the new
11645 * connector list, disable it. */
11646 if ((!set->fb || ro == set->num_connectors) &&
11647 connector->base.encoder &&
11648 connector->base.encoder->crtc == set->crtc) {
11649 connector->new_encoder = NULL;
11650
11651 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11652 connector->base.base.id,
c23cc417 11653 connector->base.name);
9a935856
DV		 11654 }
11655
11656
11657 if (&connector->new_encoder->base != connector->base.encoder) {
10634189
ACO		 11658 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n",
11659 connector->base.base.id,
11660 connector->base.name);
5e2b584e 11661 config->mode_changed = true;
50f56119
DV		 11662 }
11663 }
9a935856 11664 /* connector->new_encoder is now updated for all connectors. */
50f56119 11665
9a935856 11666 /* Update crtc of enabled connectors. */
3a3371ff 11667 for_each_intel_connector(dev, connector) {
7668851f
VS		 11668 struct drm_crtc *new_crtc;
11669
9a935856 11670 if (!connector->new_encoder)
50f56119
DV		 11671 continue;
11672
9a935856 11673 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 11674
11675 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 11676 if (set->connectors[ro] == &connector->base)
50f56119
DV		 11677 new_crtc = set->crtc;
11678 }
11679
11680 /* Make sure the new CRTC will work with the encoder */
14509916
TR		 11681 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11682 new_crtc)) {
5e2b584e 11683 return -EINVAL;
50f56119 11684 }
0e32b39c 11685 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
9a935856
DV		 11686
11687 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11688 connector->base.base.id,
c23cc417 11689 connector->base.name,
9a935856
DV		 11690 new_crtc->base.id);
11691 }
11692
11693 /* Check for any encoders that needs to be disabled. */
b2784e15 11694 for_each_intel_encoder(dev, encoder) {
5a65f358 11695 int num_connectors = 0;
3a3371ff 11696 for_each_intel_connector(dev, connector) {
9a935856
DV		 11697 if (connector->new_encoder == encoder) {
11698 WARN_ON(!connector->new_encoder->new_crtc);
5a65f358 11699 num_connectors++;
9a935856
DV		 11700 }
11701 }
5a65f358
PZ		 11702
11703 if (num_connectors == 0)
11704 encoder->new_crtc = NULL;
11705 else if (num_connectors > 1)
11706 return -EINVAL;
11707
9a935856
DV		 11708 /* Only now check for crtc changes so we don't miss encoders
11709 * that will be disabled. */
11710 if (&encoder->new_crtc->base != encoder->base.crtc) {
10634189
ACO		 11711 DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n",
11712 encoder->base.base.id,
11713 encoder->base.name);
5e2b584e 11714 config->mode_changed = true;
50f56119
DV		 11715 }
11716 }
9a935856 11717 /* Now we've also updated encoder->new_crtc for all encoders. */
3a3371ff 11718 for_each_intel_connector(dev, connector) {
0e32b39c
DA		 11719 if (connector->new_encoder)
11720 if (connector->new_encoder != connector->encoder)
11721 connector->encoder = connector->new_encoder;
11722 }
d3fcc808 11723 for_each_intel_crtc(dev, crtc) {
7668851f
VS		 11724 crtc->new_enabled = false;
11725
b2784e15 11726 for_each_intel_encoder(dev, encoder) {
7668851f
VS		 11727 if (encoder->new_crtc == crtc) {
11728 crtc->new_enabled = true;
11729 break;
11730 }
11731 }
11732
83d65738 11733 if (crtc->new_enabled != crtc->base.state->enable) {
10634189
ACO		 11734 DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n",
11735 crtc->base.base.id,
7668851f
VS		 11736 crtc->new_enabled ? "en" : "dis");
11737 config->mode_changed = true;
11738 }
7bd0a8e7
VS		 11739
11740 if (crtc->new_enabled)
6e3c9717 11741 crtc->new_config = crtc->config;
7bd0a8e7
VS		 11742 else
11743 crtc->new_config = NULL;
7668851f
VS		 11744 }
11745
2e431051
DV		 11746 return 0;
11747}
11748
7d00a1f5
VS		 11749static void disable_crtc_nofb(struct intel_crtc *crtc)
11750{
11751 struct drm_device *dev = crtc->base.dev;
11752 struct intel_encoder *encoder;
11753 struct intel_connector *connector;
11754
11755 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11756 pipe_name(crtc->pipe));
11757
3a3371ff 11758 for_each_intel_connector(dev, connector) {
7d00a1f5
VS		 11759 if (connector->new_encoder &&
11760 connector->new_encoder->new_crtc == crtc)
11761 connector->new_encoder = NULL;
11762 }
11763
b2784e15 11764 for_each_intel_encoder(dev, encoder) {
7d00a1f5
VS		 11765 if (encoder->new_crtc == crtc)
11766 encoder->new_crtc = NULL;
11767 }
11768
11769 crtc->new_enabled = false;
7bd0a8e7 11770 crtc->new_config = NULL;
7d00a1f5
VS		 11771}
11772
2e431051
DV		 11773static int intel_crtc_set_config(struct drm_mode_set *set)
11774{
11775 struct drm_device *dev;
2e431051
DV		 11776 struct drm_mode_set save_set;
11777 struct intel_set_config *config;
5cec258b 11778 struct intel_crtc_state *pipe_config;
50f52756 11779 unsigned modeset_pipes, prepare_pipes, disable_pipes;
2e431051 11780 int ret;
2e431051 11781
8d3e375e
DV		 11782 BUG_ON(!set);
11783 BUG_ON(!set->crtc);
11784 BUG_ON(!set->crtc->helper_private);
2e431051 11785
7e53f3a4
DV		 11786 /* Enforce sane interface api - has been abused by the fb helper. */
11787 BUG_ON(!set->mode && set->fb);
11788 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 11789
2e431051
DV		 11790 if (set->fb) {
11791 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11792 set->crtc->base.id, set->fb->base.id,
11793 (int)set->num_connectors, set->x, set->y);
11794 } else {
11795 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 11796 }
11797
11798 dev = set->crtc->dev;
11799
11800 ret = -ENOMEM;
11801 config = kzalloc(sizeof(*config), GFP_KERNEL);
11802 if (!config)
11803 goto out_config;
11804
11805 ret = intel_set_config_save_state(dev, config);
11806 if (ret)
11807 goto out_config;
11808
11809 save_set.crtc = set->crtc;
11810 save_set.mode = &set->crtc->mode;
11811 save_set.x = set->crtc->x;
11812 save_set.y = set->crtc->y;
f4510a27 11813 save_set.fb = set->crtc->primary->fb;
2e431051
DV		 11814
11815 /* Compute whether we need a full modeset, only an fb base update or no
11816 * change at all. In the future we might also check whether only the
11817 * mode changed, e.g. for LVDS where we only change the panel fitter in
11818 * such cases. */
11819 intel_set_config_compute_mode_changes(set, config);
11820
9a935856 11821 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 11822 if (ret)
11823 goto fail;
11824
50f52756
JB		 11825 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
11826 set->fb,
11827 &modeset_pipes,
11828 &prepare_pipes,
11829 &disable_pipes);
20664591 11830 if (IS_ERR(pipe_config)) {
6ac0483b 11831 ret = PTR_ERR(pipe_config);
50f52756 11832 goto fail;
20664591 11833 } else if (pipe_config) {
b9950a13 11834 if (pipe_config->has_audio !=
6e3c9717 11835 to_intel_crtc(set->crtc)->config->has_audio)
20664591
JB		 11836 config->mode_changed = true;
11837
af15d2ce
JB		 11838 /*
11839 * Note we have an issue here with infoframes: current code
11840 * only updates them on the full mode set path per hw
11841 * requirements. So here we should be checking for any
11842 * required changes and forcing a mode set.
11843 */
20664591 11844 }
50f52756
JB		 11845
11846 /* set_mode will free it in the mode_changed case */
11847 if (!config->mode_changed)
11848 kfree(pipe_config);
11849
1f9954d0
JB		 11850 intel_update_pipe_size(to_intel_crtc(set->crtc));
11851
5e2b584e 11852 if (config->mode_changed) {
50f52756
JB		 11853 ret = intel_set_mode_pipes(set->crtc, set->mode,
11854 set->x, set->y, set->fb, pipe_config,
11855 modeset_pipes, prepare_pipes,
11856 disable_pipes);
5e2b584e 11857 } else if (config->fb_changed) {
3b150f08 11858 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
455a6808
GP		 11859 struct drm_plane *primary = set->crtc->primary;
11860 int vdisplay, hdisplay;
3b150f08 11861
455a6808
GP		 11862 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
11863 ret = primary->funcs->update_plane(primary, set->crtc, set->fb,
11864 0, 0, hdisplay, vdisplay,
11865 set->x << 16, set->y << 16,
11866 hdisplay << 16, vdisplay << 16);
3b150f08
MR		 11867
11868 /*
11869 * We need to make sure the primary plane is re-enabled if it
11870 * has previously been turned off.
11871 */
11872 if (!intel_crtc->primary_enabled && ret == 0) {
11873 WARN_ON(!intel_crtc->active);
fdd508a6 11874 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
3b150f08
MR		 11875 }
11876
7ca51a3a
JB		 11877 /*
11878 * In the fastboot case this may be our only check of the
11879 * state after boot. It would be better to only do it on
11880 * the first update, but we don't have a nice way of doing that
11881 * (and really, set_config isn't used much for high freq page
11882 * flipping, so increasing its cost here shouldn't be a big
11883 * deal).
11884 */
d330a953 11885 if (i915.fastboot && ret == 0)
7ca51a3a 11886 intel_modeset_check_state(set->crtc->dev);
50f56119
DV		 11887 }
11888
2d05eae1 11889 if (ret) {
bf67dfeb
DV		 11890 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11891 set->crtc->base.id, ret);
50f56119 11892fail:
2d05eae1 11893 intel_set_config_restore_state(dev, config);
50f56119 11894
7d00a1f5
VS		 11895 /*
11896 * HACK: if the pipe was on, but we didn't have a framebuffer,
11897 * force the pipe off to avoid oopsing in the modeset code
11898 * due to fb==NULL. This should only happen during boot since
11899 * we don't yet reconstruct the FB from the hardware state.
11900 */
11901 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11902 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11903
2d05eae1
CW		 11904 /* Try to restore the config */
11905 if (config->mode_changed &&
11906 intel_set_mode(save_set.crtc, save_set.mode,
11907 save_set.x, save_set.y, save_set.fb))
11908 DRM_ERROR("failed to restore config after modeset failure\n");
11909 }
50f56119 11910
d9e55608
DV		 11911out_config:
11912 intel_set_config_free(config);
50f56119
DV		 11913 return ret;
11914}
f6e5b160
CW		 11915
11916static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 11917 .gamma_set = intel_crtc_gamma_set,
50f56119 11918 .set_config = intel_crtc_set_config,
f6e5b160
CW		 11919 .destroy = intel_crtc_destroy,
11920 .page_flip = intel_crtc_page_flip,
1356837e
MR		 11921 .atomic_duplicate_state = intel_crtc_duplicate_state,
11922 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 11923};
11924
5358901f
DV		 11925static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11926 struct intel_shared_dpll *pll,
11927 struct intel_dpll_hw_state *hw_state)
ee7b9f93 11928{
5358901f 11929 uint32_t val;
ee7b9f93 11930
f458ebbc 11931 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 11932 return false;
11933
5358901f 11934 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 11935 hw_state->dpll = val;
11936 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11937 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 11938
11939 return val & DPLL_VCO_ENABLE;
11940}
11941
15bdd4cf
DV		 11942static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11943 struct intel_shared_dpll *pll)
11944{
3e369b76
ACO		 11945 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11946 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 11947}
11948
e7b903d2
DV		 11949static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11950 struct intel_shared_dpll *pll)
11951{
e7b903d2 11952 /* PCH refclock must be enabled first */
89eff4be 11953 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 11954
3e369b76 11955 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 11956
11957 /* Wait for the clocks to stabilize. */
11958 POSTING_READ(PCH_DPLL(pll->id));
11959 udelay(150);
11960
11961 /* The pixel multiplier can only be updated once the
11962 * DPLL is enabled and the clocks are stable.
11963 *
11964 * So write it again.
11965 */
3e369b76 11966 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 11967 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 11968 udelay(200);
11969}
11970
11971static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11972 struct intel_shared_dpll *pll)
11973{
11974 struct drm_device *dev = dev_priv->dev;
11975 struct intel_crtc *crtc;
e7b903d2
DV		 11976
11977 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 11978 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 11979 if (intel_crtc_to_shared_dpll(crtc) == pll)
11980 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 11981 }
11982
15bdd4cf
DV		 11983 I915_WRITE(PCH_DPLL(pll->id), 0);
11984 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 11985 udelay(200);
11986}
11987
46edb027
DV		 11988static char *ibx_pch_dpll_names[] = {
11989 "PCH DPLL A",
11990 "PCH DPLL B",
11991};
11992
7c74ade1 11993static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 11994{
e7b903d2 11995 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 11996 int i;
11997
7c74ade1 11998 dev_priv->num_shared_dpll = 2;
ee7b9f93 11999
e72f9fbf 12000 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 12001 dev_priv->shared_dplls[i].id = i;
12002 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 12003 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 12004 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
12005 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 12006 dev_priv->shared_dplls[i].get_hw_state =
12007 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 12008 }
12009}
12010
7c74ade1
DV		 12011static void intel_shared_dpll_init(struct drm_device *dev)
12012{
e7b903d2 12013 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 12014
9cd86933
DV		 12015 if (HAS_DDI(dev))
12016 intel_ddi_pll_init(dev);
12017 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 12018 ibx_pch_dpll_init(dev);
12019 else
12020 dev_priv->num_shared_dpll = 0;
12021
12022 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 12023}
12024
6beb8c23
MR		 12025/**
12026 * intel_prepare_plane_fb - Prepare fb for usage on plane
12027 * @plane: drm plane to prepare for
12028 * @fb: framebuffer to prepare for presentation
12029 *
12030 * Prepares a framebuffer for usage on a display plane. Generally this
12031 * involves pinning the underlying object and updating the frontbuffer tracking
12032 * bits. Some older platforms need special physical address handling for
12033 * cursor planes.
12034 *
12035 * Returns 0 on success, negative error code on failure.
12036 */
12037int
12038intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee
TU		 12039 struct drm_framebuffer *fb,
12040 const struct drm_plane_state *new_state)
465c120c
MR		 12041{
12042 struct drm_device *dev = plane->dev;
6beb8c23
MR		 12043 struct intel_plane *intel_plane = to_intel_plane(plane);
12044 enum pipe pipe = intel_plane->pipe;
12045 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12046 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
12047 unsigned frontbuffer_bits = 0;
12048 int ret = 0;
465c120c 12049
ea2c67bb 12050 if (!obj)
465c120c
MR		 12051 return 0;
12052
6beb8c23
MR		 12053 switch (plane->type) {
12054 case DRM_PLANE_TYPE_PRIMARY:
12055 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
12056 break;
12057 case DRM_PLANE_TYPE_CURSOR:
12058 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
12059 break;
12060 case DRM_PLANE_TYPE_OVERLAY:
12061 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
12062 break;
12063 }
465c120c 12064
6beb8c23 12065 mutex_lock(&dev->struct_mutex);
465c120c 12066
6beb8c23
MR		 12067 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
12068 INTEL_INFO(dev)->cursor_needs_physical) {
12069 int align = IS_I830(dev) ? 16 * 1024 : 256;
12070 ret = i915_gem_object_attach_phys(obj, align);
12071 if (ret)
12072 DRM_DEBUG_KMS("failed to attach phys object\n");
12073 } else {
82bc3b2d 12074 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
6beb8c23 12075 }
465c120c 12076
6beb8c23
MR		 12077 if (ret == 0)
12078 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
fdd508a6 12079
4c34574f 12080 mutex_unlock(&dev->struct_mutex);
465c120c 12081
6beb8c23
MR		 12082 return ret;
12083}
12084
38f3ce3a
MR		 12085/**
12086 * intel_cleanup_plane_fb - Cleans up an fb after plane use
12087 * @plane: drm plane to clean up for
12088 * @fb: old framebuffer that was on plane
12089 *
12090 * Cleans up a framebuffer that has just been removed from a plane.
12091 */
12092void
12093intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee
TU		 12094 struct drm_framebuffer *fb,
12095 const struct drm_plane_state *old_state)
38f3ce3a
MR		 12096{
12097 struct drm_device *dev = plane->dev;
12098 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12099
12100 if (WARN_ON(!obj))
12101 return;
12102
12103 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
12104 !INTEL_INFO(dev)->cursor_needs_physical) {
12105 mutex_lock(&dev->struct_mutex);
82bc3b2d 12106 intel_unpin_fb_obj(fb, old_state);
38f3ce3a
MR		 12107 mutex_unlock(&dev->struct_mutex);
12108 }
465c120c
MR		 12109}
12110
12111static int
3c692a41
GP		 12112intel_check_primary_plane(struct drm_plane *plane,
12113 struct intel_plane_state *state)
12114{
32b7eeec
MR		 12115 struct drm_device *dev = plane->dev;
12116 struct drm_i915_private *dev_priv = dev->dev_private;
2b875c22 12117 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 12118 struct intel_crtc *intel_crtc;
2b875c22 12119 struct drm_framebuffer *fb = state->base.fb;
3c692a41
GP		 12120 struct drm_rect *dest = &state->dst;
12121 struct drm_rect *src = &state->src;
12122 const struct drm_rect *clip = &state->clip;
465c120c
MR		 12123 int ret;
12124
ea2c67bb
MR		 12125 crtc = crtc ? crtc : plane->crtc;
12126 intel_crtc = to_intel_crtc(crtc);
12127
c59cb179
MR		 12128 ret = drm_plane_helper_check_update(plane, crtc, fb,
12129 src, dest, clip,
12130 DRM_PLANE_HELPER_NO_SCALING,
12131 DRM_PLANE_HELPER_NO_SCALING,
12132 false, true, &state->visible);
12133 if (ret)
12134 return ret;
465c120c 12135
32b7eeec
MR		 12136 if (intel_crtc->active) {
12137 intel_crtc->atomic.wait_for_flips = true;
12138
12139 /*
12140 * FBC does not work on some platforms for rotated
12141 * planes, so disable it when rotation is not 0 and
12142 * update it when rotation is set back to 0.
12143 *
12144 * FIXME: This is redundant with the fbc update done in
12145 * the primary plane enable function except that that
12146 * one is done too late. We eventually need to unify
12147 * this.
12148 */
12149 if (intel_crtc->primary_enabled &&
12150 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
e35fef21 12151 dev_priv->fbc.crtc == intel_crtc &&
8e7d688b 12152 state->base.rotation != BIT(DRM_ROTATE_0)) {
32b7eeec
MR		 12153 intel_crtc->atomic.disable_fbc = true;
12154 }
12155
12156 if (state->visible) {
12157 /*
12158 * BDW signals flip done immediately if the plane
12159 * is disabled, even if the plane enable is already
12160 * armed to occur at the next vblank :(
12161 */
12162 if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
12163 intel_crtc->atomic.wait_vblank = true;
12164 }
12165
12166 intel_crtc->atomic.fb_bits |=
12167 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
12168
12169 intel_crtc->atomic.update_fbc = true;
0fda6568
TU		 12170
12171 /* Update watermarks on tiling changes. */
12172 if (!plane->state->fb || !state->base.fb ||
12173 plane->state->fb->modifier[0] !=
12174 state->base.fb->modifier[0])
12175 intel_crtc->atomic.update_wm = true;
ccc759dc
GP		 12176 }
12177
14af293f
GP		 12178 return 0;
12179}
12180
12181static void
12182intel_commit_primary_plane(struct drm_plane *plane,
12183 struct intel_plane_state *state)
12184{
2b875c22
MR		 12185 struct drm_crtc *crtc = state->base.crtc;
12186 struct drm_framebuffer *fb = state->base.fb;
12187 struct drm_device *dev = plane->dev;
14af293f 12188 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 12189 struct intel_crtc *intel_crtc;
14af293f
GP		 12190 struct drm_rect *src = &state->src;
12191
ea2c67bb
MR		 12192 crtc = crtc ? crtc : plane->crtc;
12193 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR		 12194
12195 plane->fb = fb;
9dc806fc
MR		 12196 crtc->x = src->x1 >> 16;
12197 crtc->y = src->y1 >> 16;
ccc759dc 12198
ccc759dc 12199 if (intel_crtc->active) {
ccc759dc 12200 if (state->visible) {
ccc759dc
GP		 12201 /* FIXME: kill this fastboot hack */
12202 intel_update_pipe_size(intel_crtc);
465c120c 12203
ccc759dc 12204 intel_crtc->primary_enabled = true;
465c120c 12205
ccc759dc
GP		 12206 dev_priv->display.update_primary_plane(crtc, plane->fb,
12207 crtc->x, crtc->y);
ccc759dc
GP		 12208 } else {
12209 /*
12210 * If clipping results in a non-visible primary plane,
12211 * we'll disable the primary plane. Note that this is
12212 * a bit different than what happens if userspace
12213 * explicitly disables the plane by passing fb=0
12214 * because plane->fb still gets set and pinned.
12215 */
12216 intel_disable_primary_hw_plane(plane, crtc);
48404c1e 12217 }
ccc759dc 12218 }
465c120c
MR		 12219}
12220
32b7eeec 12221static void intel_begin_crtc_commit(struct drm_crtc *crtc)
3c692a41 12222{
32b7eeec 12223 struct drm_device *dev = crtc->dev;
140fd38d 12224 struct drm_i915_private *dev_priv = dev->dev_private;
3c692a41 12225 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ea2c67bb
MR		 12226 struct intel_plane *intel_plane;
12227 struct drm_plane *p;
12228 unsigned fb_bits = 0;
12229
12230 /* Track fb's for any planes being disabled */
12231 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
12232 intel_plane = to_intel_plane(p);
12233
12234 if (intel_crtc->atomic.disabled_planes &
12235 (1 << drm_plane_index(p))) {
12236 switch (p->type) {
12237 case DRM_PLANE_TYPE_PRIMARY:
12238 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
12239 break;
12240 case DRM_PLANE_TYPE_CURSOR:
12241 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
12242 break;
12243 case DRM_PLANE_TYPE_OVERLAY:
12244 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
12245 break;
12246 }
3c692a41 12247
ea2c67bb
MR		 12248 mutex_lock(&dev->struct_mutex);
12249 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
12250 mutex_unlock(&dev->struct_mutex);
12251 }
12252 }
3c692a41 12253
32b7eeec
MR		 12254 if (intel_crtc->atomic.wait_for_flips)
12255 intel_crtc_wait_for_pending_flips(crtc);
3c692a41 12256
32b7eeec
MR		 12257 if (intel_crtc->atomic.disable_fbc)
12258 intel_fbc_disable(dev);
3c692a41 12259
32b7eeec
MR		 12260 if (intel_crtc->atomic.pre_disable_primary)
12261 intel_pre_disable_primary(crtc);
3c692a41 12262
32b7eeec
MR		 12263 if (intel_crtc->atomic.update_wm)
12264 intel_update_watermarks(crtc);
3c692a41 12265
32b7eeec 12266 intel_runtime_pm_get(dev_priv);
3c692a41 12267
c34c9ee4
MR		 12268 /* Perform vblank evasion around commit operation */
12269 if (intel_crtc->active)
12270 intel_crtc->atomic.evade =
12271 intel_pipe_update_start(intel_crtc,
12272 &intel_crtc->atomic.start_vbl_count);
32b7eeec
MR		 12273}
12274
12275static void intel_finish_crtc_commit(struct drm_crtc *crtc)
12276{
12277 struct drm_device *dev = crtc->dev;
12278 struct drm_i915_private *dev_priv = dev->dev_private;
12279 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12280 struct drm_plane *p;
12281
c34c9ee4
MR		 12282 if (intel_crtc->atomic.evade)
12283 intel_pipe_update_end(intel_crtc,
12284 intel_crtc->atomic.start_vbl_count);
3c692a41 12285
140fd38d 12286 intel_runtime_pm_put(dev_priv);
3c692a41 12287
32b7eeec
MR		 12288 if (intel_crtc->atomic.wait_vblank)
12289 intel_wait_for_vblank(dev, intel_crtc->pipe);
12290
12291 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
12292
12293 if (intel_crtc->atomic.update_fbc) {
ccc759dc 12294 mutex_lock(&dev->struct_mutex);
7ff0ebcc 12295 intel_fbc_update(dev);
ccc759dc 12296 mutex_unlock(&dev->struct_mutex);
38f3ce3a 12297 }
3c692a41 12298
32b7eeec
MR		 12299 if (intel_crtc->atomic.post_enable_primary)
12300 intel_post_enable_primary(crtc);
3c692a41 12301
32b7eeec
MR		 12302 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
12303 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
12304 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
12305 false, false);
12306
12307 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
3c692a41
GP		 12308}
12309
cf4c7c12 12310/**
4a3b8769
MR		 12311 * intel_plane_destroy - destroy a plane
12312 * @plane: plane to destroy
cf4c7c12 12313 *
4a3b8769
MR		 12314 * Common destruction function for all types of planes (primary, cursor,
12315 * sprite).
cf4c7c12 12316 */
4a3b8769 12317void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 12318{
12319 struct intel_plane *intel_plane = to_intel_plane(plane);
12320 drm_plane_cleanup(plane);
12321 kfree(intel_plane);
12322}
12323
65a3fea0 12324const struct drm_plane_funcs intel_plane_funcs = {
ff42e093
DV		 12325 .update_plane = drm_plane_helper_update,
12326 .disable_plane = drm_plane_helper_disable,
3d7d6510 12327 .destroy = intel_plane_destroy,
c196e1d6 12328 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 12329 .atomic_get_property = intel_plane_atomic_get_property,
12330 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 12331 .atomic_duplicate_state = intel_plane_duplicate_state,
12332 .atomic_destroy_state = intel_plane_destroy_state,
12333
465c120c
MR		 12334};
12335
12336static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
12337 int pipe)
12338{
12339 struct intel_plane *primary;
8e7d688b 12340 struct intel_plane_state *state;
465c120c
MR		 12341 const uint32_t *intel_primary_formats;
12342 int num_formats;
12343
12344 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12345 if (primary == NULL)
12346 return NULL;
12347
8e7d688b
MR		 12348 state = intel_create_plane_state(&primary->base);
12349 if (!state) {
ea2c67bb
MR		 12350 kfree(primary);
12351 return NULL;
12352 }
8e7d688b 12353 primary->base.state = &state->base;
ea2c67bb 12354
465c120c
MR		 12355 primary->can_scale = false;
12356 primary->max_downscale = 1;
12357 primary->pipe = pipe;
12358 primary->plane = pipe;
c59cb179
MR		 12359 primary->check_plane = intel_check_primary_plane;
12360 primary->commit_plane = intel_commit_primary_plane;
465c120c
MR		 12361 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12362 primary->plane = !pipe;
12363
12364 if (INTEL_INFO(dev)->gen <= 3) {
12365 intel_primary_formats = intel_primary_formats_gen2;
12366 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12367 } else {
12368 intel_primary_formats = intel_primary_formats_gen4;
12369 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12370 }
12371
12372 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 12373 &intel_plane_funcs,
465c120c
MR		 12374 intel_primary_formats, num_formats,
12375 DRM_PLANE_TYPE_PRIMARY);
48404c1e
SJ		 12376
12377 if (INTEL_INFO(dev)->gen >= 4) {
12378 if (!dev->mode_config.rotation_property)
12379 dev->mode_config.rotation_property =
12380 drm_mode_create_rotation_property(dev,
12381 BIT(DRM_ROTATE_0) |
12382 BIT(DRM_ROTATE_180));
12383 if (dev->mode_config.rotation_property)
12384 drm_object_attach_property(&primary->base.base,
12385 dev->mode_config.rotation_property,
8e7d688b 12386 state->base.rotation);
48404c1e
SJ		 12387 }
12388
ea2c67bb
MR		 12389 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
12390
465c120c
MR		 12391 return &primary->base;
12392}
12393
3d7d6510 12394static int
852e787c
GP		 12395intel_check_cursor_plane(struct drm_plane *plane,
12396 struct intel_plane_state *state)
3d7d6510 12397{
2b875c22 12398 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 12399 struct drm_device *dev = plane->dev;
2b875c22 12400 struct drm_framebuffer *fb = state->base.fb;
852e787c
GP		 12401 struct drm_rect *dest = &state->dst;
12402 struct drm_rect *src = &state->src;
12403 const struct drm_rect *clip = &state->clip;
757f9a3e 12404 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
ea2c67bb 12405 struct intel_crtc *intel_crtc;
757f9a3e
GP		 12406 unsigned stride;
12407 int ret;
3d7d6510 12408
ea2c67bb
MR		 12409 crtc = crtc ? crtc : plane->crtc;
12410 intel_crtc = to_intel_crtc(crtc);
12411
757f9a3e 12412 ret = drm_plane_helper_check_update(plane, crtc, fb,
852e787c 12413 src, dest, clip,
3d7d6510
MR		 12414 DRM_PLANE_HELPER_NO_SCALING,
12415 DRM_PLANE_HELPER_NO_SCALING,
852e787c 12416 true, true, &state->visible);
757f9a3e
GP		 12417 if (ret)
12418 return ret;
12419
12420
12421 /* if we want to turn off the cursor ignore width and height */
12422 if (!obj)
32b7eeec 12423 goto finish;
757f9a3e 12424
757f9a3e 12425 /* Check for which cursor types we support */
ea2c67bb
MR		 12426 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
12427 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12428 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 12429 return -EINVAL;
12430 }
12431
ea2c67bb
MR		 12432 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
12433 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 12434 DRM_DEBUG_KMS("buffer is too small\n");
12435 return -ENOMEM;
12436 }
12437
3a656b54 12438 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e
GP		 12439 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12440 ret = -EINVAL;
12441 }
757f9a3e 12442
32b7eeec
MR		 12443finish:
12444 if (intel_crtc->active) {
3749f463 12445 if (plane->state->crtc_w != state->base.crtc_w)
32b7eeec
MR		 12446 intel_crtc->atomic.update_wm = true;
12447
12448 intel_crtc->atomic.fb_bits |=
12449 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
12450 }
12451
757f9a3e 12452 return ret;
852e787c 12453}
3d7d6510 12454
f4a2cf29 12455static void
852e787c
GP		 12456intel_commit_cursor_plane(struct drm_plane *plane,
12457 struct intel_plane_state *state)
12458{
2b875c22 12459 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 12460 struct drm_device *dev = plane->dev;
12461 struct intel_crtc *intel_crtc;
2b875c22 12462 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 12463 uint32_t addr;
852e787c 12464
ea2c67bb
MR		 12465 crtc = crtc ? crtc : plane->crtc;
12466 intel_crtc = to_intel_crtc(crtc);
12467
2b875c22 12468 plane->fb = state->base.fb;
ea2c67bb
MR		 12469 crtc->cursor_x = state->base.crtc_x;
12470 crtc->cursor_y = state->base.crtc_y;
12471
a912f12f
GP		 12472 if (intel_crtc->cursor_bo == obj)
12473 goto update;
4ed91096 12474
f4a2cf29 12475 if (!obj)
a912f12f 12476 addr = 0;
f4a2cf29 12477 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 12478 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 12479 else
a912f12f 12480 addr = obj->phys_handle->busaddr;
852e787c 12481
a912f12f
GP		 12482 intel_crtc->cursor_addr = addr;
12483 intel_crtc->cursor_bo = obj;
12484update:
852e787c 12485
32b7eeec 12486 if (intel_crtc->active)
a912f12f 12487 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 12488}
12489
3d7d6510
MR		 12490static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12491 int pipe)
12492{
12493 struct intel_plane *cursor;
8e7d688b 12494 struct intel_plane_state *state;
3d7d6510
MR		 12495
12496 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12497 if (cursor == NULL)
12498 return NULL;
12499
8e7d688b
MR		 12500 state = intel_create_plane_state(&cursor->base);
12501 if (!state) {
ea2c67bb
MR		 12502 kfree(cursor);
12503 return NULL;
12504 }
8e7d688b 12505 cursor->base.state = &state->base;
ea2c67bb 12506
3d7d6510
MR		 12507 cursor->can_scale = false;
12508 cursor->max_downscale = 1;
12509 cursor->pipe = pipe;
12510 cursor->plane = pipe;
c59cb179
MR		 12511 cursor->check_plane = intel_check_cursor_plane;
12512 cursor->commit_plane = intel_commit_cursor_plane;
3d7d6510
MR		 12513
12514 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 12515 &intel_plane_funcs,
3d7d6510
MR		 12516 intel_cursor_formats,
12517 ARRAY_SIZE(intel_cursor_formats),
12518 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 12519
12520 if (INTEL_INFO(dev)->gen >= 4) {
12521 if (!dev->mode_config.rotation_property)
12522 dev->mode_config.rotation_property =
12523 drm_mode_create_rotation_property(dev,
12524 BIT(DRM_ROTATE_0) |
12525 BIT(DRM_ROTATE_180));
12526 if (dev->mode_config.rotation_property)
12527 drm_object_attach_property(&cursor->base.base,
12528 dev->mode_config.rotation_property,
8e7d688b 12529 state->base.rotation);
4398ad45
VS		 12530 }
12531
ea2c67bb
MR		 12532 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
12533
3d7d6510
MR		 12534 return &cursor->base;
12535}
12536
b358d0a6 12537static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 12538{
fbee40df 12539 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 12540 struct intel_crtc *intel_crtc;
f5de6e07 12541 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 12542 struct drm_plane *primary = NULL;
12543 struct drm_plane *cursor = NULL;
465c120c 12544 int i, ret;
79e53945 12545
955382f3 12546 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 12547 if (intel_crtc == NULL)
12548 return;
12549
f5de6e07
ACO		 12550 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
12551 if (!crtc_state)
12552 goto fail;
12553 intel_crtc_set_state(intel_crtc, crtc_state);
07878248 12554 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 12555
465c120c 12556 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 12557 if (!primary)
12558 goto fail;
12559
12560 cursor = intel_cursor_plane_create(dev, pipe);
12561 if (!cursor)
12562 goto fail;
12563
465c120c 12564 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 12565 cursor, &intel_crtc_funcs);
12566 if (ret)
12567 goto fail;
79e53945
JB		 12568
12569 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 12570 for (i = 0; i < 256; i++) {
12571 intel_crtc->lut_r[i] = i;
12572 intel_crtc->lut_g[i] = i;
12573 intel_crtc->lut_b[i] = i;
12574 }
12575
1f1c2e24
VS		 12576 /*
12577 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 12578 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 12579 */
80824003
JB		 12580 intel_crtc->pipe = pipe;
12581 intel_crtc->plane = pipe;
3a77c4c4 12582 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 12583 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 12584 intel_crtc->plane = !pipe;
80824003
JB		 12585 }
12586
4b0e333e
CW		 12587 intel_crtc->cursor_base = ~0;
12588 intel_crtc->cursor_cntl = ~0;
dc41c154 12589 intel_crtc->cursor_size = ~0;
8d7849db 12590
22fd0fab
JB		 12591 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12592 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12593 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12594 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12595
9362c7c5
ACO		 12596 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12597
79e53945 12598 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 12599
12600 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 12601 return;
12602
12603fail:
12604 if (primary)
12605 drm_plane_cleanup(primary);
12606 if (cursor)
12607 drm_plane_cleanup(cursor);
f5de6e07 12608 kfree(crtc_state);
3d7d6510 12609 kfree(intel_crtc);
79e53945
JB		 12610}
12611
752aa88a
JB		 12612enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12613{
12614 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 12615 struct drm_device *dev = connector->base.dev;
752aa88a 12616
51fd371b 12617 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 12618
d3babd3f 12619 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 12620 return INVALID_PIPE;
12621
12622 return to_intel_crtc(encoder->crtc)->pipe;
12623}
12624
08d7b3d1 12625int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 12626 struct drm_file *file)
08d7b3d1 12627{
08d7b3d1 12628 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 12629 struct drm_crtc *drmmode_crtc;
c05422d5 12630 struct intel_crtc *crtc;
08d7b3d1 12631
7707e653 12632 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 12633
7707e653 12634 if (!drmmode_crtc) {
08d7b3d1 12635 DRM_ERROR("no such CRTC id\n");
3f2c2057 12636 return -ENOENT;
08d7b3d1
CW		 12637 }
12638
7707e653 12639 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 12640 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 12641
c05422d5 12642 return 0;
08d7b3d1
CW		 12643}
12644
66a9278e 12645static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 12646{
66a9278e
DV		 12647 struct drm_device *dev = encoder->base.dev;
12648 struct intel_encoder *source_encoder;
79e53945 12649 int index_mask = 0;
79e53945
JB		 12650 int entry = 0;
12651
b2784e15 12652 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 12653 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 12654 index_mask |= (1 << entry);
12655
79e53945
JB		 12656 entry++;
12657 }
4ef69c7a 12658
79e53945
JB		 12659 return index_mask;
12660}
12661
4d302442
CW		 12662static bool has_edp_a(struct drm_device *dev)
12663{
12664 struct drm_i915_private *dev_priv = dev->dev_private;
12665
12666 if (!IS_MOBILE(dev))
12667 return false;
12668
12669 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12670 return false;
12671
e3589908 12672 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 12673 return false;
12674
12675 return true;
12676}
12677
84b4e042
JB		 12678static bool intel_crt_present(struct drm_device *dev)
12679{
12680 struct drm_i915_private *dev_priv = dev->dev_private;
12681
884497ed
DL		 12682 if (INTEL_INFO(dev)->gen >= 9)
12683 return false;
12684
cf404ce4 12685 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 12686 return false;
12687
12688 if (IS_CHERRYVIEW(dev))
12689 return false;
12690
12691 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12692 return false;
12693
12694 return true;
12695}
12696
79e53945
JB		 12697static void intel_setup_outputs(struct drm_device *dev)
12698{
725e30ad 12699 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 12700 struct intel_encoder *encoder;
c6f95f27 12701 struct drm_connector *connector;
cb0953d7 12702 bool dpd_is_edp = false;
79e53945 12703
c9093354 12704 intel_lvds_init(dev);
79e53945 12705
84b4e042 12706 if (intel_crt_present(dev))
79935fca 12707 intel_crt_init(dev);
cb0953d7 12708
affa9354 12709 if (HAS_DDI(dev)) {
0e72a5b5
ED		 12710 int found;
12711
de31facd
JB		 12712 /*
12713 * Haswell uses DDI functions to detect digital outputs.
12714 * On SKL pre-D0 the strap isn't connected, so we assume
12715 * it's there.
12716 */
0e72a5b5 12717 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
de31facd
JB		 12718 /* WaIgnoreDDIAStrap: skl */
12719 if (found ||
12720 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
0e72a5b5
ED		 12721 intel_ddi_init(dev, PORT_A);
12722
12723 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12724 * register */
12725 found = I915_READ(SFUSE_STRAP);
12726
12727 if (found & SFUSE_STRAP_DDIB_DETECTED)
12728 intel_ddi_init(dev, PORT_B);
12729 if (found & SFUSE_STRAP_DDIC_DETECTED)
12730 intel_ddi_init(dev, PORT_C);
12731 if (found & SFUSE_STRAP_DDID_DETECTED)
12732 intel_ddi_init(dev, PORT_D);
12733 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 12734 int found;
5d8a7752 12735 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 12736
12737 if (has_edp_a(dev))
12738 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 12739
dc0fa718 12740 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 12741 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 12742 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 12743 if (!found)
e2debe91 12744 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 12745 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 12746 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 12747 }
12748
dc0fa718 12749 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 12750 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 12751
dc0fa718 12752 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 12753 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 12754
5eb08b69 12755 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 12756 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 12757
270b3042 12758 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 12759 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 12760 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 12761 /*
12762 * The DP_DETECTED bit is the latched state of the DDC
12763 * SDA pin at boot. However since eDP doesn't require DDC
12764 * (no way to plug in a DP->HDMI dongle) the DDC pins for
12765 * eDP ports may have been muxed to an alternate function.
12766 * Thus we can't rely on the DP_DETECTED bit alone to detect
12767 * eDP ports. Consult the VBT as well as DP_DETECTED to
12768 * detect eDP ports.
12769 */
d2182a66
VS		 12770 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
12771 !intel_dp_is_edp(dev, PORT_B))
585a94b8
AB		 12772 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12773 PORT_B);
e17ac6db
VS		 12774 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12775 intel_dp_is_edp(dev, PORT_B))
12776 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
585a94b8 12777
d2182a66
VS		 12778 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
12779 !intel_dp_is_edp(dev, PORT_C))
6f6005a5
JB		 12780 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12781 PORT_C);
e17ac6db
VS		 12782 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12783 intel_dp_is_edp(dev, PORT_C))
12784 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 12785
9418c1f1 12786 if (IS_CHERRYVIEW(dev)) {
e17ac6db 12787 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
9418c1f1
VS		 12788 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12789 PORT_D);
e17ac6db
VS		 12790 /* eDP not supported on port D, so don't check VBT */
12791 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12792 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
9418c1f1
VS		 12793 }
12794
3cfca973 12795 intel_dsi_init(dev);
103a196f 12796 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 12797 bool found = false;
7d57382e 12798
e2debe91 12799 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 12800 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 12801 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 12802 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12803 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 12804 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 12805 }
27185ae1 12806
e7281eab 12807 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 12808 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 12809 }
13520b05
KH		 12810
12811 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 12812
e2debe91 12813 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 12814 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 12815 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 12816 }
27185ae1 12817
e2debe91 12818 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 12819
b01f2c3a
JB		 12820 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12821 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 12822 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 12823 }
e7281eab 12824 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 12825 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 12826 }
27185ae1 12827
b01f2c3a 12828 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 12829 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 12830 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 12831 } else if (IS_GEN2(dev))
79e53945
JB		 12832 intel_dvo_init(dev);
12833
103a196f 12834 if (SUPPORTS_TV(dev))
79e53945
JB		 12835 intel_tv_init(dev);
12836
c6f95f27
MR		 12837 /*
12838 * FIXME: We don't have full atomic support yet, but we want to be
12839 * able to enable/test plane updates via the atomic interface in the
12840 * meantime. However as soon as we flip DRIVER_ATOMIC on, the DRM core
12841 * will take some atomic codepaths to lookup properties during
12842 * drmModeGetConnector() that unconditionally dereference
12843 * connector->state.
12844 *
12845 * We create a dummy connector state here for each connector to ensure
12846 * the DRM core doesn't try to dereference a NULL connector->state.
12847 * The actual connector properties will never be updated or contain
12848 * useful information, but since we're doing this specifically for
12849 * testing/debug of the plane operations (and only when a specific
12850 * kernel module option is given), that shouldn't really matter.
12851 *
12852 * Once atomic support for crtc's + connectors lands, this loop should
12853 * be removed since we'll be setting up real connector state, which
12854 * will contain Intel-specific properties.
12855 */
12856 if (drm_core_check_feature(dev, DRIVER_ATOMIC)) {
12857 list_for_each_entry(connector,
12858 &dev->mode_config.connector_list,
12859 head) {
12860 if (!WARN_ON(connector->state)) {
12861 connector->state =
12862 kzalloc(sizeof(*connector->state),
12863 GFP_KERNEL);
12864 }
12865 }
12866 }
12867
0bc12bcb 12868 intel_psr_init(dev);
7c8f8a70 12869
b2784e15 12870 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 12871 encoder->base.possible_crtcs = encoder->crtc_mask;
12872 encoder->base.possible_clones =
66a9278e 12873 intel_encoder_clones(encoder);
79e53945 12874 }
47356eb6 12875
dde86e2d 12876 intel_init_pch_refclk(dev);
270b3042
DV		 12877
12878 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 12879}
12880
12881static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12882{
60a5ca01 12883 struct drm_device *dev = fb->dev;
79e53945 12884 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 12885
ef2d633e 12886 drm_framebuffer_cleanup(fb);
60a5ca01 12887 mutex_lock(&dev->struct_mutex);
ef2d633e 12888 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 12889 drm_gem_object_unreference(&intel_fb->obj->base);
12890 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 12891 kfree(intel_fb);
12892}
12893
12894static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 12895 struct drm_file *file,
79e53945
JB		 12896 unsigned int *handle)
12897{
12898 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 12899 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 12900
05394f39 12901 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 12902}
12903
12904static const struct drm_framebuffer_funcs intel_fb_funcs = {
12905 .destroy = intel_user_framebuffer_destroy,
12906 .create_handle = intel_user_framebuffer_create_handle,
12907};
12908
b321803d
DL		 12909static
12910u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
12911 uint32_t pixel_format)
12912{
12913 u32 gen = INTEL_INFO(dev)->gen;
12914
12915 if (gen >= 9) {
12916 /* "The stride in bytes must not exceed the of the size of 8K
12917 * pixels and 32K bytes."
12918 */
12919 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
12920 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
12921 return 32*1024;
12922 } else if (gen >= 4) {
12923 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
12924 return 16*1024;
12925 else
12926 return 32*1024;
12927 } else if (gen >= 3) {
12928 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
12929 return 8*1024;
12930 else
12931 return 16*1024;
12932 } else {
12933 /* XXX DSPC is limited to 4k tiled */
12934 return 8*1024;
12935 }
12936}
12937
b5ea642a
DV		 12938static int intel_framebuffer_init(struct drm_device *dev,
12939 struct intel_framebuffer *intel_fb,
12940 struct drm_mode_fb_cmd2 *mode_cmd,
12941 struct drm_i915_gem_object *obj)
79e53945 12942{
6761dd31 12943 unsigned int aligned_height;
79e53945 12944 int ret;
b321803d 12945 u32 pitch_limit, stride_alignment;
79e53945 12946
dd4916c5
DV		 12947 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12948
2a80eada
DV		 12949 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
12950 /* Enforce that fb modifier and tiling mode match, but only for
12951 * X-tiled. This is needed for FBC. */
12952 if (!!(obj->tiling_mode == I915_TILING_X) !=
12953 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
12954 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
12955 return -EINVAL;
12956 }
12957 } else {
12958 if (obj->tiling_mode == I915_TILING_X)
12959 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
12960 else if (obj->tiling_mode == I915_TILING_Y) {
12961 DRM_DEBUG("No Y tiling for legacy addfb\n");
12962 return -EINVAL;
12963 }
12964 }
12965
9a8f0a12
TU		 12966 /* Passed in modifier sanity checking. */
12967 switch (mode_cmd->modifier[0]) {
12968 case I915_FORMAT_MOD_Y_TILED:
12969 case I915_FORMAT_MOD_Yf_TILED:
12970 if (INTEL_INFO(dev)->gen < 9) {
12971 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
12972 mode_cmd->modifier[0]);
12973 return -EINVAL;
12974 }
12975 case DRM_FORMAT_MOD_NONE:
12976 case I915_FORMAT_MOD_X_TILED:
12977 break;
12978 default:
12979 DRM_ERROR("Unsupported fb modifier 0x%llx!\n",
12980 mode_cmd->modifier[0]);
57cd6508 12981 return -EINVAL;
c16ed4be 12982 }
57cd6508 12983
b321803d
DL		 12984 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
12985 mode_cmd->pixel_format);
12986 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
12987 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
12988 mode_cmd->pitches[0], stride_alignment);
57cd6508 12989 return -EINVAL;
c16ed4be 12990 }
57cd6508 12991
b321803d
DL		 12992 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
12993 mode_cmd->pixel_format);
a35cdaa0 12994 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 12995 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
12996 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 12997 "tiled" : "linear",
a35cdaa0 12998 mode_cmd->pitches[0], pitch_limit);
5d7bd705 12999 return -EINVAL;
c16ed4be 13000 }
5d7bd705 13001
2a80eada 13002 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 13003 mode_cmd->pitches[0] != obj->stride) {
13004 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
13005 mode_cmd->pitches[0], obj->stride);
5d7bd705 13006 return -EINVAL;
c16ed4be 13007 }
5d7bd705 13008
57779d06 13009 /* Reject formats not supported by any plane early. */
308e5bcb 13010 switch (mode_cmd->pixel_format) {
57779d06 13011 case DRM_FORMAT_C8:
04b3924d
VS		 13012 case DRM_FORMAT_RGB565:
13013 case DRM_FORMAT_XRGB8888:
13014 case DRM_FORMAT_ARGB8888:
57779d06
VS		 13015 break;
13016 case DRM_FORMAT_XRGB1555:
13017 case DRM_FORMAT_ARGB1555:
c16ed4be 13018 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 13019 DRM_DEBUG("unsupported pixel format: %s\n",
13020 drm_get_format_name(mode_cmd->pixel_format));
57779d06 13021 return -EINVAL;
c16ed4be 13022 }
57779d06
VS		 13023 break;
13024 case DRM_FORMAT_XBGR8888:
13025 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 13026 case DRM_FORMAT_XRGB2101010:
13027 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 13028 case DRM_FORMAT_XBGR2101010:
13029 case DRM_FORMAT_ABGR2101010:
c16ed4be 13030 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 13031 DRM_DEBUG("unsupported pixel format: %s\n",
13032 drm_get_format_name(mode_cmd->pixel_format));
57779d06 13033 return -EINVAL;
c16ed4be 13034 }
b5626747 13035 break;
04b3924d
VS		 13036 case DRM_FORMAT_YUYV:
13037 case DRM_FORMAT_UYVY:
13038 case DRM_FORMAT_YVYU:
13039 case DRM_FORMAT_VYUY:
c16ed4be 13040 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 13041 DRM_DEBUG("unsupported pixel format: %s\n",
13042 drm_get_format_name(mode_cmd->pixel_format));
57779d06 13043 return -EINVAL;
c16ed4be 13044 }
57cd6508
CW		 13045 break;
13046 default:
4ee62c76
VS		 13047 DRM_DEBUG("unsupported pixel format: %s\n",
13048 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 13049 return -EINVAL;
13050 }
13051
90f9a336
VS		 13052 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
13053 if (mode_cmd->offsets[0] != 0)
13054 return -EINVAL;
13055
ec2c981e 13056 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 13057 mode_cmd->pixel_format,
13058 mode_cmd->modifier[0]);
53155c0a
DV		 13059 /* FIXME drm helper for size checks (especially planar formats)? */
13060 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
13061 return -EINVAL;
13062
c7d73f6a
DV		 13063 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
13064 intel_fb->obj = obj;
80075d49 13065 intel_fb->obj->framebuffer_references++;
c7d73f6a 13066
79e53945
JB		 13067 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
13068 if (ret) {
13069 DRM_ERROR("framebuffer init failed %d\n", ret);
13070 return ret;
13071 }
13072
79e53945
JB		 13073 return 0;
13074}
13075
79e53945
JB		 13076static struct drm_framebuffer *
13077intel_user_framebuffer_create(struct drm_device *dev,
13078 struct drm_file *filp,
308e5bcb 13079 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 13080{
05394f39 13081 struct drm_i915_gem_object *obj;
79e53945 13082
308e5bcb
JB		 13083 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
13084 mode_cmd->handles[0]));
c8725226 13085 if (&obj->base == NULL)
cce13ff7 13086 return ERR_PTR(-ENOENT);
79e53945 13087
d2dff872 13088 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 13089}
13090
4520f53a 13091#ifndef CONFIG_DRM_I915_FBDEV
0632fef6 13092static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 13093{
13094}
13095#endif
13096
79e53945 13097static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 13098 .fb_create = intel_user_framebuffer_create,
0632fef6 13099 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 13100 .atomic_check = intel_atomic_check,
13101 .atomic_commit = intel_atomic_commit,
79e53945
JB		 13102};
13103
e70236a8
JB		 13104/* Set up chip specific display functions */
13105static void intel_init_display(struct drm_device *dev)
13106{
13107 struct drm_i915_private *dev_priv = dev->dev_private;
13108
ee9300bb
DV		 13109 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
13110 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 13111 else if (IS_CHERRYVIEW(dev))
13112 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 13113 else if (IS_VALLEYVIEW(dev))
13114 dev_priv->display.find_dpll = vlv_find_best_dpll;
13115 else if (IS_PINEVIEW(dev))
13116 dev_priv->display.find_dpll = pnv_find_best_dpll;
13117 else
13118 dev_priv->display.find_dpll = i9xx_find_best_dpll;
13119
bc8d7dff
DL		 13120 if (INTEL_INFO(dev)->gen >= 9) {
13121 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 13122 dev_priv->display.get_initial_plane_config =
13123 skylake_get_initial_plane_config;
bc8d7dff
DL		 13124 dev_priv->display.crtc_compute_clock =
13125 haswell_crtc_compute_clock;
13126 dev_priv->display.crtc_enable = haswell_crtc_enable;
13127 dev_priv->display.crtc_disable = haswell_crtc_disable;
13128 dev_priv->display.off = ironlake_crtc_off;
13129 dev_priv->display.update_primary_plane =
13130 skylake_update_primary_plane;
13131 } else if (HAS_DDI(dev)) {
0e8ffe1b 13132 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 13133 dev_priv->display.get_initial_plane_config =
13134 ironlake_get_initial_plane_config;
797d0259
ACO		 13135 dev_priv->display.crtc_compute_clock =
13136 haswell_crtc_compute_clock;
4f771f10
PZ		 13137 dev_priv->display.crtc_enable = haswell_crtc_enable;
13138 dev_priv->display.crtc_disable = haswell_crtc_disable;
df8ad70c 13139 dev_priv->display.off = ironlake_crtc_off;
bc8d7dff
DL		 13140 dev_priv->display.update_primary_plane =
13141 ironlake_update_primary_plane;
09b4ddf9 13142 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 13143 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 13144 dev_priv->display.get_initial_plane_config =
13145 ironlake_get_initial_plane_config;
3fb37703
ACO		 13146 dev_priv->display.crtc_compute_clock =
13147 ironlake_crtc_compute_clock;
76e5a89c
DV		 13148 dev_priv->display.crtc_enable = ironlake_crtc_enable;
13149 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 13150 dev_priv->display.off = ironlake_crtc_off;
262ca2b0
MR		 13151 dev_priv->display.update_primary_plane =
13152 ironlake_update_primary_plane;
89b667f8
JB		 13153 } else if (IS_VALLEYVIEW(dev)) {
13154 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 13155 dev_priv->display.get_initial_plane_config =
13156 i9xx_get_initial_plane_config;
d6dfee7a 13157 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 13158 dev_priv->display.crtc_enable = valleyview_crtc_enable;
13159 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13160 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR		 13161 dev_priv->display.update_primary_plane =
13162 i9xx_update_primary_plane;
f564048e 13163 } else {
0e8ffe1b 13164 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 13165 dev_priv->display.get_initial_plane_config =
13166 i9xx_get_initial_plane_config;
d6dfee7a 13167 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 13168 dev_priv->display.crtc_enable = i9xx_crtc_enable;
13169 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 13170 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR		 13171 dev_priv->display.update_primary_plane =
13172 i9xx_update_primary_plane;
f564048e 13173 }
e70236a8 13174
e70236a8 13175 /* Returns the core display clock speed */
25eb05fc
JB		 13176 if (IS_VALLEYVIEW(dev))
13177 dev_priv->display.get_display_clock_speed =
13178 valleyview_get_display_clock_speed;
13179 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 13180 dev_priv->display.get_display_clock_speed =
13181 i945_get_display_clock_speed;
13182 else if (IS_I915G(dev))
13183 dev_priv->display.get_display_clock_speed =
13184 i915_get_display_clock_speed;
257a7ffc 13185 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 13186 dev_priv->display.get_display_clock_speed =
13187 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 13188 else if (IS_PINEVIEW(dev))
13189 dev_priv->display.get_display_clock_speed =
13190 pnv_get_display_clock_speed;
e70236a8
JB		 13191 else if (IS_I915GM(dev))
13192 dev_priv->display.get_display_clock_speed =
13193 i915gm_get_display_clock_speed;
13194 else if (IS_I865G(dev))
13195 dev_priv->display.get_display_clock_speed =
13196 i865_get_display_clock_speed;
f0f8a9ce 13197 else if (IS_I85X(dev))
e70236a8
JB		 13198 dev_priv->display.get_display_clock_speed =
13199 i855_get_display_clock_speed;
13200 else /* 852, 830 */
13201 dev_priv->display.get_display_clock_speed =
13202 i830_get_display_clock_speed;
13203
7c10a2b5 13204 if (IS_GEN5(dev)) {
3bb11b53 13205 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 13206 } else if (IS_GEN6(dev)) {
13207 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 13208 } else if (IS_IVYBRIDGE(dev)) {
13209 /* FIXME: detect B0+ stepping and use auto training */
13210 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 13211 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 13212 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
30a970c6
JB		 13213 } else if (IS_VALLEYVIEW(dev)) {
13214 dev_priv->display.modeset_global_resources =
13215 valleyview_modeset_global_resources;
e70236a8 13216 }
8c9f3aaf 13217
8c9f3aaf
JB		 13218 switch (INTEL_INFO(dev)->gen) {
13219 case 2:
13220 dev_priv->display.queue_flip = intel_gen2_queue_flip;
13221 break;
13222
13223 case 3:
13224 dev_priv->display.queue_flip = intel_gen3_queue_flip;
13225 break;
13226
13227 case 4:
13228 case 5:
13229 dev_priv->display.queue_flip = intel_gen4_queue_flip;
13230 break;
13231
13232 case 6:
13233 dev_priv->display.queue_flip = intel_gen6_queue_flip;
13234 break;
7c9017e5 13235 case 7:
4e0bbc31 13236 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 13237 dev_priv->display.queue_flip = intel_gen7_queue_flip;
13238 break;
830c81db 13239 case 9:
ba343e02
TU		 13240 /* Drop through - unsupported since execlist only. */
13241 default:
13242 /* Default just returns -ENODEV to indicate unsupported */
13243 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 13244 }
7bd688cd
JN		 13245
13246 intel_panel_init_backlight_funcs(dev);
e39b999a
VS		 13247
13248 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 13249}
13250
b690e96c
JB		 13251/*
13252 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
13253 * resume, or other times. This quirk makes sure that's the case for
13254 * affected systems.
13255 */
0206e353 13256static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 13257{
13258 struct drm_i915_private *dev_priv = dev->dev_private;
13259
13260 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 13261 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 13262}
13263
b6b5d049
VS		 13264static void quirk_pipeb_force(struct drm_device *dev)
13265{
13266 struct drm_i915_private *dev_priv = dev->dev_private;
13267
13268 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
13269 DRM_INFO("applying pipe b force quirk\n");
13270}
13271
435793df
KP		 13272/*
13273 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
13274 */
13275static void quirk_ssc_force_disable(struct drm_device *dev)
13276{
13277 struct drm_i915_private *dev_priv = dev->dev_private;
13278 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 13279 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 13280}
13281
4dca20ef 13282/*
5a15ab5b
CE		 13283 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
13284 * brightness value
4dca20ef
CE		 13285 */
13286static void quirk_invert_brightness(struct drm_device *dev)
13287{
13288 struct drm_i915_private *dev_priv = dev->dev_private;
13289 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 13290 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 13291}
13292
9c72cc6f
SD		 13293/* Some VBT's incorrectly indicate no backlight is present */
13294static void quirk_backlight_present(struct drm_device *dev)
13295{
13296 struct drm_i915_private *dev_priv = dev->dev_private;
13297 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
13298 DRM_INFO("applying backlight present quirk\n");
13299}
13300
b690e96c
JB		 13301struct intel_quirk {
13302 int device;
13303 int subsystem_vendor;
13304 int subsystem_device;
13305 void (*hook)(struct drm_device *dev);
13306};
13307
5f85f176
EE		 13308/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13309struct intel_dmi_quirk {
13310 void (*hook)(struct drm_device *dev);
13311 const struct dmi_system_id (*dmi_id_list)[];
13312};
13313
13314static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
13315{
13316 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
13317 return 1;
13318}
13319
13320static const struct intel_dmi_quirk intel_dmi_quirks[] = {
13321 {
13322 .dmi_id_list = &(const struct dmi_system_id[]) {
13323 {
13324 .callback = intel_dmi_reverse_brightness,
13325 .ident = "NCR Corporation",
13326 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
13327 DMI_MATCH(DMI_PRODUCT_NAME, ""),
13328 },
13329 },
13330 { } /* terminating entry */
13331 },
13332 .hook = quirk_invert_brightness,
13333 },
13334};
13335
c43b5634 13336static struct intel_quirk intel_quirks[] = {
b690e96c 13337 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 13338 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 13339
b690e96c
JB		 13340 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
13341 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
13342
b690e96c
JB		 13343 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
13344 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
13345
5f080c0f
VS		 13346 /* 830 needs to leave pipe A & dpll A up */
13347 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
13348
b6b5d049
VS		 13349 /* 830 needs to leave pipe B & dpll B up */
13350 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
13351
435793df
KP		 13352 /* Lenovo U160 cannot use SSC on LVDS */
13353 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 13354
13355 /* Sony Vaio Y cannot use SSC on LVDS */
13356 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 13357
be505f64
AH		 13358 /* Acer Aspire 5734Z must invert backlight brightness */
13359 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
13360
13361 /* Acer/eMachines G725 */
13362 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
13363
13364 /* Acer/eMachines e725 */
13365 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
13366
13367 /* Acer/Packard Bell NCL20 */
13368 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
13369
13370 /* Acer Aspire 4736Z */
13371 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 13372
13373 /* Acer Aspire 5336 */
13374 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 13375
13376 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13377 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 13378
dfb3d47b
SD		 13379 /* Acer C720 Chromebook (Core i3 4005U) */
13380 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
13381
b2a9601c 13382 /* Apple Macbook 2,1 (Core 2 T7400) */
13383 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
13384
d4967d8c
SD		 13385 /* Toshiba CB35 Chromebook (Celeron 2955U) */
13386 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 13387
13388 /* HP Chromebook 14 (Celeron 2955U) */
13389 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 13390
13391 /* Dell Chromebook 11 */
13392 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 13393};
13394
13395static void intel_init_quirks(struct drm_device *dev)
13396{
13397 struct pci_dev *d = dev->pdev;
13398 int i;
13399
13400 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
13401 struct intel_quirk *q = &intel_quirks[i];
13402
13403 if (d->device == q->device &&
13404 (d->subsystem_vendor == q->subsystem_vendor ||
13405 q->subsystem_vendor == PCI_ANY_ID) &&
13406 (d->subsystem_device == q->subsystem_device ||
13407 q->subsystem_device == PCI_ANY_ID))
13408 q->hook(dev);
13409 }
5f85f176
EE		 13410 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
13411 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
13412 intel_dmi_quirks[i].hook(dev);
13413 }
b690e96c
JB		 13414}
13415
9cce37f4
JB		 13416/* Disable the VGA plane that we never use */
13417static void i915_disable_vga(struct drm_device *dev)
13418{
13419 struct drm_i915_private *dev_priv = dev->dev_private;
13420 u8 sr1;
766aa1c4 13421 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 13422
2b37c616 13423 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 13424 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 13425 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 13426 sr1 = inb(VGA_SR_DATA);
13427 outb(sr1 | 1<<5, VGA_SR_DATA);
13428 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
13429 udelay(300);
13430
01f5a626 13431 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 13432 POSTING_READ(vga_reg);
13433}
13434
f817586c
DV		 13435void intel_modeset_init_hw(struct drm_device *dev)
13436{
a8f78b58
ED		 13437 intel_prepare_ddi(dev);
13438
f8bf63fd
VS		 13439 if (IS_VALLEYVIEW(dev))
13440 vlv_update_cdclk(dev);
13441
f817586c
DV		 13442 intel_init_clock_gating(dev);
13443
8090c6b9 13444 intel_enable_gt_powersave(dev);
f817586c
DV		 13445}
13446
79e53945
JB		 13447void intel_modeset_init(struct drm_device *dev)
13448{
652c393a 13449 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 13450 int sprite, ret;
8cc87b75 13451 enum pipe pipe;
46f297fb 13452 struct intel_crtc *crtc;
79e53945
JB		 13453
13454 drm_mode_config_init(dev);
13455
13456 dev->mode_config.min_width = 0;
13457 dev->mode_config.min_height = 0;
13458
019d96cb
DA		 13459 dev->mode_config.preferred_depth = 24;
13460 dev->mode_config.prefer_shadow = 1;
13461
25bab385
TU		 13462 dev->mode_config.allow_fb_modifiers = true;
13463
e6ecefaa 13464 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 13465
b690e96c
JB		 13466 intel_init_quirks(dev);
13467
1fa61106
ED		 13468 intel_init_pm(dev);
13469
e3c74757
BW		 13470 if (INTEL_INFO(dev)->num_pipes == 0)
13471 return;
13472
e70236a8 13473 intel_init_display(dev);
7c10a2b5 13474 intel_init_audio(dev);
e70236a8 13475
a6c45cf0
CW		 13476 if (IS_GEN2(dev)) {
13477 dev->mode_config.max_width = 2048;
13478 dev->mode_config.max_height = 2048;
13479 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 13480 dev->mode_config.max_width = 4096;
13481 dev->mode_config.max_height = 4096;
79e53945 13482 } else {
a6c45cf0
CW		 13483 dev->mode_config.max_width = 8192;
13484 dev->mode_config.max_height = 8192;
79e53945 13485 }
068be561 13486
dc41c154
VS		 13487 if (IS_845G(dev) || IS_I865G(dev)) {
13488 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13489 dev->mode_config.cursor_height = 1023;
13490 } else if (IS_GEN2(dev)) {
068be561
DL		 13491 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13492 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13493 } else {
13494 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13495 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13496 }
13497
5d4545ae 13498 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 13499
28c97730 13500 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 13501 INTEL_INFO(dev)->num_pipes,
13502 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 13503
055e393f 13504 for_each_pipe(dev_priv, pipe) {
8cc87b75 13505 intel_crtc_init(dev, pipe);
3bdcfc0c 13506 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 13507 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 13508 if (ret)
06da8da2 13509 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 13510 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 13511 }
79e53945
JB		 13512 }
13513
f42bb70d
JB		 13514 intel_init_dpio(dev);
13515
e72f9fbf 13516 intel_shared_dpll_init(dev);
ee7b9f93 13517
9cce37f4
JB		 13518 /* Just disable it once at startup */
13519 i915_disable_vga(dev);
79e53945 13520 intel_setup_outputs(dev);
11be49eb
CW		 13521
13522 /* Just in case the BIOS is doing something questionable. */
7ff0ebcc 13523 intel_fbc_disable(dev);
fa9fa083 13524
6e9f798d 13525 drm_modeset_lock_all(dev);
fa9fa083 13526 intel_modeset_setup_hw_state(dev, false);
6e9f798d 13527 drm_modeset_unlock_all(dev);
46f297fb 13528
d3fcc808 13529 for_each_intel_crtc(dev, crtc) {
46f297fb
JB		 13530 if (!crtc->active)
13531 continue;
13532
46f297fb 13533 /*
46f297fb
JB		 13534 * Note that reserving the BIOS fb up front prevents us
13535 * from stuffing other stolen allocations like the ring
13536 * on top. This prevents some ugliness at boot time, and
13537 * can even allow for smooth boot transitions if the BIOS
13538 * fb is large enough for the active pipe configuration.
13539 */
5724dbd1
DL		 13540 if (dev_priv->display.get_initial_plane_config) {
13541 dev_priv->display.get_initial_plane_config(crtc,
46f297fb
JB		 13542 &crtc->plane_config);
13543 /*
13544 * If the fb is shared between multiple heads, we'll
13545 * just get the first one.
13546 */
484b41dd 13547 intel_find_plane_obj(crtc, &crtc->plane_config);
46f297fb 13548 }
46f297fb 13549 }
2c7111db
CW		 13550}
13551
7fad798e
DV		 13552static void intel_enable_pipe_a(struct drm_device *dev)
13553{
13554 struct intel_connector *connector;
13555 struct drm_connector *crt = NULL;
13556 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 13557 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 13558
13559 /* We can't just switch on the pipe A, we need to set things up with a
13560 * proper mode and output configuration. As a gross hack, enable pipe A
13561 * by enabling the load detect pipe once. */
3a3371ff 13562 for_each_intel_connector(dev, connector) {
7fad798e
DV		 13563 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13564 crt = &connector->base;
13565 break;
13566 }
13567 }
13568
13569 if (!crt)
13570 return;
13571
208bf9fd
VS		 13572 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13573 intel_release_load_detect_pipe(crt, &load_detect_temp);
7fad798e
DV		 13574}
13575
fa555837
DV		 13576static bool
13577intel_check_plane_mapping(struct intel_crtc *crtc)
13578{
7eb552ae
BW		 13579 struct drm_device *dev = crtc->base.dev;
13580 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 13581 u32 reg, val;
13582
7eb552ae 13583 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 13584 return true;
13585
13586 reg = DSPCNTR(!crtc->plane);
13587 val = I915_READ(reg);
13588
13589 if ((val & DISPLAY_PLANE_ENABLE) &&
13590 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13591 return false;
13592
13593 return true;
13594}
13595
24929352
DV		 13596static void intel_sanitize_crtc(struct intel_crtc *crtc)
13597{
13598 struct drm_device *dev = crtc->base.dev;
13599 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 13600 u32 reg;
24929352 13601
24929352 13602 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 13603 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 13604 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13605
d3eaf884 13606 /* restore vblank interrupts to correct state */
9625604c 13607 drm_crtc_vblank_reset(&crtc->base);
d297e103
VS		 13608 if (crtc->active) {
13609 update_scanline_offset(crtc);
9625604c
DV		 13610 drm_crtc_vblank_on(&crtc->base);
13611 }
d3eaf884 13612
24929352 13613 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 13614 * disable the crtc (and hence change the state) if it is wrong. Note
13615 * that gen4+ has a fixed plane -> pipe mapping. */
13616 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 13617 struct intel_connector *connector;
13618 bool plane;
13619
24929352
DV		 13620 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13621 crtc->base.base.id);
13622
13623 /* Pipe has the wrong plane attached and the plane is active.
13624 * Temporarily change the plane mapping and disable everything
13625 * ... */
13626 plane = crtc->plane;
13627 crtc->plane = !plane;
9c8958bc 13628 crtc->primary_enabled = true;
24929352
DV		 13629 dev_priv->display.crtc_disable(&crtc->base);
13630 crtc->plane = plane;
13631
13632 /* ... and break all links. */
3a3371ff 13633 for_each_intel_connector(dev, connector) {
24929352
DV		 13634 if (connector->encoder->base.crtc != &crtc->base)
13635 continue;
13636
7f1950fb
EE		 13637 connector->base.dpms = DRM_MODE_DPMS_OFF;
13638 connector->base.encoder = NULL;
24929352 13639 }
7f1950fb
EE		 13640 /* multiple connectors may have the same encoder:
13641 * handle them and break crtc link separately */
3a3371ff 13642 for_each_intel_connector(dev, connector)
7f1950fb
EE		 13643 if (connector->encoder->base.crtc == &crtc->base) {
13644 connector->encoder->base.crtc = NULL;
13645 connector->encoder->connectors_active = false;
13646 }
24929352
DV		 13647
13648 WARN_ON(crtc->active);
83d65738 13649 crtc->base.state->enable = false;
24929352
DV		 13650 crtc->base.enabled = false;
13651 }
24929352 13652
7fad798e
DV		 13653 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13654 crtc->pipe == PIPE_A && !crtc->active) {
13655 /* BIOS forgot to enable pipe A, this mostly happens after
13656 * resume. Force-enable the pipe to fix this, the update_dpms
13657 * call below we restore the pipe to the right state, but leave
13658 * the required bits on. */
13659 intel_enable_pipe_a(dev);
13660 }
13661
24929352
DV		 13662 /* Adjust the state of the output pipe according to whether we
13663 * have active connectors/encoders. */
13664 intel_crtc_update_dpms(&crtc->base);
13665
83d65738 13666 if (crtc->active != crtc->base.state->enable) {
24929352
DV		 13667 struct intel_encoder *encoder;
13668
13669 /* This can happen either due to bugs in the get_hw_state
13670 * functions or because the pipe is force-enabled due to the
13671 * pipe A quirk. */
13672 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13673 crtc->base.base.id,
83d65738 13674 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 13675 crtc->active ? "enabled" : "disabled");
13676
83d65738 13677 crtc->base.state->enable = crtc->active;
24929352
DV		 13678 crtc->base.enabled = crtc->active;
13679
13680 /* Because we only establish the connector -> encoder ->
13681 * crtc links if something is active, this means the
13682 * crtc is now deactivated. Break the links. connector
13683 * -> encoder links are only establish when things are
13684 * actually up, hence no need to break them. */
13685 WARN_ON(crtc->active);
13686
13687 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13688 WARN_ON(encoder->connectors_active);
13689 encoder->base.crtc = NULL;
13690 }
13691 }
c5ab3bc0 13692
a3ed6aad 13693 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 13694 /*
13695 * We start out with underrun reporting disabled to avoid races.
13696 * For correct bookkeeping mark this on active crtcs.
13697 *
c5ab3bc0
DV		 13698 * Also on gmch platforms we dont have any hardware bits to
13699 * disable the underrun reporting. Which means we need to start
13700 * out with underrun reporting disabled also on inactive pipes,
13701 * since otherwise we'll complain about the garbage we read when
13702 * e.g. coming up after runtime pm.
13703 *
4cc31489
DV		 13704 * No protection against concurrent access is required - at
13705 * worst a fifo underrun happens which also sets this to false.
13706 */
13707 crtc->cpu_fifo_underrun_disabled = true;
13708 crtc->pch_fifo_underrun_disabled = true;
13709 }
24929352
DV		 13710}
13711
13712static void intel_sanitize_encoder(struct intel_encoder *encoder)
13713{
13714 struct intel_connector *connector;
13715 struct drm_device *dev = encoder->base.dev;
13716
13717 /* We need to check both for a crtc link (meaning that the
13718 * encoder is active and trying to read from a pipe) and the
13719 * pipe itself being active. */
13720 bool has_active_crtc = encoder->base.crtc &&
13721 to_intel_crtc(encoder->base.crtc)->active;
13722
13723 if (encoder->connectors_active && !has_active_crtc) {
13724 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13725 encoder->base.base.id,
8e329a03 13726 encoder->base.name);
24929352
DV		 13727
13728 /* Connector is active, but has no active pipe. This is
13729 * fallout from our resume register restoring. Disable
13730 * the encoder manually again. */
13731 if (encoder->base.crtc) {
13732 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13733 encoder->base.base.id,
8e329a03 13734 encoder->base.name);
24929352 13735 encoder->disable(encoder);
a62d1497
VS		 13736 if (encoder->post_disable)
13737 encoder->post_disable(encoder);
24929352 13738 }
7f1950fb
EE		 13739 encoder->base.crtc = NULL;
13740 encoder->connectors_active = false;
24929352
DV		 13741
13742 /* Inconsistent output/port/pipe state happens presumably due to
13743 * a bug in one of the get_hw_state functions. Or someplace else
13744 * in our code, like the register restore mess on resume. Clamp
13745 * things to off as a safer default. */
3a3371ff 13746 for_each_intel_connector(dev, connector) {
24929352
DV		 13747 if (connector->encoder != encoder)
13748 continue;
7f1950fb
EE		 13749 connector->base.dpms = DRM_MODE_DPMS_OFF;
13750 connector->base.encoder = NULL;
24929352
DV		 13751 }
13752 }
13753 /* Enabled encoders without active connectors will be fixed in
13754 * the crtc fixup. */
13755}
13756
04098753 13757void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 13758{
13759 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 13760 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 13761
04098753
ID		 13762 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13763 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13764 i915_disable_vga(dev);
13765 }
13766}
13767
13768void i915_redisable_vga(struct drm_device *dev)
13769{
13770 struct drm_i915_private *dev_priv = dev->dev_private;
13771
8dc8a27c
PZ		 13772 /* This function can be called both from intel_modeset_setup_hw_state or
13773 * at a very early point in our resume sequence, where the power well
13774 * structures are not yet restored. Since this function is at a very
13775 * paranoid "someone might have enabled VGA while we were not looking"
13776 * level, just check if the power well is enabled instead of trying to
13777 * follow the "don't touch the power well if we don't need it" policy
13778 * the rest of the driver uses. */
f458ebbc 13779 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 13780 return;
13781
04098753 13782 i915_redisable_vga_power_on(dev);
0fde901f
KM		 13783}
13784
98ec7739
VS		 13785static bool primary_get_hw_state(struct intel_crtc *crtc)
13786{
13787 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13788
13789 if (!crtc->active)
13790 return false;
13791
13792 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13793}
13794
30e984df 13795static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 13796{
13797 struct drm_i915_private *dev_priv = dev->dev_private;
13798 enum pipe pipe;
24929352
DV		 13799 struct intel_crtc *crtc;
13800 struct intel_encoder *encoder;
13801 struct intel_connector *connector;
5358901f 13802 int i;
24929352 13803
d3fcc808 13804 for_each_intel_crtc(dev, crtc) {
6e3c9717 13805 memset(crtc->config, 0, sizeof(*crtc->config));
3b117c8f 13806
6e3c9717 13807 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
9953599b 13808
0e8ffe1b 13809 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 13810 crtc->config);
24929352 13811
83d65738 13812 crtc->base.state->enable = crtc->active;
24929352 13813 crtc->base.enabled = crtc->active;
98ec7739 13814 crtc->primary_enabled = primary_get_hw_state(crtc);
24929352
DV		 13815
13816 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13817 crtc->base.base.id,
13818 crtc->active ? "enabled" : "disabled");
13819 }
13820
5358901f
DV		 13821 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13822 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13823
3e369b76
ACO		 13824 pll->on = pll->get_hw_state(dev_priv, pll,
13825 &pll->config.hw_state);
5358901f 13826 pll->active = 0;
3e369b76 13827 pll->config.crtc_mask = 0;
d3fcc808 13828 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 13829 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 13830 pll->active++;
3e369b76 13831 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 13832 }
5358901f 13833 }
5358901f 13834
1e6f2ddc 13835 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 13836 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 13837
3e369b76 13838 if (pll->config.crtc_mask)
bd2bb1b9 13839 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 13840 }
13841
b2784e15 13842 for_each_intel_encoder(dev, encoder) {
24929352
DV		 13843 pipe = 0;
13844
13845 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 13846 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13847 encoder->base.crtc = &crtc->base;
6e3c9717 13848 encoder->get_config(encoder, crtc->config);
24929352
DV		 13849 } else {
13850 encoder->base.crtc = NULL;
13851 }
13852
13853 encoder->connectors_active = false;
6f2bcceb 13854 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 13855 encoder->base.base.id,
8e329a03 13856 encoder->base.name,
24929352 13857 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 13858 pipe_name(pipe));
24929352
DV		 13859 }
13860
3a3371ff 13861 for_each_intel_connector(dev, connector) {
24929352
DV		 13862 if (connector->get_hw_state(connector)) {
13863 connector->base.dpms = DRM_MODE_DPMS_ON;
13864 connector->encoder->connectors_active = true;
13865 connector->base.encoder = &connector->encoder->base;
13866 } else {
13867 connector->base.dpms = DRM_MODE_DPMS_OFF;
13868 connector->base.encoder = NULL;
13869 }
13870 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13871 connector->base.base.id,
c23cc417 13872 connector->base.name,
24929352
DV		 13873 connector->base.encoder ? "enabled" : "disabled");
13874 }
30e984df
DV		 13875}
13876
13877/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13878 * and i915 state tracking structures. */
13879void intel_modeset_setup_hw_state(struct drm_device *dev,
13880 bool force_restore)
13881{
13882 struct drm_i915_private *dev_priv = dev->dev_private;
13883 enum pipe pipe;
30e984df
DV		 13884 struct intel_crtc *crtc;
13885 struct intel_encoder *encoder;
35c95375 13886 int i;
30e984df
DV		 13887
13888 intel_modeset_readout_hw_state(dev);
24929352 13889
babea61d
JB		 13890 /*
13891 * Now that we have the config, copy it to each CRTC struct
13892 * Note that this could go away if we move to using crtc_config
13893 * checking everywhere.
13894 */
d3fcc808 13895 for_each_intel_crtc(dev, crtc) {
d330a953 13896 if (crtc->active && i915.fastboot) {
6e3c9717
ACO		 13897 intel_mode_from_pipe_config(&crtc->base.mode,
13898 crtc->config);
babea61d
JB		 13899 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13900 crtc->base.base.id);
13901 drm_mode_debug_printmodeline(&crtc->base.mode);
13902 }
13903 }
13904
24929352 13905 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 13906 for_each_intel_encoder(dev, encoder) {
24929352
DV		 13907 intel_sanitize_encoder(encoder);
13908 }
13909
055e393f 13910 for_each_pipe(dev_priv, pipe) {
24929352
DV		 13911 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13912 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 13913 intel_dump_pipe_config(crtc, crtc->config,
13914 "[setup_hw_state]");
24929352 13915 }
9a935856 13916
35c95375
DV		 13917 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13918 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13919
13920 if (!pll->on || pll->active)
13921 continue;
13922
13923 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13924
13925 pll->disable(dev_priv, pll);
13926 pll->on = false;
13927 }
13928
3078999f
PB		 13929 if (IS_GEN9(dev))
13930 skl_wm_get_hw_state(dev);
13931 else if (HAS_PCH_SPLIT(dev))
243e6a44
VS		 13932 ilk_wm_get_hw_state(dev);
13933
45e2b5f6 13934 if (force_restore) {
7d0bc1ea
VS		 13935 i915_redisable_vga(dev);
13936
f30da187
DV		 13937 /*
13938 * We need to use raw interfaces for restoring state to avoid
13939 * checking (bogus) intermediate states.
13940 */
055e393f 13941 for_each_pipe(dev_priv, pipe) {
b5644d05
JB		 13942 struct drm_crtc *crtc =
13943 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187 13944
7f27126e
JB		 13945 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13946 crtc->primary->fb);
45e2b5f6
DV		 13947 }
13948 } else {
13949 intel_modeset_update_staged_output_state(dev);
13950 }
8af6cf88
DV		 13951
13952 intel_modeset_check_state(dev);
2c7111db
CW		 13953}
13954
13955void intel_modeset_gem_init(struct drm_device *dev)
13956{
92122789 13957 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd 13958 struct drm_crtc *c;
2ff8fde1 13959 struct drm_i915_gem_object *obj;
484b41dd 13960
ae48434c
ID		 13961 mutex_lock(&dev->struct_mutex);
13962 intel_init_gt_powersave(dev);
13963 mutex_unlock(&dev->struct_mutex);
13964
92122789
JB		 13965 /*
13966 * There may be no VBT; and if the BIOS enabled SSC we can
13967 * just keep using it to avoid unnecessary flicker. Whereas if the
13968 * BIOS isn't using it, don't assume it will work even if the VBT
13969 * indicates as much.
13970 */
13971 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13972 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
13973 DREF_SSC1_ENABLE);
13974
1833b134 13975 intel_modeset_init_hw(dev);
02e792fb
DV		 13976
13977 intel_setup_overlay(dev);
484b41dd
JB		 13978
13979 /*
13980 * Make sure any fbs we allocated at startup are properly
13981 * pinned & fenced. When we do the allocation it's too early
13982 * for this.
13983 */
13984 mutex_lock(&dev->struct_mutex);
70e1e0ec 13985 for_each_crtc(dev, c) {
2ff8fde1
MR		 13986 obj = intel_fb_obj(c->primary->fb);
13987 if (obj == NULL)
484b41dd
JB		 13988 continue;
13989
850c4cdc
TU		 13990 if (intel_pin_and_fence_fb_obj(c->primary,
13991 c->primary->fb,
82bc3b2d 13992 c->primary->state,
850c4cdc 13993 NULL)) {
484b41dd
JB		 13994 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13995 to_intel_crtc(c)->pipe);
66e514c1
DA		 13996 drm_framebuffer_unreference(c->primary->fb);
13997 c->primary->fb = NULL;
afd65eb4 13998 update_state_fb(c->primary);
484b41dd
JB		 13999 }
14000 }
14001 mutex_unlock(&dev->struct_mutex);
0962c3c9
VS		 14002
14003 intel_backlight_register(dev);
79e53945
JB		 14004}
14005
4932e2c3
ID		 14006void intel_connector_unregister(struct intel_connector *intel_connector)
14007{
14008 struct drm_connector *connector = &intel_connector->base;
14009
14010 intel_panel_destroy_backlight(connector);
34ea3d38 14011 drm_connector_unregister(connector);
4932e2c3
ID		 14012}
14013
79e53945
JB		 14014void intel_modeset_cleanup(struct drm_device *dev)
14015{
652c393a 14016 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 14017 struct drm_connector *connector;
652c393a 14018
2eb5252e
ID		 14019 intel_disable_gt_powersave(dev);
14020
0962c3c9
VS		 14021 intel_backlight_unregister(dev);
14022
fd0c0642
DV		 14023 /*
14024 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 14025 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 14026 * experience fancy races otherwise.
14027 */
2aeb7d3a 14028 intel_irq_uninstall(dev_priv);
eb21b92b 14029
fd0c0642
DV		 14030 /*
14031 * Due to the hpd irq storm handling the hotplug work can re-arm the
14032 * poll handlers. Hence disable polling after hpd handling is shut down.
14033 */
f87ea761 14034 drm_kms_helper_poll_fini(dev);
fd0c0642 14035
652c393a
JB		 14036 mutex_lock(&dev->struct_mutex);
14037
723bfd70
JB		 14038 intel_unregister_dsm_handler();
14039
7ff0ebcc 14040 intel_fbc_disable(dev);
e70236a8 14041
69341a5e
KH		 14042 mutex_unlock(&dev->struct_mutex);
14043
1630fe75
CW		 14044 /* flush any delayed tasks or pending work */
14045 flush_scheduled_work();
14046
db31af1d
JN		 14047 /* destroy the backlight and sysfs files before encoders/connectors */
14048 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 14049 struct intel_connector *intel_connector;
14050
14051 intel_connector = to_intel_connector(connector);
14052 intel_connector->unregister(intel_connector);
db31af1d 14053 }
d9255d57 14054
79e53945 14055 drm_mode_config_cleanup(dev);
4d7bb011
DV		 14056
14057 intel_cleanup_overlay(dev);
ae48434c
ID		 14058
14059 mutex_lock(&dev->struct_mutex);
14060 intel_cleanup_gt_powersave(dev);
14061 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 14062}
14063
f1c79df3
ZW		 14064/*
14065 * Return which encoder is currently attached for connector.
14066 */
df0e9248 14067struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 14068{
df0e9248
CW		 14069 return &intel_attached_encoder(connector)->base;
14070}
f1c79df3 14071
df0e9248
CW		 14072void intel_connector_attach_encoder(struct intel_connector *connector,
14073 struct intel_encoder *encoder)
14074{
14075 connector->encoder = encoder;
14076 drm_mode_connector_attach_encoder(&connector->base,
14077 &encoder->base);
79e53945 14078}
28d52043
DA		 14079
14080/*
14081 * set vga decode state - true == enable VGA decode
14082 */
14083int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
14084{
14085 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 14086 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 14087 u16 gmch_ctrl;
14088
75fa041d
CW		 14089 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
14090 DRM_ERROR("failed to read control word\n");
14091 return -EIO;
14092 }
14093
c0cc8a55
CW		 14094 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
14095 return 0;
14096
28d52043
DA		 14097 if (state)
14098 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
14099 else
14100 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 14101
14102 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
14103 DRM_ERROR("failed to write control word\n");
14104 return -EIO;
14105 }
14106
28d52043
DA		 14107 return 0;
14108}
c4a1d9e4 14109
c4a1d9e4 14110struct intel_display_error_state {
ff57f1b0
PZ		 14111
14112 u32 power_well_driver;
14113
63b66e5b
CW		 14114 int num_transcoders;
14115
c4a1d9e4
CW		 14116 struct intel_cursor_error_state {
14117 u32 control;
14118 u32 position;
14119 u32 base;
14120 u32 size;
52331309 14121 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 14122
14123 struct intel_pipe_error_state {
ddf9c536 14124 bool power_domain_on;
c4a1d9e4 14125 u32 source;
f301b1e1 14126 u32 stat;
52331309 14127 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 14128
14129 struct intel_plane_error_state {
14130 u32 control;
14131 u32 stride;
14132 u32 size;
14133 u32 pos;
14134 u32 addr;
14135 u32 surface;
14136 u32 tile_offset;
52331309 14137 } plane[I915_MAX_PIPES];
63b66e5b
CW		 14138
14139 struct intel_transcoder_error_state {
ddf9c536 14140 bool power_domain_on;
63b66e5b
CW		 14141 enum transcoder cpu_transcoder;
14142
14143 u32 conf;
14144
14145 u32 htotal;
14146 u32 hblank;
14147 u32 hsync;
14148 u32 vtotal;
14149 u32 vblank;
14150 u32 vsync;
14151 } transcoder[4];
c4a1d9e4
CW		 14152};
14153
14154struct intel_display_error_state *
14155intel_display_capture_error_state(struct drm_device *dev)
14156{
fbee40df 14157 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 14158 struct intel_display_error_state *error;
63b66e5b
CW		 14159 int transcoders[] = {
14160 TRANSCODER_A,
14161 TRANSCODER_B,
14162 TRANSCODER_C,
14163 TRANSCODER_EDP,
14164 };
c4a1d9e4
CW		 14165 int i;
14166
63b66e5b
CW		 14167 if (INTEL_INFO(dev)->num_pipes == 0)
14168 return NULL;
14169
9d1cb914 14170 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 14171 if (error == NULL)
14172 return NULL;
14173
190be112 14174 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 14175 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
14176
055e393f 14177 for_each_pipe(dev_priv, i) {
ddf9c536 14178 error->pipe[i].power_domain_on =
f458ebbc
DV		 14179 __intel_display_power_is_enabled(dev_priv,
14180 POWER_DOMAIN_PIPE(i));
ddf9c536 14181 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 14182 continue;
14183
5efb3e28
VS		 14184 error->cursor[i].control = I915_READ(CURCNTR(i));
14185 error->cursor[i].position = I915_READ(CURPOS(i));
14186 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 14187
14188 error->plane[i].control = I915_READ(DSPCNTR(i));
14189 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 14190 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 14191 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 14192 error->plane[i].pos = I915_READ(DSPPOS(i));
14193 }
ca291363
PZ		 14194 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14195 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 14196 if (INTEL_INFO(dev)->gen >= 4) {
14197 error->plane[i].surface = I915_READ(DSPSURF(i));
14198 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
14199 }
14200
c4a1d9e4 14201 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 14202
3abfce77 14203 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 14204 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 14205 }
14206
14207 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
14208 if (HAS_DDI(dev_priv->dev))
14209 error->num_transcoders++; /* Account for eDP. */
14210
14211 for (i = 0; i < error->num_transcoders; i++) {
14212 enum transcoder cpu_transcoder = transcoders[i];
14213
ddf9c536 14214 error->transcoder[i].power_domain_on =
f458ebbc 14215 __intel_display_power_is_enabled(dev_priv,
38cc1daf 14216 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 14217 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 14218 continue;
14219
63b66e5b
CW		 14220 error->transcoder[i].cpu_transcoder = cpu_transcoder;
14221
14222 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
14223 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
14224 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
14225 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
14226 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
14227 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
14228 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 14229 }
14230
14231 return error;
14232}
14233
edc3d884
MK		 14234#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
14235
c4a1d9e4 14236void
edc3d884 14237intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 14238 struct drm_device *dev,
14239 struct intel_display_error_state *error)
14240{
055e393f 14241 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 14242 int i;
14243
63b66e5b
CW		 14244 if (!error)
14245 return;
14246
edc3d884 14247 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 14248 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 14249 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 14250 error->power_well_driver);
055e393f 14251 for_each_pipe(dev_priv, i) {
edc3d884 14252 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 14253 err_printf(m, " Power: %s\n",
14254 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 14255 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 14256 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 14257
14258 err_printf(m, "Plane [%d]:\n", i);
14259 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
14260 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 14261 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 14262 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
14263 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 14264 }
4b71a570 14265 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 14266 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 14267 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 14268 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
14269 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 14270 }
14271
edc3d884
MK		 14272 err_printf(m, "Cursor [%d]:\n", i);
14273 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
14274 err_printf(m, " POS: %08x\n", error->cursor[i].position);
14275 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 14276 }
63b66e5b
CW		 14277
14278 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 14279 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 14280 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 14281 err_printf(m, " Power: %s\n",
14282 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 14283 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
14284 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
14285 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
14286 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
14287 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
14288 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
14289 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
14290 }
c4a1d9e4 14291}
e2fcdaa9
VS		 14292
14293void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
14294{
14295 struct intel_crtc *crtc;
14296
14297 for_each_intel_crtc(dev, crtc) {
14298 struct intel_unpin_work *work;
e2fcdaa9 14299
5e2d7afc 14300 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 14301
14302 work = crtc->unpin_work;
14303
14304 if (work && work->event &&
14305 work->event->base.file_priv == file) {
14306 kfree(work->event);
14307 work->event = NULL;
14308 }
14309
5e2d7afc 14310 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 14311 }
14312}
Linux kernel - Deliverables
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