projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: Remove usage of encoder->new_crtc from clock computations
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c
MR		 48/* Primary plane formats supported by all gen */
49#define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_C8, \
51 DRM_FORMAT_RGB565, \
52 DRM_FORMAT_XRGB8888, \
53 DRM_FORMAT_ARGB8888
54
55/* Primary plane formats for gen <= 3 */
56static const uint32_t intel_primary_formats_gen2[] = {
57 COMMON_PRIMARY_FORMATS,
58 DRM_FORMAT_XRGB1555,
59 DRM_FORMAT_ARGB1555,
60};
61
62/* Primary plane formats for gen >= 4 */
63static const uint32_t intel_primary_formats_gen4[] = {
64 COMMON_PRIMARY_FORMATS, \
65 DRM_FORMAT_XBGR8888,
66 DRM_FORMAT_ABGR8888,
67 DRM_FORMAT_XRGB2101010,
68 DRM_FORMAT_ARGB2101010,
69 DRM_FORMAT_XBGR2101010,
70 DRM_FORMAT_ABGR2101010,
71};
72
3d7d6510
MR		 73/* Cursor formats */
74static const uint32_t intel_cursor_formats[] = {
75 DRM_FORMAT_ARGB8888,
76};
77
6b383a7f 78static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 79
f1f644dc 80static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 81 struct intel_crtc_state *pipe_config);
18442d08 82static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 83 struct intel_crtc_state *pipe_config);
f1f644dc 84
e7457a9a 85static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
83a57153
ACO		 86 int x, int y, struct drm_framebuffer *old_fb,
87 struct drm_atomic_state *state);
eb1bfe80
JB		 88static int intel_framebuffer_init(struct drm_device *dev,
89 struct intel_framebuffer *ifb,
90 struct drm_mode_fb_cmd2 *mode_cmd,
91 struct drm_i915_gem_object *obj);
5b18e57c
DV		 92static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
93static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 94static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 95 struct intel_link_m_n *m_n,
96 struct intel_link_m_n *m2_n2);
29407aab 97static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 98static void haswell_set_pipeconf(struct drm_crtc *crtc);
99static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 100static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 101 const struct intel_crtc_state *pipe_config);
d288f65f 102static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 103 const struct intel_crtc_state *pipe_config);
ea2c67bb
MR		 104static void intel_begin_crtc_commit(struct drm_crtc *crtc);
105static void intel_finish_crtc_commit(struct drm_crtc *crtc);
e7457a9a 106
0e32b39c
DA		 107static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
108{
109 if (!connector->mst_port)
110 return connector->encoder;
111 else
112 return &connector->mst_port->mst_encoders[pipe]->base;
113}
114
79e53945 115typedef struct {
0206e353 116 int min, max;
79e53945
JB		 117} intel_range_t;
118
119typedef struct {
0206e353
AJ		 120 int dot_limit;
121 int p2_slow, p2_fast;
79e53945
JB		 122} intel_p2_t;
123
d4906093
ML		 124typedef struct intel_limit intel_limit_t;
125struct intel_limit {
0206e353
AJ		 126 intel_range_t dot, vco, n, m, m1, m2, p, p1;
127 intel_p2_t p2;
d4906093 128};
79e53945 129
d2acd215
DV		 130int
131intel_pch_rawclk(struct drm_device *dev)
132{
133 struct drm_i915_private *dev_priv = dev->dev_private;
134
135 WARN_ON(!HAS_PCH_SPLIT(dev));
136
137 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
138}
139
021357ac
CW		 140static inline u32 /* units of 100MHz */
141intel_fdi_link_freq(struct drm_device *dev)
142{
8b99e68c
CW		 143 if (IS_GEN5(dev)) {
144 struct drm_i915_private *dev_priv = dev->dev_private;
145 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
146 } else
147 return 27;
021357ac
CW		 148}
149
5d536e28 150static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 151 .dot = { .min = 25000, .max = 350000 },
9c333719 152 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 153 .n = { .min = 2, .max = 16 },
0206e353
AJ		 154 .m = { .min = 96, .max = 140 },
155 .m1 = { .min = 18, .max = 26 },
156 .m2 = { .min = 6, .max = 16 },
157 .p = { .min = 4, .max = 128 },
158 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 159 .p2 = { .dot_limit = 165000,
160 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 161};
162
5d536e28
DV		 163static const intel_limit_t intel_limits_i8xx_dvo = {
164 .dot = { .min = 25000, .max = 350000 },
9c333719 165 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 166 .n = { .min = 2, .max = 16 },
5d536e28
DV		 167 .m = { .min = 96, .max = 140 },
168 .m1 = { .min = 18, .max = 26 },
169 .m2 = { .min = 6, .max = 16 },
170 .p = { .min = 4, .max = 128 },
171 .p1 = { .min = 2, .max = 33 },
172 .p2 = { .dot_limit = 165000,
173 .p2_slow = 4, .p2_fast = 4 },
174};
175
e4b36699 176static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 177 .dot = { .min = 25000, .max = 350000 },
9c333719 178 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 179 .n = { .min = 2, .max = 16 },
0206e353
AJ		 180 .m = { .min = 96, .max = 140 },
181 .m1 = { .min = 18, .max = 26 },
182 .m2 = { .min = 6, .max = 16 },
183 .p = { .min = 4, .max = 128 },
184 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 185 .p2 = { .dot_limit = 165000,
186 .p2_slow = 14, .p2_fast = 7 },
e4b36699 187};
273e27ca 188
e4b36699 189static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 190 .dot = { .min = 20000, .max = 400000 },
191 .vco = { .min = 1400000, .max = 2800000 },
192 .n = { .min = 1, .max = 6 },
193 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 194 .m1 = { .min = 8, .max = 18 },
195 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 196 .p = { .min = 5, .max = 80 },
197 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 198 .p2 = { .dot_limit = 200000,
199 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 200};
201
202static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 203 .dot = { .min = 20000, .max = 400000 },
204 .vco = { .min = 1400000, .max = 2800000 },
205 .n = { .min = 1, .max = 6 },
206 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 207 .m1 = { .min = 8, .max = 18 },
208 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 209 .p = { .min = 7, .max = 98 },
210 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 211 .p2 = { .dot_limit = 112000,
212 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 213};
214
273e27ca 215
e4b36699 216static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 217 .dot = { .min = 25000, .max = 270000 },
218 .vco = { .min = 1750000, .max = 3500000},
219 .n = { .min = 1, .max = 4 },
220 .m = { .min = 104, .max = 138 },
221 .m1 = { .min = 17, .max = 23 },
222 .m2 = { .min = 5, .max = 11 },
223 .p = { .min = 10, .max = 30 },
224 .p1 = { .min = 1, .max = 3},
225 .p2 = { .dot_limit = 270000,
226 .p2_slow = 10,
227 .p2_fast = 10
044c7c41 228 },
e4b36699
KP		 229};
230
231static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 232 .dot = { .min = 22000, .max = 400000 },
233 .vco = { .min = 1750000, .max = 3500000},
234 .n = { .min = 1, .max = 4 },
235 .m = { .min = 104, .max = 138 },
236 .m1 = { .min = 16, .max = 23 },
237 .m2 = { .min = 5, .max = 11 },
238 .p = { .min = 5, .max = 80 },
239 .p1 = { .min = 1, .max = 8},
240 .p2 = { .dot_limit = 165000,
241 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 242};
243
244static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 245 .dot = { .min = 20000, .max = 115000 },
246 .vco = { .min = 1750000, .max = 3500000 },
247 .n = { .min = 1, .max = 3 },
248 .m = { .min = 104, .max = 138 },
249 .m1 = { .min = 17, .max = 23 },
250 .m2 = { .min = 5, .max = 11 },
251 .p = { .min = 28, .max = 112 },
252 .p1 = { .min = 2, .max = 8 },
253 .p2 = { .dot_limit = 0,
254 .p2_slow = 14, .p2_fast = 14
044c7c41 255 },
e4b36699
KP		 256};
257
258static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 259 .dot = { .min = 80000, .max = 224000 },
260 .vco = { .min = 1750000, .max = 3500000 },
261 .n = { .min = 1, .max = 3 },
262 .m = { .min = 104, .max = 138 },
263 .m1 = { .min = 17, .max = 23 },
264 .m2 = { .min = 5, .max = 11 },
265 .p = { .min = 14, .max = 42 },
266 .p1 = { .min = 2, .max = 6 },
267 .p2 = { .dot_limit = 0,
268 .p2_slow = 7, .p2_fast = 7
044c7c41 269 },
e4b36699
KP		 270};
271
f2b115e6 272static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 273 .dot = { .min = 20000, .max = 400000},
274 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 275 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 276 .n = { .min = 3, .max = 6 },
277 .m = { .min = 2, .max = 256 },
273e27ca 278 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 279 .m1 = { .min = 0, .max = 0 },
280 .m2 = { .min = 0, .max = 254 },
281 .p = { .min = 5, .max = 80 },
282 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 283 .p2 = { .dot_limit = 200000,
284 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 285};
286
f2b115e6 287static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 288 .dot = { .min = 20000, .max = 400000 },
289 .vco = { .min = 1700000, .max = 3500000 },
290 .n = { .min = 3, .max = 6 },
291 .m = { .min = 2, .max = 256 },
292 .m1 = { .min = 0, .max = 0 },
293 .m2 = { .min = 0, .max = 254 },
294 .p = { .min = 7, .max = 112 },
295 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 296 .p2 = { .dot_limit = 112000,
297 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 298};
299
273e27ca
EA		 300/* Ironlake / Sandybridge
301 *
302 * We calculate clock using (register_value + 2) for N/M1/M2, so here
303 * the range value for them is (actual_value - 2).
304 */
b91ad0ec 305static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 306 .dot = { .min = 25000, .max = 350000 },
307 .vco = { .min = 1760000, .max = 3510000 },
308 .n = { .min = 1, .max = 5 },
309 .m = { .min = 79, .max = 127 },
310 .m1 = { .min = 12, .max = 22 },
311 .m2 = { .min = 5, .max = 9 },
312 .p = { .min = 5, .max = 80 },
313 .p1 = { .min = 1, .max = 8 },
314 .p2 = { .dot_limit = 225000,
315 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 316};
317
b91ad0ec 318static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 319 .dot = { .min = 25000, .max = 350000 },
320 .vco = { .min = 1760000, .max = 3510000 },
321 .n = { .min = 1, .max = 3 },
322 .m = { .min = 79, .max = 118 },
323 .m1 = { .min = 12, .max = 22 },
324 .m2 = { .min = 5, .max = 9 },
325 .p = { .min = 28, .max = 112 },
326 .p1 = { .min = 2, .max = 8 },
327 .p2 = { .dot_limit = 225000,
328 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 329};
330
331static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 332 .dot = { .min = 25000, .max = 350000 },
333 .vco = { .min = 1760000, .max = 3510000 },
334 .n = { .min = 1, .max = 3 },
335 .m = { .min = 79, .max = 127 },
336 .m1 = { .min = 12, .max = 22 },
337 .m2 = { .min = 5, .max = 9 },
338 .p = { .min = 14, .max = 56 },
339 .p1 = { .min = 2, .max = 8 },
340 .p2 = { .dot_limit = 225000,
341 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 342};
343
273e27ca 344/* LVDS 100mhz refclk limits. */
b91ad0ec 345static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 346 .dot = { .min = 25000, .max = 350000 },
347 .vco = { .min = 1760000, .max = 3510000 },
348 .n = { .min = 1, .max = 2 },
349 .m = { .min = 79, .max = 126 },
350 .m1 = { .min = 12, .max = 22 },
351 .m2 = { .min = 5, .max = 9 },
352 .p = { .min = 28, .max = 112 },
0206e353 353 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 354 .p2 = { .dot_limit = 225000,
355 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 356};
357
358static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 359 .dot = { .min = 25000, .max = 350000 },
360 .vco = { .min = 1760000, .max = 3510000 },
361 .n = { .min = 1, .max = 3 },
362 .m = { .min = 79, .max = 126 },
363 .m1 = { .min = 12, .max = 22 },
364 .m2 = { .min = 5, .max = 9 },
365 .p = { .min = 14, .max = 42 },
0206e353 366 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 367 .p2 = { .dot_limit = 225000,
368 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 369};
370
dc730512 371static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 372 /*
373 * These are the data rate limits (measured in fast clocks)
374 * since those are the strictest limits we have. The fast
375 * clock and actual rate limits are more relaxed, so checking
376 * them would make no difference.
377 */
378 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 379 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 380 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 381 .m1 = { .min = 2, .max = 3 },
382 .m2 = { .min = 11, .max = 156 },
b99ab663 383 .p1 = { .min = 2, .max = 3 },
5fdc9c49 384 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 385};
386
ef9348c8
CML		 387static const intel_limit_t intel_limits_chv = {
388 /*
389 * These are the data rate limits (measured in fast clocks)
390 * since those are the strictest limits we have. The fast
391 * clock and actual rate limits are more relaxed, so checking
392 * them would make no difference.
393 */
394 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 395 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 396 .n = { .min = 1, .max = 1 },
397 .m1 = { .min = 2, .max = 2 },
398 .m2 = { .min = 24 << 22, .max = 175 << 22 },
399 .p1 = { .min = 2, .max = 4 },
400 .p2 = { .p2_slow = 1, .p2_fast = 14 },
401};
402
6b4bf1c4
VS		 403static void vlv_clock(int refclk, intel_clock_t *clock)
404{
405 clock->m = clock->m1 * clock->m2;
406 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 407 if (WARN_ON(clock->n == 0 || clock->p == 0))
408 return;
fb03ac01
VS		 409 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
410 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
6b4bf1c4
VS		 411}
412
e0638cdf
PZ		 413/**
414 * Returns whether any output on the specified pipe is of the specified type
415 */
4093561b 416bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 417{
409ee761 418 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 419 struct intel_encoder *encoder;
420
409ee761 421 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 422 if (encoder->type == type)
423 return true;
424
425 return false;
426}
427
d0737e1d
ACO		 428/**
429 * Returns whether any output on the specified pipe will have the specified
430 * type after a staged modeset is complete, i.e., the same as
431 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
432 * encoder->crtc.
433 */
a93e255f
ACO		 434static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
435 int type)
d0737e1d 436{
a93e255f
ACO		 437 struct drm_atomic_state *state = crtc_state->base.state;
438 struct drm_connector_state *connector_state;
d0737e1d 439 struct intel_encoder *encoder;
a93e255f
ACO		 440 int i, num_connectors = 0;
441
442 for (i = 0; i < state->num_connector; i++) {
443 if (!state->connectors[i])
444 continue;
445
446 connector_state = state->connector_states[i];
447 if (connector_state->crtc != crtc_state->base.crtc)
448 continue;
449
450 num_connectors++;
d0737e1d 451
a93e255f
ACO		 452 encoder = to_intel_encoder(connector_state->best_encoder);
453 if (encoder->type == type)
d0737e1d 454 return true;
a93e255f
ACO		 455 }
456
457 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 458
459 return false;
460}
461
a93e255f
ACO		 462static const intel_limit_t *
463intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 464{
a93e255f 465 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 466 const intel_limit_t *limit;
b91ad0ec 467
a93e255f 468 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 469 if (intel_is_dual_link_lvds(dev)) {
1b894b59 470 if (refclk == 100000)
b91ad0ec
ZW		 471 limit = &intel_limits_ironlake_dual_lvds_100m;
472 else
473 limit = &intel_limits_ironlake_dual_lvds;
474 } else {
1b894b59 475 if (refclk == 100000)
b91ad0ec
ZW		 476 limit = &intel_limits_ironlake_single_lvds_100m;
477 else
478 limit = &intel_limits_ironlake_single_lvds;
479 }
c6bb3538 480 } else
b91ad0ec 481 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 482
483 return limit;
484}
485
a93e255f
ACO		 486static const intel_limit_t *
487intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 488{
a93e255f 489 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 490 const intel_limit_t *limit;
491
a93e255f 492 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 493 if (intel_is_dual_link_lvds(dev))
e4b36699 494 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 495 else
e4b36699 496 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 497 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
498 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 499 limit = &intel_limits_g4x_hdmi;
a93e255f 500 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 501 limit = &intel_limits_g4x_sdvo;
044c7c41 502 } else /* The option is for other outputs */
e4b36699 503 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 504
505 return limit;
506}
507
a93e255f
ACO		 508static const intel_limit_t *
509intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 510{
a93e255f 511 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 512 const intel_limit_t *limit;
513
bad720ff 514 if (HAS_PCH_SPLIT(dev))
a93e255f 515 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 516 else if (IS_G4X(dev)) {
a93e255f 517 limit = intel_g4x_limit(crtc_state);
f2b115e6 518 } else if (IS_PINEVIEW(dev)) {
a93e255f 519 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 520 limit = &intel_limits_pineview_lvds;
2177832f 521 else
f2b115e6 522 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 523 } else if (IS_CHERRYVIEW(dev)) {
524 limit = &intel_limits_chv;
a0c4da24 525 } else if (IS_VALLEYVIEW(dev)) {
dc730512 526 limit = &intel_limits_vlv;
a6c45cf0 527 } else if (!IS_GEN2(dev)) {
a93e255f 528 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 529 limit = &intel_limits_i9xx_lvds;
530 else
531 limit = &intel_limits_i9xx_sdvo;
79e53945 532 } else {
a93e255f 533 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 534 limit = &intel_limits_i8xx_lvds;
a93e255f 535 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 536 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 537 else
538 limit = &intel_limits_i8xx_dac;
79e53945
JB		 539 }
540 return limit;
541}
542
f2b115e6
AJ		 543/* m1 is reserved as 0 in Pineview, n is a ring counter */
544static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 545{
2177832f
SL		 546 clock->m = clock->m2 + 2;
547 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 548 if (WARN_ON(clock->n == 0 || clock->p == 0))
549 return;
fb03ac01
VS		 550 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
551 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
2177832f
SL		 552}
553
7429e9d4
DV		 554static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
555{
556 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
557}
558
ac58c3f0 559static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 560{
7429e9d4 561 clock->m = i9xx_dpll_compute_m(clock);
79e53945 562 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 563 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
564 return;
fb03ac01
VS		 565 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
566 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
79e53945
JB		 567}
568
ef9348c8
CML		 569static void chv_clock(int refclk, intel_clock_t *clock)
570{
571 clock->m = clock->m1 * clock->m2;
572 clock->p = clock->p1 * clock->p2;
573 if (WARN_ON(clock->n == 0 || clock->p == 0))
574 return;
575 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
576 clock->n << 22);
577 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
578}
579
7c04d1d9 580#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 581/**
582 * Returns whether the given set of divisors are valid for a given refclk with
583 * the given connectors.
584 */
585
1b894b59
CW		 586static bool intel_PLL_is_valid(struct drm_device *dev,
587 const intel_limit_t *limit,
588 const intel_clock_t *clock)
79e53945 589{
f01b7962
VS		 590 if (clock->n < limit->n.min || limit->n.max < clock->n)
591 INTELPllInvalid("n out of range\n");
79e53945 592 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 593 INTELPllInvalid("p1 out of range\n");
79e53945 594 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 595 INTELPllInvalid("m2 out of range\n");
79e53945 596 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 597 INTELPllInvalid("m1 out of range\n");
f01b7962
VS		 598
599 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
600 if (clock->m1 <= clock->m2)
601 INTELPllInvalid("m1 <= m2\n");
602
603 if (!IS_VALLEYVIEW(dev)) {
604 if (clock->p < limit->p.min || limit->p.max < clock->p)
605 INTELPllInvalid("p out of range\n");
606 if (clock->m < limit->m.min || limit->m.max < clock->m)
607 INTELPllInvalid("m out of range\n");
608 }
609
79e53945 610 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 611 INTELPllInvalid("vco out of range\n");
79e53945
JB		 612 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
613 * connector, etc., rather than just a single range.
614 */
615 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 616 INTELPllInvalid("dot out of range\n");
79e53945
JB		 617
618 return true;
619}
620
d4906093 621static bool
a93e255f
ACO		 622i9xx_find_best_dpll(const intel_limit_t *limit,
623 struct intel_crtc_state *crtc_state,
cec2f356
SP		 624 int target, int refclk, intel_clock_t *match_clock,
625 intel_clock_t *best_clock)
79e53945 626{
a93e255f 627 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 628 struct drm_device *dev = crtc->base.dev;
79e53945 629 intel_clock_t clock;
79e53945
JB		 630 int err = target;
631
a93e255f 632 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 633 /*
a210b028
DV		 634 * For LVDS just rely on its current settings for dual-channel.
635 * We haven't figured out how to reliably set up different
636 * single/dual channel state, if we even can.
79e53945 637 */
1974cad0 638 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 639 clock.p2 = limit->p2.p2_fast;
640 else
641 clock.p2 = limit->p2.p2_slow;
642 } else {
643 if (target < limit->p2.dot_limit)
644 clock.p2 = limit->p2.p2_slow;
645 else
646 clock.p2 = limit->p2.p2_fast;
647 }
648
0206e353 649 memset(best_clock, 0, sizeof(*best_clock));
79e53945 650
42158660
ZY		 651 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
652 clock.m1++) {
653 for (clock.m2 = limit->m2.min;
654 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 655 if (clock.m2 >= clock.m1)
42158660
ZY		 656 break;
657 for (clock.n = limit->n.min;
658 clock.n <= limit->n.max; clock.n++) {
659 for (clock.p1 = limit->p1.min;
660 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 661 int this_err;
662
ac58c3f0
DV		 663 i9xx_clock(refclk, &clock);
664 if (!intel_PLL_is_valid(dev, limit,
665 &clock))
666 continue;
667 if (match_clock &&
668 clock.p != match_clock->p)
669 continue;
670
671 this_err = abs(clock.dot - target);
672 if (this_err < err) {
673 *best_clock = clock;
674 err = this_err;
675 }
676 }
677 }
678 }
679 }
680
681 return (err != target);
682}
683
684static bool
a93e255f
ACO		 685pnv_find_best_dpll(const intel_limit_t *limit,
686 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 687 int target, int refclk, intel_clock_t *match_clock,
688 intel_clock_t *best_clock)
79e53945 689{
a93e255f 690 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 691 struct drm_device *dev = crtc->base.dev;
79e53945 692 intel_clock_t clock;
79e53945
JB		 693 int err = target;
694
a93e255f 695 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 696 /*
a210b028
DV		 697 * For LVDS just rely on its current settings for dual-channel.
698 * We haven't figured out how to reliably set up different
699 * single/dual channel state, if we even can.
79e53945 700 */
1974cad0 701 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 702 clock.p2 = limit->p2.p2_fast;
703 else
704 clock.p2 = limit->p2.p2_slow;
705 } else {
706 if (target < limit->p2.dot_limit)
707 clock.p2 = limit->p2.p2_slow;
708 else
709 clock.p2 = limit->p2.p2_fast;
710 }
711
0206e353 712 memset(best_clock, 0, sizeof(*best_clock));
79e53945 713
42158660
ZY		 714 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
715 clock.m1++) {
716 for (clock.m2 = limit->m2.min;
717 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 718 for (clock.n = limit->n.min;
719 clock.n <= limit->n.max; clock.n++) {
720 for (clock.p1 = limit->p1.min;
721 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 722 int this_err;
723
ac58c3f0 724 pineview_clock(refclk, &clock);
1b894b59
CW		 725 if (!intel_PLL_is_valid(dev, limit,
726 &clock))
79e53945 727 continue;
cec2f356
SP		 728 if (match_clock &&
729 clock.p != match_clock->p)
730 continue;
79e53945
JB		 731
732 this_err = abs(clock.dot - target);
733 if (this_err < err) {
734 *best_clock = clock;
735 err = this_err;
736 }
737 }
738 }
739 }
740 }
741
742 return (err != target);
743}
744
d4906093 745static bool
a93e255f
ACO		 746g4x_find_best_dpll(const intel_limit_t *limit,
747 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 748 int target, int refclk, intel_clock_t *match_clock,
749 intel_clock_t *best_clock)
d4906093 750{
a93e255f 751 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 752 struct drm_device *dev = crtc->base.dev;
d4906093
ML		 753 intel_clock_t clock;
754 int max_n;
755 bool found;
6ba770dc
AJ		 756 /* approximately equals target * 0.00585 */
757 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 758 found = false;
759
a93e255f 760 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 761 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 762 clock.p2 = limit->p2.p2_fast;
763 else
764 clock.p2 = limit->p2.p2_slow;
765 } else {
766 if (target < limit->p2.dot_limit)
767 clock.p2 = limit->p2.p2_slow;
768 else
769 clock.p2 = limit->p2.p2_fast;
770 }
771
772 memset(best_clock, 0, sizeof(*best_clock));
773 max_n = limit->n.max;
f77f13e2 774 /* based on hardware requirement, prefer smaller n to precision */
d4906093 775 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 776 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 777 for (clock.m1 = limit->m1.max;
778 clock.m1 >= limit->m1.min; clock.m1--) {
779 for (clock.m2 = limit->m2.max;
780 clock.m2 >= limit->m2.min; clock.m2--) {
781 for (clock.p1 = limit->p1.max;
782 clock.p1 >= limit->p1.min; clock.p1--) {
783 int this_err;
784
ac58c3f0 785 i9xx_clock(refclk, &clock);
1b894b59
CW		 786 if (!intel_PLL_is_valid(dev, limit,
787 &clock))
d4906093 788 continue;
1b894b59
CW		 789
790 this_err = abs(clock.dot - target);
d4906093
ML		 791 if (this_err < err_most) {
792 *best_clock = clock;
793 err_most = this_err;
794 max_n = clock.n;
795 found = true;
796 }
797 }
798 }
799 }
800 }
2c07245f
ZW		 801 return found;
802}
803
d5dd62bd
ID		 804/*
805 * Check if the calculated PLL configuration is more optimal compared to the
806 * best configuration and error found so far. Return the calculated error.
807 */
808static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
809 const intel_clock_t *calculated_clock,
810 const intel_clock_t *best_clock,
811 unsigned int best_error_ppm,
812 unsigned int *error_ppm)
813{
9ca3ba01
ID		 814 /*
815 * For CHV ignore the error and consider only the P value.
816 * Prefer a bigger P value based on HW requirements.
817 */
818 if (IS_CHERRYVIEW(dev)) {
819 *error_ppm = 0;
820
821 return calculated_clock->p > best_clock->p;
822 }
823
24be4e46
ID		 824 if (WARN_ON_ONCE(!target_freq))
825 return false;
826
d5dd62bd
ID		 827 *error_ppm = div_u64(1000000ULL *
828 abs(target_freq - calculated_clock->dot),
829 target_freq);
830 /*
831 * Prefer a better P value over a better (smaller) error if the error
832 * is small. Ensure this preference for future configurations too by
833 * setting the error to 0.
834 */
835 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
836 *error_ppm = 0;
837
838 return true;
839 }
840
841 return *error_ppm + 10 < best_error_ppm;
842}
843
a0c4da24 844static bool
a93e255f
ACO		 845vlv_find_best_dpll(const intel_limit_t *limit,
846 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 847 int target, int refclk, intel_clock_t *match_clock,
848 intel_clock_t *best_clock)
a0c4da24 849{
a93e255f 850 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 851 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 852 intel_clock_t clock;
69e4f900 853 unsigned int bestppm = 1000000;
27e639bf
VS		 854 /* min update 19.2 MHz */
855 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 856 bool found = false;
a0c4da24 857
6b4bf1c4
VS		 858 target *= 5; /* fast clock */
859
860 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 861
862 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 863 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 864 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 865 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 866 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 867 clock.p = clock.p1 * clock.p2;
a0c4da24 868 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 869 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 870 unsigned int ppm;
69e4f900 871
6b4bf1c4
VS		 872 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
873 refclk * clock.m1);
874
875 vlv_clock(refclk, &clock);
43b0ac53 876
f01b7962
VS		 877 if (!intel_PLL_is_valid(dev, limit,
878 &clock))
43b0ac53
VS		 879 continue;
880
d5dd62bd
ID		 881 if (!vlv_PLL_is_optimal(dev, target,
882 &clock,
883 best_clock,
884 bestppm, &ppm))
885 continue;
6b4bf1c4 886
d5dd62bd
ID		 887 *best_clock = clock;
888 bestppm = ppm;
889 found = true;
a0c4da24
JB		 890 }
891 }
892 }
893 }
a0c4da24 894
49e497ef 895 return found;
a0c4da24 896}
a4fc5ed6 897
ef9348c8 898static bool
a93e255f
ACO		 899chv_find_best_dpll(const intel_limit_t *limit,
900 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 901 int target, int refclk, intel_clock_t *match_clock,
902 intel_clock_t *best_clock)
903{
a93e255f 904 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 905 struct drm_device *dev = crtc->base.dev;
9ca3ba01 906 unsigned int best_error_ppm;
ef9348c8
CML		 907 intel_clock_t clock;
908 uint64_t m2;
909 int found = false;
910
911 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 912 best_error_ppm = 1000000;
ef9348c8
CML		 913
914 /*
915 * Based on hardware doc, the n always set to 1, and m1 always
916 * set to 2. If requires to support 200Mhz refclk, we need to
917 * revisit this because n may not 1 anymore.
918 */
919 clock.n = 1, clock.m1 = 2;
920 target *= 5; /* fast clock */
921
922 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
923 for (clock.p2 = limit->p2.p2_fast;
924 clock.p2 >= limit->p2.p2_slow;
925 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 926 unsigned int error_ppm;
ef9348c8
CML		 927
928 clock.p = clock.p1 * clock.p2;
929
930 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
931 clock.n) << 22, refclk * clock.m1);
932
933 if (m2 > INT_MAX/clock.m1)
934 continue;
935
936 clock.m2 = m2;
937
938 chv_clock(refclk, &clock);
939
940 if (!intel_PLL_is_valid(dev, limit, &clock))
941 continue;
942
9ca3ba01
ID		 943 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
944 best_error_ppm, &error_ppm))
945 continue;
946
947 *best_clock = clock;
948 best_error_ppm = error_ppm;
949 found = true;
ef9348c8
CML		 950 }
951 }
952
953 return found;
954}
955
20ddf665
VS		 956bool intel_crtc_active(struct drm_crtc *crtc)
957{
958 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
959
960 /* Be paranoid as we can arrive here with only partial
961 * state retrieved from the hardware during setup.
962 *
241bfc38 963 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 964 * as Haswell has gained clock readout/fastboot support.
965 *
66e514c1 966 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 967 * properly reconstruct framebuffers.
c3d1f436
MR		 968 *
969 * FIXME: The intel_crtc->active here should be switched to
970 * crtc->state->active once we have proper CRTC states wired up
971 * for atomic.
20ddf665 972 */
c3d1f436 973 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 974 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 975}
976
a5c961d1
PZ		 977enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
978 enum pipe pipe)
979{
980 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
981 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
982
6e3c9717 983 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 984}
985
fbf49ea2
VS		 986static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
987{
988 struct drm_i915_private *dev_priv = dev->dev_private;
989 u32 reg = PIPEDSL(pipe);
990 u32 line1, line2;
991 u32 line_mask;
992
993 if (IS_GEN2(dev))
994 line_mask = DSL_LINEMASK_GEN2;
995 else
996 line_mask = DSL_LINEMASK_GEN3;
997
998 line1 = I915_READ(reg) & line_mask;
999 mdelay(5);
1000 line2 = I915_READ(reg) & line_mask;
1001
1002 return line1 == line2;
1003}
1004
ab7ad7f6
KP		 1005/*
1006 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1007 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1008 *
1009 * After disabling a pipe, we can't wait for vblank in the usual way,
1010 * spinning on the vblank interrupt status bit, since we won't actually
1011 * see an interrupt when the pipe is disabled.
1012 *
ab7ad7f6
KP		 1013 * On Gen4 and above:
1014 * wait for the pipe register state bit to turn off
1015 *
1016 * Otherwise:
1017 * wait for the display line value to settle (it usually
1018 * ends up stopping at the start of the next frame).
58e10eb9 1019 *
9d0498a2 1020 */
575f7ab7 1021static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1022{
575f7ab7 1023 struct drm_device *dev = crtc->base.dev;
9d0498a2 1024 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1025 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1026 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1027
1028 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1029 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1030
1031 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1032 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1033 100))
284637d9 1034 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1035 } else {
ab7ad7f6 1036 /* Wait for the display line to settle */
fbf49ea2 1037 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1038 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1039 }
79e53945
JB		 1040}
1041
b0ea7d37
DL		 1042/*
1043 * ibx_digital_port_connected - is the specified port connected?
1044 * @dev_priv: i915 private structure
1045 * @port: the port to test
1046 *
1047 * Returns true if @port is connected, false otherwise.
1048 */
1049bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1050 struct intel_digital_port *port)
1051{
1052 u32 bit;
1053
c36346e3 1054 if (HAS_PCH_IBX(dev_priv->dev)) {
eba905b2 1055 switch (port->port) {
c36346e3
DL		 1056 case PORT_B:
1057 bit = SDE_PORTB_HOTPLUG;
1058 break;
1059 case PORT_C:
1060 bit = SDE_PORTC_HOTPLUG;
1061 break;
1062 case PORT_D:
1063 bit = SDE_PORTD_HOTPLUG;
1064 break;
1065 default:
1066 return true;
1067 }
1068 } else {
eba905b2 1069 switch (port->port) {
c36346e3
DL		 1070 case PORT_B:
1071 bit = SDE_PORTB_HOTPLUG_CPT;
1072 break;
1073 case PORT_C:
1074 bit = SDE_PORTC_HOTPLUG_CPT;
1075 break;
1076 case PORT_D:
1077 bit = SDE_PORTD_HOTPLUG_CPT;
1078 break;
1079 default:
1080 return true;
1081 }
b0ea7d37
DL		 1082 }
1083
1084 return I915_READ(SDEISR) & bit;
1085}
1086
b24e7179
JB		 1087static const char *state_string(bool enabled)
1088{
1089 return enabled ? "on" : "off";
1090}
1091
1092/* Only for pre-ILK configs */
55607e8a
DV		 1093void assert_pll(struct drm_i915_private *dev_priv,
1094 enum pipe pipe, bool state)
b24e7179
JB		 1095{
1096 int reg;
1097 u32 val;
1098 bool cur_state;
1099
1100 reg = DPLL(pipe);
1101 val = I915_READ(reg);
1102 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1103 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1104 "PLL state assertion failure (expected %s, current %s)\n",
1105 state_string(state), state_string(cur_state));
1106}
b24e7179 1107
23538ef1
JN		 1108/* XXX: the dsi pll is shared between MIPI DSI ports */
1109static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1110{
1111 u32 val;
1112 bool cur_state;
1113
1114 mutex_lock(&dev_priv->dpio_lock);
1115 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1116 mutex_unlock(&dev_priv->dpio_lock);
1117
1118 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1119 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1120 "DSI PLL state assertion failure (expected %s, current %s)\n",
1121 state_string(state), state_string(cur_state));
1122}
1123#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1124#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1125
55607e8a 1126struct intel_shared_dpll *
e2b78267
DV		 1127intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1128{
1129 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1130
6e3c9717 1131 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1132 return NULL;
1133
6e3c9717 1134 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1135}
1136
040484af 1137/* For ILK+ */
55607e8a
DV		 1138void assert_shared_dpll(struct drm_i915_private *dev_priv,
1139 struct intel_shared_dpll *pll,
1140 bool state)
040484af 1141{
040484af 1142 bool cur_state;
5358901f 1143 struct intel_dpll_hw_state hw_state;
040484af 1144
92b27b08 1145 if (WARN (!pll,
46edb027 1146 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1147 return;
ee7b9f93 1148
5358901f 1149 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1150 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1151 "%s assertion failure (expected %s, current %s)\n",
1152 pll->name, state_string(state), state_string(cur_state));
040484af 1153}
040484af
JB		 1154
1155static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1156 enum pipe pipe, bool state)
1157{
1158 int reg;
1159 u32 val;
1160 bool cur_state;
ad80a810
PZ		 1161 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1162 pipe);
040484af 1163
affa9354
PZ		 1164 if (HAS_DDI(dev_priv->dev)) {
1165 /* DDI does not have a specific FDI_TX register */
ad80a810 1166 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1167 val = I915_READ(reg);
ad80a810 1168 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1169 } else {
1170 reg = FDI_TX_CTL(pipe);
1171 val = I915_READ(reg);
1172 cur_state = !!(val & FDI_TX_ENABLE);
1173 }
e2c719b7 1174 I915_STATE_WARN(cur_state != state,
040484af
JB		 1175 "FDI TX state assertion failure (expected %s, current %s)\n",
1176 state_string(state), state_string(cur_state));
1177}
1178#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1179#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1180
1181static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1182 enum pipe pipe, bool state)
1183{
1184 int reg;
1185 u32 val;
1186 bool cur_state;
1187
d63fa0dc
PZ		 1188 reg = FDI_RX_CTL(pipe);
1189 val = I915_READ(reg);
1190 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1191 I915_STATE_WARN(cur_state != state,
040484af
JB		 1192 "FDI RX state assertion failure (expected %s, current %s)\n",
1193 state_string(state), state_string(cur_state));
1194}
1195#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1196#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1197
1198static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1199 enum pipe pipe)
1200{
1201 int reg;
1202 u32 val;
1203
1204 /* ILK FDI PLL is always enabled */
3d13ef2e 1205 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1206 return;
1207
bf507ef7 1208 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1209 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1210 return;
1211
040484af
JB		 1212 reg = FDI_TX_CTL(pipe);
1213 val = I915_READ(reg);
e2c719b7 1214 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1215}
1216
55607e8a
DV		 1217void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1218 enum pipe pipe, bool state)
040484af
JB		 1219{
1220 int reg;
1221 u32 val;
55607e8a 1222 bool cur_state;
040484af
JB		 1223
1224 reg = FDI_RX_CTL(pipe);
1225 val = I915_READ(reg);
55607e8a 1226 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1227 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1228 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1229 state_string(state), state_string(cur_state));
040484af
JB		 1230}
1231
b680c37a
DV		 1232void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1233 enum pipe pipe)
ea0760cf 1234{
bedd4dba
JN		 1235 struct drm_device *dev = dev_priv->dev;
1236 int pp_reg;
ea0760cf
JB		 1237 u32 val;
1238 enum pipe panel_pipe = PIPE_A;
0de3b485 1239 bool locked = true;
ea0760cf 1240
bedd4dba
JN		 1241 if (WARN_ON(HAS_DDI(dev)))
1242 return;
1243
1244 if (HAS_PCH_SPLIT(dev)) {
1245 u32 port_sel;
1246
ea0760cf 1247 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1248 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1249
1250 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1251 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1252 panel_pipe = PIPE_B;
1253 /* XXX: else fix for eDP */
1254 } else if (IS_VALLEYVIEW(dev)) {
1255 /* presumably write lock depends on pipe, not port select */
1256 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1257 panel_pipe = pipe;
ea0760cf
JB		 1258 } else {
1259 pp_reg = PP_CONTROL;
bedd4dba
JN		 1260 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1261 panel_pipe = PIPE_B;
ea0760cf
JB		 1262 }
1263
1264 val = I915_READ(pp_reg);
1265 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1266 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1267 locked = false;
1268
e2c719b7 1269 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1270 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1271 pipe_name(pipe));
ea0760cf
JB		 1272}
1273
93ce0ba6
JN		 1274static void assert_cursor(struct drm_i915_private *dev_priv,
1275 enum pipe pipe, bool state)
1276{
1277 struct drm_device *dev = dev_priv->dev;
1278 bool cur_state;
1279
d9d82081 1280 if (IS_845G(dev) || IS_I865G(dev))
93ce0ba6 1281 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
d9d82081 1282 else
5efb3e28 1283 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1284
e2c719b7 1285 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1286 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1287 pipe_name(pipe), state_string(state), state_string(cur_state));
1288}
1289#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1290#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1291
b840d907
JB		 1292void assert_pipe(struct drm_i915_private *dev_priv,
1293 enum pipe pipe, bool state)
b24e7179
JB		 1294{
1295 int reg;
1296 u32 val;
63d7bbe9 1297 bool cur_state;
702e7a56
PZ		 1298 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1299 pipe);
b24e7179 1300
b6b5d049
VS		 1301 /* if we need the pipe quirk it must be always on */
1302 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1303 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1304 state = true;
1305
f458ebbc 1306 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1307 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1308 cur_state = false;
1309 } else {
1310 reg = PIPECONF(cpu_transcoder);
1311 val = I915_READ(reg);
1312 cur_state = !!(val & PIPECONF_ENABLE);
1313 }
1314
e2c719b7 1315 I915_STATE_WARN(cur_state != state,
63d7bbe9 1316 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1317 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1318}
1319
931872fc
CW		 1320static void assert_plane(struct drm_i915_private *dev_priv,
1321 enum plane plane, bool state)
b24e7179
JB		 1322{
1323 int reg;
1324 u32 val;
931872fc 1325 bool cur_state;
b24e7179
JB		 1326
1327 reg = DSPCNTR(plane);
1328 val = I915_READ(reg);
931872fc 1329 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1330 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1331 "plane %c assertion failure (expected %s, current %s)\n",
1332 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1333}
1334
931872fc
CW		 1335#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1336#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1337
b24e7179
JB		 1338static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1339 enum pipe pipe)
1340{
653e1026 1341 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1342 int reg, i;
1343 u32 val;
1344 int cur_pipe;
1345
653e1026
VS		 1346 /* Primary planes are fixed to pipes on gen4+ */
1347 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1348 reg = DSPCNTR(pipe);
1349 val = I915_READ(reg);
e2c719b7 1350 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1351 "plane %c assertion failure, should be disabled but not\n",
1352 plane_name(pipe));
19ec1358 1353 return;
28c05794 1354 }
19ec1358 1355
b24e7179 1356 /* Need to check both planes against the pipe */
055e393f 1357 for_each_pipe(dev_priv, i) {
b24e7179
JB		 1358 reg = DSPCNTR(i);
1359 val = I915_READ(reg);
1360 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1361 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1362 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1363 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1364 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1365 }
1366}
1367
19332d7a
JB		 1368static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1369 enum pipe pipe)
1370{
20674eef 1371 struct drm_device *dev = dev_priv->dev;
1fe47785 1372 int reg, sprite;
19332d7a
JB		 1373 u32 val;
1374
7feb8b88 1375 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1376 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1377 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1378 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1379 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1380 sprite, pipe_name(pipe));
1381 }
1382 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1383 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1384 reg = SPCNTR(pipe, sprite);
20674eef 1385 val = I915_READ(reg);
e2c719b7 1386 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1387 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1388 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1389 }
1390 } else if (INTEL_INFO(dev)->gen >= 7) {
1391 reg = SPRCTL(pipe);
19332d7a 1392 val = I915_READ(reg);
e2c719b7 1393 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1394 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1395 plane_name(pipe), pipe_name(pipe));
1396 } else if (INTEL_INFO(dev)->gen >= 5) {
1397 reg = DVSCNTR(pipe);
19332d7a 1398 val = I915_READ(reg);
e2c719b7 1399 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1400 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1401 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1402 }
1403}
1404
08c71e5e
VS		 1405static void assert_vblank_disabled(struct drm_crtc *crtc)
1406{
e2c719b7 1407 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1408 drm_crtc_vblank_put(crtc);
1409}
1410
89eff4be 1411static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1412{
1413 u32 val;
1414 bool enabled;
1415
e2c719b7 1416 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1417
92f2584a
JB		 1418 val = I915_READ(PCH_DREF_CONTROL);
1419 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1420 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1421 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1422}
1423
ab9412ba
DV		 1424static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1425 enum pipe pipe)
92f2584a
JB		 1426{
1427 int reg;
1428 u32 val;
1429 bool enabled;
1430
ab9412ba 1431 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1432 val = I915_READ(reg);
1433 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1434 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1435 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1436 pipe_name(pipe));
92f2584a
JB		 1437}
1438
4e634389
KP		 1439static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1440 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1441{
1442 if ((val & DP_PORT_EN) == 0)
1443 return false;
1444
1445 if (HAS_PCH_CPT(dev_priv->dev)) {
1446 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1447 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1448 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1449 return false;
44f37d1f
CML		 1450 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1451 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1452 return false;
f0575e92
KP		 1453 } else {
1454 if ((val & DP_PIPE_MASK) != (pipe << 30))
1455 return false;
1456 }
1457 return true;
1458}
1459
1519b995
KP		 1460static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1461 enum pipe pipe, u32 val)
1462{
dc0fa718 1463 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1464 return false;
1465
1466 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1467 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1468 return false;
44f37d1f
CML		 1469 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1470 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1471 return false;
1519b995 1472 } else {
dc0fa718 1473 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1474 return false;
1475 }
1476 return true;
1477}
1478
1479static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1480 enum pipe pipe, u32 val)
1481{
1482 if ((val & LVDS_PORT_EN) == 0)
1483 return false;
1484
1485 if (HAS_PCH_CPT(dev_priv->dev)) {
1486 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1487 return false;
1488 } else {
1489 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1490 return false;
1491 }
1492 return true;
1493}
1494
1495static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1496 enum pipe pipe, u32 val)
1497{
1498 if ((val & ADPA_DAC_ENABLE) == 0)
1499 return false;
1500 if (HAS_PCH_CPT(dev_priv->dev)) {
1501 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1502 return false;
1503 } else {
1504 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1505 return false;
1506 }
1507 return true;
1508}
1509
291906f1 1510static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1511 enum pipe pipe, int reg, u32 port_sel)
291906f1 1512{
47a05eca 1513 u32 val = I915_READ(reg);
e2c719b7 1514 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1515 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1516 reg, pipe_name(pipe));
de9a35ab 1517
e2c719b7 1518 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1519 && (val & DP_PIPEB_SELECT),
de9a35ab 1520 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1521}
1522
1523static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1524 enum pipe pipe, int reg)
1525{
47a05eca 1526 u32 val = I915_READ(reg);
e2c719b7 1527 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1528 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1529 reg, pipe_name(pipe));
de9a35ab 1530
e2c719b7 1531 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1532 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1533 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1534}
1535
1536static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1537 enum pipe pipe)
1538{
1539 int reg;
1540 u32 val;
291906f1 1541
f0575e92
KP		 1542 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1543 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1544 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1545
1546 reg = PCH_ADPA;
1547 val = I915_READ(reg);
e2c719b7 1548 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1549 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1550 pipe_name(pipe));
291906f1
JB		 1551
1552 reg = PCH_LVDS;
1553 val = I915_READ(reg);
e2c719b7 1554 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1555 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1556 pipe_name(pipe));
291906f1 1557
e2debe91
PZ		 1558 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1559 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1560 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1561}
1562
40e9cf64
JB		 1563static void intel_init_dpio(struct drm_device *dev)
1564{
1565 struct drm_i915_private *dev_priv = dev->dev_private;
1566
1567 if (!IS_VALLEYVIEW(dev))
1568 return;
1569
a09caddd
CML		 1570 /*
1571 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1572 * CHV x1 PHY (DP/HDMI D)
1573 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1574 */
1575 if (IS_CHERRYVIEW(dev)) {
1576 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1577 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1578 } else {
1579 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1580 }
5382f5f3
JB		 1581}
1582
d288f65f 1583static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1584 const struct intel_crtc_state *pipe_config)
87442f73 1585{
426115cf
DV		 1586 struct drm_device *dev = crtc->base.dev;
1587 struct drm_i915_private *dev_priv = dev->dev_private;
1588 int reg = DPLL(crtc->pipe);
d288f65f 1589 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1590
426115cf 1591 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1592
1593 /* No really, not for ILK+ */
1594 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1595
1596 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1597 if (IS_MOBILE(dev_priv->dev))
426115cf 1598 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1599
426115cf
DV		 1600 I915_WRITE(reg, dpll);
1601 POSTING_READ(reg);
1602 udelay(150);
1603
1604 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1605 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1606
d288f65f 1607 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1608 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1609
1610 /* We do this three times for luck */
426115cf 1611 I915_WRITE(reg, dpll);
87442f73
DV		 1612 POSTING_READ(reg);
1613 udelay(150); /* wait for warmup */
426115cf 1614 I915_WRITE(reg, dpll);
87442f73
DV		 1615 POSTING_READ(reg);
1616 udelay(150); /* wait for warmup */
426115cf 1617 I915_WRITE(reg, dpll);
87442f73
DV		 1618 POSTING_READ(reg);
1619 udelay(150); /* wait for warmup */
1620}
1621
d288f65f 1622static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1623 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1624{
1625 struct drm_device *dev = crtc->base.dev;
1626 struct drm_i915_private *dev_priv = dev->dev_private;
1627 int pipe = crtc->pipe;
1628 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1629 u32 tmp;
1630
1631 assert_pipe_disabled(dev_priv, crtc->pipe);
1632
1633 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1634
1635 mutex_lock(&dev_priv->dpio_lock);
1636
1637 /* Enable back the 10bit clock to display controller */
1638 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1639 tmp |= DPIO_DCLKP_EN;
1640 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1641
1642 /*
1643 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1644 */
1645 udelay(1);
1646
1647 /* Enable PLL */
d288f65f 1648 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1649
1650 /* Check PLL is locked */
a11b0703 1651 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1652 DRM_ERROR("PLL %d failed to lock\n", pipe);
1653
a11b0703 1654 /* not sure when this should be written */
d288f65f 1655 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703
VS		 1656 POSTING_READ(DPLL_MD(pipe));
1657
9d556c99
CML		 1658 mutex_unlock(&dev_priv->dpio_lock);
1659}
1660
1c4e0274
VS		 1661static int intel_num_dvo_pipes(struct drm_device *dev)
1662{
1663 struct intel_crtc *crtc;
1664 int count = 0;
1665
1666 for_each_intel_crtc(dev, crtc)
1667 count += crtc->active &&
409ee761 1668 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1669
1670 return count;
1671}
1672
66e3d5c0 1673static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1674{
66e3d5c0
DV		 1675 struct drm_device *dev = crtc->base.dev;
1676 struct drm_i915_private *dev_priv = dev->dev_private;
1677 int reg = DPLL(crtc->pipe);
6e3c9717 1678 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1679
66e3d5c0 1680 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1681
63d7bbe9 1682 /* No really, not for ILK+ */
3d13ef2e 1683 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1684
1685 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1686 if (IS_MOBILE(dev) && !IS_I830(dev))
1687 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1688
1c4e0274
VS		 1689 /* Enable DVO 2x clock on both PLLs if necessary */
1690 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1691 /*
1692 * It appears to be important that we don't enable this
1693 * for the current pipe before otherwise configuring the
1694 * PLL. No idea how this should be handled if multiple
1695 * DVO outputs are enabled simultaneosly.
1696 */
1697 dpll |= DPLL_DVO_2X_MODE;
1698 I915_WRITE(DPLL(!crtc->pipe),
1699 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1700 }
66e3d5c0
DV		 1701
1702 /* Wait for the clocks to stabilize. */
1703 POSTING_READ(reg);
1704 udelay(150);
1705
1706 if (INTEL_INFO(dev)->gen >= 4) {
1707 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1708 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1709 } else {
1710 /* The pixel multiplier can only be updated once the
1711 * DPLL is enabled and the clocks are stable.
1712 *
1713 * So write it again.
1714 */
1715 I915_WRITE(reg, dpll);
1716 }
63d7bbe9
JB		 1717
1718 /* We do this three times for luck */
66e3d5c0 1719 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1720 POSTING_READ(reg);
1721 udelay(150); /* wait for warmup */
66e3d5c0 1722 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1723 POSTING_READ(reg);
1724 udelay(150); /* wait for warmup */
66e3d5c0 1725 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1726 POSTING_READ(reg);
1727 udelay(150); /* wait for warmup */
1728}
1729
1730/**
50b44a44 1731 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1732 * @dev_priv: i915 private structure
1733 * @pipe: pipe PLL to disable
1734 *
1735 * Disable the PLL for @pipe, making sure the pipe is off first.
1736 *
1737 * Note! This is for pre-ILK only.
1738 */
1c4e0274 1739static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1740{
1c4e0274
VS		 1741 struct drm_device *dev = crtc->base.dev;
1742 struct drm_i915_private *dev_priv = dev->dev_private;
1743 enum pipe pipe = crtc->pipe;
1744
1745 /* Disable DVO 2x clock on both PLLs if necessary */
1746 if (IS_I830(dev) &&
409ee761 1747 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1c4e0274
VS		 1748 intel_num_dvo_pipes(dev) == 1) {
1749 I915_WRITE(DPLL(PIPE_B),
1750 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1751 I915_WRITE(DPLL(PIPE_A),
1752 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1753 }
1754
b6b5d049
VS		 1755 /* Don't disable pipe or pipe PLLs if needed */
1756 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1757 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1758 return;
1759
1760 /* Make sure the pipe isn't still relying on us */
1761 assert_pipe_disabled(dev_priv, pipe);
1762
50b44a44
DV		 1763 I915_WRITE(DPLL(pipe), 0);
1764 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1765}
1766
f6071166
JB		 1767static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1768{
1769 u32 val = 0;
1770
1771 /* Make sure the pipe isn't still relying on us */
1772 assert_pipe_disabled(dev_priv, pipe);
1773
e5cbfbfb
ID		 1774 /*
1775 * Leave integrated clock source and reference clock enabled for pipe B.
1776 * The latter is needed for VGA hotplug / manual detection.
1777 */
f6071166 1778 if (pipe == PIPE_B)
e5cbfbfb 1779 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
f6071166
JB		 1780 I915_WRITE(DPLL(pipe), val);
1781 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1782
1783}
1784
1785static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1786{
d752048d 1787 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1788 u32 val;
1789
a11b0703
VS		 1790 /* Make sure the pipe isn't still relying on us */
1791 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1792
a11b0703 1793 /* Set PLL en = 0 */
d17ec4ce 1794 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
a11b0703
VS		 1795 if (pipe != PIPE_A)
1796 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1797 I915_WRITE(DPLL(pipe), val);
1798 POSTING_READ(DPLL(pipe));
d752048d
VS		 1799
1800 mutex_lock(&dev_priv->dpio_lock);
1801
1802 /* Disable 10bit clock to display controller */
1803 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1804 val &= ~DPIO_DCLKP_EN;
1805 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1806
61407f6d
VS		 1807 /* disable left/right clock distribution */
1808 if (pipe != PIPE_B) {
1809 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1810 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1811 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1812 } else {
1813 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1814 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1815 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1816 }
1817
d752048d 1818 mutex_unlock(&dev_priv->dpio_lock);
f6071166
JB		 1819}
1820
e4607fcf
CML		 1821void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1822 struct intel_digital_port *dport)
89b667f8
JB		 1823{
1824 u32 port_mask;
00fc31b7 1825 int dpll_reg;
89b667f8 1826
e4607fcf
CML		 1827 switch (dport->port) {
1828 case PORT_B:
89b667f8 1829 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1830 dpll_reg = DPLL(0);
e4607fcf
CML		 1831 break;
1832 case PORT_C:
89b667f8 1833 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7
CML		 1834 dpll_reg = DPLL(0);
1835 break;
1836 case PORT_D:
1837 port_mask = DPLL_PORTD_READY_MASK;
1838 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1839 break;
1840 default:
1841 BUG();
1842 }
89b667f8 1843
00fc31b7 1844 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
89b667f8 1845 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
00fc31b7 1846 port_name(dport->port), I915_READ(dpll_reg));
89b667f8
JB		 1847}
1848
b14b1055
DV		 1849static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1850{
1851 struct drm_device *dev = crtc->base.dev;
1852 struct drm_i915_private *dev_priv = dev->dev_private;
1853 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1854
be19f0ff
CW		 1855 if (WARN_ON(pll == NULL))
1856 return;
1857
3e369b76 1858 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1859 if (pll->active == 0) {
1860 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1861 WARN_ON(pll->on);
1862 assert_shared_dpll_disabled(dev_priv, pll);
1863
1864 pll->mode_set(dev_priv, pll);
1865 }
1866}
1867
92f2584a 1868/**
85b3894f 1869 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1870 * @dev_priv: i915 private structure
1871 * @pipe: pipe PLL to enable
1872 *
1873 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1874 * drives the transcoder clock.
1875 */
85b3894f 1876static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1877{
3d13ef2e
DL		 1878 struct drm_device *dev = crtc->base.dev;
1879 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1880 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1881
87a875bb 1882 if (WARN_ON(pll == NULL))
48da64a8
CW		 1883 return;
1884
3e369b76 1885 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1886 return;
ee7b9f93 1887
74dd6928 1888 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1889 pll->name, pll->active, pll->on,
e2b78267 1890 crtc->base.base.id);
92f2584a 1891
cdbd2316
DV		 1892 if (pll->active++) {
1893 WARN_ON(!pll->on);
e9d6944e 1894 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1895 return;
1896 }
f4a091c7 1897 WARN_ON(pll->on);
ee7b9f93 1898
bd2bb1b9
PZ		 1899 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1900
46edb027 1901 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1902 pll->enable(dev_priv, pll);
ee7b9f93 1903 pll->on = true;
92f2584a
JB		 1904}
1905
f6daaec2 1906static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1907{
3d13ef2e
DL		 1908 struct drm_device *dev = crtc->base.dev;
1909 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1910 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1911
92f2584a 1912 /* PCH only available on ILK+ */
3d13ef2e 1913 BUG_ON(INTEL_INFO(dev)->gen < 5);
87a875bb 1914 if (WARN_ON(pll == NULL))
ee7b9f93 1915 return;
92f2584a 1916
3e369b76 1917 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1918 return;
7a419866 1919
46edb027
DV		 1920 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1921 pll->name, pll->active, pll->on,
e2b78267 1922 crtc->base.base.id);
7a419866 1923
48da64a8 1924 if (WARN_ON(pll->active == 0)) {
e9d6944e 1925 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1926 return;
1927 }
1928
e9d6944e 1929 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1930 WARN_ON(!pll->on);
cdbd2316 1931 if (--pll->active)
7a419866 1932 return;
ee7b9f93 1933
46edb027 1934 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1935 pll->disable(dev_priv, pll);
ee7b9f93 1936 pll->on = false;
bd2bb1b9
PZ		 1937
1938 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1939}
1940
b8a4f404
PZ		 1941static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1942 enum pipe pipe)
040484af 1943{
23670b32 1944 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1945 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1946 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1947 uint32_t reg, val, pipeconf_val;
040484af
JB		 1948
1949 /* PCH only available on ILK+ */
55522f37 1950 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1951
1952 /* Make sure PCH DPLL is enabled */
e72f9fbf 1953 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1954 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1955
1956 /* FDI must be feeding us bits for PCH ports */
1957 assert_fdi_tx_enabled(dev_priv, pipe);
1958 assert_fdi_rx_enabled(dev_priv, pipe);
1959
23670b32
DV		 1960 if (HAS_PCH_CPT(dev)) {
1961 /* Workaround: Set the timing override bit before enabling the
1962 * pch transcoder. */
1963 reg = TRANS_CHICKEN2(pipe);
1964 val = I915_READ(reg);
1965 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1966 I915_WRITE(reg, val);
59c859d6 1967 }
23670b32 1968
ab9412ba 1969 reg = PCH_TRANSCONF(pipe);
040484af 1970 val = I915_READ(reg);
5f7f726d 1971 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1972
1973 if (HAS_PCH_IBX(dev_priv->dev)) {
1974 /*
1975 * make the BPC in transcoder be consistent with
1976 * that in pipeconf reg.
1977 */
dfd07d72
DV		 1978 val &= ~PIPECONF_BPC_MASK;
1979 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1980 }
5f7f726d
PZ		 1981
1982 val &= ~TRANS_INTERLACE_MASK;
1983 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 1984 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 1985 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 1986 val |= TRANS_LEGACY_INTERLACED_ILK;
1987 else
1988 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1989 else
1990 val |= TRANS_PROGRESSIVE;
1991
040484af
JB		 1992 I915_WRITE(reg, val | TRANS_ENABLE);
1993 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1994 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1995}
1996
8fb033d7 1997static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1998 enum transcoder cpu_transcoder)
040484af 1999{
8fb033d7 2000 u32 val, pipeconf_val;
8fb033d7
PZ		 2001
2002 /* PCH only available on ILK+ */
55522f37 2003 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 2004
8fb033d7 2005 /* FDI must be feeding us bits for PCH ports */
1a240d4d 2006 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2007 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2008
223a6fdf
PZ		 2009 /* Workaround: set timing override bit. */
2010 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2011 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 2012 I915_WRITE(_TRANSA_CHICKEN2, val);
2013
25f3ef11 2014 val = TRANS_ENABLE;
937bb610 2015 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2016
9a76b1c6
PZ		 2017 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2018 PIPECONF_INTERLACED_ILK)
a35f2679 2019 val |= TRANS_INTERLACED;
8fb033d7
PZ		 2020 else
2021 val |= TRANS_PROGRESSIVE;
2022
ab9412ba
DV		 2023 I915_WRITE(LPT_TRANSCONF, val);
2024 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2025 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 2026}
2027
b8a4f404
PZ		 2028static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2029 enum pipe pipe)
040484af 2030{
23670b32
DV		 2031 struct drm_device *dev = dev_priv->dev;
2032 uint32_t reg, val;
040484af
JB		 2033
2034 /* FDI relies on the transcoder */
2035 assert_fdi_tx_disabled(dev_priv, pipe);
2036 assert_fdi_rx_disabled(dev_priv, pipe);
2037
291906f1
JB		 2038 /* Ports must be off as well */
2039 assert_pch_ports_disabled(dev_priv, pipe);
2040
ab9412ba 2041 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2042 val = I915_READ(reg);
2043 val &= ~TRANS_ENABLE;
2044 I915_WRITE(reg, val);
2045 /* wait for PCH transcoder off, transcoder state */
2046 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2047 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2048
2049 if (!HAS_PCH_IBX(dev)) {
2050 /* Workaround: Clear the timing override chicken bit again. */
2051 reg = TRANS_CHICKEN2(pipe);
2052 val = I915_READ(reg);
2053 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2054 I915_WRITE(reg, val);
2055 }
040484af
JB		 2056}
2057
ab4d966c 2058static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2059{
8fb033d7
PZ		 2060 u32 val;
2061
ab9412ba 2062 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2063 val &= ~TRANS_ENABLE;
ab9412ba 2064 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2065 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2066 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2067 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2068
2069 /* Workaround: clear timing override bit. */
2070 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2071 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 2072 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 2073}
2074
b24e7179 2075/**
309cfea8 2076 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2077 * @crtc: crtc responsible for the pipe
b24e7179 2078 *
0372264a 2079 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2080 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2081 */
e1fdc473 2082static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2083{
0372264a
PZ		 2084 struct drm_device *dev = crtc->base.dev;
2085 struct drm_i915_private *dev_priv = dev->dev_private;
2086 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2087 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2088 pipe);
1a240d4d 2089 enum pipe pch_transcoder;
b24e7179
JB		 2090 int reg;
2091 u32 val;
2092
58c6eaa2 2093 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2094 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2095 assert_sprites_disabled(dev_priv, pipe);
2096
681e5811 2097 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2098 pch_transcoder = TRANSCODER_A;
2099 else
2100 pch_transcoder = pipe;
2101
b24e7179
JB		 2102 /*
2103 * A pipe without a PLL won't actually be able to drive bits from
2104 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2105 * need the check.
2106 */
2107 if (!HAS_PCH_SPLIT(dev_priv->dev))
409ee761 2108 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2109 assert_dsi_pll_enabled(dev_priv);
2110 else
2111 assert_pll_enabled(dev_priv, pipe);
040484af 2112 else {
6e3c9717 2113 if (crtc->config->has_pch_encoder) {
040484af 2114 /* if driving the PCH, we need FDI enabled */
cc391bbb 2115 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2116 assert_fdi_tx_pll_enabled(dev_priv,
2117 (enum pipe) cpu_transcoder);
040484af
JB		 2118 }
2119 /* FIXME: assert CPU port conditions for SNB+ */
2120 }
b24e7179 2121
702e7a56 2122 reg = PIPECONF(cpu_transcoder);
b24e7179 2123 val = I915_READ(reg);
7ad25d48 2124 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2125 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2126 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2127 return;
7ad25d48 2128 }
00d70b15
CW		 2129
2130 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2131 POSTING_READ(reg);
b24e7179
JB		 2132}
2133
2134/**
309cfea8 2135 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2136 * @crtc: crtc whose pipes is to be disabled
b24e7179 2137 *
575f7ab7
VS		 2138 * Disable the pipe of @crtc, making sure that various hardware
2139 * specific requirements are met, if applicable, e.g. plane
2140 * disabled, panel fitter off, etc.
b24e7179
JB		 2141 *
2142 * Will wait until the pipe has shut down before returning.
2143 */
575f7ab7 2144static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2145{
575f7ab7 2146 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2147 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2148 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2149 int reg;
2150 u32 val;
2151
2152 /*
2153 * Make sure planes won't keep trying to pump pixels to us,
2154 * or we might hang the display.
2155 */
2156 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2157 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2158 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2159
702e7a56 2160 reg = PIPECONF(cpu_transcoder);
b24e7179 2161 val = I915_READ(reg);
00d70b15
CW		 2162 if ((val & PIPECONF_ENABLE) == 0)
2163 return;
2164
67adc644
VS		 2165 /*
2166 * Double wide has implications for planes
2167 * so best keep it disabled when not needed.
2168 */
6e3c9717 2169 if (crtc->config->double_wide)
67adc644
VS		 2170 val &= ~PIPECONF_DOUBLE_WIDE;
2171
2172 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2173 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2174 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2175 val &= ~PIPECONF_ENABLE;
2176
2177 I915_WRITE(reg, val);
2178 if ((val & PIPECONF_ENABLE) == 0)
2179 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2180}
2181
d74362c9
KP		 2182/*
2183 * Plane regs are double buffered, going from enabled->disabled needs a
2184 * trigger in order to latch. The display address reg provides this.
2185 */
1dba99f4
VS		 2186void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2187 enum plane plane)
d74362c9 2188{
3d13ef2e
DL		 2189 struct drm_device *dev = dev_priv->dev;
2190 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1dba99f4
VS		 2191
2192 I915_WRITE(reg, I915_READ(reg));
2193 POSTING_READ(reg);
d74362c9
KP		 2194}
2195
b24e7179 2196/**
262ca2b0 2197 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
fdd508a6
VS		 2198 * @plane: plane to be enabled
2199 * @crtc: crtc for the plane
b24e7179 2200 *
fdd508a6 2201 * Enable @plane on @crtc, making sure that the pipe is running first.
b24e7179 2202 */
fdd508a6
VS		 2203static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2204 struct drm_crtc *crtc)
b24e7179 2205{
fdd508a6
VS		 2206 struct drm_device *dev = plane->dev;
2207 struct drm_i915_private *dev_priv = dev->dev_private;
2208 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b24e7179
JB		 2209
2210 /* If the pipe isn't enabled, we can't pump pixels and may hang */
fdd508a6 2211 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
b24e7179 2212
98ec7739
VS		 2213 if (intel_crtc->primary_enabled)
2214 return;
0037f71c 2215
4c445e0e 2216 intel_crtc->primary_enabled = true;
939c2fe8 2217
fdd508a6
VS		 2218 dev_priv->display.update_primary_plane(crtc, plane->fb,
2219 crtc->x, crtc->y);
33c3b0d1
VS		 2220
2221 /*
2222 * BDW signals flip done immediately if the plane
2223 * is disabled, even if the plane enable is already
2224 * armed to occur at the next vblank :(
2225 */
2226 if (IS_BROADWELL(dev))
2227 intel_wait_for_vblank(dev, intel_crtc->pipe);
b24e7179
JB		 2228}
2229
b24e7179 2230/**
262ca2b0 2231 * intel_disable_primary_hw_plane - disable the primary hardware plane
fdd508a6
VS		 2232 * @plane: plane to be disabled
2233 * @crtc: crtc for the plane
b24e7179 2234 *
fdd508a6 2235 * Disable @plane on @crtc, making sure that the pipe is running first.
b24e7179 2236 */
fdd508a6
VS		 2237static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2238 struct drm_crtc *crtc)
b24e7179 2239{
fdd508a6
VS		 2240 struct drm_device *dev = plane->dev;
2241 struct drm_i915_private *dev_priv = dev->dev_private;
2242 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2243
32b7eeec
MR		 2244 if (WARN_ON(!intel_crtc->active))
2245 return;
b24e7179 2246
98ec7739
VS		 2247 if (!intel_crtc->primary_enabled)
2248 return;
0037f71c 2249
4c445e0e 2250 intel_crtc->primary_enabled = false;
939c2fe8 2251
fdd508a6
VS		 2252 dev_priv->display.update_primary_plane(crtc, plane->fb,
2253 crtc->x, crtc->y);
b24e7179
JB		 2254}
2255
693db184
CW		 2256static bool need_vtd_wa(struct drm_device *dev)
2257{
2258#ifdef CONFIG_INTEL_IOMMU
2259 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2260 return true;
2261#endif
2262 return false;
2263}
2264
50470bb0 2265unsigned int
6761dd31
TU		 2266intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2267 uint64_t fb_format_modifier)
a57ce0b2 2268{
6761dd31
TU		 2269 unsigned int tile_height;
2270 uint32_t pixel_bytes;
a57ce0b2 2271
b5d0e9bf
DL		 2272 switch (fb_format_modifier) {
2273 case DRM_FORMAT_MOD_NONE:
2274 tile_height = 1;
2275 break;
2276 case I915_FORMAT_MOD_X_TILED:
2277 tile_height = IS_GEN2(dev) ? 16 : 8;
2278 break;
2279 case I915_FORMAT_MOD_Y_TILED:
2280 tile_height = 32;
2281 break;
2282 case I915_FORMAT_MOD_Yf_TILED:
6761dd31
TU		 2283 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2284 switch (pixel_bytes) {
b5d0e9bf 2285 default:
6761dd31 2286 case 1:
b5d0e9bf
DL		 2287 tile_height = 64;
2288 break;
6761dd31
TU		 2289 case 2:
2290 case 4:
b5d0e9bf
DL		 2291 tile_height = 32;
2292 break;
6761dd31 2293 case 8:
b5d0e9bf
DL		 2294 tile_height = 16;
2295 break;
6761dd31 2296 case 16:
b5d0e9bf
DL		 2297 WARN_ONCE(1,
2298 "128-bit pixels are not supported for display!");
2299 tile_height = 16;
2300 break;
2301 }
2302 break;
2303 default:
2304 MISSING_CASE(fb_format_modifier);
2305 tile_height = 1;
2306 break;
2307 }
091df6cb 2308
6761dd31
TU		 2309 return tile_height;
2310}
2311
2312unsigned int
2313intel_fb_align_height(struct drm_device *dev, unsigned int height,
2314 uint32_t pixel_format, uint64_t fb_format_modifier)
2315{
2316 return ALIGN(height, intel_tile_height(dev, pixel_format,
2317 fb_format_modifier));
a57ce0b2
JB		 2318}
2319
f64b98cd
TU		 2320static int
2321intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2322 const struct drm_plane_state *plane_state)
2323{
50470bb0
TU		 2324 struct intel_rotation_info *info = &view->rotation_info;
2325 static const struct i915_ggtt_view rotated_view =
2326 { .type = I915_GGTT_VIEW_ROTATED };
2327
f64b98cd
TU		 2328 *view = i915_ggtt_view_normal;
2329
50470bb0
TU		 2330 if (!plane_state)
2331 return 0;
2332
121920fa 2333 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2334 return 0;
2335
2336 *view = rotated_view;
2337
2338 info->height = fb->height;
2339 info->pixel_format = fb->pixel_format;
2340 info->pitch = fb->pitches[0];
2341 info->fb_modifier = fb->modifier[0];
2342
2343 if (!(info->fb_modifier == I915_FORMAT_MOD_Y_TILED ||
2344 info->fb_modifier == I915_FORMAT_MOD_Yf_TILED)) {
2345 DRM_DEBUG_KMS(
2346 "Y or Yf tiling is needed for 90/270 rotation!\n");
2347 return -EINVAL;
2348 }
2349
f64b98cd
TU		 2350 return 0;
2351}
2352
127bd2ac 2353int
850c4cdc
TU		 2354intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2355 struct drm_framebuffer *fb,
82bc3b2d 2356 const struct drm_plane_state *plane_state,
a4872ba6 2357 struct intel_engine_cs *pipelined)
6b95a207 2358{
850c4cdc 2359 struct drm_device *dev = fb->dev;
ce453d81 2360 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2361 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2362 struct i915_ggtt_view view;
6b95a207
KH		 2363 u32 alignment;
2364 int ret;
2365
ebcdd39e
MR		 2366 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2367
7b911adc
TU		 2368 switch (fb->modifier[0]) {
2369 case DRM_FORMAT_MOD_NONE:
1fada4cc
DL		 2370 if (INTEL_INFO(dev)->gen >= 9)
2371 alignment = 256 * 1024;
2372 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
534843da 2373 alignment = 128 * 1024;
a6c45cf0 2374 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 2375 alignment = 4 * 1024;
2376 else
2377 alignment = 64 * 1024;
6b95a207 2378 break;
7b911adc 2379 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2380 if (INTEL_INFO(dev)->gen >= 9)
2381 alignment = 256 * 1024;
2382 else {
2383 /* pin() will align the object as required by fence */
2384 alignment = 0;
2385 }
6b95a207 2386 break;
7b911adc 2387 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2388 case I915_FORMAT_MOD_Yf_TILED:
2389 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2390 "Y tiling bo slipped through, driver bug!\n"))
2391 return -EINVAL;
2392 alignment = 1 * 1024 * 1024;
2393 break;
6b95a207 2394 default:
7b911adc
TU		 2395 MISSING_CASE(fb->modifier[0]);
2396 return -EINVAL;
6b95a207
KH		 2397 }
2398
f64b98cd
TU		 2399 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2400 if (ret)
2401 return ret;
2402
693db184
CW		 2403 /* Note that the w/a also requires 64 PTE of padding following the
2404 * bo. We currently fill all unused PTE with the shadow page and so
2405 * we should always have valid PTE following the scanout preventing
2406 * the VT-d warning.
2407 */
2408 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2409 alignment = 256 * 1024;
2410
d6dd6843
PZ		 2411 /*
2412 * Global gtt pte registers are special registers which actually forward
2413 * writes to a chunk of system memory. Which means that there is no risk
2414 * that the register values disappear as soon as we call
2415 * intel_runtime_pm_put(), so it is correct to wrap only the
2416 * pin/unpin/fence and not more.
2417 */
2418 intel_runtime_pm_get(dev_priv);
2419
ce453d81 2420 dev_priv->mm.interruptible = false;
e6617330 2421 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
f64b98cd 2422 &view);
48b956c5 2423 if (ret)
ce453d81 2424 goto err_interruptible;
6b95a207
KH		 2425
2426 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2427 * fence, whereas 965+ only requires a fence if using
2428 * framebuffer compression. For simplicity, we always install
2429 * a fence as the cost is not that onerous.
2430 */
06d98131 2431 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2432 if (ret)
2433 goto err_unpin;
1690e1eb 2434
9a5a53b3 2435 i915_gem_object_pin_fence(obj);
6b95a207 2436
ce453d81 2437 dev_priv->mm.interruptible = true;
d6dd6843 2438 intel_runtime_pm_put(dev_priv);
6b95a207 2439 return 0;
48b956c5
CW		 2440
2441err_unpin:
f64b98cd 2442 i915_gem_object_unpin_from_display_plane(obj, &view);
ce453d81
CW		 2443err_interruptible:
2444 dev_priv->mm.interruptible = true;
d6dd6843 2445 intel_runtime_pm_put(dev_priv);
48b956c5 2446 return ret;
6b95a207
KH		 2447}
2448
82bc3b2d
TU		 2449static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2450 const struct drm_plane_state *plane_state)
1690e1eb 2451{
82bc3b2d 2452 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2453 struct i915_ggtt_view view;
2454 int ret;
82bc3b2d 2455
ebcdd39e
MR		 2456 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2457
f64b98cd
TU		 2458 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2459 WARN_ONCE(ret, "Couldn't get view from plane state!");
2460
1690e1eb 2461 i915_gem_object_unpin_fence(obj);
f64b98cd 2462 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2463}
2464
c2c75131
DV		 2465/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2466 * is assumed to be a power-of-two. */
bc752862
CW		 2467unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2468 unsigned int tiling_mode,
2469 unsigned int cpp,
2470 unsigned int pitch)
c2c75131 2471{
bc752862
CW		 2472 if (tiling_mode != I915_TILING_NONE) {
2473 unsigned int tile_rows, tiles;
c2c75131 2474
bc752862
CW		 2475 tile_rows = *y / 8;
2476 *y %= 8;
c2c75131 2477
bc752862
CW		 2478 tiles = *x / (512/cpp);
2479 *x %= 512/cpp;
2480
2481 return tile_rows * pitch * 8 + tiles * 4096;
2482 } else {
2483 unsigned int offset;
2484
2485 offset = *y * pitch + *x * cpp;
2486 *y = 0;
2487 *x = (offset & 4095) / cpp;
2488 return offset & -4096;
2489 }
c2c75131
DV		 2490}
2491
b35d63fa 2492static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2493{
2494 switch (format) {
2495 case DISPPLANE_8BPP:
2496 return DRM_FORMAT_C8;
2497 case DISPPLANE_BGRX555:
2498 return DRM_FORMAT_XRGB1555;
2499 case DISPPLANE_BGRX565:
2500 return DRM_FORMAT_RGB565;
2501 default:
2502 case DISPPLANE_BGRX888:
2503 return DRM_FORMAT_XRGB8888;
2504 case DISPPLANE_RGBX888:
2505 return DRM_FORMAT_XBGR8888;
2506 case DISPPLANE_BGRX101010:
2507 return DRM_FORMAT_XRGB2101010;
2508 case DISPPLANE_RGBX101010:
2509 return DRM_FORMAT_XBGR2101010;
2510 }
2511}
2512
bc8d7dff
DL		 2513static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2514{
2515 switch (format) {
2516 case PLANE_CTL_FORMAT_RGB_565:
2517 return DRM_FORMAT_RGB565;
2518 default:
2519 case PLANE_CTL_FORMAT_XRGB_8888:
2520 if (rgb_order) {
2521 if (alpha)
2522 return DRM_FORMAT_ABGR8888;
2523 else
2524 return DRM_FORMAT_XBGR8888;
2525 } else {
2526 if (alpha)
2527 return DRM_FORMAT_ARGB8888;
2528 else
2529 return DRM_FORMAT_XRGB8888;
2530 }
2531 case PLANE_CTL_FORMAT_XRGB_2101010:
2532 if (rgb_order)
2533 return DRM_FORMAT_XBGR2101010;
2534 else
2535 return DRM_FORMAT_XRGB2101010;
2536 }
2537}
2538
5724dbd1 2539static bool
f6936e29
DV		 2540intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2541 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2542{
2543 struct drm_device *dev = crtc->base.dev;
2544 struct drm_i915_gem_object *obj = NULL;
2545 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2546 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2547 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2548 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2549 PAGE_SIZE);
2550
2551 size_aligned -= base_aligned;
46f297fb 2552
ff2652ea
CW		 2553 if (plane_config->size == 0)
2554 return false;
2555
f37b5c2b
DV		 2556 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2557 base_aligned,
2558 base_aligned,
2559 size_aligned);
46f297fb 2560 if (!obj)
484b41dd 2561 return false;
46f297fb 2562
49af449b
DL		 2563 obj->tiling_mode = plane_config->tiling;
2564 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2565 obj->stride = fb->pitches[0];
46f297fb 2566
6bf129df
DL		 2567 mode_cmd.pixel_format = fb->pixel_format;
2568 mode_cmd.width = fb->width;
2569 mode_cmd.height = fb->height;
2570 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2571 mode_cmd.modifier[0] = fb->modifier[0];
2572 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2573
2574 mutex_lock(&dev->struct_mutex);
6bf129df 2575 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2576 &mode_cmd, obj)) {
46f297fb
JB		 2577 DRM_DEBUG_KMS("intel fb init failed\n");
2578 goto out_unref_obj;
2579 }
46f297fb 2580 mutex_unlock(&dev->struct_mutex);
484b41dd 2581
f6936e29 2582 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2583 return true;
46f297fb
JB		 2584
2585out_unref_obj:
2586 drm_gem_object_unreference(&obj->base);
2587 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2588 return false;
2589}
2590
afd65eb4
MR		 2591/* Update plane->state->fb to match plane->fb after driver-internal updates */
2592static void
2593update_state_fb(struct drm_plane *plane)
2594{
2595 if (plane->fb == plane->state->fb)
2596 return;
2597
2598 if (plane->state->fb)
2599 drm_framebuffer_unreference(plane->state->fb);
2600 plane->state->fb = plane->fb;
2601 if (plane->state->fb)
2602 drm_framebuffer_reference(plane->state->fb);
2603}
2604
5724dbd1 2605static void
f6936e29
DV		 2606intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2607 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2608{
2609 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2610 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2611 struct drm_crtc *c;
2612 struct intel_crtc *i;
2ff8fde1 2613 struct drm_i915_gem_object *obj;
88595ac9
DV		 2614 struct drm_plane *primary = intel_crtc->base.primary;
2615 struct drm_framebuffer *fb;
484b41dd 2616
2d14030b 2617 if (!plane_config->fb)
484b41dd
JB		 2618 return;
2619
f6936e29 2620 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2621 fb = &plane_config->fb->base;
2622 goto valid_fb;
f55548b5 2623 }
484b41dd 2624
2d14030b 2625 kfree(plane_config->fb);
484b41dd
JB		 2626
2627 /*
2628 * Failed to alloc the obj, check to see if we should share
2629 * an fb with another CRTC instead
2630 */
70e1e0ec 2631 for_each_crtc(dev, c) {
484b41dd
JB		 2632 i = to_intel_crtc(c);
2633
2634 if (c == &intel_crtc->base)
2635 continue;
2636
2ff8fde1
MR		 2637 if (!i->active)
2638 continue;
2639
88595ac9
DV		 2640 fb = c->primary->fb;
2641 if (!fb)
484b41dd
JB		 2642 continue;
2643
88595ac9 2644 obj = intel_fb_obj(fb);
2ff8fde1 2645 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2646 drm_framebuffer_reference(fb);
2647 goto valid_fb;
484b41dd
JB		 2648 }
2649 }
88595ac9
DV		 2650
2651 return;
2652
2653valid_fb:
2654 obj = intel_fb_obj(fb);
2655 if (obj->tiling_mode != I915_TILING_NONE)
2656 dev_priv->preserve_bios_swizzle = true;
2657
2658 primary->fb = fb;
2659 primary->state->crtc = &intel_crtc->base;
2660 primary->crtc = &intel_crtc->base;
2661 update_state_fb(primary);
2662 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
46f297fb
JB		 2663}
2664
29b9bde6
DV		 2665static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2666 struct drm_framebuffer *fb,
2667 int x, int y)
81255565
JB		 2668{
2669 struct drm_device *dev = crtc->dev;
2670 struct drm_i915_private *dev_priv = dev->dev_private;
2671 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
c9ba6fad 2672 struct drm_i915_gem_object *obj;
81255565 2673 int plane = intel_crtc->plane;
e506a0c6 2674 unsigned long linear_offset;
81255565 2675 u32 dspcntr;
f45651ba 2676 u32 reg = DSPCNTR(plane);
48404c1e 2677 int pixel_size;
f45651ba 2678
fdd508a6
VS		 2679 if (!intel_crtc->primary_enabled) {
2680 I915_WRITE(reg, 0);
2681 if (INTEL_INFO(dev)->gen >= 4)
2682 I915_WRITE(DSPSURF(plane), 0);
2683 else
2684 I915_WRITE(DSPADDR(plane), 0);
2685 POSTING_READ(reg);
2686 return;
2687 }
2688
c9ba6fad
VS		 2689 obj = intel_fb_obj(fb);
2690 if (WARN_ON(obj == NULL))
2691 return;
2692
2693 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2694
f45651ba
VS		 2695 dspcntr = DISPPLANE_GAMMA_ENABLE;
2696
fdd508a6 2697 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2698
2699 if (INTEL_INFO(dev)->gen < 4) {
2700 if (intel_crtc->pipe == PIPE_B)
2701 dspcntr |= DISPPLANE_SEL_PIPE_B;
2702
2703 /* pipesrc and dspsize control the size that is scaled from,
2704 * which should always be the user's requested size.
2705 */
2706 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2707 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2708 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2709 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2710 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2711 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2712 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2713 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2714 I915_WRITE(PRIMPOS(plane), 0);
2715 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2716 }
81255565 2717
57779d06
VS		 2718 switch (fb->pixel_format) {
2719 case DRM_FORMAT_C8:
81255565
JB		 2720 dspcntr |= DISPPLANE_8BPP;
2721 break;
57779d06
VS		 2722 case DRM_FORMAT_XRGB1555:
2723 case DRM_FORMAT_ARGB1555:
2724 dspcntr |= DISPPLANE_BGRX555;
81255565 2725 break;
57779d06
VS		 2726 case DRM_FORMAT_RGB565:
2727 dspcntr |= DISPPLANE_BGRX565;
2728 break;
2729 case DRM_FORMAT_XRGB8888:
2730 case DRM_FORMAT_ARGB8888:
2731 dspcntr |= DISPPLANE_BGRX888;
2732 break;
2733 case DRM_FORMAT_XBGR8888:
2734 case DRM_FORMAT_ABGR8888:
2735 dspcntr |= DISPPLANE_RGBX888;
2736 break;
2737 case DRM_FORMAT_XRGB2101010:
2738 case DRM_FORMAT_ARGB2101010:
2739 dspcntr |= DISPPLANE_BGRX101010;
2740 break;
2741 case DRM_FORMAT_XBGR2101010:
2742 case DRM_FORMAT_ABGR2101010:
2743 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2744 break;
2745 default:
baba133a 2746 BUG();
81255565 2747 }
57779d06 2748
f45651ba
VS		 2749 if (INTEL_INFO(dev)->gen >= 4 &&
2750 obj->tiling_mode != I915_TILING_NONE)
2751 dspcntr |= DISPPLANE_TILED;
81255565 2752
de1aa629
VS		 2753 if (IS_G4X(dev))
2754 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2755
b9897127 2756 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2757
c2c75131
DV		 2758 if (INTEL_INFO(dev)->gen >= 4) {
2759 intel_crtc->dspaddr_offset =
bc752862 2760 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2761 pixel_size,
bc752862 2762 fb->pitches[0]);
c2c75131
DV		 2763 linear_offset -= intel_crtc->dspaddr_offset;
2764 } else {
e506a0c6 2765 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2766 }
e506a0c6 2767
8e7d688b 2768 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2769 dspcntr |= DISPPLANE_ROTATE_180;
2770
6e3c9717
ACO		 2771 x += (intel_crtc->config->pipe_src_w - 1);
2772 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2773
2774 /* Finding the last pixel of the last line of the display
2775 data and adding to linear_offset*/
2776 linear_offset +=
6e3c9717
ACO		 2777 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2778 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2779 }
2780
2781 I915_WRITE(reg, dspcntr);
2782
01f2c773 2783 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2784 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2785 I915_WRITE(DSPSURF(plane),
2786 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2787 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2788 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2789 } else
f343c5f6 2790 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2791 POSTING_READ(reg);
17638cd6
JB		 2792}
2793
29b9bde6
DV		 2794static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2795 struct drm_framebuffer *fb,
2796 int x, int y)
17638cd6
JB		 2797{
2798 struct drm_device *dev = crtc->dev;
2799 struct drm_i915_private *dev_priv = dev->dev_private;
2800 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
c9ba6fad 2801 struct drm_i915_gem_object *obj;
17638cd6 2802 int plane = intel_crtc->plane;
e506a0c6 2803 unsigned long linear_offset;
17638cd6 2804 u32 dspcntr;
f45651ba 2805 u32 reg = DSPCNTR(plane);
48404c1e 2806 int pixel_size;
f45651ba 2807
fdd508a6
VS		 2808 if (!intel_crtc->primary_enabled) {
2809 I915_WRITE(reg, 0);
2810 I915_WRITE(DSPSURF(plane), 0);
2811 POSTING_READ(reg);
2812 return;
2813 }
2814
c9ba6fad
VS		 2815 obj = intel_fb_obj(fb);
2816 if (WARN_ON(obj == NULL))
2817 return;
2818
2819 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2820
f45651ba
VS		 2821 dspcntr = DISPPLANE_GAMMA_ENABLE;
2822
fdd508a6 2823 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2824
2825 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2826 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2827
57779d06
VS		 2828 switch (fb->pixel_format) {
2829 case DRM_FORMAT_C8:
17638cd6
JB		 2830 dspcntr |= DISPPLANE_8BPP;
2831 break;
57779d06
VS		 2832 case DRM_FORMAT_RGB565:
2833 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2834 break;
57779d06
VS		 2835 case DRM_FORMAT_XRGB8888:
2836 case DRM_FORMAT_ARGB8888:
2837 dspcntr |= DISPPLANE_BGRX888;
2838 break;
2839 case DRM_FORMAT_XBGR8888:
2840 case DRM_FORMAT_ABGR8888:
2841 dspcntr |= DISPPLANE_RGBX888;
2842 break;
2843 case DRM_FORMAT_XRGB2101010:
2844 case DRM_FORMAT_ARGB2101010:
2845 dspcntr |= DISPPLANE_BGRX101010;
2846 break;
2847 case DRM_FORMAT_XBGR2101010:
2848 case DRM_FORMAT_ABGR2101010:
2849 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2850 break;
2851 default:
baba133a 2852 BUG();
17638cd6
JB		 2853 }
2854
2855 if (obj->tiling_mode != I915_TILING_NONE)
2856 dspcntr |= DISPPLANE_TILED;
17638cd6 2857
f45651ba 2858 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2859 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2860
b9897127 2861 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2862 intel_crtc->dspaddr_offset =
bc752862 2863 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2864 pixel_size,
bc752862 2865 fb->pitches[0]);
c2c75131 2866 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2867 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2868 dspcntr |= DISPPLANE_ROTATE_180;
2869
2870 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2871 x += (intel_crtc->config->pipe_src_w - 1);
2872 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2873
2874 /* Finding the last pixel of the last line of the display
2875 data and adding to linear_offset*/
2876 linear_offset +=
6e3c9717
ACO		 2877 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2878 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2879 }
2880 }
2881
2882 I915_WRITE(reg, dspcntr);
17638cd6 2883
01f2c773 2884 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2885 I915_WRITE(DSPSURF(plane),
2886 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2887 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2888 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2889 } else {
2890 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2891 I915_WRITE(DSPLINOFF(plane), linear_offset);
2892 }
17638cd6 2893 POSTING_READ(reg);
17638cd6
JB		 2894}
2895
b321803d
DL		 2896u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2897 uint32_t pixel_format)
2898{
2899 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2900
2901 /*
2902 * The stride is either expressed as a multiple of 64 bytes
2903 * chunks for linear buffers or in number of tiles for tiled
2904 * buffers.
2905 */
2906 switch (fb_modifier) {
2907 case DRM_FORMAT_MOD_NONE:
2908 return 64;
2909 case I915_FORMAT_MOD_X_TILED:
2910 if (INTEL_INFO(dev)->gen == 2)
2911 return 128;
2912 return 512;
2913 case I915_FORMAT_MOD_Y_TILED:
2914 /* No need to check for old gens and Y tiling since this is
2915 * about the display engine and those will be blocked before
2916 * we get here.
2917 */
2918 return 128;
2919 case I915_FORMAT_MOD_Yf_TILED:
2920 if (bits_per_pixel == 8)
2921 return 64;
2922 else
2923 return 128;
2924 default:
2925 MISSING_CASE(fb_modifier);
2926 return 64;
2927 }
2928}
2929
121920fa
TU		 2930unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2931 struct drm_i915_gem_object *obj)
2932{
2933 enum i915_ggtt_view_type view = I915_GGTT_VIEW_NORMAL;
2934
2935 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2936 view = I915_GGTT_VIEW_ROTATED;
2937
2938 return i915_gem_obj_ggtt_offset_view(obj, view);
2939}
2940
70d21f0e
DL		 2941static void skylake_update_primary_plane(struct drm_crtc *crtc,
2942 struct drm_framebuffer *fb,
2943 int x, int y)
2944{
2945 struct drm_device *dev = crtc->dev;
2946 struct drm_i915_private *dev_priv = dev->dev_private;
2947 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
70d21f0e
DL		 2948 struct drm_i915_gem_object *obj;
2949 int pipe = intel_crtc->pipe;
b321803d 2950 u32 plane_ctl, stride_div;
121920fa 2951 unsigned long surf_addr;
70d21f0e
DL		 2952
2953 if (!intel_crtc->primary_enabled) {
2954 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2955 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2956 POSTING_READ(PLANE_CTL(pipe, 0));
2957 return;
2958 }
2959
2960 plane_ctl = PLANE_CTL_ENABLE |
2961 PLANE_CTL_PIPE_GAMMA_ENABLE |
2962 PLANE_CTL_PIPE_CSC_ENABLE;
2963
2964 switch (fb->pixel_format) {
2965 case DRM_FORMAT_RGB565:
2966 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2967 break;
2968 case DRM_FORMAT_XRGB8888:
2969 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2970 break;
f75fb42a
JN		 2971 case DRM_FORMAT_ARGB8888:
2972 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2973 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2974 break;
70d21f0e
DL		 2975 case DRM_FORMAT_XBGR8888:
2976 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2977 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2978 break;
f75fb42a
JN		 2979 case DRM_FORMAT_ABGR8888:
2980 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2981 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2982 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2983 break;
70d21f0e
DL		 2984 case DRM_FORMAT_XRGB2101010:
2985 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2986 break;
2987 case DRM_FORMAT_XBGR2101010:
2988 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2989 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2990 break;
2991 default:
2992 BUG();
2993 }
2994
30af77c4
DV		 2995 switch (fb->modifier[0]) {
2996 case DRM_FORMAT_MOD_NONE:
70d21f0e 2997 break;
30af77c4 2998 case I915_FORMAT_MOD_X_TILED:
70d21f0e 2999 plane_ctl |= PLANE_CTL_TILED_X;
b321803d
DL		 3000 break;
3001 case I915_FORMAT_MOD_Y_TILED:
3002 plane_ctl |= PLANE_CTL_TILED_Y;
3003 break;
3004 case I915_FORMAT_MOD_Yf_TILED:
3005 plane_ctl |= PLANE_CTL_TILED_YF;
70d21f0e
DL		 3006 break;
3007 default:
b321803d 3008 MISSING_CASE(fb->modifier[0]);
70d21f0e
DL		 3009 }
3010
3011 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
8e7d688b 3012 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180))
1447dde0 3013 plane_ctl |= PLANE_CTL_ROTATE_180;
70d21f0e 3014
b321803d
DL		 3015 obj = intel_fb_obj(fb);
3016 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3017 fb->pixel_format);
121920fa 3018 surf_addr = intel_plane_obj_offset(to_intel_plane(crtc->primary), obj);
b321803d 3019
70d21f0e 3020 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
70d21f0e
DL		 3021 I915_WRITE(PLANE_POS(pipe, 0), 0);
3022 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
3023 I915_WRITE(PLANE_SIZE(pipe, 0),
6e3c9717
ACO		 3024 (intel_crtc->config->pipe_src_h - 1) << 16 |
3025 (intel_crtc->config->pipe_src_w - 1));
b321803d 3026 I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
121920fa 3027 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3028
3029 POSTING_READ(PLANE_SURF(pipe, 0));
3030}
3031
17638cd6
JB		 3032/* Assume fb object is pinned & idle & fenced and just update base pointers */
3033static int
3034intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3035 int x, int y, enum mode_set_atomic state)
3036{
3037 struct drm_device *dev = crtc->dev;
3038 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3039
6b8e6ed0
CW		 3040 if (dev_priv->display.disable_fbc)
3041 dev_priv->display.disable_fbc(dev);
81255565 3042
29b9bde6
DV		 3043 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3044
3045 return 0;
81255565
JB		 3046}
3047
7514747d 3048static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3049{
96a02917
VS		 3050 struct drm_crtc *crtc;
3051
70e1e0ec 3052 for_each_crtc(dev, crtc) {
96a02917
VS		 3053 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3054 enum plane plane = intel_crtc->plane;
3055
3056 intel_prepare_page_flip(dev, plane);
3057 intel_finish_page_flip_plane(dev, plane);
3058 }
7514747d
VS		 3059}
3060
3061static void intel_update_primary_planes(struct drm_device *dev)
3062{
3063 struct drm_i915_private *dev_priv = dev->dev_private;
3064 struct drm_crtc *crtc;
96a02917 3065
70e1e0ec 3066 for_each_crtc(dev, crtc) {
96a02917
VS		 3067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3068
51fd371b 3069 drm_modeset_lock(&crtc->mutex, NULL);
947fdaad
CW		 3070 /*
3071 * FIXME: Once we have proper support for primary planes (and
3072 * disabling them without disabling the entire crtc) allow again
66e514c1 3073 * a NULL crtc->primary->fb.
947fdaad 3074 */
f4510a27 3075 if (intel_crtc->active && crtc->primary->fb)
262ca2b0 3076 dev_priv->display.update_primary_plane(crtc,
66e514c1 3077 crtc->primary->fb,
262ca2b0
MR		 3078 crtc->x,
3079 crtc->y);
51fd371b 3080 drm_modeset_unlock(&crtc->mutex);
96a02917
VS		 3081 }
3082}
3083
7514747d
VS		 3084void intel_prepare_reset(struct drm_device *dev)
3085{
f98ce92f
VS		 3086 struct drm_i915_private *dev_priv = to_i915(dev);
3087 struct intel_crtc *crtc;
3088
7514747d
VS		 3089 /* no reset support for gen2 */
3090 if (IS_GEN2(dev))
3091 return;
3092
3093 /* reset doesn't touch the display */
3094 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3095 return;
3096
3097 drm_modeset_lock_all(dev);
f98ce92f
VS		 3098
3099 /*
3100 * Disabling the crtcs gracefully seems nicer. Also the
3101 * g33 docs say we should at least disable all the planes.
3102 */
3103 for_each_intel_crtc(dev, crtc) {
3104 if (crtc->active)
3105 dev_priv->display.crtc_disable(&crtc->base);
3106 }
7514747d
VS		 3107}
3108
3109void intel_finish_reset(struct drm_device *dev)
3110{
3111 struct drm_i915_private *dev_priv = to_i915(dev);
3112
3113 /*
3114 * Flips in the rings will be nuked by the reset,
3115 * so complete all pending flips so that user space
3116 * will get its events and not get stuck.
3117 */
3118 intel_complete_page_flips(dev);
3119
3120 /* no reset support for gen2 */
3121 if (IS_GEN2(dev))
3122 return;
3123
3124 /* reset doesn't touch the display */
3125 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3126 /*
3127 * Flips in the rings have been nuked by the reset,
3128 * so update the base address of all primary
3129 * planes to the the last fb to make sure we're
3130 * showing the correct fb after a reset.
3131 */
3132 intel_update_primary_planes(dev);
3133 return;
3134 }
3135
3136 /*
3137 * The display has been reset as well,
3138 * so need a full re-initialization.
3139 */
3140 intel_runtime_pm_disable_interrupts(dev_priv);
3141 intel_runtime_pm_enable_interrupts(dev_priv);
3142
3143 intel_modeset_init_hw(dev);
3144
3145 spin_lock_irq(&dev_priv->irq_lock);
3146 if (dev_priv->display.hpd_irq_setup)
3147 dev_priv->display.hpd_irq_setup(dev);
3148 spin_unlock_irq(&dev_priv->irq_lock);
3149
3150 intel_modeset_setup_hw_state(dev, true);
3151
3152 intel_hpd_init(dev_priv);
3153
3154 drm_modeset_unlock_all(dev);
3155}
3156
14667a4b
CW		 3157static int
3158intel_finish_fb(struct drm_framebuffer *old_fb)
3159{
2ff8fde1 3160 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
14667a4b
CW		 3161 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3162 bool was_interruptible = dev_priv->mm.interruptible;
3163 int ret;
3164
14667a4b
CW		 3165 /* Big Hammer, we also need to ensure that any pending
3166 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3167 * current scanout is retired before unpinning the old
3168 * framebuffer.
3169 *
3170 * This should only fail upon a hung GPU, in which case we
3171 * can safely continue.
3172 */
3173 dev_priv->mm.interruptible = false;
3174 ret = i915_gem_object_finish_gpu(obj);
3175 dev_priv->mm.interruptible = was_interruptible;
3176
3177 return ret;
3178}
3179
7d5e3799
CW		 3180static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3181{
3182 struct drm_device *dev = crtc->dev;
3183 struct drm_i915_private *dev_priv = dev->dev_private;
3184 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3185 bool pending;
3186
3187 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3188 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3189 return false;
3190
5e2d7afc 3191 spin_lock_irq(&dev->event_lock);
7d5e3799 3192 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3193 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3194
3195 return pending;
3196}
3197
e30e8f75
GP		 3198static void intel_update_pipe_size(struct intel_crtc *crtc)
3199{
3200 struct drm_device *dev = crtc->base.dev;
3201 struct drm_i915_private *dev_priv = dev->dev_private;
3202 const struct drm_display_mode *adjusted_mode;
3203
3204 if (!i915.fastboot)
3205 return;
3206
3207 /*
3208 * Update pipe size and adjust fitter if needed: the reason for this is
3209 * that in compute_mode_changes we check the native mode (not the pfit
3210 * mode) to see if we can flip rather than do a full mode set. In the
3211 * fastboot case, we'll flip, but if we don't update the pipesrc and
3212 * pfit state, we'll end up with a big fb scanned out into the wrong
3213 * sized surface.
3214 *
3215 * To fix this properly, we need to hoist the checks up into
3216 * compute_mode_changes (or above), check the actual pfit state and
3217 * whether the platform allows pfit disable with pipe active, and only
3218 * then update the pipesrc and pfit state, even on the flip path.
3219 */
3220
6e3c9717 3221 adjusted_mode = &crtc->config->base.adjusted_mode;
e30e8f75
GP		 3222
3223 I915_WRITE(PIPESRC(crtc->pipe),
3224 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3225 (adjusted_mode->crtc_vdisplay - 1));
6e3c9717 3226 if (!crtc->config->pch_pfit.enabled &&
409ee761
ACO		 3227 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3228 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
e30e8f75
GP		 3229 I915_WRITE(PF_CTL(crtc->pipe), 0);
3230 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3231 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3232 }
6e3c9717
ACO		 3233 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3234 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
e30e8f75
GP		 3235}
3236
5e84e1a4
ZW		 3237static void intel_fdi_normal_train(struct drm_crtc *crtc)
3238{
3239 struct drm_device *dev = crtc->dev;
3240 struct drm_i915_private *dev_priv = dev->dev_private;
3241 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3242 int pipe = intel_crtc->pipe;
3243 u32 reg, temp;
3244
3245 /* enable normal train */
3246 reg = FDI_TX_CTL(pipe);
3247 temp = I915_READ(reg);
61e499bf 3248 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3249 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3250 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3251 } else {
3252 temp &= ~FDI_LINK_TRAIN_NONE;
3253 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3254 }
5e84e1a4
ZW		 3255 I915_WRITE(reg, temp);
3256
3257 reg = FDI_RX_CTL(pipe);
3258 temp = I915_READ(reg);
3259 if (HAS_PCH_CPT(dev)) {
3260 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3261 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3262 } else {
3263 temp &= ~FDI_LINK_TRAIN_NONE;
3264 temp |= FDI_LINK_TRAIN_NONE;
3265 }
3266 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3267
3268 /* wait one idle pattern time */
3269 POSTING_READ(reg);
3270 udelay(1000);
357555c0
JB		 3271
3272 /* IVB wants error correction enabled */
3273 if (IS_IVYBRIDGE(dev))
3274 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3275 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3276}
3277
8db9d77b
ZW		 3278/* The FDI link training functions for ILK/Ibexpeak. */
3279static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3280{
3281 struct drm_device *dev = crtc->dev;
3282 struct drm_i915_private *dev_priv = dev->dev_private;
3283 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3284 int pipe = intel_crtc->pipe;
5eddb70b 3285 u32 reg, temp, tries;
8db9d77b 3286
1c8562f6 3287 /* FDI needs bits from pipe first */
0fc932b8 3288 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3289
e1a44743
AJ		 3290 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3291 for train result */
5eddb70b
CW		 3292 reg = FDI_RX_IMR(pipe);
3293 temp = I915_READ(reg);
e1a44743
AJ		 3294 temp &= ~FDI_RX_SYMBOL_LOCK;
3295 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3296 I915_WRITE(reg, temp);
3297 I915_READ(reg);
e1a44743
AJ		 3298 udelay(150);
3299
8db9d77b 3300 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3301 reg = FDI_TX_CTL(pipe);
3302 temp = I915_READ(reg);
627eb5a3 3303 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3304 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3305 temp &= ~FDI_LINK_TRAIN_NONE;
3306 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3307 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3308
5eddb70b
CW		 3309 reg = FDI_RX_CTL(pipe);
3310 temp = I915_READ(reg);
8db9d77b
ZW		 3311 temp &= ~FDI_LINK_TRAIN_NONE;
3312 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3313 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3314
3315 POSTING_READ(reg);
8db9d77b
ZW		 3316 udelay(150);
3317
5b2adf89 3318 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3319 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3320 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3321 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3322
5eddb70b 3323 reg = FDI_RX_IIR(pipe);
e1a44743 3324 for (tries = 0; tries < 5; tries++) {
5eddb70b 3325 temp = I915_READ(reg);
8db9d77b
ZW		 3326 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3327
3328 if ((temp & FDI_RX_BIT_LOCK)) {
3329 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3330 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3331 break;
3332 }
8db9d77b 3333 }
e1a44743 3334 if (tries == 5)
5eddb70b 3335 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3336
3337 /* Train 2 */
5eddb70b
CW		 3338 reg = FDI_TX_CTL(pipe);
3339 temp = I915_READ(reg);
8db9d77b
ZW		 3340 temp &= ~FDI_LINK_TRAIN_NONE;
3341 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3342 I915_WRITE(reg, temp);
8db9d77b 3343
5eddb70b
CW		 3344 reg = FDI_RX_CTL(pipe);
3345 temp = I915_READ(reg);
8db9d77b
ZW		 3346 temp &= ~FDI_LINK_TRAIN_NONE;
3347 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3348 I915_WRITE(reg, temp);
8db9d77b 3349
5eddb70b
CW		 3350 POSTING_READ(reg);
3351 udelay(150);
8db9d77b 3352
5eddb70b 3353 reg = FDI_RX_IIR(pipe);
e1a44743 3354 for (tries = 0; tries < 5; tries++) {
5eddb70b 3355 temp = I915_READ(reg);
8db9d77b
ZW		 3356 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3357
3358 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3359 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3360 DRM_DEBUG_KMS("FDI train 2 done.\n");
3361 break;
3362 }
8db9d77b 3363 }
e1a44743 3364 if (tries == 5)
5eddb70b 3365 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3366
3367 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3368
8db9d77b
ZW		 3369}
3370
0206e353 3371static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3372 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3373 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3374 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3375 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3376};
3377
3378/* The FDI link training functions for SNB/Cougarpoint. */
3379static void gen6_fdi_link_train(struct drm_crtc *crtc)
3380{
3381 struct drm_device *dev = crtc->dev;
3382 struct drm_i915_private *dev_priv = dev->dev_private;
3383 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3384 int pipe = intel_crtc->pipe;
fa37d39e 3385 u32 reg, temp, i, retry;
8db9d77b 3386
e1a44743
AJ		 3387 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3388 for train result */
5eddb70b
CW		 3389 reg = FDI_RX_IMR(pipe);
3390 temp = I915_READ(reg);
e1a44743
AJ		 3391 temp &= ~FDI_RX_SYMBOL_LOCK;
3392 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3393 I915_WRITE(reg, temp);
3394
3395 POSTING_READ(reg);
e1a44743
AJ		 3396 udelay(150);
3397
8db9d77b 3398 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3399 reg = FDI_TX_CTL(pipe);
3400 temp = I915_READ(reg);
627eb5a3 3401 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3402 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3403 temp &= ~FDI_LINK_TRAIN_NONE;
3404 temp |= FDI_LINK_TRAIN_PATTERN_1;
3405 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3406 /* SNB-B */
3407 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3408 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3409
d74cf324
DV		 3410 I915_WRITE(FDI_RX_MISC(pipe),
3411 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3412
5eddb70b
CW		 3413 reg = FDI_RX_CTL(pipe);
3414 temp = I915_READ(reg);
8db9d77b
ZW		 3415 if (HAS_PCH_CPT(dev)) {
3416 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3417 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3418 } else {
3419 temp &= ~FDI_LINK_TRAIN_NONE;
3420 temp |= FDI_LINK_TRAIN_PATTERN_1;
3421 }
5eddb70b
CW		 3422 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3423
3424 POSTING_READ(reg);
8db9d77b
ZW		 3425 udelay(150);
3426
0206e353 3427 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3428 reg = FDI_TX_CTL(pipe);
3429 temp = I915_READ(reg);
8db9d77b
ZW		 3430 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3431 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3432 I915_WRITE(reg, temp);
3433
3434 POSTING_READ(reg);
8db9d77b
ZW		 3435 udelay(500);
3436
fa37d39e
SP		 3437 for (retry = 0; retry < 5; retry++) {
3438 reg = FDI_RX_IIR(pipe);
3439 temp = I915_READ(reg);
3440 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3441 if (temp & FDI_RX_BIT_LOCK) {
3442 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3443 DRM_DEBUG_KMS("FDI train 1 done.\n");
3444 break;
3445 }
3446 udelay(50);
8db9d77b 3447 }
fa37d39e
SP		 3448 if (retry < 5)
3449 break;
8db9d77b
ZW		 3450 }
3451 if (i == 4)
5eddb70b 3452 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3453
3454 /* Train 2 */
5eddb70b
CW		 3455 reg = FDI_TX_CTL(pipe);
3456 temp = I915_READ(reg);
8db9d77b
ZW		 3457 temp &= ~FDI_LINK_TRAIN_NONE;
3458 temp |= FDI_LINK_TRAIN_PATTERN_2;
3459 if (IS_GEN6(dev)) {
3460 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3461 /* SNB-B */
3462 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3463 }
5eddb70b 3464 I915_WRITE(reg, temp);
8db9d77b 3465
5eddb70b
CW		 3466 reg = FDI_RX_CTL(pipe);
3467 temp = I915_READ(reg);
8db9d77b
ZW		 3468 if (HAS_PCH_CPT(dev)) {
3469 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3470 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3471 } else {
3472 temp &= ~FDI_LINK_TRAIN_NONE;
3473 temp |= FDI_LINK_TRAIN_PATTERN_2;
3474 }
5eddb70b
CW		 3475 I915_WRITE(reg, temp);
3476
3477 POSTING_READ(reg);
8db9d77b
ZW		 3478 udelay(150);
3479
0206e353 3480 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3481 reg = FDI_TX_CTL(pipe);
3482 temp = I915_READ(reg);
8db9d77b
ZW		 3483 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3484 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3485 I915_WRITE(reg, temp);
3486
3487 POSTING_READ(reg);
8db9d77b
ZW		 3488 udelay(500);
3489
fa37d39e
SP		 3490 for (retry = 0; retry < 5; retry++) {
3491 reg = FDI_RX_IIR(pipe);
3492 temp = I915_READ(reg);
3493 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3494 if (temp & FDI_RX_SYMBOL_LOCK) {
3495 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3496 DRM_DEBUG_KMS("FDI train 2 done.\n");
3497 break;
3498 }
3499 udelay(50);
8db9d77b 3500 }
fa37d39e
SP		 3501 if (retry < 5)
3502 break;
8db9d77b
ZW		 3503 }
3504 if (i == 4)
5eddb70b 3505 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3506
3507 DRM_DEBUG_KMS("FDI train done.\n");
3508}
3509
357555c0
JB		 3510/* Manual link training for Ivy Bridge A0 parts */
3511static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3512{
3513 struct drm_device *dev = crtc->dev;
3514 struct drm_i915_private *dev_priv = dev->dev_private;
3515 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3516 int pipe = intel_crtc->pipe;
139ccd3f 3517 u32 reg, temp, i, j;
357555c0
JB		 3518
3519 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3520 for train result */
3521 reg = FDI_RX_IMR(pipe);
3522 temp = I915_READ(reg);
3523 temp &= ~FDI_RX_SYMBOL_LOCK;
3524 temp &= ~FDI_RX_BIT_LOCK;
3525 I915_WRITE(reg, temp);
3526
3527 POSTING_READ(reg);
3528 udelay(150);
3529
01a415fd
DV		 3530 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3531 I915_READ(FDI_RX_IIR(pipe)));
3532
139ccd3f
JB		 3533 /* Try each vswing and preemphasis setting twice before moving on */
3534 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3535 /* disable first in case we need to retry */
3536 reg = FDI_TX_CTL(pipe);
3537 temp = I915_READ(reg);
3538 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3539 temp &= ~FDI_TX_ENABLE;
3540 I915_WRITE(reg, temp);
357555c0 3541
139ccd3f
JB		 3542 reg = FDI_RX_CTL(pipe);
3543 temp = I915_READ(reg);
3544 temp &= ~FDI_LINK_TRAIN_AUTO;
3545 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3546 temp &= ~FDI_RX_ENABLE;
3547 I915_WRITE(reg, temp);
357555c0 3548
139ccd3f 3549 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3550 reg = FDI_TX_CTL(pipe);
3551 temp = I915_READ(reg);
139ccd3f 3552 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3553 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3554 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3555 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3556 temp |= snb_b_fdi_train_param[j/2];
3557 temp |= FDI_COMPOSITE_SYNC;
3558 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3559
139ccd3f
JB		 3560 I915_WRITE(FDI_RX_MISC(pipe),
3561 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3562
139ccd3f 3563 reg = FDI_RX_CTL(pipe);
357555c0 3564 temp = I915_READ(reg);
139ccd3f
JB		 3565 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3566 temp |= FDI_COMPOSITE_SYNC;
3567 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3568
139ccd3f
JB		 3569 POSTING_READ(reg);
3570 udelay(1); /* should be 0.5us */
357555c0 3571
139ccd3f
JB		 3572 for (i = 0; i < 4; i++) {
3573 reg = FDI_RX_IIR(pipe);
3574 temp = I915_READ(reg);
3575 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3576
139ccd3f
JB		 3577 if (temp & FDI_RX_BIT_LOCK ||
3578 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3579 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3580 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3581 i);
3582 break;
3583 }
3584 udelay(1); /* should be 0.5us */
3585 }
3586 if (i == 4) {
3587 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3588 continue;
3589 }
357555c0 3590
139ccd3f 3591 /* Train 2 */
357555c0
JB		 3592 reg = FDI_TX_CTL(pipe);
3593 temp = I915_READ(reg);
139ccd3f
JB		 3594 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3595 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3596 I915_WRITE(reg, temp);
3597
3598 reg = FDI_RX_CTL(pipe);
3599 temp = I915_READ(reg);
3600 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3601 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3602 I915_WRITE(reg, temp);
3603
3604 POSTING_READ(reg);
139ccd3f 3605 udelay(2); /* should be 1.5us */
357555c0 3606
139ccd3f
JB		 3607 for (i = 0; i < 4; i++) {
3608 reg = FDI_RX_IIR(pipe);
3609 temp = I915_READ(reg);
3610 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3611
139ccd3f
JB		 3612 if (temp & FDI_RX_SYMBOL_LOCK ||
3613 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3614 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3615 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3616 i);
3617 goto train_done;
3618 }
3619 udelay(2); /* should be 1.5us */
357555c0 3620 }
139ccd3f
JB		 3621 if (i == 4)
3622 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3623 }
357555c0 3624
139ccd3f 3625train_done:
357555c0
JB		 3626 DRM_DEBUG_KMS("FDI train done.\n");
3627}
3628
88cefb6c 3629static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3630{
88cefb6c 3631 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3632 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3633 int pipe = intel_crtc->pipe;
5eddb70b 3634 u32 reg, temp;
79e53945 3635
c64e311e 3636
c98e9dcf 3637 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3638 reg = FDI_RX_CTL(pipe);
3639 temp = I915_READ(reg);
627eb5a3 3640 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3641 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3642 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3643 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3644
3645 POSTING_READ(reg);
c98e9dcf
JB		 3646 udelay(200);
3647
3648 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3649 temp = I915_READ(reg);
3650 I915_WRITE(reg, temp | FDI_PCDCLK);
3651
3652 POSTING_READ(reg);
c98e9dcf
JB		 3653 udelay(200);
3654
20749730
PZ		 3655 /* Enable CPU FDI TX PLL, always on for Ironlake */
3656 reg = FDI_TX_CTL(pipe);
3657 temp = I915_READ(reg);
3658 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3659 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3660
20749730
PZ		 3661 POSTING_READ(reg);
3662 udelay(100);
6be4a607 3663 }
0e23b99d
JB		 3664}
3665
88cefb6c
DV		 3666static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3667{
3668 struct drm_device *dev = intel_crtc->base.dev;
3669 struct drm_i915_private *dev_priv = dev->dev_private;
3670 int pipe = intel_crtc->pipe;
3671 u32 reg, temp;
3672
3673 /* Switch from PCDclk to Rawclk */
3674 reg = FDI_RX_CTL(pipe);
3675 temp = I915_READ(reg);
3676 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3677
3678 /* Disable CPU FDI TX PLL */
3679 reg = FDI_TX_CTL(pipe);
3680 temp = I915_READ(reg);
3681 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3682
3683 POSTING_READ(reg);
3684 udelay(100);
3685
3686 reg = FDI_RX_CTL(pipe);
3687 temp = I915_READ(reg);
3688 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3689
3690 /* Wait for the clocks to turn off. */
3691 POSTING_READ(reg);
3692 udelay(100);
3693}
3694
0fc932b8
JB		 3695static void ironlake_fdi_disable(struct drm_crtc *crtc)
3696{
3697 struct drm_device *dev = crtc->dev;
3698 struct drm_i915_private *dev_priv = dev->dev_private;
3699 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3700 int pipe = intel_crtc->pipe;
3701 u32 reg, temp;
3702
3703 /* disable CPU FDI tx and PCH FDI rx */
3704 reg = FDI_TX_CTL(pipe);
3705 temp = I915_READ(reg);
3706 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3707 POSTING_READ(reg);
3708
3709 reg = FDI_RX_CTL(pipe);
3710 temp = I915_READ(reg);
3711 temp &= ~(0x7 << 16);
dfd07d72 3712 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3713 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3714
3715 POSTING_READ(reg);
3716 udelay(100);
3717
3718 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3719 if (HAS_PCH_IBX(dev))
6f06ce18 3720 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3721
3722 /* still set train pattern 1 */
3723 reg = FDI_TX_CTL(pipe);
3724 temp = I915_READ(reg);
3725 temp &= ~FDI_LINK_TRAIN_NONE;
3726 temp |= FDI_LINK_TRAIN_PATTERN_1;
3727 I915_WRITE(reg, temp);
3728
3729 reg = FDI_RX_CTL(pipe);
3730 temp = I915_READ(reg);
3731 if (HAS_PCH_CPT(dev)) {
3732 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3733 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3734 } else {
3735 temp &= ~FDI_LINK_TRAIN_NONE;
3736 temp |= FDI_LINK_TRAIN_PATTERN_1;
3737 }
3738 /* BPC in FDI rx is consistent with that in PIPECONF */
3739 temp &= ~(0x07 << 16);
dfd07d72 3740 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3741 I915_WRITE(reg, temp);
3742
3743 POSTING_READ(reg);
3744 udelay(100);
3745}
3746
5dce5b93
CW		 3747bool intel_has_pending_fb_unpin(struct drm_device *dev)
3748{
3749 struct intel_crtc *crtc;
3750
3751 /* Note that we don't need to be called with mode_config.lock here
3752 * as our list of CRTC objects is static for the lifetime of the
3753 * device and so cannot disappear as we iterate. Similarly, we can
3754 * happily treat the predicates as racy, atomic checks as userspace
3755 * cannot claim and pin a new fb without at least acquring the
3756 * struct_mutex and so serialising with us.
3757 */
d3fcc808 3758 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3759 if (atomic_read(&crtc->unpin_work_count) == 0)
3760 continue;
3761
3762 if (crtc->unpin_work)
3763 intel_wait_for_vblank(dev, crtc->pipe);
3764
3765 return true;
3766 }
3767
3768 return false;
3769}
3770
d6bbafa1
CW		 3771static void page_flip_completed(struct intel_crtc *intel_crtc)
3772{
3773 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3774 struct intel_unpin_work *work = intel_crtc->unpin_work;
3775
3776 /* ensure that the unpin work is consistent wrt ->pending. */
3777 smp_rmb();
3778 intel_crtc->unpin_work = NULL;
3779
3780 if (work->event)
3781 drm_send_vblank_event(intel_crtc->base.dev,
3782 intel_crtc->pipe,
3783 work->event);
3784
3785 drm_crtc_vblank_put(&intel_crtc->base);
3786
3787 wake_up_all(&dev_priv->pending_flip_queue);
3788 queue_work(dev_priv->wq, &work->work);
3789
3790 trace_i915_flip_complete(intel_crtc->plane,
3791 work->pending_flip_obj);
3792}
3793
46a55d30 3794void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3795{
0f91128d 3796 struct drm_device *dev = crtc->dev;
5bb61643 3797 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3798
2c10d571 3799 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW		 3800 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3801 !intel_crtc_has_pending_flip(crtc),
3802 60*HZ) == 0)) {
3803 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3804
5e2d7afc 3805 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3806 if (intel_crtc->unpin_work) {
3807 WARN_ONCE(1, "Removing stuck page flip\n");
3808 page_flip_completed(intel_crtc);
3809 }
5e2d7afc 3810 spin_unlock_irq(&dev->event_lock);
9c787942 3811 }
5bb61643 3812
975d568a
CW		 3813 if (crtc->primary->fb) {
3814 mutex_lock(&dev->struct_mutex);
3815 intel_finish_fb(crtc->primary->fb);
3816 mutex_unlock(&dev->struct_mutex);
3817 }
e6c3a2a6
CW		 3818}
3819
e615efe4
ED		 3820/* Program iCLKIP clock to the desired frequency */
3821static void lpt_program_iclkip(struct drm_crtc *crtc)
3822{
3823 struct drm_device *dev = crtc->dev;
3824 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3825 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3826 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3827 u32 temp;
3828
09153000
DV		 3829 mutex_lock(&dev_priv->dpio_lock);
3830
e615efe4
ED		 3831 /* It is necessary to ungate the pixclk gate prior to programming
3832 * the divisors, and gate it back when it is done.
3833 */
3834 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3835
3836 /* Disable SSCCTL */
3837 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3838 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3839 SBI_SSCCTL_DISABLE,
3840 SBI_ICLK);
e615efe4
ED		 3841
3842 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3843 if (clock == 20000) {
e615efe4
ED		 3844 auxdiv = 1;
3845 divsel = 0x41;
3846 phaseinc = 0x20;
3847 } else {
3848 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3849 * but the adjusted_mode->crtc_clock in in KHz. To get the
3850 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3851 * convert the virtual clock precision to KHz here for higher
3852 * precision.
3853 */
3854 u32 iclk_virtual_root_freq = 172800 * 1000;
3855 u32 iclk_pi_range = 64;
3856 u32 desired_divisor, msb_divisor_value, pi_value;
3857
12d7ceed 3858 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3859 msb_divisor_value = desired_divisor / iclk_pi_range;
3860 pi_value = desired_divisor % iclk_pi_range;
3861
3862 auxdiv = 0;
3863 divsel = msb_divisor_value - 2;
3864 phaseinc = pi_value;
3865 }
3866
3867 /* This should not happen with any sane values */
3868 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3869 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3870 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3871 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3872
3873 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3874 clock,
e615efe4
ED		 3875 auxdiv,
3876 divsel,
3877 phasedir,
3878 phaseinc);
3879
3880 /* Program SSCDIVINTPHASE6 */
988d6ee8 3881 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3882 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3883 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3884 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3885 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3886 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3887 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3888 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3889
3890 /* Program SSCAUXDIV */
988d6ee8 3891 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3892 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3893 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3894 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3895
3896 /* Enable modulator and associated divider */
988d6ee8 3897 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3898 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3899 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3900
3901 /* Wait for initialization time */
3902 udelay(24);
3903
3904 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3905
3906 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3907}
3908
275f01b2
DV		 3909static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3910 enum pipe pch_transcoder)
3911{
3912 struct drm_device *dev = crtc->base.dev;
3913 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3914 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 3915
3916 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3917 I915_READ(HTOTAL(cpu_transcoder)));
3918 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3919 I915_READ(HBLANK(cpu_transcoder)));
3920 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3921 I915_READ(HSYNC(cpu_transcoder)));
3922
3923 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3924 I915_READ(VTOTAL(cpu_transcoder)));
3925 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3926 I915_READ(VBLANK(cpu_transcoder)));
3927 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3928 I915_READ(VSYNC(cpu_transcoder)));
3929 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3930 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3931}
3932
003632d9 3933static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 3934{
3935 struct drm_i915_private *dev_priv = dev->dev_private;
3936 uint32_t temp;
3937
3938 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 3939 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 3940 return;
3941
3942 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3943 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3944
003632d9
ACO		 3945 temp &= ~FDI_BC_BIFURCATION_SELECT;
3946 if (enable)
3947 temp |= FDI_BC_BIFURCATION_SELECT;
3948
3949 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 3950 I915_WRITE(SOUTH_CHICKEN1, temp);
3951 POSTING_READ(SOUTH_CHICKEN1);
3952}
3953
3954static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3955{
3956 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 3957
3958 switch (intel_crtc->pipe) {
3959 case PIPE_A:
3960 break;
3961 case PIPE_B:
6e3c9717 3962 if (intel_crtc->config->fdi_lanes > 2)
003632d9 3963 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 3964 else
003632d9 3965 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 3966
3967 break;
3968 case PIPE_C:
003632d9 3969 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 3970
3971 break;
3972 default:
3973 BUG();
3974 }
3975}
3976
f67a559d
JB		 3977/*
3978 * Enable PCH resources required for PCH ports:
3979 * - PCH PLLs
3980 * - FDI training & RX/TX
3981 * - update transcoder timings
3982 * - DP transcoding bits
3983 * - transcoder
3984 */
3985static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3986{
3987 struct drm_device *dev = crtc->dev;
3988 struct drm_i915_private *dev_priv = dev->dev_private;
3989 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3990 int pipe = intel_crtc->pipe;
ee7b9f93 3991 u32 reg, temp;
2c07245f 3992
ab9412ba 3993 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 3994
1fbc0d78
DV		 3995 if (IS_IVYBRIDGE(dev))
3996 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3997
cd986abb
DV		 3998 /* Write the TU size bits before fdi link training, so that error
3999 * detection works. */
4000 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4001 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4002
c98e9dcf 4003 /* For PCH output, training FDI link */
674cf967 4004 dev_priv->display.fdi_link_train(crtc);
2c07245f 4005
3ad8a208
DV		 4006 /* We need to program the right clock selection before writing the pixel
4007 * mutliplier into the DPLL. */
303b81e0 4008 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4009 u32 sel;
4b645f14 4010
c98e9dcf 4011 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4012 temp |= TRANS_DPLL_ENABLE(pipe);
4013 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4014 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4015 temp |= sel;
4016 else
4017 temp &= ~sel;
c98e9dcf 4018 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4019 }
5eddb70b 4020
3ad8a208
DV		 4021 /* XXX: pch pll's can be enabled any time before we enable the PCH
4022 * transcoder, and we actually should do this to not upset any PCH
4023 * transcoder that already use the clock when we share it.
4024 *
4025 * Note that enable_shared_dpll tries to do the right thing, but
4026 * get_shared_dpll unconditionally resets the pll - we need that to have
4027 * the right LVDS enable sequence. */
85b3894f 4028 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4029
d9b6cb56
JB		 4030 /* set transcoder timing, panel must allow it */
4031 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4032 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4033
303b81e0 4034 intel_fdi_normal_train(crtc);
5e84e1a4 4035
c98e9dcf 4036 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4037 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4038 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4039 reg = TRANS_DP_CTL(pipe);
4040 temp = I915_READ(reg);
4041 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4042 TRANS_DP_SYNC_MASK |
4043 TRANS_DP_BPC_MASK);
5eddb70b
CW		 4044 temp |= (TRANS_DP_OUTPUT_ENABLE |
4045 TRANS_DP_ENH_FRAMING);
9325c9f0 4046 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4047
4048 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4049 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4050 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4051 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4052
4053 switch (intel_trans_dp_port_sel(crtc)) {
4054 case PCH_DP_B:
5eddb70b 4055 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4056 break;
4057 case PCH_DP_C:
5eddb70b 4058 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4059 break;
4060 case PCH_DP_D:
5eddb70b 4061 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4062 break;
4063 default:
e95d41e1 4064 BUG();
32f9d658 4065 }
2c07245f 4066
5eddb70b 4067 I915_WRITE(reg, temp);
6be4a607 4068 }
b52eb4dc 4069
b8a4f404 4070 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4071}
4072
1507e5bd
PZ		 4073static void lpt_pch_enable(struct drm_crtc *crtc)
4074{
4075 struct drm_device *dev = crtc->dev;
4076 struct drm_i915_private *dev_priv = dev->dev_private;
4077 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4078 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4079
ab9412ba 4080 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4081
8c52b5e8 4082 lpt_program_iclkip(crtc);
1507e5bd 4083
0540e488 4084 /* Set transcoder timing. */
275f01b2 4085 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4086
937bb610 4087 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4088}
4089
716c2e55 4090void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 4091{
e2b78267 4092 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 4093
4094 if (pll == NULL)
4095 return;
4096
3e369b76 4097 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
1e6f2ddc 4098 WARN(1, "bad %s crtc mask\n", pll->name);
ee7b9f93
JB		 4099 return;
4100 }
4101
3e369b76
ACO		 4102 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4103 if (pll->config.crtc_mask == 0) {
f4a091c7
DV		 4104 WARN_ON(pll->on);
4105 WARN_ON(pll->active);
4106 }
4107
6e3c9717 4108 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 4109}
4110
190f68c5
ACO		 4111struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4112 struct intel_crtc_state *crtc_state)
ee7b9f93 4113{
e2b78267 4114 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4115 struct intel_shared_dpll *pll;
e2b78267 4116 enum intel_dpll_id i;
ee7b9f93 4117
98b6bd99
DV		 4118 if (HAS_PCH_IBX(dev_priv->dev)) {
4119 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4120 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4121 pll = &dev_priv->shared_dplls[i];
98b6bd99 4122
46edb027
DV		 4123 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4124 crtc->base.base.id, pll->name);
98b6bd99 4125
8bd31e67 4126 WARN_ON(pll->new_config->crtc_mask);
f2a69f44 4127
98b6bd99
DV		 4128 goto found;
4129 }
4130
e72f9fbf
DV		 4131 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4132 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4133
4134 /* Only want to check enabled timings first */
8bd31e67 4135 if (pll->new_config->crtc_mask == 0)
ee7b9f93
JB		 4136 continue;
4137
190f68c5 4138 if (memcmp(&crtc_state->dpll_hw_state,
8bd31e67
ACO		 4139 &pll->new_config->hw_state,
4140 sizeof(pll->new_config->hw_state)) == 0) {
4141 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4142 crtc->base.base.id, pll->name,
8bd31e67
ACO		 4143 pll->new_config->crtc_mask,
4144 pll->active);
ee7b9f93
JB		 4145 goto found;
4146 }
4147 }
4148
4149 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4150 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4151 pll = &dev_priv->shared_dplls[i];
8bd31e67 4152 if (pll->new_config->crtc_mask == 0) {
46edb027
DV		 4153 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4154 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4155 goto found;
4156 }
4157 }
4158
4159 return NULL;
4160
4161found:
8bd31e67 4162 if (pll->new_config->crtc_mask == 0)
190f68c5 4163 pll->new_config->hw_state = crtc_state->dpll_hw_state;
f2a69f44 4164
190f68c5 4165 crtc_state->shared_dpll = i;
46edb027
DV		 4166 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4167 pipe_name(crtc->pipe));
ee7b9f93 4168
8bd31e67 4169 pll->new_config->crtc_mask |= 1 << crtc->pipe;
e04c7350 4170
ee7b9f93
JB		 4171 return pll;
4172}
4173
8bd31e67
ACO		 4174/**
4175 * intel_shared_dpll_start_config - start a new PLL staged config
4176 * @dev_priv: DRM device
4177 * @clear_pipes: mask of pipes that will have their PLLs freed
4178 *
4179 * Starts a new PLL staged config, copying the current config but
4180 * releasing the references of pipes specified in clear_pipes.
4181 */
4182static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4183 unsigned clear_pipes)
4184{
4185 struct intel_shared_dpll *pll;
4186 enum intel_dpll_id i;
4187
4188 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4189 pll = &dev_priv->shared_dplls[i];
4190
4191 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4192 GFP_KERNEL);
4193 if (!pll->new_config)
4194 goto cleanup;
4195
4196 pll->new_config->crtc_mask &= ~clear_pipes;
4197 }
4198
4199 return 0;
4200
4201cleanup:
4202 while (--i >= 0) {
4203 pll = &dev_priv->shared_dplls[i];
f354d733 4204 kfree(pll->new_config);
8bd31e67
ACO		 4205 pll->new_config = NULL;
4206 }
4207
4208 return -ENOMEM;
4209}
4210
4211static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4212{
4213 struct intel_shared_dpll *pll;
4214 enum intel_dpll_id i;
4215
4216 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4217 pll = &dev_priv->shared_dplls[i];
4218
4219 WARN_ON(pll->new_config == &pll->config);
4220
4221 pll->config = *pll->new_config;
4222 kfree(pll->new_config);
4223 pll->new_config = NULL;
4224 }
4225}
4226
4227static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4228{
4229 struct intel_shared_dpll *pll;
4230 enum intel_dpll_id i;
4231
4232 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4233 pll = &dev_priv->shared_dplls[i];
4234
4235 WARN_ON(pll->new_config == &pll->config);
4236
4237 kfree(pll->new_config);
4238 pll->new_config = NULL;
4239 }
4240}
4241
a1520318 4242static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4243{
4244 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4245 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4246 u32 temp;
4247
4248 temp = I915_READ(dslreg);
4249 udelay(500);
4250 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4251 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4252 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4253 }
4254}
4255
bd2e244f
JB		 4256static void skylake_pfit_enable(struct intel_crtc *crtc)
4257{
4258 struct drm_device *dev = crtc->base.dev;
4259 struct drm_i915_private *dev_priv = dev->dev_private;
4260 int pipe = crtc->pipe;
4261
6e3c9717 4262 if (crtc->config->pch_pfit.enabled) {
bd2e244f 4263 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
6e3c9717
ACO		 4264 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4265 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
bd2e244f
JB		 4266 }
4267}
4268
b074cec8
JB		 4269static void ironlake_pfit_enable(struct intel_crtc *crtc)
4270{
4271 struct drm_device *dev = crtc->base.dev;
4272 struct drm_i915_private *dev_priv = dev->dev_private;
4273 int pipe = crtc->pipe;
4274
6e3c9717 4275 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4276 /* Force use of hard-coded filter coefficients
4277 * as some pre-programmed values are broken,
4278 * e.g. x201.
4279 */
4280 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4281 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4282 PF_PIPE_SEL_IVB(pipe));
4283 else
4284 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4285 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4286 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4287 }
4288}
4289
4a3b8769 4290static void intel_enable_sprite_planes(struct drm_crtc *crtc)
bb53d4ae
VS		 4291{
4292 struct drm_device *dev = crtc->dev;
4293 enum pipe pipe = to_intel_crtc(crtc)->pipe;
af2b653b 4294 struct drm_plane *plane;
bb53d4ae
VS		 4295 struct intel_plane *intel_plane;
4296
af2b653b
MR		 4297 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4298 intel_plane = to_intel_plane(plane);
bb53d4ae
VS		 4299 if (intel_plane->pipe == pipe)
4300 intel_plane_restore(&intel_plane->base);
af2b653b 4301 }
bb53d4ae
VS		 4302}
4303
0d703d4e
MR		 4304/*
4305 * Disable a plane internally without actually modifying the plane's state.
4306 * This will allow us to easily restore the plane later by just reprogramming
4307 * its state.
4308 */
4309static void disable_plane_internal(struct drm_plane *plane)
4310{
4311 struct intel_plane *intel_plane = to_intel_plane(plane);
4312 struct drm_plane_state *state =
4313 plane->funcs->atomic_duplicate_state(plane);
4314 struct intel_plane_state *intel_state = to_intel_plane_state(state);
4315
4316 intel_state->visible = false;
4317 intel_plane->commit_plane(plane, intel_state);
4318
4319 intel_plane_destroy_state(plane, state);
4320}
4321
4a3b8769 4322static void intel_disable_sprite_planes(struct drm_crtc *crtc)
bb53d4ae
VS		 4323{
4324 struct drm_device *dev = crtc->dev;
4325 enum pipe pipe = to_intel_crtc(crtc)->pipe;
af2b653b 4326 struct drm_plane *plane;
bb53d4ae
VS		 4327 struct intel_plane *intel_plane;
4328
af2b653b
MR		 4329 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4330 intel_plane = to_intel_plane(plane);
0d703d4e
MR		 4331 if (plane->fb && intel_plane->pipe == pipe)
4332 disable_plane_internal(plane);
af2b653b 4333 }
bb53d4ae
VS		 4334}
4335
20bc8673 4336void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4337{
cea165c3
VS		 4338 struct drm_device *dev = crtc->base.dev;
4339 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4340
6e3c9717 4341 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4342 return;
4343
cea165c3
VS		 4344 /* We can only enable IPS after we enable a plane and wait for a vblank */
4345 intel_wait_for_vblank(dev, crtc->pipe);
4346
d77e4531 4347 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4348 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4349 mutex_lock(&dev_priv->rps.hw_lock);
4350 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4351 mutex_unlock(&dev_priv->rps.hw_lock);
4352 /* Quoting Art Runyan: "its not safe to expect any particular
4353 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4354 * mailbox." Moreover, the mailbox may return a bogus state,
4355 * so we need to just enable it and continue on.
2a114cc1
BW		 4356 */
4357 } else {
4358 I915_WRITE(IPS_CTL, IPS_ENABLE);
4359 /* The bit only becomes 1 in the next vblank, so this wait here
4360 * is essentially intel_wait_for_vblank. If we don't have this
4361 * and don't wait for vblanks until the end of crtc_enable, then
4362 * the HW state readout code will complain that the expected
4363 * IPS_CTL value is not the one we read. */
4364 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4365 DRM_ERROR("Timed out waiting for IPS enable\n");
4366 }
d77e4531
PZ		 4367}
4368
20bc8673 4369void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4370{
4371 struct drm_device *dev = crtc->base.dev;
4372 struct drm_i915_private *dev_priv = dev->dev_private;
4373
6e3c9717 4374 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4375 return;
4376
4377 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4378 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4379 mutex_lock(&dev_priv->rps.hw_lock);
4380 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4381 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4382 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4383 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4384 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4385 } else {
2a114cc1 4386 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4387 POSTING_READ(IPS_CTL);
4388 }
d77e4531
PZ		 4389
4390 /* We need to wait for a vblank before we can disable the plane. */
4391 intel_wait_for_vblank(dev, crtc->pipe);
4392}
4393
4394/** Loads the palette/gamma unit for the CRTC with the prepared values */
4395static void intel_crtc_load_lut(struct drm_crtc *crtc)
4396{
4397 struct drm_device *dev = crtc->dev;
4398 struct drm_i915_private *dev_priv = dev->dev_private;
4399 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4400 enum pipe pipe = intel_crtc->pipe;
4401 int palreg = PALETTE(pipe);
4402 int i;
4403 bool reenable_ips = false;
4404
4405 /* The clocks have to be on to load the palette. */
83d65738 4406 if (!crtc->state->enable || !intel_crtc->active)
d77e4531
PZ		 4407 return;
4408
4409 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
409ee761 4410 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4411 assert_dsi_pll_enabled(dev_priv);
4412 else
4413 assert_pll_enabled(dev_priv, pipe);
4414 }
4415
4416 /* use legacy palette for Ironlake */
7a1db49a 4417 if (!HAS_GMCH_DISPLAY(dev))
d77e4531
PZ		 4418 palreg = LGC_PALETTE(pipe);
4419
4420 /* Workaround : Do not read or write the pipe palette/gamma data while
4421 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4422 */
6e3c9717 4423 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4424 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4425 GAMMA_MODE_MODE_SPLIT)) {
4426 hsw_disable_ips(intel_crtc);
4427 reenable_ips = true;
4428 }
4429
4430 for (i = 0; i < 256; i++) {
4431 I915_WRITE(palreg + 4 * i,
4432 (intel_crtc->lut_r[i] << 16) |
4433 (intel_crtc->lut_g[i] << 8) |
4434 intel_crtc->lut_b[i]);
4435 }
4436
4437 if (reenable_ips)
4438 hsw_enable_ips(intel_crtc);
4439}
4440
d3eedb1a
VS		 4441static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4442{
4443 if (!enable && intel_crtc->overlay) {
4444 struct drm_device *dev = intel_crtc->base.dev;
4445 struct drm_i915_private *dev_priv = dev->dev_private;
4446
4447 mutex_lock(&dev->struct_mutex);
4448 dev_priv->mm.interruptible = false;
4449 (void) intel_overlay_switch_off(intel_crtc->overlay);
4450 dev_priv->mm.interruptible = true;
4451 mutex_unlock(&dev->struct_mutex);
4452 }
4453
4454 /* Let userspace switch the overlay on again. In most cases userspace
4455 * has to recompute where to put it anyway.
4456 */
4457}
4458
d3eedb1a 4459static void intel_crtc_enable_planes(struct drm_crtc *crtc)
a5c4d7bc
VS		 4460{
4461 struct drm_device *dev = crtc->dev;
a5c4d7bc
VS		 4462 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4463 int pipe = intel_crtc->pipe;
a5c4d7bc 4464
fdd508a6 4465 intel_enable_primary_hw_plane(crtc->primary, crtc);
4a3b8769 4466 intel_enable_sprite_planes(crtc);
a5c4d7bc 4467 intel_crtc_update_cursor(crtc, true);
d3eedb1a 4468 intel_crtc_dpms_overlay(intel_crtc, true);
a5c4d7bc
VS		 4469
4470 hsw_enable_ips(intel_crtc);
4471
4472 mutex_lock(&dev->struct_mutex);
7ff0ebcc 4473 intel_fbc_update(dev);
a5c4d7bc 4474 mutex_unlock(&dev->struct_mutex);
f99d7069
DV		 4475
4476 /*
4477 * FIXME: Once we grow proper nuclear flip support out of this we need
4478 * to compute the mask of flip planes precisely. For the time being
4479 * consider this a flip from a NULL plane.
4480 */
4481 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4482}
4483
d3eedb1a 4484static void intel_crtc_disable_planes(struct drm_crtc *crtc)
a5c4d7bc
VS		 4485{
4486 struct drm_device *dev = crtc->dev;
4487 struct drm_i915_private *dev_priv = dev->dev_private;
4488 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4489 int pipe = intel_crtc->pipe;
a5c4d7bc
VS		 4490
4491 intel_crtc_wait_for_pending_flips(crtc);
a5c4d7bc 4492
e35fef21 4493 if (dev_priv->fbc.crtc == intel_crtc)
7ff0ebcc 4494 intel_fbc_disable(dev);
a5c4d7bc
VS		 4495
4496 hsw_disable_ips(intel_crtc);
4497
d3eedb1a 4498 intel_crtc_dpms_overlay(intel_crtc, false);
a5c4d7bc 4499 intel_crtc_update_cursor(crtc, false);
4a3b8769 4500 intel_disable_sprite_planes(crtc);
fdd508a6 4501 intel_disable_primary_hw_plane(crtc->primary, crtc);
f98551ae 4502
f99d7069
DV		 4503 /*
4504 * FIXME: Once we grow proper nuclear flip support out of this we need
4505 * to compute the mask of flip planes precisely. For the time being
4506 * consider this a flip to a NULL plane.
4507 */
4508 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4509}
4510
f67a559d
JB		 4511static void ironlake_crtc_enable(struct drm_crtc *crtc)
4512{
4513 struct drm_device *dev = crtc->dev;
4514 struct drm_i915_private *dev_priv = dev->dev_private;
4515 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4516 struct intel_encoder *encoder;
f67a559d 4517 int pipe = intel_crtc->pipe;
f67a559d 4518
83d65738 4519 WARN_ON(!crtc->state->enable);
08a48469 4520
f67a559d
JB		 4521 if (intel_crtc->active)
4522 return;
4523
6e3c9717 4524 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4525 intel_prepare_shared_dpll(intel_crtc);
4526
6e3c9717 4527 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4528 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4529
4530 intel_set_pipe_timings(intel_crtc);
4531
6e3c9717 4532 if (intel_crtc->config->has_pch_encoder) {
29407aab 4533 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4534 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4535 }
4536
4537 ironlake_set_pipeconf(crtc);
4538
f67a559d 4539 intel_crtc->active = true;
8664281b 4540
a72e4c9f
DV		 4541 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4542 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4543
f6736a1a 4544 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4545 if (encoder->pre_enable)
4546 encoder->pre_enable(encoder);
f67a559d 4547
6e3c9717 4548 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4549 /* Note: FDI PLL enabling _must_ be done before we enable the
4550 * cpu pipes, hence this is separate from all the other fdi/pch
4551 * enabling. */
88cefb6c 4552 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4553 } else {
4554 assert_fdi_tx_disabled(dev_priv, pipe);
4555 assert_fdi_rx_disabled(dev_priv, pipe);
4556 }
f67a559d 4557
b074cec8 4558 ironlake_pfit_enable(intel_crtc);
f67a559d 4559
9c54c0dd
JB		 4560 /*
4561 * On ILK+ LUT must be loaded before the pipe is running but with
4562 * clocks enabled
4563 */
4564 intel_crtc_load_lut(crtc);
4565
f37fcc2a 4566 intel_update_watermarks(crtc);
e1fdc473 4567 intel_enable_pipe(intel_crtc);
f67a559d 4568
6e3c9717 4569 if (intel_crtc->config->has_pch_encoder)
f67a559d 4570 ironlake_pch_enable(crtc);
c98e9dcf 4571
f9b61ff6
DV		 4572 assert_vblank_disabled(crtc);
4573 drm_crtc_vblank_on(crtc);
4574
fa5c73b1
DV		 4575 for_each_encoder_on_crtc(dev, crtc, encoder)
4576 encoder->enable(encoder);
61b77ddd
DV		 4577
4578 if (HAS_PCH_CPT(dev))
a1520318 4579 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100 4580
d3eedb1a 4581 intel_crtc_enable_planes(crtc);
6be4a607
JB		 4582}
4583
42db64ef
PZ		 4584/* IPS only exists on ULT machines and is tied to pipe A. */
4585static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4586{
f5adf94e 4587 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4588}
4589
e4916946
PZ		 4590/*
4591 * This implements the workaround described in the "notes" section of the mode
4592 * set sequence documentation. When going from no pipes or single pipe to
4593 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4594 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4595 */
4596static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4597{
4598 struct drm_device *dev = crtc->base.dev;
4599 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4600
4601 /* We want to get the other_active_crtc only if there's only 1 other
4602 * active crtc. */
d3fcc808 4603 for_each_intel_crtc(dev, crtc_it) {
e4916946
PZ		 4604 if (!crtc_it->active || crtc_it == crtc)
4605 continue;
4606
4607 if (other_active_crtc)
4608 return;
4609
4610 other_active_crtc = crtc_it;
4611 }
4612 if (!other_active_crtc)
4613 return;
4614
4615 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4616 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4617}
4618
4f771f10
PZ		 4619static void haswell_crtc_enable(struct drm_crtc *crtc)
4620{
4621 struct drm_device *dev = crtc->dev;
4622 struct drm_i915_private *dev_priv = dev->dev_private;
4623 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4624 struct intel_encoder *encoder;
4625 int pipe = intel_crtc->pipe;
4f771f10 4626
83d65738 4627 WARN_ON(!crtc->state->enable);
4f771f10
PZ		 4628
4629 if (intel_crtc->active)
4630 return;
4631
df8ad70c
DV		 4632 if (intel_crtc_to_shared_dpll(intel_crtc))
4633 intel_enable_shared_dpll(intel_crtc);
4634
6e3c9717 4635 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4636 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 4637
4638 intel_set_pipe_timings(intel_crtc);
4639
6e3c9717
ACO		 4640 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4641 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4642 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 4643 }
4644
6e3c9717 4645 if (intel_crtc->config->has_pch_encoder) {
229fca97 4646 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4647 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 4648 }
4649
4650 haswell_set_pipeconf(crtc);
4651
4652 intel_set_pipe_csc(crtc);
4653
4f771f10 4654 intel_crtc->active = true;
8664281b 4655
a72e4c9f 4656 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ		 4657 for_each_encoder_on_crtc(dev, crtc, encoder)
4658 if (encoder->pre_enable)
4659 encoder->pre_enable(encoder);
4660
6e3c9717 4661 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 4662 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4663 true);
4fe9467d
ID		 4664 dev_priv->display.fdi_link_train(crtc);
4665 }
4666
1f544388 4667 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 4668
bd2e244f
JB		 4669 if (IS_SKYLAKE(dev))
4670 skylake_pfit_enable(intel_crtc);
4671 else
4672 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 4673
4674 /*
4675 * On ILK+ LUT must be loaded before the pipe is running but with
4676 * clocks enabled
4677 */
4678 intel_crtc_load_lut(crtc);
4679
1f544388 4680 intel_ddi_set_pipe_settings(crtc);
8228c251 4681 intel_ddi_enable_transcoder_func(crtc);
4f771f10 4682
f37fcc2a 4683 intel_update_watermarks(crtc);
e1fdc473 4684 intel_enable_pipe(intel_crtc);
42db64ef 4685
6e3c9717 4686 if (intel_crtc->config->has_pch_encoder)
1507e5bd 4687 lpt_pch_enable(crtc);
4f771f10 4688
6e3c9717 4689 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA		 4690 intel_ddi_set_vc_payload_alloc(crtc, true);
4691
f9b61ff6
DV		 4692 assert_vblank_disabled(crtc);
4693 drm_crtc_vblank_on(crtc);
4694
8807e55b 4695 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 4696 encoder->enable(encoder);
8807e55b
JN		 4697 intel_opregion_notify_encoder(encoder, true);
4698 }
4f771f10 4699
e4916946
PZ		 4700 /* If we change the relative order between pipe/planes enabling, we need
4701 * to change the workaround. */
4702 haswell_mode_set_planes_workaround(intel_crtc);
d3eedb1a 4703 intel_crtc_enable_planes(crtc);
4f771f10
PZ		 4704}
4705
bd2e244f
JB		 4706static void skylake_pfit_disable(struct intel_crtc *crtc)
4707{
4708 struct drm_device *dev = crtc->base.dev;
4709 struct drm_i915_private *dev_priv = dev->dev_private;
4710 int pipe = crtc->pipe;
4711
4712 /* To avoid upsetting the power well on haswell only disable the pfit if
4713 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 4714 if (crtc->config->pch_pfit.enabled) {
bd2e244f
JB		 4715 I915_WRITE(PS_CTL(pipe), 0);
4716 I915_WRITE(PS_WIN_POS(pipe), 0);
4717 I915_WRITE(PS_WIN_SZ(pipe), 0);
4718 }
4719}
4720
3f8dce3a
DV		 4721static void ironlake_pfit_disable(struct intel_crtc *crtc)
4722{
4723 struct drm_device *dev = crtc->base.dev;
4724 struct drm_i915_private *dev_priv = dev->dev_private;
4725 int pipe = crtc->pipe;
4726
4727 /* To avoid upsetting the power well on haswell only disable the pfit if
4728 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 4729 if (crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 4730 I915_WRITE(PF_CTL(pipe), 0);
4731 I915_WRITE(PF_WIN_POS(pipe), 0);
4732 I915_WRITE(PF_WIN_SZ(pipe), 0);
4733 }
4734}
4735
6be4a607
JB		 4736static void ironlake_crtc_disable(struct drm_crtc *crtc)
4737{
4738 struct drm_device *dev = crtc->dev;
4739 struct drm_i915_private *dev_priv = dev->dev_private;
4740 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4741 struct intel_encoder *encoder;
6be4a607 4742 int pipe = intel_crtc->pipe;
5eddb70b 4743 u32 reg, temp;
b52eb4dc 4744
f7abfe8b
CW		 4745 if (!intel_crtc->active)
4746 return;
4747
d3eedb1a 4748 intel_crtc_disable_planes(crtc);
a5c4d7bc 4749
ea9d758d
DV		 4750 for_each_encoder_on_crtc(dev, crtc, encoder)
4751 encoder->disable(encoder);
4752
f9b61ff6
DV		 4753 drm_crtc_vblank_off(crtc);
4754 assert_vblank_disabled(crtc);
4755
6e3c9717 4756 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 4757 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 4758
575f7ab7 4759 intel_disable_pipe(intel_crtc);
32f9d658 4760
3f8dce3a 4761 ironlake_pfit_disable(intel_crtc);
2c07245f 4762
bf49ec8c
DV		 4763 for_each_encoder_on_crtc(dev, crtc, encoder)
4764 if (encoder->post_disable)
4765 encoder->post_disable(encoder);
2c07245f 4766
6e3c9717 4767 if (intel_crtc->config->has_pch_encoder) {
d925c59a 4768 ironlake_fdi_disable(crtc);
913d8d11 4769
d925c59a 4770 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 4771
d925c59a
DV		 4772 if (HAS_PCH_CPT(dev)) {
4773 /* disable TRANS_DP_CTL */
4774 reg = TRANS_DP_CTL(pipe);
4775 temp = I915_READ(reg);
4776 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4777 TRANS_DP_PORT_SEL_MASK);
4778 temp |= TRANS_DP_PORT_SEL_NONE;
4779 I915_WRITE(reg, temp);
4780
4781 /* disable DPLL_SEL */
4782 temp = I915_READ(PCH_DPLL_SEL);
11887397 4783 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 4784 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 4785 }
e3421a18 4786
d925c59a 4787 /* disable PCH DPLL */
e72f9fbf 4788 intel_disable_shared_dpll(intel_crtc);
8db9d77b 4789
d925c59a
DV		 4790 ironlake_fdi_pll_disable(intel_crtc);
4791 }
6b383a7f 4792
f7abfe8b 4793 intel_crtc->active = false;
46ba614c 4794 intel_update_watermarks(crtc);
d1ebd816
BW		 4795
4796 mutex_lock(&dev->struct_mutex);
7ff0ebcc 4797 intel_fbc_update(dev);
d1ebd816 4798 mutex_unlock(&dev->struct_mutex);
6be4a607 4799}
1b3c7a47 4800
4f771f10 4801static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 4802{
4f771f10
PZ		 4803 struct drm_device *dev = crtc->dev;
4804 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 4805 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 4806 struct intel_encoder *encoder;
6e3c9717 4807 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 4808
4f771f10
PZ		 4809 if (!intel_crtc->active)
4810 return;
4811
d3eedb1a 4812 intel_crtc_disable_planes(crtc);
dda9a66a 4813
8807e55b
JN		 4814 for_each_encoder_on_crtc(dev, crtc, encoder) {
4815 intel_opregion_notify_encoder(encoder, false);
4f771f10 4816 encoder->disable(encoder);
8807e55b 4817 }
4f771f10 4818
f9b61ff6
DV		 4819 drm_crtc_vblank_off(crtc);
4820 assert_vblank_disabled(crtc);
4821
6e3c9717 4822 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 4823 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4824 false);
575f7ab7 4825 intel_disable_pipe(intel_crtc);
4f771f10 4826
6e3c9717 4827 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 4828 intel_ddi_set_vc_payload_alloc(crtc, false);
4829
ad80a810 4830 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 4831
bd2e244f
JB		 4832 if (IS_SKYLAKE(dev))
4833 skylake_pfit_disable(intel_crtc);
4834 else
4835 ironlake_pfit_disable(intel_crtc);
4f771f10 4836
1f544388 4837 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 4838
6e3c9717 4839 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 4840 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 4841 intel_ddi_fdi_disable(crtc);
83616634 4842 }
4f771f10 4843
97b040aa
ID		 4844 for_each_encoder_on_crtc(dev, crtc, encoder)
4845 if (encoder->post_disable)
4846 encoder->post_disable(encoder);
4847
4f771f10 4848 intel_crtc->active = false;
46ba614c 4849 intel_update_watermarks(crtc);
4f771f10
PZ		 4850
4851 mutex_lock(&dev->struct_mutex);
7ff0ebcc 4852 intel_fbc_update(dev);
4f771f10 4853 mutex_unlock(&dev->struct_mutex);
df8ad70c
DV		 4854
4855 if (intel_crtc_to_shared_dpll(intel_crtc))
4856 intel_disable_shared_dpll(intel_crtc);
4f771f10
PZ		 4857}
4858
ee7b9f93
JB		 4859static void ironlake_crtc_off(struct drm_crtc *crtc)
4860{
4861 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 4862 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 4863}
4864
6441ab5f 4865
2dd24552
JB		 4866static void i9xx_pfit_enable(struct intel_crtc *crtc)
4867{
4868 struct drm_device *dev = crtc->base.dev;
4869 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 4870 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 4871
681a8504 4872 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 4873 return;
4874
2dd24552 4875 /*
c0b03411
DV		 4876 * The panel fitter should only be adjusted whilst the pipe is disabled,
4877 * according to register description and PRM.
2dd24552 4878 */
c0b03411
DV		 4879 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4880 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 4881
b074cec8
JB		 4882 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4883 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 4884
4885 /* Border color in case we don't scale up to the full screen. Black by
4886 * default, change to something else for debugging. */
4887 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 4888}
4889
d05410f9
DA		 4890static enum intel_display_power_domain port_to_power_domain(enum port port)
4891{
4892 switch (port) {
4893 case PORT_A:
4894 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4895 case PORT_B:
4896 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4897 case PORT_C:
4898 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4899 case PORT_D:
4900 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4901 default:
4902 WARN_ON_ONCE(1);
4903 return POWER_DOMAIN_PORT_OTHER;
4904 }
4905}
4906
77d22dca
ID		 4907#define for_each_power_domain(domain, mask) \
4908 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4909 if ((1 << (domain)) & (mask))
4910
319be8ae
ID		 4911enum intel_display_power_domain
4912intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4913{
4914 struct drm_device *dev = intel_encoder->base.dev;
4915 struct intel_digital_port *intel_dig_port;
4916
4917 switch (intel_encoder->type) {
4918 case INTEL_OUTPUT_UNKNOWN:
4919 /* Only DDI platforms should ever use this output type */
4920 WARN_ON_ONCE(!HAS_DDI(dev));
4921 case INTEL_OUTPUT_DISPLAYPORT:
4922 case INTEL_OUTPUT_HDMI:
4923 case INTEL_OUTPUT_EDP:
4924 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 4925 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 4926 case INTEL_OUTPUT_DP_MST:
4927 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4928 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 4929 case INTEL_OUTPUT_ANALOG:
4930 return POWER_DOMAIN_PORT_CRT;
4931 case INTEL_OUTPUT_DSI:
4932 return POWER_DOMAIN_PORT_DSI;
4933 default:
4934 return POWER_DOMAIN_PORT_OTHER;
4935 }
4936}
4937
4938static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 4939{
319be8ae
ID		 4940 struct drm_device *dev = crtc->dev;
4941 struct intel_encoder *intel_encoder;
4942 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4943 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 4944 unsigned long mask;
4945 enum transcoder transcoder;
4946
4947 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4948
4949 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4950 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 4951 if (intel_crtc->config->pch_pfit.enabled ||
4952 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 4953 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4954
319be8ae
ID		 4955 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4956 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4957
77d22dca
ID		 4958 return mask;
4959}
4960
679dacd4 4961static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
77d22dca 4962{
679dacd4 4963 struct drm_device *dev = state->dev;
77d22dca
ID		 4964 struct drm_i915_private *dev_priv = dev->dev_private;
4965 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4966 struct intel_crtc *crtc;
4967
4968 /*
4969 * First get all needed power domains, then put all unneeded, to avoid
4970 * any unnecessary toggling of the power wells.
4971 */
d3fcc808 4972 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 4973 enum intel_display_power_domain domain;
4974
83d65738 4975 if (!crtc->base.state->enable)
77d22dca
ID		 4976 continue;
4977
319be8ae 4978 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
77d22dca
ID		 4979
4980 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4981 intel_display_power_get(dev_priv, domain);
4982 }
4983
50f6e502 4984 if (dev_priv->display.modeset_global_resources)
679dacd4 4985 dev_priv->display.modeset_global_resources(state);
50f6e502 4986
d3fcc808 4987 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 4988 enum intel_display_power_domain domain;
4989
4990 for_each_power_domain(domain, crtc->enabled_power_domains)
4991 intel_display_power_put(dev_priv, domain);
4992
4993 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4994 }
4995
4996 intel_display_set_init_power(dev_priv, false);
4997}
4998
dfcab17e 4999/* returns HPLL frequency in kHz */
f8bf63fd 5000static int valleyview_get_vco(struct drm_i915_private *dev_priv)
30a970c6 5001{
586f49dc 5002 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
30a970c6 5003
586f49dc
JB		 5004 /* Obtain SKU information */
5005 mutex_lock(&dev_priv->dpio_lock);
5006 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5007 CCK_FUSE_HPLL_FREQ_MASK;
5008 mutex_unlock(&dev_priv->dpio_lock);
30a970c6 5009
dfcab17e 5010 return vco_freq[hpll_freq] * 1000;
30a970c6
JB		 5011}
5012
f8bf63fd
VS		 5013static void vlv_update_cdclk(struct drm_device *dev)
5014{
5015 struct drm_i915_private *dev_priv = dev->dev_private;
5016
5017 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
43dc52c3 5018 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
f8bf63fd
VS		 5019 dev_priv->vlv_cdclk_freq);
5020
5021 /*
5022 * Program the gmbus_freq based on the cdclk frequency.
5023 * BSpec erroneously claims we should aim for 4MHz, but
5024 * in fact 1MHz is the correct frequency.
5025 */
6be1e3d3 5026 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
f8bf63fd
VS		 5027}
5028
30a970c6
JB		 5029/* Adjust CDclk dividers to allow high res or save power if possible */
5030static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5031{
5032 struct drm_i915_private *dev_priv = dev->dev_private;
5033 u32 val, cmd;
5034
d197b7d3 5035 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
d60c4473 5036
dfcab17e 5037 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5038 cmd = 2;
dfcab17e 5039 else if (cdclk == 266667)
30a970c6
JB		 5040 cmd = 1;
5041 else
5042 cmd = 0;
5043
5044 mutex_lock(&dev_priv->rps.hw_lock);
5045 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5046 val &= ~DSPFREQGUAR_MASK;
5047 val |= (cmd << DSPFREQGUAR_SHIFT);
5048 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5049 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5050 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5051 50)) {
5052 DRM_ERROR("timed out waiting for CDclk change\n");
5053 }
5054 mutex_unlock(&dev_priv->rps.hw_lock);
5055
dfcab17e 5056 if (cdclk == 400000) {
6bcda4f0 5057 u32 divider;
30a970c6 5058
6bcda4f0 5059 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6
JB		 5060
5061 mutex_lock(&dev_priv->dpio_lock);
5062 /* adjust cdclk divider */
5063 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
9cf33db5 5064 val &= ~DISPLAY_FREQUENCY_VALUES;
30a970c6
JB		 5065 val |= divider;
5066 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5067
5068 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5069 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5070 50))
5071 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5072 mutex_unlock(&dev_priv->dpio_lock);
5073 }
5074
5075 mutex_lock(&dev_priv->dpio_lock);
5076 /* adjust self-refresh exit latency value */
5077 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5078 val &= ~0x7f;
5079
5080 /*
5081 * For high bandwidth configs, we set a higher latency in the bunit
5082 * so that the core display fetch happens in time to avoid underruns.
5083 */
dfcab17e 5084 if (cdclk == 400000)
30a970c6
JB		 5085 val |= 4500 / 250; /* 4.5 usec */
5086 else
5087 val |= 3000 / 250; /* 3.0 usec */
5088 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5089 mutex_unlock(&dev_priv->dpio_lock);
5090
f8bf63fd 5091 vlv_update_cdclk(dev);
30a970c6
JB		 5092}
5093
383c5a6a
VS		 5094static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5095{
5096 struct drm_i915_private *dev_priv = dev->dev_private;
5097 u32 val, cmd;
5098
5099 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
5100
5101 switch (cdclk) {
383c5a6a
VS		 5102 case 333333:
5103 case 320000:
383c5a6a 5104 case 266667:
383c5a6a 5105 case 200000:
383c5a6a
VS		 5106 break;
5107 default:
5f77eeb0 5108 MISSING_CASE(cdclk);
383c5a6a
VS		 5109 return;
5110 }
5111
9d0d3fda
VS		 5112 /*
5113 * Specs are full of misinformation, but testing on actual
5114 * hardware has shown that we just need to write the desired
5115 * CCK divider into the Punit register.
5116 */
5117 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5118
383c5a6a
VS		 5119 mutex_lock(&dev_priv->rps.hw_lock);
5120 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5121 val &= ~DSPFREQGUAR_MASK_CHV;
5122 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5123 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5124 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5125 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5126 50)) {
5127 DRM_ERROR("timed out waiting for CDclk change\n");
5128 }
5129 mutex_unlock(&dev_priv->rps.hw_lock);
5130
5131 vlv_update_cdclk(dev);
5132}
5133
30a970c6
JB		 5134static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5135 int max_pixclk)
5136{
6bcda4f0 5137 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5138 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5139
30a970c6
JB		 5140 /*
5141 * Really only a few cases to deal with, as only 4 CDclks are supported:
5142 * 200MHz
5143 * 267MHz
29dc7ef3 5144 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5145 * 400MHz (VLV only)
5146 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5147 * of the lower bin and adjust if needed.
e37c67a1
VS		 5148 *
5149 * We seem to get an unstable or solid color picture at 200MHz.
5150 * Not sure what's wrong. For now use 200MHz only when all pipes
5151 * are off.
30a970c6 5152 */
6cca3195
VS		 5153 if (!IS_CHERRYVIEW(dev_priv) &&
5154 max_pixclk > freq_320*limit/100)
dfcab17e 5155 return 400000;
6cca3195 5156 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5157 return freq_320;
e37c67a1 5158 else if (max_pixclk > 0)
dfcab17e 5159 return 266667;
e37c67a1
VS		 5160 else
5161 return 200000;
30a970c6
JB		 5162}
5163
2f2d7aa1
VS		 5164/* compute the max pixel clock for new configuration */
5165static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
30a970c6
JB		 5166{
5167 struct drm_device *dev = dev_priv->dev;
5168 struct intel_crtc *intel_crtc;
5169 int max_pixclk = 0;
5170
d3fcc808 5171 for_each_intel_crtc(dev, intel_crtc) {
2f2d7aa1 5172 if (intel_crtc->new_enabled)
30a970c6 5173 max_pixclk = max(max_pixclk,
2d112de7 5174 intel_crtc->new_config->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5175 }
5176
5177 return max_pixclk;
5178}
5179
5180static void valleyview_modeset_global_pipes(struct drm_device *dev,
2f2d7aa1 5181 unsigned *prepare_pipes)
30a970c6
JB		 5182{
5183 struct drm_i915_private *dev_priv = dev->dev_private;
5184 struct intel_crtc *intel_crtc;
2f2d7aa1 5185 int max_pixclk = intel_mode_max_pixclk(dev_priv);
30a970c6 5186
d60c4473
ID		 5187 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
5188 dev_priv->vlv_cdclk_freq)
30a970c6
JB		 5189 return;
5190
2f2d7aa1 5191 /* disable/enable all currently active pipes while we change cdclk */
d3fcc808 5192 for_each_intel_crtc(dev, intel_crtc)
83d65738 5193 if (intel_crtc->base.state->enable)
30a970c6
JB		 5194 *prepare_pipes |= (1 << intel_crtc->pipe);
5195}
5196
1e69cd74
VS		 5197static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5198{
5199 unsigned int credits, default_credits;
5200
5201 if (IS_CHERRYVIEW(dev_priv))
5202 default_credits = PFI_CREDIT(12);
5203 else
5204 default_credits = PFI_CREDIT(8);
5205
5206 if (DIV_ROUND_CLOSEST(dev_priv->vlv_cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5207 /* CHV suggested value is 31 or 63 */
5208 if (IS_CHERRYVIEW(dev_priv))
5209 credits = PFI_CREDIT_31;
5210 else
5211 credits = PFI_CREDIT(15);
5212 } else {
5213 credits = default_credits;
5214 }
5215
5216 /*
5217 * WA - write default credits before re-programming
5218 * FIXME: should we also set the resend bit here?
5219 */
5220 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5221 default_credits);
5222
5223 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5224 credits | PFI_CREDIT_RESEND);
5225
5226 /*
5227 * FIXME is this guaranteed to clear
5228 * immediately or should we poll for it?
5229 */
5230 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5231}
5232
679dacd4 5233static void valleyview_modeset_global_resources(struct drm_atomic_state *state)
30a970c6 5234{
679dacd4 5235 struct drm_device *dev = state->dev;
30a970c6 5236 struct drm_i915_private *dev_priv = dev->dev_private;
2f2d7aa1 5237 int max_pixclk = intel_mode_max_pixclk(dev_priv);
30a970c6
JB		 5238 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5239
383c5a6a 5240 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
738c05c0
ID		 5241 /*
5242 * FIXME: We can end up here with all power domains off, yet
5243 * with a CDCLK frequency other than the minimum. To account
5244 * for this take the PIPE-A power domain, which covers the HW
5245 * blocks needed for the following programming. This can be
5246 * removed once it's guaranteed that we get here either with
5247 * the minimum CDCLK set, or the required power domains
5248 * enabled.
5249 */
5250 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5251
383c5a6a
VS		 5252 if (IS_CHERRYVIEW(dev))
5253 cherryview_set_cdclk(dev, req_cdclk);
5254 else
5255 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 5256
1e69cd74
VS		 5257 vlv_program_pfi_credits(dev_priv);
5258
738c05c0 5259 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
383c5a6a 5260 }
30a970c6
JB		 5261}
5262
89b667f8
JB		 5263static void valleyview_crtc_enable(struct drm_crtc *crtc)
5264{
5265 struct drm_device *dev = crtc->dev;
a72e4c9f 5266 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 5267 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5268 struct intel_encoder *encoder;
5269 int pipe = intel_crtc->pipe;
23538ef1 5270 bool is_dsi;
89b667f8 5271
83d65738 5272 WARN_ON(!crtc->state->enable);
89b667f8
JB		 5273
5274 if (intel_crtc->active)
5275 return;
5276
409ee761 5277 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 5278
1ae0d137
VS		 5279 if (!is_dsi) {
5280 if (IS_CHERRYVIEW(dev))
6e3c9717 5281 chv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 5282 else
6e3c9717 5283 vlv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 5284 }
5b18e57c 5285
6e3c9717 5286 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5287 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 5288
5289 intel_set_pipe_timings(intel_crtc);
5290
c14b0485
VS		 5291 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5292 struct drm_i915_private *dev_priv = dev->dev_private;
5293
5294 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5295 I915_WRITE(CHV_CANVAS(pipe), 0);
5296 }
5297
5b18e57c
DV		 5298 i9xx_set_pipeconf(intel_crtc);
5299
89b667f8 5300 intel_crtc->active = true;
89b667f8 5301
a72e4c9f 5302 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5303
89b667f8
JB		 5304 for_each_encoder_on_crtc(dev, crtc, encoder)
5305 if (encoder->pre_pll_enable)
5306 encoder->pre_pll_enable(encoder);
5307
9d556c99
CML		 5308 if (!is_dsi) {
5309 if (IS_CHERRYVIEW(dev))
6e3c9717 5310 chv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 5311 else
6e3c9717 5312 vlv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 5313 }
89b667f8
JB		 5314
5315 for_each_encoder_on_crtc(dev, crtc, encoder)
5316 if (encoder->pre_enable)
5317 encoder->pre_enable(encoder);
5318
2dd24552
JB		 5319 i9xx_pfit_enable(intel_crtc);
5320
63cbb074
VS		 5321 intel_crtc_load_lut(crtc);
5322
f37fcc2a 5323 intel_update_watermarks(crtc);
e1fdc473 5324 intel_enable_pipe(intel_crtc);
be6a6f8e 5325
4b3a9526
VS		 5326 assert_vblank_disabled(crtc);
5327 drm_crtc_vblank_on(crtc);
5328
f9b61ff6
DV		 5329 for_each_encoder_on_crtc(dev, crtc, encoder)
5330 encoder->enable(encoder);
5331
9ab0460b 5332 intel_crtc_enable_planes(crtc);
d40d9187 5333
56b80e1f 5334 /* Underruns don't raise interrupts, so check manually. */
a72e4c9f 5335 i9xx_check_fifo_underruns(dev_priv);
89b667f8
JB		 5336}
5337
f13c2ef3
DV		 5338static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5339{
5340 struct drm_device *dev = crtc->base.dev;
5341 struct drm_i915_private *dev_priv = dev->dev_private;
5342
6e3c9717
ACO		 5343 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5344 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 5345}
5346
0b8765c6 5347static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 5348{
5349 struct drm_device *dev = crtc->dev;
a72e4c9f 5350 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 5351 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5352 struct intel_encoder *encoder;
79e53945 5353 int pipe = intel_crtc->pipe;
79e53945 5354
83d65738 5355 WARN_ON(!crtc->state->enable);
08a48469 5356
f7abfe8b
CW		 5357 if (intel_crtc->active)
5358 return;
5359
f13c2ef3
DV		 5360 i9xx_set_pll_dividers(intel_crtc);
5361
6e3c9717 5362 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5363 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 5364
5365 intel_set_pipe_timings(intel_crtc);
5366
5b18e57c
DV		 5367 i9xx_set_pipeconf(intel_crtc);
5368
f7abfe8b 5369 intel_crtc->active = true;
6b383a7f 5370
4a3436e8 5371 if (!IS_GEN2(dev))
a72e4c9f 5372 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5373
9d6d9f19
MK		 5374 for_each_encoder_on_crtc(dev, crtc, encoder)
5375 if (encoder->pre_enable)
5376 encoder->pre_enable(encoder);
5377
f6736a1a
DV		 5378 i9xx_enable_pll(intel_crtc);
5379
2dd24552
JB		 5380 i9xx_pfit_enable(intel_crtc);
5381
63cbb074
VS		 5382 intel_crtc_load_lut(crtc);
5383
f37fcc2a 5384 intel_update_watermarks(crtc);
e1fdc473 5385 intel_enable_pipe(intel_crtc);
be6a6f8e 5386
4b3a9526
VS		 5387 assert_vblank_disabled(crtc);
5388 drm_crtc_vblank_on(crtc);
5389
f9b61ff6
DV		 5390 for_each_encoder_on_crtc(dev, crtc, encoder)
5391 encoder->enable(encoder);
5392
9ab0460b 5393 intel_crtc_enable_planes(crtc);
d40d9187 5394
4a3436e8
VS		 5395 /*
5396 * Gen2 reports pipe underruns whenever all planes are disabled.
5397 * So don't enable underrun reporting before at least some planes
5398 * are enabled.
5399 * FIXME: Need to fix the logic to work when we turn off all planes
5400 * but leave the pipe running.
5401 */
5402 if (IS_GEN2(dev))
a72e4c9f 5403 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5404
56b80e1f 5405 /* Underruns don't raise interrupts, so check manually. */
a72e4c9f 5406 i9xx_check_fifo_underruns(dev_priv);
0b8765c6 5407}
79e53945 5408
87476d63
DV		 5409static void i9xx_pfit_disable(struct intel_crtc *crtc)
5410{
5411 struct drm_device *dev = crtc->base.dev;
5412 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 5413
6e3c9717 5414 if (!crtc->config->gmch_pfit.control)
328d8e82 5415 return;
87476d63 5416
328d8e82 5417 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 5418
328d8e82
DV		 5419 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5420 I915_READ(PFIT_CONTROL));
5421 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 5422}
5423
0b8765c6
JB		 5424static void i9xx_crtc_disable(struct drm_crtc *crtc)
5425{
5426 struct drm_device *dev = crtc->dev;
5427 struct drm_i915_private *dev_priv = dev->dev_private;
5428 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5429 struct intel_encoder *encoder;
0b8765c6 5430 int pipe = intel_crtc->pipe;
ef9c3aee 5431
f7abfe8b
CW		 5432 if (!intel_crtc->active)
5433 return;
5434
4a3436e8
VS		 5435 /*
5436 * Gen2 reports pipe underruns whenever all planes are disabled.
5437 * So diasble underrun reporting before all the planes get disabled.
5438 * FIXME: Need to fix the logic to work when we turn off all planes
5439 * but leave the pipe running.
5440 */
5441 if (IS_GEN2(dev))
a72e4c9f 5442 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4a3436e8 5443
564ed191
ID		 5444 /*
5445 * Vblank time updates from the shadow to live plane control register
5446 * are blocked if the memory self-refresh mode is active at that
5447 * moment. So to make sure the plane gets truly disabled, disable
5448 * first the self-refresh mode. The self-refresh enable bit in turn
5449 * will be checked/applied by the HW only at the next frame start
5450 * event which is after the vblank start event, so we need to have a
5451 * wait-for-vblank between disabling the plane and the pipe.
5452 */
5453 intel_set_memory_cxsr(dev_priv, false);
9ab0460b
VS		 5454 intel_crtc_disable_planes(crtc);
5455
6304cd91
VS		 5456 /*
5457 * On gen2 planes are double buffered but the pipe isn't, so we must
5458 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 5459 * We also need to wait on all gmch platforms because of the
5460 * self-refresh mode constraint explained above.
6304cd91 5461 */
564ed191 5462 intel_wait_for_vblank(dev, pipe);
6304cd91 5463
4b3a9526
VS		 5464 for_each_encoder_on_crtc(dev, crtc, encoder)
5465 encoder->disable(encoder);
5466
f9b61ff6
DV		 5467 drm_crtc_vblank_off(crtc);
5468 assert_vblank_disabled(crtc);
5469
575f7ab7 5470 intel_disable_pipe(intel_crtc);
24a1f16d 5471
87476d63 5472 i9xx_pfit_disable(intel_crtc);
24a1f16d 5473
89b667f8
JB		 5474 for_each_encoder_on_crtc(dev, crtc, encoder)
5475 if (encoder->post_disable)
5476 encoder->post_disable(encoder);
5477
409ee761 5478 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 5479 if (IS_CHERRYVIEW(dev))
5480 chv_disable_pll(dev_priv, pipe);
5481 else if (IS_VALLEYVIEW(dev))
5482 vlv_disable_pll(dev_priv, pipe);
5483 else
1c4e0274 5484 i9xx_disable_pll(intel_crtc);
076ed3b2 5485 }
0b8765c6 5486
4a3436e8 5487 if (!IS_GEN2(dev))
a72e4c9f 5488 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4a3436e8 5489
f7abfe8b 5490 intel_crtc->active = false;
46ba614c 5491 intel_update_watermarks(crtc);
f37fcc2a 5492
efa9624e 5493 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5494 intel_fbc_update(dev);
efa9624e 5495 mutex_unlock(&dev->struct_mutex);
0b8765c6
JB		 5496}
5497
ee7b9f93
JB		 5498static void i9xx_crtc_off(struct drm_crtc *crtc)
5499{
5500}
5501
b04c5bd6
BF		 5502/* Master function to enable/disable CRTC and corresponding power wells */
5503void intel_crtc_control(struct drm_crtc *crtc, bool enable)
976f8a20
DV		 5504{
5505 struct drm_device *dev = crtc->dev;
5506 struct drm_i915_private *dev_priv = dev->dev_private;
0e572fe7 5507 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
0e572fe7
DV		 5508 enum intel_display_power_domain domain;
5509 unsigned long domains;
976f8a20 5510
0e572fe7
DV		 5511 if (enable) {
5512 if (!intel_crtc->active) {
e1e9fb84
DV		 5513 domains = get_crtc_power_domains(crtc);
5514 for_each_power_domain(domain, domains)
5515 intel_display_power_get(dev_priv, domain);
5516 intel_crtc->enabled_power_domains = domains;
0e572fe7
DV		 5517
5518 dev_priv->display.crtc_enable(crtc);
5519 }
5520 } else {
5521 if (intel_crtc->active) {
5522 dev_priv->display.crtc_disable(crtc);
5523
e1e9fb84
DV		 5524 domains = intel_crtc->enabled_power_domains;
5525 for_each_power_domain(domain, domains)
5526 intel_display_power_put(dev_priv, domain);
5527 intel_crtc->enabled_power_domains = 0;
0e572fe7
DV		 5528 }
5529 }
b04c5bd6
BF		 5530}
5531
5532/**
5533 * Sets the power management mode of the pipe and plane.
5534 */
5535void intel_crtc_update_dpms(struct drm_crtc *crtc)
5536{
5537 struct drm_device *dev = crtc->dev;
5538 struct intel_encoder *intel_encoder;
5539 bool enable = false;
5540
5541 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5542 enable |= intel_encoder->connectors_active;
5543
5544 intel_crtc_control(crtc, enable);
976f8a20
DV		 5545}
5546
cdd59983
CW		 5547static void intel_crtc_disable(struct drm_crtc *crtc)
5548{
cdd59983 5549 struct drm_device *dev = crtc->dev;
976f8a20 5550 struct drm_connector *connector;
ee7b9f93 5551 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 5552
976f8a20 5553 /* crtc should still be enabled when we disable it. */
83d65738 5554 WARN_ON(!crtc->state->enable);
976f8a20
DV		 5555
5556 dev_priv->display.crtc_disable(crtc);
ee7b9f93
JB		 5557 dev_priv->display.off(crtc);
5558
455a6808 5559 crtc->primary->funcs->disable_plane(crtc->primary);
976f8a20
DV		 5560
5561 /* Update computed state. */
5562 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5563 if (!connector->encoder || !connector->encoder->crtc)
5564 continue;
5565
5566 if (connector->encoder->crtc != crtc)
5567 continue;
5568
5569 connector->dpms = DRM_MODE_DPMS_OFF;
5570 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 5571 }
5572}
5573
ea5b213a 5574void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 5575{
4ef69c7a 5576 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 5577
ea5b213a
CW		 5578 drm_encoder_cleanup(encoder);
5579 kfree(intel_encoder);
7e7d76c3
JB		 5580}
5581
9237329d 5582/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 5583 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5584 * state of the entire output pipe. */
9237329d 5585static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 5586{
5ab432ef
DV		 5587 if (mode == DRM_MODE_DPMS_ON) {
5588 encoder->connectors_active = true;
5589
b2cabb0e 5590 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 5591 } else {
5592 encoder->connectors_active = false;
5593
b2cabb0e 5594 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 5595 }
79e53945
JB		 5596}
5597
0a91ca29
DV		 5598/* Cross check the actual hw state with our own modeset state tracking (and it's
5599 * internal consistency). */
b980514c 5600static void intel_connector_check_state(struct intel_connector *connector)
79e53945 5601{
0a91ca29
DV		 5602 if (connector->get_hw_state(connector)) {
5603 struct intel_encoder *encoder = connector->encoder;
5604 struct drm_crtc *crtc;
5605 bool encoder_enabled;
5606 enum pipe pipe;
5607
5608 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5609 connector->base.base.id,
c23cc417 5610 connector->base.name);
0a91ca29 5611
0e32b39c
DA		 5612 /* there is no real hw state for MST connectors */
5613 if (connector->mst_port)
5614 return;
5615
e2c719b7 5616 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
0a91ca29 5617 "wrong connector dpms state\n");
e2c719b7 5618 I915_STATE_WARN(connector->base.encoder != &encoder->base,
0a91ca29 5619 "active connector not linked to encoder\n");
0a91ca29 5620
36cd7444 5621 if (encoder) {
e2c719b7 5622 I915_STATE_WARN(!encoder->connectors_active,
36cd7444
DA		 5623 "encoder->connectors_active not set\n");
5624
5625 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
e2c719b7
RC		 5626 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
5627 if (I915_STATE_WARN_ON(!encoder->base.crtc))
36cd7444 5628 return;
0a91ca29 5629
36cd7444 5630 crtc = encoder->base.crtc;
0a91ca29 5631
83d65738
MR		 5632 I915_STATE_WARN(!crtc->state->enable,
5633 "crtc not enabled\n");
e2c719b7
RC		 5634 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5635 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
36cd7444
DA		 5636 "encoder active on the wrong pipe\n");
5637 }
0a91ca29 5638 }
79e53945
JB		 5639}
5640
5ab432ef
DV		 5641/* Even simpler default implementation, if there's really no special case to
5642 * consider. */
5643void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 5644{
5ab432ef
DV		 5645 /* All the simple cases only support two dpms states. */
5646 if (mode != DRM_MODE_DPMS_ON)
5647 mode = DRM_MODE_DPMS_OFF;
d4270e57 5648
5ab432ef
DV		 5649 if (mode == connector->dpms)
5650 return;
5651
5652 connector->dpms = mode;
5653
5654 /* Only need to change hw state when actually enabled */
c9976dcf
CW		 5655 if (connector->encoder)
5656 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
0a91ca29 5657
b980514c 5658 intel_modeset_check_state(connector->dev);
79e53945
JB		 5659}
5660
f0947c37
DV		 5661/* Simple connector->get_hw_state implementation for encoders that support only
5662 * one connector and no cloning and hence the encoder state determines the state
5663 * of the connector. */
5664bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 5665{
24929352 5666 enum pipe pipe = 0;
f0947c37 5667 struct intel_encoder *encoder = connector->encoder;
ea5b213a 5668
f0947c37 5669 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 5670}
5671
d272ddfa
VS		 5672static int pipe_required_fdi_lanes(struct drm_device *dev, enum pipe pipe)
5673{
5674 struct intel_crtc *crtc =
5675 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5676
5677 if (crtc->base.state->enable &&
5678 crtc->config->has_pch_encoder)
5679 return crtc->config->fdi_lanes;
5680
5681 return 0;
5682}
5683
1857e1da 5684static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 5685 struct intel_crtc_state *pipe_config)
1857e1da 5686{
1857e1da
DV		 5687 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5688 pipe_name(pipe), pipe_config->fdi_lanes);
5689 if (pipe_config->fdi_lanes > 4) {
5690 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5691 pipe_name(pipe), pipe_config->fdi_lanes);
5692 return false;
5693 }
5694
bafb6553 5695 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 5696 if (pipe_config->fdi_lanes > 2) {
5697 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5698 pipe_config->fdi_lanes);
5699 return false;
5700 } else {
5701 return true;
5702 }
5703 }
5704
5705 if (INTEL_INFO(dev)->num_pipes == 2)
5706 return true;
5707
5708 /* Ivybridge 3 pipe is really complicated */
5709 switch (pipe) {
5710 case PIPE_A:
5711 return true;
5712 case PIPE_B:
d272ddfa
VS		 5713 if (pipe_config->fdi_lanes > 2 &&
5714 pipe_required_fdi_lanes(dev, PIPE_C) > 0) {
1857e1da
DV		 5715 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5716 pipe_name(pipe), pipe_config->fdi_lanes);
5717 return false;
5718 }
5719 return true;
5720 case PIPE_C:
251cc67c
VS		 5721 if (pipe_config->fdi_lanes > 2) {
5722 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
5723 pipe_name(pipe), pipe_config->fdi_lanes);
5724 return false;
5725 }
d272ddfa 5726 if (pipe_required_fdi_lanes(dev, PIPE_B) > 2) {
1857e1da
DV		 5727 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5728 return false;
5729 }
5730 return true;
5731 default:
5732 BUG();
5733 }
5734}
5735
e29c22c0
DV		 5736#define RETRY 1
5737static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 5738 struct intel_crtc_state *pipe_config)
877d48d5 5739{
1857e1da 5740 struct drm_device *dev = intel_crtc->base.dev;
2d112de7 5741 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
ff9a6750 5742 int lane, link_bw, fdi_dotclock;
e29c22c0 5743 bool setup_ok, needs_recompute = false;
877d48d5 5744
e29c22c0 5745retry:
877d48d5
DV		 5746 /* FDI is a binary signal running at ~2.7GHz, encoding
5747 * each output octet as 10 bits. The actual frequency
5748 * is stored as a divider into a 100MHz clock, and the
5749 * mode pixel clock is stored in units of 1KHz.
5750 * Hence the bw of each lane in terms of the mode signal
5751 * is:
5752 */
5753 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5754
241bfc38 5755 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 5756
2bd89a07 5757 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 5758 pipe_config->pipe_bpp);
5759
5760 pipe_config->fdi_lanes = lane;
5761
2bd89a07 5762 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 5763 link_bw, &pipe_config->fdi_m_n);
1857e1da 5764
e29c22c0
DV		 5765 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5766 intel_crtc->pipe, pipe_config);
5767 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5768 pipe_config->pipe_bpp -= 2*3;
5769 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5770 pipe_config->pipe_bpp);
5771 needs_recompute = true;
5772 pipe_config->bw_constrained = true;
5773
5774 goto retry;
5775 }
5776
5777 if (needs_recompute)
5778 return RETRY;
5779
5780 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 5781}
5782
42db64ef 5783static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 5784 struct intel_crtc_state *pipe_config)
42db64ef 5785{
d330a953 5786 pipe_config->ips_enabled = i915.enable_ips &&
3c4ca58c 5787 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 5788 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 5789}
5790
a43f6e0f 5791static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 5792 struct intel_crtc_state *pipe_config)
79e53945 5793{
a43f6e0f 5794 struct drm_device *dev = crtc->base.dev;
8bd31e67 5795 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 5796 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
89749350 5797
ad3a4479 5798 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 5799 if (INTEL_INFO(dev)->gen < 4) {
cf532bb2
VS		 5800 int clock_limit =
5801 dev_priv->display.get_display_clock_speed(dev);
5802
5803 /*
5804 * Enable pixel doubling when the dot clock
5805 * is > 90% of the (display) core speed.
5806 *
b397c96b
VS		 5807 * GDG double wide on either pipe,
5808 * otherwise pipe A only.
cf532bb2 5809 */
b397c96b 5810 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 5811 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 5812 clock_limit *= 2;
cf532bb2 5813 pipe_config->double_wide = true;
ad3a4479
VS		 5814 }
5815
241bfc38 5816 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 5817 return -EINVAL;
2c07245f 5818 }
89749350 5819
1d1d0e27
VS		 5820 /*
5821 * Pipe horizontal size must be even in:
5822 * - DVO ganged mode
5823 * - LVDS dual channel mode
5824 * - Double wide pipe
5825 */
a93e255f 5826 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 5827 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5828 pipe_config->pipe_src_w &= ~1;
5829
8693a824
DL		 5830 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5831 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 5832 */
5833 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5834 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 5835 return -EINVAL;
44f46b42 5836
bd080ee5 5837 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 5838 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 5839 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 5840 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5841 * for lvds. */
5842 pipe_config->pipe_bpp = 8*3;
5843 }
5844
f5adf94e 5845 if (HAS_IPS(dev))
a43f6e0f
DV		 5846 hsw_compute_ips_config(crtc, pipe_config);
5847
877d48d5 5848 if (pipe_config->has_pch_encoder)
a43f6e0f 5849 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 5850
e29c22c0 5851 return 0;
79e53945
JB		 5852}
5853
25eb05fc
JB		 5854static int valleyview_get_display_clock_speed(struct drm_device *dev)
5855{
d197b7d3 5856 struct drm_i915_private *dev_priv = dev->dev_private;
d197b7d3
VS		 5857 u32 val;
5858 int divider;
5859
6bcda4f0
VS		 5860 if (dev_priv->hpll_freq == 0)
5861 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5862
d197b7d3
VS		 5863 mutex_lock(&dev_priv->dpio_lock);
5864 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5865 mutex_unlock(&dev_priv->dpio_lock);
5866
5867 divider = val & DISPLAY_FREQUENCY_VALUES;
5868
7d007f40
VS		 5869 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5870 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5871 "cdclk change in progress\n");
5872
6bcda4f0 5873 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
25eb05fc
JB		 5874}
5875
e70236a8
JB		 5876static int i945_get_display_clock_speed(struct drm_device *dev)
5877{
5878 return 400000;
5879}
79e53945 5880
e70236a8 5881static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 5882{
e70236a8
JB		 5883 return 333000;
5884}
79e53945 5885
e70236a8
JB		 5886static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5887{
5888 return 200000;
5889}
79e53945 5890
257a7ffc
DV		 5891static int pnv_get_display_clock_speed(struct drm_device *dev)
5892{
5893 u16 gcfgc = 0;
5894
5895 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5896
5897 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5898 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5899 return 267000;
5900 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5901 return 333000;
5902 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5903 return 444000;
5904 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5905 return 200000;
5906 default:
5907 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5908 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5909 return 133000;
5910 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5911 return 167000;
5912 }
5913}
5914
e70236a8
JB		 5915static int i915gm_get_display_clock_speed(struct drm_device *dev)
5916{
5917 u16 gcfgc = 0;
79e53945 5918
e70236a8
JB		 5919 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5920
5921 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5922 return 133000;
5923 else {
5924 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5925 case GC_DISPLAY_CLOCK_333_MHZ:
5926 return 333000;
5927 default:
5928 case GC_DISPLAY_CLOCK_190_200_MHZ:
5929 return 190000;
79e53945 5930 }
e70236a8
JB		 5931 }
5932}
5933
5934static int i865_get_display_clock_speed(struct drm_device *dev)
5935{
5936 return 266000;
5937}
5938
5939static int i855_get_display_clock_speed(struct drm_device *dev)
5940{
5941 u16 hpllcc = 0;
5942 /* Assume that the hardware is in the high speed state. This
5943 * should be the default.
5944 */
5945 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5946 case GC_CLOCK_133_200:
5947 case GC_CLOCK_100_200:
5948 return 200000;
5949 case GC_CLOCK_166_250:
5950 return 250000;
5951 case GC_CLOCK_100_133:
79e53945 5952 return 133000;
e70236a8 5953 }
79e53945 5954
e70236a8
JB		 5955 /* Shouldn't happen */
5956 return 0;
5957}
79e53945 5958
e70236a8
JB		 5959static int i830_get_display_clock_speed(struct drm_device *dev)
5960{
5961 return 133000;
79e53945
JB		 5962}
5963
2c07245f 5964static void
a65851af 5965intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 5966{
a65851af
VS		 5967 while (*num > DATA_LINK_M_N_MASK ||
5968 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 5969 *num >>= 1;
5970 *den >>= 1;
5971 }
5972}
5973
a65851af
VS		 5974static void compute_m_n(unsigned int m, unsigned int n,
5975 uint32_t *ret_m, uint32_t *ret_n)
5976{
5977 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5978 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5979 intel_reduce_m_n_ratio(ret_m, ret_n);
5980}
5981
e69d0bc1
DV		 5982void
5983intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5984 int pixel_clock, int link_clock,
5985 struct intel_link_m_n *m_n)
2c07245f 5986{
e69d0bc1 5987 m_n->tu = 64;
a65851af
VS		 5988
5989 compute_m_n(bits_per_pixel * pixel_clock,
5990 link_clock * nlanes * 8,
5991 &m_n->gmch_m, &m_n->gmch_n);
5992
5993 compute_m_n(pixel_clock, link_clock,
5994 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 5995}
5996
a7615030
CW		 5997static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5998{
d330a953
JN		 5999 if (i915.panel_use_ssc >= 0)
6000 return i915.panel_use_ssc != 0;
41aa3448 6001 return dev_priv->vbt.lvds_use_ssc
435793df 6002 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 6003}
6004
a93e255f
ACO		 6005static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
6006 int num_connectors)
c65d77d8 6007{
a93e255f 6008 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 6009 struct drm_i915_private *dev_priv = dev->dev_private;
6010 int refclk;
6011
a93e255f
ACO		 6012 WARN_ON(!crtc_state->base.state);
6013
a0c4da24 6014 if (IS_VALLEYVIEW(dev)) {
9a0ea498 6015 refclk = 100000;
a93e255f 6016 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 6017 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 6018 refclk = dev_priv->vbt.lvds_ssc_freq;
6019 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 6020 } else if (!IS_GEN2(dev)) {
6021 refclk = 96000;
6022 } else {
6023 refclk = 48000;
6024 }
6025
6026 return refclk;
6027}
6028
7429e9d4 6029static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 6030{
7df00d7a 6031 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 6032}
f47709a9 6033
7429e9d4
DV		 6034static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6035{
6036 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 6037}
6038
f47709a9 6039static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 6040 struct intel_crtc_state *crtc_state,
a7516a05
JB		 6041 intel_clock_t *reduced_clock)
6042{
f47709a9 6043 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 6044 u32 fp, fp2 = 0;
6045
6046 if (IS_PINEVIEW(dev)) {
190f68c5 6047 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 6048 if (reduced_clock)
7429e9d4 6049 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 6050 } else {
190f68c5 6051 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 6052 if (reduced_clock)
7429e9d4 6053 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 6054 }
6055
190f68c5 6056 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 6057
f47709a9 6058 crtc->lowfreq_avail = false;
a93e255f 6059 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 6060 reduced_clock) {
190f68c5 6061 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 6062 crtc->lowfreq_avail = true;
a7516a05 6063 } else {
190f68c5 6064 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 6065 }
6066}
6067
5e69f97f
CML		 6068static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6069 pipe)
89b667f8
JB		 6070{
6071 u32 reg_val;
6072
6073 /*
6074 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6075 * and set it to a reasonable value instead.
6076 */
ab3c759a 6077 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 6078 reg_val &= 0xffffff00;
6079 reg_val |= 0x00000030;
ab3c759a 6080 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 6081
ab3c759a 6082 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 6083 reg_val &= 0x8cffffff;
6084 reg_val = 0x8c000000;
ab3c759a 6085 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 6086
ab3c759a 6087 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 6088 reg_val &= 0xffffff00;
ab3c759a 6089 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 6090
ab3c759a 6091 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 6092 reg_val &= 0x00ffffff;
6093 reg_val |= 0xb0000000;
ab3c759a 6094 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 6095}
6096
b551842d
DV		 6097static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6098 struct intel_link_m_n *m_n)
6099{
6100 struct drm_device *dev = crtc->base.dev;
6101 struct drm_i915_private *dev_priv = dev->dev_private;
6102 int pipe = crtc->pipe;
6103
e3b95f1e
DV		 6104 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6105 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6106 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6107 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 6108}
6109
6110static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 6111 struct intel_link_m_n *m_n,
6112 struct intel_link_m_n *m2_n2)
b551842d
DV		 6113{
6114 struct drm_device *dev = crtc->base.dev;
6115 struct drm_i915_private *dev_priv = dev->dev_private;
6116 int pipe = crtc->pipe;
6e3c9717 6117 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 6118
6119 if (INTEL_INFO(dev)->gen >= 5) {
6120 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6121 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6122 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6123 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 6124 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6125 * for gen < 8) and if DRRS is supported (to make sure the
6126 * registers are not unnecessarily accessed).
6127 */
44395bfe 6128 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 6129 crtc->config->has_drrs) {
f769cd24
VK		 6130 I915_WRITE(PIPE_DATA_M2(transcoder),
6131 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6132 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6133 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6134 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6135 }
b551842d 6136 } else {
e3b95f1e
DV		 6137 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6138 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6139 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6140 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 6141 }
6142}
6143
fe3cd48d 6144void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 6145{
fe3cd48d
R		 6146 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6147
6148 if (m_n == M1_N1) {
6149 dp_m_n = &crtc->config->dp_m_n;
6150 dp_m2_n2 = &crtc->config->dp_m2_n2;
6151 } else if (m_n == M2_N2) {
6152
6153 /*
6154 * M2_N2 registers are not supported. Hence m2_n2 divider value
6155 * needs to be programmed into M1_N1.
6156 */
6157 dp_m_n = &crtc->config->dp_m2_n2;
6158 } else {
6159 DRM_ERROR("Unsupported divider value\n");
6160 return;
6161 }
6162
6e3c9717
ACO		 6163 if (crtc->config->has_pch_encoder)
6164 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 6165 else
fe3cd48d 6166 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 6167}
6168
d288f65f 6169static void vlv_update_pll(struct intel_crtc *crtc,
5cec258b 6170 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 6171{
6172 u32 dpll, dpll_md;
6173
6174 /*
6175 * Enable DPIO clock input. We should never disable the reference
6176 * clock for pipe B, since VGA hotplug / manual detection depends
6177 * on it.
6178 */
6179 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6180 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6181 /* We should never disable this, set it here for state tracking */
6182 if (crtc->pipe == PIPE_B)
6183 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6184 dpll |= DPLL_VCO_ENABLE;
d288f65f 6185 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 6186
d288f65f 6187 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 6188 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 6189 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 6190}
6191
d288f65f 6192static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 6193 const struct intel_crtc_state *pipe_config)
a0c4da24 6194{
f47709a9 6195 struct drm_device *dev = crtc->base.dev;
a0c4da24 6196 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 6197 int pipe = crtc->pipe;
bdd4b6a6 6198 u32 mdiv;
a0c4da24 6199 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 6200 u32 coreclk, reg_val;
a0c4da24 6201
09153000
DV		 6202 mutex_lock(&dev_priv->dpio_lock);
6203
d288f65f
VS		 6204 bestn = pipe_config->dpll.n;
6205 bestm1 = pipe_config->dpll.m1;
6206 bestm2 = pipe_config->dpll.m2;
6207 bestp1 = pipe_config->dpll.p1;
6208 bestp2 = pipe_config->dpll.p2;
a0c4da24 6209
89b667f8
JB		 6210 /* See eDP HDMI DPIO driver vbios notes doc */
6211
6212 /* PLL B needs special handling */
bdd4b6a6 6213 if (pipe == PIPE_B)
5e69f97f 6214 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 6215
6216 /* Set up Tx target for periodic Rcomp update */
ab3c759a 6217 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 6218
6219 /* Disable target IRef on PLL */
ab3c759a 6220 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 6221 reg_val &= 0x00ffffff;
ab3c759a 6222 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 6223
6224 /* Disable fast lock */
ab3c759a 6225 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 6226
6227 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 6228 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6229 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6230 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 6231 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 6232
6233 /*
6234 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6235 * but we don't support that).
6236 * Note: don't use the DAC post divider as it seems unstable.
6237 */
6238 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 6239 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 6240
a0c4da24 6241 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 6242 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 6243
89b667f8 6244 /* Set HBR and RBR LPF coefficients */
d288f65f 6245 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 6246 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6247 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 6248 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 6249 0x009f0003);
89b667f8 6250 else
ab3c759a 6251 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 6252 0x00d0000f);
6253
681a8504 6254 if (pipe_config->has_dp_encoder) {
89b667f8 6255 /* Use SSC source */
bdd4b6a6 6256 if (pipe == PIPE_A)
ab3c759a 6257 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6258 0x0df40000);
6259 else
ab3c759a 6260 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6261 0x0df70000);
6262 } else { /* HDMI or VGA */
6263 /* Use bend source */
bdd4b6a6 6264 if (pipe == PIPE_A)
ab3c759a 6265 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6266 0x0df70000);
6267 else
ab3c759a 6268 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6269 0x0df40000);
6270 }
a0c4da24 6271
ab3c759a 6272 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 6273 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 6274 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6275 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 6276 coreclk |= 0x01000000;
ab3c759a 6277 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 6278
ab3c759a 6279 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
09153000 6280 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 6281}
6282
d288f65f 6283static void chv_update_pll(struct intel_crtc *crtc,
5cec258b 6284 struct intel_crtc_state *pipe_config)
1ae0d137 6285{
d288f65f 6286 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
1ae0d137
VS		 6287 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6288 DPLL_VCO_ENABLE;
6289 if (crtc->pipe != PIPE_A)
d288f65f 6290 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 6291
d288f65f
VS		 6292 pipe_config->dpll_hw_state.dpll_md =
6293 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 6294}
6295
d288f65f 6296static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 6297 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 6298{
6299 struct drm_device *dev = crtc->base.dev;
6300 struct drm_i915_private *dev_priv = dev->dev_private;
6301 int pipe = crtc->pipe;
6302 int dpll_reg = DPLL(crtc->pipe);
6303 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 6304 u32 loopfilter, tribuf_calcntr;
9d556c99 6305 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 6306 u32 dpio_val;
9cbe40c1 6307 int vco;
9d556c99 6308
d288f65f
VS		 6309 bestn = pipe_config->dpll.n;
6310 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6311 bestm1 = pipe_config->dpll.m1;
6312 bestm2 = pipe_config->dpll.m2 >> 22;
6313 bestp1 = pipe_config->dpll.p1;
6314 bestp2 = pipe_config->dpll.p2;
9cbe40c1 6315 vco = pipe_config->dpll.vco;
a945ce7e 6316 dpio_val = 0;
9cbe40c1 6317 loopfilter = 0;
9d556c99
CML		 6318
6319 /*
6320 * Enable Refclk and SSC
6321 */
a11b0703 6322 I915_WRITE(dpll_reg,
d288f65f 6323 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703
VS		 6324
6325 mutex_lock(&dev_priv->dpio_lock);
9d556c99 6326
9d556c99
CML		 6327 /* p1 and p2 divider */
6328 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6329 5 << DPIO_CHV_S1_DIV_SHIFT |
6330 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6331 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6332 1 << DPIO_CHV_K_DIV_SHIFT);
6333
6334 /* Feedback post-divider - m2 */
6335 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6336
6337 /* Feedback refclk divider - n and m1 */
6338 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6339 DPIO_CHV_M1_DIV_BY_2 |
6340 1 << DPIO_CHV_N_DIV_SHIFT);
6341
6342 /* M2 fraction division */
a945ce7e
VP		 6343 if (bestm2_frac)
6344 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 6345
6346 /* M2 fraction division enable */
a945ce7e
VP		 6347 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6348 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6349 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6350 if (bestm2_frac)
6351 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6352 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 6353
de3a0fde
VP		 6354 /* Program digital lock detect threshold */
6355 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6356 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6357 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6358 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6359 if (!bestm2_frac)
6360 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6361 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6362
9d556c99 6363 /* Loop filter */
9cbe40c1
VP		 6364 if (vco == 5400000) {
6365 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6366 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6367 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6368 tribuf_calcntr = 0x9;
6369 } else if (vco <= 6200000) {
6370 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6371 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6372 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6373 tribuf_calcntr = 0x9;
6374 } else if (vco <= 6480000) {
6375 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6376 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6377 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6378 tribuf_calcntr = 0x8;
6379 } else {
6380 /* Not supported. Apply the same limits as in the max case */
6381 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6382 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6383 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6384 tribuf_calcntr = 0;
6385 }
9d556c99
CML		 6386 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6387
968040b2 6388 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 6389 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6390 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6391 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6392
9d556c99
CML		 6393 /* AFC Recal */
6394 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6395 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6396 DPIO_AFC_RECAL);
6397
6398 mutex_unlock(&dev_priv->dpio_lock);
6399}
6400
d288f65f
VS		 6401/**
6402 * vlv_force_pll_on - forcibly enable just the PLL
6403 * @dev_priv: i915 private structure
6404 * @pipe: pipe PLL to enable
6405 * @dpll: PLL configuration
6406 *
6407 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6408 * in cases where we need the PLL enabled even when @pipe is not going to
6409 * be enabled.
6410 */
6411void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6412 const struct dpll *dpll)
6413{
6414 struct intel_crtc *crtc =
6415 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 6416 struct intel_crtc_state pipe_config = {
a93e255f 6417 .base.crtc = &crtc->base,
d288f65f
VS		 6418 .pixel_multiplier = 1,
6419 .dpll = *dpll,
6420 };
6421
6422 if (IS_CHERRYVIEW(dev)) {
6423 chv_update_pll(crtc, &pipe_config);
6424 chv_prepare_pll(crtc, &pipe_config);
6425 chv_enable_pll(crtc, &pipe_config);
6426 } else {
6427 vlv_update_pll(crtc, &pipe_config);
6428 vlv_prepare_pll(crtc, &pipe_config);
6429 vlv_enable_pll(crtc, &pipe_config);
6430 }
6431}
6432
6433/**
6434 * vlv_force_pll_off - forcibly disable just the PLL
6435 * @dev_priv: i915 private structure
6436 * @pipe: pipe PLL to disable
6437 *
6438 * Disable the PLL for @pipe. To be used in cases where we need
6439 * the PLL enabled even when @pipe is not going to be enabled.
6440 */
6441void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6442{
6443 if (IS_CHERRYVIEW(dev))
6444 chv_disable_pll(to_i915(dev), pipe);
6445 else
6446 vlv_disable_pll(to_i915(dev), pipe);
6447}
6448
f47709a9 6449static void i9xx_update_pll(struct intel_crtc *crtc,
190f68c5 6450 struct intel_crtc_state *crtc_state,
f47709a9 6451 intel_clock_t *reduced_clock,
eb1cbe48
DV		 6452 int num_connectors)
6453{
f47709a9 6454 struct drm_device *dev = crtc->base.dev;
eb1cbe48 6455 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 6456 u32 dpll;
6457 bool is_sdvo;
190f68c5 6458 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 6459
190f68c5 6460 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 6461
a93e255f
ACO		 6462 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
6463 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 6464
6465 dpll = DPLL_VGA_MODE_DIS;
6466
a93e255f 6467 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 6468 dpll |= DPLLB_MODE_LVDS;
6469 else
6470 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 6471
ef1b460d 6472 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 6473 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 6474 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 6475 }
198a037f
DV		 6476
6477 if (is_sdvo)
4a33e48d 6478 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 6479
190f68c5 6480 if (crtc_state->has_dp_encoder)
4a33e48d 6481 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 6482
6483 /* compute bitmask from p1 value */
6484 if (IS_PINEVIEW(dev))
6485 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6486 else {
6487 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6488 if (IS_G4X(dev) && reduced_clock)
6489 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6490 }
6491 switch (clock->p2) {
6492 case 5:
6493 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6494 break;
6495 case 7:
6496 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6497 break;
6498 case 10:
6499 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6500 break;
6501 case 14:
6502 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6503 break;
6504 }
6505 if (INTEL_INFO(dev)->gen >= 4)
6506 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6507
190f68c5 6508 if (crtc_state->sdvo_tv_clock)
eb1cbe48 6509 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 6510 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 6511 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6512 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6513 else
6514 dpll |= PLL_REF_INPUT_DREFCLK;
6515
6516 dpll |= DPLL_VCO_ENABLE;
190f68c5 6517 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 6518
eb1cbe48 6519 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 6520 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 6521 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 6522 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 6523 }
6524}
6525
f47709a9 6526static void i8xx_update_pll(struct intel_crtc *crtc,
190f68c5 6527 struct intel_crtc_state *crtc_state,
f47709a9 6528 intel_clock_t *reduced_clock,
eb1cbe48
DV		 6529 int num_connectors)
6530{
f47709a9 6531 struct drm_device *dev = crtc->base.dev;
eb1cbe48 6532 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 6533 u32 dpll;
190f68c5 6534 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 6535
190f68c5 6536 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 6537
eb1cbe48
DV		 6538 dpll = DPLL_VGA_MODE_DIS;
6539
a93e255f 6540 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 6541 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6542 } else {
6543 if (clock->p1 == 2)
6544 dpll |= PLL_P1_DIVIDE_BY_TWO;
6545 else
6546 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6547 if (clock->p2 == 4)
6548 dpll |= PLL_P2_DIVIDE_BY_4;
6549 }
6550
a93e255f 6551 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 6552 dpll |= DPLL_DVO_2X_MODE;
6553
a93e255f 6554 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 6555 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6556 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6557 else
6558 dpll |= PLL_REF_INPUT_DREFCLK;
6559
6560 dpll |= DPLL_VCO_ENABLE;
190f68c5 6561 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 6562}
6563
8a654f3b 6564static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 6565{
6566 struct drm_device *dev = intel_crtc->base.dev;
6567 struct drm_i915_private *dev_priv = dev->dev_private;
6568 enum pipe pipe = intel_crtc->pipe;
6e3c9717 6569 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8a654f3b 6570 struct drm_display_mode *adjusted_mode =
6e3c9717 6571 &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 6572 uint32_t crtc_vtotal, crtc_vblank_end;
6573 int vsyncshift = 0;
4d8a62ea
DV		 6574
6575 /* We need to be careful not to changed the adjusted mode, for otherwise
6576 * the hw state checker will get angry at the mismatch. */
6577 crtc_vtotal = adjusted_mode->crtc_vtotal;
6578 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 6579
609aeaca 6580 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 6581 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 6582 crtc_vtotal -= 1;
6583 crtc_vblank_end -= 1;
609aeaca 6584
409ee761 6585 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 6586 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6587 else
6588 vsyncshift = adjusted_mode->crtc_hsync_start -
6589 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 6590 if (vsyncshift < 0)
6591 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 6592 }
6593
6594 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 6595 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 6596
fe2b8f9d 6597 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 6598 (adjusted_mode->crtc_hdisplay - 1) |
6599 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 6600 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 6601 (adjusted_mode->crtc_hblank_start - 1) |
6602 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 6603 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 6604 (adjusted_mode->crtc_hsync_start - 1) |
6605 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6606
fe2b8f9d 6607 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 6608 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 6609 ((crtc_vtotal - 1) << 16));
fe2b8f9d 6610 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 6611 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 6612 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 6613 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 6614 (adjusted_mode->crtc_vsync_start - 1) |
6615 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6616
b5e508d4
PZ		 6617 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6618 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6619 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6620 * bits. */
6621 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6622 (pipe == PIPE_B || pipe == PIPE_C))
6623 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6624
b0e77b9c
PZ		 6625 /* pipesrc controls the size that is scaled from, which should
6626 * always be the user's requested size.
6627 */
6628 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 6629 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6630 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 6631}
6632
1bd1bd80 6633static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 6634 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 6635{
6636 struct drm_device *dev = crtc->base.dev;
6637 struct drm_i915_private *dev_priv = dev->dev_private;
6638 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6639 uint32_t tmp;
6640
6641 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 6642 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6643 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 6644 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 6645 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6646 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 6647 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 6648 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6649 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 6650
6651 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 6652 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6653 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 6654 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 6655 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6656 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 6657 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 6658 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6659 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 6660
6661 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 6662 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6663 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6664 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 6665 }
6666
6667 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 6668 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6669 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6670
2d112de7
ACO		 6671 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6672 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 6673}
6674
f6a83288 6675void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 6676 struct intel_crtc_state *pipe_config)
babea61d 6677{
2d112de7
ACO		 6678 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6679 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6680 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6681 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 6682
2d112de7
ACO		 6683 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6684 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6685 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6686 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 6687
2d112de7 6688 mode->flags = pipe_config->base.adjusted_mode.flags;
babea61d 6689
2d112de7
ACO		 6690 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6691 mode->flags |= pipe_config->base.adjusted_mode.flags;
babea61d
JB		 6692}
6693
84b046f3
DV		 6694static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6695{
6696 struct drm_device *dev = intel_crtc->base.dev;
6697 struct drm_i915_private *dev_priv = dev->dev_private;
6698 uint32_t pipeconf;
6699
9f11a9e4 6700 pipeconf = 0;
84b046f3 6701
b6b5d049
VS		 6702 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6703 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6704 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 6705
6e3c9717 6706 if (intel_crtc->config->double_wide)
cf532bb2 6707 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 6708
ff9ce46e
DV		 6709 /* only g4x and later have fancy bpc/dither controls */
6710 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 6711 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 6712 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 6713 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 6714 PIPECONF_DITHER_TYPE_SP;
84b046f3 6715
6e3c9717 6716 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 6717 case 18:
6718 pipeconf |= PIPECONF_6BPC;
6719 break;
6720 case 24:
6721 pipeconf |= PIPECONF_8BPC;
6722 break;
6723 case 30:
6724 pipeconf |= PIPECONF_10BPC;
6725 break;
6726 default:
6727 /* Case prevented by intel_choose_pipe_bpp_dither. */
6728 BUG();
84b046f3
DV		 6729 }
6730 }
6731
6732 if (HAS_PIPE_CXSR(dev)) {
6733 if (intel_crtc->lowfreq_avail) {
6734 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6735 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6736 } else {
6737 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 6738 }
6739 }
6740
6e3c9717 6741 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 6742 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 6743 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 6744 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6745 else
6746 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6747 } else
84b046f3
DV		 6748 pipeconf |= PIPECONF_PROGRESSIVE;
6749
6e3c9717 6750 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 6751 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 6752
84b046f3
DV		 6753 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6754 POSTING_READ(PIPECONF(intel_crtc->pipe));
6755}
6756
190f68c5
ACO		 6757static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
6758 struct intel_crtc_state *crtc_state)
79e53945 6759{
c7653199 6760 struct drm_device *dev = crtc->base.dev;
79e53945 6761 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 6762 int refclk, num_connectors = 0;
652c393a 6763 intel_clock_t clock, reduced_clock;
a16af721 6764 bool ok, has_reduced_clock = false;
e9fd1c02 6765 bool is_lvds = false, is_dsi = false;
5eddb70b 6766 struct intel_encoder *encoder;
d4906093 6767 const intel_limit_t *limit;
55bb9992
ACO		 6768 struct drm_atomic_state *state = crtc_state->base.state;
6769 struct drm_connector_state *connector_state;
6770 int i;
79e53945 6771
55bb9992
ACO		 6772 for (i = 0; i < state->num_connector; i++) {
6773 if (!state->connectors[i])
d0737e1d
ACO		 6774 continue;
6775
55bb9992
ACO		 6776 connector_state = state->connector_states[i];
6777 if (connector_state->crtc != &crtc->base)
6778 continue;
6779
6780 encoder = to_intel_encoder(connector_state->best_encoder);
6781
5eddb70b 6782 switch (encoder->type) {
79e53945
JB		 6783 case INTEL_OUTPUT_LVDS:
6784 is_lvds = true;
6785 break;
e9fd1c02
JN		 6786 case INTEL_OUTPUT_DSI:
6787 is_dsi = true;
6788 break;
6847d71b
PZ		 6789 default:
6790 break;
79e53945 6791 }
43565a06 6792
c751ce4f 6793 num_connectors++;
79e53945
JB		 6794 }
6795
f2335330 6796 if (is_dsi)
5b18e57c 6797 return 0;
f2335330 6798
190f68c5 6799 if (!crtc_state->clock_set) {
a93e255f 6800 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 6801
e9fd1c02
JN		 6802 /*
6803 * Returns a set of divisors for the desired target clock with
6804 * the given refclk, or FALSE. The returned values represent
6805 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6806 * 2) / p1 / p2.
6807 */
a93e255f
ACO		 6808 limit = intel_limit(crtc_state, refclk);
6809 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 6810 crtc_state->port_clock,
e9fd1c02 6811 refclk, NULL, &clock);
f2335330 6812 if (!ok) {
e9fd1c02
JN		 6813 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6814 return -EINVAL;
6815 }
79e53945 6816
f2335330
JN		 6817 if (is_lvds && dev_priv->lvds_downclock_avail) {
6818 /*
6819 * Ensure we match the reduced clock's P to the target
6820 * clock. If the clocks don't match, we can't switch
6821 * the display clock by using the FP0/FP1. In such case
6822 * we will disable the LVDS downclock feature.
6823 */
6824 has_reduced_clock =
a93e255f 6825 dev_priv->display.find_dpll(limit, crtc_state,
f2335330
JN		 6826 dev_priv->lvds_downclock,
6827 refclk, &clock,
6828 &reduced_clock);
6829 }
6830 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 6831 crtc_state->dpll.n = clock.n;
6832 crtc_state->dpll.m1 = clock.m1;
6833 crtc_state->dpll.m2 = clock.m2;
6834 crtc_state->dpll.p1 = clock.p1;
6835 crtc_state->dpll.p2 = clock.p2;
f47709a9 6836 }
7026d4ac 6837
e9fd1c02 6838 if (IS_GEN2(dev)) {
190f68c5 6839 i8xx_update_pll(crtc, crtc_state,
2a8f64ca
VP		 6840 has_reduced_clock ? &reduced_clock : NULL,
6841 num_connectors);
9d556c99 6842 } else if (IS_CHERRYVIEW(dev)) {
190f68c5 6843 chv_update_pll(crtc, crtc_state);
e9fd1c02 6844 } else if (IS_VALLEYVIEW(dev)) {
190f68c5 6845 vlv_update_pll(crtc, crtc_state);
e9fd1c02 6846 } else {
190f68c5 6847 i9xx_update_pll(crtc, crtc_state,
eb1cbe48 6848 has_reduced_clock ? &reduced_clock : NULL,
eba905b2 6849 num_connectors);
e9fd1c02 6850 }
79e53945 6851
c8f7a0db 6852 return 0;
f564048e
EA		 6853}
6854
2fa2fe9a 6855static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 6856 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 6857{
6858 struct drm_device *dev = crtc->base.dev;
6859 struct drm_i915_private *dev_priv = dev->dev_private;
6860 uint32_t tmp;
6861
dc9e7dec
VS		 6862 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6863 return;
6864
2fa2fe9a 6865 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 6866 if (!(tmp & PFIT_ENABLE))
6867 return;
2fa2fe9a 6868
06922821 6869 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 6870 if (INTEL_INFO(dev)->gen < 4) {
6871 if (crtc->pipe != PIPE_B)
6872 return;
2fa2fe9a
DV		 6873 } else {
6874 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6875 return;
6876 }
6877
06922821 6878 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 6879 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6880 if (INTEL_INFO(dev)->gen < 5)
6881 pipe_config->gmch_pfit.lvds_border_bits =
6882 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6883}
6884
acbec814 6885static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 6886 struct intel_crtc_state *pipe_config)
acbec814
JB		 6887{
6888 struct drm_device *dev = crtc->base.dev;
6889 struct drm_i915_private *dev_priv = dev->dev_private;
6890 int pipe = pipe_config->cpu_transcoder;
6891 intel_clock_t clock;
6892 u32 mdiv;
662c6ecb 6893 int refclk = 100000;
acbec814 6894
f573de5a
SK		 6895 /* In case of MIPI DPLL will not even be used */
6896 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6897 return;
6898
acbec814 6899 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 6900 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
acbec814
JB		 6901 mutex_unlock(&dev_priv->dpio_lock);
6902
6903 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6904 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6905 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6906 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6907 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6908
f646628b 6909 vlv_clock(refclk, &clock);
acbec814 6910
f646628b
VS		 6911 /* clock.dot is the fast clock */
6912 pipe_config->port_clock = clock.dot / 5;
acbec814
JB		 6913}
6914
5724dbd1
DL		 6915static void
6916i9xx_get_initial_plane_config(struct intel_crtc *crtc,
6917 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 6918{
6919 struct drm_device *dev = crtc->base.dev;
6920 struct drm_i915_private *dev_priv = dev->dev_private;
6921 u32 val, base, offset;
6922 int pipe = crtc->pipe, plane = crtc->plane;
6923 int fourcc, pixel_format;
6761dd31 6924 unsigned int aligned_height;
b113d5ee 6925 struct drm_framebuffer *fb;
1b842c89 6926 struct intel_framebuffer *intel_fb;
1ad292b5 6927
42a7b088
DL		 6928 val = I915_READ(DSPCNTR(plane));
6929 if (!(val & DISPLAY_PLANE_ENABLE))
6930 return;
6931
d9806c9f 6932 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 6933 if (!intel_fb) {
1ad292b5
JB		 6934 DRM_DEBUG_KMS("failed to alloc fb\n");
6935 return;
6936 }
6937
1b842c89
DL		 6938 fb = &intel_fb->base;
6939
18c5247e
DV		 6940 if (INTEL_INFO(dev)->gen >= 4) {
6941 if (val & DISPPLANE_TILED) {
49af449b 6942 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 6943 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
6944 }
6945 }
1ad292b5
JB		 6946
6947 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 6948 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 6949 fb->pixel_format = fourcc;
6950 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 6951
6952 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 6953 if (plane_config->tiling)
1ad292b5
JB		 6954 offset = I915_READ(DSPTILEOFF(plane));
6955 else
6956 offset = I915_READ(DSPLINOFF(plane));
6957 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6958 } else {
6959 base = I915_READ(DSPADDR(plane));
6960 }
6961 plane_config->base = base;
6962
6963 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 6964 fb->width = ((val >> 16) & 0xfff) + 1;
6965 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 6966
6967 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 6968 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 6969
b113d5ee 6970 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 6971 fb->pixel_format,
6972 fb->modifier[0]);
1ad292b5 6973
f37b5c2b 6974 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 6975
2844a921
DL		 6976 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6977 pipe_name(pipe), plane, fb->width, fb->height,
6978 fb->bits_per_pixel, base, fb->pitches[0],
6979 plane_config->size);
1ad292b5 6980
2d14030b 6981 plane_config->fb = intel_fb;
1ad292b5
JB		 6982}
6983
70b23a98 6984static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 6985 struct intel_crtc_state *pipe_config)
70b23a98
VS		 6986{
6987 struct drm_device *dev = crtc->base.dev;
6988 struct drm_i915_private *dev_priv = dev->dev_private;
6989 int pipe = pipe_config->cpu_transcoder;
6990 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6991 intel_clock_t clock;
6992 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6993 int refclk = 100000;
6994
6995 mutex_lock(&dev_priv->dpio_lock);
6996 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6997 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6998 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6999 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7000 mutex_unlock(&dev_priv->dpio_lock);
7001
7002 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7003 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
7004 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7005 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7006 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7007
7008 chv_clock(refclk, &clock);
7009
7010 /* clock.dot is the fast clock */
7011 pipe_config->port_clock = clock.dot / 5;
7012}
7013
0e8ffe1b 7014static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 7015 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 7016{
7017 struct drm_device *dev = crtc->base.dev;
7018 struct drm_i915_private *dev_priv = dev->dev_private;
7019 uint32_t tmp;
7020
f458ebbc
DV		 7021 if (!intel_display_power_is_enabled(dev_priv,
7022 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 7023 return false;
7024
e143a21c 7025 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 7026 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 7027
0e8ffe1b
DV		 7028 tmp = I915_READ(PIPECONF(crtc->pipe));
7029 if (!(tmp & PIPECONF_ENABLE))
7030 return false;
7031
42571aef
VS		 7032 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7033 switch (tmp & PIPECONF_BPC_MASK) {
7034 case PIPECONF_6BPC:
7035 pipe_config->pipe_bpp = 18;
7036 break;
7037 case PIPECONF_8BPC:
7038 pipe_config->pipe_bpp = 24;
7039 break;
7040 case PIPECONF_10BPC:
7041 pipe_config->pipe_bpp = 30;
7042 break;
7043 default:
7044 break;
7045 }
7046 }
7047
b5a9fa09
DV		 7048 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
7049 pipe_config->limited_color_range = true;
7050
282740f7
VS		 7051 if (INTEL_INFO(dev)->gen < 4)
7052 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7053
1bd1bd80
DV		 7054 intel_get_pipe_timings(crtc, pipe_config);
7055
2fa2fe9a
DV		 7056 i9xx_get_pfit_config(crtc, pipe_config);
7057
6c49f241
DV		 7058 if (INTEL_INFO(dev)->gen >= 4) {
7059 tmp = I915_READ(DPLL_MD(crtc->pipe));
7060 pipe_config->pixel_multiplier =
7061 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7062 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 7063 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 7064 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7065 tmp = I915_READ(DPLL(crtc->pipe));
7066 pipe_config->pixel_multiplier =
7067 ((tmp & SDVO_MULTIPLIER_MASK)
7068 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7069 } else {
7070 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7071 * port and will be fixed up in the encoder->get_config
7072 * function. */
7073 pipe_config->pixel_multiplier = 1;
7074 }
8bcc2795
DV		 7075 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7076 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 7077 /*
7078 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7079 * on 830. Filter it out here so that we don't
7080 * report errors due to that.
7081 */
7082 if (IS_I830(dev))
7083 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7084
8bcc2795
DV		 7085 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7086 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 7087 } else {
7088 /* Mask out read-only status bits. */
7089 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7090 DPLL_PORTC_READY_MASK |
7091 DPLL_PORTB_READY_MASK);
8bcc2795 7092 }
6c49f241 7093
70b23a98
VS		 7094 if (IS_CHERRYVIEW(dev))
7095 chv_crtc_clock_get(crtc, pipe_config);
7096 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 7097 vlv_crtc_clock_get(crtc, pipe_config);
7098 else
7099 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 7100
0e8ffe1b
DV		 7101 return true;
7102}
7103
dde86e2d 7104static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 7105{
7106 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 7107 struct intel_encoder *encoder;
74cfd7ac 7108 u32 val, final;
13d83a67 7109 bool has_lvds = false;
199e5d79 7110 bool has_cpu_edp = false;
199e5d79 7111 bool has_panel = false;
99eb6a01
KP		 7112 bool has_ck505 = false;
7113 bool can_ssc = false;
13d83a67
JB		 7114
7115 /* We need to take the global config into account */
b2784e15 7116 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 7117 switch (encoder->type) {
7118 case INTEL_OUTPUT_LVDS:
7119 has_panel = true;
7120 has_lvds = true;
7121 break;
7122 case INTEL_OUTPUT_EDP:
7123 has_panel = true;
2de6905f 7124 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 7125 has_cpu_edp = true;
7126 break;
6847d71b
PZ		 7127 default:
7128 break;
13d83a67
JB		 7129 }
7130 }
7131
99eb6a01 7132 if (HAS_PCH_IBX(dev)) {
41aa3448 7133 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 7134 can_ssc = has_ck505;
7135 } else {
7136 has_ck505 = false;
7137 can_ssc = true;
7138 }
7139
2de6905f
ID		 7140 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7141 has_panel, has_lvds, has_ck505);
13d83a67
JB		 7142
7143 /* Ironlake: try to setup display ref clock before DPLL
7144 * enabling. This is only under driver's control after
7145 * PCH B stepping, previous chipset stepping should be
7146 * ignoring this setting.
7147 */
74cfd7ac
CW		 7148 val = I915_READ(PCH_DREF_CONTROL);
7149
7150 /* As we must carefully and slowly disable/enable each source in turn,
7151 * compute the final state we want first and check if we need to
7152 * make any changes at all.
7153 */
7154 final = val;
7155 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7156 if (has_ck505)
7157 final |= DREF_NONSPREAD_CK505_ENABLE;
7158 else
7159 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7160
7161 final &= ~DREF_SSC_SOURCE_MASK;
7162 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7163 final &= ~DREF_SSC1_ENABLE;
7164
7165 if (has_panel) {
7166 final |= DREF_SSC_SOURCE_ENABLE;
7167
7168 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7169 final |= DREF_SSC1_ENABLE;
7170
7171 if (has_cpu_edp) {
7172 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7173 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7174 else
7175 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7176 } else
7177 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7178 } else {
7179 final |= DREF_SSC_SOURCE_DISABLE;
7180 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7181 }
7182
7183 if (final == val)
7184 return;
7185
13d83a67 7186 /* Always enable nonspread source */
74cfd7ac 7187 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 7188
99eb6a01 7189 if (has_ck505)
74cfd7ac 7190 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 7191 else
74cfd7ac 7192 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 7193
199e5d79 7194 if (has_panel) {
74cfd7ac
CW		 7195 val &= ~DREF_SSC_SOURCE_MASK;
7196 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 7197
199e5d79 7198 /* SSC must be turned on before enabling the CPU output */
99eb6a01 7199 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 7200 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 7201 val |= DREF_SSC1_ENABLE;
e77166b5 7202 } else
74cfd7ac 7203 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 7204
7205 /* Get SSC going before enabling the outputs */
74cfd7ac 7206 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7207 POSTING_READ(PCH_DREF_CONTROL);
7208 udelay(200);
7209
74cfd7ac 7210 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 7211
7212 /* Enable CPU source on CPU attached eDP */
199e5d79 7213 if (has_cpu_edp) {
99eb6a01 7214 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 7215 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 7216 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 7217 } else
74cfd7ac 7218 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 7219 } else
74cfd7ac 7220 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 7221
74cfd7ac 7222 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7223 POSTING_READ(PCH_DREF_CONTROL);
7224 udelay(200);
7225 } else {
7226 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7227
74cfd7ac 7228 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 7229
7230 /* Turn off CPU output */
74cfd7ac 7231 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 7232
74cfd7ac 7233 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7234 POSTING_READ(PCH_DREF_CONTROL);
7235 udelay(200);
7236
7237 /* Turn off the SSC source */
74cfd7ac
CW		 7238 val &= ~DREF_SSC_SOURCE_MASK;
7239 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 7240
7241 /* Turn off SSC1 */
74cfd7ac 7242 val &= ~DREF_SSC1_ENABLE;
199e5d79 7243
74cfd7ac 7244 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 7245 POSTING_READ(PCH_DREF_CONTROL);
7246 udelay(200);
7247 }
74cfd7ac
CW		 7248
7249 BUG_ON(val != final);
13d83a67
JB		 7250}
7251
f31f2d55 7252static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 7253{
f31f2d55 7254 uint32_t tmp;
dde86e2d 7255
0ff066a9
PZ		 7256 tmp = I915_READ(SOUTH_CHICKEN2);
7257 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7258 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 7259
0ff066a9
PZ		 7260 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7261 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7262 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 7263
0ff066a9
PZ		 7264 tmp = I915_READ(SOUTH_CHICKEN2);
7265 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7266 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 7267
0ff066a9
PZ		 7268 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7269 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7270 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 7271}
7272
7273/* WaMPhyProgramming:hsw */
7274static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7275{
7276 uint32_t tmp;
dde86e2d
PZ		 7277
7278 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7279 tmp &= ~(0xFF << 24);
7280 tmp |= (0x12 << 24);
7281 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7282
dde86e2d
PZ		 7283 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7284 tmp |= (1 << 11);
7285 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7286
7287 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7288 tmp |= (1 << 11);
7289 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7290
dde86e2d
PZ		 7291 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7292 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7293 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7294
7295 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7296 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7297 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7298
0ff066a9
PZ		 7299 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7300 tmp &= ~(7 << 13);
7301 tmp |= (5 << 13);
7302 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 7303
0ff066a9
PZ		 7304 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7305 tmp &= ~(7 << 13);
7306 tmp |= (5 << 13);
7307 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 7308
7309 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7310 tmp &= ~0xFF;
7311 tmp |= 0x1C;
7312 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7313
7314 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7315 tmp &= ~0xFF;
7316 tmp |= 0x1C;
7317 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7318
7319 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7320 tmp &= ~(0xFF << 16);
7321 tmp |= (0x1C << 16);
7322 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7323
7324 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7325 tmp &= ~(0xFF << 16);
7326 tmp |= (0x1C << 16);
7327 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7328
0ff066a9
PZ		 7329 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7330 tmp |= (1 << 27);
7331 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 7332
0ff066a9
PZ		 7333 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7334 tmp |= (1 << 27);
7335 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 7336
0ff066a9
PZ		 7337 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7338 tmp &= ~(0xF << 28);
7339 tmp |= (4 << 28);
7340 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 7341
0ff066a9
PZ		 7342 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7343 tmp &= ~(0xF << 28);
7344 tmp |= (4 << 28);
7345 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 7346}
7347
2fa86a1f
PZ		 7348/* Implements 3 different sequences from BSpec chapter "Display iCLK
7349 * Programming" based on the parameters passed:
7350 * - Sequence to enable CLKOUT_DP
7351 * - Sequence to enable CLKOUT_DP without spread
7352 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7353 */
7354static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7355 bool with_fdi)
f31f2d55
PZ		 7356{
7357 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 7358 uint32_t reg, tmp;
7359
7360 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7361 with_spread = true;
7362 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7363 with_fdi, "LP PCH doesn't have FDI\n"))
7364 with_fdi = false;
f31f2d55
PZ		 7365
7366 mutex_lock(&dev_priv->dpio_lock);
7367
7368 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7369 tmp &= ~SBI_SSCCTL_DISABLE;
7370 tmp |= SBI_SSCCTL_PATHALT;
7371 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7372
7373 udelay(24);
7374
2fa86a1f
PZ		 7375 if (with_spread) {
7376 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7377 tmp &= ~SBI_SSCCTL_PATHALT;
7378 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 7379
2fa86a1f
PZ		 7380 if (with_fdi) {
7381 lpt_reset_fdi_mphy(dev_priv);
7382 lpt_program_fdi_mphy(dev_priv);
7383 }
7384 }
dde86e2d 7385
2fa86a1f
PZ		 7386 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7387 SBI_GEN0 : SBI_DBUFF0;
7388 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7389 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7390 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 7391
7392 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 7393}
7394
47701c3b
PZ		 7395/* Sequence to disable CLKOUT_DP */
7396static void lpt_disable_clkout_dp(struct drm_device *dev)
7397{
7398 struct drm_i915_private *dev_priv = dev->dev_private;
7399 uint32_t reg, tmp;
7400
7401 mutex_lock(&dev_priv->dpio_lock);
7402
7403 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7404 SBI_GEN0 : SBI_DBUFF0;
7405 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7406 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7407 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7408
7409 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7410 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7411 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7412 tmp |= SBI_SSCCTL_PATHALT;
7413 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7414 udelay(32);
7415 }
7416 tmp |= SBI_SSCCTL_DISABLE;
7417 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7418 }
7419
7420 mutex_unlock(&dev_priv->dpio_lock);
7421}
7422
bf8fa3d3
PZ		 7423static void lpt_init_pch_refclk(struct drm_device *dev)
7424{
bf8fa3d3
PZ		 7425 struct intel_encoder *encoder;
7426 bool has_vga = false;
7427
b2784e15 7428 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 7429 switch (encoder->type) {
7430 case INTEL_OUTPUT_ANALOG:
7431 has_vga = true;
7432 break;
6847d71b
PZ		 7433 default:
7434 break;
bf8fa3d3
PZ		 7435 }
7436 }
7437
47701c3b
PZ		 7438 if (has_vga)
7439 lpt_enable_clkout_dp(dev, true, true);
7440 else
7441 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 7442}
7443
dde86e2d
PZ		 7444/*
7445 * Initialize reference clocks when the driver loads
7446 */
7447void intel_init_pch_refclk(struct drm_device *dev)
7448{
7449 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7450 ironlake_init_pch_refclk(dev);
7451 else if (HAS_PCH_LPT(dev))
7452 lpt_init_pch_refclk(dev);
7453}
7454
55bb9992 7455static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 7456{
55bb9992 7457 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 7458 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992
ACO		 7459 struct drm_atomic_state *state = crtc_state->base.state;
7460 struct drm_connector_state *connector_state;
d9d444cb 7461 struct intel_encoder *encoder;
55bb9992 7462 int num_connectors = 0, i;
d9d444cb
JB		 7463 bool is_lvds = false;
7464
55bb9992
ACO		 7465 for (i = 0; i < state->num_connector; i++) {
7466 if (!state->connectors[i])
d0737e1d
ACO		 7467 continue;
7468
55bb9992
ACO		 7469 connector_state = state->connector_states[i];
7470 if (connector_state->crtc != crtc_state->base.crtc)
7471 continue;
7472
7473 encoder = to_intel_encoder(connector_state->best_encoder);
7474
d9d444cb
JB		 7475 switch (encoder->type) {
7476 case INTEL_OUTPUT_LVDS:
7477 is_lvds = true;
7478 break;
6847d71b
PZ		 7479 default:
7480 break;
d9d444cb
JB		 7481 }
7482 num_connectors++;
7483 }
7484
7485 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 7486 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 7487 dev_priv->vbt.lvds_ssc_freq);
e91e941b 7488 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 7489 }
7490
7491 return 120000;
7492}
7493
6ff93609 7494static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 7495{
c8203565 7496 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 7497 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7498 int pipe = intel_crtc->pipe;
c8203565
PZ		 7499 uint32_t val;
7500
78114071 7501 val = 0;
c8203565 7502
6e3c9717 7503 switch (intel_crtc->config->pipe_bpp) {
c8203565 7504 case 18:
dfd07d72 7505 val |= PIPECONF_6BPC;
c8203565
PZ		 7506 break;
7507 case 24:
dfd07d72 7508 val |= PIPECONF_8BPC;
c8203565
PZ		 7509 break;
7510 case 30:
dfd07d72 7511 val |= PIPECONF_10BPC;
c8203565
PZ		 7512 break;
7513 case 36:
dfd07d72 7514 val |= PIPECONF_12BPC;
c8203565
PZ		 7515 break;
7516 default:
cc769b62
PZ		 7517 /* Case prevented by intel_choose_pipe_bpp_dither. */
7518 BUG();
c8203565
PZ		 7519 }
7520
6e3c9717 7521 if (intel_crtc->config->dither)
c8203565
PZ		 7522 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7523
6e3c9717 7524 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 7525 val |= PIPECONF_INTERLACED_ILK;
7526 else
7527 val |= PIPECONF_PROGRESSIVE;
7528
6e3c9717 7529 if (intel_crtc->config->limited_color_range)
3685a8f3 7530 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 7531
c8203565
PZ		 7532 I915_WRITE(PIPECONF(pipe), val);
7533 POSTING_READ(PIPECONF(pipe));
7534}
7535
86d3efce
VS		 7536/*
7537 * Set up the pipe CSC unit.
7538 *
7539 * Currently only full range RGB to limited range RGB conversion
7540 * is supported, but eventually this should handle various
7541 * RGB<->YCbCr scenarios as well.
7542 */
50f3b016 7543static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 7544{
7545 struct drm_device *dev = crtc->dev;
7546 struct drm_i915_private *dev_priv = dev->dev_private;
7547 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7548 int pipe = intel_crtc->pipe;
7549 uint16_t coeff = 0x7800; /* 1.0 */
7550
7551 /*
7552 * TODO: Check what kind of values actually come out of the pipe
7553 * with these coeff/postoff values and adjust to get the best
7554 * accuracy. Perhaps we even need to take the bpc value into
7555 * consideration.
7556 */
7557
6e3c9717 7558 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 7559 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7560
7561 /*
7562 * GY/GU and RY/RU should be the other way around according
7563 * to BSpec, but reality doesn't agree. Just set them up in
7564 * a way that results in the correct picture.
7565 */
7566 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7567 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7568
7569 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7570 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7571
7572 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7573 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7574
7575 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7576 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7577 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7578
7579 if (INTEL_INFO(dev)->gen > 6) {
7580 uint16_t postoff = 0;
7581
6e3c9717 7582 if (intel_crtc->config->limited_color_range)
32cf0cb0 7583 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 7584
7585 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7586 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7587 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7588
7589 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7590 } else {
7591 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7592
6e3c9717 7593 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 7594 mode |= CSC_BLACK_SCREEN_OFFSET;
7595
7596 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7597 }
7598}
7599
6ff93609 7600static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 7601{
756f85cf
PZ		 7602 struct drm_device *dev = crtc->dev;
7603 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 7604 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 7605 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7606 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 7607 uint32_t val;
7608
3eff4faa 7609 val = 0;
ee2b0b38 7610
6e3c9717 7611 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 7612 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7613
6e3c9717 7614 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 7615 val |= PIPECONF_INTERLACED_ILK;
7616 else
7617 val |= PIPECONF_PROGRESSIVE;
7618
702e7a56
PZ		 7619 I915_WRITE(PIPECONF(cpu_transcoder), val);
7620 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 7621
7622 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7623 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 7624
3cdf122c 7625 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 7626 val = 0;
7627
6e3c9717 7628 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 7629 case 18:
7630 val |= PIPEMISC_DITHER_6_BPC;
7631 break;
7632 case 24:
7633 val |= PIPEMISC_DITHER_8_BPC;
7634 break;
7635 case 30:
7636 val |= PIPEMISC_DITHER_10_BPC;
7637 break;
7638 case 36:
7639 val |= PIPEMISC_DITHER_12_BPC;
7640 break;
7641 default:
7642 /* Case prevented by pipe_config_set_bpp. */
7643 BUG();
7644 }
7645
6e3c9717 7646 if (intel_crtc->config->dither)
756f85cf
PZ		 7647 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7648
7649 I915_WRITE(PIPEMISC(pipe), val);
7650 }
ee2b0b38
PZ		 7651}
7652
6591c6e4 7653static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 7654 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 7655 intel_clock_t *clock,
7656 bool *has_reduced_clock,
7657 intel_clock_t *reduced_clock)
7658{
7659 struct drm_device *dev = crtc->dev;
7660 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 7661 int refclk;
d4906093 7662 const intel_limit_t *limit;
a16af721 7663 bool ret, is_lvds = false;
79e53945 7664
a93e255f 7665 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
79e53945 7666
55bb9992 7667 refclk = ironlake_get_refclk(crtc_state);
79e53945 7668
d4906093
ML		 7669 /*
7670 * Returns a set of divisors for the desired target clock with the given
7671 * refclk, or FALSE. The returned values represent the clock equation:
7672 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7673 */
a93e255f
ACO		 7674 limit = intel_limit(crtc_state, refclk);
7675 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7676 crtc_state->port_clock,
ee9300bb 7677 refclk, NULL, clock);
6591c6e4
PZ		 7678 if (!ret)
7679 return false;
cda4b7d3 7680
ddc9003c 7681 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 7682 /*
7683 * Ensure we match the reduced clock's P to the target clock.
7684 * If the clocks don't match, we can't switch the display clock
7685 * by using the FP0/FP1. In such case we will disable the LVDS
7686 * downclock feature.
7687 */
ee9300bb 7688 *has_reduced_clock =
a93e255f 7689 dev_priv->display.find_dpll(limit, crtc_state,
ee9300bb
DV		 7690 dev_priv->lvds_downclock,
7691 refclk, clock,
7692 reduced_clock);
652c393a 7693 }
61e9653f 7694
6591c6e4
PZ		 7695 return true;
7696}
7697
d4b1931c
PZ		 7698int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7699{
7700 /*
7701 * Account for spread spectrum to avoid
7702 * oversubscribing the link. Max center spread
7703 * is 2.5%; use 5% for safety's sake.
7704 */
7705 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 7706 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 7707}
7708
7429e9d4 7709static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 7710{
7429e9d4 7711 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 7712}
7713
de13a2e3 7714static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 7715 struct intel_crtc_state *crtc_state,
7429e9d4 7716 u32 *fp,
9a7c7890 7717 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 7718{
de13a2e3 7719 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 7720 struct drm_device *dev = crtc->dev;
7721 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992
ACO		 7722 struct drm_atomic_state *state = crtc_state->base.state;
7723 struct drm_connector_state *connector_state;
7724 struct intel_encoder *encoder;
de13a2e3 7725 uint32_t dpll;
55bb9992 7726 int factor, num_connectors = 0, i;
09ede541 7727 bool is_lvds = false, is_sdvo = false;
79e53945 7728
55bb9992
ACO		 7729 for (i = 0; i < state->num_connector; i++) {
7730 if (!state->connectors[i])
d0737e1d
ACO		 7731 continue;
7732
55bb9992
ACO		 7733 connector_state = state->connector_states[i];
7734 if (connector_state->crtc != crtc_state->base.crtc)
7735 continue;
7736
7737 encoder = to_intel_encoder(connector_state->best_encoder);
7738
7739 switch (encoder->type) {
79e53945
JB		 7740 case INTEL_OUTPUT_LVDS:
7741 is_lvds = true;
7742 break;
7743 case INTEL_OUTPUT_SDVO:
7d57382e 7744 case INTEL_OUTPUT_HDMI:
79e53945 7745 is_sdvo = true;
79e53945 7746 break;
6847d71b
PZ		 7747 default:
7748 break;
79e53945 7749 }
43565a06 7750
c751ce4f 7751 num_connectors++;
79e53945 7752 }
79e53945 7753
c1858123 7754 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 7755 factor = 21;
7756 if (is_lvds) {
7757 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 7758 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 7759 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 7760 factor = 25;
190f68c5 7761 } else if (crtc_state->sdvo_tv_clock)
8febb297 7762 factor = 20;
c1858123 7763
190f68c5 7764 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 7765 *fp |= FP_CB_TUNE;
2c07245f 7766
9a7c7890
DV		 7767 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7768 *fp2 |= FP_CB_TUNE;
7769
5eddb70b 7770 dpll = 0;
2c07245f 7771
a07d6787
EA		 7772 if (is_lvds)
7773 dpll |= DPLLB_MODE_LVDS;
7774 else
7775 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 7776
190f68c5 7777 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 7778 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 7779
7780 if (is_sdvo)
4a33e48d 7781 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 7782 if (crtc_state->has_dp_encoder)
4a33e48d 7783 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 7784
a07d6787 7785 /* compute bitmask from p1 value */
190f68c5 7786 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 7787 /* also FPA1 */
190f68c5 7788 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 7789
190f68c5 7790 switch (crtc_state->dpll.p2) {
a07d6787
EA		 7791 case 5:
7792 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7793 break;
7794 case 7:
7795 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7796 break;
7797 case 10:
7798 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7799 break;
7800 case 14:
7801 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7802 break;
79e53945
JB		 7803 }
7804
b4c09f3b 7805 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 7806 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 7807 else
7808 dpll |= PLL_REF_INPUT_DREFCLK;
7809
959e16d6 7810 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 7811}
7812
190f68c5
ACO		 7813static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
7814 struct intel_crtc_state *crtc_state)
de13a2e3 7815{
c7653199 7816 struct drm_device *dev = crtc->base.dev;
de13a2e3 7817 intel_clock_t clock, reduced_clock;
cbbab5bd 7818 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 7819 bool ok, has_reduced_clock = false;
8b47047b 7820 bool is_lvds = false;
e2b78267 7821 struct intel_shared_dpll *pll;
de13a2e3 7822
409ee761 7823 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 7824
5dc5298b
PZ		 7825 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7826 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 7827
190f68c5 7828 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 7829 &has_reduced_clock, &reduced_clock);
190f68c5 7830 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 7831 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7832 return -EINVAL;
79e53945 7833 }
f47709a9 7834 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7835 if (!crtc_state->clock_set) {
7836 crtc_state->dpll.n = clock.n;
7837 crtc_state->dpll.m1 = clock.m1;
7838 crtc_state->dpll.m2 = clock.m2;
7839 crtc_state->dpll.p1 = clock.p1;
7840 crtc_state->dpll.p2 = clock.p2;
f47709a9 7841 }
79e53945 7842
5dc5298b 7843 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 7844 if (crtc_state->has_pch_encoder) {
7845 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 7846 if (has_reduced_clock)
7429e9d4 7847 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 7848
190f68c5 7849 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 7850 &fp, &reduced_clock,
7851 has_reduced_clock ? &fp2 : NULL);
7852
190f68c5
ACO		 7853 crtc_state->dpll_hw_state.dpll = dpll;
7854 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 7855 if (has_reduced_clock)
190f68c5 7856 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 7857 else
190f68c5 7858 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 7859
190f68c5 7860 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 7861 if (pll == NULL) {
84f44ce7 7862 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 7863 pipe_name(crtc->pipe));
4b645f14
JB		 7864 return -EINVAL;
7865 }
3fb37703 7866 }
79e53945 7867
ab585dea 7868 if (is_lvds && has_reduced_clock)
c7653199 7869 crtc->lowfreq_avail = true;
bcd644e0 7870 else
c7653199 7871 crtc->lowfreq_avail = false;
e2b78267 7872
c8f7a0db 7873 return 0;
79e53945
JB		 7874}
7875
eb14cb74
VS		 7876static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7877 struct intel_link_m_n *m_n)
7878{
7879 struct drm_device *dev = crtc->base.dev;
7880 struct drm_i915_private *dev_priv = dev->dev_private;
7881 enum pipe pipe = crtc->pipe;
7882
7883 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7884 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7885 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7886 & ~TU_SIZE_MASK;
7887 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7888 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7889 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7890}
7891
7892static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7893 enum transcoder transcoder,
b95af8be
VK		 7894 struct intel_link_m_n *m_n,
7895 struct intel_link_m_n *m2_n2)
72419203
DV		 7896{
7897 struct drm_device *dev = crtc->base.dev;
7898 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 7899 enum pipe pipe = crtc->pipe;
72419203 7900
eb14cb74
VS		 7901 if (INTEL_INFO(dev)->gen >= 5) {
7902 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7903 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7904 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7905 & ~TU_SIZE_MASK;
7906 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7907 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7908 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 7909 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7910 * gen < 8) and if DRRS is supported (to make sure the
7911 * registers are not unnecessarily read).
7912 */
7913 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 7914 crtc->config->has_drrs) {
b95af8be
VK		 7915 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7916 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7917 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7918 & ~TU_SIZE_MASK;
7919 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7920 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7921 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7922 }
eb14cb74
VS		 7923 } else {
7924 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7925 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7926 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7927 & ~TU_SIZE_MASK;
7928 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7929 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7930 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7931 }
7932}
7933
7934void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 7935 struct intel_crtc_state *pipe_config)
eb14cb74 7936{
681a8504 7937 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 7938 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7939 else
7940 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 7941 &pipe_config->dp_m_n,
7942 &pipe_config->dp_m2_n2);
eb14cb74 7943}
72419203 7944
eb14cb74 7945static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 7946 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 7947{
7948 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 7949 &pipe_config->fdi_m_n, NULL);
72419203
DV		 7950}
7951
bd2e244f 7952static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7953 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 7954{
7955 struct drm_device *dev = crtc->base.dev;
7956 struct drm_i915_private *dev_priv = dev->dev_private;
7957 uint32_t tmp;
7958
7959 tmp = I915_READ(PS_CTL(crtc->pipe));
7960
7961 if (tmp & PS_ENABLE) {
7962 pipe_config->pch_pfit.enabled = true;
7963 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
7964 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
7965 }
7966}
7967
5724dbd1
DL		 7968static void
7969skylake_get_initial_plane_config(struct intel_crtc *crtc,
7970 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 7971{
7972 struct drm_device *dev = crtc->base.dev;
7973 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 7974 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 7975 int pipe = crtc->pipe;
7976 int fourcc, pixel_format;
6761dd31 7977 unsigned int aligned_height;
bc8d7dff 7978 struct drm_framebuffer *fb;
1b842c89 7979 struct intel_framebuffer *intel_fb;
bc8d7dff 7980
d9806c9f 7981 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 7982 if (!intel_fb) {
bc8d7dff
DL		 7983 DRM_DEBUG_KMS("failed to alloc fb\n");
7984 return;
7985 }
7986
1b842c89
DL		 7987 fb = &intel_fb->base;
7988
bc8d7dff 7989 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 7990 if (!(val & PLANE_CTL_ENABLE))
7991 goto error;
7992
bc8d7dff
DL		 7993 pixel_format = val & PLANE_CTL_FORMAT_MASK;
7994 fourcc = skl_format_to_fourcc(pixel_format,
7995 val & PLANE_CTL_ORDER_RGBX,
7996 val & PLANE_CTL_ALPHA_MASK);
7997 fb->pixel_format = fourcc;
7998 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7999
40f46283
DL		 8000 tiling = val & PLANE_CTL_TILED_MASK;
8001 switch (tiling) {
8002 case PLANE_CTL_TILED_LINEAR:
8003 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
8004 break;
8005 case PLANE_CTL_TILED_X:
8006 plane_config->tiling = I915_TILING_X;
8007 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8008 break;
8009 case PLANE_CTL_TILED_Y:
8010 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
8011 break;
8012 case PLANE_CTL_TILED_YF:
8013 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
8014 break;
8015 default:
8016 MISSING_CASE(tiling);
8017 goto error;
8018 }
8019
bc8d7dff
DL		 8020 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8021 plane_config->base = base;
8022
8023 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8024
8025 val = I915_READ(PLANE_SIZE(pipe, 0));
8026 fb->height = ((val >> 16) & 0xfff) + 1;
8027 fb->width = ((val >> 0) & 0x1fff) + 1;
8028
8029 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 8030 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
8031 fb->pixel_format);
bc8d7dff
DL		 8032 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8033
8034 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8035 fb->pixel_format,
8036 fb->modifier[0]);
bc8d7dff 8037
f37b5c2b 8038 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 8039
8040 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8041 pipe_name(pipe), fb->width, fb->height,
8042 fb->bits_per_pixel, base, fb->pitches[0],
8043 plane_config->size);
8044
2d14030b 8045 plane_config->fb = intel_fb;
bc8d7dff
DL		 8046 return;
8047
8048error:
8049 kfree(fb);
8050}
8051
2fa2fe9a 8052static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8053 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 8054{
8055 struct drm_device *dev = crtc->base.dev;
8056 struct drm_i915_private *dev_priv = dev->dev_private;
8057 uint32_t tmp;
8058
8059 tmp = I915_READ(PF_CTL(crtc->pipe));
8060
8061 if (tmp & PF_ENABLE) {
fd4daa9c 8062 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 8063 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8064 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 8065
8066 /* We currently do not free assignements of panel fitters on
8067 * ivb/hsw (since we don't use the higher upscaling modes which
8068 * differentiates them) so just WARN about this case for now. */
8069 if (IS_GEN7(dev)) {
8070 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8071 PF_PIPE_SEL_IVB(crtc->pipe));
8072 }
2fa2fe9a 8073 }
79e53945
JB		 8074}
8075
5724dbd1
DL		 8076static void
8077ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8078 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 8079{
8080 struct drm_device *dev = crtc->base.dev;
8081 struct drm_i915_private *dev_priv = dev->dev_private;
8082 u32 val, base, offset;
aeee5a49 8083 int pipe = crtc->pipe;
4c6baa59 8084 int fourcc, pixel_format;
6761dd31 8085 unsigned int aligned_height;
b113d5ee 8086 struct drm_framebuffer *fb;
1b842c89 8087 struct intel_framebuffer *intel_fb;
4c6baa59 8088
42a7b088
DL		 8089 val = I915_READ(DSPCNTR(pipe));
8090 if (!(val & DISPLAY_PLANE_ENABLE))
8091 return;
8092
d9806c9f 8093 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8094 if (!intel_fb) {
4c6baa59
JB		 8095 DRM_DEBUG_KMS("failed to alloc fb\n");
8096 return;
8097 }
8098
1b842c89
DL		 8099 fb = &intel_fb->base;
8100
18c5247e
DV		 8101 if (INTEL_INFO(dev)->gen >= 4) {
8102 if (val & DISPPLANE_TILED) {
49af449b 8103 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 8104 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8105 }
8106 }
4c6baa59
JB		 8107
8108 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 8109 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 8110 fb->pixel_format = fourcc;
8111 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 8112
aeee5a49 8113 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 8114 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 8115 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 8116 } else {
49af449b 8117 if (plane_config->tiling)
aeee5a49 8118 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 8119 else
aeee5a49 8120 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 8121 }
8122 plane_config->base = base;
8123
8124 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 8125 fb->width = ((val >> 16) & 0xfff) + 1;
8126 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 8127
8128 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 8129 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 8130
b113d5ee 8131 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8132 fb->pixel_format,
8133 fb->modifier[0]);
4c6baa59 8134
f37b5c2b 8135 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 8136
2844a921
DL		 8137 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8138 pipe_name(pipe), fb->width, fb->height,
8139 fb->bits_per_pixel, base, fb->pitches[0],
8140 plane_config->size);
b113d5ee 8141
2d14030b 8142 plane_config->fb = intel_fb;
4c6baa59
JB		 8143}
8144
0e8ffe1b 8145static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8146 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8147{
8148 struct drm_device *dev = crtc->base.dev;
8149 struct drm_i915_private *dev_priv = dev->dev_private;
8150 uint32_t tmp;
8151
f458ebbc
DV		 8152 if (!intel_display_power_is_enabled(dev_priv,
8153 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 8154 return false;
8155
e143a21c 8156 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8157 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8158
0e8ffe1b
DV		 8159 tmp = I915_READ(PIPECONF(crtc->pipe));
8160 if (!(tmp & PIPECONF_ENABLE))
8161 return false;
8162
42571aef
VS		 8163 switch (tmp & PIPECONF_BPC_MASK) {
8164 case PIPECONF_6BPC:
8165 pipe_config->pipe_bpp = 18;
8166 break;
8167 case PIPECONF_8BPC:
8168 pipe_config->pipe_bpp = 24;
8169 break;
8170 case PIPECONF_10BPC:
8171 pipe_config->pipe_bpp = 30;
8172 break;
8173 case PIPECONF_12BPC:
8174 pipe_config->pipe_bpp = 36;
8175 break;
8176 default:
8177 break;
8178 }
8179
b5a9fa09
DV		 8180 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8181 pipe_config->limited_color_range = true;
8182
ab9412ba 8183 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 8184 struct intel_shared_dpll *pll;
8185
88adfff1
DV		 8186 pipe_config->has_pch_encoder = true;
8187
627eb5a3
DV		 8188 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8189 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8190 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 8191
8192 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 8193
c0d43d62 8194 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 8195 pipe_config->shared_dpll =
8196 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 8197 } else {
8198 tmp = I915_READ(PCH_DPLL_SEL);
8199 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8200 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8201 else
8202 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8203 }
66e985c0
DV		 8204
8205 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8206
8207 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8208 &pipe_config->dpll_hw_state));
c93f54cf
DV		 8209
8210 tmp = pipe_config->dpll_hw_state.dpll;
8211 pipe_config->pixel_multiplier =
8212 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8213 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 8214
8215 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 8216 } else {
8217 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 8218 }
8219
1bd1bd80
DV		 8220 intel_get_pipe_timings(crtc, pipe_config);
8221
2fa2fe9a
DV		 8222 ironlake_get_pfit_config(crtc, pipe_config);
8223
0e8ffe1b
DV		 8224 return true;
8225}
8226
be256dc7
PZ		 8227static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8228{
8229 struct drm_device *dev = dev_priv->dev;
be256dc7 8230 struct intel_crtc *crtc;
be256dc7 8231
d3fcc808 8232 for_each_intel_crtc(dev, crtc)
e2c719b7 8233 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 8234 pipe_name(crtc->pipe));
8235
e2c719b7
RC		 8236 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8237 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8238 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8239 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8240 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8241 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 8242 "CPU PWM1 enabled\n");
c5107b87 8243 if (IS_HASWELL(dev))
e2c719b7 8244 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 8245 "CPU PWM2 enabled\n");
e2c719b7 8246 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 8247 "PCH PWM1 enabled\n");
e2c719b7 8248 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 8249 "Utility pin enabled\n");
e2c719b7 8250 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 8251
9926ada1
PZ		 8252 /*
8253 * In theory we can still leave IRQs enabled, as long as only the HPD
8254 * interrupts remain enabled. We used to check for that, but since it's
8255 * gen-specific and since we only disable LCPLL after we fully disable
8256 * the interrupts, the check below should be enough.
8257 */
e2c719b7 8258 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 8259}
8260
9ccd5aeb
PZ		 8261static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8262{
8263 struct drm_device *dev = dev_priv->dev;
8264
8265 if (IS_HASWELL(dev))
8266 return I915_READ(D_COMP_HSW);
8267 else
8268 return I915_READ(D_COMP_BDW);
8269}
8270
3c4c9b81
PZ		 8271static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8272{
8273 struct drm_device *dev = dev_priv->dev;
8274
8275 if (IS_HASWELL(dev)) {
8276 mutex_lock(&dev_priv->rps.hw_lock);
8277 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8278 val))
f475dadf 8279 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 8280 mutex_unlock(&dev_priv->rps.hw_lock);
8281 } else {
9ccd5aeb
PZ		 8282 I915_WRITE(D_COMP_BDW, val);
8283 POSTING_READ(D_COMP_BDW);
3c4c9b81 8284 }
be256dc7
PZ		 8285}
8286
8287/*
8288 * This function implements pieces of two sequences from BSpec:
8289 * - Sequence for display software to disable LCPLL
8290 * - Sequence for display software to allow package C8+
8291 * The steps implemented here are just the steps that actually touch the LCPLL
8292 * register. Callers should take care of disabling all the display engine
8293 * functions, doing the mode unset, fixing interrupts, etc.
8294 */
6ff58d53
PZ		 8295static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8296 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 8297{
8298 uint32_t val;
8299
8300 assert_can_disable_lcpll(dev_priv);
8301
8302 val = I915_READ(LCPLL_CTL);
8303
8304 if (switch_to_fclk) {
8305 val |= LCPLL_CD_SOURCE_FCLK;
8306 I915_WRITE(LCPLL_CTL, val);
8307
8308 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
8309 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8310 DRM_ERROR("Switching to FCLK failed\n");
8311
8312 val = I915_READ(LCPLL_CTL);
8313 }
8314
8315 val |= LCPLL_PLL_DISABLE;
8316 I915_WRITE(LCPLL_CTL, val);
8317 POSTING_READ(LCPLL_CTL);
8318
8319 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
8320 DRM_ERROR("LCPLL still locked\n");
8321
9ccd5aeb 8322 val = hsw_read_dcomp(dev_priv);
be256dc7 8323 val |= D_COMP_COMP_DISABLE;
3c4c9b81 8324 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 8325 ndelay(100);
8326
9ccd5aeb
PZ		 8327 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8328 1))
be256dc7
PZ		 8329 DRM_ERROR("D_COMP RCOMP still in progress\n");
8330
8331 if (allow_power_down) {
8332 val = I915_READ(LCPLL_CTL);
8333 val |= LCPLL_POWER_DOWN_ALLOW;
8334 I915_WRITE(LCPLL_CTL, val);
8335 POSTING_READ(LCPLL_CTL);
8336 }
8337}
8338
8339/*
8340 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8341 * source.
8342 */
6ff58d53 8343static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 8344{
8345 uint32_t val;
8346
8347 val = I915_READ(LCPLL_CTL);
8348
8349 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8350 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8351 return;
8352
a8a8bd54
PZ		 8353 /*
8354 * Make sure we're not on PC8 state before disabling PC8, otherwise
8355 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 8356 */
59bad947 8357 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 8358
be256dc7
PZ		 8359 if (val & LCPLL_POWER_DOWN_ALLOW) {
8360 val &= ~LCPLL_POWER_DOWN_ALLOW;
8361 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 8362 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 8363 }
8364
9ccd5aeb 8365 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 8366 val |= D_COMP_COMP_FORCE;
8367 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 8368 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 8369
8370 val = I915_READ(LCPLL_CTL);
8371 val &= ~LCPLL_PLL_DISABLE;
8372 I915_WRITE(LCPLL_CTL, val);
8373
8374 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
8375 DRM_ERROR("LCPLL not locked yet\n");
8376
8377 if (val & LCPLL_CD_SOURCE_FCLK) {
8378 val = I915_READ(LCPLL_CTL);
8379 val &= ~LCPLL_CD_SOURCE_FCLK;
8380 I915_WRITE(LCPLL_CTL, val);
8381
8382 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
8383 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8384 DRM_ERROR("Switching back to LCPLL failed\n");
8385 }
215733fa 8386
59bad947 8387 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
be256dc7
PZ		 8388}
8389
765dab67
PZ		 8390/*
8391 * Package states C8 and deeper are really deep PC states that can only be
8392 * reached when all the devices on the system allow it, so even if the graphics
8393 * device allows PC8+, it doesn't mean the system will actually get to these
8394 * states. Our driver only allows PC8+ when going into runtime PM.
8395 *
8396 * The requirements for PC8+ are that all the outputs are disabled, the power
8397 * well is disabled and most interrupts are disabled, and these are also
8398 * requirements for runtime PM. When these conditions are met, we manually do
8399 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8400 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8401 * hang the machine.
8402 *
8403 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8404 * the state of some registers, so when we come back from PC8+ we need to
8405 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8406 * need to take care of the registers kept by RC6. Notice that this happens even
8407 * if we don't put the device in PCI D3 state (which is what currently happens
8408 * because of the runtime PM support).
8409 *
8410 * For more, read "Display Sequences for Package C8" on the hardware
8411 * documentation.
8412 */
a14cb6fc 8413void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 8414{
c67a470b
PZ		 8415 struct drm_device *dev = dev_priv->dev;
8416 uint32_t val;
8417
c67a470b
PZ		 8418 DRM_DEBUG_KMS("Enabling package C8+\n");
8419
c67a470b
PZ		 8420 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8421 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8422 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8423 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8424 }
8425
8426 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 8427 hsw_disable_lcpll(dev_priv, true, true);
8428}
8429
a14cb6fc 8430void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 8431{
8432 struct drm_device *dev = dev_priv->dev;
8433 uint32_t val;
8434
c67a470b
PZ		 8435 DRM_DEBUG_KMS("Disabling package C8+\n");
8436
8437 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 8438 lpt_init_pch_refclk(dev);
8439
8440 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8441 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8442 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8443 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8444 }
8445
8446 intel_prepare_ddi(dev);
c67a470b
PZ		 8447}
8448
190f68c5
ACO		 8449static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8450 struct intel_crtc_state *crtc_state)
09b4ddf9 8451{
190f68c5 8452 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 8453 return -EINVAL;
716c2e55 8454
c7653199 8455 crtc->lowfreq_avail = false;
644cef34 8456
c8f7a0db 8457 return 0;
79e53945
JB		 8458}
8459
96b7dfb7
S		 8460static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8461 enum port port,
5cec258b 8462 struct intel_crtc_state *pipe_config)
96b7dfb7 8463{
3148ade7 8464 u32 temp, dpll_ctl1;
96b7dfb7
S		 8465
8466 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8467 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
8468
8469 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 8470 case SKL_DPLL0:
8471 /*
8472 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8473 * of the shared DPLL framework and thus needs to be read out
8474 * separately
8475 */
8476 dpll_ctl1 = I915_READ(DPLL_CTRL1);
8477 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
8478 break;
96b7dfb7
S		 8479 case SKL_DPLL1:
8480 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8481 break;
8482 case SKL_DPLL2:
8483 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8484 break;
8485 case SKL_DPLL3:
8486 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8487 break;
96b7dfb7
S		 8488 }
8489}
8490
7d2c8175
DL		 8491static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8492 enum port port,
5cec258b 8493 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 8494{
8495 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8496
8497 switch (pipe_config->ddi_pll_sel) {
8498 case PORT_CLK_SEL_WRPLL1:
8499 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8500 break;
8501 case PORT_CLK_SEL_WRPLL2:
8502 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8503 break;
8504 }
8505}
8506
26804afd 8507static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 8508 struct intel_crtc_state *pipe_config)
26804afd
DV		 8509{
8510 struct drm_device *dev = crtc->base.dev;
8511 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 8512 struct intel_shared_dpll *pll;
26804afd
DV		 8513 enum port port;
8514 uint32_t tmp;
8515
8516 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8517
8518 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8519
96b7dfb7
S		 8520 if (IS_SKYLAKE(dev))
8521 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8522 else
8523 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 8524
d452c5b6
DV		 8525 if (pipe_config->shared_dpll >= 0) {
8526 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8527
8528 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8529 &pipe_config->dpll_hw_state));
8530 }
8531
26804afd
DV		 8532 /*
8533 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8534 * DDI E. So just check whether this pipe is wired to DDI E and whether
8535 * the PCH transcoder is on.
8536 */
ca370455
DL		 8537 if (INTEL_INFO(dev)->gen < 9 &&
8538 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 8539 pipe_config->has_pch_encoder = true;
8540
8541 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8542 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8543 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8544
8545 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8546 }
8547}
8548
0e8ffe1b 8549static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8550 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8551{
8552 struct drm_device *dev = crtc->base.dev;
8553 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 8554 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 8555 uint32_t tmp;
8556
f458ebbc 8557 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 8558 POWER_DOMAIN_PIPE(crtc->pipe)))
8559 return false;
8560
e143a21c 8561 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 8562 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8563
eccb140b
DV		 8564 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8565 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8566 enum pipe trans_edp_pipe;
8567 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8568 default:
8569 WARN(1, "unknown pipe linked to edp transcoder\n");
8570 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8571 case TRANS_DDI_EDP_INPUT_A_ON:
8572 trans_edp_pipe = PIPE_A;
8573 break;
8574 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8575 trans_edp_pipe = PIPE_B;
8576 break;
8577 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8578 trans_edp_pipe = PIPE_C;
8579 break;
8580 }
8581
8582 if (trans_edp_pipe == crtc->pipe)
8583 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8584 }
8585
f458ebbc 8586 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 8587 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 8588 return false;
8589
eccb140b 8590 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 8591 if (!(tmp & PIPECONF_ENABLE))
8592 return false;
8593
26804afd 8594 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 8595
1bd1bd80
DV		 8596 intel_get_pipe_timings(crtc, pipe_config);
8597
2fa2fe9a 8598 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
bd2e244f
JB		 8599 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8600 if (IS_SKYLAKE(dev))
8601 skylake_get_pfit_config(crtc, pipe_config);
8602 else
8603 ironlake_get_pfit_config(crtc, pipe_config);
8604 }
88adfff1 8605
e59150dc
JB		 8606 if (IS_HASWELL(dev))
8607 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8608 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 8609
ebb69c95
CT		 8610 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8611 pipe_config->pixel_multiplier =
8612 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8613 } else {
8614 pipe_config->pixel_multiplier = 1;
8615 }
6c49f241 8616
0e8ffe1b
DV		 8617 return true;
8618}
8619
560b85bb
CW		 8620static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8621{
8622 struct drm_device *dev = crtc->dev;
8623 struct drm_i915_private *dev_priv = dev->dev_private;
8624 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 8625 uint32_t cntl = 0, size = 0;
560b85bb 8626
dc41c154 8627 if (base) {
3dd512fb
MR		 8628 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
8629 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 8630 unsigned int stride = roundup_pow_of_two(width) * 4;
8631
8632 switch (stride) {
8633 default:
8634 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8635 width, stride);
8636 stride = 256;
8637 /* fallthrough */
8638 case 256:
8639 case 512:
8640 case 1024:
8641 case 2048:
8642 break;
4b0e333e
CW		 8643 }
8644
dc41c154
VS		 8645 cntl |= CURSOR_ENABLE |
8646 CURSOR_GAMMA_ENABLE |
8647 CURSOR_FORMAT_ARGB |
8648 CURSOR_STRIDE(stride);
8649
8650 size = (height << 12) | width;
4b0e333e 8651 }
560b85bb 8652
dc41c154
VS		 8653 if (intel_crtc->cursor_cntl != 0 &&
8654 (intel_crtc->cursor_base != base ||
8655 intel_crtc->cursor_size != size ||
8656 intel_crtc->cursor_cntl != cntl)) {
8657 /* On these chipsets we can only modify the base/size/stride
8658 * whilst the cursor is disabled.
8659 */
8660 I915_WRITE(_CURACNTR, 0);
4b0e333e 8661 POSTING_READ(_CURACNTR);
dc41c154 8662 intel_crtc->cursor_cntl = 0;
4b0e333e 8663 }
560b85bb 8664
99d1f387 8665 if (intel_crtc->cursor_base != base) {
9db4a9c7 8666 I915_WRITE(_CURABASE, base);
99d1f387
VS		 8667 intel_crtc->cursor_base = base;
8668 }
4726e0b0 8669
dc41c154
VS		 8670 if (intel_crtc->cursor_size != size) {
8671 I915_WRITE(CURSIZE, size);
8672 intel_crtc->cursor_size = size;
4b0e333e 8673 }
560b85bb 8674
4b0e333e 8675 if (intel_crtc->cursor_cntl != cntl) {
4b0e333e
CW		 8676 I915_WRITE(_CURACNTR, cntl);
8677 POSTING_READ(_CURACNTR);
4b0e333e 8678 intel_crtc->cursor_cntl = cntl;
560b85bb 8679 }
560b85bb
CW		 8680}
8681
560b85bb 8682static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 8683{
8684 struct drm_device *dev = crtc->dev;
8685 struct drm_i915_private *dev_priv = dev->dev_private;
8686 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8687 int pipe = intel_crtc->pipe;
4b0e333e
CW		 8688 uint32_t cntl;
8689
8690 cntl = 0;
8691 if (base) {
8692 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 8693 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 8694 case 64:
8695 cntl |= CURSOR_MODE_64_ARGB_AX;
8696 break;
8697 case 128:
8698 cntl |= CURSOR_MODE_128_ARGB_AX;
8699 break;
8700 case 256:
8701 cntl |= CURSOR_MODE_256_ARGB_AX;
8702 break;
8703 default:
3dd512fb 8704 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 8705 return;
65a21cd6 8706 }
4b0e333e 8707 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS		 8708
8709 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8710 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 8711 }
65a21cd6 8712
8e7d688b 8713 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 8714 cntl |= CURSOR_ROTATE_180;
8715
4b0e333e
CW		 8716 if (intel_crtc->cursor_cntl != cntl) {
8717 I915_WRITE(CURCNTR(pipe), cntl);
8718 POSTING_READ(CURCNTR(pipe));
8719 intel_crtc->cursor_cntl = cntl;
65a21cd6 8720 }
4b0e333e 8721
65a21cd6 8722 /* and commit changes on next vblank */
5efb3e28
VS		 8723 I915_WRITE(CURBASE(pipe), base);
8724 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 8725
8726 intel_crtc->cursor_base = base;
65a21cd6
JB		 8727}
8728
cda4b7d3 8729/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 8730static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8731 bool on)
cda4b7d3
CW		 8732{
8733 struct drm_device *dev = crtc->dev;
8734 struct drm_i915_private *dev_priv = dev->dev_private;
8735 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8736 int pipe = intel_crtc->pipe;
3d7d6510
MR		 8737 int x = crtc->cursor_x;
8738 int y = crtc->cursor_y;
d6e4db15 8739 u32 base = 0, pos = 0;
cda4b7d3 8740
d6e4db15 8741 if (on)
cda4b7d3 8742 base = intel_crtc->cursor_addr;
cda4b7d3 8743
6e3c9717 8744 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 8745 base = 0;
8746
6e3c9717 8747 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 8748 base = 0;
8749
8750 if (x < 0) {
3dd512fb 8751 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
cda4b7d3
CW		 8752 base = 0;
8753
8754 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8755 x = -x;
8756 }
8757 pos |= x << CURSOR_X_SHIFT;
8758
8759 if (y < 0) {
3dd512fb 8760 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
cda4b7d3
CW		 8761 base = 0;
8762
8763 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8764 y = -y;
8765 }
8766 pos |= y << CURSOR_Y_SHIFT;
8767
4b0e333e 8768 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 8769 return;
8770
5efb3e28
VS		 8771 I915_WRITE(CURPOS(pipe), pos);
8772
4398ad45
VS		 8773 /* ILK+ do this automagically */
8774 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 8775 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
3dd512fb
MR		 8776 base += (intel_crtc->base.cursor->state->crtc_h *
8777 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
4398ad45
VS		 8778 }
8779
8ac54669 8780 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 8781 i845_update_cursor(crtc, base);
8782 else
8783 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 8784}
8785
dc41c154
VS		 8786static bool cursor_size_ok(struct drm_device *dev,
8787 uint32_t width, uint32_t height)
8788{
8789 if (width == 0 || height == 0)
8790 return false;
8791
8792 /*
8793 * 845g/865g are special in that they are only limited by
8794 * the width of their cursors, the height is arbitrary up to
8795 * the precision of the register. Everything else requires
8796 * square cursors, limited to a few power-of-two sizes.
8797 */
8798 if (IS_845G(dev) || IS_I865G(dev)) {
8799 if ((width & 63) != 0)
8800 return false;
8801
8802 if (width > (IS_845G(dev) ? 64 : 512))
8803 return false;
8804
8805 if (height > 1023)
8806 return false;
8807 } else {
8808 switch (width | height) {
8809 case 256:
8810 case 128:
8811 if (IS_GEN2(dev))
8812 return false;
8813 case 64:
8814 break;
8815 default:
8816 return false;
8817 }
8818 }
8819
8820 return true;
8821}
8822
79e53945 8823static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 8824 u16 *blue, uint32_t start, uint32_t size)
79e53945 8825{
7203425a 8826 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 8827 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 8828
7203425a 8829 for (i = start; i < end; i++) {
79e53945
JB		 8830 intel_crtc->lut_r[i] = red[i] >> 8;
8831 intel_crtc->lut_g[i] = green[i] >> 8;
8832 intel_crtc->lut_b[i] = blue[i] >> 8;
8833 }
8834
8835 intel_crtc_load_lut(crtc);
8836}
8837
79e53945
JB		 8838/* VESA 640x480x72Hz mode to set on the pipe */
8839static struct drm_display_mode load_detect_mode = {
8840 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8841 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8842};
8843
a8bb6818
DV		 8844struct drm_framebuffer *
8845__intel_framebuffer_create(struct drm_device *dev,
8846 struct drm_mode_fb_cmd2 *mode_cmd,
8847 struct drm_i915_gem_object *obj)
d2dff872
CW		 8848{
8849 struct intel_framebuffer *intel_fb;
8850 int ret;
8851
8852 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8853 if (!intel_fb) {
6ccb81f2 8854 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 8855 return ERR_PTR(-ENOMEM);
8856 }
8857
8858 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 8859 if (ret)
8860 goto err;
d2dff872
CW		 8861
8862 return &intel_fb->base;
dd4916c5 8863err:
6ccb81f2 8864 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 8865 kfree(intel_fb);
8866
8867 return ERR_PTR(ret);
d2dff872
CW		 8868}
8869
b5ea642a 8870static struct drm_framebuffer *
a8bb6818
DV		 8871intel_framebuffer_create(struct drm_device *dev,
8872 struct drm_mode_fb_cmd2 *mode_cmd,
8873 struct drm_i915_gem_object *obj)
8874{
8875 struct drm_framebuffer *fb;
8876 int ret;
8877
8878 ret = i915_mutex_lock_interruptible(dev);
8879 if (ret)
8880 return ERR_PTR(ret);
8881 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8882 mutex_unlock(&dev->struct_mutex);
8883
8884 return fb;
8885}
8886
d2dff872
CW		 8887static u32
8888intel_framebuffer_pitch_for_width(int width, int bpp)
8889{
8890 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8891 return ALIGN(pitch, 64);
8892}
8893
8894static u32
8895intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8896{
8897 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 8898 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 8899}
8900
8901static struct drm_framebuffer *
8902intel_framebuffer_create_for_mode(struct drm_device *dev,
8903 struct drm_display_mode *mode,
8904 int depth, int bpp)
8905{
8906 struct drm_i915_gem_object *obj;
0fed39bd 8907 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 8908
8909 obj = i915_gem_alloc_object(dev,
8910 intel_framebuffer_size_for_mode(mode, bpp));
8911 if (obj == NULL)
8912 return ERR_PTR(-ENOMEM);
8913
8914 mode_cmd.width = mode->hdisplay;
8915 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 8916 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8917 bpp);
5ca0c34a 8918 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 8919
8920 return intel_framebuffer_create(dev, &mode_cmd, obj);
8921}
8922
8923static struct drm_framebuffer *
8924mode_fits_in_fbdev(struct drm_device *dev,
8925 struct drm_display_mode *mode)
8926{
4520f53a 8927#ifdef CONFIG_DRM_I915_FBDEV
d2dff872
CW		 8928 struct drm_i915_private *dev_priv = dev->dev_private;
8929 struct drm_i915_gem_object *obj;
8930 struct drm_framebuffer *fb;
8931
4c0e5528 8932 if (!dev_priv->fbdev)
d2dff872
CW		 8933 return NULL;
8934
4c0e5528 8935 if (!dev_priv->fbdev->fb)
d2dff872
CW		 8936 return NULL;
8937
4c0e5528
DV		 8938 obj = dev_priv->fbdev->fb->obj;
8939 BUG_ON(!obj);
8940
8bcd4553 8941 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 8942 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8943 fb->bits_per_pixel))
d2dff872
CW		 8944 return NULL;
8945
01f2c773 8946 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 8947 return NULL;
8948
8949 return fb;
4520f53a
DV		 8950#else
8951 return NULL;
8952#endif
d2dff872
CW		 8953}
8954
d2434ab7 8955bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 8956 struct drm_display_mode *mode,
51fd371b
RC		 8957 struct intel_load_detect_pipe *old,
8958 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 8959{
8960 struct intel_crtc *intel_crtc;
d2434ab7
DV		 8961 struct intel_encoder *intel_encoder =
8962 intel_attached_encoder(connector);
79e53945 8963 struct drm_crtc *possible_crtc;
4ef69c7a 8964 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 8965 struct drm_crtc *crtc = NULL;
8966 struct drm_device *dev = encoder->dev;
94352cf9 8967 struct drm_framebuffer *fb;
51fd371b 8968 struct drm_mode_config *config = &dev->mode_config;
83a57153 8969 struct drm_atomic_state *state = NULL;
944b0c76 8970 struct drm_connector_state *connector_state;
51fd371b 8971 int ret, i = -1;
79e53945 8972
d2dff872 8973 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 8974 connector->base.id, connector->name,
8e329a03 8975 encoder->base.id, encoder->name);
d2dff872 8976
51fd371b
RC		 8977retry:
8978 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8979 if (ret)
8980 goto fail_unlock;
6e9f798d 8981
79e53945
JB		 8982 /*
8983 * Algorithm gets a little messy:
7a5e4805 8984 *
79e53945
JB		 8985 * - if the connector already has an assigned crtc, use it (but make
8986 * sure it's on first)
7a5e4805 8987 *
79e53945
JB		 8988 * - try to find the first unused crtc that can drive this connector,
8989 * and use that if we find one
79e53945
JB		 8990 */
8991
8992 /* See if we already have a CRTC for this connector */
8993 if (encoder->crtc) {
8994 crtc = encoder->crtc;
8261b191 8995
51fd371b 8996 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de
DV		 8997 if (ret)
8998 goto fail_unlock;
8999 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b
RC		 9000 if (ret)
9001 goto fail_unlock;
7b24056b 9002
24218aac 9003 old->dpms_mode = connector->dpms;
8261b191
CW		 9004 old->load_detect_temp = false;
9005
9006 /* Make sure the crtc and connector are running */
24218aac
DV		 9007 if (connector->dpms != DRM_MODE_DPMS_ON)
9008 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 9009
7173188d 9010 return true;
79e53945
JB		 9011 }
9012
9013 /* Find an unused one (if possible) */
70e1e0ec 9014 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 9015 i++;
9016 if (!(encoder->possible_crtcs & (1 << i)))
9017 continue;
83d65738 9018 if (possible_crtc->state->enable)
a459249c
VS		 9019 continue;
9020 /* This can occur when applying the pipe A quirk on resume. */
9021 if (to_intel_crtc(possible_crtc)->new_enabled)
9022 continue;
9023
9024 crtc = possible_crtc;
9025 break;
79e53945
JB		 9026 }
9027
9028 /*
9029 * If we didn't find an unused CRTC, don't use any.
9030 */
9031 if (!crtc) {
7173188d 9032 DRM_DEBUG_KMS("no pipe available for load-detect\n");
51fd371b 9033 goto fail_unlock;
79e53945
JB		 9034 }
9035
51fd371b
RC		 9036 ret = drm_modeset_lock(&crtc->mutex, ctx);
9037 if (ret)
4d02e2de
DV		 9038 goto fail_unlock;
9039 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9040 if (ret)
51fd371b 9041 goto fail_unlock;
fc303101
DV		 9042 intel_encoder->new_crtc = to_intel_crtc(crtc);
9043 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 9044
9045 intel_crtc = to_intel_crtc(crtc);
412b61d8 9046 intel_crtc->new_enabled = true;
6e3c9717 9047 intel_crtc->new_config = intel_crtc->config;
24218aac 9048 old->dpms_mode = connector->dpms;
8261b191 9049 old->load_detect_temp = true;
d2dff872 9050 old->release_fb = NULL;
79e53945 9051
83a57153
ACO		 9052 state = drm_atomic_state_alloc(dev);
9053 if (!state)
9054 return false;
9055
9056 state->acquire_ctx = ctx;
9057
944b0c76
ACO		 9058 connector_state = drm_atomic_get_connector_state(state, connector);
9059 if (IS_ERR(connector_state)) {
9060 ret = PTR_ERR(connector_state);
9061 goto fail;
9062 }
9063
9064 connector_state->crtc = crtc;
9065 connector_state->best_encoder = &intel_encoder->base;
9066
6492711d
CW		 9067 if (!mode)
9068 mode = &load_detect_mode;
79e53945 9069
d2dff872
CW		 9070 /* We need a framebuffer large enough to accommodate all accesses
9071 * that the plane may generate whilst we perform load detection.
9072 * We can not rely on the fbcon either being present (we get called
9073 * during its initialisation to detect all boot displays, or it may
9074 * not even exist) or that it is large enough to satisfy the
9075 * requested mode.
9076 */
94352cf9
DV		 9077 fb = mode_fits_in_fbdev(dev, mode);
9078 if (fb == NULL) {
d2dff872 9079 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 9080 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9081 old->release_fb = fb;
d2dff872
CW		 9082 } else
9083 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 9084 if (IS_ERR(fb)) {
d2dff872 9085 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 9086 goto fail;
79e53945 9087 }
79e53945 9088
83a57153 9089 if (intel_set_mode(crtc, mode, 0, 0, fb, state)) {
6492711d 9090 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 9091 if (old->release_fb)
9092 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 9093 goto fail;
79e53945 9094 }
9128b040 9095 crtc->primary->crtc = crtc;
7173188d 9096
79e53945 9097 /* let the connector get through one full cycle before testing */
9d0498a2 9098 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 9099 return true;
412b61d8
VS		 9100
9101 fail:
83d65738 9102 intel_crtc->new_enabled = crtc->state->enable;
412b61d8 9103 if (intel_crtc->new_enabled)
6e3c9717 9104 intel_crtc->new_config = intel_crtc->config;
412b61d8
VS		 9105 else
9106 intel_crtc->new_config = NULL;
51fd371b 9107fail_unlock:
83a57153
ACO		 9108 if (state) {
9109 drm_atomic_state_free(state);
9110 state = NULL;
9111 }
9112
51fd371b
RC		 9113 if (ret == -EDEADLK) {
9114 drm_modeset_backoff(ctx);
9115 goto retry;
9116 }
9117
412b61d8 9118 return false;
79e53945
JB		 9119}
9120
d2434ab7 9121void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 9122 struct intel_load_detect_pipe *old,
9123 struct drm_modeset_acquire_ctx *ctx)
79e53945 9124{
83a57153 9125 struct drm_device *dev = connector->dev;
d2434ab7
DV		 9126 struct intel_encoder *intel_encoder =
9127 intel_attached_encoder(connector);
4ef69c7a 9128 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 9129 struct drm_crtc *crtc = encoder->crtc;
412b61d8 9130 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 9131 struct drm_atomic_state *state;
944b0c76 9132 struct drm_connector_state *connector_state;
79e53945 9133
d2dff872 9134 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 9135 connector->base.id, connector->name,
8e329a03 9136 encoder->base.id, encoder->name);
d2dff872 9137
8261b191 9138 if (old->load_detect_temp) {
83a57153 9139 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 9140 if (!state)
9141 goto fail;
83a57153
ACO		 9142
9143 state->acquire_ctx = ctx;
9144
944b0c76
ACO		 9145 connector_state = drm_atomic_get_connector_state(state, connector);
9146 if (IS_ERR(connector_state))
9147 goto fail;
9148
fc303101
DV		 9149 to_intel_connector(connector)->new_encoder = NULL;
9150 intel_encoder->new_crtc = NULL;
412b61d8
VS		 9151 intel_crtc->new_enabled = false;
9152 intel_crtc->new_config = NULL;
944b0c76
ACO		 9153
9154 connector_state->best_encoder = NULL;
9155 connector_state->crtc = NULL;
9156
83a57153
ACO		 9157 intel_set_mode(crtc, NULL, 0, 0, NULL, state);
9158
9159 drm_atomic_state_free(state);
d2dff872 9160
36206361
DV		 9161 if (old->release_fb) {
9162 drm_framebuffer_unregister_private(old->release_fb);
9163 drm_framebuffer_unreference(old->release_fb);
9164 }
d2dff872 9165
0622a53c 9166 return;
79e53945
JB		 9167 }
9168
c751ce4f 9169 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 9170 if (old->dpms_mode != DRM_MODE_DPMS_ON)
9171 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 9172
9173 return;
9174fail:
9175 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
9176 drm_atomic_state_free(state);
79e53945
JB		 9177}
9178
da4a1efa 9179static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 9180 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 9181{
9182 struct drm_i915_private *dev_priv = dev->dev_private;
9183 u32 dpll = pipe_config->dpll_hw_state.dpll;
9184
9185 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 9186 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 9187 else if (HAS_PCH_SPLIT(dev))
9188 return 120000;
9189 else if (!IS_GEN2(dev))
9190 return 96000;
9191 else
9192 return 48000;
9193}
9194
79e53945 9195/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 9196static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 9197 struct intel_crtc_state *pipe_config)
79e53945 9198{
f1f644dc 9199 struct drm_device *dev = crtc->base.dev;
79e53945 9200 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 9201 int pipe = pipe_config->cpu_transcoder;
293623f7 9202 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 9203 u32 fp;
9204 intel_clock_t clock;
da4a1efa 9205 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 9206
9207 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 9208 fp = pipe_config->dpll_hw_state.fp0;
79e53945 9209 else
293623f7 9210 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 9211
9212 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 9213 if (IS_PINEVIEW(dev)) {
9214 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9215 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 9216 } else {
9217 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9218 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9219 }
9220
a6c45cf0 9221 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 9222 if (IS_PINEVIEW(dev))
9223 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9224 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 9225 else
9226 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 9227 DPLL_FPA01_P1_POST_DIV_SHIFT);
9228
9229 switch (dpll & DPLL_MODE_MASK) {
9230 case DPLLB_MODE_DAC_SERIAL:
9231 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9232 5 : 10;
9233 break;
9234 case DPLLB_MODE_LVDS:
9235 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9236 7 : 14;
9237 break;
9238 default:
28c97730 9239 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 9240 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 9241 return;
79e53945
JB		 9242 }
9243
ac58c3f0 9244 if (IS_PINEVIEW(dev))
da4a1efa 9245 pineview_clock(refclk, &clock);
ac58c3f0 9246 else
da4a1efa 9247 i9xx_clock(refclk, &clock);
79e53945 9248 } else {
0fb58223 9249 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 9250 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 9251
9252 if (is_lvds) {
9253 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9254 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 9255
9256 if (lvds & LVDS_CLKB_POWER_UP)
9257 clock.p2 = 7;
9258 else
9259 clock.p2 = 14;
79e53945
JB		 9260 } else {
9261 if (dpll & PLL_P1_DIVIDE_BY_TWO)
9262 clock.p1 = 2;
9263 else {
9264 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9265 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9266 }
9267 if (dpll & PLL_P2_DIVIDE_BY_4)
9268 clock.p2 = 4;
9269 else
9270 clock.p2 = 2;
79e53945 9271 }
da4a1efa
VS		 9272
9273 i9xx_clock(refclk, &clock);
79e53945
JB		 9274 }
9275
18442d08
VS		 9276 /*
9277 * This value includes pixel_multiplier. We will use
241bfc38 9278 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 9279 * encoder's get_config() function.
9280 */
9281 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 9282}
9283
6878da05
VS		 9284int intel_dotclock_calculate(int link_freq,
9285 const struct intel_link_m_n *m_n)
f1f644dc 9286{
f1f644dc
JB		 9287 /*
9288 * The calculation for the data clock is:
1041a02f 9289 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 9290 * But we want to avoid losing precison if possible, so:
1041a02f 9291 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 9292 *
9293 * and the link clock is simpler:
1041a02f 9294 * link_clock = (m * link_clock) / n
f1f644dc
JB		 9295 */
9296
6878da05
VS		 9297 if (!m_n->link_n)
9298 return 0;
f1f644dc 9299
6878da05
VS		 9300 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9301}
f1f644dc 9302
18442d08 9303static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 9304 struct intel_crtc_state *pipe_config)
6878da05
VS		 9305{
9306 struct drm_device *dev = crtc->base.dev;
79e53945 9307
18442d08
VS		 9308 /* read out port_clock from the DPLL */
9309 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 9310
f1f644dc 9311 /*
18442d08 9312 * This value does not include pixel_multiplier.
241bfc38 9313 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 9314 * agree once we know their relationship in the encoder's
9315 * get_config() function.
79e53945 9316 */
2d112de7 9317 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 9318 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
9319 &pipe_config->fdi_m_n);
79e53945
JB		 9320}
9321
9322/** Returns the currently programmed mode of the given pipe. */
9323struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9324 struct drm_crtc *crtc)
9325{
548f245b 9326 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 9327 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 9328 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 9329 struct drm_display_mode *mode;
5cec258b 9330 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 9331 int htot = I915_READ(HTOTAL(cpu_transcoder));
9332 int hsync = I915_READ(HSYNC(cpu_transcoder));
9333 int vtot = I915_READ(VTOTAL(cpu_transcoder));
9334 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 9335 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 9336
9337 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9338 if (!mode)
9339 return NULL;
9340
f1f644dc
JB		 9341 /*
9342 * Construct a pipe_config sufficient for getting the clock info
9343 * back out of crtc_clock_get.
9344 *
9345 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9346 * to use a real value here instead.
9347 */
293623f7 9348 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 9349 pipe_config.pixel_multiplier = 1;
293623f7
VS		 9350 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9351 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9352 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 9353 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
9354
773ae034 9355 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 9356 mode->hdisplay = (htot & 0xffff) + 1;
9357 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9358 mode->hsync_start = (hsync & 0xffff) + 1;
9359 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9360 mode->vdisplay = (vtot & 0xffff) + 1;
9361 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9362 mode->vsync_start = (vsync & 0xffff) + 1;
9363 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9364
9365 drm_mode_set_name(mode);
79e53945
JB		 9366
9367 return mode;
9368}
9369
652c393a
JB		 9370static void intel_decrease_pllclock(struct drm_crtc *crtc)
9371{
9372 struct drm_device *dev = crtc->dev;
fbee40df 9373 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 9374 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 9375
baff296c 9376 if (!HAS_GMCH_DISPLAY(dev))
652c393a
JB		 9377 return;
9378
9379 if (!dev_priv->lvds_downclock_avail)
9380 return;
9381
9382 /*
9383 * Since this is called by a timer, we should never get here in
9384 * the manual case.
9385 */
9386 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 9387 int pipe = intel_crtc->pipe;
9388 int dpll_reg = DPLL(pipe);
9389 int dpll;
f6e5b160 9390
44d98a61 9391 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 9392
8ac5a6d5 9393 assert_panel_unlocked(dev_priv, pipe);
652c393a 9394
dc257cf1 9395 dpll = I915_READ(dpll_reg);
652c393a
JB		 9396 dpll |= DISPLAY_RATE_SELECT_FPA1;
9397 I915_WRITE(dpll_reg, dpll);
9d0498a2 9398 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 9399 dpll = I915_READ(dpll_reg);
9400 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 9401 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 9402 }
9403
9404}
9405
f047e395
CW		 9406void intel_mark_busy(struct drm_device *dev)
9407{
c67a470b
PZ		 9408 struct drm_i915_private *dev_priv = dev->dev_private;
9409
f62a0076
CW		 9410 if (dev_priv->mm.busy)
9411 return;
9412
43694d69 9413 intel_runtime_pm_get(dev_priv);
c67a470b 9414 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 9415 if (INTEL_INFO(dev)->gen >= 6)
9416 gen6_rps_busy(dev_priv);
f62a0076 9417 dev_priv->mm.busy = true;
f047e395
CW		 9418}
9419
9420void intel_mark_idle(struct drm_device *dev)
652c393a 9421{
c67a470b 9422 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 9423 struct drm_crtc *crtc;
652c393a 9424
f62a0076
CW		 9425 if (!dev_priv->mm.busy)
9426 return;
9427
9428 dev_priv->mm.busy = false;
9429
70e1e0ec 9430 for_each_crtc(dev, crtc) {
f4510a27 9431 if (!crtc->primary->fb)
652c393a
JB		 9432 continue;
9433
725a5b54 9434 intel_decrease_pllclock(crtc);
652c393a 9435 }
b29c19b6 9436
3d13ef2e 9437 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 9438 gen6_rps_idle(dev->dev_private);
bb4cdd53 9439
43694d69 9440 intel_runtime_pm_put(dev_priv);
652c393a
JB		 9441}
9442
f5de6e07
ACO		 9443static void intel_crtc_set_state(struct intel_crtc *crtc,
9444 struct intel_crtc_state *crtc_state)
9445{
9446 kfree(crtc->config);
9447 crtc->config = crtc_state;
16f3f658 9448 crtc->base.state = &crtc_state->base;
f5de6e07
ACO		 9449}
9450
79e53945
JB		 9451static void intel_crtc_destroy(struct drm_crtc *crtc)
9452{
9453 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 9454 struct drm_device *dev = crtc->dev;
9455 struct intel_unpin_work *work;
67e77c5a 9456
5e2d7afc 9457 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 9458 work = intel_crtc->unpin_work;
9459 intel_crtc->unpin_work = NULL;
5e2d7afc 9460 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 9461
9462 if (work) {
9463 cancel_work_sync(&work->work);
9464 kfree(work);
9465 }
79e53945 9466
f5de6e07 9467 intel_crtc_set_state(intel_crtc, NULL);
79e53945 9468 drm_crtc_cleanup(crtc);
67e77c5a 9469
79e53945
JB		 9470 kfree(intel_crtc);
9471}
9472
6b95a207
KH		 9473static void intel_unpin_work_fn(struct work_struct *__work)
9474{
9475 struct intel_unpin_work *work =
9476 container_of(__work, struct intel_unpin_work, work);
b4a98e57 9477 struct drm_device *dev = work->crtc->dev;
f99d7069 9478 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
6b95a207 9479
b4a98e57 9480 mutex_lock(&dev->struct_mutex);
82bc3b2d 9481 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
05394f39 9482 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 9483
7ff0ebcc 9484 intel_fbc_update(dev);
f06cc1b9
JH		 9485
9486 if (work->flip_queued_req)
146d84f0 9487 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 9488 mutex_unlock(&dev->struct_mutex);
9489
f99d7069 9490 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
89ed88ba 9491 drm_framebuffer_unreference(work->old_fb);
f99d7069 9492
b4a98e57
CW		 9493 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9494 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9495
6b95a207
KH		 9496 kfree(work);
9497}
9498
1afe3e9d 9499static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 9500 struct drm_crtc *crtc)
6b95a207 9501{
6b95a207
KH		 9502 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9503 struct intel_unpin_work *work;
6b95a207
KH		 9504 unsigned long flags;
9505
9506 /* Ignore early vblank irqs */
9507 if (intel_crtc == NULL)
9508 return;
9509
f326038a
DV		 9510 /*
9511 * This is called both by irq handlers and the reset code (to complete
9512 * lost pageflips) so needs the full irqsave spinlocks.
9513 */
6b95a207
KH		 9514 spin_lock_irqsave(&dev->event_lock, flags);
9515 work = intel_crtc->unpin_work;
e7d841ca
CW		 9516
9517 /* Ensure we don't miss a work->pending update ... */
9518 smp_rmb();
9519
9520 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 9521 spin_unlock_irqrestore(&dev->event_lock, flags);
9522 return;
9523 }
9524
d6bbafa1 9525 page_flip_completed(intel_crtc);
0af7e4df 9526
6b95a207 9527 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 9528}
9529
1afe3e9d
JB		 9530void intel_finish_page_flip(struct drm_device *dev, int pipe)
9531{
fbee40df 9532 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 9533 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9534
49b14a5c 9535 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 9536}
9537
9538void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9539{
fbee40df 9540 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 9541 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9542
49b14a5c 9543 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 9544}
9545
75f7f3ec
VS		 9546/* Is 'a' after or equal to 'b'? */
9547static bool g4x_flip_count_after_eq(u32 a, u32 b)
9548{
9549 return !((a - b) & 0x80000000);
9550}
9551
9552static bool page_flip_finished(struct intel_crtc *crtc)
9553{
9554 struct drm_device *dev = crtc->base.dev;
9555 struct drm_i915_private *dev_priv = dev->dev_private;
9556
bdfa7542
VS		 9557 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9558 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9559 return true;
9560
75f7f3ec
VS		 9561 /*
9562 * The relevant registers doen't exist on pre-ctg.
9563 * As the flip done interrupt doesn't trigger for mmio
9564 * flips on gmch platforms, a flip count check isn't
9565 * really needed there. But since ctg has the registers,
9566 * include it in the check anyway.
9567 */
9568 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9569 return true;
9570
9571 /*
9572 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9573 * used the same base address. In that case the mmio flip might
9574 * have completed, but the CS hasn't even executed the flip yet.
9575 *
9576 * A flip count check isn't enough as the CS might have updated
9577 * the base address just after start of vblank, but before we
9578 * managed to process the interrupt. This means we'd complete the
9579 * CS flip too soon.
9580 *
9581 * Combining both checks should get us a good enough result. It may
9582 * still happen that the CS flip has been executed, but has not
9583 * yet actually completed. But in case the base address is the same
9584 * anyway, we don't really care.
9585 */
9586 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9587 crtc->unpin_work->gtt_offset &&
9588 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9589 crtc->unpin_work->flip_count);
9590}
9591
6b95a207
KH		 9592void intel_prepare_page_flip(struct drm_device *dev, int plane)
9593{
fbee40df 9594 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 9595 struct intel_crtc *intel_crtc =
9596 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9597 unsigned long flags;
9598
f326038a
DV		 9599
9600 /*
9601 * This is called both by irq handlers and the reset code (to complete
9602 * lost pageflips) so needs the full irqsave spinlocks.
9603 *
9604 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 9605 * generate a page-flip completion irq, i.e. every modeset
9606 * is also accompanied by a spurious intel_prepare_page_flip().
9607 */
6b95a207 9608 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 9609 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 9610 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 9611 spin_unlock_irqrestore(&dev->event_lock, flags);
9612}
9613
eba905b2 9614static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW		 9615{
9616 /* Ensure that the work item is consistent when activating it ... */
9617 smp_wmb();
9618 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9619 /* and that it is marked active as soon as the irq could fire. */
9620 smp_wmb();
9621}
9622
8c9f3aaf
JB		 9623static int intel_gen2_queue_flip(struct drm_device *dev,
9624 struct drm_crtc *crtc,
9625 struct drm_framebuffer *fb,
ed8d1975 9626 struct drm_i915_gem_object *obj,
a4872ba6 9627 struct intel_engine_cs *ring,
ed8d1975 9628 uint32_t flags)
8c9f3aaf 9629{
8c9f3aaf 9630 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 9631 u32 flip_mask;
9632 int ret;
9633
6d90c952 9634 ret = intel_ring_begin(ring, 6);
8c9f3aaf 9635 if (ret)
4fa62c89 9636 return ret;
8c9f3aaf
JB		 9637
9638 /* Can't queue multiple flips, so wait for the previous
9639 * one to finish before executing the next.
9640 */
9641 if (intel_crtc->plane)
9642 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9643 else
9644 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 9645 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9646 intel_ring_emit(ring, MI_NOOP);
9647 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9648 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9649 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 9650 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 9651 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 9652
9653 intel_mark_page_flip_active(intel_crtc);
09246732 9654 __intel_ring_advance(ring);
83d4092b 9655 return 0;
8c9f3aaf
JB		 9656}
9657
9658static int intel_gen3_queue_flip(struct drm_device *dev,
9659 struct drm_crtc *crtc,
9660 struct drm_framebuffer *fb,
ed8d1975 9661 struct drm_i915_gem_object *obj,
a4872ba6 9662 struct intel_engine_cs *ring,
ed8d1975 9663 uint32_t flags)
8c9f3aaf 9664{
8c9f3aaf 9665 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 9666 u32 flip_mask;
9667 int ret;
9668
6d90c952 9669 ret = intel_ring_begin(ring, 6);
8c9f3aaf 9670 if (ret)
4fa62c89 9671 return ret;
8c9f3aaf
JB		 9672
9673 if (intel_crtc->plane)
9674 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9675 else
9676 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 9677 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9678 intel_ring_emit(ring, MI_NOOP);
9679 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9680 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9681 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 9682 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 9683 intel_ring_emit(ring, MI_NOOP);
9684
e7d841ca 9685 intel_mark_page_flip_active(intel_crtc);
09246732 9686 __intel_ring_advance(ring);
83d4092b 9687 return 0;
8c9f3aaf
JB		 9688}
9689
9690static int intel_gen4_queue_flip(struct drm_device *dev,
9691 struct drm_crtc *crtc,
9692 struct drm_framebuffer *fb,
ed8d1975 9693 struct drm_i915_gem_object *obj,
a4872ba6 9694 struct intel_engine_cs *ring,
ed8d1975 9695 uint32_t flags)
8c9f3aaf
JB		 9696{
9697 struct drm_i915_private *dev_priv = dev->dev_private;
9698 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9699 uint32_t pf, pipesrc;
9700 int ret;
9701
6d90c952 9702 ret = intel_ring_begin(ring, 4);
8c9f3aaf 9703 if (ret)
4fa62c89 9704 return ret;
8c9f3aaf
JB		 9705
9706 /* i965+ uses the linear or tiled offsets from the
9707 * Display Registers (which do not change across a page-flip)
9708 * so we need only reprogram the base address.
9709 */
6d90c952
DV		 9710 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9711 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9712 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 9713 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 9714 obj->tiling_mode);
8c9f3aaf
JB		 9715
9716 /* XXX Enabling the panel-fitter across page-flip is so far
9717 * untested on non-native modes, so ignore it for now.
9718 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9719 */
9720 pf = 0;
9721 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 9722 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 9723
9724 intel_mark_page_flip_active(intel_crtc);
09246732 9725 __intel_ring_advance(ring);
83d4092b 9726 return 0;
8c9f3aaf
JB		 9727}
9728
9729static int intel_gen6_queue_flip(struct drm_device *dev,
9730 struct drm_crtc *crtc,
9731 struct drm_framebuffer *fb,
ed8d1975 9732 struct drm_i915_gem_object *obj,
a4872ba6 9733 struct intel_engine_cs *ring,
ed8d1975 9734 uint32_t flags)
8c9f3aaf
JB		 9735{
9736 struct drm_i915_private *dev_priv = dev->dev_private;
9737 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9738 uint32_t pf, pipesrc;
9739 int ret;
9740
6d90c952 9741 ret = intel_ring_begin(ring, 4);
8c9f3aaf 9742 if (ret)
4fa62c89 9743 return ret;
8c9f3aaf 9744
6d90c952
DV		 9745 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9746 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9747 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 9748 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 9749
dc257cf1
DV		 9750 /* Contrary to the suggestions in the documentation,
9751 * "Enable Panel Fitter" does not seem to be required when page
9752 * flipping with a non-native mode, and worse causes a normal
9753 * modeset to fail.
9754 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9755 */
9756 pf = 0;
8c9f3aaf 9757 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 9758 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 9759
9760 intel_mark_page_flip_active(intel_crtc);
09246732 9761 __intel_ring_advance(ring);
83d4092b 9762 return 0;
8c9f3aaf
JB		 9763}
9764
7c9017e5
JB		 9765static int intel_gen7_queue_flip(struct drm_device *dev,
9766 struct drm_crtc *crtc,
9767 struct drm_framebuffer *fb,
ed8d1975 9768 struct drm_i915_gem_object *obj,
a4872ba6 9769 struct intel_engine_cs *ring,
ed8d1975 9770 uint32_t flags)
7c9017e5 9771{
7c9017e5 9772 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 9773 uint32_t plane_bit = 0;
ffe74d75
CW		 9774 int len, ret;
9775
eba905b2 9776 switch (intel_crtc->plane) {
cb05d8de
DV		 9777 case PLANE_A:
9778 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9779 break;
9780 case PLANE_B:
9781 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9782 break;
9783 case PLANE_C:
9784 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9785 break;
9786 default:
9787 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 9788 return -ENODEV;
cb05d8de
DV		 9789 }
9790
ffe74d75 9791 len = 4;
f476828a 9792 if (ring->id == RCS) {
ffe74d75 9793 len += 6;
f476828a
DL		 9794 /*
9795 * On Gen 8, SRM is now taking an extra dword to accommodate
9796 * 48bits addresses, and we need a NOOP for the batch size to
9797 * stay even.
9798 */
9799 if (IS_GEN8(dev))
9800 len += 2;
9801 }
ffe74d75 9802
f66fab8e
VS		 9803 /*
9804 * BSpec MI_DISPLAY_FLIP for IVB:
9805 * "The full packet must be contained within the same cache line."
9806 *
9807 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9808 * cacheline, if we ever start emitting more commands before
9809 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9810 * then do the cacheline alignment, and finally emit the
9811 * MI_DISPLAY_FLIP.
9812 */
9813 ret = intel_ring_cacheline_align(ring);
9814 if (ret)
4fa62c89 9815 return ret;
f66fab8e 9816
ffe74d75 9817 ret = intel_ring_begin(ring, len);
7c9017e5 9818 if (ret)
4fa62c89 9819 return ret;
7c9017e5 9820
ffe74d75
CW		 9821 /* Unmask the flip-done completion message. Note that the bspec says that
9822 * we should do this for both the BCS and RCS, and that we must not unmask
9823 * more than one flip event at any time (or ensure that one flip message
9824 * can be sent by waiting for flip-done prior to queueing new flips).
9825 * Experimentation says that BCS works despite DERRMR masking all
9826 * flip-done completion events and that unmasking all planes at once
9827 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9828 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9829 */
9830 if (ring->id == RCS) {
9831 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9832 intel_ring_emit(ring, DERRMR);
9833 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9834 DERRMR_PIPEB_PRI_FLIP_DONE |
9835 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a
DL		 9836 if (IS_GEN8(dev))
9837 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9838 MI_SRM_LRM_GLOBAL_GTT);
9839 else
9840 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9841 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 9842 intel_ring_emit(ring, DERRMR);
9843 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 9844 if (IS_GEN8(dev)) {
9845 intel_ring_emit(ring, 0);
9846 intel_ring_emit(ring, MI_NOOP);
9847 }
ffe74d75
CW		 9848 }
9849
cb05d8de 9850 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 9851 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 9852 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 9853 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 9854
9855 intel_mark_page_flip_active(intel_crtc);
09246732 9856 __intel_ring_advance(ring);
83d4092b 9857 return 0;
7c9017e5
JB		 9858}
9859
84c33a64
SG		 9860static bool use_mmio_flip(struct intel_engine_cs *ring,
9861 struct drm_i915_gem_object *obj)
9862{
9863 /*
9864 * This is not being used for older platforms, because
9865 * non-availability of flip done interrupt forces us to use
9866 * CS flips. Older platforms derive flip done using some clever
9867 * tricks involving the flip_pending status bits and vblank irqs.
9868 * So using MMIO flips there would disrupt this mechanism.
9869 */
9870
8e09bf83
CW		 9871 if (ring == NULL)
9872 return true;
9873
84c33a64
SG		 9874 if (INTEL_INFO(ring->dev)->gen < 5)
9875 return false;
9876
9877 if (i915.use_mmio_flip < 0)
9878 return false;
9879 else if (i915.use_mmio_flip > 0)
9880 return true;
14bf993e
OM		 9881 else if (i915.enable_execlists)
9882 return true;
84c33a64 9883 else
41c52415 9884 return ring != i915_gem_request_get_ring(obj->last_read_req);
84c33a64
SG		 9885}
9886
ff944564
DL		 9887static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
9888{
9889 struct drm_device *dev = intel_crtc->base.dev;
9890 struct drm_i915_private *dev_priv = dev->dev_private;
9891 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
9892 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9893 struct drm_i915_gem_object *obj = intel_fb->obj;
9894 const enum pipe pipe = intel_crtc->pipe;
9895 u32 ctl, stride;
9896
9897 ctl = I915_READ(PLANE_CTL(pipe, 0));
9898 ctl &= ~PLANE_CTL_TILED_MASK;
9899 if (obj->tiling_mode == I915_TILING_X)
9900 ctl |= PLANE_CTL_TILED_X;
9901
9902 /*
9903 * The stride is either expressed as a multiple of 64 bytes chunks for
9904 * linear buffers or in number of tiles for tiled buffers.
9905 */
9906 stride = fb->pitches[0] >> 6;
9907 if (obj->tiling_mode == I915_TILING_X)
9908 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
9909
9910 /*
9911 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9912 * PLANE_SURF updates, the update is then guaranteed to be atomic.
9913 */
9914 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
9915 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
9916
9917 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
9918 POSTING_READ(PLANE_SURF(pipe, 0));
9919}
9920
9921static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG		 9922{
9923 struct drm_device *dev = intel_crtc->base.dev;
9924 struct drm_i915_private *dev_priv = dev->dev_private;
9925 struct intel_framebuffer *intel_fb =
9926 to_intel_framebuffer(intel_crtc->base.primary->fb);
9927 struct drm_i915_gem_object *obj = intel_fb->obj;
9928 u32 dspcntr;
9929 u32 reg;
9930
84c33a64
SG		 9931 reg = DSPCNTR(intel_crtc->plane);
9932 dspcntr = I915_READ(reg);
9933
c5d97472
DL		 9934 if (obj->tiling_mode != I915_TILING_NONE)
9935 dspcntr |= DISPPLANE_TILED;
9936 else
9937 dspcntr &= ~DISPPLANE_TILED;
9938
84c33a64
SG		 9939 I915_WRITE(reg, dspcntr);
9940
9941 I915_WRITE(DSPSURF(intel_crtc->plane),
9942 intel_crtc->unpin_work->gtt_offset);
9943 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 9944
ff944564
DL		 9945}
9946
9947/*
9948 * XXX: This is the temporary way to update the plane registers until we get
9949 * around to using the usual plane update functions for MMIO flips
9950 */
9951static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9952{
9953 struct drm_device *dev = intel_crtc->base.dev;
9954 bool atomic_update;
9955 u32 start_vbl_count;
9956
9957 intel_mark_page_flip_active(intel_crtc);
9958
9959 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9960
9961 if (INTEL_INFO(dev)->gen >= 9)
9962 skl_do_mmio_flip(intel_crtc);
9963 else
9964 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9965 ilk_do_mmio_flip(intel_crtc);
9966
9362c7c5
ACO		 9967 if (atomic_update)
9968 intel_pipe_update_end(intel_crtc, start_vbl_count);
84c33a64
SG		 9969}
9970
9362c7c5 9971static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 9972{
cc8c4cc2 9973 struct intel_crtc *crtc =
9362c7c5 9974 container_of(work, struct intel_crtc, mmio_flip.work);
cc8c4cc2 9975 struct intel_mmio_flip *mmio_flip;
84c33a64 9976
cc8c4cc2
JH		 9977 mmio_flip = &crtc->mmio_flip;
9978 if (mmio_flip->req)
9c654818
JH		 9979 WARN_ON(__i915_wait_request(mmio_flip->req,
9980 crtc->reset_counter,
9981 false, NULL, NULL) != 0);
84c33a64 9982
cc8c4cc2
JH		 9983 intel_do_mmio_flip(crtc);
9984 if (mmio_flip->req) {
9985 mutex_lock(&crtc->base.dev->struct_mutex);
146d84f0 9986 i915_gem_request_assign(&mmio_flip->req, NULL);
cc8c4cc2
JH		 9987 mutex_unlock(&crtc->base.dev->struct_mutex);
9988 }
84c33a64
SG		 9989}
9990
9991static int intel_queue_mmio_flip(struct drm_device *dev,
9992 struct drm_crtc *crtc,
9993 struct drm_framebuffer *fb,
9994 struct drm_i915_gem_object *obj,
9995 struct intel_engine_cs *ring,
9996 uint32_t flags)
9997{
84c33a64 9998 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
84c33a64 9999
cc8c4cc2
JH		 10000 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
10001 obj->last_write_req);
536f5b5e
ACO		 10002
10003 schedule_work(&intel_crtc->mmio_flip.work);
84c33a64 10004
84c33a64
SG		 10005 return 0;
10006}
10007
8c9f3aaf
JB		 10008static int intel_default_queue_flip(struct drm_device *dev,
10009 struct drm_crtc *crtc,
10010 struct drm_framebuffer *fb,
ed8d1975 10011 struct drm_i915_gem_object *obj,
a4872ba6 10012 struct intel_engine_cs *ring,
ed8d1975 10013 uint32_t flags)
8c9f3aaf
JB		 10014{
10015 return -ENODEV;
10016}
10017
d6bbafa1
CW		 10018static bool __intel_pageflip_stall_check(struct drm_device *dev,
10019 struct drm_crtc *crtc)
10020{
10021 struct drm_i915_private *dev_priv = dev->dev_private;
10022 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10023 struct intel_unpin_work *work = intel_crtc->unpin_work;
10024 u32 addr;
10025
10026 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
10027 return true;
10028
10029 if (!work->enable_stall_check)
10030 return false;
10031
10032 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 10033 if (work->flip_queued_req &&
10034 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 10035 return false;
10036
1e3feefd 10037 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 10038 }
10039
1e3feefd 10040 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 10041 return false;
10042
10043 /* Potential stall - if we see that the flip has happened,
10044 * assume a missed interrupt. */
10045 if (INTEL_INFO(dev)->gen >= 4)
10046 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
10047 else
10048 addr = I915_READ(DSPADDR(intel_crtc->plane));
10049
10050 /* There is a potential issue here with a false positive after a flip
10051 * to the same address. We could address this by checking for a
10052 * non-incrementing frame counter.
10053 */
10054 return addr == work->gtt_offset;
10055}
10056
10057void intel_check_page_flip(struct drm_device *dev, int pipe)
10058{
10059 struct drm_i915_private *dev_priv = dev->dev_private;
10060 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10061 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
f326038a 10062
6c51d46f 10063 WARN_ON(!in_interrupt());
d6bbafa1
CW		 10064
10065 if (crtc == NULL)
10066 return;
10067
f326038a 10068 spin_lock(&dev->event_lock);
d6bbafa1
CW		 10069 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
10070 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
1e3feefd
DV		 10071 intel_crtc->unpin_work->flip_queued_vblank,
10072 drm_vblank_count(dev, pipe));
d6bbafa1
CW		 10073 page_flip_completed(intel_crtc);
10074 }
f326038a 10075 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 10076}
10077
6b95a207
KH		 10078static int intel_crtc_page_flip(struct drm_crtc *crtc,
10079 struct drm_framebuffer *fb,
ed8d1975
KP		 10080 struct drm_pending_vblank_event *event,
10081 uint32_t page_flip_flags)
6b95a207
KH		 10082{
10083 struct drm_device *dev = crtc->dev;
10084 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 10085 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 10086 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 10087 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 10088 struct drm_plane *primary = crtc->primary;
a071fa00 10089 enum pipe pipe = intel_crtc->pipe;
6b95a207 10090 struct intel_unpin_work *work;
a4872ba6 10091 struct intel_engine_cs *ring;
52e68630 10092 int ret;
6b95a207 10093
2ff8fde1
MR		 10094 /*
10095 * drm_mode_page_flip_ioctl() should already catch this, but double
10096 * check to be safe. In the future we may enable pageflipping from
10097 * a disabled primary plane.
10098 */
10099 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10100 return -EBUSY;
10101
e6a595d2 10102 /* Can't change pixel format via MI display flips. */
f4510a27 10103 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 10104 return -EINVAL;
10105
10106 /*
10107 * TILEOFF/LINOFF registers can't be changed via MI display flips.
10108 * Note that pitch changes could also affect these register.
10109 */
10110 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 10111 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10112 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 10113 return -EINVAL;
10114
f900db47
CW		 10115 if (i915_terminally_wedged(&dev_priv->gpu_error))
10116 goto out_hang;
10117
b14c5679 10118 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 10119 if (work == NULL)
10120 return -ENOMEM;
10121
6b95a207 10122 work->event = event;
b4a98e57 10123 work->crtc = crtc;
ab8d6675 10124 work->old_fb = old_fb;
6b95a207
KH		 10125 INIT_WORK(&work->work, intel_unpin_work_fn);
10126
87b6b101 10127 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 10128 if (ret)
10129 goto free_work;
10130
6b95a207 10131 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 10132 spin_lock_irq(&dev->event_lock);
6b95a207 10133 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 10134 /* Before declaring the flip queue wedged, check if
10135 * the hardware completed the operation behind our backs.
10136 */
10137 if (__intel_pageflip_stall_check(dev, crtc)) {
10138 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10139 page_flip_completed(intel_crtc);
10140 } else {
10141 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 10142 spin_unlock_irq(&dev->event_lock);
468f0b44 10143
d6bbafa1
CW		 10144 drm_crtc_vblank_put(crtc);
10145 kfree(work);
10146 return -EBUSY;
10147 }
6b95a207
KH		 10148 }
10149 intel_crtc->unpin_work = work;
5e2d7afc 10150 spin_unlock_irq(&dev->event_lock);
6b95a207 10151
b4a98e57
CW		 10152 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10153 flush_workqueue(dev_priv->wq);
10154
75dfca80 10155 /* Reference the objects for the scheduled work. */
ab8d6675 10156 drm_framebuffer_reference(work->old_fb);
05394f39 10157 drm_gem_object_reference(&obj->base);
6b95a207 10158
f4510a27 10159 crtc->primary->fb = fb;
afd65eb4 10160 update_state_fb(crtc->primary);
1ed1f968 10161
e1f99ce6 10162 work->pending_flip_obj = obj;
e1f99ce6 10163
89ed88ba
CW		 10164 ret = i915_mutex_lock_interruptible(dev);
10165 if (ret)
10166 goto cleanup;
10167
b4a98e57 10168 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 10169 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 10170
75f7f3ec 10171 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 10172 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 10173
4fa62c89
VS		 10174 if (IS_VALLEYVIEW(dev)) {
10175 ring = &dev_priv->ring[BCS];
ab8d6675 10176 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 10177 /* vlv: DISPLAY_FLIP fails to change tiling */
10178 ring = NULL;
48bf5b2d 10179 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 10180 ring = &dev_priv->ring[BCS];
4fa62c89 10181 } else if (INTEL_INFO(dev)->gen >= 7) {
41c52415 10182 ring = i915_gem_request_get_ring(obj->last_read_req);
4fa62c89
VS		 10183 if (ring == NULL || ring->id != RCS)
10184 ring = &dev_priv->ring[BCS];
10185 } else {
10186 ring = &dev_priv->ring[RCS];
10187 }
10188
82bc3b2d
TU		 10189 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
10190 crtc->primary->state, ring);
8c9f3aaf
JB		 10191 if (ret)
10192 goto cleanup_pending;
6b95a207 10193
121920fa
TU		 10194 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
10195 + intel_crtc->dspaddr_offset;
4fa62c89 10196
d6bbafa1 10197 if (use_mmio_flip(ring, obj)) {
84c33a64
SG		 10198 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
10199 page_flip_flags);
d6bbafa1
CW		 10200 if (ret)
10201 goto cleanup_unpin;
10202
f06cc1b9
JH		 10203 i915_gem_request_assign(&work->flip_queued_req,
10204 obj->last_write_req);
d6bbafa1 10205 } else {
84c33a64 10206 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
d6bbafa1
CW		 10207 page_flip_flags);
10208 if (ret)
10209 goto cleanup_unpin;
10210
f06cc1b9
JH		 10211 i915_gem_request_assign(&work->flip_queued_req,
10212 intel_ring_get_request(ring));
d6bbafa1
CW		 10213 }
10214
1e3feefd 10215 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 10216 work->enable_stall_check = true;
4fa62c89 10217
ab8d6675 10218 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a071fa00
DV		 10219 INTEL_FRONTBUFFER_PRIMARY(pipe));
10220
7ff0ebcc 10221 intel_fbc_disable(dev);
f99d7069 10222 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
6b95a207
KH		 10223 mutex_unlock(&dev->struct_mutex);
10224
e5510fac
JB		 10225 trace_i915_flip_request(intel_crtc->plane, obj);
10226
6b95a207 10227 return 0;
96b099fd 10228
4fa62c89 10229cleanup_unpin:
82bc3b2d 10230 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 10231cleanup_pending:
b4a98e57 10232 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 10233 mutex_unlock(&dev->struct_mutex);
10234cleanup:
f4510a27 10235 crtc->primary->fb = old_fb;
afd65eb4 10236 update_state_fb(crtc->primary);
89ed88ba
CW		 10237
10238 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 10239 drm_framebuffer_unreference(work->old_fb);
96b099fd 10240
5e2d7afc 10241 spin_lock_irq(&dev->event_lock);
96b099fd 10242 intel_crtc->unpin_work = NULL;
5e2d7afc 10243 spin_unlock_irq(&dev->event_lock);
96b099fd 10244
87b6b101 10245 drm_crtc_vblank_put(crtc);
7317c75e 10246free_work:
96b099fd
CW		 10247 kfree(work);
10248
f900db47
CW		 10249 if (ret == -EIO) {
10250out_hang:
53a366b9 10251 ret = intel_plane_restore(primary);
f0d3dad3 10252 if (ret == 0 && event) {
5e2d7afc 10253 spin_lock_irq(&dev->event_lock);
a071fa00 10254 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 10255 spin_unlock_irq(&dev->event_lock);
f0d3dad3 10256 }
f900db47 10257 }
96b099fd 10258 return ret;
6b95a207
KH		 10259}
10260
f6e5b160 10261static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 10262 .mode_set_base_atomic = intel_pipe_set_base_atomic,
10263 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 10264 .atomic_begin = intel_begin_crtc_commit,
10265 .atomic_flush = intel_finish_crtc_commit,
f6e5b160
CW		 10266};
10267
9a935856
DV		 10268/**
10269 * intel_modeset_update_staged_output_state
10270 *
10271 * Updates the staged output configuration state, e.g. after we've read out the
10272 * current hw state.
10273 */
10274static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 10275{
7668851f 10276 struct intel_crtc *crtc;
9a935856
DV		 10277 struct intel_encoder *encoder;
10278 struct intel_connector *connector;
f6e5b160 10279
3a3371ff 10280 for_each_intel_connector(dev, connector) {
9a935856
DV		 10281 connector->new_encoder =
10282 to_intel_encoder(connector->base.encoder);
10283 }
f6e5b160 10284
b2784e15 10285 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 10286 encoder->new_crtc =
10287 to_intel_crtc(encoder->base.crtc);
10288 }
7668851f 10289
d3fcc808 10290 for_each_intel_crtc(dev, crtc) {
83d65738 10291 crtc->new_enabled = crtc->base.state->enable;
7bd0a8e7
VS		 10292
10293 if (crtc->new_enabled)
6e3c9717 10294 crtc->new_config = crtc->config;
7bd0a8e7
VS		 10295 else
10296 crtc->new_config = NULL;
7668851f 10297 }
f6e5b160
CW		 10298}
10299
d29b2f9d
ACO		 10300/* Transitional helper to copy current connector/encoder state to
10301 * connector->state. This is needed so that code that is partially
10302 * converted to atomic does the right thing.
10303 */
10304static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
10305{
10306 struct intel_connector *connector;
10307
10308 for_each_intel_connector(dev, connector) {
10309 if (connector->base.encoder) {
10310 connector->base.state->best_encoder =
10311 connector->base.encoder;
10312 connector->base.state->crtc =
10313 connector->base.encoder->crtc;
10314 } else {
10315 connector->base.state->best_encoder = NULL;
10316 connector->base.state->crtc = NULL;
10317 }
10318 }
10319}
10320
9a935856
DV		 10321/**
10322 * intel_modeset_commit_output_state
10323 *
10324 * This function copies the stage display pipe configuration to the real one.
10325 */
10326static void intel_modeset_commit_output_state(struct drm_device *dev)
10327{
7668851f 10328 struct intel_crtc *crtc;
9a935856
DV		 10329 struct intel_encoder *encoder;
10330 struct intel_connector *connector;
f6e5b160 10331
3a3371ff 10332 for_each_intel_connector(dev, connector) {
9a935856
DV		 10333 connector->base.encoder = &connector->new_encoder->base;
10334 }
f6e5b160 10335
b2784e15 10336 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 10337 encoder->base.crtc = &encoder->new_crtc->base;
10338 }
7668851f 10339
d3fcc808 10340 for_each_intel_crtc(dev, crtc) {
83d65738 10341 crtc->base.state->enable = crtc->new_enabled;
7668851f
VS		 10342 crtc->base.enabled = crtc->new_enabled;
10343 }
d29b2f9d
ACO		 10344
10345 intel_modeset_update_connector_atomic_state(dev);
9a935856
DV		 10346}
10347
050f7aeb 10348static void
eba905b2 10349connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 10350 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 10351{
10352 int bpp = pipe_config->pipe_bpp;
10353
10354 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10355 connector->base.base.id,
c23cc417 10356 connector->base.name);
050f7aeb
DV		 10357
10358 /* Don't use an invalid EDID bpc value */
10359 if (connector->base.display_info.bpc &&
10360 connector->base.display_info.bpc * 3 < bpp) {
10361 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10362 bpp, connector->base.display_info.bpc*3);
10363 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10364 }
10365
10366 /* Clamp bpp to 8 on screens without EDID 1.4 */
10367 if (connector->base.display_info.bpc == 0 && bpp > 24) {
10368 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10369 bpp);
10370 pipe_config->pipe_bpp = 24;
10371 }
10372}
10373
4e53c2e0 10374static int
050f7aeb
DV		 10375compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10376 struct drm_framebuffer *fb,
5cec258b 10377 struct intel_crtc_state *pipe_config)
4e53c2e0 10378{
050f7aeb 10379 struct drm_device *dev = crtc->base.dev;
1486017f 10380 struct drm_atomic_state *state;
050f7aeb 10381 struct intel_connector *connector;
1486017f 10382 int bpp, i;
4e53c2e0 10383
d42264b1
DV		 10384 switch (fb->pixel_format) {
10385 case DRM_FORMAT_C8:
4e53c2e0
DV		 10386 bpp = 8*3; /* since we go through a colormap */
10387 break;
d42264b1
DV		 10388 case DRM_FORMAT_XRGB1555:
10389 case DRM_FORMAT_ARGB1555:
10390 /* checked in intel_framebuffer_init already */
10391 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10392 return -EINVAL;
10393 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 10394 bpp = 6*3; /* min is 18bpp */
10395 break;
d42264b1
DV		 10396 case DRM_FORMAT_XBGR8888:
10397 case DRM_FORMAT_ABGR8888:
10398 /* checked in intel_framebuffer_init already */
10399 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10400 return -EINVAL;
10401 case DRM_FORMAT_XRGB8888:
10402 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 10403 bpp = 8*3;
10404 break;
d42264b1
DV		 10405 case DRM_FORMAT_XRGB2101010:
10406 case DRM_FORMAT_ARGB2101010:
10407 case DRM_FORMAT_XBGR2101010:
10408 case DRM_FORMAT_ABGR2101010:
10409 /* checked in intel_framebuffer_init already */
10410 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 10411 return -EINVAL;
4e53c2e0
DV		 10412 bpp = 10*3;
10413 break;
baba133a 10414 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 10415 default:
10416 DRM_DEBUG_KMS("unsupported depth\n");
10417 return -EINVAL;
10418 }
10419
4e53c2e0
DV		 10420 pipe_config->pipe_bpp = bpp;
10421
1486017f
ACO		 10422 state = pipe_config->base.state;
10423
4e53c2e0 10424 /* Clamp display bpp to EDID value */
1486017f
ACO		 10425 for (i = 0; i < state->num_connector; i++) {
10426 if (!state->connectors[i])
10427 continue;
10428
10429 connector = to_intel_connector(state->connectors[i]);
10430 if (state->connector_states[i]->crtc != &crtc->base)
4e53c2e0
DV		 10431 continue;
10432
050f7aeb 10433 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 10434 }
10435
10436 return bpp;
10437}
10438
644db711
DV		 10439static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10440{
10441 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10442 "type: 0x%x flags: 0x%x\n",
1342830c 10443 mode->crtc_clock,
644db711
DV		 10444 mode->crtc_hdisplay, mode->crtc_hsync_start,
10445 mode->crtc_hsync_end, mode->crtc_htotal,
10446 mode->crtc_vdisplay, mode->crtc_vsync_start,
10447 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10448}
10449
c0b03411 10450static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 10451 struct intel_crtc_state *pipe_config,
c0b03411
DV		 10452 const char *context)
10453{
10454 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10455 context, pipe_name(crtc->pipe));
10456
10457 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10458 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10459 pipe_config->pipe_bpp, pipe_config->dither);
10460 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10461 pipe_config->has_pch_encoder,
10462 pipe_config->fdi_lanes,
10463 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10464 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10465 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 10466 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10467 pipe_config->has_dp_encoder,
10468 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10469 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10470 pipe_config->dp_m_n.tu);
b95af8be
VK		 10471
10472 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10473 pipe_config->has_dp_encoder,
10474 pipe_config->dp_m2_n2.gmch_m,
10475 pipe_config->dp_m2_n2.gmch_n,
10476 pipe_config->dp_m2_n2.link_m,
10477 pipe_config->dp_m2_n2.link_n,
10478 pipe_config->dp_m2_n2.tu);
10479
55072d19
DV		 10480 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10481 pipe_config->has_audio,
10482 pipe_config->has_infoframe);
10483
c0b03411 10484 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 10485 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 10486 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 10487 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10488 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 10489 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 10490 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10491 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
c0b03411
DV		 10492 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10493 pipe_config->gmch_pfit.control,
10494 pipe_config->gmch_pfit.pgm_ratios,
10495 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 10496 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 10497 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 10498 pipe_config->pch_pfit.size,
10499 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 10500 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 10501 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
c0b03411
DV		 10502}
10503
bc079e8b
VS		 10504static bool encoders_cloneable(const struct intel_encoder *a,
10505 const struct intel_encoder *b)
accfc0c5 10506{
bc079e8b
VS		 10507 /* masks could be asymmetric, so check both ways */
10508 return a == b || (a->cloneable & (1 << b->type) &&
10509 b->cloneable & (1 << a->type));
10510}
10511
10512static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10513 struct intel_encoder *encoder)
10514{
10515 struct drm_device *dev = crtc->base.dev;
10516 struct intel_encoder *source_encoder;
10517
b2784e15 10518 for_each_intel_encoder(dev, source_encoder) {
bc079e8b
VS		 10519 if (source_encoder->new_crtc != crtc)
10520 continue;
10521
10522 if (!encoders_cloneable(encoder, source_encoder))
10523 return false;
10524 }
10525
10526 return true;
10527}
10528
10529static bool check_encoder_cloning(struct intel_crtc *crtc)
10530{
10531 struct drm_device *dev = crtc->base.dev;
accfc0c5
DV		 10532 struct intel_encoder *encoder;
10533
b2784e15 10534 for_each_intel_encoder(dev, encoder) {
bc079e8b 10535 if (encoder->new_crtc != crtc)
accfc0c5
DV		 10536 continue;
10537
bc079e8b
VS		 10538 if (!check_single_encoder_cloning(crtc, encoder))
10539 return false;
accfc0c5
DV		 10540 }
10541
bc079e8b 10542 return true;
accfc0c5
DV		 10543}
10544
00f0b378
VS		 10545static bool check_digital_port_conflicts(struct drm_device *dev)
10546{
10547 struct intel_connector *connector;
10548 unsigned int used_ports = 0;
10549
10550 /*
10551 * Walk the connector list instead of the encoder
10552 * list to detect the problem on ddi platforms
10553 * where there's just one encoder per digital port.
10554 */
3a3371ff 10555 for_each_intel_connector(dev, connector) {
00f0b378
VS		 10556 struct intel_encoder *encoder = connector->new_encoder;
10557
10558 if (!encoder)
10559 continue;
10560
10561 WARN_ON(!encoder->new_crtc);
10562
10563 switch (encoder->type) {
10564 unsigned int port_mask;
10565 case INTEL_OUTPUT_UNKNOWN:
10566 if (WARN_ON(!HAS_DDI(dev)))
10567 break;
10568 case INTEL_OUTPUT_DISPLAYPORT:
10569 case INTEL_OUTPUT_HDMI:
10570 case INTEL_OUTPUT_EDP:
10571 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10572
10573 /* the same port mustn't appear more than once */
10574 if (used_ports & port_mask)
10575 return false;
10576
10577 used_ports |= port_mask;
10578 default:
10579 break;
10580 }
10581 }
10582
10583 return true;
10584}
10585
83a57153
ACO		 10586static void
10587clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
10588{
10589 struct drm_crtc_state tmp_state;
10590
10591 /* Clear only the intel specific part of the crtc state */
10592 tmp_state = crtc_state->base;
10593 memset(crtc_state, 0, sizeof *crtc_state);
10594 crtc_state->base = tmp_state;
10595}
10596
5cec258b 10597static struct intel_crtc_state *
b8cecdf5 10598intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 10599 struct drm_framebuffer *fb,
83a57153
ACO		 10600 struct drm_display_mode *mode,
10601 struct drm_atomic_state *state)
ee7b9f93 10602{
7758a113 10603 struct drm_device *dev = crtc->dev;
7758a113 10604 struct intel_encoder *encoder;
0b901879
ACO		 10605 struct intel_connector *connector;
10606 struct drm_connector_state *connector_state;
5cec258b 10607 struct intel_crtc_state *pipe_config;
e29c22c0 10608 int plane_bpp, ret = -EINVAL;
0b901879 10609 int i;
e29c22c0 10610 bool retry = true;
ee7b9f93 10611
bc079e8b 10612 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
accfc0c5
DV		 10613 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10614 return ERR_PTR(-EINVAL);
10615 }
10616
00f0b378
VS		 10617 if (!check_digital_port_conflicts(dev)) {
10618 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10619 return ERR_PTR(-EINVAL);
10620 }
10621
83a57153
ACO		 10622 pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
10623 if (IS_ERR(pipe_config))
10624 return pipe_config;
10625
10626 clear_intel_crtc_state(pipe_config);
7758a113 10627
07878248 10628 pipe_config->base.crtc = crtc;
2d112de7
ACO		 10629 drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
10630 drm_mode_copy(&pipe_config->base.mode, mode);
37327abd 10631
e143a21c
DV		 10632 pipe_config->cpu_transcoder =
10633 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 10634 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 10635
2960bc9c
ID		 10636 /*
10637 * Sanitize sync polarity flags based on requested ones. If neither
10638 * positive or negative polarity is requested, treat this as meaning
10639 * negative polarity.
10640 */
2d112de7 10641 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 10642 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 10643 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 10644
2d112de7 10645 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 10646 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 10647 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 10648
050f7aeb
DV		 10649 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10650 * plane pixel format and any sink constraints into account. Returns the
10651 * source plane bpp so that dithering can be selected on mismatches
10652 * after encoders and crtc also have had their say. */
10653 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10654 fb, pipe_config);
4e53c2e0
DV		 10655 if (plane_bpp < 0)
10656 goto fail;
10657
e41a56be
VS		 10658 /*
10659 * Determine the real pipe dimensions. Note that stereo modes can
10660 * increase the actual pipe size due to the frame doubling and
10661 * insertion of additional space for blanks between the frame. This
10662 * is stored in the crtc timings. We use the requested mode to do this
10663 * computation to clearly distinguish it from the adjusted mode, which
10664 * can be changed by the connectors in the below retry loop.
10665 */
2d112de7 10666 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 10667 &pipe_config->pipe_src_w,
10668 &pipe_config->pipe_src_h);
e41a56be 10669
e29c22c0 10670encoder_retry:
ef1b460d 10671 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 10672 pipe_config->port_clock = 0;
ef1b460d 10673 pipe_config->pixel_multiplier = 1;
ff9a6750 10674
135c81b8 10675 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 10676 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10677 CRTC_STEREO_DOUBLE);
135c81b8 10678
7758a113
DV		 10679 /* Pass our mode to the connectors and the CRTC to give them a chance to
10680 * adjust it according to limitations or connector properties, and also
10681 * a chance to reject the mode entirely.
47f1c6c9 10682 */
0b901879
ACO		 10683 for (i = 0; i < state->num_connector; i++) {
10684 connector = to_intel_connector(state->connectors[i]);
10685 if (!connector)
10686 continue;
47f1c6c9 10687
0b901879
ACO		 10688 connector_state = state->connector_states[i];
10689 if (connector_state->crtc != crtc)
7758a113 10690 continue;
7ae89233 10691
0b901879
ACO		 10692 encoder = to_intel_encoder(connector_state->best_encoder);
10693
efea6e8e
DV		 10694 if (!(encoder->compute_config(encoder, pipe_config))) {
10695 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 10696 goto fail;
10697 }
ee7b9f93 10698 }
47f1c6c9 10699
ff9a6750
DV		 10700 /* Set default port clock if not overwritten by the encoder. Needs to be
10701 * done afterwards in case the encoder adjusts the mode. */
10702 if (!pipe_config->port_clock)
2d112de7 10703 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 10704 * pipe_config->pixel_multiplier;
ff9a6750 10705
a43f6e0f 10706 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 10707 if (ret < 0) {
7758a113
DV		 10708 DRM_DEBUG_KMS("CRTC fixup failed\n");
10709 goto fail;
ee7b9f93 10710 }
e29c22c0
DV		 10711
10712 if (ret == RETRY) {
10713 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10714 ret = -EINVAL;
10715 goto fail;
10716 }
10717
10718 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10719 retry = false;
10720 goto encoder_retry;
10721 }
10722
4e53c2e0
DV		 10723 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10724 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10725 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10726
b8cecdf5 10727 return pipe_config;
7758a113 10728fail:
e29c22c0 10729 return ERR_PTR(ret);
ee7b9f93 10730}
47f1c6c9 10731
e2e1ed41
DV		 10732/* Computes which crtcs are affected and sets the relevant bits in the mask. For
10733 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10734static void
10735intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10736 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 10737{
10738 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 10739 struct drm_device *dev = crtc->dev;
10740 struct intel_encoder *encoder;
10741 struct intel_connector *connector;
10742 struct drm_crtc *tmp_crtc;
79e53945 10743
e2e1ed41 10744 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 10745
e2e1ed41
DV		 10746 /* Check which crtcs have changed outputs connected to them, these need
10747 * to be part of the prepare_pipes mask. We don't (yet) support global
10748 * modeset across multiple crtcs, so modeset_pipes will only have one
10749 * bit set at most. */
3a3371ff 10750 for_each_intel_connector(dev, connector) {
e2e1ed41
DV		 10751 if (connector->base.encoder == &connector->new_encoder->base)
10752 continue;
79e53945 10753
e2e1ed41
DV		 10754 if (connector->base.encoder) {
10755 tmp_crtc = connector->base.encoder->crtc;
10756
10757 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10758 }
10759
10760 if (connector->new_encoder)
10761 *prepare_pipes |=
10762 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 10763 }
10764
b2784e15 10765 for_each_intel_encoder(dev, encoder) {
e2e1ed41
DV		 10766 if (encoder->base.crtc == &encoder->new_crtc->base)
10767 continue;
10768
10769 if (encoder->base.crtc) {
10770 tmp_crtc = encoder->base.crtc;
10771
10772 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10773 }
10774
10775 if (encoder->new_crtc)
10776 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 10777 }
10778
7668851f 10779 /* Check for pipes that will be enabled/disabled ... */
d3fcc808 10780 for_each_intel_crtc(dev, intel_crtc) {
83d65738 10781 if (intel_crtc->base.state->enable == intel_crtc->new_enabled)
e2e1ed41 10782 continue;
7e7d76c3 10783
7668851f 10784 if (!intel_crtc->new_enabled)
e2e1ed41 10785 *disable_pipes |= 1 << intel_crtc->pipe;
7668851f
VS		 10786 else
10787 *prepare_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 10788 }
10789
e2e1ed41
DV		 10790
10791 /* set_mode is also used to update properties on life display pipes. */
10792 intel_crtc = to_intel_crtc(crtc);
7668851f 10793 if (intel_crtc->new_enabled)
e2e1ed41
DV		 10794 *prepare_pipes |= 1 << intel_crtc->pipe;
10795
b6c5164d
DV		 10796 /*
10797 * For simplicity do a full modeset on any pipe where the output routing
10798 * changed. We could be more clever, but that would require us to be
10799 * more careful with calling the relevant encoder->mode_set functions.
10800 */
e2e1ed41
DV		 10801 if (*prepare_pipes)
10802 *modeset_pipes = *prepare_pipes;
10803
10804 /* ... and mask these out. */
10805 *modeset_pipes &= ~(*disable_pipes);
10806 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 10807
10808 /*
10809 * HACK: We don't (yet) fully support global modesets. intel_set_config
10810 * obies this rule, but the modeset restore mode of
10811 * intel_modeset_setup_hw_state does not.
10812 */
10813 *modeset_pipes &= 1 << intel_crtc->pipe;
10814 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 10815
10816 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10817 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 10818}
79e53945 10819
ea9d758d 10820static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 10821{
ea9d758d 10822 struct drm_encoder *encoder;
f6e5b160 10823 struct drm_device *dev = crtc->dev;
f6e5b160 10824
ea9d758d
DV		 10825 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10826 if (encoder->crtc == crtc)
10827 return true;
10828
10829 return false;
10830}
10831
10832static void
10833intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10834{
ba41c0de 10835 struct drm_i915_private *dev_priv = dev->dev_private;
ea9d758d
DV		 10836 struct intel_encoder *intel_encoder;
10837 struct intel_crtc *intel_crtc;
10838 struct drm_connector *connector;
10839
ba41c0de
DV		 10840 intel_shared_dpll_commit(dev_priv);
10841
b2784e15 10842 for_each_intel_encoder(dev, intel_encoder) {
ea9d758d
DV		 10843 if (!intel_encoder->base.crtc)
10844 continue;
10845
10846 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10847
10848 if (prepare_pipes & (1 << intel_crtc->pipe))
10849 intel_encoder->connectors_active = false;
10850 }
10851
10852 intel_modeset_commit_output_state(dev);
10853
7668851f 10854 /* Double check state. */
d3fcc808 10855 for_each_intel_crtc(dev, intel_crtc) {
83d65738 10856 WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base));
7bd0a8e7 10857 WARN_ON(intel_crtc->new_config &&
6e3c9717 10858 intel_crtc->new_config != intel_crtc->config);
83d65738 10859 WARN_ON(intel_crtc->base.state->enable != !!intel_crtc->new_config);
ea9d758d
DV		 10860 }
10861
10862 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10863 if (!connector->encoder || !connector->encoder->crtc)
10864 continue;
10865
10866 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10867
10868 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 10869 struct drm_property *dpms_property =
10870 dev->mode_config.dpms_property;
10871
ea9d758d 10872 connector->dpms = DRM_MODE_DPMS_ON;
662595df 10873 drm_object_property_set_value(&connector->base,
68d34720
DV		 10874 dpms_property,
10875 DRM_MODE_DPMS_ON);
ea9d758d
DV		 10876
10877 intel_encoder = to_intel_encoder(connector->encoder);
10878 intel_encoder->connectors_active = true;
10879 }
10880 }
10881
10882}
10883
3bd26263 10884static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 10885{
3bd26263 10886 int diff;
f1f644dc
JB		 10887
10888 if (clock1 == clock2)
10889 return true;
10890
10891 if (!clock1 || !clock2)
10892 return false;
10893
10894 diff = abs(clock1 - clock2);
10895
10896 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10897 return true;
10898
10899 return false;
10900}
10901
25c5b266
DV		 10902#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10903 list_for_each_entry((intel_crtc), \
10904 &(dev)->mode_config.crtc_list, \
10905 base.head) \
0973f18f 10906 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 10907
0e8ffe1b 10908static bool
2fa2fe9a 10909intel_pipe_config_compare(struct drm_device *dev,
5cec258b
ACO		 10910 struct intel_crtc_state *current_config,
10911 struct intel_crtc_state *pipe_config)
0e8ffe1b 10912{
66e985c0
DV		 10913#define PIPE_CONF_CHECK_X(name) \
10914 if (current_config->name != pipe_config->name) { \
10915 DRM_ERROR("mismatch in " #name " " \
10916 "(expected 0x%08x, found 0x%08x)\n", \
10917 current_config->name, \
10918 pipe_config->name); \
10919 return false; \
10920 }
10921
08a24034
DV		 10922#define PIPE_CONF_CHECK_I(name) \
10923 if (current_config->name != pipe_config->name) { \
10924 DRM_ERROR("mismatch in " #name " " \
10925 "(expected %i, found %i)\n", \
10926 current_config->name, \
10927 pipe_config->name); \
10928 return false; \
88adfff1
DV		 10929 }
10930
b95af8be
VK		 10931/* This is required for BDW+ where there is only one set of registers for
10932 * switching between high and low RR.
10933 * This macro can be used whenever a comparison has to be made between one
10934 * hw state and multiple sw state variables.
10935 */
10936#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10937 if ((current_config->name != pipe_config->name) && \
10938 (current_config->alt_name != pipe_config->name)) { \
10939 DRM_ERROR("mismatch in " #name " " \
10940 "(expected %i or %i, found %i)\n", \
10941 current_config->name, \
10942 current_config->alt_name, \
10943 pipe_config->name); \
10944 return false; \
10945 }
10946
1bd1bd80
DV		 10947#define PIPE_CONF_CHECK_FLAGS(name, mask) \
10948 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 10949 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 10950 "(expected %i, found %i)\n", \
10951 current_config->name & (mask), \
10952 pipe_config->name & (mask)); \
10953 return false; \
10954 }
10955
5e550656
VS		 10956#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10957 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10958 DRM_ERROR("mismatch in " #name " " \
10959 "(expected %i, found %i)\n", \
10960 current_config->name, \
10961 pipe_config->name); \
10962 return false; \
10963 }
10964
bb760063
DV		 10965#define PIPE_CONF_QUIRK(quirk) \
10966 ((current_config->quirks | pipe_config->quirks) & (quirk))
10967
eccb140b
DV		 10968 PIPE_CONF_CHECK_I(cpu_transcoder);
10969
08a24034
DV		 10970 PIPE_CONF_CHECK_I(has_pch_encoder);
10971 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 10972 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10973 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10974 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10975 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10976 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 10977
eb14cb74 10978 PIPE_CONF_CHECK_I(has_dp_encoder);
b95af8be
VK		 10979
10980 if (INTEL_INFO(dev)->gen < 8) {
10981 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10982 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10983 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10984 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10985 PIPE_CONF_CHECK_I(dp_m_n.tu);
10986
10987 if (current_config->has_drrs) {
10988 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10989 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10990 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10991 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10992 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10993 }
10994 } else {
10995 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10996 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10997 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10998 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10999 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
11000 }
eb14cb74 11001
2d112de7
ACO		 11002 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11003 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11004 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11005 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11006 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11007 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 11008
2d112de7
ACO		 11009 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11010 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11011 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11012 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11013 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11014 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 11015
c93f54cf 11016 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 11017 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 11018 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
11019 IS_VALLEYVIEW(dev))
11020 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 11021 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 11022
9ed109a7
DV		 11023 PIPE_CONF_CHECK_I(has_audio);
11024
2d112de7 11025 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 11026 DRM_MODE_FLAG_INTERLACE);
11027
bb760063 11028 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 11029 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 11030 DRM_MODE_FLAG_PHSYNC);
2d112de7 11031 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 11032 DRM_MODE_FLAG_NHSYNC);
2d112de7 11033 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 11034 DRM_MODE_FLAG_PVSYNC);
2d112de7 11035 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 11036 DRM_MODE_FLAG_NVSYNC);
11037 }
045ac3b5 11038
37327abd
VS		 11039 PIPE_CONF_CHECK_I(pipe_src_w);
11040 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 11041
9953599b
DV		 11042 /*
11043 * FIXME: BIOS likes to set up a cloned config with lvds+external
11044 * screen. Since we don't yet re-compute the pipe config when moving
11045 * just the lvds port away to another pipe the sw tracking won't match.
11046 *
11047 * Proper atomic modesets with recomputed global state will fix this.
11048 * Until then just don't check gmch state for inherited modes.
11049 */
11050 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
11051 PIPE_CONF_CHECK_I(gmch_pfit.control);
11052 /* pfit ratios are autocomputed by the hw on gen4+ */
11053 if (INTEL_INFO(dev)->gen < 4)
11054 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
11055 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
11056 }
11057
fd4daa9c
CW		 11058 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11059 if (current_config->pch_pfit.enabled) {
11060 PIPE_CONF_CHECK_I(pch_pfit.pos);
11061 PIPE_CONF_CHECK_I(pch_pfit.size);
11062 }
2fa2fe9a 11063
e59150dc
JB		 11064 /* BDW+ don't expose a synchronous way to read the state */
11065 if (IS_HASWELL(dev))
11066 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 11067
282740f7
VS		 11068 PIPE_CONF_CHECK_I(double_wide);
11069
26804afd
DV		 11070 PIPE_CONF_CHECK_X(ddi_pll_sel);
11071
c0d43d62 11072 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 11073 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 11074 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 11075 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11076 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 11077 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 11078 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11079 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11080 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 11081
42571aef
VS		 11082 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
11083 PIPE_CONF_CHECK_I(pipe_bpp);
11084
2d112de7 11085 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 11086 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 11087
66e985c0 11088#undef PIPE_CONF_CHECK_X
08a24034 11089#undef PIPE_CONF_CHECK_I
b95af8be 11090#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 11091#undef PIPE_CONF_CHECK_FLAGS
5e550656 11092#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 11093#undef PIPE_CONF_QUIRK
88adfff1 11094
0e8ffe1b
DV		 11095 return true;
11096}
11097
08db6652
DL		 11098static void check_wm_state(struct drm_device *dev)
11099{
11100 struct drm_i915_private *dev_priv = dev->dev_private;
11101 struct skl_ddb_allocation hw_ddb, *sw_ddb;
11102 struct intel_crtc *intel_crtc;
11103 int plane;
11104
11105 if (INTEL_INFO(dev)->gen < 9)
11106 return;
11107
11108 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11109 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11110
11111 for_each_intel_crtc(dev, intel_crtc) {
11112 struct skl_ddb_entry *hw_entry, *sw_entry;
11113 const enum pipe pipe = intel_crtc->pipe;
11114
11115 if (!intel_crtc->active)
11116 continue;
11117
11118 /* planes */
dd740780 11119 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 11120 hw_entry = &hw_ddb.plane[pipe][plane];
11121 sw_entry = &sw_ddb->plane[pipe][plane];
11122
11123 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11124 continue;
11125
11126 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
11127 "(expected (%u,%u), found (%u,%u))\n",
11128 pipe_name(pipe), plane + 1,
11129 sw_entry->start, sw_entry->end,
11130 hw_entry->start, hw_entry->end);
11131 }
11132
11133 /* cursor */
11134 hw_entry = &hw_ddb.cursor[pipe];
11135 sw_entry = &sw_ddb->cursor[pipe];
11136
11137 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11138 continue;
11139
11140 DRM_ERROR("mismatch in DDB state pipe %c cursor "
11141 "(expected (%u,%u), found (%u,%u))\n",
11142 pipe_name(pipe),
11143 sw_entry->start, sw_entry->end,
11144 hw_entry->start, hw_entry->end);
11145 }
11146}
11147
91d1b4bd
DV		 11148static void
11149check_connector_state(struct drm_device *dev)
8af6cf88 11150{
8af6cf88
DV		 11151 struct intel_connector *connector;
11152
3a3371ff 11153 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 11154 /* This also checks the encoder/connector hw state with the
11155 * ->get_hw_state callbacks. */
11156 intel_connector_check_state(connector);
11157
e2c719b7 11158 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
8af6cf88
DV		 11159 "connector's staged encoder doesn't match current encoder\n");
11160 }
91d1b4bd
DV		 11161}
11162
11163static void
11164check_encoder_state(struct drm_device *dev)
11165{
11166 struct intel_encoder *encoder;
11167 struct intel_connector *connector;
8af6cf88 11168
b2784e15 11169 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 11170 bool enabled = false;
11171 bool active = false;
11172 enum pipe pipe, tracked_pipe;
11173
11174 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11175 encoder->base.base.id,
8e329a03 11176 encoder->base.name);
8af6cf88 11177
e2c719b7 11178 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
8af6cf88 11179 "encoder's stage crtc doesn't match current crtc\n");
e2c719b7 11180 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
8af6cf88
DV		 11181 "encoder's active_connectors set, but no crtc\n");
11182
3a3371ff 11183 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 11184 if (connector->base.encoder != &encoder->base)
11185 continue;
11186 enabled = true;
11187 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
11188 active = true;
11189 }
0e32b39c
DA		 11190 /*
11191 * for MST connectors if we unplug the connector is gone
11192 * away but the encoder is still connected to a crtc
11193 * until a modeset happens in response to the hotplug.
11194 */
11195 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
11196 continue;
11197
e2c719b7 11198 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 11199 "encoder's enabled state mismatch "
11200 "(expected %i, found %i)\n",
11201 !!encoder->base.crtc, enabled);
e2c719b7 11202 I915_STATE_WARN(active && !encoder->base.crtc,
8af6cf88
DV		 11203 "active encoder with no crtc\n");
11204
e2c719b7 11205 I915_STATE_WARN(encoder->connectors_active != active,
8af6cf88
DV		 11206 "encoder's computed active state doesn't match tracked active state "
11207 "(expected %i, found %i)\n", active, encoder->connectors_active);
11208
11209 active = encoder->get_hw_state(encoder, &pipe);
e2c719b7 11210 I915_STATE_WARN(active != encoder->connectors_active,
8af6cf88
DV		 11211 "encoder's hw state doesn't match sw tracking "
11212 "(expected %i, found %i)\n",
11213 encoder->connectors_active, active);
11214
11215 if (!encoder->base.crtc)
11216 continue;
11217
11218 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
e2c719b7 11219 I915_STATE_WARN(active && pipe != tracked_pipe,
8af6cf88
DV		 11220 "active encoder's pipe doesn't match"
11221 "(expected %i, found %i)\n",
11222 tracked_pipe, pipe);
11223
11224 }
91d1b4bd
DV		 11225}
11226
11227static void
11228check_crtc_state(struct drm_device *dev)
11229{
fbee40df 11230 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 11231 struct intel_crtc *crtc;
11232 struct intel_encoder *encoder;
5cec258b 11233 struct intel_crtc_state pipe_config;
8af6cf88 11234
d3fcc808 11235 for_each_intel_crtc(dev, crtc) {
8af6cf88
DV		 11236 bool enabled = false;
11237 bool active = false;
11238
045ac3b5
JB		 11239 memset(&pipe_config, 0, sizeof(pipe_config));
11240
8af6cf88
DV		 11241 DRM_DEBUG_KMS("[CRTC:%d]\n",
11242 crtc->base.base.id);
11243
83d65738 11244 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
8af6cf88
DV		 11245 "active crtc, but not enabled in sw tracking\n");
11246
b2784e15 11247 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 11248 if (encoder->base.crtc != &crtc->base)
11249 continue;
11250 enabled = true;
11251 if (encoder->connectors_active)
11252 active = true;
11253 }
6c49f241 11254
e2c719b7 11255 I915_STATE_WARN(active != crtc->active,
8af6cf88
DV		 11256 "crtc's computed active state doesn't match tracked active state "
11257 "(expected %i, found %i)\n", active, crtc->active);
83d65738 11258 I915_STATE_WARN(enabled != crtc->base.state->enable,
8af6cf88 11259 "crtc's computed enabled state doesn't match tracked enabled state "
83d65738
MR		 11260 "(expected %i, found %i)\n", enabled,
11261 crtc->base.state->enable);
8af6cf88 11262
0e8ffe1b
DV		 11263 active = dev_priv->display.get_pipe_config(crtc,
11264 &pipe_config);
d62cf62a 11265
b6b5d049
VS		 11266 /* hw state is inconsistent with the pipe quirk */
11267 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
11268 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
d62cf62a
DV		 11269 active = crtc->active;
11270
b2784e15 11271 for_each_intel_encoder(dev, encoder) {
3eaba51c 11272 enum pipe pipe;
6c49f241
DV		 11273 if (encoder->base.crtc != &crtc->base)
11274 continue;
1d37b689 11275 if (encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 11276 encoder->get_config(encoder, &pipe_config);
11277 }
11278
e2c719b7 11279 I915_STATE_WARN(crtc->active != active,
0e8ffe1b
DV		 11280 "crtc active state doesn't match with hw state "
11281 "(expected %i, found %i)\n", crtc->active, active);
11282
c0b03411 11283 if (active &&
6e3c9717 11284 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
e2c719b7 11285 I915_STATE_WARN(1, "pipe state doesn't match!\n");
c0b03411
DV		 11286 intel_dump_pipe_config(crtc, &pipe_config,
11287 "[hw state]");
6e3c9717 11288 intel_dump_pipe_config(crtc, crtc->config,
c0b03411
DV		 11289 "[sw state]");
11290 }
8af6cf88
DV		 11291 }
11292}
11293
91d1b4bd
DV		 11294static void
11295check_shared_dpll_state(struct drm_device *dev)
11296{
fbee40df 11297 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 11298 struct intel_crtc *crtc;
11299 struct intel_dpll_hw_state dpll_hw_state;
11300 int i;
5358901f
DV		 11301
11302 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11303 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11304 int enabled_crtcs = 0, active_crtcs = 0;
11305 bool active;
11306
11307 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11308
11309 DRM_DEBUG_KMS("%s\n", pll->name);
11310
11311 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
11312
e2c719b7 11313 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 11314 "more active pll users than references: %i vs %i\n",
3e369b76 11315 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 11316 I915_STATE_WARN(pll->active && !pll->on,
5358901f 11317 "pll in active use but not on in sw tracking\n");
e2c719b7 11318 I915_STATE_WARN(pll->on && !pll->active,
35c95375 11319 "pll in on but not on in use in sw tracking\n");
e2c719b7 11320 I915_STATE_WARN(pll->on != active,
5358901f
DV		 11321 "pll on state mismatch (expected %i, found %i)\n",
11322 pll->on, active);
11323
d3fcc808 11324 for_each_intel_crtc(dev, crtc) {
83d65738 11325 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 11326 enabled_crtcs++;
11327 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11328 active_crtcs++;
11329 }
e2c719b7 11330 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 11331 "pll active crtcs mismatch (expected %i, found %i)\n",
11332 pll->active, active_crtcs);
e2c719b7 11333 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 11334 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 11335 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 11336
e2c719b7 11337 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 11338 sizeof(dpll_hw_state)),
11339 "pll hw state mismatch\n");
5358901f 11340 }
8af6cf88
DV		 11341}
11342
91d1b4bd
DV		 11343void
11344intel_modeset_check_state(struct drm_device *dev)
11345{
08db6652 11346 check_wm_state(dev);
91d1b4bd
DV		 11347 check_connector_state(dev);
11348 check_encoder_state(dev);
11349 check_crtc_state(dev);
11350 check_shared_dpll_state(dev);
11351}
11352
5cec258b 11353void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 11354 int dotclock)
11355{
11356 /*
11357 * FDI already provided one idea for the dotclock.
11358 * Yell if the encoder disagrees.
11359 */
2d112de7 11360 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 11361 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 11362 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 11363}
11364
80715b2f
VS		 11365static void update_scanline_offset(struct intel_crtc *crtc)
11366{
11367 struct drm_device *dev = crtc->base.dev;
11368
11369 /*
11370 * The scanline counter increments at the leading edge of hsync.
11371 *
11372 * On most platforms it starts counting from vtotal-1 on the
11373 * first active line. That means the scanline counter value is
11374 * always one less than what we would expect. Ie. just after
11375 * start of vblank, which also occurs at start of hsync (on the
11376 * last active line), the scanline counter will read vblank_start-1.
11377 *
11378 * On gen2 the scanline counter starts counting from 1 instead
11379 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11380 * to keep the value positive), instead of adding one.
11381 *
11382 * On HSW+ the behaviour of the scanline counter depends on the output
11383 * type. For DP ports it behaves like most other platforms, but on HDMI
11384 * there's an extra 1 line difference. So we need to add two instead of
11385 * one to the value.
11386 */
11387 if (IS_GEN2(dev)) {
6e3c9717 11388 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 11389 int vtotal;
11390
11391 vtotal = mode->crtc_vtotal;
11392 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
11393 vtotal /= 2;
11394
11395 crtc->scanline_offset = vtotal - 1;
11396 } else if (HAS_DDI(dev) &&
409ee761 11397 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 11398 crtc->scanline_offset = 2;
11399 } else
11400 crtc->scanline_offset = 1;
11401}
11402
5cec258b 11403static struct intel_crtc_state *
7f27126e
JB		 11404intel_modeset_compute_config(struct drm_crtc *crtc,
11405 struct drm_display_mode *mode,
11406 struct drm_framebuffer *fb,
83a57153 11407 struct drm_atomic_state *state,
7f27126e
JB		 11408 unsigned *modeset_pipes,
11409 unsigned *prepare_pipes,
11410 unsigned *disable_pipes)
11411{
db7542dd 11412 struct drm_device *dev = crtc->dev;
5cec258b 11413 struct intel_crtc_state *pipe_config = NULL;
db7542dd 11414 struct intel_crtc *intel_crtc;
0b901879
ACO		 11415 int ret = 0;
11416
11417 ret = drm_atomic_add_affected_connectors(state, crtc);
11418 if (ret)
11419 return ERR_PTR(ret);
7f27126e
JB		 11420
11421 intel_modeset_affected_pipes(crtc, modeset_pipes,
11422 prepare_pipes, disable_pipes);
11423
db7542dd
ACO		 11424 for_each_intel_crtc_masked(dev, *disable_pipes, intel_crtc) {
11425 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
11426 if (IS_ERR(pipe_config))
11427 return pipe_config;
11428
11429 pipe_config->base.enable = false;
11430 }
7f27126e
JB		 11431
11432 /*
11433 * Note this needs changes when we start tracking multiple modes
11434 * and crtcs. At that point we'll need to compute the whole config
11435 * (i.e. one pipe_config for each crtc) rather than just the one
11436 * for this crtc.
11437 */
db7542dd
ACO		 11438 for_each_intel_crtc_masked(dev, *modeset_pipes, intel_crtc) {
11439 /* FIXME: For now we still expect modeset_pipes has at most
11440 * one bit set. */
11441 if (WARN_ON(&intel_crtc->base != crtc))
11442 continue;
83a57153 11443
db7542dd
ACO		 11444 pipe_config = intel_modeset_pipe_config(crtc, fb, mode, state);
11445 if (IS_ERR(pipe_config))
11446 return pipe_config;
7f27126e 11447
db7542dd
ACO		 11448 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11449 "[modeset]");
11450 }
11451
11452 return intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));;
7f27126e
JB		 11453}
11454
ed6739ef
ACO		 11455static int __intel_set_mode_setup_plls(struct drm_device *dev,
11456 unsigned modeset_pipes,
11457 unsigned disable_pipes)
11458{
11459 struct drm_i915_private *dev_priv = to_i915(dev);
11460 unsigned clear_pipes = modeset_pipes | disable_pipes;
11461 struct intel_crtc *intel_crtc;
11462 int ret = 0;
11463
11464 if (!dev_priv->display.crtc_compute_clock)
11465 return 0;
11466
11467 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
11468 if (ret)
11469 goto done;
11470
11471 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11472 struct intel_crtc_state *state = intel_crtc->new_config;
11473 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11474 state);
11475 if (ret) {
11476 intel_shared_dpll_abort_config(dev_priv);
11477 goto done;
11478 }
11479 }
11480
11481done:
11482 return ret;
11483}
11484
f30da187
DV		 11485static int __intel_set_mode(struct drm_crtc *crtc,
11486 struct drm_display_mode *mode,
7f27126e 11487 int x, int y, struct drm_framebuffer *fb,
5cec258b 11488 struct intel_crtc_state *pipe_config,
7f27126e
JB		 11489 unsigned modeset_pipes,
11490 unsigned prepare_pipes,
11491 unsigned disable_pipes)
a6778b3c
DV		 11492{
11493 struct drm_device *dev = crtc->dev;
fbee40df 11494 struct drm_i915_private *dev_priv = dev->dev_private;
4b4b9238 11495 struct drm_display_mode *saved_mode;
83a57153 11496 struct intel_crtc_state *crtc_state_copy = NULL;
25c5b266 11497 struct intel_crtc *intel_crtc;
c0c36b94 11498 int ret = 0;
a6778b3c 11499
4b4b9238 11500 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 11501 if (!saved_mode)
11502 return -ENOMEM;
a6778b3c 11503
83a57153
ACO		 11504 crtc_state_copy = kmalloc(sizeof(*crtc_state_copy), GFP_KERNEL);
11505 if (!crtc_state_copy) {
11506 ret = -ENOMEM;
11507 goto done;
11508 }
11509
3ac18232 11510 *saved_mode = crtc->mode;
a6778b3c 11511
b9950a13
VS		 11512 if (modeset_pipes)
11513 to_intel_crtc(crtc)->new_config = pipe_config;
11514
30a970c6
JB		 11515 /*
11516 * See if the config requires any additional preparation, e.g.
11517 * to adjust global state with pipes off. We need to do this
11518 * here so we can get the modeset_pipe updated config for the new
11519 * mode set on this crtc. For other crtcs we need to use the
11520 * adjusted_mode bits in the crtc directly.
11521 */
c164f833 11522 if (IS_VALLEYVIEW(dev)) {
2f2d7aa1 11523 valleyview_modeset_global_pipes(dev, &prepare_pipes);
30a970c6 11524
c164f833
VS		 11525 /* may have added more to prepare_pipes than we should */
11526 prepare_pipes &= ~disable_pipes;
11527 }
11528
ed6739ef
ACO		 11529 ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
11530 if (ret)
11531 goto done;
8bd31e67 11532
460da916
DV		 11533 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11534 intel_crtc_disable(&intel_crtc->base);
11535
ea9d758d 11536 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
83d65738 11537 if (intel_crtc->base.state->enable)
ea9d758d
DV		 11538 dev_priv->display.crtc_disable(&intel_crtc->base);
11539 }
a6778b3c 11540
6c4c86f5
DV		 11541 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11542 * to set it here already despite that we pass it down the callchain.
7f27126e
JB		 11543 *
11544 * Note we'll need to fix this up when we start tracking multiple
11545 * pipes; here we assume a single modeset_pipe and only track the
11546 * single crtc and mode.
f6e5b160 11547 */
b8cecdf5 11548 if (modeset_pipes) {
25c5b266 11549 crtc->mode = *mode;
b8cecdf5
DV		 11550 /* mode_set/enable/disable functions rely on a correct pipe
11551 * config. */
f5de6e07 11552 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
c326c0a9
VS		 11553
11554 /*
11555 * Calculate and store various constants which
11556 * are later needed by vblank and swap-completion
11557 * timestamping. They are derived from true hwmode.
11558 */
11559 drm_calc_timestamping_constants(crtc,
2d112de7 11560 &pipe_config->base.adjusted_mode);
b8cecdf5 11561 }
7758a113 11562
ea9d758d
DV		 11563 /* Only after disabling all output pipelines that will be changed can we
11564 * update the the output configuration. */
11565 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 11566
679dacd4 11567 modeset_update_crtc_power_domains(pipe_config->base.state);
47fab737 11568
a6778b3c
DV		 11569 /* Set up the DPLL and any encoders state that needs to adjust or depend
11570 * on the DPLL.
f6e5b160 11571 */
25c5b266 11572 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
455a6808
GP		 11573 struct drm_plane *primary = intel_crtc->base.primary;
11574 int vdisplay, hdisplay;
4c10794f 11575
455a6808
GP		 11576 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11577 ret = primary->funcs->update_plane(primary, &intel_crtc->base,
11578 fb, 0, 0,
11579 hdisplay, vdisplay,
11580 x << 16, y << 16,
11581 hdisplay << 16, vdisplay << 16);
a6778b3c
DV		 11582 }
11583
11584 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
80715b2f
VS		 11585 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11586 update_scanline_offset(intel_crtc);
11587
25c5b266 11588 dev_priv->display.crtc_enable(&intel_crtc->base);
80715b2f 11589 }
a6778b3c 11590
a6778b3c
DV		 11591 /* FIXME: add subpixel order */
11592done:
83d65738 11593 if (ret && crtc->state->enable)
3ac18232 11594 crtc->mode = *saved_mode;
a6778b3c 11595
83a57153
ACO		 11596 if (ret == 0 && pipe_config) {
11597 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11598
11599 /* The pipe_config will be freed with the atomic state, so
11600 * make a copy. */
11601 memcpy(crtc_state_copy, intel_crtc->config,
11602 sizeof *crtc_state_copy);
11603 intel_crtc->config = crtc_state_copy;
11604 intel_crtc->base.state = &crtc_state_copy->base;
11605
11606 if (modeset_pipes)
11607 intel_crtc->new_config = intel_crtc->config;
11608 } else {
11609 kfree(crtc_state_copy);
11610 }
11611
3ac18232 11612 kfree(saved_mode);
a6778b3c 11613 return ret;
f6e5b160
CW		 11614}
11615
7f27126e
JB		 11616static int intel_set_mode_pipes(struct drm_crtc *crtc,
11617 struct drm_display_mode *mode,
11618 int x, int y, struct drm_framebuffer *fb,
5cec258b 11619 struct intel_crtc_state *pipe_config,
7f27126e
JB		 11620 unsigned modeset_pipes,
11621 unsigned prepare_pipes,
11622 unsigned disable_pipes)
f30da187
DV		 11623{
11624 int ret;
11625
7f27126e
JB		 11626 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11627 prepare_pipes, disable_pipes);
f30da187
DV		 11628
11629 if (ret == 0)
11630 intel_modeset_check_state(crtc->dev);
11631
11632 return ret;
11633}
11634
7f27126e
JB		 11635static int intel_set_mode(struct drm_crtc *crtc,
11636 struct drm_display_mode *mode,
83a57153
ACO		 11637 int x, int y, struct drm_framebuffer *fb,
11638 struct drm_atomic_state *state)
7f27126e 11639{
5cec258b 11640 struct intel_crtc_state *pipe_config;
7f27126e 11641 unsigned modeset_pipes, prepare_pipes, disable_pipes;
83a57153 11642 int ret = 0;
7f27126e 11643
83a57153 11644 pipe_config = intel_modeset_compute_config(crtc, mode, fb, state,
7f27126e
JB		 11645 &modeset_pipes,
11646 &prepare_pipes,
11647 &disable_pipes);
11648
83a57153
ACO		 11649 if (IS_ERR(pipe_config)) {
11650 ret = PTR_ERR(pipe_config);
11651 goto out;
11652 }
11653
11654 ret = intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11655 modeset_pipes, prepare_pipes,
11656 disable_pipes);
11657 if (ret)
11658 goto out;
7f27126e 11659
83a57153
ACO		 11660out:
11661 return ret;
7f27126e
JB		 11662}
11663
c0c36b94
CW		 11664void intel_crtc_restore_mode(struct drm_crtc *crtc)
11665{
83a57153
ACO		 11666 struct drm_device *dev = crtc->dev;
11667 struct drm_atomic_state *state;
11668 struct intel_encoder *encoder;
11669 struct intel_connector *connector;
11670 struct drm_connector_state *connector_state;
11671
11672 state = drm_atomic_state_alloc(dev);
11673 if (!state) {
11674 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
11675 crtc->base.id);
11676 return;
11677 }
11678
11679 state->acquire_ctx = dev->mode_config.acquire_ctx;
11680
11681 /* The force restore path in the HW readout code relies on the staged
11682 * config still keeping the user requested config while the actual
11683 * state has been overwritten by the configuration read from HW. We
11684 * need to copy the staged config to the atomic state, otherwise the
11685 * mode set will just reapply the state the HW is already in. */
11686 for_each_intel_encoder(dev, encoder) {
11687 if (&encoder->new_crtc->base != crtc)
11688 continue;
11689
11690 for_each_intel_connector(dev, connector) {
11691 if (connector->new_encoder != encoder)
11692 continue;
11693
11694 connector_state = drm_atomic_get_connector_state(state, &connector->base);
11695 if (IS_ERR(connector_state)) {
11696 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
11697 connector->base.base.id,
11698 connector->base.name,
11699 PTR_ERR(connector_state));
11700 continue;
11701 }
11702
11703 connector_state->crtc = crtc;
11704 connector_state->best_encoder = &encoder->base;
11705 }
11706 }
11707
11708 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb,
11709 state);
11710
11711 drm_atomic_state_free(state);
c0c36b94
CW		 11712}
11713
25c5b266
DV		 11714#undef for_each_intel_crtc_masked
11715
d9e55608
DV		 11716static void intel_set_config_free(struct intel_set_config *config)
11717{
11718 if (!config)
11719 return;
11720
1aa4b628
DV		 11721 kfree(config->save_connector_encoders);
11722 kfree(config->save_encoder_crtcs);
7668851f 11723 kfree(config->save_crtc_enabled);
d9e55608
DV		 11724 kfree(config);
11725}
11726
85f9eb71
DV		 11727static int intel_set_config_save_state(struct drm_device *dev,
11728 struct intel_set_config *config)
11729{
7668851f 11730 struct drm_crtc *crtc;
85f9eb71
DV		 11731 struct drm_encoder *encoder;
11732 struct drm_connector *connector;
11733 int count;
11734
7668851f
VS		 11735 config->save_crtc_enabled =
11736 kcalloc(dev->mode_config.num_crtc,
11737 sizeof(bool), GFP_KERNEL);
11738 if (!config->save_crtc_enabled)
11739 return -ENOMEM;
11740
1aa4b628
DV		 11741 config->save_encoder_crtcs =
11742 kcalloc(dev->mode_config.num_encoder,
11743 sizeof(struct drm_crtc *), GFP_KERNEL);
11744 if (!config->save_encoder_crtcs)
85f9eb71
DV		 11745 return -ENOMEM;
11746
1aa4b628
DV		 11747 config->save_connector_encoders =
11748 kcalloc(dev->mode_config.num_connector,
11749 sizeof(struct drm_encoder *), GFP_KERNEL);
11750 if (!config->save_connector_encoders)
85f9eb71
DV		 11751 return -ENOMEM;
11752
11753 /* Copy data. Note that driver private data is not affected.
11754 * Should anything bad happen only the expected state is
11755 * restored, not the drivers personal bookkeeping.
11756 */
7668851f 11757 count = 0;
70e1e0ec 11758 for_each_crtc(dev, crtc) {
83d65738 11759 config->save_crtc_enabled[count++] = crtc->state->enable;
7668851f
VS		 11760 }
11761
85f9eb71
DV		 11762 count = 0;
11763 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 11764 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 11765 }
11766
11767 count = 0;
11768 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 11769 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 11770 }
11771
11772 return 0;
11773}
11774
11775static void intel_set_config_restore_state(struct drm_device *dev,
11776 struct intel_set_config *config)
11777{
7668851f 11778 struct intel_crtc *crtc;
9a935856
DV		 11779 struct intel_encoder *encoder;
11780 struct intel_connector *connector;
85f9eb71
DV		 11781 int count;
11782
7668851f 11783 count = 0;
d3fcc808 11784 for_each_intel_crtc(dev, crtc) {
7668851f 11785 crtc->new_enabled = config->save_crtc_enabled[count++];
7bd0a8e7
VS		 11786
11787 if (crtc->new_enabled)
6e3c9717 11788 crtc->new_config = crtc->config;
7bd0a8e7
VS		 11789 else
11790 crtc->new_config = NULL;
7668851f
VS		 11791 }
11792
85f9eb71 11793 count = 0;
b2784e15 11794 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 11795 encoder->new_crtc =
11796 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 11797 }
11798
11799 count = 0;
3a3371ff 11800 for_each_intel_connector(dev, connector) {
9a935856
DV		 11801 connector->new_encoder =
11802 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 11803 }
11804}
11805
e3de42b6 11806static bool
2e57f47d 11807is_crtc_connector_off(struct drm_mode_set *set)
e3de42b6
ID		 11808{
11809 int i;
11810
2e57f47d
CW		 11811 if (set->num_connectors == 0)
11812 return false;
11813
11814 if (WARN_ON(set->connectors == NULL))
11815 return false;
11816
11817 for (i = 0; i < set->num_connectors; i++)
11818 if (set->connectors[i]->encoder &&
11819 set->connectors[i]->encoder->crtc == set->crtc &&
11820 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
e3de42b6
ID		 11821 return true;
11822
11823 return false;
11824}
11825
5e2b584e
DV		 11826static void
11827intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11828 struct intel_set_config *config)
11829{
11830
11831 /* We should be able to check here if the fb has the same properties
11832 * and then just flip_or_move it */
2e57f47d
CW		 11833 if (is_crtc_connector_off(set)) {
11834 config->mode_changed = true;
f4510a27 11835 } else if (set->crtc->primary->fb != set->fb) {
3b150f08
MR		 11836 /*
11837 * If we have no fb, we can only flip as long as the crtc is
11838 * active, otherwise we need a full mode set. The crtc may
11839 * be active if we've only disabled the primary plane, or
11840 * in fastboot situations.
11841 */
f4510a27 11842 if (set->crtc->primary->fb == NULL) {
319d9827
JB		 11843 struct intel_crtc *intel_crtc =
11844 to_intel_crtc(set->crtc);
11845
3b150f08 11846 if (intel_crtc->active) {
319d9827
JB		 11847 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11848 config->fb_changed = true;
11849 } else {
11850 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11851 config->mode_changed = true;
11852 }
5e2b584e
DV		 11853 } else if (set->fb == NULL) {
11854 config->mode_changed = true;
72f4901e 11855 } else if (set->fb->pixel_format !=
f4510a27 11856 set->crtc->primary->fb->pixel_format) {
5e2b584e 11857 config->mode_changed = true;
e3de42b6 11858 } else {
5e2b584e 11859 config->fb_changed = true;
e3de42b6 11860 }
5e2b584e
DV		 11861 }
11862
835c5873 11863 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 11864 config->fb_changed = true;
11865
11866 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11867 DRM_DEBUG_KMS("modes are different, full mode set\n");
11868 drm_mode_debug_printmodeline(&set->crtc->mode);
11869 drm_mode_debug_printmodeline(set->mode);
11870 config->mode_changed = true;
11871 }
a1d95703
CW		 11872
11873 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11874 set->crtc->base.id, config->mode_changed, config->fb_changed);
5e2b584e
DV		 11875}
11876
2e431051 11877static int
9a935856
DV		 11878intel_modeset_stage_output_state(struct drm_device *dev,
11879 struct drm_mode_set *set,
944b0c76
ACO		 11880 struct intel_set_config *config,
11881 struct drm_atomic_state *state)
50f56119 11882{
9a935856 11883 struct intel_connector *connector;
944b0c76 11884 struct drm_connector_state *connector_state;
9a935856 11885 struct intel_encoder *encoder;
7668851f 11886 struct intel_crtc *crtc;
f3f08572 11887 int ro;
50f56119 11888
9abdda74 11889 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 11890 * of connectors. For paranoia, double-check this. */
11891 WARN_ON(!set->fb && (set->num_connectors != 0));
11892 WARN_ON(set->fb && (set->num_connectors == 0));
11893
3a3371ff 11894 for_each_intel_connector(dev, connector) {
9a935856
DV		 11895 /* Otherwise traverse passed in connector list and get encoders
11896 * for them. */
50f56119 11897 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 11898 if (set->connectors[ro] == &connector->base) {
0e32b39c 11899 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
50f56119
DV		 11900 break;
11901 }
11902 }
11903
9a935856
DV		 11904 /* If we disable the crtc, disable all its connectors. Also, if
11905 * the connector is on the changing crtc but not on the new
11906 * connector list, disable it. */
11907 if ((!set->fb || ro == set->num_connectors) &&
11908 connector->base.encoder &&
11909 connector->base.encoder->crtc == set->crtc) {
11910 connector->new_encoder = NULL;
11911
11912 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11913 connector->base.base.id,
c23cc417 11914 connector->base.name);
9a935856
DV		 11915 }
11916
11917
11918 if (&connector->new_encoder->base != connector->base.encoder) {
10634189
ACO		 11919 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n",
11920 connector->base.base.id,
11921 connector->base.name);
5e2b584e 11922 config->mode_changed = true;
50f56119
DV		 11923 }
11924 }
9a935856 11925 /* connector->new_encoder is now updated for all connectors. */
50f56119 11926
9a935856 11927 /* Update crtc of enabled connectors. */
3a3371ff 11928 for_each_intel_connector(dev, connector) {
7668851f
VS		 11929 struct drm_crtc *new_crtc;
11930
9a935856 11931 if (!connector->new_encoder)
50f56119
DV		 11932 continue;
11933
9a935856 11934 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 11935
11936 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 11937 if (set->connectors[ro] == &connector->base)
50f56119
DV		 11938 new_crtc = set->crtc;
11939 }
11940
11941 /* Make sure the new CRTC will work with the encoder */
14509916
TR		 11942 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11943 new_crtc)) {
5e2b584e 11944 return -EINVAL;
50f56119 11945 }
0e32b39c 11946 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
9a935856 11947
944b0c76
ACO		 11948 connector_state =
11949 drm_atomic_get_connector_state(state, &connector->base);
11950 if (IS_ERR(connector_state))
11951 return PTR_ERR(connector_state);
11952
11953 connector_state->crtc = new_crtc;
11954 connector_state->best_encoder = &connector->new_encoder->base;
11955
9a935856
DV		 11956 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11957 connector->base.base.id,
c23cc417 11958 connector->base.name,
9a935856
DV		 11959 new_crtc->base.id);
11960 }
11961
11962 /* Check for any encoders that needs to be disabled. */
b2784e15 11963 for_each_intel_encoder(dev, encoder) {
5a65f358 11964 int num_connectors = 0;
3a3371ff 11965 for_each_intel_connector(dev, connector) {
9a935856
DV		 11966 if (connector->new_encoder == encoder) {
11967 WARN_ON(!connector->new_encoder->new_crtc);
5a65f358 11968 num_connectors++;
9a935856
DV		 11969 }
11970 }
5a65f358
PZ		 11971
11972 if (num_connectors == 0)
11973 encoder->new_crtc = NULL;
11974 else if (num_connectors > 1)
11975 return -EINVAL;
11976
9a935856
DV		 11977 /* Only now check for crtc changes so we don't miss encoders
11978 * that will be disabled. */
11979 if (&encoder->new_crtc->base != encoder->base.crtc) {
10634189
ACO		 11980 DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n",
11981 encoder->base.base.id,
11982 encoder->base.name);
5e2b584e 11983 config->mode_changed = true;
50f56119
DV		 11984 }
11985 }
9a935856 11986 /* Now we've also updated encoder->new_crtc for all encoders. */
3a3371ff 11987 for_each_intel_connector(dev, connector) {
944b0c76
ACO		 11988 connector_state =
11989 drm_atomic_get_connector_state(state, &connector->base);
11990
11991 if (connector->new_encoder) {
0e32b39c
DA		 11992 if (connector->new_encoder != connector->encoder)
11993 connector->encoder = connector->new_encoder;
944b0c76
ACO		 11994 } else {
11995 connector_state->crtc = NULL;
11996 }
0e32b39c 11997 }
d3fcc808 11998 for_each_intel_crtc(dev, crtc) {
7668851f
VS		 11999 crtc->new_enabled = false;
12000
b2784e15 12001 for_each_intel_encoder(dev, encoder) {
7668851f
VS		 12002 if (encoder->new_crtc == crtc) {
12003 crtc->new_enabled = true;
12004 break;
12005 }
12006 }
12007
83d65738 12008 if (crtc->new_enabled != crtc->base.state->enable) {
10634189
ACO		 12009 DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n",
12010 crtc->base.base.id,
7668851f
VS		 12011 crtc->new_enabled ? "en" : "dis");
12012 config->mode_changed = true;
12013 }
7bd0a8e7
VS		 12014
12015 if (crtc->new_enabled)
6e3c9717 12016 crtc->new_config = crtc->config;
7bd0a8e7
VS		 12017 else
12018 crtc->new_config = NULL;
7668851f
VS		 12019 }
12020
2e431051
DV		 12021 return 0;
12022}
12023
7d00a1f5
VS		 12024static void disable_crtc_nofb(struct intel_crtc *crtc)
12025{
12026 struct drm_device *dev = crtc->base.dev;
12027 struct intel_encoder *encoder;
12028 struct intel_connector *connector;
12029
12030 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
12031 pipe_name(crtc->pipe));
12032
3a3371ff 12033 for_each_intel_connector(dev, connector) {
7d00a1f5
VS		 12034 if (connector->new_encoder &&
12035 connector->new_encoder->new_crtc == crtc)
12036 connector->new_encoder = NULL;
12037 }
12038
b2784e15 12039 for_each_intel_encoder(dev, encoder) {
7d00a1f5
VS		 12040 if (encoder->new_crtc == crtc)
12041 encoder->new_crtc = NULL;
12042 }
12043
12044 crtc->new_enabled = false;
7bd0a8e7 12045 crtc->new_config = NULL;
7d00a1f5
VS		 12046}
12047
2e431051
DV		 12048static int intel_crtc_set_config(struct drm_mode_set *set)
12049{
12050 struct drm_device *dev;
2e431051 12051 struct drm_mode_set save_set;
83a57153 12052 struct drm_atomic_state *state = NULL;
2e431051 12053 struct intel_set_config *config;
5cec258b 12054 struct intel_crtc_state *pipe_config;
50f52756 12055 unsigned modeset_pipes, prepare_pipes, disable_pipes;
2e431051 12056 int ret;
2e431051 12057
8d3e375e
DV		 12058 BUG_ON(!set);
12059 BUG_ON(!set->crtc);
12060 BUG_ON(!set->crtc->helper_private);
2e431051 12061
7e53f3a4
DV		 12062 /* Enforce sane interface api - has been abused by the fb helper. */
12063 BUG_ON(!set->mode && set->fb);
12064 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 12065
2e431051
DV		 12066 if (set->fb) {
12067 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
12068 set->crtc->base.id, set->fb->base.id,
12069 (int)set->num_connectors, set->x, set->y);
12070 } else {
12071 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 12072 }
12073
12074 dev = set->crtc->dev;
12075
12076 ret = -ENOMEM;
12077 config = kzalloc(sizeof(*config), GFP_KERNEL);
12078 if (!config)
12079 goto out_config;
12080
12081 ret = intel_set_config_save_state(dev, config);
12082 if (ret)
12083 goto out_config;
12084
12085 save_set.crtc = set->crtc;
12086 save_set.mode = &set->crtc->mode;
12087 save_set.x = set->crtc->x;
12088 save_set.y = set->crtc->y;
f4510a27 12089 save_set.fb = set->crtc->primary->fb;
2e431051
DV		 12090
12091 /* Compute whether we need a full modeset, only an fb base update or no
12092 * change at all. In the future we might also check whether only the
12093 * mode changed, e.g. for LVDS where we only change the panel fitter in
12094 * such cases. */
12095 intel_set_config_compute_mode_changes(set, config);
12096
83a57153
ACO		 12097 state = drm_atomic_state_alloc(dev);
12098 if (!state) {
12099 ret = -ENOMEM;
12100 goto out_config;
12101 }
12102
12103 state->acquire_ctx = dev->mode_config.acquire_ctx;
12104
944b0c76 12105 ret = intel_modeset_stage_output_state(dev, set, config, state);
2e431051
DV		 12106 if (ret)
12107 goto fail;
12108
50f52756 12109 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
83a57153 12110 set->fb, state,
50f52756
JB		 12111 &modeset_pipes,
12112 &prepare_pipes,
12113 &disable_pipes);
20664591 12114 if (IS_ERR(pipe_config)) {
6ac0483b 12115 ret = PTR_ERR(pipe_config);
50f52756 12116 goto fail;
20664591 12117 } else if (pipe_config) {
b9950a13 12118 if (pipe_config->has_audio !=
6e3c9717 12119 to_intel_crtc(set->crtc)->config->has_audio)
20664591
JB		 12120 config->mode_changed = true;
12121
af15d2ce
JB		 12122 /*
12123 * Note we have an issue here with infoframes: current code
12124 * only updates them on the full mode set path per hw
12125 * requirements. So here we should be checking for any
12126 * required changes and forcing a mode set.
12127 */
20664591 12128 }
50f52756 12129
1f9954d0
JB		 12130 intel_update_pipe_size(to_intel_crtc(set->crtc));
12131
5e2b584e 12132 if (config->mode_changed) {
50f52756
JB		 12133 ret = intel_set_mode_pipes(set->crtc, set->mode,
12134 set->x, set->y, set->fb, pipe_config,
12135 modeset_pipes, prepare_pipes,
12136 disable_pipes);
5e2b584e 12137 } else if (config->fb_changed) {
3b150f08 12138 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
455a6808
GP		 12139 struct drm_plane *primary = set->crtc->primary;
12140 int vdisplay, hdisplay;
3b150f08 12141
455a6808
GP		 12142 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
12143 ret = primary->funcs->update_plane(primary, set->crtc, set->fb,
12144 0, 0, hdisplay, vdisplay,
12145 set->x << 16, set->y << 16,
12146 hdisplay << 16, vdisplay << 16);
3b150f08
MR		 12147
12148 /*
12149 * We need to make sure the primary plane is re-enabled if it
12150 * has previously been turned off.
12151 */
12152 if (!intel_crtc->primary_enabled && ret == 0) {
12153 WARN_ON(!intel_crtc->active);
fdd508a6 12154 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
3b150f08
MR		 12155 }
12156
7ca51a3a
JB		 12157 /*
12158 * In the fastboot case this may be our only check of the
12159 * state after boot. It would be better to only do it on
12160 * the first update, but we don't have a nice way of doing that
12161 * (and really, set_config isn't used much for high freq page
12162 * flipping, so increasing its cost here shouldn't be a big
12163 * deal).
12164 */
d330a953 12165 if (i915.fastboot && ret == 0)
7ca51a3a 12166 intel_modeset_check_state(set->crtc->dev);
50f56119
DV		 12167 }
12168
2d05eae1 12169 if (ret) {
bf67dfeb
DV		 12170 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
12171 set->crtc->base.id, ret);
50f56119 12172fail:
2d05eae1 12173 intel_set_config_restore_state(dev, config);
50f56119 12174
83a57153
ACO		 12175 drm_atomic_state_clear(state);
12176
7d00a1f5
VS		 12177 /*
12178 * HACK: if the pipe was on, but we didn't have a framebuffer,
12179 * force the pipe off to avoid oopsing in the modeset code
12180 * due to fb==NULL. This should only happen during boot since
12181 * we don't yet reconstruct the FB from the hardware state.
12182 */
12183 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
12184 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
12185
2d05eae1
CW		 12186 /* Try to restore the config */
12187 if (config->mode_changed &&
12188 intel_set_mode(save_set.crtc, save_set.mode,
83a57153
ACO		 12189 save_set.x, save_set.y, save_set.fb,
12190 state))
2d05eae1
CW		 12191 DRM_ERROR("failed to restore config after modeset failure\n");
12192 }
50f56119 12193
d9e55608 12194out_config:
83a57153
ACO		 12195 if (state)
12196 drm_atomic_state_free(state);
12197
d9e55608 12198 intel_set_config_free(config);
50f56119
DV		 12199 return ret;
12200}
f6e5b160
CW		 12201
12202static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 12203 .gamma_set = intel_crtc_gamma_set,
50f56119 12204 .set_config = intel_crtc_set_config,
f6e5b160
CW		 12205 .destroy = intel_crtc_destroy,
12206 .page_flip = intel_crtc_page_flip,
1356837e
MR		 12207 .atomic_duplicate_state = intel_crtc_duplicate_state,
12208 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 12209};
12210
5358901f
DV		 12211static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
12212 struct intel_shared_dpll *pll,
12213 struct intel_dpll_hw_state *hw_state)
ee7b9f93 12214{
5358901f 12215 uint32_t val;
ee7b9f93 12216
f458ebbc 12217 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 12218 return false;
12219
5358901f 12220 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 12221 hw_state->dpll = val;
12222 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
12223 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 12224
12225 return val & DPLL_VCO_ENABLE;
12226}
12227
15bdd4cf
DV		 12228static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
12229 struct intel_shared_dpll *pll)
12230{
3e369b76
ACO		 12231 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
12232 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 12233}
12234
e7b903d2
DV		 12235static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
12236 struct intel_shared_dpll *pll)
12237{
e7b903d2 12238 /* PCH refclock must be enabled first */
89eff4be 12239 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 12240
3e369b76 12241 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 12242
12243 /* Wait for the clocks to stabilize. */
12244 POSTING_READ(PCH_DPLL(pll->id));
12245 udelay(150);
12246
12247 /* The pixel multiplier can only be updated once the
12248 * DPLL is enabled and the clocks are stable.
12249 *
12250 * So write it again.
12251 */
3e369b76 12252 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 12253 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 12254 udelay(200);
12255}
12256
12257static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
12258 struct intel_shared_dpll *pll)
12259{
12260 struct drm_device *dev = dev_priv->dev;
12261 struct intel_crtc *crtc;
e7b903d2
DV		 12262
12263 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 12264 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 12265 if (intel_crtc_to_shared_dpll(crtc) == pll)
12266 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 12267 }
12268
15bdd4cf
DV		 12269 I915_WRITE(PCH_DPLL(pll->id), 0);
12270 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 12271 udelay(200);
12272}
12273
46edb027
DV		 12274static char *ibx_pch_dpll_names[] = {
12275 "PCH DPLL A",
12276 "PCH DPLL B",
12277};
12278
7c74ade1 12279static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 12280{
e7b903d2 12281 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 12282 int i;
12283
7c74ade1 12284 dev_priv->num_shared_dpll = 2;
ee7b9f93 12285
e72f9fbf 12286 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 12287 dev_priv->shared_dplls[i].id = i;
12288 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 12289 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 12290 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
12291 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 12292 dev_priv->shared_dplls[i].get_hw_state =
12293 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 12294 }
12295}
12296
7c74ade1
DV		 12297static void intel_shared_dpll_init(struct drm_device *dev)
12298{
e7b903d2 12299 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 12300
9cd86933
DV		 12301 if (HAS_DDI(dev))
12302 intel_ddi_pll_init(dev);
12303 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 12304 ibx_pch_dpll_init(dev);
12305 else
12306 dev_priv->num_shared_dpll = 0;
12307
12308 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 12309}
12310
1fc0a8f7
TU		 12311/**
12312 * intel_wm_need_update - Check whether watermarks need updating
12313 * @plane: drm plane
12314 * @state: new plane state
12315 *
12316 * Check current plane state versus the new one to determine whether
12317 * watermarks need to be recalculated.
12318 *
12319 * Returns true or false.
12320 */
12321bool intel_wm_need_update(struct drm_plane *plane,
12322 struct drm_plane_state *state)
12323{
12324 /* Update watermarks on tiling changes. */
12325 if (!plane->state->fb || !state->fb ||
12326 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
12327 plane->state->rotation != state->rotation)
12328 return true;
12329
12330 return false;
12331}
12332
6beb8c23
MR		 12333/**
12334 * intel_prepare_plane_fb - Prepare fb for usage on plane
12335 * @plane: drm plane to prepare for
12336 * @fb: framebuffer to prepare for presentation
12337 *
12338 * Prepares a framebuffer for usage on a display plane. Generally this
12339 * involves pinning the underlying object and updating the frontbuffer tracking
12340 * bits. Some older platforms need special physical address handling for
12341 * cursor planes.
12342 *
12343 * Returns 0 on success, negative error code on failure.
12344 */
12345int
12346intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee
TU		 12347 struct drm_framebuffer *fb,
12348 const struct drm_plane_state *new_state)
465c120c
MR		 12349{
12350 struct drm_device *dev = plane->dev;
6beb8c23
MR		 12351 struct intel_plane *intel_plane = to_intel_plane(plane);
12352 enum pipe pipe = intel_plane->pipe;
12353 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12354 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
12355 unsigned frontbuffer_bits = 0;
12356 int ret = 0;
465c120c 12357
ea2c67bb 12358 if (!obj)
465c120c
MR		 12359 return 0;
12360
6beb8c23
MR		 12361 switch (plane->type) {
12362 case DRM_PLANE_TYPE_PRIMARY:
12363 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
12364 break;
12365 case DRM_PLANE_TYPE_CURSOR:
12366 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
12367 break;
12368 case DRM_PLANE_TYPE_OVERLAY:
12369 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
12370 break;
12371 }
465c120c 12372
6beb8c23 12373 mutex_lock(&dev->struct_mutex);
465c120c 12374
6beb8c23
MR		 12375 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
12376 INTEL_INFO(dev)->cursor_needs_physical) {
12377 int align = IS_I830(dev) ? 16 * 1024 : 256;
12378 ret = i915_gem_object_attach_phys(obj, align);
12379 if (ret)
12380 DRM_DEBUG_KMS("failed to attach phys object\n");
12381 } else {
82bc3b2d 12382 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
6beb8c23 12383 }
465c120c 12384
6beb8c23
MR		 12385 if (ret == 0)
12386 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
fdd508a6 12387
4c34574f 12388 mutex_unlock(&dev->struct_mutex);
465c120c 12389
6beb8c23
MR		 12390 return ret;
12391}
12392
38f3ce3a
MR		 12393/**
12394 * intel_cleanup_plane_fb - Cleans up an fb after plane use
12395 * @plane: drm plane to clean up for
12396 * @fb: old framebuffer that was on plane
12397 *
12398 * Cleans up a framebuffer that has just been removed from a plane.
12399 */
12400void
12401intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee
TU		 12402 struct drm_framebuffer *fb,
12403 const struct drm_plane_state *old_state)
38f3ce3a
MR		 12404{
12405 struct drm_device *dev = plane->dev;
12406 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12407
12408 if (WARN_ON(!obj))
12409 return;
12410
12411 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
12412 !INTEL_INFO(dev)->cursor_needs_physical) {
12413 mutex_lock(&dev->struct_mutex);
82bc3b2d 12414 intel_unpin_fb_obj(fb, old_state);
38f3ce3a
MR		 12415 mutex_unlock(&dev->struct_mutex);
12416 }
465c120c
MR		 12417}
12418
12419static int
3c692a41
GP		 12420intel_check_primary_plane(struct drm_plane *plane,
12421 struct intel_plane_state *state)
12422{
32b7eeec
MR		 12423 struct drm_device *dev = plane->dev;
12424 struct drm_i915_private *dev_priv = dev->dev_private;
2b875c22 12425 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 12426 struct intel_crtc *intel_crtc;
2b875c22 12427 struct drm_framebuffer *fb = state->base.fb;
3c692a41
GP		 12428 struct drm_rect *dest = &state->dst;
12429 struct drm_rect *src = &state->src;
12430 const struct drm_rect *clip = &state->clip;
465c120c
MR		 12431 int ret;
12432
ea2c67bb
MR		 12433 crtc = crtc ? crtc : plane->crtc;
12434 intel_crtc = to_intel_crtc(crtc);
12435
c59cb179
MR		 12436 ret = drm_plane_helper_check_update(plane, crtc, fb,
12437 src, dest, clip,
12438 DRM_PLANE_HELPER_NO_SCALING,
12439 DRM_PLANE_HELPER_NO_SCALING,
12440 false, true, &state->visible);
12441 if (ret)
12442 return ret;
465c120c 12443
32b7eeec
MR		 12444 if (intel_crtc->active) {
12445 intel_crtc->atomic.wait_for_flips = true;
12446
12447 /*
12448 * FBC does not work on some platforms for rotated
12449 * planes, so disable it when rotation is not 0 and
12450 * update it when rotation is set back to 0.
12451 *
12452 * FIXME: This is redundant with the fbc update done in
12453 * the primary plane enable function except that that
12454 * one is done too late. We eventually need to unify
12455 * this.
12456 */
12457 if (intel_crtc->primary_enabled &&
12458 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
e35fef21 12459 dev_priv->fbc.crtc == intel_crtc &&
8e7d688b 12460 state->base.rotation != BIT(DRM_ROTATE_0)) {
32b7eeec
MR		 12461 intel_crtc->atomic.disable_fbc = true;
12462 }
12463
12464 if (state->visible) {
12465 /*
12466 * BDW signals flip done immediately if the plane
12467 * is disabled, even if the plane enable is already
12468 * armed to occur at the next vblank :(
12469 */
12470 if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
12471 intel_crtc->atomic.wait_vblank = true;
12472 }
12473
12474 intel_crtc->atomic.fb_bits |=
12475 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
12476
12477 intel_crtc->atomic.update_fbc = true;
0fda6568 12478
1fc0a8f7 12479 if (intel_wm_need_update(plane, &state->base))
0fda6568 12480 intel_crtc->atomic.update_wm = true;
ccc759dc
GP		 12481 }
12482
14af293f
GP		 12483 return 0;
12484}
12485
12486static void
12487intel_commit_primary_plane(struct drm_plane *plane,
12488 struct intel_plane_state *state)
12489{
2b875c22
MR		 12490 struct drm_crtc *crtc = state->base.crtc;
12491 struct drm_framebuffer *fb = state->base.fb;
12492 struct drm_device *dev = plane->dev;
14af293f 12493 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 12494 struct intel_crtc *intel_crtc;
14af293f
GP		 12495 struct drm_rect *src = &state->src;
12496
ea2c67bb
MR		 12497 crtc = crtc ? crtc : plane->crtc;
12498 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR		 12499
12500 plane->fb = fb;
9dc806fc
MR		 12501 crtc->x = src->x1 >> 16;
12502 crtc->y = src->y1 >> 16;
ccc759dc 12503
ccc759dc 12504 if (intel_crtc->active) {
ccc759dc 12505 if (state->visible) {
ccc759dc
GP		 12506 /* FIXME: kill this fastboot hack */
12507 intel_update_pipe_size(intel_crtc);
465c120c 12508
ccc759dc 12509 intel_crtc->primary_enabled = true;
465c120c 12510
ccc759dc
GP		 12511 dev_priv->display.update_primary_plane(crtc, plane->fb,
12512 crtc->x, crtc->y);
ccc759dc
GP		 12513 } else {
12514 /*
12515 * If clipping results in a non-visible primary plane,
12516 * we'll disable the primary plane. Note that this is
12517 * a bit different than what happens if userspace
12518 * explicitly disables the plane by passing fb=0
12519 * because plane->fb still gets set and pinned.
12520 */
12521 intel_disable_primary_hw_plane(plane, crtc);
48404c1e 12522 }
ccc759dc 12523 }
465c120c
MR		 12524}
12525
32b7eeec 12526static void intel_begin_crtc_commit(struct drm_crtc *crtc)
3c692a41 12527{
32b7eeec 12528 struct drm_device *dev = crtc->dev;
140fd38d 12529 struct drm_i915_private *dev_priv = dev->dev_private;
3c692a41 12530 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ea2c67bb
MR		 12531 struct intel_plane *intel_plane;
12532 struct drm_plane *p;
12533 unsigned fb_bits = 0;
12534
12535 /* Track fb's for any planes being disabled */
12536 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
12537 intel_plane = to_intel_plane(p);
12538
12539 if (intel_crtc->atomic.disabled_planes &
12540 (1 << drm_plane_index(p))) {
12541 switch (p->type) {
12542 case DRM_PLANE_TYPE_PRIMARY:
12543 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
12544 break;
12545 case DRM_PLANE_TYPE_CURSOR:
12546 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
12547 break;
12548 case DRM_PLANE_TYPE_OVERLAY:
12549 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
12550 break;
12551 }
3c692a41 12552
ea2c67bb
MR		 12553 mutex_lock(&dev->struct_mutex);
12554 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
12555 mutex_unlock(&dev->struct_mutex);
12556 }
12557 }
3c692a41 12558
32b7eeec
MR		 12559 if (intel_crtc->atomic.wait_for_flips)
12560 intel_crtc_wait_for_pending_flips(crtc);
3c692a41 12561
32b7eeec
MR		 12562 if (intel_crtc->atomic.disable_fbc)
12563 intel_fbc_disable(dev);
3c692a41 12564
32b7eeec
MR		 12565 if (intel_crtc->atomic.pre_disable_primary)
12566 intel_pre_disable_primary(crtc);
3c692a41 12567
32b7eeec
MR		 12568 if (intel_crtc->atomic.update_wm)
12569 intel_update_watermarks(crtc);
3c692a41 12570
32b7eeec 12571 intel_runtime_pm_get(dev_priv);
3c692a41 12572
c34c9ee4
MR		 12573 /* Perform vblank evasion around commit operation */
12574 if (intel_crtc->active)
12575 intel_crtc->atomic.evade =
12576 intel_pipe_update_start(intel_crtc,
12577 &intel_crtc->atomic.start_vbl_count);
32b7eeec
MR		 12578}
12579
12580static void intel_finish_crtc_commit(struct drm_crtc *crtc)
12581{
12582 struct drm_device *dev = crtc->dev;
12583 struct drm_i915_private *dev_priv = dev->dev_private;
12584 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12585 struct drm_plane *p;
12586
c34c9ee4
MR		 12587 if (intel_crtc->atomic.evade)
12588 intel_pipe_update_end(intel_crtc,
12589 intel_crtc->atomic.start_vbl_count);
3c692a41 12590
140fd38d 12591 intel_runtime_pm_put(dev_priv);
3c692a41 12592
32b7eeec
MR		 12593 if (intel_crtc->atomic.wait_vblank)
12594 intel_wait_for_vblank(dev, intel_crtc->pipe);
12595
12596 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
12597
12598 if (intel_crtc->atomic.update_fbc) {
ccc759dc 12599 mutex_lock(&dev->struct_mutex);
7ff0ebcc 12600 intel_fbc_update(dev);
ccc759dc 12601 mutex_unlock(&dev->struct_mutex);
38f3ce3a 12602 }
3c692a41 12603
32b7eeec
MR		 12604 if (intel_crtc->atomic.post_enable_primary)
12605 intel_post_enable_primary(crtc);
3c692a41 12606
32b7eeec
MR		 12607 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
12608 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
12609 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
12610 false, false);
12611
12612 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
3c692a41
GP		 12613}
12614
cf4c7c12 12615/**
4a3b8769
MR		 12616 * intel_plane_destroy - destroy a plane
12617 * @plane: plane to destroy
cf4c7c12 12618 *
4a3b8769
MR		 12619 * Common destruction function for all types of planes (primary, cursor,
12620 * sprite).
cf4c7c12 12621 */
4a3b8769 12622void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 12623{
12624 struct intel_plane *intel_plane = to_intel_plane(plane);
12625 drm_plane_cleanup(plane);
12626 kfree(intel_plane);
12627}
12628
65a3fea0 12629const struct drm_plane_funcs intel_plane_funcs = {
ff42e093
DV		 12630 .update_plane = drm_plane_helper_update,
12631 .disable_plane = drm_plane_helper_disable,
3d7d6510 12632 .destroy = intel_plane_destroy,
c196e1d6 12633 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 12634 .atomic_get_property = intel_plane_atomic_get_property,
12635 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 12636 .atomic_duplicate_state = intel_plane_duplicate_state,
12637 .atomic_destroy_state = intel_plane_destroy_state,
12638
465c120c
MR		 12639};
12640
12641static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
12642 int pipe)
12643{
12644 struct intel_plane *primary;
8e7d688b 12645 struct intel_plane_state *state;
465c120c
MR		 12646 const uint32_t *intel_primary_formats;
12647 int num_formats;
12648
12649 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12650 if (primary == NULL)
12651 return NULL;
12652
8e7d688b
MR		 12653 state = intel_create_plane_state(&primary->base);
12654 if (!state) {
ea2c67bb
MR		 12655 kfree(primary);
12656 return NULL;
12657 }
8e7d688b 12658 primary->base.state = &state->base;
ea2c67bb 12659
465c120c
MR		 12660 primary->can_scale = false;
12661 primary->max_downscale = 1;
12662 primary->pipe = pipe;
12663 primary->plane = pipe;
c59cb179
MR		 12664 primary->check_plane = intel_check_primary_plane;
12665 primary->commit_plane = intel_commit_primary_plane;
465c120c
MR		 12666 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12667 primary->plane = !pipe;
12668
12669 if (INTEL_INFO(dev)->gen <= 3) {
12670 intel_primary_formats = intel_primary_formats_gen2;
12671 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12672 } else {
12673 intel_primary_formats = intel_primary_formats_gen4;
12674 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12675 }
12676
12677 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 12678 &intel_plane_funcs,
465c120c
MR		 12679 intel_primary_formats, num_formats,
12680 DRM_PLANE_TYPE_PRIMARY);
48404c1e
SJ		 12681
12682 if (INTEL_INFO(dev)->gen >= 4) {
12683 if (!dev->mode_config.rotation_property)
12684 dev->mode_config.rotation_property =
12685 drm_mode_create_rotation_property(dev,
12686 BIT(DRM_ROTATE_0) |
12687 BIT(DRM_ROTATE_180));
12688 if (dev->mode_config.rotation_property)
12689 drm_object_attach_property(&primary->base.base,
12690 dev->mode_config.rotation_property,
8e7d688b 12691 state->base.rotation);
48404c1e
SJ		 12692 }
12693
ea2c67bb
MR		 12694 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
12695
465c120c
MR		 12696 return &primary->base;
12697}
12698
3d7d6510 12699static int
852e787c
GP		 12700intel_check_cursor_plane(struct drm_plane *plane,
12701 struct intel_plane_state *state)
3d7d6510 12702{
2b875c22 12703 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 12704 struct drm_device *dev = plane->dev;
2b875c22 12705 struct drm_framebuffer *fb = state->base.fb;
852e787c
GP		 12706 struct drm_rect *dest = &state->dst;
12707 struct drm_rect *src = &state->src;
12708 const struct drm_rect *clip = &state->clip;
757f9a3e 12709 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
ea2c67bb 12710 struct intel_crtc *intel_crtc;
757f9a3e
GP		 12711 unsigned stride;
12712 int ret;
3d7d6510 12713
ea2c67bb
MR		 12714 crtc = crtc ? crtc : plane->crtc;
12715 intel_crtc = to_intel_crtc(crtc);
12716
757f9a3e 12717 ret = drm_plane_helper_check_update(plane, crtc, fb,
852e787c 12718 src, dest, clip,
3d7d6510
MR		 12719 DRM_PLANE_HELPER_NO_SCALING,
12720 DRM_PLANE_HELPER_NO_SCALING,
852e787c 12721 true, true, &state->visible);
757f9a3e
GP		 12722 if (ret)
12723 return ret;
12724
12725
12726 /* if we want to turn off the cursor ignore width and height */
12727 if (!obj)
32b7eeec 12728 goto finish;
757f9a3e 12729
757f9a3e 12730 /* Check for which cursor types we support */
ea2c67bb
MR		 12731 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
12732 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12733 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 12734 return -EINVAL;
12735 }
12736
ea2c67bb
MR		 12737 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
12738 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 12739 DRM_DEBUG_KMS("buffer is too small\n");
12740 return -ENOMEM;
12741 }
12742
3a656b54 12743 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e
GP		 12744 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12745 ret = -EINVAL;
12746 }
757f9a3e 12747
32b7eeec
MR		 12748finish:
12749 if (intel_crtc->active) {
3749f463 12750 if (plane->state->crtc_w != state->base.crtc_w)
32b7eeec
MR		 12751 intel_crtc->atomic.update_wm = true;
12752
12753 intel_crtc->atomic.fb_bits |=
12754 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
12755 }
12756
757f9a3e 12757 return ret;
852e787c 12758}
3d7d6510 12759
f4a2cf29 12760static void
852e787c
GP		 12761intel_commit_cursor_plane(struct drm_plane *plane,
12762 struct intel_plane_state *state)
12763{
2b875c22 12764 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 12765 struct drm_device *dev = plane->dev;
12766 struct intel_crtc *intel_crtc;
2b875c22 12767 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 12768 uint32_t addr;
852e787c 12769
ea2c67bb
MR		 12770 crtc = crtc ? crtc : plane->crtc;
12771 intel_crtc = to_intel_crtc(crtc);
12772
2b875c22 12773 plane->fb = state->base.fb;
ea2c67bb
MR		 12774 crtc->cursor_x = state->base.crtc_x;
12775 crtc->cursor_y = state->base.crtc_y;
12776
a912f12f
GP		 12777 if (intel_crtc->cursor_bo == obj)
12778 goto update;
4ed91096 12779
f4a2cf29 12780 if (!obj)
a912f12f 12781 addr = 0;
f4a2cf29 12782 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 12783 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 12784 else
a912f12f 12785 addr = obj->phys_handle->busaddr;
852e787c 12786
a912f12f
GP		 12787 intel_crtc->cursor_addr = addr;
12788 intel_crtc->cursor_bo = obj;
12789update:
852e787c 12790
32b7eeec 12791 if (intel_crtc->active)
a912f12f 12792 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 12793}
12794
3d7d6510
MR		 12795static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12796 int pipe)
12797{
12798 struct intel_plane *cursor;
8e7d688b 12799 struct intel_plane_state *state;
3d7d6510
MR		 12800
12801 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12802 if (cursor == NULL)
12803 return NULL;
12804
8e7d688b
MR		 12805 state = intel_create_plane_state(&cursor->base);
12806 if (!state) {
ea2c67bb
MR		 12807 kfree(cursor);
12808 return NULL;
12809 }
8e7d688b 12810 cursor->base.state = &state->base;
ea2c67bb 12811
3d7d6510
MR		 12812 cursor->can_scale = false;
12813 cursor->max_downscale = 1;
12814 cursor->pipe = pipe;
12815 cursor->plane = pipe;
c59cb179
MR		 12816 cursor->check_plane = intel_check_cursor_plane;
12817 cursor->commit_plane = intel_commit_cursor_plane;
3d7d6510
MR		 12818
12819 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 12820 &intel_plane_funcs,
3d7d6510
MR		 12821 intel_cursor_formats,
12822 ARRAY_SIZE(intel_cursor_formats),
12823 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 12824
12825 if (INTEL_INFO(dev)->gen >= 4) {
12826 if (!dev->mode_config.rotation_property)
12827 dev->mode_config.rotation_property =
12828 drm_mode_create_rotation_property(dev,
12829 BIT(DRM_ROTATE_0) |
12830 BIT(DRM_ROTATE_180));
12831 if (dev->mode_config.rotation_property)
12832 drm_object_attach_property(&cursor->base.base,
12833 dev->mode_config.rotation_property,
8e7d688b 12834 state->base.rotation);
4398ad45
VS		 12835 }
12836
ea2c67bb
MR		 12837 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
12838
3d7d6510
MR		 12839 return &cursor->base;
12840}
12841
b358d0a6 12842static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 12843{
fbee40df 12844 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 12845 struct intel_crtc *intel_crtc;
f5de6e07 12846 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 12847 struct drm_plane *primary = NULL;
12848 struct drm_plane *cursor = NULL;
465c120c 12849 int i, ret;
79e53945 12850
955382f3 12851 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 12852 if (intel_crtc == NULL)
12853 return;
12854
f5de6e07
ACO		 12855 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
12856 if (!crtc_state)
12857 goto fail;
12858 intel_crtc_set_state(intel_crtc, crtc_state);
07878248 12859 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 12860
465c120c 12861 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 12862 if (!primary)
12863 goto fail;
12864
12865 cursor = intel_cursor_plane_create(dev, pipe);
12866 if (!cursor)
12867 goto fail;
12868
465c120c 12869 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 12870 cursor, &intel_crtc_funcs);
12871 if (ret)
12872 goto fail;
79e53945
JB		 12873
12874 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 12875 for (i = 0; i < 256; i++) {
12876 intel_crtc->lut_r[i] = i;
12877 intel_crtc->lut_g[i] = i;
12878 intel_crtc->lut_b[i] = i;
12879 }
12880
1f1c2e24
VS		 12881 /*
12882 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 12883 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 12884 */
80824003
JB		 12885 intel_crtc->pipe = pipe;
12886 intel_crtc->plane = pipe;
3a77c4c4 12887 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 12888 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 12889 intel_crtc->plane = !pipe;
80824003
JB		 12890 }
12891
4b0e333e
CW		 12892 intel_crtc->cursor_base = ~0;
12893 intel_crtc->cursor_cntl = ~0;
dc41c154 12894 intel_crtc->cursor_size = ~0;
8d7849db 12895
22fd0fab
JB		 12896 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12897 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12898 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12899 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12900
9362c7c5
ACO		 12901 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12902
79e53945 12903 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 12904
12905 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 12906 return;
12907
12908fail:
12909 if (primary)
12910 drm_plane_cleanup(primary);
12911 if (cursor)
12912 drm_plane_cleanup(cursor);
f5de6e07 12913 kfree(crtc_state);
3d7d6510 12914 kfree(intel_crtc);
79e53945
JB		 12915}
12916
752aa88a
JB		 12917enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12918{
12919 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 12920 struct drm_device *dev = connector->base.dev;
752aa88a 12921
51fd371b 12922 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 12923
d3babd3f 12924 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 12925 return INVALID_PIPE;
12926
12927 return to_intel_crtc(encoder->crtc)->pipe;
12928}
12929
08d7b3d1 12930int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 12931 struct drm_file *file)
08d7b3d1 12932{
08d7b3d1 12933 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 12934 struct drm_crtc *drmmode_crtc;
c05422d5 12935 struct intel_crtc *crtc;
08d7b3d1 12936
7707e653 12937 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 12938
7707e653 12939 if (!drmmode_crtc) {
08d7b3d1 12940 DRM_ERROR("no such CRTC id\n");
3f2c2057 12941 return -ENOENT;
08d7b3d1
CW		 12942 }
12943
7707e653 12944 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 12945 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 12946
c05422d5 12947 return 0;
08d7b3d1
CW		 12948}
12949
66a9278e 12950static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 12951{
66a9278e
DV		 12952 struct drm_device *dev = encoder->base.dev;
12953 struct intel_encoder *source_encoder;
79e53945 12954 int index_mask = 0;
79e53945
JB		 12955 int entry = 0;
12956
b2784e15 12957 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 12958 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 12959 index_mask |= (1 << entry);
12960
79e53945
JB		 12961 entry++;
12962 }
4ef69c7a 12963
79e53945
JB		 12964 return index_mask;
12965}
12966
4d302442
CW		 12967static bool has_edp_a(struct drm_device *dev)
12968{
12969 struct drm_i915_private *dev_priv = dev->dev_private;
12970
12971 if (!IS_MOBILE(dev))
12972 return false;
12973
12974 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12975 return false;
12976
e3589908 12977 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 12978 return false;
12979
12980 return true;
12981}
12982
84b4e042
JB		 12983static bool intel_crt_present(struct drm_device *dev)
12984{
12985 struct drm_i915_private *dev_priv = dev->dev_private;
12986
884497ed
DL		 12987 if (INTEL_INFO(dev)->gen >= 9)
12988 return false;
12989
cf404ce4 12990 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 12991 return false;
12992
12993 if (IS_CHERRYVIEW(dev))
12994 return false;
12995
12996 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12997 return false;
12998
12999 return true;
13000}
13001
79e53945
JB		 13002static void intel_setup_outputs(struct drm_device *dev)
13003{
725e30ad 13004 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 13005 struct intel_encoder *encoder;
c6f95f27 13006 struct drm_connector *connector;
cb0953d7 13007 bool dpd_is_edp = false;
79e53945 13008
c9093354 13009 intel_lvds_init(dev);
79e53945 13010
84b4e042 13011 if (intel_crt_present(dev))
79935fca 13012 intel_crt_init(dev);
cb0953d7 13013
affa9354 13014 if (HAS_DDI(dev)) {
0e72a5b5
ED		 13015 int found;
13016
de31facd
JB		 13017 /*
13018 * Haswell uses DDI functions to detect digital outputs.
13019 * On SKL pre-D0 the strap isn't connected, so we assume
13020 * it's there.
13021 */
0e72a5b5 13022 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
de31facd
JB		 13023 /* WaIgnoreDDIAStrap: skl */
13024 if (found ||
13025 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
0e72a5b5
ED		 13026 intel_ddi_init(dev, PORT_A);
13027
13028 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13029 * register */
13030 found = I915_READ(SFUSE_STRAP);
13031
13032 if (found & SFUSE_STRAP_DDIB_DETECTED)
13033 intel_ddi_init(dev, PORT_B);
13034 if (found & SFUSE_STRAP_DDIC_DETECTED)
13035 intel_ddi_init(dev, PORT_C);
13036 if (found & SFUSE_STRAP_DDID_DETECTED)
13037 intel_ddi_init(dev, PORT_D);
13038 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 13039 int found;
5d8a7752 13040 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 13041
13042 if (has_edp_a(dev))
13043 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 13044
dc0fa718 13045 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 13046 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 13047 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 13048 if (!found)
e2debe91 13049 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 13050 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 13051 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 13052 }
13053
dc0fa718 13054 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 13055 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 13056
dc0fa718 13057 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 13058 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 13059
5eb08b69 13060 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 13061 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 13062
270b3042 13063 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 13064 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 13065 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 13066 /*
13067 * The DP_DETECTED bit is the latched state of the DDC
13068 * SDA pin at boot. However since eDP doesn't require DDC
13069 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13070 * eDP ports may have been muxed to an alternate function.
13071 * Thus we can't rely on the DP_DETECTED bit alone to detect
13072 * eDP ports. Consult the VBT as well as DP_DETECTED to
13073 * detect eDP ports.
13074 */
d2182a66
VS		 13075 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
13076 !intel_dp_is_edp(dev, PORT_B))
585a94b8
AB		 13077 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
13078 PORT_B);
e17ac6db
VS		 13079 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
13080 intel_dp_is_edp(dev, PORT_B))
13081 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
585a94b8 13082
d2182a66
VS		 13083 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
13084 !intel_dp_is_edp(dev, PORT_C))
6f6005a5
JB		 13085 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
13086 PORT_C);
e17ac6db
VS		 13087 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
13088 intel_dp_is_edp(dev, PORT_C))
13089 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 13090
9418c1f1 13091 if (IS_CHERRYVIEW(dev)) {
e17ac6db 13092 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
9418c1f1
VS		 13093 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
13094 PORT_D);
e17ac6db
VS		 13095 /* eDP not supported on port D, so don't check VBT */
13096 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
13097 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
9418c1f1
VS		 13098 }
13099
3cfca973 13100 intel_dsi_init(dev);
103a196f 13101 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 13102 bool found = false;
7d57382e 13103
e2debe91 13104 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 13105 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 13106 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 13107 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
13108 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 13109 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 13110 }
27185ae1 13111
e7281eab 13112 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 13113 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 13114 }
13520b05
KH		 13115
13116 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 13117
e2debe91 13118 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 13119 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 13120 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 13121 }
27185ae1 13122
e2debe91 13123 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 13124
b01f2c3a
JB		 13125 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
13126 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 13127 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 13128 }
e7281eab 13129 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 13130 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 13131 }
27185ae1 13132
b01f2c3a 13133 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 13134 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 13135 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 13136 } else if (IS_GEN2(dev))
79e53945
JB		 13137 intel_dvo_init(dev);
13138
103a196f 13139 if (SUPPORTS_TV(dev))
79e53945
JB		 13140 intel_tv_init(dev);
13141
c6f95f27
MR		 13142 /*
13143 * FIXME: We don't have full atomic support yet, but we want to be
13144 * able to enable/test plane updates via the atomic interface in the
13145 * meantime. However as soon as we flip DRIVER_ATOMIC on, the DRM core
13146 * will take some atomic codepaths to lookup properties during
13147 * drmModeGetConnector() that unconditionally dereference
13148 * connector->state.
13149 *
13150 * We create a dummy connector state here for each connector to ensure
13151 * the DRM core doesn't try to dereference a NULL connector->state.
13152 * The actual connector properties will never be updated or contain
13153 * useful information, but since we're doing this specifically for
13154 * testing/debug of the plane operations (and only when a specific
13155 * kernel module option is given), that shouldn't really matter.
13156 *
d29b2f9d
ACO		 13157 * We are also relying on these states to convert the legacy mode set
13158 * to use a drm_atomic_state struct. The states are kept consistent
13159 * with actual state, so that it is safe to rely on that instead of
13160 * the staged config.
13161 *
c6f95f27
MR		 13162 * Once atomic support for crtc's + connectors lands, this loop should
13163 * be removed since we'll be setting up real connector state, which
13164 * will contain Intel-specific properties.
13165 */
d29b2f9d
ACO		 13166 list_for_each_entry(connector,
13167 &dev->mode_config.connector_list,
13168 head) {
13169 if (!WARN_ON(connector->state)) {
13170 connector->state = kzalloc(sizeof(*connector->state),
13171 GFP_KERNEL);
c6f95f27
MR		 13172 }
13173 }
13174
0bc12bcb 13175 intel_psr_init(dev);
7c8f8a70 13176
b2784e15 13177 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 13178 encoder->base.possible_crtcs = encoder->crtc_mask;
13179 encoder->base.possible_clones =
66a9278e 13180 intel_encoder_clones(encoder);
79e53945 13181 }
47356eb6 13182
dde86e2d 13183 intel_init_pch_refclk(dev);
270b3042
DV		 13184
13185 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 13186}
13187
13188static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
13189{
60a5ca01 13190 struct drm_device *dev = fb->dev;
79e53945 13191 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 13192
ef2d633e 13193 drm_framebuffer_cleanup(fb);
60a5ca01 13194 mutex_lock(&dev->struct_mutex);
ef2d633e 13195 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 13196 drm_gem_object_unreference(&intel_fb->obj->base);
13197 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 13198 kfree(intel_fb);
13199}
13200
13201static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 13202 struct drm_file *file,
79e53945
JB		 13203 unsigned int *handle)
13204{
13205 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 13206 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 13207
05394f39 13208 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 13209}
13210
13211static const struct drm_framebuffer_funcs intel_fb_funcs = {
13212 .destroy = intel_user_framebuffer_destroy,
13213 .create_handle = intel_user_framebuffer_create_handle,
13214};
13215
b321803d
DL		 13216static
13217u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
13218 uint32_t pixel_format)
13219{
13220 u32 gen = INTEL_INFO(dev)->gen;
13221
13222 if (gen >= 9) {
13223 /* "The stride in bytes must not exceed the of the size of 8K
13224 * pixels and 32K bytes."
13225 */
13226 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
13227 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
13228 return 32*1024;
13229 } else if (gen >= 4) {
13230 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13231 return 16*1024;
13232 else
13233 return 32*1024;
13234 } else if (gen >= 3) {
13235 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13236 return 8*1024;
13237 else
13238 return 16*1024;
13239 } else {
13240 /* XXX DSPC is limited to 4k tiled */
13241 return 8*1024;
13242 }
13243}
13244
b5ea642a
DV		 13245static int intel_framebuffer_init(struct drm_device *dev,
13246 struct intel_framebuffer *intel_fb,
13247 struct drm_mode_fb_cmd2 *mode_cmd,
13248 struct drm_i915_gem_object *obj)
79e53945 13249{
6761dd31 13250 unsigned int aligned_height;
79e53945 13251 int ret;
b321803d 13252 u32 pitch_limit, stride_alignment;
79e53945 13253
dd4916c5
DV		 13254 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
13255
2a80eada
DV		 13256 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
13257 /* Enforce that fb modifier and tiling mode match, but only for
13258 * X-tiled. This is needed for FBC. */
13259 if (!!(obj->tiling_mode == I915_TILING_X) !=
13260 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
13261 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
13262 return -EINVAL;
13263 }
13264 } else {
13265 if (obj->tiling_mode == I915_TILING_X)
13266 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
13267 else if (obj->tiling_mode == I915_TILING_Y) {
13268 DRM_DEBUG("No Y tiling for legacy addfb\n");
13269 return -EINVAL;
13270 }
13271 }
13272
9a8f0a12
TU		 13273 /* Passed in modifier sanity checking. */
13274 switch (mode_cmd->modifier[0]) {
13275 case I915_FORMAT_MOD_Y_TILED:
13276 case I915_FORMAT_MOD_Yf_TILED:
13277 if (INTEL_INFO(dev)->gen < 9) {
13278 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
13279 mode_cmd->modifier[0]);
13280 return -EINVAL;
13281 }
13282 case DRM_FORMAT_MOD_NONE:
13283 case I915_FORMAT_MOD_X_TILED:
13284 break;
13285 default:
c0f40428
JB		 13286 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
13287 mode_cmd->modifier[0]);
57cd6508 13288 return -EINVAL;
c16ed4be 13289 }
57cd6508 13290
b321803d
DL		 13291 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
13292 mode_cmd->pixel_format);
13293 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
13294 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
13295 mode_cmd->pitches[0], stride_alignment);
57cd6508 13296 return -EINVAL;
c16ed4be 13297 }
57cd6508 13298
b321803d
DL		 13299 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
13300 mode_cmd->pixel_format);
a35cdaa0 13301 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 13302 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
13303 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 13304 "tiled" : "linear",
a35cdaa0 13305 mode_cmd->pitches[0], pitch_limit);
5d7bd705 13306 return -EINVAL;
c16ed4be 13307 }
5d7bd705 13308
2a80eada 13309 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 13310 mode_cmd->pitches[0] != obj->stride) {
13311 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
13312 mode_cmd->pitches[0], obj->stride);
5d7bd705 13313 return -EINVAL;
c16ed4be 13314 }
5d7bd705 13315
57779d06 13316 /* Reject formats not supported by any plane early. */
308e5bcb 13317 switch (mode_cmd->pixel_format) {
57779d06 13318 case DRM_FORMAT_C8:
04b3924d
VS		 13319 case DRM_FORMAT_RGB565:
13320 case DRM_FORMAT_XRGB8888:
13321 case DRM_FORMAT_ARGB8888:
57779d06
VS		 13322 break;
13323 case DRM_FORMAT_XRGB1555:
13324 case DRM_FORMAT_ARGB1555:
c16ed4be 13325 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 13326 DRM_DEBUG("unsupported pixel format: %s\n",
13327 drm_get_format_name(mode_cmd->pixel_format));
57779d06 13328 return -EINVAL;
c16ed4be 13329 }
57779d06
VS		 13330 break;
13331 case DRM_FORMAT_XBGR8888:
13332 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 13333 case DRM_FORMAT_XRGB2101010:
13334 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 13335 case DRM_FORMAT_XBGR2101010:
13336 case DRM_FORMAT_ABGR2101010:
c16ed4be 13337 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 13338 DRM_DEBUG("unsupported pixel format: %s\n",
13339 drm_get_format_name(mode_cmd->pixel_format));
57779d06 13340 return -EINVAL;
c16ed4be 13341 }
b5626747 13342 break;
04b3924d
VS		 13343 case DRM_FORMAT_YUYV:
13344 case DRM_FORMAT_UYVY:
13345 case DRM_FORMAT_YVYU:
13346 case DRM_FORMAT_VYUY:
c16ed4be 13347 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 13348 DRM_DEBUG("unsupported pixel format: %s\n",
13349 drm_get_format_name(mode_cmd->pixel_format));
57779d06 13350 return -EINVAL;
c16ed4be 13351 }
57cd6508
CW		 13352 break;
13353 default:
4ee62c76
VS		 13354 DRM_DEBUG("unsupported pixel format: %s\n",
13355 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 13356 return -EINVAL;
13357 }
13358
90f9a336
VS		 13359 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
13360 if (mode_cmd->offsets[0] != 0)
13361 return -EINVAL;
13362
ec2c981e 13363 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 13364 mode_cmd->pixel_format,
13365 mode_cmd->modifier[0]);
53155c0a
DV		 13366 /* FIXME drm helper for size checks (especially planar formats)? */
13367 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
13368 return -EINVAL;
13369
c7d73f6a
DV		 13370 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
13371 intel_fb->obj = obj;
80075d49 13372 intel_fb->obj->framebuffer_references++;
c7d73f6a 13373
79e53945
JB		 13374 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
13375 if (ret) {
13376 DRM_ERROR("framebuffer init failed %d\n", ret);
13377 return ret;
13378 }
13379
79e53945
JB		 13380 return 0;
13381}
13382
79e53945
JB		 13383static struct drm_framebuffer *
13384intel_user_framebuffer_create(struct drm_device *dev,
13385 struct drm_file *filp,
308e5bcb 13386 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 13387{
05394f39 13388 struct drm_i915_gem_object *obj;
79e53945 13389
308e5bcb
JB		 13390 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
13391 mode_cmd->handles[0]));
c8725226 13392 if (&obj->base == NULL)
cce13ff7 13393 return ERR_PTR(-ENOENT);
79e53945 13394
d2dff872 13395 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 13396}
13397
4520f53a 13398#ifndef CONFIG_DRM_I915_FBDEV
0632fef6 13399static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 13400{
13401}
13402#endif
13403
79e53945 13404static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 13405 .fb_create = intel_user_framebuffer_create,
0632fef6 13406 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 13407 .atomic_check = intel_atomic_check,
13408 .atomic_commit = intel_atomic_commit,
79e53945
JB		 13409};
13410
e70236a8
JB		 13411/* Set up chip specific display functions */
13412static void intel_init_display(struct drm_device *dev)
13413{
13414 struct drm_i915_private *dev_priv = dev->dev_private;
13415
ee9300bb
DV		 13416 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
13417 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 13418 else if (IS_CHERRYVIEW(dev))
13419 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 13420 else if (IS_VALLEYVIEW(dev))
13421 dev_priv->display.find_dpll = vlv_find_best_dpll;
13422 else if (IS_PINEVIEW(dev))
13423 dev_priv->display.find_dpll = pnv_find_best_dpll;
13424 else
13425 dev_priv->display.find_dpll = i9xx_find_best_dpll;
13426
bc8d7dff
DL		 13427 if (INTEL_INFO(dev)->gen >= 9) {
13428 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 13429 dev_priv->display.get_initial_plane_config =
13430 skylake_get_initial_plane_config;
bc8d7dff
DL		 13431 dev_priv->display.crtc_compute_clock =
13432 haswell_crtc_compute_clock;
13433 dev_priv->display.crtc_enable = haswell_crtc_enable;
13434 dev_priv->display.crtc_disable = haswell_crtc_disable;
13435 dev_priv->display.off = ironlake_crtc_off;
13436 dev_priv->display.update_primary_plane =
13437 skylake_update_primary_plane;
13438 } else if (HAS_DDI(dev)) {
0e8ffe1b 13439 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 13440 dev_priv->display.get_initial_plane_config =
13441 ironlake_get_initial_plane_config;
797d0259
ACO		 13442 dev_priv->display.crtc_compute_clock =
13443 haswell_crtc_compute_clock;
4f771f10
PZ		 13444 dev_priv->display.crtc_enable = haswell_crtc_enable;
13445 dev_priv->display.crtc_disable = haswell_crtc_disable;
df8ad70c 13446 dev_priv->display.off = ironlake_crtc_off;
bc8d7dff
DL		 13447 dev_priv->display.update_primary_plane =
13448 ironlake_update_primary_plane;
09b4ddf9 13449 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 13450 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 13451 dev_priv->display.get_initial_plane_config =
13452 ironlake_get_initial_plane_config;
3fb37703
ACO		 13453 dev_priv->display.crtc_compute_clock =
13454 ironlake_crtc_compute_clock;
76e5a89c
DV		 13455 dev_priv->display.crtc_enable = ironlake_crtc_enable;
13456 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 13457 dev_priv->display.off = ironlake_crtc_off;
262ca2b0
MR		 13458 dev_priv->display.update_primary_plane =
13459 ironlake_update_primary_plane;
89b667f8
JB		 13460 } else if (IS_VALLEYVIEW(dev)) {
13461 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 13462 dev_priv->display.get_initial_plane_config =
13463 i9xx_get_initial_plane_config;
d6dfee7a 13464 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 13465 dev_priv->display.crtc_enable = valleyview_crtc_enable;
13466 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13467 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR		 13468 dev_priv->display.update_primary_plane =
13469 i9xx_update_primary_plane;
f564048e 13470 } else {
0e8ffe1b 13471 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 13472 dev_priv->display.get_initial_plane_config =
13473 i9xx_get_initial_plane_config;
d6dfee7a 13474 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 13475 dev_priv->display.crtc_enable = i9xx_crtc_enable;
13476 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 13477 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR		 13478 dev_priv->display.update_primary_plane =
13479 i9xx_update_primary_plane;
f564048e 13480 }
e70236a8 13481
e70236a8 13482 /* Returns the core display clock speed */
25eb05fc
JB		 13483 if (IS_VALLEYVIEW(dev))
13484 dev_priv->display.get_display_clock_speed =
13485 valleyview_get_display_clock_speed;
13486 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 13487 dev_priv->display.get_display_clock_speed =
13488 i945_get_display_clock_speed;
13489 else if (IS_I915G(dev))
13490 dev_priv->display.get_display_clock_speed =
13491 i915_get_display_clock_speed;
257a7ffc 13492 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 13493 dev_priv->display.get_display_clock_speed =
13494 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 13495 else if (IS_PINEVIEW(dev))
13496 dev_priv->display.get_display_clock_speed =
13497 pnv_get_display_clock_speed;
e70236a8
JB		 13498 else if (IS_I915GM(dev))
13499 dev_priv->display.get_display_clock_speed =
13500 i915gm_get_display_clock_speed;
13501 else if (IS_I865G(dev))
13502 dev_priv->display.get_display_clock_speed =
13503 i865_get_display_clock_speed;
f0f8a9ce 13504 else if (IS_I85X(dev))
e70236a8
JB		 13505 dev_priv->display.get_display_clock_speed =
13506 i855_get_display_clock_speed;
13507 else /* 852, 830 */
13508 dev_priv->display.get_display_clock_speed =
13509 i830_get_display_clock_speed;
13510
7c10a2b5 13511 if (IS_GEN5(dev)) {
3bb11b53 13512 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 13513 } else if (IS_GEN6(dev)) {
13514 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 13515 } else if (IS_IVYBRIDGE(dev)) {
13516 /* FIXME: detect B0+ stepping and use auto training */
13517 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 13518 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 13519 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
30a970c6
JB		 13520 } else if (IS_VALLEYVIEW(dev)) {
13521 dev_priv->display.modeset_global_resources =
13522 valleyview_modeset_global_resources;
e70236a8 13523 }
8c9f3aaf 13524
8c9f3aaf
JB		 13525 switch (INTEL_INFO(dev)->gen) {
13526 case 2:
13527 dev_priv->display.queue_flip = intel_gen2_queue_flip;
13528 break;
13529
13530 case 3:
13531 dev_priv->display.queue_flip = intel_gen3_queue_flip;
13532 break;
13533
13534 case 4:
13535 case 5:
13536 dev_priv->display.queue_flip = intel_gen4_queue_flip;
13537 break;
13538
13539 case 6:
13540 dev_priv->display.queue_flip = intel_gen6_queue_flip;
13541 break;
7c9017e5 13542 case 7:
4e0bbc31 13543 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 13544 dev_priv->display.queue_flip = intel_gen7_queue_flip;
13545 break;
830c81db 13546 case 9:
ba343e02
TU		 13547 /* Drop through - unsupported since execlist only. */
13548 default:
13549 /* Default just returns -ENODEV to indicate unsupported */
13550 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 13551 }
7bd688cd
JN		 13552
13553 intel_panel_init_backlight_funcs(dev);
e39b999a
VS		 13554
13555 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 13556}
13557
b690e96c
JB		 13558/*
13559 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
13560 * resume, or other times. This quirk makes sure that's the case for
13561 * affected systems.
13562 */
0206e353 13563static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 13564{
13565 struct drm_i915_private *dev_priv = dev->dev_private;
13566
13567 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 13568 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 13569}
13570
b6b5d049
VS		 13571static void quirk_pipeb_force(struct drm_device *dev)
13572{
13573 struct drm_i915_private *dev_priv = dev->dev_private;
13574
13575 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
13576 DRM_INFO("applying pipe b force quirk\n");
13577}
13578
435793df
KP		 13579/*
13580 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
13581 */
13582static void quirk_ssc_force_disable(struct drm_device *dev)
13583{
13584 struct drm_i915_private *dev_priv = dev->dev_private;
13585 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 13586 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 13587}
13588
4dca20ef 13589/*
5a15ab5b
CE		 13590 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
13591 * brightness value
4dca20ef
CE		 13592 */
13593static void quirk_invert_brightness(struct drm_device *dev)
13594{
13595 struct drm_i915_private *dev_priv = dev->dev_private;
13596 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 13597 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 13598}
13599
9c72cc6f
SD		 13600/* Some VBT's incorrectly indicate no backlight is present */
13601static void quirk_backlight_present(struct drm_device *dev)
13602{
13603 struct drm_i915_private *dev_priv = dev->dev_private;
13604 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
13605 DRM_INFO("applying backlight present quirk\n");
13606}
13607
b690e96c
JB		 13608struct intel_quirk {
13609 int device;
13610 int subsystem_vendor;
13611 int subsystem_device;
13612 void (*hook)(struct drm_device *dev);
13613};
13614
5f85f176
EE		 13615/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13616struct intel_dmi_quirk {
13617 void (*hook)(struct drm_device *dev);
13618 const struct dmi_system_id (*dmi_id_list)[];
13619};
13620
13621static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
13622{
13623 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
13624 return 1;
13625}
13626
13627static const struct intel_dmi_quirk intel_dmi_quirks[] = {
13628 {
13629 .dmi_id_list = &(const struct dmi_system_id[]) {
13630 {
13631 .callback = intel_dmi_reverse_brightness,
13632 .ident = "NCR Corporation",
13633 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
13634 DMI_MATCH(DMI_PRODUCT_NAME, ""),
13635 },
13636 },
13637 { } /* terminating entry */
13638 },
13639 .hook = quirk_invert_brightness,
13640 },
13641};
13642
c43b5634 13643static struct intel_quirk intel_quirks[] = {
b690e96c 13644 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 13645 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 13646
b690e96c
JB		 13647 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
13648 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
13649
b690e96c
JB		 13650 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
13651 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
13652
5f080c0f
VS		 13653 /* 830 needs to leave pipe A & dpll A up */
13654 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
13655
b6b5d049
VS		 13656 /* 830 needs to leave pipe B & dpll B up */
13657 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
13658
435793df
KP		 13659 /* Lenovo U160 cannot use SSC on LVDS */
13660 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 13661
13662 /* Sony Vaio Y cannot use SSC on LVDS */
13663 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 13664
be505f64
AH		 13665 /* Acer Aspire 5734Z must invert backlight brightness */
13666 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
13667
13668 /* Acer/eMachines G725 */
13669 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
13670
13671 /* Acer/eMachines e725 */
13672 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
13673
13674 /* Acer/Packard Bell NCL20 */
13675 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
13676
13677 /* Acer Aspire 4736Z */
13678 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 13679
13680 /* Acer Aspire 5336 */
13681 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 13682
13683 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13684 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 13685
dfb3d47b
SD		 13686 /* Acer C720 Chromebook (Core i3 4005U) */
13687 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
13688
b2a9601c 13689 /* Apple Macbook 2,1 (Core 2 T7400) */
13690 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
13691
d4967d8c
SD		 13692 /* Toshiba CB35 Chromebook (Celeron 2955U) */
13693 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 13694
13695 /* HP Chromebook 14 (Celeron 2955U) */
13696 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 13697
13698 /* Dell Chromebook 11 */
13699 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 13700};
13701
13702static void intel_init_quirks(struct drm_device *dev)
13703{
13704 struct pci_dev *d = dev->pdev;
13705 int i;
13706
13707 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
13708 struct intel_quirk *q = &intel_quirks[i];
13709
13710 if (d->device == q->device &&
13711 (d->subsystem_vendor == q->subsystem_vendor ||
13712 q->subsystem_vendor == PCI_ANY_ID) &&
13713 (d->subsystem_device == q->subsystem_device ||
13714 q->subsystem_device == PCI_ANY_ID))
13715 q->hook(dev);
13716 }
5f85f176
EE		 13717 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
13718 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
13719 intel_dmi_quirks[i].hook(dev);
13720 }
b690e96c
JB		 13721}
13722
9cce37f4
JB		 13723/* Disable the VGA plane that we never use */
13724static void i915_disable_vga(struct drm_device *dev)
13725{
13726 struct drm_i915_private *dev_priv = dev->dev_private;
13727 u8 sr1;
766aa1c4 13728 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 13729
2b37c616 13730 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 13731 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 13732 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 13733 sr1 = inb(VGA_SR_DATA);
13734 outb(sr1 | 1<<5, VGA_SR_DATA);
13735 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
13736 udelay(300);
13737
01f5a626 13738 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 13739 POSTING_READ(vga_reg);
13740}
13741
f817586c
DV		 13742void intel_modeset_init_hw(struct drm_device *dev)
13743{
a8f78b58
ED		 13744 intel_prepare_ddi(dev);
13745
f8bf63fd
VS		 13746 if (IS_VALLEYVIEW(dev))
13747 vlv_update_cdclk(dev);
13748
f817586c
DV		 13749 intel_init_clock_gating(dev);
13750
8090c6b9 13751 intel_enable_gt_powersave(dev);
f817586c
DV		 13752}
13753
79e53945
JB		 13754void intel_modeset_init(struct drm_device *dev)
13755{
652c393a 13756 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 13757 int sprite, ret;
8cc87b75 13758 enum pipe pipe;
46f297fb 13759 struct intel_crtc *crtc;
79e53945
JB		 13760
13761 drm_mode_config_init(dev);
13762
13763 dev->mode_config.min_width = 0;
13764 dev->mode_config.min_height = 0;
13765
019d96cb
DA		 13766 dev->mode_config.preferred_depth = 24;
13767 dev->mode_config.prefer_shadow = 1;
13768
25bab385
TU		 13769 dev->mode_config.allow_fb_modifiers = true;
13770
e6ecefaa 13771 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 13772
b690e96c
JB		 13773 intel_init_quirks(dev);
13774
1fa61106
ED		 13775 intel_init_pm(dev);
13776
e3c74757
BW		 13777 if (INTEL_INFO(dev)->num_pipes == 0)
13778 return;
13779
e70236a8 13780 intel_init_display(dev);
7c10a2b5 13781 intel_init_audio(dev);
e70236a8 13782
a6c45cf0
CW		 13783 if (IS_GEN2(dev)) {
13784 dev->mode_config.max_width = 2048;
13785 dev->mode_config.max_height = 2048;
13786 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 13787 dev->mode_config.max_width = 4096;
13788 dev->mode_config.max_height = 4096;
79e53945 13789 } else {
a6c45cf0
CW		 13790 dev->mode_config.max_width = 8192;
13791 dev->mode_config.max_height = 8192;
79e53945 13792 }
068be561 13793
dc41c154
VS		 13794 if (IS_845G(dev) || IS_I865G(dev)) {
13795 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13796 dev->mode_config.cursor_height = 1023;
13797 } else if (IS_GEN2(dev)) {
068be561
DL		 13798 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13799 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13800 } else {
13801 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13802 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13803 }
13804
5d4545ae 13805 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 13806
28c97730 13807 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 13808 INTEL_INFO(dev)->num_pipes,
13809 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 13810
055e393f 13811 for_each_pipe(dev_priv, pipe) {
8cc87b75 13812 intel_crtc_init(dev, pipe);
3bdcfc0c 13813 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 13814 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 13815 if (ret)
06da8da2 13816 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 13817 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 13818 }
79e53945
JB		 13819 }
13820
f42bb70d
JB		 13821 intel_init_dpio(dev);
13822
e72f9fbf 13823 intel_shared_dpll_init(dev);
ee7b9f93 13824
9cce37f4
JB		 13825 /* Just disable it once at startup */
13826 i915_disable_vga(dev);
79e53945 13827 intel_setup_outputs(dev);
11be49eb
CW		 13828
13829 /* Just in case the BIOS is doing something questionable. */
7ff0ebcc 13830 intel_fbc_disable(dev);
fa9fa083 13831
6e9f798d 13832 drm_modeset_lock_all(dev);
fa9fa083 13833 intel_modeset_setup_hw_state(dev, false);
6e9f798d 13834 drm_modeset_unlock_all(dev);
46f297fb 13835
d3fcc808 13836 for_each_intel_crtc(dev, crtc) {
46f297fb
JB		 13837 if (!crtc->active)
13838 continue;
13839
46f297fb 13840 /*
46f297fb
JB		 13841 * Note that reserving the BIOS fb up front prevents us
13842 * from stuffing other stolen allocations like the ring
13843 * on top. This prevents some ugliness at boot time, and
13844 * can even allow for smooth boot transitions if the BIOS
13845 * fb is large enough for the active pipe configuration.
13846 */
5724dbd1
DL		 13847 if (dev_priv->display.get_initial_plane_config) {
13848 dev_priv->display.get_initial_plane_config(crtc,
46f297fb
JB		 13849 &crtc->plane_config);
13850 /*
13851 * If the fb is shared between multiple heads, we'll
13852 * just get the first one.
13853 */
f6936e29 13854 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
46f297fb 13855 }
46f297fb 13856 }
2c7111db
CW		 13857}
13858
7fad798e
DV		 13859static void intel_enable_pipe_a(struct drm_device *dev)
13860{
13861 struct intel_connector *connector;
13862 struct drm_connector *crt = NULL;
13863 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 13864 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 13865
13866 /* We can't just switch on the pipe A, we need to set things up with a
13867 * proper mode and output configuration. As a gross hack, enable pipe A
13868 * by enabling the load detect pipe once. */
3a3371ff 13869 for_each_intel_connector(dev, connector) {
7fad798e
DV		 13870 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13871 crt = &connector->base;
13872 break;
13873 }
13874 }
13875
13876 if (!crt)
13877 return;
13878
208bf9fd 13879 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 13880 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 13881}
13882
fa555837
DV		 13883static bool
13884intel_check_plane_mapping(struct intel_crtc *crtc)
13885{
7eb552ae
BW		 13886 struct drm_device *dev = crtc->base.dev;
13887 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 13888 u32 reg, val;
13889
7eb552ae 13890 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 13891 return true;
13892
13893 reg = DSPCNTR(!crtc->plane);
13894 val = I915_READ(reg);
13895
13896 if ((val & DISPLAY_PLANE_ENABLE) &&
13897 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13898 return false;
13899
13900 return true;
13901}
13902
24929352
DV		 13903static void intel_sanitize_crtc(struct intel_crtc *crtc)
13904{
13905 struct drm_device *dev = crtc->base.dev;
13906 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 13907 u32 reg;
24929352 13908
24929352 13909 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 13910 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 13911 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13912
d3eaf884 13913 /* restore vblank interrupts to correct state */
9625604c 13914 drm_crtc_vblank_reset(&crtc->base);
d297e103
VS		 13915 if (crtc->active) {
13916 update_scanline_offset(crtc);
9625604c
DV		 13917 drm_crtc_vblank_on(&crtc->base);
13918 }
d3eaf884 13919
24929352 13920 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 13921 * disable the crtc (and hence change the state) if it is wrong. Note
13922 * that gen4+ has a fixed plane -> pipe mapping. */
13923 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 13924 struct intel_connector *connector;
13925 bool plane;
13926
24929352
DV		 13927 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13928 crtc->base.base.id);
13929
13930 /* Pipe has the wrong plane attached and the plane is active.
13931 * Temporarily change the plane mapping and disable everything
13932 * ... */
13933 plane = crtc->plane;
13934 crtc->plane = !plane;
9c8958bc 13935 crtc->primary_enabled = true;
24929352
DV		 13936 dev_priv->display.crtc_disable(&crtc->base);
13937 crtc->plane = plane;
13938
13939 /* ... and break all links. */
3a3371ff 13940 for_each_intel_connector(dev, connector) {
24929352
DV		 13941 if (connector->encoder->base.crtc != &crtc->base)
13942 continue;
13943
7f1950fb
EE		 13944 connector->base.dpms = DRM_MODE_DPMS_OFF;
13945 connector->base.encoder = NULL;
24929352 13946 }
7f1950fb
EE		 13947 /* multiple connectors may have the same encoder:
13948 * handle them and break crtc link separately */
3a3371ff 13949 for_each_intel_connector(dev, connector)
7f1950fb
EE		 13950 if (connector->encoder->base.crtc == &crtc->base) {
13951 connector->encoder->base.crtc = NULL;
13952 connector->encoder->connectors_active = false;
13953 }
24929352
DV		 13954
13955 WARN_ON(crtc->active);
83d65738 13956 crtc->base.state->enable = false;
24929352
DV		 13957 crtc->base.enabled = false;
13958 }
24929352 13959
7fad798e
DV		 13960 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13961 crtc->pipe == PIPE_A && !crtc->active) {
13962 /* BIOS forgot to enable pipe A, this mostly happens after
13963 * resume. Force-enable the pipe to fix this, the update_dpms
13964 * call below we restore the pipe to the right state, but leave
13965 * the required bits on. */
13966 intel_enable_pipe_a(dev);
13967 }
13968
24929352
DV		 13969 /* Adjust the state of the output pipe according to whether we
13970 * have active connectors/encoders. */
13971 intel_crtc_update_dpms(&crtc->base);
13972
83d65738 13973 if (crtc->active != crtc->base.state->enable) {
24929352
DV		 13974 struct intel_encoder *encoder;
13975
13976 /* This can happen either due to bugs in the get_hw_state
13977 * functions or because the pipe is force-enabled due to the
13978 * pipe A quirk. */
13979 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13980 crtc->base.base.id,
83d65738 13981 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 13982 crtc->active ? "enabled" : "disabled");
13983
83d65738 13984 crtc->base.state->enable = crtc->active;
24929352
DV		 13985 crtc->base.enabled = crtc->active;
13986
13987 /* Because we only establish the connector -> encoder ->
13988 * crtc links if something is active, this means the
13989 * crtc is now deactivated. Break the links. connector
13990 * -> encoder links are only establish when things are
13991 * actually up, hence no need to break them. */
13992 WARN_ON(crtc->active);
13993
13994 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13995 WARN_ON(encoder->connectors_active);
13996 encoder->base.crtc = NULL;
13997 }
13998 }
c5ab3bc0 13999
a3ed6aad 14000 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 14001 /*
14002 * We start out with underrun reporting disabled to avoid races.
14003 * For correct bookkeeping mark this on active crtcs.
14004 *
c5ab3bc0
DV		 14005 * Also on gmch platforms we dont have any hardware bits to
14006 * disable the underrun reporting. Which means we need to start
14007 * out with underrun reporting disabled also on inactive pipes,
14008 * since otherwise we'll complain about the garbage we read when
14009 * e.g. coming up after runtime pm.
14010 *
4cc31489
DV		 14011 * No protection against concurrent access is required - at
14012 * worst a fifo underrun happens which also sets this to false.
14013 */
14014 crtc->cpu_fifo_underrun_disabled = true;
14015 crtc->pch_fifo_underrun_disabled = true;
14016 }
24929352
DV		 14017}
14018
14019static void intel_sanitize_encoder(struct intel_encoder *encoder)
14020{
14021 struct intel_connector *connector;
14022 struct drm_device *dev = encoder->base.dev;
14023
14024 /* We need to check both for a crtc link (meaning that the
14025 * encoder is active and trying to read from a pipe) and the
14026 * pipe itself being active. */
14027 bool has_active_crtc = encoder->base.crtc &&
14028 to_intel_crtc(encoder->base.crtc)->active;
14029
14030 if (encoder->connectors_active && !has_active_crtc) {
14031 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14032 encoder->base.base.id,
8e329a03 14033 encoder->base.name);
24929352
DV		 14034
14035 /* Connector is active, but has no active pipe. This is
14036 * fallout from our resume register restoring. Disable
14037 * the encoder manually again. */
14038 if (encoder->base.crtc) {
14039 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14040 encoder->base.base.id,
8e329a03 14041 encoder->base.name);
24929352 14042 encoder->disable(encoder);
a62d1497
VS		 14043 if (encoder->post_disable)
14044 encoder->post_disable(encoder);
24929352 14045 }
7f1950fb
EE		 14046 encoder->base.crtc = NULL;
14047 encoder->connectors_active = false;
24929352
DV		 14048
14049 /* Inconsistent output/port/pipe state happens presumably due to
14050 * a bug in one of the get_hw_state functions. Or someplace else
14051 * in our code, like the register restore mess on resume. Clamp
14052 * things to off as a safer default. */
3a3371ff 14053 for_each_intel_connector(dev, connector) {
24929352
DV		 14054 if (connector->encoder != encoder)
14055 continue;
7f1950fb
EE		 14056 connector->base.dpms = DRM_MODE_DPMS_OFF;
14057 connector->base.encoder = NULL;
24929352
DV		 14058 }
14059 }
14060 /* Enabled encoders without active connectors will be fixed in
14061 * the crtc fixup. */
14062}
14063
04098753 14064void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 14065{
14066 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 14067 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 14068
04098753
ID		 14069 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14070 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14071 i915_disable_vga(dev);
14072 }
14073}
14074
14075void i915_redisable_vga(struct drm_device *dev)
14076{
14077 struct drm_i915_private *dev_priv = dev->dev_private;
14078
8dc8a27c
PZ		 14079 /* This function can be called both from intel_modeset_setup_hw_state or
14080 * at a very early point in our resume sequence, where the power well
14081 * structures are not yet restored. Since this function is at a very
14082 * paranoid "someone might have enabled VGA while we were not looking"
14083 * level, just check if the power well is enabled instead of trying to
14084 * follow the "don't touch the power well if we don't need it" policy
14085 * the rest of the driver uses. */
f458ebbc 14086 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 14087 return;
14088
04098753 14089 i915_redisable_vga_power_on(dev);
0fde901f
KM		 14090}
14091
98ec7739
VS		 14092static bool primary_get_hw_state(struct intel_crtc *crtc)
14093{
14094 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
14095
14096 if (!crtc->active)
14097 return false;
14098
14099 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
14100}
14101
30e984df 14102static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 14103{
14104 struct drm_i915_private *dev_priv = dev->dev_private;
14105 enum pipe pipe;
24929352
DV		 14106 struct intel_crtc *crtc;
14107 struct intel_encoder *encoder;
14108 struct intel_connector *connector;
5358901f 14109 int i;
24929352 14110
d3fcc808 14111 for_each_intel_crtc(dev, crtc) {
6e3c9717 14112 memset(crtc->config, 0, sizeof(*crtc->config));
3b117c8f 14113
6e3c9717 14114 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
9953599b 14115
0e8ffe1b 14116 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 14117 crtc->config);
24929352 14118
83d65738 14119 crtc->base.state->enable = crtc->active;
24929352 14120 crtc->base.enabled = crtc->active;
98ec7739 14121 crtc->primary_enabled = primary_get_hw_state(crtc);
24929352
DV		 14122
14123 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
14124 crtc->base.base.id,
14125 crtc->active ? "enabled" : "disabled");
14126 }
14127
5358901f
DV		 14128 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14129 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14130
3e369b76
ACO		 14131 pll->on = pll->get_hw_state(dev_priv, pll,
14132 &pll->config.hw_state);
5358901f 14133 pll->active = 0;
3e369b76 14134 pll->config.crtc_mask = 0;
d3fcc808 14135 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 14136 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 14137 pll->active++;
3e369b76 14138 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 14139 }
5358901f 14140 }
5358901f 14141
1e6f2ddc 14142 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 14143 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 14144
3e369b76 14145 if (pll->config.crtc_mask)
bd2bb1b9 14146 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 14147 }
14148
b2784e15 14149 for_each_intel_encoder(dev, encoder) {
24929352
DV		 14150 pipe = 0;
14151
14152 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 14153 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14154 encoder->base.crtc = &crtc->base;
6e3c9717 14155 encoder->get_config(encoder, crtc->config);
24929352
DV		 14156 } else {
14157 encoder->base.crtc = NULL;
14158 }
14159
14160 encoder->connectors_active = false;
6f2bcceb 14161 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 14162 encoder->base.base.id,
8e329a03 14163 encoder->base.name,
24929352 14164 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 14165 pipe_name(pipe));
24929352
DV		 14166 }
14167
3a3371ff 14168 for_each_intel_connector(dev, connector) {
24929352
DV		 14169 if (connector->get_hw_state(connector)) {
14170 connector->base.dpms = DRM_MODE_DPMS_ON;
14171 connector->encoder->connectors_active = true;
14172 connector->base.encoder = &connector->encoder->base;
14173 } else {
14174 connector->base.dpms = DRM_MODE_DPMS_OFF;
14175 connector->base.encoder = NULL;
14176 }
14177 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
14178 connector->base.base.id,
c23cc417 14179 connector->base.name,
24929352
DV		 14180 connector->base.encoder ? "enabled" : "disabled");
14181 }
30e984df
DV		 14182}
14183
14184/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
14185 * and i915 state tracking structures. */
14186void intel_modeset_setup_hw_state(struct drm_device *dev,
14187 bool force_restore)
14188{
14189 struct drm_i915_private *dev_priv = dev->dev_private;
14190 enum pipe pipe;
30e984df
DV		 14191 struct intel_crtc *crtc;
14192 struct intel_encoder *encoder;
35c95375 14193 int i;
30e984df
DV		 14194
14195 intel_modeset_readout_hw_state(dev);
24929352 14196
babea61d
JB		 14197 /*
14198 * Now that we have the config, copy it to each CRTC struct
14199 * Note that this could go away if we move to using crtc_config
14200 * checking everywhere.
14201 */
d3fcc808 14202 for_each_intel_crtc(dev, crtc) {
d330a953 14203 if (crtc->active && i915.fastboot) {
6e3c9717
ACO		 14204 intel_mode_from_pipe_config(&crtc->base.mode,
14205 crtc->config);
babea61d
JB		 14206 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
14207 crtc->base.base.id);
14208 drm_mode_debug_printmodeline(&crtc->base.mode);
14209 }
14210 }
14211
24929352 14212 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 14213 for_each_intel_encoder(dev, encoder) {
24929352
DV		 14214 intel_sanitize_encoder(encoder);
14215 }
14216
055e393f 14217 for_each_pipe(dev_priv, pipe) {
24929352
DV		 14218 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14219 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 14220 intel_dump_pipe_config(crtc, crtc->config,
14221 "[setup_hw_state]");
24929352 14222 }
9a935856 14223
d29b2f9d
ACO		 14224 intel_modeset_update_connector_atomic_state(dev);
14225
35c95375
DV		 14226 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14227 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14228
14229 if (!pll->on || pll->active)
14230 continue;
14231
14232 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
14233
14234 pll->disable(dev_priv, pll);
14235 pll->on = false;
14236 }
14237
3078999f
PB		 14238 if (IS_GEN9(dev))
14239 skl_wm_get_hw_state(dev);
14240 else if (HAS_PCH_SPLIT(dev))
243e6a44
VS		 14241 ilk_wm_get_hw_state(dev);
14242
45e2b5f6 14243 if (force_restore) {
7d0bc1ea
VS		 14244 i915_redisable_vga(dev);
14245
f30da187
DV		 14246 /*
14247 * We need to use raw interfaces for restoring state to avoid
14248 * checking (bogus) intermediate states.
14249 */
055e393f 14250 for_each_pipe(dev_priv, pipe) {
b5644d05
JB		 14251 struct drm_crtc *crtc =
14252 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187 14253
83a57153 14254 intel_crtc_restore_mode(crtc);
45e2b5f6
DV		 14255 }
14256 } else {
14257 intel_modeset_update_staged_output_state(dev);
14258 }
8af6cf88
DV		 14259
14260 intel_modeset_check_state(dev);
2c7111db
CW		 14261}
14262
14263void intel_modeset_gem_init(struct drm_device *dev)
14264{
92122789 14265 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd 14266 struct drm_crtc *c;
2ff8fde1 14267 struct drm_i915_gem_object *obj;
484b41dd 14268
ae48434c
ID		 14269 mutex_lock(&dev->struct_mutex);
14270 intel_init_gt_powersave(dev);
14271 mutex_unlock(&dev->struct_mutex);
14272
92122789
JB		 14273 /*
14274 * There may be no VBT; and if the BIOS enabled SSC we can
14275 * just keep using it to avoid unnecessary flicker. Whereas if the
14276 * BIOS isn't using it, don't assume it will work even if the VBT
14277 * indicates as much.
14278 */
14279 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
14280 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14281 DREF_SSC1_ENABLE);
14282
1833b134 14283 intel_modeset_init_hw(dev);
02e792fb
DV		 14284
14285 intel_setup_overlay(dev);
484b41dd
JB		 14286
14287 /*
14288 * Make sure any fbs we allocated at startup are properly
14289 * pinned & fenced. When we do the allocation it's too early
14290 * for this.
14291 */
14292 mutex_lock(&dev->struct_mutex);
70e1e0ec 14293 for_each_crtc(dev, c) {
2ff8fde1
MR		 14294 obj = intel_fb_obj(c->primary->fb);
14295 if (obj == NULL)
484b41dd
JB		 14296 continue;
14297
850c4cdc
TU		 14298 if (intel_pin_and_fence_fb_obj(c->primary,
14299 c->primary->fb,
82bc3b2d 14300 c->primary->state,
850c4cdc 14301 NULL)) {
484b41dd
JB		 14302 DRM_ERROR("failed to pin boot fb on pipe %d\n",
14303 to_intel_crtc(c)->pipe);
66e514c1
DA		 14304 drm_framebuffer_unreference(c->primary->fb);
14305 c->primary->fb = NULL;
afd65eb4 14306 update_state_fb(c->primary);
484b41dd
JB		 14307 }
14308 }
14309 mutex_unlock(&dev->struct_mutex);
0962c3c9
VS		 14310
14311 intel_backlight_register(dev);
79e53945
JB		 14312}
14313
4932e2c3
ID		 14314void intel_connector_unregister(struct intel_connector *intel_connector)
14315{
14316 struct drm_connector *connector = &intel_connector->base;
14317
14318 intel_panel_destroy_backlight(connector);
34ea3d38 14319 drm_connector_unregister(connector);
4932e2c3
ID		 14320}
14321
79e53945
JB		 14322void intel_modeset_cleanup(struct drm_device *dev)
14323{
652c393a 14324 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 14325 struct drm_connector *connector;
652c393a 14326
2eb5252e
ID		 14327 intel_disable_gt_powersave(dev);
14328
0962c3c9
VS		 14329 intel_backlight_unregister(dev);
14330
fd0c0642
DV		 14331 /*
14332 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 14333 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 14334 * experience fancy races otherwise.
14335 */
2aeb7d3a 14336 intel_irq_uninstall(dev_priv);
eb21b92b 14337
fd0c0642
DV		 14338 /*
14339 * Due to the hpd irq storm handling the hotplug work can re-arm the
14340 * poll handlers. Hence disable polling after hpd handling is shut down.
14341 */
f87ea761 14342 drm_kms_helper_poll_fini(dev);
fd0c0642 14343
652c393a
JB		 14344 mutex_lock(&dev->struct_mutex);
14345
723bfd70
JB		 14346 intel_unregister_dsm_handler();
14347
7ff0ebcc 14348 intel_fbc_disable(dev);
e70236a8 14349
69341a5e
KH		 14350 mutex_unlock(&dev->struct_mutex);
14351
1630fe75
CW		 14352 /* flush any delayed tasks or pending work */
14353 flush_scheduled_work();
14354
db31af1d
JN		 14355 /* destroy the backlight and sysfs files before encoders/connectors */
14356 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 14357 struct intel_connector *intel_connector;
14358
14359 intel_connector = to_intel_connector(connector);
14360 intel_connector->unregister(intel_connector);
db31af1d 14361 }
d9255d57 14362
79e53945 14363 drm_mode_config_cleanup(dev);
4d7bb011
DV		 14364
14365 intel_cleanup_overlay(dev);
ae48434c
ID		 14366
14367 mutex_lock(&dev->struct_mutex);
14368 intel_cleanup_gt_powersave(dev);
14369 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 14370}
14371
f1c79df3
ZW		 14372/*
14373 * Return which encoder is currently attached for connector.
14374 */
df0e9248 14375struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 14376{
df0e9248
CW		 14377 return &intel_attached_encoder(connector)->base;
14378}
f1c79df3 14379
df0e9248
CW		 14380void intel_connector_attach_encoder(struct intel_connector *connector,
14381 struct intel_encoder *encoder)
14382{
14383 connector->encoder = encoder;
14384 drm_mode_connector_attach_encoder(&connector->base,
14385 &encoder->base);
79e53945 14386}
28d52043
DA		 14387
14388/*
14389 * set vga decode state - true == enable VGA decode
14390 */
14391int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
14392{
14393 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 14394 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 14395 u16 gmch_ctrl;
14396
75fa041d
CW		 14397 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
14398 DRM_ERROR("failed to read control word\n");
14399 return -EIO;
14400 }
14401
c0cc8a55
CW		 14402 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
14403 return 0;
14404
28d52043
DA		 14405 if (state)
14406 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
14407 else
14408 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 14409
14410 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
14411 DRM_ERROR("failed to write control word\n");
14412 return -EIO;
14413 }
14414
28d52043
DA		 14415 return 0;
14416}
c4a1d9e4 14417
c4a1d9e4 14418struct intel_display_error_state {
ff57f1b0
PZ		 14419
14420 u32 power_well_driver;
14421
63b66e5b
CW		 14422 int num_transcoders;
14423
c4a1d9e4
CW		 14424 struct intel_cursor_error_state {
14425 u32 control;
14426 u32 position;
14427 u32 base;
14428 u32 size;
52331309 14429 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 14430
14431 struct intel_pipe_error_state {
ddf9c536 14432 bool power_domain_on;
c4a1d9e4 14433 u32 source;
f301b1e1 14434 u32 stat;
52331309 14435 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 14436
14437 struct intel_plane_error_state {
14438 u32 control;
14439 u32 stride;
14440 u32 size;
14441 u32 pos;
14442 u32 addr;
14443 u32 surface;
14444 u32 tile_offset;
52331309 14445 } plane[I915_MAX_PIPES];
63b66e5b
CW		 14446
14447 struct intel_transcoder_error_state {
ddf9c536 14448 bool power_domain_on;
63b66e5b
CW		 14449 enum transcoder cpu_transcoder;
14450
14451 u32 conf;
14452
14453 u32 htotal;
14454 u32 hblank;
14455 u32 hsync;
14456 u32 vtotal;
14457 u32 vblank;
14458 u32 vsync;
14459 } transcoder[4];
c4a1d9e4
CW		 14460};
14461
14462struct intel_display_error_state *
14463intel_display_capture_error_state(struct drm_device *dev)
14464{
fbee40df 14465 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 14466 struct intel_display_error_state *error;
63b66e5b
CW		 14467 int transcoders[] = {
14468 TRANSCODER_A,
14469 TRANSCODER_B,
14470 TRANSCODER_C,
14471 TRANSCODER_EDP,
14472 };
c4a1d9e4
CW		 14473 int i;
14474
63b66e5b
CW		 14475 if (INTEL_INFO(dev)->num_pipes == 0)
14476 return NULL;
14477
9d1cb914 14478 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 14479 if (error == NULL)
14480 return NULL;
14481
190be112 14482 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 14483 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
14484
055e393f 14485 for_each_pipe(dev_priv, i) {
ddf9c536 14486 error->pipe[i].power_domain_on =
f458ebbc
DV		 14487 __intel_display_power_is_enabled(dev_priv,
14488 POWER_DOMAIN_PIPE(i));
ddf9c536 14489 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 14490 continue;
14491
5efb3e28
VS		 14492 error->cursor[i].control = I915_READ(CURCNTR(i));
14493 error->cursor[i].position = I915_READ(CURPOS(i));
14494 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 14495
14496 error->plane[i].control = I915_READ(DSPCNTR(i));
14497 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 14498 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 14499 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 14500 error->plane[i].pos = I915_READ(DSPPOS(i));
14501 }
ca291363
PZ		 14502 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14503 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 14504 if (INTEL_INFO(dev)->gen >= 4) {
14505 error->plane[i].surface = I915_READ(DSPSURF(i));
14506 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
14507 }
14508
c4a1d9e4 14509 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 14510
3abfce77 14511 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 14512 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 14513 }
14514
14515 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
14516 if (HAS_DDI(dev_priv->dev))
14517 error->num_transcoders++; /* Account for eDP. */
14518
14519 for (i = 0; i < error->num_transcoders; i++) {
14520 enum transcoder cpu_transcoder = transcoders[i];
14521
ddf9c536 14522 error->transcoder[i].power_domain_on =
f458ebbc 14523 __intel_display_power_is_enabled(dev_priv,
38cc1daf 14524 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 14525 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 14526 continue;
14527
63b66e5b
CW		 14528 error->transcoder[i].cpu_transcoder = cpu_transcoder;
14529
14530 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
14531 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
14532 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
14533 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
14534 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
14535 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
14536 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 14537 }
14538
14539 return error;
14540}
14541
edc3d884
MK		 14542#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
14543
c4a1d9e4 14544void
edc3d884 14545intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 14546 struct drm_device *dev,
14547 struct intel_display_error_state *error)
14548{
055e393f 14549 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 14550 int i;
14551
63b66e5b
CW		 14552 if (!error)
14553 return;
14554
edc3d884 14555 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 14556 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 14557 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 14558 error->power_well_driver);
055e393f 14559 for_each_pipe(dev_priv, i) {
edc3d884 14560 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 14561 err_printf(m, " Power: %s\n",
14562 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 14563 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 14564 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 14565
14566 err_printf(m, "Plane [%d]:\n", i);
14567 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
14568 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 14569 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 14570 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
14571 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 14572 }
4b71a570 14573 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 14574 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 14575 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 14576 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
14577 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 14578 }
14579
edc3d884
MK		 14580 err_printf(m, "Cursor [%d]:\n", i);
14581 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
14582 err_printf(m, " POS: %08x\n", error->cursor[i].position);
14583 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 14584 }
63b66e5b
CW		 14585
14586 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 14587 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 14588 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 14589 err_printf(m, " Power: %s\n",
14590 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 14591 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
14592 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
14593 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
14594 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
14595 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
14596 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
14597 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
14598 }
c4a1d9e4 14599}
e2fcdaa9
VS		 14600
14601void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
14602{
14603 struct intel_crtc *crtc;
14604
14605 for_each_intel_crtc(dev, crtc) {
14606 struct intel_unpin_work *work;
e2fcdaa9 14607
5e2d7afc 14608 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 14609
14610 work = crtc->unpin_work;
14611
14612 if (work && work->event &&
14613 work->event->base.file_priv == file) {
14614 kfree(work->event);
14615 work->event = NULL;
14616 }
14617
5e2d7afc 14618 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 14619 }
14620}
Linux kernel - Deliverables
This page took 3.515095 seconds and 5 git commands to generate.